Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 21
- Kernel Errors: 35
- Errors: 1
1 23:10:31.972611 lava-dispatcher, installed at version: 2023.10
2 23:10:31.972841 start: 0 validate
3 23:10:31.973043 Start time: 2023-12-01 23:10:31.973033+00:00 (UTC)
4 23:10:31.973162 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:10:31.973291 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 23:10:32.258990 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:10:32.259744 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:10:32.532331 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:10:32.533194 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:10:32.813521 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:10:32.814428 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.64-cip10%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:10:33.090951 validate duration: 1.12
14 23:10:33.092301 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:10:33.092852 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:10:33.093342 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:10:33.094017 Not decompressing ramdisk as can be used compressed.
18 23:10:33.094598 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 23:10:33.095140 saving as /var/lib/lava/dispatcher/tmp/12154446/tftp-deploy-g5gjd_yr/ramdisk/rootfs.cpio.gz
20 23:10:33.095534 total size: 26246609 (25 MB)
21 23:10:33.101246 progress 0 % (0 MB)
22 23:10:33.124905 progress 5 % (1 MB)
23 23:10:33.136431 progress 10 % (2 MB)
24 23:10:33.145068 progress 15 % (3 MB)
25 23:10:33.152475 progress 20 % (5 MB)
26 23:10:33.159608 progress 25 % (6 MB)
27 23:10:33.167026 progress 30 % (7 MB)
28 23:10:33.174348 progress 35 % (8 MB)
29 23:10:33.181365 progress 40 % (10 MB)
30 23:10:33.188352 progress 45 % (11 MB)
31 23:10:33.195297 progress 50 % (12 MB)
32 23:10:33.202241 progress 55 % (13 MB)
33 23:10:33.209157 progress 60 % (15 MB)
34 23:10:33.216070 progress 65 % (16 MB)
35 23:10:33.222904 progress 70 % (17 MB)
36 23:10:33.229868 progress 75 % (18 MB)
37 23:10:33.236750 progress 80 % (20 MB)
38 23:10:33.243549 progress 85 % (21 MB)
39 23:10:33.250285 progress 90 % (22 MB)
40 23:10:33.256940 progress 95 % (23 MB)
41 23:10:33.263643 progress 100 % (25 MB)
42 23:10:33.263889 25 MB downloaded in 0.17 s (148.65 MB/s)
43 23:10:33.264053 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:10:33.264314 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:10:33.264401 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:10:33.264485 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:10:33.264624 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:10:33.264692 saving as /var/lib/lava/dispatcher/tmp/12154446/tftp-deploy-g5gjd_yr/kernel/Image
50 23:10:33.264756 total size: 49172992 (46 MB)
51 23:10:33.264819 No compression specified
52 23:10:33.265924 progress 0 % (0 MB)
53 23:10:33.279208 progress 5 % (2 MB)
54 23:10:33.292463 progress 10 % (4 MB)
55 23:10:33.305270 progress 15 % (7 MB)
56 23:10:33.318162 progress 20 % (9 MB)
57 23:10:33.331179 progress 25 % (11 MB)
58 23:10:33.343947 progress 30 % (14 MB)
59 23:10:33.356561 progress 35 % (16 MB)
60 23:10:33.369525 progress 40 % (18 MB)
61 23:10:33.382594 progress 45 % (21 MB)
62 23:10:33.395478 progress 50 % (23 MB)
63 23:10:33.408223 progress 55 % (25 MB)
64 23:10:33.421181 progress 60 % (28 MB)
65 23:10:33.434306 progress 65 % (30 MB)
66 23:10:33.447337 progress 70 % (32 MB)
67 23:10:33.460272 progress 75 % (35 MB)
68 23:10:33.472906 progress 80 % (37 MB)
69 23:10:33.485781 progress 85 % (39 MB)
70 23:10:33.498640 progress 90 % (42 MB)
71 23:10:33.511225 progress 95 % (44 MB)
72 23:10:33.523996 progress 100 % (46 MB)
73 23:10:33.524221 46 MB downloaded in 0.26 s (180.74 MB/s)
74 23:10:33.524395 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:10:33.524749 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:10:33.524858 start: 1.3 download-retry (timeout 00:10:00) [common]
78 23:10:33.524959 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 23:10:33.525123 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:10:33.525201 saving as /var/lib/lava/dispatcher/tmp/12154446/tftp-deploy-g5gjd_yr/dtb/mt8192-asurada-spherion-r0.dtb
81 23:10:33.525285 total size: 47278 (0 MB)
82 23:10:33.525384 No compression specified
83 23:10:33.527089 progress 69 % (0 MB)
84 23:10:33.527397 progress 100 % (0 MB)
85 23:10:33.527575 0 MB downloaded in 0.00 s (19.70 MB/s)
86 23:10:33.527717 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:10:33.527969 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:10:33.528080 start: 1.4 download-retry (timeout 00:10:00) [common]
90 23:10:33.528182 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 23:10:33.528322 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.64-cip10/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:10:33.528419 saving as /var/lib/lava/dispatcher/tmp/12154446/tftp-deploy-g5gjd_yr/modules/modules.tar
93 23:10:33.528517 total size: 8616152 (8 MB)
94 23:10:33.528633 Using unxz to decompress xz
95 23:10:33.533017 progress 0 % (0 MB)
96 23:10:33.553971 progress 5 % (0 MB)
97 23:10:33.577536 progress 10 % (0 MB)
98 23:10:33.601164 progress 15 % (1 MB)
99 23:10:33.624975 progress 20 % (1 MB)
100 23:10:33.649840 progress 25 % (2 MB)
101 23:10:33.675784 progress 30 % (2 MB)
102 23:10:33.702329 progress 35 % (2 MB)
103 23:10:33.726441 progress 40 % (3 MB)
104 23:10:33.751564 progress 45 % (3 MB)
105 23:10:33.777598 progress 50 % (4 MB)
106 23:10:33.801932 progress 55 % (4 MB)
107 23:10:33.826591 progress 60 % (4 MB)
108 23:10:33.853533 progress 65 % (5 MB)
109 23:10:33.882074 progress 70 % (5 MB)
110 23:10:33.908312 progress 75 % (6 MB)
111 23:10:33.939192 progress 80 % (6 MB)
112 23:10:33.966625 progress 85 % (7 MB)
113 23:10:33.991536 progress 90 % (7 MB)
114 23:10:34.020919 progress 95 % (7 MB)
115 23:10:34.048574 progress 100 % (8 MB)
116 23:10:34.054895 8 MB downloaded in 0.53 s (15.61 MB/s)
117 23:10:34.055143 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:10:34.055417 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:10:34.055513 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:10:34.055611 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:10:34.055692 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:10:34.055779 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:10:34.056008 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1
125 23:10:34.056146 makedir: /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin
126 23:10:34.056254 makedir: /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/tests
127 23:10:34.056353 makedir: /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/results
128 23:10:34.056471 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-add-keys
129 23:10:34.056624 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-add-sources
130 23:10:34.056760 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-background-process-start
131 23:10:34.056893 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-background-process-stop
132 23:10:34.057023 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-common-functions
133 23:10:34.057151 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-echo-ipv4
134 23:10:34.057277 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-install-packages
135 23:10:34.057405 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-installed-packages
136 23:10:34.057531 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-os-build
137 23:10:34.057738 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-probe-channel
138 23:10:34.057865 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-probe-ip
139 23:10:34.057992 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-target-ip
140 23:10:34.058119 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-target-mac
141 23:10:34.058246 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-target-storage
142 23:10:34.058377 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-test-case
143 23:10:34.058508 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-test-event
144 23:10:34.058635 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-test-feedback
145 23:10:34.058761 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-test-raise
146 23:10:34.058891 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-test-reference
147 23:10:34.059018 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-test-runner
148 23:10:34.059145 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-test-set
149 23:10:34.059273 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-test-shell
150 23:10:34.059403 Updating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-install-packages (oe)
151 23:10:34.059556 Updating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/bin/lava-installed-packages (oe)
152 23:10:34.059688 Creating /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/environment
153 23:10:34.059793 LAVA metadata
154 23:10:34.059868 - LAVA_JOB_ID=12154446
155 23:10:34.059934 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:10:34.060038 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:10:34.060105 skipped lava-vland-overlay
158 23:10:34.060179 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:10:34.060259 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:10:34.060328 skipped lava-multinode-overlay
161 23:10:34.060403 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:10:34.060489 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:10:34.060565 Loading test definitions
164 23:10:34.060656 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:10:34.060731 Using /lava-12154446 at stage 0
166 23:10:34.061041 uuid=12154446_1.5.2.3.1 testdef=None
167 23:10:34.061129 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:10:34.061216 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:10:34.061783 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:10:34.062010 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:10:34.062641 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:10:34.062873 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:10:34.063473 runner path: /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/0/tests/0_v4l2-compliance-uvc test_uuid 12154446_1.5.2.3.1
176 23:10:34.063636 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:10:34.063848 Creating lava-test-runner.conf files
179 23:10:34.063912 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12154446/lava-overlay-cb383gx1/lava-12154446/0 for stage 0
180 23:10:34.064001 - 0_v4l2-compliance-uvc
181 23:10:34.064098 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:10:34.064182 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:10:34.071078 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:10:34.071205 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:10:34.071298 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:10:34.071386 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:10:34.071479 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:10:34.801045 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:10:34.801427 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 23:10:34.801548 extracting modules file /var/lib/lava/dispatcher/tmp/12154446/tftp-deploy-g5gjd_yr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12154446/extract-overlay-ramdisk-348jk8n0/ramdisk
191 23:10:35.034932 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:10:35.035111 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 23:10:35.035212 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154446/compress-overlay-o9tyroh8/overlay-1.5.2.4.tar.gz to ramdisk
194 23:10:35.035285 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12154446/compress-overlay-o9tyroh8/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12154446/extract-overlay-ramdisk-348jk8n0/ramdisk
195 23:10:35.043451 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:10:35.043566 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 23:10:35.043659 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:10:35.043750 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 23:10:35.043830 Building ramdisk /var/lib/lava/dispatcher/tmp/12154446/extract-overlay-ramdisk-348jk8n0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12154446/extract-overlay-ramdisk-348jk8n0/ramdisk
200 23:10:35.690806 >> 228439 blocks
201 23:10:39.550063 rename /var/lib/lava/dispatcher/tmp/12154446/extract-overlay-ramdisk-348jk8n0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12154446/tftp-deploy-g5gjd_yr/ramdisk/ramdisk.cpio.gz
202 23:10:39.550512 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 23:10:39.550651 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 23:10:39.550760 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 23:10:39.550868 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12154446/tftp-deploy-g5gjd_yr/kernel/Image'
206 23:10:51.456800 Returned 0 in 11 seconds
207 23:10:51.557805 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12154446/tftp-deploy-g5gjd_yr/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12154446/tftp-deploy-g5gjd_yr/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12154446/tftp-deploy-g5gjd_yr/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12154446/tftp-deploy-g5gjd_yr/kernel/image.itb
208 23:10:52.189655 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:10:52.190045 output: Created: Fri Dec 1 23:10:52 2023
210 23:10:52.190124 output: Image 0 (kernel-1)
211 23:10:52.190189 output: Description:
212 23:10:52.190252 output: Created: Fri Dec 1 23:10:52 2023
213 23:10:52.190316 output: Type: Kernel Image
214 23:10:52.190379 output: Compression: lzma compressed
215 23:10:52.190436 output: Data Size: 11043984 Bytes = 10785.14 KiB = 10.53 MiB
216 23:10:52.190493 output: Architecture: AArch64
217 23:10:52.190548 output: OS: Linux
218 23:10:52.190603 output: Load Address: 0x00000000
219 23:10:52.190657 output: Entry Point: 0x00000000
220 23:10:52.190711 output: Hash algo: crc32
221 23:10:52.190765 output: Hash value: 36c84243
222 23:10:52.190817 output: Image 1 (fdt-1)
223 23:10:52.190871 output: Description: mt8192-asurada-spherion-r0
224 23:10:52.190923 output: Created: Fri Dec 1 23:10:52 2023
225 23:10:52.190975 output: Type: Flat Device Tree
226 23:10:52.191026 output: Compression: uncompressed
227 23:10:52.191078 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 23:10:52.191131 output: Architecture: AArch64
229 23:10:52.191187 output: Hash algo: crc32
230 23:10:52.191282 output: Hash value: cc4352de
231 23:10:52.191363 output: Image 2 (ramdisk-1)
232 23:10:52.191415 output: Description: unavailable
233 23:10:52.191467 output: Created: Fri Dec 1 23:10:52 2023
234 23:10:52.191519 output: Type: RAMDisk Image
235 23:10:52.191570 output: Compression: Unknown Compression
236 23:10:52.191622 output: Data Size: 39360131 Bytes = 38437.63 KiB = 37.54 MiB
237 23:10:52.191674 output: Architecture: AArch64
238 23:10:52.191726 output: OS: Linux
239 23:10:52.191777 output: Load Address: unavailable
240 23:10:52.191829 output: Entry Point: unavailable
241 23:10:52.191881 output: Hash algo: crc32
242 23:10:52.191932 output: Hash value: 75d4c21c
243 23:10:52.191983 output: Default Configuration: 'conf-1'
244 23:10:52.192035 output: Configuration 0 (conf-1)
245 23:10:52.192086 output: Description: mt8192-asurada-spherion-r0
246 23:10:52.192138 output: Kernel: kernel-1
247 23:10:52.192190 output: Init Ramdisk: ramdisk-1
248 23:10:52.192241 output: FDT: fdt-1
249 23:10:52.192292 output: Loadables: kernel-1
250 23:10:52.192344 output:
251 23:10:52.192539 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 23:10:52.192635 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 23:10:52.192736 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 23:10:52.192828 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 23:10:52.192905 No LXC device requested
256 23:10:52.192984 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:10:52.193067 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 23:10:52.193144 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:10:52.193222 Checking files for TFTP limit of 4294967296 bytes.
260 23:10:52.193757 end: 1 tftp-deploy (duration 00:00:19) [common]
261 23:10:52.193859 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:10:52.193946 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:10:52.194068 substitutions:
264 23:10:52.194135 - {DTB}: 12154446/tftp-deploy-g5gjd_yr/dtb/mt8192-asurada-spherion-r0.dtb
265 23:10:52.194199 - {INITRD}: 12154446/tftp-deploy-g5gjd_yr/ramdisk/ramdisk.cpio.gz
266 23:10:52.194257 - {KERNEL}: 12154446/tftp-deploy-g5gjd_yr/kernel/Image
267 23:10:52.194314 - {LAVA_MAC}: None
268 23:10:52.194369 - {PRESEED_CONFIG}: None
269 23:10:52.194423 - {PRESEED_LOCAL}: None
270 23:10:52.194476 - {RAMDISK}: 12154446/tftp-deploy-g5gjd_yr/ramdisk/ramdisk.cpio.gz
271 23:10:52.194530 - {ROOT_PART}: None
272 23:10:52.194583 - {ROOT}: None
273 23:10:52.194635 - {SERVER_IP}: 192.168.201.1
274 23:10:52.194687 - {TEE}: None
275 23:10:52.194740 Parsed boot commands:
276 23:10:52.194793 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:10:52.194968 Parsed boot commands: tftpboot 192.168.201.1 12154446/tftp-deploy-g5gjd_yr/kernel/image.itb 12154446/tftp-deploy-g5gjd_yr/kernel/cmdline
278 23:10:52.195093 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:10:52.195183 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:10:52.195284 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:10:52.195367 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:10:52.195436 Not connected, no need to disconnect.
283 23:10:52.195507 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:10:52.195582 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:10:52.195646 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 23:10:52.199903 Setting prompt string to ['lava-test: # ']
287 23:10:52.200300 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:10:52.200427 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:10:52.200557 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:10:52.200647 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:10:52.200914 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 23:10:57.350929 >> Command sent successfully.
293 23:10:57.361508 Returned 0 in 5 seconds
294 23:10:57.462816 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:10:57.464459 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:10:57.465034 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:10:57.465504 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:10:57.466172 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:10:57.466752 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:10:57.468126 [Enter `^Ec?' for help]
302 23:10:57.627251
303 23:10:57.627855
304 23:10:57.628255 F0: 102B 0000
305 23:10:57.628652
306 23:10:57.628996 F3: 1001 0000 [0200]
307 23:10:57.630543
308 23:10:57.631018 F3: 1001 0000
309 23:10:57.631421
310 23:10:57.631772 F7: 102D 0000
311 23:10:57.632106
312 23:10:57.633870 F1: 0000 0000
313 23:10:57.634353
314 23:10:57.634724 V0: 0000 0000 [0001]
315 23:10:57.635070
316 23:10:57.637332 00: 0007 8000
317 23:10:57.638073
318 23:10:57.638457 01: 0000 0000
319 23:10:57.638820
320 23:10:57.640176 BP: 0C00 0209 [0000]
321 23:10:57.640644
322 23:10:57.641012 G0: 1182 0000
323 23:10:57.641360
324 23:10:57.643766 EC: 0000 0021 [4000]
325 23:10:57.644227
326 23:10:57.644598 S7: 0000 0000 [0000]
327 23:10:57.644942
328 23:10:57.647985 CC: 0000 0000 [0001]
329 23:10:57.648548
330 23:10:57.648925 T0: 0000 0040 [010F]
331 23:10:57.649273
332 23:10:57.649861 Jump to BL
333 23:10:57.650285
334 23:10:57.673873
335 23:10:57.674449
336 23:10:57.674820
337 23:10:57.681756 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 23:10:57.685149 ARM64: Exception handlers installed.
339 23:10:57.688993 ARM64: Testing exception
340 23:10:57.692312 ARM64: Done test exception
341 23:10:57.698940 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 23:10:57.708650 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 23:10:57.716081 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 23:10:57.725816 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 23:10:57.732520 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 23:10:57.739152 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 23:10:57.750580 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 23:10:57.757318 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 23:10:57.776865 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 23:10:57.780298 WDT: Last reset was cold boot
351 23:10:57.783274 SPI1(PAD0) initialized at 2873684 Hz
352 23:10:57.786909 SPI5(PAD0) initialized at 992727 Hz
353 23:10:57.790246 VBOOT: Loading verstage.
354 23:10:57.796775 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 23:10:57.801505 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 23:10:57.804524 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 23:10:57.808231 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 23:10:57.814542 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 23:10:57.821171 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 23:10:57.831649 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 23:10:57.832258
362 23:10:57.832645
363 23:10:57.842910 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 23:10:57.846193 ARM64: Exception handlers installed.
365 23:10:57.849106 ARM64: Testing exception
366 23:10:57.849732 ARM64: Done test exception
367 23:10:57.855487 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 23:10:57.859429 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 23:10:57.873126 Probing TPM: . done!
370 23:10:57.873750 TPM ready after 0 ms
371 23:10:57.880178 Connected to device vid:did:rid of 1ae0:0028:00
372 23:10:57.887162 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 23:10:57.946466 Initialized TPM device CR50 revision 0
374 23:10:57.957766 tlcl_send_startup: Startup return code is 0
375 23:10:57.958334 TPM: setup succeeded
376 23:10:57.969090 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 23:10:57.978155 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:10:57.990601 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 23:10:58.000245 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 23:10:58.003958 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 23:10:58.007467 in-header: 03 07 00 00 08 00 00 00
382 23:10:58.011885 in-data: aa e4 47 04 13 02 00 00
383 23:10:58.012474 Chrome EC: UHEPI supported
384 23:10:58.018396 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 23:10:58.023404 in-header: 03 95 00 00 08 00 00 00
386 23:10:58.027571 in-data: 18 20 20 08 00 00 00 00
387 23:10:58.028225 Phase 1
388 23:10:58.030764 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 23:10:58.038924 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 23:10:58.046263 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 23:10:58.046835 Recovery requested (1009000e)
392 23:10:58.057147 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 23:10:58.061702 tlcl_extend: response is 0
394 23:10:58.072307 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 23:10:58.077269 tlcl_extend: response is 0
396 23:10:58.083668 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 23:10:58.103681 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 23:10:58.109797 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 23:10:58.110352
400 23:10:58.110733
401 23:10:58.120294 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 23:10:58.123404 ARM64: Exception handlers installed.
403 23:10:58.126556 ARM64: Testing exception
404 23:10:58.127125 ARM64: Done test exception
405 23:10:58.149443 pmic_efuse_setting: Set efuses in 11 msecs
406 23:10:58.152716 pmwrap_interface_init: Select PMIF_VLD_RDY
407 23:10:58.158925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 23:10:58.162570 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 23:10:58.169881 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 23:10:58.173788 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 23:10:58.177936 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 23:10:58.181352 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 23:10:58.188385 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 23:10:58.192458 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 23:10:58.195960 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 23:10:58.199890 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 23:10:58.207474 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 23:10:58.211564 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 23:10:58.214909 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 23:10:58.222200 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 23:10:58.225756 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 23:10:58.233716 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 23:10:58.237740 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 23:10:58.244600 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 23:10:58.248604 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 23:10:58.255924 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 23:10:58.259659 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 23:10:58.267828 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 23:10:58.271363 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 23:10:58.278723 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 23:10:58.282535 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 23:10:58.290051 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 23:10:58.293739 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 23:10:58.297770 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 23:10:58.304857 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 23:10:58.308349 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 23:10:58.311687 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 23:10:58.318948 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 23:10:58.323012 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 23:10:58.326476 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 23:10:58.334360 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 23:10:58.337893 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 23:10:58.341404 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 23:10:58.349199 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 23:10:58.352323 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 23:10:58.356343 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 23:10:58.360165 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 23:10:58.367435 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 23:10:58.371312 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 23:10:58.374863 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 23:10:58.378219 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 23:10:58.382280 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 23:10:58.385868 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 23:10:58.392868 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 23:10:58.396556 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 23:10:58.400015 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 23:10:58.404205 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 23:10:58.411616 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 23:10:58.418707 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 23:10:58.426397 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 23:10:58.433717 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 23:10:58.441152 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 23:10:58.444751 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 23:10:58.452055 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:10:58.455700 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 23:10:58.463221 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde71, sec=0x29
467 23:10:58.466661 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 23:10:58.474269 [RTC]rtc_osc_init,62: osc32con val = 0xde71
469 23:10:58.478062 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 23:10:58.486845 [RTC]rtc_get_frequency_meter,154: input=15, output=760
471 23:10:58.496645 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 23:10:58.505557 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 23:10:58.515253 [RTC]rtc_get_frequency_meter,154: input=17, output=804
474 23:10:58.524896 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 23:10:58.534393 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 23:10:58.544372 [RTC]rtc_get_frequency_meter,154: input=17, output=806
477 23:10:58.548126 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 23:10:58.552597 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 23:10:58.556072 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 23:10:58.563234 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 23:10:58.567208 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 23:10:58.570360 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 23:10:58.574711 ADC[4]: Raw value=905465 ID=7
484 23:10:58.575278 ADC[3]: Raw value=213810 ID=1
485 23:10:58.577745 RAM Code: 0x71
486 23:10:58.581686 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 23:10:58.585325 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 23:10:58.596599 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 23:10:58.600445 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 23:10:58.603819 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 23:10:58.607533 in-header: 03 07 00 00 08 00 00 00
492 23:10:58.611551 in-data: aa e4 47 04 13 02 00 00
493 23:10:58.615220 Chrome EC: UHEPI supported
494 23:10:58.622145 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 23:10:58.626121 in-header: 03 95 00 00 08 00 00 00
496 23:10:58.630065 in-data: 18 20 20 08 00 00 00 00
497 23:10:58.630489 MRC: failed to locate region type 0.
498 23:10:58.637431 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 23:10:58.640778 DRAM-K: Running full calibration
500 23:10:58.648109 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 23:10:58.648624 header.status = 0x0
502 23:10:58.652078 header.version = 0x6 (expected: 0x6)
503 23:10:58.655915 header.size = 0xd00 (expected: 0xd00)
504 23:10:58.656334 header.flags = 0x0
505 23:10:58.662773 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 23:10:58.681017 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 23:10:58.689203 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 23:10:58.692462 dram_init: ddr_geometry: 2
509 23:10:58.692887 [EMI] MDL number = 2
510 23:10:58.696579 [EMI] Get MDL freq = 0
511 23:10:58.697128 dram_init: ddr_type: 0
512 23:10:58.700016 is_discrete_lpddr4: 1
513 23:10:58.703156 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 23:10:58.703630
515 23:10:58.704013
516 23:10:58.707100 [Bian_co] ETT version 0.0.0.1
517 23:10:58.710517 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 23:10:58.710946
519 23:10:58.714180 dramc_set_vcore_voltage set vcore to 650000
520 23:10:58.714608 Read voltage for 800, 4
521 23:10:58.717913 Vio18 = 0
522 23:10:58.718337 Vcore = 650000
523 23:10:58.718681 Vdram = 0
524 23:10:58.721931 Vddq = 0
525 23:10:58.722373 Vmddr = 0
526 23:10:58.722715 dram_init: config_dvfs: 1
527 23:10:58.729435 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 23:10:58.732812 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 23:10:58.736663 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 23:10:58.740751 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 23:10:58.744515 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 23:10:58.748487 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 23:10:58.752354 MEM_TYPE=3, freq_sel=18
534 23:10:58.756208 sv_algorithm_assistance_LP4_1600
535 23:10:58.759028 ============ PULL DRAM RESETB DOWN ============
536 23:10:58.762061 ========== PULL DRAM RESETB DOWN end =========
537 23:10:58.765410 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 23:10:58.769148 ===================================
539 23:10:58.773121 LPDDR4 DRAM CONFIGURATION
540 23:10:58.776196 ===================================
541 23:10:58.779541 EX_ROW_EN[0] = 0x0
542 23:10:58.780009 EX_ROW_EN[1] = 0x0
543 23:10:58.783076 LP4Y_EN = 0x0
544 23:10:58.783544 WORK_FSP = 0x0
545 23:10:58.786777 WL = 0x2
546 23:10:58.787408 RL = 0x2
547 23:10:58.790235 BL = 0x2
548 23:10:58.790767 RPST = 0x0
549 23:10:58.794336 RD_PRE = 0x0
550 23:10:58.794930 WR_PRE = 0x1
551 23:10:58.795450 WR_PST = 0x0
552 23:10:58.797638 DBI_WR = 0x0
553 23:10:58.798111 DBI_RD = 0x0
554 23:10:58.801405 OTF = 0x1
555 23:10:58.803846 ===================================
556 23:10:58.807752 ===================================
557 23:10:58.808323 ANA top config
558 23:10:58.810605 ===================================
559 23:10:58.813902 DLL_ASYNC_EN = 0
560 23:10:58.817477 ALL_SLAVE_EN = 1
561 23:10:58.820995 NEW_RANK_MODE = 1
562 23:10:58.821571 DLL_IDLE_MODE = 1
563 23:10:58.824116 LP45_APHY_COMB_EN = 1
564 23:10:58.827845 TX_ODT_DIS = 1
565 23:10:58.830951 NEW_8X_MODE = 1
566 23:10:58.834542 ===================================
567 23:10:58.838103 ===================================
568 23:10:58.838576 data_rate = 1600
569 23:10:58.841545 CKR = 1
570 23:10:58.845159 DQ_P2S_RATIO = 8
571 23:10:58.848072 ===================================
572 23:10:58.851597 CA_P2S_RATIO = 8
573 23:10:58.854928 DQ_CA_OPEN = 0
574 23:10:58.858052 DQ_SEMI_OPEN = 0
575 23:10:58.858530 CA_SEMI_OPEN = 0
576 23:10:58.861428 CA_FULL_RATE = 0
577 23:10:58.864525 DQ_CKDIV4_EN = 1
578 23:10:58.868260 CA_CKDIV4_EN = 1
579 23:10:58.871087 CA_PREDIV_EN = 0
580 23:10:58.871512 PH8_DLY = 0
581 23:10:58.875017 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 23:10:58.878052 DQ_AAMCK_DIV = 4
583 23:10:58.881103 CA_AAMCK_DIV = 4
584 23:10:58.884557 CA_ADMCK_DIV = 4
585 23:10:58.888480 DQ_TRACK_CA_EN = 0
586 23:10:58.891656 CA_PICK = 800
587 23:10:58.892186 CA_MCKIO = 800
588 23:10:58.895142 MCKIO_SEMI = 0
589 23:10:58.898558 PLL_FREQ = 3068
590 23:10:58.902468 DQ_UI_PI_RATIO = 32
591 23:10:58.905783 CA_UI_PI_RATIO = 0
592 23:10:58.906213 ===================================
593 23:10:58.909817 ===================================
594 23:10:58.913252 memory_type:LPDDR4
595 23:10:58.917412 GP_NUM : 10
596 23:10:58.917925 SRAM_EN : 1
597 23:10:58.921238 MD32_EN : 0
598 23:10:58.921779 ===================================
599 23:10:58.924587 [ANA_INIT] >>>>>>>>>>>>>>
600 23:10:58.928862 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 23:10:58.932366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 23:10:58.935179 ===================================
603 23:10:58.938708 data_rate = 1600,PCW = 0X7600
604 23:10:58.942094 ===================================
605 23:10:58.945693 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 23:10:58.949158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:10:58.955503 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 23:10:58.958482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 23:10:58.962240 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:10:58.965446 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 23:10:58.968621 [ANA_INIT] flow start
612 23:10:58.972331 [ANA_INIT] PLL >>>>>>>>
613 23:10:58.972853 [ANA_INIT] PLL <<<<<<<<
614 23:10:58.975620 [ANA_INIT] MIDPI >>>>>>>>
615 23:10:58.978651 [ANA_INIT] MIDPI <<<<<<<<
616 23:10:58.979082 [ANA_INIT] DLL >>>>>>>>
617 23:10:58.982034 [ANA_INIT] flow end
618 23:10:58.985721 ============ LP4 DIFF to SE enter ============
619 23:10:58.989275 ============ LP4 DIFF to SE exit ============
620 23:10:58.992218 [ANA_INIT] <<<<<<<<<<<<<
621 23:10:58.996296 [Flow] Enable top DCM control >>>>>
622 23:10:58.998769 [Flow] Enable top DCM control <<<<<
623 23:10:59.002441 Enable DLL master slave shuffle
624 23:10:59.009355 ==============================================================
625 23:10:59.009985 Gating Mode config
626 23:10:59.016061 ==============================================================
627 23:10:59.016623 Config description:
628 23:10:59.025900 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 23:10:59.032495 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 23:10:59.038990 SELPH_MODE 0: By rank 1: By Phase
631 23:10:59.042412 ==============================================================
632 23:10:59.046157 GAT_TRACK_EN = 1
633 23:10:59.049443 RX_GATING_MODE = 2
634 23:10:59.052843 RX_GATING_TRACK_MODE = 2
635 23:10:59.055777 SELPH_MODE = 1
636 23:10:59.059621 PICG_EARLY_EN = 1
637 23:10:59.062928 VALID_LAT_VALUE = 1
638 23:10:59.065537 ==============================================================
639 23:10:59.069027 Enter into Gating configuration >>>>
640 23:10:59.072387 Exit from Gating configuration <<<<
641 23:10:59.075917 Enter into DVFS_PRE_config >>>>>
642 23:10:59.089227 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 23:10:59.089859 Exit from DVFS_PRE_config <<<<<
644 23:10:59.092503 Enter into PICG configuration >>>>
645 23:10:59.096203 Exit from PICG configuration <<<<
646 23:10:59.099278 [RX_INPUT] configuration >>>>>
647 23:10:59.102718 [RX_INPUT] configuration <<<<<
648 23:10:59.109374 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 23:10:59.112868 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 23:10:59.120157 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 23:10:59.126157 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 23:10:59.132863 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 23:10:59.139391 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 23:10:59.142646 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 23:10:59.146516 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 23:10:59.149507 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 23:10:59.156244 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 23:10:59.159690 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 23:10:59.163162 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 23:10:59.166387 ===================================
661 23:10:59.169686 LPDDR4 DRAM CONFIGURATION
662 23:10:59.172866 ===================================
663 23:10:59.173433 EX_ROW_EN[0] = 0x0
664 23:10:59.176642 EX_ROW_EN[1] = 0x0
665 23:10:59.177217 LP4Y_EN = 0x0
666 23:10:59.179465 WORK_FSP = 0x0
667 23:10:59.182841 WL = 0x2
668 23:10:59.183459 RL = 0x2
669 23:10:59.185922 BL = 0x2
670 23:10:59.186492 RPST = 0x0
671 23:10:59.189493 RD_PRE = 0x0
672 23:10:59.190114 WR_PRE = 0x1
673 23:10:59.192635 WR_PST = 0x0
674 23:10:59.193203 DBI_WR = 0x0
675 23:10:59.196067 DBI_RD = 0x0
676 23:10:59.196635 OTF = 0x1
677 23:10:59.199059 ===================================
678 23:10:59.202347 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 23:10:59.209643 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 23:10:59.212636 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 23:10:59.215549 ===================================
682 23:10:59.219102 LPDDR4 DRAM CONFIGURATION
683 23:10:59.222476 ===================================
684 23:10:59.222996 EX_ROW_EN[0] = 0x10
685 23:10:59.225937 EX_ROW_EN[1] = 0x0
686 23:10:59.226406 LP4Y_EN = 0x0
687 23:10:59.229699 WORK_FSP = 0x0
688 23:10:59.230269 WL = 0x2
689 23:10:59.232979 RL = 0x2
690 23:10:59.233547 BL = 0x2
691 23:10:59.236015 RPST = 0x0
692 23:10:59.236486 RD_PRE = 0x0
693 23:10:59.239448 WR_PRE = 0x1
694 23:10:59.242531 WR_PST = 0x0
695 23:10:59.243004 DBI_WR = 0x0
696 23:10:59.245965 DBI_RD = 0x0
697 23:10:59.246448 OTF = 0x1
698 23:10:59.249437 ===================================
699 23:10:59.256340 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 23:10:59.259832 nWR fixed to 40
701 23:10:59.263691 [ModeRegInit_LP4] CH0 RK0
702 23:10:59.264297 [ModeRegInit_LP4] CH0 RK1
703 23:10:59.266232 [ModeRegInit_LP4] CH1 RK0
704 23:10:59.269513 [ModeRegInit_LP4] CH1 RK1
705 23:10:59.270167 match AC timing 13
706 23:10:59.276130 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 23:10:59.279324 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 23:10:59.282924 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 23:10:59.289696 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 23:10:59.292725 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 23:10:59.293298 [EMI DOE] emi_dcm 0
712 23:10:59.299845 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 23:10:59.300428 ==
714 23:10:59.302633 Dram Type= 6, Freq= 0, CH_0, rank 0
715 23:10:59.306101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 23:10:59.306845 ==
717 23:10:59.312569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 23:10:59.318952 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 23:10:59.326741 [CA 0] Center 36 (6~67) winsize 62
720 23:10:59.330621 [CA 1] Center 36 (6~67) winsize 62
721 23:10:59.333782 [CA 2] Center 34 (3~65) winsize 63
722 23:10:59.336882 [CA 3] Center 33 (3~64) winsize 62
723 23:10:59.340146 [CA 4] Center 33 (3~63) winsize 61
724 23:10:59.343876 [CA 5] Center 32 (2~62) winsize 61
725 23:10:59.344507
726 23:10:59.347165 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 23:10:59.347678
728 23:10:59.350696 [CATrainingPosCal] consider 1 rank data
729 23:10:59.353714 u2DelayCellTimex100 = 270/100 ps
730 23:10:59.357240 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 23:10:59.360873 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 23:10:59.367089 CA2 delay=34 (3~65),Diff = 2 PI (14 cell)
733 23:10:59.370149 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 23:10:59.373820 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
735 23:10:59.376995 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 23:10:59.377560
737 23:10:59.380498 CA PerBit enable=1, Macro0, CA PI delay=32
738 23:10:59.381070
739 23:10:59.383359 [CBTSetCACLKResult] CA Dly = 32
740 23:10:59.383926 CS Dly: 4 (0~35)
741 23:10:59.384303 ==
742 23:10:59.386860 Dram Type= 6, Freq= 0, CH_0, rank 1
743 23:10:59.393333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 23:10:59.393921 ==
745 23:10:59.396731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 23:10:59.403718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 23:10:59.413070 [CA 0] Center 36 (6~67) winsize 62
748 23:10:59.416407 [CA 1] Center 36 (6~67) winsize 62
749 23:10:59.419558 [CA 2] Center 34 (4~65) winsize 62
750 23:10:59.423020 [CA 3] Center 34 (4~65) winsize 62
751 23:10:59.426115 [CA 4] Center 33 (2~64) winsize 63
752 23:10:59.429103 [CA 5] Center 32 (2~63) winsize 62
753 23:10:59.429572
754 23:10:59.432871 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 23:10:59.433341
756 23:10:59.436044 [CATrainingPosCal] consider 2 rank data
757 23:10:59.439504 u2DelayCellTimex100 = 270/100 ps
758 23:10:59.442748 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 23:10:59.449667 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 23:10:59.452850 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 23:10:59.456177 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 23:10:59.460059 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 23:10:59.462862 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 23:10:59.463428
765 23:10:59.466392 CA PerBit enable=1, Macro0, CA PI delay=32
766 23:10:59.466988
767 23:10:59.469768 [CBTSetCACLKResult] CA Dly = 32
768 23:10:59.470335 CS Dly: 5 (0~37)
769 23:10:59.473552
770 23:10:59.474173 ----->DramcWriteLeveling(PI) begin...
771 23:10:59.474582 ==
772 23:10:59.476461 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:10:59.483985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 23:10:59.484552 ==
775 23:10:59.484927 Write leveling (Byte 0): 36 => 36
776 23:10:59.487924 Write leveling (Byte 1): 29 => 29
777 23:10:59.491378 DramcWriteLeveling(PI) end<-----
778 23:10:59.491941
779 23:10:59.492315 ==
780 23:10:59.494340 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:10:59.498276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:10:59.501532 ==
783 23:10:59.502148 [Gating] SW mode calibration
784 23:10:59.508782 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 23:10:59.514890 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 23:10:59.518317 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 23:10:59.521662 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 23:10:59.528315 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 23:10:59.531750 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:10:59.534809 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:10:59.541649 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:10:59.545147 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:10:59.548170 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:10:59.554878 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:10:59.558164 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:10:59.561899 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:10:59.568570 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:10:59.572012 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:10:59.575361 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:10:59.581661 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:10:59.585181 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:10:59.588833 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:10:59.595291 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 23:10:59.598874 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 23:10:59.601785 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 23:10:59.605096 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:10:59.612029 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:10:59.615544 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:10:59.618397 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:10:59.625298 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:10:59.628522 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:10:59.632178 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
813 23:10:59.638749 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 23:10:59.641809 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:10:59.645636 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:10:59.652222 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:10:59.655243 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:10:59.658842 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 23:10:59.665663 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
820 23:10:59.668886 0 10 8 | B1->B0 | 3333 2424 | 0 0 | (0 1) (1 0)
821 23:10:59.672202 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
822 23:10:59.679281 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:10:59.682365 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:10:59.685795 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:10:59.688790 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:10:59.695950 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:10:59.698999 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
828 23:10:59.702364 0 11 8 | B1->B0 | 2f2f 3e3e | 0 0 | (1 1) (0 0)
829 23:10:59.708940 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
830 23:10:59.712560 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:10:59.716169 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:10:59.722734 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:10:59.725261 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:10:59.729126 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:10:59.736221 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 23:10:59.739133 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 23:10:59.742576 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:10:59.745809 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:10:59.752463 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:10:59.755729 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:10:59.759170 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:10:59.765658 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:10:59.769225 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:10:59.772948 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:10:59.779398 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:10:59.782963 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:10:59.785753 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:10:59.792738 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:10:59.796407 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:10:59.800018 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:10:59.806285 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 23:10:59.809434 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 23:10:59.812635 Total UI for P1: 0, mck2ui 16
854 23:10:59.816254 best dqsien dly found for B0: ( 0, 14, 6)
855 23:10:59.819955 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 23:10:59.822778 Total UI for P1: 0, mck2ui 16
857 23:10:59.826158 best dqsien dly found for B1: ( 0, 14, 8)
858 23:10:59.829657 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 23:10:59.832864 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 23:10:59.833415
861 23:10:59.836468 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 23:10:59.839834 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 23:10:59.842912 [Gating] SW calibration Done
864 23:10:59.843381 ==
865 23:10:59.846356 Dram Type= 6, Freq= 0, CH_0, rank 0
866 23:10:59.850002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 23:10:59.852937 ==
868 23:10:59.853489 RX Vref Scan: 0
869 23:10:59.853941
870 23:10:59.856442 RX Vref 0 -> 0, step: 1
871 23:10:59.856909
872 23:10:59.859721 RX Delay -130 -> 252, step: 16
873 23:10:59.862903 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 23:10:59.866274 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 23:10:59.869995 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
876 23:10:59.873568 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
877 23:10:59.879646 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 23:10:59.883052 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 23:10:59.886780 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 23:10:59.889981 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 23:10:59.892948 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 23:10:59.896364 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
883 23:10:59.902819 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
884 23:10:59.906826 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 23:10:59.910179 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
886 23:10:59.912914 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 23:10:59.920048 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 23:10:59.923238 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
889 23:10:59.923668 ==
890 23:10:59.926752 Dram Type= 6, Freq= 0, CH_0, rank 0
891 23:10:59.929671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 23:10:59.930132 ==
893 23:10:59.930480 DQS Delay:
894 23:10:59.933127 DQS0 = 0, DQS1 = 0
895 23:10:59.933555 DQM Delay:
896 23:10:59.936333 DQM0 = 92, DQM1 = 86
897 23:10:59.936761 DQ Delay:
898 23:10:59.939755 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
899 23:10:59.943278 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
900 23:10:59.946956 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
901 23:10:59.949655 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 23:10:59.950087
903 23:10:59.950430
904 23:10:59.950748 ==
905 23:10:59.953198 Dram Type= 6, Freq= 0, CH_0, rank 0
906 23:10:59.956526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 23:10:59.959872 ==
908 23:10:59.960429
909 23:10:59.960780
910 23:10:59.961105 TX Vref Scan disable
911 23:10:59.963052 == TX Byte 0 ==
912 23:10:59.966445 Update DQ dly =587 (2 ,2, 11) DQ OEN =(1 ,7)
913 23:10:59.969853 Update DQM dly =587 (2 ,2, 11) DQM OEN =(1 ,7)
914 23:10:59.973074 == TX Byte 1 ==
915 23:10:59.976621 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 23:10:59.979560 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 23:10:59.984110 ==
918 23:10:59.984695 Dram Type= 6, Freq= 0, CH_0, rank 0
919 23:10:59.990064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 23:10:59.990498 ==
921 23:11:00.003010 TX Vref=22, minBit 10, minWin=27, winSum=449
922 23:11:00.006128 TX Vref=24, minBit 8, minWin=27, winSum=449
923 23:11:00.009355 TX Vref=26, minBit 4, minWin=28, winSum=456
924 23:11:00.013043 TX Vref=28, minBit 5, minWin=28, winSum=457
925 23:11:00.016231 TX Vref=30, minBit 5, minWin=28, winSum=460
926 23:11:00.022549 TX Vref=32, minBit 5, minWin=28, winSum=456
927 23:11:00.025986 [TxChooseVref] Worse bit 5, Min win 28, Win sum 460, Final Vref 30
928 23:11:00.026463
929 23:11:00.029779 Final TX Range 1 Vref 30
930 23:11:00.030358
931 23:11:00.030737 ==
932 23:11:00.033233 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:11:00.036104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:11:00.036691 ==
935 23:11:00.039842
936 23:11:00.040312
937 23:11:00.040688 TX Vref Scan disable
938 23:11:00.043067 == TX Byte 0 ==
939 23:11:00.046868 Update DQ dly =587 (2 ,2, 11) DQ OEN =(1 ,7)
940 23:11:00.049689 Update DQM dly =587 (2 ,2, 11) DQM OEN =(1 ,7)
941 23:11:00.053345 == TX Byte 1 ==
942 23:11:00.056037 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 23:11:00.060078 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 23:11:00.063135
945 23:11:00.063602 [DATLAT]
946 23:11:00.064032 Freq=800, CH0 RK0
947 23:11:00.064406
948 23:11:00.066226 DATLAT Default: 0xa
949 23:11:00.066694 0, 0xFFFF, sum = 0
950 23:11:00.069491 1, 0xFFFF, sum = 0
951 23:11:00.070029 2, 0xFFFF, sum = 0
952 23:11:00.073112 3, 0xFFFF, sum = 0
953 23:11:00.073743 4, 0xFFFF, sum = 0
954 23:11:00.076073 5, 0xFFFF, sum = 0
955 23:11:00.076550 6, 0xFFFF, sum = 0
956 23:11:00.079768 7, 0xFFFF, sum = 0
957 23:11:00.083096 8, 0xFFFF, sum = 0
958 23:11:00.083572 9, 0x0, sum = 1
959 23:11:00.083953 10, 0x0, sum = 2
960 23:11:00.086784 11, 0x0, sum = 3
961 23:11:00.087303 12, 0x0, sum = 4
962 23:11:00.089717 best_step = 10
963 23:11:00.090197
964 23:11:00.090574 ==
965 23:11:00.093106 Dram Type= 6, Freq= 0, CH_0, rank 0
966 23:11:00.096695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 23:11:00.097271 ==
968 23:11:00.099726 RX Vref Scan: 1
969 23:11:00.100341
970 23:11:00.100729 Set Vref Range= 32 -> 127
971 23:11:00.101083
972 23:11:00.103078 RX Vref 32 -> 127, step: 1
973 23:11:00.103654
974 23:11:00.106094 RX Delay -79 -> 252, step: 8
975 23:11:00.106758
976 23:11:00.109501 Set Vref, RX VrefLevel [Byte0]: 32
977 23:11:00.112896 [Byte1]: 32
978 23:11:00.113365
979 23:11:00.116587 Set Vref, RX VrefLevel [Byte0]: 33
980 23:11:00.119570 [Byte1]: 33
981 23:11:00.122946
982 23:11:00.123413 Set Vref, RX VrefLevel [Byte0]: 34
983 23:11:00.126449 [Byte1]: 34
984 23:11:00.130774
985 23:11:00.131238 Set Vref, RX VrefLevel [Byte0]: 35
986 23:11:00.134029 [Byte1]: 35
987 23:11:00.138692
988 23:11:00.139272 Set Vref, RX VrefLevel [Byte0]: 36
989 23:11:00.141695 [Byte1]: 36
990 23:11:00.145570
991 23:11:00.149319 Set Vref, RX VrefLevel [Byte0]: 37
992 23:11:00.149852 [Byte1]: 37
993 23:11:00.154011
994 23:11:00.154576 Set Vref, RX VrefLevel [Byte0]: 38
995 23:11:00.157089 [Byte1]: 38
996 23:11:00.161494
997 23:11:00.162110 Set Vref, RX VrefLevel [Byte0]: 39
998 23:11:00.164771 [Byte1]: 39
999 23:11:00.168892
1000 23:11:00.169361 Set Vref, RX VrefLevel [Byte0]: 40
1001 23:11:00.172541 [Byte1]: 40
1002 23:11:00.176411
1003 23:11:00.176980 Set Vref, RX VrefLevel [Byte0]: 41
1004 23:11:00.179666 [Byte1]: 41
1005 23:11:00.183753
1006 23:11:00.184331 Set Vref, RX VrefLevel [Byte0]: 42
1007 23:11:00.187127 [Byte1]: 42
1008 23:11:00.191807
1009 23:11:00.192384 Set Vref, RX VrefLevel [Byte0]: 43
1010 23:11:00.194423 [Byte1]: 43
1011 23:11:00.198998
1012 23:11:00.199568 Set Vref, RX VrefLevel [Byte0]: 44
1013 23:11:00.201658 [Byte1]: 44
1014 23:11:00.206238
1015 23:11:00.206842 Set Vref, RX VrefLevel [Byte0]: 45
1016 23:11:00.209573 [Byte1]: 45
1017 23:11:00.213556
1018 23:11:00.214076 Set Vref, RX VrefLevel [Byte0]: 46
1019 23:11:00.217040 [Byte1]: 46
1020 23:11:00.221233
1021 23:11:00.221751 Set Vref, RX VrefLevel [Byte0]: 47
1022 23:11:00.224537 [Byte1]: 47
1023 23:11:00.229279
1024 23:11:00.229909 Set Vref, RX VrefLevel [Byte0]: 48
1025 23:11:00.232067 [Byte1]: 48
1026 23:11:00.236543
1027 23:11:00.237108 Set Vref, RX VrefLevel [Byte0]: 49
1028 23:11:00.239823 [Byte1]: 49
1029 23:11:00.243925
1030 23:11:00.244484 Set Vref, RX VrefLevel [Byte0]: 50
1031 23:11:00.246934 [Byte1]: 50
1032 23:11:00.251813
1033 23:11:00.252375 Set Vref, RX VrefLevel [Byte0]: 51
1034 23:11:00.254974 [Byte1]: 51
1035 23:11:00.259500
1036 23:11:00.260067 Set Vref, RX VrefLevel [Byte0]: 52
1037 23:11:00.262219 [Byte1]: 52
1038 23:11:00.266550
1039 23:11:00.267118 Set Vref, RX VrefLevel [Byte0]: 53
1040 23:11:00.270214 [Byte1]: 53
1041 23:11:00.274165
1042 23:11:00.274677 Set Vref, RX VrefLevel [Byte0]: 54
1043 23:11:00.277516 [Byte1]: 54
1044 23:11:00.282159
1045 23:11:00.282721 Set Vref, RX VrefLevel [Byte0]: 55
1046 23:11:00.285758 [Byte1]: 55
1047 23:11:00.289222
1048 23:11:00.289824 Set Vref, RX VrefLevel [Byte0]: 56
1049 23:11:00.292552 [Byte1]: 56
1050 23:11:00.297252
1051 23:11:00.297856 Set Vref, RX VrefLevel [Byte0]: 57
1052 23:11:00.300457 [Byte1]: 57
1053 23:11:00.304767
1054 23:11:00.305331 Set Vref, RX VrefLevel [Byte0]: 58
1055 23:11:00.307733 [Byte1]: 58
1056 23:11:00.311571
1057 23:11:00.312039 Set Vref, RX VrefLevel [Byte0]: 59
1058 23:11:00.315642 [Byte1]: 59
1059 23:11:00.319578
1060 23:11:00.320038 Set Vref, RX VrefLevel [Byte0]: 60
1061 23:11:00.322458 [Byte1]: 60
1062 23:11:00.327362
1063 23:11:00.327820 Set Vref, RX VrefLevel [Byte0]: 61
1064 23:11:00.331248 [Byte1]: 61
1065 23:11:00.334571
1066 23:11:00.335032 Set Vref, RX VrefLevel [Byte0]: 62
1067 23:11:00.338242 [Byte1]: 62
1068 23:11:00.342577
1069 23:11:00.343139 Set Vref, RX VrefLevel [Byte0]: 63
1070 23:11:00.345976 [Byte1]: 63
1071 23:11:00.349508
1072 23:11:00.350039 Set Vref, RX VrefLevel [Byte0]: 64
1073 23:11:00.352861 [Byte1]: 64
1074 23:11:00.357077
1075 23:11:00.357658 Set Vref, RX VrefLevel [Byte0]: 65
1076 23:11:00.360335 [Byte1]: 65
1077 23:11:00.364724
1078 23:11:00.365277 Set Vref, RX VrefLevel [Byte0]: 66
1079 23:11:00.368170 [Byte1]: 66
1080 23:11:00.372411
1081 23:11:00.372872 Set Vref, RX VrefLevel [Byte0]: 67
1082 23:11:00.376082 [Byte1]: 67
1083 23:11:00.379718
1084 23:11:00.380182 Set Vref, RX VrefLevel [Byte0]: 68
1085 23:11:00.383367 [Byte1]: 68
1086 23:11:00.387792
1087 23:11:00.388347 Set Vref, RX VrefLevel [Byte0]: 69
1088 23:11:00.390937 [Byte1]: 69
1089 23:11:00.394860
1090 23:11:00.395412 Set Vref, RX VrefLevel [Byte0]: 70
1091 23:11:00.398149 [Byte1]: 70
1092 23:11:00.402579
1093 23:11:00.403134 Set Vref, RX VrefLevel [Byte0]: 71
1094 23:11:00.405996 [Byte1]: 71
1095 23:11:00.410459
1096 23:11:00.411027 Set Vref, RX VrefLevel [Byte0]: 72
1097 23:11:00.413467 [Byte1]: 72
1098 23:11:00.418075
1099 23:11:00.418634 Set Vref, RX VrefLevel [Byte0]: 73
1100 23:11:00.421154 [Byte1]: 73
1101 23:11:00.425177
1102 23:11:00.428523 Set Vref, RX VrefLevel [Byte0]: 74
1103 23:11:00.431497 [Byte1]: 74
1104 23:11:00.432057
1105 23:11:00.434846 Set Vref, RX VrefLevel [Byte0]: 75
1106 23:11:00.438541 [Byte1]: 75
1107 23:11:00.439106
1108 23:11:00.441771 Set Vref, RX VrefLevel [Byte0]: 76
1109 23:11:00.444697 [Byte1]: 76
1110 23:11:00.445157
1111 23:11:00.448389 Set Vref, RX VrefLevel [Byte0]: 77
1112 23:11:00.451944 [Byte1]: 77
1113 23:11:00.455596
1114 23:11:00.456051 Final RX Vref Byte 0 = 59 to rank0
1115 23:11:00.458534 Final RX Vref Byte 1 = 60 to rank0
1116 23:11:00.462296 Final RX Vref Byte 0 = 59 to rank1
1117 23:11:00.465728 Final RX Vref Byte 1 = 60 to rank1==
1118 23:11:00.468423 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 23:11:00.472288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 23:11:00.475328 ==
1121 23:11:00.475896 DQS Delay:
1122 23:11:00.476266 DQS0 = 0, DQS1 = 0
1123 23:11:00.478578 DQM Delay:
1124 23:11:00.479057 DQM0 = 92, DQM1 = 86
1125 23:11:00.482421 DQ Delay:
1126 23:11:00.485652 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1127 23:11:00.488441 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1128 23:11:00.488906 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =76
1129 23:11:00.495663 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1130 23:11:00.496230
1131 23:11:00.496599
1132 23:11:00.502324 [DQSOSCAuto] RK0, (LSB)MR18= 0x483e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
1133 23:11:00.505494 CH0 RK0: MR19=606, MR18=483E
1134 23:11:00.511860 CH0_RK0: MR19=0x606, MR18=0x483E, DQSOSC=391, MR23=63, INC=96, DEC=64
1135 23:11:00.512321
1136 23:11:00.515417 ----->DramcWriteLeveling(PI) begin...
1137 23:11:00.515884 ==
1138 23:11:00.518755 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 23:11:00.522726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 23:11:00.523311 ==
1141 23:11:00.525526 Write leveling (Byte 0): 33 => 33
1142 23:11:00.528772 Write leveling (Byte 1): 32 => 32
1143 23:11:00.531836 DramcWriteLeveling(PI) end<-----
1144 23:11:00.532419
1145 23:11:00.532785 ==
1146 23:11:00.535256 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 23:11:00.538783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 23:11:00.539246 ==
1149 23:11:00.541789 [Gating] SW mode calibration
1150 23:11:00.589434 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 23:11:00.590049 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 23:11:00.590425 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 23:11:00.590774 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 23:11:00.591482 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 23:11:00.591849 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:11:00.592180 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:11:00.592499 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:11:00.592812 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:11:00.593126 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:11:00.633681 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:11:00.634676 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:11:00.635169 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:11:00.635529 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:11:00.635865 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:11:00.636364 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:11:00.636716 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:11:00.637043 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:11:00.637357 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:11:00.637728 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1170 23:11:00.660984 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 23:11:00.661636 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:11:00.662393 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:11:00.662775 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:11:00.663117 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:11:00.663447 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:11:00.665421 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:11:00.668611 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:11:00.671678 0 9 8 | B1->B0 | 2a2a 2828 | 0 1 | (0 0) (1 1)
1179 23:11:00.678548 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 23:11:00.681994 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 23:11:00.685555 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 23:11:00.691947 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 23:11:00.695029 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 23:11:00.698556 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 23:11:00.705307 0 10 4 | B1->B0 | 3232 3333 | 1 0 | (1 1) (0 0)
1186 23:11:00.708466 0 10 8 | B1->B0 | 2c2c 2a2a | 0 0 | (0 0) (1 0)
1187 23:11:00.711721 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:11:00.719011 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:11:00.722475 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:11:00.726165 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 23:11:00.729986 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 23:11:00.733629 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 23:11:00.740124 0 11 4 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
1194 23:11:00.743731 0 11 8 | B1->B0 | 3b3b 3838 | 1 0 | (0 0) (0 0)
1195 23:11:00.747201 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 23:11:00.750783 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:11:00.757743 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 23:11:00.760780 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 23:11:00.764162 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 23:11:00.770533 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 23:11:00.774441 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 23:11:00.777627 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 23:11:00.783831 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:11:00.787647 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:11:00.790760 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:11:00.797492 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:11:00.801089 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:11:00.804812 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:11:00.811132 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:11:00.813934 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:11:00.817437 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:11:00.820959 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:11:00.827227 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:11:00.831094 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:11:00.833998 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:11:00.840813 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 23:11:00.844574 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 23:11:00.847483 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1219 23:11:00.854417 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 23:11:00.857875 Total UI for P1: 0, mck2ui 16
1221 23:11:00.861464 best dqsien dly found for B0: ( 0, 14, 10)
1222 23:11:00.862085 Total UI for P1: 0, mck2ui 16
1223 23:11:00.867179 best dqsien dly found for B1: ( 0, 14, 8)
1224 23:11:00.870620 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1225 23:11:00.874450 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 23:11:00.875002
1227 23:11:00.877617 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1228 23:11:00.880997 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 23:11:00.884170 [Gating] SW calibration Done
1230 23:11:00.884681 ==
1231 23:11:00.887882 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 23:11:00.890982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 23:11:00.891549 ==
1234 23:11:00.894529 RX Vref Scan: 0
1235 23:11:00.895087
1236 23:11:00.895456 RX Vref 0 -> 0, step: 1
1237 23:11:00.895799
1238 23:11:00.897761 RX Delay -130 -> 252, step: 16
1239 23:11:00.901341 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1240 23:11:00.907661 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1241 23:11:00.911027 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1242 23:11:00.914207 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1243 23:11:00.917446 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1244 23:11:00.920616 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1245 23:11:00.927598 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1246 23:11:00.931137 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1247 23:11:00.934361 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1248 23:11:00.937731 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1249 23:11:00.940875 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1250 23:11:00.947520 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1251 23:11:00.951102 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1252 23:11:00.954925 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1253 23:11:00.957696 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1254 23:11:00.961300 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1255 23:11:00.961757 ==
1256 23:11:00.964650 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 23:11:00.971542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 23:11:00.971963 ==
1259 23:11:00.972315 DQS Delay:
1260 23:11:00.974970 DQS0 = 0, DQS1 = 0
1261 23:11:00.975500 DQM Delay:
1262 23:11:00.975835 DQM0 = 93, DQM1 = 85
1263 23:11:00.978156 DQ Delay:
1264 23:11:00.981329 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1265 23:11:00.984675 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1266 23:11:00.988179 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
1267 23:11:00.991629 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1268 23:11:00.992049
1269 23:11:00.992381
1270 23:11:00.992686 ==
1271 23:11:00.994411 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 23:11:00.998434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 23:11:00.998964 ==
1274 23:11:00.999300
1275 23:11:00.999604
1276 23:11:01.000999 TX Vref Scan disable
1277 23:11:01.001513 == TX Byte 0 ==
1278 23:11:01.007830 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1279 23:11:01.011251 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1280 23:11:01.011667 == TX Byte 1 ==
1281 23:11:01.017672 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1282 23:11:01.021261 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1283 23:11:01.021831 ==
1284 23:11:01.024840 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 23:11:01.027982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 23:11:01.028405 ==
1287 23:11:01.042518 TX Vref=22, minBit 8, minWin=27, winSum=444
1288 23:11:01.045747 TX Vref=24, minBit 1, minWin=28, winSum=456
1289 23:11:01.048977 TX Vref=26, minBit 8, minWin=27, winSum=455
1290 23:11:01.052418 TX Vref=28, minBit 10, minWin=27, winSum=457
1291 23:11:01.056021 TX Vref=30, minBit 10, minWin=27, winSum=454
1292 23:11:01.062584 TX Vref=32, minBit 10, minWin=27, winSum=451
1293 23:11:01.065536 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 24
1294 23:11:01.066031
1295 23:11:01.069051 Final TX Range 1 Vref 24
1296 23:11:01.069507
1297 23:11:01.069909 ==
1298 23:11:01.072102 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 23:11:01.075904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 23:11:01.076359 ==
1301 23:11:01.076722
1302 23:11:01.077059
1303 23:11:01.078644 TX Vref Scan disable
1304 23:11:01.082395 == TX Byte 0 ==
1305 23:11:01.085428 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1306 23:11:01.088717 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1307 23:11:01.092631 == TX Byte 1 ==
1308 23:11:01.095817 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1309 23:11:01.098937 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1310 23:11:01.099267
1311 23:11:01.101991 [DATLAT]
1312 23:11:01.102228 Freq=800, CH0 RK1
1313 23:11:01.102418
1314 23:11:01.105631 DATLAT Default: 0xa
1315 23:11:01.105965 0, 0xFFFF, sum = 0
1316 23:11:01.108837 1, 0xFFFF, sum = 0
1317 23:11:01.109176 2, 0xFFFF, sum = 0
1318 23:11:01.112693 3, 0xFFFF, sum = 0
1319 23:11:01.112944 4, 0xFFFF, sum = 0
1320 23:11:01.115578 5, 0xFFFF, sum = 0
1321 23:11:01.115818 6, 0xFFFF, sum = 0
1322 23:11:01.119260 7, 0xFFFF, sum = 0
1323 23:11:01.119610 8, 0xFFFF, sum = 0
1324 23:11:01.122290 9, 0x0, sum = 1
1325 23:11:01.122534 10, 0x0, sum = 2
1326 23:11:01.125845 11, 0x0, sum = 3
1327 23:11:01.126142 12, 0x0, sum = 4
1328 23:11:01.128950 best_step = 10
1329 23:11:01.129326
1330 23:11:01.129669 ==
1331 23:11:01.132391 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 23:11:01.135866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 23:11:01.136364 ==
1334 23:11:01.139255 RX Vref Scan: 0
1335 23:11:01.139707
1336 23:11:01.140068 RX Vref 0 -> 0, step: 1
1337 23:11:01.140385
1338 23:11:01.142519 RX Delay -95 -> 252, step: 8
1339 23:11:01.149657 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1340 23:11:01.152808 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1341 23:11:01.156498 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1342 23:11:01.159640 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1343 23:11:01.162960 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1344 23:11:01.166083 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1345 23:11:01.173375 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1346 23:11:01.176337 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1347 23:11:01.179742 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1348 23:11:01.183310 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1349 23:11:01.185975 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1350 23:11:01.193086 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1351 23:11:01.196067 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1352 23:11:01.199701 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1353 23:11:01.203460 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1354 23:11:01.206343 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1355 23:11:01.209599 ==
1356 23:11:01.210154 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 23:11:01.216524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 23:11:01.217104 ==
1359 23:11:01.217480 DQS Delay:
1360 23:11:01.219894 DQS0 = 0, DQS1 = 0
1361 23:11:01.220448 DQM Delay:
1362 23:11:01.222743 DQM0 = 93, DQM1 = 83
1363 23:11:01.223295 DQ Delay:
1364 23:11:01.226190 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1365 23:11:01.229698 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1366 23:11:01.233138 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1367 23:11:01.236309 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1368 23:11:01.236896
1369 23:11:01.237263
1370 23:11:01.243244 [DQSOSCAuto] RK1, (LSB)MR18= 0x4415, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1371 23:11:01.246517 CH0 RK1: MR19=606, MR18=4415
1372 23:11:01.253188 CH0_RK1: MR19=0x606, MR18=0x4415, DQSOSC=392, MR23=63, INC=96, DEC=64
1373 23:11:01.256585 [RxdqsGatingPostProcess] freq 800
1374 23:11:01.259548 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 23:11:01.262981 Pre-setting of DQS Precalculation
1376 23:11:01.269679 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 23:11:01.270136 ==
1378 23:11:01.273431 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 23:11:01.276794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 23:11:01.277356 ==
1381 23:11:01.283384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 23:11:01.290003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 23:11:01.297702 [CA 0] Center 36 (6~67) winsize 62
1384 23:11:01.300990 [CA 1] Center 36 (6~67) winsize 62
1385 23:11:01.304071 [CA 2] Center 35 (5~65) winsize 61
1386 23:11:01.307549 [CA 3] Center 34 (4~65) winsize 62
1387 23:11:01.310977 [CA 4] Center 35 (5~65) winsize 61
1388 23:11:01.314063 [CA 5] Center 34 (4~65) winsize 62
1389 23:11:01.314520
1390 23:11:01.317495 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1391 23:11:01.318084
1392 23:11:01.320798 [CATrainingPosCal] consider 1 rank data
1393 23:11:01.323802 u2DelayCellTimex100 = 270/100 ps
1394 23:11:01.327520 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 23:11:01.330962 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 23:11:01.337132 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1397 23:11:01.341180 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 23:11:01.343910 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1399 23:11:01.347100 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 23:11:01.347558
1401 23:11:01.350873 CA PerBit enable=1, Macro0, CA PI delay=34
1402 23:11:01.351434
1403 23:11:01.354193 [CBTSetCACLKResult] CA Dly = 34
1404 23:11:01.354748 CS Dly: 5 (0~36)
1405 23:11:01.355109 ==
1406 23:11:01.357143 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 23:11:01.364084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 23:11:01.364547 ==
1409 23:11:01.367033 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 23:11:01.373970 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 23:11:01.383747 [CA 0] Center 36 (6~67) winsize 62
1412 23:11:01.387641 [CA 1] Center 37 (6~68) winsize 63
1413 23:11:01.391426 [CA 2] Center 35 (4~66) winsize 63
1414 23:11:01.395126 [CA 3] Center 34 (4~65) winsize 62
1415 23:11:01.398821 [CA 4] Center 35 (5~66) winsize 62
1416 23:11:01.399540 [CA 5] Center 34 (4~65) winsize 62
1417 23:11:01.402726
1418 23:11:01.403291 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 23:11:01.406900
1420 23:11:01.407492 [CATrainingPosCal] consider 2 rank data
1421 23:11:01.410456 u2DelayCellTimex100 = 270/100 ps
1422 23:11:01.414008 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 23:11:01.417905 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 23:11:01.421143 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1425 23:11:01.424335 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 23:11:01.428203 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 23:11:01.430980 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 23:11:01.431582
1429 23:11:01.437893 CA PerBit enable=1, Macro0, CA PI delay=34
1430 23:11:01.438359
1431 23:11:01.441166 [CBTSetCACLKResult] CA Dly = 34
1432 23:11:01.441661 CS Dly: 6 (0~38)
1433 23:11:01.442037
1434 23:11:01.444729 ----->DramcWriteLeveling(PI) begin...
1435 23:11:01.445285 ==
1436 23:11:01.447909 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 23:11:01.451483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 23:11:01.452247 ==
1439 23:11:01.455264 Write leveling (Byte 0): 30 => 30
1440 23:11:01.458032 Write leveling (Byte 1): 25 => 25
1441 23:11:01.461363 DramcWriteLeveling(PI) end<-----
1442 23:11:01.461963
1443 23:11:01.462336 ==
1444 23:11:01.465145 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 23:11:01.468107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 23:11:01.471519 ==
1447 23:11:01.472136 [Gating] SW mode calibration
1448 23:11:01.481416 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 23:11:01.484612 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 23:11:01.488314 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 23:11:01.494845 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1452 23:11:01.498226 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 23:11:01.501056 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 23:11:01.508399 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:11:01.511627 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:11:01.514923 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:11:01.521041 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:11:01.525028 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:11:01.527667 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:11:01.534614 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:11:01.537637 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:11:01.541008 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:11:01.548115 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:11:01.551133 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:11:01.554732 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:11:01.561149 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1467 23:11:01.564457 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1468 23:11:01.567793 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:11:01.571426 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:11:01.578284 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:11:01.581225 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:11:01.584988 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:11:01.591529 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 23:11:01.594531 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 23:11:01.597927 0 9 4 | B1->B0 | 2323 2929 | 1 0 | (1 1) (0 0)
1476 23:11:01.604855 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1477 23:11:01.607862 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 23:11:01.611456 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 23:11:01.617764 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 23:11:01.620960 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 23:11:01.625133 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 23:11:01.631672 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1483 23:11:01.634451 0 10 4 | B1->B0 | 3232 2d2d | 0 0 | (0 1) (0 1)
1484 23:11:01.638099 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:11:01.644647 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:11:01.647994 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:11:01.651385 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:11:01.654942 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 23:11:01.661757 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 23:11:01.664943 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 23:11:01.667996 0 11 4 | B1->B0 | 2626 3535 | 0 0 | (1 1) (0 0)
1492 23:11:01.674744 0 11 8 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
1493 23:11:01.677705 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 23:11:01.681693 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 23:11:01.688389 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 23:11:01.690965 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 23:11:01.694539 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 23:11:01.701341 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 23:11:01.704923 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 23:11:01.708353 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 23:11:01.714832 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:11:01.717763 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:11:01.721113 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:11:01.727746 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:11:01.731165 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:11:01.735003 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:11:01.741713 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:11:01.744633 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:11:01.747638 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:11:01.754728 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:11:01.758060 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:11:01.761343 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 23:11:01.764869 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 23:11:01.771020 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 23:11:01.774765 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1516 23:11:01.778496 Total UI for P1: 0, mck2ui 16
1517 23:11:01.781213 best dqsien dly found for B0: ( 0, 14, 2)
1518 23:11:01.784761 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 23:11:01.788033 Total UI for P1: 0, mck2ui 16
1520 23:11:01.791320 best dqsien dly found for B1: ( 0, 14, 4)
1521 23:11:01.794866 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1522 23:11:01.798209 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1523 23:11:01.798675
1524 23:11:01.804827 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1525 23:11:01.808274 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 23:11:01.808841 [Gating] SW calibration Done
1527 23:11:01.811609 ==
1528 23:11:01.812206 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 23:11:01.818618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 23:11:01.819183 ==
1531 23:11:01.819553 RX Vref Scan: 0
1532 23:11:01.819894
1533 23:11:01.821345 RX Vref 0 -> 0, step: 1
1534 23:11:01.821861
1535 23:11:01.824788 RX Delay -130 -> 252, step: 16
1536 23:11:01.827909 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1537 23:11:01.830721 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1538 23:11:01.837780 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1539 23:11:01.840731 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1540 23:11:01.844742 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1541 23:11:01.847508 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1542 23:11:01.850940 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1543 23:11:01.854315 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1544 23:11:01.860756 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1545 23:11:01.864659 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1546 23:11:01.867822 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1547 23:11:01.871286 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1548 23:11:01.874543 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1549 23:11:01.881448 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1550 23:11:01.885236 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1551 23:11:01.887601 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1552 23:11:01.888108 ==
1553 23:11:01.891174 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 23:11:01.894829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 23:11:01.898057 ==
1556 23:11:01.898629 DQS Delay:
1557 23:11:01.899001 DQS0 = 0, DQS1 = 0
1558 23:11:01.901390 DQM Delay:
1559 23:11:01.901889 DQM0 = 92, DQM1 = 87
1560 23:11:01.902259 DQ Delay:
1561 23:11:01.904543 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1562 23:11:01.908377 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1563 23:11:01.911440 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1564 23:11:01.914523 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1565 23:11:01.915083
1566 23:11:01.915457
1567 23:11:01.918043 ==
1568 23:11:01.921444 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 23:11:01.924567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 23:11:01.925031 ==
1571 23:11:01.925398
1572 23:11:01.925790
1573 23:11:01.927910 TX Vref Scan disable
1574 23:11:01.928379 == TX Byte 0 ==
1575 23:11:01.931651 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1576 23:11:01.938248 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1577 23:11:01.938798 == TX Byte 1 ==
1578 23:11:01.941410 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1579 23:11:01.948239 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1580 23:11:01.949022 ==
1581 23:11:01.951679 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 23:11:01.954276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 23:11:01.954741 ==
1584 23:11:01.968476 TX Vref=22, minBit 0, minWin=26, winSum=434
1585 23:11:01.972110 TX Vref=24, minBit 2, minWin=27, winSum=440
1586 23:11:01.975691 TX Vref=26, minBit 1, minWin=27, winSum=442
1587 23:11:01.979113 TX Vref=28, minBit 1, minWin=27, winSum=446
1588 23:11:01.982457 TX Vref=30, minBit 3, minWin=27, winSum=448
1589 23:11:01.985443 TX Vref=32, minBit 1, minWin=27, winSum=444
1590 23:11:01.992208 [TxChooseVref] Worse bit 3, Min win 27, Win sum 448, Final Vref 30
1591 23:11:01.992628
1592 23:11:01.995631 Final TX Range 1 Vref 30
1593 23:11:01.996051
1594 23:11:01.996384 ==
1595 23:11:01.998994 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 23:11:02.002268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 23:11:02.002689 ==
1598 23:11:02.003020
1599 23:11:02.003327
1600 23:11:02.005596 TX Vref Scan disable
1601 23:11:02.009720 == TX Byte 0 ==
1602 23:11:02.012304 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1603 23:11:02.015834 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1604 23:11:02.018803 == TX Byte 1 ==
1605 23:11:02.022505 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1606 23:11:02.025847 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1607 23:11:02.026266
1608 23:11:02.028912 [DATLAT]
1609 23:11:02.029330 Freq=800, CH1 RK0
1610 23:11:02.029813
1611 23:11:02.032545 DATLAT Default: 0xa
1612 23:11:02.033071 0, 0xFFFF, sum = 0
1613 23:11:02.035420 1, 0xFFFF, sum = 0
1614 23:11:02.035845 2, 0xFFFF, sum = 0
1615 23:11:02.038760 3, 0xFFFF, sum = 0
1616 23:11:02.039185 4, 0xFFFF, sum = 0
1617 23:11:02.042296 5, 0xFFFF, sum = 0
1618 23:11:02.042760 6, 0xFFFF, sum = 0
1619 23:11:02.045349 7, 0xFFFF, sum = 0
1620 23:11:02.045826 8, 0xFFFF, sum = 0
1621 23:11:02.048838 9, 0x0, sum = 1
1622 23:11:02.049432 10, 0x0, sum = 2
1623 23:11:02.052348 11, 0x0, sum = 3
1624 23:11:02.052880 12, 0x0, sum = 4
1625 23:11:02.056421 best_step = 10
1626 23:11:02.056941
1627 23:11:02.057274 ==
1628 23:11:02.058891 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 23:11:02.062783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 23:11:02.063310 ==
1631 23:11:02.063694 RX Vref Scan: 1
1632 23:11:02.064026
1633 23:11:02.065458 Set Vref Range= 32 -> 127
1634 23:11:02.065950
1635 23:11:02.069149 RX Vref 32 -> 127, step: 1
1636 23:11:02.069572
1637 23:11:02.072396 RX Delay -79 -> 252, step: 8
1638 23:11:02.072811
1639 23:11:02.075982 Set Vref, RX VrefLevel [Byte0]: 32
1640 23:11:02.079147 [Byte1]: 32
1641 23:11:02.079672
1642 23:11:02.082631 Set Vref, RX VrefLevel [Byte0]: 33
1643 23:11:02.085859 [Byte1]: 33
1644 23:11:02.086391
1645 23:11:02.089387 Set Vref, RX VrefLevel [Byte0]: 34
1646 23:11:02.092653 [Byte1]: 34
1647 23:11:02.096319
1648 23:11:02.096832 Set Vref, RX VrefLevel [Byte0]: 35
1649 23:11:02.099277 [Byte1]: 35
1650 23:11:02.103617
1651 23:11:02.104147 Set Vref, RX VrefLevel [Byte0]: 36
1652 23:11:02.106926 [Byte1]: 36
1653 23:11:02.111495
1654 23:11:02.112013 Set Vref, RX VrefLevel [Byte0]: 37
1655 23:11:02.114304 [Byte1]: 37
1656 23:11:02.118863
1657 23:11:02.119378 Set Vref, RX VrefLevel [Byte0]: 38
1658 23:11:02.122154 [Byte1]: 38
1659 23:11:02.126518
1660 23:11:02.126982 Set Vref, RX VrefLevel [Byte0]: 39
1661 23:11:02.129706 [Byte1]: 39
1662 23:11:02.134142
1663 23:11:02.134558 Set Vref, RX VrefLevel [Byte0]: 40
1664 23:11:02.137118 [Byte1]: 40
1665 23:11:02.141800
1666 23:11:02.142524 Set Vref, RX VrefLevel [Byte0]: 41
1667 23:11:02.144854 [Byte1]: 41
1668 23:11:02.148775
1669 23:11:02.149192 Set Vref, RX VrefLevel [Byte0]: 42
1670 23:11:02.151990 [Byte1]: 42
1671 23:11:02.156486
1672 23:11:02.157010 Set Vref, RX VrefLevel [Byte0]: 43
1673 23:11:02.159961 [Byte1]: 43
1674 23:11:02.164444
1675 23:11:02.164964 Set Vref, RX VrefLevel [Byte0]: 44
1676 23:11:02.167863 [Byte1]: 44
1677 23:11:02.171481
1678 23:11:02.171896 Set Vref, RX VrefLevel [Byte0]: 45
1679 23:11:02.175200 [Byte1]: 45
1680 23:11:02.179420
1681 23:11:02.179950 Set Vref, RX VrefLevel [Byte0]: 46
1682 23:11:02.182759 [Byte1]: 46
1683 23:11:02.186547
1684 23:11:02.187073 Set Vref, RX VrefLevel [Byte0]: 47
1685 23:11:02.190081 [Byte1]: 47
1686 23:11:02.194244
1687 23:11:02.194766 Set Vref, RX VrefLevel [Byte0]: 48
1688 23:11:02.197488 [Byte1]: 48
1689 23:11:02.202057
1690 23:11:02.202579 Set Vref, RX VrefLevel [Byte0]: 49
1691 23:11:02.205209 [Byte1]: 49
1692 23:11:02.209483
1693 23:11:02.210050 Set Vref, RX VrefLevel [Byte0]: 50
1694 23:11:02.212576 [Byte1]: 50
1695 23:11:02.217305
1696 23:11:02.217882 Set Vref, RX VrefLevel [Byte0]: 51
1697 23:11:02.220084 [Byte1]: 51
1698 23:11:02.224118
1699 23:11:02.224542 Set Vref, RX VrefLevel [Byte0]: 52
1700 23:11:02.227399 [Byte1]: 52
1701 23:11:02.231817
1702 23:11:02.232235 Set Vref, RX VrefLevel [Byte0]: 53
1703 23:11:02.235199 [Byte1]: 53
1704 23:11:02.239298
1705 23:11:02.239718 Set Vref, RX VrefLevel [Byte0]: 54
1706 23:11:02.242797 [Byte1]: 54
1707 23:11:02.247490
1708 23:11:02.248028 Set Vref, RX VrefLevel [Byte0]: 55
1709 23:11:02.250199 [Byte1]: 55
1710 23:11:02.254684
1711 23:11:02.255207 Set Vref, RX VrefLevel [Byte0]: 56
1712 23:11:02.257903 [Byte1]: 56
1713 23:11:02.262041
1714 23:11:02.262585 Set Vref, RX VrefLevel [Byte0]: 57
1715 23:11:02.265600 [Byte1]: 57
1716 23:11:02.269874
1717 23:11:02.270288 Set Vref, RX VrefLevel [Byte0]: 58
1718 23:11:02.272563 [Byte1]: 58
1719 23:11:02.277398
1720 23:11:02.277860 Set Vref, RX VrefLevel [Byte0]: 59
1721 23:11:02.280837 [Byte1]: 59
1722 23:11:02.284671
1723 23:11:02.285134 Set Vref, RX VrefLevel [Byte0]: 60
1724 23:11:02.288156 [Byte1]: 60
1725 23:11:02.292471
1726 23:11:02.293031 Set Vref, RX VrefLevel [Byte0]: 61
1727 23:11:02.295683 [Byte1]: 61
1728 23:11:02.300558
1729 23:11:02.301126 Set Vref, RX VrefLevel [Byte0]: 62
1730 23:11:02.303103 [Byte1]: 62
1731 23:11:02.307660
1732 23:11:02.308220 Set Vref, RX VrefLevel [Byte0]: 63
1733 23:11:02.310764 [Byte1]: 63
1734 23:11:02.315259
1735 23:11:02.315846 Set Vref, RX VrefLevel [Byte0]: 64
1736 23:11:02.318946 [Byte1]: 64
1737 23:11:02.322505
1738 23:11:02.323088 Set Vref, RX VrefLevel [Byte0]: 65
1739 23:11:02.325673 [Byte1]: 65
1740 23:11:02.330552
1741 23:11:02.331014 Set Vref, RX VrefLevel [Byte0]: 66
1742 23:11:02.333818 [Byte1]: 66
1743 23:11:02.337991
1744 23:11:02.338575 Set Vref, RX VrefLevel [Byte0]: 67
1745 23:11:02.340993 [Byte1]: 67
1746 23:11:02.345447
1747 23:11:02.346053 Set Vref, RX VrefLevel [Byte0]: 68
1748 23:11:02.348258 [Byte1]: 68
1749 23:11:02.352616
1750 23:11:02.353077 Set Vref, RX VrefLevel [Byte0]: 69
1751 23:11:02.355920 [Byte1]: 69
1752 23:11:02.360572
1753 23:11:02.361151 Set Vref, RX VrefLevel [Byte0]: 70
1754 23:11:02.363390 [Byte1]: 70
1755 23:11:02.367713
1756 23:11:02.368172 Set Vref, RX VrefLevel [Byte0]: 71
1757 23:11:02.370733 [Byte1]: 71
1758 23:11:02.375658
1759 23:11:02.376220 Set Vref, RX VrefLevel [Byte0]: 72
1760 23:11:02.378512 [Byte1]: 72
1761 23:11:02.383077
1762 23:11:02.383699 Set Vref, RX VrefLevel [Byte0]: 73
1763 23:11:02.386485 [Byte1]: 73
1764 23:11:02.390455
1765 23:11:02.391048 Final RX Vref Byte 0 = 60 to rank0
1766 23:11:02.393705 Final RX Vref Byte 1 = 55 to rank0
1767 23:11:02.396744 Final RX Vref Byte 0 = 60 to rank1
1768 23:11:02.400423 Final RX Vref Byte 1 = 55 to rank1==
1769 23:11:02.404171 Dram Type= 6, Freq= 0, CH_1, rank 0
1770 23:11:02.410520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1771 23:11:02.411087 ==
1772 23:11:02.411453 DQS Delay:
1773 23:11:02.411797 DQS0 = 0, DQS1 = 0
1774 23:11:02.414195 DQM Delay:
1775 23:11:02.414759 DQM0 = 95, DQM1 = 89
1776 23:11:02.417673 DQ Delay:
1777 23:11:02.420251 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1778 23:11:02.424084 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1779 23:11:02.427095 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1780 23:11:02.430044 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1781 23:11:02.430543
1782 23:11:02.430909
1783 23:11:02.437268 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1784 23:11:02.440353 CH1 RK0: MR19=606, MR18=2E4A
1785 23:11:02.447437 CH1_RK0: MR19=0x606, MR18=0x2E4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1786 23:11:02.448021
1787 23:11:02.450518 ----->DramcWriteLeveling(PI) begin...
1788 23:11:02.450984 ==
1789 23:11:02.453750 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 23:11:02.457688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 23:11:02.458149 ==
1792 23:11:02.461373 Write leveling (Byte 0): 28 => 28
1793 23:11:02.463600 Write leveling (Byte 1): 29 => 29
1794 23:11:02.466838 DramcWriteLeveling(PI) end<-----
1795 23:11:02.467394
1796 23:11:02.467757 ==
1797 23:11:02.470436 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 23:11:02.473532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 23:11:02.474083 ==
1800 23:11:02.476977 [Gating] SW mode calibration
1801 23:11:02.483729 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1802 23:11:02.490511 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1803 23:11:02.493744 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1804 23:11:02.496983 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1805 23:11:02.504012 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 23:11:02.507183 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 23:11:02.510355 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 23:11:02.516906 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 23:11:02.520217 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 23:11:02.523806 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 23:11:02.530078 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 23:11:02.533653 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 23:11:02.537352 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 23:11:02.543594 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 23:11:02.546855 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 23:11:02.550232 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 23:11:02.556802 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 23:11:02.560451 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1819 23:11:02.563584 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1820 23:11:02.567249 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1821 23:11:02.573766 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:11:02.577175 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:11:02.580697 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:11:02.586956 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:11:02.590820 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:11:02.594143 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:11:02.600734 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:11:02.604536 0 9 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (1 1)
1829 23:11:02.607629 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
1830 23:11:02.614000 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 23:11:02.618158 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 23:11:02.620835 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 23:11:02.627874 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 23:11:02.630932 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 23:11:02.634105 0 10 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1836 23:11:02.640963 0 10 4 | B1->B0 | 2e2e 3030 | 0 0 | (1 1) (0 0)
1837 23:11:02.643810 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:11:02.647562 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:11:02.650643 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:11:02.657364 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:11:02.660845 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 23:11:02.663665 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 23:11:02.670804 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1844 23:11:02.674114 0 11 4 | B1->B0 | 4040 2a29 | 1 1 | (0 0) (0 0)
1845 23:11:02.677758 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1846 23:11:02.684147 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 23:11:02.687612 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 23:11:02.691030 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 23:11:02.697512 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 23:11:02.700502 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 23:11:02.704202 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1852 23:11:02.710696 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1853 23:11:02.713723 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 23:11:02.717000 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 23:11:02.724694 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 23:11:02.727889 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 23:11:02.730907 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 23:11:02.734466 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 23:11:02.740670 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 23:11:02.744481 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 23:11:02.747640 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 23:11:02.753993 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 23:11:02.757388 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 23:11:02.760910 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 23:11:02.767784 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 23:11:02.770927 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 23:11:02.773901 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 23:11:02.780947 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1869 23:11:02.784357 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 23:11:02.787701 Total UI for P1: 0, mck2ui 16
1871 23:11:02.790844 best dqsien dly found for B0: ( 0, 14, 4)
1872 23:11:02.794726 Total UI for P1: 0, mck2ui 16
1873 23:11:02.797515 best dqsien dly found for B1: ( 0, 14, 4)
1874 23:11:02.800974 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1875 23:11:02.804039 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1876 23:11:02.804502
1877 23:11:02.807467 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1878 23:11:02.810850 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1879 23:11:02.813839 [Gating] SW calibration Done
1880 23:11:02.814298 ==
1881 23:11:02.817747 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 23:11:02.820472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1883 23:11:02.820937 ==
1884 23:11:02.824137 RX Vref Scan: 0
1885 23:11:02.824594
1886 23:11:02.827380 RX Vref 0 -> 0, step: 1
1887 23:11:02.827883
1888 23:11:02.828251 RX Delay -130 -> 252, step: 16
1889 23:11:02.834126 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1890 23:11:02.837693 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1891 23:11:02.841094 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1892 23:11:02.844303 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1893 23:11:02.847417 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1894 23:11:02.854173 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1895 23:11:02.857681 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1896 23:11:02.861446 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1897 23:11:02.863885 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1898 23:11:02.867738 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1899 23:11:02.873926 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1900 23:11:02.877728 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1901 23:11:02.881239 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1902 23:11:02.884452 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1903 23:11:02.887869 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1904 23:11:02.894562 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1905 23:11:02.895113 ==
1906 23:11:02.897554 Dram Type= 6, Freq= 0, CH_1, rank 1
1907 23:11:02.900876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1908 23:11:02.901336 ==
1909 23:11:02.901743 DQS Delay:
1910 23:11:02.904091 DQS0 = 0, DQS1 = 0
1911 23:11:02.904548 DQM Delay:
1912 23:11:02.907842 DQM0 = 92, DQM1 = 91
1913 23:11:02.908397 DQ Delay:
1914 23:11:02.910833 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1915 23:11:02.914268 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1916 23:11:02.917649 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1917 23:11:02.920699 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1918 23:11:02.921247
1919 23:11:02.921725
1920 23:11:02.922263 ==
1921 23:11:02.924116 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 23:11:02.927672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 23:11:02.930894 ==
1924 23:11:02.931355
1925 23:11:02.931759
1926 23:11:02.932146 TX Vref Scan disable
1927 23:11:02.934833 == TX Byte 0 ==
1928 23:11:02.937684 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1929 23:11:02.940893 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1930 23:11:02.944586 == TX Byte 1 ==
1931 23:11:02.947500 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1932 23:11:02.951181 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1933 23:11:02.951649 ==
1934 23:11:02.954524 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 23:11:02.961086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 23:11:02.961684 ==
1937 23:11:02.973307 TX Vref=22, minBit 0, minWin=27, winSum=444
1938 23:11:02.976292 TX Vref=24, minBit 2, minWin=27, winSum=446
1939 23:11:02.980036 TX Vref=26, minBit 2, minWin=27, winSum=449
1940 23:11:02.982999 TX Vref=28, minBit 2, minWin=27, winSum=452
1941 23:11:02.986471 TX Vref=30, minBit 2, minWin=27, winSum=451
1942 23:11:02.989819 TX Vref=32, minBit 2, minWin=27, winSum=449
1943 23:11:02.996952 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 28
1944 23:11:02.997563
1945 23:11:02.999731 Final TX Range 1 Vref 28
1946 23:11:03.000191
1947 23:11:03.000554 ==
1948 23:11:03.003039 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 23:11:03.006812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 23:11:03.007439 ==
1951 23:11:03.008141
1952 23:11:03.008651
1953 23:11:03.009414 TX Vref Scan disable
1954 23:11:03.013410 == TX Byte 0 ==
1955 23:11:03.016381 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1956 23:11:03.019234 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1957 23:11:03.023141 == TX Byte 1 ==
1958 23:11:03.026079 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1959 23:11:03.029685 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1960 23:11:03.033552
1961 23:11:03.034089 [DATLAT]
1962 23:11:03.034457 Freq=800, CH1 RK1
1963 23:11:03.034806
1964 23:11:03.036613 DATLAT Default: 0xa
1965 23:11:03.037069 0, 0xFFFF, sum = 0
1966 23:11:03.039584 1, 0xFFFF, sum = 0
1967 23:11:03.040131 2, 0xFFFF, sum = 0
1968 23:11:03.043592 3, 0xFFFF, sum = 0
1969 23:11:03.044185 4, 0xFFFF, sum = 0
1970 23:11:03.046928 5, 0xFFFF, sum = 0
1971 23:11:03.047395 6, 0xFFFF, sum = 0
1972 23:11:03.049761 7, 0xFFFF, sum = 0
1973 23:11:03.050230 8, 0xFFFF, sum = 0
1974 23:11:03.053760 9, 0x0, sum = 1
1975 23:11:03.054229 10, 0x0, sum = 2
1976 23:11:03.056452 11, 0x0, sum = 3
1977 23:11:03.056878 12, 0x0, sum = 4
1978 23:11:03.059950 best_step = 10
1979 23:11:03.060463
1980 23:11:03.060796 ==
1981 23:11:03.063321 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 23:11:03.067463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 23:11:03.067997 ==
1984 23:11:03.069705 RX Vref Scan: 0
1985 23:11:03.070124
1986 23:11:03.070459 RX Vref 0 -> 0, step: 1
1987 23:11:03.070773
1988 23:11:03.072894 RX Delay -79 -> 252, step: 8
1989 23:11:03.080764 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
1990 23:11:03.083482 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1991 23:11:03.087306 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1992 23:11:03.089744 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1993 23:11:03.093653 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1994 23:11:03.096592 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1995 23:11:03.103399 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1996 23:11:03.106932 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1997 23:11:03.109932 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1998 23:11:03.113737 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1999 23:11:03.117143 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2000 23:11:03.123719 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2001 23:11:03.126456 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2002 23:11:03.129685 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2003 23:11:03.133262 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2004 23:11:03.137045 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2005 23:11:03.137555 ==
2006 23:11:03.139571 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 23:11:03.146334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 23:11:03.146834 ==
2009 23:11:03.147170 DQS Delay:
2010 23:11:03.149482 DQS0 = 0, DQS1 = 0
2011 23:11:03.149974 DQM Delay:
2012 23:11:03.150313 DQM0 = 96, DQM1 = 90
2013 23:11:03.152899 DQ Delay:
2014 23:11:03.156407 DQ0 =96, DQ1 =92, DQ2 =84, DQ3 =92
2015 23:11:03.160103 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2016 23:11:03.163099 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2017 23:11:03.166253 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2018 23:11:03.166762
2019 23:11:03.167098
2020 23:11:03.173017 [DQSOSCAuto] RK1, (LSB)MR18= 0x440f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2021 23:11:03.176206 CH1 RK1: MR19=606, MR18=440F
2022 23:11:03.183467 CH1_RK1: MR19=0x606, MR18=0x440F, DQSOSC=392, MR23=63, INC=96, DEC=64
2023 23:11:03.186382 [RxdqsGatingPostProcess] freq 800
2024 23:11:03.189828 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2025 23:11:03.193834 Pre-setting of DQS Precalculation
2026 23:11:03.200451 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2027 23:11:03.206543 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2028 23:11:03.213670 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2029 23:11:03.214187
2030 23:11:03.214519
2031 23:11:03.217089 [Calibration Summary] 1600 Mbps
2032 23:11:03.217504 CH 0, Rank 0
2033 23:11:03.220259 SW Impedance : PASS
2034 23:11:03.223616 DUTY Scan : NO K
2035 23:11:03.224124 ZQ Calibration : PASS
2036 23:11:03.227044 Jitter Meter : NO K
2037 23:11:03.230265 CBT Training : PASS
2038 23:11:03.230729 Write leveling : PASS
2039 23:11:03.233263 RX DQS gating : PASS
2040 23:11:03.237002 RX DQ/DQS(RDDQC) : PASS
2041 23:11:03.237419 TX DQ/DQS : PASS
2042 23:11:03.240062 RX DATLAT : PASS
2043 23:11:03.240480 RX DQ/DQS(Engine): PASS
2044 23:11:03.243226 TX OE : NO K
2045 23:11:03.243645 All Pass.
2046 23:11:03.243977
2047 23:11:03.246680 CH 0, Rank 1
2048 23:11:03.247095 SW Impedance : PASS
2049 23:11:03.249874 DUTY Scan : NO K
2050 23:11:03.253274 ZQ Calibration : PASS
2051 23:11:03.253738 Jitter Meter : NO K
2052 23:11:03.256843 CBT Training : PASS
2053 23:11:03.259864 Write leveling : PASS
2054 23:11:03.260285 RX DQS gating : PASS
2055 23:11:03.263631 RX DQ/DQS(RDDQC) : PASS
2056 23:11:03.266848 TX DQ/DQS : PASS
2057 23:11:03.267362 RX DATLAT : PASS
2058 23:11:03.269818 RX DQ/DQS(Engine): PASS
2059 23:11:03.273614 TX OE : NO K
2060 23:11:03.274198 All Pass.
2061 23:11:03.274541
2062 23:11:03.274855 CH 1, Rank 0
2063 23:11:03.276592 SW Impedance : PASS
2064 23:11:03.277009 DUTY Scan : NO K
2065 23:11:03.279960 ZQ Calibration : PASS
2066 23:11:03.283447 Jitter Meter : NO K
2067 23:11:03.283958 CBT Training : PASS
2068 23:11:03.286794 Write leveling : PASS
2069 23:11:03.290314 RX DQS gating : PASS
2070 23:11:03.290838 RX DQ/DQS(RDDQC) : PASS
2071 23:11:03.293945 TX DQ/DQS : PASS
2072 23:11:03.296908 RX DATLAT : PASS
2073 23:11:03.297430 RX DQ/DQS(Engine): PASS
2074 23:11:03.299915 TX OE : NO K
2075 23:11:03.300422 All Pass.
2076 23:11:03.300757
2077 23:11:03.303349 CH 1, Rank 1
2078 23:11:03.303881 SW Impedance : PASS
2079 23:11:03.306685 DUTY Scan : NO K
2080 23:11:03.310571 ZQ Calibration : PASS
2081 23:11:03.311094 Jitter Meter : NO K
2082 23:11:03.313331 CBT Training : PASS
2083 23:11:03.316819 Write leveling : PASS
2084 23:11:03.317341 RX DQS gating : PASS
2085 23:11:03.320237 RX DQ/DQS(RDDQC) : PASS
2086 23:11:03.323851 TX DQ/DQS : PASS
2087 23:11:03.324416 RX DATLAT : PASS
2088 23:11:03.326617 RX DQ/DQS(Engine): PASS
2089 23:11:03.327079 TX OE : NO K
2090 23:11:03.330149 All Pass.
2091 23:11:03.330638
2092 23:11:03.331035 DramC Write-DBI off
2093 23:11:03.333179 PER_BANK_REFRESH: Hybrid Mode
2094 23:11:03.337148 TX_TRACKING: ON
2095 23:11:03.339974 [GetDramInforAfterCalByMRR] Vendor 6.
2096 23:11:03.343315 [GetDramInforAfterCalByMRR] Revision 606.
2097 23:11:03.347053 [GetDramInforAfterCalByMRR] Revision 2 0.
2098 23:11:03.347618 MR0 0x3b3b
2099 23:11:03.347987 MR8 0x5151
2100 23:11:03.353764 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 23:11:03.354230
2102 23:11:03.354596 MR0 0x3b3b
2103 23:11:03.354942 MR8 0x5151
2104 23:11:03.356823 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 23:11:03.357335
2106 23:11:03.366987 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2107 23:11:03.370286 [FAST_K] Save calibration result to emmc
2108 23:11:03.373700 [FAST_K] Save calibration result to emmc
2109 23:11:03.376755 dram_init: config_dvfs: 1
2110 23:11:03.380416 dramc_set_vcore_voltage set vcore to 662500
2111 23:11:03.383391 Read voltage for 1200, 2
2112 23:11:03.383852 Vio18 = 0
2113 23:11:03.384223 Vcore = 662500
2114 23:11:03.387180 Vdram = 0
2115 23:11:03.387746 Vddq = 0
2116 23:11:03.388115 Vmddr = 0
2117 23:11:03.393772 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2118 23:11:03.397074 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2119 23:11:03.400330 MEM_TYPE=3, freq_sel=15
2120 23:11:03.403688 sv_algorithm_assistance_LP4_1600
2121 23:11:03.407027 ============ PULL DRAM RESETB DOWN ============
2122 23:11:03.410509 ========== PULL DRAM RESETB DOWN end =========
2123 23:11:03.416843 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2124 23:11:03.420922 ===================================
2125 23:11:03.421485 LPDDR4 DRAM CONFIGURATION
2126 23:11:03.423645 ===================================
2127 23:11:03.427159 EX_ROW_EN[0] = 0x0
2128 23:11:03.430181 EX_ROW_EN[1] = 0x0
2129 23:11:03.430674 LP4Y_EN = 0x0
2130 23:11:03.433516 WORK_FSP = 0x0
2131 23:11:03.434031 WL = 0x4
2132 23:11:03.437091 RL = 0x4
2133 23:11:03.437702 BL = 0x2
2134 23:11:03.440617 RPST = 0x0
2135 23:11:03.441075 RD_PRE = 0x0
2136 23:11:03.443504 WR_PRE = 0x1
2137 23:11:03.443967 WR_PST = 0x0
2138 23:11:03.447135 DBI_WR = 0x0
2139 23:11:03.447686 DBI_RD = 0x0
2140 23:11:03.450456 OTF = 0x1
2141 23:11:03.453540 ===================================
2142 23:11:03.457237 ===================================
2143 23:11:03.457857 ANA top config
2144 23:11:03.460450 ===================================
2145 23:11:03.463779 DLL_ASYNC_EN = 0
2146 23:11:03.467286 ALL_SLAVE_EN = 0
2147 23:11:03.470352 NEW_RANK_MODE = 1
2148 23:11:03.470816 DLL_IDLE_MODE = 1
2149 23:11:03.473501 LP45_APHY_COMB_EN = 1
2150 23:11:03.476873 TX_ODT_DIS = 1
2151 23:11:03.480423 NEW_8X_MODE = 1
2152 23:11:03.483734 ===================================
2153 23:11:03.486759 ===================================
2154 23:11:03.490278 data_rate = 2400
2155 23:11:03.490833 CKR = 1
2156 23:11:03.493534 DQ_P2S_RATIO = 8
2157 23:11:03.497092 ===================================
2158 23:11:03.500222 CA_P2S_RATIO = 8
2159 23:11:03.503892 DQ_CA_OPEN = 0
2160 23:11:03.507116 DQ_SEMI_OPEN = 0
2161 23:11:03.507671 CA_SEMI_OPEN = 0
2162 23:11:03.510600 CA_FULL_RATE = 0
2163 23:11:03.514019 DQ_CKDIV4_EN = 0
2164 23:11:03.517164 CA_CKDIV4_EN = 0
2165 23:11:03.520341 CA_PREDIV_EN = 0
2166 23:11:03.523649 PH8_DLY = 17
2167 23:11:03.524203 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2168 23:11:03.527297 DQ_AAMCK_DIV = 4
2169 23:11:03.530575 CA_AAMCK_DIV = 4
2170 23:11:03.533544 CA_ADMCK_DIV = 4
2171 23:11:03.537639 DQ_TRACK_CA_EN = 0
2172 23:11:03.540801 CA_PICK = 1200
2173 23:11:03.541383 CA_MCKIO = 1200
2174 23:11:03.544496 MCKIO_SEMI = 0
2175 23:11:03.547353 PLL_FREQ = 2366
2176 23:11:03.550903 DQ_UI_PI_RATIO = 32
2177 23:11:03.554277 CA_UI_PI_RATIO = 0
2178 23:11:03.557294 ===================================
2179 23:11:03.560774 ===================================
2180 23:11:03.563909 memory_type:LPDDR4
2181 23:11:03.564429 GP_NUM : 10
2182 23:11:03.567442 SRAM_EN : 1
2183 23:11:03.567992 MD32_EN : 0
2184 23:11:03.570353 ===================================
2185 23:11:03.573958 [ANA_INIT] >>>>>>>>>>>>>>
2186 23:11:03.577632 <<<<<< [CONFIGURE PHASE]: ANA_TX
2187 23:11:03.580903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2188 23:11:03.584358 ===================================
2189 23:11:03.587539 data_rate = 2400,PCW = 0X5b00
2190 23:11:03.590743 ===================================
2191 23:11:03.593782 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2192 23:11:03.597421 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 23:11:03.604393 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 23:11:03.607680 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2195 23:11:03.610718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2196 23:11:03.614246 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2197 23:11:03.617759 [ANA_INIT] flow start
2198 23:11:03.621164 [ANA_INIT] PLL >>>>>>>>
2199 23:11:03.621765 [ANA_INIT] PLL <<<<<<<<
2200 23:11:03.624464 [ANA_INIT] MIDPI >>>>>>>>
2201 23:11:03.627373 [ANA_INIT] MIDPI <<<<<<<<
2202 23:11:03.630515 [ANA_INIT] DLL >>>>>>>>
2203 23:11:03.631001 [ANA_INIT] DLL <<<<<<<<
2204 23:11:03.634223 [ANA_INIT] flow end
2205 23:11:03.637682 ============ LP4 DIFF to SE enter ============
2206 23:11:03.640647 ============ LP4 DIFF to SE exit ============
2207 23:11:03.644116 [ANA_INIT] <<<<<<<<<<<<<
2208 23:11:03.648199 [Flow] Enable top DCM control >>>>>
2209 23:11:03.650712 [Flow] Enable top DCM control <<<<<
2210 23:11:03.654091 Enable DLL master slave shuffle
2211 23:11:03.660917 ==============================================================
2212 23:11:03.661484 Gating Mode config
2213 23:11:03.667860 ==============================================================
2214 23:11:03.668418 Config description:
2215 23:11:03.677722 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2216 23:11:03.684303 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2217 23:11:03.691320 SELPH_MODE 0: By rank 1: By Phase
2218 23:11:03.694444 ==============================================================
2219 23:11:03.697784 GAT_TRACK_EN = 1
2220 23:11:03.701386 RX_GATING_MODE = 2
2221 23:11:03.704149 RX_GATING_TRACK_MODE = 2
2222 23:11:03.707562 SELPH_MODE = 1
2223 23:11:03.711305 PICG_EARLY_EN = 1
2224 23:11:03.714828 VALID_LAT_VALUE = 1
2225 23:11:03.717972 ==============================================================
2226 23:11:03.721033 Enter into Gating configuration >>>>
2227 23:11:03.724601 Exit from Gating configuration <<<<
2228 23:11:03.727581 Enter into DVFS_PRE_config >>>>>
2229 23:11:03.740877 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2230 23:11:03.741453 Exit from DVFS_PRE_config <<<<<
2231 23:11:03.744321 Enter into PICG configuration >>>>
2232 23:11:03.747985 Exit from PICG configuration <<<<
2233 23:11:03.751363 [RX_INPUT] configuration >>>>>
2234 23:11:03.754113 [RX_INPUT] configuration <<<<<
2235 23:11:03.760755 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2236 23:11:03.764658 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2237 23:11:03.771302 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2238 23:11:03.777363 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2239 23:11:03.784500 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2240 23:11:03.791117 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2241 23:11:03.794355 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2242 23:11:03.798152 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2243 23:11:03.801057 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2244 23:11:03.807716 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2245 23:11:03.811247 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2246 23:11:03.814384 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2247 23:11:03.817735 ===================================
2248 23:11:03.821056 LPDDR4 DRAM CONFIGURATION
2249 23:11:03.824038 ===================================
2250 23:11:03.824586 EX_ROW_EN[0] = 0x0
2251 23:11:03.827506 EX_ROW_EN[1] = 0x0
2252 23:11:03.828059 LP4Y_EN = 0x0
2253 23:11:03.830749 WORK_FSP = 0x0
2254 23:11:03.831212 WL = 0x4
2255 23:11:03.834203 RL = 0x4
2256 23:11:03.837782 BL = 0x2
2257 23:11:03.838237 RPST = 0x0
2258 23:11:03.841108 RD_PRE = 0x0
2259 23:11:03.841704 WR_PRE = 0x1
2260 23:11:03.844648 WR_PST = 0x0
2261 23:11:03.845097 DBI_WR = 0x0
2262 23:11:03.847558 DBI_RD = 0x0
2263 23:11:03.848032 OTF = 0x1
2264 23:11:03.851045 ===================================
2265 23:11:03.854368 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2266 23:11:03.861137 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2267 23:11:03.864375 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 23:11:03.867961 ===================================
2269 23:11:03.870990 LPDDR4 DRAM CONFIGURATION
2270 23:11:03.874021 ===================================
2271 23:11:03.874495 EX_ROW_EN[0] = 0x10
2272 23:11:03.877670 EX_ROW_EN[1] = 0x0
2273 23:11:03.878145 LP4Y_EN = 0x0
2274 23:11:03.880878 WORK_FSP = 0x0
2275 23:11:03.881469 WL = 0x4
2276 23:11:03.884218 RL = 0x4
2277 23:11:03.884770 BL = 0x2
2278 23:11:03.887463 RPST = 0x0
2279 23:11:03.888015 RD_PRE = 0x0
2280 23:11:03.890912 WR_PRE = 0x1
2281 23:11:03.891465 WR_PST = 0x0
2282 23:11:03.894430 DBI_WR = 0x0
2283 23:11:03.894896 DBI_RD = 0x0
2284 23:11:03.897457 OTF = 0x1
2285 23:11:03.900946 ===================================
2286 23:11:03.907579 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2287 23:11:03.908118 ==
2288 23:11:03.910960 Dram Type= 6, Freq= 0, CH_0, rank 0
2289 23:11:03.914536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2290 23:11:03.915094 ==
2291 23:11:03.917352 [Duty_Offset_Calibration]
2292 23:11:03.917941 B0:2 B1:1 CA:1
2293 23:11:03.918312
2294 23:11:03.920903 [DutyScan_Calibration_Flow] k_type=0
2295 23:11:03.931706
2296 23:11:03.932217 ==CLK 0==
2297 23:11:03.934805 Final CLK duty delay cell = 0
2298 23:11:03.937986 [0] MAX Duty = 5187%(X100), DQS PI = 24
2299 23:11:03.941554 [0] MIN Duty = 4875%(X100), DQS PI = 0
2300 23:11:03.942005 [0] AVG Duty = 5031%(X100)
2301 23:11:03.945126
2302 23:11:03.945528 CH0 CLK Duty spec in!! Max-Min= 312%
2303 23:11:03.951559 [DutyScan_Calibration_Flow] ====Done====
2304 23:11:03.952086
2305 23:11:03.954903 [DutyScan_Calibration_Flow] k_type=1
2306 23:11:03.970060
2307 23:11:03.970466 ==DQS 0 ==
2308 23:11:03.973965 Final DQS duty delay cell = -4
2309 23:11:03.976793 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2310 23:11:03.980527 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2311 23:11:03.983694 [-4] AVG Duty = 4953%(X100)
2312 23:11:03.984108
2313 23:11:03.984434 ==DQS 1 ==
2314 23:11:03.986594 Final DQS duty delay cell = 0
2315 23:11:03.990062 [0] MAX Duty = 5156%(X100), DQS PI = 6
2316 23:11:03.993564 [0] MIN Duty = 5000%(X100), DQS PI = 34
2317 23:11:03.996765 [0] AVG Duty = 5078%(X100)
2318 23:11:03.997173
2319 23:11:04.000368 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2320 23:11:04.000885
2321 23:11:04.004026 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2322 23:11:04.006985 [DutyScan_Calibration_Flow] ====Done====
2323 23:11:04.007532
2324 23:11:04.010528 [DutyScan_Calibration_Flow] k_type=3
2325 23:11:04.027410
2326 23:11:04.027964 ==DQM 0 ==
2327 23:11:04.030706 Final DQM duty delay cell = 0
2328 23:11:04.033267 [0] MAX Duty = 5156%(X100), DQS PI = 30
2329 23:11:04.036656 [0] MIN Duty = 4875%(X100), DQS PI = 58
2330 23:11:04.037135 [0] AVG Duty = 5015%(X100)
2331 23:11:04.040170
2332 23:11:04.040620 ==DQM 1 ==
2333 23:11:04.043825 Final DQM duty delay cell = 0
2334 23:11:04.046848 [0] MAX Duty = 5093%(X100), DQS PI = 0
2335 23:11:04.049944 [0] MIN Duty = 5031%(X100), DQS PI = 14
2336 23:11:04.050369 [0] AVG Duty = 5062%(X100)
2337 23:11:04.053314
2338 23:11:04.056531 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2339 23:11:04.056958
2340 23:11:04.060134 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2341 23:11:04.063683 [DutyScan_Calibration_Flow] ====Done====
2342 23:11:04.064132
2343 23:11:04.067071 [DutyScan_Calibration_Flow] k_type=2
2344 23:11:04.083467
2345 23:11:04.084024 ==DQ 0 ==
2346 23:11:04.086914 Final DQ duty delay cell = 0
2347 23:11:04.090064 [0] MAX Duty = 5031%(X100), DQS PI = 24
2348 23:11:04.094054 [0] MIN Duty = 4844%(X100), DQS PI = 62
2349 23:11:04.094620 [0] AVG Duty = 4937%(X100)
2350 23:11:04.096978
2351 23:11:04.097375 ==DQ 1 ==
2352 23:11:04.099833 Final DQ duty delay cell = 0
2353 23:11:04.103584 [0] MAX Duty = 5093%(X100), DQS PI = 24
2354 23:11:04.106775 [0] MIN Duty = 4907%(X100), DQS PI = 36
2355 23:11:04.107403 [0] AVG Duty = 5000%(X100)
2356 23:11:04.107776
2357 23:11:04.110517 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2358 23:11:04.111073
2359 23:11:04.113961 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2360 23:11:04.120432 [DutyScan_Calibration_Flow] ====Done====
2361 23:11:04.121038 ==
2362 23:11:04.123615 Dram Type= 6, Freq= 0, CH_1, rank 0
2363 23:11:04.126909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2364 23:11:04.127364 ==
2365 23:11:04.130087 [Duty_Offset_Calibration]
2366 23:11:04.130539 B0:1 B1:0 CA:0
2367 23:11:04.130898
2368 23:11:04.133428 [DutyScan_Calibration_Flow] k_type=0
2369 23:11:04.142760
2370 23:11:04.143306 ==CLK 0==
2371 23:11:04.145893 Final CLK duty delay cell = -4
2372 23:11:04.149223 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2373 23:11:04.152912 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2374 23:11:04.156141 [-4] AVG Duty = 4937%(X100)
2375 23:11:04.156691
2376 23:11:04.159477 CH1 CLK Duty spec in!! Max-Min= 125%
2377 23:11:04.162298 [DutyScan_Calibration_Flow] ====Done====
2378 23:11:04.162747
2379 23:11:04.165805 [DutyScan_Calibration_Flow] k_type=1
2380 23:11:04.182707
2381 23:11:04.183255 ==DQS 0 ==
2382 23:11:04.186141 Final DQS duty delay cell = 0
2383 23:11:04.189408 [0] MAX Duty = 5062%(X100), DQS PI = 22
2384 23:11:04.192816 [0] MIN Duty = 4875%(X100), DQS PI = 0
2385 23:11:04.193374 [0] AVG Duty = 4968%(X100)
2386 23:11:04.193791
2387 23:11:04.196011 ==DQS 1 ==
2388 23:11:04.199190 Final DQS duty delay cell = 0
2389 23:11:04.202458 [0] MAX Duty = 5218%(X100), DQS PI = 18
2390 23:11:04.206511 [0] MIN Duty = 4938%(X100), DQS PI = 12
2391 23:11:04.207078 [0] AVG Duty = 5078%(X100)
2392 23:11:04.207438
2393 23:11:04.209952 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2394 23:11:04.213237
2395 23:11:04.216134 CH1 DQS 1 Duty spec in!! Max-Min= 280%
2396 23:11:04.219496 [DutyScan_Calibration_Flow] ====Done====
2397 23:11:04.219952
2398 23:11:04.222836 [DutyScan_Calibration_Flow] k_type=3
2399 23:11:04.239467
2400 23:11:04.240026 ==DQM 0 ==
2401 23:11:04.242381 Final DQM duty delay cell = 0
2402 23:11:04.245390 [0] MAX Duty = 5156%(X100), DQS PI = 6
2403 23:11:04.248972 [0] MIN Duty = 5031%(X100), DQS PI = 0
2404 23:11:04.249530 [0] AVG Duty = 5093%(X100)
2405 23:11:04.252242
2406 23:11:04.252797 ==DQM 1 ==
2407 23:11:04.255538 Final DQM duty delay cell = 0
2408 23:11:04.258906 [0] MAX Duty = 5031%(X100), DQS PI = 24
2409 23:11:04.262234 [0] MIN Duty = 4875%(X100), DQS PI = 36
2410 23:11:04.262793 [0] AVG Duty = 4953%(X100)
2411 23:11:04.265606
2412 23:11:04.269462 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2413 23:11:04.270085
2414 23:11:04.272750 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2415 23:11:04.275803 [DutyScan_Calibration_Flow] ====Done====
2416 23:11:04.276266
2417 23:11:04.278929 [DutyScan_Calibration_Flow] k_type=2
2418 23:11:04.294686
2419 23:11:04.295247 ==DQ 0 ==
2420 23:11:04.297945 Final DQ duty delay cell = -4
2421 23:11:04.301840 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2422 23:11:04.305092 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2423 23:11:04.308502 [-4] AVG Duty = 4984%(X100)
2424 23:11:04.309058
2425 23:11:04.309423 ==DQ 1 ==
2426 23:11:04.311712 Final DQ duty delay cell = 0
2427 23:11:04.314995 [0] MAX Duty = 5125%(X100), DQS PI = 20
2428 23:11:04.318258 [0] MIN Duty = 4969%(X100), DQS PI = 12
2429 23:11:04.318821 [0] AVG Duty = 5047%(X100)
2430 23:11:04.321151
2431 23:11:04.324743 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2432 23:11:04.325299
2433 23:11:04.328497 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2434 23:11:04.331199 [DutyScan_Calibration_Flow] ====Done====
2435 23:11:04.334660 nWR fixed to 30
2436 23:11:04.335141 [ModeRegInit_LP4] CH0 RK0
2437 23:11:04.338363 [ModeRegInit_LP4] CH0 RK1
2438 23:11:04.341686 [ModeRegInit_LP4] CH1 RK0
2439 23:11:04.344958 [ModeRegInit_LP4] CH1 RK1
2440 23:11:04.345412 match AC timing 7
2441 23:11:04.348391 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2442 23:11:04.355002 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2443 23:11:04.358199 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2444 23:11:04.361789 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2445 23:11:04.368534 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2446 23:11:04.369094 ==
2447 23:11:04.371922 Dram Type= 6, Freq= 0, CH_0, rank 0
2448 23:11:04.374503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2449 23:11:04.374965 ==
2450 23:11:04.381419 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2451 23:11:04.388202 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2452 23:11:04.395039 [CA 0] Center 39 (8~70) winsize 63
2453 23:11:04.397999 [CA 1] Center 39 (8~70) winsize 63
2454 23:11:04.401698 [CA 2] Center 35 (5~66) winsize 62
2455 23:11:04.404767 [CA 3] Center 34 (4~65) winsize 62
2456 23:11:04.409116 [CA 4] Center 33 (3~64) winsize 62
2457 23:11:04.411845 [CA 5] Center 32 (3~62) winsize 60
2458 23:11:04.412401
2459 23:11:04.414817 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2460 23:11:04.415377
2461 23:11:04.418590 [CATrainingPosCal] consider 1 rank data
2462 23:11:04.421873 u2DelayCellTimex100 = 270/100 ps
2463 23:11:04.425359 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2464 23:11:04.428551 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2465 23:11:04.434895 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2466 23:11:04.438292 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2467 23:11:04.441608 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2468 23:11:04.444943 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2469 23:11:04.445397
2470 23:11:04.448107 CA PerBit enable=1, Macro0, CA PI delay=32
2471 23:11:04.448565
2472 23:11:04.452177 [CBTSetCACLKResult] CA Dly = 32
2473 23:11:04.452746 CS Dly: 6 (0~37)
2474 23:11:04.453117 ==
2475 23:11:04.455324 Dram Type= 6, Freq= 0, CH_0, rank 1
2476 23:11:04.462212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2477 23:11:04.462774 ==
2478 23:11:04.465380 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2479 23:11:04.471758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2480 23:11:04.480988 [CA 0] Center 38 (8~69) winsize 62
2481 23:11:04.484105 [CA 1] Center 38 (8~69) winsize 62
2482 23:11:04.487633 [CA 2] Center 35 (5~66) winsize 62
2483 23:11:04.491228 [CA 3] Center 34 (4~65) winsize 62
2484 23:11:04.494182 [CA 4] Center 33 (3~64) winsize 62
2485 23:11:04.497422 [CA 5] Center 32 (3~62) winsize 60
2486 23:11:04.497939
2487 23:11:04.500981 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2488 23:11:04.501536
2489 23:11:04.504636 [CATrainingPosCal] consider 2 rank data
2490 23:11:04.507635 u2DelayCellTimex100 = 270/100 ps
2491 23:11:04.511142 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2492 23:11:04.514305 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2493 23:11:04.521243 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2494 23:11:04.524087 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2495 23:11:04.527839 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2496 23:11:04.530483 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2497 23:11:04.530941
2498 23:11:04.534210 CA PerBit enable=1, Macro0, CA PI delay=32
2499 23:11:04.534672
2500 23:11:04.537388 [CBTSetCACLKResult] CA Dly = 32
2501 23:11:04.537998 CS Dly: 6 (0~38)
2502 23:11:04.538378
2503 23:11:04.541064 ----->DramcWriteLeveling(PI) begin...
2504 23:11:04.544155 ==
2505 23:11:04.547419 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 23:11:04.551214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 23:11:04.551785 ==
2508 23:11:04.554104 Write leveling (Byte 0): 32 => 32
2509 23:11:04.557671 Write leveling (Byte 1): 31 => 31
2510 23:11:04.560610 DramcWriteLeveling(PI) end<-----
2511 23:11:04.561227
2512 23:11:04.561641 ==
2513 23:11:04.564344 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 23:11:04.567867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 23:11:04.568434 ==
2516 23:11:04.571410 [Gating] SW mode calibration
2517 23:11:04.577451 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2518 23:11:04.580811 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2519 23:11:04.587602 0 15 0 | B1->B0 | 2323 3333 | 1 1 | (0 0) (1 1)
2520 23:11:04.590767 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 23:11:04.594421 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 23:11:04.600842 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 23:11:04.604463 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 23:11:04.607528 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 23:11:04.614266 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2526 23:11:04.617702 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
2527 23:11:04.620748 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2528 23:11:04.627794 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 23:11:04.630525 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 23:11:04.634131 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 23:11:04.637187 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 23:11:04.643694 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 23:11:04.647500 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2534 23:11:04.650690 1 0 28 | B1->B0 | 2424 4545 | 0 1 | (0 0) (0 0)
2535 23:11:04.657526 1 1 0 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
2536 23:11:04.661041 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 23:11:04.664352 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 23:11:04.671107 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 23:11:04.674507 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 23:11:04.677396 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 23:11:04.684679 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 23:11:04.688459 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2543 23:11:04.691533 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2544 23:11:04.698053 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 23:11:04.701616 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 23:11:04.704785 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 23:11:04.711380 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 23:11:04.714586 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 23:11:04.718142 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 23:11:04.721561 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 23:11:04.727875 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 23:11:04.731294 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 23:11:04.734566 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 23:11:04.741251 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 23:11:04.744700 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 23:11:04.748156 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 23:11:04.754840 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 23:11:04.757948 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2559 23:11:04.761176 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2560 23:11:04.765273 Total UI for P1: 0, mck2ui 16
2561 23:11:04.768404 best dqsien dly found for B0: ( 1, 3, 28)
2562 23:11:04.774770 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 23:11:04.775319 Total UI for P1: 0, mck2ui 16
2564 23:11:04.781907 best dqsien dly found for B1: ( 1, 4, 0)
2565 23:11:04.784849 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2566 23:11:04.788085 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2567 23:11:04.788644
2568 23:11:04.791749 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2569 23:11:04.794860 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2570 23:11:04.798512 [Gating] SW calibration Done
2571 23:11:04.799070 ==
2572 23:11:04.801541 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 23:11:04.805015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 23:11:04.805609 ==
2575 23:11:04.805987 RX Vref Scan: 0
2576 23:11:04.808700
2577 23:11:04.809269 RX Vref 0 -> 0, step: 1
2578 23:11:04.809679
2579 23:11:04.812094 RX Delay -40 -> 252, step: 8
2580 23:11:04.814972 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2581 23:11:04.818469 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2582 23:11:04.825013 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2583 23:11:04.828201 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2584 23:11:04.831407 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2585 23:11:04.834666 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2586 23:11:04.838350 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2587 23:11:04.845012 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2588 23:11:04.848462 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2589 23:11:04.851829 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2590 23:11:04.855429 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2591 23:11:04.858500 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2592 23:11:04.861843 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2593 23:11:04.868317 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2594 23:11:04.872219 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2595 23:11:04.875383 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2596 23:11:04.875840 ==
2597 23:11:04.878158 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 23:11:04.882041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 23:11:04.882500 ==
2600 23:11:04.885010 DQS Delay:
2601 23:11:04.885463 DQS0 = 0, DQS1 = 0
2602 23:11:04.888768 DQM Delay:
2603 23:11:04.889222 DQM0 = 121, DQM1 = 113
2604 23:11:04.892292 DQ Delay:
2605 23:11:04.895263 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2606 23:11:04.898668 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2607 23:11:04.902181 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2608 23:11:04.905233 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2609 23:11:04.905822
2610 23:11:04.906188
2611 23:11:04.906525 ==
2612 23:11:04.908432 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 23:11:04.911826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 23:11:04.912288 ==
2615 23:11:04.912647
2616 23:11:04.912992
2617 23:11:04.915596 TX Vref Scan disable
2618 23:11:04.918868 == TX Byte 0 ==
2619 23:11:04.922559 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2620 23:11:04.925677 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2621 23:11:04.928571 == TX Byte 1 ==
2622 23:11:04.932086 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2623 23:11:04.935357 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2624 23:11:04.935772 ==
2625 23:11:04.938718 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 23:11:04.941666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 23:11:04.945063 ==
2628 23:11:04.955330 TX Vref=22, minBit 0, minWin=25, winSum=404
2629 23:11:04.958505 TX Vref=24, minBit 1, minWin=25, winSum=410
2630 23:11:04.962099 TX Vref=26, minBit 10, minWin=25, winSum=416
2631 23:11:04.964986 TX Vref=28, minBit 1, minWin=26, winSum=424
2632 23:11:04.968864 TX Vref=30, minBit 3, minWin=26, winSum=424
2633 23:11:04.972192 TX Vref=32, minBit 0, minWin=26, winSum=419
2634 23:11:04.978676 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 28
2635 23:11:04.979266
2636 23:11:04.981776 Final TX Range 1 Vref 28
2637 23:11:04.982295
2638 23:11:04.982628 ==
2639 23:11:04.985065 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 23:11:04.988707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 23:11:04.989232 ==
2642 23:11:04.989563
2643 23:11:04.992020
2644 23:11:04.992572 TX Vref Scan disable
2645 23:11:04.995296 == TX Byte 0 ==
2646 23:11:04.998944 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2647 23:11:05.002120 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2648 23:11:05.005490 == TX Byte 1 ==
2649 23:11:05.009003 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2650 23:11:05.011988 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2651 23:11:05.012405
2652 23:11:05.015748 [DATLAT]
2653 23:11:05.016278 Freq=1200, CH0 RK0
2654 23:11:05.016612
2655 23:11:05.018433 DATLAT Default: 0xd
2656 23:11:05.018847 0, 0xFFFF, sum = 0
2657 23:11:05.022499 1, 0xFFFF, sum = 0
2658 23:11:05.023023 2, 0xFFFF, sum = 0
2659 23:11:05.025723 3, 0xFFFF, sum = 0
2660 23:11:05.026270 4, 0xFFFF, sum = 0
2661 23:11:05.028704 5, 0xFFFF, sum = 0
2662 23:11:05.029228 6, 0xFFFF, sum = 0
2663 23:11:05.032222 7, 0xFFFF, sum = 0
2664 23:11:05.032751 8, 0xFFFF, sum = 0
2665 23:11:05.034880 9, 0xFFFF, sum = 0
2666 23:11:05.038404 10, 0xFFFF, sum = 0
2667 23:11:05.038824 11, 0xFFFF, sum = 0
2668 23:11:05.041793 12, 0x0, sum = 1
2669 23:11:05.042233 13, 0x0, sum = 2
2670 23:11:05.042682 14, 0x0, sum = 3
2671 23:11:05.045024 15, 0x0, sum = 4
2672 23:11:05.045457 best_step = 13
2673 23:11:05.045950
2674 23:11:05.046365 ==
2675 23:11:05.048738 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 23:11:05.055293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 23:11:05.055835 ==
2678 23:11:05.056292 RX Vref Scan: 1
2679 23:11:05.056719
2680 23:11:05.059080 Set Vref Range= 32 -> 127
2681 23:11:05.059623
2682 23:11:05.062149 RX Vref 32 -> 127, step: 1
2683 23:11:05.062583
2684 23:11:05.065603 RX Delay -13 -> 252, step: 4
2685 23:11:05.066040
2686 23:11:05.068518 Set Vref, RX VrefLevel [Byte0]: 32
2687 23:11:05.068953 [Byte1]: 32
2688 23:11:05.073433
2689 23:11:05.073900 Set Vref, RX VrefLevel [Byte0]: 33
2690 23:11:05.076877 [Byte1]: 33
2691 23:11:05.081286
2692 23:11:05.081751 Set Vref, RX VrefLevel [Byte0]: 34
2693 23:11:05.084304 [Byte1]: 34
2694 23:11:05.089353
2695 23:11:05.089822 Set Vref, RX VrefLevel [Byte0]: 35
2696 23:11:05.093055 [Byte1]: 35
2697 23:11:05.096861
2698 23:11:05.097271 Set Vref, RX VrefLevel [Byte0]: 36
2699 23:11:05.100381 [Byte1]: 36
2700 23:11:05.105699
2701 23:11:05.106283 Set Vref, RX VrefLevel [Byte0]: 37
2702 23:11:05.108802 [Byte1]: 37
2703 23:11:05.113125
2704 23:11:05.113706 Set Vref, RX VrefLevel [Byte0]: 38
2705 23:11:05.116617 [Byte1]: 38
2706 23:11:05.120974
2707 23:11:05.121512 Set Vref, RX VrefLevel [Byte0]: 39
2708 23:11:05.124063 [Byte1]: 39
2709 23:11:05.129064
2710 23:11:05.129623 Set Vref, RX VrefLevel [Byte0]: 40
2711 23:11:05.132164 [Byte1]: 40
2712 23:11:05.136801
2713 23:11:05.137334 Set Vref, RX VrefLevel [Byte0]: 41
2714 23:11:05.139566 [Byte1]: 41
2715 23:11:05.144923
2716 23:11:05.145432 Set Vref, RX VrefLevel [Byte0]: 42
2717 23:11:05.147787 [Byte1]: 42
2718 23:11:05.152501
2719 23:11:05.153057 Set Vref, RX VrefLevel [Byte0]: 43
2720 23:11:05.155980 [Byte1]: 43
2721 23:11:05.160227
2722 23:11:05.160776 Set Vref, RX VrefLevel [Byte0]: 44
2723 23:11:05.163710 [Byte1]: 44
2724 23:11:05.168174
2725 23:11:05.168668 Set Vref, RX VrefLevel [Byte0]: 45
2726 23:11:05.171477 [Byte1]: 45
2727 23:11:05.176214
2728 23:11:05.176766 Set Vref, RX VrefLevel [Byte0]: 46
2729 23:11:05.179058 [Byte1]: 46
2730 23:11:05.183877
2731 23:11:05.184439 Set Vref, RX VrefLevel [Byte0]: 47
2732 23:11:05.187331 [Byte1]: 47
2733 23:11:05.192016
2734 23:11:05.192734 Set Vref, RX VrefLevel [Byte0]: 48
2735 23:11:05.195330 [Byte1]: 48
2736 23:11:05.199970
2737 23:11:05.200521 Set Vref, RX VrefLevel [Byte0]: 49
2738 23:11:05.203402 [Byte1]: 49
2739 23:11:05.207842
2740 23:11:05.210628 Set Vref, RX VrefLevel [Byte0]: 50
2741 23:11:05.211180 [Byte1]: 50
2742 23:11:05.215689
2743 23:11:05.216242 Set Vref, RX VrefLevel [Byte0]: 51
2744 23:11:05.218473 [Byte1]: 51
2745 23:11:05.223323
2746 23:11:05.223887 Set Vref, RX VrefLevel [Byte0]: 52
2747 23:11:05.226817 [Byte1]: 52
2748 23:11:05.231418
2749 23:11:05.231880 Set Vref, RX VrefLevel [Byte0]: 53
2750 23:11:05.234372 [Byte1]: 53
2751 23:11:05.238835
2752 23:11:05.239343 Set Vref, RX VrefLevel [Byte0]: 54
2753 23:11:05.242421 [Byte1]: 54
2754 23:11:05.246962
2755 23:11:05.247516 Set Vref, RX VrefLevel [Byte0]: 55
2756 23:11:05.250162 [Byte1]: 55
2757 23:11:05.254863
2758 23:11:05.255416 Set Vref, RX VrefLevel [Byte0]: 56
2759 23:11:05.257990 [Byte1]: 56
2760 23:11:05.262629
2761 23:11:05.263217 Set Vref, RX VrefLevel [Byte0]: 57
2762 23:11:05.266098 [Byte1]: 57
2763 23:11:05.270987
2764 23:11:05.271540 Set Vref, RX VrefLevel [Byte0]: 58
2765 23:11:05.274304 [Byte1]: 58
2766 23:11:05.278535
2767 23:11:05.278995 Set Vref, RX VrefLevel [Byte0]: 59
2768 23:11:05.282546 [Byte1]: 59
2769 23:11:05.287160
2770 23:11:05.287711 Set Vref, RX VrefLevel [Byte0]: 60
2771 23:11:05.290208 [Byte1]: 60
2772 23:11:05.294593
2773 23:11:05.295050 Set Vref, RX VrefLevel [Byte0]: 61
2774 23:11:05.297857 [Byte1]: 61
2775 23:11:05.302424
2776 23:11:05.303033 Set Vref, RX VrefLevel [Byte0]: 62
2777 23:11:05.305508 [Byte1]: 62
2778 23:11:05.310429
2779 23:11:05.311253 Set Vref, RX VrefLevel [Byte0]: 63
2780 23:11:05.313291 [Byte1]: 63
2781 23:11:05.318256
2782 23:11:05.318828 Set Vref, RX VrefLevel [Byte0]: 64
2783 23:11:05.321044 [Byte1]: 64
2784 23:11:05.326279
2785 23:11:05.326858 Set Vref, RX VrefLevel [Byte0]: 65
2786 23:11:05.329124 [Byte1]: 65
2787 23:11:05.333764
2788 23:11:05.334230 Set Vref, RX VrefLevel [Byte0]: 66
2789 23:11:05.337253 [Byte1]: 66
2790 23:11:05.341352
2791 23:11:05.341935 Set Vref, RX VrefLevel [Byte0]: 67
2792 23:11:05.345059 [Byte1]: 67
2793 23:11:05.349694
2794 23:11:05.350154 Set Vref, RX VrefLevel [Byte0]: 68
2795 23:11:05.353145 [Byte1]: 68
2796 23:11:05.357567
2797 23:11:05.358133 Set Vref, RX VrefLevel [Byte0]: 69
2798 23:11:05.360575 [Byte1]: 69
2799 23:11:05.365108
2800 23:11:05.365708 Set Vref, RX VrefLevel [Byte0]: 70
2801 23:11:05.368658 [Byte1]: 70
2802 23:11:05.373814
2803 23:11:05.374363 Final RX Vref Byte 0 = 54 to rank0
2804 23:11:05.377109 Final RX Vref Byte 1 = 55 to rank0
2805 23:11:05.379862 Final RX Vref Byte 0 = 54 to rank1
2806 23:11:05.383059 Final RX Vref Byte 1 = 55 to rank1==
2807 23:11:05.386430 Dram Type= 6, Freq= 0, CH_0, rank 0
2808 23:11:05.390206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2809 23:11:05.393525 ==
2810 23:11:05.394123 DQS Delay:
2811 23:11:05.394493 DQS0 = 0, DQS1 = 0
2812 23:11:05.396769 DQM Delay:
2813 23:11:05.397227 DQM0 = 120, DQM1 = 113
2814 23:11:05.400125 DQ Delay:
2815 23:11:05.403134 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2816 23:11:05.406654 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2817 23:11:05.409950 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =106
2818 23:11:05.413698 DQ12 =120, DQ13 =116, DQ14 =126, DQ15 =122
2819 23:11:05.414255
2820 23:11:05.414623
2821 23:11:05.420222 [DQSOSCAuto] RK0, (LSB)MR18= 0x130c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2822 23:11:05.423587 CH0 RK0: MR19=404, MR18=130C
2823 23:11:05.430153 CH0_RK0: MR19=0x404, MR18=0x130C, DQSOSC=402, MR23=63, INC=40, DEC=27
2824 23:11:05.430697
2825 23:11:05.433756 ----->DramcWriteLeveling(PI) begin...
2826 23:11:05.434225 ==
2827 23:11:05.436523 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 23:11:05.439991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 23:11:05.443459 ==
2830 23:11:05.444018 Write leveling (Byte 0): 32 => 32
2831 23:11:05.446851 Write leveling (Byte 1): 28 => 28
2832 23:11:05.449985 DramcWriteLeveling(PI) end<-----
2833 23:11:05.450448
2834 23:11:05.450811 ==
2835 23:11:05.453711 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 23:11:05.460449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 23:11:05.461023 ==
2838 23:11:05.461395 [Gating] SW mode calibration
2839 23:11:05.470421 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2840 23:11:05.473725 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2841 23:11:05.476961 0 15 0 | B1->B0 | 2e2e 2c2c | 1 0 | (1 1) (1 1)
2842 23:11:05.483526 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 23:11:05.487505 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 23:11:05.490234 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 23:11:05.496866 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 23:11:05.500849 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 23:11:05.503855 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 23:11:05.511061 0 15 28 | B1->B0 | 2e2e 2b2b | 1 0 | (1 1) (0 1)
2849 23:11:05.514177 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2850 23:11:05.517722 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 23:11:05.524409 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 23:11:05.527655 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 23:11:05.530900 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 23:11:05.533762 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 23:11:05.540939 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2856 23:11:05.543895 1 0 28 | B1->B0 | 3232 3838 | 0 0 | (0 0) (0 0)
2857 23:11:05.547795 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 23:11:05.553763 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 23:11:05.557306 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 23:11:05.560715 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 23:11:05.567238 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 23:11:05.570899 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 23:11:05.574470 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 23:11:05.580758 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2865 23:11:05.584323 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2866 23:11:05.587655 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 23:11:05.594082 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 23:11:05.597368 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 23:11:05.601069 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 23:11:05.604262 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 23:11:05.611007 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 23:11:05.614544 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 23:11:05.617486 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 23:11:05.624736 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 23:11:05.627591 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 23:11:05.630791 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 23:11:05.637664 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 23:11:05.640944 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 23:11:05.644278 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 23:11:05.650593 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2881 23:11:05.654626 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 23:11:05.657525 Total UI for P1: 0, mck2ui 16
2883 23:11:05.661407 best dqsien dly found for B0: ( 1, 3, 28)
2884 23:11:05.664297 Total UI for P1: 0, mck2ui 16
2885 23:11:05.667435 best dqsien dly found for B1: ( 1, 3, 28)
2886 23:11:05.670913 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2887 23:11:05.674143 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2888 23:11:05.674601
2889 23:11:05.677306 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2890 23:11:05.680844 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2891 23:11:05.684635 [Gating] SW calibration Done
2892 23:11:05.685190 ==
2893 23:11:05.687604 Dram Type= 6, Freq= 0, CH_0, rank 1
2894 23:11:05.690897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2895 23:11:05.691455 ==
2896 23:11:05.694601 RX Vref Scan: 0
2897 23:11:05.695211
2898 23:11:05.697327 RX Vref 0 -> 0, step: 1
2899 23:11:05.697933
2900 23:11:05.698298 RX Delay -40 -> 252, step: 8
2901 23:11:05.704040 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2902 23:11:05.707638 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2903 23:11:05.711157 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2904 23:11:05.714555 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2905 23:11:05.717300 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2906 23:11:05.724215 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2907 23:11:05.727725 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2908 23:11:05.730584 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2909 23:11:05.734240 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2910 23:11:05.737528 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2911 23:11:05.744133 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2912 23:11:05.747460 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2913 23:11:05.750716 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2914 23:11:05.754607 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2915 23:11:05.757494 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2916 23:11:05.764214 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2917 23:11:05.764770 ==
2918 23:11:05.767293 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 23:11:05.770978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 23:11:05.771531 ==
2921 23:11:05.771899 DQS Delay:
2922 23:11:05.774184 DQS0 = 0, DQS1 = 0
2923 23:11:05.774640 DQM Delay:
2924 23:11:05.777692 DQM0 = 122, DQM1 = 114
2925 23:11:05.778143 DQ Delay:
2926 23:11:05.781219 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2927 23:11:05.784267 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2928 23:11:05.787180 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =107
2929 23:11:05.791168 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2930 23:11:05.791680
2931 23:11:05.792011
2932 23:11:05.794246 ==
2933 23:11:05.797967 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 23:11:05.801321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 23:11:05.801880 ==
2936 23:11:05.802221
2937 23:11:05.802526
2938 23:11:05.804364 TX Vref Scan disable
2939 23:11:05.804877 == TX Byte 0 ==
2940 23:11:05.807430 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2941 23:11:05.814344 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2942 23:11:05.814856 == TX Byte 1 ==
2943 23:11:05.818023 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2944 23:11:05.824897 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2945 23:11:05.825416 ==
2946 23:11:05.828092 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 23:11:05.831808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 23:11:05.832347 ==
2949 23:11:05.843099 TX Vref=22, minBit 1, minWin=25, winSum=416
2950 23:11:05.846153 TX Vref=24, minBit 1, minWin=25, winSum=419
2951 23:11:05.849761 TX Vref=26, minBit 13, minWin=25, winSum=419
2952 23:11:05.853111 TX Vref=28, minBit 3, minWin=25, winSum=429
2953 23:11:05.856285 TX Vref=30, minBit 7, minWin=26, winSum=433
2954 23:11:05.863528 TX Vref=32, minBit 0, minWin=26, winSum=427
2955 23:11:05.866598 [TxChooseVref] Worse bit 7, Min win 26, Win sum 433, Final Vref 30
2956 23:11:05.867056
2957 23:11:05.869810 Final TX Range 1 Vref 30
2958 23:11:05.870354
2959 23:11:05.870720 ==
2960 23:11:05.873053 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 23:11:05.876401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 23:11:05.876961 ==
2963 23:11:05.879786
2964 23:11:05.880333
2965 23:11:05.880697 TX Vref Scan disable
2966 23:11:05.883318 == TX Byte 0 ==
2967 23:11:05.886199 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2968 23:11:05.889846 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2969 23:11:05.892979 == TX Byte 1 ==
2970 23:11:05.896656 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2971 23:11:05.903097 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2972 23:11:05.903646
2973 23:11:05.904010 [DATLAT]
2974 23:11:05.904348 Freq=1200, CH0 RK1
2975 23:11:05.904676
2976 23:11:05.905966 DATLAT Default: 0xd
2977 23:11:05.906508 0, 0xFFFF, sum = 0
2978 23:11:05.910102 1, 0xFFFF, sum = 0
2979 23:11:05.910662 2, 0xFFFF, sum = 0
2980 23:11:05.913204 3, 0xFFFF, sum = 0
2981 23:11:05.916318 4, 0xFFFF, sum = 0
2982 23:11:05.916931 5, 0xFFFF, sum = 0
2983 23:11:05.919876 6, 0xFFFF, sum = 0
2984 23:11:05.920433 7, 0xFFFF, sum = 0
2985 23:11:05.923150 8, 0xFFFF, sum = 0
2986 23:11:05.923616 9, 0xFFFF, sum = 0
2987 23:11:05.926258 10, 0xFFFF, sum = 0
2988 23:11:05.926721 11, 0xFFFF, sum = 0
2989 23:11:05.929713 12, 0x0, sum = 1
2990 23:11:05.930271 13, 0x0, sum = 2
2991 23:11:05.932992 14, 0x0, sum = 3
2992 23:11:05.933456 15, 0x0, sum = 4
2993 23:11:05.933881 best_step = 13
2994 23:11:05.936633
2995 23:11:05.937077 ==
2996 23:11:05.939696 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 23:11:05.942746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 23:11:05.943204 ==
2999 23:11:05.943566 RX Vref Scan: 0
3000 23:11:05.943901
3001 23:11:05.946160 RX Vref 0 -> 0, step: 1
3002 23:11:05.946613
3003 23:11:05.949751 RX Delay -13 -> 252, step: 4
3004 23:11:05.952936 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3005 23:11:05.959909 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3006 23:11:05.962988 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3007 23:11:05.966033 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3008 23:11:05.969471 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3009 23:11:05.973016 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3010 23:11:05.976657 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3011 23:11:05.983108 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3012 23:11:05.986681 iDelay=195, Bit 8, Center 102 (35 ~ 170) 136
3013 23:11:05.990203 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3014 23:11:05.993231 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3015 23:11:05.996540 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3016 23:11:06.003236 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3017 23:11:06.006327 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3018 23:11:06.009801 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3019 23:11:06.013664 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3020 23:11:06.014179 ==
3021 23:11:06.016509 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 23:11:06.023868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 23:11:06.024426 ==
3024 23:11:06.024792 DQS Delay:
3025 23:11:06.026323 DQS0 = 0, DQS1 = 0
3026 23:11:06.026974 DQM Delay:
3027 23:11:06.027522 DQM0 = 121, DQM1 = 111
3028 23:11:06.029866 DQ Delay:
3029 23:11:06.033573 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3030 23:11:06.036418 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3031 23:11:06.039722 DQ8 =102, DQ9 =100, DQ10 =112, DQ11 =104
3032 23:11:06.043260 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3033 23:11:06.043687
3034 23:11:06.044127
3035 23:11:06.049723 [DQSOSCAuto] RK1, (LSB)MR18= 0xdef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3036 23:11:06.053365 CH0 RK1: MR19=403, MR18=DEF
3037 23:11:06.059977 CH0_RK1: MR19=0x403, MR18=0xDEF, DQSOSC=405, MR23=63, INC=39, DEC=26
3038 23:11:06.063229 [RxdqsGatingPostProcess] freq 1200
3039 23:11:06.069859 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3040 23:11:06.073931 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 23:11:06.074525 best DQS1 dly(2T, 0.5T) = (0, 12)
3042 23:11:06.076825 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 23:11:06.080158 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3044 23:11:06.083767 best DQS0 dly(2T, 0.5T) = (0, 11)
3045 23:11:06.086814 best DQS1 dly(2T, 0.5T) = (0, 11)
3046 23:11:06.090223 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3047 23:11:06.093810 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3048 23:11:06.096866 Pre-setting of DQS Precalculation
3049 23:11:06.100324 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3050 23:11:06.103676 ==
3051 23:11:06.106668 Dram Type= 6, Freq= 0, CH_1, rank 0
3052 23:11:06.110104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 23:11:06.110592 ==
3054 23:11:06.113688 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3055 23:11:06.120350 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3056 23:11:06.129734 [CA 0] Center 37 (7~68) winsize 62
3057 23:11:06.132695 [CA 1] Center 37 (7~68) winsize 62
3058 23:11:06.136294 [CA 2] Center 35 (5~65) winsize 61
3059 23:11:06.139349 [CA 3] Center 34 (4~64) winsize 61
3060 23:11:06.142439 [CA 4] Center 34 (4~64) winsize 61
3061 23:11:06.146129 [CA 5] Center 33 (3~63) winsize 61
3062 23:11:06.146556
3063 23:11:06.149259 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3064 23:11:06.149726
3065 23:11:06.152791 [CATrainingPosCal] consider 1 rank data
3066 23:11:06.156043 u2DelayCellTimex100 = 270/100 ps
3067 23:11:06.160011 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3068 23:11:06.162576 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3069 23:11:06.165792 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3070 23:11:06.172705 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3071 23:11:06.176137 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3072 23:11:06.179618 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3073 23:11:06.180034
3074 23:11:06.182772 CA PerBit enable=1, Macro0, CA PI delay=33
3075 23:11:06.183186
3076 23:11:06.185801 [CBTSetCACLKResult] CA Dly = 33
3077 23:11:06.186333 CS Dly: 8 (0~39)
3078 23:11:06.186761 ==
3079 23:11:06.189569 Dram Type= 6, Freq= 0, CH_1, rank 1
3080 23:11:06.196153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 23:11:06.196627 ==
3082 23:11:06.199090 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3083 23:11:06.206101 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3084 23:11:06.215161 [CA 0] Center 37 (7~68) winsize 62
3085 23:11:06.218182 [CA 1] Center 37 (7~68) winsize 62
3086 23:11:06.221925 [CA 2] Center 35 (5~65) winsize 61
3087 23:11:06.224831 [CA 3] Center 34 (4~65) winsize 62
3088 23:11:06.228497 [CA 4] Center 34 (4~65) winsize 62
3089 23:11:06.231307 [CA 5] Center 34 (4~64) winsize 61
3090 23:11:06.231722
3091 23:11:06.235295 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3092 23:11:06.235911
3093 23:11:06.238031 [CATrainingPosCal] consider 2 rank data
3094 23:11:06.241985 u2DelayCellTimex100 = 270/100 ps
3095 23:11:06.244720 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3096 23:11:06.248284 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3097 23:11:06.255028 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3098 23:11:06.258485 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3099 23:11:06.261552 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3100 23:11:06.264926 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3101 23:11:06.265355
3102 23:11:06.267979 CA PerBit enable=1, Macro0, CA PI delay=33
3103 23:11:06.268404
3104 23:11:06.271404 [CBTSetCACLKResult] CA Dly = 33
3105 23:11:06.271825 CS Dly: 9 (0~41)
3106 23:11:06.272258
3107 23:11:06.274977 ----->DramcWriteLeveling(PI) begin...
3108 23:11:06.278370 ==
3109 23:11:06.278794 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 23:11:06.284852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 23:11:06.285268 ==
3112 23:11:06.288151 Write leveling (Byte 0): 26 => 26
3113 23:11:06.291834 Write leveling (Byte 1): 27 => 27
3114 23:11:06.295288 DramcWriteLeveling(PI) end<-----
3115 23:11:06.295699
3116 23:11:06.296028 ==
3117 23:11:06.298285 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 23:11:06.302003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 23:11:06.302514 ==
3120 23:11:06.304676 [Gating] SW mode calibration
3121 23:11:06.311432 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3122 23:11:06.314644 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3123 23:11:06.321666 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3124 23:11:06.325060 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 23:11:06.328850 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 23:11:06.334518 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 23:11:06.338134 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 23:11:06.341434 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 23:11:06.348232 0 15 24 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (0 0)
3130 23:11:06.351498 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3131 23:11:06.354941 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 23:11:06.361334 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 23:11:06.364505 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 23:11:06.368249 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 23:11:06.374556 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 23:11:06.378214 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 23:11:06.381221 1 0 24 | B1->B0 | 3333 4141 | 1 0 | (0 0) (0 0)
3138 23:11:06.388038 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 23:11:06.391311 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 23:11:06.394637 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 23:11:06.401140 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 23:11:06.404498 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 23:11:06.407722 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 23:11:06.411591 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 23:11:06.418302 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3146 23:11:06.421154 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3147 23:11:06.424637 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 23:11:06.431292 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 23:11:06.434708 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 23:11:06.438054 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 23:11:06.445145 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 23:11:06.447868 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 23:11:06.451328 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 23:11:06.458407 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 23:11:06.462073 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 23:11:06.465144 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 23:11:06.471608 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 23:11:06.474911 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 23:11:06.478427 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 23:11:06.484985 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 23:11:06.488699 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3162 23:11:06.491247 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3163 23:11:06.495386 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 23:11:06.498311 Total UI for P1: 0, mck2ui 16
3165 23:11:06.501865 best dqsien dly found for B0: ( 1, 3, 26)
3166 23:11:06.505053 Total UI for P1: 0, mck2ui 16
3167 23:11:06.508172 best dqsien dly found for B1: ( 1, 3, 26)
3168 23:11:06.511766 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3169 23:11:06.515044 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3170 23:11:06.518125
3171 23:11:06.521785 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3172 23:11:06.525407 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3173 23:11:06.528453 [Gating] SW calibration Done
3174 23:11:06.529002 ==
3175 23:11:06.531717 Dram Type= 6, Freq= 0, CH_1, rank 0
3176 23:11:06.535159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3177 23:11:06.535867 ==
3178 23:11:06.536419 RX Vref Scan: 0
3179 23:11:06.536816
3180 23:11:06.538113 RX Vref 0 -> 0, step: 1
3181 23:11:06.538651
3182 23:11:06.541176 RX Delay -40 -> 252, step: 8
3183 23:11:06.544569 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3184 23:11:06.548032 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3185 23:11:06.554905 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3186 23:11:06.558804 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3187 23:11:06.561398 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3188 23:11:06.564717 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3189 23:11:06.568330 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3190 23:11:06.575102 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3191 23:11:06.578196 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3192 23:11:06.581410 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3193 23:11:06.584744 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3194 23:11:06.588172 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3195 23:11:06.594737 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3196 23:11:06.598215 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3197 23:11:06.601273 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3198 23:11:06.604689 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3199 23:11:06.605151 ==
3200 23:11:06.607966 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 23:11:06.615088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 23:11:06.615524 ==
3203 23:11:06.615862 DQS Delay:
3204 23:11:06.617692 DQS0 = 0, DQS1 = 0
3205 23:11:06.618112 DQM Delay:
3206 23:11:06.618449 DQM0 = 120, DQM1 = 116
3207 23:11:06.621474 DQ Delay:
3208 23:11:06.624806 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3209 23:11:06.628360 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3210 23:11:06.631371 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3211 23:11:06.634610 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3212 23:11:06.635030
3213 23:11:06.635360
3214 23:11:06.635665 ==
3215 23:11:06.638023 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 23:11:06.641205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 23:11:06.644740 ==
3218 23:11:06.645156
3219 23:11:06.645489
3220 23:11:06.645886 TX Vref Scan disable
3221 23:11:06.647998 == TX Byte 0 ==
3222 23:11:06.651122 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3223 23:11:06.655023 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3224 23:11:06.657901 == TX Byte 1 ==
3225 23:11:06.661182 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3226 23:11:06.665343 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3227 23:11:06.666048 ==
3228 23:11:06.668114 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 23:11:06.674561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 23:11:06.674979 ==
3231 23:11:06.685077 TX Vref=22, minBit 9, minWin=24, winSum=413
3232 23:11:06.688239 TX Vref=24, minBit 9, minWin=24, winSum=416
3233 23:11:06.691484 TX Vref=26, minBit 9, minWin=25, winSum=420
3234 23:11:06.695019 TX Vref=28, minBit 12, minWin=25, winSum=426
3235 23:11:06.698341 TX Vref=30, minBit 1, minWin=26, winSum=431
3236 23:11:06.705750 TX Vref=32, minBit 9, minWin=26, winSum=430
3237 23:11:06.708783 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3238 23:11:06.709204
3239 23:11:06.712097 Final TX Range 1 Vref 30
3240 23:11:06.712616
3241 23:11:06.712948 ==
3242 23:11:06.715177 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 23:11:06.718713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 23:11:06.719285 ==
3245 23:11:06.719676
3246 23:11:06.722092
3247 23:11:06.722607 TX Vref Scan disable
3248 23:11:06.725042 == TX Byte 0 ==
3249 23:11:06.728271 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3250 23:11:06.731500 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3251 23:11:06.735131 == TX Byte 1 ==
3252 23:11:06.738618 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3253 23:11:06.741528 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3254 23:11:06.742075
3255 23:11:06.745348 [DATLAT]
3256 23:11:06.746026 Freq=1200, CH1 RK0
3257 23:11:06.746523
3258 23:11:06.748056 DATLAT Default: 0xd
3259 23:11:06.748547 0, 0xFFFF, sum = 0
3260 23:11:06.751823 1, 0xFFFF, sum = 0
3261 23:11:06.752251 2, 0xFFFF, sum = 0
3262 23:11:06.755327 3, 0xFFFF, sum = 0
3263 23:11:06.755750 4, 0xFFFF, sum = 0
3264 23:11:06.758678 5, 0xFFFF, sum = 0
3265 23:11:06.759103 6, 0xFFFF, sum = 0
3266 23:11:06.762234 7, 0xFFFF, sum = 0
3267 23:11:06.762661 8, 0xFFFF, sum = 0
3268 23:11:06.764947 9, 0xFFFF, sum = 0
3269 23:11:06.768337 10, 0xFFFF, sum = 0
3270 23:11:06.768893 11, 0xFFFF, sum = 0
3271 23:11:06.771871 12, 0x0, sum = 1
3272 23:11:06.772444 13, 0x0, sum = 2
3273 23:11:06.772997 14, 0x0, sum = 3
3274 23:11:06.775127 15, 0x0, sum = 4
3275 23:11:06.775691 best_step = 13
3276 23:11:06.776163
3277 23:11:06.776535 ==
3278 23:11:06.778098 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 23:11:06.785246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 23:11:06.785721 ==
3281 23:11:06.786087 RX Vref Scan: 1
3282 23:11:06.786435
3283 23:11:06.788656 Set Vref Range= 32 -> 127
3284 23:11:06.789072
3285 23:11:06.791814 RX Vref 32 -> 127, step: 1
3286 23:11:06.792248
3287 23:11:06.795477 RX Delay -5 -> 252, step: 4
3288 23:11:06.796035
3289 23:11:06.798389 Set Vref, RX VrefLevel [Byte0]: 32
3290 23:11:06.801712 [Byte1]: 32
3291 23:11:06.802134
3292 23:11:06.804999 Set Vref, RX VrefLevel [Byte0]: 33
3293 23:11:06.808458 [Byte1]: 33
3294 23:11:06.808826
3295 23:11:06.811645 Set Vref, RX VrefLevel [Byte0]: 34
3296 23:11:06.815051 [Byte1]: 34
3297 23:11:06.818870
3298 23:11:06.819282 Set Vref, RX VrefLevel [Byte0]: 35
3299 23:11:06.822085 [Byte1]: 35
3300 23:11:06.826955
3301 23:11:06.827341 Set Vref, RX VrefLevel [Byte0]: 36
3302 23:11:06.829946 [Byte1]: 36
3303 23:11:06.834499
3304 23:11:06.834792 Set Vref, RX VrefLevel [Byte0]: 37
3305 23:11:06.837926 [Byte1]: 37
3306 23:11:06.842490
3307 23:11:06.842668 Set Vref, RX VrefLevel [Byte0]: 38
3308 23:11:06.845616 [Byte1]: 38
3309 23:11:06.850296
3310 23:11:06.850462 Set Vref, RX VrefLevel [Byte0]: 39
3311 23:11:06.853050 [Byte1]: 39
3312 23:11:06.857944
3313 23:11:06.858060 Set Vref, RX VrefLevel [Byte0]: 40
3314 23:11:06.861572 [Byte1]: 40
3315 23:11:06.865759
3316 23:11:06.865859 Set Vref, RX VrefLevel [Byte0]: 41
3317 23:11:06.868899 [Byte1]: 41
3318 23:11:06.873398
3319 23:11:06.873498 Set Vref, RX VrefLevel [Byte0]: 42
3320 23:11:06.877557 [Byte1]: 42
3321 23:11:06.881659
3322 23:11:06.881821 Set Vref, RX VrefLevel [Byte0]: 43
3323 23:11:06.884749 [Byte1]: 43
3324 23:11:06.889453
3325 23:11:06.889638 Set Vref, RX VrefLevel [Byte0]: 44
3326 23:11:06.892691 [Byte1]: 44
3327 23:11:06.897506
3328 23:11:06.897684 Set Vref, RX VrefLevel [Byte0]: 45
3329 23:11:06.900680 [Byte1]: 45
3330 23:11:06.904907
3331 23:11:06.905028 Set Vref, RX VrefLevel [Byte0]: 46
3332 23:11:06.908413 [Byte1]: 46
3333 23:11:06.912832
3334 23:11:06.913002 Set Vref, RX VrefLevel [Byte0]: 47
3335 23:11:06.916129 [Byte1]: 47
3336 23:11:06.921021
3337 23:11:06.921257 Set Vref, RX VrefLevel [Byte0]: 48
3338 23:11:06.923920 [Byte1]: 48
3339 23:11:06.928838
3340 23:11:06.929131 Set Vref, RX VrefLevel [Byte0]: 49
3341 23:11:06.932126 [Byte1]: 49
3342 23:11:06.936412
3343 23:11:06.936839 Set Vref, RX VrefLevel [Byte0]: 50
3344 23:11:06.939759 [Byte1]: 50
3345 23:11:06.944210
3346 23:11:06.944624 Set Vref, RX VrefLevel [Byte0]: 51
3347 23:11:06.947934 [Byte1]: 51
3348 23:11:06.952233
3349 23:11:06.952650 Set Vref, RX VrefLevel [Byte0]: 52
3350 23:11:06.955768 [Byte1]: 52
3351 23:11:06.960243
3352 23:11:06.960652 Set Vref, RX VrefLevel [Byte0]: 53
3353 23:11:06.963866 [Byte1]: 53
3354 23:11:06.968116
3355 23:11:06.968531 Set Vref, RX VrefLevel [Byte0]: 54
3356 23:11:06.971857 [Byte1]: 54
3357 23:11:06.975845
3358 23:11:06.976257 Set Vref, RX VrefLevel [Byte0]: 55
3359 23:11:06.979484 [Byte1]: 55
3360 23:11:06.983848
3361 23:11:06.984263 Set Vref, RX VrefLevel [Byte0]: 56
3362 23:11:06.987271 [Byte1]: 56
3363 23:11:06.991886
3364 23:11:06.992419 Set Vref, RX VrefLevel [Byte0]: 57
3365 23:11:06.995136 [Byte1]: 57
3366 23:11:06.999418
3367 23:11:06.999967 Set Vref, RX VrefLevel [Byte0]: 58
3368 23:11:07.003253 [Byte1]: 58
3369 23:11:07.007270
3370 23:11:07.007730 Set Vref, RX VrefLevel [Byte0]: 59
3371 23:11:07.010474 [Byte1]: 59
3372 23:11:07.015325
3373 23:11:07.015742 Set Vref, RX VrefLevel [Byte0]: 60
3374 23:11:07.018285 [Byte1]: 60
3375 23:11:07.023579
3376 23:11:07.024104 Set Vref, RX VrefLevel [Byte0]: 61
3377 23:11:07.026870 [Byte1]: 61
3378 23:11:07.030745
3379 23:11:07.031553 Set Vref, RX VrefLevel [Byte0]: 62
3380 23:11:07.034318 [Byte1]: 62
3381 23:11:07.038441
3382 23:11:07.038856 Set Vref, RX VrefLevel [Byte0]: 63
3383 23:11:07.041914 [Byte1]: 63
3384 23:11:07.046716
3385 23:11:07.047154 Set Vref, RX VrefLevel [Byte0]: 64
3386 23:11:07.049860 [Byte1]: 64
3387 23:11:07.054235
3388 23:11:07.054669 Set Vref, RX VrefLevel [Byte0]: 65
3389 23:11:07.058012 [Byte1]: 65
3390 23:11:07.062285
3391 23:11:07.062695 Set Vref, RX VrefLevel [Byte0]: 66
3392 23:11:07.065948 [Byte1]: 66
3393 23:11:07.070318
3394 23:11:07.070729 Set Vref, RX VrefLevel [Byte0]: 67
3395 23:11:07.073278 [Byte1]: 67
3396 23:11:07.077967
3397 23:11:07.078378 Final RX Vref Byte 0 = 54 to rank0
3398 23:11:07.081409 Final RX Vref Byte 1 = 54 to rank0
3399 23:11:07.084607 Final RX Vref Byte 0 = 54 to rank1
3400 23:11:07.087937 Final RX Vref Byte 1 = 54 to rank1==
3401 23:11:07.091675 Dram Type= 6, Freq= 0, CH_1, rank 0
3402 23:11:07.094789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3403 23:11:07.098024 ==
3404 23:11:07.098475 DQS Delay:
3405 23:11:07.098838 DQS0 = 0, DQS1 = 0
3406 23:11:07.101401 DQM Delay:
3407 23:11:07.101855 DQM0 = 119, DQM1 = 117
3408 23:11:07.104514 DQ Delay:
3409 23:11:07.107702 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3410 23:11:07.111648 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =120
3411 23:11:07.114948 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3412 23:11:07.117885 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3413 23:11:07.118309
3414 23:11:07.118655
3415 23:11:07.125277 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3416 23:11:07.128327 CH1 RK0: MR19=404, MR18=215
3417 23:11:07.134972 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3418 23:11:07.135404
3419 23:11:07.138068 ----->DramcWriteLeveling(PI) begin...
3420 23:11:07.138645 ==
3421 23:11:07.141217 Dram Type= 6, Freq= 0, CH_1, rank 1
3422 23:11:07.144821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 23:11:07.145442 ==
3424 23:11:07.147916 Write leveling (Byte 0): 25 => 25
3425 23:11:07.151066 Write leveling (Byte 1): 29 => 29
3426 23:11:07.154543 DramcWriteLeveling(PI) end<-----
3427 23:11:07.154998
3428 23:11:07.155338 ==
3429 23:11:07.157908 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 23:11:07.164860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 23:11:07.165466 ==
3432 23:11:07.165894 [Gating] SW mode calibration
3433 23:11:07.175016 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3434 23:11:07.177802 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3435 23:11:07.181441 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 23:11:07.188262 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 23:11:07.191566 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 23:11:07.194492 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 23:11:07.200959 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 23:11:07.204716 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3441 23:11:07.208088 0 15 24 | B1->B0 | 2a2a 3434 | 1 1 | (1 0) (1 1)
3442 23:11:07.214892 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
3443 23:11:07.218016 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 23:11:07.221648 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 23:11:07.228143 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 23:11:07.231159 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 23:11:07.234745 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 23:11:07.241508 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3449 23:11:07.244522 1 0 24 | B1->B0 | 4545 2626 | 0 0 | (0 0) (0 0)
3450 23:11:07.247945 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 23:11:07.254711 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 23:11:07.258079 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 23:11:07.261299 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 23:11:07.264184 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 23:11:07.271091 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 23:11:07.274704 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3457 23:11:07.277880 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3458 23:11:07.284582 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3459 23:11:07.287787 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3460 23:11:07.290806 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 23:11:07.297697 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 23:11:07.301039 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 23:11:07.304032 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 23:11:07.311184 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 23:11:07.314174 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 23:11:07.317424 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 23:11:07.324989 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 23:11:07.327717 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 23:11:07.330763 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 23:11:07.337740 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 23:11:07.340842 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 23:11:07.344309 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3473 23:11:07.350654 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3474 23:11:07.353799 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3475 23:11:07.357558 Total UI for P1: 0, mck2ui 16
3476 23:11:07.360528 best dqsien dly found for B1: ( 1, 3, 22)
3477 23:11:07.364351 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 23:11:07.367645 Total UI for P1: 0, mck2ui 16
3479 23:11:07.370824 best dqsien dly found for B0: ( 1, 3, 26)
3480 23:11:07.373931 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3481 23:11:07.377132 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3482 23:11:07.377544
3483 23:11:07.383924 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3484 23:11:07.387667 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3485 23:11:07.388178 [Gating] SW calibration Done
3486 23:11:07.390345 ==
3487 23:11:07.393796 Dram Type= 6, Freq= 0, CH_1, rank 1
3488 23:11:07.396884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 23:11:07.397429 ==
3490 23:11:07.397891 RX Vref Scan: 0
3491 23:11:07.398389
3492 23:11:07.400250 RX Vref 0 -> 0, step: 1
3493 23:11:07.400914
3494 23:11:07.403552 RX Delay -40 -> 252, step: 8
3495 23:11:07.407069 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3496 23:11:07.410493 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3497 23:11:07.416760 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3498 23:11:07.420371 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3499 23:11:07.423846 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3500 23:11:07.426816 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3501 23:11:07.430105 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3502 23:11:07.436895 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3503 23:11:07.440129 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3504 23:11:07.443535 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3505 23:11:07.446810 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3506 23:11:07.449968 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3507 23:11:07.456629 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3508 23:11:07.460067 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3509 23:11:07.463589 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3510 23:11:07.467651 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3511 23:11:07.468065 ==
3512 23:11:07.470448 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 23:11:07.477025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 23:11:07.477439 ==
3515 23:11:07.477852 DQS Delay:
3516 23:11:07.478173 DQS0 = 0, DQS1 = 0
3517 23:11:07.480142 DQM Delay:
3518 23:11:07.480552 DQM0 = 121, DQM1 = 117
3519 23:11:07.483489 DQ Delay:
3520 23:11:07.486999 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3521 23:11:07.490090 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3522 23:11:07.493790 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3523 23:11:07.496741 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3524 23:11:07.497153
3525 23:11:07.497479
3526 23:11:07.497838 ==
3527 23:11:07.500516 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 23:11:07.503958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 23:11:07.504499 ==
3530 23:11:07.506897
3531 23:11:07.507308
3532 23:11:07.507632 TX Vref Scan disable
3533 23:11:07.510576 == TX Byte 0 ==
3534 23:11:07.514014 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3535 23:11:07.516598 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3536 23:11:07.520397 == TX Byte 1 ==
3537 23:11:07.523657 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3538 23:11:07.526666 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3539 23:11:07.527175 ==
3540 23:11:07.530130 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 23:11:07.536769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 23:11:07.537336 ==
3543 23:11:07.547495 TX Vref=22, minBit 1, minWin=25, winSum=419
3544 23:11:07.550986 TX Vref=24, minBit 1, minWin=26, winSum=426
3545 23:11:07.553957 TX Vref=26, minBit 2, minWin=26, winSum=431
3546 23:11:07.557112 TX Vref=28, minBit 9, minWin=26, winSum=435
3547 23:11:07.560230 TX Vref=30, minBit 9, minWin=26, winSum=435
3548 23:11:07.563987 TX Vref=32, minBit 9, minWin=26, winSum=437
3549 23:11:07.570879 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 32
3550 23:11:07.571296
3551 23:11:07.573652 Final TX Range 1 Vref 32
3552 23:11:07.574146
3553 23:11:07.574669 ==
3554 23:11:07.577234 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 23:11:07.580308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 23:11:07.580763 ==
3557 23:11:07.581275
3558 23:11:07.584164
3559 23:11:07.584708 TX Vref Scan disable
3560 23:11:07.587621 == TX Byte 0 ==
3561 23:11:07.590530 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3562 23:11:07.593918 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3563 23:11:07.597337 == TX Byte 1 ==
3564 23:11:07.600999 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3565 23:11:07.603746 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3566 23:11:07.604159
3567 23:11:07.607083 [DATLAT]
3568 23:11:07.607492 Freq=1200, CH1 RK1
3569 23:11:07.607821
3570 23:11:07.610561 DATLAT Default: 0xd
3571 23:11:07.610974 0, 0xFFFF, sum = 0
3572 23:11:07.613702 1, 0xFFFF, sum = 0
3573 23:11:07.614125 2, 0xFFFF, sum = 0
3574 23:11:07.617451 3, 0xFFFF, sum = 0
3575 23:11:07.617917 4, 0xFFFF, sum = 0
3576 23:11:07.620521 5, 0xFFFF, sum = 0
3577 23:11:07.620941 6, 0xFFFF, sum = 0
3578 23:11:07.623589 7, 0xFFFF, sum = 0
3579 23:11:07.627274 8, 0xFFFF, sum = 0
3580 23:11:07.627689 9, 0xFFFF, sum = 0
3581 23:11:07.630262 10, 0xFFFF, sum = 0
3582 23:11:07.630683 11, 0xFFFF, sum = 0
3583 23:11:07.633660 12, 0x0, sum = 1
3584 23:11:07.634084 13, 0x0, sum = 2
3585 23:11:07.636857 14, 0x0, sum = 3
3586 23:11:07.637441 15, 0x0, sum = 4
3587 23:11:07.637964 best_step = 13
3588 23:11:07.640362
3589 23:11:07.640786 ==
3590 23:11:07.643670 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 23:11:07.646968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 23:11:07.647471 ==
3593 23:11:07.647811 RX Vref Scan: 0
3594 23:11:07.648178
3595 23:11:07.650155 RX Vref 0 -> 0, step: 1
3596 23:11:07.650566
3597 23:11:07.653298 RX Delay -5 -> 252, step: 4
3598 23:11:07.657366 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3599 23:11:07.663534 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3600 23:11:07.666815 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3601 23:11:07.670287 iDelay=195, Bit 3, Center 114 (55 ~ 174) 120
3602 23:11:07.673859 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3603 23:11:07.676808 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3604 23:11:07.683751 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3605 23:11:07.686659 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3606 23:11:07.690546 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3607 23:11:07.693339 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3608 23:11:07.696421 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3609 23:11:07.703606 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3610 23:11:07.706742 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3611 23:11:07.710305 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3612 23:11:07.713728 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3613 23:11:07.716320 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3614 23:11:07.719820 ==
3615 23:11:07.723123 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 23:11:07.726405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 23:11:07.726844 ==
3618 23:11:07.727200 DQS Delay:
3619 23:11:07.730099 DQS0 = 0, DQS1 = 0
3620 23:11:07.730542 DQM Delay:
3621 23:11:07.733365 DQM0 = 119, DQM1 = 118
3622 23:11:07.733965 DQ Delay:
3623 23:11:07.736114 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =114
3624 23:11:07.739489 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3625 23:11:07.742633 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3626 23:11:07.746348 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3627 23:11:07.746917
3628 23:11:07.747455
3629 23:11:07.756244 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3630 23:11:07.759776 CH1 RK1: MR19=403, MR18=11EF
3631 23:11:07.762629 CH1_RK1: MR19=0x403, MR18=0x11EF, DQSOSC=403, MR23=63, INC=40, DEC=26
3632 23:11:07.765875 [RxdqsGatingPostProcess] freq 1200
3633 23:11:07.772983 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3634 23:11:07.775763 best DQS0 dly(2T, 0.5T) = (0, 11)
3635 23:11:07.779335 best DQS1 dly(2T, 0.5T) = (0, 11)
3636 23:11:07.782845 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3637 23:11:07.785998 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3638 23:11:07.789323 best DQS0 dly(2T, 0.5T) = (0, 11)
3639 23:11:07.792701 best DQS1 dly(2T, 0.5T) = (0, 11)
3640 23:11:07.796148 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3641 23:11:07.799813 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3642 23:11:07.802609 Pre-setting of DQS Precalculation
3643 23:11:07.806211 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3644 23:11:07.813170 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3645 23:11:07.819656 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3646 23:11:07.820203
3647 23:11:07.822533
3648 23:11:07.822988 [Calibration Summary] 2400 Mbps
3649 23:11:07.825966 CH 0, Rank 0
3650 23:11:07.826418 SW Impedance : PASS
3651 23:11:07.829640 DUTY Scan : NO K
3652 23:11:07.833277 ZQ Calibration : PASS
3653 23:11:07.833892 Jitter Meter : NO K
3654 23:11:07.836236 CBT Training : PASS
3655 23:11:07.839534 Write leveling : PASS
3656 23:11:07.839998 RX DQS gating : PASS
3657 23:11:07.843078 RX DQ/DQS(RDDQC) : PASS
3658 23:11:07.843535 TX DQ/DQS : PASS
3659 23:11:07.846067 RX DATLAT : PASS
3660 23:11:07.849130 RX DQ/DQS(Engine): PASS
3661 23:11:07.849600 TX OE : NO K
3662 23:11:07.852590 All Pass.
3663 23:11:07.853192
3664 23:11:07.853541 CH 0, Rank 1
3665 23:11:07.856418 SW Impedance : PASS
3666 23:11:07.856834 DUTY Scan : NO K
3667 23:11:07.859505 ZQ Calibration : PASS
3668 23:11:07.862840 Jitter Meter : NO K
3669 23:11:07.863406 CBT Training : PASS
3670 23:11:07.865896 Write leveling : PASS
3671 23:11:07.869055 RX DQS gating : PASS
3672 23:11:07.869473 RX DQ/DQS(RDDQC) : PASS
3673 23:11:07.872573 TX DQ/DQS : PASS
3674 23:11:07.876428 RX DATLAT : PASS
3675 23:11:07.876839 RX DQ/DQS(Engine): PASS
3676 23:11:07.880150 TX OE : NO K
3677 23:11:07.880683 All Pass.
3678 23:11:07.881083
3679 23:11:07.882951 CH 1, Rank 0
3680 23:11:07.883405 SW Impedance : PASS
3681 23:11:07.885975 DUTY Scan : NO K
3682 23:11:07.889104 ZQ Calibration : PASS
3683 23:11:07.889512 Jitter Meter : NO K
3684 23:11:07.892758 CBT Training : PASS
3685 23:11:07.895875 Write leveling : PASS
3686 23:11:07.896287 RX DQS gating : PASS
3687 23:11:07.899571 RX DQ/DQS(RDDQC) : PASS
3688 23:11:07.900015 TX DQ/DQS : PASS
3689 23:11:07.903232 RX DATLAT : PASS
3690 23:11:07.905828 RX DQ/DQS(Engine): PASS
3691 23:11:07.906270 TX OE : NO K
3692 23:11:07.909294 All Pass.
3693 23:11:07.909862
3694 23:11:07.910374 CH 1, Rank 1
3695 23:11:07.912425 SW Impedance : PASS
3696 23:11:07.913003 DUTY Scan : NO K
3697 23:11:07.916256 ZQ Calibration : PASS
3698 23:11:07.919016 Jitter Meter : NO K
3699 23:11:07.919429 CBT Training : PASS
3700 23:11:07.922604 Write leveling : PASS
3701 23:11:07.925800 RX DQS gating : PASS
3702 23:11:07.926210 RX DQ/DQS(RDDQC) : PASS
3703 23:11:07.928904 TX DQ/DQS : PASS
3704 23:11:07.932520 RX DATLAT : PASS
3705 23:11:07.932930 RX DQ/DQS(Engine): PASS
3706 23:11:07.939455 TX OE : NO K
3707 23:11:07.940091 All Pass.
3708 23:11:07.940444
3709 23:11:07.940766 DramC Write-DBI off
3710 23:11:07.942295 PER_BANK_REFRESH: Hybrid Mode
3711 23:11:07.942705 TX_TRACKING: ON
3712 23:11:07.952420 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3713 23:11:07.955780 [FAST_K] Save calibration result to emmc
3714 23:11:07.959055 dramc_set_vcore_voltage set vcore to 650000
3715 23:11:07.962336 Read voltage for 600, 5
3716 23:11:07.962747 Vio18 = 0
3717 23:11:07.963071 Vcore = 650000
3718 23:11:07.966137 Vdram = 0
3719 23:11:07.966561 Vddq = 0
3720 23:11:07.966888 Vmddr = 0
3721 23:11:07.972223 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3722 23:11:07.975777 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3723 23:11:07.978849 MEM_TYPE=3, freq_sel=19
3724 23:11:07.982323 sv_algorithm_assistance_LP4_1600
3725 23:11:07.985631 ============ PULL DRAM RESETB DOWN ============
3726 23:11:07.988956 ========== PULL DRAM RESETB DOWN end =========
3727 23:11:07.996142 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3728 23:11:07.998835 ===================================
3729 23:11:07.999255 LPDDR4 DRAM CONFIGURATION
3730 23:11:08.002529 ===================================
3731 23:11:08.005849 EX_ROW_EN[0] = 0x0
3732 23:11:08.009191 EX_ROW_EN[1] = 0x0
3733 23:11:08.009821 LP4Y_EN = 0x0
3734 23:11:08.012340 WORK_FSP = 0x0
3735 23:11:08.012755 WL = 0x2
3736 23:11:08.015506 RL = 0x2
3737 23:11:08.015921 BL = 0x2
3738 23:11:08.019036 RPST = 0x0
3739 23:11:08.019447 RD_PRE = 0x0
3740 23:11:08.022556 WR_PRE = 0x1
3741 23:11:08.022974 WR_PST = 0x0
3742 23:11:08.026026 DBI_WR = 0x0
3743 23:11:08.026443 DBI_RD = 0x0
3744 23:11:08.028871 OTF = 0x1
3745 23:11:08.032345 ===================================
3746 23:11:08.035643 ===================================
3747 23:11:08.036055 ANA top config
3748 23:11:08.039339 ===================================
3749 23:11:08.042422 DLL_ASYNC_EN = 0
3750 23:11:08.045595 ALL_SLAVE_EN = 1
3751 23:11:08.046007 NEW_RANK_MODE = 1
3752 23:11:08.049087 DLL_IDLE_MODE = 1
3753 23:11:08.052129 LP45_APHY_COMB_EN = 1
3754 23:11:08.055334 TX_ODT_DIS = 1
3755 23:11:08.058802 NEW_8X_MODE = 1
3756 23:11:08.061955 ===================================
3757 23:11:08.065533 ===================================
3758 23:11:08.066039 data_rate = 1200
3759 23:11:08.068798 CKR = 1
3760 23:11:08.072374 DQ_P2S_RATIO = 8
3761 23:11:08.075658 ===================================
3762 23:11:08.078661 CA_P2S_RATIO = 8
3763 23:11:08.082721 DQ_CA_OPEN = 0
3764 23:11:08.085344 DQ_SEMI_OPEN = 0
3765 23:11:08.085841 CA_SEMI_OPEN = 0
3766 23:11:08.088421 CA_FULL_RATE = 0
3767 23:11:08.092198 DQ_CKDIV4_EN = 1
3768 23:11:08.095393 CA_CKDIV4_EN = 1
3769 23:11:08.098602 CA_PREDIV_EN = 0
3770 23:11:08.102153 PH8_DLY = 0
3771 23:11:08.102764 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3772 23:11:08.105183 DQ_AAMCK_DIV = 4
3773 23:11:08.108727 CA_AAMCK_DIV = 4
3774 23:11:08.112106 CA_ADMCK_DIV = 4
3775 23:11:08.115407 DQ_TRACK_CA_EN = 0
3776 23:11:08.118512 CA_PICK = 600
3777 23:11:08.121699 CA_MCKIO = 600
3778 23:11:08.122308 MCKIO_SEMI = 0
3779 23:11:08.125056 PLL_FREQ = 2288
3780 23:11:08.128979 DQ_UI_PI_RATIO = 32
3781 23:11:08.131939 CA_UI_PI_RATIO = 0
3782 23:11:08.135646 ===================================
3783 23:11:08.138493 ===================================
3784 23:11:08.141982 memory_type:LPDDR4
3785 23:11:08.142393 GP_NUM : 10
3786 23:11:08.145340 SRAM_EN : 1
3787 23:11:08.145800 MD32_EN : 0
3788 23:11:08.148912 ===================================
3789 23:11:08.151939 [ANA_INIT] >>>>>>>>>>>>>>
3790 23:11:08.155449 <<<<<< [CONFIGURE PHASE]: ANA_TX
3791 23:11:08.158592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3792 23:11:08.162028 ===================================
3793 23:11:08.165036 data_rate = 1200,PCW = 0X5800
3794 23:11:08.168608 ===================================
3795 23:11:08.172236 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3796 23:11:08.178929 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 23:11:08.182168 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3798 23:11:08.188665 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3799 23:11:08.192044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3800 23:11:08.195017 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3801 23:11:08.195498 [ANA_INIT] flow start
3802 23:11:08.198458 [ANA_INIT] PLL >>>>>>>>
3803 23:11:08.201930 [ANA_INIT] PLL <<<<<<<<
3804 23:11:08.202346 [ANA_INIT] MIDPI >>>>>>>>
3805 23:11:08.204864 [ANA_INIT] MIDPI <<<<<<<<
3806 23:11:08.208536 [ANA_INIT] DLL >>>>>>>>
3807 23:11:08.208944 [ANA_INIT] flow end
3808 23:11:08.215743 ============ LP4 DIFF to SE enter ============
3809 23:11:08.218560 ============ LP4 DIFF to SE exit ============
3810 23:11:08.221303 [ANA_INIT] <<<<<<<<<<<<<
3811 23:11:08.224994 [Flow] Enable top DCM control >>>>>
3812 23:11:08.227976 [Flow] Enable top DCM control <<<<<
3813 23:11:08.228482 Enable DLL master slave shuffle
3814 23:11:08.234395 ==============================================================
3815 23:11:08.237856 Gating Mode config
3816 23:11:08.240846 ==============================================================
3817 23:11:08.244185 Config description:
3818 23:11:08.254443 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3819 23:11:08.261413 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3820 23:11:08.264504 SELPH_MODE 0: By rank 1: By Phase
3821 23:11:08.271234 ==============================================================
3822 23:11:08.274486 GAT_TRACK_EN = 1
3823 23:11:08.277712 RX_GATING_MODE = 2
3824 23:11:08.280937 RX_GATING_TRACK_MODE = 2
3825 23:11:08.284482 SELPH_MODE = 1
3826 23:11:08.285054 PICG_EARLY_EN = 1
3827 23:11:08.287664 VALID_LAT_VALUE = 1
3828 23:11:08.294486 ==============================================================
3829 23:11:08.297953 Enter into Gating configuration >>>>
3830 23:11:08.300890 Exit from Gating configuration <<<<
3831 23:11:08.304664 Enter into DVFS_PRE_config >>>>>
3832 23:11:08.314490 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3833 23:11:08.317768 Exit from DVFS_PRE_config <<<<<
3834 23:11:08.321050 Enter into PICG configuration >>>>
3835 23:11:08.324516 Exit from PICG configuration <<<<
3836 23:11:08.327738 [RX_INPUT] configuration >>>>>
3837 23:11:08.331252 [RX_INPUT] configuration <<<<<
3838 23:11:08.334779 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3839 23:11:08.340952 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3840 23:11:08.347363 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3841 23:11:08.353923 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3842 23:11:08.360734 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 23:11:08.363920 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 23:11:08.370575 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3845 23:11:08.374416 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3846 23:11:08.377541 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3847 23:11:08.380510 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3848 23:11:08.387577 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3849 23:11:08.390522 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3850 23:11:08.394244 ===================================
3851 23:11:08.397426 LPDDR4 DRAM CONFIGURATION
3852 23:11:08.400650 ===================================
3853 23:11:08.401072 EX_ROW_EN[0] = 0x0
3854 23:11:08.403674 EX_ROW_EN[1] = 0x0
3855 23:11:08.404093 LP4Y_EN = 0x0
3856 23:11:08.407130 WORK_FSP = 0x0
3857 23:11:08.407547 WL = 0x2
3858 23:11:08.410562 RL = 0x2
3859 23:11:08.410980 BL = 0x2
3860 23:11:08.413982 RPST = 0x0
3861 23:11:08.416918 RD_PRE = 0x0
3862 23:11:08.417334 WR_PRE = 0x1
3863 23:11:08.420258 WR_PST = 0x0
3864 23:11:08.420676 DBI_WR = 0x0
3865 23:11:08.423814 DBI_RD = 0x0
3866 23:11:08.424235 OTF = 0x1
3867 23:11:08.427091 ===================================
3868 23:11:08.430492 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3869 23:11:08.437132 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3870 23:11:08.440337 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3871 23:11:08.443664 ===================================
3872 23:11:08.447164 LPDDR4 DRAM CONFIGURATION
3873 23:11:08.450175 ===================================
3874 23:11:08.450596 EX_ROW_EN[0] = 0x10
3875 23:11:08.453341 EX_ROW_EN[1] = 0x0
3876 23:11:08.453667 LP4Y_EN = 0x0
3877 23:11:08.457003 WORK_FSP = 0x0
3878 23:11:08.457229 WL = 0x2
3879 23:11:08.460288 RL = 0x2
3880 23:11:08.460515 BL = 0x2
3881 23:11:08.463266 RPST = 0x0
3882 23:11:08.463491 RD_PRE = 0x0
3883 23:11:08.466360 WR_PRE = 0x1
3884 23:11:08.466604 WR_PST = 0x0
3885 23:11:08.469670 DBI_WR = 0x0
3886 23:11:08.473686 DBI_RD = 0x0
3887 23:11:08.473913 OTF = 0x1
3888 23:11:08.476945 ===================================
3889 23:11:08.483419 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3890 23:11:08.486606 nWR fixed to 30
3891 23:11:08.490270 [ModeRegInit_LP4] CH0 RK0
3892 23:11:08.490494 [ModeRegInit_LP4] CH0 RK1
3893 23:11:08.493524 [ModeRegInit_LP4] CH1 RK0
3894 23:11:08.497219 [ModeRegInit_LP4] CH1 RK1
3895 23:11:08.497712 match AC timing 17
3896 23:11:08.503866 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3897 23:11:08.507074 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3898 23:11:08.510763 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3899 23:11:08.517236 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3900 23:11:08.520627 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3901 23:11:08.521182 ==
3902 23:11:08.524320 Dram Type= 6, Freq= 0, CH_0, rank 0
3903 23:11:08.527192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3904 23:11:08.527760 ==
3905 23:11:08.533767 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3906 23:11:08.540081 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3907 23:11:08.543632 [CA 0] Center 36 (5~67) winsize 63
3908 23:11:08.546954 [CA 1] Center 36 (5~67) winsize 63
3909 23:11:08.549868 [CA 2] Center 34 (3~65) winsize 63
3910 23:11:08.553386 [CA 3] Center 33 (3~64) winsize 62
3911 23:11:08.556882 [CA 4] Center 33 (2~64) winsize 63
3912 23:11:08.559886 [CA 5] Center 32 (2~63) winsize 62
3913 23:11:08.560310
3914 23:11:08.563605 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3915 23:11:08.564120
3916 23:11:08.566502 [CATrainingPosCal] consider 1 rank data
3917 23:11:08.570463 u2DelayCellTimex100 = 270/100 ps
3918 23:11:08.573102 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3919 23:11:08.576396 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3920 23:11:08.579775 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3921 23:11:08.583116 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3922 23:11:08.586361 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3923 23:11:08.593105 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3924 23:11:08.593527
3925 23:11:08.596523 CA PerBit enable=1, Macro0, CA PI delay=32
3926 23:11:08.597128
3927 23:11:08.599694 [CBTSetCACLKResult] CA Dly = 32
3928 23:11:08.600312 CS Dly: 4 (0~35)
3929 23:11:08.600822 ==
3930 23:11:08.603148 Dram Type= 6, Freq= 0, CH_0, rank 1
3931 23:11:08.606499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3932 23:11:08.609546 ==
3933 23:11:08.612718 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3934 23:11:08.619326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3935 23:11:08.623305 [CA 0] Center 35 (5~66) winsize 62
3936 23:11:08.625906 [CA 1] Center 35 (5~66) winsize 62
3937 23:11:08.629398 [CA 2] Center 34 (3~65) winsize 63
3938 23:11:08.632985 [CA 3] Center 34 (3~65) winsize 63
3939 23:11:08.636572 [CA 4] Center 33 (2~64) winsize 63
3940 23:11:08.639171 [CA 5] Center 32 (2~63) winsize 62
3941 23:11:08.639771
3942 23:11:08.642799 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3943 23:11:08.643301
3944 23:11:08.646095 [CATrainingPosCal] consider 2 rank data
3945 23:11:08.649114 u2DelayCellTimex100 = 270/100 ps
3946 23:11:08.652610 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3947 23:11:08.656224 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3948 23:11:08.659864 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3949 23:11:08.666307 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3950 23:11:08.669894 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3951 23:11:08.673094 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3952 23:11:08.673642
3953 23:11:08.676374 CA PerBit enable=1, Macro0, CA PI delay=32
3954 23:11:08.676885
3955 23:11:08.679325 [CBTSetCACLKResult] CA Dly = 32
3956 23:11:08.679757 CS Dly: 4 (0~36)
3957 23:11:08.680091
3958 23:11:08.682692 ----->DramcWriteLeveling(PI) begin...
3959 23:11:08.683162 ==
3960 23:11:08.685999 Dram Type= 6, Freq= 0, CH_0, rank 0
3961 23:11:08.693073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3962 23:11:08.693674 ==
3963 23:11:08.696304 Write leveling (Byte 0): 34 => 34
3964 23:11:08.699424 Write leveling (Byte 1): 30 => 30
3965 23:11:08.702350 DramcWriteLeveling(PI) end<-----
3966 23:11:08.702772
3967 23:11:08.703104 ==
3968 23:11:08.705955 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 23:11:08.709256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 23:11:08.709753 ==
3971 23:11:08.712690 [Gating] SW mode calibration
3972 23:11:08.718992 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3973 23:11:08.722297 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3974 23:11:08.729175 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 23:11:08.732396 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 23:11:08.735590 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 23:11:08.742016 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
3978 23:11:08.745445 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
3979 23:11:08.748938 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 23:11:08.755514 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 23:11:08.759431 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 23:11:08.762214 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 23:11:08.769055 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 23:11:08.772139 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 23:11:08.775526 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
3986 23:11:08.781821 0 10 16 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
3987 23:11:08.785102 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 23:11:08.788422 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 23:11:08.795310 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 23:11:08.798161 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 23:11:08.802023 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 23:11:08.808007 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 23:11:08.811380 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3994 23:11:08.814843 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3995 23:11:08.821908 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 23:11:08.825369 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 23:11:08.828393 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 23:11:08.835185 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 23:11:08.838411 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 23:11:08.841389 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 23:11:08.848669 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 23:11:08.851875 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 23:11:08.855759 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 23:11:08.861490 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 23:11:08.865196 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 23:11:08.868273 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 23:11:08.872200 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 23:11:08.878088 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 23:11:08.881852 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4010 23:11:08.884506 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 23:11:08.888548 Total UI for P1: 0, mck2ui 16
4012 23:11:08.891792 best dqsien dly found for B0: ( 0, 13, 12)
4013 23:11:08.895166 Total UI for P1: 0, mck2ui 16
4014 23:11:08.898276 best dqsien dly found for B1: ( 0, 13, 12)
4015 23:11:08.901905 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4016 23:11:08.908478 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4017 23:11:08.909034
4018 23:11:08.911699 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4019 23:11:08.914797 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4020 23:11:08.917758 [Gating] SW calibration Done
4021 23:11:08.918384 ==
4022 23:11:08.921101 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 23:11:08.924692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 23:11:08.925147 ==
4025 23:11:08.927672 RX Vref Scan: 0
4026 23:11:08.928091
4027 23:11:08.928427 RX Vref 0 -> 0, step: 1
4028 23:11:08.928737
4029 23:11:08.930905 RX Delay -230 -> 252, step: 16
4030 23:11:08.934393 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4031 23:11:08.941639 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4032 23:11:08.944517 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4033 23:11:08.948039 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4034 23:11:08.950988 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4035 23:11:08.955084 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4036 23:11:08.961344 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4037 23:11:08.964359 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4038 23:11:08.967559 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4039 23:11:08.971699 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4040 23:11:08.977977 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4041 23:11:08.980976 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4042 23:11:08.984444 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4043 23:11:08.987445 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4044 23:11:08.994932 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4045 23:11:08.998140 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4046 23:11:08.998558 ==
4047 23:11:09.000794 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 23:11:09.004272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 23:11:09.004692 ==
4050 23:11:09.008006 DQS Delay:
4051 23:11:09.008422 DQS0 = 0, DQS1 = 0
4052 23:11:09.008752 DQM Delay:
4053 23:11:09.011141 DQM0 = 49, DQM1 = 45
4054 23:11:09.011659 DQ Delay:
4055 23:11:09.014802 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4056 23:11:09.017691 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4057 23:11:09.020973 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4058 23:11:09.024729 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4059 23:11:09.025252
4060 23:11:09.025616
4061 23:11:09.025966 ==
4062 23:11:09.027817 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 23:11:09.034897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 23:11:09.035427 ==
4065 23:11:09.035764
4066 23:11:09.036075
4067 23:11:09.036375 TX Vref Scan disable
4068 23:11:09.037796 == TX Byte 0 ==
4069 23:11:09.041109 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4070 23:11:09.047414 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4071 23:11:09.048129 == TX Byte 1 ==
4072 23:11:09.050711 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4073 23:11:09.057529 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4074 23:11:09.058019 ==
4075 23:11:09.060839 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 23:11:09.064310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 23:11:09.064738 ==
4078 23:11:09.065066
4079 23:11:09.065373
4080 23:11:09.067927 TX Vref Scan disable
4081 23:11:09.070661 == TX Byte 0 ==
4082 23:11:09.074342 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4083 23:11:09.077687 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4084 23:11:09.080465 == TX Byte 1 ==
4085 23:11:09.084056 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4086 23:11:09.087701 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4087 23:11:09.088121
4088 23:11:09.088452 [DATLAT]
4089 23:11:09.090601 Freq=600, CH0 RK0
4090 23:11:09.091017
4091 23:11:09.094490 DATLAT Default: 0x9
4092 23:11:09.095016 0, 0xFFFF, sum = 0
4093 23:11:09.097400 1, 0xFFFF, sum = 0
4094 23:11:09.097863 2, 0xFFFF, sum = 0
4095 23:11:09.100893 3, 0xFFFF, sum = 0
4096 23:11:09.101320 4, 0xFFFF, sum = 0
4097 23:11:09.104094 5, 0xFFFF, sum = 0
4098 23:11:09.104521 6, 0xFFFF, sum = 0
4099 23:11:09.107438 7, 0xFFFF, sum = 0
4100 23:11:09.107966 8, 0x0, sum = 1
4101 23:11:09.110498 9, 0x0, sum = 2
4102 23:11:09.110934 10, 0x0, sum = 3
4103 23:11:09.111278 11, 0x0, sum = 4
4104 23:11:09.114071 best_step = 9
4105 23:11:09.114489
4106 23:11:09.114823 ==
4107 23:11:09.117755 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 23:11:09.120699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 23:11:09.121121 ==
4110 23:11:09.124075 RX Vref Scan: 1
4111 23:11:09.124596
4112 23:11:09.125116 RX Vref 0 -> 0, step: 1
4113 23:11:09.125689
4114 23:11:09.127253 RX Delay -163 -> 252, step: 8
4115 23:11:09.127745
4116 23:11:09.130698 Set Vref, RX VrefLevel [Byte0]: 54
4117 23:11:09.134043 [Byte1]: 55
4118 23:11:09.138249
4119 23:11:09.138848 Final RX Vref Byte 0 = 54 to rank0
4120 23:11:09.141547 Final RX Vref Byte 1 = 55 to rank0
4121 23:11:09.144988 Final RX Vref Byte 0 = 54 to rank1
4122 23:11:09.148361 Final RX Vref Byte 1 = 55 to rank1==
4123 23:11:09.151452 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 23:11:09.158028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 23:11:09.158598 ==
4126 23:11:09.159141 DQS Delay:
4127 23:11:09.159650 DQS0 = 0, DQS1 = 0
4128 23:11:09.161050 DQM Delay:
4129 23:11:09.161620 DQM0 = 52, DQM1 = 47
4130 23:11:09.164431 DQ Delay:
4131 23:11:09.167769 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4132 23:11:09.171325 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4133 23:11:09.174209 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =44
4134 23:11:09.177719 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4135 23:11:09.178155
4136 23:11:09.178594
4137 23:11:09.184825 [DQSOSCAuto] RK0, (LSB)MR18= 0x6b5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
4138 23:11:09.188130 CH0 RK0: MR19=808, MR18=6B5E
4139 23:11:09.194431 CH0_RK0: MR19=0x808, MR18=0x6B5E, DQSOSC=389, MR23=63, INC=173, DEC=115
4140 23:11:09.194869
4141 23:11:09.198237 ----->DramcWriteLeveling(PI) begin...
4142 23:11:09.198673 ==
4143 23:11:09.201318 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 23:11:09.204513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 23:11:09.204945 ==
4146 23:11:09.207676 Write leveling (Byte 0): 35 => 35
4147 23:11:09.210988 Write leveling (Byte 1): 31 => 31
4148 23:11:09.214256 DramcWriteLeveling(PI) end<-----
4149 23:11:09.214686
4150 23:11:09.215125 ==
4151 23:11:09.217913 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 23:11:09.221004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 23:11:09.221439 ==
4154 23:11:09.225148 [Gating] SW mode calibration
4155 23:11:09.230904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4156 23:11:09.237628 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4157 23:11:09.241127 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 23:11:09.247651 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 23:11:09.251101 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 23:11:09.253976 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
4161 23:11:09.257397 0 9 16 | B1->B0 | 2d2d 2a2a | 0 0 | (1 1) (0 0)
4162 23:11:09.265053 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 23:11:09.268129 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 23:11:09.271138 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 23:11:09.277375 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 23:11:09.280712 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 23:11:09.284504 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 23:11:09.290874 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4169 23:11:09.294593 0 10 16 | B1->B0 | 3c3c 4141 | 0 0 | (0 0) (0 0)
4170 23:11:09.297350 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 23:11:09.303744 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 23:11:09.307337 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 23:11:09.310594 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 23:11:09.317008 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 23:11:09.320385 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 23:11:09.324200 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4177 23:11:09.330272 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4178 23:11:09.333479 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 23:11:09.337207 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 23:11:09.343623 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 23:11:09.347014 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 23:11:09.350669 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 23:11:09.357057 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 23:11:09.360090 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 23:11:09.363787 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 23:11:09.370771 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 23:11:09.374201 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 23:11:09.376783 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 23:11:09.383958 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 23:11:09.386711 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 23:11:09.390283 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 23:11:09.397010 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4193 23:11:09.400418 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 23:11:09.403710 Total UI for P1: 0, mck2ui 16
4195 23:11:09.407336 best dqsien dly found for B0: ( 0, 13, 12)
4196 23:11:09.410059 Total UI for P1: 0, mck2ui 16
4197 23:11:09.413559 best dqsien dly found for B1: ( 0, 13, 12)
4198 23:11:09.417209 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4199 23:11:09.420148 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4200 23:11:09.420564
4201 23:11:09.423887 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4202 23:11:09.427103 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4203 23:11:09.430467 [Gating] SW calibration Done
4204 23:11:09.430921 ==
4205 23:11:09.433219 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 23:11:09.436635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 23:11:09.437094 ==
4208 23:11:09.440111 RX Vref Scan: 0
4209 23:11:09.440522
4210 23:11:09.443581 RX Vref 0 -> 0, step: 1
4211 23:11:09.444078
4212 23:11:09.444571 RX Delay -230 -> 252, step: 16
4213 23:11:09.450335 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4214 23:11:09.453803 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4215 23:11:09.456638 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4216 23:11:09.460423 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4217 23:11:09.466693 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4218 23:11:09.470053 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4219 23:11:09.473455 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4220 23:11:09.476637 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4221 23:11:09.480000 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4222 23:11:09.486497 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4223 23:11:09.489852 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4224 23:11:09.493159 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4225 23:11:09.496642 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4226 23:11:09.503416 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4227 23:11:09.506723 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4228 23:11:09.510280 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4229 23:11:09.511093 ==
4230 23:11:09.513882 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 23:11:09.516783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 23:11:09.520251 ==
4233 23:11:09.520663 DQS Delay:
4234 23:11:09.520988 DQS0 = 0, DQS1 = 0
4235 23:11:09.523408 DQM Delay:
4236 23:11:09.523917 DQM0 = 51, DQM1 = 44
4237 23:11:09.526846 DQ Delay:
4238 23:11:09.530525 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4239 23:11:09.531039 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4240 23:11:09.533088 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4241 23:11:09.540026 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4242 23:11:09.540518
4243 23:11:09.540864
4244 23:11:09.541171 ==
4245 23:11:09.542862 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 23:11:09.546497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 23:11:09.546956 ==
4248 23:11:09.547286
4249 23:11:09.547590
4250 23:11:09.550195 TX Vref Scan disable
4251 23:11:09.550604 == TX Byte 0 ==
4252 23:11:09.556105 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4253 23:11:09.559787 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4254 23:11:09.560221 == TX Byte 1 ==
4255 23:11:09.566254 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4256 23:11:09.569481 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4257 23:11:09.569960 ==
4258 23:11:09.572723 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 23:11:09.575932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 23:11:09.576434 ==
4261 23:11:09.576771
4262 23:11:09.579097
4263 23:11:09.579514 TX Vref Scan disable
4264 23:11:09.582673 == TX Byte 0 ==
4265 23:11:09.586420 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4266 23:11:09.592920 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4267 23:11:09.593433 == TX Byte 1 ==
4268 23:11:09.596142 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4269 23:11:09.602931 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4270 23:11:09.603426
4271 23:11:09.603760 [DATLAT]
4272 23:11:09.604074 Freq=600, CH0 RK1
4273 23:11:09.604383
4274 23:11:09.605890 DATLAT Default: 0x9
4275 23:11:09.606332 0, 0xFFFF, sum = 0
4276 23:11:09.609549 1, 0xFFFF, sum = 0
4277 23:11:09.610058 2, 0xFFFF, sum = 0
4278 23:11:09.613081 3, 0xFFFF, sum = 0
4279 23:11:09.613507 4, 0xFFFF, sum = 0
4280 23:11:09.616656 5, 0xFFFF, sum = 0
4281 23:11:09.619453 6, 0xFFFF, sum = 0
4282 23:11:09.619878 7, 0xFFFF, sum = 0
4283 23:11:09.620217 8, 0x0, sum = 1
4284 23:11:09.622830 9, 0x0, sum = 2
4285 23:11:09.623252 10, 0x0, sum = 3
4286 23:11:09.625929 11, 0x0, sum = 4
4287 23:11:09.626499 best_step = 9
4288 23:11:09.626837
4289 23:11:09.627150 ==
4290 23:11:09.629270 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 23:11:09.636261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 23:11:09.636679 ==
4293 23:11:09.637009 RX Vref Scan: 0
4294 23:11:09.637313
4295 23:11:09.639218 RX Vref 0 -> 0, step: 1
4296 23:11:09.639630
4297 23:11:09.642881 RX Delay -163 -> 252, step: 8
4298 23:11:09.646548 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4299 23:11:09.652428 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4300 23:11:09.655886 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4301 23:11:09.659155 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4302 23:11:09.662123 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4303 23:11:09.665991 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4304 23:11:09.672267 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4305 23:11:09.676068 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4306 23:11:09.679227 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4307 23:11:09.682089 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4308 23:11:09.685569 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4309 23:11:09.692997 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4310 23:11:09.695898 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4311 23:11:09.699237 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4312 23:11:09.702047 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4313 23:11:09.705804 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4314 23:11:09.709445 ==
4315 23:11:09.712312 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 23:11:09.715440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 23:11:09.715822 ==
4318 23:11:09.716121 DQS Delay:
4319 23:11:09.718906 DQS0 = 0, DQS1 = 0
4320 23:11:09.719359 DQM Delay:
4321 23:11:09.722602 DQM0 = 53, DQM1 = 46
4322 23:11:09.723011 DQ Delay:
4323 23:11:09.725617 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4324 23:11:09.728723 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4325 23:11:09.731976 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4326 23:11:09.736205 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4327 23:11:09.736632
4328 23:11:09.736957
4329 23:11:09.742038 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f1f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
4330 23:11:09.745572 CH0 RK1: MR19=808, MR18=5F1F
4331 23:11:09.751827 CH0_RK1: MR19=0x808, MR18=0x5F1F, DQSOSC=391, MR23=63, INC=171, DEC=114
4332 23:11:09.755047 [RxdqsGatingPostProcess] freq 600
4333 23:11:09.761791 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4334 23:11:09.765390 Pre-setting of DQS Precalculation
4335 23:11:09.768887 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4336 23:11:09.769112 ==
4337 23:11:09.771615 Dram Type= 6, Freq= 0, CH_1, rank 0
4338 23:11:09.775181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 23:11:09.775361 ==
4340 23:11:09.781276 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4341 23:11:09.788068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4342 23:11:09.791162 [CA 0] Center 35 (5~66) winsize 62
4343 23:11:09.794945 [CA 1] Center 35 (5~66) winsize 62
4344 23:11:09.797925 [CA 2] Center 34 (4~65) winsize 62
4345 23:11:09.801098 [CA 3] Center 34 (4~65) winsize 62
4346 23:11:09.804654 [CA 4] Center 34 (4~65) winsize 62
4347 23:11:09.808022 [CA 5] Center 33 (3~64) winsize 62
4348 23:11:09.808132
4349 23:11:09.811216 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4350 23:11:09.811332
4351 23:11:09.814598 [CATrainingPosCal] consider 1 rank data
4352 23:11:09.817939 u2DelayCellTimex100 = 270/100 ps
4353 23:11:09.821232 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4354 23:11:09.824535 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4355 23:11:09.828170 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4356 23:11:09.831167 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4357 23:11:09.834759 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4358 23:11:09.841475 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4359 23:11:09.841597
4360 23:11:09.844272 CA PerBit enable=1, Macro0, CA PI delay=33
4361 23:11:09.844382
4362 23:11:09.847517 [CBTSetCACLKResult] CA Dly = 33
4363 23:11:09.847627 CS Dly: 5 (0~36)
4364 23:11:09.847714 ==
4365 23:11:09.851294 Dram Type= 6, Freq= 0, CH_1, rank 1
4366 23:11:09.854433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 23:11:09.857404 ==
4368 23:11:09.861416 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 23:11:09.867809 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4370 23:11:09.871343 [CA 0] Center 36 (5~67) winsize 63
4371 23:11:09.874651 [CA 1] Center 36 (5~67) winsize 63
4372 23:11:09.877966 [CA 2] Center 34 (4~65) winsize 62
4373 23:11:09.881627 [CA 3] Center 34 (4~65) winsize 62
4374 23:11:09.884646 [CA 4] Center 34 (4~65) winsize 62
4375 23:11:09.887602 [CA 5] Center 34 (3~65) winsize 63
4376 23:11:09.887936
4377 23:11:09.891275 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4378 23:11:09.891685
4379 23:11:09.894734 [CATrainingPosCal] consider 2 rank data
4380 23:11:09.897879 u2DelayCellTimex100 = 270/100 ps
4381 23:11:09.901036 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4382 23:11:09.904626 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4383 23:11:09.907650 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4384 23:11:09.914751 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4385 23:11:09.917521 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 23:11:09.921024 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4387 23:11:09.921438
4388 23:11:09.924571 CA PerBit enable=1, Macro0, CA PI delay=33
4389 23:11:09.925087
4390 23:11:09.927845 [CBTSetCACLKResult] CA Dly = 33
4391 23:11:09.928261 CS Dly: 6 (0~38)
4392 23:11:09.928591
4393 23:11:09.931391 ----->DramcWriteLeveling(PI) begin...
4394 23:11:09.931984 ==
4395 23:11:09.934145 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 23:11:09.940964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 23:11:09.941481 ==
4398 23:11:09.944405 Write leveling (Byte 0): 30 => 30
4399 23:11:09.947462 Write leveling (Byte 1): 31 => 31
4400 23:11:09.947895 DramcWriteLeveling(PI) end<-----
4401 23:11:09.948344
4402 23:11:09.951566 ==
4403 23:11:09.954121 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 23:11:09.957572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 23:11:09.958045 ==
4406 23:11:09.960862 [Gating] SW mode calibration
4407 23:11:09.967365 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4408 23:11:09.970836 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4409 23:11:09.977488 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 23:11:09.980627 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 23:11:09.984351 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4412 23:11:09.990852 0 9 12 | B1->B0 | 3030 2d2d | 1 1 | (0 1) (1 0)
4413 23:11:09.994467 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 23:11:09.997686 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 23:11:10.004531 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 23:11:10.007434 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 23:11:10.010586 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 23:11:10.017538 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 23:11:10.020999 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 23:11:10.024030 0 10 12 | B1->B0 | 3535 3b3b | 0 0 | (0 0) (0 0)
4421 23:11:10.030861 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 23:11:10.033775 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 23:11:10.037243 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 23:11:10.043935 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 23:11:10.046993 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 23:11:10.050919 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 23:11:10.054400 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 23:11:10.060649 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 23:11:10.064042 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 23:11:10.067141 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 23:11:10.073937 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 23:11:10.076988 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 23:11:10.080285 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 23:11:10.087038 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 23:11:10.090621 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 23:11:10.093695 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 23:11:10.100779 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 23:11:10.103895 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 23:11:10.106953 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 23:11:10.113960 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 23:11:10.116878 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 23:11:10.120153 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 23:11:10.127378 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 23:11:10.130816 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4445 23:11:10.134050 Total UI for P1: 0, mck2ui 16
4446 23:11:10.136922 best dqsien dly found for B0: ( 0, 13, 10)
4447 23:11:10.140654 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4448 23:11:10.147482 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 23:11:10.147905 Total UI for P1: 0, mck2ui 16
4450 23:11:10.150221 best dqsien dly found for B1: ( 0, 13, 14)
4451 23:11:10.156754 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4452 23:11:10.160051 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4453 23:11:10.160461
4454 23:11:10.163578 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4455 23:11:10.166970 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4456 23:11:10.169898 [Gating] SW calibration Done
4457 23:11:10.170631 ==
4458 23:11:10.173681 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 23:11:10.176624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 23:11:10.177059 ==
4461 23:11:10.179777 RX Vref Scan: 0
4462 23:11:10.180181
4463 23:11:10.180579 RX Vref 0 -> 0, step: 1
4464 23:11:10.180932
4465 23:11:10.183550 RX Delay -230 -> 252, step: 16
4466 23:11:10.189955 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4467 23:11:10.193232 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4468 23:11:10.196620 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4469 23:11:10.199782 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4470 23:11:10.203184 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4471 23:11:10.209828 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4472 23:11:10.212891 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4473 23:11:10.216365 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4474 23:11:10.219940 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4475 23:11:10.226286 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4476 23:11:10.229464 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4477 23:11:10.232673 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4478 23:11:10.235959 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4479 23:11:10.242711 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4480 23:11:10.246174 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4481 23:11:10.249758 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4482 23:11:10.249940 ==
4483 23:11:10.252655 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 23:11:10.256326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 23:11:10.256503 ==
4486 23:11:10.259726 DQS Delay:
4487 23:11:10.259901 DQS0 = 0, DQS1 = 0
4488 23:11:10.262973 DQM Delay:
4489 23:11:10.263151 DQM0 = 52, DQM1 = 49
4490 23:11:10.263299 DQ Delay:
4491 23:11:10.266208 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4492 23:11:10.269524 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4493 23:11:10.273112 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4494 23:11:10.276133 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4495 23:11:10.276325
4496 23:11:10.276476
4497 23:11:10.276609 ==
4498 23:11:10.279879 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 23:11:10.285704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 23:11:10.285887 ==
4501 23:11:10.286037
4502 23:11:10.286170
4503 23:11:10.289297 TX Vref Scan disable
4504 23:11:10.289527 == TX Byte 0 ==
4505 23:11:10.292447 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4506 23:11:10.299220 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4507 23:11:10.299403 == TX Byte 1 ==
4508 23:11:10.302590 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4509 23:11:10.309379 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4510 23:11:10.309568 ==
4511 23:11:10.312117 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 23:11:10.315333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 23:11:10.315492 ==
4514 23:11:10.315624
4515 23:11:10.315750
4516 23:11:10.318803 TX Vref Scan disable
4517 23:11:10.322126 == TX Byte 0 ==
4518 23:11:10.325728 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4519 23:11:10.328820 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4520 23:11:10.331866 == TX Byte 1 ==
4521 23:11:10.335572 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4522 23:11:10.338750 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4523 23:11:10.338959
4524 23:11:10.342555 [DATLAT]
4525 23:11:10.342876 Freq=600, CH1 RK0
4526 23:11:10.343147
4527 23:11:10.346007 DATLAT Default: 0x9
4528 23:11:10.346258 0, 0xFFFF, sum = 0
4529 23:11:10.349044 1, 0xFFFF, sum = 0
4530 23:11:10.349298 2, 0xFFFF, sum = 0
4531 23:11:10.352121 3, 0xFFFF, sum = 0
4532 23:11:10.352375 4, 0xFFFF, sum = 0
4533 23:11:10.355571 5, 0xFFFF, sum = 0
4534 23:11:10.355824 6, 0xFFFF, sum = 0
4535 23:11:10.358725 7, 0xFFFF, sum = 0
4536 23:11:10.359030 8, 0x0, sum = 1
4537 23:11:10.362114 9, 0x0, sum = 2
4538 23:11:10.362368 10, 0x0, sum = 3
4539 23:11:10.365336 11, 0x0, sum = 4
4540 23:11:10.365614 best_step = 9
4541 23:11:10.365902
4542 23:11:10.366240 ==
4543 23:11:10.368777 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 23:11:10.372318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 23:11:10.374996 ==
4546 23:11:10.375256 RX Vref Scan: 1
4547 23:11:10.375471
4548 23:11:10.378941 RX Vref 0 -> 0, step: 1
4549 23:11:10.379268
4550 23:11:10.382506 RX Delay -147 -> 252, step: 8
4551 23:11:10.382766
4552 23:11:10.385656 Set Vref, RX VrefLevel [Byte0]: 54
4553 23:11:10.388619 [Byte1]: 54
4554 23:11:10.388906
4555 23:11:10.392047 Final RX Vref Byte 0 = 54 to rank0
4556 23:11:10.395146 Final RX Vref Byte 1 = 54 to rank0
4557 23:11:10.398376 Final RX Vref Byte 0 = 54 to rank1
4558 23:11:10.402180 Final RX Vref Byte 1 = 54 to rank1==
4559 23:11:10.405503 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 23:11:10.409017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 23:11:10.409269 ==
4562 23:11:10.409468 DQS Delay:
4563 23:11:10.411886 DQS0 = 0, DQS1 = 0
4564 23:11:10.412138 DQM Delay:
4565 23:11:10.415296 DQM0 = 47, DQM1 = 45
4566 23:11:10.415548 DQ Delay:
4567 23:11:10.418555 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4568 23:11:10.422204 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4569 23:11:10.425570 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4570 23:11:10.428574 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4571 23:11:10.428834
4572 23:11:10.429034
4573 23:11:10.438594 [DQSOSCAuto] RK0, (LSB)MR18= 0x4267, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
4574 23:11:10.438847 CH1 RK0: MR19=808, MR18=4267
4575 23:11:10.444881 CH1_RK0: MR19=0x808, MR18=0x4267, DQSOSC=390, MR23=63, INC=172, DEC=114
4576 23:11:10.445240
4577 23:11:10.448367 ----->DramcWriteLeveling(PI) begin...
4578 23:11:10.448621 ==
4579 23:11:10.451912 Dram Type= 6, Freq= 0, CH_1, rank 1
4580 23:11:10.458511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 23:11:10.458763 ==
4582 23:11:10.461985 Write leveling (Byte 0): 30 => 30
4583 23:11:10.465071 Write leveling (Byte 1): 30 => 30
4584 23:11:10.465322 DramcWriteLeveling(PI) end<-----
4585 23:11:10.465522
4586 23:11:10.468212 ==
4587 23:11:10.471606 Dram Type= 6, Freq= 0, CH_1, rank 1
4588 23:11:10.474831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 23:11:10.475083 ==
4590 23:11:10.478185 [Gating] SW mode calibration
4591 23:11:10.484633 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4592 23:11:10.488260 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4593 23:11:10.495510 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 23:11:10.498422 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 23:11:10.501860 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
4596 23:11:10.508202 0 9 12 | B1->B0 | 2c2c 2f2f | 0 0 | (0 0) (0 0)
4597 23:11:10.511981 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4598 23:11:10.515041 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 23:11:10.521378 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 23:11:10.524613 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 23:11:10.527986 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 23:11:10.534903 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 23:11:10.537953 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 23:11:10.541818 0 10 12 | B1->B0 | 3f3f 3a3a | 0 0 | (0 0) (0 0)
4605 23:11:10.548108 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 23:11:10.551968 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 23:11:10.554660 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 23:11:10.561794 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 23:11:10.564970 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 23:11:10.568127 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 23:11:10.574734 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 23:11:10.578136 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4613 23:11:10.581245 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 23:11:10.588065 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 23:11:10.591548 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 23:11:10.594467 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 23:11:10.601230 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 23:11:10.604349 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 23:11:10.608169 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 23:11:10.611049 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 23:11:10.617805 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 23:11:10.620936 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 23:11:10.624366 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 23:11:10.631682 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 23:11:10.634035 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 23:11:10.638039 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 23:11:10.644460 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4628 23:11:10.647773 Total UI for P1: 0, mck2ui 16
4629 23:11:10.651467 best dqsien dly found for B1: ( 0, 13, 6)
4630 23:11:10.654973 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4631 23:11:10.657816 Total UI for P1: 0, mck2ui 16
4632 23:11:10.660876 best dqsien dly found for B0: ( 0, 13, 8)
4633 23:11:10.664503 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4634 23:11:10.667827 best DQS1 dly(MCK, UI, PI) = (0, 13, 6)
4635 23:11:10.668240
4636 23:11:10.670691 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4637 23:11:10.674631 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 6)
4638 23:11:10.677873 [Gating] SW calibration Done
4639 23:11:10.678423 ==
4640 23:11:10.681205 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 23:11:10.684120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 23:11:10.687470 ==
4643 23:11:10.687926 RX Vref Scan: 0
4644 23:11:10.688287
4645 23:11:10.691166 RX Vref 0 -> 0, step: 1
4646 23:11:10.691619
4647 23:11:10.694843 RX Delay -230 -> 252, step: 16
4648 23:11:10.697673 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4649 23:11:10.700978 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4650 23:11:10.704406 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4651 23:11:10.710898 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4652 23:11:10.714051 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4653 23:11:10.717622 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4654 23:11:10.720738 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4655 23:11:10.723857 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4656 23:11:10.731181 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4657 23:11:10.734148 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4658 23:11:10.737215 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4659 23:11:10.740902 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4660 23:11:10.747380 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4661 23:11:10.750205 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4662 23:11:10.753987 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4663 23:11:10.757466 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4664 23:11:10.757950 ==
4665 23:11:10.761156 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 23:11:10.767110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 23:11:10.767525 ==
4668 23:11:10.767971 DQS Delay:
4669 23:11:10.768441 DQS0 = 0, DQS1 = 0
4670 23:11:10.770726 DQM Delay:
4671 23:11:10.771137 DQM0 = 50, DQM1 = 48
4672 23:11:10.774010 DQ Delay:
4673 23:11:10.776986 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4674 23:11:10.780989 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4675 23:11:10.783420 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4676 23:11:10.786762 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4677 23:11:10.787175
4678 23:11:10.787499
4679 23:11:10.787803 ==
4680 23:11:10.791084 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 23:11:10.793850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 23:11:10.794265 ==
4683 23:11:10.794596
4684 23:11:10.794900
4685 23:11:10.796760 TX Vref Scan disable
4686 23:11:10.797172 == TX Byte 0 ==
4687 23:11:10.803887 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4688 23:11:10.807060 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4689 23:11:10.807475 == TX Byte 1 ==
4690 23:11:10.813791 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4691 23:11:10.817024 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4692 23:11:10.817435 ==
4693 23:11:10.820699 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 23:11:10.823792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 23:11:10.824202 ==
4696 23:11:10.824527
4697 23:11:10.827066
4698 23:11:10.827473 TX Vref Scan disable
4699 23:11:10.830564 == TX Byte 0 ==
4700 23:11:10.834046 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4701 23:11:10.840480 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4702 23:11:10.840892 == TX Byte 1 ==
4703 23:11:10.843754 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4704 23:11:10.850147 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4705 23:11:10.850565
4706 23:11:10.850890 [DATLAT]
4707 23:11:10.851194 Freq=600, CH1 RK1
4708 23:11:10.851492
4709 23:11:10.853550 DATLAT Default: 0x9
4710 23:11:10.854111 0, 0xFFFF, sum = 0
4711 23:11:10.857128 1, 0xFFFF, sum = 0
4712 23:11:10.860250 2, 0xFFFF, sum = 0
4713 23:11:10.860669 3, 0xFFFF, sum = 0
4714 23:11:10.863431 4, 0xFFFF, sum = 0
4715 23:11:10.863850 5, 0xFFFF, sum = 0
4716 23:11:10.866732 6, 0xFFFF, sum = 0
4717 23:11:10.867155 7, 0xFFFF, sum = 0
4718 23:11:10.870130 8, 0x0, sum = 1
4719 23:11:10.870549 9, 0x0, sum = 2
4720 23:11:10.870883 10, 0x0, sum = 3
4721 23:11:10.873680 11, 0x0, sum = 4
4722 23:11:10.874100 best_step = 9
4723 23:11:10.874427
4724 23:11:10.874730 ==
4725 23:11:10.876640 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 23:11:10.883647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 23:11:10.884061 ==
4728 23:11:10.884386 RX Vref Scan: 0
4729 23:11:10.884697
4730 23:11:10.886946 RX Vref 0 -> 0, step: 1
4731 23:11:10.887359
4732 23:11:10.889977 RX Delay -163 -> 252, step: 8
4733 23:11:10.893561 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4734 23:11:10.900359 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4735 23:11:10.903538 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4736 23:11:10.906577 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4737 23:11:10.910364 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4738 23:11:10.912929 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4739 23:11:10.919693 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4740 23:11:10.923041 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4741 23:11:10.926721 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4742 23:11:10.929890 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4743 23:11:10.933295 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4744 23:11:10.939454 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4745 23:11:10.943213 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4746 23:11:10.946257 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4747 23:11:10.949550 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4748 23:11:10.956527 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4749 23:11:10.956941 ==
4750 23:11:10.959937 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 23:11:10.963264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 23:11:10.963681 ==
4753 23:11:10.964012 DQS Delay:
4754 23:11:10.966239 DQS0 = 0, DQS1 = 0
4755 23:11:10.966652 DQM Delay:
4756 23:11:10.969533 DQM0 = 48, DQM1 = 45
4757 23:11:10.970083 DQ Delay:
4758 23:11:10.973150 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4759 23:11:10.976175 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4760 23:11:10.979644 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4761 23:11:10.983053 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4762 23:11:10.983463
4763 23:11:10.983788
4764 23:11:10.989508 [DQSOSCAuto] RK1, (LSB)MR18= 0x6921, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 390 ps
4765 23:11:10.992646 CH1 RK1: MR19=808, MR18=6921
4766 23:11:10.999998 CH1_RK1: MR19=0x808, MR18=0x6921, DQSOSC=390, MR23=63, INC=172, DEC=114
4767 23:11:11.002766 [RxdqsGatingPostProcess] freq 600
4768 23:11:11.009906 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4769 23:11:11.013081 Pre-setting of DQS Precalculation
4770 23:11:11.016121 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4771 23:11:11.023133 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4772 23:11:11.029504 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4773 23:11:11.029980
4774 23:11:11.030314
4775 23:11:11.032684 [Calibration Summary] 1200 Mbps
4776 23:11:11.036134 CH 0, Rank 0
4777 23:11:11.036548 SW Impedance : PASS
4778 23:11:11.039686 DUTY Scan : NO K
4779 23:11:11.043403 ZQ Calibration : PASS
4780 23:11:11.043813 Jitter Meter : NO K
4781 23:11:11.046219 CBT Training : PASS
4782 23:11:11.046628 Write leveling : PASS
4783 23:11:11.049864 RX DQS gating : PASS
4784 23:11:11.052821 RX DQ/DQS(RDDQC) : PASS
4785 23:11:11.053232 TX DQ/DQS : PASS
4786 23:11:11.056818 RX DATLAT : PASS
4787 23:11:11.059375 RX DQ/DQS(Engine): PASS
4788 23:11:11.059792 TX OE : NO K
4789 23:11:11.062935 All Pass.
4790 23:11:11.063524
4791 23:11:11.063986 CH 0, Rank 1
4792 23:11:11.065949 SW Impedance : PASS
4793 23:11:11.066382 DUTY Scan : NO K
4794 23:11:11.069523 ZQ Calibration : PASS
4795 23:11:11.072563 Jitter Meter : NO K
4796 23:11:11.073116 CBT Training : PASS
4797 23:11:11.075989 Write leveling : PASS
4798 23:11:11.079420 RX DQS gating : PASS
4799 23:11:11.080056 RX DQ/DQS(RDDQC) : PASS
4800 23:11:11.082678 TX DQ/DQS : PASS
4801 23:11:11.085934 RX DATLAT : PASS
4802 23:11:11.086351 RX DQ/DQS(Engine): PASS
4803 23:11:11.089180 TX OE : NO K
4804 23:11:11.089754 All Pass.
4805 23:11:11.090238
4806 23:11:11.092466 CH 1, Rank 0
4807 23:11:11.093070 SW Impedance : PASS
4808 23:11:11.096286 DUTY Scan : NO K
4809 23:11:11.099077 ZQ Calibration : PASS
4810 23:11:11.099652 Jitter Meter : NO K
4811 23:11:11.102172 CBT Training : PASS
4812 23:11:11.102699 Write leveling : PASS
4813 23:11:11.105882 RX DQS gating : PASS
4814 23:11:11.108823 RX DQ/DQS(RDDQC) : PASS
4815 23:11:11.109238 TX DQ/DQS : PASS
4816 23:11:11.112201 RX DATLAT : PASS
4817 23:11:11.115654 RX DQ/DQS(Engine): PASS
4818 23:11:11.116068 TX OE : NO K
4819 23:11:11.118977 All Pass.
4820 23:11:11.119423
4821 23:11:11.119997 CH 1, Rank 1
4822 23:11:11.122174 SW Impedance : PASS
4823 23:11:11.122806 DUTY Scan : NO K
4824 23:11:11.125991 ZQ Calibration : PASS
4825 23:11:11.129283 Jitter Meter : NO K
4826 23:11:11.129837 CBT Training : PASS
4827 23:11:11.132315 Write leveling : PASS
4828 23:11:11.136135 RX DQS gating : PASS
4829 23:11:11.136646 RX DQ/DQS(RDDQC) : PASS
4830 23:11:11.139342 TX DQ/DQS : PASS
4831 23:11:11.142631 RX DATLAT : PASS
4832 23:11:11.143138 RX DQ/DQS(Engine): PASS
4833 23:11:11.145830 TX OE : NO K
4834 23:11:11.146400 All Pass.
4835 23:11:11.146814
4836 23:11:11.150302 DramC Write-DBI off
4837 23:11:11.152237 PER_BANK_REFRESH: Hybrid Mode
4838 23:11:11.152724 TX_TRACKING: ON
4839 23:11:11.162450 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4840 23:11:11.166163 [FAST_K] Save calibration result to emmc
4841 23:11:11.169052 dramc_set_vcore_voltage set vcore to 662500
4842 23:11:11.172640 Read voltage for 933, 3
4843 23:11:11.173054 Vio18 = 0
4844 23:11:11.173384 Vcore = 662500
4845 23:11:11.173733 Vdram = 0
4846 23:11:11.176359 Vddq = 0
4847 23:11:11.176872 Vmddr = 0
4848 23:11:11.182523 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4849 23:11:11.185797 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4850 23:11:11.189247 MEM_TYPE=3, freq_sel=17
4851 23:11:11.192463 sv_algorithm_assistance_LP4_1600
4852 23:11:11.195730 ============ PULL DRAM RESETB DOWN ============
4853 23:11:11.198906 ========== PULL DRAM RESETB DOWN end =========
4854 23:11:11.205767 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4855 23:11:11.209200 ===================================
4856 23:11:11.209746 LPDDR4 DRAM CONFIGURATION
4857 23:11:11.212260 ===================================
4858 23:11:11.215887 EX_ROW_EN[0] = 0x0
4859 23:11:11.218967 EX_ROW_EN[1] = 0x0
4860 23:11:11.219476 LP4Y_EN = 0x0
4861 23:11:11.222155 WORK_FSP = 0x0
4862 23:11:11.222737 WL = 0x3
4863 23:11:11.225351 RL = 0x3
4864 23:11:11.225910 BL = 0x2
4865 23:11:11.228836 RPST = 0x0
4866 23:11:11.229498 RD_PRE = 0x0
4867 23:11:11.232555 WR_PRE = 0x1
4868 23:11:11.233101 WR_PST = 0x0
4869 23:11:11.235360 DBI_WR = 0x0
4870 23:11:11.235806 DBI_RD = 0x0
4871 23:11:11.238931 OTF = 0x1
4872 23:11:11.242191 ===================================
4873 23:11:11.245621 ===================================
4874 23:11:11.246046 ANA top config
4875 23:11:11.248860 ===================================
4876 23:11:11.252424 DLL_ASYNC_EN = 0
4877 23:11:11.256130 ALL_SLAVE_EN = 1
4878 23:11:11.256546 NEW_RANK_MODE = 1
4879 23:11:11.259172 DLL_IDLE_MODE = 1
4880 23:11:11.262047 LP45_APHY_COMB_EN = 1
4881 23:11:11.265372 TX_ODT_DIS = 1
4882 23:11:11.268997 NEW_8X_MODE = 1
4883 23:11:11.269431 ===================================
4884 23:11:11.271904 ===================================
4885 23:11:11.275881 data_rate = 1866
4886 23:11:11.278946 CKR = 1
4887 23:11:11.282142 DQ_P2S_RATIO = 8
4888 23:11:11.285268 ===================================
4889 23:11:11.288563 CA_P2S_RATIO = 8
4890 23:11:11.292378 DQ_CA_OPEN = 0
4891 23:11:11.295543 DQ_SEMI_OPEN = 0
4892 23:11:11.296113 CA_SEMI_OPEN = 0
4893 23:11:11.298514 CA_FULL_RATE = 0
4894 23:11:11.302257 DQ_CKDIV4_EN = 1
4895 23:11:11.305175 CA_CKDIV4_EN = 1
4896 23:11:11.308542 CA_PREDIV_EN = 0
4897 23:11:11.308851 PH8_DLY = 0
4898 23:11:11.311808 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4899 23:11:11.315268 DQ_AAMCK_DIV = 4
4900 23:11:11.318540 CA_AAMCK_DIV = 4
4901 23:11:11.321770 CA_ADMCK_DIV = 4
4902 23:11:11.325254 DQ_TRACK_CA_EN = 0
4903 23:11:11.328470 CA_PICK = 933
4904 23:11:11.328694 CA_MCKIO = 933
4905 23:11:11.331760 MCKIO_SEMI = 0
4906 23:11:11.334799 PLL_FREQ = 3732
4907 23:11:11.338318 DQ_UI_PI_RATIO = 32
4908 23:11:11.341881 CA_UI_PI_RATIO = 0
4909 23:11:11.344889 ===================================
4910 23:11:11.348775 ===================================
4911 23:11:11.351691 memory_type:LPDDR4
4912 23:11:11.352086 GP_NUM : 10
4913 23:11:11.355032 SRAM_EN : 1
4914 23:11:11.355443 MD32_EN : 0
4915 23:11:11.358682 ===================================
4916 23:11:11.361693 [ANA_INIT] >>>>>>>>>>>>>>
4917 23:11:11.364912 <<<<<< [CONFIGURE PHASE]: ANA_TX
4918 23:11:11.368498 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4919 23:11:11.371552 ===================================
4920 23:11:11.375114 data_rate = 1866,PCW = 0X8f00
4921 23:11:11.378094 ===================================
4922 23:11:11.381103 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4923 23:11:11.387967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4924 23:11:11.391310 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 23:11:11.398008 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4926 23:11:11.401236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4927 23:11:11.404485 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4928 23:11:11.405062 [ANA_INIT] flow start
4929 23:11:11.407863 [ANA_INIT] PLL >>>>>>>>
4930 23:11:11.411330 [ANA_INIT] PLL <<<<<<<<
4931 23:11:11.411743 [ANA_INIT] MIDPI >>>>>>>>
4932 23:11:11.415156 [ANA_INIT] MIDPI <<<<<<<<
4933 23:11:11.417691 [ANA_INIT] DLL >>>>>>>>
4934 23:11:11.418108 [ANA_INIT] flow end
4935 23:11:11.424500 ============ LP4 DIFF to SE enter ============
4936 23:11:11.427760 ============ LP4 DIFF to SE exit ============
4937 23:11:11.430835 [ANA_INIT] <<<<<<<<<<<<<
4938 23:11:11.434242 [Flow] Enable top DCM control >>>>>
4939 23:11:11.437705 [Flow] Enable top DCM control <<<<<
4940 23:11:11.438131 Enable DLL master slave shuffle
4941 23:11:11.444341 ==============================================================
4942 23:11:11.447552 Gating Mode config
4943 23:11:11.450894 ==============================================================
4944 23:11:11.454205 Config description:
4945 23:11:11.464290 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4946 23:11:11.471077 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4947 23:11:11.474170 SELPH_MODE 0: By rank 1: By Phase
4948 23:11:11.481289 ==============================================================
4949 23:11:11.484417 GAT_TRACK_EN = 1
4950 23:11:11.487582 RX_GATING_MODE = 2
4951 23:11:11.490825 RX_GATING_TRACK_MODE = 2
4952 23:11:11.494240 SELPH_MODE = 1
4953 23:11:11.494668 PICG_EARLY_EN = 1
4954 23:11:11.497744 VALID_LAT_VALUE = 1
4955 23:11:11.504172 ==============================================================
4956 23:11:11.508024 Enter into Gating configuration >>>>
4957 23:11:11.510824 Exit from Gating configuration <<<<
4958 23:11:11.513758 Enter into DVFS_PRE_config >>>>>
4959 23:11:11.524438 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4960 23:11:11.527486 Exit from DVFS_PRE_config <<<<<
4961 23:11:11.530328 Enter into PICG configuration >>>>
4962 23:11:11.534086 Exit from PICG configuration <<<<
4963 23:11:11.537561 [RX_INPUT] configuration >>>>>
4964 23:11:11.540808 [RX_INPUT] configuration <<<<<
4965 23:11:11.544475 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4966 23:11:11.550996 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4967 23:11:11.557322 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 23:11:11.563867 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 23:11:11.570311 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 23:11:11.573789 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 23:11:11.580181 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4972 23:11:11.583451 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4973 23:11:11.586640 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4974 23:11:11.590207 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4975 23:11:11.596843 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4976 23:11:11.600266 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4977 23:11:11.603442 ===================================
4978 23:11:11.606808 LPDDR4 DRAM CONFIGURATION
4979 23:11:11.610242 ===================================
4980 23:11:11.610662 EX_ROW_EN[0] = 0x0
4981 23:11:11.613476 EX_ROW_EN[1] = 0x0
4982 23:11:11.613918 LP4Y_EN = 0x0
4983 23:11:11.616813 WORK_FSP = 0x0
4984 23:11:11.617228 WL = 0x3
4985 23:11:11.620447 RL = 0x3
4986 23:11:11.621004 BL = 0x2
4987 23:11:11.623772 RPST = 0x0
4988 23:11:11.624299 RD_PRE = 0x0
4989 23:11:11.627036 WR_PRE = 0x1
4990 23:11:11.627517 WR_PST = 0x0
4991 23:11:11.630075 DBI_WR = 0x0
4992 23:11:11.633520 DBI_RD = 0x0
4993 23:11:11.633989 OTF = 0x1
4994 23:11:11.636932 ===================================
4995 23:11:11.640624 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4996 23:11:11.643484 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4997 23:11:11.650446 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 23:11:11.653435 ===================================
4999 23:11:11.657356 LPDDR4 DRAM CONFIGURATION
5000 23:11:11.660871 ===================================
5001 23:11:11.661418 EX_ROW_EN[0] = 0x10
5002 23:11:11.663321 EX_ROW_EN[1] = 0x0
5003 23:11:11.663738 LP4Y_EN = 0x0
5004 23:11:11.667005 WORK_FSP = 0x0
5005 23:11:11.667531 WL = 0x3
5006 23:11:11.670776 RL = 0x3
5007 23:11:11.671348 BL = 0x2
5008 23:11:11.673328 RPST = 0x0
5009 23:11:11.673999 RD_PRE = 0x0
5010 23:11:11.676442 WR_PRE = 0x1
5011 23:11:11.676862 WR_PST = 0x0
5012 23:11:11.679920 DBI_WR = 0x0
5013 23:11:11.680447 DBI_RD = 0x0
5014 23:11:11.683615 OTF = 0x1
5015 23:11:11.687035 ===================================
5016 23:11:11.693099 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5017 23:11:11.697052 nWR fixed to 30
5018 23:11:11.700320 [ModeRegInit_LP4] CH0 RK0
5019 23:11:11.700739 [ModeRegInit_LP4] CH0 RK1
5020 23:11:11.703703 [ModeRegInit_LP4] CH1 RK0
5021 23:11:11.706499 [ModeRegInit_LP4] CH1 RK1
5022 23:11:11.707046 match AC timing 9
5023 23:11:11.713065 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5024 23:11:11.716450 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5025 23:11:11.720156 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5026 23:11:11.726604 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5027 23:11:11.729663 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5028 23:11:11.730224 ==
5029 23:11:11.733262 Dram Type= 6, Freq= 0, CH_0, rank 0
5030 23:11:11.736236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5031 23:11:11.736858 ==
5032 23:11:11.742672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5033 23:11:11.749573 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5034 23:11:11.753279 [CA 0] Center 37 (6~68) winsize 63
5035 23:11:11.756224 [CA 1] Center 37 (7~68) winsize 62
5036 23:11:11.759391 [CA 2] Center 34 (4~65) winsize 62
5037 23:11:11.762976 [CA 3] Center 34 (3~65) winsize 63
5038 23:11:11.765883 [CA 4] Center 33 (3~64) winsize 62
5039 23:11:11.769522 [CA 5] Center 32 (2~62) winsize 61
5040 23:11:11.770102
5041 23:11:11.774405 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5042 23:11:11.775010
5043 23:11:11.775980 [CATrainingPosCal] consider 1 rank data
5044 23:11:11.779580 u2DelayCellTimex100 = 270/100 ps
5045 23:11:11.782683 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5046 23:11:11.785789 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5047 23:11:11.788925 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5048 23:11:11.792709 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5049 23:11:11.795437 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5050 23:11:11.802237 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5051 23:11:11.802420
5052 23:11:11.806186 CA PerBit enable=1, Macro0, CA PI delay=32
5053 23:11:11.806344
5054 23:11:11.808997 [CBTSetCACLKResult] CA Dly = 32
5055 23:11:11.809127 CS Dly: 5 (0~36)
5056 23:11:11.809229 ==
5057 23:11:11.812599 Dram Type= 6, Freq= 0, CH_0, rank 1
5058 23:11:11.815605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 23:11:11.818835 ==
5060 23:11:11.822086 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 23:11:11.828782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5062 23:11:11.831887 [CA 0] Center 37 (6~68) winsize 63
5063 23:11:11.835367 [CA 1] Center 37 (6~68) winsize 63
5064 23:11:11.838857 [CA 2] Center 34 (4~65) winsize 62
5065 23:11:11.842008 [CA 3] Center 34 (3~65) winsize 63
5066 23:11:11.845163 [CA 4] Center 32 (2~63) winsize 62
5067 23:11:11.848646 [CA 5] Center 32 (2~62) winsize 61
5068 23:11:11.848736
5069 23:11:11.851999 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5070 23:11:11.852086
5071 23:11:11.855222 [CATrainingPosCal] consider 2 rank data
5072 23:11:11.858811 u2DelayCellTimex100 = 270/100 ps
5073 23:11:11.861589 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5074 23:11:11.865143 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5075 23:11:11.871688 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5076 23:11:11.874819 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5077 23:11:11.878471 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5078 23:11:11.881484 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5079 23:11:11.881632
5080 23:11:11.885134 CA PerBit enable=1, Macro0, CA PI delay=32
5081 23:11:11.885221
5082 23:11:11.888152 [CBTSetCACLKResult] CA Dly = 32
5083 23:11:11.888252 CS Dly: 5 (0~37)
5084 23:11:11.888318
5085 23:11:11.891466 ----->DramcWriteLeveling(PI) begin...
5086 23:11:11.894932 ==
5087 23:11:11.895042 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 23:11:11.901385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 23:11:11.901509 ==
5090 23:11:11.905304 Write leveling (Byte 0): 31 => 31
5091 23:11:11.908015 Write leveling (Byte 1): 29 => 29
5092 23:11:11.911412 DramcWriteLeveling(PI) end<-----
5093 23:11:11.911495
5094 23:11:11.911558 ==
5095 23:11:11.914675 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 23:11:11.917889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 23:11:11.917968 ==
5098 23:11:11.921032 [Gating] SW mode calibration
5099 23:11:11.927881 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5100 23:11:11.934561 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5101 23:11:11.938029 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5102 23:11:11.941159 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 23:11:11.947610 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 23:11:11.951369 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 23:11:11.954328 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 23:11:11.961056 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 23:11:11.964304 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5108 23:11:11.967872 0 14 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
5109 23:11:11.970954 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5110 23:11:11.977509 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 23:11:11.981304 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 23:11:11.984140 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 23:11:11.990965 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 23:11:11.994056 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 23:11:11.997739 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5116 23:11:12.004455 0 15 28 | B1->B0 | 2727 4141 | 0 1 | (0 0) (0 0)
5117 23:11:12.007537 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5118 23:11:12.010812 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 23:11:12.017740 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 23:11:12.021159 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 23:11:12.024183 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 23:11:12.030746 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 23:11:12.034084 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5124 23:11:12.037890 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5125 23:11:12.043934 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5126 23:11:12.047253 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 23:11:12.050642 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 23:11:12.057646 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 23:11:12.060681 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 23:11:12.063877 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 23:11:12.070772 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 23:11:12.074018 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 23:11:12.077114 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 23:11:12.083986 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 23:11:12.087369 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 23:11:12.090666 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 23:11:12.097316 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 23:11:12.100821 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 23:11:12.103749 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 23:11:12.110470 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5141 23:11:12.110937 Total UI for P1: 0, mck2ui 16
5142 23:11:12.117628 best dqsien dly found for B0: ( 1, 2, 26)
5143 23:11:12.120514 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 23:11:12.123651 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 23:11:12.127155 Total UI for P1: 0, mck2ui 16
5146 23:11:12.130524 best dqsien dly found for B1: ( 1, 3, 0)
5147 23:11:12.133709 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5148 23:11:12.137093 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5149 23:11:12.137566
5150 23:11:12.140491 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5151 23:11:12.143804 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5152 23:11:12.147133 [Gating] SW calibration Done
5153 23:11:12.147542 ==
5154 23:11:12.150677 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 23:11:12.156968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 23:11:12.157381 ==
5157 23:11:12.157762 RX Vref Scan: 0
5158 23:11:12.158233
5159 23:11:12.160983 RX Vref 0 -> 0, step: 1
5160 23:11:12.161527
5161 23:11:12.163800 RX Delay -80 -> 252, step: 8
5162 23:11:12.167043 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5163 23:11:12.170858 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5164 23:11:12.173892 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5165 23:11:12.177128 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5166 23:11:12.183800 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5167 23:11:12.187179 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5168 23:11:12.190239 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5169 23:11:12.193540 iDelay=208, Bit 7, Center 111 (24 ~ 199) 176
5170 23:11:12.196994 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5171 23:11:12.200067 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5172 23:11:12.206707 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5173 23:11:12.210429 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5174 23:11:12.213554 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5175 23:11:12.216664 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5176 23:11:12.220320 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5177 23:11:12.227035 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5178 23:11:12.227551 ==
5179 23:11:12.230970 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 23:11:12.233687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 23:11:12.234246 ==
5182 23:11:12.234614 DQS Delay:
5183 23:11:12.237268 DQS0 = 0, DQS1 = 0
5184 23:11:12.237885 DQM Delay:
5185 23:11:12.240026 DQM0 = 103, DQM1 = 95
5186 23:11:12.240503 DQ Delay:
5187 23:11:12.243283 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5188 23:11:12.246857 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =111
5189 23:11:12.249878 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5190 23:11:12.253121 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5191 23:11:12.253697
5192 23:11:12.254051
5193 23:11:12.254463 ==
5194 23:11:12.256727 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 23:11:12.259783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 23:11:12.263286 ==
5197 23:11:12.263706
5198 23:11:12.264130
5199 23:11:12.264525 TX Vref Scan disable
5200 23:11:12.266174 == TX Byte 0 ==
5201 23:11:12.269829 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5202 23:11:12.273136 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5203 23:11:12.276680 == TX Byte 1 ==
5204 23:11:12.279709 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5205 23:11:12.283197 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5206 23:11:12.286295 ==
5207 23:11:12.289707 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 23:11:12.293050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 23:11:12.293487 ==
5210 23:11:12.293893
5211 23:11:12.294210
5212 23:11:12.296837 TX Vref Scan disable
5213 23:11:12.297256 == TX Byte 0 ==
5214 23:11:12.303567 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5215 23:11:12.306373 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5216 23:11:12.306786 == TX Byte 1 ==
5217 23:11:12.312913 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5218 23:11:12.316101 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5219 23:11:12.316598
5220 23:11:12.317019 [DATLAT]
5221 23:11:12.319503 Freq=933, CH0 RK0
5222 23:11:12.320162
5223 23:11:12.320770 DATLAT Default: 0xd
5224 23:11:12.323249 0, 0xFFFF, sum = 0
5225 23:11:12.323879 1, 0xFFFF, sum = 0
5226 23:11:12.326639 2, 0xFFFF, sum = 0
5227 23:11:12.327058 3, 0xFFFF, sum = 0
5228 23:11:12.329741 4, 0xFFFF, sum = 0
5229 23:11:12.330451 5, 0xFFFF, sum = 0
5230 23:11:12.332884 6, 0xFFFF, sum = 0
5231 23:11:12.333393 7, 0xFFFF, sum = 0
5232 23:11:12.336805 8, 0xFFFF, sum = 0
5233 23:11:12.337224 9, 0xFFFF, sum = 0
5234 23:11:12.339446 10, 0x0, sum = 1
5235 23:11:12.340128 11, 0x0, sum = 2
5236 23:11:12.342937 12, 0x0, sum = 3
5237 23:11:12.343546 13, 0x0, sum = 4
5238 23:11:12.346162 best_step = 11
5239 23:11:12.346574
5240 23:11:12.346900 ==
5241 23:11:12.349562 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 23:11:12.352832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 23:11:12.353279 ==
5244 23:11:12.356328 RX Vref Scan: 1
5245 23:11:12.356736
5246 23:11:12.357064 RX Vref 0 -> 0, step: 1
5247 23:11:12.357371
5248 23:11:12.359632 RX Delay -45 -> 252, step: 4
5249 23:11:12.360046
5250 23:11:12.363020 Set Vref, RX VrefLevel [Byte0]: 54
5251 23:11:12.366615 [Byte1]: 55
5252 23:11:12.370229
5253 23:11:12.370732 Final RX Vref Byte 0 = 54 to rank0
5254 23:11:12.373539 Final RX Vref Byte 1 = 55 to rank0
5255 23:11:12.376609 Final RX Vref Byte 0 = 54 to rank1
5256 23:11:12.380342 Final RX Vref Byte 1 = 55 to rank1==
5257 23:11:12.383115 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 23:11:12.389694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 23:11:12.390115 ==
5260 23:11:12.390446 DQS Delay:
5261 23:11:12.392984 DQS0 = 0, DQS1 = 0
5262 23:11:12.393396 DQM Delay:
5263 23:11:12.393777 DQM0 = 104, DQM1 = 97
5264 23:11:12.397290 DQ Delay:
5265 23:11:12.399931 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5266 23:11:12.403363 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5267 23:11:12.406262 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =92
5268 23:11:12.409889 DQ12 =102, DQ13 =102, DQ14 =106, DQ15 =104
5269 23:11:12.410308
5270 23:11:12.410634
5271 23:11:12.416433 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5272 23:11:12.419671 CH0 RK0: MR19=505, MR18=2E26
5273 23:11:12.426335 CH0_RK0: MR19=0x505, MR18=0x2E26, DQSOSC=407, MR23=63, INC=65, DEC=43
5274 23:11:12.426760
5275 23:11:12.429495 ----->DramcWriteLeveling(PI) begin...
5276 23:11:12.429969 ==
5277 23:11:12.433171 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 23:11:12.436532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 23:11:12.439826 ==
5280 23:11:12.440241 Write leveling (Byte 0): 33 => 33
5281 23:11:12.442866 Write leveling (Byte 1): 28 => 28
5282 23:11:12.446723 DramcWriteLeveling(PI) end<-----
5283 23:11:12.447141
5284 23:11:12.447488 ==
5285 23:11:12.449635 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 23:11:12.456447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 23:11:12.456868 ==
5288 23:11:12.459574 [Gating] SW mode calibration
5289 23:11:12.465872 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5290 23:11:12.469678 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5291 23:11:12.476486 0 14 0 | B1->B0 | 3434 3332 | 1 1 | (1 1) (0 0)
5292 23:11:12.479174 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 23:11:12.482782 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 23:11:12.489937 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 23:11:12.493248 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 23:11:12.496188 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 23:11:12.502797 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 23:11:12.506520 0 14 28 | B1->B0 | 2929 2929 | 0 0 | (0 0) (0 0)
5299 23:11:12.509424 0 15 0 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
5300 23:11:12.515472 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 23:11:12.519226 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 23:11:12.522439 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 23:11:12.528708 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 23:11:12.532223 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 23:11:12.535651 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5306 23:11:12.542295 0 15 28 | B1->B0 | 3636 3535 | 1 0 | (0 0) (0 0)
5307 23:11:12.545416 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5308 23:11:12.548970 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 23:11:12.551839 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 23:11:12.558590 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 23:11:12.561968 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 23:11:12.565260 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 23:11:12.571985 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 23:11:12.575503 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5315 23:11:12.578897 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5316 23:11:12.585437 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 23:11:12.588985 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 23:11:12.592685 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 23:11:12.599080 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 23:11:12.602387 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 23:11:12.605544 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 23:11:12.612429 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 23:11:12.615467 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 23:11:12.618777 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 23:11:12.625310 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 23:11:12.628676 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 23:11:12.632257 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 23:11:12.639139 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 23:11:12.642025 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 23:11:12.645736 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5331 23:11:12.651899 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 23:11:12.652319 Total UI for P1: 0, mck2ui 16
5333 23:11:12.658910 best dqsien dly found for B0: ( 1, 2, 28)
5334 23:11:12.659449 Total UI for P1: 0, mck2ui 16
5335 23:11:12.661763 best dqsien dly found for B1: ( 1, 2, 30)
5336 23:11:12.668509 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5337 23:11:12.671581 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5338 23:11:12.672090
5339 23:11:12.674959 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5340 23:11:12.677781 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5341 23:11:12.681255 [Gating] SW calibration Done
5342 23:11:12.681826 ==
5343 23:11:12.684839 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 23:11:12.688471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 23:11:12.688882 ==
5346 23:11:12.691887 RX Vref Scan: 0
5347 23:11:12.692310
5348 23:11:12.692722 RX Vref 0 -> 0, step: 1
5349 23:11:12.693074
5350 23:11:12.694704 RX Delay -80 -> 252, step: 8
5351 23:11:12.697963 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5352 23:11:12.704639 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5353 23:11:12.707895 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5354 23:11:12.711317 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5355 23:11:12.714666 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5356 23:11:12.718006 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5357 23:11:12.721325 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5358 23:11:12.727935 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5359 23:11:12.730951 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5360 23:11:12.734773 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5361 23:11:12.738005 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5362 23:11:12.741379 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5363 23:11:12.744409 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5364 23:11:12.751122 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5365 23:11:12.754580 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5366 23:11:12.757870 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5367 23:11:12.758357 ==
5368 23:11:12.761174 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 23:11:12.764360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 23:11:12.764957 ==
5371 23:11:12.767848 DQS Delay:
5372 23:11:12.768396 DQS0 = 0, DQS1 = 0
5373 23:11:12.771270 DQM Delay:
5374 23:11:12.771678 DQM0 = 104, DQM1 = 95
5375 23:11:12.772004 DQ Delay:
5376 23:11:12.774253 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5377 23:11:12.777855 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5378 23:11:12.781069 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5379 23:11:12.787513 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5380 23:11:12.788007
5381 23:11:12.788334
5382 23:11:12.788634 ==
5383 23:11:12.791456 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 23:11:12.794103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 23:11:12.794538 ==
5386 23:11:12.794870
5387 23:11:12.795239
5388 23:11:12.797713 TX Vref Scan disable
5389 23:11:12.798123 == TX Byte 0 ==
5390 23:11:12.804327 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5391 23:11:12.807572 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5392 23:11:12.808054 == TX Byte 1 ==
5393 23:11:12.814312 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5394 23:11:12.817942 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5395 23:11:12.818357 ==
5396 23:11:12.821384 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 23:11:12.824640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 23:11:12.825163 ==
5399 23:11:12.825503
5400 23:11:12.825873
5401 23:11:12.827774 TX Vref Scan disable
5402 23:11:12.830765 == TX Byte 0 ==
5403 23:11:12.834336 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5404 23:11:12.837749 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5405 23:11:12.841011 == TX Byte 1 ==
5406 23:11:12.844484 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5407 23:11:12.847509 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5408 23:11:12.847940
5409 23:11:12.850644 [DATLAT]
5410 23:11:12.851050 Freq=933, CH0 RK1
5411 23:11:12.851378
5412 23:11:12.854038 DATLAT Default: 0xb
5413 23:11:12.854463 0, 0xFFFF, sum = 0
5414 23:11:12.857535 1, 0xFFFF, sum = 0
5415 23:11:12.858075 2, 0xFFFF, sum = 0
5416 23:11:12.860832 3, 0xFFFF, sum = 0
5417 23:11:12.861304 4, 0xFFFF, sum = 0
5418 23:11:12.863855 5, 0xFFFF, sum = 0
5419 23:11:12.864499 6, 0xFFFF, sum = 0
5420 23:11:12.867113 7, 0xFFFF, sum = 0
5421 23:11:12.867530 8, 0xFFFF, sum = 0
5422 23:11:12.870879 9, 0xFFFF, sum = 0
5423 23:11:12.871363 10, 0x0, sum = 1
5424 23:11:12.874163 11, 0x0, sum = 2
5425 23:11:12.874697 12, 0x0, sum = 3
5426 23:11:12.876963 13, 0x0, sum = 4
5427 23:11:12.877509 best_step = 11
5428 23:11:12.878082
5429 23:11:12.878626 ==
5430 23:11:12.880941 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 23:11:12.887051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 23:11:12.887594 ==
5433 23:11:12.888011 RX Vref Scan: 0
5434 23:11:12.888326
5435 23:11:12.890602 RX Vref 0 -> 0, step: 1
5436 23:11:12.891073
5437 23:11:12.893341 RX Delay -45 -> 252, step: 4
5438 23:11:12.897062 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5439 23:11:12.903247 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5440 23:11:12.906596 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5441 23:11:12.910472 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5442 23:11:12.913365 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5443 23:11:12.916401 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5444 23:11:12.923217 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5445 23:11:12.926976 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5446 23:11:12.930445 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5447 23:11:12.933558 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5448 23:11:12.937048 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5449 23:11:12.940300 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5450 23:11:12.946591 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5451 23:11:12.949692 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5452 23:11:12.953756 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5453 23:11:12.956648 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5454 23:11:12.957063 ==
5455 23:11:12.959513 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 23:11:12.966529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 23:11:12.966942 ==
5458 23:11:12.967265 DQS Delay:
5459 23:11:12.970395 DQS0 = 0, DQS1 = 0
5460 23:11:12.970818 DQM Delay:
5461 23:11:12.971146 DQM0 = 104, DQM1 = 95
5462 23:11:12.973125 DQ Delay:
5463 23:11:12.976305 DQ0 =100, DQ1 =108, DQ2 =102, DQ3 =100
5464 23:11:12.979695 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5465 23:11:12.983221 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =90
5466 23:11:12.986586 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5467 23:11:12.986995
5468 23:11:12.987316
5469 23:11:12.993269 [DQSOSCAuto] RK1, (LSB)MR18= 0x2902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5470 23:11:12.996202 CH0 RK1: MR19=505, MR18=2902
5471 23:11:13.003012 CH0_RK1: MR19=0x505, MR18=0x2902, DQSOSC=408, MR23=63, INC=65, DEC=43
5472 23:11:13.007036 [RxdqsGatingPostProcess] freq 933
5473 23:11:13.013148 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5474 23:11:13.016625 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 23:11:13.020098 best DQS1 dly(2T, 0.5T) = (0, 11)
5476 23:11:13.022486 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 23:11:13.025923 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5478 23:11:13.026332 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 23:11:13.029783 best DQS1 dly(2T, 0.5T) = (0, 10)
5480 23:11:13.033026 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 23:11:13.036477 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5482 23:11:13.039534 Pre-setting of DQS Precalculation
5483 23:11:13.045971 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5484 23:11:13.046383 ==
5485 23:11:13.049807 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 23:11:13.053250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 23:11:13.053849 ==
5488 23:11:13.059837 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5489 23:11:13.062821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5490 23:11:13.067004 [CA 0] Center 36 (6~67) winsize 62
5491 23:11:13.070191 [CA 1] Center 36 (6~67) winsize 62
5492 23:11:13.073616 [CA 2] Center 34 (4~65) winsize 62
5493 23:11:13.077073 [CA 3] Center 34 (4~65) winsize 62
5494 23:11:13.080322 [CA 4] Center 34 (4~64) winsize 61
5495 23:11:13.083491 [CA 5] Center 33 (3~64) winsize 62
5496 23:11:13.083908
5497 23:11:13.087047 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5498 23:11:13.087455
5499 23:11:13.090429 [CATrainingPosCal] consider 1 rank data
5500 23:11:13.093319 u2DelayCellTimex100 = 270/100 ps
5501 23:11:13.096714 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5502 23:11:13.103402 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5503 23:11:13.106992 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5504 23:11:13.110548 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5505 23:11:13.113330 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5506 23:11:13.116974 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5507 23:11:13.117484
5508 23:11:13.120669 CA PerBit enable=1, Macro0, CA PI delay=33
5509 23:11:13.121226
5510 23:11:13.123613 [CBTSetCACLKResult] CA Dly = 33
5511 23:11:13.124068 CS Dly: 6 (0~37)
5512 23:11:13.127247 ==
5513 23:11:13.130547 Dram Type= 6, Freq= 0, CH_1, rank 1
5514 23:11:13.134086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 23:11:13.134639 ==
5516 23:11:13.137185 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 23:11:13.143002 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5518 23:11:13.147871 [CA 0] Center 36 (6~67) winsize 62
5519 23:11:13.150292 [CA 1] Center 37 (7~68) winsize 62
5520 23:11:13.153562 [CA 2] Center 34 (4~65) winsize 62
5521 23:11:13.157028 [CA 3] Center 34 (4~65) winsize 62
5522 23:11:13.160556 [CA 4] Center 34 (4~65) winsize 62
5523 23:11:13.163655 [CA 5] Center 33 (3~64) winsize 62
5524 23:11:13.164112
5525 23:11:13.167242 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5526 23:11:13.167655
5527 23:11:13.170158 [CATrainingPosCal] consider 2 rank data
5528 23:11:13.174058 u2DelayCellTimex100 = 270/100 ps
5529 23:11:13.177255 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 23:11:13.180907 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5531 23:11:13.187655 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5532 23:11:13.190457 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5533 23:11:13.193726 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5534 23:11:13.197393 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5535 23:11:13.197843
5536 23:11:13.200755 CA PerBit enable=1, Macro0, CA PI delay=33
5537 23:11:13.201318
5538 23:11:13.203877 [CBTSetCACLKResult] CA Dly = 33
5539 23:11:13.204431 CS Dly: 7 (0~40)
5540 23:11:13.204793
5541 23:11:13.207317 ----->DramcWriteLeveling(PI) begin...
5542 23:11:13.210682 ==
5543 23:11:13.213543 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 23:11:13.217494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 23:11:13.218095 ==
5546 23:11:13.220513 Write leveling (Byte 0): 28 => 28
5547 23:11:13.223946 Write leveling (Byte 1): 28 => 28
5548 23:11:13.227237 DramcWriteLeveling(PI) end<-----
5549 23:11:13.227792
5550 23:11:13.228152 ==
5551 23:11:13.230307 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 23:11:13.233883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 23:11:13.234430 ==
5554 23:11:13.237511 [Gating] SW mode calibration
5555 23:11:13.243522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5556 23:11:13.246801 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5557 23:11:13.253467 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 23:11:13.256717 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 23:11:13.260161 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 23:11:13.266732 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 23:11:13.270302 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 23:11:13.273639 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 23:11:13.280059 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (0 1) (1 0)
5564 23:11:13.283743 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (1 0)
5565 23:11:13.287444 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 23:11:13.293831 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 23:11:13.296627 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 23:11:13.300390 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 23:11:13.307252 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 23:11:13.309902 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 23:11:13.313992 0 15 24 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
5572 23:11:13.319991 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5573 23:11:13.323523 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 23:11:13.326540 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 23:11:13.332967 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 23:11:13.336906 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 23:11:13.339771 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 23:11:13.347181 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5579 23:11:13.349515 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5580 23:11:13.352879 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 23:11:13.359835 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 23:11:13.362837 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 23:11:13.366001 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 23:11:13.372700 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 23:11:13.375904 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 23:11:13.379269 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 23:11:13.386134 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 23:11:13.389287 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 23:11:13.392150 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 23:11:13.399166 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 23:11:13.402591 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 23:11:13.405907 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 23:11:13.409027 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 23:11:13.415615 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 23:11:13.419455 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5596 23:11:13.422430 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 23:11:13.425952 Total UI for P1: 0, mck2ui 16
5598 23:11:13.428789 best dqsien dly found for B0: ( 1, 2, 24)
5599 23:11:13.432092 Total UI for P1: 0, mck2ui 16
5600 23:11:13.435615 best dqsien dly found for B1: ( 1, 2, 24)
5601 23:11:13.438621 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5602 23:11:13.442152 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5603 23:11:13.446099
5604 23:11:13.448592 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5605 23:11:13.451962 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5606 23:11:13.455590 [Gating] SW calibration Done
5607 23:11:13.455675 ==
5608 23:11:13.458874 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 23:11:13.462109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 23:11:13.462191 ==
5611 23:11:13.462256 RX Vref Scan: 0
5612 23:11:13.465781
5613 23:11:13.465862 RX Vref 0 -> 0, step: 1
5614 23:11:13.465926
5615 23:11:13.468679 RX Delay -80 -> 252, step: 8
5616 23:11:13.472334 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5617 23:11:13.475635 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5618 23:11:13.482050 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5619 23:11:13.485611 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5620 23:11:13.488700 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5621 23:11:13.491742 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5622 23:11:13.495619 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5623 23:11:13.498716 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5624 23:11:13.505202 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5625 23:11:13.509247 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5626 23:11:13.511722 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5627 23:11:13.515480 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5628 23:11:13.518409 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5629 23:11:13.521871 iDelay=208, Bit 13, Center 107 (24 ~ 191) 168
5630 23:11:13.528642 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5631 23:11:13.531871 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5632 23:11:13.531953 ==
5633 23:11:13.535366 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 23:11:13.538690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 23:11:13.538771 ==
5636 23:11:13.541500 DQS Delay:
5637 23:11:13.541609 DQS0 = 0, DQS1 = 0
5638 23:11:13.541676 DQM Delay:
5639 23:11:13.545125 DQM0 = 102, DQM1 = 99
5640 23:11:13.545207 DQ Delay:
5641 23:11:13.548301 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5642 23:11:13.551859 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5643 23:11:13.554844 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5644 23:11:13.558168 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5645 23:11:13.561616
5646 23:11:13.561698
5647 23:11:13.561763 ==
5648 23:11:13.564938 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 23:11:13.568326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 23:11:13.568408 ==
5651 23:11:13.568473
5652 23:11:13.568532
5653 23:11:13.571388 TX Vref Scan disable
5654 23:11:13.571469 == TX Byte 0 ==
5655 23:11:13.578428 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5656 23:11:13.581507 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5657 23:11:13.581647 == TX Byte 1 ==
5658 23:11:13.587981 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5659 23:11:13.591465 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5660 23:11:13.591547 ==
5661 23:11:13.594787 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 23:11:13.598239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 23:11:13.598322 ==
5664 23:11:13.598387
5665 23:11:13.598447
5666 23:11:13.601324 TX Vref Scan disable
5667 23:11:13.604908 == TX Byte 0 ==
5668 23:11:13.608144 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5669 23:11:13.611598 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5670 23:11:13.614573 == TX Byte 1 ==
5671 23:11:13.617908 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5672 23:11:13.621235 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5673 23:11:13.621316
5674 23:11:13.624622 [DATLAT]
5675 23:11:13.624702 Freq=933, CH1 RK0
5676 23:11:13.624767
5677 23:11:13.627924 DATLAT Default: 0xd
5678 23:11:13.628004 0, 0xFFFF, sum = 0
5679 23:11:13.631334 1, 0xFFFF, sum = 0
5680 23:11:13.631415 2, 0xFFFF, sum = 0
5681 23:11:13.634609 3, 0xFFFF, sum = 0
5682 23:11:13.634691 4, 0xFFFF, sum = 0
5683 23:11:13.638291 5, 0xFFFF, sum = 0
5684 23:11:13.638373 6, 0xFFFF, sum = 0
5685 23:11:13.641075 7, 0xFFFF, sum = 0
5686 23:11:13.641157 8, 0xFFFF, sum = 0
5687 23:11:13.644563 9, 0xFFFF, sum = 0
5688 23:11:13.644646 10, 0x0, sum = 1
5689 23:11:13.647797 11, 0x0, sum = 2
5690 23:11:13.647878 12, 0x0, sum = 3
5691 23:11:13.650996 13, 0x0, sum = 4
5692 23:11:13.651079 best_step = 11
5693 23:11:13.651143
5694 23:11:13.651202 ==
5695 23:11:13.654578 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 23:11:13.661142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 23:11:13.661224 ==
5698 23:11:13.661288 RX Vref Scan: 1
5699 23:11:13.661348
5700 23:11:13.664340 RX Vref 0 -> 0, step: 1
5701 23:11:13.664421
5702 23:11:13.668079 RX Delay -45 -> 252, step: 4
5703 23:11:13.668161
5704 23:11:13.671123 Set Vref, RX VrefLevel [Byte0]: 54
5705 23:11:13.674384 [Byte1]: 54
5706 23:11:13.674465
5707 23:11:13.677927 Final RX Vref Byte 0 = 54 to rank0
5708 23:11:13.680994 Final RX Vref Byte 1 = 54 to rank0
5709 23:11:13.684813 Final RX Vref Byte 0 = 54 to rank1
5710 23:11:13.688194 Final RX Vref Byte 1 = 54 to rank1==
5711 23:11:13.691271 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 23:11:13.694726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 23:11:13.694859 ==
5714 23:11:13.698009 DQS Delay:
5715 23:11:13.698169 DQS0 = 0, DQS1 = 0
5716 23:11:13.698246 DQM Delay:
5717 23:11:13.701510 DQM0 = 102, DQM1 = 99
5718 23:11:13.701719 DQ Delay:
5719 23:11:13.704731 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5720 23:11:13.708083 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =102
5721 23:11:13.711369 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5722 23:11:13.714637 DQ12 =104, DQ13 =104, DQ14 =106, DQ15 =106
5723 23:11:13.714798
5724 23:11:13.718228
5725 23:11:13.724671 [DQSOSCAuto] RK0, (LSB)MR18= 0x152c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5726 23:11:13.727713 CH1 RK0: MR19=505, MR18=152C
5727 23:11:13.734681 CH1_RK0: MR19=0x505, MR18=0x152C, DQSOSC=408, MR23=63, INC=65, DEC=43
5728 23:11:13.734808
5729 23:11:13.737431 ----->DramcWriteLeveling(PI) begin...
5730 23:11:13.737532 ==
5731 23:11:13.741184 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 23:11:13.744648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 23:11:13.744730 ==
5734 23:11:13.747724 Write leveling (Byte 0): 28 => 28
5735 23:11:13.750876 Write leveling (Byte 1): 30 => 30
5736 23:11:13.754106 DramcWriteLeveling(PI) end<-----
5737 23:11:13.754193
5738 23:11:13.754257 ==
5739 23:11:13.757477 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 23:11:13.760732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 23:11:13.760816 ==
5742 23:11:13.763885 [Gating] SW mode calibration
5743 23:11:13.771029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5744 23:11:13.777389 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5745 23:11:13.781002 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 23:11:13.783744 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 23:11:13.790665 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 23:11:13.794363 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 23:11:13.797152 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 23:11:13.804012 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 23:11:13.807313 0 14 24 | B1->B0 | 2f2f 3131 | 1 0 | (1 0) (0 1)
5752 23:11:13.810932 0 14 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 0)
5753 23:11:13.817412 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 23:11:13.820427 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 23:11:13.823960 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 23:11:13.830628 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 23:11:13.833875 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 23:11:13.837377 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 23:11:13.843866 0 15 24 | B1->B0 | 3636 2b2b | 0 0 | (1 1) (1 1)
5760 23:11:13.847348 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5761 23:11:13.850398 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 23:11:13.856989 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 23:11:13.860263 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 23:11:13.863550 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 23:11:13.866868 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 23:11:13.873531 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 23:11:13.877033 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5768 23:11:13.880326 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5769 23:11:13.887124 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 23:11:13.890295 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 23:11:13.893422 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 23:11:13.900459 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 23:11:13.903799 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 23:11:13.906781 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 23:11:13.913544 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 23:11:13.917030 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 23:11:13.919906 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 23:11:13.926546 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 23:11:13.930242 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 23:11:13.933728 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 23:11:13.940329 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 23:11:13.943581 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 23:11:13.947030 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5784 23:11:13.953743 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 23:11:13.953830 Total UI for P1: 0, mck2ui 16
5786 23:11:13.959989 best dqsien dly found for B0: ( 1, 2, 24)
5787 23:11:13.960077 Total UI for P1: 0, mck2ui 16
5788 23:11:13.966730 best dqsien dly found for B1: ( 1, 2, 24)
5789 23:11:13.969838 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5790 23:11:13.973185 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5791 23:11:13.973270
5792 23:11:13.976630 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5793 23:11:13.979408 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5794 23:11:13.982976 [Gating] SW calibration Done
5795 23:11:13.983064 ==
5796 23:11:13.986189 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 23:11:13.989862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 23:11:13.989946 ==
5799 23:11:13.992863 RX Vref Scan: 0
5800 23:11:13.992971
5801 23:11:13.993063 RX Vref 0 -> 0, step: 1
5802 23:11:13.993151
5803 23:11:13.996281 RX Delay -80 -> 252, step: 8
5804 23:11:14.003460 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5805 23:11:14.006737 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5806 23:11:14.010217 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5807 23:11:14.013476 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5808 23:11:14.016767 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5809 23:11:14.020064 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5810 23:11:14.023183 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5811 23:11:14.029777 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5812 23:11:14.033156 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5813 23:11:14.036179 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5814 23:11:14.039501 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5815 23:11:14.043315 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5816 23:11:14.046105 iDelay=208, Bit 12, Center 111 (24 ~ 199) 176
5817 23:11:14.052878 iDelay=208, Bit 13, Center 111 (24 ~ 199) 176
5818 23:11:14.056290 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5819 23:11:14.059941 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5820 23:11:14.060025 ==
5821 23:11:14.063264 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 23:11:14.066396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 23:11:14.066480 ==
5824 23:11:14.069234 DQS Delay:
5825 23:11:14.069316 DQS0 = 0, DQS1 = 0
5826 23:11:14.072895 DQM Delay:
5827 23:11:14.072979 DQM0 = 103, DQM1 = 100
5828 23:11:14.076482 DQ Delay:
5829 23:11:14.076567 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =99
5830 23:11:14.079712 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5831 23:11:14.082653 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5832 23:11:14.089176 DQ12 =111, DQ13 =111, DQ14 =103, DQ15 =107
5833 23:11:14.089261
5834 23:11:14.089345
5835 23:11:14.089424 ==
5836 23:11:14.092455 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 23:11:14.095909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 23:11:14.095994 ==
5839 23:11:14.096079
5840 23:11:14.096159
5841 23:11:14.099235 TX Vref Scan disable
5842 23:11:14.099318 == TX Byte 0 ==
5843 23:11:14.105900 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5844 23:11:14.109940 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5845 23:11:14.110023 == TX Byte 1 ==
5846 23:11:14.115794 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5847 23:11:14.119355 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5848 23:11:14.119440 ==
5849 23:11:14.122782 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 23:11:14.125880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 23:11:14.125961 ==
5852 23:11:14.126026
5853 23:11:14.126086
5854 23:11:14.129676 TX Vref Scan disable
5855 23:11:14.132909 == TX Byte 0 ==
5856 23:11:14.135695 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5857 23:11:14.139266 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5858 23:11:14.142289 == TX Byte 1 ==
5859 23:11:14.146294 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5860 23:11:14.149049 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5861 23:11:14.149131
5862 23:11:14.152386 [DATLAT]
5863 23:11:14.152472 Freq=933, CH1 RK1
5864 23:11:14.152537
5865 23:11:14.155594 DATLAT Default: 0xb
5866 23:11:14.155708 0, 0xFFFF, sum = 0
5867 23:11:14.158836 1, 0xFFFF, sum = 0
5868 23:11:14.158921 2, 0xFFFF, sum = 0
5869 23:11:14.162433 3, 0xFFFF, sum = 0
5870 23:11:14.162518 4, 0xFFFF, sum = 0
5871 23:11:14.165845 5, 0xFFFF, sum = 0
5872 23:11:14.165928 6, 0xFFFF, sum = 0
5873 23:11:14.169119 7, 0xFFFF, sum = 0
5874 23:11:14.172771 8, 0xFFFF, sum = 0
5875 23:11:14.172856 9, 0xFFFF, sum = 0
5876 23:11:14.172941 10, 0x0, sum = 1
5877 23:11:14.175701 11, 0x0, sum = 2
5878 23:11:14.175785 12, 0x0, sum = 3
5879 23:11:14.179117 13, 0x0, sum = 4
5880 23:11:14.179201 best_step = 11
5881 23:11:14.179286
5882 23:11:14.179365 ==
5883 23:11:14.182358 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 23:11:14.189162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 23:11:14.189247 ==
5886 23:11:14.189331 RX Vref Scan: 0
5887 23:11:14.189410
5888 23:11:14.192091 RX Vref 0 -> 0, step: 1
5889 23:11:14.192173
5890 23:11:14.195867 RX Delay -45 -> 252, step: 4
5891 23:11:14.199392 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5892 23:11:14.205491 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5893 23:11:14.208924 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5894 23:11:14.212348 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5895 23:11:14.215828 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5896 23:11:14.218728 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5897 23:11:14.222004 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5898 23:11:14.228755 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5899 23:11:14.232246 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5900 23:11:14.235645 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5901 23:11:14.238739 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5902 23:11:14.242439 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5903 23:11:14.248730 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5904 23:11:14.252216 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5905 23:11:14.255464 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5906 23:11:14.258424 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5907 23:11:14.258513 ==
5908 23:11:14.261704 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 23:11:14.269040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 23:11:14.269129 ==
5911 23:11:14.269214 DQS Delay:
5912 23:11:14.271914 DQS0 = 0, DQS1 = 0
5913 23:11:14.271997 DQM Delay:
5914 23:11:14.272082 DQM0 = 104, DQM1 = 99
5915 23:11:14.275547 DQ Delay:
5916 23:11:14.278240 DQ0 =108, DQ1 =102, DQ2 =94, DQ3 =100
5917 23:11:14.281787 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5918 23:11:14.285223 DQ8 =92, DQ9 =88, DQ10 =102, DQ11 =94
5919 23:11:14.288570 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5920 23:11:14.288653
5921 23:11:14.288737
5922 23:11:14.298107 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5923 23:11:14.298198 CH1 RK1: MR19=504, MR18=2BFE
5924 23:11:14.305027 CH1_RK1: MR19=0x504, MR18=0x2BFE, DQSOSC=408, MR23=63, INC=65, DEC=43
5925 23:11:14.308280 [RxdqsGatingPostProcess] freq 933
5926 23:11:14.315018 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5927 23:11:14.318563 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 23:11:14.321350 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 23:11:14.324868 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 23:11:14.327844 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 23:11:14.327926 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 23:11:14.331336 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 23:11:14.335116 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 23:11:14.338220 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 23:11:14.341448 Pre-setting of DQS Precalculation
5936 23:11:14.348466 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5937 23:11:14.354978 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5938 23:11:14.361573 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5939 23:11:14.361699
5940 23:11:14.361765
5941 23:11:14.364481 [Calibration Summary] 1866 Mbps
5942 23:11:14.364562 CH 0, Rank 0
5943 23:11:14.367956 SW Impedance : PASS
5944 23:11:14.371460 DUTY Scan : NO K
5945 23:11:14.371562 ZQ Calibration : PASS
5946 23:11:14.374538 Jitter Meter : NO K
5947 23:11:14.377980 CBT Training : PASS
5948 23:11:14.378062 Write leveling : PASS
5949 23:11:14.381167 RX DQS gating : PASS
5950 23:11:14.384580 RX DQ/DQS(RDDQC) : PASS
5951 23:11:14.384667 TX DQ/DQS : PASS
5952 23:11:14.387872 RX DATLAT : PASS
5953 23:11:14.390930 RX DQ/DQS(Engine): PASS
5954 23:11:14.391009 TX OE : NO K
5955 23:11:14.394387 All Pass.
5956 23:11:14.394474
5957 23:11:14.394572 CH 0, Rank 1
5958 23:11:14.398153 SW Impedance : PASS
5959 23:11:14.398237 DUTY Scan : NO K
5960 23:11:14.401211 ZQ Calibration : PASS
5961 23:11:14.401364 Jitter Meter : NO K
5962 23:11:14.404382 CBT Training : PASS
5963 23:11:14.407791 Write leveling : PASS
5964 23:11:14.407872 RX DQS gating : PASS
5965 23:11:14.411350 RX DQ/DQS(RDDQC) : PASS
5966 23:11:14.414301 TX DQ/DQS : PASS
5967 23:11:14.414383 RX DATLAT : PASS
5968 23:11:14.417898 RX DQ/DQS(Engine): PASS
5969 23:11:14.421424 TX OE : NO K
5970 23:11:14.421506 All Pass.
5971 23:11:14.421569
5972 23:11:14.421674 CH 1, Rank 0
5973 23:11:14.424456 SW Impedance : PASS
5974 23:11:14.427501 DUTY Scan : NO K
5975 23:11:14.427581 ZQ Calibration : PASS
5976 23:11:14.431133 Jitter Meter : NO K
5977 23:11:14.434643 CBT Training : PASS
5978 23:11:14.434724 Write leveling : PASS
5979 23:11:14.437534 RX DQS gating : PASS
5980 23:11:14.441421 RX DQ/DQS(RDDQC) : PASS
5981 23:11:14.441501 TX DQ/DQS : PASS
5982 23:11:14.444507 RX DATLAT : PASS
5983 23:11:14.447672 RX DQ/DQS(Engine): PASS
5984 23:11:14.447753 TX OE : NO K
5985 23:11:14.447817 All Pass.
5986 23:11:14.451187
5987 23:11:14.451267 CH 1, Rank 1
5988 23:11:14.454645 SW Impedance : PASS
5989 23:11:14.454726 DUTY Scan : NO K
5990 23:11:14.457658 ZQ Calibration : PASS
5991 23:11:14.457739 Jitter Meter : NO K
5992 23:11:14.460881 CBT Training : PASS
5993 23:11:14.464185 Write leveling : PASS
5994 23:11:14.464266 RX DQS gating : PASS
5995 23:11:14.467625 RX DQ/DQS(RDDQC) : PASS
5996 23:11:14.470970 TX DQ/DQS : PASS
5997 23:11:14.471053 RX DATLAT : PASS
5998 23:11:14.474275 RX DQ/DQS(Engine): PASS
5999 23:11:14.477543 TX OE : NO K
6000 23:11:14.477673 All Pass.
6001 23:11:14.477740
6002 23:11:14.481023 DramC Write-DBI off
6003 23:11:14.481104 PER_BANK_REFRESH: Hybrid Mode
6004 23:11:14.484173 TX_TRACKING: ON
6005 23:11:14.490873 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6006 23:11:14.497800 [FAST_K] Save calibration result to emmc
6007 23:11:14.501104 dramc_set_vcore_voltage set vcore to 650000
6008 23:11:14.501187 Read voltage for 400, 6
6009 23:11:14.504290 Vio18 = 0
6010 23:11:14.504370 Vcore = 650000
6011 23:11:14.504434 Vdram = 0
6012 23:11:14.507184 Vddq = 0
6013 23:11:14.507265 Vmddr = 0
6014 23:11:14.510721 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6015 23:11:14.517774 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6016 23:11:14.520560 MEM_TYPE=3, freq_sel=20
6017 23:11:14.523725 sv_algorithm_assistance_LP4_800
6018 23:11:14.527507 ============ PULL DRAM RESETB DOWN ============
6019 23:11:14.530722 ========== PULL DRAM RESETB DOWN end =========
6020 23:11:14.537047 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6021 23:11:14.540580 ===================================
6022 23:11:14.540662 LPDDR4 DRAM CONFIGURATION
6023 23:11:14.543722 ===================================
6024 23:11:14.547204 EX_ROW_EN[0] = 0x0
6025 23:11:14.547285 EX_ROW_EN[1] = 0x0
6026 23:11:14.550495 LP4Y_EN = 0x0
6027 23:11:14.550578 WORK_FSP = 0x0
6028 23:11:14.553769 WL = 0x2
6029 23:11:14.553850 RL = 0x2
6030 23:11:14.557255 BL = 0x2
6031 23:11:14.557336 RPST = 0x0
6032 23:11:14.560827 RD_PRE = 0x0
6033 23:11:14.563493 WR_PRE = 0x1
6034 23:11:14.563604 WR_PST = 0x0
6035 23:11:14.567285 DBI_WR = 0x0
6036 23:11:14.567367 DBI_RD = 0x0
6037 23:11:14.570495 OTF = 0x1
6038 23:11:14.573638 ===================================
6039 23:11:14.577204 ===================================
6040 23:11:14.577285 ANA top config
6041 23:11:14.580330 ===================================
6042 23:11:14.583371 DLL_ASYNC_EN = 0
6043 23:11:14.587449 ALL_SLAVE_EN = 1
6044 23:11:14.587532 NEW_RANK_MODE = 1
6045 23:11:14.590147 DLL_IDLE_MODE = 1
6046 23:11:14.593639 LP45_APHY_COMB_EN = 1
6047 23:11:14.596696 TX_ODT_DIS = 1
6048 23:11:14.596778 NEW_8X_MODE = 1
6049 23:11:14.601129 ===================================
6050 23:11:14.603869 ===================================
6051 23:11:14.607149 data_rate = 800
6052 23:11:14.610323 CKR = 1
6053 23:11:14.613844 DQ_P2S_RATIO = 4
6054 23:11:14.616898 ===================================
6055 23:11:14.620345 CA_P2S_RATIO = 4
6056 23:11:14.623678 DQ_CA_OPEN = 0
6057 23:11:14.623760 DQ_SEMI_OPEN = 1
6058 23:11:14.627004 CA_SEMI_OPEN = 1
6059 23:11:14.630239 CA_FULL_RATE = 0
6060 23:11:14.633506 DQ_CKDIV4_EN = 0
6061 23:11:14.637306 CA_CKDIV4_EN = 1
6062 23:11:14.640478 CA_PREDIV_EN = 0
6063 23:11:14.640560 PH8_DLY = 0
6064 23:11:14.643980 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6065 23:11:14.646855 DQ_AAMCK_DIV = 0
6066 23:11:14.650377 CA_AAMCK_DIV = 0
6067 23:11:14.653101 CA_ADMCK_DIV = 4
6068 23:11:14.656767 DQ_TRACK_CA_EN = 0
6069 23:11:14.660288 CA_PICK = 800
6070 23:11:14.660370 CA_MCKIO = 400
6071 23:11:14.663141 MCKIO_SEMI = 400
6072 23:11:14.666864 PLL_FREQ = 3016
6073 23:11:14.670368 DQ_UI_PI_RATIO = 32
6074 23:11:14.673335 CA_UI_PI_RATIO = 32
6075 23:11:14.676429 ===================================
6076 23:11:14.680272 ===================================
6077 23:11:14.683292 memory_type:LPDDR4
6078 23:11:14.683376 GP_NUM : 10
6079 23:11:14.686773 SRAM_EN : 1
6080 23:11:14.686856 MD32_EN : 0
6081 23:11:14.689895 ===================================
6082 23:11:14.693477 [ANA_INIT] >>>>>>>>>>>>>>
6083 23:11:14.696813 <<<<<< [CONFIGURE PHASE]: ANA_TX
6084 23:11:14.699710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6085 23:11:14.703421 ===================================
6086 23:11:14.706342 data_rate = 800,PCW = 0X7400
6087 23:11:14.709526 ===================================
6088 23:11:14.713012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6089 23:11:14.719668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6090 23:11:14.729342 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 23:11:14.732731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6092 23:11:14.736075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6093 23:11:14.739571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6094 23:11:14.742884 [ANA_INIT] flow start
6095 23:11:14.746162 [ANA_INIT] PLL >>>>>>>>
6096 23:11:14.746244 [ANA_INIT] PLL <<<<<<<<
6097 23:11:14.749471 [ANA_INIT] MIDPI >>>>>>>>
6098 23:11:14.752576 [ANA_INIT] MIDPI <<<<<<<<
6099 23:11:14.756064 [ANA_INIT] DLL >>>>>>>>
6100 23:11:14.756148 [ANA_INIT] flow end
6101 23:11:14.759453 ============ LP4 DIFF to SE enter ============
6102 23:11:14.766022 ============ LP4 DIFF to SE exit ============
6103 23:11:14.766113 [ANA_INIT] <<<<<<<<<<<<<
6104 23:11:14.769459 [Flow] Enable top DCM control >>>>>
6105 23:11:14.772948 [Flow] Enable top DCM control <<<<<
6106 23:11:14.775779 Enable DLL master slave shuffle
6107 23:11:14.782259 ==============================================================
6108 23:11:14.782346 Gating Mode config
6109 23:11:14.789297 ==============================================================
6110 23:11:14.792371 Config description:
6111 23:11:14.802711 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6112 23:11:14.809499 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6113 23:11:14.812328 SELPH_MODE 0: By rank 1: By Phase
6114 23:11:14.818967 ==============================================================
6115 23:11:14.822483 GAT_TRACK_EN = 0
6116 23:11:14.826107 RX_GATING_MODE = 2
6117 23:11:14.826189 RX_GATING_TRACK_MODE = 2
6118 23:11:14.828943 SELPH_MODE = 1
6119 23:11:14.831978 PICG_EARLY_EN = 1
6120 23:11:14.835508 VALID_LAT_VALUE = 1
6121 23:11:14.842125 ==============================================================
6122 23:11:14.845339 Enter into Gating configuration >>>>
6123 23:11:14.848678 Exit from Gating configuration <<<<
6124 23:11:14.852057 Enter into DVFS_PRE_config >>>>>
6125 23:11:14.862189 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6126 23:11:14.865380 Exit from DVFS_PRE_config <<<<<
6127 23:11:14.868734 Enter into PICG configuration >>>>
6128 23:11:14.872428 Exit from PICG configuration <<<<
6129 23:11:14.875754 [RX_INPUT] configuration >>>>>
6130 23:11:14.878968 [RX_INPUT] configuration <<<<<
6131 23:11:14.882683 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6132 23:11:14.889044 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6133 23:11:14.895371 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6134 23:11:14.899159 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6135 23:11:14.905635 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6136 23:11:14.912284 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6137 23:11:14.915671 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6138 23:11:14.919416 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6139 23:11:14.925933 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6140 23:11:14.928688 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6141 23:11:14.932262 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6142 23:11:14.938638 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6143 23:11:14.942635 ===================================
6144 23:11:14.942719 LPDDR4 DRAM CONFIGURATION
6145 23:11:14.946114 ===================================
6146 23:11:14.948759 EX_ROW_EN[0] = 0x0
6147 23:11:14.948841 EX_ROW_EN[1] = 0x0
6148 23:11:14.952213 LP4Y_EN = 0x0
6149 23:11:14.955266 WORK_FSP = 0x0
6150 23:11:14.955349 WL = 0x2
6151 23:11:14.958880 RL = 0x2
6152 23:11:14.958962 BL = 0x2
6153 23:11:14.962388 RPST = 0x0
6154 23:11:14.962469 RD_PRE = 0x0
6155 23:11:14.966114 WR_PRE = 0x1
6156 23:11:14.966197 WR_PST = 0x0
6157 23:11:14.968795 DBI_WR = 0x0
6158 23:11:14.968876 DBI_RD = 0x0
6159 23:11:14.972781 OTF = 0x1
6160 23:11:14.975714 ===================================
6161 23:11:14.979297 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6162 23:11:14.982340 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6163 23:11:14.985816 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6164 23:11:14.989016 ===================================
6165 23:11:14.992704 LPDDR4 DRAM CONFIGURATION
6166 23:11:14.995556 ===================================
6167 23:11:14.999344 EX_ROW_EN[0] = 0x10
6168 23:11:14.999426 EX_ROW_EN[1] = 0x0
6169 23:11:15.002060 LP4Y_EN = 0x0
6170 23:11:15.002141 WORK_FSP = 0x0
6171 23:11:15.005376 WL = 0x2
6172 23:11:15.005458 RL = 0x2
6173 23:11:15.008713 BL = 0x2
6174 23:11:15.008793 RPST = 0x0
6175 23:11:15.012595 RD_PRE = 0x0
6176 23:11:15.012675 WR_PRE = 0x1
6177 23:11:15.015694 WR_PST = 0x0
6178 23:11:15.018532 DBI_WR = 0x0
6179 23:11:15.018613 DBI_RD = 0x0
6180 23:11:15.022418 OTF = 0x1
6181 23:11:15.025599 ===================================
6182 23:11:15.028567 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6183 23:11:15.034000 nWR fixed to 30
6184 23:11:15.037874 [ModeRegInit_LP4] CH0 RK0
6185 23:11:15.037957 [ModeRegInit_LP4] CH0 RK1
6186 23:11:15.040791 [ModeRegInit_LP4] CH1 RK0
6187 23:11:15.044495 [ModeRegInit_LP4] CH1 RK1
6188 23:11:15.044576 match AC timing 19
6189 23:11:15.050684 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6190 23:11:15.054541 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6191 23:11:15.057209 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6192 23:11:15.064264 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6193 23:11:15.067396 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6194 23:11:15.067479 ==
6195 23:11:15.070757 Dram Type= 6, Freq= 0, CH_0, rank 0
6196 23:11:15.073890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6197 23:11:15.073972 ==
6198 23:11:15.080662 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6199 23:11:15.087191 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6200 23:11:15.090530 [CA 0] Center 36 (8~64) winsize 57
6201 23:11:15.094020 [CA 1] Center 36 (8~64) winsize 57
6202 23:11:15.094102 [CA 2] Center 36 (8~64) winsize 57
6203 23:11:15.097126 [CA 3] Center 36 (8~64) winsize 57
6204 23:11:15.101132 [CA 4] Center 36 (8~64) winsize 57
6205 23:11:15.103802 [CA 5] Center 36 (8~64) winsize 57
6206 23:11:15.103885
6207 23:11:15.107263 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6208 23:11:15.110903
6209 23:11:15.114154 [CATrainingPosCal] consider 1 rank data
6210 23:11:15.114237 u2DelayCellTimex100 = 270/100 ps
6211 23:11:15.120883 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 23:11:15.123660 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 23:11:15.126998 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 23:11:15.130453 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 23:11:15.133699 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 23:11:15.137068 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 23:11:15.137149
6218 23:11:15.140390 CA PerBit enable=1, Macro0, CA PI delay=36
6219 23:11:15.140472
6220 23:11:15.143646 [CBTSetCACLKResult] CA Dly = 36
6221 23:11:15.147113 CS Dly: 1 (0~32)
6222 23:11:15.147193 ==
6223 23:11:15.150078 Dram Type= 6, Freq= 0, CH_0, rank 1
6224 23:11:15.153565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 23:11:15.153687 ==
6226 23:11:15.160074 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 23:11:15.163503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6228 23:11:15.166744 [CA 0] Center 36 (8~64) winsize 57
6229 23:11:15.170049 [CA 1] Center 36 (8~64) winsize 57
6230 23:11:15.173378 [CA 2] Center 36 (8~64) winsize 57
6231 23:11:15.176642 [CA 3] Center 36 (8~64) winsize 57
6232 23:11:15.180018 [CA 4] Center 36 (8~64) winsize 57
6233 23:11:15.183414 [CA 5] Center 36 (8~64) winsize 57
6234 23:11:15.183528
6235 23:11:15.186662 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6236 23:11:15.186745
6237 23:11:15.190312 [CATrainingPosCal] consider 2 rank data
6238 23:11:15.193915 u2DelayCellTimex100 = 270/100 ps
6239 23:11:15.196805 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 23:11:15.200235 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 23:11:15.206638 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 23:11:15.209905 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 23:11:15.213187 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 23:11:15.216687 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 23:11:15.216768
6246 23:11:15.220227 CA PerBit enable=1, Macro0, CA PI delay=36
6247 23:11:15.220309
6248 23:11:15.222906 [CBTSetCACLKResult] CA Dly = 36
6249 23:11:15.222988 CS Dly: 1 (0~32)
6250 23:11:15.223052
6251 23:11:15.226768 ----->DramcWriteLeveling(PI) begin...
6252 23:11:15.230372 ==
6253 23:11:15.233024 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 23:11:15.236494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 23:11:15.236576 ==
6256 23:11:15.240158 Write leveling (Byte 0): 40 => 8
6257 23:11:15.243462 Write leveling (Byte 1): 40 => 8
6258 23:11:15.243544 DramcWriteLeveling(PI) end<-----
6259 23:11:15.246668
6260 23:11:15.246749 ==
6261 23:11:15.249471 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 23:11:15.253548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 23:11:15.253679 ==
6264 23:11:15.256245 [Gating] SW mode calibration
6265 23:11:15.263351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6266 23:11:15.266304 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6267 23:11:15.273104 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 23:11:15.276258 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 23:11:15.279743 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 23:11:15.286817 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 23:11:15.289554 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 23:11:15.292884 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 23:11:15.299701 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 23:11:15.303337 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 23:11:15.306549 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 23:11:15.309760 Total UI for P1: 0, mck2ui 16
6277 23:11:15.312904 best dqsien dly found for B0: ( 0, 14, 24)
6278 23:11:15.316644 Total UI for P1: 0, mck2ui 16
6279 23:11:15.319516 best dqsien dly found for B1: ( 0, 14, 24)
6280 23:11:15.322873 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6281 23:11:15.326412 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6282 23:11:15.326505
6283 23:11:15.333157 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6284 23:11:15.336056 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 23:11:15.339824 [Gating] SW calibration Done
6286 23:11:15.339906 ==
6287 23:11:15.342516 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 23:11:15.346316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 23:11:15.346399 ==
6290 23:11:15.346463 RX Vref Scan: 0
6291 23:11:15.346524
6292 23:11:15.349463 RX Vref 0 -> 0, step: 1
6293 23:11:15.349545
6294 23:11:15.353163 RX Delay -410 -> 252, step: 16
6295 23:11:15.356205 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6296 23:11:15.363083 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6297 23:11:15.365818 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6298 23:11:15.369482 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6299 23:11:15.372848 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6300 23:11:15.379109 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6301 23:11:15.382556 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6302 23:11:15.386150 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6303 23:11:15.389222 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6304 23:11:15.392717 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6305 23:11:15.399126 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6306 23:11:15.402311 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6307 23:11:15.405782 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6308 23:11:15.412530 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6309 23:11:15.416256 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6310 23:11:15.418836 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6311 23:11:15.418988 ==
6312 23:11:15.422504 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 23:11:15.425641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 23:11:15.428638 ==
6315 23:11:15.428718 DQS Delay:
6316 23:11:15.428782 DQS0 = 27, DQS1 = 35
6317 23:11:15.432320 DQM Delay:
6318 23:11:15.432402 DQM0 = 10, DQM1 = 12
6319 23:11:15.435370 DQ Delay:
6320 23:11:15.435452 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6321 23:11:15.438830 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6322 23:11:15.442448 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6323 23:11:15.445451 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6324 23:11:15.445532
6325 23:11:15.445605
6326 23:11:15.449032 ==
6327 23:11:15.451918 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 23:11:15.455323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 23:11:15.455404 ==
6330 23:11:15.455477
6331 23:11:15.455608
6332 23:11:15.458608 TX Vref Scan disable
6333 23:11:15.458715 == TX Byte 0 ==
6334 23:11:15.462178 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 23:11:15.468235 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 23:11:15.468317 == TX Byte 1 ==
6337 23:11:15.471976 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 23:11:15.478357 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 23:11:15.478439 ==
6340 23:11:15.481586 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 23:11:15.485178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 23:11:15.485265 ==
6343 23:11:15.485330
6344 23:11:15.485389
6345 23:11:15.488708 TX Vref Scan disable
6346 23:11:15.488788 == TX Byte 0 ==
6347 23:11:15.491904 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 23:11:15.498067 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 23:11:15.498152 == TX Byte 1 ==
6350 23:11:15.501581 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 23:11:15.508540 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 23:11:15.508622
6353 23:11:15.508694 [DATLAT]
6354 23:11:15.508755 Freq=400, CH0 RK0
6355 23:11:15.508813
6356 23:11:15.511727 DATLAT Default: 0xf
6357 23:11:15.514682 0, 0xFFFF, sum = 0
6358 23:11:15.514797 1, 0xFFFF, sum = 0
6359 23:11:15.518115 2, 0xFFFF, sum = 0
6360 23:11:15.518201 3, 0xFFFF, sum = 0
6361 23:11:15.521468 4, 0xFFFF, sum = 0
6362 23:11:15.521549 5, 0xFFFF, sum = 0
6363 23:11:15.524769 6, 0xFFFF, sum = 0
6364 23:11:15.524851 7, 0xFFFF, sum = 0
6365 23:11:15.528421 8, 0xFFFF, sum = 0
6366 23:11:15.528527 9, 0xFFFF, sum = 0
6367 23:11:15.531375 10, 0xFFFF, sum = 0
6368 23:11:15.531456 11, 0xFFFF, sum = 0
6369 23:11:15.534895 12, 0xFFFF, sum = 0
6370 23:11:15.534977 13, 0x0, sum = 1
6371 23:11:15.538148 14, 0x0, sum = 2
6372 23:11:15.538229 15, 0x0, sum = 3
6373 23:11:15.541526 16, 0x0, sum = 4
6374 23:11:15.541655 best_step = 14
6375 23:11:15.541719
6376 23:11:15.541779 ==
6377 23:11:15.544890 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 23:11:15.548129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 23:11:15.551264 ==
6380 23:11:15.551349 RX Vref Scan: 1
6381 23:11:15.551416
6382 23:11:15.555072 RX Vref 0 -> 0, step: 1
6383 23:11:15.555154
6384 23:11:15.558446 RX Delay -311 -> 252, step: 8
6385 23:11:15.558527
6386 23:11:15.561295 Set Vref, RX VrefLevel [Byte0]: 54
6387 23:11:15.564589 [Byte1]: 55
6388 23:11:15.564670
6389 23:11:15.568120 Final RX Vref Byte 0 = 54 to rank0
6390 23:11:15.571450 Final RX Vref Byte 1 = 55 to rank0
6391 23:11:15.574698 Final RX Vref Byte 0 = 54 to rank1
6392 23:11:15.578000 Final RX Vref Byte 1 = 55 to rank1==
6393 23:11:15.581066 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 23:11:15.584564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 23:11:15.584652 ==
6396 23:11:15.587973 DQS Delay:
6397 23:11:15.588054 DQS0 = 28, DQS1 = 36
6398 23:11:15.590920 DQM Delay:
6399 23:11:15.591001 DQM0 = 12, DQM1 = 12
6400 23:11:15.591065 DQ Delay:
6401 23:11:15.594569 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6402 23:11:15.597991 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6403 23:11:15.601086 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6404 23:11:15.604467 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6405 23:11:15.604548
6406 23:11:15.604612
6407 23:11:15.614755 [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6408 23:11:15.617598 CH0 RK0: MR19=C0C, MR18=C8B5
6409 23:11:15.621194 CH0_RK0: MR19=0xC0C, MR18=0xC8B5, DQSOSC=385, MR23=63, INC=398, DEC=265
6410 23:11:15.624393 ==
6411 23:11:15.628019 Dram Type= 6, Freq= 0, CH_0, rank 1
6412 23:11:15.631085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 23:11:15.631167 ==
6414 23:11:15.634411 [Gating] SW mode calibration
6415 23:11:15.640881 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6416 23:11:15.644308 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6417 23:11:15.650794 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6418 23:11:15.654206 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 23:11:15.657958 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 23:11:15.664435 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 23:11:15.667548 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 23:11:15.670953 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 23:11:15.677562 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 23:11:15.680524 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 23:11:15.684236 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 23:11:15.687388 Total UI for P1: 0, mck2ui 16
6427 23:11:15.690955 best dqsien dly found for B0: ( 0, 14, 24)
6428 23:11:15.694240 Total UI for P1: 0, mck2ui 16
6429 23:11:15.697383 best dqsien dly found for B1: ( 0, 14, 24)
6430 23:11:15.700744 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6431 23:11:15.704243 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6432 23:11:15.704353
6433 23:11:15.710503 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6434 23:11:15.714252 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 23:11:15.714335 [Gating] SW calibration Done
6436 23:11:15.717119 ==
6437 23:11:15.720664 Dram Type= 6, Freq= 0, CH_0, rank 1
6438 23:11:15.724470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 23:11:15.724553 ==
6440 23:11:15.724618 RX Vref Scan: 0
6441 23:11:15.724679
6442 23:11:15.726956 RX Vref 0 -> 0, step: 1
6443 23:11:15.727037
6444 23:11:15.730336 RX Delay -410 -> 252, step: 16
6445 23:11:15.734027 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6446 23:11:15.737696 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6447 23:11:15.743904 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6448 23:11:15.747006 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6449 23:11:15.750265 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6450 23:11:15.753722 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6451 23:11:15.760214 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6452 23:11:15.763649 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6453 23:11:15.767060 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6454 23:11:15.770291 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6455 23:11:15.776902 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6456 23:11:15.780068 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6457 23:11:15.783509 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6458 23:11:15.790497 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6459 23:11:15.793547 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6460 23:11:15.796672 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6461 23:11:15.796780 ==
6462 23:11:15.800018 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 23:11:15.803316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 23:11:15.803399 ==
6465 23:11:15.806838 DQS Delay:
6466 23:11:15.806920 DQS0 = 19, DQS1 = 35
6467 23:11:15.810079 DQM Delay:
6468 23:11:15.810160 DQM0 = 5, DQM1 = 10
6469 23:11:15.813505 DQ Delay:
6470 23:11:15.813596 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6471 23:11:15.816944 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6472 23:11:15.820091 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6473 23:11:15.823318 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6474 23:11:15.823399
6475 23:11:15.823470
6476 23:11:15.823532 ==
6477 23:11:15.826739 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 23:11:15.833013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 23:11:15.833121 ==
6480 23:11:15.833209
6481 23:11:15.833274
6482 23:11:15.833332 TX Vref Scan disable
6483 23:11:15.836536 == TX Byte 0 ==
6484 23:11:15.839998 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6485 23:11:15.843158 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6486 23:11:15.846490 == TX Byte 1 ==
6487 23:11:15.849810 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6488 23:11:15.852993 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6489 23:11:15.853075 ==
6490 23:11:15.856609 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 23:11:15.863003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 23:11:15.863087 ==
6493 23:11:15.863152
6494 23:11:15.863211
6495 23:11:15.863269 TX Vref Scan disable
6496 23:11:15.866588 == TX Byte 0 ==
6497 23:11:15.870084 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6498 23:11:15.873440 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6499 23:11:15.876791 == TX Byte 1 ==
6500 23:11:15.880078 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6501 23:11:15.882999 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6502 23:11:15.883081
6503 23:11:15.886366 [DATLAT]
6504 23:11:15.886478 Freq=400, CH0 RK1
6505 23:11:15.886561
6506 23:11:15.889733 DATLAT Default: 0xe
6507 23:11:15.889814 0, 0xFFFF, sum = 0
6508 23:11:15.892984 1, 0xFFFF, sum = 0
6509 23:11:15.893072 2, 0xFFFF, sum = 0
6510 23:11:15.896755 3, 0xFFFF, sum = 0
6511 23:11:15.896865 4, 0xFFFF, sum = 0
6512 23:11:15.899907 5, 0xFFFF, sum = 0
6513 23:11:15.900017 6, 0xFFFF, sum = 0
6514 23:11:15.902626 7, 0xFFFF, sum = 0
6515 23:11:15.902740 8, 0xFFFF, sum = 0
6516 23:11:15.906424 9, 0xFFFF, sum = 0
6517 23:11:15.909581 10, 0xFFFF, sum = 0
6518 23:11:15.909677 11, 0xFFFF, sum = 0
6519 23:11:15.913092 12, 0xFFFF, sum = 0
6520 23:11:15.913169 13, 0x0, sum = 1
6521 23:11:15.915924 14, 0x0, sum = 2
6522 23:11:15.915999 15, 0x0, sum = 3
6523 23:11:15.916062 16, 0x0, sum = 4
6524 23:11:15.919504 best_step = 14
6525 23:11:15.919580
6526 23:11:15.919647 ==
6527 23:11:15.923218 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 23:11:15.926051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 23:11:15.926125 ==
6530 23:11:15.929372 RX Vref Scan: 0
6531 23:11:15.929448
6532 23:11:15.929510 RX Vref 0 -> 0, step: 1
6533 23:11:15.932849
6534 23:11:15.932926 RX Delay -311 -> 252, step: 8
6535 23:11:15.941070 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6536 23:11:15.944902 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6537 23:11:15.947931 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6538 23:11:15.951272 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6539 23:11:15.957906 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6540 23:11:15.961217 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6541 23:11:15.964467 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6542 23:11:15.967590 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6543 23:11:15.974427 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6544 23:11:15.977708 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6545 23:11:15.980773 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6546 23:11:15.984130 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6547 23:11:15.990960 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6548 23:11:15.994420 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6549 23:11:15.997404 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6550 23:11:16.004146 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6551 23:11:16.004258 ==
6552 23:11:16.007425 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 23:11:16.011054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 23:11:16.011173 ==
6555 23:11:16.011273 DQS Delay:
6556 23:11:16.014474 DQS0 = 24, DQS1 = 32
6557 23:11:16.014553 DQM Delay:
6558 23:11:16.017464 DQM0 = 8, DQM1 = 9
6559 23:11:16.017563 DQ Delay:
6560 23:11:16.020678 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6561 23:11:16.024273 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6562 23:11:16.027970 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6563 23:11:16.031126 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =16
6564 23:11:16.031203
6565 23:11:16.031266
6566 23:11:16.037800 [DQSOSCAuto] RK1, (LSB)MR18= 0xb555, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6567 23:11:16.040844 CH0 RK1: MR19=C0C, MR18=B555
6568 23:11:16.047654 CH0_RK1: MR19=0xC0C, MR18=0xB555, DQSOSC=387, MR23=63, INC=394, DEC=262
6569 23:11:16.051449 [RxdqsGatingPostProcess] freq 400
6570 23:11:16.054022 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6571 23:11:16.057532 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 23:11:16.060723 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 23:11:16.064264 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 23:11:16.067375 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 23:11:16.070864 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 23:11:16.074316 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 23:11:16.077539 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 23:11:16.081005 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 23:11:16.084125 Pre-setting of DQS Precalculation
6580 23:11:16.087298 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6581 23:11:16.087381 ==
6582 23:11:16.090993 Dram Type= 6, Freq= 0, CH_1, rank 0
6583 23:11:16.097478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 23:11:16.097594 ==
6585 23:11:16.100497 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6586 23:11:16.107644 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6587 23:11:16.110992 [CA 0] Center 36 (8~64) winsize 57
6588 23:11:16.114138 [CA 1] Center 36 (8~64) winsize 57
6589 23:11:16.117270 [CA 2] Center 36 (8~64) winsize 57
6590 23:11:16.120959 [CA 3] Center 36 (8~64) winsize 57
6591 23:11:16.123873 [CA 4] Center 36 (8~64) winsize 57
6592 23:11:16.127172 [CA 5] Center 36 (8~64) winsize 57
6593 23:11:16.127253
6594 23:11:16.130857 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6595 23:11:16.130938
6596 23:11:16.134188 [CATrainingPosCal] consider 1 rank data
6597 23:11:16.137035 u2DelayCellTimex100 = 270/100 ps
6598 23:11:16.140824 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 23:11:16.144281 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 23:11:16.147267 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 23:11:16.150437 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 23:11:16.153792 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 23:11:16.160717 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 23:11:16.160798
6605 23:11:16.163654 CA PerBit enable=1, Macro0, CA PI delay=36
6606 23:11:16.163730
6607 23:11:16.167059 [CBTSetCACLKResult] CA Dly = 36
6608 23:11:16.167158 CS Dly: 1 (0~32)
6609 23:11:16.167251 ==
6610 23:11:16.170596 Dram Type= 6, Freq= 0, CH_1, rank 1
6611 23:11:16.174117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 23:11:16.176952 ==
6613 23:11:16.180295 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 23:11:16.187348 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6615 23:11:16.190048 [CA 0] Center 36 (8~64) winsize 57
6616 23:11:16.193360 [CA 1] Center 36 (8~64) winsize 57
6617 23:11:16.196912 [CA 2] Center 36 (8~64) winsize 57
6618 23:11:16.199946 [CA 3] Center 36 (8~64) winsize 57
6619 23:11:16.203603 [CA 4] Center 36 (8~64) winsize 57
6620 23:11:16.206763 [CA 5] Center 36 (8~64) winsize 57
6621 23:11:16.206844
6622 23:11:16.209935 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6623 23:11:16.210070
6624 23:11:16.213548 [CATrainingPosCal] consider 2 rank data
6625 23:11:16.216439 u2DelayCellTimex100 = 270/100 ps
6626 23:11:16.220056 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 23:11:16.223269 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 23:11:16.226616 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 23:11:16.229778 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 23:11:16.233471 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 23:11:16.236666 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 23:11:16.236748
6633 23:11:16.243098 CA PerBit enable=1, Macro0, CA PI delay=36
6634 23:11:16.243180
6635 23:11:16.243244 [CBTSetCACLKResult] CA Dly = 36
6636 23:11:16.246569 CS Dly: 1 (0~32)
6637 23:11:16.246649
6638 23:11:16.249891 ----->DramcWriteLeveling(PI) begin...
6639 23:11:16.249974 ==
6640 23:11:16.253349 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 23:11:16.256672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 23:11:16.256755 ==
6643 23:11:16.260073 Write leveling (Byte 0): 40 => 8
6644 23:11:16.263295 Write leveling (Byte 1): 40 => 8
6645 23:11:16.266823 DramcWriteLeveling(PI) end<-----
6646 23:11:16.266904
6647 23:11:16.266968 ==
6648 23:11:16.269723 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 23:11:16.272915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 23:11:16.272996 ==
6651 23:11:16.276557 [Gating] SW mode calibration
6652 23:11:16.283475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6653 23:11:16.289749 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6654 23:11:16.293271 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6655 23:11:16.300084 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 23:11:16.302913 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 23:11:16.306524 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 23:11:16.312841 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 23:11:16.316386 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 23:11:16.319797 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 23:11:16.322915 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 23:11:16.329429 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 23:11:16.332958 Total UI for P1: 0, mck2ui 16
6664 23:11:16.336256 best dqsien dly found for B0: ( 0, 14, 24)
6665 23:11:16.339810 Total UI for P1: 0, mck2ui 16
6666 23:11:16.342927 best dqsien dly found for B1: ( 0, 14, 24)
6667 23:11:16.346105 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6668 23:11:16.349904 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6669 23:11:16.349986
6670 23:11:16.352621 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6671 23:11:16.356421 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 23:11:16.359316 [Gating] SW calibration Done
6673 23:11:16.359398 ==
6674 23:11:16.362904 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 23:11:16.366275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 23:11:16.366359 ==
6677 23:11:16.369783 RX Vref Scan: 0
6678 23:11:16.369865
6679 23:11:16.372525 RX Vref 0 -> 0, step: 1
6680 23:11:16.372618
6681 23:11:16.372684 RX Delay -410 -> 252, step: 16
6682 23:11:16.379903 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6683 23:11:16.383172 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6684 23:11:16.386208 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6685 23:11:16.389311 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6686 23:11:16.396104 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6687 23:11:16.399540 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6688 23:11:16.403001 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6689 23:11:16.406202 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6690 23:11:16.412915 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6691 23:11:16.416601 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6692 23:11:16.419874 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6693 23:11:16.422608 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6694 23:11:16.429314 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6695 23:11:16.433010 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6696 23:11:16.436105 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6697 23:11:16.439683 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6698 23:11:16.442733 ==
6699 23:11:16.446695 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 23:11:16.449864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 23:11:16.449955 ==
6702 23:11:16.450023 DQS Delay:
6703 23:11:16.452706 DQS0 = 35, DQS1 = 35
6704 23:11:16.452788 DQM Delay:
6705 23:11:16.456262 DQM0 = 17, DQM1 = 13
6706 23:11:16.456346 DQ Delay:
6707 23:11:16.459514 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6708 23:11:16.463185 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6709 23:11:16.466428 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6710 23:11:16.469276 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6711 23:11:16.469358
6712 23:11:16.469440
6713 23:11:16.469502 ==
6714 23:11:16.472626 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 23:11:16.475909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 23:11:16.475998 ==
6717 23:11:16.476067
6718 23:11:16.476128
6719 23:11:16.479317 TX Vref Scan disable
6720 23:11:16.479424 == TX Byte 0 ==
6721 23:11:16.486229 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 23:11:16.489558 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 23:11:16.489680 == TX Byte 1 ==
6724 23:11:16.495981 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 23:11:16.499155 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 23:11:16.499236 ==
6727 23:11:16.502651 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 23:11:16.506298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 23:11:16.506379 ==
6730 23:11:16.506443
6731 23:11:16.506502
6732 23:11:16.509244 TX Vref Scan disable
6733 23:11:16.509327 == TX Byte 0 ==
6734 23:11:16.516020 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 23:11:16.519391 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 23:11:16.519472 == TX Byte 1 ==
6737 23:11:16.526008 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 23:11:16.528928 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 23:11:16.529010
6740 23:11:16.529074 [DATLAT]
6741 23:11:16.532272 Freq=400, CH1 RK0
6742 23:11:16.532352
6743 23:11:16.532416 DATLAT Default: 0xf
6744 23:11:16.535973 0, 0xFFFF, sum = 0
6745 23:11:16.536054 1, 0xFFFF, sum = 0
6746 23:11:16.538948 2, 0xFFFF, sum = 0
6747 23:11:16.539030 3, 0xFFFF, sum = 0
6748 23:11:16.542606 4, 0xFFFF, sum = 0
6749 23:11:16.542712 5, 0xFFFF, sum = 0
6750 23:11:16.545467 6, 0xFFFF, sum = 0
6751 23:11:16.545581 7, 0xFFFF, sum = 0
6752 23:11:16.549306 8, 0xFFFF, sum = 0
6753 23:11:16.552198 9, 0xFFFF, sum = 0
6754 23:11:16.552321 10, 0xFFFF, sum = 0
6755 23:11:16.555632 11, 0xFFFF, sum = 0
6756 23:11:16.555716 12, 0xFFFF, sum = 0
6757 23:11:16.559246 13, 0x0, sum = 1
6758 23:11:16.559358 14, 0x0, sum = 2
6759 23:11:16.562285 15, 0x0, sum = 3
6760 23:11:16.562367 16, 0x0, sum = 4
6761 23:11:16.562433 best_step = 14
6762 23:11:16.566054
6763 23:11:16.566135 ==
6764 23:11:16.569159 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 23:11:16.572251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 23:11:16.572332 ==
6767 23:11:16.572395 RX Vref Scan: 1
6768 23:11:16.572455
6769 23:11:16.575598 RX Vref 0 -> 0, step: 1
6770 23:11:16.575679
6771 23:11:16.579323 RX Delay -311 -> 252, step: 8
6772 23:11:16.579403
6773 23:11:16.582385 Set Vref, RX VrefLevel [Byte0]: 54
6774 23:11:16.585559 [Byte1]: 54
6775 23:11:16.589165
6776 23:11:16.589246 Final RX Vref Byte 0 = 54 to rank0
6777 23:11:16.592303 Final RX Vref Byte 1 = 54 to rank0
6778 23:11:16.596004 Final RX Vref Byte 0 = 54 to rank1
6779 23:11:16.599113 Final RX Vref Byte 1 = 54 to rank1==
6780 23:11:16.602800 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 23:11:16.609297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 23:11:16.609408 ==
6783 23:11:16.609501 DQS Delay:
6784 23:11:16.612529 DQS0 = 28, DQS1 = 32
6785 23:11:16.612609 DQM Delay:
6786 23:11:16.612673 DQM0 = 10, DQM1 = 10
6787 23:11:16.616029 DQ Delay:
6788 23:11:16.618838 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =12
6789 23:11:16.622210 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6790 23:11:16.622289 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6791 23:11:16.626115 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6792 23:11:16.629144
6793 23:11:16.629232
6794 23:11:16.635441 [DQSOSCAuto] RK0, (LSB)MR18= 0x90c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6795 23:11:16.638820 CH1 RK0: MR19=C0C, MR18=90C9
6796 23:11:16.645560 CH1_RK0: MR19=0xC0C, MR18=0x90C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6797 23:11:16.645683 ==
6798 23:11:16.648869 Dram Type= 6, Freq= 0, CH_1, rank 1
6799 23:11:16.652226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 23:11:16.652333 ==
6801 23:11:16.655347 [Gating] SW mode calibration
6802 23:11:16.661900 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6803 23:11:16.668987 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6804 23:11:16.672115 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6805 23:11:16.675250 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 23:11:16.681890 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 23:11:16.685460 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 23:11:16.688749 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 23:11:16.691880 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 23:11:16.698961 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 23:11:16.702100 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 23:11:16.705666 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 23:11:16.708404 Total UI for P1: 0, mck2ui 16
6814 23:11:16.712012 best dqsien dly found for B0: ( 0, 14, 24)
6815 23:11:16.715353 Total UI for P1: 0, mck2ui 16
6816 23:11:16.718655 best dqsien dly found for B1: ( 0, 14, 24)
6817 23:11:16.722100 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6818 23:11:16.728562 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6819 23:11:16.728644
6820 23:11:16.732013 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6821 23:11:16.735450 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 23:11:16.738389 [Gating] SW calibration Done
6823 23:11:16.738470 ==
6824 23:11:16.742268 Dram Type= 6, Freq= 0, CH_1, rank 1
6825 23:11:16.745390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 23:11:16.745467 ==
6827 23:11:16.745530 RX Vref Scan: 0
6828 23:11:16.748412
6829 23:11:16.748486 RX Vref 0 -> 0, step: 1
6830 23:11:16.748548
6831 23:11:16.751664 RX Delay -410 -> 252, step: 16
6832 23:11:16.754930 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6833 23:11:16.761888 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6834 23:11:16.765066 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6835 23:11:16.768325 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6836 23:11:16.771759 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6837 23:11:16.778536 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6838 23:11:16.782019 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6839 23:11:16.785241 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6840 23:11:16.788571 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6841 23:11:16.795391 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6842 23:11:16.798664 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6843 23:11:16.801747 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6844 23:11:16.805561 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6845 23:11:16.811719 iDelay=230, Bit 13, Center -3 (-234 ~ 229) 464
6846 23:11:16.815235 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6847 23:11:16.818748 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6848 23:11:16.818830 ==
6849 23:11:16.821886 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 23:11:16.825235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 23:11:16.828435 ==
6852 23:11:16.828532 DQS Delay:
6853 23:11:16.828610 DQS0 = 35, DQS1 = 35
6854 23:11:16.831627 DQM Delay:
6855 23:11:16.831708 DQM0 = 19, DQM1 = 16
6856 23:11:16.834860 DQ Delay:
6857 23:11:16.834944 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6858 23:11:16.838576 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6859 23:11:16.841686 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6860 23:11:16.845262 DQ12 =24, DQ13 =32, DQ14 =16, DQ15 =24
6861 23:11:16.845344
6862 23:11:16.845408
6863 23:11:16.848547 ==
6864 23:11:16.852028 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 23:11:16.855350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 23:11:16.855431 ==
6867 23:11:16.855495
6868 23:11:16.855554
6869 23:11:16.858720 TX Vref Scan disable
6870 23:11:16.858800 == TX Byte 0 ==
6871 23:11:16.861900 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6872 23:11:16.868051 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6873 23:11:16.868133 == TX Byte 1 ==
6874 23:11:16.871332 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6875 23:11:16.878263 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6876 23:11:16.878345 ==
6877 23:11:16.881558 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 23:11:16.884879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 23:11:16.884981 ==
6880 23:11:16.885049
6881 23:11:16.885110
6882 23:11:16.888109 TX Vref Scan disable
6883 23:11:16.888193 == TX Byte 0 ==
6884 23:11:16.891214 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6885 23:11:16.897804 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6886 23:11:16.897888 == TX Byte 1 ==
6887 23:11:16.901321 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6888 23:11:16.908147 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6889 23:11:16.908236
6890 23:11:16.908322 [DATLAT]
6891 23:11:16.908403 Freq=400, CH1 RK1
6892 23:11:16.908483
6893 23:11:16.911341 DATLAT Default: 0xe
6894 23:11:16.911425 0, 0xFFFF, sum = 0
6895 23:11:16.914496 1, 0xFFFF, sum = 0
6896 23:11:16.918098 2, 0xFFFF, sum = 0
6897 23:11:16.918181 3, 0xFFFF, sum = 0
6898 23:11:16.921216 4, 0xFFFF, sum = 0
6899 23:11:16.921299 5, 0xFFFF, sum = 0
6900 23:11:16.924756 6, 0xFFFF, sum = 0
6901 23:11:16.924839 7, 0xFFFF, sum = 0
6902 23:11:16.927742 8, 0xFFFF, sum = 0
6903 23:11:16.927824 9, 0xFFFF, sum = 0
6904 23:11:16.931691 10, 0xFFFF, sum = 0
6905 23:11:16.931773 11, 0xFFFF, sum = 0
6906 23:11:16.934771 12, 0xFFFF, sum = 0
6907 23:11:16.934853 13, 0x0, sum = 1
6908 23:11:16.937846 14, 0x0, sum = 2
6909 23:11:16.937928 15, 0x0, sum = 3
6910 23:11:16.940932 16, 0x0, sum = 4
6911 23:11:16.941014 best_step = 14
6912 23:11:16.941079
6913 23:11:16.941139 ==
6914 23:11:16.944555 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 23:11:16.947533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 23:11:16.951397 ==
6917 23:11:16.951479 RX Vref Scan: 0
6918 23:11:16.951543
6919 23:11:16.954465 RX Vref 0 -> 0, step: 1
6920 23:11:16.954571
6921 23:11:16.957565 RX Delay -311 -> 252, step: 8
6922 23:11:16.964006 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6923 23:11:16.967543 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6924 23:11:16.970826 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6925 23:11:16.973993 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6926 23:11:16.981168 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6927 23:11:16.984112 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6928 23:11:16.987272 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6929 23:11:16.990938 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6930 23:11:16.994032 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6931 23:11:17.001064 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6932 23:11:17.003750 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6933 23:11:17.007457 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6934 23:11:17.014104 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6935 23:11:17.017172 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6936 23:11:17.020601 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6937 23:11:17.024347 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6938 23:11:17.024425 ==
6939 23:11:17.027583 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 23:11:17.034299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 23:11:17.034382 ==
6942 23:11:17.034466 DQS Delay:
6943 23:11:17.037148 DQS0 = 28, DQS1 = 36
6944 23:11:17.037228 DQM Delay:
6945 23:11:17.037292 DQM0 = 11, DQM1 = 14
6946 23:11:17.040647 DQ Delay:
6947 23:11:17.044157 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =4
6948 23:11:17.047113 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
6949 23:11:17.047194 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6950 23:11:17.054174 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6951 23:11:17.054256
6952 23:11:17.054321
6953 23:11:17.060408 [DQSOSCAuto] RK1, (LSB)MR18= 0xc052, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
6954 23:11:17.063597 CH1 RK1: MR19=C0C, MR18=C052
6955 23:11:17.070585 CH1_RK1: MR19=0xC0C, MR18=0xC052, DQSOSC=386, MR23=63, INC=396, DEC=264
6956 23:11:17.073756 [RxdqsGatingPostProcess] freq 400
6957 23:11:17.077162 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6958 23:11:17.080556 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 23:11:17.083978 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 23:11:17.087231 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 23:11:17.090142 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 23:11:17.093492 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 23:11:17.096760 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 23:11:17.100373 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 23:11:17.103754 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 23:11:17.106977 Pre-setting of DQS Precalculation
6967 23:11:17.110010 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6968 23:11:17.116651 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6969 23:11:17.127149 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6970 23:11:17.127246
6971 23:11:17.127310
6972 23:11:17.130498 [Calibration Summary] 800 Mbps
6973 23:11:17.130583 CH 0, Rank 0
6974 23:11:17.133515 SW Impedance : PASS
6975 23:11:17.133618 DUTY Scan : NO K
6976 23:11:17.136946 ZQ Calibration : PASS
6977 23:11:17.139886 Jitter Meter : NO K
6978 23:11:17.139974 CBT Training : PASS
6979 23:11:17.143598 Write leveling : PASS
6980 23:11:17.143676 RX DQS gating : PASS
6981 23:11:17.147024 RX DQ/DQS(RDDQC) : PASS
6982 23:11:17.150230 TX DQ/DQS : PASS
6983 23:11:17.150305 RX DATLAT : PASS
6984 23:11:17.153554 RX DQ/DQS(Engine): PASS
6985 23:11:17.157098 TX OE : NO K
6986 23:11:17.157175 All Pass.
6987 23:11:17.157239
6988 23:11:17.157298 CH 0, Rank 1
6989 23:11:17.159966 SW Impedance : PASS
6990 23:11:17.163343 DUTY Scan : NO K
6991 23:11:17.163444 ZQ Calibration : PASS
6992 23:11:17.166589 Jitter Meter : NO K
6993 23:11:17.169801 CBT Training : PASS
6994 23:11:17.169887 Write leveling : NO K
6995 23:11:17.174125 RX DQS gating : PASS
6996 23:11:17.176404 RX DQ/DQS(RDDQC) : PASS
6997 23:11:17.176476 TX DQ/DQS : PASS
6998 23:11:17.180072 RX DATLAT : PASS
6999 23:11:17.183073 RX DQ/DQS(Engine): PASS
7000 23:11:17.183146 TX OE : NO K
7001 23:11:17.183208 All Pass.
7002 23:11:17.186259
7003 23:11:17.186361 CH 1, Rank 0
7004 23:11:17.189723 SW Impedance : PASS
7005 23:11:17.189822 DUTY Scan : NO K
7006 23:11:17.193055 ZQ Calibration : PASS
7007 23:11:17.196576 Jitter Meter : NO K
7008 23:11:17.196674 CBT Training : PASS
7009 23:11:17.199889 Write leveling : PASS
7010 23:11:17.200007 RX DQS gating : PASS
7011 23:11:17.203455 RX DQ/DQS(RDDQC) : PASS
7012 23:11:17.206171 TX DQ/DQS : PASS
7013 23:11:17.206254 RX DATLAT : PASS
7014 23:11:17.209955 RX DQ/DQS(Engine): PASS
7015 23:11:17.213299 TX OE : NO K
7016 23:11:17.213382 All Pass.
7017 23:11:17.213448
7018 23:11:17.213509 CH 1, Rank 1
7019 23:11:17.216483 SW Impedance : PASS
7020 23:11:17.219946 DUTY Scan : NO K
7021 23:11:17.220028 ZQ Calibration : PASS
7022 23:11:17.223493 Jitter Meter : NO K
7023 23:11:17.226374 CBT Training : PASS
7024 23:11:17.226455 Write leveling : NO K
7025 23:11:17.229615 RX DQS gating : PASS
7026 23:11:17.233268 RX DQ/DQS(RDDQC) : PASS
7027 23:11:17.233353 TX DQ/DQS : PASS
7028 23:11:17.236781 RX DATLAT : PASS
7029 23:11:17.236863 RX DQ/DQS(Engine): PASS
7030 23:11:17.239697 TX OE : NO K
7031 23:11:17.239779 All Pass.
7032 23:11:17.239849
7033 23:11:17.243112 DramC Write-DBI off
7034 23:11:17.246954 PER_BANK_REFRESH: Hybrid Mode
7035 23:11:17.247036 TX_TRACKING: ON
7036 23:11:17.257109 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7037 23:11:17.259727 [FAST_K] Save calibration result to emmc
7038 23:11:17.263424 dramc_set_vcore_voltage set vcore to 725000
7039 23:11:17.266569 Read voltage for 1600, 0
7040 23:11:17.266651 Vio18 = 0
7041 23:11:17.269869 Vcore = 725000
7042 23:11:17.269950 Vdram = 0
7043 23:11:17.270016 Vddq = 0
7044 23:11:17.270076 Vmddr = 0
7045 23:11:17.276474 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7046 23:11:17.282795 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7047 23:11:17.282880 MEM_TYPE=3, freq_sel=13
7048 23:11:17.286337 sv_algorithm_assistance_LP4_3733
7049 23:11:17.289902 ============ PULL DRAM RESETB DOWN ============
7050 23:11:17.296525 ========== PULL DRAM RESETB DOWN end =========
7051 23:11:17.299655 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7052 23:11:17.302922 ===================================
7053 23:11:17.306801 LPDDR4 DRAM CONFIGURATION
7054 23:11:17.309494 ===================================
7055 23:11:17.309596 EX_ROW_EN[0] = 0x0
7056 23:11:17.312816 EX_ROW_EN[1] = 0x0
7057 23:11:17.312896 LP4Y_EN = 0x0
7058 23:11:17.315964 WORK_FSP = 0x1
7059 23:11:17.316046 WL = 0x5
7060 23:11:17.319411 RL = 0x5
7061 23:11:17.319492 BL = 0x2
7062 23:11:17.322711 RPST = 0x0
7063 23:11:17.325858 RD_PRE = 0x0
7064 23:11:17.325939 WR_PRE = 0x1
7065 23:11:17.329405 WR_PST = 0x1
7066 23:11:17.329485 DBI_WR = 0x0
7067 23:11:17.332965 DBI_RD = 0x0
7068 23:11:17.333046 OTF = 0x1
7069 23:11:17.336079 ===================================
7070 23:11:17.339330 ===================================
7071 23:11:17.342471 ANA top config
7072 23:11:17.345929 ===================================
7073 23:11:17.346010 DLL_ASYNC_EN = 0
7074 23:11:17.349220 ALL_SLAVE_EN = 0
7075 23:11:17.353038 NEW_RANK_MODE = 1
7076 23:11:17.355653 DLL_IDLE_MODE = 1
7077 23:11:17.355734 LP45_APHY_COMB_EN = 1
7078 23:11:17.359016 TX_ODT_DIS = 0
7079 23:11:17.362391 NEW_8X_MODE = 1
7080 23:11:17.365806 ===================================
7081 23:11:17.369604 ===================================
7082 23:11:17.372834 data_rate = 3200
7083 23:11:17.376144 CKR = 1
7084 23:11:17.376224 DQ_P2S_RATIO = 8
7085 23:11:17.379380 ===================================
7086 23:11:17.382468 CA_P2S_RATIO = 8
7087 23:11:17.386604 DQ_CA_OPEN = 0
7088 23:11:17.389495 DQ_SEMI_OPEN = 0
7089 23:11:17.392515 CA_SEMI_OPEN = 0
7090 23:11:17.396069 CA_FULL_RATE = 0
7091 23:11:17.396154 DQ_CKDIV4_EN = 0
7092 23:11:17.399202 CA_CKDIV4_EN = 0
7093 23:11:17.402643 CA_PREDIV_EN = 0
7094 23:11:17.406169 PH8_DLY = 12
7095 23:11:17.409006 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7096 23:11:17.412360 DQ_AAMCK_DIV = 4
7097 23:11:17.412441 CA_AAMCK_DIV = 4
7098 23:11:17.415740 CA_ADMCK_DIV = 4
7099 23:11:17.418946 DQ_TRACK_CA_EN = 0
7100 23:11:17.422221 CA_PICK = 1600
7101 23:11:17.425468 CA_MCKIO = 1600
7102 23:11:17.428890 MCKIO_SEMI = 0
7103 23:11:17.432079 PLL_FREQ = 3068
7104 23:11:17.435651 DQ_UI_PI_RATIO = 32
7105 23:11:17.435731 CA_UI_PI_RATIO = 0
7106 23:11:17.438861 ===================================
7107 23:11:17.442273 ===================================
7108 23:11:17.445771 memory_type:LPDDR4
7109 23:11:17.448681 GP_NUM : 10
7110 23:11:17.448761 SRAM_EN : 1
7111 23:11:17.452427 MD32_EN : 0
7112 23:11:17.455747 ===================================
7113 23:11:17.458875 [ANA_INIT] >>>>>>>>>>>>>>
7114 23:11:17.462058 <<<<<< [CONFIGURE PHASE]: ANA_TX
7115 23:11:17.465549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7116 23:11:17.469160 ===================================
7117 23:11:17.469243 data_rate = 3200,PCW = 0X7600
7118 23:11:17.472366 ===================================
7119 23:11:17.475702 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7120 23:11:17.482123 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7121 23:11:17.488750 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 23:11:17.492062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7123 23:11:17.495835 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7124 23:11:17.498580 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7125 23:11:17.502168 [ANA_INIT] flow start
7126 23:11:17.502245 [ANA_INIT] PLL >>>>>>>>
7127 23:11:17.506049 [ANA_INIT] PLL <<<<<<<<
7128 23:11:17.508888 [ANA_INIT] MIDPI >>>>>>>>
7129 23:11:17.511931 [ANA_INIT] MIDPI <<<<<<<<
7130 23:11:17.512041 [ANA_INIT] DLL >>>>>>>>
7131 23:11:17.515554 [ANA_INIT] DLL <<<<<<<<
7132 23:11:17.515651 [ANA_INIT] flow end
7133 23:11:17.522277 ============ LP4 DIFF to SE enter ============
7134 23:11:17.525583 ============ LP4 DIFF to SE exit ============
7135 23:11:17.528879 [ANA_INIT] <<<<<<<<<<<<<
7136 23:11:17.531738 [Flow] Enable top DCM control >>>>>
7137 23:11:17.535227 [Flow] Enable top DCM control <<<<<
7138 23:11:17.538300 Enable DLL master slave shuffle
7139 23:11:17.541743 ==============================================================
7140 23:11:17.545194 Gating Mode config
7141 23:11:17.548615 ==============================================================
7142 23:11:17.551649 Config description:
7143 23:11:17.561345 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7144 23:11:17.568641 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7145 23:11:17.571217 SELPH_MODE 0: By rank 1: By Phase
7146 23:11:17.578169 ==============================================================
7147 23:11:17.581488 GAT_TRACK_EN = 1
7148 23:11:17.584789 RX_GATING_MODE = 2
7149 23:11:17.587998 RX_GATING_TRACK_MODE = 2
7150 23:11:17.591164 SELPH_MODE = 1
7151 23:11:17.594620 PICG_EARLY_EN = 1
7152 23:11:17.597938 VALID_LAT_VALUE = 1
7153 23:11:17.601148 ==============================================================
7154 23:11:17.604788 Enter into Gating configuration >>>>
7155 23:11:17.607923 Exit from Gating configuration <<<<
7156 23:11:17.610927 Enter into DVFS_PRE_config >>>>>
7157 23:11:17.624777 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7158 23:11:17.624869 Exit from DVFS_PRE_config <<<<<
7159 23:11:17.627627 Enter into PICG configuration >>>>
7160 23:11:17.631189 Exit from PICG configuration <<<<
7161 23:11:17.634291 [RX_INPUT] configuration >>>>>
7162 23:11:17.638016 [RX_INPUT] configuration <<<<<
7163 23:11:17.644212 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7164 23:11:17.647374 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7165 23:11:17.654206 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7166 23:11:17.660751 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7167 23:11:17.667155 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7168 23:11:17.673761 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7169 23:11:17.676947 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7170 23:11:17.680899 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7171 23:11:17.684078 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7172 23:11:17.690289 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7173 23:11:17.694052 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7174 23:11:17.697043 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7175 23:11:17.700265 ===================================
7176 23:11:17.703876 LPDDR4 DRAM CONFIGURATION
7177 23:11:17.707223 ===================================
7178 23:11:17.710471 EX_ROW_EN[0] = 0x0
7179 23:11:17.710551 EX_ROW_EN[1] = 0x0
7180 23:11:17.713849 LP4Y_EN = 0x0
7181 23:11:17.713930 WORK_FSP = 0x1
7182 23:11:17.717183 WL = 0x5
7183 23:11:17.717263 RL = 0x5
7184 23:11:17.720476 BL = 0x2
7185 23:11:17.720557 RPST = 0x0
7186 23:11:17.724024 RD_PRE = 0x0
7187 23:11:17.724105 WR_PRE = 0x1
7188 23:11:17.726999 WR_PST = 0x1
7189 23:11:17.727079 DBI_WR = 0x0
7190 23:11:17.730459 DBI_RD = 0x0
7191 23:11:17.730538 OTF = 0x1
7192 23:11:17.733852 ===================================
7193 23:11:17.736963 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7194 23:11:17.743875 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7195 23:11:17.747156 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7196 23:11:17.750561 ===================================
7197 23:11:17.753894 LPDDR4 DRAM CONFIGURATION
7198 23:11:17.757047 ===================================
7199 23:11:17.757129 EX_ROW_EN[0] = 0x10
7200 23:11:17.760273 EX_ROW_EN[1] = 0x0
7201 23:11:17.764058 LP4Y_EN = 0x0
7202 23:11:17.764144 WORK_FSP = 0x1
7203 23:11:17.766584 WL = 0x5
7204 23:11:17.766666 RL = 0x5
7205 23:11:17.770424 BL = 0x2
7206 23:11:17.770525 RPST = 0x0
7207 23:11:17.773882 RD_PRE = 0x0
7208 23:11:17.773960 WR_PRE = 0x1
7209 23:11:17.776555 WR_PST = 0x1
7210 23:11:17.776626 DBI_WR = 0x0
7211 23:11:17.780429 DBI_RD = 0x0
7212 23:11:17.780504 OTF = 0x1
7213 23:11:17.783419 ===================================
7214 23:11:17.790214 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7215 23:11:17.790303 ==
7216 23:11:17.793375 Dram Type= 6, Freq= 0, CH_0, rank 0
7217 23:11:17.796880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7218 23:11:17.796963 ==
7219 23:11:17.800226 [Duty_Offset_Calibration]
7220 23:11:17.803675 B0:2 B1:1 CA:1
7221 23:11:17.803755
7222 23:11:17.806810 [DutyScan_Calibration_Flow] k_type=0
7223 23:11:17.815513
7224 23:11:17.815595 ==CLK 0==
7225 23:11:17.819083 Final CLK duty delay cell = 0
7226 23:11:17.822394 [0] MAX Duty = 5156%(X100), DQS PI = 22
7227 23:11:17.825592 [0] MIN Duty = 4907%(X100), DQS PI = 0
7228 23:11:17.825673 [0] AVG Duty = 5031%(X100)
7229 23:11:17.828979
7230 23:11:17.832637 CH0 CLK Duty spec in!! Max-Min= 249%
7231 23:11:17.835048 [DutyScan_Calibration_Flow] ====Done====
7232 23:11:17.835130
7233 23:11:17.838764 [DutyScan_Calibration_Flow] k_type=1
7234 23:11:17.854549
7235 23:11:17.854635 ==DQS 0 ==
7236 23:11:17.857928 Final DQS duty delay cell = -4
7237 23:11:17.861339 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7238 23:11:17.864463 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7239 23:11:17.868061 [-4] AVG Duty = 4891%(X100)
7240 23:11:17.868142
7241 23:11:17.868207 ==DQS 1 ==
7242 23:11:17.871020 Final DQS duty delay cell = 0
7243 23:11:17.874429 [0] MAX Duty = 5187%(X100), DQS PI = 10
7244 23:11:17.877939 [0] MIN Duty = 5031%(X100), DQS PI = 52
7245 23:11:17.880842 [0] AVG Duty = 5109%(X100)
7246 23:11:17.880923
7247 23:11:17.884239 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7248 23:11:17.884321
7249 23:11:17.887703 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7250 23:11:17.891324 [DutyScan_Calibration_Flow] ====Done====
7251 23:11:17.891407
7252 23:11:17.894256 [DutyScan_Calibration_Flow] k_type=3
7253 23:11:17.912109
7254 23:11:17.912200 ==DQM 0 ==
7255 23:11:17.915046 Final DQM duty delay cell = 0
7256 23:11:17.918401 [0] MAX Duty = 5187%(X100), DQS PI = 26
7257 23:11:17.921988 [0] MIN Duty = 4875%(X100), DQS PI = 60
7258 23:11:17.925521 [0] AVG Duty = 5031%(X100)
7259 23:11:17.925610
7260 23:11:17.925675 ==DQM 1 ==
7261 23:11:17.928562 Final DQM duty delay cell = 0
7262 23:11:17.932082 [0] MAX Duty = 5187%(X100), DQS PI = 2
7263 23:11:17.935055 [0] MIN Duty = 5031%(X100), DQS PI = 48
7264 23:11:17.938360 [0] AVG Duty = 5109%(X100)
7265 23:11:17.938442
7266 23:11:17.941835 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7267 23:11:17.941917
7268 23:11:17.945200 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7269 23:11:17.948751 [DutyScan_Calibration_Flow] ====Done====
7270 23:11:17.948832
7271 23:11:17.951723 [DutyScan_Calibration_Flow] k_type=2
7272 23:11:17.969735
7273 23:11:17.969823 ==DQ 0 ==
7274 23:11:17.972639 Final DQ duty delay cell = 0
7275 23:11:17.975914 [0] MAX Duty = 5062%(X100), DQS PI = 24
7276 23:11:17.979327 [0] MIN Duty = 4907%(X100), DQS PI = 0
7277 23:11:17.979409 [0] AVG Duty = 4984%(X100)
7278 23:11:17.979474
7279 23:11:17.982363 ==DQ 1 ==
7280 23:11:17.985728 Final DQ duty delay cell = 0
7281 23:11:17.989459 [0] MAX Duty = 5156%(X100), DQS PI = 22
7282 23:11:17.993012 [0] MIN Duty = 4907%(X100), DQS PI = 34
7283 23:11:17.993095 [0] AVG Duty = 5031%(X100)
7284 23:11:17.993160
7285 23:11:17.995603 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7286 23:11:17.999014
7287 23:11:18.002602 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7288 23:11:18.006320 [DutyScan_Calibration_Flow] ====Done====
7289 23:11:18.006401 ==
7290 23:11:18.009244 Dram Type= 6, Freq= 0, CH_1, rank 0
7291 23:11:18.012199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7292 23:11:18.012368 ==
7293 23:11:18.015887 [Duty_Offset_Calibration]
7294 23:11:18.015968 B0:1 B1:0 CA:0
7295 23:11:18.016033
7296 23:11:18.018941 [DutyScan_Calibration_Flow] k_type=0
7297 23:11:18.028645
7298 23:11:18.028735 ==CLK 0==
7299 23:11:18.031934 Final CLK duty delay cell = -4
7300 23:11:18.035180 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7301 23:11:18.038403 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7302 23:11:18.041847 [-4] AVG Duty = 4906%(X100)
7303 23:11:18.041927
7304 23:11:18.045440 CH1 CLK Duty spec in!! Max-Min= 125%
7305 23:11:18.049216 [DutyScan_Calibration_Flow] ====Done====
7306 23:11:18.049322
7307 23:11:18.051927 [DutyScan_Calibration_Flow] k_type=1
7308 23:11:18.068566
7309 23:11:18.068695 ==DQS 0 ==
7310 23:11:18.071705 Final DQS duty delay cell = 0
7311 23:11:18.075453 [0] MAX Duty = 5094%(X100), DQS PI = 16
7312 23:11:18.078646 [0] MIN Duty = 4844%(X100), DQS PI = 48
7313 23:11:18.078726 [0] AVG Duty = 4969%(X100)
7314 23:11:18.082243
7315 23:11:18.082323 ==DQS 1 ==
7316 23:11:18.085431 Final DQS duty delay cell = 0
7317 23:11:18.088333 [0] MAX Duty = 5249%(X100), DQS PI = 18
7318 23:11:18.091831 [0] MIN Duty = 4969%(X100), DQS PI = 8
7319 23:11:18.091913 [0] AVG Duty = 5109%(X100)
7320 23:11:18.095059
7321 23:11:18.098564 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7322 23:11:18.098645
7323 23:11:18.101620 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7324 23:11:18.104921 [DutyScan_Calibration_Flow] ====Done====
7325 23:11:18.105001
7326 23:11:18.108304 [DutyScan_Calibration_Flow] k_type=3
7327 23:11:18.125216
7328 23:11:18.125307 ==DQM 0 ==
7329 23:11:18.128899 Final DQM duty delay cell = 0
7330 23:11:18.132388 [0] MAX Duty = 5218%(X100), DQS PI = 18
7331 23:11:18.135156 [0] MIN Duty = 4969%(X100), DQS PI = 48
7332 23:11:18.138767 [0] AVG Duty = 5093%(X100)
7333 23:11:18.138847
7334 23:11:18.138911 ==DQM 1 ==
7335 23:11:18.141933 Final DQM duty delay cell = 0
7336 23:11:18.145456 [0] MAX Duty = 5093%(X100), DQS PI = 16
7337 23:11:18.148396 [0] MIN Duty = 4907%(X100), DQS PI = 50
7338 23:11:18.152206 [0] AVG Duty = 5000%(X100)
7339 23:11:18.152325
7340 23:11:18.155195 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7341 23:11:18.155293
7342 23:11:18.158547 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7343 23:11:18.162305 [DutyScan_Calibration_Flow] ====Done====
7344 23:11:18.162387
7345 23:11:18.165353 [DutyScan_Calibration_Flow] k_type=2
7346 23:11:18.181250
7347 23:11:18.181346 ==DQ 0 ==
7348 23:11:18.184794 Final DQ duty delay cell = -4
7349 23:11:18.188309 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7350 23:11:18.191818 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7351 23:11:18.194736 [-4] AVG Duty = 4968%(X100)
7352 23:11:18.194816
7353 23:11:18.194879 ==DQ 1 ==
7354 23:11:18.198232 Final DQ duty delay cell = 0
7355 23:11:18.201714 [0] MAX Duty = 5124%(X100), DQS PI = 16
7356 23:11:18.204986 [0] MIN Duty = 4938%(X100), DQS PI = 10
7357 23:11:18.208064 [0] AVG Duty = 5031%(X100)
7358 23:11:18.208144
7359 23:11:18.211625 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7360 23:11:18.211705
7361 23:11:18.214540 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7362 23:11:18.218140 [DutyScan_Calibration_Flow] ====Done====
7363 23:11:18.221211 nWR fixed to 30
7364 23:11:18.224530 [ModeRegInit_LP4] CH0 RK0
7365 23:11:18.224636 [ModeRegInit_LP4] CH0 RK1
7366 23:11:18.228328 [ModeRegInit_LP4] CH1 RK0
7367 23:11:18.231678 [ModeRegInit_LP4] CH1 RK1
7368 23:11:18.231758 match AC timing 5
7369 23:11:18.237807 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7370 23:11:18.241106 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7371 23:11:18.244725 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7372 23:11:18.251394 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7373 23:11:18.254937 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7374 23:11:18.255019 [MiockJmeterHQA]
7375 23:11:18.255082
7376 23:11:18.257838 [DramcMiockJmeter] u1RxGatingPI = 0
7377 23:11:18.261220 0 : 4255, 4027
7378 23:11:18.261327 4 : 4255, 4027
7379 23:11:18.264429 8 : 4258, 4029
7380 23:11:18.264510 12 : 4252, 4027
7381 23:11:18.264576 16 : 4252, 4027
7382 23:11:18.267984 20 : 4252, 4027
7383 23:11:18.268074 24 : 4255, 4029
7384 23:11:18.271198 28 : 4363, 4137
7385 23:11:18.271312 32 : 4253, 4027
7386 23:11:18.274760 36 : 4252, 4026
7387 23:11:18.274843 40 : 4252, 4027
7388 23:11:18.277961 44 : 4254, 4029
7389 23:11:18.278043 48 : 4252, 4027
7390 23:11:18.278108 52 : 4363, 4138
7391 23:11:18.281535 56 : 4360, 4137
7392 23:11:18.281655 60 : 4250, 4027
7393 23:11:18.284190 64 : 4253, 4027
7394 23:11:18.284272 68 : 4250, 4027
7395 23:11:18.287782 72 : 4250, 4027
7396 23:11:18.287864 76 : 4253, 4029
7397 23:11:18.291209 80 : 4360, 4137
7398 23:11:18.291293 84 : 4250, 4027
7399 23:11:18.291359 88 : 4250, 153
7400 23:11:18.294340 92 : 4360, 0
7401 23:11:18.294422 96 : 4249, 0
7402 23:11:18.294487 100 : 4249, 0
7403 23:11:18.297896 104 : 4363, 0
7404 23:11:18.297979 108 : 4250, 0
7405 23:11:18.301079 112 : 4361, 0
7406 23:11:18.301193 116 : 4249, 0
7407 23:11:18.301293 120 : 4250, 0
7408 23:11:18.304640 124 : 4250, 0
7409 23:11:18.304721 128 : 4250, 0
7410 23:11:18.307597 132 : 4252, 0
7411 23:11:18.307678 136 : 4250, 0
7412 23:11:18.307764 140 : 4250, 0
7413 23:11:18.310983 144 : 4252, 0
7414 23:11:18.311065 148 : 4360, 0
7415 23:11:18.314087 152 : 4250, 0
7416 23:11:18.314169 156 : 4361, 0
7417 23:11:18.314234 160 : 4250, 0
7418 23:11:18.317770 164 : 4361, 0
7419 23:11:18.317851 168 : 4250, 0
7420 23:11:18.317916 172 : 4250, 0
7421 23:11:18.321417 176 : 4250, 0
7422 23:11:18.321524 180 : 4250, 0
7423 23:11:18.324791 184 : 4252, 0
7424 23:11:18.324873 188 : 4250, 0
7425 23:11:18.324938 192 : 4250, 0
7426 23:11:18.328225 196 : 4252, 0
7427 23:11:18.328331 200 : 4360, 0
7428 23:11:18.331057 204 : 4250, 1163
7429 23:11:18.331139 208 : 4250, 3983
7430 23:11:18.334315 212 : 4250, 4026
7431 23:11:18.334401 216 : 4361, 4137
7432 23:11:18.337773 220 : 4252, 4029
7433 23:11:18.337855 224 : 4250, 4027
7434 23:11:18.337920 228 : 4250, 4026
7435 23:11:18.341170 232 : 4250, 4027
7436 23:11:18.341256 236 : 4250, 4027
7437 23:11:18.344480 240 : 4250, 4027
7438 23:11:18.344562 244 : 4360, 4137
7439 23:11:18.347610 248 : 4249, 4027
7440 23:11:18.347703 252 : 4361, 4137
7441 23:11:18.351272 256 : 4360, 4137
7442 23:11:18.351370 260 : 4250, 4027
7443 23:11:18.354527 264 : 4250, 4026
7444 23:11:18.354608 268 : 4363, 4140
7445 23:11:18.357992 272 : 4249, 4027
7446 23:11:18.358101 276 : 4250, 4027
7447 23:11:18.361566 280 : 4252, 4029
7448 23:11:18.361670 284 : 4252, 4029
7449 23:11:18.361737 288 : 4250, 4026
7450 23:11:18.364414 292 : 4250, 4027
7451 23:11:18.364509 296 : 4360, 4138
7452 23:11:18.367440 300 : 4249, 4027
7453 23:11:18.367523 304 : 4250, 4027
7454 23:11:18.370768 308 : 4360, 4059
7455 23:11:18.370850 312 : 4250, 2150
7456 23:11:18.374601 316 : 4250, 27
7457 23:11:18.374683
7458 23:11:18.374747 MIOCK jitter meter ch=0
7459 23:11:18.374807
7460 23:11:18.377720 1T = (316-88) = 228 dly cells
7461 23:11:18.384649 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7462 23:11:18.384732 ==
7463 23:11:18.387694 Dram Type= 6, Freq= 0, CH_0, rank 0
7464 23:11:18.391020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7465 23:11:18.391106 ==
7466 23:11:18.397483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7467 23:11:18.400771 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7468 23:11:18.404029 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7469 23:11:18.410663 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7470 23:11:18.420906 [CA 0] Center 42 (12~73) winsize 62
7471 23:11:18.423993 [CA 1] Center 42 (12~73) winsize 62
7472 23:11:18.427079 [CA 2] Center 37 (8~67) winsize 60
7473 23:11:18.430661 [CA 3] Center 37 (7~67) winsize 61
7474 23:11:18.433903 [CA 4] Center 36 (6~66) winsize 61
7475 23:11:18.437297 [CA 5] Center 35 (6~64) winsize 59
7476 23:11:18.437381
7477 23:11:18.440243 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7478 23:11:18.440327
7479 23:11:18.443610 [CATrainingPosCal] consider 1 rank data
7480 23:11:18.447170 u2DelayCellTimex100 = 285/100 ps
7481 23:11:18.450724 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7482 23:11:18.457179 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7483 23:11:18.460533 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7484 23:11:18.464386 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7485 23:11:18.466939 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7486 23:11:18.470211 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7487 23:11:18.470294
7488 23:11:18.473843 CA PerBit enable=1, Macro0, CA PI delay=35
7489 23:11:18.473927
7490 23:11:18.476830 [CBTSetCACLKResult] CA Dly = 35
7491 23:11:18.480719 CS Dly: 9 (0~40)
7492 23:11:18.483558 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7493 23:11:18.487133 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7494 23:11:18.487218 ==
7495 23:11:18.490002 Dram Type= 6, Freq= 0, CH_0, rank 1
7496 23:11:18.493394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7497 23:11:18.496716 ==
7498 23:11:18.500035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7499 23:11:18.503975 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7500 23:11:18.510067 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7501 23:11:18.516640 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7502 23:11:18.523966 [CA 0] Center 43 (13~73) winsize 61
7503 23:11:18.527263 [CA 1] Center 43 (13~73) winsize 61
7504 23:11:18.530616 [CA 2] Center 38 (8~68) winsize 61
7505 23:11:18.533760 [CA 3] Center 38 (8~68) winsize 61
7506 23:11:18.537428 [CA 4] Center 36 (6~66) winsize 61
7507 23:11:18.540870 [CA 5] Center 35 (6~65) winsize 60
7508 23:11:18.540949
7509 23:11:18.543933 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7510 23:11:18.544019
7511 23:11:18.547275 [CATrainingPosCal] consider 2 rank data
7512 23:11:18.550331 u2DelayCellTimex100 = 285/100 ps
7513 23:11:18.553829 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7514 23:11:18.560312 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7515 23:11:18.563814 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7516 23:11:18.567454 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7517 23:11:18.570428 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7518 23:11:18.573722 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7519 23:11:18.573805
7520 23:11:18.577417 CA PerBit enable=1, Macro0, CA PI delay=35
7521 23:11:18.577499
7522 23:11:18.580581 [CBTSetCACLKResult] CA Dly = 35
7523 23:11:18.583472 CS Dly: 10 (0~42)
7524 23:11:18.586760 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7525 23:11:18.590047 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7526 23:11:18.590131
7527 23:11:18.593559 ----->DramcWriteLeveling(PI) begin...
7528 23:11:18.593682 ==
7529 23:11:18.596977 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 23:11:18.600324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 23:11:18.604281 ==
7532 23:11:18.604363 Write leveling (Byte 0): 36 => 36
7533 23:11:18.606727 Write leveling (Byte 1): 29 => 29
7534 23:11:18.610443 DramcWriteLeveling(PI) end<-----
7535 23:11:18.610525
7536 23:11:18.610590 ==
7537 23:11:18.613414 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 23:11:18.620216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 23:11:18.620300 ==
7540 23:11:18.623437 [Gating] SW mode calibration
7541 23:11:18.630052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7542 23:11:18.633736 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7543 23:11:18.640079 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7544 23:11:18.643776 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7545 23:11:18.646620 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7546 23:11:18.650251 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7547 23:11:18.657449 1 4 16 | B1->B0 | 2323 3535 | 1 1 | (1 1) (1 1)
7548 23:11:18.660525 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7549 23:11:18.663541 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7550 23:11:18.670417 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7551 23:11:18.673279 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7552 23:11:18.677022 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7553 23:11:18.683545 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
7554 23:11:18.686472 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
7555 23:11:18.689697 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7556 23:11:18.696726 1 5 20 | B1->B0 | 2727 2525 | 0 0 | (1 0) (0 0)
7557 23:11:18.699695 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 23:11:18.703170 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 23:11:18.709846 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7560 23:11:18.713538 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7561 23:11:18.717007 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
7562 23:11:18.723075 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7563 23:11:18.726473 1 6 16 | B1->B0 | 2f2f 4646 | 0 0 | (1 1) (0 0)
7564 23:11:18.729691 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7565 23:11:18.736884 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 23:11:18.739937 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 23:11:18.743521 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 23:11:18.750093 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 23:11:18.753567 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 23:11:18.756679 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7571 23:11:18.759949 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7572 23:11:18.766662 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7573 23:11:18.769735 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 23:11:18.773157 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 23:11:18.779923 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 23:11:18.783556 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 23:11:18.786238 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 23:11:18.793189 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 23:11:18.796607 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 23:11:18.799975 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 23:11:18.806748 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 23:11:18.809481 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 23:11:18.813248 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 23:11:18.819613 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 23:11:18.823504 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7586 23:11:18.826902 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7587 23:11:18.832859 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7588 23:11:18.832942 Total UI for P1: 0, mck2ui 16
7589 23:11:18.839925 best dqsien dly found for B0: ( 1, 9, 10)
7590 23:11:18.843201 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 23:11:18.846432 Total UI for P1: 0, mck2ui 16
7592 23:11:18.849446 best dqsien dly found for B1: ( 1, 9, 16)
7593 23:11:18.853206 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7594 23:11:18.856221 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7595 23:11:18.856328
7596 23:11:18.859816 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7597 23:11:18.863074 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7598 23:11:18.866269 [Gating] SW calibration Done
7599 23:11:18.866351 ==
7600 23:11:18.869448 Dram Type= 6, Freq= 0, CH_0, rank 0
7601 23:11:18.876020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 23:11:18.876106 ==
7603 23:11:18.876173 RX Vref Scan: 0
7604 23:11:18.876234
7605 23:11:18.879478 RX Vref 0 -> 0, step: 1
7606 23:11:18.879561
7607 23:11:18.882711 RX Delay 0 -> 252, step: 8
7608 23:11:18.885893 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7609 23:11:18.889396 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7610 23:11:18.892750 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7611 23:11:18.896044 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7612 23:11:18.902812 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7613 23:11:18.906092 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7614 23:11:18.909120 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7615 23:11:18.912791 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7616 23:11:18.915888 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7617 23:11:18.919132 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7618 23:11:18.926169 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7619 23:11:18.929024 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7620 23:11:18.932863 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7621 23:11:18.936315 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7622 23:11:18.942550 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7623 23:11:18.946281 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7624 23:11:18.946363 ==
7625 23:11:18.949009 Dram Type= 6, Freq= 0, CH_0, rank 0
7626 23:11:18.952927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 23:11:18.953009 ==
7628 23:11:18.953074 DQS Delay:
7629 23:11:18.955893 DQS0 = 0, DQS1 = 0
7630 23:11:18.956007 DQM Delay:
7631 23:11:18.959178 DQM0 = 136, DQM1 = 130
7632 23:11:18.959259 DQ Delay:
7633 23:11:18.962621 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7634 23:11:18.965689 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7635 23:11:18.969471 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7636 23:11:18.972578 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7637 23:11:18.975924
7638 23:11:18.976005
7639 23:11:18.976070 ==
7640 23:11:18.979624 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 23:11:18.982512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 23:11:18.982594 ==
7643 23:11:18.982661
7644 23:11:18.982728
7645 23:11:18.985522 TX Vref Scan disable
7646 23:11:18.985640 == TX Byte 0 ==
7647 23:11:18.992346 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7648 23:11:18.995838 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7649 23:11:18.995920 == TX Byte 1 ==
7650 23:11:19.002542 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7651 23:11:19.005644 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7652 23:11:19.005726 ==
7653 23:11:19.009217 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 23:11:19.012074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 23:11:19.012156 ==
7656 23:11:19.025378
7657 23:11:19.028274 TX Vref early break, caculate TX vref
7658 23:11:19.032520 TX Vref=16, minBit 0, minWin=22, winSum=373
7659 23:11:19.035158 TX Vref=18, minBit 0, minWin=23, winSum=385
7660 23:11:19.038658 TX Vref=20, minBit 7, minWin=23, winSum=395
7661 23:11:19.041528 TX Vref=22, minBit 1, minWin=25, winSum=410
7662 23:11:19.045206 TX Vref=24, minBit 0, minWin=25, winSum=416
7663 23:11:19.051955 TX Vref=26, minBit 2, minWin=25, winSum=424
7664 23:11:19.054896 TX Vref=28, minBit 2, minWin=24, winSum=423
7665 23:11:19.058646 TX Vref=30, minBit 0, minWin=24, winSum=410
7666 23:11:19.061797 TX Vref=32, minBit 6, minWin=23, winSum=400
7667 23:11:19.068148 [TxChooseVref] Worse bit 2, Min win 25, Win sum 424, Final Vref 26
7668 23:11:19.068232
7669 23:11:19.071300 Final TX Range 0 Vref 26
7670 23:11:19.071382
7671 23:11:19.071447 ==
7672 23:11:19.074739 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 23:11:19.078074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 23:11:19.078156 ==
7675 23:11:19.078220
7676 23:11:19.078284
7677 23:11:19.081711 TX Vref Scan disable
7678 23:11:19.088052 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7679 23:11:19.088138 == TX Byte 0 ==
7680 23:11:19.091806 u2DelayCellOfst[0]=10 cells (3 PI)
7681 23:11:19.094783 u2DelayCellOfst[1]=13 cells (4 PI)
7682 23:11:19.097893 u2DelayCellOfst[2]=10 cells (3 PI)
7683 23:11:19.101243 u2DelayCellOfst[3]=6 cells (2 PI)
7684 23:11:19.104522 u2DelayCellOfst[4]=6 cells (2 PI)
7685 23:11:19.108106 u2DelayCellOfst[5]=0 cells (0 PI)
7686 23:11:19.108214 u2DelayCellOfst[6]=17 cells (5 PI)
7687 23:11:19.111256 u2DelayCellOfst[7]=13 cells (4 PI)
7688 23:11:19.118119 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7689 23:11:19.121267 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7690 23:11:19.121348 == TX Byte 1 ==
7691 23:11:19.124616 u2DelayCellOfst[8]=0 cells (0 PI)
7692 23:11:19.127742 u2DelayCellOfst[9]=0 cells (0 PI)
7693 23:11:19.131567 u2DelayCellOfst[10]=6 cells (2 PI)
7694 23:11:19.134904 u2DelayCellOfst[11]=3 cells (1 PI)
7695 23:11:19.137815 u2DelayCellOfst[12]=10 cells (3 PI)
7696 23:11:19.141289 u2DelayCellOfst[13]=10 cells (3 PI)
7697 23:11:19.144490 u2DelayCellOfst[14]=13 cells (4 PI)
7698 23:11:19.148144 u2DelayCellOfst[15]=10 cells (3 PI)
7699 23:11:19.151336 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7700 23:11:19.154739 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7701 23:11:19.158182 DramC Write-DBI on
7702 23:11:19.158268 ==
7703 23:11:19.161426 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 23:11:19.164933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 23:11:19.165015 ==
7706 23:11:19.165080
7707 23:11:19.165139
7708 23:11:19.167629 TX Vref Scan disable
7709 23:11:19.170919 == TX Byte 0 ==
7710 23:11:19.174840 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7711 23:11:19.177763 == TX Byte 1 ==
7712 23:11:19.181229 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7713 23:11:19.181310 DramC Write-DBI off
7714 23:11:19.181376
7715 23:11:19.184908 [DATLAT]
7716 23:11:19.184989 Freq=1600, CH0 RK0
7717 23:11:19.185064
7718 23:11:19.187901 DATLAT Default: 0xf
7719 23:11:19.187982 0, 0xFFFF, sum = 0
7720 23:11:19.191059 1, 0xFFFF, sum = 0
7721 23:11:19.191161 2, 0xFFFF, sum = 0
7722 23:11:19.194802 3, 0xFFFF, sum = 0
7723 23:11:19.194915 4, 0xFFFF, sum = 0
7724 23:11:19.198034 5, 0xFFFF, sum = 0
7725 23:11:19.198117 6, 0xFFFF, sum = 0
7726 23:11:19.201176 7, 0xFFFF, sum = 0
7727 23:11:19.201258 8, 0xFFFF, sum = 0
7728 23:11:19.204198 9, 0xFFFF, sum = 0
7729 23:11:19.207668 10, 0xFFFF, sum = 0
7730 23:11:19.207751 11, 0xFFFF, sum = 0
7731 23:11:19.211027 12, 0xFFFF, sum = 0
7732 23:11:19.211110 13, 0xFFFF, sum = 0
7733 23:11:19.214850 14, 0x0, sum = 1
7734 23:11:19.214932 15, 0x0, sum = 2
7735 23:11:19.217371 16, 0x0, sum = 3
7736 23:11:19.217453 17, 0x0, sum = 4
7737 23:11:19.217520 best_step = 15
7738 23:11:19.221046
7739 23:11:19.221126 ==
7740 23:11:19.224519 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 23:11:19.227679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 23:11:19.227761 ==
7743 23:11:19.227827 RX Vref Scan: 1
7744 23:11:19.227888
7745 23:11:19.231114 Set Vref Range= 24 -> 127
7746 23:11:19.231195
7747 23:11:19.234292 RX Vref 24 -> 127, step: 1
7748 23:11:19.234373
7749 23:11:19.237561 RX Delay 19 -> 252, step: 4
7750 23:11:19.237648
7751 23:11:19.240910 Set Vref, RX VrefLevel [Byte0]: 24
7752 23:11:19.244193 [Byte1]: 24
7753 23:11:19.244274
7754 23:11:19.247682 Set Vref, RX VrefLevel [Byte0]: 25
7755 23:11:19.250755 [Byte1]: 25
7756 23:11:19.250836
7757 23:11:19.253937 Set Vref, RX VrefLevel [Byte0]: 26
7758 23:11:19.257175 [Byte1]: 26
7759 23:11:19.261000
7760 23:11:19.261081 Set Vref, RX VrefLevel [Byte0]: 27
7761 23:11:19.263999 [Byte1]: 27
7762 23:11:19.268563
7763 23:11:19.268648 Set Vref, RX VrefLevel [Byte0]: 28
7764 23:11:19.271949 [Byte1]: 28
7765 23:11:19.276348
7766 23:11:19.276433 Set Vref, RX VrefLevel [Byte0]: 29
7767 23:11:19.279332 [Byte1]: 29
7768 23:11:19.283771
7769 23:11:19.283854 Set Vref, RX VrefLevel [Byte0]: 30
7770 23:11:19.287210 [Byte1]: 30
7771 23:11:19.291494
7772 23:11:19.291578 Set Vref, RX VrefLevel [Byte0]: 31
7773 23:11:19.294427 [Byte1]: 31
7774 23:11:19.298943
7775 23:11:19.299027 Set Vref, RX VrefLevel [Byte0]: 32
7776 23:11:19.301973 [Byte1]: 32
7777 23:11:19.306363
7778 23:11:19.306447 Set Vref, RX VrefLevel [Byte0]: 33
7779 23:11:19.309832 [Byte1]: 33
7780 23:11:19.314057
7781 23:11:19.314141 Set Vref, RX VrefLevel [Byte0]: 34
7782 23:11:19.317493 [Byte1]: 34
7783 23:11:19.321991
7784 23:11:19.322075 Set Vref, RX VrefLevel [Byte0]: 35
7785 23:11:19.325103 [Byte1]: 35
7786 23:11:19.329130
7787 23:11:19.329214 Set Vref, RX VrefLevel [Byte0]: 36
7788 23:11:19.332649 [Byte1]: 36
7789 23:11:19.336739
7790 23:11:19.336822 Set Vref, RX VrefLevel [Byte0]: 37
7791 23:11:19.340324 [Byte1]: 37
7792 23:11:19.344133
7793 23:11:19.344216 Set Vref, RX VrefLevel [Byte0]: 38
7794 23:11:19.347728 [Byte1]: 38
7795 23:11:19.351841
7796 23:11:19.351924 Set Vref, RX VrefLevel [Byte0]: 39
7797 23:11:19.354886 [Byte1]: 39
7798 23:11:19.359593
7799 23:11:19.359677 Set Vref, RX VrefLevel [Byte0]: 40
7800 23:11:19.363107 [Byte1]: 40
7801 23:11:19.366966
7802 23:11:19.367047 Set Vref, RX VrefLevel [Byte0]: 41
7803 23:11:19.370926 [Byte1]: 41
7804 23:11:19.374729
7805 23:11:19.374810 Set Vref, RX VrefLevel [Byte0]: 42
7806 23:11:19.377811 [Byte1]: 42
7807 23:11:19.381950
7808 23:11:19.382030 Set Vref, RX VrefLevel [Byte0]: 43
7809 23:11:19.385451 [Byte1]: 43
7810 23:11:19.389540
7811 23:11:19.389657 Set Vref, RX VrefLevel [Byte0]: 44
7812 23:11:19.393061 [Byte1]: 44
7813 23:11:19.397567
7814 23:11:19.397684 Set Vref, RX VrefLevel [Byte0]: 45
7815 23:11:19.400950 [Byte1]: 45
7816 23:11:19.404746
7817 23:11:19.404830 Set Vref, RX VrefLevel [Byte0]: 46
7818 23:11:19.408188 [Byte1]: 46
7819 23:11:19.412425
7820 23:11:19.412509 Set Vref, RX VrefLevel [Byte0]: 47
7821 23:11:19.415772 [Byte1]: 47
7822 23:11:19.420058
7823 23:11:19.420142 Set Vref, RX VrefLevel [Byte0]: 48
7824 23:11:19.423451 [Byte1]: 48
7825 23:11:19.427515
7826 23:11:19.427599 Set Vref, RX VrefLevel [Byte0]: 49
7827 23:11:19.431226 [Byte1]: 49
7828 23:11:19.435560
7829 23:11:19.435644 Set Vref, RX VrefLevel [Byte0]: 50
7830 23:11:19.441619 [Byte1]: 50
7831 23:11:19.441703
7832 23:11:19.445066 Set Vref, RX VrefLevel [Byte0]: 51
7833 23:11:19.448509 [Byte1]: 51
7834 23:11:19.448593
7835 23:11:19.452039 Set Vref, RX VrefLevel [Byte0]: 52
7836 23:11:19.454766 [Byte1]: 52
7837 23:11:19.454850
7838 23:11:19.458420 Set Vref, RX VrefLevel [Byte0]: 53
7839 23:11:19.461491 [Byte1]: 53
7840 23:11:19.465427
7841 23:11:19.465511 Set Vref, RX VrefLevel [Byte0]: 54
7842 23:11:19.468797 [Byte1]: 54
7843 23:11:19.473236
7844 23:11:19.473320 Set Vref, RX VrefLevel [Byte0]: 55
7845 23:11:19.476313 [Byte1]: 55
7846 23:11:19.480564
7847 23:11:19.480645 Set Vref, RX VrefLevel [Byte0]: 56
7848 23:11:19.484255 [Byte1]: 56
7849 23:11:19.487924
7850 23:11:19.488007 Set Vref, RX VrefLevel [Byte0]: 57
7851 23:11:19.491910 [Byte1]: 57
7852 23:11:19.495519
7853 23:11:19.495603 Set Vref, RX VrefLevel [Byte0]: 58
7854 23:11:19.498923 [Byte1]: 58
7855 23:11:19.503358
7856 23:11:19.503442 Set Vref, RX VrefLevel [Byte0]: 59
7857 23:11:19.506907 [Byte1]: 59
7858 23:11:19.510975
7859 23:11:19.511059 Set Vref, RX VrefLevel [Byte0]: 60
7860 23:11:19.514006 [Byte1]: 60
7861 23:11:19.518308
7862 23:11:19.518394 Set Vref, RX VrefLevel [Byte0]: 61
7863 23:11:19.521606 [Byte1]: 61
7864 23:11:19.526229
7865 23:11:19.526311 Set Vref, RX VrefLevel [Byte0]: 62
7866 23:11:19.529177 [Byte1]: 62
7867 23:11:19.533459
7868 23:11:19.533589 Set Vref, RX VrefLevel [Byte0]: 63
7869 23:11:19.537172 [Byte1]: 63
7870 23:11:19.541413
7871 23:11:19.541495 Set Vref, RX VrefLevel [Byte0]: 64
7872 23:11:19.544477 [Byte1]: 64
7873 23:11:19.548645
7874 23:11:19.548727 Set Vref, RX VrefLevel [Byte0]: 65
7875 23:11:19.551985 [Byte1]: 65
7876 23:11:19.556741
7877 23:11:19.556885 Set Vref, RX VrefLevel [Byte0]: 66
7878 23:11:19.559934 [Byte1]: 66
7879 23:11:19.564165
7880 23:11:19.564249 Set Vref, RX VrefLevel [Byte0]: 67
7881 23:11:19.567128 [Byte1]: 67
7882 23:11:19.571309
7883 23:11:19.571389 Set Vref, RX VrefLevel [Byte0]: 68
7884 23:11:19.575034 [Byte1]: 68
7885 23:11:19.579011
7886 23:11:19.579093 Set Vref, RX VrefLevel [Byte0]: 69
7887 23:11:19.582850 [Byte1]: 69
7888 23:11:19.586976
7889 23:11:19.587057 Set Vref, RX VrefLevel [Byte0]: 70
7890 23:11:19.590157 [Byte1]: 70
7891 23:11:19.594452
7892 23:11:19.594534 Set Vref, RX VrefLevel [Byte0]: 71
7893 23:11:19.597313 [Byte1]: 71
7894 23:11:19.602013
7895 23:11:19.602094 Set Vref, RX VrefLevel [Byte0]: 72
7896 23:11:19.605394 [Byte1]: 72
7897 23:11:19.609431
7898 23:11:19.609511 Set Vref, RX VrefLevel [Byte0]: 73
7899 23:11:19.612574 [Byte1]: 73
7900 23:11:19.617023
7901 23:11:19.617104 Set Vref, RX VrefLevel [Byte0]: 74
7902 23:11:19.620093 [Byte1]: 74
7903 23:11:19.624400
7904 23:11:19.624481 Set Vref, RX VrefLevel [Byte0]: 75
7905 23:11:19.627828 [Byte1]: 75
7906 23:11:19.631924
7907 23:11:19.632004 Set Vref, RX VrefLevel [Byte0]: 76
7908 23:11:19.635595 [Byte1]: 76
7909 23:11:19.639917
7910 23:11:19.639998 Final RX Vref Byte 0 = 57 to rank0
7911 23:11:19.642930 Final RX Vref Byte 1 = 59 to rank0
7912 23:11:19.646422 Final RX Vref Byte 0 = 57 to rank1
7913 23:11:19.649535 Final RX Vref Byte 1 = 59 to rank1==
7914 23:11:19.652766 Dram Type= 6, Freq= 0, CH_0, rank 0
7915 23:11:19.659626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7916 23:11:19.659708 ==
7917 23:11:19.659773 DQS Delay:
7918 23:11:19.659833 DQS0 = 0, DQS1 = 0
7919 23:11:19.663185 DQM Delay:
7920 23:11:19.663266 DQM0 = 134, DQM1 = 127
7921 23:11:19.665886 DQ Delay:
7922 23:11:19.669377 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7923 23:11:19.672636 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7924 23:11:19.675984 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7925 23:11:19.679773 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
7926 23:11:19.679855
7927 23:11:19.679919
7928 23:11:19.679978
7929 23:11:19.683020 [DramC_TX_OE_Calibration] TA2
7930 23:11:19.686405 Original DQ_B0 (3 6) =30, OEN = 27
7931 23:11:19.689956 Original DQ_B1 (3 6) =30, OEN = 27
7932 23:11:19.692805 24, 0x0, End_B0=24 End_B1=24
7933 23:11:19.692896 25, 0x0, End_B0=25 End_B1=25
7934 23:11:19.696634 26, 0x0, End_B0=26 End_B1=26
7935 23:11:19.699456 27, 0x0, End_B0=27 End_B1=27
7936 23:11:19.703189 28, 0x0, End_B0=28 End_B1=28
7937 23:11:19.703271 29, 0x0, End_B0=29 End_B1=29
7938 23:11:19.706071 30, 0x0, End_B0=30 End_B1=30
7939 23:11:19.709714 31, 0x4545, End_B0=30 End_B1=30
7940 23:11:19.713229 Byte0 end_step=30 best_step=27
7941 23:11:19.716372 Byte1 end_step=30 best_step=27
7942 23:11:19.719651 Byte0 TX OE(2T, 0.5T) = (3, 3)
7943 23:11:19.719733 Byte1 TX OE(2T, 0.5T) = (3, 3)
7944 23:11:19.719798
7945 23:11:19.722883
7946 23:11:19.729460 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
7947 23:11:19.733194 CH0 RK0: MR19=303, MR18=241F
7948 23:11:19.739724 CH0_RK0: MR19=0x303, MR18=0x241F, DQSOSC=391, MR23=63, INC=24, DEC=16
7949 23:11:19.739806
7950 23:11:19.743144 ----->DramcWriteLeveling(PI) begin...
7951 23:11:19.743231 ==
7952 23:11:19.745861 Dram Type= 6, Freq= 0, CH_0, rank 1
7953 23:11:19.749224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 23:11:19.749309 ==
7955 23:11:19.752837 Write leveling (Byte 0): 36 => 36
7956 23:11:19.756376 Write leveling (Byte 1): 30 => 30
7957 23:11:19.759225 DramcWriteLeveling(PI) end<-----
7958 23:11:19.759310
7959 23:11:19.759395 ==
7960 23:11:19.762617 Dram Type= 6, Freq= 0, CH_0, rank 1
7961 23:11:19.766447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7962 23:11:19.766531 ==
7963 23:11:19.769443 [Gating] SW mode calibration
7964 23:11:19.776224 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7965 23:11:19.782445 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7966 23:11:19.785738 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7967 23:11:19.789209 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 23:11:19.795822 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7969 23:11:19.799456 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7970 23:11:19.802466 1 4 16 | B1->B0 | 2e2e 3333 | 0 1 | (0 0) (1 1)
7971 23:11:19.809288 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7972 23:11:19.812774 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7973 23:11:19.816244 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7974 23:11:19.822679 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7975 23:11:19.826238 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
7976 23:11:19.829057 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7977 23:11:19.835920 1 5 12 | B1->B0 | 3434 3636 | 1 1 | (1 0) (1 0)
7978 23:11:19.839213 1 5 16 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (1 0)
7979 23:11:19.842553 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7980 23:11:19.849392 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7981 23:11:19.853137 1 5 28 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
7982 23:11:19.855704 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7983 23:11:19.862228 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7984 23:11:19.865911 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7985 23:11:19.868908 1 6 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7986 23:11:19.875539 1 6 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7987 23:11:19.879118 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7988 23:11:19.882416 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 23:11:19.886151 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 23:11:19.892582 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 23:11:19.895644 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 23:11:19.899061 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 23:11:19.905732 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 23:11:19.909072 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7995 23:11:19.912357 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 23:11:19.919153 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 23:11:19.922332 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 23:11:19.925429 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 23:11:19.932059 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 23:11:19.935133 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 23:11:19.938847 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 23:11:19.945332 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 23:11:19.948674 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 23:11:19.952395 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 23:11:19.959398 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 23:11:19.962386 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 23:11:19.965621 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 23:11:19.971885 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 23:11:19.975055 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8010 23:11:19.978854 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8011 23:11:19.985492 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 23:11:19.985600 Total UI for P1: 0, mck2ui 16
8013 23:11:19.992208 best dqsien dly found for B0: ( 1, 9, 14)
8014 23:11:19.992297 Total UI for P1: 0, mck2ui 16
8015 23:11:19.994948 best dqsien dly found for B1: ( 1, 9, 14)
8016 23:11:20.001815 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8017 23:11:20.004738 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8018 23:11:20.004819
8019 23:11:20.008517 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8020 23:11:20.012033 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8021 23:11:20.015014 [Gating] SW calibration Done
8022 23:11:20.015094 ==
8023 23:11:20.018559 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 23:11:20.021859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 23:11:20.021940 ==
8026 23:11:20.024903 RX Vref Scan: 0
8027 23:11:20.024985
8028 23:11:20.025049 RX Vref 0 -> 0, step: 1
8029 23:11:20.025109
8030 23:11:20.028529 RX Delay 0 -> 252, step: 8
8031 23:11:20.031287 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8032 23:11:20.037967 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8033 23:11:20.041465 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8034 23:11:20.045085 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8035 23:11:20.048206 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8036 23:11:20.051402 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8037 23:11:20.058077 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8038 23:11:20.061303 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8039 23:11:20.064641 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8040 23:11:20.068203 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8041 23:11:20.071545 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8042 23:11:20.077939 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8043 23:11:20.081812 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8044 23:11:20.084704 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8045 23:11:20.088105 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8046 23:11:20.091510 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8047 23:11:20.094630 ==
8048 23:11:20.094714 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 23:11:20.101428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 23:11:20.101513 ==
8051 23:11:20.101588 DQS Delay:
8052 23:11:20.104994 DQS0 = 0, DQS1 = 0
8053 23:11:20.105108 DQM Delay:
8054 23:11:20.107966 DQM0 = 136, DQM1 = 128
8055 23:11:20.108048 DQ Delay:
8056 23:11:20.111603 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8057 23:11:20.114956 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8058 23:11:20.118204 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8059 23:11:20.121206 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8060 23:11:20.121289
8061 23:11:20.121353
8062 23:11:20.121412 ==
8063 23:11:20.124431 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 23:11:20.131017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 23:11:20.131101 ==
8066 23:11:20.131168
8067 23:11:20.131229
8068 23:11:20.131287 TX Vref Scan disable
8069 23:11:20.134985 == TX Byte 0 ==
8070 23:11:20.138523 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8071 23:11:20.144611 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8072 23:11:20.144695 == TX Byte 1 ==
8073 23:11:20.148141 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8074 23:11:20.155049 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8075 23:11:20.155131 ==
8076 23:11:20.157958 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 23:11:20.161262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 23:11:20.161344 ==
8079 23:11:20.174472
8080 23:11:20.178070 TX Vref early break, caculate TX vref
8081 23:11:20.181084 TX Vref=16, minBit 1, minWin=23, winSum=389
8082 23:11:20.184002 TX Vref=18, minBit 1, minWin=23, winSum=394
8083 23:11:20.187634 TX Vref=20, minBit 1, minWin=23, winSum=405
8084 23:11:20.190671 TX Vref=22, minBit 0, minWin=24, winSum=412
8085 23:11:20.194245 TX Vref=24, minBit 1, minWin=25, winSum=421
8086 23:11:20.200837 TX Vref=26, minBit 4, minWin=25, winSum=428
8087 23:11:20.204541 TX Vref=28, minBit 0, minWin=25, winSum=424
8088 23:11:20.207475 TX Vref=30, minBit 4, minWin=25, winSum=421
8089 23:11:20.210711 TX Vref=32, minBit 0, minWin=25, winSum=411
8090 23:11:20.214138 TX Vref=34, minBit 0, minWin=24, winSum=399
8091 23:11:20.220828 [TxChooseVref] Worse bit 4, Min win 25, Win sum 428, Final Vref 26
8092 23:11:20.220911
8093 23:11:20.224163 Final TX Range 0 Vref 26
8094 23:11:20.224245
8095 23:11:20.224308 ==
8096 23:11:20.227228 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 23:11:20.230630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 23:11:20.230711 ==
8099 23:11:20.230776
8100 23:11:20.230836
8101 23:11:20.233964 TX Vref Scan disable
8102 23:11:20.240904 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8103 23:11:20.240986 == TX Byte 0 ==
8104 23:11:20.244154 u2DelayCellOfst[0]=13 cells (4 PI)
8105 23:11:20.247524 u2DelayCellOfst[1]=17 cells (5 PI)
8106 23:11:20.250640 u2DelayCellOfst[2]=13 cells (4 PI)
8107 23:11:20.254007 u2DelayCellOfst[3]=10 cells (3 PI)
8108 23:11:20.257650 u2DelayCellOfst[4]=13 cells (4 PI)
8109 23:11:20.260479 u2DelayCellOfst[5]=0 cells (0 PI)
8110 23:11:20.263996 u2DelayCellOfst[6]=17 cells (5 PI)
8111 23:11:20.267346 u2DelayCellOfst[7]=17 cells (5 PI)
8112 23:11:20.271130 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8113 23:11:20.273847 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8114 23:11:20.277212 == TX Byte 1 ==
8115 23:11:20.277293 u2DelayCellOfst[8]=3 cells (1 PI)
8116 23:11:20.280734 u2DelayCellOfst[9]=0 cells (0 PI)
8117 23:11:20.284517 u2DelayCellOfst[10]=6 cells (2 PI)
8118 23:11:20.287545 u2DelayCellOfst[11]=3 cells (1 PI)
8119 23:11:20.290502 u2DelayCellOfst[12]=10 cells (3 PI)
8120 23:11:20.294596 u2DelayCellOfst[13]=13 cells (4 PI)
8121 23:11:20.297385 u2DelayCellOfst[14]=17 cells (5 PI)
8122 23:11:20.301225 u2DelayCellOfst[15]=10 cells (3 PI)
8123 23:11:20.303829 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8124 23:11:20.310865 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8125 23:11:20.310948 DramC Write-DBI on
8126 23:11:20.311013 ==
8127 23:11:20.313922 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 23:11:20.317038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 23:11:20.317120 ==
8130 23:11:20.320719
8131 23:11:20.320800
8132 23:11:20.320870 TX Vref Scan disable
8133 23:11:20.324110 == TX Byte 0 ==
8134 23:11:20.327040 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8135 23:11:20.330886 == TX Byte 1 ==
8136 23:11:20.333888 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8137 23:11:20.337383 DramC Write-DBI off
8138 23:11:20.337466
8139 23:11:20.337530 [DATLAT]
8140 23:11:20.337616 Freq=1600, CH0 RK1
8141 23:11:20.337689
8142 23:11:20.340385 DATLAT Default: 0xf
8143 23:11:20.343920 0, 0xFFFF, sum = 0
8144 23:11:20.344003 1, 0xFFFF, sum = 0
8145 23:11:20.347043 2, 0xFFFF, sum = 0
8146 23:11:20.347125 3, 0xFFFF, sum = 0
8147 23:11:20.350684 4, 0xFFFF, sum = 0
8148 23:11:20.350766 5, 0xFFFF, sum = 0
8149 23:11:20.353549 6, 0xFFFF, sum = 0
8150 23:11:20.353652 7, 0xFFFF, sum = 0
8151 23:11:20.357054 8, 0xFFFF, sum = 0
8152 23:11:20.357136 9, 0xFFFF, sum = 0
8153 23:11:20.360618 10, 0xFFFF, sum = 0
8154 23:11:20.360700 11, 0xFFFF, sum = 0
8155 23:11:20.364394 12, 0xFFFF, sum = 0
8156 23:11:20.364475 13, 0xFFFF, sum = 0
8157 23:11:20.366914 14, 0x0, sum = 1
8158 23:11:20.366996 15, 0x0, sum = 2
8159 23:11:20.370309 16, 0x0, sum = 3
8160 23:11:20.370390 17, 0x0, sum = 4
8161 23:11:20.373909 best_step = 15
8162 23:11:20.373989
8163 23:11:20.374054 ==
8164 23:11:20.377105 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 23:11:20.380200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 23:11:20.380282 ==
8167 23:11:20.383741 RX Vref Scan: 0
8168 23:11:20.383821
8169 23:11:20.383885 RX Vref 0 -> 0, step: 1
8170 23:11:20.383945
8171 23:11:20.386859 RX Delay 19 -> 252, step: 4
8172 23:11:20.390608 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8173 23:11:20.397112 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8174 23:11:20.400471 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8175 23:11:20.403840 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8176 23:11:20.407436 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8177 23:11:20.410543 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8178 23:11:20.417036 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8179 23:11:20.420333 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8180 23:11:20.423671 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8181 23:11:20.427356 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8182 23:11:20.430325 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8183 23:11:20.437025 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8184 23:11:20.440007 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8185 23:11:20.443816 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8186 23:11:20.446815 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8187 23:11:20.450133 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8188 23:11:20.453352 ==
8189 23:11:20.456574 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 23:11:20.460118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 23:11:20.460200 ==
8192 23:11:20.460264 DQS Delay:
8193 23:11:20.463217 DQS0 = 0, DQS1 = 0
8194 23:11:20.463297 DQM Delay:
8195 23:11:20.467276 DQM0 = 135, DQM1 = 127
8196 23:11:20.467357 DQ Delay:
8197 23:11:20.469974 DQ0 =134, DQ1 =138, DQ2 =132, DQ3 =134
8198 23:11:20.473400 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8199 23:11:20.476455 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8200 23:11:20.479956 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8201 23:11:20.480038
8202 23:11:20.480103
8203 23:11:20.480164
8204 23:11:20.483647 [DramC_TX_OE_Calibration] TA2
8205 23:11:20.487036 Original DQ_B0 (3 6) =30, OEN = 27
8206 23:11:20.490017 Original DQ_B1 (3 6) =30, OEN = 27
8207 23:11:20.493504 24, 0x0, End_B0=24 End_B1=24
8208 23:11:20.497008 25, 0x0, End_B0=25 End_B1=25
8209 23:11:20.497091 26, 0x0, End_B0=26 End_B1=26
8210 23:11:20.499923 27, 0x0, End_B0=27 End_B1=27
8211 23:11:20.503501 28, 0x0, End_B0=28 End_B1=28
8212 23:11:20.506671 29, 0x0, End_B0=29 End_B1=29
8213 23:11:20.506754 30, 0x0, End_B0=30 End_B1=30
8214 23:11:20.510353 31, 0x4141, End_B0=30 End_B1=30
8215 23:11:20.513447 Byte0 end_step=30 best_step=27
8216 23:11:20.516765 Byte1 end_step=30 best_step=27
8217 23:11:20.519806 Byte0 TX OE(2T, 0.5T) = (3, 3)
8218 23:11:20.523389 Byte1 TX OE(2T, 0.5T) = (3, 3)
8219 23:11:20.523470
8220 23:11:20.523534
8221 23:11:20.530285 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
8222 23:11:20.533454 CH0 RK1: MR19=303, MR18=1F08
8223 23:11:20.539935 CH0_RK1: MR19=0x303, MR18=0x1F08, DQSOSC=394, MR23=63, INC=23, DEC=15
8224 23:11:20.543013 [RxdqsGatingPostProcess] freq 1600
8225 23:11:20.546907 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8226 23:11:20.549836 best DQS0 dly(2T, 0.5T) = (1, 1)
8227 23:11:20.553160 best DQS1 dly(2T, 0.5T) = (1, 1)
8228 23:11:20.556647 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8229 23:11:20.559828 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8230 23:11:20.563158 best DQS0 dly(2T, 0.5T) = (1, 1)
8231 23:11:20.566602 best DQS1 dly(2T, 0.5T) = (1, 1)
8232 23:11:20.570188 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8233 23:11:20.573138 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8234 23:11:20.576653 Pre-setting of DQS Precalculation
8235 23:11:20.579704 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8236 23:11:20.579786 ==
8237 23:11:20.583211 Dram Type= 6, Freq= 0, CH_1, rank 0
8238 23:11:20.586610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 23:11:20.589626 ==
8240 23:11:20.593118 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8241 23:11:20.596464 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8242 23:11:20.603582 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8243 23:11:20.609907 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8244 23:11:20.617176 [CA 0] Center 42 (12~72) winsize 61
8245 23:11:20.620851 [CA 1] Center 42 (13~72) winsize 60
8246 23:11:20.623526 [CA 2] Center 38 (9~68) winsize 60
8247 23:11:20.627073 [CA 3] Center 38 (10~67) winsize 58
8248 23:11:20.630521 [CA 4] Center 38 (9~68) winsize 60
8249 23:11:20.633901 [CA 5] Center 37 (8~67) winsize 60
8250 23:11:20.633982
8251 23:11:20.637088 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8252 23:11:20.637168
8253 23:11:20.640298 [CATrainingPosCal] consider 1 rank data
8254 23:11:20.643972 u2DelayCellTimex100 = 285/100 ps
8255 23:11:20.646750 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8256 23:11:20.653924 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8257 23:11:20.656880 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8258 23:11:20.660304 CA3 delay=38 (10~67),Diff = 1 PI (3 cell)
8259 23:11:20.663758 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8260 23:11:20.667154 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8261 23:11:20.667235
8262 23:11:20.670590 CA PerBit enable=1, Macro0, CA PI delay=37
8263 23:11:20.670708
8264 23:11:20.673858 [CBTSetCACLKResult] CA Dly = 37
8265 23:11:20.676683 CS Dly: 10 (0~41)
8266 23:11:20.680389 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8267 23:11:20.683733 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8268 23:11:20.683844 ==
8269 23:11:20.686734 Dram Type= 6, Freq= 0, CH_1, rank 1
8270 23:11:20.690300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8271 23:11:20.693271 ==
8272 23:11:20.696770 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8273 23:11:20.700127 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8274 23:11:20.706913 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8275 23:11:20.709846 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8276 23:11:20.720774 [CA 0] Center 42 (13~72) winsize 60
8277 23:11:20.723563 [CA 1] Center 41 (12~71) winsize 60
8278 23:11:20.727168 [CA 2] Center 38 (9~68) winsize 60
8279 23:11:20.730027 [CA 3] Center 37 (8~67) winsize 60
8280 23:11:20.733318 [CA 4] Center 38 (8~68) winsize 61
8281 23:11:20.737050 [CA 5] Center 37 (8~67) winsize 60
8282 23:11:20.737160
8283 23:11:20.740085 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8284 23:11:20.740196
8285 23:11:20.743330 [CATrainingPosCal] consider 2 rank data
8286 23:11:20.747004 u2DelayCellTimex100 = 285/100 ps
8287 23:11:20.749980 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8288 23:11:20.756907 CA1 delay=42 (13~71),Diff = 5 PI (17 cell)
8289 23:11:20.759970 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8290 23:11:20.763519 CA3 delay=38 (10~67),Diff = 1 PI (3 cell)
8291 23:11:20.766819 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8292 23:11:20.770451 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8293 23:11:20.770563
8294 23:11:20.773573 CA PerBit enable=1, Macro0, CA PI delay=37
8295 23:11:20.773722
8296 23:11:20.776618 [CBTSetCACLKResult] CA Dly = 37
8297 23:11:20.780319 CS Dly: 11 (0~44)
8298 23:11:20.783737 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8299 23:11:20.786773 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8300 23:11:20.786853
8301 23:11:20.790041 ----->DramcWriteLeveling(PI) begin...
8302 23:11:20.790123 ==
8303 23:11:20.793299 Dram Type= 6, Freq= 0, CH_1, rank 0
8304 23:11:20.800423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8305 23:11:20.800512 ==
8306 23:11:20.803465 Write leveling (Byte 0): 26 => 26
8307 23:11:20.803545 Write leveling (Byte 1): 26 => 26
8308 23:11:20.807171 DramcWriteLeveling(PI) end<-----
8309 23:11:20.807252
8310 23:11:20.807315 ==
8311 23:11:20.810122 Dram Type= 6, Freq= 0, CH_1, rank 0
8312 23:11:20.817006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 23:11:20.817117 ==
8314 23:11:20.820613 [Gating] SW mode calibration
8315 23:11:20.826700 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8316 23:11:20.829866 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8317 23:11:20.836675 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 23:11:20.840137 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 23:11:20.843526 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
8320 23:11:20.847030 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8321 23:11:20.853305 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 23:11:20.856707 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 23:11:20.860496 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 23:11:20.866853 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 23:11:20.869882 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 23:11:20.873255 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8327 23:11:20.880111 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
8328 23:11:20.883346 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (1 0)
8329 23:11:20.886447 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 23:11:20.893217 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 23:11:20.896716 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 23:11:20.900459 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 23:11:20.906550 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 23:11:20.909733 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 23:11:20.912835 1 6 8 | B1->B0 | 2626 4242 | 0 0 | (0 0) (0 0)
8336 23:11:20.920126 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 23:11:20.923220 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 23:11:20.926720 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 23:11:20.933389 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 23:11:20.936457 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 23:11:20.939414 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 23:11:20.946468 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 23:11:20.949475 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8344 23:11:20.952819 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8345 23:11:20.959398 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 23:11:20.962777 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 23:11:20.966037 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 23:11:20.972669 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 23:11:20.975831 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 23:11:20.979309 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 23:11:20.986109 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 23:11:20.989129 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 23:11:20.992465 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 23:11:20.999275 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 23:11:21.002447 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 23:11:21.006007 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 23:11:21.012413 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 23:11:21.015761 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 23:11:21.019384 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8360 23:11:21.023000 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8361 23:11:21.029170 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 23:11:21.032537 Total UI for P1: 0, mck2ui 16
8363 23:11:21.035939 best dqsien dly found for B0: ( 1, 9, 10)
8364 23:11:21.039230 Total UI for P1: 0, mck2ui 16
8365 23:11:21.043001 best dqsien dly found for B1: ( 1, 9, 10)
8366 23:11:21.046187 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8367 23:11:21.049439 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8368 23:11:21.049523
8369 23:11:21.052611 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8370 23:11:21.056004 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8371 23:11:21.059407 [Gating] SW calibration Done
8372 23:11:21.059492 ==
8373 23:11:21.062369 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 23:11:21.066112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 23:11:21.066223 ==
8376 23:11:21.069462 RX Vref Scan: 0
8377 23:11:21.069573
8378 23:11:21.069715 RX Vref 0 -> 0, step: 1
8379 23:11:21.072856
8380 23:11:21.072969 RX Delay 0 -> 252, step: 8
8381 23:11:21.076326 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8382 23:11:21.082613 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8383 23:11:21.086312 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8384 23:11:21.088920 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8385 23:11:21.092673 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8386 23:11:21.096249 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8387 23:11:21.102072 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8388 23:11:21.105430 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8389 23:11:21.108810 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8390 23:11:21.112415 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8391 23:11:21.115607 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8392 23:11:21.122311 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8393 23:11:21.125509 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8394 23:11:21.128953 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8395 23:11:21.132194 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8396 23:11:21.139517 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8397 23:11:21.139636 ==
8398 23:11:21.142430 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 23:11:21.145994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 23:11:21.146107 ==
8401 23:11:21.146207 DQS Delay:
8402 23:11:21.149019 DQS0 = 0, DQS1 = 0
8403 23:11:21.149130 DQM Delay:
8404 23:11:21.152556 DQM0 = 135, DQM1 = 132
8405 23:11:21.152664 DQ Delay:
8406 23:11:21.155423 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8407 23:11:21.158781 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8408 23:11:21.162804 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8409 23:11:21.165329 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8410 23:11:21.165413
8411 23:11:21.165477
8412 23:11:21.165538 ==
8413 23:11:21.169013 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 23:11:21.176285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 23:11:21.176372 ==
8416 23:11:21.176459
8417 23:11:21.176541
8418 23:11:21.176621 TX Vref Scan disable
8419 23:11:21.179214 == TX Byte 0 ==
8420 23:11:21.182474 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8421 23:11:21.189184 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8422 23:11:21.189268 == TX Byte 1 ==
8423 23:11:21.192281 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8424 23:11:21.199015 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8425 23:11:21.199100 ==
8426 23:11:21.202493 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 23:11:21.206173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 23:11:21.206254 ==
8429 23:11:21.217791
8430 23:11:21.221355 TX Vref early break, caculate TX vref
8431 23:11:21.224200 TX Vref=16, minBit 1, minWin=22, winSum=380
8432 23:11:21.227537 TX Vref=18, minBit 1, minWin=23, winSum=390
8433 23:11:21.230940 TX Vref=20, minBit 0, minWin=24, winSum=402
8434 23:11:21.234508 TX Vref=22, minBit 0, minWin=25, winSum=410
8435 23:11:21.237638 TX Vref=24, minBit 0, minWin=25, winSum=423
8436 23:11:21.244248 TX Vref=26, minBit 1, minWin=25, winSum=423
8437 23:11:21.247415 TX Vref=28, minBit 0, minWin=25, winSum=428
8438 23:11:21.251231 TX Vref=30, minBit 0, minWin=25, winSum=424
8439 23:11:21.254621 TX Vref=32, minBit 0, minWin=24, winSum=413
8440 23:11:21.257517 TX Vref=34, minBit 2, minWin=23, winSum=401
8441 23:11:21.264012 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
8442 23:11:21.264096
8443 23:11:21.267879 Final TX Range 0 Vref 28
8444 23:11:21.267988
8445 23:11:21.268067 ==
8446 23:11:21.270723 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 23:11:21.274037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 23:11:21.274120 ==
8449 23:11:21.274186
8450 23:11:21.274245
8451 23:11:21.277446 TX Vref Scan disable
8452 23:11:21.284110 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8453 23:11:21.284196 == TX Byte 0 ==
8454 23:11:21.287545 u2DelayCellOfst[0]=20 cells (6 PI)
8455 23:11:21.291097 u2DelayCellOfst[1]=13 cells (4 PI)
8456 23:11:21.293815 u2DelayCellOfst[2]=0 cells (0 PI)
8457 23:11:21.297219 u2DelayCellOfst[3]=10 cells (3 PI)
8458 23:11:21.300590 u2DelayCellOfst[4]=13 cells (4 PI)
8459 23:11:21.304308 u2DelayCellOfst[5]=20 cells (6 PI)
8460 23:11:21.307510 u2DelayCellOfst[6]=20 cells (6 PI)
8461 23:11:21.307593 u2DelayCellOfst[7]=6 cells (2 PI)
8462 23:11:21.313771 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8463 23:11:21.317148 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8464 23:11:21.317230 == TX Byte 1 ==
8465 23:11:21.320455 u2DelayCellOfst[8]=0 cells (0 PI)
8466 23:11:21.324031 u2DelayCellOfst[9]=3 cells (1 PI)
8467 23:11:21.327239 u2DelayCellOfst[10]=13 cells (4 PI)
8468 23:11:21.330300 u2DelayCellOfst[11]=3 cells (1 PI)
8469 23:11:21.333810 u2DelayCellOfst[12]=17 cells (5 PI)
8470 23:11:21.337230 u2DelayCellOfst[13]=17 cells (5 PI)
8471 23:11:21.340599 u2DelayCellOfst[14]=20 cells (6 PI)
8472 23:11:21.343582 u2DelayCellOfst[15]=17 cells (5 PI)
8473 23:11:21.346962 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8474 23:11:21.353848 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8475 23:11:21.353994 DramC Write-DBI on
8476 23:11:21.354062 ==
8477 23:11:21.357059 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 23:11:21.360379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 23:11:21.363570 ==
8480 23:11:21.363650
8481 23:11:21.363715
8482 23:11:21.363774 TX Vref Scan disable
8483 23:11:21.366910 == TX Byte 0 ==
8484 23:11:21.370507 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8485 23:11:21.373376 == TX Byte 1 ==
8486 23:11:21.377234 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8487 23:11:21.380844 DramC Write-DBI off
8488 23:11:21.380924
8489 23:11:21.380989 [DATLAT]
8490 23:11:21.381049 Freq=1600, CH1 RK0
8491 23:11:21.381107
8492 23:11:21.383819 DATLAT Default: 0xf
8493 23:11:21.383899 0, 0xFFFF, sum = 0
8494 23:11:21.387208 1, 0xFFFF, sum = 0
8495 23:11:21.387290 2, 0xFFFF, sum = 0
8496 23:11:21.390222 3, 0xFFFF, sum = 0
8497 23:11:21.394513 4, 0xFFFF, sum = 0
8498 23:11:21.394624 5, 0xFFFF, sum = 0
8499 23:11:21.397860 6, 0xFFFF, sum = 0
8500 23:11:21.397943 7, 0xFFFF, sum = 0
8501 23:11:21.400271 8, 0xFFFF, sum = 0
8502 23:11:21.400352 9, 0xFFFF, sum = 0
8503 23:11:21.403366 10, 0xFFFF, sum = 0
8504 23:11:21.403448 11, 0xFFFF, sum = 0
8505 23:11:21.407045 12, 0xFFFF, sum = 0
8506 23:11:21.407127 13, 0xFFFF, sum = 0
8507 23:11:21.410443 14, 0x0, sum = 1
8508 23:11:21.410537 15, 0x0, sum = 2
8509 23:11:21.413546 16, 0x0, sum = 3
8510 23:11:21.413684 17, 0x0, sum = 4
8511 23:11:21.416877 best_step = 15
8512 23:11:21.416961
8513 23:11:21.417047 ==
8514 23:11:21.420290 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 23:11:21.423484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 23:11:21.423569 ==
8517 23:11:21.423658 RX Vref Scan: 1
8518 23:11:21.427105
8519 23:11:21.427188 Set Vref Range= 24 -> 127
8520 23:11:21.427274
8521 23:11:21.430346 RX Vref 24 -> 127, step: 1
8522 23:11:21.430430
8523 23:11:21.433511 RX Delay 27 -> 252, step: 4
8524 23:11:21.433637
8525 23:11:21.437275 Set Vref, RX VrefLevel [Byte0]: 24
8526 23:11:21.440260 [Byte1]: 24
8527 23:11:21.440345
8528 23:11:21.443663 Set Vref, RX VrefLevel [Byte0]: 25
8529 23:11:21.447052 [Byte1]: 25
8530 23:11:21.447136
8531 23:11:21.449992 Set Vref, RX VrefLevel [Byte0]: 26
8532 23:11:21.453381 [Byte1]: 26
8533 23:11:21.457121
8534 23:11:21.457205 Set Vref, RX VrefLevel [Byte0]: 27
8535 23:11:21.460674 [Byte1]: 27
8536 23:11:21.465079
8537 23:11:21.465163 Set Vref, RX VrefLevel [Byte0]: 28
8538 23:11:21.467981 [Byte1]: 28
8539 23:11:21.472703
8540 23:11:21.472787 Set Vref, RX VrefLevel [Byte0]: 29
8541 23:11:21.475546 [Byte1]: 29
8542 23:11:21.479458
8543 23:11:21.479542 Set Vref, RX VrefLevel [Byte0]: 30
8544 23:11:21.483105 [Byte1]: 30
8545 23:11:21.487414
8546 23:11:21.487498 Set Vref, RX VrefLevel [Byte0]: 31
8547 23:11:21.490666 [Byte1]: 31
8548 23:11:21.495280
8549 23:11:21.495365 Set Vref, RX VrefLevel [Byte0]: 32
8550 23:11:21.497886 [Byte1]: 32
8551 23:11:21.502680
8552 23:11:21.502764 Set Vref, RX VrefLevel [Byte0]: 33
8553 23:11:21.505733 [Byte1]: 33
8554 23:11:21.510003
8555 23:11:21.510087 Set Vref, RX VrefLevel [Byte0]: 34
8556 23:11:21.516492 [Byte1]: 34
8557 23:11:21.516580
8558 23:11:21.519506 Set Vref, RX VrefLevel [Byte0]: 35
8559 23:11:21.523069 [Byte1]: 35
8560 23:11:21.523153
8561 23:11:21.526422 Set Vref, RX VrefLevel [Byte0]: 36
8562 23:11:21.529295 [Byte1]: 36
8563 23:11:21.529403
8564 23:11:21.532909 Set Vref, RX VrefLevel [Byte0]: 37
8565 23:11:21.536359 [Byte1]: 37
8566 23:11:21.540099
8567 23:11:21.540183 Set Vref, RX VrefLevel [Byte0]: 38
8568 23:11:21.543269 [Byte1]: 38
8569 23:11:21.547625
8570 23:11:21.547708 Set Vref, RX VrefLevel [Byte0]: 39
8571 23:11:21.550930 [Byte1]: 39
8572 23:11:21.555258
8573 23:11:21.555343 Set Vref, RX VrefLevel [Byte0]: 40
8574 23:11:21.558809 [Byte1]: 40
8575 23:11:21.562732
8576 23:11:21.562860 Set Vref, RX VrefLevel [Byte0]: 41
8577 23:11:21.565684 [Byte1]: 41
8578 23:11:21.570065
8579 23:11:21.570166 Set Vref, RX VrefLevel [Byte0]: 42
8580 23:11:21.573327 [Byte1]: 42
8581 23:11:21.577811
8582 23:11:21.577898 Set Vref, RX VrefLevel [Byte0]: 43
8583 23:11:21.581540 [Byte1]: 43
8584 23:11:21.585424
8585 23:11:21.585511 Set Vref, RX VrefLevel [Byte0]: 44
8586 23:11:21.588170 [Byte1]: 44
8587 23:11:21.593417
8588 23:11:21.593498 Set Vref, RX VrefLevel [Byte0]: 45
8589 23:11:21.596028 [Byte1]: 45
8590 23:11:21.600195
8591 23:11:21.600282 Set Vref, RX VrefLevel [Byte0]: 46
8592 23:11:21.603581 [Byte1]: 46
8593 23:11:21.607935
8594 23:11:21.608045 Set Vref, RX VrefLevel [Byte0]: 47
8595 23:11:21.611227 [Byte1]: 47
8596 23:11:21.615189
8597 23:11:21.615277 Set Vref, RX VrefLevel [Byte0]: 48
8598 23:11:21.618590 [Byte1]: 48
8599 23:11:21.622764
8600 23:11:21.622848 Set Vref, RX VrefLevel [Byte0]: 49
8601 23:11:21.626423 [Byte1]: 49
8602 23:11:21.630461
8603 23:11:21.630545 Set Vref, RX VrefLevel [Byte0]: 50
8604 23:11:21.634103 [Byte1]: 50
8605 23:11:21.638364
8606 23:11:21.638447 Set Vref, RX VrefLevel [Byte0]: 51
8607 23:11:21.641227 [Byte1]: 51
8608 23:11:21.645694
8609 23:11:21.645777 Set Vref, RX VrefLevel [Byte0]: 52
8610 23:11:21.648771 [Byte1]: 52
8611 23:11:21.652918
8612 23:11:21.653002 Set Vref, RX VrefLevel [Byte0]: 53
8613 23:11:21.656100 [Byte1]: 53
8614 23:11:21.660265
8615 23:11:21.660349 Set Vref, RX VrefLevel [Byte0]: 54
8616 23:11:21.664242 [Byte1]: 54
8617 23:11:21.667819
8618 23:11:21.667902 Set Vref, RX VrefLevel [Byte0]: 55
8619 23:11:21.671168 [Byte1]: 55
8620 23:11:21.675462
8621 23:11:21.675546 Set Vref, RX VrefLevel [Byte0]: 56
8622 23:11:21.679113 [Byte1]: 56
8623 23:11:21.683377
8624 23:11:21.683462 Set Vref, RX VrefLevel [Byte0]: 57
8625 23:11:21.686571 [Byte1]: 57
8626 23:11:21.690360
8627 23:11:21.690444 Set Vref, RX VrefLevel [Byte0]: 58
8628 23:11:21.693806 [Byte1]: 58
8629 23:11:21.698226
8630 23:11:21.698311 Set Vref, RX VrefLevel [Byte0]: 59
8631 23:11:21.701288 [Byte1]: 59
8632 23:11:21.705645
8633 23:11:21.705730 Set Vref, RX VrefLevel [Byte0]: 60
8634 23:11:21.709093 [Byte1]: 60
8635 23:11:21.713012
8636 23:11:21.713096 Set Vref, RX VrefLevel [Byte0]: 61
8637 23:11:21.716491 [Byte1]: 61
8638 23:11:21.720643
8639 23:11:21.720727 Set Vref, RX VrefLevel [Byte0]: 62
8640 23:11:21.723912 [Byte1]: 62
8641 23:11:21.728353
8642 23:11:21.728437 Set Vref, RX VrefLevel [Byte0]: 63
8643 23:11:21.734543 [Byte1]: 63
8644 23:11:21.734627
8645 23:11:21.738160 Set Vref, RX VrefLevel [Byte0]: 64
8646 23:11:21.741700 [Byte1]: 64
8647 23:11:21.741784
8648 23:11:21.745178 Set Vref, RX VrefLevel [Byte0]: 65
8649 23:11:21.748313 [Byte1]: 65
8650 23:11:21.748398
8651 23:11:21.751067 Set Vref, RX VrefLevel [Byte0]: 66
8652 23:11:21.754914 [Byte1]: 66
8653 23:11:21.758794
8654 23:11:21.758877 Set Vref, RX VrefLevel [Byte0]: 67
8655 23:11:21.761476 [Byte1]: 67
8656 23:11:21.766235
8657 23:11:21.766318 Set Vref, RX VrefLevel [Byte0]: 68
8658 23:11:21.769090 [Byte1]: 68
8659 23:11:21.773290
8660 23:11:21.773369 Set Vref, RX VrefLevel [Byte0]: 69
8661 23:11:21.776883 [Byte1]: 69
8662 23:11:21.781192
8663 23:11:21.781275 Set Vref, RX VrefLevel [Byte0]: 70
8664 23:11:21.784335 [Byte1]: 70
8665 23:11:21.788441
8666 23:11:21.788521 Set Vref, RX VrefLevel [Byte0]: 71
8667 23:11:21.792255 [Byte1]: 71
8668 23:11:21.796048
8669 23:11:21.796129 Set Vref, RX VrefLevel [Byte0]: 72
8670 23:11:21.799204 [Byte1]: 72
8671 23:11:21.803567
8672 23:11:21.803646 Set Vref, RX VrefLevel [Byte0]: 73
8673 23:11:21.806774 [Byte1]: 73
8674 23:11:21.811001
8675 23:11:21.811082 Set Vref, RX VrefLevel [Byte0]: 74
8676 23:11:21.814497 [Byte1]: 74
8677 23:11:21.818639
8678 23:11:21.818719 Set Vref, RX VrefLevel [Byte0]: 75
8679 23:11:21.822188 [Byte1]: 75
8680 23:11:21.826123
8681 23:11:21.826203 Set Vref, RX VrefLevel [Byte0]: 76
8682 23:11:21.829864 [Byte1]: 76
8683 23:11:21.833975
8684 23:11:21.834055 Set Vref, RX VrefLevel [Byte0]: 77
8685 23:11:21.836983 [Byte1]: 77
8686 23:11:21.841319
8687 23:11:21.841399 Final RX Vref Byte 0 = 57 to rank0
8688 23:11:21.844405 Final RX Vref Byte 1 = 51 to rank0
8689 23:11:21.847823 Final RX Vref Byte 0 = 57 to rank1
8690 23:11:21.850880 Final RX Vref Byte 1 = 51 to rank1==
8691 23:11:21.854536 Dram Type= 6, Freq= 0, CH_1, rank 0
8692 23:11:21.860940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8693 23:11:21.861022 ==
8694 23:11:21.861087 DQS Delay:
8695 23:11:21.864471 DQS0 = 0, DQS1 = 0
8696 23:11:21.864551 DQM Delay:
8697 23:11:21.864615 DQM0 = 134, DQM1 = 130
8698 23:11:21.867930 DQ Delay:
8699 23:11:21.870820 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8700 23:11:21.874553 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8701 23:11:21.878130 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8702 23:11:21.880980 DQ12 =136, DQ13 =136, DQ14 =140, DQ15 =140
8703 23:11:21.881061
8704 23:11:21.881124
8705 23:11:21.881183
8706 23:11:21.884248 [DramC_TX_OE_Calibration] TA2
8707 23:11:21.888215 Original DQ_B0 (3 6) =30, OEN = 27
8708 23:11:21.890942 Original DQ_B1 (3 6) =30, OEN = 27
8709 23:11:21.894272 24, 0x0, End_B0=24 End_B1=24
8710 23:11:21.894354 25, 0x0, End_B0=25 End_B1=25
8711 23:11:21.897598 26, 0x0, End_B0=26 End_B1=26
8712 23:11:21.901508 27, 0x0, End_B0=27 End_B1=27
8713 23:11:21.904576 28, 0x0, End_B0=28 End_B1=28
8714 23:11:21.907858 29, 0x0, End_B0=29 End_B1=29
8715 23:11:21.907940 30, 0x0, End_B0=30 End_B1=30
8716 23:11:21.910913 31, 0x4141, End_B0=30 End_B1=30
8717 23:11:21.914469 Byte0 end_step=30 best_step=27
8718 23:11:21.917475 Byte1 end_step=30 best_step=27
8719 23:11:21.921163 Byte0 TX OE(2T, 0.5T) = (3, 3)
8720 23:11:21.923930 Byte1 TX OE(2T, 0.5T) = (3, 3)
8721 23:11:21.924010
8722 23:11:21.924073
8723 23:11:21.931053 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8724 23:11:21.933838 CH1 RK0: MR19=303, MR18=1523
8725 23:11:21.940657 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8726 23:11:21.940739
8727 23:11:21.944031 ----->DramcWriteLeveling(PI) begin...
8728 23:11:21.944113 ==
8729 23:11:21.947329 Dram Type= 6, Freq= 0, CH_1, rank 1
8730 23:11:21.950771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8731 23:11:21.950873 ==
8732 23:11:21.953827 Write leveling (Byte 0): 25 => 25
8733 23:11:21.957562 Write leveling (Byte 1): 28 => 28
8734 23:11:21.960818 DramcWriteLeveling(PI) end<-----
8735 23:11:21.960899
8736 23:11:21.960963 ==
8737 23:11:21.964218 Dram Type= 6, Freq= 0, CH_1, rank 1
8738 23:11:21.967452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8739 23:11:21.967533 ==
8740 23:11:21.970498 [Gating] SW mode calibration
8741 23:11:21.977171 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8742 23:11:21.984042 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8743 23:11:21.987322 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 23:11:21.990956 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 23:11:21.997177 1 4 8 | B1->B0 | 2b2b 2323 | 1 0 | (1 1) (0 0)
8746 23:11:22.000581 1 4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
8747 23:11:22.004320 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 23:11:22.011011 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 23:11:22.013891 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 23:11:22.017349 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 23:11:22.023858 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 23:11:22.027277 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8753 23:11:22.030866 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
8754 23:11:22.037297 1 5 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8755 23:11:22.040553 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 23:11:22.043871 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 23:11:22.050708 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 23:11:22.053803 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 23:11:22.057195 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 23:11:22.063860 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 23:11:22.067171 1 6 8 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8762 23:11:22.070871 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 23:11:22.077447 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 23:11:22.080285 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 23:11:22.084103 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 23:11:22.090476 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 23:11:22.094022 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 23:11:22.097086 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 23:11:22.100179 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8770 23:11:22.107014 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8771 23:11:22.110453 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 23:11:22.113989 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 23:11:22.120546 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 23:11:22.123904 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 23:11:22.127246 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 23:11:22.133560 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 23:11:22.136995 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 23:11:22.140743 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 23:11:22.147074 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 23:11:22.150214 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 23:11:22.153583 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 23:11:22.160381 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 23:11:22.163965 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 23:11:22.166994 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8785 23:11:22.173932 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8786 23:11:22.176751 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8787 23:11:22.180383 Total UI for P1: 0, mck2ui 16
8788 23:11:22.183677 best dqsien dly found for B1: ( 1, 9, 6)
8789 23:11:22.186674 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 23:11:22.190305 Total UI for P1: 0, mck2ui 16
8791 23:11:22.193893 best dqsien dly found for B0: ( 1, 9, 12)
8792 23:11:22.196866 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8793 23:11:22.200407 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8794 23:11:22.200488
8795 23:11:22.203720 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8796 23:11:22.210252 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8797 23:11:22.210366 [Gating] SW calibration Done
8798 23:11:22.213274 ==
8799 23:11:22.213348 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 23:11:22.220153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 23:11:22.220232 ==
8802 23:11:22.220295 RX Vref Scan: 0
8803 23:11:22.220381
8804 23:11:22.223357 RX Vref 0 -> 0, step: 1
8805 23:11:22.223428
8806 23:11:22.226737 RX Delay 0 -> 252, step: 8
8807 23:11:22.229993 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8808 23:11:22.233135 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8809 23:11:22.236414 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8810 23:11:22.242923 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8811 23:11:22.246131 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8812 23:11:22.249897 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8813 23:11:22.252977 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8814 23:11:22.256216 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8815 23:11:22.262947 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8816 23:11:22.266844 iDelay=208, Bit 9, Center 123 (64 ~ 183) 120
8817 23:11:22.269678 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8818 23:11:22.272826 iDelay=208, Bit 11, Center 131 (80 ~ 183) 104
8819 23:11:22.277044 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8820 23:11:22.282907 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8821 23:11:22.286556 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8822 23:11:22.289446 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8823 23:11:22.289536 ==
8824 23:11:22.293356 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 23:11:22.296845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 23:11:22.296927 ==
8827 23:11:22.299492 DQS Delay:
8828 23:11:22.299572 DQS0 = 0, DQS1 = 0
8829 23:11:22.303191 DQM Delay:
8830 23:11:22.303271 DQM0 = 136, DQM1 = 134
8831 23:11:22.306448 DQ Delay:
8832 23:11:22.309977 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8833 23:11:22.312953 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8834 23:11:22.316619 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =131
8835 23:11:22.319595 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8836 23:11:22.319675
8837 23:11:22.319776
8838 23:11:22.319833 ==
8839 23:11:22.322767 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 23:11:22.326085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 23:11:22.326165 ==
8842 23:11:22.326228
8843 23:11:22.326287
8844 23:11:22.329446 TX Vref Scan disable
8845 23:11:22.332698 == TX Byte 0 ==
8846 23:11:22.336190 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8847 23:11:22.339517 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8848 23:11:22.342915 == TX Byte 1 ==
8849 23:11:22.346465 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8850 23:11:22.349539 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8851 23:11:22.349646 ==
8852 23:11:22.352997 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 23:11:22.359183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 23:11:22.359264 ==
8855 23:11:22.371748
8856 23:11:22.375471 TX Vref early break, caculate TX vref
8857 23:11:22.378118 TX Vref=16, minBit 0, minWin=23, winSum=382
8858 23:11:22.381788 TX Vref=18, minBit 0, minWin=23, winSum=393
8859 23:11:22.385072 TX Vref=20, minBit 0, minWin=24, winSum=402
8860 23:11:22.388722 TX Vref=22, minBit 0, minWin=24, winSum=409
8861 23:11:22.391651 TX Vref=24, minBit 0, minWin=25, winSum=417
8862 23:11:22.398174 TX Vref=26, minBit 0, minWin=25, winSum=425
8863 23:11:22.401499 TX Vref=28, minBit 0, minWin=25, winSum=423
8864 23:11:22.405080 TX Vref=30, minBit 6, minWin=25, winSum=422
8865 23:11:22.408851 TX Vref=32, minBit 0, minWin=25, winSum=412
8866 23:11:22.411545 TX Vref=34, minBit 0, minWin=23, winSum=405
8867 23:11:22.415172 TX Vref=36, minBit 0, minWin=23, winSum=394
8868 23:11:22.422093 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8869 23:11:22.422174
8870 23:11:22.424988 Final TX Range 0 Vref 26
8871 23:11:22.425069
8872 23:11:22.425134 ==
8873 23:11:22.428355 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 23:11:22.431275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 23:11:22.431356 ==
8876 23:11:22.431420
8877 23:11:22.431479
8878 23:11:22.435020 TX Vref Scan disable
8879 23:11:22.441673 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8880 23:11:22.441759 == TX Byte 0 ==
8881 23:11:22.444852 u2DelayCellOfst[0]=17 cells (5 PI)
8882 23:11:22.448228 u2DelayCellOfst[1]=10 cells (3 PI)
8883 23:11:22.451456 u2DelayCellOfst[2]=0 cells (0 PI)
8884 23:11:22.454897 u2DelayCellOfst[3]=6 cells (2 PI)
8885 23:11:22.458093 u2DelayCellOfst[4]=10 cells (3 PI)
8886 23:11:22.461341 u2DelayCellOfst[5]=17 cells (5 PI)
8887 23:11:22.464812 u2DelayCellOfst[6]=17 cells (5 PI)
8888 23:11:22.468033 u2DelayCellOfst[7]=6 cells (2 PI)
8889 23:11:22.471221 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8890 23:11:22.474943 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8891 23:11:22.477918 == TX Byte 1 ==
8892 23:11:22.481358 u2DelayCellOfst[8]=0 cells (0 PI)
8893 23:11:22.484346 u2DelayCellOfst[9]=3 cells (1 PI)
8894 23:11:22.484429 u2DelayCellOfst[10]=10 cells (3 PI)
8895 23:11:22.487761 u2DelayCellOfst[11]=3 cells (1 PI)
8896 23:11:22.491264 u2DelayCellOfst[12]=13 cells (4 PI)
8897 23:11:22.494584 u2DelayCellOfst[13]=17 cells (5 PI)
8898 23:11:22.498110 u2DelayCellOfst[14]=17 cells (5 PI)
8899 23:11:22.501345 u2DelayCellOfst[15]=17 cells (5 PI)
8900 23:11:22.504559 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8901 23:11:22.511131 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8902 23:11:22.511219 DramC Write-DBI on
8903 23:11:22.511284 ==
8904 23:11:22.514269 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 23:11:22.521196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 23:11:22.521281 ==
8907 23:11:22.521376
8908 23:11:22.521436
8909 23:11:22.521493 TX Vref Scan disable
8910 23:11:22.524856 == TX Byte 0 ==
8911 23:11:22.528417 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8912 23:11:22.531919 == TX Byte 1 ==
8913 23:11:22.535395 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8914 23:11:22.535478 DramC Write-DBI off
8915 23:11:22.538365
8916 23:11:22.538445 [DATLAT]
8917 23:11:22.538509 Freq=1600, CH1 RK1
8918 23:11:22.538569
8919 23:11:22.542079 DATLAT Default: 0xf
8920 23:11:22.542161 0, 0xFFFF, sum = 0
8921 23:11:22.545029 1, 0xFFFF, sum = 0
8922 23:11:22.548089 2, 0xFFFF, sum = 0
8923 23:11:22.548198 3, 0xFFFF, sum = 0
8924 23:11:22.551651 4, 0xFFFF, sum = 0
8925 23:11:22.551728 5, 0xFFFF, sum = 0
8926 23:11:22.554868 6, 0xFFFF, sum = 0
8927 23:11:22.554949 7, 0xFFFF, sum = 0
8928 23:11:22.557944 8, 0xFFFF, sum = 0
8929 23:11:22.558019 9, 0xFFFF, sum = 0
8930 23:11:22.561298 10, 0xFFFF, sum = 0
8931 23:11:22.561375 11, 0xFFFF, sum = 0
8932 23:11:22.565288 12, 0xFFFF, sum = 0
8933 23:11:22.565374 13, 0xFFFF, sum = 0
8934 23:11:22.567987 14, 0x0, sum = 1
8935 23:11:22.568087 15, 0x0, sum = 2
8936 23:11:22.571297 16, 0x0, sum = 3
8937 23:11:22.571394 17, 0x0, sum = 4
8938 23:11:22.574635 best_step = 15
8939 23:11:22.574718
8940 23:11:22.574796 ==
8941 23:11:22.578022 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 23:11:22.581342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 23:11:22.581426 ==
8944 23:11:22.581491 RX Vref Scan: 0
8945 23:11:22.584896
8946 23:11:22.584979 RX Vref 0 -> 0, step: 1
8947 23:11:22.585044
8948 23:11:22.588289 RX Delay 19 -> 252, step: 4
8949 23:11:22.591264 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8950 23:11:22.597974 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8951 23:11:22.601473 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8952 23:11:22.604811 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8953 23:11:22.608106 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8954 23:11:22.611431 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8955 23:11:22.614771 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8956 23:11:22.621254 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8957 23:11:22.625083 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8958 23:11:22.628705 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8959 23:11:22.631494 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8960 23:11:22.634862 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8961 23:11:22.641652 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8962 23:11:22.644598 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
8963 23:11:22.648079 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8964 23:11:22.651613 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
8965 23:11:22.651696 ==
8966 23:11:22.655101 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 23:11:22.661542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 23:11:22.661684 ==
8969 23:11:22.661751 DQS Delay:
8970 23:11:22.661812 DQS0 = 0, DQS1 = 0
8971 23:11:22.665321 DQM Delay:
8972 23:11:22.665402 DQM0 = 134, DQM1 = 131
8973 23:11:22.668094 DQ Delay:
8974 23:11:22.671388 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8975 23:11:22.674787 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8976 23:11:22.678570 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =126
8977 23:11:22.681317 DQ12 =140, DQ13 =136, DQ14 =136, DQ15 =142
8978 23:11:22.681403
8979 23:11:22.681507
8980 23:11:22.681603
8981 23:11:22.684543 [DramC_TX_OE_Calibration] TA2
8982 23:11:22.687812 Original DQ_B0 (3 6) =30, OEN = 27
8983 23:11:22.691812 Original DQ_B1 (3 6) =30, OEN = 27
8984 23:11:22.694618 24, 0x0, End_B0=24 End_B1=24
8985 23:11:22.694698 25, 0x0, End_B0=25 End_B1=25
8986 23:11:22.697906 26, 0x0, End_B0=26 End_B1=26
8987 23:11:22.701838 27, 0x0, End_B0=27 End_B1=27
8988 23:11:22.704895 28, 0x0, End_B0=28 End_B1=28
8989 23:11:22.704987 29, 0x0, End_B0=29 End_B1=29
8990 23:11:22.707765 30, 0x0, End_B0=30 End_B1=30
8991 23:11:22.711571 31, 0x4545, End_B0=30 End_B1=30
8992 23:11:22.714889 Byte0 end_step=30 best_step=27
8993 23:11:22.718119 Byte1 end_step=30 best_step=27
8994 23:11:22.720904 Byte0 TX OE(2T, 0.5T) = (3, 3)
8995 23:11:22.724697 Byte1 TX OE(2T, 0.5T) = (3, 3)
8996 23:11:22.724786
8997 23:11:22.724851
8998 23:11:22.731212 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
8999 23:11:22.734560 CH1 RK1: MR19=303, MR18=2409
9000 23:11:22.740991 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
9001 23:11:22.744482 [RxdqsGatingPostProcess] freq 1600
9002 23:11:22.747561 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9003 23:11:22.751241 best DQS0 dly(2T, 0.5T) = (1, 1)
9004 23:11:22.754682 best DQS1 dly(2T, 0.5T) = (1, 1)
9005 23:11:22.757480 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9006 23:11:22.760995 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9007 23:11:22.764369 best DQS0 dly(2T, 0.5T) = (1, 1)
9008 23:11:22.767970 best DQS1 dly(2T, 0.5T) = (1, 1)
9009 23:11:22.771085 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9010 23:11:22.774378 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9011 23:11:22.777498 Pre-setting of DQS Precalculation
9012 23:11:22.781030 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9013 23:11:22.787382 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9014 23:11:22.794560 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9015 23:11:22.794675
9016 23:11:22.797534
9017 23:11:22.797671 [Calibration Summary] 3200 Mbps
9018 23:11:22.801028 CH 0, Rank 0
9019 23:11:22.801116 SW Impedance : PASS
9020 23:11:22.804126 DUTY Scan : NO K
9021 23:11:22.808083 ZQ Calibration : PASS
9022 23:11:22.808172 Jitter Meter : NO K
9023 23:11:22.811034 CBT Training : PASS
9024 23:11:22.814271 Write leveling : PASS
9025 23:11:22.814359 RX DQS gating : PASS
9026 23:11:22.817782 RX DQ/DQS(RDDQC) : PASS
9027 23:11:22.820773 TX DQ/DQS : PASS
9028 23:11:22.820858 RX DATLAT : PASS
9029 23:11:22.824596 RX DQ/DQS(Engine): PASS
9030 23:11:22.827407 TX OE : PASS
9031 23:11:22.827492 All Pass.
9032 23:11:22.827556
9033 23:11:22.827617 CH 0, Rank 1
9034 23:11:22.830472 SW Impedance : PASS
9035 23:11:22.833868 DUTY Scan : NO K
9036 23:11:22.833952 ZQ Calibration : PASS
9037 23:11:22.837425 Jitter Meter : NO K
9038 23:11:22.840712 CBT Training : PASS
9039 23:11:22.840800 Write leveling : PASS
9040 23:11:22.844297 RX DQS gating : PASS
9041 23:11:22.844382 RX DQ/DQS(RDDQC) : PASS
9042 23:11:22.847397 TX DQ/DQS : PASS
9043 23:11:22.850456 RX DATLAT : PASS
9044 23:11:22.850544 RX DQ/DQS(Engine): PASS
9045 23:11:22.854049 TX OE : PASS
9046 23:11:22.854135 All Pass.
9047 23:11:22.854200
9048 23:11:22.856978 CH 1, Rank 0
9049 23:11:22.857063 SW Impedance : PASS
9050 23:11:22.860506 DUTY Scan : NO K
9051 23:11:22.863757 ZQ Calibration : PASS
9052 23:11:22.863843 Jitter Meter : NO K
9053 23:11:22.866964 CBT Training : PASS
9054 23:11:22.870384 Write leveling : PASS
9055 23:11:22.870475 RX DQS gating : PASS
9056 23:11:22.874082 RX DQ/DQS(RDDQC) : PASS
9057 23:11:22.877773 TX DQ/DQS : PASS
9058 23:11:22.877865 RX DATLAT : PASS
9059 23:11:22.880415 RX DQ/DQS(Engine): PASS
9060 23:11:22.883493 TX OE : PASS
9061 23:11:22.883581 All Pass.
9062 23:11:22.883646
9063 23:11:22.883707 CH 1, Rank 1
9064 23:11:22.887072 SW Impedance : PASS
9065 23:11:22.890303 DUTY Scan : NO K
9066 23:11:22.890391 ZQ Calibration : PASS
9067 23:11:22.893976 Jitter Meter : NO K
9068 23:11:22.894063 CBT Training : PASS
9069 23:11:22.897092 Write leveling : PASS
9070 23:11:22.900629 RX DQS gating : PASS
9071 23:11:22.900722 RX DQ/DQS(RDDQC) : PASS
9072 23:11:22.903540 TX DQ/DQS : PASS
9073 23:11:22.907080 RX DATLAT : PASS
9074 23:11:22.907168 RX DQ/DQS(Engine): PASS
9075 23:11:22.910705 TX OE : PASS
9076 23:11:22.910791 All Pass.
9077 23:11:22.910856
9078 23:11:22.913463 DramC Write-DBI on
9079 23:11:22.916850 PER_BANK_REFRESH: Hybrid Mode
9080 23:11:22.916937 TX_TRACKING: ON
9081 23:11:22.927022 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9082 23:11:22.933846 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9083 23:11:22.940699 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9084 23:11:22.943559 [FAST_K] Save calibration result to emmc
9085 23:11:22.947027 sync common calibartion params.
9086 23:11:22.950416 sync cbt_mode0:1, 1:1
9087 23:11:22.953994 dram_init: ddr_geometry: 2
9088 23:11:22.954081 dram_init: ddr_geometry: 2
9089 23:11:22.956904 dram_init: ddr_geometry: 2
9090 23:11:22.960266 0:dram_rank_size:100000000
9091 23:11:22.963659 1:dram_rank_size:100000000
9092 23:11:22.967018 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9093 23:11:22.970646 DFS_SHUFFLE_HW_MODE: ON
9094 23:11:22.973839 dramc_set_vcore_voltage set vcore to 725000
9095 23:11:22.977152 Read voltage for 1600, 0
9096 23:11:22.977240 Vio18 = 0
9097 23:11:22.977305 Vcore = 725000
9098 23:11:22.979994 Vdram = 0
9099 23:11:22.980078 Vddq = 0
9100 23:11:22.980143 Vmddr = 0
9101 23:11:22.983510 switch to 3200 Mbps bootup
9102 23:11:22.986829 [DramcRunTimeConfig]
9103 23:11:22.986916 PHYPLL
9104 23:11:22.986981 DPM_CONTROL_AFTERK: ON
9105 23:11:22.990006 PER_BANK_REFRESH: ON
9106 23:11:22.993910 REFRESH_OVERHEAD_REDUCTION: ON
9107 23:11:22.994001 CMD_PICG_NEW_MODE: OFF
9108 23:11:22.996836 XRTWTW_NEW_MODE: ON
9109 23:11:23.000146 XRTRTR_NEW_MODE: ON
9110 23:11:23.000238 TX_TRACKING: ON
9111 23:11:23.000304 RDSEL_TRACKING: OFF
9112 23:11:23.003583 DQS Precalculation for DVFS: ON
9113 23:11:23.007192 RX_TRACKING: OFF
9114 23:11:23.007286 HW_GATING DBG: ON
9115 23:11:23.010214 ZQCS_ENABLE_LP4: ON
9116 23:11:23.010301 RX_PICG_NEW_MODE: ON
9117 23:11:23.013567 TX_PICG_NEW_MODE: ON
9118 23:11:23.017041 ENABLE_RX_DCM_DPHY: ON
9119 23:11:23.019806 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9120 23:11:23.019892 DUMMY_READ_FOR_TRACKING: OFF
9121 23:11:23.023090 !!! SPM_CONTROL_AFTERK: OFF
9122 23:11:23.026431 !!! SPM could not control APHY
9123 23:11:23.029987 IMPEDANCE_TRACKING: ON
9124 23:11:23.030078 TEMP_SENSOR: ON
9125 23:11:23.033118 HW_SAVE_FOR_SR: OFF
9126 23:11:23.033202 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9127 23:11:23.040311 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9128 23:11:23.040417 Read ODT Tracking: ON
9129 23:11:23.043536 Refresh Rate DeBounce: ON
9130 23:11:23.043622 DFS_NO_QUEUE_FLUSH: ON
9131 23:11:23.046661 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9132 23:11:23.050222 ENABLE_DFS_RUNTIME_MRW: OFF
9133 23:11:23.053027 DDR_RESERVE_NEW_MODE: ON
9134 23:11:23.056338 MR_CBT_SWITCH_FREQ: ON
9135 23:11:23.056424 =========================
9136 23:11:23.075823 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9137 23:11:23.079094 dram_init: ddr_geometry: 2
9138 23:11:23.097447 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9139 23:11:23.100798 dram_init: dram init end (result: 0)
9140 23:11:23.107298 DRAM-K: Full calibration passed in 24455 msecs
9141 23:11:23.110580 MRC: failed to locate region type 0.
9142 23:11:23.110678 DRAM rank0 size:0x100000000,
9143 23:11:23.114104 DRAM rank1 size=0x100000000
9144 23:11:23.124076 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9145 23:11:23.130593 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9146 23:11:23.137293 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9147 23:11:23.143965 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9148 23:11:23.147523 DRAM rank0 size:0x100000000,
9149 23:11:23.150552 DRAM rank1 size=0x100000000
9150 23:11:23.150635 CBMEM:
9151 23:11:23.153933 IMD: root @ 0xfffff000 254 entries.
9152 23:11:23.157939 IMD: root @ 0xffffec00 62 entries.
9153 23:11:23.160650 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9154 23:11:23.164193 WARNING: RO_VPD is uninitialized or empty.
9155 23:11:23.170406 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9156 23:11:23.177309 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9157 23:11:23.190183 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9158 23:11:23.201865 BS: romstage times (exec / console): total (unknown) / 23985 ms
9159 23:11:23.201964
9160 23:11:23.202030
9161 23:11:23.211645 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9162 23:11:23.214674 ARM64: Exception handlers installed.
9163 23:11:23.218106 ARM64: Testing exception
9164 23:11:23.221702 ARM64: Done test exception
9165 23:11:23.221784 Enumerating buses...
9166 23:11:23.225316 Show all devs... Before device enumeration.
9167 23:11:23.228542 Root Device: enabled 1
9168 23:11:23.232330 CPU_CLUSTER: 0: enabled 1
9169 23:11:23.232411 CPU: 00: enabled 1
9170 23:11:23.235109 Compare with tree...
9171 23:11:23.235224 Root Device: enabled 1
9172 23:11:23.238348 CPU_CLUSTER: 0: enabled 1
9173 23:11:23.241586 CPU: 00: enabled 1
9174 23:11:23.241668 Root Device scanning...
9175 23:11:23.244792 scan_static_bus for Root Device
9176 23:11:23.248411 CPU_CLUSTER: 0 enabled
9177 23:11:23.251775 scan_static_bus for Root Device done
9178 23:11:23.255154 scan_bus: bus Root Device finished in 8 msecs
9179 23:11:23.255236 done
9180 23:11:23.261498 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9181 23:11:23.265157 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9182 23:11:23.271475 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9183 23:11:23.274966 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9184 23:11:23.277999 Allocating resources...
9185 23:11:23.281508 Reading resources...
9186 23:11:23.285286 Root Device read_resources bus 0 link: 0
9187 23:11:23.285393 DRAM rank0 size:0x100000000,
9188 23:11:23.288005 DRAM rank1 size=0x100000000
9189 23:11:23.291357 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9190 23:11:23.295004 CPU: 00 missing read_resources
9191 23:11:23.297806 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9192 23:11:23.304962 Root Device read_resources bus 0 link: 0 done
9193 23:11:23.305059 Done reading resources.
9194 23:11:23.311444 Show resources in subtree (Root Device)...After reading.
9195 23:11:23.314961 Root Device child on link 0 CPU_CLUSTER: 0
9196 23:11:23.318328 CPU_CLUSTER: 0 child on link 0 CPU: 00
9197 23:11:23.328140 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9198 23:11:23.328293 CPU: 00
9199 23:11:23.331432 Root Device assign_resources, bus 0 link: 0
9200 23:11:23.334726 CPU_CLUSTER: 0 missing set_resources
9201 23:11:23.338459 Root Device assign_resources, bus 0 link: 0 done
9202 23:11:23.342054 Done setting resources.
9203 23:11:23.348254 Show resources in subtree (Root Device)...After assigning values.
9204 23:11:23.351570 Root Device child on link 0 CPU_CLUSTER: 0
9205 23:11:23.354711 CPU_CLUSTER: 0 child on link 0 CPU: 00
9206 23:11:23.364625 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9207 23:11:23.364761 CPU: 00
9208 23:11:23.368492 Done allocating resources.
9209 23:11:23.371460 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9210 23:11:23.374534 Enabling resources...
9211 23:11:23.374664 done.
9212 23:11:23.381432 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9213 23:11:23.381566 Initializing devices...
9214 23:11:23.384571 Root Device init
9215 23:11:23.384701 init hardware done!
9216 23:11:23.387995 0x00000018: ctrlr->caps
9217 23:11:23.391701 52.000 MHz: ctrlr->f_max
9218 23:11:23.391833 0.400 MHz: ctrlr->f_min
9219 23:11:23.394400 0x40ff8080: ctrlr->voltages
9220 23:11:23.394529 sclk: 390625
9221 23:11:23.398192 Bus Width = 1
9222 23:11:23.398319 sclk: 390625
9223 23:11:23.398440 Bus Width = 1
9224 23:11:23.401571 Early init status = 3
9225 23:11:23.407641 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9226 23:11:23.411215 in-header: 03 fc 00 00 01 00 00 00
9227 23:11:23.411348 in-data: 00
9228 23:11:23.417836 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9229 23:11:23.421240 in-header: 03 fd 00 00 00 00 00 00
9230 23:11:23.421373 in-data:
9231 23:11:23.427757 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9232 23:11:23.430950 in-header: 03 fc 00 00 01 00 00 00
9233 23:11:23.434829 in-data: 00
9234 23:11:23.437481 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9235 23:11:23.441789 in-header: 03 fd 00 00 00 00 00 00
9236 23:11:23.444881 in-data:
9237 23:11:23.448072 [SSUSB] Setting up USB HOST controller...
9238 23:11:23.451737 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9239 23:11:23.454707 [SSUSB] phy power-on done.
9240 23:11:23.457894 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9241 23:11:23.465383 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9242 23:11:23.468864 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9243 23:11:23.474780 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9244 23:11:23.481308 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9245 23:11:23.488051 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9246 23:11:23.494491 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9247 23:11:23.501508 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9248 23:11:23.504438 SPM: binary array size = 0x9dc
9249 23:11:23.508025 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9250 23:11:23.514479 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9251 23:11:23.521500 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9252 23:11:23.525077 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9253 23:11:23.531002 configure_display: Starting display init
9254 23:11:23.565093 anx7625_power_on_init: Init interface.
9255 23:11:23.567965 anx7625_disable_pd_protocol: Disabled PD feature.
9256 23:11:23.571775 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9257 23:11:23.599311 anx7625_start_dp_work: Secure OCM version=00
9258 23:11:23.602979 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9259 23:11:23.617840 sp_tx_get_edid_block: EDID Block = 1
9260 23:11:23.720486 Extracted contents:
9261 23:11:23.723389 header: 00 ff ff ff ff ff ff 00
9262 23:11:23.726988 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9263 23:11:23.730334 version: 01 04
9264 23:11:23.733162 basic params: 95 1f 11 78 0a
9265 23:11:23.736828 chroma info: 76 90 94 55 54 90 27 21 50 54
9266 23:11:23.740329 established: 00 00 00
9267 23:11:23.746606 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9268 23:11:23.749862 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9269 23:11:23.756355 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9270 23:11:23.763207 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9271 23:11:23.770257 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9272 23:11:23.773303 extensions: 00
9273 23:11:23.773388 checksum: fb
9274 23:11:23.773453
9275 23:11:23.776525 Manufacturer: IVO Model 57d Serial Number 0
9276 23:11:23.779929 Made week 0 of 2020
9277 23:11:23.780010 EDID version: 1.4
9278 23:11:23.783276 Digital display
9279 23:11:23.786407 6 bits per primary color channel
9280 23:11:23.786490 DisplayPort interface
9281 23:11:23.789782 Maximum image size: 31 cm x 17 cm
9282 23:11:23.793376 Gamma: 220%
9283 23:11:23.793468 Check DPMS levels
9284 23:11:23.796303 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9285 23:11:23.799775 First detailed timing is preferred timing
9286 23:11:23.803241 Established timings supported:
9287 23:11:23.806336 Standard timings supported:
9288 23:11:23.809797 Detailed timings
9289 23:11:23.812839 Hex of detail: 383680a07038204018303c0035ae10000019
9290 23:11:23.816169 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9291 23:11:23.822812 0780 0798 07c8 0820 hborder 0
9292 23:11:23.826527 0438 043b 0447 0458 vborder 0
9293 23:11:23.829850 -hsync -vsync
9294 23:11:23.829948 Did detailed timing
9295 23:11:23.836119 Hex of detail: 000000000000000000000000000000000000
9296 23:11:23.836203 Manufacturer-specified data, tag 0
9297 23:11:23.842871 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9298 23:11:23.846173 ASCII string: InfoVision
9299 23:11:23.849474 Hex of detail: 000000fe00523134304e574635205248200a
9300 23:11:23.852631 ASCII string: R140NWF5 RH
9301 23:11:23.852717 Checksum
9302 23:11:23.855639 Checksum: 0xfb (valid)
9303 23:11:23.859225 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9304 23:11:23.862735 DSI data_rate: 832800000 bps
9305 23:11:23.869171 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9306 23:11:23.872573 anx7625_parse_edid: pixelclock(138800).
9307 23:11:23.875902 hactive(1920), hsync(48), hfp(24), hbp(88)
9308 23:11:23.879247 vactive(1080), vsync(12), vfp(3), vbp(17)
9309 23:11:23.882264 anx7625_dsi_config: config dsi.
9310 23:11:23.888774 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9311 23:11:23.902524 anx7625_dsi_config: success to config DSI
9312 23:11:23.905584 anx7625_dp_start: MIPI phy setup OK.
9313 23:11:23.908746 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9314 23:11:23.912549 mtk_ddp_mode_set invalid vrefresh 60
9315 23:11:23.915676 main_disp_path_setup
9316 23:11:23.915756 ovl_layer_smi_id_en
9317 23:11:23.918610 ovl_layer_smi_id_en
9318 23:11:23.918691 ccorr_config
9319 23:11:23.918754 aal_config
9320 23:11:23.921927 gamma_config
9321 23:11:23.922007 postmask_config
9322 23:11:23.925403 dither_config
9323 23:11:23.928636 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9324 23:11:23.935419 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9325 23:11:23.938657 Root Device init finished in 551 msecs
9326 23:11:23.941679 CPU_CLUSTER: 0 init
9327 23:11:23.948183 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9328 23:11:23.955410 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9329 23:11:23.955495 APU_MBOX 0x190000b0 = 0x10001
9330 23:11:23.958685 APU_MBOX 0x190001b0 = 0x10001
9331 23:11:23.961725 APU_MBOX 0x190005b0 = 0x10001
9332 23:11:23.965099 APU_MBOX 0x190006b0 = 0x10001
9333 23:11:23.971353 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9334 23:11:23.980953 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9335 23:11:23.993263 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9336 23:11:24.000242 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9337 23:11:24.011833 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9338 23:11:24.020848 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9339 23:11:24.024529 CPU_CLUSTER: 0 init finished in 81 msecs
9340 23:11:24.028196 Devices initialized
9341 23:11:24.030793 Show all devs... After init.
9342 23:11:24.030885 Root Device: enabled 1
9343 23:11:24.034411 CPU_CLUSTER: 0: enabled 1
9344 23:11:24.037775 CPU: 00: enabled 1
9345 23:11:24.040652 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9346 23:11:24.044542 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9347 23:11:24.047671 ELOG: NV offset 0x57f000 size 0x1000
9348 23:11:24.053985 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9349 23:11:24.060745 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9350 23:11:24.064221 ELOG: Event(17) added with size 13 at 2023-12-01 23:09:10 UTC
9351 23:11:24.067247 out: cmd=0x121: 03 db 21 01 00 00 00 00
9352 23:11:24.071358 in-header: 03 dc 00 00 2c 00 00 00
9353 23:11:24.084389 in-data: 83 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9354 23:11:24.091214 ELOG: Event(A1) added with size 10 at 2023-12-01 23:09:10 UTC
9355 23:11:24.097988 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9356 23:11:24.104157 ELOG: Event(A0) added with size 9 at 2023-12-01 23:09:10 UTC
9357 23:11:24.107700 elog_add_boot_reason: Logged dev mode boot
9358 23:11:24.110900 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9359 23:11:24.114297 Finalize devices...
9360 23:11:24.114378 Devices finalized
9361 23:11:24.120884 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9362 23:11:24.124545 Writing coreboot table at 0xffe64000
9363 23:11:24.127618 0. 000000000010a000-0000000000113fff: RAMSTAGE
9364 23:11:24.130676 1. 0000000040000000-00000000400fffff: RAM
9365 23:11:24.137523 2. 0000000040100000-000000004032afff: RAMSTAGE
9366 23:11:24.140750 3. 000000004032b000-00000000545fffff: RAM
9367 23:11:24.144360 4. 0000000054600000-000000005465ffff: BL31
9368 23:11:24.147220 5. 0000000054660000-00000000ffe63fff: RAM
9369 23:11:24.153551 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9370 23:11:24.157149 7. 0000000100000000-000000023fffffff: RAM
9371 23:11:24.160556 Passing 5 GPIOs to payload:
9372 23:11:24.163521 NAME | PORT | POLARITY | VALUE
9373 23:11:24.167018 EC in RW | 0x000000aa | low | undefined
9374 23:11:24.173894 EC interrupt | 0x00000005 | low | undefined
9375 23:11:24.177052 TPM interrupt | 0x000000ab | high | undefined
9376 23:11:24.183795 SD card detect | 0x00000011 | high | undefined
9377 23:11:24.187155 speaker enable | 0x00000093 | high | undefined
9378 23:11:24.190259 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9379 23:11:24.193617 in-header: 03 f9 00 00 02 00 00 00
9380 23:11:24.193712 in-data: 02 00
9381 23:11:24.196985 ADC[4]: Raw value=904357 ID=7
9382 23:11:24.200261 ADC[3]: Raw value=213810 ID=1
9383 23:11:24.203708 RAM Code: 0x71
9384 23:11:24.203805 ADC[6]: Raw value=75701 ID=0
9385 23:11:24.206879 ADC[5]: Raw value=212703 ID=1
9386 23:11:24.210323 SKU Code: 0x1
9387 23:11:24.213921 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum dbc0
9388 23:11:24.216871 coreboot table: 964 bytes.
9389 23:11:24.220630 IMD ROOT 0. 0xfffff000 0x00001000
9390 23:11:24.223389 IMD SMALL 1. 0xffffe000 0x00001000
9391 23:11:24.227368 RO MCACHE 2. 0xffffc000 0x00001104
9392 23:11:24.230439 CONSOLE 3. 0xfff7c000 0x00080000
9393 23:11:24.233536 FMAP 4. 0xfff7b000 0x00000452
9394 23:11:24.237012 TIME STAMP 5. 0xfff7a000 0x00000910
9395 23:11:24.240573 VBOOT WORK 6. 0xfff66000 0x00014000
9396 23:11:24.243536 RAMOOPS 7. 0xffe66000 0x00100000
9397 23:11:24.247351 COREBOOT 8. 0xffe64000 0x00002000
9398 23:11:24.247435 IMD small region:
9399 23:11:24.250334 IMD ROOT 0. 0xffffec00 0x00000400
9400 23:11:24.253795 VPD 1. 0xffffeb80 0x0000006c
9401 23:11:24.256945 MMC STATUS 2. 0xffffeb60 0x00000004
9402 23:11:24.263409 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9403 23:11:24.266998 Probing TPM: done!
9404 23:11:24.270557 Connected to device vid:did:rid of 1ae0:0028:00
9405 23:11:24.280098 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9406 23:11:24.283390 Initialized TPM device CR50 revision 0
9407 23:11:24.287327 Checking cr50 for pending updates
9408 23:11:24.290640 Reading cr50 TPM mode
9409 23:11:24.299087 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9410 23:11:24.305732 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9411 23:11:24.346015 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9412 23:11:24.349808 Checking segment from ROM address 0x40100000
9413 23:11:24.353247 Checking segment from ROM address 0x4010001c
9414 23:11:24.359372 Loading segment from ROM address 0x40100000
9415 23:11:24.359593 code (compression=0)
9416 23:11:24.369899 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9417 23:11:24.376324 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9418 23:11:24.376657 it's not compressed!
9419 23:11:24.382802 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9420 23:11:24.386452 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9421 23:11:24.407151 Loading segment from ROM address 0x4010001c
9422 23:11:24.407642 Entry Point 0x80000000
9423 23:11:24.410050 Loaded segments
9424 23:11:24.413689 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9425 23:11:24.420134 Jumping to boot code at 0x80000000(0xffe64000)
9426 23:11:24.426987 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9427 23:11:24.433410 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9428 23:11:24.441437 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9429 23:11:24.444482 Checking segment from ROM address 0x40100000
9430 23:11:24.447893 Checking segment from ROM address 0x4010001c
9431 23:11:24.454400 Loading segment from ROM address 0x40100000
9432 23:11:24.454912 code (compression=1)
9433 23:11:24.461190 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9434 23:11:24.470832 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9435 23:11:24.471376 using LZMA
9436 23:11:24.479353 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9437 23:11:24.486553 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9438 23:11:24.489633 Loading segment from ROM address 0x4010001c
9439 23:11:24.490164 Entry Point 0x54601000
9440 23:11:24.492967 Loaded segments
9441 23:11:24.496425 NOTICE: MT8192 bl31_setup
9442 23:11:24.503754 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9443 23:11:24.506217 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9444 23:11:24.509879 WARNING: region 0:
9445 23:11:24.513431 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9446 23:11:24.514012 WARNING: region 1:
9447 23:11:24.520241 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9448 23:11:24.523169 WARNING: region 2:
9449 23:11:24.526424 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9450 23:11:24.530030 WARNING: region 3:
9451 23:11:24.533625 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9452 23:11:24.536893 WARNING: region 4:
9453 23:11:24.540352 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9454 23:11:24.543287 WARNING: region 5:
9455 23:11:24.546770 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 23:11:24.549997 WARNING: region 6:
9457 23:11:24.553829 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 23:11:24.554397 WARNING: region 7:
9459 23:11:24.560117 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 23:11:24.566792 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9461 23:11:24.570111 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9462 23:11:24.573141 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9463 23:11:24.580123 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9464 23:11:24.583134 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9465 23:11:24.586605 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9466 23:11:24.593498 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9467 23:11:24.596720 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9468 23:11:24.600015 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9469 23:11:24.606533 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9470 23:11:24.609880 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9471 23:11:24.616781 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9472 23:11:24.620281 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9473 23:11:24.623531 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9474 23:11:24.629646 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9475 23:11:24.632726 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9476 23:11:24.636552 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9477 23:11:24.643334 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9478 23:11:24.646452 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9479 23:11:24.649823 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9480 23:11:24.656847 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9481 23:11:24.660492 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9482 23:11:24.666698 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9483 23:11:24.670016 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9484 23:11:24.676551 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9485 23:11:24.679991 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9486 23:11:24.683262 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9487 23:11:24.689838 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9488 23:11:24.693351 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9489 23:11:24.697015 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9490 23:11:24.703383 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9491 23:11:24.707002 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9492 23:11:24.710100 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9493 23:11:24.716699 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9494 23:11:24.720258 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9495 23:11:24.723674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9496 23:11:24.726944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9497 23:11:24.733718 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9498 23:11:24.736990 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9499 23:11:24.740439 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9500 23:11:24.743918 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9501 23:11:24.750875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9502 23:11:24.753937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9503 23:11:24.757253 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9504 23:11:24.761145 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9505 23:11:24.767308 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9506 23:11:24.771328 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9507 23:11:24.774189 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9508 23:11:24.780634 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9509 23:11:24.784206 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9510 23:11:24.787395 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9511 23:11:24.794553 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9512 23:11:24.797083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9513 23:11:24.803776 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9514 23:11:24.807016 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9515 23:11:24.810422 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9516 23:11:24.816881 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9517 23:11:24.820439 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9518 23:11:24.827683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9519 23:11:24.830391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9520 23:11:24.837100 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9521 23:11:24.840596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9522 23:11:24.847150 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9523 23:11:24.850640 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9524 23:11:24.853636 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9525 23:11:24.860715 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9526 23:11:24.864276 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9527 23:11:24.870479 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9528 23:11:24.873816 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9529 23:11:24.877393 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9530 23:11:24.883932 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9531 23:11:24.886943 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9532 23:11:24.893418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9533 23:11:24.897318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9534 23:11:24.903676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9535 23:11:24.907154 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9536 23:11:24.910194 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9537 23:11:24.917177 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9538 23:11:24.920370 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9539 23:11:24.927366 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9540 23:11:24.930227 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9541 23:11:24.937086 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9542 23:11:24.940442 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9543 23:11:24.944079 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9544 23:11:24.950432 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9545 23:11:24.954008 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9546 23:11:24.960243 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9547 23:11:24.963701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9548 23:11:24.970716 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9549 23:11:24.973839 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9550 23:11:24.976936 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9551 23:11:24.983860 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9552 23:11:24.987252 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9553 23:11:24.993807 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9554 23:11:24.997157 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9555 23:11:25.003832 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9556 23:11:25.006868 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9557 23:11:25.010727 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9558 23:11:25.013842 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9559 23:11:25.020144 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9560 23:11:25.023771 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9561 23:11:25.027179 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9562 23:11:25.033758 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9563 23:11:25.037425 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9564 23:11:25.044145 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9565 23:11:25.047533 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9566 23:11:25.050280 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9567 23:11:25.057433 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9568 23:11:25.060564 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9569 23:11:25.067360 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9570 23:11:25.070397 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9571 23:11:25.074033 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9572 23:11:25.080340 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9573 23:11:25.083798 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9574 23:11:25.087421 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9575 23:11:25.094305 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9576 23:11:25.097733 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9577 23:11:25.100461 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9578 23:11:25.107370 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9579 23:11:25.110960 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9580 23:11:25.114053 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9581 23:11:25.117049 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9582 23:11:25.123944 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9583 23:11:25.127420 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9584 23:11:25.130541 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9585 23:11:25.137314 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9586 23:11:25.140826 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9587 23:11:25.144080 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9588 23:11:25.150699 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9589 23:11:25.154481 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9590 23:11:25.160403 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9591 23:11:25.163587 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9592 23:11:25.167473 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9593 23:11:25.174393 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9594 23:11:25.177463 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9595 23:11:25.183986 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9596 23:11:25.187728 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9597 23:11:25.191126 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9598 23:11:25.197635 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9599 23:11:25.201467 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9600 23:11:25.204818 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9601 23:11:25.210964 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9602 23:11:25.214783 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9603 23:11:25.221084 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9604 23:11:25.224287 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9605 23:11:25.227862 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9606 23:11:25.234590 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9607 23:11:25.237846 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9608 23:11:25.240884 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9609 23:11:25.247425 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9610 23:11:25.251102 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9611 23:11:25.257724 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9612 23:11:25.261325 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9613 23:11:25.264252 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9614 23:11:25.271254 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9615 23:11:25.274147 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9616 23:11:25.281150 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9617 23:11:25.284874 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9618 23:11:25.288267 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9619 23:11:25.294260 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9620 23:11:25.297635 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9621 23:11:25.300850 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9622 23:11:25.307445 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9623 23:11:25.310855 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9624 23:11:25.317208 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9625 23:11:25.320722 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9626 23:11:25.324367 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9627 23:11:25.330298 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9628 23:11:25.334086 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9629 23:11:25.340414 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9630 23:11:25.343592 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9631 23:11:25.347273 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9632 23:11:25.354051 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9633 23:11:25.357096 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9634 23:11:25.364136 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9635 23:11:25.367306 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9636 23:11:25.371154 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9637 23:11:25.377114 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9638 23:11:25.380485 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9639 23:11:25.386994 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9640 23:11:25.390546 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9641 23:11:25.393590 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9642 23:11:25.400487 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9643 23:11:25.403802 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9644 23:11:25.410308 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9645 23:11:25.413682 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9646 23:11:25.416971 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9647 23:11:25.423768 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9648 23:11:25.427022 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9649 23:11:25.433078 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9650 23:11:25.436496 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9651 23:11:25.440092 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9652 23:11:25.447210 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9653 23:11:25.450575 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9654 23:11:25.456809 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9655 23:11:25.460107 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9656 23:11:25.463258 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9657 23:11:25.470179 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9658 23:11:25.473517 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9659 23:11:25.480421 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9660 23:11:25.483220 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9661 23:11:25.486532 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9662 23:11:25.493220 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9663 23:11:25.496483 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9664 23:11:25.502930 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9665 23:11:25.507407 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9666 23:11:25.513451 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9667 23:11:25.516536 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9668 23:11:25.519900 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9669 23:11:25.526700 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9670 23:11:25.530197 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9671 23:11:25.536608 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9672 23:11:25.539954 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9673 23:11:25.543303 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9674 23:11:25.550494 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9675 23:11:25.553252 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9676 23:11:25.560340 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9677 23:11:25.564164 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9678 23:11:25.570292 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9679 23:11:25.573433 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9680 23:11:25.576953 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9681 23:11:25.583669 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9682 23:11:25.587494 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9683 23:11:25.593229 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9684 23:11:25.596871 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9685 23:11:25.600537 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9686 23:11:25.606306 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9687 23:11:25.609816 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9688 23:11:25.616330 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9689 23:11:25.619382 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9690 23:11:25.623111 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9691 23:11:25.626724 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9692 23:11:25.629801 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9693 23:11:25.636449 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9694 23:11:25.639607 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9695 23:11:25.642878 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9696 23:11:25.649603 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9697 23:11:25.653605 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9698 23:11:25.656961 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9699 23:11:25.663124 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9700 23:11:25.666639 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9701 23:11:25.672687 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9702 23:11:25.676643 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9703 23:11:25.679444 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9704 23:11:25.686200 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9705 23:11:25.689838 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9706 23:11:25.696652 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9707 23:11:25.699601 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9708 23:11:25.702852 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9709 23:11:25.709466 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9710 23:11:25.712811 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9711 23:11:25.715941 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9712 23:11:25.723035 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9713 23:11:25.726515 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9714 23:11:25.729879 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9715 23:11:25.736218 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9716 23:11:25.739539 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9717 23:11:25.746063 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9718 23:11:25.749539 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9719 23:11:25.752774 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9720 23:11:25.759635 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9721 23:11:25.762608 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9722 23:11:25.765767 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9723 23:11:25.772855 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9724 23:11:25.776000 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9725 23:11:25.779538 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9726 23:11:25.785943 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9727 23:11:25.789388 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9728 23:11:25.792573 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9729 23:11:25.799649 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9730 23:11:25.802798 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9731 23:11:25.805735 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9732 23:11:25.809427 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9733 23:11:25.812870 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9734 23:11:25.819077 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9735 23:11:25.822007 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9736 23:11:25.825798 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9737 23:11:25.832130 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9738 23:11:25.835605 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9739 23:11:25.838726 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9740 23:11:25.845468 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9741 23:11:25.848688 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9742 23:11:25.852335 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9743 23:11:25.858689 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9744 23:11:25.862067 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9745 23:11:25.865434 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9746 23:11:25.872538 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9747 23:11:25.875562 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9748 23:11:25.882041 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9749 23:11:25.885456 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9750 23:11:25.888712 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9751 23:11:25.895188 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9752 23:11:25.898322 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9753 23:11:25.905523 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9754 23:11:25.908783 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9755 23:11:25.915385 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9756 23:11:25.918820 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9757 23:11:25.921866 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9758 23:11:25.928536 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9759 23:11:25.931725 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9760 23:11:25.938098 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9761 23:11:25.941837 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9762 23:11:25.944859 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9763 23:11:25.951424 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9764 23:11:25.954945 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9765 23:11:25.958890 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9766 23:11:25.964908 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9767 23:11:25.968104 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9768 23:11:25.975121 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9769 23:11:25.978689 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9770 23:11:25.985053 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9771 23:11:25.988289 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9772 23:11:25.994614 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9773 23:11:25.997677 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9774 23:11:26.001550 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9775 23:11:26.008240 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9776 23:11:26.011834 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9777 23:11:26.018449 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9778 23:11:26.021529 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9779 23:11:26.024656 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9780 23:11:26.031355 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9781 23:11:26.034215 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9782 23:11:26.041031 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9783 23:11:26.044676 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9784 23:11:26.047672 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9785 23:11:26.054198 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9786 23:11:26.057327 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9787 23:11:26.064711 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9788 23:11:26.067755 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9789 23:11:26.071318 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9790 23:11:26.077456 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9791 23:11:26.080646 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9792 23:11:26.087760 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9793 23:11:26.090930 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9794 23:11:26.097374 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9795 23:11:26.100539 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9796 23:11:26.103910 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9797 23:11:26.110497 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9798 23:11:26.114358 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9799 23:11:26.120708 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9800 23:11:26.124168 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9801 23:11:26.127491 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9802 23:11:26.133540 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9803 23:11:26.137742 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9804 23:11:26.143828 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9805 23:11:26.147673 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9806 23:11:26.150493 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9807 23:11:26.157124 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9808 23:11:26.160529 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9809 23:11:26.167141 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9810 23:11:26.170460 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9811 23:11:26.177113 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9812 23:11:26.180768 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9813 23:11:26.183875 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9814 23:11:26.190459 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9815 23:11:26.194018 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9816 23:11:26.200577 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9817 23:11:26.203514 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9818 23:11:26.210238 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9819 23:11:26.214057 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9820 23:11:26.216856 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9821 23:11:26.223344 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9822 23:11:26.227142 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9823 23:11:26.233513 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9824 23:11:26.237399 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9825 23:11:26.243159 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9826 23:11:26.246638 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9827 23:11:26.249733 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9828 23:11:26.256569 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9829 23:11:26.260427 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9830 23:11:26.266998 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9831 23:11:26.270178 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9832 23:11:26.276472 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9833 23:11:26.280163 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9834 23:11:26.283458 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9835 23:11:26.289784 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9836 23:11:26.293020 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9837 23:11:26.299887 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9838 23:11:26.302894 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9839 23:11:26.309488 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9840 23:11:26.313195 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9841 23:11:26.316103 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9842 23:11:26.323481 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9843 23:11:26.326085 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9844 23:11:26.333418 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9845 23:11:26.336246 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9846 23:11:26.342848 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9847 23:11:26.346345 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9848 23:11:26.349994 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9849 23:11:26.356088 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9850 23:11:26.359817 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9851 23:11:26.366302 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9852 23:11:26.369536 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9853 23:11:26.376191 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9854 23:11:26.379266 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9855 23:11:26.385801 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9856 23:11:26.389373 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9857 23:11:26.392577 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9858 23:11:26.399499 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9859 23:11:26.403197 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9860 23:11:26.409625 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9861 23:11:26.412591 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9862 23:11:26.416130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9863 23:11:26.422973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9864 23:11:26.425909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9865 23:11:26.432840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9866 23:11:26.436339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9867 23:11:26.442959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9868 23:11:26.446214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9869 23:11:26.453013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9870 23:11:26.456022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9871 23:11:26.462839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9872 23:11:26.466126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9873 23:11:26.472483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9874 23:11:26.476128 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9875 23:11:26.482458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9876 23:11:26.486445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9877 23:11:26.489486 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9878 23:11:26.496001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9879 23:11:26.499562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9880 23:11:26.505958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9881 23:11:26.509651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9882 23:11:26.516433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9883 23:11:26.519252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9884 23:11:26.526145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9885 23:11:26.528989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9886 23:11:26.535681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9887 23:11:26.539020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9888 23:11:26.546166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9889 23:11:26.548819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9890 23:11:26.555522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9891 23:11:26.558872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9892 23:11:26.565453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9893 23:11:26.568695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9894 23:11:26.575439 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9895 23:11:26.575567 INFO: [APUAPC] vio 0
9896 23:11:26.582569 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9897 23:11:26.585964 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9898 23:11:26.588950 INFO: [APUAPC] D0_APC_0: 0x400510
9899 23:11:26.592567 INFO: [APUAPC] D0_APC_1: 0x0
9900 23:11:26.596114 INFO: [APUAPC] D0_APC_2: 0x1540
9901 23:11:26.599381 INFO: [APUAPC] D0_APC_3: 0x0
9902 23:11:26.602368 INFO: [APUAPC] D1_APC_0: 0xffffffff
9903 23:11:26.606138 INFO: [APUAPC] D1_APC_1: 0xffffffff
9904 23:11:26.609546 INFO: [APUAPC] D1_APC_2: 0x3fffff
9905 23:11:26.612636 INFO: [APUAPC] D1_APC_3: 0x0
9906 23:11:26.615959 INFO: [APUAPC] D2_APC_0: 0xffffffff
9907 23:11:26.619294 INFO: [APUAPC] D2_APC_1: 0xffffffff
9908 23:11:26.622545 INFO: [APUAPC] D2_APC_2: 0x3fffff
9909 23:11:26.626125 INFO: [APUAPC] D2_APC_3: 0x0
9910 23:11:26.629201 INFO: [APUAPC] D3_APC_0: 0xffffffff
9911 23:11:26.632290 INFO: [APUAPC] D3_APC_1: 0xffffffff
9912 23:11:26.635686 INFO: [APUAPC] D3_APC_2: 0x3fffff
9913 23:11:26.639331 INFO: [APUAPC] D3_APC_3: 0x0
9914 23:11:26.642557 INFO: [APUAPC] D4_APC_0: 0xffffffff
9915 23:11:26.645617 INFO: [APUAPC] D4_APC_1: 0xffffffff
9916 23:11:26.648866 INFO: [APUAPC] D4_APC_2: 0x3fffff
9917 23:11:26.649112 INFO: [APUAPC] D4_APC_3: 0x0
9918 23:11:26.652354 INFO: [APUAPC] D5_APC_0: 0xffffffff
9919 23:11:26.659387 INFO: [APUAPC] D5_APC_1: 0xffffffff
9920 23:11:26.662235 INFO: [APUAPC] D5_APC_2: 0x3fffff
9921 23:11:26.662403 INFO: [APUAPC] D5_APC_3: 0x0
9922 23:11:26.665273 INFO: [APUAPC] D6_APC_0: 0xffffffff
9923 23:11:26.669195 INFO: [APUAPC] D6_APC_1: 0xffffffff
9924 23:11:26.671985 INFO: [APUAPC] D6_APC_2: 0x3fffff
9925 23:11:26.675668 INFO: [APUAPC] D6_APC_3: 0x0
9926 23:11:26.678981 INFO: [APUAPC] D7_APC_0: 0xffffffff
9927 23:11:26.682575 INFO: [APUAPC] D7_APC_1: 0xffffffff
9928 23:11:26.686099 INFO: [APUAPC] D7_APC_2: 0x3fffff
9929 23:11:26.688992 INFO: [APUAPC] D7_APC_3: 0x0
9930 23:11:26.692646 INFO: [APUAPC] D8_APC_0: 0xffffffff
9931 23:11:26.696175 INFO: [APUAPC] D8_APC_1: 0xffffffff
9932 23:11:26.699307 INFO: [APUAPC] D8_APC_2: 0x3fffff
9933 23:11:26.702541 INFO: [APUAPC] D8_APC_3: 0x0
9934 23:11:26.705650 INFO: [APUAPC] D9_APC_0: 0xffffffff
9935 23:11:26.708823 INFO: [APUAPC] D9_APC_1: 0xffffffff
9936 23:11:26.712521 INFO: [APUAPC] D9_APC_2: 0x3fffff
9937 23:11:26.715330 INFO: [APUAPC] D9_APC_3: 0x0
9938 23:11:26.718746 INFO: [APUAPC] D10_APC_0: 0xffffffff
9939 23:11:26.722526 INFO: [APUAPC] D10_APC_1: 0xffffffff
9940 23:11:26.725116 INFO: [APUAPC] D10_APC_2: 0x3fffff
9941 23:11:26.728550 INFO: [APUAPC] D10_APC_3: 0x0
9942 23:11:26.732182 INFO: [APUAPC] D11_APC_0: 0xffffffff
9943 23:11:26.735055 INFO: [APUAPC] D11_APC_1: 0xffffffff
9944 23:11:26.738677 INFO: [APUAPC] D11_APC_2: 0x3fffff
9945 23:11:26.741968 INFO: [APUAPC] D11_APC_3: 0x0
9946 23:11:26.745523 INFO: [APUAPC] D12_APC_0: 0xffffffff
9947 23:11:26.748358 INFO: [APUAPC] D12_APC_1: 0xffffffff
9948 23:11:26.751928 INFO: [APUAPC] D12_APC_2: 0x3fffff
9949 23:11:26.755200 INFO: [APUAPC] D12_APC_3: 0x0
9950 23:11:26.758416 INFO: [APUAPC] D13_APC_0: 0xffffffff
9951 23:11:26.761817 INFO: [APUAPC] D13_APC_1: 0xffffffff
9952 23:11:26.765322 INFO: [APUAPC] D13_APC_2: 0x3fffff
9953 23:11:26.768550 INFO: [APUAPC] D13_APC_3: 0x0
9954 23:11:26.771731 INFO: [APUAPC] D14_APC_0: 0xffffffff
9955 23:11:26.774991 INFO: [APUAPC] D14_APC_1: 0xffffffff
9956 23:11:26.778380 INFO: [APUAPC] D14_APC_2: 0x3fffff
9957 23:11:26.781937 INFO: [APUAPC] D14_APC_3: 0x0
9958 23:11:26.784740 INFO: [APUAPC] D15_APC_0: 0xffffffff
9959 23:11:26.787927 INFO: [APUAPC] D15_APC_1: 0xffffffff
9960 23:11:26.791660 INFO: [APUAPC] D15_APC_2: 0x3fffff
9961 23:11:26.794859 INFO: [APUAPC] D15_APC_3: 0x0
9962 23:11:26.798140 INFO: [APUAPC] APC_CON: 0x4
9963 23:11:26.802124 INFO: [NOCDAPC] D0_APC_0: 0x0
9964 23:11:26.804827 INFO: [NOCDAPC] D0_APC_1: 0x0
9965 23:11:26.808548 INFO: [NOCDAPC] D1_APC_0: 0x0
9966 23:11:26.811506 INFO: [NOCDAPC] D1_APC_1: 0xfff
9967 23:11:26.811681 INFO: [NOCDAPC] D2_APC_0: 0x0
9968 23:11:26.814705 INFO: [NOCDAPC] D2_APC_1: 0xfff
9969 23:11:26.817869 INFO: [NOCDAPC] D3_APC_0: 0x0
9970 23:11:26.821234 INFO: [NOCDAPC] D3_APC_1: 0xfff
9971 23:11:26.824823 INFO: [NOCDAPC] D4_APC_0: 0x0
9972 23:11:26.827971 INFO: [NOCDAPC] D4_APC_1: 0xfff
9973 23:11:26.831147 INFO: [NOCDAPC] D5_APC_0: 0x0
9974 23:11:26.834980 INFO: [NOCDAPC] D5_APC_1: 0xfff
9975 23:11:26.837991 INFO: [NOCDAPC] D6_APC_0: 0x0
9976 23:11:26.841486 INFO: [NOCDAPC] D6_APC_1: 0xfff
9977 23:11:26.844320 INFO: [NOCDAPC] D7_APC_0: 0x0
9978 23:11:26.848050 INFO: [NOCDAPC] D7_APC_1: 0xfff
9979 23:11:26.848189 INFO: [NOCDAPC] D8_APC_0: 0x0
9980 23:11:26.850909 INFO: [NOCDAPC] D8_APC_1: 0xfff
9981 23:11:26.854564 INFO: [NOCDAPC] D9_APC_0: 0x0
9982 23:11:26.857490 INFO: [NOCDAPC] D9_APC_1: 0xfff
9983 23:11:26.860794 INFO: [NOCDAPC] D10_APC_0: 0x0
9984 23:11:26.864776 INFO: [NOCDAPC] D10_APC_1: 0xfff
9985 23:11:26.867454 INFO: [NOCDAPC] D11_APC_0: 0x0
9986 23:11:26.871360 INFO: [NOCDAPC] D11_APC_1: 0xfff
9987 23:11:26.873994 INFO: [NOCDAPC] D12_APC_0: 0x0
9988 23:11:26.877749 INFO: [NOCDAPC] D12_APC_1: 0xfff
9989 23:11:26.880994 INFO: [NOCDAPC] D13_APC_0: 0x0
9990 23:11:26.884054 INFO: [NOCDAPC] D13_APC_1: 0xfff
9991 23:11:26.887284 INFO: [NOCDAPC] D14_APC_0: 0x0
9992 23:11:26.891242 INFO: [NOCDAPC] D14_APC_1: 0xfff
9993 23:11:26.891381 INFO: [NOCDAPC] D15_APC_0: 0x0
9994 23:11:26.894072 INFO: [NOCDAPC] D15_APC_1: 0xfff
9995 23:11:26.897408 INFO: [NOCDAPC] APC_CON: 0x4
9996 23:11:26.901051 INFO: [APUAPC] set_apusys_apc done
9997 23:11:26.904526 INFO: [DEVAPC] devapc_init done
9998 23:11:26.907471 INFO: GICv3 without legacy support detected.
9999 23:11:26.913945 INFO: ARM GICv3 driver initialized in EL3
10000 23:11:26.917565 INFO: Maximum SPI INTID supported: 639
10001 23:11:26.921067 INFO: BL31: Initializing runtime services
10002 23:11:26.927917 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10003 23:11:26.931309 INFO: SPM: enable CPC mode
10004 23:11:26.934278 INFO: mcdi ready for mcusys-off-idle and system suspend
10005 23:11:26.941134 INFO: BL31: Preparing for EL3 exit to normal world
10006 23:11:26.944503 INFO: Entry point address = 0x80000000
10007 23:11:26.944921 INFO: SPSR = 0x8
10008 23:11:26.950696
10009 23:11:26.951109
10010 23:11:26.951434
10011 23:11:26.954545 Starting depthcharge on Spherion...
10012 23:11:26.954959
10013 23:11:26.955288 Wipe memory regions:
10014 23:11:26.955592
10015 23:11:26.958151 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10016 23:11:26.958637 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10017 23:11:26.959031 Setting prompt string to ['asurada:']
10018 23:11:26.959406 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10019 23:11:26.960063 [0x00000040000000, 0x00000054600000)
10020 23:11:27.079527
10021 23:11:27.079684 [0x00000054660000, 0x00000080000000)
10022 23:11:27.340068
10023 23:11:27.340201 [0x000000821a7280, 0x000000ffe64000)
10024 23:11:28.084939
10025 23:11:28.085090 [0x00000100000000, 0x00000240000000)
10026 23:11:29.975457
10027 23:11:29.978773 Initializing XHCI USB controller at 0x11200000.
10028 23:11:31.016362
10029 23:11:31.019292 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10030 23:11:31.019388
10031 23:11:31.019452
10032 23:11:31.019511
10033 23:11:31.019788 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10035 23:11:31.120195 asurada: tftpboot 192.168.201.1 12154446/tftp-deploy-g5gjd_yr/kernel/image.itb 12154446/tftp-deploy-g5gjd_yr/kernel/cmdline
10036 23:11:31.120337 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10037 23:11:31.120427 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10038 23:11:31.125247 tftpboot 192.168.201.1 12154446/tftp-deploy-g5gjd_yr/kernel/image.ittp-deploy-g5gjd_yr/kernel/cmdline
10039 23:11:31.125332
10040 23:11:31.125397 Waiting for link
10041 23:11:31.285854
10042 23:11:31.285978 R8152: Initializing
10043 23:11:31.286045
10044 23:11:31.289022 Version 9 (ocp_data = 6010)
10045 23:11:31.289102
10046 23:11:31.292288 R8152: Done initializing
10047 23:11:31.292368
10048 23:11:31.292433 Adding net device
10049 23:11:33.238102
10050 23:11:33.238251 done.
10051 23:11:33.238317
10052 23:11:33.238378 MAC: 00:e0:4c:78:7a:aa
10053 23:11:33.238438
10054 23:11:33.241383 Sending DHCP discover... done.
10055 23:11:33.241491
10056 23:11:33.244791 Waiting for reply... done.
10057 23:11:33.244872
10058 23:11:33.248158 Sending DHCP request... done.
10059 23:11:33.248239
10060 23:11:33.248304 Waiting for reply... done.
10061 23:11:33.248366
10062 23:11:33.251400 My ip is 192.168.201.12
10063 23:11:33.251480
10064 23:11:33.254857 The DHCP server ip is 192.168.201.1
10065 23:11:33.254938
10066 23:11:33.258195 TFTP server IP predefined by user: 192.168.201.1
10067 23:11:33.258276
10068 23:11:33.264967 Bootfile predefined by user: 12154446/tftp-deploy-g5gjd_yr/kernel/image.itb
10069 23:11:33.265049
10070 23:11:33.268578 Sending tftp read request... done.
10071 23:11:33.268659
10072 23:11:33.271377 Waiting for the transfer...
10073 23:11:33.271459
10074 23:11:33.567426 00000000 ################################################################
10075 23:11:33.567568
10076 23:11:33.864200 00080000 ################################################################
10077 23:11:33.864343
10078 23:11:34.162477 00100000 ################################################################
10079 23:11:34.162621
10080 23:11:34.455316 00180000 ################################################################
10081 23:11:34.455457
10082 23:11:34.748152 00200000 ################################################################
10083 23:11:34.748337
10084 23:11:35.030220 00280000 ################################################################
10085 23:11:35.030356
10086 23:11:35.291935 00300000 ################################################################
10087 23:11:35.292091
10088 23:11:35.550393 00380000 ################################################################
10089 23:11:35.550532
10090 23:11:35.821468 00400000 ################################################################
10091 23:11:35.821652
10092 23:11:36.098776 00480000 ################################################################
10093 23:11:36.098922
10094 23:11:36.379029 00500000 ################################################################
10095 23:11:36.379177
10096 23:11:36.671961 00580000 ################################################################
10097 23:11:36.672109
10098 23:11:36.963941 00600000 ################################################################
10099 23:11:36.964095
10100 23:11:37.262140 00680000 ################################################################
10101 23:11:37.262290
10102 23:11:37.563939 00700000 ################################################################
10103 23:11:37.564074
10104 23:11:37.854687 00780000 ################################################################
10105 23:11:37.854836
10106 23:11:38.147388 00800000 ################################################################
10107 23:11:38.147563
10108 23:11:38.441963 00880000 ################################################################
10109 23:11:38.442107
10110 23:11:38.740382 00900000 ################################################################
10111 23:11:38.740528
10112 23:11:39.022185 00980000 ################################################################
10113 23:11:39.022337
10114 23:11:39.311145 00a00000 ################################################################
10115 23:11:39.311300
10116 23:11:39.598731 00a80000 ################################################################
10117 23:11:39.598920
10118 23:11:39.893572 00b00000 ################################################################
10119 23:11:39.893791
10120 23:11:40.160933 00b80000 ################################################################
10121 23:11:40.161109
10122 23:11:40.431760 00c00000 ################################################################
10123 23:11:40.431951
10124 23:11:40.729636 00c80000 ################################################################
10125 23:11:40.729786
10126 23:11:41.026756 00d00000 ################################################################
10127 23:11:41.026908
10128 23:11:41.323206 00d80000 ################################################################
10129 23:11:41.323357
10130 23:11:41.619924 00e00000 ################################################################
10131 23:11:41.620071
10132 23:11:41.917109 00e80000 ################################################################
10133 23:11:41.917258
10134 23:11:42.212393 00f00000 ################################################################
10135 23:11:42.212546
10136 23:11:42.508710 00f80000 ################################################################
10137 23:11:42.508867
10138 23:11:42.786699 01000000 ################################################################
10139 23:11:42.786843
10140 23:11:43.036861 01080000 ################################################################
10141 23:11:43.037003
10142 23:11:43.295328 01100000 ################################################################
10143 23:11:43.295485
10144 23:11:43.558246 01180000 ################################################################
10145 23:11:43.558399
10146 23:11:43.816100 01200000 ################################################################
10147 23:11:43.816254
10148 23:11:44.091854 01280000 ################################################################
10149 23:11:44.092036
10150 23:11:44.381384 01300000 ################################################################
10151 23:11:44.381554
10152 23:11:44.654925 01380000 ################################################################
10153 23:11:44.655082
10154 23:11:44.950518 01400000 ################################################################
10155 23:11:44.950670
10156 23:11:45.223493 01480000 ################################################################
10157 23:11:45.223648
10158 23:11:45.475971 01500000 ################################################################
10159 23:11:45.476131
10160 23:11:45.722110 01580000 ################################################################
10161 23:11:45.722250
10162 23:11:45.960891 01600000 ################################################################
10163 23:11:45.961036
10164 23:11:46.201287 01680000 ################################################################
10165 23:11:46.201427
10166 23:11:46.457937 01700000 ################################################################
10167 23:11:46.458086
10168 23:11:46.728089 01780000 ################################################################
10169 23:11:46.728242
10170 23:11:46.988561 01800000 ################################################################
10171 23:11:46.988713
10172 23:11:47.261022 01880000 ################################################################
10173 23:11:47.261174
10174 23:11:47.549016 01900000 ################################################################
10175 23:11:47.549174
10176 23:11:47.842314 01980000 ################################################################
10177 23:11:47.842466
10178 23:11:48.139373 01a00000 ################################################################
10179 23:11:48.139527
10180 23:11:48.429837 01a80000 ################################################################
10181 23:11:48.429985
10182 23:11:48.704505 01b00000 ################################################################
10183 23:11:48.704697
10184 23:11:49.004442 01b80000 ################################################################
10185 23:11:49.004587
10186 23:11:49.301367 01c00000 ################################################################
10187 23:11:49.301518
10188 23:11:49.590439 01c80000 ################################################################
10189 23:11:49.590591
10190 23:11:49.866686 01d00000 ################################################################
10191 23:11:49.866838
10192 23:11:50.130400 01d80000 ################################################################
10193 23:11:50.130554
10194 23:11:50.425223 01e00000 ################################################################
10195 23:11:50.425373
10196 23:11:50.720328 01e80000 ################################################################
10197 23:11:50.720481
10198 23:11:51.021859 01f00000 ################################################################
10199 23:11:51.022037
10200 23:11:51.337120 01f80000 ################################################################
10201 23:11:51.337312
10202 23:11:51.632858 02000000 ################################################################
10203 23:11:51.633054
10204 23:11:51.922567 02080000 ################################################################
10205 23:11:51.922716
10206 23:11:52.204838 02100000 ################################################################
10207 23:11:52.204978
10208 23:11:52.492186 02180000 ################################################################
10209 23:11:52.492331
10210 23:11:52.779598 02200000 ################################################################
10211 23:11:52.779742
10212 23:11:53.070280 02280000 ################################################################
10213 23:11:53.070419
10214 23:11:53.355000 02300000 ################################################################
10215 23:11:53.355142
10216 23:11:53.630224 02380000 ################################################################
10217 23:11:53.630370
10218 23:11:53.879825 02400000 ################################################################
10219 23:11:53.879974
10220 23:11:54.129247 02480000 ################################################################
10221 23:11:54.129383
10222 23:11:54.384467 02500000 ################################################################
10223 23:11:54.384606
10224 23:11:54.651421 02580000 ################################################################
10225 23:11:54.651560
10226 23:11:54.912925 02600000 ################################################################
10227 23:11:54.913067
10228 23:11:55.165983 02680000 ################################################################
10229 23:11:55.166122
10230 23:11:55.440301 02700000 ################################################################
10231 23:11:55.440440
10232 23:11:55.716984 02780000 ################################################################
10233 23:11:55.717128
10234 23:11:56.002224 02800000 ################################################################
10235 23:11:56.002368
10236 23:11:56.288777 02880000 ################################################################
10237 23:11:56.288917
10238 23:11:56.576951 02900000 ################################################################
10239 23:11:56.577101
10240 23:11:56.820993 02980000 ################################################################
10241 23:11:56.821185
10242 23:11:57.061775 02a00000 ################################################################
10243 23:11:57.061926
10244 23:11:57.306006 02a80000 ################################################################
10245 23:11:57.306162
10246 23:11:57.566287 02b00000 ################################################################
10247 23:11:57.566417
10248 23:11:57.828342 02b80000 ################################################################
10249 23:11:57.828474
10250 23:11:58.090900 02c00000 ################################################################
10251 23:11:58.091035
10252 23:11:58.344633 02c80000 ################################################################
10253 23:11:58.344774
10254 23:11:58.602745 02d00000 ################################################################
10255 23:11:58.602879
10256 23:11:58.851830 02d80000 ################################################################
10257 23:11:58.851965
10258 23:11:59.101875 02e00000 ################################################################
10259 23:11:59.102014
10260 23:11:59.385180 02e80000 ################################################################
10261 23:11:59.385326
10262 23:11:59.680551 02f00000 ################################################################
10263 23:11:59.680691
10264 23:11:59.935018 02f80000 ################################################################
10265 23:11:59.935161
10266 23:11:59.993943 03000000 ############### done.
10267 23:11:59.994045
10268 23:11:59.997037 The bootfile was 50453426 bytes long.
10269 23:11:59.997128
10270 23:12:00.000958 Sending tftp read request... done.
10271 23:12:00.001141
10272 23:12:00.001277 Waiting for the transfer...
10273 23:12:00.001397
10274 23:12:00.004207 00000000 # done.
10275 23:12:00.004330
10276 23:12:00.010286 Command line loaded dynamically from TFTP file: 12154446/tftp-deploy-g5gjd_yr/kernel/cmdline
10277 23:12:00.010397
10278 23:12:00.024137 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10279 23:12:00.024353
10280 23:12:00.027503 Loading FIT.
10281 23:12:00.027737
10282 23:12:00.030458 Image ramdisk-1 has 39360131 bytes.
10283 23:12:00.030656
10284 23:12:00.030793 Image fdt-1 has 47278 bytes.
10285 23:12:00.033714
10286 23:12:00.033883 Image kernel-1 has 11043984 bytes.
10287 23:12:00.034018
10288 23:12:00.043686 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10289 23:12:00.044004
10290 23:12:00.060824 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10291 23:12:00.061366
10292 23:12:00.067455 Choosing best match conf-1 for compat google,spherion-rev2.
10293 23:12:00.071407
10294 23:12:00.076274 Connected to device vid:did:rid of 1ae0:0028:00
10295 23:12:00.084537
10296 23:12:00.088202 tpm_get_response: command 0x17b, return code 0x0
10297 23:12:00.088716
10298 23:12:00.090510 ec_init: CrosEC protocol v3 supported (256, 248)
10299 23:12:00.095152
10300 23:12:00.097953 tpm_cleanup: add release locality here.
10301 23:12:00.098370
10302 23:12:00.098699 Shutting down all USB controllers.
10303 23:12:00.101691
10304 23:12:00.102153 Removing current net device
10305 23:12:00.102486
10306 23:12:00.107792 Exiting depthcharge with code 4 at timestamp: 62430411
10307 23:12:00.108223
10308 23:12:00.111723 LZMA decompressing kernel-1 to 0x821a6718
10309 23:12:00.112165
10310 23:12:00.114436 LZMA decompressing kernel-1 to 0x40000000
10311 23:12:01.507909
10312 23:12:01.508062 jumping to kernel
10313 23:12:01.508570 end: 2.2.4 bootloader-commands (duration 00:00:35) [common]
10314 23:12:01.508666 start: 2.2.5 auto-login-action (timeout 00:03:51) [common]
10315 23:12:01.508740 Setting prompt string to ['Linux version [0-9]']
10316 23:12:01.508808 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10317 23:12:01.508875 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10318 23:12:01.590061
10319 23:12:01.593436 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10320 23:12:01.596955 start: 2.2.5.1 login-action (timeout 00:03:51) [common]
10321 23:12:01.597048 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10322 23:12:01.597119 Setting prompt string to []
10323 23:12:01.597215 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10324 23:12:01.597295 Using line separator: #'\n'#
10325 23:12:01.597355 No login prompt set.
10326 23:12:01.597416 Parsing kernel messages
10327 23:12:01.597472 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10328 23:12:01.597585 [login-action] Waiting for messages, (timeout 00:03:51)
10329 23:12:01.616308 [ 0.000000] Linux version 6.1.64-cip10 (KernelCI@build-j31357-arm64-gcc-10-defconfig-arm64-chromebook-69txj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023
10330 23:12:01.619823 [ 0.000000] random: crng init done
10331 23:12:01.626371 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10332 23:12:01.629573 [ 0.000000] efi: UEFI not found.
10333 23:12:01.636061 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10334 23:12:01.642966 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10335 23:12:01.652869 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10336 23:12:01.662489 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10337 23:12:01.669283 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10338 23:12:01.675751 [ 0.000000] printk: bootconsole [mtk8250] enabled
10339 23:12:01.682449 [ 0.000000] NUMA: No NUMA configuration found
10340 23:12:01.688911 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10341 23:12:01.692899 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10342 23:12:01.695642 [ 0.000000] Zone ranges:
10343 23:12:01.702128 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10344 23:12:01.705738 [ 0.000000] DMA32 empty
10345 23:12:01.712082 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10346 23:12:01.715328 [ 0.000000] Movable zone start for each node
10347 23:12:01.719276 [ 0.000000] Early memory node ranges
10348 23:12:01.726067 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10349 23:12:01.732221 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10350 23:12:01.738935 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10351 23:12:01.745441 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10352 23:12:01.749051 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10353 23:12:01.758517 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10354 23:12:01.814280 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10355 23:12:01.821246 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10356 23:12:01.828129 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10357 23:12:01.831072 [ 0.000000] psci: probing for conduit method from DT.
10358 23:12:01.838180 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10359 23:12:01.841252 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10360 23:12:01.847339 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10361 23:12:01.850871 [ 0.000000] psci: SMC Calling Convention v1.2
10362 23:12:01.857292 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10363 23:12:01.860795 [ 0.000000] Detected VIPT I-cache on CPU0
10364 23:12:01.867415 [ 0.000000] CPU features: detected: GIC system register CPU interface
10365 23:12:01.873620 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10366 23:12:01.880613 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10367 23:12:01.887202 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10368 23:12:01.893495 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10369 23:12:01.900472 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10370 23:12:01.906998 [ 0.000000] alternatives: applying boot alternatives
10371 23:12:01.913700 [ 0.000000] Fallback order for Node 0: 0
10372 23:12:01.920374 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10373 23:12:01.923405 [ 0.000000] Policy zone: Normal
10374 23:12:01.937020 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10375 23:12:01.946852 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10376 23:12:01.958578 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10377 23:12:01.968363 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10378 23:12:01.975189 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10379 23:12:01.978266 <6>[ 0.000000] software IO TLB: area num 8.
10380 23:12:02.035047 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10381 23:12:02.183802 <6>[ 0.000000] Memory: 7931116K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 421652K reserved, 32768K cma-reserved)
10382 23:12:02.190482 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10383 23:12:02.197026 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10384 23:12:02.200327 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10385 23:12:02.207165 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10386 23:12:02.213524 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10387 23:12:02.217171 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10388 23:12:02.227147 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10389 23:12:02.233694 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10390 23:12:02.239826 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10391 23:12:02.246574 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10392 23:12:02.249750 <6>[ 0.000000] GICv3: 608 SPIs implemented
10393 23:12:02.253100 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10394 23:12:02.259999 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10395 23:12:02.263135 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10396 23:12:02.269568 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10397 23:12:02.282897 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10398 23:12:02.296324 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10399 23:12:02.303204 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10400 23:12:02.310578 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10401 23:12:02.324097 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10402 23:12:02.330274 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10403 23:12:02.337229 <6>[ 0.009185] Console: colour dummy device 80x25
10404 23:12:02.346867 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10405 23:12:02.353550 <6>[ 0.024408] pid_max: default: 32768 minimum: 301
10406 23:12:02.357172 <6>[ 0.029279] LSM: Security Framework initializing
10407 23:12:02.363766 <6>[ 0.034246] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10408 23:12:02.373748 <6>[ 0.042060] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10409 23:12:02.380281 <6>[ 0.051533] cblist_init_generic: Setting adjustable number of callback queues.
10410 23:12:02.386678 <6>[ 0.058975] cblist_init_generic: Setting shift to 3 and lim to 1.
10411 23:12:02.396782 <6>[ 0.065312] cblist_init_generic: Setting adjustable number of callback queues.
10412 23:12:02.403137 <6>[ 0.072740] cblist_init_generic: Setting shift to 3 and lim to 1.
10413 23:12:02.406674 <6>[ 0.079140] rcu: Hierarchical SRCU implementation.
10414 23:12:02.413248 <6>[ 0.084155] rcu: Max phase no-delay instances is 1000.
10415 23:12:02.420362 <6>[ 0.091184] EFI services will not be available.
10416 23:12:02.423171 <6>[ 0.096144] smp: Bringing up secondary CPUs ...
10417 23:12:02.431326 <6>[ 0.101196] Detected VIPT I-cache on CPU1
10418 23:12:02.437959 <6>[ 0.101265] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10419 23:12:02.444597 <6>[ 0.101294] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10420 23:12:02.447808 <6>[ 0.101636] Detected VIPT I-cache on CPU2
10421 23:12:02.454442 <6>[ 0.101687] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10422 23:12:02.460885 <6>[ 0.101703] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10423 23:12:02.467676 <6>[ 0.101966] Detected VIPT I-cache on CPU3
10424 23:12:02.474288 <6>[ 0.102013] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10425 23:12:02.481048 <6>[ 0.102027] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10426 23:12:02.484646 <6>[ 0.102334] CPU features: detected: Spectre-v4
10427 23:12:02.491358 <6>[ 0.102340] CPU features: detected: Spectre-BHB
10428 23:12:02.494540 <6>[ 0.102345] Detected PIPT I-cache on CPU4
10429 23:12:02.500841 <6>[ 0.102401] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10430 23:12:02.507637 <6>[ 0.102418] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10431 23:12:02.514322 <6>[ 0.102710] Detected PIPT I-cache on CPU5
10432 23:12:02.521112 <6>[ 0.102770] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10433 23:12:02.527854 <6>[ 0.102787] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10434 23:12:02.531121 <6>[ 0.103069] Detected PIPT I-cache on CPU6
10435 23:12:02.537636 <6>[ 0.103135] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10436 23:12:02.544114 <6>[ 0.103152] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10437 23:12:02.550970 <6>[ 0.103447] Detected PIPT I-cache on CPU7
10438 23:12:02.557399 <6>[ 0.103511] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10439 23:12:02.563802 <6>[ 0.103527] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10440 23:12:02.567347 <6>[ 0.103574] smp: Brought up 1 node, 8 CPUs
10441 23:12:02.574314 <6>[ 0.245017] SMP: Total of 8 processors activated.
10442 23:12:02.577337 <6>[ 0.249938] CPU features: detected: 32-bit EL0 Support
10443 23:12:02.587551 <6>[ 0.255302] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10444 23:12:02.594075 <6>[ 0.264157] CPU features: detected: Common not Private translations
10445 23:12:02.597269 <6>[ 0.270633] CPU features: detected: CRC32 instructions
10446 23:12:02.603809 <6>[ 0.276017] CPU features: detected: RCpc load-acquire (LDAPR)
10447 23:12:02.610416 <6>[ 0.282014] CPU features: detected: LSE atomic instructions
10448 23:12:02.616647 <6>[ 0.287795] CPU features: detected: Privileged Access Never
10449 23:12:02.620488 <6>[ 0.293575] CPU features: detected: RAS Extension Support
10450 23:12:02.630732 <6>[ 0.299183] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10451 23:12:02.633937 <6>[ 0.306448] CPU: All CPU(s) started at EL2
10452 23:12:02.640429 <6>[ 0.310765] alternatives: applying system-wide alternatives
10453 23:12:02.649234 <6>[ 0.321472] devtmpfs: initialized
10454 23:12:02.661190 <6>[ 0.330399] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10455 23:12:02.671131 <6>[ 0.340359] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10456 23:12:02.677907 <6>[ 0.348592] pinctrl core: initialized pinctrl subsystem
10457 23:12:02.681402 <6>[ 0.355239] DMI not present or invalid.
10458 23:12:02.688024 <6>[ 0.359645] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10459 23:12:02.697888 <6>[ 0.366460] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10460 23:12:02.704111 <6>[ 0.374042] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10461 23:12:02.714155 <6>[ 0.382269] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10462 23:12:02.717550 <6>[ 0.390514] audit: initializing netlink subsys (disabled)
10463 23:12:02.727686 <5>[ 0.396202] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10464 23:12:02.734241 <6>[ 0.396900] thermal_sys: Registered thermal governor 'step_wise'
10465 23:12:02.741735 <6>[ 0.404170] thermal_sys: Registered thermal governor 'power_allocator'
10466 23:12:02.744717 <6>[ 0.410426] cpuidle: using governor menu
10467 23:12:02.750727 <6>[ 0.421389] NET: Registered PF_QIPCRTR protocol family
10468 23:12:02.757899 <6>[ 0.426859] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10469 23:12:02.760892 <6>[ 0.433959] ASID allocator initialised with 32768 entries
10470 23:12:02.768029 <6>[ 0.440512] Serial: AMBA PL011 UART driver
10471 23:12:02.776780 <4>[ 0.449243] Trying to register duplicate clock ID: 134
10472 23:12:02.830921 <6>[ 0.506814] KASLR enabled
10473 23:12:02.845551 <6>[ 0.514532] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10474 23:12:02.852292 <6>[ 0.521545] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10475 23:12:02.859015 <6>[ 0.528036] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10476 23:12:02.865782 <6>[ 0.535041] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10477 23:12:02.872090 <6>[ 0.541530] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10478 23:12:02.878587 <6>[ 0.548534] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10479 23:12:02.885323 <6>[ 0.555020] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10480 23:12:02.891958 <6>[ 0.562025] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10481 23:12:02.895463 <6>[ 0.569541] ACPI: Interpreter disabled.
10482 23:12:02.903511 <6>[ 0.575946] iommu: Default domain type: Translated
10483 23:12:02.910052 <6>[ 0.581058] iommu: DMA domain TLB invalidation policy: strict mode
10484 23:12:02.913899 <5>[ 0.587719] SCSI subsystem initialized
10485 23:12:02.920155 <6>[ 0.591881] usbcore: registered new interface driver usbfs
10486 23:12:02.926934 <6>[ 0.597615] usbcore: registered new interface driver hub
10487 23:12:02.930348 <6>[ 0.603167] usbcore: registered new device driver usb
10488 23:12:02.936977 <6>[ 0.609268] pps_core: LinuxPPS API ver. 1 registered
10489 23:12:02.947050 <6>[ 0.614463] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10490 23:12:02.950625 <6>[ 0.623810] PTP clock support registered
10491 23:12:02.953827 <6>[ 0.628050] EDAC MC: Ver: 3.0.0
10492 23:12:02.960863 <6>[ 0.633207] FPGA manager framework
10493 23:12:02.964074 <6>[ 0.636887] Advanced Linux Sound Architecture Driver Initialized.
10494 23:12:02.967840 <6>[ 0.643668] vgaarb: loaded
10495 23:12:02.975554 <6>[ 0.646823] clocksource: Switched to clocksource arch_sys_counter
10496 23:12:02.981734 <5>[ 0.653262] VFS: Disk quotas dquot_6.6.0
10497 23:12:02.987836 <6>[ 0.657449] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10498 23:12:02.991547 <6>[ 0.664637] pnp: PnP ACPI: disabled
10499 23:12:02.999050 <6>[ 0.671309] NET: Registered PF_INET protocol family
10500 23:12:03.008822 <6>[ 0.676904] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10501 23:12:03.020261 <6>[ 0.689267] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10502 23:12:03.030186 <6>[ 0.698084] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10503 23:12:03.036791 <6>[ 0.706054] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10504 23:12:03.043247 <6>[ 0.714753] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10505 23:12:03.055227 <6>[ 0.724515] TCP: Hash tables configured (established 65536 bind 65536)
10506 23:12:03.062229 <6>[ 0.731378] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10507 23:12:03.068839 <6>[ 0.738577] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10508 23:12:03.075260 <6>[ 0.746278] NET: Registered PF_UNIX/PF_LOCAL protocol family
10509 23:12:03.081768 <6>[ 0.752429] RPC: Registered named UNIX socket transport module.
10510 23:12:03.085632 <6>[ 0.758581] RPC: Registered udp transport module.
10511 23:12:03.092445 <6>[ 0.763515] RPC: Registered tcp transport module.
10512 23:12:03.098603 <6>[ 0.768447] RPC: Registered tcp NFSv4.1 backchannel transport module.
10513 23:12:03.101854 <6>[ 0.775111] PCI: CLS 0 bytes, default 64
10514 23:12:03.105265 <6>[ 0.779436] Unpacking initramfs...
10515 23:12:03.122503 <6>[ 0.791369] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10516 23:12:03.132518 <6>[ 0.800030] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10517 23:12:03.135903 <6>[ 0.808887] kvm [1]: IPA Size Limit: 40 bits
10518 23:12:03.142518 <6>[ 0.813415] kvm [1]: GICv3: no GICV resource entry
10519 23:12:03.145550 <6>[ 0.818437] kvm [1]: disabling GICv2 emulation
10520 23:12:03.152192 <6>[ 0.823123] kvm [1]: GIC system register CPU interface enabled
10521 23:12:03.159087 <6>[ 0.830841] kvm [1]: vgic interrupt IRQ18
10522 23:12:03.162412 <6>[ 0.835213] kvm [1]: VHE mode initialized successfully
10523 23:12:03.169602 <5>[ 0.841568] Initialise system trusted keyrings
10524 23:12:03.175833 <6>[ 0.846361] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10525 23:12:03.183771 <6>[ 0.856344] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10526 23:12:03.190535 <5>[ 0.862744] NFS: Registering the id_resolver key type
10527 23:12:03.194327 <5>[ 0.868047] Key type id_resolver registered
10528 23:12:03.200993 <5>[ 0.872462] Key type id_legacy registered
10529 23:12:03.207202 <6>[ 0.876737] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10530 23:12:03.214028 <6>[ 0.883660] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10531 23:12:03.220705 <6>[ 0.891402] 9p: Installing v9fs 9p2000 file system support
10532 23:12:03.257012 <5>[ 0.929440] Key type asymmetric registered
10533 23:12:03.260182 <5>[ 0.933772] Asymmetric key parser 'x509' registered
10534 23:12:03.270737 <6>[ 0.938918] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10535 23:12:03.273434 <6>[ 0.946533] io scheduler mq-deadline registered
10536 23:12:03.277018 <6>[ 0.951294] io scheduler kyber registered
10537 23:12:03.296007 <6>[ 0.968315] EINJ: ACPI disabled.
10538 23:12:03.328689 <4>[ 0.993668] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10539 23:12:03.338028 <4>[ 1.004322] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10540 23:12:03.352577 <6>[ 1.024880] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10541 23:12:03.360567 <6>[ 1.032852] printk: console [ttyS0] disabled
10542 23:12:03.388760 <6>[ 1.057507] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10543 23:12:03.395106 <6>[ 1.067016] printk: console [ttyS0] enabled
10544 23:12:03.398352 <6>[ 1.067016] printk: console [ttyS0] enabled
10545 23:12:03.405373 <6>[ 1.075941] printk: bootconsole [mtk8250] disabled
10546 23:12:03.408084 <6>[ 1.075941] printk: bootconsole [mtk8250] disabled
10547 23:12:03.414956 <6>[ 1.087059] SuperH (H)SCI(F) driver initialized
10548 23:12:03.418183 <6>[ 1.092335] msm_serial: driver initialized
10549 23:12:03.432422 <6>[ 1.101338] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10550 23:12:03.442144 <6>[ 1.109890] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10551 23:12:03.448543 <6>[ 1.118442] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10552 23:12:03.458668 <6>[ 1.127071] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10553 23:12:03.465498 <6>[ 1.135778] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10554 23:12:03.475813 <6>[ 1.144491] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10555 23:12:03.485538 <6>[ 1.153030] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10556 23:12:03.492060 <6>[ 1.161855] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10557 23:12:03.502445 <6>[ 1.170399] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10558 23:12:03.514187 <6>[ 1.186105] loop: module loaded
10559 23:12:03.520448 <6>[ 1.192088] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10560 23:12:03.542969 <4>[ 1.215501] mtk-pmic-keys: Failed to locate of_node [id: -1]
10561 23:12:03.550179 <6>[ 1.222417] megasas: 07.719.03.00-rc1
10562 23:12:03.559816 <6>[ 1.232170] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10563 23:12:03.569849 <6>[ 1.242191] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10564 23:12:03.586824 <6>[ 1.259012] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10565 23:12:03.643343 <6>[ 1.309344] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10566 23:12:04.693777 <6>[ 2.366496] Freeing initrd memory: 38436K
10567 23:12:04.703934 <6>[ 2.376751] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10568 23:12:04.715442 <6>[ 2.387703] tun: Universal TUN/TAP device driver, 1.6
10569 23:12:04.718690 <6>[ 2.393761] thunder_xcv, ver 1.0
10570 23:12:04.721553 <6>[ 2.397266] thunder_bgx, ver 1.0
10571 23:12:04.724952 <6>[ 2.400761] nicpf, ver 1.0
10572 23:12:04.735614 <6>[ 2.404784] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10573 23:12:04.739088 <6>[ 2.412259] hns3: Copyright (c) 2017 Huawei Corporation.
10574 23:12:04.742202 <6>[ 2.417845] hclge is initializing
10575 23:12:04.749293 <6>[ 2.421421] e1000: Intel(R) PRO/1000 Network Driver
10576 23:12:04.756141 <6>[ 2.426550] e1000: Copyright (c) 1999-2006 Intel Corporation.
10577 23:12:04.759192 <6>[ 2.432567] e1000e: Intel(R) PRO/1000 Network Driver
10578 23:12:04.765914 <6>[ 2.437783] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10579 23:12:04.772170 <6>[ 2.443970] igb: Intel(R) Gigabit Ethernet Network Driver
10580 23:12:04.778780 <6>[ 2.449619] igb: Copyright (c) 2007-2014 Intel Corporation.
10581 23:12:04.785521 <6>[ 2.455456] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10582 23:12:04.791910 <6>[ 2.461973] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10583 23:12:04.795103 <6>[ 2.468436] sky2: driver version 1.30
10584 23:12:04.801520 <6>[ 2.473450] VFIO - User Level meta-driver version: 0.3
10585 23:12:04.809159 <6>[ 2.481668] usbcore: registered new interface driver usb-storage
10586 23:12:04.815712 <6>[ 2.488117] usbcore: registered new device driver onboard-usb-hub
10587 23:12:04.824812 <6>[ 2.497300] mt6397-rtc mt6359-rtc: registered as rtc0
10588 23:12:04.834603 <6>[ 2.502765] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-01T23:09:51 UTC (1701472191)
10589 23:12:04.838190 <6>[ 2.512334] i2c_dev: i2c /dev entries driver
10590 23:12:04.854814 <6>[ 2.524118] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10591 23:12:04.875958 <6>[ 2.548116] cpu cpu0: EM: created perf domain
10592 23:12:04.879160 <6>[ 2.553033] cpu cpu4: EM: created perf domain
10593 23:12:04.886301 <6>[ 2.558659] sdhci: Secure Digital Host Controller Interface driver
10594 23:12:04.892807 <6>[ 2.565093] sdhci: Copyright(c) Pierre Ossman
10595 23:12:04.899870 <6>[ 2.570044] Synopsys Designware Multimedia Card Interface Driver
10596 23:12:04.905987 <6>[ 2.576687] sdhci-pltfm: SDHCI platform and OF driver helper
10597 23:12:04.909529 <6>[ 2.576732] mmc0: CQHCI version 5.10
10598 23:12:04.916117 <6>[ 2.586597] ledtrig-cpu: registered to indicate activity on CPUs
10599 23:12:04.922716 <6>[ 2.593523] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10600 23:12:04.929159 <6>[ 2.600568] usbcore: registered new interface driver usbhid
10601 23:12:04.932506 <6>[ 2.606390] usbhid: USB HID core driver
10602 23:12:04.939230 <6>[ 2.610591] spi_master spi0: will run message pump with realtime priority
10603 23:12:04.981604 <6>[ 2.647451] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10604 23:12:05.000254 <6>[ 2.662807] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10605 23:12:05.007242 <6>[ 2.678604] cros-ec-spi spi0.0: Chrome EC device registered
10606 23:12:05.010391 <6>[ 2.678681] mmc0: Command Queue Engine enabled
10607 23:12:05.016832 <6>[ 2.689210] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10608 23:12:05.024161 <6>[ 2.696498] mmcblk0: mmc0:0001 DA4128 116 GiB
10609 23:12:05.036534 <6>[ 2.708836] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10610 23:12:05.043789 <6>[ 2.716318] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10611 23:12:05.053793 <6>[ 2.719515] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10612 23:12:05.057634 <6>[ 2.722217] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10613 23:12:05.063933 <6>[ 2.732033] NET: Registered PF_PACKET protocol family
10614 23:12:05.070775 <6>[ 2.736844] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10615 23:12:05.073939 <6>[ 2.741445] 9pnet: Installing 9P2000 support
10616 23:12:05.080011 <5>[ 2.752446] Key type dns_resolver registered
10617 23:12:05.083859 <6>[ 2.757399] registered taskstats version 1
10618 23:12:05.090265 <5>[ 2.761777] Loading compiled-in X.509 certificates
10619 23:12:05.117851 <4>[ 2.784028] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10620 23:12:05.128087 <4>[ 2.795050] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10621 23:12:05.134850 <3>[ 2.805598] debugfs: File 'uA_load' in directory '/' already present!
10622 23:12:05.140894 <3>[ 2.812356] debugfs: File 'min_uV' in directory '/' already present!
10623 23:12:05.147886 <3>[ 2.818996] debugfs: File 'max_uV' in directory '/' already present!
10624 23:12:05.154564 <3>[ 2.825701] debugfs: File 'constraint_flags' in directory '/' already present!
10625 23:12:05.166158 <3>[ 2.835268] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10626 23:12:05.176003 <6>[ 2.848336] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10627 23:12:05.182491 <6>[ 2.855115] xhci-mtk 11200000.usb: xHCI Host Controller
10628 23:12:05.188995 <6>[ 2.860623] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10629 23:12:05.199526 <6>[ 2.868481] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10630 23:12:05.205849 <6>[ 2.877915] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10631 23:12:05.212399 <6>[ 2.883983] xhci-mtk 11200000.usb: xHCI Host Controller
10632 23:12:05.219447 <6>[ 2.889457] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10633 23:12:05.225835 <6>[ 2.897127] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10634 23:12:05.232910 <6>[ 2.904971] hub 1-0:1.0: USB hub found
10635 23:12:05.235911 <6>[ 2.908995] hub 1-0:1.0: 1 port detected
10636 23:12:05.242410 <6>[ 2.913248] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10637 23:12:05.249866 <6>[ 2.921976] hub 2-0:1.0: USB hub found
10638 23:12:05.252926 <6>[ 2.925995] hub 2-0:1.0: 1 port detected
10639 23:12:05.261400 <6>[ 2.933874] mtk-msdc 11f70000.mmc: Got CD GPIO
10640 23:12:05.272653 <6>[ 2.941453] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10641 23:12:05.278949 <6>[ 2.949504] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10642 23:12:05.288776 <4>[ 2.957473] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10643 23:12:05.298675 <6>[ 2.967006] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10644 23:12:05.305764 <6>[ 2.975108] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10645 23:12:05.311867 <6>[ 2.983111] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10646 23:12:05.322489 <6>[ 2.991041] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10647 23:12:05.328862 <6>[ 2.998859] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10648 23:12:05.338459 <6>[ 3.006679] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10649 23:12:05.348077 <6>[ 3.017107] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10650 23:12:05.354841 <6>[ 3.025466] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10651 23:12:05.365366 <6>[ 3.033829] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10652 23:12:05.371755 <6>[ 3.042169] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10653 23:12:05.381807 <6>[ 3.050519] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10654 23:12:05.388153 <6>[ 3.058861] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10655 23:12:05.398026 <6>[ 3.067212] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10656 23:12:05.404922 <6>[ 3.075553] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10657 23:12:05.414697 <6>[ 3.083903] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10658 23:12:05.424480 <6>[ 3.092246] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10659 23:12:05.431818 <6>[ 3.100595] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10660 23:12:05.441334 <6>[ 3.108937] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10661 23:12:05.447655 <6>[ 3.117275] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10662 23:12:05.457912 <6>[ 3.125614] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10663 23:12:05.464831 <6>[ 3.133952] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10664 23:12:05.470903 <6>[ 3.142677] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10665 23:12:05.477492 <6>[ 3.149868] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10666 23:12:05.483842 <6>[ 3.156688] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10667 23:12:05.493946 <6>[ 3.163464] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10668 23:12:05.500679 <6>[ 3.170403] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10669 23:12:05.507524 <6>[ 3.177247] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10670 23:12:05.516940 <6>[ 3.186373] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10671 23:12:05.527430 <6>[ 3.195491] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10672 23:12:05.536900 <6>[ 3.204785] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10673 23:12:05.546857 <6>[ 3.214275] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10674 23:12:05.553680 <6>[ 3.223749] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10675 23:12:05.563825 <6>[ 3.232870] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10676 23:12:05.573631 <6>[ 3.242337] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10677 23:12:05.583816 <6>[ 3.251457] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10678 23:12:05.594030 <6>[ 3.260750] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10679 23:12:05.603399 <6>[ 3.270913] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10680 23:12:05.613308 <6>[ 3.282403] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10681 23:12:05.642197 <6>[ 3.311349] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10682 23:12:05.670703 <6>[ 3.342752] hub 2-1:1.0: USB hub found
10683 23:12:05.674000 <6>[ 3.347236] hub 2-1:1.0: 3 ports detected
10684 23:12:05.682363 <6>[ 3.354596] hub 2-1:1.0: USB hub found
10685 23:12:05.685158 <6>[ 3.359036] hub 2-1:1.0: 3 ports detected
10686 23:12:05.793899 <6>[ 3.463121] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10687 23:12:05.952613 <6>[ 3.625180] hub 1-1:1.0: USB hub found
10688 23:12:05.955996 <6>[ 3.629736] hub 1-1:1.0: 4 ports detected
10689 23:12:05.965700 <6>[ 3.638642] hub 1-1:1.0: USB hub found
10690 23:12:05.969083 <6>[ 3.643295] hub 1-1:1.0: 4 ports detected
10691 23:12:06.038311 <6>[ 3.707298] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10692 23:12:06.289857 <6>[ 3.959142] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10693 23:12:06.422857 <6>[ 4.095136] hub 1-1.4:1.0: USB hub found
10694 23:12:06.425888 <6>[ 4.099812] hub 1-1.4:1.0: 2 ports detected
10695 23:12:06.435577 <6>[ 4.108156] hub 1-1.4:1.0: USB hub found
10696 23:12:06.439263 <6>[ 4.112744] hub 1-1.4:1.0: 2 ports detected
10697 23:12:06.738012 <6>[ 4.407113] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10698 23:12:06.929464 <6>[ 4.599113] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10699 23:12:17.891323 <6>[ 15.568091] ALSA device list:
10700 23:12:17.898383 <6>[ 15.571384] No soundcards found.
10701 23:12:17.905787 <6>[ 15.579436] Freeing unused kernel memory: 8448K
10702 23:12:17.909259 <6>[ 15.584417] Run /init as init process
10703 23:12:17.958398 <6>[ 15.631340] NET: Registered PF_INET6 protocol family
10704 23:12:17.964392 <6>[ 15.637593] Segment Routing with IPv6
10705 23:12:17.967895 <6>[ 15.641566] In-situ OAM (IOAM) with IPv6
10706 23:12:18.003878 <30>[ 15.657750] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10707 23:12:18.008014 <30>[ 15.681614] systemd[1]: Detected architecture arm64.
10708 23:12:18.008576
10709 23:12:18.014786 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10710 23:12:18.015367
10711 23:12:18.029840 <30>[ 15.703092] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10712 23:12:18.179183 <30>[ 15.849679] systemd[1]: Queued start job for default target Graphical Interface.
10713 23:12:18.226019 <30>[ 15.899849] systemd[1]: Created slice system-getty.slice.
10714 23:12:18.233102 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10715 23:12:18.250282 <30>[ 15.923677] systemd[1]: Created slice system-modprobe.slice.
10716 23:12:18.256675 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10717 23:12:18.274288 <30>[ 15.948346] systemd[1]: Created slice system-serial\x2dgetty.slice.
10718 23:12:18.284348 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10719 23:12:18.297842 <30>[ 15.971563] systemd[1]: Created slice User and Session Slice.
10720 23:12:18.304481 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10721 23:12:18.325318 <30>[ 15.995785] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10722 23:12:18.334991 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10723 23:12:18.353756 <30>[ 16.023840] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10724 23:12:18.360530 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10725 23:12:18.384890 <30>[ 16.051611] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10726 23:12:18.391436 <30>[ 16.063892] systemd[1]: Reached target Local Encrypted Volumes.
10727 23:12:18.398110 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10728 23:12:18.414136 <30>[ 16.087684] systemd[1]: Reached target Paths.
10729 23:12:18.417417 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10730 23:12:18.433218 <30>[ 16.107106] systemd[1]: Reached target Remote File Systems.
10731 23:12:18.439830 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10732 23:12:18.457850 <30>[ 16.131468] systemd[1]: Reached target Slices.
10733 23:12:18.464375 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10734 23:12:18.477445 <30>[ 16.151132] systemd[1]: Reached target Swap.
10735 23:12:18.481014 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10736 23:12:18.501341 <30>[ 16.171593] systemd[1]: Listening on initctl Compatibility Named Pipe.
10737 23:12:18.508375 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10738 23:12:18.514665 <30>[ 16.186739] systemd[1]: Listening on Journal Audit Socket.
10739 23:12:18.520637 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10740 23:12:18.533806 <30>[ 16.207580] systemd[1]: Listening on Journal Socket (/dev/log).
10741 23:12:18.540394 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10742 23:12:18.559114 <30>[ 16.232330] systemd[1]: Listening on Journal Socket.
10743 23:12:18.565288 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10744 23:12:18.581171 <30>[ 16.251792] systemd[1]: Listening on Network Service Netlink Socket.
10745 23:12:18.588421 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10746 23:12:18.602723 <30>[ 16.276316] systemd[1]: Listening on udev Control Socket.
10747 23:12:18.609475 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10748 23:12:18.626842 <30>[ 16.300194] systemd[1]: Listening on udev Kernel Socket.
10749 23:12:18.633850 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10750 23:12:18.690318 <30>[ 16.363322] systemd[1]: Mounting Huge Pages File System...
10751 23:12:18.696861 Mounting [0;1;39mHuge Pages File System[0m...
10752 23:12:18.712652 <30>[ 16.386165] systemd[1]: Mounting POSIX Message Queue File System...
10753 23:12:18.719280 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10754 23:12:18.735550 <30>[ 16.409039] systemd[1]: Mounting Kernel Debug File System...
10755 23:12:18.742208 Mounting [0;1;39mKernel Debug File System[0m...
10756 23:12:18.760889 <30>[ 16.431289] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10757 23:12:18.772938 <30>[ 16.443209] systemd[1]: Starting Create list of static device nodes for the current kernel...
10758 23:12:18.779219 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10759 23:12:18.802158 <30>[ 16.475705] systemd[1]: Starting Load Kernel Module configfs...
10760 23:12:18.808658 Starting [0;1;39mLoad Kernel Module configfs[0m...
10761 23:12:18.825980 <30>[ 16.499788] systemd[1]: Starting Load Kernel Module drm...
10762 23:12:18.832610 Starting [0;1;39mLoad Kernel Module drm[0m...
10763 23:12:18.848874 <30>[ 16.519433] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10764 23:12:18.863488 <30>[ 16.537245] systemd[1]: Starting Journal Service...
10765 23:12:18.866450 Starting [0;1;39mJournal Service[0m...
10766 23:12:18.890661 <30>[ 16.564654] systemd[1]: Starting Load Kernel Modules...
10767 23:12:18.897400 Starting [0;1;39mLoad Kernel Modules[0m...
10768 23:12:18.949799 <30>[ 16.620182] systemd[1]: Starting Remount Root and Kernel File Systems...
10769 23:12:18.955841 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10770 23:12:18.971379 <30>[ 16.644926] systemd[1]: Starting Coldplug All udev Devices...
10771 23:12:18.977807 Starting [0;1;39mColdplug All udev Devices[0m...
10772 23:12:18.996100 <30>[ 16.670079] systemd[1]: Started Journal Service.
10773 23:12:19.002960 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10774 23:12:19.020416 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10775 23:12:19.038160 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10776 23:12:19.054923 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10777 23:12:19.074737 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10778 23:12:19.090708 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10779 23:12:19.107964 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10780 23:12:19.126783 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10781 23:12:19.147787 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10782 23:12:19.161018 See 'systemctl status systemd-remount-fs.service' for details.
10783 23:12:19.214966 Mounting [0;1;39mKernel Configuration File System[0m...
10784 23:12:19.231962 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10785 23:12:19.246143 <46>[ 16.916464] systemd-journald[187]: Received client request to flush runtime journal.
10786 23:12:19.256592 Starting [0;1;39mLoad/Save Random Seed[0m...
10787 23:12:19.277951 Starting [0;1;39mApply Kernel Variables[0m...
10788 23:12:19.302646 Starting [0;1;39mCreate System Users[0m...
10789 23:12:19.326149 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10790 23:12:19.346083 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10791 23:12:19.370111 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10792 23:12:19.387273 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10793 23:12:19.405424 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10794 23:12:19.423262 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10795 23:12:19.453507 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10796 23:12:19.477437 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10797 23:12:19.493499 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10798 23:12:19.509868 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10799 23:12:19.557993 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10800 23:12:19.582373 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10801 23:12:19.603202 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10802 23:12:19.625342 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10803 23:12:19.703887 Starting [0;1;39mNetwork Service[0m...
10804 23:12:19.723517 Starting [0;1;39mNetwork Time Synchronization[0m...
10805 23:12:19.741111 <6>[ 17.411984] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10806 23:12:19.748011 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10807 23:12:19.754230 <6>[ 17.428469] remoteproc remoteproc0: scp is available
10808 23:12:19.761234 <6>[ 17.434056] remoteproc remoteproc0: powering up scp
10809 23:12:19.771590 <6>[ 17.440558] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10810 23:12:19.777811 <6>[ 17.450404] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10811 23:12:19.787889 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10812 23:12:19.803517 <6>[ 17.474178] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10813 23:12:19.809870 <3>[ 17.475502] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10814 23:12:19.820192 <6>[ 17.481882] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10815 23:12:19.827032 <3>[ 17.490306] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10816 23:12:19.836680 <6>[ 17.498827] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10817 23:12:19.843137 <3>[ 17.506783] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10818 23:12:19.852859 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10819 23:12:19.867103 <3>[ 17.537904] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10820 23:12:19.873727 <3>[ 17.546069] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10821 23:12:19.884174 <3>[ 17.554214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10822 23:12:19.890488 <3>[ 17.562310] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10823 23:12:19.901057 <3>[ 17.570393] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10824 23:12:19.910776 <4>[ 17.580439] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10825 23:12:19.917215 <3>[ 17.584863] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10826 23:12:19.923706 <6>[ 17.585143] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10827 23:12:19.933961 <6>[ 17.587821] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10828 23:12:19.940442 <4>[ 17.603456] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10829 23:12:19.947128 <6>[ 17.611444] remoteproc remoteproc0: remote processor scp is now up
10830 23:12:19.953169 <3>[ 17.615706] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10831 23:12:19.963656 <3>[ 17.615728] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10832 23:12:19.970419 <3>[ 17.615741] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10833 23:12:19.980061 <3>[ 17.617061] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10834 23:12:19.986879 <3>[ 17.617071] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10835 23:12:19.993391 <3>[ 17.617075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10836 23:12:20.003006 <3>[ 17.617080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10837 23:12:20.009829 <3>[ 17.617083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10838 23:12:20.019347 <3>[ 17.617105] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 23:12:20.026094 <6>[ 17.624968] usbcore: registered new interface driver r8152
10840 23:12:20.029647 <6>[ 17.624999] mc: Linux media interface: v0.10
10841 23:12:20.036353 <6>[ 17.637850] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10842 23:12:20.042912 <6>[ 17.659267] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10843 23:12:20.053737 <6>[ 17.662977] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10844 23:12:20.063674 <6>[ 17.677667] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10845 23:12:20.069780 <6>[ 17.681849] pci_bus 0000:00: root bus resource [bus 00-ff]
10846 23:12:20.077139 <6>[ 17.681866] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10847 23:12:20.086884 <6>[ 17.681868] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10848 23:12:20.093247 <6>[ 17.681922] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10849 23:12:20.099716 <4>[ 17.700705] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10850 23:12:20.106694 <4>[ 17.700705] Fallback method does not support PEC.
10851 23:12:20.113200 <6>[ 17.703829] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10852 23:12:20.123164 <3>[ 17.725905] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10853 23:12:20.126253 <6>[ 17.733120] pci 0000:00:00.0: supports D1 D2
10854 23:12:20.136308 <6>[ 17.749461] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10855 23:12:20.143340 <6>[ 17.754944] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10856 23:12:20.153943 <6>[ 17.757399] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10857 23:12:20.156761 <6>[ 17.761264] videodev: Linux video capture interface: v2.00
10858 23:12:20.166806 <6>[ 17.765404] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10859 23:12:20.174350 <6>[ 17.778783] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10860 23:12:20.178318 <6>[ 17.794617] usbcore: registered new interface driver cdc_ether
10861 23:12:20.188699 <4>[ 17.807755] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10862 23:12:20.195096 <6>[ 17.807996] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10863 23:12:20.201674 <6>[ 17.808022] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10864 23:12:20.211191 <6>[ 17.808037] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10865 23:12:20.214527 <6>[ 17.808461] pci 0000:01:00.0: supports D1 D2
10866 23:12:20.220872 <6>[ 17.808466] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10867 23:12:20.224701 <6>[ 17.809073] Bluetooth: Core ver 2.22
10868 23:12:20.231981 <6>[ 17.809191] NET: Registered PF_BLUETOOTH protocol family
10869 23:12:20.235730 <6>[ 17.809196] Bluetooth: HCI device and connection manager initialized
10870 23:12:20.242493 <6>[ 17.809235] Bluetooth: HCI socket layer initialized
10871 23:12:20.249632 <6>[ 17.809249] Bluetooth: L2CAP socket layer initialized
10872 23:12:20.252683 <6>[ 17.809278] Bluetooth: SCO socket layer initialized
10873 23:12:20.259647 <6>[ 17.820427] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10874 23:12:20.265957 <4>[ 17.823487] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10875 23:12:20.272894 <6>[ 17.824217] usbcore: registered new interface driver r8153_ecm
10876 23:12:20.280249 <6>[ 17.832050] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10877 23:12:20.289869 <6>[ 17.838528] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10878 23:12:20.297186 <6>[ 17.845106] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10879 23:12:20.310345 <6>[ 17.856681] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10880 23:12:20.317201 <6>[ 17.857219] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10881 23:12:20.324494 <6>[ 17.867197] usbcore: registered new interface driver uvcvideo
10882 23:12:20.330958 <6>[ 17.867429] usbcore: registered new interface driver btusb
10883 23:12:20.341282 <4>[ 17.869136] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10884 23:12:20.345361 <3>[ 17.869162] Bluetooth: hci0: Failed to load firmware file (-2)
10885 23:12:20.351976 <3>[ 17.869171] Bluetooth: hci0: Failed to set up firmware (-2)
10886 23:12:20.361625 <4>[ 17.869180] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10887 23:12:20.371689 <6>[ 17.873775] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10888 23:12:20.378106 <6>[ 17.874948] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10889 23:12:20.384794 <3>[ 17.884466] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 23:12:20.394519 <6>[ 17.888669] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10891 23:12:20.401656 <6>[ 17.890254] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10892 23:12:20.411226 <6>[ 17.891870] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10893 23:12:20.417624 <3>[ 17.915883] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 23:12:20.424170 <6>[ 17.916156] pci 0000:00:00.0: PCI bridge to [bus 01]
10895 23:12:20.430924 <3>[ 17.935657] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 23:12:20.440765 <3>[ 17.938172] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10897 23:12:20.447447 <6>[ 17.938665] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10898 23:12:20.457492 <3>[ 17.956623] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 23:12:20.464128 <6>[ 17.961126] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10900 23:12:20.467345 <6>[ 17.963269] r8152 2-1.3:1.0 eth0: v1.12.13
10901 23:12:20.473982 <6>[ 17.973744] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10902 23:12:20.480421 <6>[ 17.976481] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10903 23:12:20.487022 <3>[ 17.988773] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 23:12:20.493820 <6>[ 17.996985] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10905 23:12:20.503928 <3>[ 18.026907] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 23:12:20.520143 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m..<5>[ 18.189482] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10907 23:12:20.520285 .
10908 23:12:20.532632 <3>[ 18.203103] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 23:12:20.538823 <5>[ 18.207804] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10910 23:12:20.553328 [[0;32m OK [0m] Started [0;1;39mNetwork Tim<4>[ 18.223590] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10911 23:12:20.560602 e Synchronizatio<6>[ 18.233248] cfg80211: failed to load regulatory.db
10912 23:12:20.570365 <3>[ 18.234681] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 23:12:20.570544 n[0m.
10914 23:12:20.591847 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10915 23:12:20.615695 <6>[ 18.285802] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10916 23:12:20.619007 <6>[ 18.293351] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10917 23:12:20.628656 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10918 23:12:20.646107 [[0;32m OK [0m] Finished [0;1;39mLoad/Save <6>[ 18.320033] mt7921e 0000:01:00.0: ASIC revision: 79610010
10919 23:12:20.651983 Screen …s of leds:white:kbd_backlight[0m.
10920 23:12:20.751358 <4>[ 18.418684] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10921 23:12:20.805807 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10922 23:12:20.820974 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10923 23:12:20.840430 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10924 23:12:20.853281 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10925 23:12:20.871466 <4>[ 18.539054] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10926 23:12:20.878294 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10927 23:12:20.901442 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10928 23:12:20.917206 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10929 23:12:20.936818 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10930 23:12:20.948975 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10931 23:12:20.965017 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10932 23:12:20.992496 [[0;32m OK [0m] Listening on [0;1;39mLoad/S<4>[ 18.659943] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10933 23:12:20.996595 ave RF …itch Status /dev/rfkill Watch[0m.
10934 23:12:21.038830 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10935 23:12:21.073790 Starting [0;1;39mUser Login Management[0m...
10936 23:12:21.097726 Starting [0;1;39mNetwork Name Resolution[0m...
10937 23:12:21.121033 <4>[ 18.788563] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10938 23:12:21.127924 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10939 23:12:21.139849 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10940 23:12:21.154268 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10941 23:12:21.169708 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10942 23:12:21.191296 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10943 23:12:21.208632 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10944 23:12:21.255085 <4>[ 18.922778] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10945 23:12:21.261557 Starting [0;1;39mPermit User Sessions[0m...
10946 23:12:21.281628 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10947 23:12:21.302493 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10948 23:12:21.323655 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10949 23:12:21.342425 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10950 23:12:21.359164 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10951 23:12:21.376382 <4>[ 19.043817] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10952 23:12:21.384001 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10953 23:12:21.451536 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10954 23:12:21.502377 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System R<4>[ 19.168817] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10955 23:12:21.502865 unlevel Changes[0m.
10956 23:12:21.542042
10957 23:12:21.542479
10958 23:12:21.545755 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10959 23:12:21.546193
10960 23:12:21.548603 debian-bullseye-arm64 login: root (automatic login)
10961 23:12:21.549025
10962 23:12:21.549359
10963 23:12:21.564542 Linux debian-bullseye-arm64 6.1.64-cip10 #1 SMP PREEMPT Fri Dec 1 22:47:09 UTC 2023 aarch64
10964 23:12:21.564966
10965 23:12:21.571164 The programs included with the Debian GNU/Linux system are free software;
10966 23:12:21.577718 the exact distribution terms for each program are described in the
10967 23:12:21.581168 individual files in /usr/share/doc/*/copyright.
10968 23:12:21.581666
10969 23:12:21.587663 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10970 23:12:21.590853 permitted by applicable law.
10971 23:12:21.592262 Matched prompt #10: / #
10973 23:12:21.593860 Setting prompt string to ['/ #']
10974 23:12:21.594442 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10976 23:12:21.595729 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10977 23:12:21.596394 start: 2.2.6 expect-shell-connection (timeout 00:03:31) [common]
10978 23:12:21.596925 Setting prompt string to ['/ #']
10979 23:12:21.597346 Forcing a shell prompt, looking for ['/ #']
10981 23:12:21.648464 / #
10982 23:12:21.649035 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10983 23:12:21.649512 Waiting using forced prompt support (timeout 00:02:30)
10984 23:12:21.650193 <4>[ 19.291453] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10985 23:12:21.653933
10986 23:12:21.654750 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10987 23:12:21.655309 start: 2.2.7 export-device-env (timeout 00:03:31) [common]
10988 23:12:21.655843 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10989 23:12:21.656491 end: 2.2 depthcharge-retry (duration 00:01:29) [common]
10990 23:12:21.657159 end: 2 depthcharge-action (duration 00:01:29) [common]
10991 23:12:21.657889 start: 3 lava-test-retry (timeout 00:08:11) [common]
10992 23:12:21.658415 start: 3.1 lava-test-shell (timeout 00:08:11) [common]
10993 23:12:21.659030 Using namespace: common
10995 23:12:21.760370 / # #
10996 23:12:21.761070 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10997 23:12:21.761735 #<4>[ 19.411612] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10998 23:12:21.766607
10999 23:12:21.767337 Using /lava-12154446
11001 23:12:21.868462 / # export SHELL=/bin/sh
11002 23:12:21.869326 export SHELL=/bin/sh<4>[ 19.531170] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11003 23:12:21.874245
11005 23:12:21.975901 / # . /lava-12154446/environment
11006 23:12:21.976602 <6>[ 19.565952] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
11007 23:12:21.977066 <6>[ 19.574012] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
11008 23:12:21.977645 . /lava-12154446/environment<3>[ 19.649200] mt7921e 0000:01:00.0: hardware init failed
11009 23:12:21.981755
11011 23:12:22.082990 / # /lava-12154446/bin/lava-test-runner /lava-12154446/0
11012 23:12:22.083118 Test shell timeout: 10s (minimum of the action and connection timeout)
11013 23:12:22.088434 /lava-12154446/bin/lava-test-runner /lava-12154446/0
11014 23:12:22.112207 + export TESTRUN_ID=0_v4l2-compliance-uvc
11015 23:12:22.115451 + cd /lava-12154446/0/tests/0_v4l2-compliance-uvc
11016 23:12:22.115534 + cat uuid
11017 23:12:22.119010 + UUID=12154446_1.5.2.3.1
11018 23:12:22.119093 + set +x
11019 23:12:22.125226 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 12154446_1.5.2.3.1>
11020 23:12:22.125490 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 12154446_1.5.2.3.1
11021 23:12:22.125618 Starting test lava.0_v4l2-compliance-uvc (12154446_1.5.2.3.1)
11022 23:12:22.125724 Skipping test definition patterns.
11023 23:12:22.128520 + /usr/bin/v4l2-parser.sh -d uvcvideo
11024 23:12:22.135238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11025 23:12:22.135320 device: /dev/video0
11026 23:12:22.135555 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11028 23:12:28.627407 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11029 23:12:28.639150 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11030 23:12:28.647062
11031 23:12:28.665889 Compliance test for uvcvideo device /dev/video0:
11032 23:12:28.674336
11033 23:12:28.687355 Driver Info:
11034 23:12:28.700202 Driver name : uvcvideo
11035 23:12:28.719124 Card type : HD User Facing: HD User Facing
11036 23:12:28.730136 Bus info : usb-11200000.usb-1.4.1
11037 23:12:28.741151 Driver version : 6.1.64
11038 23:12:28.753777 Capabilities : 0x84a00001
11039 23:12:28.769834 Metadata Capture
11040 23:12:28.783321 Streaming
11041 23:12:28.795099 Extended Pix Format
11042 23:12:28.811296 Device Capabilities
11043 23:12:28.821828 Device Caps : 0x04200001
11044 23:12:28.837628 Streaming
11045 23:12:28.847006 Extended Pix Format
11046 23:12:28.862715 Media Driver Info:
11047 23:12:28.874952 Driver name : uvcvideo
11048 23:12:28.893256 Model : HD User Facing: HD User Facing
11049 23:12:28.902113 Serial : 200901010001
11050 23:12:28.917077 Bus info : usb-11200000.usb-1.4.1
11051 23:12:28.924830 Media version : 6.1.64
11052 23:12:28.941443 Hardware revision: 0x00009758 (38744)
11053 23:12:28.949162 Driver version : 6.1.64
11054 23:12:28.963016 Interface Info:
11055 23:12:28.979136 <LAVA_SIGNAL_TESTSET START Interface-Info>
11056 23:12:28.979594 ID : 0x03000002
11057 23:12:28.980264 Received signal: <TESTSET> START Interface-Info
11058 23:12:28.980809 Starting test_set Interface-Info
11059 23:12:28.988910 Type : V4L Video
11060 23:12:28.999227 Entity Info:
11061 23:12:29.006665 <LAVA_SIGNAL_TESTSET STOP>
11062 23:12:29.007406 Received signal: <TESTSET> STOP
11063 23:12:29.007773 Closing test_set Interface-Info
11064 23:12:29.015556 <LAVA_SIGNAL_TESTSET START Entity-Info>
11065 23:12:29.016266 Received signal: <TESTSET> START Entity-Info
11066 23:12:29.016623 Starting test_set Entity-Info
11067 23:12:29.019353 ID : 0x00000001 (1)
11068 23:12:29.029213 Name : HD User Facing: HD User Facing
11069 23:12:29.035662 Function : V4L2 I/O
11070 23:12:29.047372 Flags : default
11071 23:12:29.057311 Pad 0x01000007 : 0: Sink
11072 23:12:29.077368 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11073 23:12:29.077846
11074 23:12:29.091660 Required ioctls:
11075 23:12:29.098502 <LAVA_SIGNAL_TESTSET STOP>
11076 23:12:29.099180 Received signal: <TESTSET> STOP
11077 23:12:29.099526 Closing test_set Entity-Info
11078 23:12:29.107716 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11079 23:12:29.108390 Received signal: <TESTSET> START Required-ioctls
11080 23:12:29.108754 Starting test_set Required-ioctls
11081 23:12:29.111064 test MC information (see 'Media Driver Info' above): OK
11082 23:12:29.136816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11083 23:12:29.137454 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11085 23:12:29.139355 test VIDIOC_QUERYCAP: OK
11086 23:12:29.159660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11087 23:12:29.160187 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11089 23:12:29.162727 test invalid ioctls: OK
11090 23:12:29.185961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11091 23:12:29.186383
11092 23:12:29.186849 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11094 23:12:29.197031 Allow for multiple opens:
11095 23:12:29.204103 <LAVA_SIGNAL_TESTSET STOP>
11096 23:12:29.204775 Received signal: <TESTSET> STOP
11097 23:12:29.205156 Closing test_set Required-ioctls
11098 23:12:29.213908 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11099 23:12:29.214531 Received signal: <TESTSET> START Allow-for-multiple-opens
11100 23:12:29.214886 Starting test_set Allow-for-multiple-opens
11101 23:12:29.216747 test second /dev/video0 open: OK
11102 23:12:29.238643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11103 23:12:29.239291 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11105 23:12:29.241884 test VIDIOC_QUERYCAP: OK
11106 23:12:29.263346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11107 23:12:29.263858 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11109 23:12:29.266873 test VIDIOC_G/S_PRIORITY: OK
11110 23:12:29.293979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11111 23:12:29.294624 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11113 23:12:29.297740 test for unlimited opens: OK
11114 23:12:29.319114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11115 23:12:29.319419
11116 23:12:29.319880 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11118 23:12:29.329652 Debug ioctls:
11119 23:12:29.337660 <LAVA_SIGNAL_TESTSET STOP>
11120 23:12:29.338180 Received signal: <TESTSET> STOP
11121 23:12:29.338431 Closing test_set Allow-for-multiple-opens
11122 23:12:29.346898 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11123 23:12:29.347430 Received signal: <TESTSET> START Debug-ioctls
11124 23:12:29.347682 Starting test_set Debug-ioctls
11125 23:12:29.350483 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11126 23:12:29.372165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11127 23:12:29.372691 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11129 23:12:29.378310 test VIDIOC_LOG_STATUS: OK (Not Supported)
11130 23:12:29.396209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11131 23:12:29.396511
11132 23:12:29.396973 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11134 23:12:29.407017 Input ioctls:
11135 23:12:29.418318 <LAVA_SIGNAL_TESTSET STOP>
11136 23:12:29.418839 Received signal: <TESTSET> STOP
11137 23:12:29.419089 Closing test_set Debug-ioctls
11138 23:12:29.428500 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11139 23:12:29.429022 Received signal: <TESTSET> START Input-ioctls
11140 23:12:29.429273 Starting test_set Input-ioctls
11141 23:12:29.431932 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11142 23:12:29.454271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11143 23:12:29.454537 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11145 23:12:29.457855 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11146 23:12:29.477232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11147 23:12:29.477490 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11149 23:12:29.483798 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11150 23:12:29.499804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11151 23:12:29.500073 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11153 23:12:29.506427 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11154 23:12:29.526115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11155 23:12:29.526369 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11157 23:12:29.529135 test VIDIOC_G/S/ENUMINPUT: OK
11158 23:12:29.549971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11159 23:12:29.550223 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11161 23:12:29.553305 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11162 23:12:29.575237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11163 23:12:29.575497 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11165 23:12:29.578482 Inputs: 1 Audio Inputs: 0 Tuners: 0
11166 23:12:29.586002
11167 23:12:29.603912 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11168 23:12:29.629815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11169 23:12:29.630092 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11171 23:12:29.636055 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11172 23:12:29.659614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11173 23:12:29.659986 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11175 23:12:29.666883 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11176 23:12:29.685696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11177 23:12:29.686328 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11179 23:12:29.691858 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11180 23:12:29.710875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11181 23:12:29.711516 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11183 23:12:29.717075 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11184 23:12:29.736073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11185 23:12:29.736162
11186 23:12:29.736400 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11188 23:12:29.755491 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11189 23:12:29.781464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11190 23:12:29.782224 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11192 23:12:29.788173 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11193 23:12:29.810898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11194 23:12:29.811660 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11196 23:12:29.814627 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11197 23:12:29.834088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11198 23:12:29.834800 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11200 23:12:29.836890 test VIDIOC_G/S_EDID: OK (Not Supported)
11201 23:12:29.858721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11202 23:12:29.859228
11203 23:12:29.859830 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11205 23:12:29.868479 Control ioctls (Input 0):
11206 23:12:29.877827 <LAVA_SIGNAL_TESTSET STOP>
11207 23:12:29.878734 Received signal: <TESTSET> STOP
11208 23:12:29.879265 Closing test_set Input-ioctls
11209 23:12:29.888748 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11210 23:12:29.889422 Received signal: <TESTSET> START Control-ioctls-Input-0
11211 23:12:29.889812 Starting test_set Control-ioctls-Input-0
11212 23:12:29.892359 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11213 23:12:29.917843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11214 23:12:29.918362 test VIDIOC_QUERYCTRL: OK
11215 23:12:29.919113 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11217 23:12:29.946665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11218 23:12:29.947529 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11220 23:12:29.949399 test VIDIOC_G/S_CTRL: OK
11221 23:12:29.970821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11222 23:12:29.971760 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11224 23:12:29.973824 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11225 23:12:30.001098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11226 23:12:30.002066 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11228 23:12:30.007351 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11229 23:12:30.028434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11230 23:12:30.029200 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11232 23:12:30.032352 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11233 23:12:30.050258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11234 23:12:30.051088 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11236 23:12:30.053137 Standard Controls: 16 Private Controls: 0
11237 23:12:30.061704
11238 23:12:30.070733 Format ioctls (Input 0):
11239 23:12:30.079078 <LAVA_SIGNAL_TESTSET STOP>
11240 23:12:30.079560 Received signal: <TESTSET> STOP
11241 23:12:30.079834 Closing test_set Control-ioctls-Input-0
11242 23:12:30.088282 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11243 23:12:30.088776 Received signal: <TESTSET> START Format-ioctls-Input-0
11244 23:12:30.088984 Starting test_set Format-ioctls-Input-0
11245 23:12:30.091775 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11246 23:12:30.116896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11247 23:12:30.117356 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11249 23:12:30.120061 test VIDIOC_G/S_PARM: OK
11250 23:12:30.139437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11251 23:12:30.139955 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11253 23:12:30.143237 test VIDIOC_G_FBUF: OK (Not Supported)
11254 23:12:30.165136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11255 23:12:30.165760 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11257 23:12:30.168560 test VIDIOC_G_FMT: OK
11258 23:12:30.190119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11259 23:12:30.190739 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11261 23:12:30.193324 test VIDIOC_TRY_FMT: OK
11262 23:12:30.221274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11263 23:12:30.221955 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11265 23:12:30.227786 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11266 23:12:30.231774 test VIDIOC_S_FMT: OK
11267 23:12:30.255882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11268 23:12:30.256504 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11270 23:12:30.259102 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11271 23:12:30.284265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11272 23:12:30.284932 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11274 23:12:30.287714 test Cropping: OK (Not Supported)
11275 23:12:30.310196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11276 23:12:30.310910 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11278 23:12:30.314134 test Composing: OK (Not Supported)
11279 23:12:30.334620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11280 23:12:30.335303 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11282 23:12:30.337631 test Scaling: OK (Not Supported)
11283 23:12:30.360585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11284 23:12:30.361081
11285 23:12:30.361754 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11287 23:12:30.370567 Codec ioctls (Input 0):
11288 23:12:30.379256 <LAVA_SIGNAL_TESTSET STOP>
11289 23:12:30.379956 Received signal: <TESTSET> STOP
11290 23:12:30.380305 Closing test_set Format-ioctls-Input-0
11291 23:12:30.389947 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11292 23:12:30.390718 Received signal: <TESTSET> START Codec-ioctls-Input-0
11293 23:12:30.391192 Starting test_set Codec-ioctls-Input-0
11294 23:12:30.393569 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11295 23:12:30.414147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11296 23:12:30.414882 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11298 23:12:30.420819 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11299 23:12:30.439159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11300 23:12:30.439915 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11302 23:12:30.445652 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11303 23:12:30.464583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11304 23:12:30.464670
11305 23:12:30.464905 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11307 23:12:30.478079 Buffer ioctls (Input 0):
11308 23:12:30.484967 <LAVA_SIGNAL_TESTSET STOP>
11309 23:12:30.485244 Received signal: <TESTSET> STOP
11310 23:12:30.485328 Closing test_set Codec-ioctls-Input-0
11311 23:12:30.495811 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11312 23:12:30.496139 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11313 23:12:30.496270 Starting test_set Buffer-ioctls-Input-0
11314 23:12:30.499006 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11315 23:12:30.523739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11316 23:12:30.523984 test VIDIOC_EXPBUF: OK
11317 23:12:30.524385 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11319 23:12:30.544021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11320 23:12:30.544906 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11322 23:12:30.547435 test Requests: OK (Not Supported)
11323 23:12:30.571054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11324 23:12:30.571517
11325 23:12:30.572140 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11327 23:12:30.581845 Test input 0:
11328 23:12:30.591461
11329 23:12:30.610003 Streaming ioctls:
11330 23:12:30.617680 <LAVA_SIGNAL_TESTSET STOP>
11331 23:12:30.618467 Received signal: <TESTSET> STOP
11332 23:12:30.618923 Closing test_set Buffer-ioctls-Input-0
11333 23:12:30.627459 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11334 23:12:30.628314 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11335 23:12:30.628831 Starting test_set Streaming-ioctls_Test-input-0
11336 23:12:30.630493 test read/write: OK (Not Supported)
11337 23:12:30.653411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11338 23:12:30.654320 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11340 23:12:30.657104 test blocking wait: OK
11341 23:12:30.677891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11342 23:12:30.678534 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11344 23:12:30.687875 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11345 23:12:30.688277 test MMAP (no poll): FAIL
11346 23:12:30.715482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11347 23:12:30.716024 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11349 23:12:30.725533 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11350 23:12:30.732078 test MMAP (select): FAIL
11351 23:12:30.757365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11352 23:12:30.757936 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11354 23:12:30.767375 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11355 23:12:30.770205 test MMAP (epoll): FAIL
11356 23:12:30.796574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11357 23:12:30.797017
11358 23:12:30.797671 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11360 23:12:30.809940
11361 23:12:30.995390
11362 23:12:31.002555 test USERPTR (no poll): OK
11363 23:12:31.033030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11364 23:12:31.033529
11365 23:12:31.034253 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11367 23:12:31.046215
11368 23:12:31.234143
11369 23:12:31.245042 test USERPTR (select): OK
11370 23:12:31.269514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11371 23:12:31.270056 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11373 23:12:31.275451 test DMABUF: Cannot test, specify --expbuf-device
11374 23:12:31.282838
11375 23:12:31.305083 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11376 23:12:31.307912 <LAVA_TEST_RUNNER EXIT>
11377 23:12:31.308394 ok: lava_test_shell seems to have completed
11378 23:12:31.308663 Marking unfinished test run as failed
11380 23:12:31.312039 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11381 23:12:31.312475 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11382 23:12:31.312769 end: 3 lava-test-retry (duration 00:00:10) [common]
11383 23:12:31.313096 start: 4 finalize (timeout 00:08:02) [common]
11384 23:12:31.313449 start: 4.1 power-off (timeout 00:00:30) [common]
11385 23:12:31.313998 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11386 23:12:31.428738 >> Command sent successfully.
11387 23:12:31.442076 Returned 0 in 0 seconds
11388 23:12:31.543016 end: 4.1 power-off (duration 00:00:00) [common]
11390 23:12:31.543699 start: 4.2 read-feedback (timeout 00:08:02) [common]
11391 23:12:31.544211 Listened to connection for namespace 'common' for up to 1s
11392 23:12:32.545155 Finalising connection for namespace 'common'
11393 23:12:32.545812 Disconnecting from shell: Finalise
11394 23:12:32.546193 / #
11395 23:12:32.647122 end: 4.2 read-feedback (duration 00:00:01) [common]
11396 23:12:32.647766 end: 4 finalize (duration 00:00:01) [common]
11397 23:12:32.648340 Cleaning after the job
11398 23:12:32.648817 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154446/tftp-deploy-g5gjd_yr/ramdisk
11399 23:12:32.669973 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154446/tftp-deploy-g5gjd_yr/kernel
11400 23:12:32.694482 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154446/tftp-deploy-g5gjd_yr/dtb
11401 23:12:32.694709 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12154446/tftp-deploy-g5gjd_yr/modules
11402 23:12:32.702884 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12154446
11403 23:12:32.769529 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12154446
11404 23:12:32.769724 Job finished correctly