Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 17
- Kernel Errors: 36
- Errors: 1
1 05:52:23.343398 lava-dispatcher, installed at version: 2023.10
2 05:52:23.343608 start: 0 validate
3 05:52:23.343743 Start time: 2023-12-25 05:52:23.343735+00:00 (UTC)
4 05:52:23.343877 Using caching service: 'http://localhost/cache/?uri=%s'
5 05:52:23.344013 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 05:52:23.613090 Using caching service: 'http://localhost/cache/?uri=%s'
7 05:52:23.613787 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 05:52:40.620491 Using caching service: 'http://localhost/cache/?uri=%s'
9 05:52:40.620720 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 05:52:40.878575 Using caching service: 'http://localhost/cache/?uri=%s'
11 05:52:40.878743 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:52:41.401472 Using caching service: 'http://localhost/cache/?uri=%s'
13 05:52:41.401689 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 05:52:44.407259 validate duration: 21.06
16 05:52:44.407665 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:52:44.407822 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:52:44.407972 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:52:44.408170 Not decompressing ramdisk as can be used compressed.
20 05:52:44.408307 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 05:52:44.408403 saving as /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/ramdisk/initrd.cpio.gz
22 05:52:44.408499 total size: 4665412 (4 MB)
23 05:52:44.673526 progress 0 % (0 MB)
24 05:52:44.675086 progress 5 % (0 MB)
25 05:52:44.676403 progress 10 % (0 MB)
26 05:52:44.677963 progress 15 % (0 MB)
27 05:52:44.679250 progress 20 % (0 MB)
28 05:52:44.680463 progress 25 % (1 MB)
29 05:52:44.681710 progress 30 % (1 MB)
30 05:52:44.683073 progress 35 % (1 MB)
31 05:52:44.684283 progress 40 % (1 MB)
32 05:52:44.685815 progress 45 % (2 MB)
33 05:52:44.687063 progress 50 % (2 MB)
34 05:52:44.688264 progress 55 % (2 MB)
35 05:52:44.689689 progress 60 % (2 MB)
36 05:52:44.690939 progress 65 % (2 MB)
37 05:52:44.692142 progress 70 % (3 MB)
38 05:52:44.693346 progress 75 % (3 MB)
39 05:52:44.694701 progress 80 % (3 MB)
40 05:52:44.696064 progress 85 % (3 MB)
41 05:52:44.697259 progress 90 % (4 MB)
42 05:52:44.698606 progress 95 % (4 MB)
43 05:52:44.699829 progress 100 % (4 MB)
44 05:52:44.699982 4 MB downloaded in 0.29 s (15.26 MB/s)
45 05:52:44.700143 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:52:44.700386 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:52:44.700474 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:52:44.700559 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:52:44.700692 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 05:52:44.700762 saving as /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/kernel/Image
52 05:52:44.700824 total size: 50024960 (47 MB)
53 05:52:44.700886 No compression specified
54 05:52:44.702018 progress 0 % (0 MB)
55 05:52:44.715287 progress 5 % (2 MB)
56 05:52:44.728648 progress 10 % (4 MB)
57 05:52:44.742102 progress 15 % (7 MB)
58 05:52:44.755744 progress 20 % (9 MB)
59 05:52:44.768862 progress 25 % (11 MB)
60 05:52:44.782099 progress 30 % (14 MB)
61 05:52:44.795362 progress 35 % (16 MB)
62 05:52:44.809112 progress 40 % (19 MB)
63 05:52:44.822185 progress 45 % (21 MB)
64 05:52:44.835537 progress 50 % (23 MB)
65 05:52:44.848658 progress 55 % (26 MB)
66 05:52:44.862252 progress 60 % (28 MB)
67 05:52:44.875466 progress 65 % (31 MB)
68 05:52:44.888419 progress 70 % (33 MB)
69 05:52:44.901617 progress 75 % (35 MB)
70 05:52:44.914930 progress 80 % (38 MB)
71 05:52:44.927927 progress 85 % (40 MB)
72 05:52:44.940937 progress 90 % (42 MB)
73 05:52:44.954006 progress 95 % (45 MB)
74 05:52:44.967062 progress 100 % (47 MB)
75 05:52:44.967325 47 MB downloaded in 0.27 s (179.02 MB/s)
76 05:52:44.967489 end: 1.2.1 http-download (duration 00:00:00) [common]
78 05:52:44.967726 end: 1.2 download-retry (duration 00:00:00) [common]
79 05:52:44.967814 start: 1.3 download-retry (timeout 00:09:59) [common]
80 05:52:44.967904 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 05:52:44.968085 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 05:52:44.968176 saving as /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/dtb/mt8192-asurada-spherion-r0.dtb
83 05:52:44.968254 total size: 47278 (0 MB)
84 05:52:44.968317 No compression specified
85 05:52:44.969484 progress 69 % (0 MB)
86 05:52:44.969843 progress 100 % (0 MB)
87 05:52:44.970047 0 MB downloaded in 0.00 s (25.18 MB/s)
88 05:52:44.970175 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:52:44.970407 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:52:44.970496 start: 1.4 download-retry (timeout 00:09:59) [common]
92 05:52:44.970581 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 05:52:44.970718 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 05:52:44.970817 saving as /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/nfsrootfs/full.rootfs.tar
95 05:52:44.970881 total size: 125290964 (119 MB)
96 05:52:44.970959 Using unxz to decompress xz
97 05:52:44.974791 progress 0 % (0 MB)
98 05:52:45.301441 progress 5 % (6 MB)
99 05:52:45.634820 progress 10 % (11 MB)
100 05:52:45.961667 progress 15 % (17 MB)
101 05:52:46.149872 progress 20 % (23 MB)
102 05:52:46.326739 progress 25 % (29 MB)
103 05:52:46.683393 progress 30 % (35 MB)
104 05:52:47.044427 progress 35 % (41 MB)
105 05:52:47.442352 progress 40 % (47 MB)
106 05:52:47.821969 progress 45 % (53 MB)
107 05:52:48.214661 progress 50 % (59 MB)
108 05:52:48.575979 progress 55 % (65 MB)
109 05:52:48.943046 progress 60 % (71 MB)
110 05:52:49.284620 progress 65 % (77 MB)
111 05:52:49.646196 progress 70 % (83 MB)
112 05:52:50.027717 progress 75 % (89 MB)
113 05:52:50.449842 progress 80 % (95 MB)
114 05:52:50.867521 progress 85 % (101 MB)
115 05:52:51.115986 progress 90 % (107 MB)
116 05:52:51.467387 progress 95 % (113 MB)
117 05:52:51.847489 progress 100 % (119 MB)
118 05:52:51.853324 119 MB downloaded in 6.88 s (17.36 MB/s)
119 05:52:51.853597 end: 1.4.1 http-download (duration 00:00:07) [common]
121 05:52:51.853870 end: 1.4 download-retry (duration 00:00:07) [common]
122 05:52:51.853969 start: 1.5 download-retry (timeout 00:09:53) [common]
123 05:52:51.854062 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 05:52:51.854218 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 05:52:51.854291 saving as /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/modules/modules.tar
126 05:52:51.854355 total size: 8619328 (8 MB)
127 05:52:51.854419 Using unxz to decompress xz
128 05:52:51.858175 progress 0 % (0 MB)
129 05:52:51.879858 progress 5 % (0 MB)
130 05:52:51.903941 progress 10 % (0 MB)
131 05:52:51.928529 progress 15 % (1 MB)
132 05:52:51.952958 progress 20 % (1 MB)
133 05:52:51.977284 progress 25 % (2 MB)
134 05:52:52.003498 progress 30 % (2 MB)
135 05:52:52.030877 progress 35 % (2 MB)
136 05:52:52.054464 progress 40 % (3 MB)
137 05:52:52.080545 progress 45 % (3 MB)
138 05:52:52.109242 progress 50 % (4 MB)
139 05:52:52.136436 progress 55 % (4 MB)
140 05:52:52.161205 progress 60 % (4 MB)
141 05:52:52.187005 progress 65 % (5 MB)
142 05:52:52.214407 progress 70 % (5 MB)
143 05:52:52.238077 progress 75 % (6 MB)
144 05:52:52.265187 progress 80 % (6 MB)
145 05:52:52.292202 progress 85 % (7 MB)
146 05:52:52.325933 progress 90 % (7 MB)
147 05:52:52.361539 progress 95 % (7 MB)
148 05:52:52.392492 progress 100 % (8 MB)
149 05:52:52.397481 8 MB downloaded in 0.54 s (15.13 MB/s)
150 05:52:52.397745 end: 1.5.1 http-download (duration 00:00:01) [common]
152 05:52:52.398148 end: 1.5 download-retry (duration 00:00:01) [common]
153 05:52:52.398281 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 05:52:52.398396 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 05:52:54.391281 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12379433/extract-nfsrootfs-cgiogds6
156 05:52:54.391512 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 05:52:54.391622 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 05:52:54.391819 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz
159 05:52:54.391962 makedir: /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin
160 05:52:54.392073 makedir: /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/tests
161 05:52:54.392168 makedir: /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/results
162 05:52:54.392271 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-add-keys
163 05:52:54.392410 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-add-sources
164 05:52:54.392534 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-background-process-start
165 05:52:54.392659 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-background-process-stop
166 05:52:54.392780 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-common-functions
167 05:52:54.392952 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-echo-ipv4
168 05:52:54.393126 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-install-packages
169 05:52:54.393272 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-installed-packages
170 05:52:54.393393 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-os-build
171 05:52:54.393514 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-probe-channel
172 05:52:54.393634 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-probe-ip
173 05:52:54.393754 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-target-ip
174 05:52:54.393877 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-target-mac
175 05:52:54.394064 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-target-storage
176 05:52:54.394190 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-test-case
177 05:52:54.394312 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-test-event
178 05:52:54.394431 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-test-feedback
179 05:52:54.394550 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-test-raise
180 05:52:54.394668 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-test-reference
181 05:52:54.394787 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-test-runner
182 05:52:54.394936 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-test-set
183 05:52:54.395083 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-test-shell
184 05:52:54.395233 Updating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-install-packages (oe)
185 05:52:54.395386 Updating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/bin/lava-installed-packages (oe)
186 05:52:54.395511 Creating /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/environment
187 05:52:54.395606 LAVA metadata
188 05:52:54.395678 - LAVA_JOB_ID=12379433
189 05:52:54.395741 - LAVA_DISPATCHER_IP=192.168.201.1
190 05:52:54.395852 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 05:52:54.395919 skipped lava-vland-overlay
192 05:52:54.395994 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 05:52:54.396073 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 05:52:54.396138 skipped lava-multinode-overlay
195 05:52:54.396212 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 05:52:54.396289 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 05:52:54.396365 Loading test definitions
198 05:52:54.396453 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 05:52:54.396524 Using /lava-12379433 at stage 0
200 05:52:54.396819 uuid=12379433_1.6.2.3.1 testdef=None
201 05:52:54.396911 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 05:52:54.396997 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 05:52:54.397492 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 05:52:54.397720 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 05:52:54.398774 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 05:52:54.399022 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 05:52:54.399625 runner path: /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/0/tests/0_dmesg test_uuid 12379433_1.6.2.3.1
210 05:52:54.399776 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 05:52:54.400005 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 05:52:54.400080 Using /lava-12379433 at stage 1
214 05:52:54.400366 uuid=12379433_1.6.2.3.5 testdef=None
215 05:52:54.400455 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 05:52:54.400541 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 05:52:54.400992 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 05:52:54.401211 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 05:52:54.401880 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 05:52:54.402137 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 05:52:54.402741 runner path: /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/1/tests/1_bootrr test_uuid 12379433_1.6.2.3.5
224 05:52:54.402889 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 05:52:54.403096 Creating lava-test-runner.conf files
227 05:52:54.403160 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/0 for stage 0
228 05:52:54.403248 - 0_dmesg
229 05:52:54.403327 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379433/lava-overlay-c4p_f_rz/lava-12379433/1 for stage 1
230 05:52:54.403415 - 1_bootrr
231 05:52:54.403509 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 05:52:54.403594 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 05:52:54.410850 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 05:52:54.410995 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 05:52:54.411087 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 05:52:54.411175 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 05:52:54.411262 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 05:52:54.526434 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 05:52:54.526799 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 05:52:54.526922 extracting modules file /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379433/extract-nfsrootfs-cgiogds6
241 05:52:54.763372 extracting modules file /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379433/extract-overlay-ramdisk-7r0_bd8u/ramdisk
242 05:52:54.988533 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 05:52:54.988707 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 05:52:54.988807 [common] Applying overlay to NFS
245 05:52:54.988884 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379433/compress-overlay-4vk5mm53/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12379433/extract-nfsrootfs-cgiogds6
246 05:52:54.996919 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 05:52:54.997070 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 05:52:54.997164 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 05:52:54.997255 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 05:52:54.997338 Building ramdisk /var/lib/lava/dispatcher/tmp/12379433/extract-overlay-ramdisk-7r0_bd8u/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12379433/extract-overlay-ramdisk-7r0_bd8u/ramdisk
251 05:52:55.300822 >> 119415 blocks
252 05:52:57.232728 rename /var/lib/lava/dispatcher/tmp/12379433/extract-overlay-ramdisk-7r0_bd8u/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/ramdisk/ramdisk.cpio.gz
253 05:52:57.233181 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 05:52:57.233325 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 05:52:57.233445 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 05:52:57.233563 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/kernel/Image'
257 05:53:09.813362 Returned 0 in 12 seconds
258 05:53:09.913986 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/kernel/image.itb
259 05:53:10.241285 output: FIT description: Kernel Image image with one or more FDT blobs
260 05:53:10.241633 output: Created: Mon Dec 25 05:53:10 2023
261 05:53:10.241710 output: Image 0 (kernel-1)
262 05:53:10.241776 output: Description:
263 05:53:10.241839 output: Created: Mon Dec 25 05:53:10 2023
264 05:53:10.241909 output: Type: Kernel Image
265 05:53:10.242011 output: Compression: lzma compressed
266 05:53:10.242070 output: Data Size: 11481830 Bytes = 11212.72 KiB = 10.95 MiB
267 05:53:10.242130 output: Architecture: AArch64
268 05:53:10.242189 output: OS: Linux
269 05:53:10.242249 output: Load Address: 0x00000000
270 05:53:10.242303 output: Entry Point: 0x00000000
271 05:53:10.242361 output: Hash algo: crc32
272 05:53:10.242418 output: Hash value: a47c00f1
273 05:53:10.242475 output: Image 1 (fdt-1)
274 05:53:10.242528 output: Description: mt8192-asurada-spherion-r0
275 05:53:10.242583 output: Created: Mon Dec 25 05:53:10 2023
276 05:53:10.242637 output: Type: Flat Device Tree
277 05:53:10.242690 output: Compression: uncompressed
278 05:53:10.242744 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 05:53:10.242797 output: Architecture: AArch64
280 05:53:10.242850 output: Hash algo: crc32
281 05:53:10.242903 output: Hash value: cc4352de
282 05:53:10.242956 output: Image 2 (ramdisk-1)
283 05:53:10.243008 output: Description: unavailable
284 05:53:10.243061 output: Created: Mon Dec 25 05:53:10 2023
285 05:53:10.243114 output: Type: RAMDisk Image
286 05:53:10.243168 output: Compression: Unknown Compression
287 05:53:10.243220 output: Data Size: 17804565 Bytes = 17387.27 KiB = 16.98 MiB
288 05:53:10.243274 output: Architecture: AArch64
289 05:53:10.243326 output: OS: Linux
290 05:53:10.243379 output: Load Address: unavailable
291 05:53:10.243433 output: Entry Point: unavailable
292 05:53:10.243485 output: Hash algo: crc32
293 05:53:10.243538 output: Hash value: 35b47f3c
294 05:53:10.243591 output: Default Configuration: 'conf-1'
295 05:53:10.243644 output: Configuration 0 (conf-1)
296 05:53:10.243696 output: Description: mt8192-asurada-spherion-r0
297 05:53:10.243749 output: Kernel: kernel-1
298 05:53:10.243801 output: Init Ramdisk: ramdisk-1
299 05:53:10.243855 output: FDT: fdt-1
300 05:53:10.243907 output: Loadables: kernel-1
301 05:53:10.243959 output:
302 05:53:10.244147 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 05:53:10.244249 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 05:53:10.244351 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 05:53:10.244444 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
306 05:53:10.244520 No LXC device requested
307 05:53:10.244597 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 05:53:10.244681 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
309 05:53:10.244757 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 05:53:10.244825 Checking files for TFTP limit of 4294967296 bytes.
311 05:53:10.245303 end: 1 tftp-deploy (duration 00:00:26) [common]
312 05:53:10.245408 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 05:53:10.245505 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 05:53:10.245633 substitutions:
315 05:53:10.245701 - {DTB}: 12379433/tftp-deploy-cd2_bfbv/dtb/mt8192-asurada-spherion-r0.dtb
316 05:53:10.245766 - {INITRD}: 12379433/tftp-deploy-cd2_bfbv/ramdisk/ramdisk.cpio.gz
317 05:53:10.245826 - {KERNEL}: 12379433/tftp-deploy-cd2_bfbv/kernel/Image
318 05:53:10.245884 - {LAVA_MAC}: None
319 05:53:10.245963 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12379433/extract-nfsrootfs-cgiogds6
320 05:53:10.246037 - {NFS_SERVER_IP}: 192.168.201.1
321 05:53:10.246093 - {PRESEED_CONFIG}: None
322 05:53:10.246148 - {PRESEED_LOCAL}: None
323 05:53:10.246203 - {RAMDISK}: 12379433/tftp-deploy-cd2_bfbv/ramdisk/ramdisk.cpio.gz
324 05:53:10.246258 - {ROOT_PART}: None
325 05:53:10.246312 - {ROOT}: None
326 05:53:10.246368 - {SERVER_IP}: 192.168.201.1
327 05:53:10.246422 - {TEE}: None
328 05:53:10.246477 Parsed boot commands:
329 05:53:10.246532 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 05:53:10.246703 Parsed boot commands: tftpboot 192.168.201.1 12379433/tftp-deploy-cd2_bfbv/kernel/image.itb 12379433/tftp-deploy-cd2_bfbv/kernel/cmdline
331 05:53:10.246792 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 05:53:10.246876 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 05:53:10.246965 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 05:53:10.247052 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 05:53:10.247122 Not connected, no need to disconnect.
336 05:53:10.247197 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 05:53:10.247280 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 05:53:10.247346 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
339 05:53:10.250907 Setting prompt string to ['lava-test: # ']
340 05:53:10.251370 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 05:53:10.251552 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 05:53:10.251785 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 05:53:10.251922 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 05:53:10.252135 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
345 05:53:15.389042 >> Command sent successfully.
346 05:53:15.391447 Returned 0 in 5 seconds
347 05:53:15.491901 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 05:53:15.492307 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 05:53:15.492423 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 05:53:15.492524 Setting prompt string to 'Starting depthcharge on Spherion...'
352 05:53:15.492606 Changing prompt to 'Starting depthcharge on Spherion...'
353 05:53:15.492695 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 05:53:15.493078 [Enter `^Ec?' for help]
355 05:53:15.666624
356 05:53:15.666790
357 05:53:15.666890 F0: 102B 0000
358 05:53:15.666977
359 05:53:15.667057 F3: 1001 0000 [0200]
360 05:53:15.667136
361 05:53:15.670263 F3: 1001 0000
362 05:53:15.670397
363 05:53:15.670510 F7: 102D 0000
364 05:53:15.670620
365 05:53:15.670682 F1: 0000 0000
366 05:53:15.674561
367 05:53:15.674674 V0: 0000 0000 [0001]
368 05:53:15.674745
369 05:53:15.674810 00: 0007 8000
370 05:53:15.674879
371 05:53:15.678085 01: 0000 0000
372 05:53:15.678188
373 05:53:15.678258 BP: 0C00 0209 [0000]
374 05:53:15.678322
375 05:53:15.678388 G0: 1182 0000
376 05:53:15.681623
377 05:53:15.681722 EC: 0000 0021 [4000]
378 05:53:15.681792
379 05:53:15.685761 S7: 0000 0000 [0000]
380 05:53:15.685877
381 05:53:15.685976 CC: 0000 0000 [0001]
382 05:53:15.686056
383 05:53:15.688808 T0: 0000 0040 [010F]
384 05:53:15.688906
385 05:53:15.688976 Jump to BL
386 05:53:15.689039
387 05:53:15.713400
388 05:53:15.713564
389 05:53:15.713639
390 05:53:15.721110 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 05:53:15.724484 ARM64: Exception handlers installed.
392 05:53:15.728519 ARM64: Testing exception
393 05:53:15.732108 ARM64: Done test exception
394 05:53:15.739571 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 05:53:15.746193 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 05:53:15.753632 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 05:53:15.764308 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 05:53:15.770926 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 05:53:15.781115 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 05:53:15.791987 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 05:53:15.798626 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 05:53:15.816405 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 05:53:15.819966 WDT: Last reset was cold boot
404 05:53:15.822832 SPI1(PAD0) initialized at 2873684 Hz
405 05:53:15.826281 SPI5(PAD0) initialized at 992727 Hz
406 05:53:15.829480 VBOOT: Loading verstage.
407 05:53:15.836249 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 05:53:15.839980 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 05:53:15.842920 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 05:53:15.846391 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 05:53:15.853806 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 05:53:15.860423 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 05:53:15.871318 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 05:53:15.871482
415 05:53:15.871558
416 05:53:15.881220 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 05:53:15.884967 ARM64: Exception handlers installed.
418 05:53:15.887809 ARM64: Testing exception
419 05:53:15.887925 ARM64: Done test exception
420 05:53:15.894693 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 05:53:15.897782 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 05:53:15.912432 Probing TPM: . done!
423 05:53:15.912593 TPM ready after 0 ms
424 05:53:15.919138 Connected to device vid:did:rid of 1ae0:0028:00
425 05:53:15.926662 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 05:53:15.982353 Initialized TPM device CR50 revision 0
427 05:53:15.994080 tlcl_send_startup: Startup return code is 0
428 05:53:15.994268 TPM: setup succeeded
429 05:53:16.005407 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 05:53:16.014498 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 05:53:16.024806 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 05:53:16.033880 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 05:53:16.037310 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 05:53:16.045096 in-header: 03 07 00 00 08 00 00 00
435 05:53:16.048766 in-data: aa e4 47 04 13 02 00 00
436 05:53:16.053125 Chrome EC: UHEPI supported
437 05:53:16.060448 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 05:53:16.064279 in-header: 03 ad 00 00 08 00 00 00
439 05:53:16.067812 in-data: 00 20 20 08 00 00 00 00
440 05:53:16.067939 Phase 1
441 05:53:16.071232 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 05:53:16.078432 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 05:53:16.082681 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 05:53:16.085798 Recovery requested (1009000e)
445 05:53:16.093770 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 05:53:16.099691 tlcl_extend: response is 0
447 05:53:16.108765 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 05:53:16.114489 tlcl_extend: response is 0
449 05:53:16.121412 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 05:53:16.141608 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 05:53:16.148635 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 05:53:16.148795
453 05:53:16.148870
454 05:53:16.159055 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 05:53:16.161970 ARM64: Exception handlers installed.
456 05:53:16.162111 ARM64: Testing exception
457 05:53:16.165685 ARM64: Done test exception
458 05:53:16.184248 pmic_efuse_setting: Set efuses in 11 msecs
459 05:53:16.192156 pmwrap_interface_init: Select PMIF_VLD_RDY
460 05:53:16.195652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 05:53:16.202905 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 05:53:16.206252 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 05:53:16.209222 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 05:53:16.216263 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 05:53:16.220667 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 05:53:16.223955 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 05:53:16.231385 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 05:53:16.235294 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 05:53:16.238874 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 05:53:16.242363 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 05:53:16.249664 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 05:53:16.253038 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 05:53:16.259525 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 05:53:16.266231 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 05:53:16.269702 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 05:53:16.277087 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 05:53:16.281014 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 05:53:16.288461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 05:53:16.294889 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 05:53:16.298344 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 05:53:16.305266 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 05:53:16.308731 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 05:53:16.315224 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 05:53:16.321889 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 05:53:16.325401 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 05:53:16.331784 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 05:53:16.335328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 05:53:16.341819 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 05:53:16.345351 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 05:53:16.352121 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 05:53:16.355081 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 05:53:16.362168 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 05:53:16.365326 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 05:53:16.372187 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 05:53:16.375258 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 05:53:16.382133 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 05:53:16.385523 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 05:53:16.388959 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 05:53:16.395911 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 05:53:16.398867 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 05:53:16.402156 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 05:53:16.409376 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 05:53:16.412817 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 05:53:16.416522 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 05:53:16.419908 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 05:53:16.426770 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 05:53:16.429754 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 05:53:16.433035 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 05:53:16.436446 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 05:53:16.443216 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 05:53:16.449815 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 05:53:16.459972 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 05:53:16.463013 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 05:53:16.469797 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 05:53:16.479556 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 05:53:16.483470 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 05:53:16.489972 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 05:53:16.492819 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 05:53:16.500001 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x13
520 05:53:16.506743 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 05:53:16.510080 [RTC]rtc_osc_init,62: osc32con val = 0xde70
522 05:53:16.513114 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 05:53:16.523800 [RTC]rtc_get_frequency_meter,154: input=15, output=771
524 05:53:16.534359 [RTC]rtc_get_frequency_meter,154: input=23, output=957
525 05:53:16.543181 [RTC]rtc_get_frequency_meter,154: input=19, output=864
526 05:53:16.552433 [RTC]rtc_get_frequency_meter,154: input=17, output=819
527 05:53:16.562181 [RTC]rtc_get_frequency_meter,154: input=16, output=795
528 05:53:16.565466 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
529 05:53:16.572557 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
530 05:53:16.575456 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
531 05:53:16.578653 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
532 05:53:16.581980 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
533 05:53:16.585359 ADC[4]: Raw value=902876 ID=7
534 05:53:16.588621 ADC[3]: Raw value=213179 ID=1
535 05:53:16.592059 RAM Code: 0x71
536 05:53:16.595322 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
537 05:53:16.598699 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
538 05:53:16.608711 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
539 05:53:16.615682 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
540 05:53:16.618906 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
541 05:53:16.622357 in-header: 03 07 00 00 08 00 00 00
542 05:53:16.625525 in-data: aa e4 47 04 13 02 00 00
543 05:53:16.628943 Chrome EC: UHEPI supported
544 05:53:16.635836 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
545 05:53:16.639573 in-header: 03 ed 00 00 08 00 00 00
546 05:53:16.642764 in-data: 80 20 60 08 00 00 00 00
547 05:53:16.645886 MRC: failed to locate region type 0.
548 05:53:16.652450 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
549 05:53:16.655492 DRAM-K: Running full calibration
550 05:53:16.662382 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
551 05:53:16.662557 header.status = 0x0
552 05:53:16.665575 header.version = 0x6 (expected: 0x6)
553 05:53:16.669171 header.size = 0xd00 (expected: 0xd00)
554 05:53:16.672558 header.flags = 0x0
555 05:53:16.675708 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
556 05:53:16.694956 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
557 05:53:16.701761 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
558 05:53:16.705011 dram_init: ddr_geometry: 2
559 05:53:16.708189 [EMI] MDL number = 2
560 05:53:16.708314 [EMI] Get MDL freq = 0
561 05:53:16.711554 dram_init: ddr_type: 0
562 05:53:16.711663 is_discrete_lpddr4: 1
563 05:53:16.714867 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
564 05:53:16.714984
565 05:53:16.715057
566 05:53:16.718210 [Bian_co] ETT version 0.0.0.1
567 05:53:16.722178 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
568 05:53:16.722304
569 05:53:16.729498 dramc_set_vcore_voltage set vcore to 650000
570 05:53:16.729639 Read voltage for 800, 4
571 05:53:16.729716 Vio18 = 0
572 05:53:16.733253 Vcore = 650000
573 05:53:16.733367 Vdram = 0
574 05:53:16.733439 Vddq = 0
575 05:53:16.736920 Vmddr = 0
576 05:53:16.737038 dram_init: config_dvfs: 1
577 05:53:16.740618 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
578 05:53:16.748344 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
579 05:53:16.751810 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=10
580 05:53:16.755557 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=10
581 05:53:16.759142 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
582 05:53:16.763118 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
583 05:53:16.766406 MEM_TYPE=3, freq_sel=18
584 05:53:16.766561 sv_algorithm_assistance_LP4_1600
585 05:53:16.773899 ============ PULL DRAM RESETB DOWN ============
586 05:53:16.777506 ========== PULL DRAM RESETB DOWN end =========
587 05:53:16.781613 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
588 05:53:16.784545 ===================================
589 05:53:16.788139 LPDDR4 DRAM CONFIGURATION
590 05:53:16.791131 ===================================
591 05:53:16.791252 EX_ROW_EN[0] = 0x0
592 05:53:16.794674 EX_ROW_EN[1] = 0x0
593 05:53:16.794814 LP4Y_EN = 0x0
594 05:53:16.797861 WORK_FSP = 0x0
595 05:53:16.798022 WL = 0x2
596 05:53:16.801360 RL = 0x2
597 05:53:16.801552 BL = 0x2
598 05:53:16.804469 RPST = 0x0
599 05:53:16.804615 RD_PRE = 0x0
600 05:53:16.808073 WR_PRE = 0x1
601 05:53:16.808202 WR_PST = 0x0
602 05:53:16.811534 DBI_WR = 0x0
603 05:53:16.811653 DBI_RD = 0x0
604 05:53:16.814672 OTF = 0x1
605 05:53:16.817911 ===================================
606 05:53:16.821536 ===================================
607 05:53:16.821701 ANA top config
608 05:53:16.824642 ===================================
609 05:53:16.828107 DLL_ASYNC_EN = 0
610 05:53:16.831073 ALL_SLAVE_EN = 1
611 05:53:16.835098 NEW_RANK_MODE = 1
612 05:53:16.835232 DLL_IDLE_MODE = 1
613 05:53:16.838803 LP45_APHY_COMB_EN = 1
614 05:53:16.842389 TX_ODT_DIS = 1
615 05:53:16.845829 NEW_8X_MODE = 1
616 05:53:16.845983 ===================================
617 05:53:16.849178 ===================================
618 05:53:16.852957 data_rate = 1600
619 05:53:16.856294 CKR = 1
620 05:53:16.860258 DQ_P2S_RATIO = 8
621 05:53:16.863484 ===================================
622 05:53:16.863607 CA_P2S_RATIO = 8
623 05:53:16.866733 DQ_CA_OPEN = 0
624 05:53:16.870262 DQ_SEMI_OPEN = 0
625 05:53:16.873470 CA_SEMI_OPEN = 0
626 05:53:16.877109 CA_FULL_RATE = 0
627 05:53:16.880456 DQ_CKDIV4_EN = 1
628 05:53:16.880580 CA_CKDIV4_EN = 1
629 05:53:16.883773 CA_PREDIV_EN = 0
630 05:53:16.887419 PH8_DLY = 0
631 05:53:16.890628 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
632 05:53:16.893758 DQ_AAMCK_DIV = 4
633 05:53:16.893883 CA_AAMCK_DIV = 4
634 05:53:16.897266 CA_ADMCK_DIV = 4
635 05:53:16.900377 DQ_TRACK_CA_EN = 0
636 05:53:16.904086 CA_PICK = 800
637 05:53:16.907247 CA_MCKIO = 800
638 05:53:16.910313 MCKIO_SEMI = 0
639 05:53:16.913958 PLL_FREQ = 3068
640 05:53:16.914095 DQ_UI_PI_RATIO = 32
641 05:53:16.917134 CA_UI_PI_RATIO = 0
642 05:53:16.920541 ===================================
643 05:53:16.923947 ===================================
644 05:53:16.927153 memory_type:LPDDR4
645 05:53:16.930383 GP_NUM : 10
646 05:53:16.930502 SRAM_EN : 1
647 05:53:16.933840 MD32_EN : 0
648 05:53:16.937705 ===================================
649 05:53:16.937835 [ANA_INIT] >>>>>>>>>>>>>>
650 05:53:16.941050 <<<<<< [CONFIGURE PHASE]: ANA_TX
651 05:53:16.944343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
652 05:53:16.948500 ===================================
653 05:53:16.952088 data_rate = 1600,PCW = 0X7600
654 05:53:16.955809 ===================================
655 05:53:16.959421 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
656 05:53:16.962798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
657 05:53:16.970223 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
658 05:53:16.974295 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
659 05:53:16.977280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
660 05:53:16.980488 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
661 05:53:16.983988 [ANA_INIT] flow start
662 05:53:16.984111 [ANA_INIT] PLL >>>>>>>>
663 05:53:16.987125 [ANA_INIT] PLL <<<<<<<<
664 05:53:16.990770 [ANA_INIT] MIDPI >>>>>>>>
665 05:53:16.990925 [ANA_INIT] MIDPI <<<<<<<<
666 05:53:16.994250 [ANA_INIT] DLL >>>>>>>>
667 05:53:16.997341 [ANA_INIT] flow end
668 05:53:17.000812 ============ LP4 DIFF to SE enter ============
669 05:53:17.004325 ============ LP4 DIFF to SE exit ============
670 05:53:17.007588 [ANA_INIT] <<<<<<<<<<<<<
671 05:53:17.010799 [Flow] Enable top DCM control >>>>>
672 05:53:17.014086 [Flow] Enable top DCM control <<<<<
673 05:53:17.017305 Enable DLL master slave shuffle
674 05:53:17.020769 ==============================================================
675 05:53:17.024246 Gating Mode config
676 05:53:17.027340 ==============================================================
677 05:53:17.030808 Config description:
678 05:53:17.040838 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
679 05:53:17.047453 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
680 05:53:17.051489 SELPH_MODE 0: By rank 1: By Phase
681 05:53:17.057562 ==============================================================
682 05:53:17.060843 GAT_TRACK_EN = 1
683 05:53:17.064343 RX_GATING_MODE = 2
684 05:53:17.068073 RX_GATING_TRACK_MODE = 2
685 05:53:17.070979 SELPH_MODE = 1
686 05:53:17.071097 PICG_EARLY_EN = 1
687 05:53:17.074301 VALID_LAT_VALUE = 1
688 05:53:17.080656 ==============================================================
689 05:53:17.084453 Enter into Gating configuration >>>>
690 05:53:17.087491 Exit from Gating configuration <<<<
691 05:53:17.091012 Enter into DVFS_PRE_config >>>>>
692 05:53:17.100663 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
693 05:53:17.104282 Exit from DVFS_PRE_config <<<<<
694 05:53:17.107429 Enter into PICG configuration >>>>
695 05:53:17.111520 Exit from PICG configuration <<<<
696 05:53:17.115315 [RX_INPUT] configuration >>>>>
697 05:53:17.118887 [RX_INPUT] configuration <<<<<
698 05:53:17.122624 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
699 05:53:17.126071 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
700 05:53:17.133634 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
701 05:53:17.141003 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
702 05:53:17.144550 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
703 05:53:17.151901 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
704 05:53:17.155578 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
705 05:53:17.158885 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
706 05:53:17.162818 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
707 05:53:17.170086 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
708 05:53:17.173913 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
709 05:53:17.177539 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
710 05:53:17.181200 ===================================
711 05:53:17.181330 LPDDR4 DRAM CONFIGURATION
712 05:53:17.185096 ===================================
713 05:53:17.188650 EX_ROW_EN[0] = 0x0
714 05:53:17.188779 EX_ROW_EN[1] = 0x0
715 05:53:17.192765 LP4Y_EN = 0x0
716 05:53:17.192885 WORK_FSP = 0x0
717 05:53:17.196148 WL = 0x2
718 05:53:17.196263 RL = 0x2
719 05:53:17.199993 BL = 0x2
720 05:53:17.200117 RPST = 0x0
721 05:53:17.203647 RD_PRE = 0x0
722 05:53:17.203764 WR_PRE = 0x1
723 05:53:17.207666 WR_PST = 0x0
724 05:53:17.207790 DBI_WR = 0x0
725 05:53:17.207886 DBI_RD = 0x0
726 05:53:17.211503 OTF = 0x1
727 05:53:17.215279 ===================================
728 05:53:17.219056 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
729 05:53:17.222960 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
730 05:53:17.226554 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
731 05:53:17.229887 ===================================
732 05:53:17.233587 LPDDR4 DRAM CONFIGURATION
733 05:53:17.237569 ===================================
734 05:53:17.237754 EX_ROW_EN[0] = 0x10
735 05:53:17.241070 EX_ROW_EN[1] = 0x0
736 05:53:17.241186 LP4Y_EN = 0x0
737 05:53:17.244921 WORK_FSP = 0x0
738 05:53:17.245037 WL = 0x2
739 05:53:17.245109 RL = 0x2
740 05:53:17.248815 BL = 0x2
741 05:53:17.248926 RPST = 0x0
742 05:53:17.252189 RD_PRE = 0x0
743 05:53:17.252318 WR_PRE = 0x1
744 05:53:17.255958 WR_PST = 0x0
745 05:53:17.256074 DBI_WR = 0x0
746 05:53:17.259585 DBI_RD = 0x0
747 05:53:17.259703 OTF = 0x1
748 05:53:17.263190 ===================================
749 05:53:17.270574 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
750 05:53:17.274434 nWR fixed to 40
751 05:53:17.274575 [ModeRegInit_LP4] CH0 RK0
752 05:53:17.278482 [ModeRegInit_LP4] CH0 RK1
753 05:53:17.281980 [ModeRegInit_LP4] CH1 RK0
754 05:53:17.282119 [ModeRegInit_LP4] CH1 RK1
755 05:53:17.286036 match AC timing 13
756 05:53:17.289670 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
757 05:53:17.293065 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
758 05:53:17.296467 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
759 05:53:17.303579 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
760 05:53:17.307773 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
761 05:53:17.307916 [EMI DOE] emi_dcm 0
762 05:53:17.311560 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
763 05:53:17.311680 ==
764 05:53:17.315485 Dram Type= 6, Freq= 0, CH_0, rank 0
765 05:53:17.318653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
766 05:53:17.322599 ==
767 05:53:17.326309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
768 05:53:17.333132 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
769 05:53:17.341447 [CA 0] Center 38 (7~69) winsize 63
770 05:53:17.344640 [CA 1] Center 38 (7~69) winsize 63
771 05:53:17.348422 [CA 2] Center 35 (5~66) winsize 62
772 05:53:17.352164 [CA 3] Center 35 (5~66) winsize 62
773 05:53:17.355789 [CA 4] Center 34 (4~65) winsize 62
774 05:53:17.359354 [CA 5] Center 33 (3~64) winsize 62
775 05:53:17.359484
776 05:53:17.363389 [CmdBusTrainingLP45] Vref(ca) range 1: 32
777 05:53:17.363512
778 05:53:17.366724 [CATrainingPosCal] consider 1 rank data
779 05:53:17.366834 u2DelayCellTimex100 = 270/100 ps
780 05:53:17.374247 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
781 05:53:17.374395 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
782 05:53:17.378472 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
783 05:53:17.381833 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
784 05:53:17.385480 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
785 05:53:17.389301 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
786 05:53:17.389436
787 05:53:17.392903 CA PerBit enable=1, Macro0, CA PI delay=33
788 05:53:17.396863
789 05:53:17.396995 [CBTSetCACLKResult] CA Dly = 33
790 05:53:17.400023 CS Dly: 6 (0~37)
791 05:53:17.400128 ==
792 05:53:17.403829 Dram Type= 6, Freq= 0, CH_0, rank 1
793 05:53:17.408075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
794 05:53:17.408212 ==
795 05:53:17.412104 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
796 05:53:17.418610 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
797 05:53:17.427368 [CA 0] Center 38 (7~69) winsize 63
798 05:53:17.431065 [CA 1] Center 38 (7~69) winsize 63
799 05:53:17.434221 [CA 2] Center 36 (6~67) winsize 62
800 05:53:17.437409 [CA 3] Center 36 (5~67) winsize 63
801 05:53:17.440723 [CA 4] Center 35 (4~66) winsize 63
802 05:53:17.444099 [CA 5] Center 34 (4~65) winsize 62
803 05:53:17.444223
804 05:53:17.448070 [CmdBusTrainingLP45] Vref(ca) range 1: 32
805 05:53:17.448216
806 05:53:17.451588 [CATrainingPosCal] consider 2 rank data
807 05:53:17.454670 u2DelayCellTimex100 = 270/100 ps
808 05:53:17.457952 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
809 05:53:17.460745 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
810 05:53:17.467740 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
811 05:53:17.470768 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
812 05:53:17.474216 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
813 05:53:17.477711 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
814 05:53:17.477857
815 05:53:17.480654 CA PerBit enable=1, Macro0, CA PI delay=34
816 05:53:17.480749
817 05:53:17.484175 [CBTSetCACLKResult] CA Dly = 34
818 05:53:17.484285 CS Dly: 6 (0~38)
819 05:53:17.484356
820 05:53:17.487481 ----->DramcWriteLeveling(PI) begin...
821 05:53:17.491116 ==
822 05:53:17.491253 Dram Type= 6, Freq= 0, CH_0, rank 0
823 05:53:17.497412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
824 05:53:17.497555 ==
825 05:53:17.501115 Write leveling (Byte 0): 30 => 30
826 05:53:17.504383 Write leveling (Byte 1): 29 => 29
827 05:53:17.507349 DramcWriteLeveling(PI) end<-----
828 05:53:17.507465
829 05:53:17.507539 ==
830 05:53:17.510904 Dram Type= 6, Freq= 0, CH_0, rank 0
831 05:53:17.514212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
832 05:53:17.514361 ==
833 05:53:17.517768 [Gating] SW mode calibration
834 05:53:17.525233 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
835 05:53:17.528960 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
836 05:53:17.533091 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
837 05:53:17.536506 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
838 05:53:17.543129 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
839 05:53:17.546566 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 05:53:17.550094 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 05:53:17.556776 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 05:53:17.560404 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 05:53:17.563700 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 05:53:17.570064 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 05:53:17.573327 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 05:53:17.576760 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 05:53:17.580236 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 05:53:17.586747 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 05:53:17.590084 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 05:53:17.593644 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 05:53:17.600380 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 05:53:17.603918 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
853 05:53:17.606880 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
854 05:53:17.613556 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
855 05:53:17.616869 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 05:53:17.620471 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 05:53:17.626952 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 05:53:17.630159 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 05:53:17.633515 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 05:53:17.640161 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 05:53:17.643412 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
862 05:53:17.647052 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
863 05:53:17.654445 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (1 1) (1 1)
864 05:53:17.656990 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
865 05:53:17.660239 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
866 05:53:17.663703 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
867 05:53:17.670310 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 05:53:17.673660 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 05:53:17.676864 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
870 05:53:17.683652 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
871 05:53:17.687090 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
872 05:53:17.690672 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 05:53:17.696954 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 05:53:17.700224 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 05:53:17.703546 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 05:53:17.710253 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 05:53:17.713977 0 11 4 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
878 05:53:17.717192 0 11 8 | B1->B0 | 2c2c 4444 | 0 0 | (0 0) (1 1)
879 05:53:17.724189 0 11 12 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
880 05:53:17.727257 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
881 05:53:17.730393 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
882 05:53:17.734307 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
883 05:53:17.740640 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 05:53:17.743979 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
885 05:53:17.747465 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
886 05:53:17.754247 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
887 05:53:17.757679 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
888 05:53:17.761326 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 05:53:17.767272 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
890 05:53:17.770533 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 05:53:17.774163 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 05:53:17.780541 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 05:53:17.783994 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 05:53:17.787426 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 05:53:17.794263 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 05:53:17.797535 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 05:53:17.800490 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 05:53:17.807505 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 05:53:17.810838 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 05:53:17.813847 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 05:53:17.817247 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
902 05:53:17.824004 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
903 05:53:17.827859 Total UI for P1: 0, mck2ui 16
904 05:53:17.830575 best dqsien dly found for B0: ( 0, 14, 4)
905 05:53:17.834001 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
906 05:53:17.837168 Total UI for P1: 0, mck2ui 16
907 05:53:17.840660 best dqsien dly found for B1: ( 0, 14, 6)
908 05:53:17.844053 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
909 05:53:17.847266 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
910 05:53:17.847383
911 05:53:17.850692 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
912 05:53:17.854071 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
913 05:53:17.857211 [Gating] SW calibration Done
914 05:53:17.857329 ==
915 05:53:17.860841 Dram Type= 6, Freq= 0, CH_0, rank 0
916 05:53:17.864355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 05:53:17.867492 ==
918 05:53:17.867614 RX Vref Scan: 0
919 05:53:17.867689
920 05:53:17.870468 RX Vref 0 -> 0, step: 1
921 05:53:17.870568
922 05:53:17.873975 RX Delay -130 -> 252, step: 16
923 05:53:17.877455 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
924 05:53:17.880581 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
925 05:53:17.883764 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
926 05:53:17.887152 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
927 05:53:17.893788 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
928 05:53:17.897339 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
929 05:53:17.900779 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
930 05:53:17.903901 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
931 05:53:17.907428 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
932 05:53:17.913791 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
933 05:53:17.917125 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
934 05:53:17.921435 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
935 05:53:17.924124 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
936 05:53:17.927392 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
937 05:53:17.934322 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
938 05:53:17.937061 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
939 05:53:17.937192 ==
940 05:53:17.940653 Dram Type= 6, Freq= 0, CH_0, rank 0
941 05:53:17.944076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
942 05:53:17.944196 ==
943 05:53:17.947242 DQS Delay:
944 05:53:17.947351 DQS0 = 0, DQS1 = 0
945 05:53:17.947442 DQM Delay:
946 05:53:17.950508 DQM0 = 91, DQM1 = 81
947 05:53:17.950608 DQ Delay:
948 05:53:17.953854 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
949 05:53:17.957512 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
950 05:53:17.960485 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
951 05:53:17.963823 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
952 05:53:17.963945
953 05:53:17.964018
954 05:53:17.964079 ==
955 05:53:17.967163 Dram Type= 6, Freq= 0, CH_0, rank 0
956 05:53:17.973827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 05:53:17.974036 ==
958 05:53:17.974109
959 05:53:17.974172
960 05:53:17.974232 TX Vref Scan disable
961 05:53:17.977218 == TX Byte 0 ==
962 05:53:17.980895 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
963 05:53:17.984736 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
964 05:53:17.988022 == TX Byte 1 ==
965 05:53:17.990707 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
966 05:53:17.994277 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
967 05:53:17.997610 ==
968 05:53:18.001102 Dram Type= 6, Freq= 0, CH_0, rank 0
969 05:53:18.004068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 05:53:18.004180 ==
971 05:53:18.016537 TX Vref=22, minBit 8, minWin=26, winSum=437
972 05:53:18.019579 TX Vref=24, minBit 1, minWin=27, winSum=441
973 05:53:18.023349 TX Vref=26, minBit 8, minWin=27, winSum=448
974 05:53:18.026444 TX Vref=28, minBit 3, minWin=28, winSum=454
975 05:53:18.029677 TX Vref=30, minBit 5, minWin=28, winSum=458
976 05:53:18.033246 TX Vref=32, minBit 12, minWin=27, winSum=454
977 05:53:18.039883 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 30
978 05:53:18.040038
979 05:53:18.043021 Final TX Range 1 Vref 30
980 05:53:18.043129
981 05:53:18.043200 ==
982 05:53:18.046692 Dram Type= 6, Freq= 0, CH_0, rank 0
983 05:53:18.050362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 05:53:18.050484 ==
985 05:53:18.050555
986 05:53:18.053708
987 05:53:18.053806 TX Vref Scan disable
988 05:53:18.056727 == TX Byte 0 ==
989 05:53:18.060009 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
990 05:53:18.063029 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
991 05:53:18.066454 == TX Byte 1 ==
992 05:53:18.069705 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
993 05:53:18.073344 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
994 05:53:18.073459
995 05:53:18.076752 [DATLAT]
996 05:53:18.076862 Freq=800, CH0 RK0
997 05:53:18.076931
998 05:53:18.080048 DATLAT Default: 0xa
999 05:53:18.080153 0, 0xFFFF, sum = 0
1000 05:53:18.083061 1, 0xFFFF, sum = 0
1001 05:53:18.083161 2, 0xFFFF, sum = 0
1002 05:53:18.086304 3, 0xFFFF, sum = 0
1003 05:53:18.086412 4, 0xFFFF, sum = 0
1004 05:53:18.089880 5, 0xFFFF, sum = 0
1005 05:53:18.090032 6, 0xFFFF, sum = 0
1006 05:53:18.093476 7, 0xFFFF, sum = 0
1007 05:53:18.093584 8, 0xFFFF, sum = 0
1008 05:53:18.096496 9, 0x0, sum = 1
1009 05:53:18.096612 10, 0x0, sum = 2
1010 05:53:18.100016 11, 0x0, sum = 3
1011 05:53:18.100121 12, 0x0, sum = 4
1012 05:53:18.103299 best_step = 10
1013 05:53:18.103402
1014 05:53:18.103470 ==
1015 05:53:18.106434 Dram Type= 6, Freq= 0, CH_0, rank 0
1016 05:53:18.109718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1017 05:53:18.109831 ==
1018 05:53:18.113562 RX Vref Scan: 1
1019 05:53:18.113671
1020 05:53:18.113743 Set Vref Range= 32 -> 127
1021 05:53:18.113806
1022 05:53:18.116296 RX Vref 32 -> 127, step: 1
1023 05:53:18.116386
1024 05:53:18.120055 RX Delay -79 -> 252, step: 8
1025 05:53:18.120167
1026 05:53:18.123382 Set Vref, RX VrefLevel [Byte0]: 32
1027 05:53:18.126813 [Byte1]: 32
1028 05:53:18.126933
1029 05:53:18.130114 Set Vref, RX VrefLevel [Byte0]: 33
1030 05:53:18.133317 [Byte1]: 33
1031 05:53:18.136594
1032 05:53:18.136737 Set Vref, RX VrefLevel [Byte0]: 34
1033 05:53:18.139970 [Byte1]: 34
1034 05:53:18.144346
1035 05:53:18.144471 Set Vref, RX VrefLevel [Byte0]: 35
1036 05:53:18.147776 [Byte1]: 35
1037 05:53:18.151811
1038 05:53:18.151931 Set Vref, RX VrefLevel [Byte0]: 36
1039 05:53:18.154928 [Byte1]: 36
1040 05:53:18.159343
1041 05:53:18.159469 Set Vref, RX VrefLevel [Byte0]: 37
1042 05:53:18.162733 [Byte1]: 37
1043 05:53:18.166924
1044 05:53:18.167048 Set Vref, RX VrefLevel [Byte0]: 38
1045 05:53:18.170425 [Byte1]: 38
1046 05:53:18.175468
1047 05:53:18.175601 Set Vref, RX VrefLevel [Byte0]: 39
1048 05:53:18.177976 [Byte1]: 39
1049 05:53:18.182371
1050 05:53:18.182502 Set Vref, RX VrefLevel [Byte0]: 40
1051 05:53:18.185328 [Byte1]: 40
1052 05:53:18.190145
1053 05:53:18.190296 Set Vref, RX VrefLevel [Byte0]: 41
1054 05:53:18.193303 [Byte1]: 41
1055 05:53:18.197506
1056 05:53:18.197642 Set Vref, RX VrefLevel [Byte0]: 42
1057 05:53:18.200687 [Byte1]: 42
1058 05:53:18.205140
1059 05:53:18.205271 Set Vref, RX VrefLevel [Byte0]: 43
1060 05:53:18.208075 [Byte1]: 43
1061 05:53:18.212425
1062 05:53:18.212558 Set Vref, RX VrefLevel [Byte0]: 44
1063 05:53:18.215842 [Byte1]: 44
1064 05:53:18.219603
1065 05:53:18.219734 Set Vref, RX VrefLevel [Byte0]: 45
1066 05:53:18.223200 [Byte1]: 45
1067 05:53:18.227547
1068 05:53:18.227687 Set Vref, RX VrefLevel [Byte0]: 46
1069 05:53:18.230715 [Byte1]: 46
1070 05:53:18.234897
1071 05:53:18.235021 Set Vref, RX VrefLevel [Byte0]: 47
1072 05:53:18.237954 [Byte1]: 47
1073 05:53:18.242444
1074 05:53:18.242579 Set Vref, RX VrefLevel [Byte0]: 48
1075 05:53:18.245666 [Byte1]: 48
1076 05:53:18.250198
1077 05:53:18.250336 Set Vref, RX VrefLevel [Byte0]: 49
1078 05:53:18.253218 [Byte1]: 49
1079 05:53:18.257608
1080 05:53:18.257737 Set Vref, RX VrefLevel [Byte0]: 50
1081 05:53:18.260956 [Byte1]: 50
1082 05:53:18.264765
1083 05:53:18.264886 Set Vref, RX VrefLevel [Byte0]: 51
1084 05:53:18.268380 [Byte1]: 51
1085 05:53:18.272384
1086 05:53:18.272509 Set Vref, RX VrefLevel [Byte0]: 52
1087 05:53:18.276189 [Byte1]: 52
1088 05:53:18.280084
1089 05:53:18.280209 Set Vref, RX VrefLevel [Byte0]: 53
1090 05:53:18.283392 [Byte1]: 53
1091 05:53:18.287762
1092 05:53:18.287890 Set Vref, RX VrefLevel [Byte0]: 54
1093 05:53:18.291261 [Byte1]: 54
1094 05:53:18.295098
1095 05:53:18.295219 Set Vref, RX VrefLevel [Byte0]: 55
1096 05:53:18.298512 [Byte1]: 55
1097 05:53:18.302723
1098 05:53:18.302849 Set Vref, RX VrefLevel [Byte0]: 56
1099 05:53:18.305923 [Byte1]: 56
1100 05:53:18.310786
1101 05:53:18.310916 Set Vref, RX VrefLevel [Byte0]: 57
1102 05:53:18.313489 [Byte1]: 57
1103 05:53:18.317732
1104 05:53:18.317854 Set Vref, RX VrefLevel [Byte0]: 58
1105 05:53:18.321074 [Byte1]: 58
1106 05:53:18.325530
1107 05:53:18.325655 Set Vref, RX VrefLevel [Byte0]: 59
1108 05:53:18.328808 [Byte1]: 59
1109 05:53:18.333216
1110 05:53:18.333348 Set Vref, RX VrefLevel [Byte0]: 60
1111 05:53:18.336353 [Byte1]: 60
1112 05:53:18.340415
1113 05:53:18.340547 Set Vref, RX VrefLevel [Byte0]: 61
1114 05:53:18.343736 [Byte1]: 61
1115 05:53:18.347902
1116 05:53:18.348033 Set Vref, RX VrefLevel [Byte0]: 62
1117 05:53:18.351558 [Byte1]: 62
1118 05:53:18.355514
1119 05:53:18.355641 Set Vref, RX VrefLevel [Byte0]: 63
1120 05:53:18.358654 [Byte1]: 63
1121 05:53:18.363825
1122 05:53:18.363961 Set Vref, RX VrefLevel [Byte0]: 64
1123 05:53:18.366228 [Byte1]: 64
1124 05:53:18.370783
1125 05:53:18.370911 Set Vref, RX VrefLevel [Byte0]: 65
1126 05:53:18.373786 [Byte1]: 65
1127 05:53:18.378280
1128 05:53:18.378411 Set Vref, RX VrefLevel [Byte0]: 66
1129 05:53:18.381886 [Byte1]: 66
1130 05:53:18.385647
1131 05:53:18.385768 Set Vref, RX VrefLevel [Byte0]: 67
1132 05:53:18.389350 [Byte1]: 67
1133 05:53:18.393379
1134 05:53:18.393505 Set Vref, RX VrefLevel [Byte0]: 68
1135 05:53:18.396453 [Byte1]: 68
1136 05:53:18.400810
1137 05:53:18.400942 Set Vref, RX VrefLevel [Byte0]: 69
1138 05:53:18.404076 [Byte1]: 69
1139 05:53:18.408476
1140 05:53:18.408609 Set Vref, RX VrefLevel [Byte0]: 70
1141 05:53:18.411426 [Byte1]: 70
1142 05:53:18.416184
1143 05:53:18.416315 Set Vref, RX VrefLevel [Byte0]: 71
1144 05:53:18.419106 [Byte1]: 71
1145 05:53:18.423731
1146 05:53:18.423861 Set Vref, RX VrefLevel [Byte0]: 72
1147 05:53:18.426862 [Byte1]: 72
1148 05:53:18.431534
1149 05:53:18.431666 Set Vref, RX VrefLevel [Byte0]: 73
1150 05:53:18.434109 [Byte1]: 73
1151 05:53:18.438435
1152 05:53:18.438569 Set Vref, RX VrefLevel [Byte0]: 74
1153 05:53:18.442013 [Byte1]: 74
1154 05:53:18.446102
1155 05:53:18.446230 Final RX Vref Byte 0 = 60 to rank0
1156 05:53:18.449676 Final RX Vref Byte 1 = 57 to rank0
1157 05:53:18.453149 Final RX Vref Byte 0 = 60 to rank1
1158 05:53:18.456328 Final RX Vref Byte 1 = 57 to rank1==
1159 05:53:18.459772 Dram Type= 6, Freq= 0, CH_0, rank 0
1160 05:53:18.462947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1161 05:53:18.466008 ==
1162 05:53:18.466121 DQS Delay:
1163 05:53:18.466192 DQS0 = 0, DQS1 = 0
1164 05:53:18.469465 DQM Delay:
1165 05:53:18.469565 DQM0 = 93, DQM1 = 82
1166 05:53:18.473333 DQ Delay:
1167 05:53:18.476304 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1168 05:53:18.476418 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1169 05:53:18.479595 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1170 05:53:18.486309 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1171 05:53:18.486455
1172 05:53:18.486530
1173 05:53:18.492961 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1174 05:53:18.496432 CH0 RK0: MR19=606, MR18=3D38
1175 05:53:18.502931 CH0_RK0: MR19=0x606, MR18=0x3D38, DQSOSC=394, MR23=63, INC=95, DEC=63
1176 05:53:18.503081
1177 05:53:18.506401 ----->DramcWriteLeveling(PI) begin...
1178 05:53:18.506512 ==
1179 05:53:18.509599 Dram Type= 6, Freq= 0, CH_0, rank 1
1180 05:53:18.512901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 05:53:18.513045 ==
1182 05:53:18.516191 Write leveling (Byte 0): 34 => 34
1183 05:53:18.519905 Write leveling (Byte 1): 29 => 29
1184 05:53:18.523234 DramcWriteLeveling(PI) end<-----
1185 05:53:18.523349
1186 05:53:18.523437 ==
1187 05:53:18.526213 Dram Type= 6, Freq= 0, CH_0, rank 1
1188 05:53:18.530098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 05:53:18.530215 ==
1190 05:53:18.533132 [Gating] SW mode calibration
1191 05:53:18.540185 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1192 05:53:18.546423 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1193 05:53:18.549707 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1194 05:53:18.552938 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1195 05:53:18.559657 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 05:53:18.563336 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 05:53:18.566515 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 05:53:18.570036 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 05:53:18.576767 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 05:53:18.579927 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 05:53:18.583251 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 05:53:18.590164 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 05:53:18.633861 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 05:53:18.634291 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 05:53:18.634402 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 05:53:18.634482 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 05:53:18.634569 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 05:53:18.634631 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 05:53:18.635296 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 05:53:18.635380 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1211 05:53:18.635824 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1212 05:53:18.636434 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 05:53:18.678506 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 05:53:18.678929 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 05:53:18.679029 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 05:53:18.679313 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 05:53:18.679937 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 05:53:18.680213 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1219 05:53:18.680297 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1220 05:53:18.680364 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 05:53:18.680794 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 05:53:18.681136 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 05:53:18.702708 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 05:53:18.703496 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1225 05:53:18.703594 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1226 05:53:18.703662 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 1)
1227 05:53:18.703910 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
1228 05:53:18.707204 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 05:53:18.710473 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 05:53:18.713647 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 05:53:18.717075 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 05:53:18.720473 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 05:53:18.723904 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 05:53:18.730919 0 11 4 | B1->B0 | 2323 2f2f | 1 1 | (0 0) (0 0)
1235 05:53:18.733679 0 11 8 | B1->B0 | 3c3c 4343 | 0 0 | (0 0) (0 0)
1236 05:53:18.737376 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 05:53:18.744085 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 05:53:18.747073 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 05:53:18.750655 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 05:53:18.757068 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 05:53:18.760363 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 05:53:18.764099 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1243 05:53:18.771064 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1244 05:53:18.774329 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 05:53:18.778122 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 05:53:18.782376 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 05:53:18.785554 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 05:53:18.792458 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 05:53:18.795781 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 05:53:18.799470 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 05:53:18.806047 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 05:53:18.809174 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 05:53:18.812522 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 05:53:18.816120 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 05:53:18.822973 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 05:53:18.826004 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 05:53:18.829361 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 05:53:18.836115 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 05:53:18.839310 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1260 05:53:18.842889 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 05:53:18.846148 Total UI for P1: 0, mck2ui 16
1262 05:53:18.849734 best dqsien dly found for B0: ( 0, 14, 8)
1263 05:53:18.852637 Total UI for P1: 0, mck2ui 16
1264 05:53:18.856090 best dqsien dly found for B1: ( 0, 14, 8)
1265 05:53:18.859482 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1266 05:53:18.862633 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1267 05:53:18.862746
1268 05:53:18.869820 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1269 05:53:18.873091 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1270 05:53:18.873214 [Gating] SW calibration Done
1271 05:53:18.873286 ==
1272 05:53:18.876022 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 05:53:18.883079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 05:53:18.883226 ==
1275 05:53:18.883302 RX Vref Scan: 0
1276 05:53:18.883366
1277 05:53:18.886204 RX Vref 0 -> 0, step: 1
1278 05:53:18.886299
1279 05:53:18.889643 RX Delay -130 -> 252, step: 16
1280 05:53:18.893103 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1281 05:53:18.896349 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1282 05:53:18.899850 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1283 05:53:18.906211 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1284 05:53:18.909752 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1285 05:53:18.913008 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1286 05:53:18.916392 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1287 05:53:18.919932 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1288 05:53:18.926656 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1289 05:53:18.929932 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1290 05:53:18.933037 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1291 05:53:18.936430 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1292 05:53:18.939787 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1293 05:53:18.946393 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1294 05:53:18.949847 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1295 05:53:18.953290 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1296 05:53:18.953407 ==
1297 05:53:18.956496 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 05:53:18.959904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 05:53:18.960025 ==
1300 05:53:18.963157 DQS Delay:
1301 05:53:18.963259 DQS0 = 0, DQS1 = 0
1302 05:53:18.966507 DQM Delay:
1303 05:53:18.966608 DQM0 = 92, DQM1 = 81
1304 05:53:18.966677 DQ Delay:
1305 05:53:18.969875 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1306 05:53:18.973489 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1307 05:53:18.976657 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1308 05:53:18.979907 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1309 05:53:18.980086
1310 05:53:18.980185
1311 05:53:18.980251 ==
1312 05:53:18.983124 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 05:53:18.989744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 05:53:18.989887 ==
1315 05:53:18.989968
1316 05:53:18.990062
1317 05:53:18.990185 TX Vref Scan disable
1318 05:53:18.993717 == TX Byte 0 ==
1319 05:53:18.996922 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1320 05:53:19.003845 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1321 05:53:19.003994 == TX Byte 1 ==
1322 05:53:19.006863 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1323 05:53:19.013457 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1324 05:53:19.013601 ==
1325 05:53:19.017015 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 05:53:19.019987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 05:53:19.020095 ==
1328 05:53:19.033479 TX Vref=22, minBit 3, minWin=27, winSum=446
1329 05:53:19.036731 TX Vref=24, minBit 1, minWin=27, winSum=447
1330 05:53:19.040017 TX Vref=26, minBit 1, minWin=27, winSum=450
1331 05:53:19.043476 TX Vref=28, minBit 8, minWin=27, winSum=452
1332 05:53:19.046651 TX Vref=30, minBit 8, minWin=28, winSum=457
1333 05:53:19.050218 TX Vref=32, minBit 8, minWin=27, winSum=457
1334 05:53:19.056944 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 30
1335 05:53:19.057096
1336 05:53:19.060112 Final TX Range 1 Vref 30
1337 05:53:19.060217
1338 05:53:19.060284 ==
1339 05:53:19.063817 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 05:53:19.067033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 05:53:19.067141 ==
1342 05:53:19.067214
1343 05:53:19.070371
1344 05:53:19.070468 TX Vref Scan disable
1345 05:53:19.073965 == TX Byte 0 ==
1346 05:53:19.076668 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1347 05:53:19.080339 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1348 05:53:19.083396 == TX Byte 1 ==
1349 05:53:19.086731 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1350 05:53:19.090337 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1351 05:53:19.093805
1352 05:53:19.093921 [DATLAT]
1353 05:53:19.094028 Freq=800, CH0 RK1
1354 05:53:19.094091
1355 05:53:19.097002 DATLAT Default: 0xa
1356 05:53:19.097095 0, 0xFFFF, sum = 0
1357 05:53:19.100765 1, 0xFFFF, sum = 0
1358 05:53:19.100871 2, 0xFFFF, sum = 0
1359 05:53:19.103572 3, 0xFFFF, sum = 0
1360 05:53:19.103671 4, 0xFFFF, sum = 0
1361 05:53:19.106773 5, 0xFFFF, sum = 0
1362 05:53:19.106872 6, 0xFFFF, sum = 0
1363 05:53:19.110429 7, 0xFFFF, sum = 0
1364 05:53:19.110529 8, 0xFFFF, sum = 0
1365 05:53:19.113703 9, 0x0, sum = 1
1366 05:53:19.113801 10, 0x0, sum = 2
1367 05:53:19.116969 11, 0x0, sum = 3
1368 05:53:19.117067 12, 0x0, sum = 4
1369 05:53:19.120165 best_step = 10
1370 05:53:19.120262
1371 05:53:19.120330 ==
1372 05:53:19.123466 Dram Type= 6, Freq= 0, CH_0, rank 1
1373 05:53:19.126977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 05:53:19.127086 ==
1375 05:53:19.130112 RX Vref Scan: 0
1376 05:53:19.130206
1377 05:53:19.130273 RX Vref 0 -> 0, step: 1
1378 05:53:19.130335
1379 05:53:19.133619 RX Delay -95 -> 252, step: 8
1380 05:53:19.140148 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1381 05:53:19.143441 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1382 05:53:19.146779 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1383 05:53:19.150130 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1384 05:53:19.153592 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1385 05:53:19.160430 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1386 05:53:19.163790 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1387 05:53:19.166585 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1388 05:53:19.170280 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1389 05:53:19.173426 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1390 05:53:19.180186 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1391 05:53:19.183353 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1392 05:53:19.186603 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1393 05:53:19.190077 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1394 05:53:19.193847 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1395 05:53:19.200072 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1396 05:53:19.200220 ==
1397 05:53:19.203334 Dram Type= 6, Freq= 0, CH_0, rank 1
1398 05:53:19.206957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 05:53:19.207077 ==
1400 05:53:19.207146 DQS Delay:
1401 05:53:19.210002 DQS0 = 0, DQS1 = 0
1402 05:53:19.210097 DQM Delay:
1403 05:53:19.213623 DQM0 = 91, DQM1 = 81
1404 05:53:19.213722 DQ Delay:
1405 05:53:19.216964 DQ0 =88, DQ1 =92, DQ2 =92, DQ3 =88
1406 05:53:19.220136 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1407 05:53:19.223754 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1408 05:53:19.226647 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1409 05:53:19.226757
1410 05:53:19.226824
1411 05:53:19.236597 [DQSOSCAuto] RK1, (LSB)MR18= 0x411c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1412 05:53:19.236744 CH0 RK1: MR19=606, MR18=411C
1413 05:53:19.243319 CH0_RK1: MR19=0x606, MR18=0x411C, DQSOSC=393, MR23=63, INC=95, DEC=63
1414 05:53:19.246990 [RxdqsGatingPostProcess] freq 800
1415 05:53:19.253492 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1416 05:53:19.256621 Pre-setting of DQS Precalculation
1417 05:53:19.260385 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1418 05:53:19.260495 ==
1419 05:53:19.263435 Dram Type= 6, Freq= 0, CH_1, rank 0
1420 05:53:19.267032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 05:53:19.267133 ==
1422 05:53:19.273570 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1423 05:53:19.280387 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1424 05:53:19.288515 [CA 0] Center 36 (6~67) winsize 62
1425 05:53:19.292250 [CA 1] Center 36 (6~67) winsize 62
1426 05:53:19.295353 [CA 2] Center 35 (5~65) winsize 61
1427 05:53:19.298635 [CA 3] Center 34 (3~65) winsize 63
1428 05:53:19.301968 [CA 4] Center 34 (4~65) winsize 62
1429 05:53:19.305465 [CA 5] Center 33 (3~64) winsize 62
1430 05:53:19.305559
1431 05:53:19.308713 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1432 05:53:19.308799
1433 05:53:19.312480 [CATrainingPosCal] consider 1 rank data
1434 05:53:19.315289 u2DelayCellTimex100 = 270/100 ps
1435 05:53:19.318645 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1436 05:53:19.322281 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1437 05:53:19.328923 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1438 05:53:19.331907 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1439 05:53:19.335294 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1440 05:53:19.338415 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1441 05:53:19.338508
1442 05:53:19.342070 CA PerBit enable=1, Macro0, CA PI delay=33
1443 05:53:19.342169
1444 05:53:19.345622 [CBTSetCACLKResult] CA Dly = 33
1445 05:53:19.345710 CS Dly: 6 (0~37)
1446 05:53:19.348524 ==
1447 05:53:19.348611 Dram Type= 6, Freq= 0, CH_1, rank 1
1448 05:53:19.355468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 05:53:19.355625 ==
1450 05:53:19.358567 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 05:53:19.365021 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 05:53:19.374789 [CA 0] Center 36 (6~67) winsize 62
1453 05:53:19.378045 [CA 1] Center 37 (6~68) winsize 63
1454 05:53:19.381628 [CA 2] Center 35 (5~66) winsize 62
1455 05:53:19.384983 [CA 3] Center 34 (4~65) winsize 62
1456 05:53:19.388238 [CA 4] Center 34 (4~65) winsize 62
1457 05:53:19.391664 [CA 5] Center 34 (4~64) winsize 61
1458 05:53:19.391767
1459 05:53:19.395098 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1460 05:53:19.395192
1461 05:53:19.398998 [CATrainingPosCal] consider 2 rank data
1462 05:53:19.401976 u2DelayCellTimex100 = 270/100 ps
1463 05:53:19.404964 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 05:53:19.408514 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1465 05:53:19.414969 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1466 05:53:19.418460 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 05:53:19.421679 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 05:53:19.424791 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1469 05:53:19.424888
1470 05:53:19.428408 CA PerBit enable=1, Macro0, CA PI delay=34
1471 05:53:19.428502
1472 05:53:19.431702 [CBTSetCACLKResult] CA Dly = 34
1473 05:53:19.431797 CS Dly: 6 (0~38)
1474 05:53:19.431866
1475 05:53:19.435118 ----->DramcWriteLeveling(PI) begin...
1476 05:53:19.435208 ==
1477 05:53:19.438979 Dram Type= 6, Freq= 0, CH_1, rank 0
1478 05:53:19.442491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 05:53:19.446496 ==
1480 05:53:19.446603 Write leveling (Byte 0): 26 => 26
1481 05:53:19.450105 Write leveling (Byte 1): 28 => 28
1482 05:53:19.453796 DramcWriteLeveling(PI) end<-----
1483 05:53:19.453895
1484 05:53:19.454002 ==
1485 05:53:19.457456 Dram Type= 6, Freq= 0, CH_1, rank 0
1486 05:53:19.461045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1487 05:53:19.461149 ==
1488 05:53:19.464628 [Gating] SW mode calibration
1489 05:53:19.471760 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1490 05:53:19.475135 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1491 05:53:19.481838 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1492 05:53:19.485248 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 05:53:19.488753 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 05:53:19.495421 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 05:53:19.498884 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 05:53:19.502113 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 05:53:19.505184 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 05:53:19.512303 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 05:53:19.515174 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 05:53:19.518736 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 05:53:19.525832 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 05:53:19.528768 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 05:53:19.532054 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 05:53:19.538563 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 05:53:19.541816 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 05:53:19.545852 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 05:53:19.551946 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 05:53:19.555341 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1509 05:53:19.558718 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 05:53:19.565515 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 05:53:19.568360 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 05:53:19.571953 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 05:53:19.578602 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 05:53:19.581898 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 05:53:19.585052 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 05:53:19.591920 0 9 4 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
1517 05:53:19.594951 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 05:53:19.598442 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 05:53:19.605680 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 05:53:19.608708 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 05:53:19.611601 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 05:53:19.618401 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1523 05:53:19.621761 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1524 05:53:19.625020 0 10 4 | B1->B0 | 3131 2f2f | 1 1 | (1 0) (1 0)
1525 05:53:19.628640 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1526 05:53:19.635201 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 05:53:19.638461 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 05:53:19.641746 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 05:53:19.648608 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 05:53:19.651884 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 05:53:19.655569 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 05:53:19.661830 0 11 4 | B1->B0 | 3030 3535 | 0 1 | (0 0) (0 0)
1533 05:53:19.665116 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1534 05:53:19.668511 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 05:53:19.675632 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 05:53:19.678997 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 05:53:19.681996 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 05:53:19.688644 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 05:53:19.691950 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1540 05:53:19.695405 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1541 05:53:19.698637 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 05:53:19.705557 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 05:53:19.708585 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 05:53:19.712245 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 05:53:19.718850 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 05:53:19.722092 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 05:53:19.725202 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 05:53:19.732235 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 05:53:19.735412 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 05:53:19.738620 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 05:53:19.745352 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 05:53:19.748904 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 05:53:19.752051 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 05:53:19.758627 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 05:53:19.762064 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1556 05:53:19.765374 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1557 05:53:19.768851 Total UI for P1: 0, mck2ui 16
1558 05:53:19.772095 best dqsien dly found for B0: ( 0, 14, 0)
1559 05:53:19.775625 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 05:53:19.778639 Total UI for P1: 0, mck2ui 16
1561 05:53:19.782378 best dqsien dly found for B1: ( 0, 14, 4)
1562 05:53:19.785332 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1563 05:53:19.792042 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1564 05:53:19.792138
1565 05:53:19.795542 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1566 05:53:19.798810 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1567 05:53:19.802315 [Gating] SW calibration Done
1568 05:53:19.802400 ==
1569 05:53:19.805608 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 05:53:19.809239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 05:53:19.809324 ==
1572 05:53:19.809391 RX Vref Scan: 0
1573 05:53:19.809453
1574 05:53:19.812034 RX Vref 0 -> 0, step: 1
1575 05:53:19.812117
1576 05:53:19.815484 RX Delay -130 -> 252, step: 16
1577 05:53:19.818860 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1578 05:53:19.822109 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1579 05:53:19.828805 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1580 05:53:19.832252 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1581 05:53:19.835288 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1582 05:53:19.838917 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1583 05:53:19.842222 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1584 05:53:19.849110 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1585 05:53:19.852190 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1586 05:53:19.855588 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1587 05:53:19.858998 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1588 05:53:19.862478 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1589 05:53:19.868766 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1590 05:53:19.872120 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1591 05:53:19.876155 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1592 05:53:19.878749 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1593 05:53:19.878835 ==
1594 05:53:19.882533 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 05:53:19.889342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 05:53:19.889432 ==
1597 05:53:19.889500 DQS Delay:
1598 05:53:19.889561 DQS0 = 0, DQS1 = 0
1599 05:53:19.891980 DQM Delay:
1600 05:53:19.892064 DQM0 = 90, DQM1 = 80
1601 05:53:19.895377 DQ Delay:
1602 05:53:19.898980 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93
1603 05:53:19.902332 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =85
1604 05:53:19.905551 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1605 05:53:19.908724 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1606 05:53:19.908810
1607 05:53:19.908877
1608 05:53:19.908938 ==
1609 05:53:19.912044 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 05:53:19.915594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 05:53:19.915680 ==
1612 05:53:19.915747
1613 05:53:19.915807
1614 05:53:19.919106 TX Vref Scan disable
1615 05:53:19.919190 == TX Byte 0 ==
1616 05:53:19.925661 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1617 05:53:19.928595 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1618 05:53:19.928682 == TX Byte 1 ==
1619 05:53:19.935486 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1620 05:53:19.938883 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1621 05:53:19.938973 ==
1622 05:53:19.942128 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 05:53:19.945546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 05:53:19.945634 ==
1625 05:53:19.959111 TX Vref=22, minBit 10, minWin=27, winSum=448
1626 05:53:19.962430 TX Vref=24, minBit 15, minWin=27, winSum=454
1627 05:53:19.965969 TX Vref=26, minBit 15, minWin=27, winSum=457
1628 05:53:19.969361 TX Vref=28, minBit 15, minWin=27, winSum=459
1629 05:53:19.972615 TX Vref=30, minBit 8, minWin=28, winSum=460
1630 05:53:19.979142 TX Vref=32, minBit 12, minWin=27, winSum=458
1631 05:53:19.982690 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1632 05:53:19.982783
1633 05:53:19.986100 Final TX Range 1 Vref 30
1634 05:53:19.986187
1635 05:53:19.986254 ==
1636 05:53:19.989216 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 05:53:19.992686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 05:53:19.996586 ==
1639 05:53:19.996674
1640 05:53:19.996741
1641 05:53:19.996805 TX Vref Scan disable
1642 05:53:19.999578 == TX Byte 0 ==
1643 05:53:20.002946 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1644 05:53:20.009355 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1645 05:53:20.009463 == TX Byte 1 ==
1646 05:53:20.013313 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1647 05:53:20.016372 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1648 05:53:20.020320
1649 05:53:20.020421 [DATLAT]
1650 05:53:20.020489 Freq=800, CH1 RK0
1651 05:53:20.020553
1652 05:53:20.024134 DATLAT Default: 0xa
1653 05:53:20.024219 0, 0xFFFF, sum = 0
1654 05:53:20.027324 1, 0xFFFF, sum = 0
1655 05:53:20.027415 2, 0xFFFF, sum = 0
1656 05:53:20.030708 3, 0xFFFF, sum = 0
1657 05:53:20.030797 4, 0xFFFF, sum = 0
1658 05:53:20.034300 5, 0xFFFF, sum = 0
1659 05:53:20.034388 6, 0xFFFF, sum = 0
1660 05:53:20.037389 7, 0xFFFF, sum = 0
1661 05:53:20.037475 8, 0xFFFF, sum = 0
1662 05:53:20.040536 9, 0x0, sum = 1
1663 05:53:20.040623 10, 0x0, sum = 2
1664 05:53:20.044004 11, 0x0, sum = 3
1665 05:53:20.044097 12, 0x0, sum = 4
1666 05:53:20.044166 best_step = 10
1667 05:53:20.047378
1668 05:53:20.047463 ==
1669 05:53:20.050683 Dram Type= 6, Freq= 0, CH_1, rank 0
1670 05:53:20.054214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1671 05:53:20.054302 ==
1672 05:53:20.054370 RX Vref Scan: 1
1673 05:53:20.054435
1674 05:53:20.057358 Set Vref Range= 32 -> 127
1675 05:53:20.057443
1676 05:53:20.060622 RX Vref 32 -> 127, step: 1
1677 05:53:20.060710
1678 05:53:20.063991 RX Delay -95 -> 252, step: 8
1679 05:53:20.064079
1680 05:53:20.067745 Set Vref, RX VrefLevel [Byte0]: 32
1681 05:53:20.070967 [Byte1]: 32
1682 05:53:20.071058
1683 05:53:20.074311 Set Vref, RX VrefLevel [Byte0]: 33
1684 05:53:20.077438 [Byte1]: 33
1685 05:53:20.077526
1686 05:53:20.081029 Set Vref, RX VrefLevel [Byte0]: 34
1687 05:53:20.084209 [Byte1]: 34
1688 05:53:20.087784
1689 05:53:20.087873 Set Vref, RX VrefLevel [Byte0]: 35
1690 05:53:20.091058 [Byte1]: 35
1691 05:53:20.094967
1692 05:53:20.095056 Set Vref, RX VrefLevel [Byte0]: 36
1693 05:53:20.098497 [Byte1]: 36
1694 05:53:20.102706
1695 05:53:20.102794 Set Vref, RX VrefLevel [Byte0]: 37
1696 05:53:20.105785 [Byte1]: 37
1697 05:53:20.110350
1698 05:53:20.110476 Set Vref, RX VrefLevel [Byte0]: 38
1699 05:53:20.113490 [Byte1]: 38
1700 05:53:20.118215
1701 05:53:20.118342 Set Vref, RX VrefLevel [Byte0]: 39
1702 05:53:20.121145 [Byte1]: 39
1703 05:53:20.125438
1704 05:53:20.125559 Set Vref, RX VrefLevel [Byte0]: 40
1705 05:53:20.128806 [Byte1]: 40
1706 05:53:20.133406
1707 05:53:20.133516 Set Vref, RX VrefLevel [Byte0]: 41
1708 05:53:20.136820 [Byte1]: 41
1709 05:53:20.140817
1710 05:53:20.140956 Set Vref, RX VrefLevel [Byte0]: 42
1711 05:53:20.144175 [Byte1]: 42
1712 05:53:20.148408
1713 05:53:20.148519 Set Vref, RX VrefLevel [Byte0]: 43
1714 05:53:20.151604 [Byte1]: 43
1715 05:53:20.156156
1716 05:53:20.156267 Set Vref, RX VrefLevel [Byte0]: 44
1717 05:53:20.159356 [Byte1]: 44
1718 05:53:20.163552
1719 05:53:20.163665 Set Vref, RX VrefLevel [Byte0]: 45
1720 05:53:20.166601 [Byte1]: 45
1721 05:53:20.171263
1722 05:53:20.171385 Set Vref, RX VrefLevel [Byte0]: 46
1723 05:53:20.174382 [Byte1]: 46
1724 05:53:20.178866
1725 05:53:20.178981 Set Vref, RX VrefLevel [Byte0]: 47
1726 05:53:20.181960 [Byte1]: 47
1727 05:53:20.186222
1728 05:53:20.186334 Set Vref, RX VrefLevel [Byte0]: 48
1729 05:53:20.192672 [Byte1]: 48
1730 05:53:20.192799
1731 05:53:20.195942 Set Vref, RX VrefLevel [Byte0]: 49
1732 05:53:20.199330 [Byte1]: 49
1733 05:53:20.199447
1734 05:53:20.202920 Set Vref, RX VrefLevel [Byte0]: 50
1735 05:53:20.205921 [Byte1]: 50
1736 05:53:20.206034
1737 05:53:20.209373 Set Vref, RX VrefLevel [Byte0]: 51
1738 05:53:20.212675 [Byte1]: 51
1739 05:53:20.216696
1740 05:53:20.216792 Set Vref, RX VrefLevel [Byte0]: 52
1741 05:53:20.219894 [Byte1]: 52
1742 05:53:20.224497
1743 05:53:20.224590 Set Vref, RX VrefLevel [Byte0]: 53
1744 05:53:20.227456 [Byte1]: 53
1745 05:53:20.232203
1746 05:53:20.232298 Set Vref, RX VrefLevel [Byte0]: 54
1747 05:53:20.235004 [Byte1]: 54
1748 05:53:20.239489
1749 05:53:20.239581 Set Vref, RX VrefLevel [Byte0]: 55
1750 05:53:20.242790 [Byte1]: 55
1751 05:53:20.247183
1752 05:53:20.247284 Set Vref, RX VrefLevel [Byte0]: 56
1753 05:53:20.250459 [Byte1]: 56
1754 05:53:20.254640
1755 05:53:20.254735 Set Vref, RX VrefLevel [Byte0]: 57
1756 05:53:20.257757 [Byte1]: 57
1757 05:53:20.262399
1758 05:53:20.262496 Set Vref, RX VrefLevel [Byte0]: 58
1759 05:53:20.265400 [Byte1]: 58
1760 05:53:20.270323
1761 05:53:20.270415 Set Vref, RX VrefLevel [Byte0]: 59
1762 05:53:20.272939 [Byte1]: 59
1763 05:53:20.277215
1764 05:53:20.277308 Set Vref, RX VrefLevel [Byte0]: 60
1765 05:53:20.280588 [Byte1]: 60
1766 05:53:20.284865
1767 05:53:20.284952 Set Vref, RX VrefLevel [Byte0]: 61
1768 05:53:20.291581 [Byte1]: 61
1769 05:53:20.291681
1770 05:53:20.294884 Set Vref, RX VrefLevel [Byte0]: 62
1771 05:53:20.297843 [Byte1]: 62
1772 05:53:20.297955
1773 05:53:20.301611 Set Vref, RX VrefLevel [Byte0]: 63
1774 05:53:20.305340 [Byte1]: 63
1775 05:53:20.305430
1776 05:53:20.308512 Set Vref, RX VrefLevel [Byte0]: 64
1777 05:53:20.311733 [Byte1]: 64
1778 05:53:20.315539
1779 05:53:20.315628 Set Vref, RX VrefLevel [Byte0]: 65
1780 05:53:20.318704 [Byte1]: 65
1781 05:53:20.323288
1782 05:53:20.323384 Set Vref, RX VrefLevel [Byte0]: 66
1783 05:53:20.326172 [Byte1]: 66
1784 05:53:20.330522
1785 05:53:20.330624 Set Vref, RX VrefLevel [Byte0]: 67
1786 05:53:20.333730 [Byte1]: 67
1787 05:53:20.337918
1788 05:53:20.338050 Set Vref, RX VrefLevel [Byte0]: 68
1789 05:53:20.341786 [Byte1]: 68
1790 05:53:20.345587
1791 05:53:20.345692 Set Vref, RX VrefLevel [Byte0]: 69
1792 05:53:20.349138 [Byte1]: 69
1793 05:53:20.353146
1794 05:53:20.353248 Set Vref, RX VrefLevel [Byte0]: 70
1795 05:53:20.357014 [Byte1]: 70
1796 05:53:20.360856
1797 05:53:20.360952 Set Vref, RX VrefLevel [Byte0]: 71
1798 05:53:20.364602 [Byte1]: 71
1799 05:53:20.368716
1800 05:53:20.368812 Set Vref, RX VrefLevel [Byte0]: 72
1801 05:53:20.372097 [Byte1]: 72
1802 05:53:20.376039
1803 05:53:20.376133 Set Vref, RX VrefLevel [Byte0]: 73
1804 05:53:20.379359 [Byte1]: 73
1805 05:53:20.383697
1806 05:53:20.383798 Set Vref, RX VrefLevel [Byte0]: 74
1807 05:53:20.386967 [Byte1]: 74
1808 05:53:20.391213
1809 05:53:20.391304 Set Vref, RX VrefLevel [Byte0]: 75
1810 05:53:20.394680 [Byte1]: 75
1811 05:53:20.399017
1812 05:53:20.399116 Set Vref, RX VrefLevel [Byte0]: 76
1813 05:53:20.402251 [Byte1]: 76
1814 05:53:20.406733
1815 05:53:20.406850 Set Vref, RX VrefLevel [Byte0]: 77
1816 05:53:20.409858 [Byte1]: 77
1817 05:53:20.414417
1818 05:53:20.414537 Final RX Vref Byte 0 = 54 to rank0
1819 05:53:20.417739 Final RX Vref Byte 1 = 62 to rank0
1820 05:53:20.420922 Final RX Vref Byte 0 = 54 to rank1
1821 05:53:20.424587 Final RX Vref Byte 1 = 62 to rank1==
1822 05:53:20.427561 Dram Type= 6, Freq= 0, CH_1, rank 0
1823 05:53:20.431080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1824 05:53:20.434564 ==
1825 05:53:20.434678 DQS Delay:
1826 05:53:20.434751 DQS0 = 0, DQS1 = 0
1827 05:53:20.437779 DQM Delay:
1828 05:53:20.437876 DQM0 = 91, DQM1 = 82
1829 05:53:20.441246 DQ Delay:
1830 05:53:20.441367 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1831 05:53:20.444479 DQ4 =88, DQ5 =96, DQ6 =100, DQ7 =88
1832 05:53:20.447678 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1833 05:53:20.451136 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1834 05:53:20.451248
1835 05:53:20.454962
1836 05:53:20.460958 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1837 05:53:20.464446 CH1 RK0: MR19=606, MR18=2D4B
1838 05:53:20.470911 CH1_RK0: MR19=0x606, MR18=0x2D4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1839 05:53:20.471056
1840 05:53:20.474395 ----->DramcWriteLeveling(PI) begin...
1841 05:53:20.474499 ==
1842 05:53:20.477800 Dram Type= 6, Freq= 0, CH_1, rank 1
1843 05:53:20.481121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1844 05:53:20.481232 ==
1845 05:53:20.484474 Write leveling (Byte 0): 24 => 24
1846 05:53:20.487905 Write leveling (Byte 1): 30 => 30
1847 05:53:20.491786 DramcWriteLeveling(PI) end<-----
1848 05:53:20.491901
1849 05:53:20.491990 ==
1850 05:53:20.494536 Dram Type= 6, Freq= 0, CH_1, rank 1
1851 05:53:20.497952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1852 05:53:20.498057 ==
1853 05:53:20.501301 [Gating] SW mode calibration
1854 05:53:20.508132 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1855 05:53:20.514816 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1856 05:53:20.518005 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1857 05:53:20.521758 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 05:53:20.525107 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 05:53:20.531354 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 05:53:20.534739 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 05:53:20.538090 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 05:53:20.544775 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 05:53:20.548078 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 05:53:20.551280 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 05:53:20.558360 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 05:53:20.561308 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 05:53:20.564749 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 05:53:20.571347 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 05:53:20.574767 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 05:53:20.578339 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 05:53:20.584994 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 05:53:20.588129 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 05:53:20.592188 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1874 05:53:20.598160 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 05:53:20.601888 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 05:53:20.605286 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 05:53:20.608669 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 05:53:20.615057 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 05:53:20.618300 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 05:53:20.621689 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 05:53:20.628712 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 05:53:20.631921 0 9 8 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 1)
1883 05:53:20.635605 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 05:53:20.641691 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 05:53:20.645174 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 05:53:20.648539 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 05:53:20.655288 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 05:53:20.658664 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 05:53:20.661849 0 10 4 | B1->B0 | 2d2d 3030 | 1 1 | (1 0) (1 0)
1890 05:53:20.668215 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1891 05:53:20.671670 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 05:53:20.675119 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 05:53:20.681781 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 05:53:20.685377 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 05:53:20.688436 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 05:53:20.692053 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 05:53:20.698514 0 11 4 | B1->B0 | 3130 2f2f | 1 0 | (1 1) (0 0)
1898 05:53:20.701948 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 05:53:20.704918 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 05:53:20.711711 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 05:53:20.714965 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 05:53:20.718346 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 05:53:20.725009 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 05:53:20.728858 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 05:53:20.732176 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1906 05:53:20.738759 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1907 05:53:20.741559 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 05:53:20.744879 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 05:53:20.751565 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 05:53:20.755039 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 05:53:20.758263 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 05:53:20.765014 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 05:53:20.768242 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 05:53:20.771964 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 05:53:20.778693 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 05:53:20.781560 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 05:53:20.784787 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 05:53:20.791833 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 05:53:20.795066 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 05:53:20.798335 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 05:53:20.801892 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1922 05:53:20.808186 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 05:53:20.811811 Total UI for P1: 0, mck2ui 16
1924 05:53:20.814910 best dqsien dly found for B0: ( 0, 14, 4)
1925 05:53:20.818457 Total UI for P1: 0, mck2ui 16
1926 05:53:20.821712 best dqsien dly found for B1: ( 0, 14, 4)
1927 05:53:20.824811 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1928 05:53:20.828400 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1929 05:53:20.828487
1930 05:53:20.831543 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1931 05:53:20.835014 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1932 05:53:20.838394 [Gating] SW calibration Done
1933 05:53:20.838481 ==
1934 05:53:20.841812 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 05:53:20.845030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 05:53:20.845125 ==
1937 05:53:20.848077 RX Vref Scan: 0
1938 05:53:20.848164
1939 05:53:20.848250 RX Vref 0 -> 0, step: 1
1940 05:53:20.848352
1941 05:53:20.851784 RX Delay -130 -> 252, step: 16
1942 05:53:20.855006 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1943 05:53:20.861662 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1944 05:53:20.865022 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1945 05:53:20.868301 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1946 05:53:20.871690 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1947 05:53:20.875265 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1948 05:53:20.881811 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1949 05:53:20.885196 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1950 05:53:20.888431 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1951 05:53:20.891523 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1952 05:53:20.895108 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1953 05:53:20.901757 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1954 05:53:20.905296 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1955 05:53:20.908617 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1956 05:53:20.911948 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1957 05:53:20.915057 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1958 05:53:20.918531 ==
1959 05:53:20.918619 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 05:53:20.925157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 05:53:20.925250 ==
1962 05:53:20.925338 DQS Delay:
1963 05:53:20.928371 DQS0 = 0, DQS1 = 0
1964 05:53:20.928458 DQM Delay:
1965 05:53:20.932066 DQM0 = 90, DQM1 = 82
1966 05:53:20.932152 DQ Delay:
1967 05:53:20.934961 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1968 05:53:20.938378 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1969 05:53:20.941593 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =77
1970 05:53:20.945227 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1971 05:53:20.945320
1972 05:53:20.945405
1973 05:53:20.945486 ==
1974 05:53:20.948442 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 05:53:20.951409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 05:53:20.951521 ==
1977 05:53:20.951616
1978 05:53:20.951697
1979 05:53:20.954959 TX Vref Scan disable
1980 05:53:20.958380 == TX Byte 0 ==
1981 05:53:20.961583 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1982 05:53:20.965012 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1983 05:53:20.968416 == TX Byte 1 ==
1984 05:53:20.971742 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1985 05:53:20.975112 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1986 05:53:20.975201 ==
1987 05:53:20.978589 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 05:53:20.981686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 05:53:20.984485 ==
1990 05:53:20.996923 TX Vref=22, minBit 13, minWin=27, winSum=451
1991 05:53:20.999924 TX Vref=24, minBit 13, minWin=27, winSum=454
1992 05:53:21.003463 TX Vref=26, minBit 15, minWin=27, winSum=455
1993 05:53:21.006604 TX Vref=28, minBit 13, minWin=27, winSum=459
1994 05:53:21.010353 TX Vref=30, minBit 9, minWin=27, winSum=458
1995 05:53:21.016720 TX Vref=32, minBit 9, minWin=27, winSum=458
1996 05:53:21.019982 [TxChooseVref] Worse bit 13, Min win 27, Win sum 459, Final Vref 28
1997 05:53:21.020074
1998 05:53:21.023487 Final TX Range 1 Vref 28
1999 05:53:21.023577
2000 05:53:21.023663 ==
2001 05:53:21.026674 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 05:53:21.030198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 05:53:21.033593 ==
2004 05:53:21.033682
2005 05:53:21.033768
2006 05:53:21.033869 TX Vref Scan disable
2007 05:53:21.037482 == TX Byte 0 ==
2008 05:53:21.040250 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2009 05:53:21.043736 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2010 05:53:21.046979 == TX Byte 1 ==
2011 05:53:21.050634 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2012 05:53:21.053830 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2013 05:53:21.057399
2014 05:53:21.057492 [DATLAT]
2015 05:53:21.057579 Freq=800, CH1 RK1
2016 05:53:21.057682
2017 05:53:21.060486 DATLAT Default: 0xa
2018 05:53:21.060575 0, 0xFFFF, sum = 0
2019 05:53:21.063664 1, 0xFFFF, sum = 0
2020 05:53:21.063754 2, 0xFFFF, sum = 0
2021 05:53:21.066971 3, 0xFFFF, sum = 0
2022 05:53:21.067060 4, 0xFFFF, sum = 0
2023 05:53:21.070476 5, 0xFFFF, sum = 0
2024 05:53:21.073847 6, 0xFFFF, sum = 0
2025 05:53:21.073963 7, 0xFFFF, sum = 0
2026 05:53:21.076857 8, 0xFFFF, sum = 0
2027 05:53:21.076947 9, 0x0, sum = 1
2028 05:53:21.077036 10, 0x0, sum = 2
2029 05:53:21.080375 11, 0x0, sum = 3
2030 05:53:21.080468 12, 0x0, sum = 4
2031 05:53:21.083617 best_step = 10
2032 05:53:21.083707
2033 05:53:21.083794 ==
2034 05:53:21.086970 Dram Type= 6, Freq= 0, CH_1, rank 1
2035 05:53:21.090097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2036 05:53:21.090188 ==
2037 05:53:21.093862 RX Vref Scan: 0
2038 05:53:21.093973
2039 05:53:21.094072 RX Vref 0 -> 0, step: 1
2040 05:53:21.094154
2041 05:53:21.096875 RX Delay -95 -> 252, step: 8
2042 05:53:21.104054 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2043 05:53:21.107083 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2044 05:53:21.110343 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2045 05:53:21.113987 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2046 05:53:21.117380 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2047 05:53:21.124063 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2048 05:53:21.127151 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2049 05:53:21.130568 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2050 05:53:21.133685 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2051 05:53:21.136971 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2052 05:53:21.143670 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2053 05:53:21.147140 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2054 05:53:21.150291 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2055 05:53:21.154259 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2056 05:53:21.156764 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2057 05:53:21.164011 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2058 05:53:21.164130 ==
2059 05:53:21.166755 Dram Type= 6, Freq= 0, CH_1, rank 1
2060 05:53:21.170195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2061 05:53:21.170301 ==
2062 05:53:21.170391 DQS Delay:
2063 05:53:21.173721 DQS0 = 0, DQS1 = 0
2064 05:53:21.173811 DQM Delay:
2065 05:53:21.176799 DQM0 = 91, DQM1 = 83
2066 05:53:21.176886 DQ Delay:
2067 05:53:21.180148 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2068 05:53:21.183479 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2069 05:53:21.186858 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =80
2070 05:53:21.190441 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2071 05:53:21.190538
2072 05:53:21.190626
2073 05:53:21.197010 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2074 05:53:21.200303 CH1 RK1: MR19=606, MR18=3A0F
2075 05:53:21.207235 CH1_RK1: MR19=0x606, MR18=0x3A0F, DQSOSC=395, MR23=63, INC=94, DEC=63
2076 05:53:21.210406 [RxdqsGatingPostProcess] freq 800
2077 05:53:21.216800 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2078 05:53:21.220197 Pre-setting of DQS Precalculation
2079 05:53:21.223520 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2080 05:53:21.230037 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2081 05:53:21.237054 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2082 05:53:21.237174
2083 05:53:21.237267
2084 05:53:21.240341 [Calibration Summary] 1600 Mbps
2085 05:53:21.243453 CH 0, Rank 0
2086 05:53:21.243544 SW Impedance : PASS
2087 05:53:21.246920 DUTY Scan : NO K
2088 05:53:21.250215 ZQ Calibration : PASS
2089 05:53:21.250303 Jitter Meter : NO K
2090 05:53:21.253406 CBT Training : PASS
2091 05:53:21.257032 Write leveling : PASS
2092 05:53:21.257120 RX DQS gating : PASS
2093 05:53:21.260527 RX DQ/DQS(RDDQC) : PASS
2094 05:53:21.263597 TX DQ/DQS : PASS
2095 05:53:21.263685 RX DATLAT : PASS
2096 05:53:21.267357 RX DQ/DQS(Engine): PASS
2097 05:53:21.267445 TX OE : NO K
2098 05:53:21.270366 All Pass.
2099 05:53:21.270451
2100 05:53:21.270517 CH 0, Rank 1
2101 05:53:21.273406 SW Impedance : PASS
2102 05:53:21.273493 DUTY Scan : NO K
2103 05:53:21.276974 ZQ Calibration : PASS
2104 05:53:21.280160 Jitter Meter : NO K
2105 05:53:21.280249 CBT Training : PASS
2106 05:53:21.283956 Write leveling : PASS
2107 05:53:21.286843 RX DQS gating : PASS
2108 05:53:21.286934 RX DQ/DQS(RDDQC) : PASS
2109 05:53:21.290458 TX DQ/DQS : PASS
2110 05:53:21.293814 RX DATLAT : PASS
2111 05:53:21.293905 RX DQ/DQS(Engine): PASS
2112 05:53:21.296841 TX OE : NO K
2113 05:53:21.296929 All Pass.
2114 05:53:21.296997
2115 05:53:21.300390 CH 1, Rank 0
2116 05:53:21.300477 SW Impedance : PASS
2117 05:53:21.303422 DUTY Scan : NO K
2118 05:53:21.307078 ZQ Calibration : PASS
2119 05:53:21.307172 Jitter Meter : NO K
2120 05:53:21.310541 CBT Training : PASS
2121 05:53:21.310630 Write leveling : PASS
2122 05:53:21.313550 RX DQS gating : PASS
2123 05:53:21.316695 RX DQ/DQS(RDDQC) : PASS
2124 05:53:21.316788 TX DQ/DQS : PASS
2125 05:53:21.320305 RX DATLAT : PASS
2126 05:53:21.323489 RX DQ/DQS(Engine): PASS
2127 05:53:21.323583 TX OE : NO K
2128 05:53:21.326855 All Pass.
2129 05:53:21.326969
2130 05:53:21.327039 CH 1, Rank 1
2131 05:53:21.330404 SW Impedance : PASS
2132 05:53:21.330491 DUTY Scan : NO K
2133 05:53:21.333364 ZQ Calibration : PASS
2134 05:53:21.336966 Jitter Meter : NO K
2135 05:53:21.337054 CBT Training : PASS
2136 05:53:21.340200 Write leveling : PASS
2137 05:53:21.343392 RX DQS gating : PASS
2138 05:53:21.343528 RX DQ/DQS(RDDQC) : PASS
2139 05:53:21.346763 TX DQ/DQS : PASS
2140 05:53:21.350126 RX DATLAT : PASS
2141 05:53:21.350234 RX DQ/DQS(Engine): PASS
2142 05:53:21.353324 TX OE : NO K
2143 05:53:21.353411 All Pass.
2144 05:53:21.353477
2145 05:53:21.356772 DramC Write-DBI off
2146 05:53:21.360161 PER_BANK_REFRESH: Hybrid Mode
2147 05:53:21.360249 TX_TRACKING: ON
2148 05:53:21.363416 [GetDramInforAfterCalByMRR] Vendor 6.
2149 05:53:21.367001 [GetDramInforAfterCalByMRR] Revision 606.
2150 05:53:21.370090 [GetDramInforAfterCalByMRR] Revision 2 0.
2151 05:53:21.373692 MR0 0x3b3b
2152 05:53:21.373785 MR8 0x5151
2153 05:53:21.377083 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2154 05:53:21.377171
2155 05:53:21.377239 MR0 0x3b3b
2156 05:53:21.380381 MR8 0x5151
2157 05:53:21.383662 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2158 05:53:21.383748
2159 05:53:21.390205 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2160 05:53:21.397057 [FAST_K] Save calibration result to emmc
2161 05:53:21.400046 [FAST_K] Save calibration result to emmc
2162 05:53:21.400138 dram_init: config_dvfs: 1
2163 05:53:21.403454 dramc_set_vcore_voltage set vcore to 662500
2164 05:53:21.406827 Read voltage for 1200, 2
2165 05:53:21.406915 Vio18 = 0
2166 05:53:21.410130 Vcore = 662500
2167 05:53:21.410217 Vdram = 0
2168 05:53:21.410285 Vddq = 0
2169 05:53:21.413365 Vmddr = 0
2170 05:53:21.416759 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2171 05:53:21.424051 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2172 05:53:21.424165 MEM_TYPE=3, freq_sel=15
2173 05:53:21.426854 sv_algorithm_assistance_LP4_1600
2174 05:53:21.433322 ============ PULL DRAM RESETB DOWN ============
2175 05:53:21.436624 ========== PULL DRAM RESETB DOWN end =========
2176 05:53:21.440211 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2177 05:53:21.443535 ===================================
2178 05:53:21.446678 LPDDR4 DRAM CONFIGURATION
2179 05:53:21.450081 ===================================
2180 05:53:21.453155 EX_ROW_EN[0] = 0x0
2181 05:53:21.453245 EX_ROW_EN[1] = 0x0
2182 05:53:21.456706 LP4Y_EN = 0x0
2183 05:53:21.456797 WORK_FSP = 0x0
2184 05:53:21.459873 WL = 0x4
2185 05:53:21.459960 RL = 0x4
2186 05:53:21.463327 BL = 0x2
2187 05:53:21.463417 RPST = 0x0
2188 05:53:21.466868 RD_PRE = 0x0
2189 05:53:21.466960 WR_PRE = 0x1
2190 05:53:21.470152 WR_PST = 0x0
2191 05:53:21.470241 DBI_WR = 0x0
2192 05:53:21.473440 DBI_RD = 0x0
2193 05:53:21.473530 OTF = 0x1
2194 05:53:21.476447 ===================================
2195 05:53:21.480062 ===================================
2196 05:53:21.483395 ANA top config
2197 05:53:21.486788 ===================================
2198 05:53:21.486883 DLL_ASYNC_EN = 0
2199 05:53:21.489736 ALL_SLAVE_EN = 0
2200 05:53:21.493422 NEW_RANK_MODE = 1
2201 05:53:21.496509 DLL_IDLE_MODE = 1
2202 05:53:21.500023 LP45_APHY_COMB_EN = 1
2203 05:53:21.500112 TX_ODT_DIS = 1
2204 05:53:21.503359 NEW_8X_MODE = 1
2205 05:53:21.506517 ===================================
2206 05:53:21.509891 ===================================
2207 05:53:21.513204 data_rate = 2400
2208 05:53:21.516426 CKR = 1
2209 05:53:21.519946 DQ_P2S_RATIO = 8
2210 05:53:21.523359 ===================================
2211 05:53:21.523457 CA_P2S_RATIO = 8
2212 05:53:21.526905 DQ_CA_OPEN = 0
2213 05:53:21.530132 DQ_SEMI_OPEN = 0
2214 05:53:21.533581 CA_SEMI_OPEN = 0
2215 05:53:21.536711 CA_FULL_RATE = 0
2216 05:53:21.540078 DQ_CKDIV4_EN = 0
2217 05:53:21.540172 CA_CKDIV4_EN = 0
2218 05:53:21.543588 CA_PREDIV_EN = 0
2219 05:53:21.546953 PH8_DLY = 17
2220 05:53:21.550147 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2221 05:53:21.553243 DQ_AAMCK_DIV = 4
2222 05:53:21.556581 CA_AAMCK_DIV = 4
2223 05:53:21.556671 CA_ADMCK_DIV = 4
2224 05:53:21.559989 DQ_TRACK_CA_EN = 0
2225 05:53:21.563207 CA_PICK = 1200
2226 05:53:21.566795 CA_MCKIO = 1200
2227 05:53:21.570237 MCKIO_SEMI = 0
2228 05:53:21.573457 PLL_FREQ = 2366
2229 05:53:21.576658 DQ_UI_PI_RATIO = 32
2230 05:53:21.576751 CA_UI_PI_RATIO = 0
2231 05:53:21.580060 ===================================
2232 05:53:21.583476 ===================================
2233 05:53:21.586663 memory_type:LPDDR4
2234 05:53:21.590122 GP_NUM : 10
2235 05:53:21.590211 SRAM_EN : 1
2236 05:53:21.593400 MD32_EN : 0
2237 05:53:21.596774 ===================================
2238 05:53:21.600505 [ANA_INIT] >>>>>>>>>>>>>>
2239 05:53:21.600598 <<<<<< [CONFIGURE PHASE]: ANA_TX
2240 05:53:21.603779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2241 05:53:21.607171 ===================================
2242 05:53:21.610539 data_rate = 2400,PCW = 0X5b00
2243 05:53:21.613538 ===================================
2244 05:53:21.616875 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2245 05:53:21.623997 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2246 05:53:21.630226 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2247 05:53:21.633796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2248 05:53:21.637185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2249 05:53:21.640504 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2250 05:53:21.643674 [ANA_INIT] flow start
2251 05:53:21.643771 [ANA_INIT] PLL >>>>>>>>
2252 05:53:21.647187 [ANA_INIT] PLL <<<<<<<<
2253 05:53:21.650456 [ANA_INIT] MIDPI >>>>>>>>
2254 05:53:21.650552 [ANA_INIT] MIDPI <<<<<<<<
2255 05:53:21.653729 [ANA_INIT] DLL >>>>>>>>
2256 05:53:21.657167 [ANA_INIT] DLL <<<<<<<<
2257 05:53:21.657259 [ANA_INIT] flow end
2258 05:53:21.663787 ============ LP4 DIFF to SE enter ============
2259 05:53:21.666900 ============ LP4 DIFF to SE exit ============
2260 05:53:21.670228 [ANA_INIT] <<<<<<<<<<<<<
2261 05:53:21.673653 [Flow] Enable top DCM control >>>>>
2262 05:53:21.673751 [Flow] Enable top DCM control <<<<<
2263 05:53:21.677027 Enable DLL master slave shuffle
2264 05:53:21.684030 ==============================================================
2265 05:53:21.687074 Gating Mode config
2266 05:53:21.690281 ==============================================================
2267 05:53:21.693965 Config description:
2268 05:53:21.704197 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2269 05:53:21.710530 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2270 05:53:21.713871 SELPH_MODE 0: By rank 1: By Phase
2271 05:53:21.720685 ==============================================================
2272 05:53:21.724157 GAT_TRACK_EN = 1
2273 05:53:21.724270 RX_GATING_MODE = 2
2274 05:53:21.727366 RX_GATING_TRACK_MODE = 2
2275 05:53:21.730681 SELPH_MODE = 1
2276 05:53:21.734084 PICG_EARLY_EN = 1
2277 05:53:21.737355 VALID_LAT_VALUE = 1
2278 05:53:21.743859 ==============================================================
2279 05:53:21.747071 Enter into Gating configuration >>>>
2280 05:53:21.750476 Exit from Gating configuration <<<<
2281 05:53:21.753759 Enter into DVFS_PRE_config >>>>>
2282 05:53:21.764167 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2283 05:53:21.767230 Exit from DVFS_PRE_config <<<<<
2284 05:53:21.770558 Enter into PICG configuration >>>>
2285 05:53:21.773882 Exit from PICG configuration <<<<
2286 05:53:21.777141 [RX_INPUT] configuration >>>>>
2287 05:53:21.780747 [RX_INPUT] configuration <<<<<
2288 05:53:21.784071 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2289 05:53:21.790627 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2290 05:53:21.797112 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2291 05:53:21.800489 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2292 05:53:21.807426 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2293 05:53:21.814773 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2294 05:53:21.817369 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2295 05:53:21.820717 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2296 05:53:21.827321 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2297 05:53:21.830838 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2298 05:53:21.833978 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2299 05:53:21.840681 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2300 05:53:21.843943 ===================================
2301 05:53:21.844084 LPDDR4 DRAM CONFIGURATION
2302 05:53:21.847286 ===================================
2303 05:53:21.850615 EX_ROW_EN[0] = 0x0
2304 05:53:21.850719 EX_ROW_EN[1] = 0x0
2305 05:53:21.853874 LP4Y_EN = 0x0
2306 05:53:21.854008 WORK_FSP = 0x0
2307 05:53:21.857352 WL = 0x4
2308 05:53:21.857448 RL = 0x4
2309 05:53:21.860537 BL = 0x2
2310 05:53:21.864000 RPST = 0x0
2311 05:53:21.864107 RD_PRE = 0x0
2312 05:53:21.867456 WR_PRE = 0x1
2313 05:53:21.867552 WR_PST = 0x0
2314 05:53:21.870708 DBI_WR = 0x0
2315 05:53:21.870809 DBI_RD = 0x0
2316 05:53:21.874393 OTF = 0x1
2317 05:53:21.877542 ===================================
2318 05:53:21.880792 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2319 05:53:21.884144 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2320 05:53:21.887799 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2321 05:53:21.891033 ===================================
2322 05:53:21.894152 LPDDR4 DRAM CONFIGURATION
2323 05:53:21.897755 ===================================
2324 05:53:21.900667 EX_ROW_EN[0] = 0x10
2325 05:53:21.900764 EX_ROW_EN[1] = 0x0
2326 05:53:21.903940 LP4Y_EN = 0x0
2327 05:53:21.904038 WORK_FSP = 0x0
2328 05:53:21.907732 WL = 0x4
2329 05:53:21.907877 RL = 0x4
2330 05:53:21.910608 BL = 0x2
2331 05:53:21.910728 RPST = 0x0
2332 05:53:21.914444 RD_PRE = 0x0
2333 05:53:21.914558 WR_PRE = 0x1
2334 05:53:21.917143 WR_PST = 0x0
2335 05:53:21.917284 DBI_WR = 0x0
2336 05:53:21.920705 DBI_RD = 0x0
2337 05:53:21.920838 OTF = 0x1
2338 05:53:21.924013 ===================================
2339 05:53:21.930788 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2340 05:53:21.930906 ==
2341 05:53:21.934064 Dram Type= 6, Freq= 0, CH_0, rank 0
2342 05:53:21.940882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2343 05:53:21.941023 ==
2344 05:53:21.941095 [Duty_Offset_Calibration]
2345 05:53:21.944203 B0:2 B1:0 CA:1
2346 05:53:21.944303
2347 05:53:21.947351 [DutyScan_Calibration_Flow] k_type=0
2348 05:53:21.955640
2349 05:53:21.955782 ==CLK 0==
2350 05:53:21.959048 Final CLK duty delay cell = -4
2351 05:53:21.962166 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2352 05:53:21.965569 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2353 05:53:21.968814 [-4] AVG Duty = 4953%(X100)
2354 05:53:21.968911
2355 05:53:21.972389 CH0 CLK Duty spec in!! Max-Min= 156%
2356 05:53:21.975349 [DutyScan_Calibration_Flow] ====Done====
2357 05:53:21.975442
2358 05:53:21.979171 [DutyScan_Calibration_Flow] k_type=1
2359 05:53:21.994520
2360 05:53:21.994675 ==DQS 0 ==
2361 05:53:21.997854 Final DQS duty delay cell = 0
2362 05:53:22.001028 [0] MAX Duty = 5187%(X100), DQS PI = 30
2363 05:53:22.005052 [0] MIN Duty = 4938%(X100), DQS PI = 0
2364 05:53:22.005147 [0] AVG Duty = 5062%(X100)
2365 05:53:22.005213
2366 05:53:22.008148 ==DQS 1 ==
2367 05:53:22.011326 Final DQS duty delay cell = -4
2368 05:53:22.014517 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2369 05:53:22.018065 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2370 05:53:22.018164 [-4] AVG Duty = 5031%(X100)
2371 05:53:22.021167
2372 05:53:22.024675 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2373 05:53:22.024772
2374 05:53:22.028194 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2375 05:53:22.031279 [DutyScan_Calibration_Flow] ====Done====
2376 05:53:22.031378
2377 05:53:22.034497 [DutyScan_Calibration_Flow] k_type=3
2378 05:53:22.051287
2379 05:53:22.051442 ==DQM 0 ==
2380 05:53:22.054349 Final DQM duty delay cell = 0
2381 05:53:22.057873 [0] MAX Duty = 5062%(X100), DQS PI = 22
2382 05:53:22.061090 [0] MIN Duty = 4813%(X100), DQS PI = 2
2383 05:53:22.061191 [0] AVG Duty = 4937%(X100)
2384 05:53:22.064407
2385 05:53:22.064508 ==DQM 1 ==
2386 05:53:22.067598 Final DQM duty delay cell = 0
2387 05:53:22.071358 [0] MAX Duty = 5187%(X100), DQS PI = 48
2388 05:53:22.074346 [0] MIN Duty = 5000%(X100), DQS PI = 22
2389 05:53:22.074453 [0] AVG Duty = 5093%(X100)
2390 05:53:22.077817
2391 05:53:22.081001 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2392 05:53:22.081096
2393 05:53:22.084491 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2394 05:53:22.087601 [DutyScan_Calibration_Flow] ====Done====
2395 05:53:22.087696
2396 05:53:22.090913 [DutyScan_Calibration_Flow] k_type=2
2397 05:53:22.107677
2398 05:53:22.107829 ==DQ 0 ==
2399 05:53:22.111289 Final DQ duty delay cell = -4
2400 05:53:22.114616 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2401 05:53:22.117513 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2402 05:53:22.121112 [-4] AVG Duty = 4968%(X100)
2403 05:53:22.121214
2404 05:53:22.121279 ==DQ 1 ==
2405 05:53:22.124310 Final DQ duty delay cell = 4
2406 05:53:22.127461 [4] MAX Duty = 5093%(X100), DQS PI = 6
2407 05:53:22.131006 [4] MIN Duty = 5031%(X100), DQS PI = 0
2408 05:53:22.131112 [4] AVG Duty = 5062%(X100)
2409 05:53:22.131178
2410 05:53:22.134228 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2411 05:53:22.137800
2412 05:53:22.137902 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2413 05:53:22.144365 [DutyScan_Calibration_Flow] ====Done====
2414 05:53:22.144483 ==
2415 05:53:22.147995 Dram Type= 6, Freq= 0, CH_1, rank 0
2416 05:53:22.151017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2417 05:53:22.151124 ==
2418 05:53:22.154487 [Duty_Offset_Calibration]
2419 05:53:22.154582 B0:0 B1:-1 CA:2
2420 05:53:22.154649
2421 05:53:22.157754 [DutyScan_Calibration_Flow] k_type=0
2422 05:53:22.167918
2423 05:53:22.168070 ==CLK 0==
2424 05:53:22.170820 Final CLK duty delay cell = 0
2425 05:53:22.174197 [0] MAX Duty = 5156%(X100), DQS PI = 16
2426 05:53:22.177634 [0] MIN Duty = 4938%(X100), DQS PI = 44
2427 05:53:22.177742 [0] AVG Duty = 5047%(X100)
2428 05:53:22.181050
2429 05:53:22.184158 CH1 CLK Duty spec in!! Max-Min= 218%
2430 05:53:22.187461 [DutyScan_Calibration_Flow] ====Done====
2431 05:53:22.187574
2432 05:53:22.190968 [DutyScan_Calibration_Flow] k_type=1
2433 05:53:22.207095
2434 05:53:22.207251 ==DQS 0 ==
2435 05:53:22.210396 Final DQS duty delay cell = 0
2436 05:53:22.213866 [0] MAX Duty = 5093%(X100), DQS PI = 22
2437 05:53:22.217005 [0] MIN Duty = 4969%(X100), DQS PI = 0
2438 05:53:22.217104 [0] AVG Duty = 5031%(X100)
2439 05:53:22.220700
2440 05:53:22.220791 ==DQS 1 ==
2441 05:53:22.223642 Final DQS duty delay cell = 0
2442 05:53:22.227072 [0] MAX Duty = 5156%(X100), DQS PI = 0
2443 05:53:22.230500 [0] MIN Duty = 4813%(X100), DQS PI = 36
2444 05:53:22.230595 [0] AVG Duty = 4984%(X100)
2445 05:53:22.230660
2446 05:53:22.236903 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2447 05:53:22.237012
2448 05:53:22.240576 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2449 05:53:22.244114 [DutyScan_Calibration_Flow] ====Done====
2450 05:53:22.244212
2451 05:53:22.246907 [DutyScan_Calibration_Flow] k_type=3
2452 05:53:22.263496
2453 05:53:22.263650 ==DQM 0 ==
2454 05:53:22.267216 Final DQM duty delay cell = 4
2455 05:53:22.270155 [4] MAX Duty = 5093%(X100), DQS PI = 6
2456 05:53:22.273672 [4] MIN Duty = 4938%(X100), DQS PI = 44
2457 05:53:22.273761 [4] AVG Duty = 5015%(X100)
2458 05:53:22.277011
2459 05:53:22.277094 ==DQM 1 ==
2460 05:53:22.280372 Final DQM duty delay cell = -4
2461 05:53:22.283690 [-4] MAX Duty = 5031%(X100), DQS PI = 62
2462 05:53:22.287058 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2463 05:53:22.290256 [-4] AVG Duty = 4891%(X100)
2464 05:53:22.290347
2465 05:53:22.293557 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2466 05:53:22.293645
2467 05:53:22.296872 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2468 05:53:22.300435 [DutyScan_Calibration_Flow] ====Done====
2469 05:53:22.300566
2470 05:53:22.303440 [DutyScan_Calibration_Flow] k_type=2
2471 05:53:22.320416
2472 05:53:22.320559 ==DQ 0 ==
2473 05:53:22.323871 Final DQ duty delay cell = 0
2474 05:53:22.327267 [0] MAX Duty = 5062%(X100), DQS PI = 18
2475 05:53:22.330228 [0] MIN Duty = 4938%(X100), DQS PI = 30
2476 05:53:22.330313 [0] AVG Duty = 5000%(X100)
2477 05:53:22.334274
2478 05:53:22.334357 ==DQ 1 ==
2479 05:53:22.337024 Final DQ duty delay cell = 0
2480 05:53:22.340714 [0] MAX Duty = 5031%(X100), DQS PI = 0
2481 05:53:22.343601 [0] MIN Duty = 4813%(X100), DQS PI = 34
2482 05:53:22.343688 [0] AVG Duty = 4922%(X100)
2483 05:53:22.343756
2484 05:53:22.347428 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2485 05:53:22.347516
2486 05:53:22.353561 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2487 05:53:22.357048 [DutyScan_Calibration_Flow] ====Done====
2488 05:53:22.360186 nWR fixed to 30
2489 05:53:22.360273 [ModeRegInit_LP4] CH0 RK0
2490 05:53:22.363873 [ModeRegInit_LP4] CH0 RK1
2491 05:53:22.366834 [ModeRegInit_LP4] CH1 RK0
2492 05:53:22.366925 [ModeRegInit_LP4] CH1 RK1
2493 05:53:22.370239 match AC timing 7
2494 05:53:22.373607 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2495 05:53:22.376892 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2496 05:53:22.383783 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2497 05:53:22.386934 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2498 05:53:22.393512 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2499 05:53:22.393610 ==
2500 05:53:22.396729 Dram Type= 6, Freq= 0, CH_0, rank 0
2501 05:53:22.400532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2502 05:53:22.400656 ==
2503 05:53:22.407441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2504 05:53:22.410569 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2505 05:53:22.420252 [CA 0] Center 38 (8~69) winsize 62
2506 05:53:22.423637 [CA 1] Center 38 (7~69) winsize 63
2507 05:53:22.427095 [CA 2] Center 35 (5~66) winsize 62
2508 05:53:22.430348 [CA 3] Center 35 (5~66) winsize 62
2509 05:53:22.433782 [CA 4] Center 34 (4~65) winsize 62
2510 05:53:22.436931 [CA 5] Center 33 (3~63) winsize 61
2511 05:53:22.437019
2512 05:53:22.440246 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2513 05:53:22.440331
2514 05:53:22.443466 [CATrainingPosCal] consider 1 rank data
2515 05:53:22.446708 u2DelayCellTimex100 = 270/100 ps
2516 05:53:22.450075 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2517 05:53:22.453582 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2518 05:53:22.460208 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2519 05:53:22.463442 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2520 05:53:22.466660 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2521 05:53:22.470151 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2522 05:53:22.470242
2523 05:53:22.473546 CA PerBit enable=1, Macro0, CA PI delay=33
2524 05:53:22.473634
2525 05:53:22.477003 [CBTSetCACLKResult] CA Dly = 33
2526 05:53:22.477091 CS Dly: 6 (0~37)
2527 05:53:22.479937 ==
2528 05:53:22.480025 Dram Type= 6, Freq= 0, CH_0, rank 1
2529 05:53:22.486818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 05:53:22.486919 ==
2531 05:53:22.489869 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2532 05:53:22.496910 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2533 05:53:22.505902 [CA 0] Center 39 (8~70) winsize 63
2534 05:53:22.509154 [CA 1] Center 38 (8~69) winsize 62
2535 05:53:22.512882 [CA 2] Center 35 (5~66) winsize 62
2536 05:53:22.515901 [CA 3] Center 35 (5~66) winsize 62
2537 05:53:22.519629 [CA 4] Center 34 (4~65) winsize 62
2538 05:53:22.522911 [CA 5] Center 34 (4~64) winsize 61
2539 05:53:22.523000
2540 05:53:22.526102 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2541 05:53:22.526190
2542 05:53:22.529514 [CATrainingPosCal] consider 2 rank data
2543 05:53:22.532894 u2DelayCellTimex100 = 270/100 ps
2544 05:53:22.535954 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2545 05:53:22.539238 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2546 05:53:22.545866 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2547 05:53:22.549454 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2548 05:53:22.552699 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2549 05:53:22.556188 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2550 05:53:22.556300
2551 05:53:22.559292 CA PerBit enable=1, Macro0, CA PI delay=33
2552 05:53:22.559402
2553 05:53:22.562866 [CBTSetCACLKResult] CA Dly = 33
2554 05:53:22.562983 CS Dly: 7 (0~39)
2555 05:53:22.563081
2556 05:53:22.566032 ----->DramcWriteLeveling(PI) begin...
2557 05:53:22.569348 ==
2558 05:53:22.569458 Dram Type= 6, Freq= 0, CH_0, rank 0
2559 05:53:22.575992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2560 05:53:22.576112 ==
2561 05:53:22.579802 Write leveling (Byte 0): 34 => 34
2562 05:53:22.582700 Write leveling (Byte 1): 30 => 30
2563 05:53:22.582811 DramcWriteLeveling(PI) end<-----
2564 05:53:22.586212
2565 05:53:22.586320 ==
2566 05:53:22.589398 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 05:53:22.592619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 05:53:22.592732 ==
2569 05:53:22.595898 [Gating] SW mode calibration
2570 05:53:22.602592 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2571 05:53:22.605966 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2572 05:53:22.613071 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2573 05:53:22.616029 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2574 05:53:22.619246 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2575 05:53:22.626297 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2576 05:53:22.629328 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2577 05:53:22.632913 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 05:53:22.639499 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2579 05:53:22.642798 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
2580 05:53:22.646324 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
2581 05:53:22.653127 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2582 05:53:22.656561 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 05:53:22.659636 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 05:53:22.663235 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 05:53:22.669425 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 05:53:22.672875 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
2587 05:53:22.676311 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2588 05:53:22.682858 1 1 0 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
2589 05:53:22.686226 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2590 05:53:22.689703 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 05:53:22.696122 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 05:53:22.700077 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 05:53:22.703061 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 05:53:22.709860 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 05:53:22.712908 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2596 05:53:22.716369 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2597 05:53:22.722868 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2598 05:53:22.726310 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 05:53:22.729710 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 05:53:22.736561 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 05:53:22.739723 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 05:53:22.743413 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 05:53:22.746336 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 05:53:22.753115 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 05:53:22.756845 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 05:53:22.760051 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 05:53:22.766447 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 05:53:22.769579 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 05:53:22.773119 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 05:53:22.779987 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 05:53:22.783213 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2612 05:53:22.786495 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2613 05:53:22.789918 Total UI for P1: 0, mck2ui 16
2614 05:53:22.792972 best dqsien dly found for B0: ( 1, 3, 28)
2615 05:53:22.799768 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 05:53:22.799861 Total UI for P1: 0, mck2ui 16
2617 05:53:22.803313 best dqsien dly found for B1: ( 1, 4, 0)
2618 05:53:22.809826 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2619 05:53:22.813207 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2620 05:53:22.813298
2621 05:53:22.816592 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2622 05:53:22.819724 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2623 05:53:22.823093 [Gating] SW calibration Done
2624 05:53:22.823180 ==
2625 05:53:22.826595 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 05:53:22.829776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 05:53:22.829864 ==
2628 05:53:22.829932 RX Vref Scan: 0
2629 05:53:22.833322
2630 05:53:22.833405 RX Vref 0 -> 0, step: 1
2631 05:53:22.833472
2632 05:53:22.836936 RX Delay -40 -> 252, step: 8
2633 05:53:22.839795 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2634 05:53:22.843601 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2635 05:53:22.850209 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2636 05:53:22.853232 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2637 05:53:22.856746 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2638 05:53:22.860004 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2639 05:53:22.863404 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2640 05:53:22.870042 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2641 05:53:22.873623 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2642 05:53:22.876584 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2643 05:53:22.880167 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2644 05:53:22.883502 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2645 05:53:22.890453 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2646 05:53:22.893586 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2647 05:53:22.897178 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2648 05:53:22.899952 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2649 05:53:22.900037 ==
2650 05:53:22.903679 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 05:53:22.906644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 05:53:22.910326 ==
2653 05:53:22.910413 DQS Delay:
2654 05:53:22.910479 DQS0 = 0, DQS1 = 0
2655 05:53:22.913763 DQM Delay:
2656 05:53:22.913875 DQM0 = 123, DQM1 = 110
2657 05:53:22.917149 DQ Delay:
2658 05:53:22.920185 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2659 05:53:22.923564 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2660 05:53:22.926954 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2661 05:53:22.930673 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2662 05:53:22.930790
2663 05:53:22.930942
2664 05:53:22.931057 ==
2665 05:53:22.933575 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 05:53:22.936943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 05:53:22.937047 ==
2668 05:53:22.937130
2669 05:53:22.937191
2670 05:53:22.940361 TX Vref Scan disable
2671 05:53:22.943488 == TX Byte 0 ==
2672 05:53:22.946873 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2673 05:53:22.950194 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2674 05:53:22.953747 == TX Byte 1 ==
2675 05:53:22.957221 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2676 05:53:22.960572 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2677 05:53:22.960659 ==
2678 05:53:22.963617 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 05:53:22.967178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 05:53:22.970291 ==
2681 05:53:22.980490 TX Vref=22, minBit 3, minWin=24, winSum=405
2682 05:53:22.983824 TX Vref=24, minBit 0, minWin=24, winSum=412
2683 05:53:22.986992 TX Vref=26, minBit 1, minWin=24, winSum=413
2684 05:53:22.990389 TX Vref=28, minBit 1, minWin=25, winSum=417
2685 05:53:22.993904 TX Vref=30, minBit 2, minWin=25, winSum=422
2686 05:53:22.997117 TX Vref=32, minBit 3, minWin=25, winSum=421
2687 05:53:23.004099 [TxChooseVref] Worse bit 2, Min win 25, Win sum 422, Final Vref 30
2688 05:53:23.004197
2689 05:53:23.007553 Final TX Range 1 Vref 30
2690 05:53:23.007639
2691 05:53:23.007706 ==
2692 05:53:23.010584 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 05:53:23.013714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 05:53:23.013799 ==
2695 05:53:23.013867
2696 05:53:23.017036
2697 05:53:23.017120 TX Vref Scan disable
2698 05:53:23.020374 == TX Byte 0 ==
2699 05:53:23.023962 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2700 05:53:23.027223 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2701 05:53:23.030483 == TX Byte 1 ==
2702 05:53:23.033646 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2703 05:53:23.037260 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2704 05:53:23.037344
2705 05:53:23.040527 [DATLAT]
2706 05:53:23.040613 Freq=1200, CH0 RK0
2707 05:53:23.040681
2708 05:53:23.043855 DATLAT Default: 0xd
2709 05:53:23.043941 0, 0xFFFF, sum = 0
2710 05:53:23.047132 1, 0xFFFF, sum = 0
2711 05:53:23.047221 2, 0xFFFF, sum = 0
2712 05:53:23.050384 3, 0xFFFF, sum = 0
2713 05:53:23.050471 4, 0xFFFF, sum = 0
2714 05:53:23.053884 5, 0xFFFF, sum = 0
2715 05:53:23.054023 6, 0xFFFF, sum = 0
2716 05:53:23.057391 7, 0xFFFF, sum = 0
2717 05:53:23.057478 8, 0xFFFF, sum = 0
2718 05:53:23.060409 9, 0xFFFF, sum = 0
2719 05:53:23.063689 10, 0xFFFF, sum = 0
2720 05:53:23.063792 11, 0xFFFF, sum = 0
2721 05:53:23.067396 12, 0x0, sum = 1
2722 05:53:23.067484 13, 0x0, sum = 2
2723 05:53:23.067571 14, 0x0, sum = 3
2724 05:53:23.070412 15, 0x0, sum = 4
2725 05:53:23.070498 best_step = 13
2726 05:53:23.070588
2727 05:53:23.070681 ==
2728 05:53:23.073781 Dram Type= 6, Freq= 0, CH_0, rank 0
2729 05:53:23.080825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2730 05:53:23.080921 ==
2731 05:53:23.080989 RX Vref Scan: 1
2732 05:53:23.081051
2733 05:53:23.083786 Set Vref Range= 32 -> 127
2734 05:53:23.083871
2735 05:53:23.087121 RX Vref 32 -> 127, step: 1
2736 05:53:23.087205
2737 05:53:23.090385 RX Delay -13 -> 252, step: 4
2738 05:53:23.090469
2739 05:53:23.093667 Set Vref, RX VrefLevel [Byte0]: 32
2740 05:53:23.097101 [Byte1]: 32
2741 05:53:23.097186
2742 05:53:23.100791 Set Vref, RX VrefLevel [Byte0]: 33
2743 05:53:23.103646 [Byte1]: 33
2744 05:53:23.103744
2745 05:53:23.107071 Set Vref, RX VrefLevel [Byte0]: 34
2746 05:53:23.110418 [Byte1]: 34
2747 05:53:23.114309
2748 05:53:23.114394 Set Vref, RX VrefLevel [Byte0]: 35
2749 05:53:23.117785 [Byte1]: 35
2750 05:53:23.122259
2751 05:53:23.122344 Set Vref, RX VrefLevel [Byte0]: 36
2752 05:53:23.125683 [Byte1]: 36
2753 05:53:23.130129
2754 05:53:23.130213 Set Vref, RX VrefLevel [Byte0]: 37
2755 05:53:23.133494 [Byte1]: 37
2756 05:53:23.137883
2757 05:53:23.137988 Set Vref, RX VrefLevel [Byte0]: 38
2758 05:53:23.142130 [Byte1]: 38
2759 05:53:23.145851
2760 05:53:23.145936 Set Vref, RX VrefLevel [Byte0]: 39
2761 05:53:23.149197 [Byte1]: 39
2762 05:53:23.153930
2763 05:53:23.154039 Set Vref, RX VrefLevel [Byte0]: 40
2764 05:53:23.157226 [Byte1]: 40
2765 05:53:23.161813
2766 05:53:23.161929 Set Vref, RX VrefLevel [Byte0]: 41
2767 05:53:23.164988 [Byte1]: 41
2768 05:53:23.169523
2769 05:53:23.169635 Set Vref, RX VrefLevel [Byte0]: 42
2770 05:53:23.172805 [Byte1]: 42
2771 05:53:23.177676
2772 05:53:23.177761 Set Vref, RX VrefLevel [Byte0]: 43
2773 05:53:23.180807 [Byte1]: 43
2774 05:53:23.185551
2775 05:53:23.185636 Set Vref, RX VrefLevel [Byte0]: 44
2776 05:53:23.188912 [Byte1]: 44
2777 05:53:23.193344
2778 05:53:23.193429 Set Vref, RX VrefLevel [Byte0]: 45
2779 05:53:23.196886 [Byte1]: 45
2780 05:53:23.201326
2781 05:53:23.201411 Set Vref, RX VrefLevel [Byte0]: 46
2782 05:53:23.204500 [Byte1]: 46
2783 05:53:23.209033
2784 05:53:23.209117 Set Vref, RX VrefLevel [Byte0]: 47
2785 05:53:23.212541 [Byte1]: 47
2786 05:53:23.217518
2787 05:53:23.217602 Set Vref, RX VrefLevel [Byte0]: 48
2788 05:53:23.220464 [Byte1]: 48
2789 05:53:23.224683
2790 05:53:23.224767 Set Vref, RX VrefLevel [Byte0]: 49
2791 05:53:23.227998 [Byte1]: 49
2792 05:53:23.232792
2793 05:53:23.232889 Set Vref, RX VrefLevel [Byte0]: 50
2794 05:53:23.236628 [Byte1]: 50
2795 05:53:23.240616
2796 05:53:23.240706 Set Vref, RX VrefLevel [Byte0]: 51
2797 05:53:23.243823 [Byte1]: 51
2798 05:53:23.248672
2799 05:53:23.248767 Set Vref, RX VrefLevel [Byte0]: 52
2800 05:53:23.251878 [Byte1]: 52
2801 05:53:23.256366
2802 05:53:23.256462 Set Vref, RX VrefLevel [Byte0]: 53
2803 05:53:23.259721 [Byte1]: 53
2804 05:53:23.264478
2805 05:53:23.264574 Set Vref, RX VrefLevel [Byte0]: 54
2806 05:53:23.267541 [Byte1]: 54
2807 05:53:23.272318
2808 05:53:23.272412 Set Vref, RX VrefLevel [Byte0]: 55
2809 05:53:23.275552 [Byte1]: 55
2810 05:53:23.280634
2811 05:53:23.280725 Set Vref, RX VrefLevel [Byte0]: 56
2812 05:53:23.283628 [Byte1]: 56
2813 05:53:23.287964
2814 05:53:23.288052 Set Vref, RX VrefLevel [Byte0]: 57
2815 05:53:23.291444 [Byte1]: 57
2816 05:53:23.295840
2817 05:53:23.295928 Set Vref, RX VrefLevel [Byte0]: 58
2818 05:53:23.299095 [Byte1]: 58
2819 05:53:23.304043
2820 05:53:23.304129 Set Vref, RX VrefLevel [Byte0]: 59
2821 05:53:23.307175 [Byte1]: 59
2822 05:53:23.311711
2823 05:53:23.311795 Set Vref, RX VrefLevel [Byte0]: 60
2824 05:53:23.315208 [Byte1]: 60
2825 05:53:23.319519
2826 05:53:23.319604 Set Vref, RX VrefLevel [Byte0]: 61
2827 05:53:23.323334 [Byte1]: 61
2828 05:53:23.327432
2829 05:53:23.327520 Set Vref, RX VrefLevel [Byte0]: 62
2830 05:53:23.330774 [Byte1]: 62
2831 05:53:23.335428
2832 05:53:23.335514 Set Vref, RX VrefLevel [Byte0]: 63
2833 05:53:23.339206 [Byte1]: 63
2834 05:53:23.343215
2835 05:53:23.343298 Set Vref, RX VrefLevel [Byte0]: 64
2836 05:53:23.346415 [Byte1]: 64
2837 05:53:23.351291
2838 05:53:23.351380 Set Vref, RX VrefLevel [Byte0]: 65
2839 05:53:23.354824 [Byte1]: 65
2840 05:53:23.359042
2841 05:53:23.359153 Set Vref, RX VrefLevel [Byte0]: 66
2842 05:53:23.362233 [Byte1]: 66
2843 05:53:23.366902
2844 05:53:23.366991 Set Vref, RX VrefLevel [Byte0]: 67
2845 05:53:23.370249 [Byte1]: 67
2846 05:53:23.375126
2847 05:53:23.375214 Set Vref, RX VrefLevel [Byte0]: 68
2848 05:53:23.378306 [Byte1]: 68
2849 05:53:23.382637
2850 05:53:23.382726 Set Vref, RX VrefLevel [Byte0]: 69
2851 05:53:23.385869 [Byte1]: 69
2852 05:53:23.390745
2853 05:53:23.390833 Set Vref, RX VrefLevel [Byte0]: 70
2854 05:53:23.394065 [Byte1]: 70
2855 05:53:23.398451
2856 05:53:23.398540 Set Vref, RX VrefLevel [Byte0]: 71
2857 05:53:23.401969 [Byte1]: 71
2858 05:53:23.406392
2859 05:53:23.406480 Final RX Vref Byte 0 = 58 to rank0
2860 05:53:23.409685 Final RX Vref Byte 1 = 54 to rank0
2861 05:53:23.412924 Final RX Vref Byte 0 = 58 to rank1
2862 05:53:23.416618 Final RX Vref Byte 1 = 54 to rank1==
2863 05:53:23.419560 Dram Type= 6, Freq= 0, CH_0, rank 0
2864 05:53:23.426376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2865 05:53:23.426468 ==
2866 05:53:23.426556 DQS Delay:
2867 05:53:23.426638 DQS0 = 0, DQS1 = 0
2868 05:53:23.429815 DQM Delay:
2869 05:53:23.429902 DQM0 = 122, DQM1 = 109
2870 05:53:23.432854 DQ Delay:
2871 05:53:23.436335 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2872 05:53:23.439791 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2873 05:53:23.443140 DQ8 =102, DQ9 =96, DQ10 =110, DQ11 =106
2874 05:53:23.446303 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2875 05:53:23.446390
2876 05:53:23.446476
2877 05:53:23.452961 [DQSOSCAuto] RK0, (LSB)MR18= 0x603, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 407 ps
2878 05:53:23.456325 CH0 RK0: MR19=404, MR18=603
2879 05:53:23.462880 CH0_RK0: MR19=0x404, MR18=0x603, DQSOSC=407, MR23=63, INC=39, DEC=26
2880 05:53:23.462973
2881 05:53:23.466743 ----->DramcWriteLeveling(PI) begin...
2882 05:53:23.466834 ==
2883 05:53:23.469934 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 05:53:23.472984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 05:53:23.473075 ==
2886 05:53:23.476697 Write leveling (Byte 0): 34 => 34
2887 05:53:23.479740 Write leveling (Byte 1): 30 => 30
2888 05:53:23.482996 DramcWriteLeveling(PI) end<-----
2889 05:53:23.483085
2890 05:53:23.483172 ==
2891 05:53:23.486375 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 05:53:23.492836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 05:53:23.492929 ==
2894 05:53:23.493017 [Gating] SW mode calibration
2895 05:53:23.502995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2896 05:53:23.506255 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2897 05:53:23.509609 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
2898 05:53:23.516554 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 05:53:23.519389 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 05:53:23.522783 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 05:53:23.529758 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 05:53:23.532786 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 05:53:23.536209 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 05:53:23.542711 0 15 28 | B1->B0 | 3131 2d2d | 0 0 | (0 1) (0 1)
2905 05:53:23.546092 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 05:53:23.549554 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 05:53:23.555894 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 05:53:23.559480 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 05:53:23.562833 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 05:53:23.569416 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 05:53:23.572862 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2912 05:53:23.575911 1 0 28 | B1->B0 | 3838 4242 | 0 0 | (0 0) (0 0)
2913 05:53:23.582656 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 05:53:23.585705 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 05:53:23.588985 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 05:53:23.595767 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 05:53:23.599102 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 05:53:23.602467 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 05:53:23.609031 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 05:53:23.612374 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2921 05:53:23.616012 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2922 05:53:23.622406 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 05:53:23.625731 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 05:53:23.628938 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 05:53:23.636069 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 05:53:23.638914 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 05:53:23.642191 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 05:53:23.645847 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 05:53:23.652672 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 05:53:23.655446 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 05:53:23.659140 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 05:53:23.665489 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 05:53:23.668949 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 05:53:23.672302 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 05:53:23.679194 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 05:53:23.682216 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2937 05:53:23.685680 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2938 05:53:23.692535 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 05:53:23.692659 Total UI for P1: 0, mck2ui 16
2940 05:53:23.699431 best dqsien dly found for B0: ( 1, 3, 30)
2941 05:53:23.699525 Total UI for P1: 0, mck2ui 16
2942 05:53:23.702508 best dqsien dly found for B1: ( 1, 3, 30)
2943 05:53:23.709018 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2944 05:53:23.712246 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2945 05:53:23.712334
2946 05:53:23.715633 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2947 05:53:23.719345 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2948 05:53:23.722561 [Gating] SW calibration Done
2949 05:53:23.722646 ==
2950 05:53:23.725920 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 05:53:23.729424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 05:53:23.729511 ==
2953 05:53:23.732683 RX Vref Scan: 0
2954 05:53:23.732768
2955 05:53:23.732834 RX Vref 0 -> 0, step: 1
2956 05:53:23.732895
2957 05:53:23.735849 RX Delay -40 -> 252, step: 8
2958 05:53:23.739575 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2959 05:53:23.746188 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2960 05:53:23.749149 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2961 05:53:23.753063 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2962 05:53:23.755817 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2963 05:53:23.759068 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2964 05:53:23.762992 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2965 05:53:23.769273 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2966 05:53:23.772380 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2967 05:53:23.775918 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2968 05:53:23.779116 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2969 05:53:23.782563 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2970 05:53:23.789378 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2971 05:53:23.792744 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2972 05:53:23.795854 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2973 05:53:23.799015 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2974 05:53:23.799102 ==
2975 05:53:23.802573 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 05:53:23.809099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 05:53:23.809222 ==
2978 05:53:23.809292 DQS Delay:
2979 05:53:23.809354 DQS0 = 0, DQS1 = 0
2980 05:53:23.812525 DQM Delay:
2981 05:53:23.812611 DQM0 = 120, DQM1 = 109
2982 05:53:23.815971 DQ Delay:
2983 05:53:23.819209 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2984 05:53:23.822541 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2985 05:53:23.826062 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2986 05:53:23.829193 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2987 05:53:23.829279
2988 05:53:23.829346
2989 05:53:23.829406 ==
2990 05:53:23.832967 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 05:53:23.835807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 05:53:23.835892 ==
2993 05:53:23.835958
2994 05:53:23.839211
2995 05:53:23.839295 TX Vref Scan disable
2996 05:53:23.842729 == TX Byte 0 ==
2997 05:53:23.845622 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2998 05:53:23.849061 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2999 05:53:23.852601 == TX Byte 1 ==
3000 05:53:23.855942 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3001 05:53:23.859323 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3002 05:53:23.859409 ==
3003 05:53:23.862701 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 05:53:23.869489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 05:53:23.869578 ==
3006 05:53:23.880111 TX Vref=22, minBit 3, minWin=24, winSum=412
3007 05:53:23.883231 TX Vref=24, minBit 0, minWin=24, winSum=416
3008 05:53:23.886645 TX Vref=26, minBit 1, minWin=24, winSum=418
3009 05:53:23.889986 TX Vref=28, minBit 1, minWin=24, winSum=420
3010 05:53:23.892993 TX Vref=30, minBit 3, minWin=25, winSum=425
3011 05:53:23.899882 TX Vref=32, minBit 0, minWin=25, winSum=420
3012 05:53:23.903404 [TxChooseVref] Worse bit 3, Min win 25, Win sum 425, Final Vref 30
3013 05:53:23.903496
3014 05:53:23.906811 Final TX Range 1 Vref 30
3015 05:53:23.906911
3016 05:53:23.906977 ==
3017 05:53:23.909698 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 05:53:23.913182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 05:53:23.913269 ==
3020 05:53:23.916141
3021 05:53:23.916225
3022 05:53:23.916291 TX Vref Scan disable
3023 05:53:23.919659 == TX Byte 0 ==
3024 05:53:23.923150 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3025 05:53:23.926543 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3026 05:53:23.929842 == TX Byte 1 ==
3027 05:53:23.933221 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3028 05:53:23.936406 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3029 05:53:23.936493
3030 05:53:23.939864 [DATLAT]
3031 05:53:23.939947 Freq=1200, CH0 RK1
3032 05:53:23.940015
3033 05:53:23.943090 DATLAT Default: 0xd
3034 05:53:23.943174 0, 0xFFFF, sum = 0
3035 05:53:23.946331 1, 0xFFFF, sum = 0
3036 05:53:23.946416 2, 0xFFFF, sum = 0
3037 05:53:23.949853 3, 0xFFFF, sum = 0
3038 05:53:23.950002 4, 0xFFFF, sum = 0
3039 05:53:23.953048 5, 0xFFFF, sum = 0
3040 05:53:23.953202 6, 0xFFFF, sum = 0
3041 05:53:23.956435 7, 0xFFFF, sum = 0
3042 05:53:23.959753 8, 0xFFFF, sum = 0
3043 05:53:23.959844 9, 0xFFFF, sum = 0
3044 05:53:23.963548 10, 0xFFFF, sum = 0
3045 05:53:23.963638 11, 0xFFFF, sum = 0
3046 05:53:23.966510 12, 0x0, sum = 1
3047 05:53:23.966609 13, 0x0, sum = 2
3048 05:53:23.969660 14, 0x0, sum = 3
3049 05:53:23.969764 15, 0x0, sum = 4
3050 05:53:23.969835 best_step = 13
3051 05:53:23.969928
3052 05:53:23.973075 ==
3053 05:53:23.973161 Dram Type= 6, Freq= 0, CH_0, rank 1
3054 05:53:23.980185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 05:53:23.980277 ==
3056 05:53:23.980344 RX Vref Scan: 0
3057 05:53:23.980407
3058 05:53:23.983306 RX Vref 0 -> 0, step: 1
3059 05:53:23.983390
3060 05:53:23.986296 RX Delay -21 -> 252, step: 4
3061 05:53:23.990190 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3062 05:53:23.996308 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3063 05:53:23.999903 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3064 05:53:24.002989 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3065 05:53:24.006295 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3066 05:53:24.009640 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3067 05:53:24.013060 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3068 05:53:24.019912 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3069 05:53:24.023541 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3070 05:53:24.026610 iDelay=195, Bit 9, Center 98 (35 ~ 162) 128
3071 05:53:24.029841 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3072 05:53:24.033127 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3073 05:53:24.039639 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3074 05:53:24.042946 iDelay=195, Bit 13, Center 112 (51 ~ 174) 124
3075 05:53:24.046517 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3076 05:53:24.049761 iDelay=195, Bit 15, Center 116 (55 ~ 178) 124
3077 05:53:24.049853 ==
3078 05:53:24.052943 Dram Type= 6, Freq= 0, CH_0, rank 1
3079 05:53:24.060054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 05:53:24.060150 ==
3081 05:53:24.060219 DQS Delay:
3082 05:53:24.063034 DQS0 = 0, DQS1 = 0
3083 05:53:24.063120 DQM Delay:
3084 05:53:24.063187 DQM0 = 119, DQM1 = 108
3085 05:53:24.066472 DQ Delay:
3086 05:53:24.069987 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3087 05:53:24.073309 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3088 05:53:24.076333 DQ8 =98, DQ9 =98, DQ10 =108, DQ11 =104
3089 05:53:24.079778 DQ12 =114, DQ13 =112, DQ14 =120, DQ15 =116
3090 05:53:24.079866
3091 05:53:24.079934
3092 05:53:24.086614 [DQSOSCAuto] RK1, (LSB)MR18= 0xef5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3093 05:53:24.090354 CH0 RK1: MR19=403, MR18=EF5
3094 05:53:24.096587 CH0_RK1: MR19=0x403, MR18=0xEF5, DQSOSC=404, MR23=63, INC=40, DEC=26
3095 05:53:24.100176 [RxdqsGatingPostProcess] freq 1200
3096 05:53:24.106640 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3097 05:53:24.109781 best DQS0 dly(2T, 0.5T) = (0, 11)
3098 05:53:24.109872 best DQS1 dly(2T, 0.5T) = (0, 12)
3099 05:53:24.113156 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3100 05:53:24.116674 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3101 05:53:24.119793 best DQS0 dly(2T, 0.5T) = (0, 11)
3102 05:53:24.123087 best DQS1 dly(2T, 0.5T) = (0, 11)
3103 05:53:24.126546 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3104 05:53:24.129807 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3105 05:53:24.133397 Pre-setting of DQS Precalculation
3106 05:53:24.136584 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3107 05:53:24.140178 ==
3108 05:53:24.143124 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 05:53:24.146909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 05:53:24.147001 ==
3111 05:53:24.150111 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3112 05:53:24.156635 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3113 05:53:24.165660 [CA 0] Center 37 (7~68) winsize 62
3114 05:53:24.169188 [CA 1] Center 37 (7~68) winsize 62
3115 05:53:24.172374 [CA 2] Center 35 (5~65) winsize 61
3116 05:53:24.175680 [CA 3] Center 34 (4~65) winsize 62
3117 05:53:24.179302 [CA 4] Center 34 (4~65) winsize 62
3118 05:53:24.182454 [CA 5] Center 33 (3~64) winsize 62
3119 05:53:24.182540
3120 05:53:24.185651 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3121 05:53:24.185737
3122 05:53:24.189192 [CATrainingPosCal] consider 1 rank data
3123 05:53:24.192356 u2DelayCellTimex100 = 270/100 ps
3124 05:53:24.195875 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3125 05:53:24.199199 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3126 05:53:24.205912 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3127 05:53:24.209108 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3128 05:53:24.212577 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3129 05:53:24.215824 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3130 05:53:24.215911
3131 05:53:24.219571 CA PerBit enable=1, Macro0, CA PI delay=33
3132 05:53:24.219657
3133 05:53:24.222929 [CBTSetCACLKResult] CA Dly = 33
3134 05:53:24.223015 CS Dly: 5 (0~36)
3135 05:53:24.223089 ==
3136 05:53:24.225902 Dram Type= 6, Freq= 0, CH_1, rank 1
3137 05:53:24.232707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 05:53:24.232805 ==
3139 05:53:24.236076 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3140 05:53:24.242648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3141 05:53:24.251380 [CA 0] Center 38 (8~68) winsize 61
3142 05:53:24.254727 [CA 1] Center 38 (7~69) winsize 63
3143 05:53:24.257893 [CA 2] Center 35 (5~66) winsize 62
3144 05:53:24.261660 [CA 3] Center 35 (5~65) winsize 61
3145 05:53:24.264832 [CA 4] Center 34 (4~64) winsize 61
3146 05:53:24.267925 [CA 5] Center 34 (4~64) winsize 61
3147 05:53:24.268014
3148 05:53:24.271302 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3149 05:53:24.271389
3150 05:53:24.274866 [CATrainingPosCal] consider 2 rank data
3151 05:53:24.278203 u2DelayCellTimex100 = 270/100 ps
3152 05:53:24.281279 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3153 05:53:24.284627 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3154 05:53:24.291461 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3155 05:53:24.295017 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3156 05:53:24.298124 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3157 05:53:24.301654 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3158 05:53:24.301741
3159 05:53:24.304952 CA PerBit enable=1, Macro0, CA PI delay=34
3160 05:53:24.305038
3161 05:53:24.308200 [CBTSetCACLKResult] CA Dly = 34
3162 05:53:24.308290 CS Dly: 6 (0~39)
3163 05:53:24.308358
3164 05:53:24.311628 ----->DramcWriteLeveling(PI) begin...
3165 05:53:24.311715 ==
3166 05:53:24.315017 Dram Type= 6, Freq= 0, CH_1, rank 0
3167 05:53:24.321638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3168 05:53:24.321730 ==
3169 05:53:24.325205 Write leveling (Byte 0): 26 => 26
3170 05:53:24.328499 Write leveling (Byte 1): 28 => 28
3171 05:53:24.328587 DramcWriteLeveling(PI) end<-----
3172 05:53:24.331506
3173 05:53:24.331606 ==
3174 05:53:24.334914 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 05:53:24.338092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 05:53:24.338180 ==
3177 05:53:24.341396 [Gating] SW mode calibration
3178 05:53:24.347761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3179 05:53:24.351184 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3180 05:53:24.357758 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 05:53:24.361641 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 05:53:24.364548 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 05:53:24.371519 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 05:53:24.374728 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 05:53:24.377854 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3186 05:53:24.384702 0 15 24 | B1->B0 | 2f2f 2a2a | 1 0 | (1 0) (0 0)
3187 05:53:24.388077 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 05:53:24.391232 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 05:53:24.398502 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 05:53:24.401408 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 05:53:24.404570 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 05:53:24.411258 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 05:53:24.414497 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 05:53:24.418031 1 0 24 | B1->B0 | 4241 4545 | 1 0 | (0 0) (0 0)
3195 05:53:24.424356 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 05:53:24.427999 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 05:53:24.431145 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 05:53:24.437929 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 05:53:24.441429 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 05:53:24.444423 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 05:53:24.451330 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 05:53:24.454430 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3203 05:53:24.457741 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 05:53:24.461056 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 05:53:24.468037 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 05:53:24.471036 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 05:53:24.474705 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 05:53:24.481192 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 05:53:24.484755 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 05:53:24.487877 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 05:53:24.494977 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 05:53:24.497884 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 05:53:24.501107 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 05:53:24.508517 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 05:53:24.511949 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 05:53:24.514682 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 05:53:24.521316 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3218 05:53:24.524817 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3219 05:53:24.527765 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 05:53:24.531264 Total UI for P1: 0, mck2ui 16
3221 05:53:24.534727 best dqsien dly found for B0: ( 1, 3, 22)
3222 05:53:24.537933 Total UI for P1: 0, mck2ui 16
3223 05:53:24.541547 best dqsien dly found for B1: ( 1, 3, 24)
3224 05:53:24.544472 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3225 05:53:24.548182 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3226 05:53:24.548270
3227 05:53:24.551510 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3228 05:53:24.557849 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3229 05:53:24.558000 [Gating] SW calibration Done
3230 05:53:24.558070 ==
3231 05:53:24.561577 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 05:53:24.568363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 05:53:24.568470 ==
3234 05:53:24.568538 RX Vref Scan: 0
3235 05:53:24.568601
3236 05:53:24.571115 RX Vref 0 -> 0, step: 1
3237 05:53:24.571199
3238 05:53:24.574599 RX Delay -40 -> 252, step: 8
3239 05:53:24.577869 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3240 05:53:24.581544 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3241 05:53:24.584562 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3242 05:53:24.591059 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3243 05:53:24.594389 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3244 05:53:24.598062 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3245 05:53:24.601642 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3246 05:53:24.604755 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3247 05:53:24.607978 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3248 05:53:24.615063 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3249 05:53:24.617956 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3250 05:53:24.621003 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3251 05:53:24.624476 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3252 05:53:24.627784 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3253 05:53:24.634583 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3254 05:53:24.637824 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3255 05:53:24.637913 ==
3256 05:53:24.641291 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 05:53:24.644647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 05:53:24.644736 ==
3259 05:53:24.647827 DQS Delay:
3260 05:53:24.647969 DQS0 = 0, DQS1 = 0
3261 05:53:24.648049 DQM Delay:
3262 05:53:24.651193 DQM0 = 120, DQM1 = 112
3263 05:53:24.651284 DQ Delay:
3264 05:53:24.654571 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3265 05:53:24.658248 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =123
3266 05:53:24.661442 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3267 05:53:24.664714 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3268 05:53:24.668052
3269 05:53:24.668139
3270 05:53:24.668205 ==
3271 05:53:24.671377 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 05:53:24.674700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 05:53:24.674788 ==
3274 05:53:24.674854
3275 05:53:24.674915
3276 05:53:24.677912 TX Vref Scan disable
3277 05:53:24.678030 == TX Byte 0 ==
3278 05:53:24.684716 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3279 05:53:24.687827 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3280 05:53:24.687913 == TX Byte 1 ==
3281 05:53:24.694817 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3282 05:53:24.698293 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3283 05:53:24.698382 ==
3284 05:53:24.701477 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 05:53:24.704535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 05:53:24.704619 ==
3287 05:53:24.716990 TX Vref=22, minBit 10, minWin=24, winSum=406
3288 05:53:24.720071 TX Vref=24, minBit 10, minWin=24, winSum=410
3289 05:53:24.723461 TX Vref=26, minBit 8, minWin=25, winSum=415
3290 05:53:24.726747 TX Vref=28, minBit 10, minWin=25, winSum=420
3291 05:53:24.730432 TX Vref=30, minBit 10, minWin=25, winSum=421
3292 05:53:24.736860 TX Vref=32, minBit 9, minWin=25, winSum=420
3293 05:53:24.740126 [TxChooseVref] Worse bit 10, Min win 25, Win sum 421, Final Vref 30
3294 05:53:24.740213
3295 05:53:24.743611 Final TX Range 1 Vref 30
3296 05:53:24.743698
3297 05:53:24.743763 ==
3298 05:53:24.747301 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 05:53:24.750700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 05:53:24.753568 ==
3301 05:53:24.753687
3302 05:53:24.753785
3303 05:53:24.753896 TX Vref Scan disable
3304 05:53:24.756800 == TX Byte 0 ==
3305 05:53:24.760178 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3306 05:53:24.763792 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3307 05:53:24.767070 == TX Byte 1 ==
3308 05:53:24.770188 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3309 05:53:24.773981 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3310 05:53:24.774095
3311 05:53:24.777239 [DATLAT]
3312 05:53:24.777327 Freq=1200, CH1 RK0
3313 05:53:24.777433
3314 05:53:24.780724 DATLAT Default: 0xd
3315 05:53:24.780848 0, 0xFFFF, sum = 0
3316 05:53:24.783596 1, 0xFFFF, sum = 0
3317 05:53:24.783713 2, 0xFFFF, sum = 0
3318 05:53:24.787064 3, 0xFFFF, sum = 0
3319 05:53:24.787176 4, 0xFFFF, sum = 0
3320 05:53:24.790397 5, 0xFFFF, sum = 0
3321 05:53:24.793862 6, 0xFFFF, sum = 0
3322 05:53:24.793977 7, 0xFFFF, sum = 0
3323 05:53:24.797632 8, 0xFFFF, sum = 0
3324 05:53:24.797722 9, 0xFFFF, sum = 0
3325 05:53:24.800736 10, 0xFFFF, sum = 0
3326 05:53:24.800825 11, 0xFFFF, sum = 0
3327 05:53:24.804006 12, 0x0, sum = 1
3328 05:53:24.804096 13, 0x0, sum = 2
3329 05:53:24.806993 14, 0x0, sum = 3
3330 05:53:24.807086 15, 0x0, sum = 4
3331 05:53:24.807174 best_step = 13
3332 05:53:24.807254
3333 05:53:24.810316 ==
3334 05:53:24.813901 Dram Type= 6, Freq= 0, CH_1, rank 0
3335 05:53:24.817186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3336 05:53:24.817278 ==
3337 05:53:24.817380 RX Vref Scan: 1
3338 05:53:24.817482
3339 05:53:24.820288 Set Vref Range= 32 -> 127
3340 05:53:24.820376
3341 05:53:24.823727 RX Vref 32 -> 127, step: 1
3342 05:53:24.823815
3343 05:53:24.827065 RX Delay -13 -> 252, step: 4
3344 05:53:24.827153
3345 05:53:24.830415 Set Vref, RX VrefLevel [Byte0]: 32
3346 05:53:24.833838 [Byte1]: 32
3347 05:53:24.833969
3348 05:53:24.837128 Set Vref, RX VrefLevel [Byte0]: 33
3349 05:53:24.840333 [Byte1]: 33
3350 05:53:24.840420
3351 05:53:24.843582 Set Vref, RX VrefLevel [Byte0]: 34
3352 05:53:24.847391 [Byte1]: 34
3353 05:53:24.851171
3354 05:53:24.851268 Set Vref, RX VrefLevel [Byte0]: 35
3355 05:53:24.854671 [Byte1]: 35
3356 05:53:24.859468
3357 05:53:24.859553 Set Vref, RX VrefLevel [Byte0]: 36
3358 05:53:24.862426 [Byte1]: 36
3359 05:53:24.867128
3360 05:53:24.867223 Set Vref, RX VrefLevel [Byte0]: 37
3361 05:53:24.870287 [Byte1]: 37
3362 05:53:24.875156
3363 05:53:24.875249 Set Vref, RX VrefLevel [Byte0]: 38
3364 05:53:24.878192 [Byte1]: 38
3365 05:53:24.882922
3366 05:53:24.883008 Set Vref, RX VrefLevel [Byte0]: 39
3367 05:53:24.886057 [Byte1]: 39
3368 05:53:24.890743
3369 05:53:24.890826 Set Vref, RX VrefLevel [Byte0]: 40
3370 05:53:24.894498 [Byte1]: 40
3371 05:53:24.898406
3372 05:53:24.898504 Set Vref, RX VrefLevel [Byte0]: 41
3373 05:53:24.901902 [Byte1]: 41
3374 05:53:24.906634
3375 05:53:24.906709 Set Vref, RX VrefLevel [Byte0]: 42
3376 05:53:24.909819 [Byte1]: 42
3377 05:53:24.914627
3378 05:53:24.914710 Set Vref, RX VrefLevel [Byte0]: 43
3379 05:53:24.917904 [Byte1]: 43
3380 05:53:24.922738
3381 05:53:24.922820 Set Vref, RX VrefLevel [Byte0]: 44
3382 05:53:24.925790 [Byte1]: 44
3383 05:53:24.930198
3384 05:53:24.930295 Set Vref, RX VrefLevel [Byte0]: 45
3385 05:53:24.933489 [Byte1]: 45
3386 05:53:24.938112
3387 05:53:24.938195 Set Vref, RX VrefLevel [Byte0]: 46
3388 05:53:24.941471 [Byte1]: 46
3389 05:53:24.946025
3390 05:53:24.946108 Set Vref, RX VrefLevel [Byte0]: 47
3391 05:53:24.949506 [Byte1]: 47
3392 05:53:24.954088
3393 05:53:24.954170 Set Vref, RX VrefLevel [Byte0]: 48
3394 05:53:24.957099 [Byte1]: 48
3395 05:53:24.961787
3396 05:53:24.961897 Set Vref, RX VrefLevel [Byte0]: 49
3397 05:53:24.964760 [Byte1]: 49
3398 05:53:24.969476
3399 05:53:24.969561 Set Vref, RX VrefLevel [Byte0]: 50
3400 05:53:24.972792 [Byte1]: 50
3401 05:53:24.977307
3402 05:53:24.977398 Set Vref, RX VrefLevel [Byte0]: 51
3403 05:53:24.980837 [Byte1]: 51
3404 05:53:24.985238
3405 05:53:24.985327 Set Vref, RX VrefLevel [Byte0]: 52
3406 05:53:24.988724 [Byte1]: 52
3407 05:53:24.993099
3408 05:53:24.993227 Set Vref, RX VrefLevel [Byte0]: 53
3409 05:53:24.996511 [Byte1]: 53
3410 05:53:25.001442
3411 05:53:25.001520 Set Vref, RX VrefLevel [Byte0]: 54
3412 05:53:25.004163 [Byte1]: 54
3413 05:53:25.009000
3414 05:53:25.009098 Set Vref, RX VrefLevel [Byte0]: 55
3415 05:53:25.012213 [Byte1]: 55
3416 05:53:25.016693
3417 05:53:25.016766 Set Vref, RX VrefLevel [Byte0]: 56
3418 05:53:25.020192 [Byte1]: 56
3419 05:53:25.024950
3420 05:53:25.025032 Set Vref, RX VrefLevel [Byte0]: 57
3421 05:53:25.028249 [Byte1]: 57
3422 05:53:25.032471
3423 05:53:25.032554 Set Vref, RX VrefLevel [Byte0]: 58
3424 05:53:25.035884 [Byte1]: 58
3425 05:53:25.040909
3426 05:53:25.040990 Set Vref, RX VrefLevel [Byte0]: 59
3427 05:53:25.043892 [Byte1]: 59
3428 05:53:25.048666
3429 05:53:25.048747 Set Vref, RX VrefLevel [Byte0]: 60
3430 05:53:25.051518 [Byte1]: 60
3431 05:53:25.056288
3432 05:53:25.056370 Set Vref, RX VrefLevel [Byte0]: 61
3433 05:53:25.059706 [Byte1]: 61
3434 05:53:25.064456
3435 05:53:25.064538 Set Vref, RX VrefLevel [Byte0]: 62
3436 05:53:25.067609 [Byte1]: 62
3437 05:53:25.072502
3438 05:53:25.072584 Set Vref, RX VrefLevel [Byte0]: 63
3439 05:53:25.075540 [Byte1]: 63
3440 05:53:25.079993
3441 05:53:25.080076 Set Vref, RX VrefLevel [Byte0]: 64
3442 05:53:25.083479 [Byte1]: 64
3443 05:53:25.087979
3444 05:53:25.088160 Set Vref, RX VrefLevel [Byte0]: 65
3445 05:53:25.091190 [Byte1]: 65
3446 05:53:25.095752
3447 05:53:25.095901 Set Vref, RX VrefLevel [Byte0]: 66
3448 05:53:25.099067 [Byte1]: 66
3449 05:53:25.103834
3450 05:53:25.103972 Set Vref, RX VrefLevel [Byte0]: 67
3451 05:53:25.106860 [Byte1]: 67
3452 05:53:25.111504
3453 05:53:25.111611 Final RX Vref Byte 0 = 52 to rank0
3454 05:53:25.115115 Final RX Vref Byte 1 = 48 to rank0
3455 05:53:25.118255 Final RX Vref Byte 0 = 52 to rank1
3456 05:53:25.121374 Final RX Vref Byte 1 = 48 to rank1==
3457 05:53:25.125608 Dram Type= 6, Freq= 0, CH_1, rank 0
3458 05:53:25.131562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3459 05:53:25.131699 ==
3460 05:53:25.131792 DQS Delay:
3461 05:53:25.131873 DQS0 = 0, DQS1 = 0
3462 05:53:25.134926 DQM Delay:
3463 05:53:25.135012 DQM0 = 119, DQM1 = 111
3464 05:53:25.138331 DQ Delay:
3465 05:53:25.141797 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3466 05:53:25.144897 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =116
3467 05:53:25.148552 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =104
3468 05:53:25.151695 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =116
3469 05:53:25.151785
3470 05:53:25.151871
3471 05:53:25.158433 [DQSOSCAuto] RK0, (LSB)MR18= 0xff13, (MSB)MR19= 0x304, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3472 05:53:25.161463 CH1 RK0: MR19=304, MR18=FF13
3473 05:53:25.168062 CH1_RK0: MR19=0x304, MR18=0xFF13, DQSOSC=402, MR23=63, INC=40, DEC=27
3474 05:53:25.168154
3475 05:53:25.171684 ----->DramcWriteLeveling(PI) begin...
3476 05:53:25.171772 ==
3477 05:53:25.175139 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 05:53:25.178317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 05:53:25.181721 ==
3480 05:53:25.181808 Write leveling (Byte 0): 25 => 25
3481 05:53:25.184846 Write leveling (Byte 1): 29 => 29
3482 05:53:25.188611 DramcWriteLeveling(PI) end<-----
3483 05:53:25.188698
3484 05:53:25.188783 ==
3485 05:53:25.191515 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 05:53:25.198204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 05:53:25.198323 ==
3488 05:53:25.198424 [Gating] SW mode calibration
3489 05:53:25.208477 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3490 05:53:25.211722 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3491 05:53:25.215053 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 05:53:25.221669 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 05:53:25.225271 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 05:53:25.228394 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 05:53:25.235159 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 05:53:25.238788 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 05:53:25.241613 0 15 24 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 1)
3498 05:53:25.248403 0 15 28 | B1->B0 | 2323 2d2d | 0 1 | (1 0) (1 0)
3499 05:53:25.252059 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 05:53:25.255154 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 05:53:25.262202 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 05:53:25.265052 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 05:53:25.268380 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 05:53:25.275092 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3505 05:53:25.278112 1 0 24 | B1->B0 | 3333 2525 | 1 0 | (0 0) (0 0)
3506 05:53:25.281757 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3507 05:53:25.288730 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 05:53:25.291771 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 05:53:25.294892 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 05:53:25.298723 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 05:53:25.305326 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 05:53:25.308419 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 05:53:25.315055 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3514 05:53:25.317976 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3515 05:53:25.321569 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 05:53:25.324840 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 05:53:25.331298 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 05:53:25.334763 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 05:53:25.338037 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 05:53:25.344734 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 05:53:25.347934 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 05:53:25.351749 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 05:53:25.358356 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 05:53:25.361365 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 05:53:25.364763 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 05:53:25.371128 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 05:53:25.374806 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 05:53:25.378158 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 05:53:25.384511 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3530 05:53:25.387798 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3531 05:53:25.391612 Total UI for P1: 0, mck2ui 16
3532 05:53:25.394560 best dqsien dly found for B1: ( 1, 3, 24)
3533 05:53:25.397849 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 05:53:25.401014 Total UI for P1: 0, mck2ui 16
3535 05:53:25.404386 best dqsien dly found for B0: ( 1, 3, 26)
3536 05:53:25.408065 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3537 05:53:25.411090 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3538 05:53:25.411247
3539 05:53:25.418039 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3540 05:53:25.421326 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3541 05:53:25.421561 [Gating] SW calibration Done
3542 05:53:25.424168 ==
3543 05:53:25.424417 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 05:53:25.430925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 05:53:25.431187 ==
3546 05:53:25.431312 RX Vref Scan: 0
3547 05:53:25.431421
3548 05:53:25.434376 RX Vref 0 -> 0, step: 1
3549 05:53:25.434542
3550 05:53:25.437661 RX Delay -40 -> 252, step: 8
3551 05:53:25.440868 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3552 05:53:25.444134 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3553 05:53:25.448040 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3554 05:53:25.454479 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3555 05:53:25.457546 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3556 05:53:25.460943 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3557 05:53:25.464371 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3558 05:53:25.467665 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3559 05:53:25.474078 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3560 05:53:25.477317 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3561 05:53:25.480857 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3562 05:53:25.483791 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3563 05:53:25.487548 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3564 05:53:25.494097 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3565 05:53:25.497465 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3566 05:53:25.500708 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3567 05:53:25.500815 ==
3568 05:53:25.503762 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 05:53:25.507158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 05:53:25.510515 ==
3571 05:53:25.510633 DQS Delay:
3572 05:53:25.510712 DQS0 = 0, DQS1 = 0
3573 05:53:25.514056 DQM Delay:
3574 05:53:25.514163 DQM0 = 120, DQM1 = 112
3575 05:53:25.516955 DQ Delay:
3576 05:53:25.520427 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =123
3577 05:53:25.523770 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3578 05:53:25.527114 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =103
3579 05:53:25.530255 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3580 05:53:25.530341
3581 05:53:25.530409
3582 05:53:25.530474 ==
3583 05:53:25.533862 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 05:53:25.536973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 05:53:25.537059 ==
3586 05:53:25.537126
3587 05:53:25.537188
3588 05:53:25.540704 TX Vref Scan disable
3589 05:53:25.544042 == TX Byte 0 ==
3590 05:53:25.546818 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3591 05:53:25.550159 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3592 05:53:25.553693 == TX Byte 1 ==
3593 05:53:25.556856 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3594 05:53:25.560451 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3595 05:53:25.560528 ==
3596 05:53:25.563676 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 05:53:25.569910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 05:53:25.570037 ==
3599 05:53:25.580760 TX Vref=22, minBit 1, minWin=25, winSum=418
3600 05:53:25.583904 TX Vref=24, minBit 1, minWin=25, winSum=419
3601 05:53:25.587386 TX Vref=26, minBit 1, minWin=26, winSum=426
3602 05:53:25.590936 TX Vref=28, minBit 0, minWin=26, winSum=428
3603 05:53:25.594209 TX Vref=30, minBit 9, minWin=25, winSum=428
3604 05:53:25.597413 TX Vref=32, minBit 9, minWin=25, winSum=425
3605 05:53:25.604206 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
3606 05:53:25.604345
3607 05:53:25.607272 Final TX Range 1 Vref 28
3608 05:53:25.607363
3609 05:53:25.607428 ==
3610 05:53:25.610598 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 05:53:25.613889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 05:53:25.614014 ==
3613 05:53:25.614082
3614 05:53:25.617377
3615 05:53:25.617460 TX Vref Scan disable
3616 05:53:25.620833 == TX Byte 0 ==
3617 05:53:25.624099 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3618 05:53:25.627196 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3619 05:53:25.630329 == TX Byte 1 ==
3620 05:53:25.633867 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3621 05:53:25.640380 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3622 05:53:25.640490
3623 05:53:25.640586 [DATLAT]
3624 05:53:25.640676 Freq=1200, CH1 RK1
3625 05:53:25.640768
3626 05:53:25.643938 DATLAT Default: 0xd
3627 05:53:25.644048 0, 0xFFFF, sum = 0
3628 05:53:25.647246 1, 0xFFFF, sum = 0
3629 05:53:25.650436 2, 0xFFFF, sum = 0
3630 05:53:25.650539 3, 0xFFFF, sum = 0
3631 05:53:25.653710 4, 0xFFFF, sum = 0
3632 05:53:25.653818 5, 0xFFFF, sum = 0
3633 05:53:25.656848 6, 0xFFFF, sum = 0
3634 05:53:25.656950 7, 0xFFFF, sum = 0
3635 05:53:25.660205 8, 0xFFFF, sum = 0
3636 05:53:25.660323 9, 0xFFFF, sum = 0
3637 05:53:25.663525 10, 0xFFFF, sum = 0
3638 05:53:25.663631 11, 0xFFFF, sum = 0
3639 05:53:25.666874 12, 0x0, sum = 1
3640 05:53:25.666978 13, 0x0, sum = 2
3641 05:53:25.670343 14, 0x0, sum = 3
3642 05:53:25.670444 15, 0x0, sum = 4
3643 05:53:25.670536 best_step = 13
3644 05:53:25.673498
3645 05:53:25.673594 ==
3646 05:53:25.677132 Dram Type= 6, Freq= 0, CH_1, rank 1
3647 05:53:25.680241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3648 05:53:25.680325 ==
3649 05:53:25.680391 RX Vref Scan: 0
3650 05:53:25.680458
3651 05:53:25.683734 RX Vref 0 -> 0, step: 1
3652 05:53:25.683817
3653 05:53:25.687086 RX Delay -13 -> 252, step: 4
3654 05:53:25.690356 iDelay=191, Bit 0, Center 122 (63 ~ 182) 120
3655 05:53:25.696961 iDelay=191, Bit 1, Center 114 (55 ~ 174) 120
3656 05:53:25.700390 iDelay=191, Bit 2, Center 108 (51 ~ 166) 116
3657 05:53:25.703565 iDelay=191, Bit 3, Center 118 (59 ~ 178) 120
3658 05:53:25.707289 iDelay=191, Bit 4, Center 120 (59 ~ 182) 124
3659 05:53:25.710346 iDelay=191, Bit 5, Center 128 (67 ~ 190) 124
3660 05:53:25.717161 iDelay=191, Bit 6, Center 124 (63 ~ 186) 124
3661 05:53:25.720368 iDelay=191, Bit 7, Center 116 (55 ~ 178) 124
3662 05:53:25.723635 iDelay=191, Bit 8, Center 98 (35 ~ 162) 128
3663 05:53:25.726749 iDelay=191, Bit 9, Center 100 (39 ~ 162) 124
3664 05:53:25.730198 iDelay=191, Bit 10, Center 112 (47 ~ 178) 132
3665 05:53:25.736711 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3666 05:53:25.740392 iDelay=191, Bit 12, Center 122 (59 ~ 186) 128
3667 05:53:25.743334 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3668 05:53:25.746704 iDelay=191, Bit 14, Center 122 (59 ~ 186) 128
3669 05:53:25.750066 iDelay=191, Bit 15, Center 122 (59 ~ 186) 128
3670 05:53:25.753599 ==
3671 05:53:25.753687 Dram Type= 6, Freq= 0, CH_1, rank 1
3672 05:53:25.760304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3673 05:53:25.760391 ==
3674 05:53:25.760477 DQS Delay:
3675 05:53:25.763507 DQS0 = 0, DQS1 = 0
3676 05:53:25.763593 DQM Delay:
3677 05:53:25.766729 DQM0 = 118, DQM1 = 112
3678 05:53:25.766817 DQ Delay:
3679 05:53:25.770105 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3680 05:53:25.773897 DQ4 =120, DQ5 =128, DQ6 =124, DQ7 =116
3681 05:53:25.777107 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =106
3682 05:53:25.780348 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3683 05:53:25.780469
3684 05:53:25.780562
3685 05:53:25.790322 [DQSOSCAuto] RK1, (LSB)MR18= 0x5ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 408 ps
3686 05:53:25.790432 CH1 RK1: MR19=403, MR18=5EA
3687 05:53:25.796564 CH1_RK1: MR19=0x403, MR18=0x5EA, DQSOSC=408, MR23=63, INC=39, DEC=26
3688 05:53:25.800350 [RxdqsGatingPostProcess] freq 1200
3689 05:53:25.807470 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3690 05:53:25.810579 best DQS0 dly(2T, 0.5T) = (0, 11)
3691 05:53:25.814131 best DQS1 dly(2T, 0.5T) = (0, 11)
3692 05:53:25.817071 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3693 05:53:25.820192 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3694 05:53:25.823770 best DQS0 dly(2T, 0.5T) = (0, 11)
3695 05:53:25.824172 best DQS1 dly(2T, 0.5T) = (0, 11)
3696 05:53:25.826746 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3697 05:53:25.830119 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3698 05:53:25.833880 Pre-setting of DQS Precalculation
3699 05:53:25.840702 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3700 05:53:25.846773 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3701 05:53:25.853649 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3702 05:53:25.854330
3703 05:53:25.854746
3704 05:53:25.857071 [Calibration Summary] 2400 Mbps
3705 05:53:25.860788 CH 0, Rank 0
3706 05:53:25.861329 SW Impedance : PASS
3707 05:53:25.864002 DUTY Scan : NO K
3708 05:53:25.864538 ZQ Calibration : PASS
3709 05:53:25.867427 Jitter Meter : NO K
3710 05:53:25.870230 CBT Training : PASS
3711 05:53:25.870667 Write leveling : PASS
3712 05:53:25.873576 RX DQS gating : PASS
3713 05:53:25.877212 RX DQ/DQS(RDDQC) : PASS
3714 05:53:25.877751 TX DQ/DQS : PASS
3715 05:53:25.880521 RX DATLAT : PASS
3716 05:53:25.883630 RX DQ/DQS(Engine): PASS
3717 05:53:25.884069 TX OE : NO K
3718 05:53:25.886943 All Pass.
3719 05:53:25.887376
3720 05:53:25.887807 CH 0, Rank 1
3721 05:53:25.890508 SW Impedance : PASS
3722 05:53:25.891051 DUTY Scan : NO K
3723 05:53:25.893556 ZQ Calibration : PASS
3724 05:53:25.897013 Jitter Meter : NO K
3725 05:53:25.897561 CBT Training : PASS
3726 05:53:25.900583 Write leveling : PASS
3727 05:53:25.901122 RX DQS gating : PASS
3728 05:53:25.903887 RX DQ/DQS(RDDQC) : PASS
3729 05:53:25.907097 TX DQ/DQS : PASS
3730 05:53:25.907640 RX DATLAT : PASS
3731 05:53:25.910215 RX DQ/DQS(Engine): PASS
3732 05:53:25.913855 TX OE : NO K
3733 05:53:25.914533 All Pass.
3734 05:53:25.914978
3735 05:53:25.915385 CH 1, Rank 0
3736 05:53:25.916960 SW Impedance : PASS
3737 05:53:25.920152 DUTY Scan : NO K
3738 05:53:25.920607 ZQ Calibration : PASS
3739 05:53:25.924137 Jitter Meter : NO K
3740 05:53:25.927148 CBT Training : PASS
3741 05:53:25.927586 Write leveling : PASS
3742 05:53:25.930173 RX DQS gating : PASS
3743 05:53:25.933484 RX DQ/DQS(RDDQC) : PASS
3744 05:53:25.933918 TX DQ/DQS : PASS
3745 05:53:25.937028 RX DATLAT : PASS
3746 05:53:25.940209 RX DQ/DQS(Engine): PASS
3747 05:53:25.940783 TX OE : NO K
3748 05:53:25.941229 All Pass.
3749 05:53:25.943411
3750 05:53:25.943844 CH 1, Rank 1
3751 05:53:25.946973 SW Impedance : PASS
3752 05:53:25.947373 DUTY Scan : NO K
3753 05:53:25.950221 ZQ Calibration : PASS
3754 05:53:25.950750 Jitter Meter : NO K
3755 05:53:25.953369 CBT Training : PASS
3756 05:53:25.957060 Write leveling : PASS
3757 05:53:25.957564 RX DQS gating : PASS
3758 05:53:25.960330 RX DQ/DQS(RDDQC) : PASS
3759 05:53:25.963432 TX DQ/DQS : PASS
3760 05:53:25.963837 RX DATLAT : PASS
3761 05:53:25.966526 RX DQ/DQS(Engine): PASS
3762 05:53:25.969722 TX OE : NO K
3763 05:53:25.970243 All Pass.
3764 05:53:25.970637
3765 05:53:25.973655 DramC Write-DBI off
3766 05:53:25.974199 PER_BANK_REFRESH: Hybrid Mode
3767 05:53:25.976682 TX_TRACKING: ON
3768 05:53:25.983098 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3769 05:53:25.990178 [FAST_K] Save calibration result to emmc
3770 05:53:25.993512 dramc_set_vcore_voltage set vcore to 650000
3771 05:53:25.994059 Read voltage for 600, 5
3772 05:53:25.996519 Vio18 = 0
3773 05:53:25.996916 Vcore = 650000
3774 05:53:25.997314 Vdram = 0
3775 05:53:26.000178 Vddq = 0
3776 05:53:26.000682 Vmddr = 0
3777 05:53:26.003225 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3778 05:53:26.009706 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3779 05:53:26.012816 MEM_TYPE=3, freq_sel=19
3780 05:53:26.016135 sv_algorithm_assistance_LP4_1600
3781 05:53:26.019528 ============ PULL DRAM RESETB DOWN ============
3782 05:53:26.022795 ========== PULL DRAM RESETB DOWN end =========
3783 05:53:26.029261 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3784 05:53:26.032892 ===================================
3785 05:53:26.033293 LPDDR4 DRAM CONFIGURATION
3786 05:53:26.036037 ===================================
3787 05:53:26.039588 EX_ROW_EN[0] = 0x0
3788 05:53:26.039988 EX_ROW_EN[1] = 0x0
3789 05:53:26.042604 LP4Y_EN = 0x0
3790 05:53:26.046118 WORK_FSP = 0x0
3791 05:53:26.046517 WL = 0x2
3792 05:53:26.049350 RL = 0x2
3793 05:53:26.049749 BL = 0x2
3794 05:53:26.052830 RPST = 0x0
3795 05:53:26.053464 RD_PRE = 0x0
3796 05:53:26.056047 WR_PRE = 0x1
3797 05:53:26.056436 WR_PST = 0x0
3798 05:53:26.059163 DBI_WR = 0x0
3799 05:53:26.059554 DBI_RD = 0x0
3800 05:53:26.063007 OTF = 0x1
3801 05:53:26.066008 ===================================
3802 05:53:26.069664 ===================================
3803 05:53:26.070298 ANA top config
3804 05:53:26.072926 ===================================
3805 05:53:26.076057 DLL_ASYNC_EN = 0
3806 05:53:26.079251 ALL_SLAVE_EN = 1
3807 05:53:26.079641 NEW_RANK_MODE = 1
3808 05:53:26.082608 DLL_IDLE_MODE = 1
3809 05:53:26.086252 LP45_APHY_COMB_EN = 1
3810 05:53:26.089657 TX_ODT_DIS = 1
3811 05:53:26.090185 NEW_8X_MODE = 1
3812 05:53:26.092848 ===================================
3813 05:53:26.096236 ===================================
3814 05:53:26.099716 data_rate = 1200
3815 05:53:26.102864 CKR = 1
3816 05:53:26.106224 DQ_P2S_RATIO = 8
3817 05:53:26.109657 ===================================
3818 05:53:26.113080 CA_P2S_RATIO = 8
3819 05:53:26.116039 DQ_CA_OPEN = 0
3820 05:53:26.116533 DQ_SEMI_OPEN = 0
3821 05:53:26.119338 CA_SEMI_OPEN = 0
3822 05:53:26.122725 CA_FULL_RATE = 0
3823 05:53:26.126075 DQ_CKDIV4_EN = 1
3824 05:53:26.129585 CA_CKDIV4_EN = 1
3825 05:53:26.133197 CA_PREDIV_EN = 0
3826 05:53:26.133690 PH8_DLY = 0
3827 05:53:26.136251 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3828 05:53:26.139644 DQ_AAMCK_DIV = 4
3829 05:53:26.143049 CA_AAMCK_DIV = 4
3830 05:53:26.145870 CA_ADMCK_DIV = 4
3831 05:53:26.149703 DQ_TRACK_CA_EN = 0
3832 05:53:26.150344 CA_PICK = 600
3833 05:53:26.152851 CA_MCKIO = 600
3834 05:53:26.155748 MCKIO_SEMI = 0
3835 05:53:26.159352 PLL_FREQ = 2288
3836 05:53:26.162652 DQ_UI_PI_RATIO = 32
3837 05:53:26.166066 CA_UI_PI_RATIO = 0
3838 05:53:26.169350 ===================================
3839 05:53:26.172359 ===================================
3840 05:53:26.175579 memory_type:LPDDR4
3841 05:53:26.176008 GP_NUM : 10
3842 05:53:26.179051 SRAM_EN : 1
3843 05:53:26.179526 MD32_EN : 0
3844 05:53:26.182368 ===================================
3845 05:53:26.185534 [ANA_INIT] >>>>>>>>>>>>>>
3846 05:53:26.189532 <<<<<< [CONFIGURE PHASE]: ANA_TX
3847 05:53:26.192502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3848 05:53:26.195781 ===================================
3849 05:53:26.199548 data_rate = 1200,PCW = 0X5800
3850 05:53:26.202884 ===================================
3851 05:53:26.206125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3852 05:53:26.209432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3853 05:53:26.215658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 05:53:26.222374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3855 05:53:26.225793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3856 05:53:26.228785 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3857 05:53:26.229212 [ANA_INIT] flow start
3858 05:53:26.232425 [ANA_INIT] PLL >>>>>>>>
3859 05:53:26.235510 [ANA_INIT] PLL <<<<<<<<
3860 05:53:26.235940 [ANA_INIT] MIDPI >>>>>>>>
3861 05:53:26.238774 [ANA_INIT] MIDPI <<<<<<<<
3862 05:53:26.242177 [ANA_INIT] DLL >>>>>>>>
3863 05:53:26.242708 [ANA_INIT] flow end
3864 05:53:26.248960 ============ LP4 DIFF to SE enter ============
3865 05:53:26.252034 ============ LP4 DIFF to SE exit ============
3866 05:53:26.255112 [ANA_INIT] <<<<<<<<<<<<<
3867 05:53:26.255539 [Flow] Enable top DCM control >>>>>
3868 05:53:26.258607 [Flow] Enable top DCM control <<<<<
3869 05:53:26.262067 Enable DLL master slave shuffle
3870 05:53:26.268719 ==============================================================
3871 05:53:26.272157 Gating Mode config
3872 05:53:26.275310 ==============================================================
3873 05:53:26.278504 Config description:
3874 05:53:26.288959 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3875 05:53:26.295392 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3876 05:53:26.298760 SELPH_MODE 0: By rank 1: By Phase
3877 05:53:26.305771 ==============================================================
3878 05:53:26.309155 GAT_TRACK_EN = 1
3879 05:53:26.312155 RX_GATING_MODE = 2
3880 05:53:26.312591 RX_GATING_TRACK_MODE = 2
3881 05:53:26.315419 SELPH_MODE = 1
3882 05:53:26.318757 PICG_EARLY_EN = 1
3883 05:53:26.321823 VALID_LAT_VALUE = 1
3884 05:53:26.329187 ==============================================================
3885 05:53:26.332021 Enter into Gating configuration >>>>
3886 05:53:26.335112 Exit from Gating configuration <<<<
3887 05:53:26.338498 Enter into DVFS_PRE_config >>>>>
3888 05:53:26.348721 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3889 05:53:26.352296 Exit from DVFS_PRE_config <<<<<
3890 05:53:26.354976 Enter into PICG configuration >>>>
3891 05:53:26.358523 Exit from PICG configuration <<<<
3892 05:53:26.362026 [RX_INPUT] configuration >>>>>
3893 05:53:26.365114 [RX_INPUT] configuration <<<<<
3894 05:53:26.368552 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3895 05:53:26.375232 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3896 05:53:26.381921 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3897 05:53:26.388677 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3898 05:53:26.391958 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3899 05:53:26.398548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3900 05:53:26.401882 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3901 05:53:26.408482 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3902 05:53:26.411843 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3903 05:53:26.415181 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3904 05:53:26.418558 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3905 05:53:26.425438 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3906 05:53:26.428799 ===================================
3907 05:53:26.429345 LPDDR4 DRAM CONFIGURATION
3908 05:53:26.431943 ===================================
3909 05:53:26.435011 EX_ROW_EN[0] = 0x0
3910 05:53:26.438261 EX_ROW_EN[1] = 0x0
3911 05:53:26.438693 LP4Y_EN = 0x0
3912 05:53:26.442278 WORK_FSP = 0x0
3913 05:53:26.442812 WL = 0x2
3914 05:53:26.445451 RL = 0x2
3915 05:53:26.446025 BL = 0x2
3916 05:53:26.448398 RPST = 0x0
3917 05:53:26.448936 RD_PRE = 0x0
3918 05:53:26.451849 WR_PRE = 0x1
3919 05:53:26.452412 WR_PST = 0x0
3920 05:53:26.454972 DBI_WR = 0x0
3921 05:53:26.455408 DBI_RD = 0x0
3922 05:53:26.458279 OTF = 0x1
3923 05:53:26.461620 ===================================
3924 05:53:26.465048 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3925 05:53:26.468493 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3926 05:53:26.474862 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3927 05:53:26.478157 ===================================
3928 05:53:26.478593 LPDDR4 DRAM CONFIGURATION
3929 05:53:26.481703 ===================================
3930 05:53:26.484655 EX_ROW_EN[0] = 0x10
3931 05:53:26.488034 EX_ROW_EN[1] = 0x0
3932 05:53:26.488469 LP4Y_EN = 0x0
3933 05:53:26.491672 WORK_FSP = 0x0
3934 05:53:26.492199 WL = 0x2
3935 05:53:26.494806 RL = 0x2
3936 05:53:26.495238 BL = 0x2
3937 05:53:26.497882 RPST = 0x0
3938 05:53:26.498342 RD_PRE = 0x0
3939 05:53:26.501572 WR_PRE = 0x1
3940 05:53:26.502142 WR_PST = 0x0
3941 05:53:26.505130 DBI_WR = 0x0
3942 05:53:26.505669 DBI_RD = 0x0
3943 05:53:26.508141 OTF = 0x1
3944 05:53:26.511581 ===================================
3945 05:53:26.518206 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3946 05:53:26.521471 nWR fixed to 30
3947 05:53:26.522049 [ModeRegInit_LP4] CH0 RK0
3948 05:53:26.524573 [ModeRegInit_LP4] CH0 RK1
3949 05:53:26.528325 [ModeRegInit_LP4] CH1 RK0
3950 05:53:26.531367 [ModeRegInit_LP4] CH1 RK1
3951 05:53:26.531801 match AC timing 17
3952 05:53:26.534907 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3953 05:53:26.541585 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3954 05:53:26.544927 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3955 05:53:26.548203 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3956 05:53:26.554703 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3957 05:53:26.555248 ==
3958 05:53:26.557714 Dram Type= 6, Freq= 0, CH_0, rank 0
3959 05:53:26.561338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 05:53:26.561882 ==
3961 05:53:26.567587 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3962 05:53:26.574304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3963 05:53:26.577387 [CA 0] Center 36 (5~67) winsize 63
3964 05:53:26.580930 [CA 1] Center 36 (6~67) winsize 62
3965 05:53:26.584076 [CA 2] Center 34 (4~65) winsize 62
3966 05:53:26.587604 [CA 3] Center 34 (3~65) winsize 63
3967 05:53:26.590881 [CA 4] Center 34 (3~65) winsize 63
3968 05:53:26.594056 [CA 5] Center 33 (2~64) winsize 63
3969 05:53:26.594487
3970 05:53:26.597692 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3971 05:53:26.598285
3972 05:53:26.601136 [CATrainingPosCal] consider 1 rank data
3973 05:53:26.604032 u2DelayCellTimex100 = 270/100 ps
3974 05:53:26.607392 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3975 05:53:26.610605 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3976 05:53:26.614014 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3977 05:53:26.617315 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3978 05:53:26.620597 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3979 05:53:26.623918 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3980 05:53:26.624457
3981 05:53:26.630578 CA PerBit enable=1, Macro0, CA PI delay=33
3982 05:53:26.631172
3983 05:53:26.631527 [CBTSetCACLKResult] CA Dly = 33
3984 05:53:26.633902 CS Dly: 4 (0~35)
3985 05:53:26.634361 ==
3986 05:53:26.637349 Dram Type= 6, Freq= 0, CH_0, rank 1
3987 05:53:26.641165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 05:53:26.641708 ==
3989 05:53:26.647439 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3990 05:53:26.653922 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3991 05:53:26.657071 [CA 0] Center 36 (6~67) winsize 62
3992 05:53:26.660659 [CA 1] Center 36 (6~67) winsize 62
3993 05:53:26.663741 [CA 2] Center 35 (5~66) winsize 62
3994 05:53:26.667228 [CA 3] Center 34 (4~65) winsize 62
3995 05:53:26.670529 [CA 4] Center 34 (3~65) winsize 63
3996 05:53:26.673802 [CA 5] Center 34 (3~65) winsize 63
3997 05:53:26.674387
3998 05:53:26.676851 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3999 05:53:26.677282
4000 05:53:26.680673 [CATrainingPosCal] consider 2 rank data
4001 05:53:26.683840 u2DelayCellTimex100 = 270/100 ps
4002 05:53:26.687043 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4003 05:53:26.690456 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4004 05:53:26.693703 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4005 05:53:26.696745 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4006 05:53:26.700553 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4007 05:53:26.706815 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4008 05:53:26.707355
4009 05:53:26.710198 CA PerBit enable=1, Macro0, CA PI delay=33
4010 05:53:26.710709
4011 05:53:26.713703 [CBTSetCACLKResult] CA Dly = 33
4012 05:53:26.714320 CS Dly: 5 (0~37)
4013 05:53:26.714675
4014 05:53:26.716649 ----->DramcWriteLeveling(PI) begin...
4015 05:53:26.717089 ==
4016 05:53:26.720562 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 05:53:26.723666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 05:53:26.727127 ==
4019 05:53:26.727662 Write leveling (Byte 0): 34 => 34
4020 05:53:26.730243 Write leveling (Byte 1): 30 => 30
4021 05:53:26.733680 DramcWriteLeveling(PI) end<-----
4022 05:53:26.734261
4023 05:53:26.734610 ==
4024 05:53:26.736691 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 05:53:26.743878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 05:53:26.744418 ==
4027 05:53:26.744768 [Gating] SW mode calibration
4028 05:53:26.753684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4029 05:53:26.756773 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4030 05:53:26.763388 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 05:53:26.767321 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 05:53:26.770389 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 05:53:26.773713 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 0)
4034 05:53:26.779734 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
4035 05:53:26.783427 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 05:53:26.786888 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 05:53:26.793505 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 05:53:26.796503 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 05:53:26.799796 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 05:53:26.806704 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 05:53:26.809602 0 10 12 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (1 1)
4042 05:53:26.813187 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4043 05:53:26.819634 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 05:53:26.822788 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 05:53:26.826368 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 05:53:26.833173 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 05:53:26.836366 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 05:53:26.839642 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 05:53:26.846525 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4050 05:53:26.849852 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4051 05:53:26.853501 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 05:53:26.859890 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 05:53:26.862548 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 05:53:26.865897 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 05:53:26.872714 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 05:53:26.875788 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 05:53:26.879596 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 05:53:26.886318 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 05:53:26.889474 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 05:53:26.892638 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 05:53:26.899561 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 05:53:26.902517 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 05:53:26.906406 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 05:53:26.912639 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 05:53:26.915707 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4066 05:53:26.919305 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4067 05:53:26.922452 Total UI for P1: 0, mck2ui 16
4068 05:53:26.925393 best dqsien dly found for B0: ( 0, 13, 12)
4069 05:53:26.932477 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 05:53:26.933015 Total UI for P1: 0, mck2ui 16
4071 05:53:26.938634 best dqsien dly found for B1: ( 0, 13, 18)
4072 05:53:26.942282 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4073 05:53:26.945756 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4074 05:53:26.946334
4075 05:53:26.949125 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4076 05:53:26.952473 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4077 05:53:26.955038 [Gating] SW calibration Done
4078 05:53:26.955464 ==
4079 05:53:26.958680 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 05:53:26.961642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 05:53:26.962118 ==
4082 05:53:26.965110 RX Vref Scan: 0
4083 05:53:26.965531
4084 05:53:26.965866 RX Vref 0 -> 0, step: 1
4085 05:53:26.966252
4086 05:53:26.968724 RX Delay -230 -> 252, step: 16
4087 05:53:26.975076 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4088 05:53:26.978440 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4089 05:53:26.981747 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4090 05:53:26.985422 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4091 05:53:26.991843 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4092 05:53:26.994845 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4093 05:53:26.998150 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4094 05:53:27.001708 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4095 05:53:27.004887 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4096 05:53:27.011173 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4097 05:53:27.014604 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4098 05:53:27.018347 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4099 05:53:27.021148 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4100 05:53:27.027990 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4101 05:53:27.031191 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4102 05:53:27.034787 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4103 05:53:27.035331 ==
4104 05:53:27.037599 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 05:53:27.040836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 05:53:27.044131 ==
4107 05:53:27.044667 DQS Delay:
4108 05:53:27.045018 DQS0 = 0, DQS1 = 0
4109 05:53:27.047842 DQM Delay:
4110 05:53:27.048293 DQM0 = 52, DQM1 = 40
4111 05:53:27.050980 DQ Delay:
4112 05:53:27.051486 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4113 05:53:27.054310 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4114 05:53:27.057550 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4115 05:53:27.060911 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4116 05:53:27.061334
4117 05:53:27.064139
4118 05:53:27.064561 ==
4119 05:53:27.067378 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 05:53:27.070708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 05:53:27.071132 ==
4122 05:53:27.071470
4123 05:53:27.071782
4124 05:53:27.074435 TX Vref Scan disable
4125 05:53:27.074860 == TX Byte 0 ==
4126 05:53:27.081270 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4127 05:53:27.084536 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4128 05:53:27.085068 == TX Byte 1 ==
4129 05:53:27.090794 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4130 05:53:27.094247 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4131 05:53:27.094774 ==
4132 05:53:27.097957 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 05:53:27.100907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 05:53:27.101437 ==
4135 05:53:27.101774
4136 05:53:27.102138
4137 05:53:27.104420 TX Vref Scan disable
4138 05:53:27.107981 == TX Byte 0 ==
4139 05:53:27.111247 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4140 05:53:27.114165 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4141 05:53:27.117397 == TX Byte 1 ==
4142 05:53:27.121180 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4143 05:53:27.124210 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4144 05:53:27.124637
4145 05:53:27.127676 [DATLAT]
4146 05:53:27.128208 Freq=600, CH0 RK0
4147 05:53:27.128550
4148 05:53:27.130982 DATLAT Default: 0x9
4149 05:53:27.131406 0, 0xFFFF, sum = 0
4150 05:53:27.134275 1, 0xFFFF, sum = 0
4151 05:53:27.134707 2, 0xFFFF, sum = 0
4152 05:53:27.137389 3, 0xFFFF, sum = 0
4153 05:53:27.137815 4, 0xFFFF, sum = 0
4154 05:53:27.140511 5, 0xFFFF, sum = 0
4155 05:53:27.140942 6, 0xFFFF, sum = 0
4156 05:53:27.144127 7, 0xFFFF, sum = 0
4157 05:53:27.144664 8, 0x0, sum = 1
4158 05:53:27.147551 9, 0x0, sum = 2
4159 05:53:27.148093 10, 0x0, sum = 3
4160 05:53:27.151061 11, 0x0, sum = 4
4161 05:53:27.151595 best_step = 9
4162 05:53:27.151939
4163 05:53:27.152252 ==
4164 05:53:27.154227 Dram Type= 6, Freq= 0, CH_0, rank 0
4165 05:53:27.161171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 05:53:27.161709 ==
4167 05:53:27.162079 RX Vref Scan: 1
4168 05:53:27.162400
4169 05:53:27.163851 RX Vref 0 -> 0, step: 1
4170 05:53:27.164275
4171 05:53:27.167483 RX Delay -179 -> 252, step: 8
4172 05:53:27.168015
4173 05:53:27.170584 Set Vref, RX VrefLevel [Byte0]: 58
4174 05:53:27.174145 [Byte1]: 54
4175 05:53:27.174679
4176 05:53:27.177031 Final RX Vref Byte 0 = 58 to rank0
4177 05:53:27.181027 Final RX Vref Byte 1 = 54 to rank0
4178 05:53:27.183851 Final RX Vref Byte 0 = 58 to rank1
4179 05:53:27.187557 Final RX Vref Byte 1 = 54 to rank1==
4180 05:53:27.190664 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 05:53:27.194171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 05:53:27.194706 ==
4183 05:53:27.197624 DQS Delay:
4184 05:53:27.198077 DQS0 = 0, DQS1 = 0
4185 05:53:27.198418 DQM Delay:
4186 05:53:27.200478 DQM0 = 49, DQM1 = 39
4187 05:53:27.201000 DQ Delay:
4188 05:53:27.203869 DQ0 =48, DQ1 =52, DQ2 =44, DQ3 =44
4189 05:53:27.207167 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4190 05:53:27.210815 DQ8 =32, DQ9 =24, DQ10 =40, DQ11 =32
4191 05:53:27.214293 DQ12 =48, DQ13 =40, DQ14 =52, DQ15 =48
4192 05:53:27.214853
4193 05:53:27.215222
4194 05:53:27.224288 [DQSOSCAuto] RK0, (LSB)MR18= 0x5a55, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4195 05:53:27.224829 CH0 RK0: MR19=808, MR18=5A55
4196 05:53:27.230663 CH0_RK0: MR19=0x808, MR18=0x5A55, DQSOSC=392, MR23=63, INC=170, DEC=113
4197 05:53:27.231207
4198 05:53:27.234023 ----->DramcWriteLeveling(PI) begin...
4199 05:53:27.236978 ==
4200 05:53:27.237506 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 05:53:27.244292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 05:53:27.244827 ==
4203 05:53:27.247015 Write leveling (Byte 0): 34 => 34
4204 05:53:27.250330 Write leveling (Byte 1): 30 => 30
4205 05:53:27.253698 DramcWriteLeveling(PI) end<-----
4206 05:53:27.254298
4207 05:53:27.254654 ==
4208 05:53:27.256911 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 05:53:27.260241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 05:53:27.260676 ==
4211 05:53:27.263929 [Gating] SW mode calibration
4212 05:53:27.270559 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4213 05:53:27.274019 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4214 05:53:27.280276 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 05:53:27.283759 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 05:53:27.286740 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 05:53:27.294069 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
4218 05:53:27.297353 0 9 16 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (0 0)
4219 05:53:27.300629 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 05:53:27.306896 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 05:53:27.310309 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 05:53:27.313609 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 05:53:27.320476 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 05:53:27.323696 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 05:53:27.326949 0 10 12 | B1->B0 | 2f2f 3030 | 1 0 | (0 0) (0 0)
4226 05:53:27.333158 0 10 16 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)
4227 05:53:27.336797 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 05:53:27.339782 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 05:53:27.346629 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 05:53:27.350354 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 05:53:27.353298 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 05:53:27.359831 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 05:53:27.362971 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4234 05:53:27.366286 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4235 05:53:27.373006 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 05:53:27.376407 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 05:53:27.379490 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 05:53:27.386848 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 05:53:27.389712 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 05:53:27.393126 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 05:53:27.400204 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 05:53:27.402829 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 05:53:27.406699 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 05:53:27.413101 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 05:53:27.416360 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 05:53:27.419757 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 05:53:27.425312 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 05:53:27.429522 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 05:53:27.432622 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4250 05:53:27.436368 Total UI for P1: 0, mck2ui 16
4251 05:53:27.439516 best dqsien dly found for B1: ( 0, 13, 10)
4252 05:53:27.443747 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4253 05:53:27.449733 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 05:53:27.452693 Total UI for P1: 0, mck2ui 16
4255 05:53:27.456014 best dqsien dly found for B0: ( 0, 13, 14)
4256 05:53:27.459317 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4257 05:53:27.462668 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4258 05:53:27.463095
4259 05:53:27.465916 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4260 05:53:27.469206 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4261 05:53:27.472685 [Gating] SW calibration Done
4262 05:53:27.473125 ==
4263 05:53:27.476466 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 05:53:27.479443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 05:53:27.479948 ==
4266 05:53:27.482662 RX Vref Scan: 0
4267 05:53:27.483137
4268 05:53:27.486061 RX Vref 0 -> 0, step: 1
4269 05:53:27.486546
4270 05:53:27.487066 RX Delay -230 -> 252, step: 16
4271 05:53:27.493011 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4272 05:53:27.496503 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4273 05:53:27.499376 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4274 05:53:27.502862 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4275 05:53:27.509647 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4276 05:53:27.512931 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4277 05:53:27.515864 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4278 05:53:27.519332 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4279 05:53:27.522727 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4280 05:53:27.529417 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4281 05:53:27.532335 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4282 05:53:27.535531 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4283 05:53:27.538843 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4284 05:53:27.545724 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4285 05:53:27.549449 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4286 05:53:27.552487 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4287 05:53:27.553016 ==
4288 05:53:27.555695 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 05:53:27.558648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 05:53:27.562053 ==
4291 05:53:27.562605 DQS Delay:
4292 05:53:27.562993 DQS0 = 0, DQS1 = 0
4293 05:53:27.565462 DQM Delay:
4294 05:53:27.565884 DQM0 = 51, DQM1 = 43
4295 05:53:27.568952 DQ Delay:
4296 05:53:27.569530 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4297 05:53:27.572301 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4298 05:53:27.575633 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =41
4299 05:53:27.579122 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4300 05:53:27.579549
4301 05:53:27.582229
4302 05:53:27.582651 ==
4303 05:53:27.585433 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 05:53:27.588901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 05:53:27.589439 ==
4306 05:53:27.589782
4307 05:53:27.590227
4308 05:53:27.592299 TX Vref Scan disable
4309 05:53:27.592842 == TX Byte 0 ==
4310 05:53:27.598911 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4311 05:53:27.602239 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4312 05:53:27.602767 == TX Byte 1 ==
4313 05:53:27.608766 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4314 05:53:27.612251 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4315 05:53:27.612784 ==
4316 05:53:27.615318 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 05:53:27.618523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 05:53:27.618951 ==
4319 05:53:27.619287
4320 05:53:27.619600
4321 05:53:27.622327 TX Vref Scan disable
4322 05:53:27.625026 == TX Byte 0 ==
4323 05:53:27.628505 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4324 05:53:27.634805 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4325 05:53:27.635231 == TX Byte 1 ==
4326 05:53:27.638474 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4327 05:53:27.645036 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4328 05:53:27.645613
4329 05:53:27.646135 [DATLAT]
4330 05:53:27.646604 Freq=600, CH0 RK1
4331 05:53:27.647066
4332 05:53:27.648052 DATLAT Default: 0x9
4333 05:53:27.648611 0, 0xFFFF, sum = 0
4334 05:53:27.651839 1, 0xFFFF, sum = 0
4335 05:53:27.654919 2, 0xFFFF, sum = 0
4336 05:53:27.655351 3, 0xFFFF, sum = 0
4337 05:53:27.658354 4, 0xFFFF, sum = 0
4338 05:53:27.658856 5, 0xFFFF, sum = 0
4339 05:53:27.661380 6, 0xFFFF, sum = 0
4340 05:53:27.661934 7, 0xFFFF, sum = 0
4341 05:53:27.664864 8, 0x0, sum = 1
4342 05:53:27.665308 9, 0x0, sum = 2
4343 05:53:27.665656 10, 0x0, sum = 3
4344 05:53:27.667839 11, 0x0, sum = 4
4345 05:53:27.668269 best_step = 9
4346 05:53:27.668599
4347 05:53:27.668907 ==
4348 05:53:27.671287 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 05:53:27.678043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 05:53:27.678463 ==
4351 05:53:27.678796 RX Vref Scan: 0
4352 05:53:27.679163
4353 05:53:27.680997 RX Vref 0 -> 0, step: 1
4354 05:53:27.681411
4355 05:53:27.684632 RX Delay -179 -> 252, step: 8
4356 05:53:27.687831 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4357 05:53:27.694312 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4358 05:53:27.697921 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4359 05:53:27.701311 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4360 05:53:27.704943 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4361 05:53:27.708289 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4362 05:53:27.714425 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4363 05:53:27.717674 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4364 05:53:27.721108 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4365 05:53:27.724431 iDelay=205, Bit 9, Center 24 (-123 ~ 172) 296
4366 05:53:27.731151 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4367 05:53:27.734423 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4368 05:53:27.737537 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4369 05:53:27.740885 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4370 05:53:27.744444 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4371 05:53:27.750997 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4372 05:53:27.751515 ==
4373 05:53:27.754347 Dram Type= 6, Freq= 0, CH_0, rank 1
4374 05:53:27.757904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 05:53:27.758461 ==
4376 05:53:27.758792 DQS Delay:
4377 05:53:27.761202 DQS0 = 0, DQS1 = 0
4378 05:53:27.761756 DQM Delay:
4379 05:53:27.764570 DQM0 = 48, DQM1 = 39
4380 05:53:27.765088 DQ Delay:
4381 05:53:27.767767 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4382 05:53:27.771141 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4383 05:53:27.774427 DQ8 =32, DQ9 =24, DQ10 =40, DQ11 =36
4384 05:53:27.777980 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =48
4385 05:53:27.778540
4386 05:53:27.778886
4387 05:53:27.787455 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d2b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
4388 05:53:27.787982 CH0 RK1: MR19=808, MR18=5D2B
4389 05:53:27.794039 CH0_RK1: MR19=0x808, MR18=0x5D2B, DQSOSC=392, MR23=63, INC=170, DEC=113
4390 05:53:27.797710 [RxdqsGatingPostProcess] freq 600
4391 05:53:27.804011 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4392 05:53:27.807413 Pre-setting of DQS Precalculation
4393 05:53:27.810668 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4394 05:53:27.811084 ==
4395 05:53:27.814045 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 05:53:27.817756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 05:53:27.818217 ==
4398 05:53:27.824306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4399 05:53:27.830659 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4400 05:53:27.833986 [CA 0] Center 35 (5~66) winsize 62
4401 05:53:27.838181 [CA 1] Center 35 (5~66) winsize 62
4402 05:53:27.840609 [CA 2] Center 34 (3~65) winsize 63
4403 05:53:27.844048 [CA 3] Center 33 (3~64) winsize 62
4404 05:53:27.847212 [CA 4] Center 34 (3~65) winsize 63
4405 05:53:27.850424 [CA 5] Center 33 (3~64) winsize 62
4406 05:53:27.850847
4407 05:53:27.853999 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4408 05:53:27.854522
4409 05:53:27.857225 [CATrainingPosCal] consider 1 rank data
4410 05:53:27.860533 u2DelayCellTimex100 = 270/100 ps
4411 05:53:27.863681 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4412 05:53:27.867189 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4413 05:53:27.870297 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4414 05:53:27.873643 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4415 05:53:27.880492 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4416 05:53:27.883642 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 05:53:27.884098
4418 05:53:27.887017 CA PerBit enable=1, Macro0, CA PI delay=33
4419 05:53:27.887441
4420 05:53:27.890495 [CBTSetCACLKResult] CA Dly = 33
4421 05:53:27.890926 CS Dly: 5 (0~36)
4422 05:53:27.891262 ==
4423 05:53:27.893460 Dram Type= 6, Freq= 0, CH_1, rank 1
4424 05:53:27.900542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 05:53:27.900970 ==
4426 05:53:27.903463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4427 05:53:27.910022 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4428 05:53:27.913701 [CA 0] Center 35 (5~66) winsize 62
4429 05:53:27.916933 [CA 1] Center 35 (5~66) winsize 62
4430 05:53:27.920093 [CA 2] Center 34 (4~65) winsize 62
4431 05:53:27.923566 [CA 3] Center 34 (4~65) winsize 62
4432 05:53:27.926804 [CA 4] Center 34 (4~64) winsize 61
4433 05:53:27.930135 [CA 5] Center 34 (4~64) winsize 61
4434 05:53:27.930560
4435 05:53:27.933468 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4436 05:53:27.933924
4437 05:53:27.936719 [CATrainingPosCal] consider 2 rank data
4438 05:53:27.940000 u2DelayCellTimex100 = 270/100 ps
4439 05:53:27.943442 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4440 05:53:27.946936 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4441 05:53:27.950023 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4442 05:53:27.956762 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4443 05:53:27.959946 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4444 05:53:27.963172 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4445 05:53:27.963660
4446 05:53:27.966611 CA PerBit enable=1, Macro0, CA PI delay=34
4447 05:53:27.967045
4448 05:53:27.969985 [CBTSetCACLKResult] CA Dly = 34
4449 05:53:27.970417 CS Dly: 5 (0~36)
4450 05:53:27.970761
4451 05:53:27.973403 ----->DramcWriteLeveling(PI) begin...
4452 05:53:27.973844 ==
4453 05:53:27.976703 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 05:53:27.983379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 05:53:27.983811 ==
4456 05:53:27.986782 Write leveling (Byte 0): 31 => 31
4457 05:53:27.989928 Write leveling (Byte 1): 30 => 30
4458 05:53:27.990390 DramcWriteLeveling(PI) end<-----
4459 05:53:27.993663
4460 05:53:27.994114 ==
4461 05:53:27.996494 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 05:53:28.000036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 05:53:28.000465 ==
4464 05:53:28.003607 [Gating] SW mode calibration
4465 05:53:28.009853 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4466 05:53:28.013104 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4467 05:53:28.019984 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 05:53:28.023346 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 05:53:28.026604 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4470 05:53:28.033176 0 9 12 | B1->B0 | 2929 2929 | 0 0 | (1 0) (0 0)
4471 05:53:28.036593 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 05:53:28.039850 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 05:53:28.046877 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 05:53:28.050141 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 05:53:28.053383 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 05:53:28.060169 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 05:53:28.063251 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 05:53:28.066552 0 10 12 | B1->B0 | 3d3d 3e3e | 0 0 | (0 0) (0 0)
4479 05:53:28.072878 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 05:53:28.076425 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 05:53:28.080030 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 05:53:28.086452 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 05:53:28.089851 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 05:53:28.093416 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 05:53:28.099518 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4486 05:53:28.103031 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4487 05:53:28.106372 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 05:53:28.110098 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 05:53:28.116235 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 05:53:28.120083 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 05:53:28.123102 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 05:53:28.130110 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 05:53:28.133235 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 05:53:28.136157 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 05:53:28.143164 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 05:53:28.146718 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 05:53:28.149897 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 05:53:28.156183 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 05:53:28.160205 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 05:53:28.163220 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 05:53:28.170090 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 05:53:28.173181 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4503 05:53:28.176379 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 05:53:28.179337 Total UI for P1: 0, mck2ui 16
4505 05:53:28.182578 best dqsien dly found for B0: ( 0, 13, 12)
4506 05:53:28.186142 Total UI for P1: 0, mck2ui 16
4507 05:53:28.189454 best dqsien dly found for B1: ( 0, 13, 12)
4508 05:53:28.192939 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4509 05:53:28.196174 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4510 05:53:28.196679
4511 05:53:28.203018 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4512 05:53:28.206106 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4513 05:53:28.206539 [Gating] SW calibration Done
4514 05:53:28.209643 ==
4515 05:53:28.210180 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 05:53:28.216264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 05:53:28.216703 ==
4518 05:53:28.217069 RX Vref Scan: 0
4519 05:53:28.217390
4520 05:53:28.219521 RX Vref 0 -> 0, step: 1
4521 05:53:28.219960
4522 05:53:28.223186 RX Delay -230 -> 252, step: 16
4523 05:53:28.226147 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4524 05:53:28.229668 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4525 05:53:28.236466 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4526 05:53:28.239419 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4527 05:53:28.242707 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4528 05:53:28.245690 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4529 05:53:28.249206 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4530 05:53:28.255770 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4531 05:53:28.259276 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4532 05:53:28.262535 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4533 05:53:28.265652 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4534 05:53:28.272153 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4535 05:53:28.275935 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4536 05:53:28.278951 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4537 05:53:28.282113 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4538 05:53:28.289392 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4539 05:53:28.289935 ==
4540 05:53:28.292030 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 05:53:28.295460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 05:53:28.295997 ==
4543 05:53:28.296345 DQS Delay:
4544 05:53:28.299105 DQS0 = 0, DQS1 = 0
4545 05:53:28.299538 DQM Delay:
4546 05:53:28.302035 DQM0 = 50, DQM1 = 41
4547 05:53:28.302546 DQ Delay:
4548 05:53:28.305530 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4549 05:53:28.308840 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4550 05:53:28.312231 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4551 05:53:28.315963 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4552 05:53:28.316496
4553 05:53:28.316843
4554 05:53:28.317244 ==
4555 05:53:28.318798 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 05:53:28.321871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 05:53:28.322357 ==
4558 05:53:28.325506
4559 05:53:28.325935
4560 05:53:28.326352 TX Vref Scan disable
4561 05:53:28.328779 == TX Byte 0 ==
4562 05:53:28.332190 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4563 05:53:28.335332 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4564 05:53:28.338449 == TX Byte 1 ==
4565 05:53:28.342004 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4566 05:53:28.345313 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4567 05:53:28.345888 ==
4568 05:53:28.348708 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 05:53:28.355561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 05:53:28.355998 ==
4571 05:53:28.356344
4572 05:53:28.356666
4573 05:53:28.356973 TX Vref Scan disable
4574 05:53:28.359733 == TX Byte 0 ==
4575 05:53:28.363190 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4576 05:53:28.366524 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4577 05:53:28.370142 == TX Byte 1 ==
4578 05:53:28.373372 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4579 05:53:28.380099 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4580 05:53:28.380604
4581 05:53:28.380948 [DATLAT]
4582 05:53:28.381272 Freq=600, CH1 RK0
4583 05:53:28.381675
4584 05:53:28.383368 DATLAT Default: 0x9
4585 05:53:28.383801 0, 0xFFFF, sum = 0
4586 05:53:28.386725 1, 0xFFFF, sum = 0
4587 05:53:28.387162 2, 0xFFFF, sum = 0
4588 05:53:28.390059 3, 0xFFFF, sum = 0
4589 05:53:28.390498 4, 0xFFFF, sum = 0
4590 05:53:28.393560 5, 0xFFFF, sum = 0
4591 05:53:28.394131 6, 0xFFFF, sum = 0
4592 05:53:28.396790 7, 0xFFFF, sum = 0
4593 05:53:28.397320 8, 0x0, sum = 1
4594 05:53:28.400230 9, 0x0, sum = 2
4595 05:53:28.400767 10, 0x0, sum = 3
4596 05:53:28.403478 11, 0x0, sum = 4
4597 05:53:28.404013 best_step = 9
4598 05:53:28.404361
4599 05:53:28.404682 ==
4600 05:53:28.407152 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 05:53:28.413588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 05:53:28.414125 ==
4603 05:53:28.414474 RX Vref Scan: 1
4604 05:53:28.414797
4605 05:53:28.416425 RX Vref 0 -> 0, step: 1
4606 05:53:28.416844
4607 05:53:28.420329 RX Delay -179 -> 252, step: 8
4608 05:53:28.420754
4609 05:53:28.423660 Set Vref, RX VrefLevel [Byte0]: 52
4610 05:53:28.426730 [Byte1]: 48
4611 05:53:28.427241
4612 05:53:28.430383 Final RX Vref Byte 0 = 52 to rank0
4613 05:53:28.433119 Final RX Vref Byte 1 = 48 to rank0
4614 05:53:28.436773 Final RX Vref Byte 0 = 52 to rank1
4615 05:53:28.439934 Final RX Vref Byte 1 = 48 to rank1==
4616 05:53:28.443311 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 05:53:28.446621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 05:53:28.447162 ==
4619 05:53:28.450057 DQS Delay:
4620 05:53:28.450579 DQS0 = 0, DQS1 = 0
4621 05:53:28.450931 DQM Delay:
4622 05:53:28.453336 DQM0 = 48, DQM1 = 40
4623 05:53:28.453767 DQ Delay:
4624 05:53:28.456668 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4625 05:53:28.459993 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4626 05:53:28.463293 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4627 05:53:28.466405 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4628 05:53:28.466838
4629 05:53:28.467178
4630 05:53:28.476427 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4631 05:53:28.479815 CH1 RK0: MR19=808, MR18=4B72
4632 05:53:28.483123 CH1_RK0: MR19=0x808, MR18=0x4B72, DQSOSC=388, MR23=63, INC=174, DEC=116
4633 05:53:28.483558
4634 05:53:28.486407 ----->DramcWriteLeveling(PI) begin...
4635 05:53:28.489763 ==
4636 05:53:28.493230 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 05:53:28.496296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 05:53:28.496743 ==
4639 05:53:28.499753 Write leveling (Byte 0): 29 => 29
4640 05:53:28.502958 Write leveling (Byte 1): 30 => 30
4641 05:53:28.506340 DramcWriteLeveling(PI) end<-----
4642 05:53:28.506877
4643 05:53:28.507325 ==
4644 05:53:28.509527 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 05:53:28.512990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 05:53:28.513532 ==
4647 05:53:28.516064 [Gating] SW mode calibration
4648 05:53:28.522573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4649 05:53:28.529072 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4650 05:53:28.532635 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 05:53:28.536000 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 05:53:28.542383 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4653 05:53:28.545812 0 9 12 | B1->B0 | 2f2f 3333 | 0 1 | (1 0) (1 0)
4654 05:53:28.548754 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 05:53:28.555654 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 05:53:28.558905 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 05:53:28.562175 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 05:53:28.568721 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 05:53:28.572167 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 05:53:28.575207 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
4661 05:53:28.581971 0 10 12 | B1->B0 | 4343 2f2f | 0 0 | (0 0) (0 0)
4662 05:53:28.585367 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 05:53:28.588682 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 05:53:28.595963 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 05:53:28.598688 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 05:53:28.602153 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 05:53:28.608554 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 05:53:28.611900 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 05:53:28.615220 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4670 05:53:28.622067 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 05:53:28.625384 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 05:53:28.628469 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 05:53:28.631956 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 05:53:28.638347 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 05:53:28.641747 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 05:53:28.645026 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 05:53:28.651674 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 05:53:28.655059 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 05:53:28.657967 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 05:53:28.664952 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 05:53:28.668187 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 05:53:28.671321 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 05:53:28.678044 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 05:53:28.681544 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4685 05:53:28.684579 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4686 05:53:28.691316 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 05:53:28.694555 Total UI for P1: 0, mck2ui 16
4688 05:53:28.697862 best dqsien dly found for B0: ( 0, 13, 10)
4689 05:53:28.698416 Total UI for P1: 0, mck2ui 16
4690 05:53:28.704705 best dqsien dly found for B1: ( 0, 13, 10)
4691 05:53:28.707943 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4692 05:53:28.711407 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4693 05:53:28.711917
4694 05:53:28.714512 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4695 05:53:28.717475 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4696 05:53:28.721191 [Gating] SW calibration Done
4697 05:53:28.721744 ==
4698 05:53:28.724644 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 05:53:28.727438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 05:53:28.727875 ==
4701 05:53:28.730766 RX Vref Scan: 0
4702 05:53:28.731271
4703 05:53:28.734378 RX Vref 0 -> 0, step: 1
4704 05:53:28.734993
4705 05:53:28.735350 RX Delay -230 -> 252, step: 16
4706 05:53:28.740890 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4707 05:53:28.744244 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4708 05:53:28.747492 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4709 05:53:28.750584 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4710 05:53:28.757489 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4711 05:53:28.760855 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4712 05:53:28.764406 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4713 05:53:28.767063 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4714 05:53:28.770491 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4715 05:53:28.777571 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4716 05:53:28.780690 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4717 05:53:28.784180 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4718 05:53:28.787866 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4719 05:53:28.794177 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4720 05:53:28.797369 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4721 05:53:28.800971 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4722 05:53:28.801553 ==
4723 05:53:28.804389 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 05:53:28.807652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 05:53:28.808220 ==
4726 05:53:28.810841 DQS Delay:
4727 05:53:28.811412 DQS0 = 0, DQS1 = 0
4728 05:53:28.814362 DQM Delay:
4729 05:53:28.814928 DQM0 = 53, DQM1 = 47
4730 05:53:28.815307 DQ Delay:
4731 05:53:28.817451 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4732 05:53:28.820973 DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =49
4733 05:53:28.824419 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4734 05:53:28.827016 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =65
4735 05:53:28.827490
4736 05:53:28.827866
4737 05:53:28.830687 ==
4738 05:53:28.831260 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 05:53:28.837651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 05:53:28.838272 ==
4741 05:53:28.838658
4742 05:53:28.839024
4743 05:53:28.840632 TX Vref Scan disable
4744 05:53:28.841122 == TX Byte 0 ==
4745 05:53:28.843579 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4746 05:53:28.850633 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4747 05:53:28.851174 == TX Byte 1 ==
4748 05:53:28.853926 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4749 05:53:28.860290 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4750 05:53:28.860721 ==
4751 05:53:28.863478 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 05:53:28.866730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 05:53:28.867187 ==
4754 05:53:28.867568
4755 05:53:28.868111
4756 05:53:28.870059 TX Vref Scan disable
4757 05:53:28.873587 == TX Byte 0 ==
4758 05:53:28.876946 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4759 05:53:28.879821 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4760 05:53:28.883347 == TX Byte 1 ==
4761 05:53:28.886870 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4762 05:53:28.890243 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4763 05:53:28.890675
4764 05:53:28.893304 [DATLAT]
4765 05:53:28.893731 Freq=600, CH1 RK1
4766 05:53:28.894107
4767 05:53:28.896791 DATLAT Default: 0x9
4768 05:53:28.897222 0, 0xFFFF, sum = 0
4769 05:53:28.900008 1, 0xFFFF, sum = 0
4770 05:53:28.900448 2, 0xFFFF, sum = 0
4771 05:53:28.903084 3, 0xFFFF, sum = 0
4772 05:53:28.903540 4, 0xFFFF, sum = 0
4773 05:53:28.906377 5, 0xFFFF, sum = 0
4774 05:53:28.906845 6, 0xFFFF, sum = 0
4775 05:53:28.909863 7, 0xFFFF, sum = 0
4776 05:53:28.910344 8, 0x0, sum = 1
4777 05:53:28.913216 9, 0x0, sum = 2
4778 05:53:28.913729 10, 0x0, sum = 3
4779 05:53:28.916639 11, 0x0, sum = 4
4780 05:53:28.917079 best_step = 9
4781 05:53:28.917424
4782 05:53:28.917745 ==
4783 05:53:28.919956 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 05:53:28.923168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 05:53:28.926571 ==
4786 05:53:28.927070 RX Vref Scan: 0
4787 05:53:28.927502
4788 05:53:28.929922 RX Vref 0 -> 0, step: 1
4789 05:53:28.930389
4790 05:53:28.933178 RX Delay -163 -> 252, step: 8
4791 05:53:28.936565 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4792 05:53:28.939761 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4793 05:53:28.946637 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4794 05:53:28.949889 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4795 05:53:28.953180 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4796 05:53:28.956464 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4797 05:53:28.959836 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4798 05:53:28.966353 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4799 05:53:28.969452 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4800 05:53:28.973295 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4801 05:53:28.976146 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4802 05:53:28.979498 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4803 05:53:28.986119 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4804 05:53:28.991811 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4805 05:53:28.992915 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4806 05:53:28.995991 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4807 05:53:28.996422 ==
4808 05:53:28.999420 Dram Type= 6, Freq= 0, CH_1, rank 1
4809 05:53:29.006285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4810 05:53:29.006719 ==
4811 05:53:29.007059 DQS Delay:
4812 05:53:29.009641 DQS0 = 0, DQS1 = 0
4813 05:53:29.010086 DQM Delay:
4814 05:53:29.010428 DQM0 = 48, DQM1 = 43
4815 05:53:29.013086 DQ Delay:
4816 05:53:29.016421 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4817 05:53:29.019581 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4818 05:53:29.023034 DQ8 =28, DQ9 =36, DQ10 =44, DQ11 =36
4819 05:53:29.026044 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4820 05:53:29.026474
4821 05:53:29.026816
4822 05:53:29.032985 [DQSOSCAuto] RK1, (LSB)MR18= 0x5218, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
4823 05:53:29.035944 CH1 RK1: MR19=808, MR18=5218
4824 05:53:29.043126 CH1_RK1: MR19=0x808, MR18=0x5218, DQSOSC=394, MR23=63, INC=168, DEC=112
4825 05:53:29.046059 [RxdqsGatingPostProcess] freq 600
4826 05:53:29.049708 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4827 05:53:29.052906 Pre-setting of DQS Precalculation
4828 05:53:29.059433 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4829 05:53:29.066049 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4830 05:53:29.072591 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4831 05:53:29.073090
4832 05:53:29.073431
4833 05:53:29.075906 [Calibration Summary] 1200 Mbps
4834 05:53:29.076334 CH 0, Rank 0
4835 05:53:29.079760 SW Impedance : PASS
4836 05:53:29.082718 DUTY Scan : NO K
4837 05:53:29.083149 ZQ Calibration : PASS
4838 05:53:29.085974 Jitter Meter : NO K
4839 05:53:29.089518 CBT Training : PASS
4840 05:53:29.090093 Write leveling : PASS
4841 05:53:29.092987 RX DQS gating : PASS
4842 05:53:29.096073 RX DQ/DQS(RDDQC) : PASS
4843 05:53:29.096538 TX DQ/DQS : PASS
4844 05:53:29.099096 RX DATLAT : PASS
4845 05:53:29.102287 RX DQ/DQS(Engine): PASS
4846 05:53:29.102719 TX OE : NO K
4847 05:53:29.103090 All Pass.
4848 05:53:29.105773
4849 05:53:29.106242 CH 0, Rank 1
4850 05:53:29.109223 SW Impedance : PASS
4851 05:53:29.109651 DUTY Scan : NO K
4852 05:53:29.112290 ZQ Calibration : PASS
4853 05:53:29.112719 Jitter Meter : NO K
4854 05:53:29.115676 CBT Training : PASS
4855 05:53:29.119041 Write leveling : PASS
4856 05:53:29.119471 RX DQS gating : PASS
4857 05:53:29.122571 RX DQ/DQS(RDDQC) : PASS
4858 05:53:29.126005 TX DQ/DQS : PASS
4859 05:53:29.126439 RX DATLAT : PASS
4860 05:53:29.129335 RX DQ/DQS(Engine): PASS
4861 05:53:29.132359 TX OE : NO K
4862 05:53:29.132685 All Pass.
4863 05:53:29.132935
4864 05:53:29.133164 CH 1, Rank 0
4865 05:53:29.135824 SW Impedance : PASS
4866 05:53:29.139099 DUTY Scan : NO K
4867 05:53:29.139402 ZQ Calibration : PASS
4868 05:53:29.142238 Jitter Meter : NO K
4869 05:53:29.145580 CBT Training : PASS
4870 05:53:29.145885 Write leveling : PASS
4871 05:53:29.148939 RX DQS gating : PASS
4872 05:53:29.152334 RX DQ/DQS(RDDQC) : PASS
4873 05:53:29.152848 TX DQ/DQS : PASS
4874 05:53:29.155629 RX DATLAT : PASS
4875 05:53:29.158857 RX DQ/DQS(Engine): PASS
4876 05:53:29.159281 TX OE : NO K
4877 05:53:29.159621 All Pass.
4878 05:53:29.159934
4879 05:53:29.162196 CH 1, Rank 1
4880 05:53:29.165769 SW Impedance : PASS
4881 05:53:29.166252 DUTY Scan : NO K
4882 05:53:29.169228 ZQ Calibration : PASS
4883 05:53:29.169852 Jitter Meter : NO K
4884 05:53:29.172341 CBT Training : PASS
4885 05:53:29.176057 Write leveling : PASS
4886 05:53:29.176482 RX DQS gating : PASS
4887 05:53:29.179519 RX DQ/DQS(RDDQC) : PASS
4888 05:53:29.182634 TX DQ/DQS : PASS
4889 05:53:29.183066 RX DATLAT : PASS
4890 05:53:29.185983 RX DQ/DQS(Engine): PASS
4891 05:53:29.189084 TX OE : NO K
4892 05:53:29.189511 All Pass.
4893 05:53:29.189849
4894 05:53:29.190235 DramC Write-DBI off
4895 05:53:29.192240 PER_BANK_REFRESH: Hybrid Mode
4896 05:53:29.195547 TX_TRACKING: ON
4897 05:53:29.202595 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4898 05:53:29.205669 [FAST_K] Save calibration result to emmc
4899 05:53:29.212377 dramc_set_vcore_voltage set vcore to 662500
4900 05:53:29.212893 Read voltage for 933, 3
4901 05:53:29.215174 Vio18 = 0
4902 05:53:29.215599 Vcore = 662500
4903 05:53:29.215935 Vdram = 0
4904 05:53:29.218790 Vddq = 0
4905 05:53:29.219214 Vmddr = 0
4906 05:53:29.222280 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4907 05:53:29.228668 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4908 05:53:29.232048 MEM_TYPE=3, freq_sel=17
4909 05:53:29.235204 sv_algorithm_assistance_LP4_1600
4910 05:53:29.238505 ============ PULL DRAM RESETB DOWN ============
4911 05:53:29.241754 ========== PULL DRAM RESETB DOWN end =========
4912 05:53:29.245543 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4913 05:53:29.248739 ===================================
4914 05:53:29.252147 LPDDR4 DRAM CONFIGURATION
4915 05:53:29.255429 ===================================
4916 05:53:29.258806 EX_ROW_EN[0] = 0x0
4917 05:53:29.259331 EX_ROW_EN[1] = 0x0
4918 05:53:29.262253 LP4Y_EN = 0x0
4919 05:53:29.262777 WORK_FSP = 0x0
4920 05:53:29.265477 WL = 0x3
4921 05:53:29.265911 RL = 0x3
4922 05:53:29.268692 BL = 0x2
4923 05:53:29.269246 RPST = 0x0
4924 05:53:29.271965 RD_PRE = 0x0
4925 05:53:29.272461 WR_PRE = 0x1
4926 05:53:29.275327 WR_PST = 0x0
4927 05:53:29.278462 DBI_WR = 0x0
4928 05:53:29.278896 DBI_RD = 0x0
4929 05:53:29.281821 OTF = 0x1
4930 05:53:29.285227 ===================================
4931 05:53:29.288483 ===================================
4932 05:53:29.289048 ANA top config
4933 05:53:29.291665 ===================================
4934 05:53:29.294913 DLL_ASYNC_EN = 0
4935 05:53:29.298260 ALL_SLAVE_EN = 1
4936 05:53:29.298848 NEW_RANK_MODE = 1
4937 05:53:29.301730 DLL_IDLE_MODE = 1
4938 05:53:29.305176 LP45_APHY_COMB_EN = 1
4939 05:53:29.308270 TX_ODT_DIS = 1
4940 05:53:29.308808 NEW_8X_MODE = 1
4941 05:53:29.311854 ===================================
4942 05:53:29.315015 ===================================
4943 05:53:29.318005 data_rate = 1866
4944 05:53:29.321512 CKR = 1
4945 05:53:29.324734 DQ_P2S_RATIO = 8
4946 05:53:29.328012 ===================================
4947 05:53:29.331537 CA_P2S_RATIO = 8
4948 05:53:29.334616 DQ_CA_OPEN = 0
4949 05:53:29.335042 DQ_SEMI_OPEN = 0
4950 05:53:29.338318 CA_SEMI_OPEN = 0
4951 05:53:29.341185 CA_FULL_RATE = 0
4952 05:53:29.344560 DQ_CKDIV4_EN = 1
4953 05:53:29.348458 CA_CKDIV4_EN = 1
4954 05:53:29.351177 CA_PREDIV_EN = 0
4955 05:53:29.351658 PH8_DLY = 0
4956 05:53:29.354893 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4957 05:53:29.357990 DQ_AAMCK_DIV = 4
4958 05:53:29.361472 CA_AAMCK_DIV = 4
4959 05:53:29.364926 CA_ADMCK_DIV = 4
4960 05:53:29.368045 DQ_TRACK_CA_EN = 0
4961 05:53:29.371155 CA_PICK = 933
4962 05:53:29.371635 CA_MCKIO = 933
4963 05:53:29.374581 MCKIO_SEMI = 0
4964 05:53:29.377916 PLL_FREQ = 3732
4965 05:53:29.381320 DQ_UI_PI_RATIO = 32
4966 05:53:29.384684 CA_UI_PI_RATIO = 0
4967 05:53:29.387723 ===================================
4968 05:53:29.391081 ===================================
4969 05:53:29.394317 memory_type:LPDDR4
4970 05:53:29.394749 GP_NUM : 10
4971 05:53:29.398100 SRAM_EN : 1
4972 05:53:29.398638 MD32_EN : 0
4973 05:53:29.400945 ===================================
4974 05:53:29.404594 [ANA_INIT] >>>>>>>>>>>>>>
4975 05:53:29.408057 <<<<<< [CONFIGURE PHASE]: ANA_TX
4976 05:53:29.411106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4977 05:53:29.414310 ===================================
4978 05:53:29.418178 data_rate = 1866,PCW = 0X8f00
4979 05:53:29.421133 ===================================
4980 05:53:29.424134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4981 05:53:29.427695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4982 05:53:29.434352 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4983 05:53:29.440721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4984 05:53:29.444121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4985 05:53:29.447934 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4986 05:53:29.448488 [ANA_INIT] flow start
4987 05:53:29.450959 [ANA_INIT] PLL >>>>>>>>
4988 05:53:29.454527 [ANA_INIT] PLL <<<<<<<<
4989 05:53:29.455067 [ANA_INIT] MIDPI >>>>>>>>
4990 05:53:29.457821 [ANA_INIT] MIDPI <<<<<<<<
4991 05:53:29.461215 [ANA_INIT] DLL >>>>>>>>
4992 05:53:29.461751 [ANA_INIT] flow end
4993 05:53:29.467695 ============ LP4 DIFF to SE enter ============
4994 05:53:29.470444 ============ LP4 DIFF to SE exit ============
4995 05:53:29.474442 [ANA_INIT] <<<<<<<<<<<<<
4996 05:53:29.474973 [Flow] Enable top DCM control >>>>>
4997 05:53:29.477608 [Flow] Enable top DCM control <<<<<
4998 05:53:29.480645 Enable DLL master slave shuffle
4999 05:53:29.486933 ==============================================================
5000 05:53:29.490386 Gating Mode config
5001 05:53:29.493706 ==============================================================
5002 05:53:29.497015 Config description:
5003 05:53:29.507408 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5004 05:53:29.514207 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5005 05:53:29.517646 SELPH_MODE 0: By rank 1: By Phase
5006 05:53:29.523573 ==============================================================
5007 05:53:29.527040 GAT_TRACK_EN = 1
5008 05:53:29.530737 RX_GATING_MODE = 2
5009 05:53:29.533935 RX_GATING_TRACK_MODE = 2
5010 05:53:29.534610 SELPH_MODE = 1
5011 05:53:29.537124 PICG_EARLY_EN = 1
5012 05:53:29.540590 VALID_LAT_VALUE = 1
5013 05:53:29.547102 ==============================================================
5014 05:53:29.550404 Enter into Gating configuration >>>>
5015 05:53:29.553716 Exit from Gating configuration <<<<
5016 05:53:29.557213 Enter into DVFS_PRE_config >>>>>
5017 05:53:29.566938 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5018 05:53:29.570569 Exit from DVFS_PRE_config <<<<<
5019 05:53:29.573845 Enter into PICG configuration >>>>
5020 05:53:29.577113 Exit from PICG configuration <<<<
5021 05:53:29.580642 [RX_INPUT] configuration >>>>>
5022 05:53:29.583657 [RX_INPUT] configuration <<<<<
5023 05:53:29.586843 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5024 05:53:29.593656 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5025 05:53:29.600378 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5026 05:53:29.607081 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5027 05:53:29.613773 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5028 05:53:29.616910 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5029 05:53:29.623440 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5030 05:53:29.626673 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5031 05:53:29.630124 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5032 05:53:29.633724 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5033 05:53:29.636931 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5034 05:53:29.643252 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5035 05:53:29.646828 ===================================
5036 05:53:29.649867 LPDDR4 DRAM CONFIGURATION
5037 05:53:29.653096 ===================================
5038 05:53:29.653529 EX_ROW_EN[0] = 0x0
5039 05:53:29.656534 EX_ROW_EN[1] = 0x0
5040 05:53:29.657104 LP4Y_EN = 0x0
5041 05:53:29.659722 WORK_FSP = 0x0
5042 05:53:29.660148 WL = 0x3
5043 05:53:29.663309 RL = 0x3
5044 05:53:29.663768 BL = 0x2
5045 05:53:29.666970 RPST = 0x0
5046 05:53:29.667541 RD_PRE = 0x0
5047 05:53:29.669612 WR_PRE = 0x1
5048 05:53:29.670080 WR_PST = 0x0
5049 05:53:29.673327 DBI_WR = 0x0
5050 05:53:29.673796 DBI_RD = 0x0
5051 05:53:29.676623 OTF = 0x1
5052 05:53:29.679971 ===================================
5053 05:53:29.683355 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5054 05:53:29.686628 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5055 05:53:29.693622 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5056 05:53:29.697003 ===================================
5057 05:53:29.697539 LPDDR4 DRAM CONFIGURATION
5058 05:53:29.699827 ===================================
5059 05:53:29.702993 EX_ROW_EN[0] = 0x10
5060 05:53:29.706628 EX_ROW_EN[1] = 0x0
5061 05:53:29.707123 LP4Y_EN = 0x0
5062 05:53:29.709920 WORK_FSP = 0x0
5063 05:53:29.710367 WL = 0x3
5064 05:53:29.713397 RL = 0x3
5065 05:53:29.713927 BL = 0x2
5066 05:53:29.716420 RPST = 0x0
5067 05:53:29.716843 RD_PRE = 0x0
5068 05:53:29.719801 WR_PRE = 0x1
5069 05:53:29.720240 WR_PST = 0x0
5070 05:53:29.722976 DBI_WR = 0x0
5071 05:53:29.723401 DBI_RD = 0x0
5072 05:53:29.726463 OTF = 0x1
5073 05:53:29.730030 ===================================
5074 05:53:29.736036 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5075 05:53:29.739708 nWR fixed to 30
5076 05:53:29.740157 [ModeRegInit_LP4] CH0 RK0
5077 05:53:29.743465 [ModeRegInit_LP4] CH0 RK1
5078 05:53:29.746348 [ModeRegInit_LP4] CH1 RK0
5079 05:53:29.749550 [ModeRegInit_LP4] CH1 RK1
5080 05:53:29.750073 match AC timing 9
5081 05:53:29.756588 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5082 05:53:29.759664 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5083 05:53:29.762716 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5084 05:53:29.769332 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5085 05:53:29.772678 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5086 05:53:29.773112 ==
5087 05:53:29.775894 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 05:53:29.779674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 05:53:29.780207 ==
5090 05:53:29.785992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5091 05:53:29.793321 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5092 05:53:29.796263 [CA 0] Center 38 (7~69) winsize 63
5093 05:53:29.799312 [CA 1] Center 38 (8~69) winsize 62
5094 05:53:29.802757 [CA 2] Center 35 (5~66) winsize 62
5095 05:53:29.806317 [CA 3] Center 35 (5~66) winsize 62
5096 05:53:29.809297 [CA 4] Center 34 (4~65) winsize 62
5097 05:53:29.812942 [CA 5] Center 33 (3~64) winsize 62
5098 05:53:29.813438
5099 05:53:29.815973 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5100 05:53:29.816403
5101 05:53:29.819319 [CATrainingPosCal] consider 1 rank data
5102 05:53:29.822648 u2DelayCellTimex100 = 270/100 ps
5103 05:53:29.825826 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5104 05:53:29.829581 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5105 05:53:29.832429 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5106 05:53:29.836230 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5107 05:53:29.839141 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5108 05:53:29.842494 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5109 05:53:29.842945
5110 05:53:29.849163 CA PerBit enable=1, Macro0, CA PI delay=33
5111 05:53:29.849653
5112 05:53:29.850031 [CBTSetCACLKResult] CA Dly = 33
5113 05:53:29.852421 CS Dly: 7 (0~38)
5114 05:53:29.852846 ==
5115 05:53:29.855810 Dram Type= 6, Freq= 0, CH_0, rank 1
5116 05:53:29.859020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 05:53:29.859515 ==
5118 05:53:29.865628 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5119 05:53:29.872175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5120 05:53:29.875496 [CA 0] Center 38 (8~69) winsize 62
5121 05:53:29.878726 [CA 1] Center 38 (8~69) winsize 62
5122 05:53:29.882388 [CA 2] Center 36 (6~66) winsize 61
5123 05:53:29.885695 [CA 3] Center 35 (5~66) winsize 62
5124 05:53:29.889269 [CA 4] Center 34 (4~65) winsize 62
5125 05:53:29.892431 [CA 5] Center 34 (4~65) winsize 62
5126 05:53:29.892901
5127 05:53:29.895653 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5128 05:53:29.896078
5129 05:53:29.899214 [CATrainingPosCal] consider 2 rank data
5130 05:53:29.902315 u2DelayCellTimex100 = 270/100 ps
5131 05:53:29.905484 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5132 05:53:29.909002 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5133 05:53:29.912310 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5134 05:53:29.915382 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5135 05:53:29.918720 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5136 05:53:29.925543 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5137 05:53:29.926109
5138 05:53:29.928792 CA PerBit enable=1, Macro0, CA PI delay=34
5139 05:53:29.929326
5140 05:53:29.932133 [CBTSetCACLKResult] CA Dly = 34
5141 05:53:29.932558 CS Dly: 8 (0~40)
5142 05:53:29.932893
5143 05:53:29.935049 ----->DramcWriteLeveling(PI) begin...
5144 05:53:29.935478 ==
5145 05:53:29.938819 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 05:53:29.945611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 05:53:29.946187 ==
5148 05:53:29.949055 Write leveling (Byte 0): 35 => 35
5149 05:53:29.949581 Write leveling (Byte 1): 30 => 30
5150 05:53:29.952162 DramcWriteLeveling(PI) end<-----
5151 05:53:29.952585
5152 05:53:29.952922 ==
5153 05:53:29.955636 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 05:53:29.962295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 05:53:29.962841 ==
5156 05:53:29.964996 [Gating] SW mode calibration
5157 05:53:29.971837 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5158 05:53:29.974991 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5159 05:53:29.982042 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5160 05:53:29.985157 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 05:53:29.988640 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 05:53:29.995144 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 05:53:29.998098 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 05:53:30.001659 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 05:53:30.008335 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5166 05:53:30.011701 0 14 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
5167 05:53:30.014970 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5168 05:53:30.021365 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 05:53:30.024630 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 05:53:30.028149 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 05:53:30.034545 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 05:53:30.038072 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 05:53:30.041559 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5174 05:53:30.047797 0 15 28 | B1->B0 | 2a2a 4242 | 0 1 | (1 1) (0 0)
5175 05:53:30.051291 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 05:53:30.054551 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 05:53:30.057798 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 05:53:30.064469 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 05:53:30.068010 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 05:53:30.071332 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 05:53:30.078060 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5182 05:53:30.081297 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5183 05:53:30.084157 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5184 05:53:30.090941 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 05:53:30.094247 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 05:53:30.097471 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 05:53:30.104106 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 05:53:30.107749 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 05:53:30.110654 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 05:53:30.117334 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 05:53:30.121007 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 05:53:30.124242 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 05:53:30.130633 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 05:53:30.134080 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 05:53:30.137091 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 05:53:30.144010 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 05:53:30.147194 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 05:53:30.150727 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5199 05:53:30.157121 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5200 05:53:30.157648 Total UI for P1: 0, mck2ui 16
5201 05:53:30.163841 best dqsien dly found for B0: ( 1, 2, 28)
5202 05:53:30.167480 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 05:53:30.170605 Total UI for P1: 0, mck2ui 16
5204 05:53:30.173999 best dqsien dly found for B1: ( 1, 3, 0)
5205 05:53:30.177161 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5206 05:53:30.180829 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5207 05:53:30.181359
5208 05:53:30.183911 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5209 05:53:30.187136 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5210 05:53:30.190268 [Gating] SW calibration Done
5211 05:53:30.190695 ==
5212 05:53:30.193792 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 05:53:30.197233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 05:53:30.197664 ==
5215 05:53:30.200239 RX Vref Scan: 0
5216 05:53:30.200663
5217 05:53:30.203903 RX Vref 0 -> 0, step: 1
5218 05:53:30.204332
5219 05:53:30.204675 RX Delay -80 -> 252, step: 8
5220 05:53:30.210625 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5221 05:53:30.213568 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5222 05:53:30.217187 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5223 05:53:30.220556 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5224 05:53:30.223822 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5225 05:53:30.230451 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5226 05:53:30.233532 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5227 05:53:30.237300 iDelay=208, Bit 7, Center 119 (32 ~ 207) 176
5228 05:53:30.240661 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5229 05:53:30.243829 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5230 05:53:30.246831 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5231 05:53:30.253698 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5232 05:53:30.257405 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5233 05:53:30.260546 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5234 05:53:30.264236 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5235 05:53:30.266801 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5236 05:53:30.267232 ==
5237 05:53:30.270528 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 05:53:30.277135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 05:53:30.277567 ==
5240 05:53:30.277909 DQS Delay:
5241 05:53:30.280031 DQS0 = 0, DQS1 = 0
5242 05:53:30.280459 DQM Delay:
5243 05:53:30.280797 DQM0 = 107, DQM1 = 90
5244 05:53:30.283788 DQ Delay:
5245 05:53:30.287144 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5246 05:53:30.290194 DQ4 =107, DQ5 =91, DQ6 =119, DQ7 =119
5247 05:53:30.293387 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5248 05:53:30.296753 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =99
5249 05:53:30.297181
5250 05:53:30.297519
5251 05:53:30.297832 ==
5252 05:53:30.300083 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 05:53:30.303586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 05:53:30.304018 ==
5255 05:53:30.304359
5256 05:53:30.304675
5257 05:53:30.306906 TX Vref Scan disable
5258 05:53:30.309814 == TX Byte 0 ==
5259 05:53:30.313522 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5260 05:53:30.316551 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5261 05:53:30.319961 == TX Byte 1 ==
5262 05:53:30.323456 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5263 05:53:30.327249 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5264 05:53:30.327781 ==
5265 05:53:30.330591 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 05:53:30.336577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 05:53:30.337104 ==
5268 05:53:30.337452
5269 05:53:30.337765
5270 05:53:30.338174 TX Vref Scan disable
5271 05:53:30.340641 == TX Byte 0 ==
5272 05:53:30.344018 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5273 05:53:30.350890 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5274 05:53:30.351344 == TX Byte 1 ==
5275 05:53:30.353674 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5276 05:53:30.360560 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5277 05:53:30.361053
5278 05:53:30.361425 [DATLAT]
5279 05:53:30.361746 Freq=933, CH0 RK0
5280 05:53:30.362286
5281 05:53:30.363710 DATLAT Default: 0xd
5282 05:53:30.364134 0, 0xFFFF, sum = 0
5283 05:53:30.367103 1, 0xFFFF, sum = 0
5284 05:53:30.367586 2, 0xFFFF, sum = 0
5285 05:53:30.370723 3, 0xFFFF, sum = 0
5286 05:53:30.371257 4, 0xFFFF, sum = 0
5287 05:53:30.373752 5, 0xFFFF, sum = 0
5288 05:53:30.377481 6, 0xFFFF, sum = 0
5289 05:53:30.377909 7, 0xFFFF, sum = 0
5290 05:53:30.380591 8, 0xFFFF, sum = 0
5291 05:53:30.381123 9, 0xFFFF, sum = 0
5292 05:53:30.384152 10, 0x0, sum = 1
5293 05:53:30.384689 11, 0x0, sum = 2
5294 05:53:30.385092 12, 0x0, sum = 3
5295 05:53:30.387253 13, 0x0, sum = 4
5296 05:53:30.387803 best_step = 11
5297 05:53:30.388149
5298 05:53:30.388502 ==
5299 05:53:30.390399 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 05:53:30.397087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 05:53:30.397558 ==
5302 05:53:30.397898 RX Vref Scan: 1
5303 05:53:30.398273
5304 05:53:30.400340 RX Vref 0 -> 0, step: 1
5305 05:53:30.400762
5306 05:53:30.403705 RX Delay -53 -> 252, step: 4
5307 05:53:30.404261
5308 05:53:30.407218 Set Vref, RX VrefLevel [Byte0]: 58
5309 05:53:30.410369 [Byte1]: 54
5310 05:53:30.410808
5311 05:53:30.414005 Final RX Vref Byte 0 = 58 to rank0
5312 05:53:30.417043 Final RX Vref Byte 1 = 54 to rank0
5313 05:53:30.420338 Final RX Vref Byte 0 = 58 to rank1
5314 05:53:30.423358 Final RX Vref Byte 1 = 54 to rank1==
5315 05:53:30.426836 Dram Type= 6, Freq= 0, CH_0, rank 0
5316 05:53:30.430010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 05:53:30.430446 ==
5318 05:53:30.433747 DQS Delay:
5319 05:53:30.434221 DQS0 = 0, DQS1 = 0
5320 05:53:30.437128 DQM Delay:
5321 05:53:30.437630 DQM0 = 107, DQM1 = 92
5322 05:53:30.440292 DQ Delay:
5323 05:53:30.443453 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5324 05:53:30.446825 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =114
5325 05:53:30.450265 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =90
5326 05:53:30.453316 DQ12 =98, DQ13 =92, DQ14 =100, DQ15 =98
5327 05:53:30.453929
5328 05:53:30.454530
5329 05:53:30.459857 [DQSOSCAuto] RK0, (LSB)MR18= 0x2421, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5330 05:53:30.463074 CH0 RK0: MR19=505, MR18=2421
5331 05:53:30.470072 CH0_RK0: MR19=0x505, MR18=0x2421, DQSOSC=410, MR23=63, INC=64, DEC=42
5332 05:53:30.470514
5333 05:53:30.473117 ----->DramcWriteLeveling(PI) begin...
5334 05:53:30.473561 ==
5335 05:53:30.476432 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 05:53:30.479797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 05:53:30.480232 ==
5338 05:53:30.482938 Write leveling (Byte 0): 30 => 30
5339 05:53:30.486351 Write leveling (Byte 1): 30 => 30
5340 05:53:30.489544 DramcWriteLeveling(PI) end<-----
5341 05:53:30.490219
5342 05:53:30.490588 ==
5343 05:53:30.492955 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 05:53:30.496088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 05:53:30.499718 ==
5346 05:53:30.500191 [Gating] SW mode calibration
5347 05:53:30.509433 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5348 05:53:30.512396 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5349 05:53:30.515984 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 05:53:30.522482 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 05:53:30.525558 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 05:53:30.528826 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 05:53:30.535324 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 05:53:30.538703 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 05:53:30.542263 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5356 05:53:30.548289 0 14 28 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5357 05:53:30.551648 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5358 05:53:30.555105 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 05:53:30.561796 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 05:53:30.565100 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 05:53:30.568657 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 05:53:30.575174 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 05:53:30.578684 0 15 24 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
5364 05:53:30.581714 0 15 28 | B1->B0 | 3a3a 4444 | 0 0 | (1 1) (0 0)
5365 05:53:30.588056 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 05:53:30.591681 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 05:53:30.595010 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 05:53:30.601184 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 05:53:30.604815 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 05:53:30.608323 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 05:53:30.615058 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 05:53:30.617921 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5373 05:53:30.621136 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5374 05:53:30.628175 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 05:53:30.631363 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 05:53:30.634409 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 05:53:30.641447 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 05:53:30.644830 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 05:53:30.648158 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 05:53:30.654539 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 05:53:30.658300 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 05:53:30.661431 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 05:53:30.668028 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 05:53:30.671666 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 05:53:30.674702 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 05:53:30.681823 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 05:53:30.685128 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 05:53:30.688102 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5389 05:53:30.694727 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 05:53:30.695262 Total UI for P1: 0, mck2ui 16
5391 05:53:30.698087 best dqsien dly found for B0: ( 1, 2, 28)
5392 05:53:30.701472 Total UI for P1: 0, mck2ui 16
5393 05:53:30.704852 best dqsien dly found for B1: ( 1, 2, 28)
5394 05:53:30.707623 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5395 05:53:30.714860 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5396 05:53:30.715291
5397 05:53:30.717831 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5398 05:53:30.721387 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5399 05:53:30.724630 [Gating] SW calibration Done
5400 05:53:30.725058 ==
5401 05:53:30.727940 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 05:53:30.731070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 05:53:30.731504 ==
5404 05:53:30.734390 RX Vref Scan: 0
5405 05:53:30.734819
5406 05:53:30.735160 RX Vref 0 -> 0, step: 1
5407 05:53:30.735516
5408 05:53:30.737605 RX Delay -80 -> 252, step: 8
5409 05:53:30.740882 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5410 05:53:30.744405 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5411 05:53:30.751074 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5412 05:53:30.754343 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5413 05:53:30.757722 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5414 05:53:30.760633 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5415 05:53:30.764237 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5416 05:53:30.770543 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5417 05:53:30.774363 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5418 05:53:30.777669 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5419 05:53:30.781021 iDelay=208, Bit 10, Center 87 (0 ~ 175) 176
5420 05:53:30.783948 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5421 05:53:30.786999 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5422 05:53:30.793631 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5423 05:53:30.797141 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5424 05:53:30.800282 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5425 05:53:30.800475 ==
5426 05:53:30.803792 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 05:53:30.806885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 05:53:30.807118 ==
5429 05:53:30.810222 DQS Delay:
5430 05:53:30.810402 DQS0 = 0, DQS1 = 0
5431 05:53:30.810512 DQM Delay:
5432 05:53:30.813594 DQM0 = 103, DQM1 = 90
5433 05:53:30.813751 DQ Delay:
5434 05:53:30.816976 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5435 05:53:30.819909 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5436 05:53:30.823524 DQ8 =83, DQ9 =83, DQ10 =87, DQ11 =87
5437 05:53:30.826902 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5438 05:53:30.826987
5439 05:53:30.827053
5440 05:53:30.830163 ==
5441 05:53:30.830249 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 05:53:30.836655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 05:53:30.836741 ==
5444 05:53:30.836809
5445 05:53:30.836872
5446 05:53:30.839875 TX Vref Scan disable
5447 05:53:30.839981 == TX Byte 0 ==
5448 05:53:30.843679 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5449 05:53:30.850122 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5450 05:53:30.850626 == TX Byte 1 ==
5451 05:53:30.853629 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5452 05:53:30.860488 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5453 05:53:30.860952 ==
5454 05:53:30.863833 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 05:53:30.866751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 05:53:30.867225 ==
5457 05:53:30.867575
5458 05:53:30.867891
5459 05:53:30.870500 TX Vref Scan disable
5460 05:53:30.873532 == TX Byte 0 ==
5461 05:53:30.876626 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5462 05:53:30.880233 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5463 05:53:30.883174 == TX Byte 1 ==
5464 05:53:30.886445 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5465 05:53:30.890091 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5466 05:53:30.890277
5467 05:53:30.893292 [DATLAT]
5468 05:53:30.893468 Freq=933, CH0 RK1
5469 05:53:30.893677
5470 05:53:30.896942 DATLAT Default: 0xb
5471 05:53:30.897118 0, 0xFFFF, sum = 0
5472 05:53:30.899764 1, 0xFFFF, sum = 0
5473 05:53:30.899910 2, 0xFFFF, sum = 0
5474 05:53:30.903274 3, 0xFFFF, sum = 0
5475 05:53:30.903455 4, 0xFFFF, sum = 0
5476 05:53:30.906590 5, 0xFFFF, sum = 0
5477 05:53:30.906696 6, 0xFFFF, sum = 0
5478 05:53:30.909779 7, 0xFFFF, sum = 0
5479 05:53:30.909888 8, 0xFFFF, sum = 0
5480 05:53:30.913198 9, 0xFFFF, sum = 0
5481 05:53:30.913301 10, 0x0, sum = 1
5482 05:53:30.916692 11, 0x0, sum = 2
5483 05:53:30.916787 12, 0x0, sum = 3
5484 05:53:30.919684 13, 0x0, sum = 4
5485 05:53:30.919806 best_step = 11
5486 05:53:30.919904
5487 05:53:30.919997 ==
5488 05:53:30.923035 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 05:53:30.926387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 05:53:30.929914 ==
5491 05:53:30.930078 RX Vref Scan: 0
5492 05:53:30.930154
5493 05:53:30.933087 RX Vref 0 -> 0, step: 1
5494 05:53:30.933171
5495 05:53:30.936708 RX Delay -53 -> 252, step: 4
5496 05:53:30.939958 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5497 05:53:30.943256 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5498 05:53:30.949790 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5499 05:53:30.953123 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5500 05:53:30.956154 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5501 05:53:30.959563 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5502 05:53:30.963074 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5503 05:53:30.966112 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5504 05:53:30.972639 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5505 05:53:30.976465 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5506 05:53:30.979415 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5507 05:53:30.983020 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5508 05:53:30.986294 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5509 05:53:30.992758 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5510 05:53:30.996147 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5511 05:53:30.999336 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5512 05:53:30.999493 ==
5513 05:53:31.002424 Dram Type= 6, Freq= 0, CH_0, rank 1
5514 05:53:31.006218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 05:53:31.006375 ==
5516 05:53:31.009390 DQS Delay:
5517 05:53:31.009567 DQS0 = 0, DQS1 = 0
5518 05:53:31.012343 DQM Delay:
5519 05:53:31.012498 DQM0 = 104, DQM1 = 92
5520 05:53:31.012622 DQ Delay:
5521 05:53:31.015820 DQ0 =102, DQ1 =106, DQ2 =100, DQ3 =98
5522 05:53:31.019115 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5523 05:53:31.022531 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =92
5524 05:53:31.025833 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =98
5525 05:53:31.029064
5526 05:53:31.029251
5527 05:53:31.035872 [DQSOSCAuto] RK1, (LSB)MR18= 0x2405, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 410 ps
5528 05:53:31.039002 CH0 RK1: MR19=505, MR18=2405
5529 05:53:31.045720 CH0_RK1: MR19=0x505, MR18=0x2405, DQSOSC=410, MR23=63, INC=64, DEC=42
5530 05:53:31.049202 [RxdqsGatingPostProcess] freq 933
5531 05:53:31.052475 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5532 05:53:31.055766 best DQS0 dly(2T, 0.5T) = (0, 10)
5533 05:53:31.059086 best DQS1 dly(2T, 0.5T) = (0, 11)
5534 05:53:31.062754 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5535 05:53:31.065681 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5536 05:53:31.068964 best DQS0 dly(2T, 0.5T) = (0, 10)
5537 05:53:31.072218 best DQS1 dly(2T, 0.5T) = (0, 10)
5538 05:53:31.075467 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5539 05:53:31.078881 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5540 05:53:31.082158 Pre-setting of DQS Precalculation
5541 05:53:31.085486 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5542 05:53:31.085588 ==
5543 05:53:31.088841 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 05:53:31.095737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 05:53:31.095840 ==
5546 05:53:31.098911 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5547 05:53:31.105649 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5548 05:53:31.109094 [CA 0] Center 37 (7~68) winsize 62
5549 05:53:31.112417 [CA 1] Center 37 (7~68) winsize 62
5550 05:53:31.115360 [CA 2] Center 36 (6~66) winsize 61
5551 05:53:31.118624 [CA 3] Center 34 (4~65) winsize 62
5552 05:53:31.122157 [CA 4] Center 35 (4~66) winsize 63
5553 05:53:31.125537 [CA 5] Center 34 (4~65) winsize 62
5554 05:53:31.125649
5555 05:53:31.128646 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5556 05:53:31.128748
5557 05:53:31.131954 [CATrainingPosCal] consider 1 rank data
5558 05:53:31.135322 u2DelayCellTimex100 = 270/100 ps
5559 05:53:31.138533 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5560 05:53:31.141847 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5561 05:53:31.145263 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5562 05:53:31.152133 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5563 05:53:31.155377 CA4 delay=35 (4~66),Diff = 1 PI (6 cell)
5564 05:53:31.158794 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5565 05:53:31.158885
5566 05:53:31.161864 CA PerBit enable=1, Macro0, CA PI delay=34
5567 05:53:31.161987
5568 05:53:31.165340 [CBTSetCACLKResult] CA Dly = 34
5569 05:53:31.165433 CS Dly: 6 (0~37)
5570 05:53:31.165523 ==
5571 05:53:31.168328 Dram Type= 6, Freq= 0, CH_1, rank 1
5572 05:53:31.175007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 05:53:31.175101 ==
5574 05:53:31.178456 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5575 05:53:31.185111 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5576 05:53:31.188578 [CA 0] Center 37 (7~68) winsize 62
5577 05:53:31.191430 [CA 1] Center 38 (8~69) winsize 62
5578 05:53:31.195186 [CA 2] Center 35 (5~66) winsize 62
5579 05:53:31.198726 [CA 3] Center 35 (5~65) winsize 61
5580 05:53:31.201909 [CA 4] Center 35 (5~65) winsize 61
5581 05:53:31.205250 [CA 5] Center 34 (5~64) winsize 60
5582 05:53:31.205376
5583 05:53:31.208231 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5584 05:53:31.208372
5585 05:53:31.211911 [CATrainingPosCal] consider 2 rank data
5586 05:53:31.215004 u2DelayCellTimex100 = 270/100 ps
5587 05:53:31.218080 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5588 05:53:31.224965 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5589 05:53:31.228457 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5590 05:53:31.231453 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5591 05:53:31.234806 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5592 05:53:31.238013 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5593 05:53:31.238224
5594 05:53:31.241838 CA PerBit enable=1, Macro0, CA PI delay=34
5595 05:53:31.242080
5596 05:53:31.244834 [CBTSetCACLKResult] CA Dly = 34
5597 05:53:31.245045 CS Dly: 7 (0~39)
5598 05:53:31.245211
5599 05:53:31.248411 ----->DramcWriteLeveling(PI) begin...
5600 05:53:31.251764 ==
5601 05:53:31.254665 Dram Type= 6, Freq= 0, CH_1, rank 0
5602 05:53:31.257970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 05:53:31.258099 ==
5604 05:53:31.261741 Write leveling (Byte 0): 28 => 28
5605 05:53:31.264678 Write leveling (Byte 1): 31 => 31
5606 05:53:31.268135 DramcWriteLeveling(PI) end<-----
5607 05:53:31.268242
5608 05:53:31.268323 ==
5609 05:53:31.271225 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 05:53:31.274761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 05:53:31.274853 ==
5612 05:53:31.278215 [Gating] SW mode calibration
5613 05:53:31.284840 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5614 05:53:31.291360 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5615 05:53:31.294780 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 05:53:31.298406 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 05:53:31.301766 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 05:53:31.308351 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 05:53:31.311694 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 05:53:31.315259 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5621 05:53:31.321574 0 14 24 | B1->B0 | 3131 2e2e | 0 1 | (0 0) (1 0)
5622 05:53:31.325031 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
5623 05:53:31.328278 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 05:53:31.334944 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 05:53:31.338304 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 05:53:31.341522 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 05:53:31.348387 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 05:53:31.351426 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 05:53:31.354725 0 15 24 | B1->B0 | 2828 2828 | 0 0 | (1 1) (0 0)
5630 05:53:31.361252 0 15 28 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
5631 05:53:31.364692 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 05:53:31.368092 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 05:53:31.374573 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 05:53:31.378151 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 05:53:31.381168 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 05:53:31.387911 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5637 05:53:31.391229 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5638 05:53:31.394556 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 05:53:31.401179 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 05:53:31.404660 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 05:53:31.408076 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 05:53:31.414819 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 05:53:31.417772 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 05:53:31.421528 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 05:53:31.428002 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 05:53:31.431090 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 05:53:31.434620 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 05:53:31.441255 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 05:53:31.444660 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 05:53:31.448125 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 05:53:31.454651 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 05:53:31.457688 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5653 05:53:31.461341 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5654 05:53:31.464432 Total UI for P1: 0, mck2ui 16
5655 05:53:31.467717 best dqsien dly found for B0: ( 1, 2, 20)
5656 05:53:31.471066 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5657 05:53:31.477656 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 05:53:31.481211 Total UI for P1: 0, mck2ui 16
5659 05:53:31.484523 best dqsien dly found for B1: ( 1, 2, 26)
5660 05:53:31.487951 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5661 05:53:31.490756 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5662 05:53:31.491190
5663 05:53:31.494643 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5664 05:53:31.497906 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5665 05:53:31.501172 [Gating] SW calibration Done
5666 05:53:31.501740 ==
5667 05:53:31.504673 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 05:53:31.508208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 05:53:31.508780 ==
5670 05:53:31.511499 RX Vref Scan: 0
5671 05:53:31.512070
5672 05:53:31.512450 RX Vref 0 -> 0, step: 1
5673 05:53:31.514141
5674 05:53:31.514776 RX Delay -80 -> 252, step: 8
5675 05:53:31.521338 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5676 05:53:31.524649 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5677 05:53:31.527976 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5678 05:53:31.531350 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5679 05:53:31.534170 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5680 05:53:31.537777 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5681 05:53:31.544623 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5682 05:53:31.547692 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5683 05:53:31.550935 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5684 05:53:31.554337 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5685 05:53:31.557361 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5686 05:53:31.560875 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5687 05:53:31.567208 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5688 05:53:31.571054 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5689 05:53:31.574514 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5690 05:53:31.577707 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5691 05:53:31.578310 ==
5692 05:53:31.580991 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 05:53:31.583804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 05:53:31.587153 ==
5695 05:53:31.587672 DQS Delay:
5696 05:53:31.588048 DQS0 = 0, DQS1 = 0
5697 05:53:31.590651 DQM Delay:
5698 05:53:31.591126 DQM0 = 102, DQM1 = 94
5699 05:53:31.593695 DQ Delay:
5700 05:53:31.597094 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5701 05:53:31.600548 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5702 05:53:31.603856 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5703 05:53:31.607095 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5704 05:53:31.607574
5705 05:53:31.607947
5706 05:53:31.608296 ==
5707 05:53:31.610711 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 05:53:31.613830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 05:53:31.614340 ==
5710 05:53:31.614736
5711 05:53:31.615087
5712 05:53:31.616883 TX Vref Scan disable
5713 05:53:31.617461 == TX Byte 0 ==
5714 05:53:31.623790 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5715 05:53:31.627221 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5716 05:53:31.627767 == TX Byte 1 ==
5717 05:53:31.633259 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5718 05:53:31.637138 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5719 05:53:31.637637 ==
5720 05:53:31.640140 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 05:53:31.643366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 05:53:31.643934 ==
5723 05:53:31.644340
5724 05:53:31.646578
5725 05:53:31.647037 TX Vref Scan disable
5726 05:53:31.650243 == TX Byte 0 ==
5727 05:53:31.653158 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5728 05:53:31.656620 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5729 05:53:31.660191 == TX Byte 1 ==
5730 05:53:31.663619 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5731 05:53:31.669885 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5732 05:53:31.670430
5733 05:53:31.670894 [DATLAT]
5734 05:53:31.671314 Freq=933, CH1 RK0
5735 05:53:31.671645
5736 05:53:31.673085 DATLAT Default: 0xd
5737 05:53:31.673512 0, 0xFFFF, sum = 0
5738 05:53:31.676446 1, 0xFFFF, sum = 0
5739 05:53:31.676944 2, 0xFFFF, sum = 0
5740 05:53:31.679731 3, 0xFFFF, sum = 0
5741 05:53:31.683361 4, 0xFFFF, sum = 0
5742 05:53:31.683801 5, 0xFFFF, sum = 0
5743 05:53:31.686704 6, 0xFFFF, sum = 0
5744 05:53:31.687157 7, 0xFFFF, sum = 0
5745 05:53:31.689929 8, 0xFFFF, sum = 0
5746 05:53:31.690404 9, 0xFFFF, sum = 0
5747 05:53:31.692937 10, 0x0, sum = 1
5748 05:53:31.693372 11, 0x0, sum = 2
5749 05:53:31.696785 12, 0x0, sum = 3
5750 05:53:31.697271 13, 0x0, sum = 4
5751 05:53:31.697700 best_step = 11
5752 05:53:31.698068
5753 05:53:31.699651 ==
5754 05:53:31.703131 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 05:53:31.706233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 05:53:31.706663 ==
5757 05:53:31.707004 RX Vref Scan: 1
5758 05:53:31.707398
5759 05:53:31.709992 RX Vref 0 -> 0, step: 1
5760 05:53:31.710419
5761 05:53:31.712881 RX Delay -53 -> 252, step: 4
5762 05:53:31.713310
5763 05:53:31.715981 Set Vref, RX VrefLevel [Byte0]: 52
5764 05:53:31.719523 [Byte1]: 48
5765 05:53:31.719951
5766 05:53:31.723152 Final RX Vref Byte 0 = 52 to rank0
5767 05:53:31.726344 Final RX Vref Byte 1 = 48 to rank0
5768 05:53:31.729220 Final RX Vref Byte 0 = 52 to rank1
5769 05:53:31.732696 Final RX Vref Byte 1 = 48 to rank1==
5770 05:53:31.736126 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 05:53:31.739626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 05:53:31.742524 ==
5773 05:53:31.742954 DQS Delay:
5774 05:53:31.743295 DQS0 = 0, DQS1 = 0
5775 05:53:31.746287 DQM Delay:
5776 05:53:31.746720 DQM0 = 103, DQM1 = 96
5777 05:53:31.749108 DQ Delay:
5778 05:53:31.752895 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5779 05:53:31.756245 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =100
5780 05:53:31.759486 DQ8 =84, DQ9 =86, DQ10 =102, DQ11 =90
5781 05:53:31.762558 DQ12 =104, DQ13 =102, DQ14 =106, DQ15 =100
5782 05:53:31.762994
5783 05:53:31.763335
5784 05:53:31.769156 [DQSOSCAuto] RK0, (LSB)MR18= 0x152d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 415 ps
5785 05:53:31.772428 CH1 RK0: MR19=505, MR18=152D
5786 05:53:31.779208 CH1_RK0: MR19=0x505, MR18=0x152D, DQSOSC=407, MR23=63, INC=65, DEC=43
5787 05:53:31.779786
5788 05:53:31.782419 ----->DramcWriteLeveling(PI) begin...
5789 05:53:31.782862 ==
5790 05:53:31.785868 Dram Type= 6, Freq= 0, CH_1, rank 1
5791 05:53:31.789317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 05:53:31.789749 ==
5793 05:53:31.792491 Write leveling (Byte 0): 29 => 29
5794 05:53:31.796058 Write leveling (Byte 1): 29 => 29
5795 05:53:31.799227 DramcWriteLeveling(PI) end<-----
5796 05:53:31.799666
5797 05:53:31.800012 ==
5798 05:53:31.802599 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 05:53:31.805980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 05:53:31.809079 ==
5801 05:53:31.809551 [Gating] SW mode calibration
5802 05:53:31.818957 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5803 05:53:31.822041 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5804 05:53:31.825670 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 05:53:31.832228 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 05:53:31.835745 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 05:53:31.839057 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 05:53:31.845393 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 05:53:31.849050 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 05:53:31.852266 0 14 24 | B1->B0 | 2f2f 3232 | 0 1 | (0 0) (1 0)
5811 05:53:31.858746 0 14 28 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (1 1)
5812 05:53:31.862337 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5813 05:53:31.865769 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 05:53:31.872360 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 05:53:31.875730 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 05:53:31.878947 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 05:53:31.885435 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 05:53:31.888917 0 15 24 | B1->B0 | 2727 2323 | 1 1 | (0 0) (0 0)
5819 05:53:31.892405 0 15 28 | B1->B0 | 4545 3f3f | 0 0 | (0 0) (0 0)
5820 05:53:31.898849 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 05:53:31.902190 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 05:53:31.905398 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 05:53:31.909032 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 05:53:31.915655 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 05:53:31.918816 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 05:53:31.922197 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 05:53:31.928535 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 05:53:31.932628 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 05:53:31.935284 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 05:53:31.942115 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 05:53:31.945292 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 05:53:31.949046 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 05:53:31.955673 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 05:53:31.959194 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 05:53:31.962381 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 05:53:31.969040 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 05:53:31.972116 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 05:53:31.975598 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 05:53:31.982331 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 05:53:31.985392 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 05:53:31.988724 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 05:53:31.995533 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5843 05:53:31.998907 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5844 05:53:32.002351 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 05:53:32.005497 Total UI for P1: 0, mck2ui 16
5846 05:53:32.008678 best dqsien dly found for B0: ( 1, 2, 26)
5847 05:53:32.012464 Total UI for P1: 0, mck2ui 16
5848 05:53:32.015477 best dqsien dly found for B1: ( 1, 2, 26)
5849 05:53:32.018617 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5850 05:53:32.022122 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5851 05:53:32.022568
5852 05:53:32.025558 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5853 05:53:32.031978 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5854 05:53:32.032407 [Gating] SW calibration Done
5855 05:53:32.032746 ==
5856 05:53:32.035543 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 05:53:32.042517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 05:53:32.043095 ==
5859 05:53:32.043530 RX Vref Scan: 0
5860 05:53:32.043886
5861 05:53:32.045657 RX Vref 0 -> 0, step: 1
5862 05:53:32.046109
5863 05:53:32.048768 RX Delay -80 -> 252, step: 8
5864 05:53:32.052473 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5865 05:53:32.055778 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5866 05:53:32.058803 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5867 05:53:32.062373 iDelay=208, Bit 3, Center 107 (24 ~ 191) 168
5868 05:53:32.069142 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5869 05:53:32.072473 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5870 05:53:32.075635 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5871 05:53:32.078906 iDelay=208, Bit 7, Center 107 (24 ~ 191) 168
5872 05:53:32.081788 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5873 05:53:32.088553 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5874 05:53:32.092171 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5875 05:53:32.095151 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5876 05:53:32.098914 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5877 05:53:32.102377 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5878 05:53:32.105418 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5879 05:53:32.111914 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5880 05:53:32.112502 ==
5881 05:53:32.115174 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 05:53:32.118359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 05:53:32.118838 ==
5884 05:53:32.119220 DQS Delay:
5885 05:53:32.121864 DQS0 = 0, DQS1 = 0
5886 05:53:32.122378 DQM Delay:
5887 05:53:32.124997 DQM0 = 104, DQM1 = 95
5888 05:53:32.125473 DQ Delay:
5889 05:53:32.128213 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =107
5890 05:53:32.131725 DQ4 =103, DQ5 =115, DQ6 =111, DQ7 =107
5891 05:53:32.135587 DQ8 =83, DQ9 =87, DQ10 =91, DQ11 =91
5892 05:53:32.138477 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =107
5893 05:53:32.139074
5894 05:53:32.139651
5895 05:53:32.140176 ==
5896 05:53:32.141910 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 05:53:32.148133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 05:53:32.148615 ==
5899 05:53:32.149067
5900 05:53:32.149428
5901 05:53:32.149764 TX Vref Scan disable
5902 05:53:32.151538 == TX Byte 0 ==
5903 05:53:32.154891 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5904 05:53:32.161971 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5905 05:53:32.162537 == TX Byte 1 ==
5906 05:53:32.165199 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5907 05:53:32.171874 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5908 05:53:32.172434 ==
5909 05:53:32.175154 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 05:53:32.178683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 05:53:32.179452 ==
5912 05:53:32.179975
5913 05:53:32.180538
5914 05:53:32.181547 TX Vref Scan disable
5915 05:53:32.182192 == TX Byte 0 ==
5916 05:53:32.188343 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5917 05:53:32.191267 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5918 05:53:32.191713 == TX Byte 1 ==
5919 05:53:32.197981 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5920 05:53:32.201562 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5921 05:53:32.202037
5922 05:53:32.202393 [DATLAT]
5923 05:53:32.204546 Freq=933, CH1 RK1
5924 05:53:32.204978
5925 05:53:32.205320 DATLAT Default: 0xb
5926 05:53:32.208340 0, 0xFFFF, sum = 0
5927 05:53:32.208781 1, 0xFFFF, sum = 0
5928 05:53:32.211615 2, 0xFFFF, sum = 0
5929 05:53:32.212053 3, 0xFFFF, sum = 0
5930 05:53:32.214947 4, 0xFFFF, sum = 0
5931 05:53:32.215387 5, 0xFFFF, sum = 0
5932 05:53:32.217524 6, 0xFFFF, sum = 0
5933 05:53:32.217609 7, 0xFFFF, sum = 0
5934 05:53:32.221254 8, 0xFFFF, sum = 0
5935 05:53:32.224357 9, 0xFFFF, sum = 0
5936 05:53:32.224442 10, 0x0, sum = 1
5937 05:53:32.224511 11, 0x0, sum = 2
5938 05:53:32.228076 12, 0x0, sum = 3
5939 05:53:32.228161 13, 0x0, sum = 4
5940 05:53:32.230899 best_step = 11
5941 05:53:32.230984
5942 05:53:32.231050 ==
5943 05:53:32.234152 Dram Type= 6, Freq= 0, CH_1, rank 1
5944 05:53:32.237687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5945 05:53:32.237772 ==
5946 05:53:32.241406 RX Vref Scan: 0
5947 05:53:32.241491
5948 05:53:32.241558 RX Vref 0 -> 0, step: 1
5949 05:53:32.241619
5950 05:53:32.244207 RX Delay -53 -> 252, step: 4
5951 05:53:32.251756 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5952 05:53:32.254702 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5953 05:53:32.257914 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5954 05:53:32.261255 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5955 05:53:32.264849 iDelay=199, Bit 4, Center 108 (27 ~ 190) 164
5956 05:53:32.271628 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5957 05:53:32.274971 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5958 05:53:32.278116 iDelay=199, Bit 7, Center 100 (19 ~ 182) 164
5959 05:53:32.281369 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5960 05:53:32.284742 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5961 05:53:32.288300 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5962 05:53:32.294899 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5963 05:53:32.298180 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5964 05:53:32.301850 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5965 05:53:32.304768 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5966 05:53:32.308064 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5967 05:53:32.311360 ==
5968 05:53:32.314555 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 05:53:32.317968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 05:53:32.318053 ==
5971 05:53:32.318121 DQS Delay:
5972 05:53:32.321213 DQS0 = 0, DQS1 = 0
5973 05:53:32.321298 DQM Delay:
5974 05:53:32.324862 DQM0 = 104, DQM1 = 96
5975 05:53:32.324978 DQ Delay:
5976 05:53:32.328037 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5977 05:53:32.331220 DQ4 =108, DQ5 =116, DQ6 =112, DQ7 =100
5978 05:53:32.334440 DQ8 =82, DQ9 =88, DQ10 =98, DQ11 =92
5979 05:53:32.337930 DQ12 =104, DQ13 =100, DQ14 =102, DQ15 =106
5980 05:53:32.338052
5981 05:53:32.338151
5982 05:53:32.347907 [DQSOSCAuto] RK1, (LSB)MR18= 0x22ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5983 05:53:32.348026 CH1 RK1: MR19=504, MR18=22FF
5984 05:53:32.354600 CH1_RK1: MR19=0x504, MR18=0x22FF, DQSOSC=411, MR23=63, INC=64, DEC=42
5985 05:53:32.357605 [RxdqsGatingPostProcess] freq 933
5986 05:53:32.364424 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5987 05:53:32.367448 best DQS0 dly(2T, 0.5T) = (0, 10)
5988 05:53:32.370647 best DQS1 dly(2T, 0.5T) = (0, 10)
5989 05:53:32.374105 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5990 05:53:32.377563 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5991 05:53:32.380750 best DQS0 dly(2T, 0.5T) = (0, 10)
5992 05:53:32.384277 best DQS1 dly(2T, 0.5T) = (0, 10)
5993 05:53:32.387268 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5994 05:53:32.390590 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5995 05:53:32.390686 Pre-setting of DQS Precalculation
5996 05:53:32.397630 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5997 05:53:32.404157 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5998 05:53:32.410825 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5999 05:53:32.410926
6000 05:53:32.411008
6001 05:53:32.414094 [Calibration Summary] 1866 Mbps
6002 05:53:32.417140 CH 0, Rank 0
6003 05:53:32.417224 SW Impedance : PASS
6004 05:53:32.420481 DUTY Scan : NO K
6005 05:53:32.423883 ZQ Calibration : PASS
6006 05:53:32.423978 Jitter Meter : NO K
6007 05:53:32.427198 CBT Training : PASS
6008 05:53:32.430727 Write leveling : PASS
6009 05:53:32.430824 RX DQS gating : PASS
6010 05:53:32.433528 RX DQ/DQS(RDDQC) : PASS
6011 05:53:32.433637 TX DQ/DQS : PASS
6012 05:53:32.436945 RX DATLAT : PASS
6013 05:53:32.440100 RX DQ/DQS(Engine): PASS
6014 05:53:32.440177 TX OE : NO K
6015 05:53:32.443845 All Pass.
6016 05:53:32.443922
6017 05:53:32.444049 CH 0, Rank 1
6018 05:53:32.447051 SW Impedance : PASS
6019 05:53:32.447127 DUTY Scan : NO K
6020 05:53:32.450192 ZQ Calibration : PASS
6021 05:53:32.453772 Jitter Meter : NO K
6022 05:53:32.453857 CBT Training : PASS
6023 05:53:32.457210 Write leveling : PASS
6024 05:53:32.460142 RX DQS gating : PASS
6025 05:53:32.460229 RX DQ/DQS(RDDQC) : PASS
6026 05:53:32.463647 TX DQ/DQS : PASS
6027 05:53:32.467190 RX DATLAT : PASS
6028 05:53:32.467277 RX DQ/DQS(Engine): PASS
6029 05:53:32.470221 TX OE : NO K
6030 05:53:32.470308 All Pass.
6031 05:53:32.470377
6032 05:53:32.473699 CH 1, Rank 0
6033 05:53:32.473785 SW Impedance : PASS
6034 05:53:32.477001 DUTY Scan : NO K
6035 05:53:32.480488 ZQ Calibration : PASS
6036 05:53:32.480589 Jitter Meter : NO K
6037 05:53:32.483456 CBT Training : PASS
6038 05:53:32.486881 Write leveling : PASS
6039 05:53:32.486968 RX DQS gating : PASS
6040 05:53:32.490140 RX DQ/DQS(RDDQC) : PASS
6041 05:53:32.490227 TX DQ/DQS : PASS
6042 05:53:32.493520 RX DATLAT : PASS
6043 05:53:32.496821 RX DQ/DQS(Engine): PASS
6044 05:53:32.496935 TX OE : NO K
6045 05:53:32.499944 All Pass.
6046 05:53:32.500031
6047 05:53:32.500100 CH 1, Rank 1
6048 05:53:32.503375 SW Impedance : PASS
6049 05:53:32.503465 DUTY Scan : NO K
6050 05:53:32.506531 ZQ Calibration : PASS
6051 05:53:32.509968 Jitter Meter : NO K
6052 05:53:32.510055 CBT Training : PASS
6053 05:53:32.513409 Write leveling : PASS
6054 05:53:32.516791 RX DQS gating : PASS
6055 05:53:32.516904 RX DQ/DQS(RDDQC) : PASS
6056 05:53:32.519732 TX DQ/DQS : PASS
6057 05:53:32.522988 RX DATLAT : PASS
6058 05:53:32.523102 RX DQ/DQS(Engine): PASS
6059 05:53:32.526529 TX OE : NO K
6060 05:53:32.526616 All Pass.
6061 05:53:32.526684
6062 05:53:32.529715 DramC Write-DBI off
6063 05:53:32.533231 PER_BANK_REFRESH: Hybrid Mode
6064 05:53:32.533318 TX_TRACKING: ON
6065 05:53:32.543097 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6066 05:53:32.546431 [FAST_K] Save calibration result to emmc
6067 05:53:32.549790 dramc_set_vcore_voltage set vcore to 650000
6068 05:53:32.553083 Read voltage for 400, 6
6069 05:53:32.553197 Vio18 = 0
6070 05:53:32.553303 Vcore = 650000
6071 05:53:32.556258 Vdram = 0
6072 05:53:32.556363 Vddq = 0
6073 05:53:32.556468 Vmddr = 0
6074 05:53:32.563255 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6075 05:53:32.566525 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6076 05:53:32.569869 MEM_TYPE=3, freq_sel=20
6077 05:53:32.572773 sv_algorithm_assistance_LP4_800
6078 05:53:32.576185 ============ PULL DRAM RESETB DOWN ============
6079 05:53:32.579567 ========== PULL DRAM RESETB DOWN end =========
6080 05:53:32.586437 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6081 05:53:32.589487 ===================================
6082 05:53:32.589575 LPDDR4 DRAM CONFIGURATION
6083 05:53:32.592876 ===================================
6084 05:53:32.596591 EX_ROW_EN[0] = 0x0
6085 05:53:32.599714 EX_ROW_EN[1] = 0x0
6086 05:53:32.599830 LP4Y_EN = 0x0
6087 05:53:32.602920 WORK_FSP = 0x0
6088 05:53:32.603006 WL = 0x2
6089 05:53:32.606428 RL = 0x2
6090 05:53:32.606516 BL = 0x2
6091 05:53:32.609678 RPST = 0x0
6092 05:53:32.609765 RD_PRE = 0x0
6093 05:53:32.613165 WR_PRE = 0x1
6094 05:53:32.613251 WR_PST = 0x0
6095 05:53:32.616133 DBI_WR = 0x0
6096 05:53:32.616219 DBI_RD = 0x0
6097 05:53:32.619588 OTF = 0x1
6098 05:53:32.622567 ===================================
6099 05:53:32.625778 ===================================
6100 05:53:32.625860 ANA top config
6101 05:53:32.629203 ===================================
6102 05:53:32.632653 DLL_ASYNC_EN = 0
6103 05:53:32.635939 ALL_SLAVE_EN = 1
6104 05:53:32.639299 NEW_RANK_MODE = 1
6105 05:53:32.639390 DLL_IDLE_MODE = 1
6106 05:53:32.642434 LP45_APHY_COMB_EN = 1
6107 05:53:32.645669 TX_ODT_DIS = 1
6108 05:53:32.648925 NEW_8X_MODE = 1
6109 05:53:32.652161 ===================================
6110 05:53:32.655681 ===================================
6111 05:53:32.658961 data_rate = 800
6112 05:53:32.659039 CKR = 1
6113 05:53:32.662359 DQ_P2S_RATIO = 4
6114 05:53:32.666031 ===================================
6115 05:53:32.669657 CA_P2S_RATIO = 4
6116 05:53:32.672602 DQ_CA_OPEN = 0
6117 05:53:32.676160 DQ_SEMI_OPEN = 1
6118 05:53:32.679222 CA_SEMI_OPEN = 1
6119 05:53:32.679333 CA_FULL_RATE = 0
6120 05:53:32.682440 DQ_CKDIV4_EN = 0
6121 05:53:32.685787 CA_CKDIV4_EN = 1
6122 05:53:32.689379 CA_PREDIV_EN = 0
6123 05:53:32.692522 PH8_DLY = 0
6124 05:53:32.696056 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6125 05:53:32.696140 DQ_AAMCK_DIV = 0
6126 05:53:32.699640 CA_AAMCK_DIV = 0
6127 05:53:32.702265 CA_ADMCK_DIV = 4
6128 05:53:32.706011 DQ_TRACK_CA_EN = 0
6129 05:53:32.709061 CA_PICK = 800
6130 05:53:32.712454 CA_MCKIO = 400
6131 05:53:32.715885 MCKIO_SEMI = 400
6132 05:53:32.715971 PLL_FREQ = 3016
6133 05:53:32.719057 DQ_UI_PI_RATIO = 32
6134 05:53:32.722329 CA_UI_PI_RATIO = 32
6135 05:53:32.725709 ===================================
6136 05:53:32.729025 ===================================
6137 05:53:32.732507 memory_type:LPDDR4
6138 05:53:32.732592 GP_NUM : 10
6139 05:53:32.735836 SRAM_EN : 1
6140 05:53:32.739352 MD32_EN : 0
6141 05:53:32.742505 ===================================
6142 05:53:32.742591 [ANA_INIT] >>>>>>>>>>>>>>
6143 05:53:32.745486 <<<<<< [CONFIGURE PHASE]: ANA_TX
6144 05:53:32.748957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6145 05:53:32.752243 ===================================
6146 05:53:32.755421 data_rate = 800,PCW = 0X7400
6147 05:53:32.758958 ===================================
6148 05:53:32.762145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6149 05:53:32.769189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6150 05:53:32.779020 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6151 05:53:32.785406 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6152 05:53:32.788754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6153 05:53:32.792523 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6154 05:53:32.792612 [ANA_INIT] flow start
6155 05:53:32.795877 [ANA_INIT] PLL >>>>>>>>
6156 05:53:32.798947 [ANA_INIT] PLL <<<<<<<<
6157 05:53:32.799028 [ANA_INIT] MIDPI >>>>>>>>
6158 05:53:32.802541 [ANA_INIT] MIDPI <<<<<<<<
6159 05:53:32.805661 [ANA_INIT] DLL >>>>>>>>
6160 05:53:32.805762 [ANA_INIT] flow end
6161 05:53:32.809163 ============ LP4 DIFF to SE enter ============
6162 05:53:32.815707 ============ LP4 DIFF to SE exit ============
6163 05:53:32.815819 [ANA_INIT] <<<<<<<<<<<<<
6164 05:53:32.819237 [Flow] Enable top DCM control >>>>>
6165 05:53:32.822649 [Flow] Enable top DCM control <<<<<
6166 05:53:32.825706 Enable DLL master slave shuffle
6167 05:53:32.832716 ==============================================================
6168 05:53:32.832817 Gating Mode config
6169 05:53:32.839292 ==============================================================
6170 05:53:32.842326 Config description:
6171 05:53:32.852321 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6172 05:53:32.858836 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6173 05:53:32.862611 SELPH_MODE 0: By rank 1: By Phase
6174 05:53:32.869041 ==============================================================
6175 05:53:32.872409 GAT_TRACK_EN = 0
6176 05:53:32.872495 RX_GATING_MODE = 2
6177 05:53:32.875512 RX_GATING_TRACK_MODE = 2
6178 05:53:32.878795 SELPH_MODE = 1
6179 05:53:32.882207 PICG_EARLY_EN = 1
6180 05:53:32.885643 VALID_LAT_VALUE = 1
6181 05:53:32.892149 ==============================================================
6182 05:53:32.895539 Enter into Gating configuration >>>>
6183 05:53:32.898945 Exit from Gating configuration <<<<
6184 05:53:32.902348 Enter into DVFS_PRE_config >>>>>
6185 05:53:32.912549 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6186 05:53:32.915659 Exit from DVFS_PRE_config <<<<<
6187 05:53:32.919199 Enter into PICG configuration >>>>
6188 05:53:32.922270 Exit from PICG configuration <<<<
6189 05:53:32.925520 [RX_INPUT] configuration >>>>>
6190 05:53:32.928865 [RX_INPUT] configuration <<<<<
6191 05:53:32.932222 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6192 05:53:32.938460 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6193 05:53:32.945124 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6194 05:53:32.948785 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6195 05:53:32.955317 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6196 05:53:32.961781 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6197 05:53:32.965217 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6198 05:53:32.971852 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6199 05:53:32.975078 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6200 05:53:32.978337 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6201 05:53:32.981609 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6202 05:53:32.988238 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6203 05:53:32.991507 ===================================
6204 05:53:32.991593 LPDDR4 DRAM CONFIGURATION
6205 05:53:32.994819 ===================================
6206 05:53:32.998167 EX_ROW_EN[0] = 0x0
6207 05:53:33.001769 EX_ROW_EN[1] = 0x0
6208 05:53:33.001845 LP4Y_EN = 0x0
6209 05:53:33.004703 WORK_FSP = 0x0
6210 05:53:33.004816 WL = 0x2
6211 05:53:33.008386 RL = 0x2
6212 05:53:33.008470 BL = 0x2
6213 05:53:33.011703 RPST = 0x0
6214 05:53:33.011787 RD_PRE = 0x0
6215 05:53:33.015112 WR_PRE = 0x1
6216 05:53:33.015195 WR_PST = 0x0
6217 05:53:33.018308 DBI_WR = 0x0
6218 05:53:33.018392 DBI_RD = 0x0
6219 05:53:33.021445 OTF = 0x1
6220 05:53:33.024905 ===================================
6221 05:53:33.028203 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6222 05:53:33.031549 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6223 05:53:33.038090 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 05:53:33.041598 ===================================
6225 05:53:33.041683 LPDDR4 DRAM CONFIGURATION
6226 05:53:33.044718 ===================================
6227 05:53:33.047998 EX_ROW_EN[0] = 0x10
6228 05:53:33.051504 EX_ROW_EN[1] = 0x0
6229 05:53:33.051589 LP4Y_EN = 0x0
6230 05:53:33.054589 WORK_FSP = 0x0
6231 05:53:33.054674 WL = 0x2
6232 05:53:33.057948 RL = 0x2
6233 05:53:33.058033 BL = 0x2
6234 05:53:33.061723 RPST = 0x0
6235 05:53:33.061808 RD_PRE = 0x0
6236 05:53:33.064904 WR_PRE = 0x1
6237 05:53:33.064988 WR_PST = 0x0
6238 05:53:33.068282 DBI_WR = 0x0
6239 05:53:33.068393 DBI_RD = 0x0
6240 05:53:33.071369 OTF = 0x1
6241 05:53:33.074906 ===================================
6242 05:53:33.081241 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6243 05:53:33.084856 nWR fixed to 30
6244 05:53:33.084943 [ModeRegInit_LP4] CH0 RK0
6245 05:53:33.088363 [ModeRegInit_LP4] CH0 RK1
6246 05:53:33.091119 [ModeRegInit_LP4] CH1 RK0
6247 05:53:33.094523 [ModeRegInit_LP4] CH1 RK1
6248 05:53:33.094604 match AC timing 19
6249 05:53:33.097770 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6250 05:53:33.104751 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6251 05:53:33.108212 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6252 05:53:33.111062 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6253 05:53:33.117615 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6254 05:53:33.117719 ==
6255 05:53:33.121359 Dram Type= 6, Freq= 0, CH_0, rank 0
6256 05:53:33.124395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 05:53:33.124502 ==
6258 05:53:33.131117 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6259 05:53:33.137739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6260 05:53:33.137846 [CA 0] Center 36 (8~64) winsize 57
6261 05:53:33.141053 [CA 1] Center 36 (8~64) winsize 57
6262 05:53:33.144249 [CA 2] Center 36 (8~64) winsize 57
6263 05:53:33.147860 [CA 3] Center 36 (8~64) winsize 57
6264 05:53:33.150842 [CA 4] Center 36 (8~64) winsize 57
6265 05:53:33.154462 [CA 5] Center 36 (8~64) winsize 57
6266 05:53:33.154537
6267 05:53:33.157574 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6268 05:53:33.157680
6269 05:53:33.160818 [CATrainingPosCal] consider 1 rank data
6270 05:53:33.164686 u2DelayCellTimex100 = 270/100 ps
6271 05:53:33.167743 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 05:53:33.171013 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 05:53:33.177475 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 05:53:33.180977 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 05:53:33.184196 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 05:53:33.187451 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 05:53:33.187534
6278 05:53:33.191008 CA PerBit enable=1, Macro0, CA PI delay=36
6279 05:53:33.191082
6280 05:53:33.194467 [CBTSetCACLKResult] CA Dly = 36
6281 05:53:33.194541 CS Dly: 1 (0~32)
6282 05:53:33.197346 ==
6283 05:53:33.197432 Dram Type= 6, Freq= 0, CH_0, rank 1
6284 05:53:33.204189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 05:53:33.204276 ==
6286 05:53:33.207284 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6287 05:53:33.214115 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6288 05:53:33.217188 [CA 0] Center 36 (8~64) winsize 57
6289 05:53:33.220699 [CA 1] Center 36 (8~64) winsize 57
6290 05:53:33.224157 [CA 2] Center 36 (8~64) winsize 57
6291 05:53:33.227480 [CA 3] Center 36 (8~64) winsize 57
6292 05:53:33.230776 [CA 4] Center 36 (8~64) winsize 57
6293 05:53:33.233915 [CA 5] Center 36 (8~64) winsize 57
6294 05:53:33.234036
6295 05:53:33.237180 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6296 05:53:33.237265
6297 05:53:33.240539 [CATrainingPosCal] consider 2 rank data
6298 05:53:33.243899 u2DelayCellTimex100 = 270/100 ps
6299 05:53:33.247179 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 05:53:33.250824 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 05:53:33.254011 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 05:53:33.257218 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 05:53:33.263916 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 05:53:33.267130 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 05:53:33.267214
6306 05:53:33.270561 CA PerBit enable=1, Macro0, CA PI delay=36
6307 05:53:33.270645
6308 05:53:33.273879 [CBTSetCACLKResult] CA Dly = 36
6309 05:53:33.273983 CS Dly: 1 (0~32)
6310 05:53:33.274051
6311 05:53:33.276975 ----->DramcWriteLeveling(PI) begin...
6312 05:53:33.277060 ==
6313 05:53:33.280537 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 05:53:33.286773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 05:53:33.286857 ==
6316 05:53:33.290419 Write leveling (Byte 0): 40 => 8
6317 05:53:33.290503 Write leveling (Byte 1): 32 => 0
6318 05:53:33.293613 DramcWriteLeveling(PI) end<-----
6319 05:53:33.293697
6320 05:53:33.293763 ==
6321 05:53:33.296997 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 05:53:33.303563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 05:53:33.303647 ==
6324 05:53:33.306800 [Gating] SW mode calibration
6325 05:53:33.313382 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6326 05:53:33.316900 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6327 05:53:33.323569 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6328 05:53:33.326828 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6329 05:53:33.330115 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 05:53:33.336728 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6331 05:53:33.340114 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 05:53:33.343309 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 05:53:33.350235 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 05:53:33.353132 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 05:53:33.356604 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 05:53:33.359850 Total UI for P1: 0, mck2ui 16
6337 05:53:33.363448 best dqsien dly found for B0: ( 0, 14, 24)
6338 05:53:33.366579 Total UI for P1: 0, mck2ui 16
6339 05:53:33.369913 best dqsien dly found for B1: ( 0, 14, 24)
6340 05:53:33.373067 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6341 05:53:33.376609 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6342 05:53:33.376693
6343 05:53:33.379816 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6344 05:53:33.386605 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6345 05:53:33.386690 [Gating] SW calibration Done
6346 05:53:33.389760 ==
6347 05:53:33.389869 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 05:53:33.396573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 05:53:33.396656 ==
6350 05:53:33.396720 RX Vref Scan: 0
6351 05:53:33.396781
6352 05:53:33.399800 RX Vref 0 -> 0, step: 1
6353 05:53:33.399883
6354 05:53:33.403146 RX Delay -410 -> 252, step: 16
6355 05:53:33.406331 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6356 05:53:33.409849 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6357 05:53:33.416023 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6358 05:53:33.419319 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6359 05:53:33.422796 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6360 05:53:33.426495 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6361 05:53:33.433238 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6362 05:53:33.436295 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6363 05:53:33.439687 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6364 05:53:33.442752 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6365 05:53:33.449626 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6366 05:53:33.452753 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6367 05:53:33.456183 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6368 05:53:33.459366 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6369 05:53:33.466057 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6370 05:53:33.469542 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6371 05:53:33.469624 ==
6372 05:53:33.472764 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 05:53:33.475980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 05:53:33.476063 ==
6375 05:53:33.479641 DQS Delay:
6376 05:53:33.479736 DQS0 = 27, DQS1 = 43
6377 05:53:33.482432 DQM Delay:
6378 05:53:33.482514 DQM0 = 12, DQM1 = 12
6379 05:53:33.482586 DQ Delay:
6380 05:53:33.485930 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6381 05:53:33.489092 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6382 05:53:33.492736 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6383 05:53:33.496117 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6384 05:53:33.496199
6385 05:53:33.496264
6386 05:53:33.496325 ==
6387 05:53:33.499308 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 05:53:33.506157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 05:53:33.506239 ==
6390 05:53:33.506304
6391 05:53:33.506364
6392 05:53:33.506422 TX Vref Scan disable
6393 05:53:33.509492 == TX Byte 0 ==
6394 05:53:33.512522 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 05:53:33.516008 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 05:53:33.519333 == TX Byte 1 ==
6397 05:53:33.522539 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6398 05:53:33.525886 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6399 05:53:33.529299 ==
6400 05:53:33.529380 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 05:53:33.535612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 05:53:33.535695 ==
6403 05:53:33.535759
6404 05:53:33.535819
6405 05:53:33.538943 TX Vref Scan disable
6406 05:53:33.539024 == TX Byte 0 ==
6407 05:53:33.542238 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 05:53:33.548962 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 05:53:33.549044 == TX Byte 1 ==
6410 05:53:33.552274 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6411 05:53:33.555956 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6412 05:53:33.559240
6413 05:53:33.559321 [DATLAT]
6414 05:53:33.559386 Freq=400, CH0 RK0
6415 05:53:33.559447
6416 05:53:33.562700 DATLAT Default: 0xf
6417 05:53:33.562781 0, 0xFFFF, sum = 0
6418 05:53:33.566058 1, 0xFFFF, sum = 0
6419 05:53:33.566143 2, 0xFFFF, sum = 0
6420 05:53:33.569272 3, 0xFFFF, sum = 0
6421 05:53:33.569357 4, 0xFFFF, sum = 0
6422 05:53:33.572302 5, 0xFFFF, sum = 0
6423 05:53:33.575699 6, 0xFFFF, sum = 0
6424 05:53:33.575784 7, 0xFFFF, sum = 0
6425 05:53:33.579042 8, 0xFFFF, sum = 0
6426 05:53:33.579127 9, 0xFFFF, sum = 0
6427 05:53:33.582595 10, 0xFFFF, sum = 0
6428 05:53:33.582680 11, 0xFFFF, sum = 0
6429 05:53:33.585908 12, 0xFFFF, sum = 0
6430 05:53:33.586038 13, 0x0, sum = 1
6431 05:53:33.589027 14, 0x0, sum = 2
6432 05:53:33.589112 15, 0x0, sum = 3
6433 05:53:33.592708 16, 0x0, sum = 4
6434 05:53:33.592814 best_step = 14
6435 05:53:33.592894
6436 05:53:33.592956 ==
6437 05:53:33.595837 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 05:53:33.599210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 05:53:33.599294 ==
6440 05:53:33.602356 RX Vref Scan: 1
6441 05:53:33.602439
6442 05:53:33.605857 RX Vref 0 -> 0, step: 1
6443 05:53:33.605999
6444 05:53:33.606067 RX Delay -327 -> 252, step: 8
6445 05:53:33.606131
6446 05:53:33.609199 Set Vref, RX VrefLevel [Byte0]: 58
6447 05:53:33.612158 [Byte1]: 54
6448 05:53:33.617795
6449 05:53:33.617904 Final RX Vref Byte 0 = 58 to rank0
6450 05:53:33.621077 Final RX Vref Byte 1 = 54 to rank0
6451 05:53:33.624407 Final RX Vref Byte 0 = 58 to rank1
6452 05:53:33.627731 Final RX Vref Byte 1 = 54 to rank1==
6453 05:53:33.630774 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 05:53:33.637814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 05:53:33.637899 ==
6456 05:53:33.637974 DQS Delay:
6457 05:53:33.640750 DQS0 = 24, DQS1 = 44
6458 05:53:33.640833 DQM Delay:
6459 05:53:33.640900 DQM0 = 8, DQM1 = 11
6460 05:53:33.644448 DQ Delay:
6461 05:53:33.644532 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6462 05:53:33.647585 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =16
6463 05:53:33.651219 DQ8 =4, DQ9 =0, DQ10 =8, DQ11 =8
6464 05:53:33.654128 DQ12 =16, DQ13 =12, DQ14 =24, DQ15 =20
6465 05:53:33.654212
6466 05:53:33.654278
6467 05:53:33.664226 [DQSOSCAuto] RK0, (LSB)MR18= 0xa8a0, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6468 05:53:33.667587 CH0 RK0: MR19=C0C, MR18=A8A0
6469 05:53:33.674386 CH0_RK0: MR19=0xC0C, MR18=0xA8A0, DQSOSC=388, MR23=63, INC=392, DEC=261
6470 05:53:33.674470 ==
6471 05:53:33.677438 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 05:53:33.680637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 05:53:33.680721 ==
6474 05:53:33.684005 [Gating] SW mode calibration
6475 05:53:33.690888 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6476 05:53:33.694173 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6477 05:53:33.700808 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 05:53:33.704127 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6479 05:53:33.707246 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 05:53:33.714252 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6481 05:53:33.717572 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 05:53:33.720897 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 05:53:33.727190 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 05:53:33.730568 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 05:53:33.733785 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 05:53:33.737507 Total UI for P1: 0, mck2ui 16
6487 05:53:33.740918 best dqsien dly found for B0: ( 0, 14, 24)
6488 05:53:33.743753 Total UI for P1: 0, mck2ui 16
6489 05:53:33.747364 best dqsien dly found for B1: ( 0, 14, 24)
6490 05:53:33.750648 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6491 05:53:33.753843 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6492 05:53:33.753987
6493 05:53:33.760669 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6494 05:53:33.763880 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6495 05:53:33.767206 [Gating] SW calibration Done
6496 05:53:33.767289 ==
6497 05:53:33.770198 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 05:53:33.773543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 05:53:33.773627 ==
6500 05:53:33.773693 RX Vref Scan: 0
6501 05:53:33.773755
6502 05:53:33.776789 RX Vref 0 -> 0, step: 1
6503 05:53:33.776872
6504 05:53:33.780211 RX Delay -410 -> 252, step: 16
6505 05:53:33.783580 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6506 05:53:33.790409 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6507 05:53:33.793709 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6508 05:53:33.796827 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6509 05:53:33.800133 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6510 05:53:33.806946 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6511 05:53:33.810176 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6512 05:53:33.813444 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6513 05:53:33.816773 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6514 05:53:33.823446 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6515 05:53:33.826576 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6516 05:53:33.830188 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6517 05:53:33.833649 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6518 05:53:33.840309 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6519 05:53:33.843587 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6520 05:53:33.846511 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6521 05:53:33.846596 ==
6522 05:53:33.850500 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 05:53:33.853218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 05:53:33.856656 ==
6525 05:53:33.856766 DQS Delay:
6526 05:53:33.856900 DQS0 = 27, DQS1 = 43
6527 05:53:33.859868 DQM Delay:
6528 05:53:33.860008 DQM0 = 9, DQM1 = 12
6529 05:53:33.863218 DQ Delay:
6530 05:53:33.863331 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6531 05:53:33.866724 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6532 05:53:33.870021 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6533 05:53:33.872897 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6534 05:53:33.872981
6535 05:53:33.873047
6536 05:53:33.873110 ==
6537 05:53:33.876352 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 05:53:33.883081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 05:53:33.883169 ==
6540 05:53:33.883237
6541 05:53:33.883298
6542 05:53:33.886215 TX Vref Scan disable
6543 05:53:33.886316 == TX Byte 0 ==
6544 05:53:33.889867 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6545 05:53:33.893112 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6546 05:53:33.896213 == TX Byte 1 ==
6547 05:53:33.899524 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6548 05:53:33.902743 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6549 05:53:33.906265 ==
6550 05:53:33.909500 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 05:53:33.912795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 05:53:33.912880 ==
6553 05:53:33.912947
6554 05:53:33.913010
6555 05:53:33.915957 TX Vref Scan disable
6556 05:53:33.916041 == TX Byte 0 ==
6557 05:53:33.919727 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6558 05:53:33.926225 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6559 05:53:33.926310 == TX Byte 1 ==
6560 05:53:33.929504 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6561 05:53:33.936335 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6562 05:53:33.936420
6563 05:53:33.936487 [DATLAT]
6564 05:53:33.936550 Freq=400, CH0 RK1
6565 05:53:33.936610
6566 05:53:33.939156 DATLAT Default: 0xe
6567 05:53:33.939240 0, 0xFFFF, sum = 0
6568 05:53:33.942783 1, 0xFFFF, sum = 0
6569 05:53:33.942868 2, 0xFFFF, sum = 0
6570 05:53:33.946421 3, 0xFFFF, sum = 0
6571 05:53:33.949374 4, 0xFFFF, sum = 0
6572 05:53:33.949459 5, 0xFFFF, sum = 0
6573 05:53:33.952742 6, 0xFFFF, sum = 0
6574 05:53:33.952828 7, 0xFFFF, sum = 0
6575 05:53:33.956002 8, 0xFFFF, sum = 0
6576 05:53:33.956088 9, 0xFFFF, sum = 0
6577 05:53:33.959116 10, 0xFFFF, sum = 0
6578 05:53:33.959203 11, 0xFFFF, sum = 0
6579 05:53:33.962502 12, 0xFFFF, sum = 0
6580 05:53:33.962588 13, 0x0, sum = 1
6581 05:53:33.965722 14, 0x0, sum = 2
6582 05:53:33.965807 15, 0x0, sum = 3
6583 05:53:33.969067 16, 0x0, sum = 4
6584 05:53:33.969153 best_step = 14
6585 05:53:33.969220
6586 05:53:33.969282 ==
6587 05:53:33.972322 Dram Type= 6, Freq= 0, CH_0, rank 1
6588 05:53:33.975876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 05:53:33.978962 ==
6590 05:53:33.979046 RX Vref Scan: 0
6591 05:53:33.979113
6592 05:53:33.982744 RX Vref 0 -> 0, step: 1
6593 05:53:33.982828
6594 05:53:33.982895 RX Delay -327 -> 252, step: 8
6595 05:53:33.991475 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6596 05:53:33.994598 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6597 05:53:33.997818 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6598 05:53:34.001548 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6599 05:53:34.007981 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6600 05:53:34.011381 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6601 05:53:34.014575 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6602 05:53:34.017785 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6603 05:53:34.024617 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6604 05:53:34.028057 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6605 05:53:34.031501 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6606 05:53:34.034490 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6607 05:53:34.041053 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6608 05:53:34.044538 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6609 05:53:34.047864 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6610 05:53:34.054062 iDelay=217, Bit 15, Center -20 (-247 ~ 208) 456
6611 05:53:34.054147 ==
6612 05:53:34.057523 Dram Type= 6, Freq= 0, CH_0, rank 1
6613 05:53:34.060815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 05:53:34.060900 ==
6615 05:53:34.060966 DQS Delay:
6616 05:53:34.064155 DQS0 = 28, DQS1 = 44
6617 05:53:34.064239 DQM Delay:
6618 05:53:34.067302 DQM0 = 10, DQM1 = 15
6619 05:53:34.067386 DQ Delay:
6620 05:53:34.070871 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6621 05:53:34.074179 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6622 05:53:34.077580 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6623 05:53:34.081053 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6624 05:53:34.081137
6625 05:53:34.081204
6626 05:53:34.087601 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf62, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
6627 05:53:34.090812 CH0 RK1: MR19=C0C, MR18=AF62
6628 05:53:34.097394 CH0_RK1: MR19=0xC0C, MR18=0xAF62, DQSOSC=388, MR23=63, INC=392, DEC=261
6629 05:53:34.100845 [RxdqsGatingPostProcess] freq 400
6630 05:53:34.107293 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6631 05:53:34.110416 best DQS0 dly(2T, 0.5T) = (0, 10)
6632 05:53:34.110501 best DQS1 dly(2T, 0.5T) = (0, 10)
6633 05:53:34.113857 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6634 05:53:34.117287 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6635 05:53:34.120628 best DQS0 dly(2T, 0.5T) = (0, 10)
6636 05:53:34.123878 best DQS1 dly(2T, 0.5T) = (0, 10)
6637 05:53:34.127043 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6638 05:53:34.130365 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6639 05:53:34.133648 Pre-setting of DQS Precalculation
6640 05:53:34.140142 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6641 05:53:34.140226 ==
6642 05:53:34.143717 Dram Type= 6, Freq= 0, CH_1, rank 0
6643 05:53:34.147051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 05:53:34.147136 ==
6645 05:53:34.153576 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6646 05:53:34.157141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6647 05:53:34.160158 [CA 0] Center 36 (8~64) winsize 57
6648 05:53:34.163856 [CA 1] Center 36 (8~64) winsize 57
6649 05:53:34.166997 [CA 2] Center 36 (8~64) winsize 57
6650 05:53:34.170169 [CA 3] Center 36 (8~64) winsize 57
6651 05:53:34.173321 [CA 4] Center 36 (8~64) winsize 57
6652 05:53:34.176606 [CA 5] Center 36 (8~64) winsize 57
6653 05:53:34.176691
6654 05:53:34.179911 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6655 05:53:34.179995
6656 05:53:34.183710 [CATrainingPosCal] consider 1 rank data
6657 05:53:34.186876 u2DelayCellTimex100 = 270/100 ps
6658 05:53:34.190250 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 05:53:34.193689 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 05:53:34.200093 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 05:53:34.203241 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 05:53:34.206879 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 05:53:34.210090 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 05:53:34.210174
6665 05:53:34.213158 CA PerBit enable=1, Macro0, CA PI delay=36
6666 05:53:34.213243
6667 05:53:34.216419 [CBTSetCACLKResult] CA Dly = 36
6668 05:53:34.216503 CS Dly: 1 (0~32)
6669 05:53:34.216570 ==
6670 05:53:34.219757 Dram Type= 6, Freq= 0, CH_1, rank 1
6671 05:53:34.226704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 05:53:34.226839 ==
6673 05:53:34.229727 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6674 05:53:34.236349 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6675 05:53:34.239781 [CA 0] Center 36 (8~64) winsize 57
6676 05:53:34.242951 [CA 1] Center 36 (8~64) winsize 57
6677 05:53:34.246581 [CA 2] Center 36 (8~64) winsize 57
6678 05:53:34.249800 [CA 3] Center 36 (8~64) winsize 57
6679 05:53:34.253105 [CA 4] Center 36 (8~64) winsize 57
6680 05:53:34.256533 [CA 5] Center 36 (8~64) winsize 57
6681 05:53:34.256617
6682 05:53:34.260013 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6683 05:53:34.260097
6684 05:53:34.263353 [CATrainingPosCal] consider 2 rank data
6685 05:53:34.266692 u2DelayCellTimex100 = 270/100 ps
6686 05:53:34.269823 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 05:53:34.273013 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 05:53:34.276696 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 05:53:34.279934 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 05:53:34.283305 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 05:53:34.286536 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 05:53:34.286621
6693 05:53:34.293005 CA PerBit enable=1, Macro0, CA PI delay=36
6694 05:53:34.293088
6695 05:53:34.296264 [CBTSetCACLKResult] CA Dly = 36
6696 05:53:34.296348 CS Dly: 1 (0~32)
6697 05:53:34.296415
6698 05:53:34.299634 ----->DramcWriteLeveling(PI) begin...
6699 05:53:34.299719 ==
6700 05:53:34.303240 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 05:53:34.306575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 05:53:34.306686 ==
6703 05:53:34.309778 Write leveling (Byte 0): 40 => 8
6704 05:53:34.313110 Write leveling (Byte 1): 32 => 0
6705 05:53:34.316760 DramcWriteLeveling(PI) end<-----
6706 05:53:34.316844
6707 05:53:34.316910 ==
6708 05:53:34.319800 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 05:53:34.322960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 05:53:34.326488 ==
6711 05:53:34.326567 [Gating] SW mode calibration
6712 05:53:34.336301 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6713 05:53:34.339593 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6714 05:53:34.342787 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6715 05:53:34.349647 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6716 05:53:34.352903 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 05:53:34.355997 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6718 05:53:34.362890 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 05:53:34.366227 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 05:53:34.369476 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 05:53:34.376476 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 05:53:34.379148 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 05:53:34.382907 Total UI for P1: 0, mck2ui 16
6724 05:53:34.386151 best dqsien dly found for B0: ( 0, 14, 24)
6725 05:53:34.389462 Total UI for P1: 0, mck2ui 16
6726 05:53:34.392557 best dqsien dly found for B1: ( 0, 14, 24)
6727 05:53:34.395876 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6728 05:53:34.399194 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6729 05:53:34.399268
6730 05:53:34.402468 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6731 05:53:34.405809 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6732 05:53:34.409304 [Gating] SW calibration Done
6733 05:53:34.409380 ==
6734 05:53:34.412709 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 05:53:34.415847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 05:53:34.419232 ==
6737 05:53:34.419304 RX Vref Scan: 0
6738 05:53:34.419368
6739 05:53:34.422713 RX Vref 0 -> 0, step: 1
6740 05:53:34.422788
6741 05:53:34.425869 RX Delay -410 -> 252, step: 16
6742 05:53:34.429508 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6743 05:53:34.432710 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6744 05:53:34.435839 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6745 05:53:34.442858 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6746 05:53:34.446052 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6747 05:53:34.449411 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6748 05:53:34.452709 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6749 05:53:34.459116 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6750 05:53:34.462413 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6751 05:53:34.465932 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6752 05:53:34.469122 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6753 05:53:34.475791 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6754 05:53:34.479143 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6755 05:53:34.482397 iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496
6756 05:53:34.485630 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6757 05:53:34.492421 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6758 05:53:34.492506 ==
6759 05:53:34.495800 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 05:53:34.498954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 05:53:34.499039 ==
6762 05:53:34.499106 DQS Delay:
6763 05:53:34.502212 DQS0 = 27, DQS1 = 43
6764 05:53:34.502296 DQM Delay:
6765 05:53:34.505579 DQM0 = 6, DQM1 = 15
6766 05:53:34.505663 DQ Delay:
6767 05:53:34.508886 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6768 05:53:34.512504 DQ4 =0, DQ5 =24, DQ6 =16, DQ7 =0
6769 05:53:34.515836 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6770 05:53:34.518999 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6771 05:53:34.519084
6772 05:53:34.519152
6773 05:53:34.519214 ==
6774 05:53:34.522324 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 05:53:34.525428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 05:53:34.525513 ==
6777 05:53:34.525581
6778 05:53:34.528999
6779 05:53:34.529083 TX Vref Scan disable
6780 05:53:34.532133 == TX Byte 0 ==
6781 05:53:34.535373 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 05:53:34.538645 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 05:53:34.542367 == TX Byte 1 ==
6784 05:53:34.545664 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6785 05:53:34.548599 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6786 05:53:34.548684 ==
6787 05:53:34.552283 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 05:53:34.555579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 05:53:34.558625 ==
6790 05:53:34.558708
6791 05:53:34.558775
6792 05:53:34.558835 TX Vref Scan disable
6793 05:53:34.561659 == TX Byte 0 ==
6794 05:53:34.565184 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 05:53:34.568860 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 05:53:34.571733 == TX Byte 1 ==
6797 05:53:34.575345 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6798 05:53:34.578700 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6799 05:53:34.578785
6800 05:53:34.581801 [DATLAT]
6801 05:53:34.581914 Freq=400, CH1 RK0
6802 05:53:34.582012
6803 05:53:34.585721 DATLAT Default: 0xf
6804 05:53:34.585805 0, 0xFFFF, sum = 0
6805 05:53:34.588584 1, 0xFFFF, sum = 0
6806 05:53:34.588710 2, 0xFFFF, sum = 0
6807 05:53:34.591915 3, 0xFFFF, sum = 0
6808 05:53:34.592001 4, 0xFFFF, sum = 0
6809 05:53:34.595220 5, 0xFFFF, sum = 0
6810 05:53:34.595306 6, 0xFFFF, sum = 0
6811 05:53:34.598650 7, 0xFFFF, sum = 0
6812 05:53:34.598736 8, 0xFFFF, sum = 0
6813 05:53:34.601779 9, 0xFFFF, sum = 0
6814 05:53:34.601864 10, 0xFFFF, sum = 0
6815 05:53:34.605157 11, 0xFFFF, sum = 0
6816 05:53:34.605242 12, 0xFFFF, sum = 0
6817 05:53:34.608354 13, 0x0, sum = 1
6818 05:53:34.608440 14, 0x0, sum = 2
6819 05:53:34.611662 15, 0x0, sum = 3
6820 05:53:34.611756 16, 0x0, sum = 4
6821 05:53:34.614966 best_step = 14
6822 05:53:34.615050
6823 05:53:34.615116 ==
6824 05:53:34.618213 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 05:53:34.621539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 05:53:34.621623 ==
6827 05:53:34.625059 RX Vref Scan: 1
6828 05:53:34.625143
6829 05:53:34.625209 RX Vref 0 -> 0, step: 1
6830 05:53:34.625271
6831 05:53:34.628221 RX Delay -327 -> 252, step: 8
6832 05:53:34.628306
6833 05:53:34.631466 Set Vref, RX VrefLevel [Byte0]: 52
6834 05:53:34.634862 [Byte1]: 48
6835 05:53:34.639869
6836 05:53:34.639953 Final RX Vref Byte 0 = 52 to rank0
6837 05:53:34.643040 Final RX Vref Byte 1 = 48 to rank0
6838 05:53:34.646627 Final RX Vref Byte 0 = 52 to rank1
6839 05:53:34.649554 Final RX Vref Byte 1 = 48 to rank1==
6840 05:53:34.652881 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 05:53:34.659928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 05:53:34.660013 ==
6843 05:53:34.660079 DQS Delay:
6844 05:53:34.663017 DQS0 = 32, DQS1 = 40
6845 05:53:34.663101 DQM Delay:
6846 05:53:34.663168 DQM0 = 11, DQM1 = 13
6847 05:53:34.666163 DQ Delay:
6848 05:53:34.669646 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6849 05:53:34.669757 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6850 05:53:34.672856 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6851 05:53:34.676343 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6852 05:53:34.676427
6853 05:53:34.676494
6854 05:53:34.686419 [DQSOSCAuto] RK0, (LSB)MR18= 0x91cb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6855 05:53:34.689592 CH1 RK0: MR19=C0C, MR18=91CB
6856 05:53:34.696325 CH1_RK0: MR19=0xC0C, MR18=0x91CB, DQSOSC=384, MR23=63, INC=400, DEC=267
6857 05:53:34.696411 ==
6858 05:53:34.699617 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 05:53:34.702853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 05:53:34.702938 ==
6861 05:53:34.706077 [Gating] SW mode calibration
6862 05:53:34.712608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6863 05:53:34.715983 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6864 05:53:34.722648 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6865 05:53:34.726196 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6866 05:53:34.729350 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 05:53:34.736200 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6868 05:53:34.739392 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 05:53:34.742560 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 05:53:34.749429 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 05:53:34.752684 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 05:53:34.756004 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 05:53:34.759198 Total UI for P1: 0, mck2ui 16
6874 05:53:34.762581 best dqsien dly found for B0: ( 0, 14, 24)
6875 05:53:34.765898 Total UI for P1: 0, mck2ui 16
6876 05:53:34.769079 best dqsien dly found for B1: ( 0, 14, 24)
6877 05:53:34.772428 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6878 05:53:34.776038 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6879 05:53:34.779009
6880 05:53:34.782344 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6881 05:53:34.785968 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6882 05:53:34.789234 [Gating] SW calibration Done
6883 05:53:34.789318 ==
6884 05:53:34.792194 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 05:53:34.795556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 05:53:34.795668 ==
6887 05:53:34.795774 RX Vref Scan: 0
6888 05:53:34.798812
6889 05:53:34.798896 RX Vref 0 -> 0, step: 1
6890 05:53:34.798964
6891 05:53:34.802004 RX Delay -410 -> 252, step: 16
6892 05:53:34.805529 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6893 05:53:34.812276 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6894 05:53:34.815473 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6895 05:53:34.818741 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6896 05:53:34.822146 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6897 05:53:34.829079 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6898 05:53:34.832160 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6899 05:53:34.835375 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6900 05:53:34.838849 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6901 05:53:34.845496 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6902 05:53:34.848671 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6903 05:53:34.852089 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6904 05:53:34.855022 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6905 05:53:34.861615 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6906 05:53:34.865236 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6907 05:53:34.868509 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6908 05:53:34.868608 ==
6909 05:53:34.871571 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 05:53:34.878108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 05:53:34.878193 ==
6912 05:53:34.878259 DQS Delay:
6913 05:53:34.881775 DQS0 = 35, DQS1 = 43
6914 05:53:34.881859 DQM Delay:
6915 05:53:34.884945 DQM0 = 16, DQM1 = 20
6916 05:53:34.885029 DQ Delay:
6917 05:53:34.888279 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6918 05:53:34.891563 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6919 05:53:34.895106 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6920 05:53:34.898178 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6921 05:53:34.898262
6922 05:53:34.898329
6923 05:53:34.898389 ==
6924 05:53:34.901547 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 05:53:34.904929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 05:53:34.905013 ==
6927 05:53:34.905080
6928 05:53:34.905142
6929 05:53:34.908149 TX Vref Scan disable
6930 05:53:34.908233 == TX Byte 0 ==
6931 05:53:34.914551 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6932 05:53:34.917873 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6933 05:53:34.918023 == TX Byte 1 ==
6934 05:53:34.924645 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6935 05:53:34.927767 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6936 05:53:34.927851 ==
6937 05:53:34.931381 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 05:53:34.934602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 05:53:34.934686 ==
6940 05:53:34.934754
6941 05:53:34.934814
6942 05:53:34.937739 TX Vref Scan disable
6943 05:53:34.937822 == TX Byte 0 ==
6944 05:53:34.944597 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6945 05:53:34.947686 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6946 05:53:34.947771 == TX Byte 1 ==
6947 05:53:34.954525 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6948 05:53:34.957993 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6949 05:53:34.958077
6950 05:53:34.958143 [DATLAT]
6951 05:53:34.961624 Freq=400, CH1 RK1
6952 05:53:34.961723
6953 05:53:34.961818 DATLAT Default: 0xe
6954 05:53:34.964666 0, 0xFFFF, sum = 0
6955 05:53:34.964751 1, 0xFFFF, sum = 0
6956 05:53:34.968234 2, 0xFFFF, sum = 0
6957 05:53:34.968319 3, 0xFFFF, sum = 0
6958 05:53:34.971010 4, 0xFFFF, sum = 0
6959 05:53:34.971094 5, 0xFFFF, sum = 0
6960 05:53:34.974197 6, 0xFFFF, sum = 0
6961 05:53:34.974282 7, 0xFFFF, sum = 0
6962 05:53:34.977772 8, 0xFFFF, sum = 0
6963 05:53:34.977857 9, 0xFFFF, sum = 0
6964 05:53:34.981108 10, 0xFFFF, sum = 0
6965 05:53:34.984374 11, 0xFFFF, sum = 0
6966 05:53:34.984458 12, 0xFFFF, sum = 0
6967 05:53:34.987456 13, 0x0, sum = 1
6968 05:53:34.987542 14, 0x0, sum = 2
6969 05:53:34.987609 15, 0x0, sum = 3
6970 05:53:34.991131 16, 0x0, sum = 4
6971 05:53:34.991216 best_step = 14
6972 05:53:34.991282
6973 05:53:34.994381 ==
6974 05:53:34.994465 Dram Type= 6, Freq= 0, CH_1, rank 1
6975 05:53:35.000936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6976 05:53:35.001020 ==
6977 05:53:35.001086 RX Vref Scan: 0
6978 05:53:35.001149
6979 05:53:35.004377 RX Vref 0 -> 0, step: 1
6980 05:53:35.004460
6981 05:53:35.007545 RX Delay -327 -> 252, step: 8
6982 05:53:35.014491 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6983 05:53:35.017900 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6984 05:53:35.020944 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6985 05:53:35.024164 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6986 05:53:35.030812 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6987 05:53:35.034399 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6988 05:53:35.037827 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6989 05:53:35.040783 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6990 05:53:35.047601 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6991 05:53:35.050761 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6992 05:53:35.054279 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6993 05:53:35.057596 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6994 05:53:35.064276 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6995 05:53:35.067602 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6996 05:53:35.070909 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6997 05:53:35.077424 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6998 05:53:35.077508 ==
6999 05:53:35.080981 Dram Type= 6, Freq= 0, CH_1, rank 1
7000 05:53:35.084298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7001 05:53:35.084382 ==
7002 05:53:35.084449 DQS Delay:
7003 05:53:35.087632 DQS0 = 32, DQS1 = 36
7004 05:53:35.087715 DQM Delay:
7005 05:53:35.090765 DQM0 = 12, DQM1 = 10
7006 05:53:35.090849 DQ Delay:
7007 05:53:35.094237 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
7008 05:53:35.097571 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =12
7009 05:53:35.100900 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7010 05:53:35.104242 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
7011 05:53:35.104326
7012 05:53:35.104392
7013 05:53:35.110661 [DQSOSCAuto] RK1, (LSB)MR18= 0xa34b, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 389 ps
7014 05:53:35.114068 CH1 RK1: MR19=C0C, MR18=A34B
7015 05:53:35.120808 CH1_RK1: MR19=0xC0C, MR18=0xA34B, DQSOSC=389, MR23=63, INC=390, DEC=260
7016 05:53:35.124160 [RxdqsGatingPostProcess] freq 400
7017 05:53:35.130655 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7018 05:53:35.134112 best DQS0 dly(2T, 0.5T) = (0, 10)
7019 05:53:35.134223 best DQS1 dly(2T, 0.5T) = (0, 10)
7020 05:53:35.137284 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7021 05:53:35.140448 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7022 05:53:35.143572 best DQS0 dly(2T, 0.5T) = (0, 10)
7023 05:53:35.147173 best DQS1 dly(2T, 0.5T) = (0, 10)
7024 05:53:35.150348 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7025 05:53:35.153529 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7026 05:53:35.157088 Pre-setting of DQS Precalculation
7027 05:53:35.163633 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7028 05:53:35.170531 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7029 05:53:35.177145 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7030 05:53:35.177230
7031 05:53:35.177294
7032 05:53:35.180487 [Calibration Summary] 800 Mbps
7033 05:53:35.180571 CH 0, Rank 0
7034 05:53:35.183608 SW Impedance : PASS
7035 05:53:35.186898 DUTY Scan : NO K
7036 05:53:35.186997 ZQ Calibration : PASS
7037 05:53:35.190197 Jitter Meter : NO K
7038 05:53:35.193326 CBT Training : PASS
7039 05:53:35.193438 Write leveling : PASS
7040 05:53:35.197320 RX DQS gating : PASS
7041 05:53:35.197404 RX DQ/DQS(RDDQC) : PASS
7042 05:53:35.200310 TX DQ/DQS : PASS
7043 05:53:35.203933 RX DATLAT : PASS
7044 05:53:35.204017 RX DQ/DQS(Engine): PASS
7045 05:53:35.206960 TX OE : NO K
7046 05:53:35.207043 All Pass.
7047 05:53:35.207109
7048 05:53:35.210193 CH 0, Rank 1
7049 05:53:35.210275 SW Impedance : PASS
7050 05:53:35.213537 DUTY Scan : NO K
7051 05:53:35.216853 ZQ Calibration : PASS
7052 05:53:35.216936 Jitter Meter : NO K
7053 05:53:35.220354 CBT Training : PASS
7054 05:53:35.223638 Write leveling : NO K
7055 05:53:35.223721 RX DQS gating : PASS
7056 05:53:35.226477 RX DQ/DQS(RDDQC) : PASS
7057 05:53:35.230108 TX DQ/DQS : PASS
7058 05:53:35.230191 RX DATLAT : PASS
7059 05:53:35.233677 RX DQ/DQS(Engine): PASS
7060 05:53:35.236836 TX OE : NO K
7061 05:53:35.236919 All Pass.
7062 05:53:35.236986
7063 05:53:35.237045 CH 1, Rank 0
7064 05:53:35.240094 SW Impedance : PASS
7065 05:53:35.243127 DUTY Scan : NO K
7066 05:53:35.243211 ZQ Calibration : PASS
7067 05:53:35.246466 Jitter Meter : NO K
7068 05:53:35.246550 CBT Training : PASS
7069 05:53:35.249843 Write leveling : PASS
7070 05:53:35.253097 RX DQS gating : PASS
7071 05:53:35.253190 RX DQ/DQS(RDDQC) : PASS
7072 05:53:35.256690 TX DQ/DQS : PASS
7073 05:53:35.259793 RX DATLAT : PASS
7074 05:53:35.259903 RX DQ/DQS(Engine): PASS
7075 05:53:35.263324 TX OE : NO K
7076 05:53:35.263434 All Pass.
7077 05:53:35.263528
7078 05:53:35.266712 CH 1, Rank 1
7079 05:53:35.266795 SW Impedance : PASS
7080 05:53:35.269859 DUTY Scan : NO K
7081 05:53:35.273113 ZQ Calibration : PASS
7082 05:53:35.273197 Jitter Meter : NO K
7083 05:53:35.276683 CBT Training : PASS
7084 05:53:35.279592 Write leveling : NO K
7085 05:53:35.279676 RX DQS gating : PASS
7086 05:53:35.283330 RX DQ/DQS(RDDQC) : PASS
7087 05:53:35.286220 TX DQ/DQS : PASS
7088 05:53:35.286304 RX DATLAT : PASS
7089 05:53:35.289828 RX DQ/DQS(Engine): PASS
7090 05:53:35.293154 TX OE : NO K
7091 05:53:35.293238 All Pass.
7092 05:53:35.293305
7093 05:53:35.293365 DramC Write-DBI off
7094 05:53:35.296424 PER_BANK_REFRESH: Hybrid Mode
7095 05:53:35.299664 TX_TRACKING: ON
7096 05:53:35.306387 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7097 05:53:35.309701 [FAST_K] Save calibration result to emmc
7098 05:53:35.316235 dramc_set_vcore_voltage set vcore to 725000
7099 05:53:35.316318 Read voltage for 1600, 0
7100 05:53:35.319489 Vio18 = 0
7101 05:53:35.319581 Vcore = 725000
7102 05:53:35.319648 Vdram = 0
7103 05:53:35.322773 Vddq = 0
7104 05:53:35.322857 Vmddr = 0
7105 05:53:35.326083 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7106 05:53:35.332550 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7107 05:53:35.336168 MEM_TYPE=3, freq_sel=13
7108 05:53:35.339344 sv_algorithm_assistance_LP4_3733
7109 05:53:35.342642 ============ PULL DRAM RESETB DOWN ============
7110 05:53:35.345732 ========== PULL DRAM RESETB DOWN end =========
7111 05:53:35.349119 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7112 05:53:35.352304 ===================================
7113 05:53:35.355577 LPDDR4 DRAM CONFIGURATION
7114 05:53:35.359250 ===================================
7115 05:53:35.362525 EX_ROW_EN[0] = 0x0
7116 05:53:35.362608 EX_ROW_EN[1] = 0x0
7117 05:53:35.365604 LP4Y_EN = 0x0
7118 05:53:35.365716 WORK_FSP = 0x1
7119 05:53:35.369235 WL = 0x5
7120 05:53:35.369319 RL = 0x5
7121 05:53:35.372396 BL = 0x2
7122 05:53:35.372479 RPST = 0x0
7123 05:53:35.375898 RD_PRE = 0x0
7124 05:53:35.375982 WR_PRE = 0x1
7125 05:53:35.379096 WR_PST = 0x1
7126 05:53:35.382623 DBI_WR = 0x0
7127 05:53:35.382707 DBI_RD = 0x0
7128 05:53:35.385713 OTF = 0x1
7129 05:53:35.389102 ===================================
7130 05:53:35.392259 ===================================
7131 05:53:35.392388 ANA top config
7132 05:53:35.395521 ===================================
7133 05:53:35.398775 DLL_ASYNC_EN = 0
7134 05:53:35.402132 ALL_SLAVE_EN = 0
7135 05:53:35.402242 NEW_RANK_MODE = 1
7136 05:53:35.405714 DLL_IDLE_MODE = 1
7137 05:53:35.408896 LP45_APHY_COMB_EN = 1
7138 05:53:35.412054 TX_ODT_DIS = 0
7139 05:53:35.412138 NEW_8X_MODE = 1
7140 05:53:35.415640 ===================================
7141 05:53:35.418983 ===================================
7142 05:53:35.422199 data_rate = 3200
7143 05:53:35.425544 CKR = 1
7144 05:53:35.428688 DQ_P2S_RATIO = 8
7145 05:53:35.431971 ===================================
7146 05:53:35.435300 CA_P2S_RATIO = 8
7147 05:53:35.438913 DQ_CA_OPEN = 0
7148 05:53:35.439011 DQ_SEMI_OPEN = 0
7149 05:53:35.442265 CA_SEMI_OPEN = 0
7150 05:53:35.445685 CA_FULL_RATE = 0
7151 05:53:35.448870 DQ_CKDIV4_EN = 0
7152 05:53:35.451924 CA_CKDIV4_EN = 0
7153 05:53:35.455189 CA_PREDIV_EN = 0
7154 05:53:35.455273 PH8_DLY = 12
7155 05:53:35.458428 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7156 05:53:35.462094 DQ_AAMCK_DIV = 4
7157 05:53:35.465293 CA_AAMCK_DIV = 4
7158 05:53:35.468451 CA_ADMCK_DIV = 4
7159 05:53:35.472011 DQ_TRACK_CA_EN = 0
7160 05:53:35.475380 CA_PICK = 1600
7161 05:53:35.475464 CA_MCKIO = 1600
7162 05:53:35.478558 MCKIO_SEMI = 0
7163 05:53:35.481720 PLL_FREQ = 3068
7164 05:53:35.484995 DQ_UI_PI_RATIO = 32
7165 05:53:35.488298 CA_UI_PI_RATIO = 0
7166 05:53:35.492059 ===================================
7167 05:53:35.494976 ===================================
7168 05:53:35.498618 memory_type:LPDDR4
7169 05:53:35.498701 GP_NUM : 10
7170 05:53:35.501918 SRAM_EN : 1
7171 05:53:35.502022 MD32_EN : 0
7172 05:53:35.505312 ===================================
7173 05:53:35.508701 [ANA_INIT] >>>>>>>>>>>>>>
7174 05:53:35.511891 <<<<<< [CONFIGURE PHASE]: ANA_TX
7175 05:53:35.515147 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7176 05:53:35.518517 ===================================
7177 05:53:35.521796 data_rate = 3200,PCW = 0X7600
7178 05:53:35.525015 ===================================
7179 05:53:35.528487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7180 05:53:35.531781 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7181 05:53:35.538358 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7182 05:53:35.544800 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7183 05:53:35.548237 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7184 05:53:35.551787 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7185 05:53:35.551871 [ANA_INIT] flow start
7186 05:53:35.554764 [ANA_INIT] PLL >>>>>>>>
7187 05:53:35.558441 [ANA_INIT] PLL <<<<<<<<
7188 05:53:35.558524 [ANA_INIT] MIDPI >>>>>>>>
7189 05:53:35.561554 [ANA_INIT] MIDPI <<<<<<<<
7190 05:53:35.564893 [ANA_INIT] DLL >>>>>>>>
7191 05:53:35.564977 [ANA_INIT] DLL <<<<<<<<
7192 05:53:35.568020 [ANA_INIT] flow end
7193 05:53:35.571640 ============ LP4 DIFF to SE enter ============
7194 05:53:35.574830 ============ LP4 DIFF to SE exit ============
7195 05:53:35.577956 [ANA_INIT] <<<<<<<<<<<<<
7196 05:53:35.581279 [Flow] Enable top DCM control >>>>>
7197 05:53:35.584674 [Flow] Enable top DCM control <<<<<
7198 05:53:35.588212 Enable DLL master slave shuffle
7199 05:53:35.594956 ==============================================================
7200 05:53:35.595041 Gating Mode config
7201 05:53:35.601319 ==============================================================
7202 05:53:35.601404 Config description:
7203 05:53:35.611565 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7204 05:53:35.617809 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7205 05:53:35.624997 SELPH_MODE 0: By rank 1: By Phase
7206 05:53:35.627838 ==============================================================
7207 05:53:35.631131 GAT_TRACK_EN = 1
7208 05:53:35.634556 RX_GATING_MODE = 2
7209 05:53:35.637982 RX_GATING_TRACK_MODE = 2
7210 05:53:35.641351 SELPH_MODE = 1
7211 05:53:35.644560 PICG_EARLY_EN = 1
7212 05:53:35.647875 VALID_LAT_VALUE = 1
7213 05:53:35.654865 ==============================================================
7214 05:53:35.658064 Enter into Gating configuration >>>>
7215 05:53:35.661155 Exit from Gating configuration <<<<
7216 05:53:35.664531 Enter into DVFS_PRE_config >>>>>
7217 05:53:35.674462 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7218 05:53:35.677620 Exit from DVFS_PRE_config <<<<<
7219 05:53:35.681234 Enter into PICG configuration >>>>
7220 05:53:35.684555 Exit from PICG configuration <<<<
7221 05:53:35.687679 [RX_INPUT] configuration >>>>>
7222 05:53:35.687763 [RX_INPUT] configuration <<<<<
7223 05:53:35.694566 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7224 05:53:35.701154 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7225 05:53:35.704279 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7226 05:53:35.711172 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7227 05:53:35.717778 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7228 05:53:35.724340 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7229 05:53:35.727664 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7230 05:53:35.730939 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7231 05:53:35.737628 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7232 05:53:35.740901 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7233 05:53:35.744203 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7234 05:53:35.747841 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7235 05:53:35.751007 ===================================
7236 05:53:35.754202 LPDDR4 DRAM CONFIGURATION
7237 05:53:35.757534 ===================================
7238 05:53:35.760805 EX_ROW_EN[0] = 0x0
7239 05:53:35.760888 EX_ROW_EN[1] = 0x0
7240 05:53:35.764332 LP4Y_EN = 0x0
7241 05:53:35.764415 WORK_FSP = 0x1
7242 05:53:35.767742 WL = 0x5
7243 05:53:35.767825 RL = 0x5
7244 05:53:35.771164 BL = 0x2
7245 05:53:35.771247 RPST = 0x0
7246 05:53:35.774184 RD_PRE = 0x0
7247 05:53:35.774291 WR_PRE = 0x1
7248 05:53:35.777692 WR_PST = 0x1
7249 05:53:35.777775 DBI_WR = 0x0
7250 05:53:35.780889 DBI_RD = 0x0
7251 05:53:35.784188 OTF = 0x1
7252 05:53:35.787624 ===================================
7253 05:53:35.790738 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7254 05:53:35.794238 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7255 05:53:35.797569 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 05:53:35.800996 ===================================
7257 05:53:35.804268 LPDDR4 DRAM CONFIGURATION
7258 05:53:35.807676 ===================================
7259 05:53:35.810693 EX_ROW_EN[0] = 0x10
7260 05:53:35.810777 EX_ROW_EN[1] = 0x0
7261 05:53:35.814341 LP4Y_EN = 0x0
7262 05:53:35.814424 WORK_FSP = 0x1
7263 05:53:35.817627 WL = 0x5
7264 05:53:35.817710 RL = 0x5
7265 05:53:35.821007 BL = 0x2
7266 05:53:35.821090 RPST = 0x0
7267 05:53:35.824177 RD_PRE = 0x0
7268 05:53:35.824261 WR_PRE = 0x1
7269 05:53:35.827543 WR_PST = 0x1
7270 05:53:35.827627 DBI_WR = 0x0
7271 05:53:35.830960 DBI_RD = 0x0
7272 05:53:35.831044 OTF = 0x1
7273 05:53:35.834354 ===================================
7274 05:53:35.840800 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7275 05:53:35.840884 ==
7276 05:53:35.844457 Dram Type= 6, Freq= 0, CH_0, rank 0
7277 05:53:35.850605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7278 05:53:35.850690 ==
7279 05:53:35.850756 [Duty_Offset_Calibration]
7280 05:53:35.854166 B0:2 B1:0 CA:1
7281 05:53:35.854249
7282 05:53:35.857006 [DutyScan_Calibration_Flow] k_type=0
7283 05:53:35.865963
7284 05:53:35.866046 ==CLK 0==
7285 05:53:35.869452 Final CLK duty delay cell = -4
7286 05:53:35.872302 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7287 05:53:35.875627 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7288 05:53:35.879003 [-4] AVG Duty = 4922%(X100)
7289 05:53:35.879086
7290 05:53:35.882189 CH0 CLK Duty spec in!! Max-Min= 218%
7291 05:53:35.885782 [DutyScan_Calibration_Flow] ====Done====
7292 05:53:35.885865
7293 05:53:35.888831 [DutyScan_Calibration_Flow] k_type=1
7294 05:53:35.905039
7295 05:53:35.905122 ==DQS 0 ==
7296 05:53:35.908411 Final DQS duty delay cell = 0
7297 05:53:35.911954 [0] MAX Duty = 5249%(X100), DQS PI = 32
7298 05:53:35.914928 [0] MIN Duty = 4969%(X100), DQS PI = 0
7299 05:53:35.918621 [0] AVG Duty = 5109%(X100)
7300 05:53:35.918705
7301 05:53:35.918771 ==DQS 1 ==
7302 05:53:35.922295 Final DQS duty delay cell = -4
7303 05:53:35.925112 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7304 05:53:35.928424 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7305 05:53:35.931655 [-4] AVG Duty = 5000%(X100)
7306 05:53:35.931738
7307 05:53:35.935084 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7308 05:53:35.935168
7309 05:53:35.938360 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7310 05:53:35.941733 [DutyScan_Calibration_Flow] ====Done====
7311 05:53:35.941817
7312 05:53:35.945096 [DutyScan_Calibration_Flow] k_type=3
7313 05:53:35.962456
7314 05:53:35.962542 ==DQM 0 ==
7315 05:53:35.965735 Final DQM duty delay cell = 0
7316 05:53:35.969403 [0] MAX Duty = 5093%(X100), DQS PI = 24
7317 05:53:35.972703 [0] MIN Duty = 4813%(X100), DQS PI = 50
7318 05:53:35.975876 [0] AVG Duty = 4953%(X100)
7319 05:53:35.975959
7320 05:53:35.976025 ==DQM 1 ==
7321 05:53:35.979229 Final DQM duty delay cell = 0
7322 05:53:35.982773 [0] MAX Duty = 5249%(X100), DQS PI = 28
7323 05:53:35.985894 [0] MIN Duty = 5000%(X100), DQS PI = 20
7324 05:53:35.989364 [0] AVG Duty = 5124%(X100)
7325 05:53:35.989447
7326 05:53:35.992399 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7327 05:53:35.992483
7328 05:53:35.995975 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7329 05:53:35.999343 [DutyScan_Calibration_Flow] ====Done====
7330 05:53:35.999437
7331 05:53:36.002342 [DutyScan_Calibration_Flow] k_type=2
7332 05:53:36.019822
7333 05:53:36.019905 ==DQ 0 ==
7334 05:53:36.023144 Final DQ duty delay cell = 0
7335 05:53:36.026489 [0] MAX Duty = 5124%(X100), DQS PI = 34
7336 05:53:36.029631 [0] MIN Duty = 5000%(X100), DQS PI = 0
7337 05:53:36.029715 [0] AVG Duty = 5062%(X100)
7338 05:53:36.033246
7339 05:53:36.033329 ==DQ 1 ==
7340 05:53:36.036150 Final DQ duty delay cell = 0
7341 05:53:36.039903 [0] MAX Duty = 4969%(X100), DQS PI = 42
7342 05:53:36.043224 [0] MIN Duty = 4875%(X100), DQS PI = 10
7343 05:53:36.043308 [0] AVG Duty = 4922%(X100)
7344 05:53:36.043374
7345 05:53:36.049790 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7346 05:53:36.049873
7347 05:53:36.053247 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7348 05:53:36.056568 [DutyScan_Calibration_Flow] ====Done====
7349 05:53:36.056650 ==
7350 05:53:36.059634 Dram Type= 6, Freq= 0, CH_1, rank 0
7351 05:53:36.063091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7352 05:53:36.063174 ==
7353 05:53:36.066407 [Duty_Offset_Calibration]
7354 05:53:36.066488 B0:0 B1:-1 CA:2
7355 05:53:36.066553
7356 05:53:36.069513 [DutyScan_Calibration_Flow] k_type=0
7357 05:53:36.080148
7358 05:53:36.080230 ==CLK 0==
7359 05:53:36.083387 Final CLK duty delay cell = 0
7360 05:53:36.086778 [0] MAX Duty = 5156%(X100), DQS PI = 10
7361 05:53:36.089887 [0] MIN Duty = 4906%(X100), DQS PI = 46
7362 05:53:36.093289 [0] AVG Duty = 5031%(X100)
7363 05:53:36.093371
7364 05:53:36.096396 CH1 CLK Duty spec in!! Max-Min= 250%
7365 05:53:36.099593 [DutyScan_Calibration_Flow] ====Done====
7366 05:53:36.099674
7367 05:53:36.102925 [DutyScan_Calibration_Flow] k_type=1
7368 05:53:36.119578
7369 05:53:36.119659 ==DQS 0 ==
7370 05:53:36.123241 Final DQS duty delay cell = 0
7371 05:53:36.126361 [0] MAX Duty = 5093%(X100), DQS PI = 26
7372 05:53:36.129634 [0] MIN Duty = 4969%(X100), DQS PI = 0
7373 05:53:36.129715 [0] AVG Duty = 5031%(X100)
7374 05:53:36.132929
7375 05:53:36.133009 ==DQS 1 ==
7376 05:53:36.136429 Final DQS duty delay cell = 0
7377 05:53:36.139694 [0] MAX Duty = 5187%(X100), DQS PI = 0
7378 05:53:36.142972 [0] MIN Duty = 4844%(X100), DQS PI = 32
7379 05:53:36.143053 [0] AVG Duty = 5015%(X100)
7380 05:53:36.146369
7381 05:53:36.149577 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7382 05:53:36.149658
7383 05:53:36.152924 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7384 05:53:36.156160 [DutyScan_Calibration_Flow] ====Done====
7385 05:53:36.156258
7386 05:53:36.159545 [DutyScan_Calibration_Flow] k_type=3
7387 05:53:36.177149
7388 05:53:36.177230 ==DQM 0 ==
7389 05:53:36.180853 Final DQM duty delay cell = 4
7390 05:53:36.183993 [4] MAX Duty = 5125%(X100), DQS PI = 8
7391 05:53:36.187293 [4] MIN Duty = 5000%(X100), DQS PI = 30
7392 05:53:36.190574 [4] AVG Duty = 5062%(X100)
7393 05:53:36.190655
7394 05:53:36.190719 ==DQM 1 ==
7395 05:53:36.193822 Final DQM duty delay cell = 0
7396 05:53:36.197403 [0] MAX Duty = 5281%(X100), DQS PI = 60
7397 05:53:36.200668 [0] MIN Duty = 4876%(X100), DQS PI = 34
7398 05:53:36.200750 [0] AVG Duty = 5078%(X100)
7399 05:53:36.204163
7400 05:53:36.207452 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7401 05:53:36.207534
7402 05:53:36.210596 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7403 05:53:36.213865 [DutyScan_Calibration_Flow] ====Done====
7404 05:53:36.213969
7405 05:53:36.217354 [DutyScan_Calibration_Flow] k_type=2
7406 05:53:36.234327
7407 05:53:36.234407 ==DQ 0 ==
7408 05:53:36.237691 Final DQ duty delay cell = 0
7409 05:53:36.240874 [0] MAX Duty = 5093%(X100), DQS PI = 18
7410 05:53:36.244146 [0] MIN Duty = 4969%(X100), DQS PI = 46
7411 05:53:36.244228 [0] AVG Duty = 5031%(X100)
7412 05:53:36.244292
7413 05:53:36.247482 ==DQ 1 ==
7414 05:53:36.250793 Final DQ duty delay cell = 0
7415 05:53:36.254060 [0] MAX Duty = 5062%(X100), DQS PI = 2
7416 05:53:36.257306 [0] MIN Duty = 4813%(X100), DQS PI = 34
7417 05:53:36.257387 [0] AVG Duty = 4937%(X100)
7418 05:53:36.257452
7419 05:53:36.260762 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7420 05:53:36.264084
7421 05:53:36.267412 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7422 05:53:36.270521 [DutyScan_Calibration_Flow] ====Done====
7423 05:53:36.274095 nWR fixed to 30
7424 05:53:36.274177 [ModeRegInit_LP4] CH0 RK0
7425 05:53:36.277573 [ModeRegInit_LP4] CH0 RK1
7426 05:53:36.280885 [ModeRegInit_LP4] CH1 RK0
7427 05:53:36.280967 [ModeRegInit_LP4] CH1 RK1
7428 05:53:36.284155 match AC timing 5
7429 05:53:36.287311 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7430 05:53:36.293757 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7431 05:53:36.297074 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7432 05:53:36.300382 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7433 05:53:36.307572 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7434 05:53:36.307657 [MiockJmeterHQA]
7435 05:53:36.307723
7436 05:53:36.310543 [DramcMiockJmeter] u1RxGatingPI = 0
7437 05:53:36.313835 0 : 4252, 4026
7438 05:53:36.313922 4 : 4253, 4027
7439 05:53:36.314013 8 : 4253, 4027
7440 05:53:36.317365 12 : 4255, 4029
7441 05:53:36.317450 16 : 4363, 4138
7442 05:53:36.320423 20 : 4253, 4027
7443 05:53:36.320508 24 : 4252, 4026
7444 05:53:36.323854 28 : 4252, 4027
7445 05:53:36.323938 32 : 4254, 4029
7446 05:53:36.327319 36 : 4363, 4137
7447 05:53:36.327404 40 : 4253, 4027
7448 05:53:36.327472 44 : 4252, 4027
7449 05:53:36.330449 48 : 4253, 4026
7450 05:53:36.330533 52 : 4255, 4029
7451 05:53:36.334121 56 : 4250, 4027
7452 05:53:36.334206 60 : 4360, 4138
7453 05:53:36.337163 64 : 4360, 4137
7454 05:53:36.337248 68 : 4250, 4027
7455 05:53:36.340706 72 : 4250, 4027
7456 05:53:36.340791 76 : 4250, 4026
7457 05:53:36.340859 80 : 4250, 4027
7458 05:53:36.343663 84 : 4252, 4029
7459 05:53:36.343748 88 : 4360, 3533
7460 05:53:36.347110 92 : 4250, 0
7461 05:53:36.347194 96 : 4250, 0
7462 05:53:36.347262 100 : 4250, 0
7463 05:53:36.350752 104 : 4361, 0
7464 05:53:36.350837 108 : 4250, 0
7465 05:53:36.353539 112 : 4250, 0
7466 05:53:36.353624 116 : 4250, 0
7467 05:53:36.353691 120 : 4252, 0
7468 05:53:36.356938 124 : 4250, 0
7469 05:53:36.357022 128 : 4250, 0
7470 05:53:36.360165 132 : 4252, 0
7471 05:53:36.360249 136 : 4360, 0
7472 05:53:36.360317 140 : 4361, 0
7473 05:53:36.363508 144 : 4250, 0
7474 05:53:36.363593 148 : 4250, 0
7475 05:53:36.363661 152 : 4250, 0
7476 05:53:36.366724 156 : 4250, 0
7477 05:53:36.366808 160 : 4253, 0
7478 05:53:36.370084 164 : 4250, 0
7479 05:53:36.370168 168 : 4250, 0
7480 05:53:36.370235 172 : 4250, 0
7481 05:53:36.373612 176 : 4250, 0
7482 05:53:36.373697 180 : 4250, 0
7483 05:53:36.376881 184 : 4250, 0
7484 05:53:36.376966 188 : 4250, 0
7485 05:53:36.377034 192 : 4250, 0
7486 05:53:36.380193 196 : 4360, 0
7487 05:53:36.380277 200 : 4361, 5
7488 05:53:36.383540 204 : 4360, 2407
7489 05:53:36.383624 208 : 4363, 4139
7490 05:53:36.386858 212 : 4249, 4027
7491 05:53:36.386942 216 : 4360, 4137
7492 05:53:36.387010 220 : 4361, 4137
7493 05:53:36.390575 224 : 4250, 4027
7494 05:53:36.390660 228 : 4250, 4027
7495 05:53:36.393797 232 : 4362, 4140
7496 05:53:36.393881 236 : 4250, 4026
7497 05:53:36.397129 240 : 4250, 4027
7498 05:53:36.397213 244 : 4250, 4027
7499 05:53:36.400058 248 : 4252, 4029
7500 05:53:36.400144 252 : 4250, 4026
7501 05:53:36.403433 256 : 4250, 4027
7502 05:53:36.403518 260 : 4360, 4138
7503 05:53:36.407170 264 : 4250, 4027
7504 05:53:36.407255 268 : 4250, 4026
7505 05:53:36.410188 272 : 4361, 4137
7506 05:53:36.410273 276 : 4250, 4027
7507 05:53:36.410340 280 : 4250, 4027
7508 05:53:36.413495 284 : 4362, 4140
7509 05:53:36.413579 288 : 4250, 4026
7510 05:53:36.416992 292 : 4250, 4027
7511 05:53:36.417077 296 : 4250, 4027
7512 05:53:36.420057 300 : 4252, 4029
7513 05:53:36.420141 304 : 4250, 4026
7514 05:53:36.423482 308 : 4250, 4027
7515 05:53:36.423566 312 : 4360, 3873
7516 05:53:36.426913 316 : 4249, 1969
7517 05:53:36.426998
7518 05:53:36.427064 MIOCK jitter meter ch=0
7519 05:53:36.427127
7520 05:53:36.430034 1T = (316-92) = 224 dly cells
7521 05:53:36.436512 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7522 05:53:36.436596 ==
7523 05:53:36.439938 Dram Type= 6, Freq= 0, CH_0, rank 0
7524 05:53:36.443237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 05:53:36.443321 ==
7526 05:53:36.450116 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7527 05:53:36.453629 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7528 05:53:36.459724 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7529 05:53:36.463147 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7530 05:53:36.472981 [CA 0] Center 42 (12~72) winsize 61
7531 05:53:36.476217 [CA 1] Center 42 (12~72) winsize 61
7532 05:53:36.479564 [CA 2] Center 37 (7~67) winsize 61
7533 05:53:36.483026 [CA 3] Center 37 (7~67) winsize 61
7534 05:53:36.486336 [CA 4] Center 36 (6~66) winsize 61
7535 05:53:36.489602 [CA 5] Center 35 (5~65) winsize 61
7536 05:53:36.489712
7537 05:53:36.492909 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7538 05:53:36.492992
7539 05:53:36.496021 [CATrainingPosCal] consider 1 rank data
7540 05:53:36.499722 u2DelayCellTimex100 = 290/100 ps
7541 05:53:36.503110 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7542 05:53:36.509416 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7543 05:53:36.512685 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7544 05:53:36.516169 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7545 05:53:36.519450 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7546 05:53:36.522794 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7547 05:53:36.522877
7548 05:53:36.526165 CA PerBit enable=1, Macro0, CA PI delay=35
7549 05:53:36.526249
7550 05:53:36.529651 [CBTSetCACLKResult] CA Dly = 35
7551 05:53:36.532814 CS Dly: 9 (0~40)
7552 05:53:36.535968 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7553 05:53:36.539395 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7554 05:53:36.539479 ==
7555 05:53:36.542412 Dram Type= 6, Freq= 0, CH_0, rank 1
7556 05:53:36.545885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 05:53:36.549038 ==
7558 05:53:36.552418 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7559 05:53:36.556065 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7560 05:53:36.562641 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7561 05:53:36.565916 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7562 05:53:36.576161 [CA 0] Center 44 (14~74) winsize 61
7563 05:53:36.580006 [CA 1] Center 43 (13~73) winsize 61
7564 05:53:36.583028 [CA 2] Center 38 (9~68) winsize 60
7565 05:53:36.586219 [CA 3] Center 38 (9~68) winsize 60
7566 05:53:36.589697 [CA 4] Center 37 (7~67) winsize 61
7567 05:53:36.592646 [CA 5] Center 36 (6~66) winsize 61
7568 05:53:36.592730
7569 05:53:36.596398 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7570 05:53:36.596481
7571 05:53:36.599582 [CATrainingPosCal] consider 2 rank data
7572 05:53:36.602757 u2DelayCellTimex100 = 290/100 ps
7573 05:53:36.606056 CA0 delay=43 (14~72),Diff = 8 PI (26 cell)
7574 05:53:36.612645 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7575 05:53:36.616008 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7576 05:53:36.619484 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7577 05:53:36.623188 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7578 05:53:36.626156 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7579 05:53:36.626239
7580 05:53:36.629343 CA PerBit enable=1, Macro0, CA PI delay=35
7581 05:53:36.629427
7582 05:53:36.632856 [CBTSetCACLKResult] CA Dly = 35
7583 05:53:36.635764 CS Dly: 10 (0~43)
7584 05:53:36.639246 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7585 05:53:36.642721 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7586 05:53:36.642804
7587 05:53:36.646208 ----->DramcWriteLeveling(PI) begin...
7588 05:53:36.646294 ==
7589 05:53:36.649193 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 05:53:36.655993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 05:53:36.656076 ==
7592 05:53:36.659245 Write leveling (Byte 0): 37 => 37
7593 05:53:36.659331 Write leveling (Byte 1): 31 => 31
7594 05:53:36.662444 DramcWriteLeveling(PI) end<-----
7595 05:53:36.662528
7596 05:53:36.665682 ==
7597 05:53:36.665766 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 05:53:36.672450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 05:53:36.672534 ==
7600 05:53:36.675775 [Gating] SW mode calibration
7601 05:53:36.682501 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7602 05:53:36.685545 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7603 05:53:36.692514 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 05:53:36.695867 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 05:53:36.699181 1 4 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
7606 05:53:36.705807 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7607 05:53:36.708970 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7608 05:53:36.712344 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7609 05:53:36.718904 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 05:53:36.722437 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 05:53:36.725639 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 05:53:36.732385 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 05:53:36.735636 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7614 05:53:36.738854 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7615 05:53:36.742657 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7616 05:53:36.748958 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7617 05:53:36.752261 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7618 05:53:36.755824 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 05:53:36.762504 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 05:53:36.765504 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 05:53:36.768630 1 6 8 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7622 05:53:36.775327 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7623 05:53:36.778629 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7624 05:53:36.782290 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 05:53:36.788337 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 05:53:36.791935 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 05:53:36.795429 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 05:53:36.801615 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 05:53:36.804867 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 05:53:36.808208 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7631 05:53:36.815094 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7632 05:53:36.818360 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7633 05:53:36.821689 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7634 05:53:36.827929 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 05:53:36.831250 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 05:53:36.834651 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 05:53:36.841344 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 05:53:36.844783 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 05:53:36.847865 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 05:53:36.854444 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 05:53:36.857904 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 05:53:36.861173 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 05:53:36.867803 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 05:53:36.871051 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 05:53:36.874467 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7646 05:53:36.881037 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7647 05:53:36.884414 Total UI for P1: 0, mck2ui 16
7648 05:53:36.887502 best dqsien dly found for B0: ( 1, 9, 8)
7649 05:53:36.890743 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7650 05:53:36.893931 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7651 05:53:36.900812 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 05:53:36.900897 Total UI for P1: 0, mck2ui 16
7653 05:53:36.907425 best dqsien dly found for B1: ( 1, 9, 18)
7654 05:53:36.910751 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7655 05:53:36.913811 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7656 05:53:36.913896
7657 05:53:36.917123 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7658 05:53:36.920331 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7659 05:53:36.924075 [Gating] SW calibration Done
7660 05:53:36.924159 ==
7661 05:53:36.927028 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 05:53:36.930628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 05:53:36.930712 ==
7664 05:53:36.933922 RX Vref Scan: 0
7665 05:53:36.934048
7666 05:53:36.934116 RX Vref 0 -> 0, step: 1
7667 05:53:36.937134
7668 05:53:36.937218 RX Delay 0 -> 252, step: 8
7669 05:53:36.940317 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7670 05:53:36.947221 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7671 05:53:36.950435 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7672 05:53:36.953590 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7673 05:53:36.957149 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7674 05:53:36.960308 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7675 05:53:36.966866 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7676 05:53:36.970149 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7677 05:53:36.973397 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7678 05:53:36.976698 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7679 05:53:36.980440 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7680 05:53:36.986677 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7681 05:53:36.990316 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7682 05:53:36.993068 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7683 05:53:36.997059 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7684 05:53:37.003042 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7685 05:53:37.003141 ==
7686 05:53:37.006347 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 05:53:37.009904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 05:53:37.010026 ==
7689 05:53:37.010094 DQS Delay:
7690 05:53:37.013176 DQS0 = 0, DQS1 = 0
7691 05:53:37.013259 DQM Delay:
7692 05:53:37.016284 DQM0 = 138, DQM1 = 127
7693 05:53:37.016375 DQ Delay:
7694 05:53:37.019566 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7695 05:53:37.022890 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7696 05:53:37.026180 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7697 05:53:37.029480 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7698 05:53:37.029564
7699 05:53:37.029628
7700 05:53:37.032815 ==
7701 05:53:37.036153 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 05:53:37.039639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 05:53:37.039727 ==
7704 05:53:37.039792
7705 05:53:37.039854
7706 05:53:37.042727 TX Vref Scan disable
7707 05:53:37.042801 == TX Byte 0 ==
7708 05:53:37.046370 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7709 05:53:37.052557 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7710 05:53:37.052632 == TX Byte 1 ==
7711 05:53:37.059354 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7712 05:53:37.062754 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7713 05:53:37.062828 ==
7714 05:53:37.066134 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 05:53:37.069151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 05:53:37.069223 ==
7717 05:53:37.082871
7718 05:53:37.085930 TX Vref early break, caculate TX vref
7719 05:53:37.089544 TX Vref=16, minBit 0, minWin=23, winSum=376
7720 05:53:37.092784 TX Vref=18, minBit 4, minWin=23, winSum=385
7721 05:53:37.096101 TX Vref=20, minBit 0, minWin=24, winSum=393
7722 05:53:37.099085 TX Vref=22, minBit 7, minWin=24, winSum=406
7723 05:53:37.102770 TX Vref=24, minBit 0, minWin=25, winSum=412
7724 05:53:37.109179 TX Vref=26, minBit 0, minWin=25, winSum=420
7725 05:53:37.112529 TX Vref=28, minBit 1, minWin=26, winSum=432
7726 05:53:37.115804 TX Vref=30, minBit 0, minWin=26, winSum=424
7727 05:53:37.118971 TX Vref=32, minBit 0, minWin=25, winSum=412
7728 05:53:37.122589 TX Vref=34, minBit 7, minWin=24, winSum=404
7729 05:53:37.129150 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 28
7730 05:53:37.129225
7731 05:53:37.132388 Final TX Range 0 Vref 28
7732 05:53:37.132463
7733 05:53:37.132525 ==
7734 05:53:37.135748 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 05:53:37.139007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 05:53:37.139078 ==
7737 05:53:37.139139
7738 05:53:37.139197
7739 05:53:37.142284 TX Vref Scan disable
7740 05:53:37.149163 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7741 05:53:37.149238 == TX Byte 0 ==
7742 05:53:37.152418 u2DelayCellOfst[0]=13 cells (4 PI)
7743 05:53:37.155686 u2DelayCellOfst[1]=16 cells (5 PI)
7744 05:53:37.158943 u2DelayCellOfst[2]=10 cells (3 PI)
7745 05:53:37.162241 u2DelayCellOfst[3]=10 cells (3 PI)
7746 05:53:37.165520 u2DelayCellOfst[4]=6 cells (2 PI)
7747 05:53:37.168906 u2DelayCellOfst[5]=0 cells (0 PI)
7748 05:53:37.172094 u2DelayCellOfst[6]=16 cells (5 PI)
7749 05:53:37.175491 u2DelayCellOfst[7]=13 cells (4 PI)
7750 05:53:37.179141 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7751 05:53:37.182153 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7752 05:53:37.185534 == TX Byte 1 ==
7753 05:53:37.185637 u2DelayCellOfst[8]=0 cells (0 PI)
7754 05:53:37.188914 u2DelayCellOfst[9]=0 cells (0 PI)
7755 05:53:37.192382 u2DelayCellOfst[10]=10 cells (3 PI)
7756 05:53:37.195774 u2DelayCellOfst[11]=3 cells (1 PI)
7757 05:53:37.198729 u2DelayCellOfst[12]=13 cells (4 PI)
7758 05:53:37.202221 u2DelayCellOfst[13]=13 cells (4 PI)
7759 05:53:37.205660 u2DelayCellOfst[14]=13 cells (4 PI)
7760 05:53:37.208946 u2DelayCellOfst[15]=10 cells (3 PI)
7761 05:53:37.212163 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7762 05:53:37.218764 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7763 05:53:37.218849 DramC Write-DBI on
7764 05:53:37.218916 ==
7765 05:53:37.222121 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 05:53:37.225271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 05:53:37.228670 ==
7768 05:53:37.228754
7769 05:53:37.228820
7770 05:53:37.228882 TX Vref Scan disable
7771 05:53:37.232180 == TX Byte 0 ==
7772 05:53:37.235463 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7773 05:53:37.238790 == TX Byte 1 ==
7774 05:53:37.242599 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7775 05:53:37.245622 DramC Write-DBI off
7776 05:53:37.245705
7777 05:53:37.245772 [DATLAT]
7778 05:53:37.245835 Freq=1600, CH0 RK0
7779 05:53:37.245895
7780 05:53:37.248893 DATLAT Default: 0xf
7781 05:53:37.248977 0, 0xFFFF, sum = 0
7782 05:53:37.252128 1, 0xFFFF, sum = 0
7783 05:53:37.255655 2, 0xFFFF, sum = 0
7784 05:53:37.255740 3, 0xFFFF, sum = 0
7785 05:53:37.259062 4, 0xFFFF, sum = 0
7786 05:53:37.259148 5, 0xFFFF, sum = 0
7787 05:53:37.261965 6, 0xFFFF, sum = 0
7788 05:53:37.262065 7, 0xFFFF, sum = 0
7789 05:53:37.265625 8, 0xFFFF, sum = 0
7790 05:53:37.265711 9, 0xFFFF, sum = 0
7791 05:53:37.268840 10, 0xFFFF, sum = 0
7792 05:53:37.268926 11, 0xFFFF, sum = 0
7793 05:53:37.272126 12, 0xFFFF, sum = 0
7794 05:53:37.272212 13, 0xFFFF, sum = 0
7795 05:53:37.275514 14, 0x0, sum = 1
7796 05:53:37.275599 15, 0x0, sum = 2
7797 05:53:37.278723 16, 0x0, sum = 3
7798 05:53:37.278808 17, 0x0, sum = 4
7799 05:53:37.281996 best_step = 15
7800 05:53:37.282094
7801 05:53:37.282160 ==
7802 05:53:37.285452 Dram Type= 6, Freq= 0, CH_0, rank 0
7803 05:53:37.288945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7804 05:53:37.289030 ==
7805 05:53:37.292196 RX Vref Scan: 1
7806 05:53:37.292280
7807 05:53:37.292347 Set Vref Range= 24 -> 127
7808 05:53:37.292409
7809 05:53:37.295149 RX Vref 24 -> 127, step: 1
7810 05:53:37.295233
7811 05:53:37.298576 RX Delay 19 -> 252, step: 4
7812 05:53:37.298660
7813 05:53:37.302285 Set Vref, RX VrefLevel [Byte0]: 24
7814 05:53:37.305291 [Byte1]: 24
7815 05:53:37.305375
7816 05:53:37.308612 Set Vref, RX VrefLevel [Byte0]: 25
7817 05:53:37.311879 [Byte1]: 25
7818 05:53:37.311964
7819 05:53:37.315101 Set Vref, RX VrefLevel [Byte0]: 26
7820 05:53:37.318413 [Byte1]: 26
7821 05:53:37.322792
7822 05:53:37.322876 Set Vref, RX VrefLevel [Byte0]: 27
7823 05:53:37.326339 [Byte1]: 27
7824 05:53:37.330121
7825 05:53:37.330216 Set Vref, RX VrefLevel [Byte0]: 28
7826 05:53:37.333506 [Byte1]: 28
7827 05:53:37.337825
7828 05:53:37.337936 Set Vref, RX VrefLevel [Byte0]: 29
7829 05:53:37.341085 [Byte1]: 29
7830 05:53:37.345332
7831 05:53:37.345416 Set Vref, RX VrefLevel [Byte0]: 30
7832 05:53:37.348671 [Byte1]: 30
7833 05:53:37.352845
7834 05:53:37.352929 Set Vref, RX VrefLevel [Byte0]: 31
7835 05:53:37.356203 [Byte1]: 31
7836 05:53:37.360547
7837 05:53:37.360631 Set Vref, RX VrefLevel [Byte0]: 32
7838 05:53:37.363792 [Byte1]: 32
7839 05:53:37.367958
7840 05:53:37.368042 Set Vref, RX VrefLevel [Byte0]: 33
7841 05:53:37.371547 [Byte1]: 33
7842 05:53:37.375640
7843 05:53:37.375724 Set Vref, RX VrefLevel [Byte0]: 34
7844 05:53:37.378968 [Byte1]: 34
7845 05:53:37.383135
7846 05:53:37.383218 Set Vref, RX VrefLevel [Byte0]: 35
7847 05:53:37.386830 [Byte1]: 35
7848 05:53:37.390806
7849 05:53:37.390911 Set Vref, RX VrefLevel [Byte0]: 36
7850 05:53:37.394307 [Byte1]: 36
7851 05:53:37.398249
7852 05:53:37.398336 Set Vref, RX VrefLevel [Byte0]: 37
7853 05:53:37.401838 [Byte1]: 37
7854 05:53:37.406224
7855 05:53:37.406307 Set Vref, RX VrefLevel [Byte0]: 38
7856 05:53:37.409329 [Byte1]: 38
7857 05:53:37.413613
7858 05:53:37.413696 Set Vref, RX VrefLevel [Byte0]: 39
7859 05:53:37.416669 [Byte1]: 39
7860 05:53:37.421267
7861 05:53:37.421350 Set Vref, RX VrefLevel [Byte0]: 40
7862 05:53:37.424173 [Byte1]: 40
7863 05:53:37.428734
7864 05:53:37.428817 Set Vref, RX VrefLevel [Byte0]: 41
7865 05:53:37.431833 [Byte1]: 41
7866 05:53:37.436300
7867 05:53:37.436384 Set Vref, RX VrefLevel [Byte0]: 42
7868 05:53:37.439595 [Byte1]: 42
7869 05:53:37.443922
7870 05:53:37.444006 Set Vref, RX VrefLevel [Byte0]: 43
7871 05:53:37.447187 [Byte1]: 43
7872 05:53:37.451353
7873 05:53:37.451436 Set Vref, RX VrefLevel [Byte0]: 44
7874 05:53:37.454619 [Byte1]: 44
7875 05:53:37.458955
7876 05:53:37.459039 Set Vref, RX VrefLevel [Byte0]: 45
7877 05:53:37.462106 [Byte1]: 45
7878 05:53:37.466415
7879 05:53:37.466499 Set Vref, RX VrefLevel [Byte0]: 46
7880 05:53:37.469668 [Byte1]: 46
7881 05:53:37.473862
7882 05:53:37.473974 Set Vref, RX VrefLevel [Byte0]: 47
7883 05:53:37.477441 [Byte1]: 47
7884 05:53:37.481710
7885 05:53:37.481793 Set Vref, RX VrefLevel [Byte0]: 48
7886 05:53:37.485097 [Byte1]: 48
7887 05:53:37.489194
7888 05:53:37.489278 Set Vref, RX VrefLevel [Byte0]: 49
7889 05:53:37.492748 [Byte1]: 49
7890 05:53:37.496703
7891 05:53:37.496787 Set Vref, RX VrefLevel [Byte0]: 50
7892 05:53:37.500089 [Byte1]: 50
7893 05:53:37.504338
7894 05:53:37.504423 Set Vref, RX VrefLevel [Byte0]: 51
7895 05:53:37.507781 [Byte1]: 51
7896 05:53:37.511892
7897 05:53:37.511975 Set Vref, RX VrefLevel [Byte0]: 52
7898 05:53:37.515326 [Byte1]: 52
7899 05:53:37.519537
7900 05:53:37.519626 Set Vref, RX VrefLevel [Byte0]: 53
7901 05:53:37.522754 [Byte1]: 53
7902 05:53:37.527063
7903 05:53:37.527150 Set Vref, RX VrefLevel [Byte0]: 54
7904 05:53:37.530360 [Byte1]: 54
7905 05:53:37.534592
7906 05:53:37.534676 Set Vref, RX VrefLevel [Byte0]: 55
7907 05:53:37.538144 [Byte1]: 55
7908 05:53:37.542519
7909 05:53:37.542629 Set Vref, RX VrefLevel [Byte0]: 56
7910 05:53:37.545559 [Byte1]: 56
7911 05:53:37.549760
7912 05:53:37.549871 Set Vref, RX VrefLevel [Byte0]: 57
7913 05:53:37.553111 [Byte1]: 57
7914 05:53:37.557461
7915 05:53:37.557547 Set Vref, RX VrefLevel [Byte0]: 58
7916 05:53:37.560740 [Byte1]: 58
7917 05:53:37.564886
7918 05:53:37.564971 Set Vref, RX VrefLevel [Byte0]: 59
7919 05:53:37.568576 [Byte1]: 59
7920 05:53:37.572728
7921 05:53:37.572812 Set Vref, RX VrefLevel [Byte0]: 60
7922 05:53:37.576114 [Byte1]: 60
7923 05:53:37.580242
7924 05:53:37.580326 Set Vref, RX VrefLevel [Byte0]: 61
7925 05:53:37.583251 [Byte1]: 61
7926 05:53:37.587578
7927 05:53:37.587662 Set Vref, RX VrefLevel [Byte0]: 62
7928 05:53:37.590859 [Byte1]: 62
7929 05:53:37.595052
7930 05:53:37.595163 Set Vref, RX VrefLevel [Byte0]: 63
7931 05:53:37.598575 [Byte1]: 63
7932 05:53:37.603167
7933 05:53:37.603251 Set Vref, RX VrefLevel [Byte0]: 64
7934 05:53:37.605922 [Byte1]: 64
7935 05:53:37.610229
7936 05:53:37.610313 Set Vref, RX VrefLevel [Byte0]: 65
7937 05:53:37.617043 [Byte1]: 65
7938 05:53:37.617128
7939 05:53:37.620270 Set Vref, RX VrefLevel [Byte0]: 66
7940 05:53:37.623666 [Byte1]: 66
7941 05:53:37.623750
7942 05:53:37.626624 Set Vref, RX VrefLevel [Byte0]: 67
7943 05:53:37.630058 [Byte1]: 67
7944 05:53:37.630142
7945 05:53:37.633368 Set Vref, RX VrefLevel [Byte0]: 68
7946 05:53:37.636642 [Byte1]: 68
7947 05:53:37.640511
7948 05:53:37.640595 Set Vref, RX VrefLevel [Byte0]: 69
7949 05:53:37.644081 [Byte1]: 69
7950 05:53:37.648404
7951 05:53:37.648503 Set Vref, RX VrefLevel [Byte0]: 70
7952 05:53:37.651655 [Byte1]: 70
7953 05:53:37.656022
7954 05:53:37.656106 Set Vref, RX VrefLevel [Byte0]: 71
7955 05:53:37.659329 [Byte1]: 71
7956 05:53:37.663531
7957 05:53:37.663615 Set Vref, RX VrefLevel [Byte0]: 72
7958 05:53:37.666987 [Byte1]: 72
7959 05:53:37.671081
7960 05:53:37.671164 Set Vref, RX VrefLevel [Byte0]: 73
7961 05:53:37.674403 [Byte1]: 73
7962 05:53:37.678858
7963 05:53:37.678942 Set Vref, RX VrefLevel [Byte0]: 74
7964 05:53:37.682033 [Byte1]: 74
7965 05:53:37.686083
7966 05:53:37.686167 Set Vref, RX VrefLevel [Byte0]: 75
7967 05:53:37.689188 [Byte1]: 75
7968 05:53:37.693512
7969 05:53:37.693596 Set Vref, RX VrefLevel [Byte0]: 76
7970 05:53:37.696989 [Byte1]: 76
7971 05:53:37.701212
7972 05:53:37.701296 Set Vref, RX VrefLevel [Byte0]: 77
7973 05:53:37.704539 [Byte1]: 77
7974 05:53:37.709075
7975 05:53:37.709159 Final RX Vref Byte 0 = 57 to rank0
7976 05:53:37.711938 Final RX Vref Byte 1 = 61 to rank0
7977 05:53:37.715317 Final RX Vref Byte 0 = 57 to rank1
7978 05:53:37.718630 Final RX Vref Byte 1 = 61 to rank1==
7979 05:53:37.722059 Dram Type= 6, Freq= 0, CH_0, rank 0
7980 05:53:37.728807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7981 05:53:37.728891 ==
7982 05:53:37.728957 DQS Delay:
7983 05:53:37.729018 DQS0 = 0, DQS1 = 0
7984 05:53:37.732353 DQM Delay:
7985 05:53:37.732436 DQM0 = 136, DQM1 = 124
7986 05:53:37.735596 DQ Delay:
7987 05:53:37.738854 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7988 05:53:37.742134 DQ4 =140, DQ5 =126, DQ6 =144, DQ7 =144
7989 05:53:37.745319 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
7990 05:53:37.748859 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
7991 05:53:37.748942
7992 05:53:37.749009
7993 05:53:37.749069
7994 05:53:37.752127 [DramC_TX_OE_Calibration] TA2
7995 05:53:37.755469 Original DQ_B0 (3 6) =30, OEN = 27
7996 05:53:37.758750 Original DQ_B1 (3 6) =30, OEN = 27
7997 05:53:37.762107 24, 0x0, End_B0=24 End_B1=24
7998 05:53:37.762196 25, 0x0, End_B0=25 End_B1=25
7999 05:53:37.765406 26, 0x0, End_B0=26 End_B1=26
8000 05:53:37.768685 27, 0x0, End_B0=27 End_B1=27
8001 05:53:37.771955 28, 0x0, End_B0=28 End_B1=28
8002 05:53:37.772040 29, 0x0, End_B0=29 End_B1=29
8003 05:53:37.775188 30, 0x0, End_B0=30 End_B1=30
8004 05:53:37.778912 31, 0x4141, End_B0=30 End_B1=30
8005 05:53:37.782086 Byte0 end_step=30 best_step=27
8006 05:53:37.784950 Byte1 end_step=30 best_step=27
8007 05:53:37.788690 Byte0 TX OE(2T, 0.5T) = (3, 3)
8008 05:53:37.791811 Byte1 TX OE(2T, 0.5T) = (3, 3)
8009 05:53:37.791895
8010 05:53:37.791961
8011 05:53:37.798374 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
8012 05:53:37.801671 CH0 RK0: MR19=303, MR18=1B19
8013 05:53:37.808512 CH0_RK0: MR19=0x303, MR18=0x1B19, DQSOSC=396, MR23=63, INC=23, DEC=15
8014 05:53:37.808597
8015 05:53:37.811660 ----->DramcWriteLeveling(PI) begin...
8016 05:53:37.811745 ==
8017 05:53:37.814856 Dram Type= 6, Freq= 0, CH_0, rank 1
8018 05:53:37.818599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8019 05:53:37.818684 ==
8020 05:53:37.821523 Write leveling (Byte 0): 38 => 38
8021 05:53:37.824921 Write leveling (Byte 1): 30 => 30
8022 05:53:37.828875 DramcWriteLeveling(PI) end<-----
8023 05:53:37.828958
8024 05:53:37.829024 ==
8025 05:53:37.831746 Dram Type= 6, Freq= 0, CH_0, rank 1
8026 05:53:37.834935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8027 05:53:37.835019 ==
8028 05:53:37.838077 [Gating] SW mode calibration
8029 05:53:37.845165 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8030 05:53:37.851690 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8031 05:53:37.855151 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 05:53:37.858483 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 05:53:37.864932 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 05:53:37.868543 1 4 12 | B1->B0 | 2323 2d2d | 1 0 | (1 1) (0 0)
8035 05:53:37.871496 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 05:53:37.877980 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 05:53:37.881228 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 05:53:37.884502 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8039 05:53:37.891781 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8040 05:53:37.894728 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 05:53:37.897852 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8042 05:53:37.904465 1 5 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (0 0)
8043 05:53:37.907814 1 5 16 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8044 05:53:37.911210 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 05:53:37.917631 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 05:53:37.920937 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 05:53:37.924402 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 05:53:37.931151 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 05:53:37.934634 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8050 05:53:37.937882 1 6 12 | B1->B0 | 2e2e 3f3e | 0 1 | (0 0) (0 0)
8051 05:53:37.944505 1 6 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8052 05:53:37.947839 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 05:53:37.951192 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 05:53:37.957521 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 05:53:37.961257 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 05:53:37.964336 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 05:53:37.970826 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 05:53:37.974110 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8059 05:53:37.977414 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8060 05:53:37.984295 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 05:53:37.987529 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 05:53:37.990786 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 05:53:37.997652 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 05:53:38.000815 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 05:53:38.004107 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 05:53:38.010818 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 05:53:38.014219 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 05:53:38.017113 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 05:53:38.020771 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 05:53:38.027136 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 05:53:38.030757 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 05:53:38.033853 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 05:53:38.040420 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 05:53:38.044026 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8075 05:53:38.047457 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8076 05:53:38.050702 Total UI for P1: 0, mck2ui 16
8077 05:53:38.053525 best dqsien dly found for B0: ( 1, 9, 12)
8078 05:53:38.060522 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 05:53:38.063603 Total UI for P1: 0, mck2ui 16
8080 05:53:38.066790 best dqsien dly found for B1: ( 1, 9, 14)
8081 05:53:38.070211 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8082 05:53:38.073545 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8083 05:53:38.073614
8084 05:53:38.076818 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8085 05:53:38.080101 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8086 05:53:38.083439 [Gating] SW calibration Done
8087 05:53:38.083508 ==
8088 05:53:38.087118 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 05:53:38.090337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 05:53:38.090424 ==
8091 05:53:38.093624 RX Vref Scan: 0
8092 05:53:38.093711
8093 05:53:38.097008 RX Vref 0 -> 0, step: 1
8094 05:53:38.097094
8095 05:53:38.097180 RX Delay 0 -> 252, step: 8
8096 05:53:38.103547 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8097 05:53:38.106836 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8098 05:53:38.110123 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8099 05:53:38.113470 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8100 05:53:38.116800 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8101 05:53:38.123300 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8102 05:53:38.126661 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8103 05:53:38.129918 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8104 05:53:38.133148 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8105 05:53:38.136740 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8106 05:53:38.143326 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8107 05:53:38.146474 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8108 05:53:38.149888 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8109 05:53:38.153242 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8110 05:53:38.156550 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8111 05:53:38.162992 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8112 05:53:38.163079 ==
8113 05:53:38.166672 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 05:53:38.169922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 05:53:38.170017 ==
8116 05:53:38.170108 DQS Delay:
8117 05:53:38.173205 DQS0 = 0, DQS1 = 0
8118 05:53:38.173291 DQM Delay:
8119 05:53:38.176573 DQM0 = 136, DQM1 = 126
8120 05:53:38.176687 DQ Delay:
8121 05:53:38.180085 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8122 05:53:38.182977 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8123 05:53:38.186213 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =123
8124 05:53:38.189811 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8125 05:53:38.189921
8126 05:53:38.192980
8127 05:53:38.193066 ==
8128 05:53:38.196163 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 05:53:38.199689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 05:53:38.199776 ==
8131 05:53:38.199861
8132 05:53:38.199942
8133 05:53:38.202828 TX Vref Scan disable
8134 05:53:38.202915 == TX Byte 0 ==
8135 05:53:38.209371 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8136 05:53:38.213082 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8137 05:53:38.213169 == TX Byte 1 ==
8138 05:53:38.219540 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8139 05:53:38.223087 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8140 05:53:38.223173 ==
8141 05:53:38.226419 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 05:53:38.229222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 05:53:38.229308 ==
8144 05:53:38.243743
8145 05:53:38.246986 TX Vref early break, caculate TX vref
8146 05:53:38.250719 TX Vref=16, minBit 0, minWin=23, winSum=387
8147 05:53:38.253971 TX Vref=18, minBit 3, minWin=24, winSum=397
8148 05:53:38.257284 TX Vref=20, minBit 8, minWin=24, winSum=407
8149 05:53:38.260488 TX Vref=22, minBit 8, minWin=24, winSum=414
8150 05:53:38.263650 TX Vref=24, minBit 0, minWin=25, winSum=423
8151 05:53:38.270830 TX Vref=26, minBit 0, minWin=26, winSum=430
8152 05:53:38.273935 TX Vref=28, minBit 2, minWin=26, winSum=433
8153 05:53:38.277289 TX Vref=30, minBit 0, minWin=25, winSum=426
8154 05:53:38.280661 TX Vref=32, minBit 4, minWin=25, winSum=421
8155 05:53:38.283896 TX Vref=34, minBit 4, minWin=24, winSum=409
8156 05:53:38.290542 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 28
8157 05:53:38.290629
8158 05:53:38.293658 Final TX Range 0 Vref 28
8159 05:53:38.293803
8160 05:53:38.293907 ==
8161 05:53:38.297175 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 05:53:38.300082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 05:53:38.300169 ==
8164 05:53:38.300274
8165 05:53:38.300376
8166 05:53:38.303638 TX Vref Scan disable
8167 05:53:38.310381 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8168 05:53:38.310468 == TX Byte 0 ==
8169 05:53:38.313571 u2DelayCellOfst[0]=16 cells (5 PI)
8170 05:53:38.316877 u2DelayCellOfst[1]=20 cells (6 PI)
8171 05:53:38.320187 u2DelayCellOfst[2]=13 cells (4 PI)
8172 05:53:38.323626 u2DelayCellOfst[3]=16 cells (5 PI)
8173 05:53:38.327163 u2DelayCellOfst[4]=10 cells (3 PI)
8174 05:53:38.330284 u2DelayCellOfst[5]=0 cells (0 PI)
8175 05:53:38.333555 u2DelayCellOfst[6]=20 cells (6 PI)
8176 05:53:38.336848 u2DelayCellOfst[7]=20 cells (6 PI)
8177 05:53:38.340180 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8178 05:53:38.343327 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8179 05:53:38.347098 == TX Byte 1 ==
8180 05:53:38.347185 u2DelayCellOfst[8]=0 cells (0 PI)
8181 05:53:38.350250 u2DelayCellOfst[9]=0 cells (0 PI)
8182 05:53:38.353453 u2DelayCellOfst[10]=6 cells (2 PI)
8183 05:53:38.356669 u2DelayCellOfst[11]=3 cells (1 PI)
8184 05:53:38.360317 u2DelayCellOfst[12]=13 cells (4 PI)
8185 05:53:38.363698 u2DelayCellOfst[13]=10 cells (3 PI)
8186 05:53:38.366693 u2DelayCellOfst[14]=16 cells (5 PI)
8187 05:53:38.369970 u2DelayCellOfst[15]=10 cells (3 PI)
8188 05:53:38.373287 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8189 05:53:38.379784 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8190 05:53:38.379867 DramC Write-DBI on
8191 05:53:38.379934 ==
8192 05:53:38.383274 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 05:53:38.386604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 05:53:38.389982 ==
8195 05:53:38.390065
8196 05:53:38.390130
8197 05:53:38.390192 TX Vref Scan disable
8198 05:53:38.393694 == TX Byte 0 ==
8199 05:53:38.396532 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8200 05:53:38.400117 == TX Byte 1 ==
8201 05:53:38.403120 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8202 05:53:38.406631 DramC Write-DBI off
8203 05:53:38.406714
8204 05:53:38.406808 [DATLAT]
8205 05:53:38.406884 Freq=1600, CH0 RK1
8206 05:53:38.406944
8207 05:53:38.410116 DATLAT Default: 0xf
8208 05:53:38.410200 0, 0xFFFF, sum = 0
8209 05:53:38.413419 1, 0xFFFF, sum = 0
8210 05:53:38.416632 2, 0xFFFF, sum = 0
8211 05:53:38.416716 3, 0xFFFF, sum = 0
8212 05:53:38.419940 4, 0xFFFF, sum = 0
8213 05:53:38.420025 5, 0xFFFF, sum = 0
8214 05:53:38.423246 6, 0xFFFF, sum = 0
8215 05:53:38.423331 7, 0xFFFF, sum = 0
8216 05:53:38.426721 8, 0xFFFF, sum = 0
8217 05:53:38.426835 9, 0xFFFF, sum = 0
8218 05:53:38.429650 10, 0xFFFF, sum = 0
8219 05:53:38.429735 11, 0xFFFF, sum = 0
8220 05:53:38.433000 12, 0xFFFF, sum = 0
8221 05:53:38.433084 13, 0xFFFF, sum = 0
8222 05:53:38.436252 14, 0x0, sum = 1
8223 05:53:38.436337 15, 0x0, sum = 2
8224 05:53:38.439556 16, 0x0, sum = 3
8225 05:53:38.439641 17, 0x0, sum = 4
8226 05:53:38.442944 best_step = 15
8227 05:53:38.443027
8228 05:53:38.443129 ==
8229 05:53:38.446114 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 05:53:38.449490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 05:53:38.449573 ==
8232 05:53:38.452809 RX Vref Scan: 0
8233 05:53:38.452895
8234 05:53:38.452962 RX Vref 0 -> 0, step: 1
8235 05:53:38.453026
8236 05:53:38.456116 RX Delay 19 -> 252, step: 4
8237 05:53:38.463044 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8238 05:53:38.466331 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8239 05:53:38.469210 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8240 05:53:38.472703 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8241 05:53:38.476142 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8242 05:53:38.479449 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8243 05:53:38.485927 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8244 05:53:38.489624 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8245 05:53:38.492620 iDelay=191, Bit 8, Center 114 (67 ~ 162) 96
8246 05:53:38.495904 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8247 05:53:38.499249 iDelay=191, Bit 10, Center 126 (79 ~ 174) 96
8248 05:53:38.505951 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8249 05:53:38.509292 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8250 05:53:38.512704 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8251 05:53:38.515964 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8252 05:53:38.519136 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8253 05:53:38.522512 ==
8254 05:53:38.525852 Dram Type= 6, Freq= 0, CH_0, rank 1
8255 05:53:38.529184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 05:53:38.529262 ==
8257 05:53:38.529326 DQS Delay:
8258 05:53:38.532453 DQS0 = 0, DQS1 = 0
8259 05:53:38.532551 DQM Delay:
8260 05:53:38.535821 DQM0 = 133, DQM1 = 123
8261 05:53:38.535895 DQ Delay:
8262 05:53:38.539133 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8263 05:53:38.542356 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8264 05:53:38.545595 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =120
8265 05:53:38.548877 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8266 05:53:38.548975
8267 05:53:38.549044
8268 05:53:38.549104
8269 05:53:38.552537 [DramC_TX_OE_Calibration] TA2
8270 05:53:38.555480 Original DQ_B0 (3 6) =30, OEN = 27
8271 05:53:38.558840 Original DQ_B1 (3 6) =30, OEN = 27
8272 05:53:38.562156 24, 0x0, End_B0=24 End_B1=24
8273 05:53:38.565382 25, 0x0, End_B0=25 End_B1=25
8274 05:53:38.565454 26, 0x0, End_B0=26 End_B1=26
8275 05:53:38.568759 27, 0x0, End_B0=27 End_B1=27
8276 05:53:38.572444 28, 0x0, End_B0=28 End_B1=28
8277 05:53:38.575385 29, 0x0, End_B0=29 End_B1=29
8278 05:53:38.578899 30, 0x0, End_B0=30 End_B1=30
8279 05:53:38.579006 31, 0x4141, End_B0=30 End_B1=30
8280 05:53:38.582357 Byte0 end_step=30 best_step=27
8281 05:53:38.585584 Byte1 end_step=30 best_step=27
8282 05:53:38.588844 Byte0 TX OE(2T, 0.5T) = (3, 3)
8283 05:53:38.592261 Byte1 TX OE(2T, 0.5T) = (3, 3)
8284 05:53:38.592364
8285 05:53:38.592466
8286 05:53:38.598891 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 395 ps
8287 05:53:38.602254 CH0 RK1: MR19=303, MR18=1C0A
8288 05:53:38.608855 CH0_RK1: MR19=0x303, MR18=0x1C0A, DQSOSC=395, MR23=63, INC=23, DEC=15
8289 05:53:38.612102 [RxdqsGatingPostProcess] freq 1600
8290 05:53:38.618845 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8291 05:53:38.618929 best DQS0 dly(2T, 0.5T) = (1, 1)
8292 05:53:38.621934 best DQS1 dly(2T, 0.5T) = (1, 1)
8293 05:53:38.625391 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8294 05:53:38.628473 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8295 05:53:38.632324 best DQS0 dly(2T, 0.5T) = (1, 1)
8296 05:53:38.635181 best DQS1 dly(2T, 0.5T) = (1, 1)
8297 05:53:38.638484 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8298 05:53:38.641833 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8299 05:53:38.645013 Pre-setting of DQS Precalculation
8300 05:53:38.648316 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8301 05:53:38.648403 ==
8302 05:53:38.651682 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 05:53:38.658561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 05:53:38.658649 ==
8305 05:53:38.661845 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8306 05:53:38.668103 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8307 05:53:38.671337 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8308 05:53:38.677793 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8309 05:53:38.686177 [CA 0] Center 41 (12~70) winsize 59
8310 05:53:38.689274 [CA 1] Center 41 (12~71) winsize 60
8311 05:53:38.692710 [CA 2] Center 37 (8~67) winsize 60
8312 05:53:38.695877 [CA 3] Center 36 (7~66) winsize 60
8313 05:53:38.699333 [CA 4] Center 37 (8~66) winsize 59
8314 05:53:38.702755 [CA 5] Center 36 (7~66) winsize 60
8315 05:53:38.702842
8316 05:53:38.706124 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8317 05:53:38.706213
8318 05:53:38.709543 [CATrainingPosCal] consider 1 rank data
8319 05:53:38.712706 u2DelayCellTimex100 = 290/100 ps
8320 05:53:38.715929 CA0 delay=41 (12~70),Diff = 5 PI (16 cell)
8321 05:53:38.722542 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8322 05:53:38.726175 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8323 05:53:38.729454 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8324 05:53:38.732724 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8325 05:53:38.735962 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8326 05:53:38.736049
8327 05:53:38.739214 CA PerBit enable=1, Macro0, CA PI delay=36
8328 05:53:38.739301
8329 05:53:38.742548 [CBTSetCACLKResult] CA Dly = 36
8330 05:53:38.745840 CS Dly: 8 (0~39)
8331 05:53:38.749262 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8332 05:53:38.752424 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8333 05:53:38.752511 ==
8334 05:53:38.755643 Dram Type= 6, Freq= 0, CH_1, rank 1
8335 05:53:38.758876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 05:53:38.762293 ==
8337 05:53:38.765571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 05:53:38.768891 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 05:53:38.775535 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 05:53:38.778927 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 05:53:38.788956 [CA 0] Center 42 (13~71) winsize 59
8342 05:53:38.792273 [CA 1] Center 41 (12~71) winsize 60
8343 05:53:38.795875 [CA 2] Center 38 (9~68) winsize 60
8344 05:53:38.799312 [CA 3] Center 37 (8~67) winsize 60
8345 05:53:38.802640 [CA 4] Center 37 (8~67) winsize 60
8346 05:53:38.805683 [CA 5] Center 37 (7~67) winsize 61
8347 05:53:38.805767
8348 05:53:38.808932 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8349 05:53:38.809015
8350 05:53:38.812613 [CATrainingPosCal] consider 2 rank data
8351 05:53:38.815645 u2DelayCellTimex100 = 290/100 ps
8352 05:53:38.819167 CA0 delay=41 (13~70),Diff = 5 PI (16 cell)
8353 05:53:38.825777 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8354 05:53:38.829039 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8355 05:53:38.832500 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8356 05:53:38.835420 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8357 05:53:38.838706 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8358 05:53:38.838789
8359 05:53:38.842502 CA PerBit enable=1, Macro0, CA PI delay=36
8360 05:53:38.842585
8361 05:53:38.845346 [CBTSetCACLKResult] CA Dly = 36
8362 05:53:38.848933 CS Dly: 9 (0~42)
8363 05:53:38.852058 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 05:53:38.855395 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 05:53:38.855478
8366 05:53:38.859177 ----->DramcWriteLeveling(PI) begin...
8367 05:53:38.859261 ==
8368 05:53:38.862423 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 05:53:38.865610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 05:53:38.868942 ==
8371 05:53:38.869024 Write leveling (Byte 0): 23 => 23
8372 05:53:38.871835 Write leveling (Byte 1): 29 => 29
8373 05:53:38.875723 DramcWriteLeveling(PI) end<-----
8374 05:53:38.875806
8375 05:53:38.875871 ==
8376 05:53:38.878875 Dram Type= 6, Freq= 0, CH_1, rank 0
8377 05:53:38.885545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 05:53:38.885628 ==
8379 05:53:38.885693 [Gating] SW mode calibration
8380 05:53:38.895389 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8381 05:53:38.898699 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8382 05:53:38.902171 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 05:53:38.908626 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 05:53:38.912078 1 4 8 | B1->B0 | 2525 3030 | 0 0 | (0 0) (0 0)
8385 05:53:38.915413 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8386 05:53:38.921921 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 05:53:38.925265 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 05:53:38.928449 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 05:53:38.935177 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 05:53:38.938395 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 05:53:38.941673 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8392 05:53:38.948443 1 5 8 | B1->B0 | 3333 2c2c | 0 0 | (0 0) (1 0)
8393 05:53:38.951772 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8394 05:53:38.954976 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8395 05:53:38.961585 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 05:53:38.964911 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 05:53:38.968053 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 05:53:38.975034 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 05:53:38.978444 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 05:53:38.981329 1 6 8 | B1->B0 | 2929 4545 | 0 0 | (1 1) (0 0)
8401 05:53:38.988372 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 05:53:38.991310 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 05:53:38.995014 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 05:53:39.001547 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 05:53:39.004848 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 05:53:39.008076 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 05:53:39.014754 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 05:53:39.017894 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8409 05:53:39.021277 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8410 05:53:39.027875 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 05:53:39.031129 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 05:53:39.034463 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 05:53:39.041346 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 05:53:39.044603 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 05:53:39.047936 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 05:53:39.054570 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 05:53:39.058137 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 05:53:39.061300 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 05:53:39.067514 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 05:53:39.070902 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 05:53:39.074387 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 05:53:39.081064 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 05:53:39.084420 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8424 05:53:39.087818 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8425 05:53:39.094337 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8426 05:53:39.094422 Total UI for P1: 0, mck2ui 16
8427 05:53:39.097592 best dqsien dly found for B0: ( 1, 9, 6)
8428 05:53:39.104051 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 05:53:39.107604 Total UI for P1: 0, mck2ui 16
8430 05:53:39.110821 best dqsien dly found for B1: ( 1, 9, 10)
8431 05:53:39.114174 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8432 05:53:39.117561 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8433 05:53:39.117646
8434 05:53:39.121217 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8435 05:53:39.124232 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8436 05:53:39.127247 [Gating] SW calibration Done
8437 05:53:39.127348 ==
8438 05:53:39.130869 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 05:53:39.133984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 05:53:39.134071 ==
8441 05:53:39.137398 RX Vref Scan: 0
8442 05:53:39.137498
8443 05:53:39.140771 RX Vref 0 -> 0, step: 1
8444 05:53:39.140863
8445 05:53:39.140929 RX Delay 0 -> 252, step: 8
8446 05:53:39.147076 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8447 05:53:39.150634 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8448 05:53:39.153893 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8449 05:53:39.157177 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8450 05:53:39.160415 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8451 05:53:39.163766 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8452 05:53:39.170320 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8453 05:53:39.173741 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8454 05:53:39.177166 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8455 05:53:39.180456 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8456 05:53:39.183790 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8457 05:53:39.190364 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8458 05:53:39.193742 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8459 05:53:39.197303 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8460 05:53:39.200444 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8461 05:53:39.203693 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8462 05:53:39.207029 ==
8463 05:53:39.210471 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 05:53:39.213592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 05:53:39.213737 ==
8466 05:53:39.213822 DQS Delay:
8467 05:53:39.217170 DQS0 = 0, DQS1 = 0
8468 05:53:39.217242 DQM Delay:
8469 05:53:39.220642 DQM0 = 138, DQM1 = 131
8470 05:53:39.220712 DQ Delay:
8471 05:53:39.223514 DQ0 =139, DQ1 =135, DQ2 =127, DQ3 =139
8472 05:53:39.227219 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8473 05:53:39.230433 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8474 05:53:39.233613 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
8475 05:53:39.233730
8476 05:53:39.233822
8477 05:53:39.233932 ==
8478 05:53:39.236998 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 05:53:39.243457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 05:53:39.243537 ==
8481 05:53:39.243632
8482 05:53:39.243724
8483 05:53:39.243815 TX Vref Scan disable
8484 05:53:39.247391 == TX Byte 0 ==
8485 05:53:39.250722 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8486 05:53:39.257345 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8487 05:53:39.257448 == TX Byte 1 ==
8488 05:53:39.260564 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8489 05:53:39.267121 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8490 05:53:39.267195 ==
8491 05:53:39.270480 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 05:53:39.273804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 05:53:39.273903 ==
8494 05:53:39.286261
8495 05:53:39.289567 TX Vref early break, caculate TX vref
8496 05:53:39.293027 TX Vref=16, minBit 15, minWin=20, winSum=367
8497 05:53:39.296332 TX Vref=18, minBit 15, minWin=21, winSum=379
8498 05:53:39.299516 TX Vref=20, minBit 13, minWin=23, winSum=390
8499 05:53:39.303098 TX Vref=22, minBit 15, minWin=23, winSum=402
8500 05:53:39.309564 TX Vref=24, minBit 15, minWin=23, winSum=407
8501 05:53:39.312984 TX Vref=26, minBit 10, minWin=25, winSum=418
8502 05:53:39.315968 TX Vref=28, minBit 10, minWin=25, winSum=427
8503 05:53:39.319551 TX Vref=30, minBit 10, minWin=25, winSum=418
8504 05:53:39.323131 TX Vref=32, minBit 10, minWin=24, winSum=409
8505 05:53:39.326307 TX Vref=34, minBit 6, minWin=24, winSum=400
8506 05:53:39.332883 [TxChooseVref] Worse bit 10, Min win 25, Win sum 427, Final Vref 28
8507 05:53:39.332966
8508 05:53:39.335981 Final TX Range 0 Vref 28
8509 05:53:39.336069
8510 05:53:39.336171 ==
8511 05:53:39.339733 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 05:53:39.342880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 05:53:39.342964 ==
8514 05:53:39.343030
8515 05:53:39.346092
8516 05:53:39.346208 TX Vref Scan disable
8517 05:53:39.353255 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8518 05:53:39.353356 == TX Byte 0 ==
8519 05:53:39.356011 u2DelayCellOfst[0]=16 cells (5 PI)
8520 05:53:39.359517 u2DelayCellOfst[1]=6 cells (2 PI)
8521 05:53:39.363027 u2DelayCellOfst[2]=0 cells (0 PI)
8522 05:53:39.366064 u2DelayCellOfst[3]=3 cells (1 PI)
8523 05:53:39.369438 u2DelayCellOfst[4]=6 cells (2 PI)
8524 05:53:39.372502 u2DelayCellOfst[5]=16 cells (5 PI)
8525 05:53:39.375958 u2DelayCellOfst[6]=16 cells (5 PI)
8526 05:53:39.379225 u2DelayCellOfst[7]=3 cells (1 PI)
8527 05:53:39.382500 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8528 05:53:39.385786 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8529 05:53:39.389165 == TX Byte 1 ==
8530 05:53:39.392638 u2DelayCellOfst[8]=0 cells (0 PI)
8531 05:53:39.392758 u2DelayCellOfst[9]=0 cells (0 PI)
8532 05:53:39.395869 u2DelayCellOfst[10]=10 cells (3 PI)
8533 05:53:39.399188 u2DelayCellOfst[11]=3 cells (1 PI)
8534 05:53:39.402565 u2DelayCellOfst[12]=13 cells (4 PI)
8535 05:53:39.405734 u2DelayCellOfst[13]=16 cells (5 PI)
8536 05:53:39.409275 u2DelayCellOfst[14]=16 cells (5 PI)
8537 05:53:39.412698 u2DelayCellOfst[15]=13 cells (4 PI)
8538 05:53:39.419052 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8539 05:53:39.422314 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8540 05:53:39.422428 DramC Write-DBI on
8541 05:53:39.422495 ==
8542 05:53:39.425611 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 05:53:39.432614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 05:53:39.432715 ==
8545 05:53:39.432781
8546 05:53:39.432859
8547 05:53:39.432948 TX Vref Scan disable
8548 05:53:39.436276 == TX Byte 0 ==
8549 05:53:39.439823 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8550 05:53:39.443182 == TX Byte 1 ==
8551 05:53:39.446162 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8552 05:53:39.449610 DramC Write-DBI off
8553 05:53:39.449693
8554 05:53:39.449789 [DATLAT]
8555 05:53:39.449852 Freq=1600, CH1 RK0
8556 05:53:39.449912
8557 05:53:39.453052 DATLAT Default: 0xf
8558 05:53:39.453165 0, 0xFFFF, sum = 0
8559 05:53:39.456334 1, 0xFFFF, sum = 0
8560 05:53:39.456435 2, 0xFFFF, sum = 0
8561 05:53:39.459529 3, 0xFFFF, sum = 0
8562 05:53:39.462980 4, 0xFFFF, sum = 0
8563 05:53:39.463095 5, 0xFFFF, sum = 0
8564 05:53:39.466131 6, 0xFFFF, sum = 0
8565 05:53:39.466256 7, 0xFFFF, sum = 0
8566 05:53:39.469596 8, 0xFFFF, sum = 0
8567 05:53:39.469702 9, 0xFFFF, sum = 0
8568 05:53:39.473221 10, 0xFFFF, sum = 0
8569 05:53:39.473330 11, 0xFFFF, sum = 0
8570 05:53:39.476082 12, 0xFFFF, sum = 0
8571 05:53:39.476198 13, 0xFFFF, sum = 0
8572 05:53:39.479547 14, 0x0, sum = 1
8573 05:53:39.479668 15, 0x0, sum = 2
8574 05:53:39.482729 16, 0x0, sum = 3
8575 05:53:39.482816 17, 0x0, sum = 4
8576 05:53:39.486094 best_step = 15
8577 05:53:39.486190
8578 05:53:39.486287 ==
8579 05:53:39.489671 Dram Type= 6, Freq= 0, CH_1, rank 0
8580 05:53:39.492650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8581 05:53:39.492760 ==
8582 05:53:39.495900 RX Vref Scan: 1
8583 05:53:39.496012
8584 05:53:39.496105 Set Vref Range= 24 -> 127
8585 05:53:39.496199
8586 05:53:39.499306 RX Vref 24 -> 127, step: 1
8587 05:53:39.499405
8588 05:53:39.502566 RX Delay 19 -> 252, step: 4
8589 05:53:39.502669
8590 05:53:39.505905 Set Vref, RX VrefLevel [Byte0]: 24
8591 05:53:39.509305 [Byte1]: 24
8592 05:53:39.509422
8593 05:53:39.512629 Set Vref, RX VrefLevel [Byte0]: 25
8594 05:53:39.516038 [Byte1]: 25
8595 05:53:39.516169
8596 05:53:39.519210 Set Vref, RX VrefLevel [Byte0]: 26
8597 05:53:39.522466 [Byte1]: 26
8598 05:53:39.526686
8599 05:53:39.526770 Set Vref, RX VrefLevel [Byte0]: 27
8600 05:53:39.530024 [Byte1]: 27
8601 05:53:39.534289
8602 05:53:39.534374 Set Vref, RX VrefLevel [Byte0]: 28
8603 05:53:39.537377 [Byte1]: 28
8604 05:53:39.542040
8605 05:53:39.542139 Set Vref, RX VrefLevel [Byte0]: 29
8606 05:53:39.545656 [Byte1]: 29
8607 05:53:39.549307
8608 05:53:39.549411 Set Vref, RX VrefLevel [Byte0]: 30
8609 05:53:39.552676 [Byte1]: 30
8610 05:53:39.557124
8611 05:53:39.557233 Set Vref, RX VrefLevel [Byte0]: 31
8612 05:53:39.560087 [Byte1]: 31
8613 05:53:39.564604
8614 05:53:39.564718 Set Vref, RX VrefLevel [Byte0]: 32
8615 05:53:39.567606 [Byte1]: 32
8616 05:53:39.572041
8617 05:53:39.572149 Set Vref, RX VrefLevel [Byte0]: 33
8618 05:53:39.575382 [Byte1]: 33
8619 05:53:39.579426
8620 05:53:39.579511 Set Vref, RX VrefLevel [Byte0]: 34
8621 05:53:39.582786 [Byte1]: 34
8622 05:53:39.587109
8623 05:53:39.587189 Set Vref, RX VrefLevel [Byte0]: 35
8624 05:53:39.590391 [Byte1]: 35
8625 05:53:39.595028
8626 05:53:39.595111 Set Vref, RX VrefLevel [Byte0]: 36
8627 05:53:39.598010 [Byte1]: 36
8628 05:53:39.602243
8629 05:53:39.602332 Set Vref, RX VrefLevel [Byte0]: 37
8630 05:53:39.605656 [Byte1]: 37
8631 05:53:39.609774
8632 05:53:39.609884 Set Vref, RX VrefLevel [Byte0]: 38
8633 05:53:39.613485 [Byte1]: 38
8634 05:53:39.617390
8635 05:53:39.617461 Set Vref, RX VrefLevel [Byte0]: 39
8636 05:53:39.620833 [Byte1]: 39
8637 05:53:39.625022
8638 05:53:39.625095 Set Vref, RX VrefLevel [Byte0]: 40
8639 05:53:39.628343 [Byte1]: 40
8640 05:53:39.632554
8641 05:53:39.632630 Set Vref, RX VrefLevel [Byte0]: 41
8642 05:53:39.635918 [Byte1]: 41
8643 05:53:39.640046
8644 05:53:39.640121 Set Vref, RX VrefLevel [Byte0]: 42
8645 05:53:39.643662 [Byte1]: 42
8646 05:53:39.647887
8647 05:53:39.647975 Set Vref, RX VrefLevel [Byte0]: 43
8648 05:53:39.651385 [Byte1]: 43
8649 05:53:39.655386
8650 05:53:39.655468 Set Vref, RX VrefLevel [Byte0]: 44
8651 05:53:39.658775 [Byte1]: 44
8652 05:53:39.663229
8653 05:53:39.663304 Set Vref, RX VrefLevel [Byte0]: 45
8654 05:53:39.666368 [Byte1]: 45
8655 05:53:39.670333
8656 05:53:39.670409 Set Vref, RX VrefLevel [Byte0]: 46
8657 05:53:39.673554 [Byte1]: 46
8658 05:53:39.678080
8659 05:53:39.678155 Set Vref, RX VrefLevel [Byte0]: 47
8660 05:53:39.681415 [Byte1]: 47
8661 05:53:39.685403
8662 05:53:39.685485 Set Vref, RX VrefLevel [Byte0]: 48
8663 05:53:39.688920 [Byte1]: 48
8664 05:53:39.693036
8665 05:53:39.696395 Set Vref, RX VrefLevel [Byte0]: 49
8666 05:53:39.699729 [Byte1]: 49
8667 05:53:39.699805
8668 05:53:39.703044 Set Vref, RX VrefLevel [Byte0]: 50
8669 05:53:39.706370 [Byte1]: 50
8670 05:53:39.706447
8671 05:53:39.709661 Set Vref, RX VrefLevel [Byte0]: 51
8672 05:53:39.713005 [Byte1]: 51
8673 05:53:39.713081
8674 05:53:39.716301 Set Vref, RX VrefLevel [Byte0]: 52
8675 05:53:39.719562 [Byte1]: 52
8676 05:53:39.723520
8677 05:53:39.723597 Set Vref, RX VrefLevel [Byte0]: 53
8678 05:53:39.727087 [Byte1]: 53
8679 05:53:39.731007
8680 05:53:39.731089 Set Vref, RX VrefLevel [Byte0]: 54
8681 05:53:39.734483 [Byte1]: 54
8682 05:53:39.739194
8683 05:53:39.739268 Set Vref, RX VrefLevel [Byte0]: 55
8684 05:53:39.741880 [Byte1]: 55
8685 05:53:39.746601
8686 05:53:39.746680 Set Vref, RX VrefLevel [Byte0]: 56
8687 05:53:39.749479 [Byte1]: 56
8688 05:53:39.753846
8689 05:53:39.753927 Set Vref, RX VrefLevel [Byte0]: 57
8690 05:53:39.757104 [Byte1]: 57
8691 05:53:39.761284
8692 05:53:39.761376 Set Vref, RX VrefLevel [Byte0]: 58
8693 05:53:39.764673 [Byte1]: 58
8694 05:53:39.769095
8695 05:53:39.769233 Set Vref, RX VrefLevel [Byte0]: 59
8696 05:53:39.772059 [Byte1]: 59
8697 05:53:39.776520
8698 05:53:39.776628 Set Vref, RX VrefLevel [Byte0]: 60
8699 05:53:39.779949 [Byte1]: 60
8700 05:53:39.784241
8701 05:53:39.784352 Set Vref, RX VrefLevel [Byte0]: 61
8702 05:53:39.787636 [Byte1]: 61
8703 05:53:39.791710
8704 05:53:39.791781 Set Vref, RX VrefLevel [Byte0]: 62
8705 05:53:39.795099 [Byte1]: 62
8706 05:53:39.799272
8707 05:53:39.799347 Set Vref, RX VrefLevel [Byte0]: 63
8708 05:53:39.802481 [Byte1]: 63
8709 05:53:39.806576
8710 05:53:39.806660 Set Vref, RX VrefLevel [Byte0]: 64
8711 05:53:39.809901 [Byte1]: 64
8712 05:53:39.814673
8713 05:53:39.814755 Set Vref, RX VrefLevel [Byte0]: 65
8714 05:53:39.817493 [Byte1]: 65
8715 05:53:39.822224
8716 05:53:39.822306 Set Vref, RX VrefLevel [Byte0]: 66
8717 05:53:39.828456 [Byte1]: 66
8718 05:53:39.828543
8719 05:53:39.831669 Set Vref, RX VrefLevel [Byte0]: 67
8720 05:53:39.835107 [Byte1]: 67
8721 05:53:39.835193
8722 05:53:39.838373 Set Vref, RX VrefLevel [Byte0]: 68
8723 05:53:39.841624 [Byte1]: 68
8724 05:53:39.841710
8725 05:53:39.845205 Set Vref, RX VrefLevel [Byte0]: 69
8726 05:53:39.848135 [Byte1]: 69
8727 05:53:39.852411
8728 05:53:39.852495 Set Vref, RX VrefLevel [Byte0]: 70
8729 05:53:39.855656 [Byte1]: 70
8730 05:53:39.859930
8731 05:53:39.860030 Set Vref, RX VrefLevel [Byte0]: 71
8732 05:53:39.863270 [Byte1]: 71
8733 05:53:39.867567
8734 05:53:39.867653 Set Vref, RX VrefLevel [Byte0]: 72
8735 05:53:39.870781 [Byte1]: 72
8736 05:53:39.874814
8737 05:53:39.874899 Final RX Vref Byte 0 = 52 to rank0
8738 05:53:39.878255 Final RX Vref Byte 1 = 64 to rank0
8739 05:53:39.881541 Final RX Vref Byte 0 = 52 to rank1
8740 05:53:39.885253 Final RX Vref Byte 1 = 64 to rank1==
8741 05:53:39.888423 Dram Type= 6, Freq= 0, CH_1, rank 0
8742 05:53:39.894967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 05:53:39.895055 ==
8744 05:53:39.895123 DQS Delay:
8745 05:53:39.895187 DQS0 = 0, DQS1 = 0
8746 05:53:39.898265 DQM Delay:
8747 05:53:39.898351 DQM0 = 133, DQM1 = 128
8748 05:53:39.901562 DQ Delay:
8749 05:53:39.904777 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8750 05:53:39.908540 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8751 05:53:39.911431 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
8752 05:53:39.914776 DQ12 =140, DQ13 =134, DQ14 =134, DQ15 =134
8753 05:53:39.914883
8754 05:53:39.914980
8755 05:53:39.915073
8756 05:53:39.918241 [DramC_TX_OE_Calibration] TA2
8757 05:53:39.921738 Original DQ_B0 (3 6) =30, OEN = 27
8758 05:53:39.925034 Original DQ_B1 (3 6) =30, OEN = 27
8759 05:53:39.928422 24, 0x0, End_B0=24 End_B1=24
8760 05:53:39.928503 25, 0x0, End_B0=25 End_B1=25
8761 05:53:39.931748 26, 0x0, End_B0=26 End_B1=26
8762 05:53:39.935037 27, 0x0, End_B0=27 End_B1=27
8763 05:53:39.938339 28, 0x0, End_B0=28 End_B1=28
8764 05:53:39.938435 29, 0x0, End_B0=29 End_B1=29
8765 05:53:39.941551 30, 0x0, End_B0=30 End_B1=30
8766 05:53:39.944910 31, 0x4141, End_B0=30 End_B1=30
8767 05:53:39.948230 Byte0 end_step=30 best_step=27
8768 05:53:39.951636 Byte1 end_step=30 best_step=27
8769 05:53:39.955032 Byte0 TX OE(2T, 0.5T) = (3, 3)
8770 05:53:39.955109 Byte1 TX OE(2T, 0.5T) = (3, 3)
8771 05:53:39.955175
8772 05:53:39.958182
8773 05:53:39.964914 [DQSOSCAuto] RK0, (LSB)MR18= 0x1422, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8774 05:53:39.968285 CH1 RK0: MR19=303, MR18=1422
8775 05:53:39.975056 CH1_RK0: MR19=0x303, MR18=0x1422, DQSOSC=392, MR23=63, INC=24, DEC=16
8776 05:53:39.975161
8777 05:53:39.978188 ----->DramcWriteLeveling(PI) begin...
8778 05:53:39.978267 ==
8779 05:53:39.981683 Dram Type= 6, Freq= 0, CH_1, rank 1
8780 05:53:39.984820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8781 05:53:39.984897 ==
8782 05:53:39.988072 Write leveling (Byte 0): 24 => 24
8783 05:53:39.991546 Write leveling (Byte 1): 28 => 28
8784 05:53:39.994842 DramcWriteLeveling(PI) end<-----
8785 05:53:39.994922
8786 05:53:39.995016 ==
8787 05:53:39.998397 Dram Type= 6, Freq= 0, CH_1, rank 1
8788 05:53:40.001372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8789 05:53:40.001452 ==
8790 05:53:40.004678 [Gating] SW mode calibration
8791 05:53:40.011670 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8792 05:53:40.017971 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8793 05:53:40.021675 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 05:53:40.024527 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 05:53:40.031118 1 4 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8796 05:53:40.034485 1 4 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8797 05:53:40.037798 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8798 05:53:40.044464 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 05:53:40.048091 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 05:53:40.051213 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 05:53:40.057932 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 05:53:40.061446 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 05:53:40.064723 1 5 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 0)
8804 05:53:40.071255 1 5 12 | B1->B0 | 2323 3333 | 0 1 | (1 0) (1 0)
8805 05:53:40.074552 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8806 05:53:40.078198 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 05:53:40.084873 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 05:53:40.087671 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 05:53:40.091170 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 05:53:40.097933 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 05:53:40.101076 1 6 8 | B1->B0 | 3b3b 2424 | 0 0 | (1 1) (0 0)
8812 05:53:40.104346 1 6 12 | B1->B0 | 4646 3434 | 0 0 | (0 0) (0 0)
8813 05:53:40.110847 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 05:53:40.114267 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 05:53:40.117609 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 05:53:40.120815 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 05:53:40.127426 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 05:53:40.130639 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 05:53:40.134050 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8820 05:53:40.140655 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8821 05:53:40.144057 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 05:53:40.147365 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 05:53:40.154209 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 05:53:40.157544 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 05:53:40.160837 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 05:53:40.167222 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 05:53:40.171026 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 05:53:40.174379 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 05:53:40.180617 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 05:53:40.184609 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 05:53:40.187530 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 05:53:40.194438 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 05:53:40.197208 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 05:53:40.200488 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8835 05:53:40.207460 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8836 05:53:40.210717 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8837 05:53:40.213803 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 05:53:40.217389 Total UI for P1: 0, mck2ui 16
8839 05:53:40.220630 best dqsien dly found for B0: ( 1, 9, 8)
8840 05:53:40.224033 Total UI for P1: 0, mck2ui 16
8841 05:53:40.227485 best dqsien dly found for B1: ( 1, 9, 12)
8842 05:53:40.230870 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8843 05:53:40.234296 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8844 05:53:40.234373
8845 05:53:40.237595 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8846 05:53:40.243998 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8847 05:53:40.244101 [Gating] SW calibration Done
8848 05:53:40.244193 ==
8849 05:53:40.247207 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 05:53:40.253750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 05:53:40.253856 ==
8852 05:53:40.253959 RX Vref Scan: 0
8853 05:53:40.254050
8854 05:53:40.257306 RX Vref 0 -> 0, step: 1
8855 05:53:40.257378
8856 05:53:40.260588 RX Delay 0 -> 252, step: 8
8857 05:53:40.263958 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8858 05:53:40.267190 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8859 05:53:40.270465 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8860 05:53:40.274060 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8861 05:53:40.280652 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8862 05:53:40.284283 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8863 05:53:40.286847 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8864 05:53:40.290132 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8865 05:53:40.293417 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8866 05:53:40.300073 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8867 05:53:40.303602 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8868 05:53:40.307119 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8869 05:53:40.310217 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8870 05:53:40.313337 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8871 05:53:40.320283 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8872 05:53:40.323493 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8873 05:53:40.323582 ==
8874 05:53:40.326911 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 05:53:40.330045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 05:53:40.330168 ==
8877 05:53:40.333303 DQS Delay:
8878 05:53:40.333404 DQS0 = 0, DQS1 = 0
8879 05:53:40.336996 DQM Delay:
8880 05:53:40.337078 DQM0 = 138, DQM1 = 130
8881 05:53:40.337145 DQ Delay:
8882 05:53:40.339996 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8883 05:53:40.343359 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =139
8884 05:53:40.349902 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8885 05:53:40.353256 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8886 05:53:40.353337
8887 05:53:40.353402
8888 05:53:40.353463 ==
8889 05:53:40.356570 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 05:53:40.359834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 05:53:40.359910 ==
8892 05:53:40.359997
8893 05:53:40.360058
8894 05:53:40.363576 TX Vref Scan disable
8895 05:53:40.366467 == TX Byte 0 ==
8896 05:53:40.369810 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8897 05:53:40.372917 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8898 05:53:40.376247 == TX Byte 1 ==
8899 05:53:40.379731 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8900 05:53:40.382846 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8901 05:53:40.382925 ==
8902 05:53:40.386142 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 05:53:40.389548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 05:53:40.392951 ==
8905 05:53:40.404361
8906 05:53:40.407385 TX Vref early break, caculate TX vref
8907 05:53:40.410660 TX Vref=16, minBit 9, minWin=23, winSum=384
8908 05:53:40.414310 TX Vref=18, minBit 9, minWin=23, winSum=395
8909 05:53:40.417477 TX Vref=20, minBit 13, minWin=23, winSum=406
8910 05:53:40.420959 TX Vref=22, minBit 9, minWin=24, winSum=410
8911 05:53:40.424128 TX Vref=24, minBit 9, minWin=25, winSum=424
8912 05:53:40.430601 TX Vref=26, minBit 13, minWin=25, winSum=430
8913 05:53:40.434102 TX Vref=28, minBit 10, minWin=25, winSum=429
8914 05:53:40.437489 TX Vref=30, minBit 9, minWin=25, winSum=422
8915 05:53:40.440526 TX Vref=32, minBit 10, minWin=24, winSum=414
8916 05:53:40.444145 TX Vref=34, minBit 10, minWin=24, winSum=404
8917 05:53:40.450661 [TxChooseVref] Worse bit 13, Min win 25, Win sum 430, Final Vref 26
8918 05:53:40.450747
8919 05:53:40.454080 Final TX Range 0 Vref 26
8920 05:53:40.454165
8921 05:53:40.454233 ==
8922 05:53:40.457195 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 05:53:40.460526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 05:53:40.460613 ==
8925 05:53:40.460709
8926 05:53:40.460839
8927 05:53:40.464185 TX Vref Scan disable
8928 05:53:40.470476 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8929 05:53:40.470563 == TX Byte 0 ==
8930 05:53:40.474175 u2DelayCellOfst[0]=13 cells (4 PI)
8931 05:53:40.477298 u2DelayCellOfst[1]=10 cells (3 PI)
8932 05:53:40.480591 u2DelayCellOfst[2]=0 cells (0 PI)
8933 05:53:40.483961 u2DelayCellOfst[3]=3 cells (1 PI)
8934 05:53:40.487300 u2DelayCellOfst[4]=6 cells (2 PI)
8935 05:53:40.490481 u2DelayCellOfst[5]=16 cells (5 PI)
8936 05:53:40.493796 u2DelayCellOfst[6]=16 cells (5 PI)
8937 05:53:40.497198 u2DelayCellOfst[7]=3 cells (1 PI)
8938 05:53:40.500526 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8939 05:53:40.503975 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8940 05:53:40.507247 == TX Byte 1 ==
8941 05:53:40.510464 u2DelayCellOfst[8]=0 cells (0 PI)
8942 05:53:40.510548 u2DelayCellOfst[9]=3 cells (1 PI)
8943 05:53:40.513602 u2DelayCellOfst[10]=10 cells (3 PI)
8944 05:53:40.517003 u2DelayCellOfst[11]=3 cells (1 PI)
8945 05:53:40.520314 u2DelayCellOfst[12]=13 cells (4 PI)
8946 05:53:40.523708 u2DelayCellOfst[13]=10 cells (3 PI)
8947 05:53:40.527121 u2DelayCellOfst[14]=16 cells (5 PI)
8948 05:53:40.530325 u2DelayCellOfst[15]=13 cells (4 PI)
8949 05:53:40.533994 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8950 05:53:40.540519 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8951 05:53:40.540603 DramC Write-DBI on
8952 05:53:40.540670 ==
8953 05:53:40.543774 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 05:53:40.547166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 05:53:40.550193 ==
8956 05:53:40.550277
8957 05:53:40.550342
8958 05:53:40.550404 TX Vref Scan disable
8959 05:53:40.554061 == TX Byte 0 ==
8960 05:53:40.557357 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8961 05:53:40.560636 == TX Byte 1 ==
8962 05:53:40.563829 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8963 05:53:40.563912 DramC Write-DBI off
8964 05:53:40.567097
8965 05:53:40.567180 [DATLAT]
8966 05:53:40.567246 Freq=1600, CH1 RK1
8967 05:53:40.567307
8968 05:53:40.570520 DATLAT Default: 0xf
8969 05:53:40.570602 0, 0xFFFF, sum = 0
8970 05:53:40.573795 1, 0xFFFF, sum = 0
8971 05:53:40.573879 2, 0xFFFF, sum = 0
8972 05:53:40.577095 3, 0xFFFF, sum = 0
8973 05:53:40.580629 4, 0xFFFF, sum = 0
8974 05:53:40.580714 5, 0xFFFF, sum = 0
8975 05:53:40.583935 6, 0xFFFF, sum = 0
8976 05:53:40.584020 7, 0xFFFF, sum = 0
8977 05:53:40.587185 8, 0xFFFF, sum = 0
8978 05:53:40.587270 9, 0xFFFF, sum = 0
8979 05:53:40.590551 10, 0xFFFF, sum = 0
8980 05:53:40.590635 11, 0xFFFF, sum = 0
8981 05:53:40.593889 12, 0xFFFF, sum = 0
8982 05:53:40.594024 13, 0xFFFF, sum = 0
8983 05:53:40.597273 14, 0x0, sum = 1
8984 05:53:40.597357 15, 0x0, sum = 2
8985 05:53:40.600496 16, 0x0, sum = 3
8986 05:53:40.600581 17, 0x0, sum = 4
8987 05:53:40.603807 best_step = 15
8988 05:53:40.603890
8989 05:53:40.603955 ==
8990 05:53:40.607183 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 05:53:40.610192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 05:53:40.610276 ==
8993 05:53:40.613439 RX Vref Scan: 0
8994 05:53:40.613554
8995 05:53:40.613621 RX Vref 0 -> 0, step: 1
8996 05:53:40.613681
8997 05:53:40.617247 RX Delay 19 -> 252, step: 4
8998 05:53:40.620038 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8999 05:53:40.626668 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
9000 05:53:40.630247 iDelay=195, Bit 2, Center 120 (75 ~ 166) 92
9001 05:53:40.633535 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9002 05:53:40.636765 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9003 05:53:40.640289 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9004 05:53:40.643135 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9005 05:53:40.649879 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
9006 05:53:40.653406 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9007 05:53:40.656814 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9008 05:53:40.659815 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9009 05:53:40.666349 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9010 05:53:40.669727 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9011 05:53:40.672970 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9012 05:53:40.676385 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9013 05:53:40.679601 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9014 05:53:40.682870 ==
9015 05:53:40.682953 Dram Type= 6, Freq= 0, CH_1, rank 1
9016 05:53:40.689778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9017 05:53:40.689862 ==
9018 05:53:40.689929 DQS Delay:
9019 05:53:40.693079 DQS0 = 0, DQS1 = 0
9020 05:53:40.693162 DQM Delay:
9021 05:53:40.696358 DQM0 = 134, DQM1 = 129
9022 05:53:40.696442 DQ Delay:
9023 05:53:40.699864 DQ0 =138, DQ1 =132, DQ2 =120, DQ3 =130
9024 05:53:40.703014 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =132
9025 05:53:40.706303 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9026 05:53:40.709632 DQ12 =138, DQ13 =136, DQ14 =136, DQ15 =138
9027 05:53:40.709716
9028 05:53:40.709782
9029 05:53:40.709843
9030 05:53:40.712552 [DramC_TX_OE_Calibration] TA2
9031 05:53:40.715816 Original DQ_B0 (3 6) =30, OEN = 27
9032 05:53:40.719574 Original DQ_B1 (3 6) =30, OEN = 27
9033 05:53:40.722781 24, 0x0, End_B0=24 End_B1=24
9034 05:53:40.726168 25, 0x0, End_B0=25 End_B1=25
9035 05:53:40.726252 26, 0x0, End_B0=26 End_B1=26
9036 05:53:40.729125 27, 0x0, End_B0=27 End_B1=27
9037 05:53:40.732518 28, 0x0, End_B0=28 End_B1=28
9038 05:53:40.736252 29, 0x0, End_B0=29 End_B1=29
9039 05:53:40.739365 30, 0x0, End_B0=30 End_B1=30
9040 05:53:40.739449 31, 0x5151, End_B0=30 End_B1=30
9041 05:53:40.742400 Byte0 end_step=30 best_step=27
9042 05:53:40.746128 Byte1 end_step=30 best_step=27
9043 05:53:40.749056 Byte0 TX OE(2T, 0.5T) = (3, 3)
9044 05:53:40.752326 Byte1 TX OE(2T, 0.5T) = (3, 3)
9045 05:53:40.752409
9046 05:53:40.752475
9047 05:53:40.759095 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9048 05:53:40.762258 CH1 RK1: MR19=303, MR18=1B06
9049 05:53:40.768885 CH1_RK1: MR19=0x303, MR18=0x1B06, DQSOSC=396, MR23=63, INC=23, DEC=15
9050 05:53:40.772164 [RxdqsGatingPostProcess] freq 1600
9051 05:53:40.779088 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9052 05:53:40.779172 best DQS0 dly(2T, 0.5T) = (1, 1)
9053 05:53:40.782224 best DQS1 dly(2T, 0.5T) = (1, 1)
9054 05:53:40.785605 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9055 05:53:40.788858 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9056 05:53:40.792152 best DQS0 dly(2T, 0.5T) = (1, 1)
9057 05:53:40.795426 best DQS1 dly(2T, 0.5T) = (1, 1)
9058 05:53:40.798682 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9059 05:53:40.802117 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9060 05:53:40.805180 Pre-setting of DQS Precalculation
9061 05:53:40.808553 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9062 05:53:40.818480 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9063 05:53:40.824997 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9064 05:53:40.825096
9065 05:53:40.825189
9066 05:53:40.828246 [Calibration Summary] 3200 Mbps
9067 05:53:40.828342 CH 0, Rank 0
9068 05:53:40.831666 SW Impedance : PASS
9069 05:53:40.831735 DUTY Scan : NO K
9070 05:53:40.835088 ZQ Calibration : PASS
9071 05:53:40.838290 Jitter Meter : NO K
9072 05:53:40.838385 CBT Training : PASS
9073 05:53:40.841424 Write leveling : PASS
9074 05:53:40.844740 RX DQS gating : PASS
9075 05:53:40.844834 RX DQ/DQS(RDDQC) : PASS
9076 05:53:40.847931 TX DQ/DQS : PASS
9077 05:53:40.851169 RX DATLAT : PASS
9078 05:53:40.851241 RX DQ/DQS(Engine): PASS
9079 05:53:40.854360 TX OE : PASS
9080 05:53:40.854444 All Pass.
9081 05:53:40.854509
9082 05:53:40.857837 CH 0, Rank 1
9083 05:53:40.857924 SW Impedance : PASS
9084 05:53:40.861135 DUTY Scan : NO K
9085 05:53:40.864402 ZQ Calibration : PASS
9086 05:53:40.864505 Jitter Meter : NO K
9087 05:53:40.867860 CBT Training : PASS
9088 05:53:40.870934 Write leveling : PASS
9089 05:53:40.871008 RX DQS gating : PASS
9090 05:53:40.874326 RX DQ/DQS(RDDQC) : PASS
9091 05:53:40.877497 TX DQ/DQS : PASS
9092 05:53:40.877594 RX DATLAT : PASS
9093 05:53:40.880953 RX DQ/DQS(Engine): PASS
9094 05:53:40.884537 TX OE : PASS
9095 05:53:40.884635 All Pass.
9096 05:53:40.884726
9097 05:53:40.884814 CH 1, Rank 0
9098 05:53:40.887496 SW Impedance : PASS
9099 05:53:40.890826 DUTY Scan : NO K
9100 05:53:40.890896 ZQ Calibration : PASS
9101 05:53:40.894098 Jitter Meter : NO K
9102 05:53:40.897672 CBT Training : PASS
9103 05:53:40.897775 Write leveling : PASS
9104 05:53:40.900583 RX DQS gating : PASS
9105 05:53:40.903922 RX DQ/DQS(RDDQC) : PASS
9106 05:53:40.904021 TX DQ/DQS : PASS
9107 05:53:40.907196 RX DATLAT : PASS
9108 05:53:40.907265 RX DQ/DQS(Engine): PASS
9109 05:53:40.910836 TX OE : PASS
9110 05:53:40.910911 All Pass.
9111 05:53:40.910976
9112 05:53:40.914088 CH 1, Rank 1
9113 05:53:40.914160 SW Impedance : PASS
9114 05:53:40.917230 DUTY Scan : NO K
9115 05:53:40.920560 ZQ Calibration : PASS
9116 05:53:40.920655 Jitter Meter : NO K
9117 05:53:40.923873 CBT Training : PASS
9118 05:53:40.926998 Write leveling : PASS
9119 05:53:40.927071 RX DQS gating : PASS
9120 05:53:40.930357 RX DQ/DQS(RDDQC) : PASS
9121 05:53:40.933675 TX DQ/DQS : PASS
9122 05:53:40.933771 RX DATLAT : PASS
9123 05:53:40.937078 RX DQ/DQS(Engine): PASS
9124 05:53:40.940399 TX OE : PASS
9125 05:53:40.940495 All Pass.
9126 05:53:40.940584
9127 05:53:40.940672 DramC Write-DBI on
9128 05:53:40.943598 PER_BANK_REFRESH: Hybrid Mode
9129 05:53:40.946970 TX_TRACKING: ON
9130 05:53:40.954051 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9131 05:53:40.963834 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9132 05:53:40.970319 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9133 05:53:40.973352 [FAST_K] Save calibration result to emmc
9134 05:53:40.976653 sync common calibartion params.
9135 05:53:40.980132 sync cbt_mode0:1, 1:1
9136 05:53:40.980230 dram_init: ddr_geometry: 2
9137 05:53:40.983156 dram_init: ddr_geometry: 2
9138 05:53:40.986686 dram_init: ddr_geometry: 2
9139 05:53:40.989843 0:dram_rank_size:100000000
9140 05:53:40.989947 1:dram_rank_size:100000000
9141 05:53:40.996821 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9142 05:53:41.000101 DFS_SHUFFLE_HW_MODE: ON
9143 05:53:41.003429 dramc_set_vcore_voltage set vcore to 725000
9144 05:53:41.003537 Read voltage for 1600, 0
9145 05:53:41.006819 Vio18 = 0
9146 05:53:41.006892 Vcore = 725000
9147 05:53:41.006959 Vdram = 0
9148 05:53:41.010198 Vddq = 0
9149 05:53:41.010310 Vmddr = 0
9150 05:53:41.013059 switch to 3200 Mbps bootup
9151 05:53:41.013133 [DramcRunTimeConfig]
9152 05:53:41.016350 PHYPLL
9153 05:53:41.016448 DPM_CONTROL_AFTERK: ON
9154 05:53:41.019645 PER_BANK_REFRESH: ON
9155 05:53:41.023265 REFRESH_OVERHEAD_REDUCTION: ON
9156 05:53:41.023355 CMD_PICG_NEW_MODE: OFF
9157 05:53:41.026496 XRTWTW_NEW_MODE: ON
9158 05:53:41.026593 XRTRTR_NEW_MODE: ON
9159 05:53:41.029675 TX_TRACKING: ON
9160 05:53:41.029774 RDSEL_TRACKING: OFF
9161 05:53:41.033488 DQS Precalculation for DVFS: ON
9162 05:53:41.036493 RX_TRACKING: OFF
9163 05:53:41.036595 HW_GATING DBG: ON
9164 05:53:41.039853 ZQCS_ENABLE_LP4: ON
9165 05:53:41.039949 RX_PICG_NEW_MODE: ON
9166 05:53:41.043236 TX_PICG_NEW_MODE: ON
9167 05:53:41.043310 ENABLE_RX_DCM_DPHY: ON
9168 05:53:41.046062 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9169 05:53:41.049648 DUMMY_READ_FOR_TRACKING: OFF
9170 05:53:41.052887 !!! SPM_CONTROL_AFTERK: OFF
9171 05:53:41.056107 !!! SPM could not control APHY
9172 05:53:41.056207 IMPEDANCE_TRACKING: ON
9173 05:53:41.059341 TEMP_SENSOR: ON
9174 05:53:41.059417 HW_SAVE_FOR_SR: OFF
9175 05:53:41.062910 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9176 05:53:41.066569 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9177 05:53:41.069376 Read ODT Tracking: ON
9178 05:53:41.072839 Refresh Rate DeBounce: ON
9179 05:53:41.072932 DFS_NO_QUEUE_FLUSH: ON
9180 05:53:41.076202 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9181 05:53:41.079392 ENABLE_DFS_RUNTIME_MRW: OFF
9182 05:53:41.082746 DDR_RESERVE_NEW_MODE: ON
9183 05:53:41.082825 MR_CBT_SWITCH_FREQ: ON
9184 05:53:41.086416 =========================
9185 05:53:41.104670 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9186 05:53:41.108009 dram_init: ddr_geometry: 2
9187 05:53:41.126295 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9188 05:53:41.129435 dram_init: dram init end (result: 0)
9189 05:53:41.136305 DRAM-K: Full calibration passed in 24470 msecs
9190 05:53:41.139650 MRC: failed to locate region type 0.
9191 05:53:41.139756 DRAM rank0 size:0x100000000,
9192 05:53:41.142862 DRAM rank1 size=0x100000000
9193 05:53:41.152575 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9194 05:53:41.159472 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9195 05:53:41.166009 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9196 05:53:41.172641 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9197 05:53:41.175941 DRAM rank0 size:0x100000000,
9198 05:53:41.179075 DRAM rank1 size=0x100000000
9199 05:53:41.179154 CBMEM:
9200 05:53:41.182748 IMD: root @ 0xfffff000 254 entries.
9201 05:53:41.185847 IMD: root @ 0xffffec00 62 entries.
9202 05:53:41.189184 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9203 05:53:41.192532 WARNING: RO_VPD is uninitialized or empty.
9204 05:53:41.199062 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9205 05:53:41.206205 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9206 05:53:41.219242 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
9207 05:53:41.230263 BS: romstage times (exec / console): total (unknown) / 23977 ms
9208 05:53:41.230343
9209 05:53:41.230410
9210 05:53:41.240115 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9211 05:53:41.243745 ARM64: Exception handlers installed.
9212 05:53:41.247049 ARM64: Testing exception
9213 05:53:41.250340 ARM64: Done test exception
9214 05:53:41.250420 Enumerating buses...
9215 05:53:41.253636 Show all devs... Before device enumeration.
9216 05:53:41.256855 Root Device: enabled 1
9217 05:53:41.260249 CPU_CLUSTER: 0: enabled 1
9218 05:53:41.260327 CPU: 00: enabled 1
9219 05:53:41.263561 Compare with tree...
9220 05:53:41.263661 Root Device: enabled 1
9221 05:53:41.266926 CPU_CLUSTER: 0: enabled 1
9222 05:53:41.270361 CPU: 00: enabled 1
9223 05:53:41.270464 Root Device scanning...
9224 05:53:41.273521 scan_static_bus for Root Device
9225 05:53:41.276835 CPU_CLUSTER: 0 enabled
9226 05:53:41.280010 scan_static_bus for Root Device done
9227 05:53:41.283517 scan_bus: bus Root Device finished in 8 msecs
9228 05:53:41.283596 done
9229 05:53:41.290292 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9230 05:53:41.293375 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9231 05:53:41.300132 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9232 05:53:41.303452 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9233 05:53:41.306933 Allocating resources...
9234 05:53:41.310393 Reading resources...
9235 05:53:41.313395 Root Device read_resources bus 0 link: 0
9236 05:53:41.313492 DRAM rank0 size:0x100000000,
9237 05:53:41.316787 DRAM rank1 size=0x100000000
9238 05:53:41.320143 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9239 05:53:41.323409 CPU: 00 missing read_resources
9240 05:53:41.326672 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9241 05:53:41.333387 Root Device read_resources bus 0 link: 0 done
9242 05:53:41.333493 Done reading resources.
9243 05:53:41.340042 Show resources in subtree (Root Device)...After reading.
9244 05:53:41.343305 Root Device child on link 0 CPU_CLUSTER: 0
9245 05:53:41.346487 CPU_CLUSTER: 0 child on link 0 CPU: 00
9246 05:53:41.356458 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9247 05:53:41.356566 CPU: 00
9248 05:53:41.359694 Root Device assign_resources, bus 0 link: 0
9249 05:53:41.363017 CPU_CLUSTER: 0 missing set_resources
9250 05:53:41.369784 Root Device assign_resources, bus 0 link: 0 done
9251 05:53:41.369903 Done setting resources.
9252 05:53:41.376493 Show resources in subtree (Root Device)...After assigning values.
9253 05:53:41.379706 Root Device child on link 0 CPU_CLUSTER: 0
9254 05:53:41.383290 CPU_CLUSTER: 0 child on link 0 CPU: 00
9255 05:53:41.393378 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9256 05:53:41.393500 CPU: 00
9257 05:53:41.396281 Done allocating resources.
9258 05:53:41.399517 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9259 05:53:41.403034 Enabling resources...
9260 05:53:41.403140 done.
9261 05:53:41.410003 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9262 05:53:41.410102 Initializing devices...
9263 05:53:41.412898 Root Device init
9264 05:53:41.413020 init hardware done!
9265 05:53:41.416274 0x00000018: ctrlr->caps
9266 05:53:41.419809 52.000 MHz: ctrlr->f_max
9267 05:53:41.419919 0.400 MHz: ctrlr->f_min
9268 05:53:41.423130 0x40ff8080: ctrlr->voltages
9269 05:53:41.423237 sclk: 390625
9270 05:53:41.426368 Bus Width = 1
9271 05:53:41.426476 sclk: 390625
9272 05:53:41.429670 Bus Width = 1
9273 05:53:41.429772 Early init status = 3
9274 05:53:41.436290 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9275 05:53:41.439564 in-header: 03 fb 00 00 01 00 00 00
9276 05:53:41.439666 in-data: 01
9277 05:53:41.446239 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9278 05:53:41.449262 in-header: 03 fb 00 00 01 00 00 00
9279 05:53:41.449364 in-data: 01
9280 05:53:41.456100 [SSUSB] Setting up USB HOST controller...
9281 05:53:41.459478 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9282 05:53:41.459556 [SSUSB] phy power-on done.
9283 05:53:41.465951 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9284 05:53:41.469382 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9285 05:53:41.476041 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9286 05:53:41.482879 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9287 05:53:41.489375 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9288 05:53:41.496087 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9289 05:53:41.502314 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9290 05:53:41.505861 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9291 05:53:41.509222 SPM: binary array size = 0x9dc
9292 05:53:41.515835 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9293 05:53:41.522638 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9294 05:53:41.529254 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9295 05:53:41.532605 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9296 05:53:41.535621 configure_display: Starting display init
9297 05:53:41.571677 anx7625_power_on_init: Init interface.
9298 05:53:41.575125 anx7625_disable_pd_protocol: Disabled PD feature.
9299 05:53:41.578228 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9300 05:53:41.606321 anx7625_start_dp_work: Secure OCM version=00
9301 05:53:41.609543 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9302 05:53:41.624181 sp_tx_get_edid_block: EDID Block = 1
9303 05:53:41.727053 Extracted contents:
9304 05:53:41.730181 header: 00 ff ff ff ff ff ff 00
9305 05:53:41.733314 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9306 05:53:41.736706 version: 01 04
9307 05:53:41.740034 basic params: 95 1f 11 78 0a
9308 05:53:41.743316 chroma info: 76 90 94 55 54 90 27 21 50 54
9309 05:53:41.746654 established: 00 00 00
9310 05:53:41.753440 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9311 05:53:41.756666 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9312 05:53:41.763519 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9313 05:53:41.769872 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9314 05:53:41.776713 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9315 05:53:41.780009 extensions: 00
9316 05:53:41.780088 checksum: fb
9317 05:53:41.780185
9318 05:53:41.783257 Manufacturer: IVO Model 57d Serial Number 0
9319 05:53:41.786634 Made week 0 of 2020
9320 05:53:41.786723 EDID version: 1.4
9321 05:53:41.790006 Digital display
9322 05:53:41.793545 6 bits per primary color channel
9323 05:53:41.793658 DisplayPort interface
9324 05:53:41.796492 Maximum image size: 31 cm x 17 cm
9325 05:53:41.799815 Gamma: 220%
9326 05:53:41.799926 Check DPMS levels
9327 05:53:41.803443 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9328 05:53:41.806736 First detailed timing is preferred timing
9329 05:53:41.809905 Established timings supported:
9330 05:53:41.813366 Standard timings supported:
9331 05:53:41.813446 Detailed timings
9332 05:53:41.819714 Hex of detail: 383680a07038204018303c0035ae10000019
9333 05:53:41.822996 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9334 05:53:41.829666 0780 0798 07c8 0820 hborder 0
9335 05:53:41.833142 0438 043b 0447 0458 vborder 0
9336 05:53:41.836296 -hsync -vsync
9337 05:53:41.836393 Did detailed timing
9338 05:53:41.839781 Hex of detail: 000000000000000000000000000000000000
9339 05:53:41.843214 Manufacturer-specified data, tag 0
9340 05:53:41.849626 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9341 05:53:41.849758 ASCII string: InfoVision
9342 05:53:41.856195 Hex of detail: 000000fe00523134304e574635205248200a
9343 05:53:41.859575 ASCII string: R140NWF5 RH
9344 05:53:41.859681 Checksum
9345 05:53:41.859748 Checksum: 0xfb (valid)
9346 05:53:41.866012 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9347 05:53:41.869312 DSI data_rate: 832800000 bps
9348 05:53:41.872691 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9349 05:53:41.879362 anx7625_parse_edid: pixelclock(138800).
9350 05:53:41.882696 hactive(1920), hsync(48), hfp(24), hbp(88)
9351 05:53:41.886137 vactive(1080), vsync(12), vfp(3), vbp(17)
9352 05:53:41.889464 anx7625_dsi_config: config dsi.
9353 05:53:41.896045 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9354 05:53:41.908867 anx7625_dsi_config: success to config DSI
9355 05:53:41.912115 anx7625_dp_start: MIPI phy setup OK.
9356 05:53:41.915457 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9357 05:53:41.919228 mtk_ddp_mode_set invalid vrefresh 60
9358 05:53:41.922074 main_disp_path_setup
9359 05:53:41.922188 ovl_layer_smi_id_en
9360 05:53:41.925699 ovl_layer_smi_id_en
9361 05:53:41.925811 ccorr_config
9362 05:53:41.925905 aal_config
9363 05:53:41.928895 gamma_config
9364 05:53:41.929004 postmask_config
9365 05:53:41.931950 dither_config
9366 05:53:41.935443 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9367 05:53:41.942230 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9368 05:53:41.945350 Root Device init finished in 529 msecs
9369 05:53:41.945434 CPU_CLUSTER: 0 init
9370 05:53:41.955379 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9371 05:53:41.958766 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9372 05:53:41.962006 APU_MBOX 0x190000b0 = 0x10001
9373 05:53:41.965364 APU_MBOX 0x190001b0 = 0x10001
9374 05:53:41.968562 APU_MBOX 0x190005b0 = 0x10001
9375 05:53:41.971752 APU_MBOX 0x190006b0 = 0x10001
9376 05:53:41.975183 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9377 05:53:41.987759 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9378 05:53:42.000558 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9379 05:53:42.007096 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9380 05:53:42.018436 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9381 05:53:42.027443 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9382 05:53:42.030897 CPU_CLUSTER: 0 init finished in 81 msecs
9383 05:53:42.034207 Devices initialized
9384 05:53:42.037662 Show all devs... After init.
9385 05:53:42.037787 Root Device: enabled 1
9386 05:53:42.040850 CPU_CLUSTER: 0: enabled 1
9387 05:53:42.044272 CPU: 00: enabled 1
9388 05:53:42.047706 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9389 05:53:42.050826 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9390 05:53:42.054235 ELOG: NV offset 0x57f000 size 0x1000
9391 05:53:42.060904 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9392 05:53:42.067486 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9393 05:53:42.070954 ELOG: Event(17) added with size 13 at 2023-12-25 05:52:59 UTC
9394 05:53:42.074141 out: cmd=0x121: 03 db 21 01 00 00 00 00
9395 05:53:42.077867 in-header: 03 6a 00 00 2c 00 00 00
9396 05:53:42.091275 in-data: f6 67 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9397 05:53:42.097788 ELOG: Event(A1) added with size 10 at 2023-12-25 05:52:59 UTC
9398 05:53:42.104527 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9399 05:53:42.111332 ELOG: Event(A0) added with size 9 at 2023-12-25 05:52:59 UTC
9400 05:53:42.114709 elog_add_boot_reason: Logged dev mode boot
9401 05:53:42.118017 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9402 05:53:42.121346 Finalize devices...
9403 05:53:42.121446 Devices finalized
9404 05:53:42.128014 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9405 05:53:42.131053 Writing coreboot table at 0xffe64000
9406 05:53:42.134390 0. 000000000010a000-0000000000113fff: RAMSTAGE
9407 05:53:42.137716 1. 0000000040000000-00000000400fffff: RAM
9408 05:53:42.144098 2. 0000000040100000-000000004032afff: RAMSTAGE
9409 05:53:42.147729 3. 000000004032b000-00000000545fffff: RAM
9410 05:53:42.150788 4. 0000000054600000-000000005465ffff: BL31
9411 05:53:42.153934 5. 0000000054660000-00000000ffe63fff: RAM
9412 05:53:42.160478 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9413 05:53:42.164115 7. 0000000100000000-000000023fffffff: RAM
9414 05:53:42.167292 Passing 5 GPIOs to payload:
9415 05:53:42.170579 NAME | PORT | POLARITY | VALUE
9416 05:53:42.174021 EC in RW | 0x000000aa | low | undefined
9417 05:53:42.180479 EC interrupt | 0x00000005 | low | undefined
9418 05:53:42.183840 TPM interrupt | 0x000000ab | high | undefined
9419 05:53:42.190405 SD card detect | 0x00000011 | high | undefined
9420 05:53:42.193924 speaker enable | 0x00000093 | high | undefined
9421 05:53:42.197351 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9422 05:53:42.200761 in-header: 03 f9 00 00 02 00 00 00
9423 05:53:42.200868 in-data: 02 00
9424 05:53:42.203979 ADC[4]: Raw value=901032 ID=7
9425 05:53:42.206930 ADC[3]: Raw value=213179 ID=1
9426 05:53:42.210264 RAM Code: 0x71
9427 05:53:42.210338 ADC[6]: Raw value=74502 ID=0
9428 05:53:42.213630 ADC[5]: Raw value=212072 ID=1
9429 05:53:42.217014 SKU Code: 0x1
9430 05:53:42.220252 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 584a
9431 05:53:42.223530 coreboot table: 964 bytes.
9432 05:53:42.227044 IMD ROOT 0. 0xfffff000 0x00001000
9433 05:53:42.230226 IMD SMALL 1. 0xffffe000 0x00001000
9434 05:53:42.233857 RO MCACHE 2. 0xffffc000 0x00001104
9435 05:53:42.236780 CONSOLE 3. 0xfff7c000 0x00080000
9436 05:53:42.240074 FMAP 4. 0xfff7b000 0x00000452
9437 05:53:42.243450 TIME STAMP 5. 0xfff7a000 0x00000910
9438 05:53:42.246842 VBOOT WORK 6. 0xfff66000 0x00014000
9439 05:53:42.250160 RAMOOPS 7. 0xffe66000 0x00100000
9440 05:53:42.253681 COREBOOT 8. 0xffe64000 0x00002000
9441 05:53:42.253794 IMD small region:
9442 05:53:42.256676 IMD ROOT 0. 0xffffec00 0x00000400
9443 05:53:42.260034 VPD 1. 0xffffeb80 0x0000006c
9444 05:53:42.263618 MMC STATUS 2. 0xffffeb60 0x00000004
9445 05:53:42.269919 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9446 05:53:42.273363 Probing TPM: done!
9447 05:53:42.276650 Connected to device vid:did:rid of 1ae0:0028:00
9448 05:53:42.286939 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9449 05:53:42.290309 Initialized TPM device CR50 revision 0
9450 05:53:42.293887 Checking cr50 for pending updates
9451 05:53:42.297347 Reading cr50 TPM mode
9452 05:53:42.306224 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9453 05:53:42.312910 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9454 05:53:42.352616 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9455 05:53:42.356181 Checking segment from ROM address 0x40100000
9456 05:53:42.359368 Checking segment from ROM address 0x4010001c
9457 05:53:42.366160 Loading segment from ROM address 0x40100000
9458 05:53:42.366274 code (compression=0)
9459 05:53:42.376009 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9460 05:53:42.382553 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9461 05:53:42.382664 it's not compressed!
9462 05:53:42.389623 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9463 05:53:42.395898 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9464 05:53:42.413695 Loading segment from ROM address 0x4010001c
9465 05:53:42.413800 Entry Point 0x80000000
9466 05:53:42.416700 Loaded segments
9467 05:53:42.420119 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9468 05:53:42.426380 Jumping to boot code at 0x80000000(0xffe64000)
9469 05:53:42.433500 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9470 05:53:42.440003 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9471 05:53:42.448022 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9472 05:53:42.451068 Checking segment from ROM address 0x40100000
9473 05:53:42.454642 Checking segment from ROM address 0x4010001c
9474 05:53:42.460943 Loading segment from ROM address 0x40100000
9475 05:53:42.461029 code (compression=1)
9476 05:53:42.467923 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9477 05:53:42.477755 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9478 05:53:42.477846 using LZMA
9479 05:53:42.486188 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9480 05:53:42.492689 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9481 05:53:42.496180 Loading segment from ROM address 0x4010001c
9482 05:53:42.496266 Entry Point 0x54601000
9483 05:53:42.499501 Loaded segments
9484 05:53:42.502474 NOTICE: MT8192 bl31_setup
9485 05:53:42.509433 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9486 05:53:42.513168 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9487 05:53:42.516540 WARNING: region 0:
9488 05:53:42.519757 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 05:53:42.519843 WARNING: region 1:
9490 05:53:42.526273 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9491 05:53:42.529657 WARNING: region 2:
9492 05:53:42.533046 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9493 05:53:42.536327 WARNING: region 3:
9494 05:53:42.539566 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9495 05:53:42.542953 WARNING: region 4:
9496 05:53:42.549506 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9497 05:53:42.549623 WARNING: region 5:
9498 05:53:42.552822 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 05:53:42.556464 WARNING: region 6:
9500 05:53:42.559725 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 05:53:42.559810 WARNING: region 7:
9502 05:53:42.566209 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 05:53:42.572778 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9504 05:53:42.576165 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9505 05:53:42.579671 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9506 05:53:42.586332 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9507 05:53:42.589921 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9508 05:53:42.592825 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9509 05:53:42.600074 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9510 05:53:42.603310 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9511 05:53:42.606566 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9512 05:53:42.613055 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9513 05:53:42.616256 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9514 05:53:42.623329 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9515 05:53:42.626647 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9516 05:53:42.629531 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9517 05:53:42.636320 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9518 05:53:42.639576 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9519 05:53:42.642927 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9520 05:53:42.649665 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9521 05:53:42.652811 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9522 05:53:42.659478 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9523 05:53:42.662949 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9524 05:53:42.666717 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9525 05:53:42.672966 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9526 05:53:42.676511 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9527 05:53:42.682963 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9528 05:53:42.686150 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9529 05:53:42.689648 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9530 05:53:42.696403 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9531 05:53:42.699572 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9532 05:53:42.703151 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9533 05:53:42.709929 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9534 05:53:42.713322 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9535 05:53:42.716509 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9536 05:53:42.723465 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9537 05:53:42.726311 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9538 05:53:42.729730 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9539 05:53:42.733095 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9540 05:53:42.739770 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9541 05:53:42.743055 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9542 05:53:42.746480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9543 05:53:42.749877 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9544 05:53:42.756623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9545 05:53:42.759980 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9546 05:53:42.762838 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9547 05:53:42.766162 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9548 05:53:42.773395 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9549 05:53:42.776494 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9550 05:53:42.780046 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9551 05:53:42.786208 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9552 05:53:42.789683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9553 05:53:42.796398 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9554 05:53:42.799874 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9555 05:53:42.803273 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9556 05:53:42.810196 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9557 05:53:42.813006 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9558 05:53:42.819671 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9559 05:53:42.823324 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9560 05:53:42.826407 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9561 05:53:42.833206 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9562 05:53:42.836586 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9563 05:53:42.843379 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9564 05:53:42.846309 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9565 05:53:42.853382 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9566 05:53:42.856632 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9567 05:53:42.863414 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9568 05:53:42.866685 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9569 05:53:42.869919 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9570 05:53:42.876545 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9571 05:53:42.880085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9572 05:53:42.886424 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9573 05:53:42.889985 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9574 05:53:42.893563 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9575 05:53:42.900096 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9576 05:53:42.903305 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9577 05:53:42.910018 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9578 05:53:42.913429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9579 05:53:42.920099 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9580 05:53:42.923352 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9581 05:53:42.926857 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9582 05:53:42.933417 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9583 05:53:42.936736 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9584 05:53:42.943646 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9585 05:53:42.946794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9586 05:53:42.953551 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9587 05:53:42.956864 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9588 05:53:42.960215 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9589 05:53:42.966914 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9590 05:53:42.970155 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9591 05:53:42.976971 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9592 05:53:42.980208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9593 05:53:42.987142 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9594 05:53:42.990327 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9595 05:53:42.993464 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9596 05:53:43.000039 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9597 05:53:43.003692 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9598 05:53:43.010344 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9599 05:53:43.013694 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9600 05:53:43.016844 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9601 05:53:43.023494 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9602 05:53:43.026790 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9603 05:53:43.030353 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9604 05:53:43.033526 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9605 05:53:43.040302 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9606 05:53:43.043592 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9607 05:53:43.050093 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9608 05:53:43.053430 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9609 05:53:43.056786 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9610 05:53:43.063439 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9611 05:53:43.066723 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9612 05:53:43.073468 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9613 05:53:43.076949 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9614 05:53:43.080087 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9615 05:53:43.086818 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9616 05:53:43.090171 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9617 05:53:43.096873 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9618 05:53:43.100476 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9619 05:53:43.103830 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9620 05:53:43.106876 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9621 05:53:43.113706 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9622 05:53:43.117168 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9623 05:53:43.120315 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9624 05:53:43.123851 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9625 05:53:43.130206 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9626 05:53:43.133656 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9627 05:53:43.137041 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9628 05:53:43.143902 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9629 05:53:43.147283 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9630 05:53:43.153891 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9631 05:53:43.157326 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9632 05:53:43.160624 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9633 05:53:43.167088 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9634 05:53:43.170467 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9635 05:53:43.173855 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9636 05:53:43.180305 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9637 05:53:43.183651 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9638 05:53:43.190514 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9639 05:53:43.194186 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9640 05:53:43.197057 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9641 05:53:43.204276 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9642 05:53:43.207296 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9643 05:53:43.210971 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9644 05:53:43.217134 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9645 05:53:43.220877 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9646 05:53:43.227359 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9647 05:53:43.230908 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9648 05:53:43.234334 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9649 05:53:43.240783 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9650 05:53:43.244086 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9651 05:53:43.250583 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9652 05:53:43.253901 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9653 05:53:43.257244 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9654 05:53:43.263957 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9655 05:53:43.267250 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9656 05:53:43.270592 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9657 05:53:43.277190 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9658 05:53:43.280878 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9659 05:53:43.287334 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9660 05:53:43.290842 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9661 05:53:43.294274 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9662 05:53:43.300585 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9663 05:53:43.303815 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9664 05:53:43.310670 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9665 05:53:43.313704 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9666 05:53:43.317133 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9667 05:53:43.323559 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9668 05:53:43.327384 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9669 05:53:43.333725 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9670 05:53:43.336777 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9671 05:53:43.340858 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9672 05:53:43.346921 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9673 05:53:43.350388 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9674 05:53:43.357385 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9675 05:53:43.360366 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9676 05:53:43.363700 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9677 05:53:43.370317 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9678 05:53:43.373739 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9679 05:53:43.376880 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9680 05:53:43.383630 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9681 05:53:43.387191 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9682 05:53:43.393799 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9683 05:53:43.397085 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9684 05:53:43.400244 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9685 05:53:43.407008 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9686 05:53:43.410242 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9687 05:53:43.417100 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9688 05:53:43.420104 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9689 05:53:43.423622 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9690 05:53:43.430130 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9691 05:53:43.433389 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9692 05:53:43.440223 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9693 05:53:43.443328 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9694 05:53:43.446798 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9695 05:53:43.453619 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9696 05:53:43.457044 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9697 05:53:43.463395 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9698 05:53:43.466759 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9699 05:53:43.470407 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9700 05:53:43.476800 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9701 05:53:43.480033 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9702 05:53:43.486757 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9703 05:53:43.490109 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9704 05:53:43.493741 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9705 05:53:43.500329 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9706 05:53:43.503673 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9707 05:53:43.510130 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9708 05:53:43.513494 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9709 05:53:43.520267 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9710 05:53:43.523688 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9711 05:53:43.526697 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9712 05:53:43.533311 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9713 05:53:43.536674 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9714 05:53:43.543259 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9715 05:53:43.546467 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9716 05:53:43.550009 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9717 05:53:43.556565 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9718 05:53:43.560311 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9719 05:53:43.566822 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9720 05:53:43.570236 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9721 05:53:43.576877 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9722 05:53:43.580446 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9723 05:53:43.583423 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9724 05:53:43.590006 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9725 05:53:43.593400 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9726 05:53:43.600191 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9727 05:53:43.603544 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9728 05:53:43.606897 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9729 05:53:43.613394 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9730 05:53:43.616742 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9731 05:53:43.623513 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9732 05:53:43.626968 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9733 05:53:43.630187 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9734 05:53:43.633368 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9735 05:53:43.636525 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9736 05:53:43.643607 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9737 05:53:43.646710 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9738 05:53:43.650178 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9739 05:53:43.656390 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9740 05:53:43.659968 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9741 05:53:43.663399 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9742 05:53:43.669882 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9743 05:53:43.673197 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9744 05:53:43.679787 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9745 05:53:43.683038 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9746 05:53:43.686380 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9747 05:53:43.692867 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9748 05:53:43.696312 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9749 05:53:43.703255 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9750 05:53:43.706431 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9751 05:53:43.709649 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9752 05:53:43.716472 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9753 05:53:43.719841 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9754 05:53:43.723178 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9755 05:53:43.729946 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9756 05:53:43.733139 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9757 05:53:43.736287 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9758 05:53:43.742914 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9759 05:53:43.746401 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9760 05:53:43.753269 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9761 05:53:43.756404 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9762 05:53:43.759604 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9763 05:53:43.766282 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9764 05:53:43.769765 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9765 05:53:43.773077 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9766 05:53:43.779384 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9767 05:53:43.782706 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9768 05:53:43.786006 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9769 05:53:43.792603 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9770 05:53:43.796010 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9771 05:53:43.799371 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9772 05:53:43.806108 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9773 05:53:43.809647 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9774 05:53:43.812627 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9775 05:53:43.816267 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9776 05:53:43.819193 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9777 05:53:43.825930 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9778 05:53:43.829345 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9779 05:53:43.832655 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9780 05:53:43.839250 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9781 05:53:43.842507 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9782 05:53:43.846024 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9783 05:53:43.849072 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9784 05:53:43.855731 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9785 05:53:43.859373 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9786 05:53:43.865878 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9787 05:53:43.869233 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9788 05:53:43.872300 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9789 05:53:43.878843 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9790 05:53:43.882524 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9791 05:53:43.888836 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9792 05:53:43.892528 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9793 05:53:43.895893 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9794 05:53:43.902468 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9795 05:53:43.905861 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9796 05:53:43.912060 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9797 05:53:43.915582 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9798 05:53:43.918876 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9799 05:53:43.925678 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9800 05:53:43.929067 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9801 05:53:43.935692 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9802 05:53:43.938922 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9803 05:53:43.942248 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9804 05:53:43.948626 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9805 05:53:43.952298 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9806 05:53:43.958840 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9807 05:53:43.962057 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9808 05:53:43.965587 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9809 05:53:43.972117 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9810 05:53:43.975483 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9811 05:53:43.981943 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9812 05:53:43.985418 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9813 05:53:43.991937 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9814 05:53:43.995387 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9815 05:53:43.998607 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9816 05:53:44.005347 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9817 05:53:44.008639 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9818 05:53:44.015502 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9819 05:53:44.018884 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9820 05:53:44.021871 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9821 05:53:44.028860 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9822 05:53:44.032293 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9823 05:53:44.038534 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9824 05:53:44.041896 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9825 05:53:44.045287 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9826 05:53:44.051718 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9827 05:53:44.055325 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9828 05:53:44.062001 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9829 05:53:44.064993 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9830 05:53:44.068526 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9831 05:53:44.074923 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9832 05:53:44.078427 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9833 05:53:44.085170 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9834 05:53:44.088324 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9835 05:53:44.091833 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9836 05:53:44.098510 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9837 05:53:44.101915 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9838 05:53:44.108410 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9839 05:53:44.111882 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9840 05:53:44.115277 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9841 05:53:44.121702 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9842 05:53:44.124801 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9843 05:53:44.131898 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9844 05:53:44.134752 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9845 05:53:44.141492 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9846 05:53:44.145205 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9847 05:53:44.148472 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9848 05:53:44.154830 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9849 05:53:44.158548 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9850 05:53:44.164840 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9851 05:53:44.168355 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9852 05:53:44.171500 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9853 05:53:44.178239 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9854 05:53:44.181312 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9855 05:53:44.188032 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9856 05:53:44.191466 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9857 05:53:44.194922 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9858 05:53:44.201296 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9859 05:53:44.205077 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9860 05:53:44.211410 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9861 05:53:44.214778 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9862 05:53:44.221370 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9863 05:53:44.225093 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9864 05:53:44.228048 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9865 05:53:44.234776 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9866 05:53:44.238123 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9867 05:53:44.244673 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9868 05:53:44.248408 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9869 05:53:44.254537 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9870 05:53:44.257831 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9871 05:53:44.264643 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9872 05:53:44.267839 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9873 05:53:44.271238 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9874 05:53:44.277828 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9875 05:53:44.281510 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9876 05:53:44.287938 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9877 05:53:44.291507 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9878 05:53:44.297845 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9879 05:53:44.301234 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9880 05:53:44.304792 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9881 05:53:44.311004 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9882 05:53:44.314275 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9883 05:53:44.321390 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9884 05:53:44.324609 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9885 05:53:44.327928 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9886 05:53:44.334788 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9887 05:53:44.337832 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9888 05:53:44.344515 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9889 05:53:44.347845 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9890 05:53:44.354529 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9891 05:53:44.357828 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9892 05:53:44.361154 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9893 05:53:44.368072 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9894 05:53:44.371308 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9895 05:53:44.377670 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9896 05:53:44.381245 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9897 05:53:44.387673 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9898 05:53:44.391106 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9899 05:53:44.394231 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9900 05:53:44.401254 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9901 05:53:44.404364 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9902 05:53:44.410912 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9903 05:53:44.414210 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9904 05:53:44.420998 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9905 05:53:44.424255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9906 05:53:44.427668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9907 05:53:44.434386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9908 05:53:44.437377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9909 05:53:44.444202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9910 05:53:44.447422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9911 05:53:44.454098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9912 05:53:44.457467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9913 05:53:44.464068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9914 05:53:44.467508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9915 05:53:44.474595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9916 05:53:44.477509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9917 05:53:44.484266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9918 05:53:44.487477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9919 05:53:44.494183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9920 05:53:44.497660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9921 05:53:44.504298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9922 05:53:44.507455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9923 05:53:44.510578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9924 05:53:44.517619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9925 05:53:44.520598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9926 05:53:44.527155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9927 05:53:44.530502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9928 05:53:44.537270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9929 05:53:44.540516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9930 05:53:44.547091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9931 05:53:44.550443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9932 05:53:44.557183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9933 05:53:44.563881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9934 05:53:44.567215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9935 05:53:44.573747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9936 05:53:44.577059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9937 05:53:44.580566 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9938 05:53:44.583817 INFO: [APUAPC] vio 0
9939 05:53:44.586857 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9940 05:53:44.593775 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9941 05:53:44.597245 INFO: [APUAPC] D0_APC_0: 0x400510
9942 05:53:44.600375 INFO: [APUAPC] D0_APC_1: 0x0
9943 05:53:44.603917 INFO: [APUAPC] D0_APC_2: 0x1540
9944 05:53:44.604003 INFO: [APUAPC] D0_APC_3: 0x0
9945 05:53:44.607177 INFO: [APUAPC] D1_APC_0: 0xffffffff
9946 05:53:44.610342 INFO: [APUAPC] D1_APC_1: 0xffffffff
9947 05:53:44.614087 INFO: [APUAPC] D1_APC_2: 0x3fffff
9948 05:53:44.617143 INFO: [APUAPC] D1_APC_3: 0x0
9949 05:53:44.620705 INFO: [APUAPC] D2_APC_0: 0xffffffff
9950 05:53:44.624009 INFO: [APUAPC] D2_APC_1: 0xffffffff
9951 05:53:44.627388 INFO: [APUAPC] D2_APC_2: 0x3fffff
9952 05:53:44.630634 INFO: [APUAPC] D2_APC_3: 0x0
9953 05:53:44.633863 INFO: [APUAPC] D3_APC_0: 0xffffffff
9954 05:53:44.637287 INFO: [APUAPC] D3_APC_1: 0xffffffff
9955 05:53:44.640533 INFO: [APUAPC] D3_APC_2: 0x3fffff
9956 05:53:44.643918 INFO: [APUAPC] D3_APC_3: 0x0
9957 05:53:44.646929 INFO: [APUAPC] D4_APC_0: 0xffffffff
9958 05:53:44.650752 INFO: [APUAPC] D4_APC_1: 0xffffffff
9959 05:53:44.654158 INFO: [APUAPC] D4_APC_2: 0x3fffff
9960 05:53:44.657019 INFO: [APUAPC] D4_APC_3: 0x0
9961 05:53:44.660421 INFO: [APUAPC] D5_APC_0: 0xffffffff
9962 05:53:44.663712 INFO: [APUAPC] D5_APC_1: 0xffffffff
9963 05:53:44.667041 INFO: [APUAPC] D5_APC_2: 0x3fffff
9964 05:53:44.670463 INFO: [APUAPC] D5_APC_3: 0x0
9965 05:53:44.673716 INFO: [APUAPC] D6_APC_0: 0xffffffff
9966 05:53:44.677089 INFO: [APUAPC] D6_APC_1: 0xffffffff
9967 05:53:44.680825 INFO: [APUAPC] D6_APC_2: 0x3fffff
9968 05:53:44.683936 INFO: [APUAPC] D6_APC_3: 0x0
9969 05:53:44.687353 INFO: [APUAPC] D7_APC_0: 0xffffffff
9970 05:53:44.690598 INFO: [APUAPC] D7_APC_1: 0xffffffff
9971 05:53:44.693879 INFO: [APUAPC] D7_APC_2: 0x3fffff
9972 05:53:44.697184 INFO: [APUAPC] D7_APC_3: 0x0
9973 05:53:44.700582 INFO: [APUAPC] D8_APC_0: 0xffffffff
9974 05:53:44.704289 INFO: [APUAPC] D8_APC_1: 0xffffffff
9975 05:53:44.707170 INFO: [APUAPC] D8_APC_2: 0x3fffff
9976 05:53:44.710710 INFO: [APUAPC] D8_APC_3: 0x0
9977 05:53:44.713789 INFO: [APUAPC] D9_APC_0: 0xffffffff
9978 05:53:44.717270 INFO: [APUAPC] D9_APC_1: 0xffffffff
9979 05:53:44.720560 INFO: [APUAPC] D9_APC_2: 0x3fffff
9980 05:53:44.723750 INFO: [APUAPC] D9_APC_3: 0x0
9981 05:53:44.727148 INFO: [APUAPC] D10_APC_0: 0xffffffff
9982 05:53:44.730394 INFO: [APUAPC] D10_APC_1: 0xffffffff
9983 05:53:44.733913 INFO: [APUAPC] D10_APC_2: 0x3fffff
9984 05:53:44.737176 INFO: [APUAPC] D10_APC_3: 0x0
9985 05:53:44.740525 INFO: [APUAPC] D11_APC_0: 0xffffffff
9986 05:53:44.743844 INFO: [APUAPC] D11_APC_1: 0xffffffff
9987 05:53:44.747267 INFO: [APUAPC] D11_APC_2: 0x3fffff
9988 05:53:44.750801 INFO: [APUAPC] D11_APC_3: 0x0
9989 05:53:44.753798 INFO: [APUAPC] D12_APC_0: 0xffffffff
9990 05:53:44.757182 INFO: [APUAPC] D12_APC_1: 0xffffffff
9991 05:53:44.760464 INFO: [APUAPC] D12_APC_2: 0x3fffff
9992 05:53:44.763925 INFO: [APUAPC] D12_APC_3: 0x0
9993 05:53:44.767087 INFO: [APUAPC] D13_APC_0: 0xffffffff
9994 05:53:44.770433 INFO: [APUAPC] D13_APC_1: 0xffffffff
9995 05:53:44.773706 INFO: [APUAPC] D13_APC_2: 0x3fffff
9996 05:53:44.776612 INFO: [APUAPC] D13_APC_3: 0x0
9997 05:53:44.780003 INFO: [APUAPC] D14_APC_0: 0xffffffff
9998 05:53:44.783547 INFO: [APUAPC] D14_APC_1: 0xffffffff
9999 05:53:44.786972 INFO: [APUAPC] D14_APC_2: 0x3fffff
10000 05:53:44.790313 INFO: [APUAPC] D14_APC_3: 0x0
10001 05:53:44.793506 INFO: [APUAPC] D15_APC_0: 0xffffffff
10002 05:53:44.796785 INFO: [APUAPC] D15_APC_1: 0xffffffff
10003 05:53:44.800119 INFO: [APUAPC] D15_APC_2: 0x3fffff
10004 05:53:44.803533 INFO: [APUAPC] D15_APC_3: 0x0
10005 05:53:44.803614 INFO: [APUAPC] APC_CON: 0x4
10006 05:53:44.806885 INFO: [NOCDAPC] D0_APC_0: 0x0
10007 05:53:44.810097 INFO: [NOCDAPC] D0_APC_1: 0x0
10008 05:53:44.813572 INFO: [NOCDAPC] D1_APC_0: 0x0
10009 05:53:44.816908 INFO: [NOCDAPC] D1_APC_1: 0xfff
10010 05:53:44.820486 INFO: [NOCDAPC] D2_APC_0: 0x0
10011 05:53:44.823561 INFO: [NOCDAPC] D2_APC_1: 0xfff
10012 05:53:44.826994 INFO: [NOCDAPC] D3_APC_0: 0x0
10013 05:53:44.830122 INFO: [NOCDAPC] D3_APC_1: 0xfff
10014 05:53:44.833500 INFO: [NOCDAPC] D4_APC_0: 0x0
10015 05:53:44.833606 INFO: [NOCDAPC] D4_APC_1: 0xfff
10016 05:53:44.836854 INFO: [NOCDAPC] D5_APC_0: 0x0
10017 05:53:44.840191 INFO: [NOCDAPC] D5_APC_1: 0xfff
10018 05:53:44.843638 INFO: [NOCDAPC] D6_APC_0: 0x0
10019 05:53:44.847105 INFO: [NOCDAPC] D6_APC_1: 0xfff
10020 05:53:44.850212 INFO: [NOCDAPC] D7_APC_0: 0x0
10021 05:53:44.853269 INFO: [NOCDAPC] D7_APC_1: 0xfff
10022 05:53:44.856985 INFO: [NOCDAPC] D8_APC_0: 0x0
10023 05:53:44.860103 INFO: [NOCDAPC] D8_APC_1: 0xfff
10024 05:53:44.863511 INFO: [NOCDAPC] D9_APC_0: 0x0
10025 05:53:44.866388 INFO: [NOCDAPC] D9_APC_1: 0xfff
10026 05:53:44.870008 INFO: [NOCDAPC] D10_APC_0: 0x0
10027 05:53:44.870112 INFO: [NOCDAPC] D10_APC_1: 0xfff
10028 05:53:44.873376 INFO: [NOCDAPC] D11_APC_0: 0x0
10029 05:53:44.876762 INFO: [NOCDAPC] D11_APC_1: 0xfff
10030 05:53:44.880031 INFO: [NOCDAPC] D12_APC_0: 0x0
10031 05:53:44.883337 INFO: [NOCDAPC] D12_APC_1: 0xfff
10032 05:53:44.886447 INFO: [NOCDAPC] D13_APC_0: 0x0
10033 05:53:44.889705 INFO: [NOCDAPC] D13_APC_1: 0xfff
10034 05:53:44.893447 INFO: [NOCDAPC] D14_APC_0: 0x0
10035 05:53:44.896365 INFO: [NOCDAPC] D14_APC_1: 0xfff
10036 05:53:44.899681 INFO: [NOCDAPC] D15_APC_0: 0x0
10037 05:53:44.903438 INFO: [NOCDAPC] D15_APC_1: 0xfff
10038 05:53:44.906710 INFO: [NOCDAPC] APC_CON: 0x4
10039 05:53:44.910119 INFO: [APUAPC] set_apusys_apc done
10040 05:53:44.912992 INFO: [DEVAPC] devapc_init done
10041 05:53:44.916548 INFO: GICv3 without legacy support detected.
10042 05:53:44.919667 INFO: ARM GICv3 driver initialized in EL3
10043 05:53:44.922924 INFO: Maximum SPI INTID supported: 639
10044 05:53:44.926338 INFO: BL31: Initializing runtime services
10045 05:53:44.933295 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10046 05:53:44.936323 INFO: SPM: enable CPC mode
10047 05:53:44.939824 INFO: mcdi ready for mcusys-off-idle and system suspend
10048 05:53:44.946285 INFO: BL31: Preparing for EL3 exit to normal world
10049 05:53:44.949627 INFO: Entry point address = 0x80000000
10050 05:53:44.952994 INFO: SPSR = 0x8
10051 05:53:44.957248
10052 05:53:44.957337
10053 05:53:44.957429
10054 05:53:44.960696 Starting depthcharge on Spherion...
10055 05:53:44.960783
10056 05:53:44.960870 Wipe memory regions:
10057 05:53:44.960952
10058 05:53:44.961740 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10059 05:53:44.961897 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10060 05:53:44.962253 Setting prompt string to ['asurada:']
10061 05:53:44.962351 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10062 05:53:44.963907 [0x00000040000000, 0x00000054600000)
10063 05:53:45.086283
10064 05:53:45.086429 [0x00000054660000, 0x00000080000000)
10065 05:53:45.346760
10066 05:53:45.346906 [0x000000821a7280, 0x000000ffe64000)
10067 05:53:46.091604
10068 05:53:46.091740 [0x00000100000000, 0x00000240000000)
10069 05:53:47.981597
10070 05:53:47.984970 Initializing XHCI USB controller at 0x11200000.
10071 05:53:49.022864
10072 05:53:49.025812 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10073 05:53:49.025927
10074 05:53:49.026030
10075 05:53:49.026096
10076 05:53:49.026384 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10078 05:53:49.126707 asurada: tftpboot 192.168.201.1 12379433/tftp-deploy-cd2_bfbv/kernel/image.itb 12379433/tftp-deploy-cd2_bfbv/kernel/cmdline
10079 05:53:49.126872 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10080 05:53:49.126965 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10081 05:53:49.131266 tftpboot 192.168.201.1 12379433/tftp-deploy-cd2_bfbv/kernel/image.itp-deploy-cd2_bfbv/kernel/cmdline
10082 05:53:49.131356
10083 05:53:49.131426 Waiting for link
10084 05:53:49.291626
10085 05:53:49.291759 R8152: Initializing
10086 05:53:49.291835
10087 05:53:49.295086 Version 9 (ocp_data = 6010)
10088 05:53:49.295165
10089 05:53:49.298299 R8152: Done initializing
10090 05:53:49.298377
10091 05:53:49.298442 Adding net device
10092 05:53:51.244296
10093 05:53:51.244447 done.
10094 05:53:51.244522
10095 05:53:51.244588 MAC: 00:e0:4c:72:2d:d6
10096 05:53:51.244652
10097 05:53:51.247482 Sending DHCP discover... done.
10098 05:53:51.247563
10099 05:53:54.487858 Waiting for reply... done.
10100 05:53:54.488001
10101 05:53:54.488072 Sending DHCP request... done.
10102 05:53:54.490857
10103 05:53:54.490940 Waiting for reply... done.
10104 05:53:54.491006
10105 05:53:54.494181 My ip is 192.168.201.21
10106 05:53:54.494263
10107 05:53:54.497493 The DHCP server ip is 192.168.201.1
10108 05:53:54.497576
10109 05:53:54.500844 TFTP server IP predefined by user: 192.168.201.1
10110 05:53:54.500927
10111 05:53:54.507346 Bootfile predefined by user: 12379433/tftp-deploy-cd2_bfbv/kernel/image.itb
10112 05:53:54.507462
10113 05:53:54.510511 Sending tftp read request... done.
10114 05:53:54.510594
10115 05:53:54.514153 Waiting for the transfer...
10116 05:53:54.514237
10117 05:53:54.800016 00000000 ################################################################
10118 05:53:54.800202
10119 05:53:55.090235 00080000 ################################################################
10120 05:53:55.090368
10121 05:53:55.370786 00100000 ################################################################
10122 05:53:55.370926
10123 05:53:55.636811 00180000 ################################################################
10124 05:53:55.636966
10125 05:53:55.889508 00200000 ################################################################
10126 05:53:55.889644
10127 05:53:56.130148 00280000 ################################################################
10128 05:53:56.130320
10129 05:53:56.372645 00300000 ################################################################
10130 05:53:56.372824
10131 05:53:56.610931 00380000 ################################################################
10132 05:53:56.611135
10133 05:53:56.878730 00400000 ################################################################
10134 05:53:56.878874
10135 05:53:57.168803 00480000 ################################################################
10136 05:53:57.168944
10137 05:53:57.428237 00500000 ################################################################
10138 05:53:57.428393
10139 05:53:57.689870 00580000 ################################################################
10140 05:53:57.690042
10141 05:53:57.959864 00600000 ################################################################
10142 05:53:57.960006
10143 05:53:58.230300 00680000 ################################################################
10144 05:53:58.230471
10145 05:53:58.501694 00700000 ################################################################
10146 05:53:58.501859
10147 05:53:58.762728 00780000 ################################################################
10148 05:53:58.762864
10149 05:53:59.035444 00800000 ################################################################
10150 05:53:59.035586
10151 05:53:59.292157 00880000 ################################################################
10152 05:53:59.292322
10153 05:53:59.565483 00900000 ################################################################
10154 05:53:59.565622
10155 05:53:59.825191 00980000 ################################################################
10156 05:53:59.825331
10157 05:54:00.082477 00a00000 ################################################################
10158 05:54:00.082619
10159 05:54:00.336164 00a80000 ################################################################
10160 05:54:00.336307
10161 05:54:00.610301 00b00000 ################################################################
10162 05:54:00.610453
10163 05:54:00.873371 00b80000 ################################################################
10164 05:54:00.873516
10165 05:54:01.146435 00c00000 ################################################################
10166 05:54:01.146584
10167 05:54:01.418069 00c80000 ################################################################
10168 05:54:01.418230
10169 05:54:01.685053 00d00000 ################################################################
10170 05:54:01.685204
10171 05:54:01.945972 00d80000 ################################################################
10172 05:54:01.946133
10173 05:54:02.210476 00e00000 ################################################################
10174 05:54:02.210628
10175 05:54:02.458717 00e80000 ################################################################
10176 05:54:02.458866
10177 05:54:02.731704 00f00000 ################################################################
10178 05:54:02.731857
10179 05:54:03.014364 00f80000 ################################################################
10180 05:54:03.014508
10181 05:54:03.280595 01000000 ################################################################
10182 05:54:03.280744
10183 05:54:03.576538 01080000 ################################################################
10184 05:54:03.576687
10185 05:54:03.861860 01100000 ################################################################
10186 05:54:03.862020
10187 05:54:04.147913 01180000 ################################################################
10188 05:54:04.148053
10189 05:54:04.444782 01200000 ################################################################
10190 05:54:04.444921
10191 05:54:04.737239 01280000 ################################################################
10192 05:54:04.737402
10193 05:54:05.037002 01300000 ################################################################
10194 05:54:05.037145
10195 05:54:05.329994 01380000 ################################################################
10196 05:54:05.330133
10197 05:54:05.619792 01400000 ################################################################
10198 05:54:05.619928
10199 05:54:05.905812 01480000 ################################################################
10200 05:54:05.905953
10201 05:54:06.202514 01500000 ################################################################
10202 05:54:06.202657
10203 05:54:06.499479 01580000 ################################################################
10204 05:54:06.499620
10205 05:54:06.791779 01600000 ################################################################
10206 05:54:06.791913
10207 05:54:07.083186 01680000 ################################################################
10208 05:54:07.083322
10209 05:54:07.333257 01700000 ################################################################
10210 05:54:07.333388
10211 05:54:07.602117 01780000 ################################################################
10212 05:54:07.602253
10213 05:54:07.953545 01800000 ################################################################
10214 05:54:07.953672
10215 05:54:08.245226 01880000 ################################################################
10216 05:54:08.245373
10217 05:54:08.540651 01900000 ################################################################
10218 05:54:08.540785
10219 05:54:08.830040 01980000 ################################################################
10220 05:54:08.830172
10221 05:54:09.232940 01a00000 ################################################################
10222 05:54:09.233504
10223 05:54:09.627007 01a80000 ################################################################
10224 05:54:09.627622
10225 05:54:10.005782 01b00000 ################################################################
10226 05:54:10.006312
10227 05:54:10.379873 01b80000 ############################################################## done.
10228 05:54:10.380427
10229 05:54:10.383536 The bootfile was 29335710 bytes long.
10230 05:54:10.384018
10231 05:54:10.386716 Sending tftp read request... done.
10232 05:54:10.387214
10233 05:54:10.387593 Waiting for the transfer...
10234 05:54:10.387975
10235 05:54:10.390104 00000000 # done.
10236 05:54:10.390594
10237 05:54:10.397032 Command line loaded dynamically from TFTP file: 12379433/tftp-deploy-cd2_bfbv/kernel/cmdline
10238 05:54:10.397661
10239 05:54:10.420431 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12379433/extract-nfsrootfs-cgiogds6,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10240 05:54:10.421034
10241 05:54:10.421421 Loading FIT.
10242 05:54:10.421773
10243 05:54:10.423309 Image ramdisk-1 has 17804565 bytes.
10244 05:54:10.423786
10245 05:54:10.427061 Image fdt-1 has 47278 bytes.
10246 05:54:10.427644
10247 05:54:10.430272 Image kernel-1 has 11481830 bytes.
10248 05:54:10.430749
10249 05:54:10.440135 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10250 05:54:10.440720
10251 05:54:10.457062 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10252 05:54:10.457657
10253 05:54:10.462996 Choosing best match conf-1 for compat google,spherion-rev2.
10254 05:54:10.463480
10255 05:54:10.470612 Connected to device vid:did:rid of 1ae0:0028:00
10256 05:54:10.477710
10257 05:54:10.480676 tpm_get_response: command 0x17b, return code 0x0
10258 05:54:10.481157
10259 05:54:10.486947 ec_init: CrosEC protocol v3 supported (256, 248)
10260 05:54:10.487572
10261 05:54:10.490523 tpm_cleanup: add release locality here.
10262 05:54:10.491005
10263 05:54:10.494209 Shutting down all USB controllers.
10264 05:54:10.494689
10265 05:54:10.497178 Removing current net device
10266 05:54:10.497655
10267 05:54:10.500340 Exiting depthcharge with code 4 at timestamp: 54785671
10268 05:54:10.500819
10269 05:54:10.504090 LZMA decompressing kernel-1 to 0x821a6718
10270 05:54:10.507472
10271 05:54:10.510610 LZMA decompressing kernel-1 to 0x40000000
10272 05:54:11.946778
10273 05:54:11.947330 jumping to kernel
10274 05:54:11.949178 end: 2.2.4 bootloader-commands (duration 00:00:27) [common]
10275 05:54:11.949727 start: 2.2.5 auto-login-action (timeout 00:03:58) [common]
10276 05:54:11.950179 Setting prompt string to ['Linux version [0-9]']
10277 05:54:11.950600 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10278 05:54:11.951003 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10279 05:54:12.029387
10280 05:54:12.033090 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10281 05:54:12.036387 start: 2.2.5.1 login-action (timeout 00:03:58) [common]
10282 05:54:12.036911 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10283 05:54:12.037320 Setting prompt string to []
10284 05:54:12.037742 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10285 05:54:12.038199 Using line separator: #'\n'#
10286 05:54:12.038553 No login prompt set.
10287 05:54:12.038912 Parsing kernel messages
10288 05:54:12.039328 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10289 05:54:12.039906 [login-action] Waiting for messages, (timeout 00:03:58)
10290 05:54:12.055794 [ 0.000000] Linux version 6.1.67-cip12 (KernelCI@build-j59664-arm64-gcc-10-defconfig-arm64-chromebook-fgc24) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023
10291 05:54:12.059316 [ 0.000000] random: crng init done
10292 05:54:12.065972 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10293 05:54:12.066536 [ 0.000000] efi: UEFI not found.
10294 05:54:12.075932 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10295 05:54:12.082438 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10296 05:54:12.092671 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10297 05:54:12.102614 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10298 05:54:12.109285 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10299 05:54:12.112384 [ 0.000000] printk: bootconsole [mtk8250] enabled
10300 05:54:12.121098 [ 0.000000] NUMA: No NUMA configuration found
10301 05:54:12.127868 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10302 05:54:12.134395 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10303 05:54:12.135116 [ 0.000000] Zone ranges:
10304 05:54:12.140717 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10305 05:54:12.144277 [ 0.000000] DMA32 empty
10306 05:54:12.150785 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10307 05:54:12.154358 [ 0.000000] Movable zone start for each node
10308 05:54:12.157670 [ 0.000000] Early memory node ranges
10309 05:54:12.164235 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10310 05:54:12.170710 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10311 05:54:12.177482 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10312 05:54:12.184322 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10313 05:54:12.190515 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10314 05:54:12.197158 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10315 05:54:12.253712 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10316 05:54:12.260312 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10317 05:54:12.267252 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10318 05:54:12.270746 [ 0.000000] psci: probing for conduit method from DT.
10319 05:54:12.276991 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10320 05:54:12.280548 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10321 05:54:12.286728 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10322 05:54:12.290288 [ 0.000000] psci: SMC Calling Convention v1.2
10323 05:54:12.297077 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10324 05:54:12.300214 [ 0.000000] Detected VIPT I-cache on CPU0
10325 05:54:12.306860 [ 0.000000] CPU features: detected: GIC system register CPU interface
10326 05:54:12.313352 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10327 05:54:12.319789 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10328 05:54:12.326730 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10329 05:54:12.332973 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10330 05:54:12.339780 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10331 05:54:12.346300 [ 0.000000] alternatives: applying boot alternatives
10332 05:54:12.353150 [ 0.000000] Fallback order for Node 0: 0
10333 05:54:12.359455 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10334 05:54:12.363280 [ 0.000000] Policy zone: Normal
10335 05:54:12.386230 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12379433/extract-nfsrootfs-cgiogds6,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10336 05:54:12.395555 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10337 05:54:12.406236 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10338 05:54:12.416113 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10339 05:54:12.422884 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10340 05:54:12.425926 <6>[ 0.000000] software IO TLB: area num 8.
10341 05:54:12.483002 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10342 05:54:12.632122 <6>[ 0.000000] Memory: 7951332K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 401436K reserved, 32768K cma-reserved)
10343 05:54:12.639054 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10344 05:54:12.645526 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10345 05:54:12.648935 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10346 05:54:12.655817 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10347 05:54:12.662171 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10348 05:54:12.665759 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10349 05:54:12.675511 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10350 05:54:12.681952 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10351 05:54:12.685495 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10352 05:54:12.693271 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10353 05:54:12.696679 <6>[ 0.000000] GICv3: 608 SPIs implemented
10354 05:54:12.702994 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10355 05:54:12.706656 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10356 05:54:12.709887 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10357 05:54:12.720054 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10358 05:54:12.729829 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10359 05:54:12.743128 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10360 05:54:12.749699 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10361 05:54:12.758708 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10362 05:54:12.771792 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10363 05:54:12.778306 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10364 05:54:12.784954 <6>[ 0.009188] Console: colour dummy device 80x25
10365 05:54:12.795034 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10366 05:54:12.798658 <6>[ 0.024355] pid_max: default: 32768 minimum: 301
10367 05:54:12.805344 <6>[ 0.029226] LSM: Security Framework initializing
10368 05:54:12.812026 <6>[ 0.034194] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10369 05:54:12.822345 <6>[ 0.042056] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10370 05:54:12.828801 <6>[ 0.051466] cblist_init_generic: Setting adjustable number of callback queues.
10371 05:54:12.835290 <6>[ 0.058909] cblist_init_generic: Setting shift to 3 and lim to 1.
10372 05:54:12.845350 <6>[ 0.065246] cblist_init_generic: Setting adjustable number of callback queues.
10373 05:54:12.848359 <6>[ 0.072674] cblist_init_generic: Setting shift to 3 and lim to 1.
10374 05:54:12.855059 <6>[ 0.079073] rcu: Hierarchical SRCU implementation.
10375 05:54:12.861889 <6>[ 0.084088] rcu: Max phase no-delay instances is 1000.
10376 05:54:12.868176 <6>[ 0.091108] EFI services will not be available.
10377 05:54:12.871650 <6>[ 0.096090] smp: Bringing up secondary CPUs ...
10378 05:54:12.879560 <6>[ 0.101166] Detected VIPT I-cache on CPU1
10379 05:54:12.886268 <6>[ 0.101235] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10380 05:54:12.892895 <6>[ 0.101265] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10381 05:54:12.896381 <6>[ 0.101597] Detected VIPT I-cache on CPU2
10382 05:54:12.902793 <6>[ 0.101646] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10383 05:54:12.912832 <6>[ 0.101662] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10384 05:54:12.916310 <6>[ 0.101918] Detected VIPT I-cache on CPU3
10385 05:54:12.922967 <6>[ 0.101965] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10386 05:54:12.929389 <6>[ 0.101979] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10387 05:54:12.933097 <6>[ 0.102281] CPU features: detected: Spectre-v4
10388 05:54:12.939422 <6>[ 0.102288] CPU features: detected: Spectre-BHB
10389 05:54:12.942501 <6>[ 0.102293] Detected PIPT I-cache on CPU4
10390 05:54:12.949353 <6>[ 0.102350] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10391 05:54:12.956128 <6>[ 0.102367] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10392 05:54:12.962453 <6>[ 0.102657] Detected PIPT I-cache on CPU5
10393 05:54:12.968914 <6>[ 0.102721] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10394 05:54:12.976449 <6>[ 0.102737] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10395 05:54:12.979144 <6>[ 0.103018] Detected PIPT I-cache on CPU6
10396 05:54:12.985643 <6>[ 0.103082] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10397 05:54:12.992307 <6>[ 0.103098] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10398 05:54:12.999029 <6>[ 0.103396] Detected PIPT I-cache on CPU7
10399 05:54:13.005507 <6>[ 0.103461] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10400 05:54:13.012400 <6>[ 0.103479] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10401 05:54:13.015957 <6>[ 0.103526] smp: Brought up 1 node, 8 CPUs
10402 05:54:13.022185 <6>[ 0.244964] SMP: Total of 8 processors activated.
10403 05:54:13.025488 <6>[ 0.249885] CPU features: detected: 32-bit EL0 Support
10404 05:54:13.035760 <6>[ 0.255248] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10405 05:54:13.042111 <6>[ 0.264049] CPU features: detected: Common not Private translations
10406 05:54:13.049231 <6>[ 0.270525] CPU features: detected: CRC32 instructions
10407 05:54:13.052199 <6>[ 0.275876] CPU features: detected: RCpc load-acquire (LDAPR)
10408 05:54:13.058850 <6>[ 0.281836] CPU features: detected: LSE atomic instructions
10409 05:54:13.065264 <6>[ 0.287617] CPU features: detected: Privileged Access Never
10410 05:54:13.072000 <6>[ 0.293433] CPU features: detected: RAS Extension Support
10411 05:54:13.078121 <6>[ 0.299042] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10412 05:54:13.081853 <6>[ 0.306263] CPU: All CPU(s) started at EL2
10413 05:54:13.088112 <6>[ 0.310579] alternatives: applying system-wide alternatives
10414 05:54:13.097556 <6>[ 0.321288] devtmpfs: initialized
10415 05:54:13.113351 <6>[ 0.330274] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10416 05:54:13.119899 <6>[ 0.340236] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10417 05:54:13.126393 <6>[ 0.348486] pinctrl core: initialized pinctrl subsystem
10418 05:54:13.129418 <6>[ 0.355168] DMI not present or invalid.
10419 05:54:13.136185 <6>[ 0.359579] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10420 05:54:13.146327 <6>[ 0.366456] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10421 05:54:13.152953 <6>[ 0.374031] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10422 05:54:13.162675 <6>[ 0.382263] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10423 05:54:13.166402 <6>[ 0.390505] audit: initializing netlink subsys (disabled)
10424 05:54:13.175886 <5>[ 0.396200] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10425 05:54:13.182810 <6>[ 0.396916] thermal_sys: Registered thermal governor 'step_wise'
10426 05:54:13.189620 <6>[ 0.404169] thermal_sys: Registered thermal governor 'power_allocator'
10427 05:54:13.192880 <6>[ 0.410427] cpuidle: using governor menu
10428 05:54:13.199574 <6>[ 0.421388] NET: Registered PF_QIPCRTR protocol family
10429 05:54:13.205755 <6>[ 0.426871] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10430 05:54:13.209062 <6>[ 0.433969] ASID allocator initialised with 32768 entries
10431 05:54:13.216518 <6>[ 0.440544] Serial: AMBA PL011 UART driver
10432 05:54:13.225484 <4>[ 0.449361] Trying to register duplicate clock ID: 134
10433 05:54:13.281795 <6>[ 0.508964] KASLR enabled
10434 05:54:13.296184 <6>[ 0.516739] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10435 05:54:13.302770 <6>[ 0.523753] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10436 05:54:13.309171 <6>[ 0.530238] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10437 05:54:13.315829 <6>[ 0.537239] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10438 05:54:13.322796 <6>[ 0.543722] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10439 05:54:13.329108 <6>[ 0.550729] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10440 05:54:13.335886 <6>[ 0.557213] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10441 05:54:13.342539 <6>[ 0.564214] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10442 05:54:13.345923 <6>[ 0.571710] ACPI: Interpreter disabled.
10443 05:54:13.354076 <6>[ 0.578121] iommu: Default domain type: Translated
10444 05:54:13.360874 <6>[ 0.583235] iommu: DMA domain TLB invalidation policy: strict mode
10445 05:54:13.363966 <5>[ 0.589891] SCSI subsystem initialized
10446 05:54:13.370926 <6>[ 0.594052] usbcore: registered new interface driver usbfs
10447 05:54:13.377483 <6>[ 0.599785] usbcore: registered new interface driver hub
10448 05:54:13.380687 <6>[ 0.605337] usbcore: registered new device driver usb
10449 05:54:13.387482 <6>[ 0.611432] pps_core: LinuxPPS API ver. 1 registered
10450 05:54:13.397122 <6>[ 0.616627] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10451 05:54:13.400644 <6>[ 0.625977] PTP clock support registered
10452 05:54:13.403736 <6>[ 0.630221] EDAC MC: Ver: 3.0.0
10453 05:54:13.411549 <6>[ 0.635367] FPGA manager framework
10454 05:54:13.417901 <6>[ 0.639046] Advanced Linux Sound Architecture Driver Initialized.
10455 05:54:13.421494 <6>[ 0.645823] vgaarb: loaded
10456 05:54:13.427715 <6>[ 0.648988] clocksource: Switched to clocksource arch_sys_counter
10457 05:54:13.431210 <5>[ 0.655416] VFS: Disk quotas dquot_6.6.0
10458 05:54:13.437983 <6>[ 0.659601] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10459 05:54:13.441025 <6>[ 0.666790] pnp: PnP ACPI: disabled
10460 05:54:13.449556 <6>[ 0.673497] NET: Registered PF_INET protocol family
10461 05:54:13.459251 <6>[ 0.679077] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10462 05:54:13.470461 <6>[ 0.691379] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10463 05:54:13.480594 <6>[ 0.700193] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10464 05:54:13.486924 <6>[ 0.708165] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10465 05:54:13.493665 <6>[ 0.716869] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10466 05:54:13.505859 <6>[ 0.726621] TCP: Hash tables configured (established 65536 bind 65536)
10467 05:54:13.512771 <6>[ 0.733481] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10468 05:54:13.519143 <6>[ 0.740676] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10469 05:54:13.525829 <6>[ 0.748376] NET: Registered PF_UNIX/PF_LOCAL protocol family
10470 05:54:13.532546 <6>[ 0.754532] RPC: Registered named UNIX socket transport module.
10471 05:54:13.536047 <6>[ 0.760687] RPC: Registered udp transport module.
10472 05:54:13.542199 <6>[ 0.765621] RPC: Registered tcp transport module.
10473 05:54:13.549221 <6>[ 0.770555] RPC: Registered tcp NFSv4.1 backchannel transport module.
10474 05:54:13.552464 <6>[ 0.777221] PCI: CLS 0 bytes, default 64
10475 05:54:13.555335 <6>[ 0.781579] Unpacking initramfs...
10476 05:54:13.580063 <6>[ 0.801072] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10477 05:54:13.589920 <6>[ 0.809715] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10478 05:54:13.593420 <6>[ 0.818563] kvm [1]: IPA Size Limit: 40 bits
10479 05:54:13.600345 <6>[ 0.823090] kvm [1]: GICv3: no GICV resource entry
10480 05:54:13.603221 <6>[ 0.828112] kvm [1]: disabling GICv2 emulation
10481 05:54:13.610123 <6>[ 0.832797] kvm [1]: GIC system register CPU interface enabled
10482 05:54:13.613490 <6>[ 0.838959] kvm [1]: vgic interrupt IRQ18
10483 05:54:13.620269 <6>[ 0.843306] kvm [1]: VHE mode initialized successfully
10484 05:54:13.626898 <5>[ 0.849775] Initialise system trusted keyrings
10485 05:54:13.633103 <6>[ 0.854639] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10486 05:54:13.640680 <6>[ 0.864669] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10487 05:54:13.647157 <5>[ 0.871046] NFS: Registering the id_resolver key type
10488 05:54:13.650639 <5>[ 0.876350] Key type id_resolver registered
10489 05:54:13.656910 <5>[ 0.880765] Key type id_legacy registered
10490 05:54:13.663786 <6>[ 0.885041] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10491 05:54:13.670012 <6>[ 0.891965] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10492 05:54:13.676972 <6>[ 0.899680] 9p: Installing v9fs 9p2000 file system support
10493 05:54:13.712566 <5>[ 0.936819] Key type asymmetric registered
10494 05:54:13.716157 <5>[ 0.941152] Asymmetric key parser 'x509' registered
10495 05:54:13.726132 <6>[ 0.946298] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10496 05:54:13.729406 <6>[ 0.953911] io scheduler mq-deadline registered
10497 05:54:13.732470 <6>[ 0.958692] io scheduler kyber registered
10498 05:54:13.751587 <6>[ 0.975679] EINJ: ACPI disabled.
10499 05:54:13.784214 <4>[ 1.001850] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10500 05:54:13.793995 <4>[ 1.012498] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10501 05:54:13.809402 <6>[ 1.033563] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10502 05:54:13.817401 <6>[ 1.041663] printk: console [ttyS0] disabled
10503 05:54:13.845629 <6>[ 1.066305] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10504 05:54:13.852070 <6>[ 1.075780] printk: console [ttyS0] enabled
10505 05:54:13.855650 <6>[ 1.075780] printk: console [ttyS0] enabled
10506 05:54:13.862202 <6>[ 1.084679] printk: bootconsole [mtk8250] disabled
10507 05:54:13.866020 <6>[ 1.084679] printk: bootconsole [mtk8250] disabled
10508 05:54:13.872819 <6>[ 1.095974] SuperH (H)SCI(F) driver initialized
10509 05:54:13.875734 <6>[ 1.101267] msm_serial: driver initialized
10510 05:54:13.889700 <6>[ 1.110275] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10511 05:54:13.899675 <6>[ 1.118824] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10512 05:54:13.906497 <6>[ 1.127367] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10513 05:54:13.916297 <6>[ 1.135997] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10514 05:54:13.926442 <6>[ 1.144705] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10515 05:54:13.932619 <6>[ 1.153429] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10516 05:54:13.943101 <6>[ 1.161970] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10517 05:54:13.949414 <6>[ 1.170794] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10518 05:54:13.959191 <6>[ 1.179338] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10519 05:54:13.971399 <6>[ 1.195071] loop: module loaded
10520 05:54:13.977702 <6>[ 1.201061] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10521 05:54:14.000777 <4>[ 1.224601] mtk-pmic-keys: Failed to locate of_node [id: -1]
10522 05:54:14.007936 <6>[ 1.231718] megasas: 07.719.03.00-rc1
10523 05:54:14.017380 <6>[ 1.241499] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10524 05:54:14.024872 <6>[ 1.248387] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10525 05:54:14.041018 <6>[ 1.264784] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10526 05:54:14.097323 <6>[ 1.314778] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10527 05:54:14.299334 <6>[ 1.523314] Freeing initrd memory: 17384K
10528 05:54:14.309769 <6>[ 1.533763] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10529 05:54:14.320641 <6>[ 1.544629] tun: Universal TUN/TAP device driver, 1.6
10530 05:54:14.323842 <6>[ 1.550692] thunder_xcv, ver 1.0
10531 05:54:14.327507 <6>[ 1.554197] thunder_bgx, ver 1.0
10532 05:54:14.330710 <6>[ 1.557694] nicpf, ver 1.0
10533 05:54:14.341029 <6>[ 1.561718] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10534 05:54:14.344600 <6>[ 1.569195] hns3: Copyright (c) 2017 Huawei Corporation.
10535 05:54:14.347548 <6>[ 1.574785] hclge is initializing
10536 05:54:14.354369 <6>[ 1.578370] e1000: Intel(R) PRO/1000 Network Driver
10537 05:54:14.361217 <6>[ 1.583500] e1000: Copyright (c) 1999-2006 Intel Corporation.
10538 05:54:14.364493 <6>[ 1.589514] e1000e: Intel(R) PRO/1000 Network Driver
10539 05:54:14.371267 <6>[ 1.594730] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10540 05:54:14.377791 <6>[ 1.600916] igb: Intel(R) Gigabit Ethernet Network Driver
10541 05:54:14.384689 <6>[ 1.606566] igb: Copyright (c) 2007-2014 Intel Corporation.
10542 05:54:14.390980 <6>[ 1.612402] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10543 05:54:14.397405 <6>[ 1.618919] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10544 05:54:14.401063 <6>[ 1.625388] sky2: driver version 1.30
10545 05:54:14.407481 <6>[ 1.630386] VFIO - User Level meta-driver version: 0.3
10546 05:54:14.414370 <6>[ 1.638627] usbcore: registered new interface driver usb-storage
10547 05:54:14.420965 <6>[ 1.645074] usbcore: registered new device driver onboard-usb-hub
10548 05:54:14.430146 <6>[ 1.654243] mt6397-rtc mt6359-rtc: registered as rtc0
10549 05:54:14.439891 <6>[ 1.659708] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-25T05:53:32 UTC (1703483612)
10550 05:54:14.443179 <6>[ 1.669284] i2c_dev: i2c /dev entries driver
10551 05:54:14.460349 <6>[ 1.681048] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10552 05:54:14.480438 <6>[ 1.704039] cpu cpu0: EM: created perf domain
10553 05:54:14.483422 <6>[ 1.708954] cpu cpu4: EM: created perf domain
10554 05:54:14.490923 <6>[ 1.714527] sdhci: Secure Digital Host Controller Interface driver
10555 05:54:14.497372 <6>[ 1.720959] sdhci: Copyright(c) Pierre Ossman
10556 05:54:14.504217 <6>[ 1.725917] Synopsys Designware Multimedia Card Interface Driver
10557 05:54:14.511232 <6>[ 1.732548] sdhci-pltfm: SDHCI platform and OF driver helper
10558 05:54:14.513981 <6>[ 1.732640] mmc0: CQHCI version 5.10
10559 05:54:14.520850 <6>[ 1.742615] ledtrig-cpu: registered to indicate activity on CPUs
10560 05:54:14.527511 <6>[ 1.749611] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10561 05:54:14.533900 <6>[ 1.756659] usbcore: registered new interface driver usbhid
10562 05:54:14.537338 <6>[ 1.762480] usbhid: USB HID core driver
10563 05:54:14.543985 <6>[ 1.766687] spi_master spi0: will run message pump with realtime priority
10564 05:54:14.588351 <6>[ 1.805295] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10565 05:54:14.607294 <6>[ 1.821229] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10566 05:54:14.610880 <6>[ 1.834834] mmc0: Command Queue Engine enabled
10567 05:54:14.617677 <6>[ 1.839609] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10568 05:54:14.624618 <6>[ 1.846544] cros-ec-spi spi0.0: Chrome EC device registered
10569 05:54:14.627296 <6>[ 1.846911] mmcblk0: mmc0:0001 DA4128 116 GiB
10570 05:54:14.637934 <6>[ 1.861869] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10571 05:54:14.645116 <6>[ 1.869128] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10572 05:54:14.651999 <6>[ 1.874973] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10573 05:54:14.658518 <6>[ 1.880843] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10574 05:54:14.668686 <6>[ 1.886031] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10575 05:54:14.675365 <6>[ 1.897948] NET: Registered PF_PACKET protocol family
10576 05:54:14.678531 <6>[ 1.903345] 9pnet: Installing 9P2000 support
10577 05:54:14.681840 <5>[ 1.907914] Key type dns_resolver registered
10578 05:54:14.688971 <6>[ 1.912883] registered taskstats version 1
10579 05:54:14.692266 <5>[ 1.917270] Loading compiled-in X.509 certificates
10580 05:54:14.724640 <4>[ 1.941863] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10581 05:54:14.734837 <4>[ 1.952649] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10582 05:54:14.741085 <3>[ 1.963201] debugfs: File 'uA_load' in directory '/' already present!
10583 05:54:14.747969 <3>[ 1.969908] debugfs: File 'min_uV' in directory '/' already present!
10584 05:54:14.754599 <3>[ 1.976519] debugfs: File 'max_uV' in directory '/' already present!
10585 05:54:14.761128 <3>[ 1.983129] debugfs: File 'constraint_flags' in directory '/' already present!
10586 05:54:14.771760 <3>[ 1.992485] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10587 05:54:14.781855 <6>[ 2.005636] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10588 05:54:14.788490 <6>[ 2.012405] xhci-mtk 11200000.usb: xHCI Host Controller
10589 05:54:14.795142 <6>[ 2.017930] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10590 05:54:14.804821 <6>[ 2.025766] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10591 05:54:14.811510 <6>[ 2.035186] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10592 05:54:14.818237 <6>[ 2.041256] xhci-mtk 11200000.usb: xHCI Host Controller
10593 05:54:14.824740 <6>[ 2.046732] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10594 05:54:14.831478 <6>[ 2.054376] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10595 05:54:14.837924 <6>[ 2.062196] hub 1-0:1.0: USB hub found
10596 05:54:14.841255 <6>[ 2.066216] hub 1-0:1.0: 1 port detected
10597 05:54:14.847988 <6>[ 2.070488] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10598 05:54:14.855066 <6>[ 2.079222] hub 2-0:1.0: USB hub found
10599 05:54:14.857960 <6>[ 2.083244] hub 2-0:1.0: 1 port detected
10600 05:54:14.867030 <6>[ 2.091245] mtk-msdc 11f70000.mmc: Got CD GPIO
10601 05:54:14.877309 <6>[ 2.098029] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10602 05:54:14.884065 <6>[ 2.106050] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10603 05:54:14.893870 <4>[ 2.113954] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10604 05:54:14.904250 <6>[ 2.123482] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10605 05:54:14.910771 <6>[ 2.131559] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10606 05:54:14.917566 <6>[ 2.139672] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10607 05:54:14.927702 <6>[ 2.147606] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10608 05:54:14.933984 <6>[ 2.155423] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10609 05:54:14.944457 <6>[ 2.163240] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10610 05:54:14.953851 <6>[ 2.173742] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10611 05:54:14.960622 <6>[ 2.182124] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10612 05:54:14.970701 <6>[ 2.190468] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10613 05:54:14.977068 <6>[ 2.198809] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10614 05:54:14.987531 <6>[ 2.207148] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10615 05:54:14.993690 <6>[ 2.215486] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10616 05:54:15.003821 <6>[ 2.223824] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10617 05:54:15.010829 <6>[ 2.232164] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10618 05:54:15.020846 <6>[ 2.240502] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10619 05:54:15.027568 <6>[ 2.248841] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10620 05:54:15.037487 <6>[ 2.257189] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10621 05:54:15.043854 <6>[ 2.265528] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10622 05:54:15.053662 <6>[ 2.273867] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10623 05:54:15.060240 <6>[ 2.282205] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10624 05:54:15.070318 <6>[ 2.290543] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10625 05:54:15.077091 <6>[ 2.299335] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10626 05:54:15.084179 <6>[ 2.306509] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10627 05:54:15.090487 <6>[ 2.313268] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10628 05:54:15.097115 <6>[ 2.320025] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10629 05:54:15.103568 <6>[ 2.326959] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10630 05:54:15.113466 <6>[ 2.333845] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10631 05:54:15.123420 <6>[ 2.342975] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10632 05:54:15.133409 <6>[ 2.352098] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10633 05:54:15.143259 <6>[ 2.361391] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10634 05:54:15.149868 <6>[ 2.370860] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10635 05:54:15.159917 <6>[ 2.380328] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10636 05:54:15.169842 <6>[ 2.389448] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10637 05:54:15.179495 <6>[ 2.398915] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10638 05:54:15.189198 <6>[ 2.408033] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10639 05:54:15.199583 <6>[ 2.417326] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10640 05:54:15.209066 <6>[ 2.427486] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10641 05:54:15.219086 <6>[ 2.439077] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10642 05:54:15.225696 <6>[ 2.448737] Trying to probe devices needed for running init ...
10643 05:54:15.248537 <6>[ 2.469262] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10644 05:54:15.276737 <6>[ 2.500800] hub 2-1:1.0: USB hub found
10645 05:54:15.280183 <6>[ 2.505287] hub 2-1:1.0: 3 ports detected
10646 05:54:15.288527 <6>[ 2.512645] hub 2-1:1.0: USB hub found
10647 05:54:15.291863 <6>[ 2.516961] hub 2-1:1.0: 3 ports detected
10648 05:54:15.400244 <6>[ 2.621204] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10649 05:54:15.555191 <6>[ 2.779452] hub 1-1:1.0: USB hub found
10650 05:54:15.558550 <6>[ 2.783904] hub 1-1:1.0: 4 ports detected
10651 05:54:15.568077 <6>[ 2.791979] hub 1-1:1.0: USB hub found
10652 05:54:15.571368 <6>[ 2.796433] hub 1-1:1.0: 4 ports detected
10653 05:54:15.640655 <6>[ 2.861521] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10654 05:54:15.892380 <6>[ 3.113301] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10655 05:54:16.025045 <6>[ 3.249121] hub 1-1.4:1.0: USB hub found
10656 05:54:16.028413 <6>[ 3.253785] hub 1-1.4:1.0: 2 ports detected
10657 05:54:16.038426 <6>[ 3.262329] hub 1-1.4:1.0: USB hub found
10658 05:54:16.041279 <6>[ 3.266933] hub 1-1.4:1.0: 2 ports detected
10659 05:54:16.340530 <6>[ 3.561298] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10660 05:54:16.532317 <6>[ 3.753298] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10661 05:54:27.504893 <6>[ 14.734270] ALSA device list:
10662 05:54:27.511557 <6>[ 14.737564] No soundcards found.
10663 05:54:27.519704 <6>[ 14.745497] Freeing unused kernel memory: 8448K
10664 05:54:27.522670 <6>[ 14.750581] Run /init as init process
10665 05:54:27.533948 Loading, please wait...
10666 05:54:27.554884 Starting version 247.3-7+deb11u2
10667 05:54:27.782811 <6>[ 15.005192] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10668 05:54:27.793837 <6>[ 15.019805] remoteproc remoteproc0: scp is available
10669 05:54:27.800387 <6>[ 15.025292] remoteproc remoteproc0: powering up scp
10670 05:54:27.807003 <6>[ 15.030434] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10671 05:54:27.813928 <6>[ 15.038898] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10672 05:54:27.831509 <6>[ 15.054062] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10673 05:54:27.837955 <6>[ 15.054509] usbcore: registered new interface driver r8152
10674 05:54:27.844860 <6>[ 15.062174] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10675 05:54:27.851325 <6>[ 15.069618] mc: Linux media interface: v0.10
10676 05:54:27.858035 <6>[ 15.076245] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10677 05:54:27.867880 <3>[ 15.076873] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 05:54:27.874565 <3>[ 15.076888] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 05:54:27.884264 <3>[ 15.076897] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 05:54:27.891358 <3>[ 15.086791] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 05:54:27.897894 <3>[ 15.121963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 05:54:27.904127 <6>[ 15.124230] usbcore: registered new interface driver cdc_ether
10683 05:54:27.911208 <6>[ 15.127027] videodev: Linux video capture interface: v2.00
10684 05:54:27.917155 <3>[ 15.136395] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 05:54:27.927503 <6>[ 15.137482] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10686 05:54:27.933828 <4>[ 15.141687] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10687 05:54:27.940610 <4>[ 15.142010] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10688 05:54:27.950415 <3>[ 15.149999] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 05:54:27.956823 <3>[ 15.150005] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 05:54:27.967040 <3>[ 15.150082] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 05:54:27.973594 <6>[ 15.165346] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10692 05:54:27.980330 <6>[ 15.169792] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10693 05:54:27.987124 <6>[ 15.172423] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10694 05:54:27.996876 <3>[ 15.174550] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 05:54:28.003586 <3>[ 15.174559] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 05:54:28.013255 <3>[ 15.174562] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 05:54:28.019808 <3>[ 15.174812] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 05:54:28.030986 <3>[ 15.174822] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 05:54:28.037309 <3>[ 15.174826] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 05:54:28.043696 <3>[ 15.174831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 05:54:28.054115 <3>[ 15.174835] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 05:54:28.060479 <3>[ 15.174860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 05:54:28.070770 <6>[ 15.176061] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10704 05:54:28.077137 <6>[ 15.179149] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10705 05:54:28.087291 <4>[ 15.182082] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10706 05:54:28.090220 <4>[ 15.182082] Fallback method does not support PEC.
10707 05:54:28.097097 <6>[ 15.188577] remoteproc remoteproc0: remote processor scp is now up
10708 05:54:28.103635 <6>[ 15.211054] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10709 05:54:28.113749 <4>[ 15.222622] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10710 05:54:28.120344 <6>[ 15.227631] pci_bus 0000:00: root bus resource [bus 00-ff]
10711 05:54:28.126789 <4>[ 15.235618] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10712 05:54:28.136612 <6>[ 15.237824] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10713 05:54:28.146756 <6>[ 15.238247] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10714 05:54:28.153206 <6>[ 15.243657] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10715 05:54:28.163507 <3>[ 15.264207] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10716 05:54:28.173181 <6>[ 15.268724] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10717 05:54:28.183137 <6>[ 15.368922] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10718 05:54:28.186659 <6>[ 15.377869] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10719 05:54:28.193926 <6>[ 15.384906] r8152 2-1.3:1.0 eth0: v1.12.13
10720 05:54:28.200288 <6>[ 15.393637] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10721 05:54:28.203744 <6>[ 15.419807] Bluetooth: Core ver 2.22
10722 05:54:28.210446 <6>[ 15.419840] usbcore: registered new interface driver r8153_ecm
10723 05:54:28.213778 <6>[ 15.423501] pci 0000:00:00.0: supports D1 D2
10724 05:54:28.223708 <3>[ 15.426612] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10725 05:54:28.230237 <6>[ 15.431015] NET: Registered PF_BLUETOOTH protocol family
10726 05:54:28.233673 <6>[ 15.432700] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10727 05:54:28.240033 <6>[ 15.434723] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10728 05:54:28.249855 <6>[ 15.435913] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10729 05:54:28.256725 <6>[ 15.440814] Bluetooth: HCI device and connection manager initialized
10730 05:54:28.260005 <6>[ 15.440836] Bluetooth: HCI socket layer initialized
10731 05:54:28.266829 <6>[ 15.445484] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10732 05:54:28.273275 <6>[ 15.454118] Bluetooth: L2CAP socket layer initialized
10733 05:54:28.279823 <6>[ 15.455297] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10734 05:54:28.292954 <6>[ 15.456421] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10735 05:54:28.299717 <6>[ 15.456528] usbcore: registered new interface driver uvcvideo
10736 05:54:28.305924 <6>[ 15.459697] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10737 05:54:28.312717 <6>[ 15.465789] Bluetooth: SCO socket layer initialized
10738 05:54:28.319473 <6>[ 15.472628] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10739 05:54:28.326098 <6>[ 15.493626] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10740 05:54:28.332913 <6>[ 15.498873] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10741 05:54:28.339482 <6>[ 15.530094] usbcore: registered new interface driver btusb
10742 05:54:28.349246 <4>[ 15.531075] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10743 05:54:28.355732 <3>[ 15.531090] Bluetooth: hci0: Failed to load firmware file (-2)
10744 05:54:28.359229 <3>[ 15.531096] Bluetooth: hci0: Failed to set up firmware (-2)
10745 05:54:28.372297 <4>[ 15.531102] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10746 05:54:28.375756 <6>[ 15.537197] pci 0000:01:00.0: supports D1 D2
10747 05:54:28.382311 <6>[ 15.606733] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10748 05:54:28.402632 <6>[ 15.625222] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10749 05:54:28.409099 <6>[ 15.632113] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10750 05:54:28.415627 <6>[ 15.640192] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10751 05:54:28.425710 <6>[ 15.648193] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10752 05:54:28.432084 <6>[ 15.656193] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10753 05:54:28.441933 <6>[ 15.664194] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10754 05:54:28.445489 <6>[ 15.672194] pci 0000:00:00.0: PCI bridge to [bus 01]
10755 05:54:28.455292 <6>[ 15.677409] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10756 05:54:28.462273 <6>[ 15.685528] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10757 05:54:28.468454 <6>[ 15.692327] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10758 05:54:28.475358 <6>[ 15.698994] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10759 05:54:28.497182 <5>[ 15.720060] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10760 05:54:28.519218 <5>[ 15.741725] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10761 05:54:28.525871 <4>[ 15.748672] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10762 05:54:28.532495 <6>[ 15.757580] cfg80211: failed to load regulatory.db
10763 05:54:28.586097 <6>[ 15.808750] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10764 05:54:28.592438 <6>[ 15.816419] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10765 05:54:28.616992 <6>[ 15.843235] mt7921e 0000:01:00.0: ASIC revision: 79610010
10766 05:54:28.718194 <6>[ 15.940955] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10767 05:54:28.721225 <6>[ 15.940955]
10768 05:54:28.736895 Begin: Loading essential drivers ... done.
10769 05:54:28.740133 Begin: Running /scripts/init-premount ... done.
10770 05:54:28.746499 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10771 05:54:28.756420 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10772 05:54:28.759943 Device /sys/class/net/enx00e04c722dd6 found
10773 05:54:28.760044 done.
10774 05:54:28.810327 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10775 05:54:28.985627 <6>[ 16.208394] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10776 05:54:29.830517 <6>[ 17.056758] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10777 05:54:29.864541 <6>[ 17.091032] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10778 05:54:29.933547 IP-Config: no response after 2 secs - giving up
10779 05:54:29.982143 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10780 05:54:30.010731 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:7b mtu 1500 DHCP
10781 05:54:30.711185 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10782 05:54:30.717898 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10783 05:54:30.724456 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10784 05:54:30.730886 host : mt8192-asurada-spherion-r0-cbg-1
10785 05:54:30.737828 domain : lava-rack
10786 05:54:30.740835 rootserver: 192.168.201.1 rootpath:
10787 05:54:30.744158 filename :
10788 05:54:30.821710 done.
10789 05:54:30.828304 Begin: Running /scripts/nfs-bottom ... done.
10790 05:54:30.846634 Begin: Running /scripts/init-bottom ... done.
10791 05:54:32.237393 <6>[ 19.463669] NET: Registered PF_INET6 protocol family
10792 05:54:32.244913 <6>[ 19.471433] Segment Routing with IPv6
10793 05:54:32.248347 <6>[ 19.475430] In-situ OAM (IOAM) with IPv6
10794 05:54:32.367703 <30>[ 19.574430] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10795 05:54:32.374287 <30>[ 19.598879] systemd[1]: Detected architecture arm64.
10796 05:54:32.390767
10797 05:54:32.393956 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10798 05:54:32.394089
10799 05:54:32.408746 <30>[ 19.635108] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10800 05:54:33.152682 <30>[ 20.376170] systemd[1]: Queued start job for default target Graphical Interface.
10801 05:54:33.180899 <30>[ 20.407595] systemd[1]: Created slice system-getty.slice.
10802 05:54:33.187598 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10803 05:54:33.203990 <30>[ 20.430618] systemd[1]: Created slice system-modprobe.slice.
10804 05:54:33.210812 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10805 05:54:33.228044 <30>[ 20.454500] systemd[1]: Created slice system-serial\x2dgetty.slice.
10806 05:54:33.237802 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10807 05:54:33.251717 <30>[ 20.478316] systemd[1]: Created slice User and Session Slice.
10808 05:54:33.258518 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10809 05:54:33.278977 <30>[ 20.502119] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10810 05:54:33.288953 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10811 05:54:33.306790 <30>[ 20.530011] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10812 05:54:33.313320 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10813 05:54:33.337300 <30>[ 20.557442] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10814 05:54:33.344124 <30>[ 20.569600] systemd[1]: Reached target Local Encrypted Volumes.
10815 05:54:33.350617 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10816 05:54:33.366922 <30>[ 20.593399] systemd[1]: Reached target Paths.
10817 05:54:33.370249 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10818 05:54:33.386783 <30>[ 20.613265] systemd[1]: Reached target Remote File Systems.
10819 05:54:33.393163 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10820 05:54:33.406955 <30>[ 20.633233] systemd[1]: Reached target Slices.
10821 05:54:33.410273 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10822 05:54:33.426818 <30>[ 20.653278] systemd[1]: Reached target Swap.
10823 05:54:33.429800 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10824 05:54:33.450376 <30>[ 20.673712] systemd[1]: Listening on initctl Compatibility Named Pipe.
10825 05:54:33.456944 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10826 05:54:33.463481 <30>[ 20.689628] systemd[1]: Listening on Journal Audit Socket.
10827 05:54:33.470060 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10828 05:54:33.487725 <30>[ 20.714420] systemd[1]: Listening on Journal Socket (/dev/log).
10829 05:54:33.494308 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10830 05:54:33.511197 <30>[ 20.737823] systemd[1]: Listening on Journal Socket.
10831 05:54:33.517842 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10832 05:54:33.535031 <30>[ 20.758600] systemd[1]: Listening on Network Service Netlink Socket.
10833 05:54:33.541692 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10834 05:54:33.557166 <30>[ 20.783737] systemd[1]: Listening on udev Control Socket.
10835 05:54:33.563750 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10836 05:54:33.579191 <30>[ 20.805711] systemd[1]: Listening on udev Kernel Socket.
10837 05:54:33.585552 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10838 05:54:33.635210 <30>[ 20.861827] systemd[1]: Mounting Huge Pages File System...
10839 05:54:33.642090 Mounting [0;1;39mHuge Pages File System[0m...
10840 05:54:33.657142 <30>[ 20.883563] systemd[1]: Mounting POSIX Message Queue File System...
10841 05:54:33.663702 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10842 05:54:33.682062 <30>[ 20.908482] systemd[1]: Mounting Kernel Debug File System...
10843 05:54:33.688232 Mounting [0;1;39mKernel Debug File System[0m...
10844 05:54:33.706198 <30>[ 20.929803] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10845 05:54:33.729238 <30>[ 20.952304] systemd[1]: Starting Create list of static device nodes for the current kernel...
10846 05:54:33.735631 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10847 05:54:33.755367 <30>[ 20.982231] systemd[1]: Starting Load Kernel Module configfs...
10848 05:54:33.762068 Starting [0;1;39mLoad Kernel Module configfs[0m...
10849 05:54:33.783538 <30>[ 21.010138] systemd[1]: Starting Load Kernel Module drm...
10850 05:54:33.789928 Starting [0;1;39mLoad Kernel Module drm[0m...
10851 05:54:33.807727 <30>[ 21.034165] systemd[1]: Starting Load Kernel Module fuse...
10852 05:54:33.813858 Starting [0;1;39mLoad Kernel Module fuse[0m...
10853 05:54:33.841463 <6>[ 21.067973] fuse: init (API version 7.37)
10854 05:54:33.851388 <30>[ 21.068562] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10855 05:54:33.903247 <30>[ 21.130112] systemd[1]: Starting Journal Service...
10856 05:54:33.909770 Starting [0;1;39mJournal Service[0m...
10857 05:54:33.931379 <30>[ 21.158099] systemd[1]: Starting Load Kernel Modules...
10858 05:54:33.937891 Starting [0;1;39mLoad Kernel Modules[0m...
10859 05:54:33.956688 <30>[ 21.180035] systemd[1]: Starting Remount Root and Kernel File Systems...
10860 05:54:33.963310 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10861 05:54:33.979213 <30>[ 21.205742] systemd[1]: Starting Coldplug All udev Devices...
10862 05:54:33.985694 Starting [0;1;39mColdplug All udev Devices[0m...
10863 05:54:34.003500 <30>[ 21.230047] systemd[1]: Mounted Huge Pages File System.
10864 05:54:34.009745 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10865 05:54:34.027550 <30>[ 21.254270] systemd[1]: Mounted POSIX Message Queue File System.
10866 05:54:34.034234 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10867 05:54:34.051970 <30>[ 21.277939] systemd[1]: Mounted Kernel Debug File System.
10868 05:54:34.062053 <3>[ 21.283493] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10869 05:54:34.068547 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10870 05:54:34.087459 <30>[ 21.310207] systemd[1]: Finished Create list of static device nodes for the current kernel.
10871 05:54:34.097270 <3>[ 21.318188] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 05:54:34.103580 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10873 05:54:34.119824 <30>[ 21.346234] systemd[1]: modprobe@configfs.service: Succeeded.
10874 05:54:34.126684 <30>[ 21.353064] systemd[1]: Finished Load Kernel Module configfs.
10875 05:54:34.134258 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10876 05:54:34.143999 <3>[ 21.366893] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 05:54:34.151359 <30>[ 21.377782] systemd[1]: modprobe@drm.service: Succeeded.
10878 05:54:34.157746 <30>[ 21.384425] systemd[1]: Finished Load Kernel Module drm.
10879 05:54:34.164333 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10880 05:54:34.176594 <3>[ 21.399996] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 05:54:34.183706 <30>[ 21.410639] systemd[1]: modprobe@fuse.service: Succeeded.
10882 05:54:34.190836 <30>[ 21.417669] systemd[1]: Finished Load Kernel Module fuse.
10883 05:54:34.198026 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10884 05:54:34.208475 <3>[ 21.431911] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 05:54:34.216719 <30>[ 21.443283] systemd[1]: Finished Load Kernel Modules.
10886 05:54:34.223239 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10887 05:54:34.242022 <3>[ 21.465542] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 05:54:34.248970 <30>[ 21.466013] systemd[1]: Finished Remount Root and Kernel File Systems.
10889 05:54:34.255238 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10890 05:54:34.273999 <3>[ 21.497320] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 05:54:34.295262 <30>[ 21.521137] systemd[1]: Mounting FUSE Control File System...
10892 05:54:34.308825 Mounting [0;1;39mFUSE <3>[ 21.529628] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 05:54:34.308953 Control File System[0m...
10894 05:54:34.325244 <30>[ 21.551929] systemd[1]: Mounting Kernel Configuration File System...
10895 05:54:34.339180 Mounting [0;1;39mKerne<3>[ 21.560748] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 05:54:34.342694 l Configuration File System[0m...
10897 05:54:34.367974 <3>[ 21.591054] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 05:54:34.377742 <30>[ 21.592336] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10899 05:54:34.387444 <30>[ 21.609018] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10900 05:54:34.411343 <30>[ 21.637965] systemd[1]: Starting Load/Save Random Seed...
10901 05:54:34.418117 Starting [0;1;39mLoad/Save Random Seed[0m...
10902 05:54:34.437911 <30>[ 21.664794] systemd[1]: Starting Apply Kernel Variables...
10903 05:54:34.444939 Starting [0;1;39mApply Kernel Variables[0m...
10904 05:54:34.471339 <30>[ 21.697788] systemd[1]: Starting Create System Users...
10905 05:54:34.477738 Starting [0;1;39mCreate System Users[0m...
10906 05:54:34.501314 <4>[ 21.718132] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10907 05:54:34.511536 <3>[ 21.733812] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10908 05:54:34.514922 <30>[ 21.737383] systemd[1]: Started Journal Service.
10909 05:54:34.521058 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10910 05:54:34.541191 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10911 05:54:34.564329 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10912 05:54:34.578629 See 'systemctl status systemd-udev-trigger.service' for details.
10913 05:54:34.595738 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10914 05:54:34.616238 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10915 05:54:34.632750 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10916 05:54:34.648431 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10917 05:54:34.687401 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10918 05:54:34.705100 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10919 05:54:34.729399 <46>[ 21.952752] systemd-journald[306]: Received client request to flush runtime journal.
10920 05:54:34.776669 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10921 05:54:34.795716 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10922 05:54:34.814771 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10923 05:54:34.863406 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10924 05:54:36.146449 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10925 05:54:36.191653 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10926 05:54:36.210611 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10927 05:54:36.238088 Starting [0;1;39mNetwork Service[0m...
10928 05:54:36.530944 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10929 05:54:36.551398 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10930 05:54:36.606621 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10931 05:54:36.911909 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10932 05:54:36.930181 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10933 05:54:36.999801 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10934 05:54:37.015786 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10935 05:54:37.036344 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10936 05:54:37.051574 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10937 05:54:37.071719 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10938 05:54:37.115414 Starting [0;1;39mNetwork Name Resolution[0m...
10939 05:54:37.163157 Starting [0;1;39mNetwork Time Synchronization[0m...
10940 05:54:37.183554 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10941 05:54:37.236758 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10942 05:54:37.595793 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10943 05:54:37.614691 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10944 05:54:37.633684 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10945 05:54:37.646309 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10946 05:54:37.662142 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10947 05:54:37.684967 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10948 05:54:37.707794 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10949 05:54:37.728202 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10950 05:54:37.748595 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10951 05:54:37.762232 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10952 05:54:37.783199 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10953 05:54:37.794350 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10954 05:54:37.810480 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10955 05:54:37.851172 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10956 05:54:37.928617 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10957 05:54:38.046630 Starting [0;1;39mUser Login Management[0m...
10958 05:54:38.064576 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10959 05:54:38.083131 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10960 05:54:38.100132 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10961 05:54:38.134243 Starting [0;1;39mPermit User Sessions[0m...
10962 05:54:38.253662 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10963 05:54:38.270418 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10964 05:54:38.315948 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10965 05:54:38.333360 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10966 05:54:38.351072 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10967 05:54:38.368177 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10968 05:54:38.384181 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10969 05:54:38.399054 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10970 05:54:38.455265 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10971 05:54:38.498218 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10972 05:54:38.612049
10973 05:54:38.612188
10974 05:54:38.615398 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10975 05:54:38.615495
10976 05:54:38.618856 debian-bullseye-arm64 login: root (automatic login)
10977 05:54:38.618940
10978 05:54:38.619012
10979 05:54:38.878641 Linux debian-bullseye-arm64 6.1.67-cip12 #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023 aarch64
10980 05:54:38.878800
10981 05:54:38.885401 The programs included with the Debian GNU/Linux system are free software;
10982 05:54:38.892332 the exact distribution terms for each program are described in the
10983 05:54:38.895507 individual files in /usr/share/doc/*/copyright.
10984 05:54:38.895594
10985 05:54:38.901884 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10986 05:54:38.905068 permitted by applicable law.
10987 05:54:38.948293 Matched prompt #10: / #
10989 05:54:38.948549 Setting prompt string to ['/ #']
10990 05:54:38.948645 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10992 05:54:38.948841 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10993 05:54:38.948930 start: 2.2.6 expect-shell-connection (timeout 00:03:31) [common]
10994 05:54:38.949001 Setting prompt string to ['/ #']
10995 05:54:38.949063 Forcing a shell prompt, looking for ['/ #']
10997 05:54:38.999287 / #
10998 05:54:38.999432 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10999 05:54:38.999526 Waiting using forced prompt support (timeout 00:02:30)
11000 05:54:39.004561
11001 05:54:39.004843 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11002 05:54:39.004938 start: 2.2.7 export-device-env (timeout 00:03:31) [common]
11004 05:54:39.105327 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12379433/extract-nfsrootfs-cgiogds6'
11005 05:54:39.110404 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12379433/extract-nfsrootfs-cgiogds6'
11007 05:54:39.210933 / # export NFS_SERVER_IP='192.168.201.1'
11008 05:54:39.216269 export NFS_SERVER_IP='192.168.201.1'
11009 05:54:39.216558 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11010 05:54:39.216662 end: 2.2 depthcharge-retry (duration 00:01:29) [common]
11011 05:54:39.216754 end: 2 depthcharge-action (duration 00:01:29) [common]
11012 05:54:39.216845 start: 3 lava-test-retry (timeout 00:01:00) [common]
11013 05:54:39.216975 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11014 05:54:39.217055 Using namespace: common
11016 05:54:39.317414 / # #
11017 05:54:39.317580 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11018 05:54:39.322610 #
11019 05:54:39.322881 Using /lava-12379433
11021 05:54:39.423179 / # export SHELL=/bin/sh
11022 05:54:39.428269 export SHELL=/bin/sh
11024 05:54:39.528832 / # . /lava-12379433/environment
11025 05:54:39.534427 . /lava-12379433/environment
11027 05:54:39.639671 / # /lava-12379433/bin/lava-test-runner /lava-12379433/0
11028 05:54:39.639838 Test shell timeout: 10s (minimum of the action and connection timeout)
11029 05:54:39.645045 /lava-12379433/bin/lava-test-runner /lava-12379433/0
11030 05:54:39.835501 + export TESTRUN_ID=0_dmesg
11031 05:54:39.838395 + cd /lava-12379433/0/tests/0_dmesg
11032 05:54:39.842140 + cat uuid
11033 05:54:39.851876 + UUID=12379433_1.<8>[ 27.075604] <LAVA_SIGNAL_STARTRUN 0_dmesg 12379433_1.6.2.3.1>
11034 05:54:39.851982 6.2.3.1
11035 05:54:39.852063 + set +x
11036 05:54:39.852310 Received signal: <STARTRUN> 0_dmesg 12379433_1.6.2.3.1
11037 05:54:39.852417 Starting test lava.0_dmesg (12379433_1.6.2.3.1)
11038 05:54:39.852504 Skipping test definition patterns.
11039 05:54:39.855177 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11040 05:54:39.928155 <8>[ 27.152301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11041 05:54:39.928468 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11043 05:54:39.984447 <8>[ 27.208430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11044 05:54:39.984752 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11046 05:54:40.048449 <8>[ 27.272224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11047 05:54:40.048760 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11049 05:54:40.051726 + set +x
11050 05:54:40.054908 <8>[ 27.281659] <LAVA_SIGNAL_ENDRUN 0_dmesg 12379433_1.6.2.3.1>
11051 05:54:40.055204 Received signal: <ENDRUN> 0_dmesg 12379433_1.6.2.3.1
11052 05:54:40.055292 Ending use of test pattern.
11053 05:54:40.055358 Ending test lava.0_dmesg (12379433_1.6.2.3.1), duration 0.20
11055 05:54:40.060744 <LAVA_TEST_RUNNER EXIT>
11056 05:54:40.060996 ok: lava_test_shell seems to have completed
11057 05:54:40.061103 alert: pass
crit: pass
emerg: pass
11058 05:54:40.061194 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11059 05:54:40.061281 end: 3 lava-test-retry (duration 00:00:01) [common]
11060 05:54:40.061365 start: 4 lava-test-retry (timeout 00:01:00) [common]
11061 05:54:40.061448 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11062 05:54:40.061513 Using namespace: common
11064 05:54:40.161859 / # #
11065 05:54:40.162036 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11066 05:54:40.162173 Using /lava-12379433
11068 05:54:40.262515 export SHELL=/bin/sh
11069 05:54:40.262726 #
11071 05:54:40.363263 / # export SHELL=/bin/sh. /lava-12379433/environment
11072 05:54:40.363457
11074 05:54:40.464030 / # . /lava-12379433/environment/lava-12379433/bin/lava-test-runner /lava-12379433/1
11075 05:54:40.464205 Test shell timeout: 10s (minimum of the action and connection timeout)
11076 05:54:40.464341
11077 05:54:40.469403 / # /lava-12379433/bin/lava-test-runner /lava-12379433/1
11078 05:54:40.568683 + export TESTRUN_ID=1_bootrr
11079 05:54:40.572033 + cd /lava-12379433/1/tests/1_bootrr
11080 05:54:40.575515 + cat uuid
11081 05:54:40.581975 Received signal: <STARTRUN> 1_bootrr 12379433_1.6.2.3.5
11082 05:54:40.582098 Starting test lava.1_bootrr (12379433_1.6.2.3.5)
11083 05:54:40.582221 Skipping test definition patterns.
11084 05:54:40.585248 + UUID=12379433_1.<8>[ 27.808385] <LAVA_SIGNAL_STARTRUN 1_bootrr 12379433_1.6.2.3.5>
11085 05:54:40.585386 6.2.3.5
11086 05:54:40.585496 + set +x
11087 05:54:40.598374 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12379433/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11088 05:54:40.598581 + cd /opt/bootrr/libexec/bootrr
11089 05:54:40.601858 + sh helpers/bootrr-auto
11090 05:54:40.655533 /lava-12379433/1/../bin/lava-test-case
11091 05:54:40.686541 <8>[ 27.910140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11092 05:54:40.687327 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11094 05:54:40.734052 /lava-12379433/1/../bin/lava-test-case
11095 05:54:40.759739 <8>[ 27.983391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11096 05:54:40.760745 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11098 05:54:40.785488 /lava-12379433/1/../bin/lava-test-case
11099 05:54:40.808814 <8>[ 28.032279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11100 05:54:40.809648 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11102 05:54:40.859442 /lava-12379433/1/../bin/lava-test-case
11103 05:54:40.883044 <8>[ 28.106904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11104 05:54:40.883784 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11106 05:54:40.928110 /lava-12379433/1/../bin/lava-test-case
11107 05:54:40.960062 <8>[ 28.183851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11108 05:54:40.960814 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11110 05:54:40.990406 /lava-12379433/1/../bin/lava-test-case
11111 05:54:41.010326 <8>[ 28.234626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11112 05:54:41.010619 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11114 05:54:41.039083 /lava-12379433/1/../bin/lava-test-case
11115 05:54:41.061559 <8>[ 28.285875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11116 05:54:41.061873 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11118 05:54:41.086962 /lava-12379433/1/../bin/lava-test-case
11119 05:54:41.105445 <8>[ 28.329510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11120 05:54:41.105735 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11122 05:54:41.125152 /lava-12379433/1/../bin/lava-test-case
11123 05:54:41.145572 <8>[ 28.369632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11124 05:54:41.145870 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11126 05:54:41.172381 /lava-12379433/1/../bin/lava-test-case
11127 05:54:41.194119 <8>[ 28.418228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11128 05:54:41.194402 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11130 05:54:41.212206 /lava-12379433/1/../bin/lava-test-case
11131 05:54:41.232677 <8>[ 28.457079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11132 05:54:41.232996 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11134 05:54:41.267315 /lava-12379433/1/../bin/lava-test-case
11135 05:54:41.288229 <8>[ 28.512523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11136 05:54:41.288529 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11138 05:54:41.316175 /lava-12379433/1/../bin/lava-test-case
11139 05:54:41.337179 <8>[ 28.561312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11140 05:54:41.337468 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11142 05:54:41.364139 /lava-12379433/1/../bin/lava-test-case
11143 05:54:41.386739 <8>[ 28.610792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11144 05:54:41.387044 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11146 05:54:41.415535 /lava-12379433/1/../bin/lava-test-case
11147 05:54:41.436112 <8>[ 28.660234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11148 05:54:41.436434 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11150 05:54:41.454798 /lava-12379433/1/../bin/lava-test-case
11151 05:54:41.475411 <8>[ 28.699802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11152 05:54:41.475681 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11154 05:54:41.504196 /lava-12379433/1/../bin/lava-test-case
11155 05:54:41.525418 <8>[ 28.749714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11156 05:54:41.525710 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11158 05:54:41.543719 /lava-12379433/1/../bin/lava-test-case
11159 05:54:41.563658 <8>[ 28.787785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11160 05:54:41.563931 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11162 05:54:41.598668 /lava-12379433/1/../bin/lava-test-case
11163 05:54:41.619063 <8>[ 28.843190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11164 05:54:41.619342 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11166 05:54:41.635538 /lava-12379433/1/../bin/lava-test-case
11167 05:54:41.658354 <8>[ 28.882626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11168 05:54:41.658632 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11170 05:54:41.684294 /lava-12379433/1/../bin/lava-test-case
11171 05:54:41.701859 <8>[ 28.926435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11172 05:54:41.702210 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11174 05:54:41.717432 /lava-12379433/1/../bin/lava-test-case
11175 05:54:41.736944 <8>[ 28.961327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11176 05:54:41.737223 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11178 05:54:41.765460 /lava-12379433/1/../bin/lava-test-case
11179 05:54:41.784544 <8>[ 29.009064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11180 05:54:41.784838 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11182 05:54:41.800711 /lava-12379433/1/../bin/lava-test-case
11183 05:54:41.820634 <8>[ 29.045044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11184 05:54:41.820906 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11186 05:54:41.847774 /lava-12379433/1/../bin/lava-test-case
11187 05:54:41.871358 <8>[ 29.095777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11188 05:54:41.871649 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11190 05:54:41.900099 /lava-12379433/1/../bin/lava-test-case
11191 05:54:41.921330 <8>[ 29.145718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11192 05:54:41.921626 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11194 05:54:41.940191 /lava-12379433/1/../bin/lava-test-case
11195 05:54:41.960569 <8>[ 29.184836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11196 05:54:41.960848 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11198 05:54:41.986706 /lava-12379433/1/../bin/lava-test-case
11199 05:54:42.008850 <8>[ 29.233103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11200 05:54:42.009174 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11202 05:54:42.026778 /lava-12379433/1/../bin/lava-test-case
11203 05:54:42.047506 <8>[ 29.271929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11204 05:54:42.047819 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11206 05:54:42.075834 /lava-12379433/1/../bin/lava-test-case
11207 05:54:42.095836 <8>[ 29.320039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11208 05:54:42.096109 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11210 05:54:42.120479 /lava-12379433/1/../bin/lava-test-case
11211 05:54:42.144023 <8>[ 29.368137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11212 05:54:42.144300 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11214 05:54:42.170258 /lava-12379433/1/../bin/lava-test-case
11215 05:54:42.190430 <8>[ 29.414958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11216 05:54:42.190697 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11218 05:54:42.232316 /lava-12379433/1/../bin/lava-test-case
11219 05:54:42.254074 <8>[ 29.478742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11220 05:54:42.254349 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11222 05:54:42.271955 /lava-12379433/1/../bin/lava-test-case
11223 05:54:42.293457 <8>[ 29.518020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11224 05:54:42.293728 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11226 05:54:42.321489 /lava-12379433/1/../bin/lava-test-case
11227 05:54:42.345015 <8>[ 29.569148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11228 05:54:42.345293 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11230 05:54:42.370892 /lava-12379433/1/../bin/lava-test-case
11231 05:54:42.392061 <8>[ 29.616551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11232 05:54:42.392337 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11234 05:54:42.409679 /lava-12379433/1/../bin/lava-test-case
11235 05:54:42.429712 <8>[ 29.654044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11236 05:54:42.429992 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11238 05:54:42.456491 /lava-12379433/1/../bin/lava-test-case
11239 05:54:42.477383 <8>[ 29.701741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11240 05:54:42.477746 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11242 05:54:42.491202 /lava-12379433/1/../bin/lava-test-case
11243 05:54:42.515027 <8>[ 29.739208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11244 05:54:42.515305 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11246 05:54:42.549149 /lava-12379433/1/../bin/lava-test-case
11247 05:54:42.569682 <8>[ 29.794089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11248 05:54:42.570016 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11250 05:54:42.587660 /lava-12379433/1/../bin/lava-test-case
11251 05:54:42.608972 <8>[ 29.833284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11252 05:54:42.609253 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11254 05:54:42.635829 /lava-12379433/1/../bin/lava-test-case
11255 05:54:42.657274 <8>[ 29.881933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11256 05:54:42.657563 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11258 05:54:42.674610 /lava-12379433/1/../bin/lava-test-case
11259 05:54:42.695724 <8>[ 29.919948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11260 05:54:42.696016 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11262 05:54:42.724662 /lava-12379433/1/../bin/lava-test-case
11263 05:54:42.744157 <8>[ 29.968702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11264 05:54:42.744453 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11266 05:54:42.763047 /lava-12379433/1/../bin/lava-test-case
11267 05:54:42.781310 <8>[ 30.005829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11268 05:54:42.781598 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11270 05:54:42.808884 /lava-12379433/1/../bin/lava-test-case
11271 05:54:42.830911 <8>[ 30.055258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11272 05:54:42.831237 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11274 05:54:42.855700 /lava-12379433/1/../bin/lava-test-case
11275 05:54:42.875820 <8>[ 30.100404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11276 05:54:42.876108 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11278 05:54:42.904884 /lava-12379433/1/../bin/lava-test-case
11279 05:54:42.925402 <8>[ 30.149834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11280 05:54:42.925722 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11282 05:54:42.942849 /lava-12379433/1/../bin/lava-test-case
11283 05:54:42.961724 <8>[ 30.186371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11284 05:54:42.962016 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11286 05:54:42.990256 /lava-12379433/1/../bin/lava-test-case
11287 05:54:43.011363 <8>[ 30.236049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11288 05:54:43.011674 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11290 05:54:43.036683 /lava-12379433/1/../bin/lava-test-case
11291 05:54:43.057248 <8>[ 30.281545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11292 05:54:43.057546 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11294 05:54:43.075058 /lava-12379433/1/../bin/lava-test-case
11295 05:54:43.094548 <8>[ 30.318981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11296 05:54:43.094856 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11298 05:54:43.120717 /lava-12379433/1/../bin/lava-test-case
11299 05:54:43.139551 <8>[ 30.364040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11300 05:54:43.139859 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11302 05:54:43.165268 /lava-12379433/1/../bin/lava-test-case
11303 05:54:43.185067 <8>[ 30.409489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11304 05:54:43.185388 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11306 05:54:43.211210 /lava-12379433/1/../bin/lava-test-case
11307 05:54:43.229850 <8>[ 30.454551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11308 05:54:43.230154 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11310 05:54:43.258621 /lava-12379433/1/../bin/lava-test-case
11311 05:54:43.280196 <8>[ 30.504500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11312 05:54:43.280518 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11314 05:54:43.305884 /lava-12379433/1/../bin/lava-test-case
11315 05:54:43.325825 <8>[ 30.550512] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11316 05:54:43.326158 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11318 05:54:43.350880 /lava-12379433/1/../bin/lava-test-case
11319 05:54:43.372141 <8>[ 30.596667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11320 05:54:43.372419 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11322 05:54:43.396763 /lava-12379433/1/../bin/lava-test-case
11323 05:54:43.416171 <8>[ 30.640777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11324 05:54:43.416465 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11326 05:54:43.433150 /lava-12379433/1/../bin/lava-test-case
11327 05:54:43.452422 <8>[ 30.677216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11328 05:54:43.452751 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11330 05:54:43.485850 /lava-12379433/1/../bin/lava-test-case
11331 05:54:43.505492 <8>[ 30.729829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11332 05:54:43.505769 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11334 05:54:43.529703 /lava-12379433/1/../bin/lava-test-case
11335 05:54:43.548213 <8>[ 30.772682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11336 05:54:43.548524 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11338 05:54:43.563665 /lava-12379433/1/../bin/lava-test-case
11339 05:54:43.585636 <8>[ 30.809851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11340 05:54:43.585927 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11342 05:54:43.612415 /lava-12379433/1/../bin/lava-test-case
11343 05:54:43.630899 <8>[ 30.855413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11344 05:54:43.631178 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11346 05:54:43.649117 /lava-12379433/1/../bin/lava-test-case
11347 05:54:43.667544 <8>[ 30.891932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11348 05:54:43.667804 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11350 05:54:43.693877 /lava-12379433/1/../bin/lava-test-case
11351 05:54:43.715028 <8>[ 30.939697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11352 05:54:43.715305 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11354 05:54:43.732531 /lava-12379433/1/../bin/lava-test-case
11355 05:54:43.751769 <8>[ 30.976363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11356 05:54:43.752047 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11358 05:54:43.783032 /lava-12379433/1/../bin/lava-test-case
11359 05:54:43.803142 <8>[ 31.027481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11360 05:54:43.803408 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11362 05:54:43.829268 /lava-12379433/1/../bin/lava-test-case
11363 05:54:43.848656 <8>[ 31.073450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11364 05:54:43.848927 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11366 05:54:43.874244 /lava-12379433/1/../bin/lava-test-case
11367 05:54:43.892533 <8>[ 31.117039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11368 05:54:43.892797 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11370 05:54:43.919215 /lava-12379433/1/../bin/lava-test-case
11371 05:54:43.937856 <8>[ 31.162349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11372 05:54:43.938184 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11374 05:54:43.965553 /lava-12379433/1/../bin/lava-test-case
11375 05:54:43.985845 <8>[ 31.210324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11376 05:54:43.986108 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11378 05:54:44.010445 /lava-12379433/1/../bin/lava-test-case
11379 05:54:44.030486 <8>[ 31.254766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11380 05:54:44.030759 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11382 05:54:44.055942 /lava-12379433/1/../bin/lava-test-case
11383 05:54:44.076425 <8>[ 31.301130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11384 05:54:44.076695 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11386 05:54:44.110275 /lava-12379433/1/../bin/lava-test-case
11387 05:54:44.134446 <8>[ 31.359162] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11388 05:54:44.134756 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11390 05:54:44.159475 /lava-12379433/1/../bin/lava-test-case
11391 05:54:44.178125 <8>[ 31.402809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11392 05:54:44.178411 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11394 05:54:44.204387 /lava-12379433/1/../bin/lava-test-case
11395 05:54:44.225338 <8>[ 31.449947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11396 05:54:44.225609 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11398 05:54:44.249696 /lava-12379433/1/../bin/lava-test-case
11399 05:54:44.269927 <8>[ 31.494252] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11400 05:54:44.270245 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11402 05:54:44.295179 /lava-12379433/1/../bin/lava-test-case
11403 05:54:44.314365 <8>[ 31.539098] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11404 05:54:44.314634 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11406 05:54:44.339315 /lava-12379433/1/../bin/lava-test-case
11407 05:54:44.357458 <8>[ 31.582004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11408 05:54:44.357745 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11410 05:54:44.382927 /lava-12379433/1/../bin/lava-test-case
11411 05:54:44.404723 <8>[ 31.628865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11412 05:54:44.405075 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11414 05:54:44.438482 /lava-12379433/1/../bin/lava-test-case
11415 05:54:44.458207 <8>[ 31.682595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11416 05:54:44.458486 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11418 05:54:44.478041 /lava-12379433/1/../bin/lava-test-case
11419 05:54:44.498479 <8>[ 31.722788] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11420 05:54:44.498769 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11422 05:54:44.528555 /lava-12379433/1/../bin/lava-test-case
11423 05:54:44.552618 <8>[ 31.776894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11424 05:54:44.553548 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11426 05:54:44.570528 /lava-12379433/1/../bin/lava-test-case
11427 05:54:44.590142 <8>[ 31.814675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11428 05:54:44.590471 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11430 05:54:44.617788 /lava-12379433/1/../bin/lava-test-case
11431 05:54:44.646005 <8>[ 31.869971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11432 05:54:44.646883 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11434 05:54:44.668091 /lava-12379433/1/../bin/lava-test-case
11435 05:54:44.692225 <8>[ 31.916478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11436 05:54:44.692918 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11438 05:54:44.729780 /lava-12379433/1/../bin/lava-test-case
11439 05:54:44.756501 <8>[ 31.980834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11440 05:54:44.757251 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11442 05:54:44.787360 /lava-12379433/1/../bin/lava-test-case
11443 05:54:44.812719 <8>[ 32.036945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11444 05:54:44.813556 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11446 05:54:44.844233 /lava-12379433/1/../bin/lava-test-case
11447 05:54:44.871250 <8>[ 32.095786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11448 05:54:44.872033 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11450 05:54:44.892124 /lava-12379433/1/../bin/lava-test-case
11451 05:54:44.916275 <8>[ 32.140487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11452 05:54:44.917162 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11454 05:54:44.949413 /lava-12379433/1/../bin/lava-test-case
11455 05:54:44.974339 <8>[ 32.199069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11456 05:54:44.974756 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11458 05:54:44.995637 /lava-12379433/1/../bin/lava-test-case
11459 05:54:45.015991 <8>[ 32.240319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11460 05:54:45.016396 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11462 05:54:45.045346 /lava-12379433/1/../bin/lava-test-case
11463 05:54:45.066474 <8>[ 32.290952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11464 05:54:45.067012 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11466 05:54:45.109246 /lava-12379433/1/../bin/lava-test-case
11467 05:54:45.135519 <8>[ 32.359893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11468 05:54:45.136308 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11470 05:54:45.157780 /lava-12379433/1/../bin/lava-test-case
11471 05:54:45.180276 <8>[ 32.404724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11472 05:54:45.180923 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11474 05:54:45.211448 /lava-12379433/1/../bin/lava-test-case
11475 05:54:45.234338 <8>[ 32.458805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11476 05:54:45.235071 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11478 05:54:45.253382 /lava-12379433/1/../bin/lava-test-case
11479 05:54:45.273676 <8>[ 32.498553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11480 05:54:45.273967 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11482 05:54:45.300603 /lava-12379433/1/../bin/lava-test-case
11483 05:54:45.320529 <8>[ 32.545317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11484 05:54:45.320818 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11486 05:54:45.335775 /lava-12379433/1/../bin/lava-test-case
11487 05:54:45.354904 <8>[ 32.579858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11488 05:54:45.355217 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11490 05:54:46.391164 /lava-12379433/1/../bin/lava-test-case
11491 05:54:46.413953 <8>[ 33.638975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11492 05:54:46.414228 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11494 05:54:46.429666 /lava-12379433/1/../bin/lava-test-case
11495 05:54:46.448869 <8>[ 33.673991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11496 05:54:46.449152 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11498 05:54:47.480674 /lava-12379433/1/../bin/lava-test-case
11499 05:54:47.503242 <8>[ 34.728089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11500 05:54:47.503524 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11502 05:54:47.521082 /lava-12379433/1/../bin/lava-test-case
11503 05:54:47.539194 <8>[ 34.764140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11504 05:54:47.539478 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11506 05:54:48.572541 /lava-12379433/1/../bin/lava-test-case
11507 05:54:48.595203 <8>[ 35.820278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11508 05:54:48.595521 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11510 05:54:48.615005 /lava-12379433/1/../bin/lava-test-case
11511 05:54:48.634671 <8>[ 35.860012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11512 05:54:48.635016 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11514 05:54:49.667935 /lava-12379433/1/../bin/lava-test-case
11515 05:54:49.689700 <8>[ 36.914888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11516 05:54:49.689964 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11518 05:54:49.706403 /lava-12379433/1/../bin/lava-test-case
11519 05:54:49.725859 <8>[ 36.951233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11520 05:54:49.726166 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11522 05:54:50.762359 /lava-12379433/1/../bin/lava-test-case
11523 05:54:50.784339 <8>[ 38.009713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11524 05:54:50.784619 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11526 05:54:50.800622 /lava-12379433/1/../bin/lava-test-case
11527 05:54:50.820329 <8>[ 38.045611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11528 05:54:50.820594 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11530 05:54:51.855591 /lava-12379433/1/../bin/lava-test-case
11531 05:54:51.883073 <8>[ 39.108642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11532 05:54:51.883392 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11534 05:54:51.901560 /lava-12379433/1/../bin/lava-test-case
11535 05:54:51.923032 <8>[ 39.148673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11536 05:54:51.923302 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11538 05:54:52.958310 /lava-12379433/1/../bin/lava-test-case
11539 05:54:52.981438 <8>[ 40.207180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11540 05:54:52.981759 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11542 05:54:53.000205 /lava-12379433/1/../bin/lava-test-case
11543 05:54:53.017044 <8>[ 40.242757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11544 05:54:53.017311 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11546 05:54:53.035365 /lava-12379433/1/../bin/lava-test-case
11547 05:54:53.057053 <8>[ 40.282744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11548 05:54:53.057332 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11550 05:54:54.091088 /lava-12379433/1/../bin/lava-test-case
11551 05:54:54.115944 <8>[ 41.341603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11552 05:54:54.116248 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11554 05:54:54.134841 /lava-12379433/1/../bin/lava-test-case
11555 05:54:54.154356 <8>[ 41.380243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11556 05:54:54.154631 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11558 05:54:54.182143 /lava-12379433/1/../bin/lava-test-case
11559 05:54:54.201306 <8>[ 41.427218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11560 05:54:54.201669 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11562 05:54:54.218663 /lava-12379433/1/../bin/lava-test-case
11563 05:54:54.239252 <8>[ 41.465061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11564 05:54:54.239536 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11566 05:54:54.267878 /lava-12379433/1/../bin/lava-test-case
11567 05:54:54.285796 <8>[ 41.511309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11568 05:54:54.286080 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11570 05:54:54.309091 /lava-12379433/1/../bin/lava-test-case
11571 05:54:54.328605 <8>[ 41.554118] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11572 05:54:54.328883 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11574 05:54:54.357452 /lava-12379433/1/../bin/lava-test-case
11575 05:54:54.375600 <8>[ 41.601164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11576 05:54:54.375874 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11578 05:54:54.400771 /lava-12379433/1/../bin/lava-test-case
11579 05:54:54.418819 <8>[ 41.644785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11580 05:54:54.419131 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11582 05:54:54.446312 /lava-12379433/1/../bin/lava-test-case
11583 05:54:54.465573 <8>[ 41.691388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11584 05:54:54.465841 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11586 05:54:54.491153 /lava-12379433/1/../bin/lava-test-case
11587 05:54:54.510700 <8>[ 41.736769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11588 05:54:54.510977 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11590 05:54:54.530912 /lava-12379433/1/../bin/lava-test-case
11591 05:54:54.549747 <8>[ 41.775518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11592 05:54:54.550049 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11594 05:54:54.576309 /lava-12379433/1/../bin/lava-test-case
11595 05:54:54.594921 <8>[ 41.820619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11596 05:54:54.595640 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11598 05:54:54.614248 /lava-12379433/1/../bin/lava-test-case
11599 05:54:54.636602 <8>[ 41.862203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11600 05:54:54.637575 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11602 05:54:54.667993 /lava-12379433/1/../bin/lava-test-case
11603 05:54:54.693003 <8>[ 41.918757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11604 05:54:54.693311 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11606 05:54:54.717589 /lava-12379433/1/../bin/lava-test-case
11607 05:54:54.737073 <8>[ 41.962646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11608 05:54:54.737366 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11610 05:54:54.762149 /lava-12379433/1/../bin/lava-test-case
11611 05:54:54.782094 <8>[ 42.007743] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11612 05:54:54.782369 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11614 05:54:54.798331 /lava-12379433/1/../bin/lava-test-case
11615 05:54:54.817661 <8>[ 42.043537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11616 05:54:54.817923 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11618 05:54:54.844067 /lava-12379433/1/../bin/lava-test-case
11619 05:54:54.864458 <8>[ 42.090328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11620 05:54:54.864749 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11622 05:54:54.881538 /lava-12379433/1/../bin/lava-test-case
11623 05:54:54.901406 <8>[ 42.127475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11624 05:54:54.901676 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11626 05:54:54.930034 /lava-12379433/1/../bin/lava-test-case
11627 05:54:54.949892 <8>[ 42.175871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11628 05:54:54.950209 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11630 05:54:54.966386 /lava-12379433/1/../bin/lava-test-case
11631 05:54:54.985626 <8>[ 42.211623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11632 05:54:54.985893 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11634 05:54:56.017291 /lava-12379433/1/../bin/lava-test-case
11635 05:54:56.044085 <8>[ 43.270203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11636 05:54:56.044401 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11638 05:54:57.080840 /lava-12379433/1/../bin/lava-test-case
11639 05:54:57.100672 <8>[ 44.327031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11640 05:54:57.100975 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11642 05:54:57.120835 /lava-12379433/1/../bin/lava-test-case
11643 05:54:57.140322 <8>[ 44.366466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11644 05:54:57.140698 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11646 05:54:57.166073 /lava-12379433/1/../bin/lava-test-case
11647 05:54:57.190689 <8>[ 44.416648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11648 05:54:57.190962 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11650 05:54:57.207623 /lava-12379433/1/../bin/lava-test-case
11651 05:54:57.228199 <8>[ 44.454383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11652 05:54:57.228491 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11654 05:54:57.255079 /lava-12379433/1/../bin/lava-test-case
11655 05:54:57.272606 <8>[ 44.498464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11656 05:54:57.272886 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11658 05:54:57.290304 /lava-12379433/1/../bin/lava-test-case
11659 05:54:57.308587 <8>[ 44.534786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11660 05:54:57.308877 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11662 05:54:57.331425 /lava-12379433/1/../bin/lava-test-case
11663 05:54:57.351787 <8>[ 44.578122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11664 05:54:57.352112 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11666 05:54:57.368491 /lava-12379433/1/../bin/lava-test-case
11667 05:54:57.389993 <8>[ 44.615977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11668 05:54:57.390274 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11670 05:54:57.421696 /lava-12379433/1/../bin/lava-test-case
11671 05:54:57.442724 <8>[ 44.669173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11672 05:54:57.443032 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11674 05:54:57.460098 /lava-12379433/1/../bin/lava-test-case
11675 05:54:57.480061 <8>[ 44.706247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11676 05:54:57.480330 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11678 05:54:57.504721 /lava-12379433/1/../bin/lava-test-case
11679 05:54:57.524525 <8>[ 44.750735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11680 05:54:57.524798 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11682 05:54:57.541614 /lava-12379433/1/../bin/lava-test-case
11683 05:54:57.562135 <8>[ 44.788394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11684 05:54:57.562407 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11686 05:54:57.586616 /lava-12379433/1/../bin/lava-test-case
11687 05:54:57.606922 <8>[ 44.833016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11688 05:54:57.607195 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11690 05:54:57.625168 /lava-12379433/1/../bin/lava-test-case
11691 05:54:57.645591 <8>[ 44.871668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11692 05:54:57.645886 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11694 05:54:57.672290 /lava-12379433/1/../bin/lava-test-case
11695 05:54:57.691600 <8>[ 44.917951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11696 05:54:57.691866 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11698 05:54:57.707949 /lava-12379433/1/../bin/lava-test-case
11699 05:54:57.727917 <8>[ 44.954274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11700 05:54:57.728192 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11702 05:54:57.761744 /lava-12379433/1/../bin/lava-test-case
11703 05:54:57.782257 <8>[ 45.008428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11704 05:54:57.782528 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11706 05:54:57.800014 /lava-12379433/1/../bin/lava-test-case
11707 05:54:57.819614 <8>[ 45.045926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11708 05:54:57.819914 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11710 05:54:57.845066 /lava-12379433/1/../bin/lava-test-case
11711 05:54:57.862910 <8>[ 45.089226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11712 05:54:57.863173 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11714 05:54:57.879736 /lava-12379433/1/../bin/lava-test-case
11715 05:54:57.899088 <8>[ 45.125179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11716 05:54:57.899382 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11718 05:54:57.925864 /lava-12379433/1/../bin/lava-test-case
11719 05:54:57.944589 <8>[ 45.170877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11720 05:54:57.944864 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11722 05:54:58.860698 <6>[ 46.093633] vpu: disabling
11723 05:54:58.863969 <6>[ 46.096746] vproc2: disabling
11724 05:54:58.867498 <6>[ 46.100098] vproc1: disabling
11725 05:54:58.870546 <6>[ 46.103435] vaud18: disabling
11726 05:54:58.877628 <6>[ 46.106940] vsram_others: disabling
11727 05:54:58.880712 <6>[ 46.110947] va09: disabling
11728 05:54:58.884233 <6>[ 46.114115] vsram_md: disabling
11729 05:54:58.887165 <6>[ 46.117707] Vgpu: disabling
11730 05:54:58.969209 /lava-12379433/1/../bin/lava-test-case
11731 05:54:58.990918 <8>[ 46.217032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11732 05:54:58.991195 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11734 05:55:00.015140 /lava-12379433/1/../bin/lava-test-case
11735 05:55:00.038595 <8>[ 47.264991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11736 05:55:00.038890 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11737 05:55:00.038984 Bad test result: blocked
11738 05:55:00.054276 /lava-12379433/1/../bin/lava-test-case
11739 05:55:00.077117 <8>[ 47.303581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11740 05:55:00.077398 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11742 05:55:01.109283 /lava-12379433/1/../bin/lava-test-case
11743 05:55:01.132623 <8>[ 48.359325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11744 05:55:01.132925 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11746 05:55:01.149447 /lava-12379433/1/../bin/lava-test-case
11747 05:55:01.171725 <8>[ 48.398320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11748 05:55:01.172016 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11750 05:55:01.195688 /lava-12379433/1/../bin/lava-test-case
11751 05:55:01.215847 <8>[ 48.442390] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11752 05:55:01.216117 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11754 05:55:01.240627 /lava-12379433/1/../bin/lava-test-case
11755 05:55:01.263897 <8>[ 48.490617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11756 05:55:01.264208 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11758 05:55:01.281209 /lava-12379433/1/../bin/lava-test-case
11759 05:55:01.301274 <8>[ 48.528039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11760 05:55:01.301552 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11762 05:55:01.329221 /lava-12379433/1/../bin/lava-test-case
11763 05:55:01.349417 <8>[ 48.576202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11764 05:55:01.349778 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11766 05:55:01.368214 /lava-12379433/1/../bin/lava-test-case
11767 05:55:01.387898 <8>[ 48.614518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11768 05:55:01.388182 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11770 05:55:02.429582 /lava-12379433/1/../bin/lava-test-case
11771 05:55:02.450549 <8>[ 49.677526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11772 05:55:02.450857 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11774 05:55:02.469001 /lava-12379433/1/../bin/lava-test-case
11775 05:55:02.487233 <8>[ 49.713980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11776 05:55:02.487519 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11778 05:55:03.519472 /lava-12379433/1/../bin/lava-test-case
11779 05:55:03.540994 <8>[ 50.767801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11780 05:55:03.541288 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11782 05:55:03.558237 /lava-12379433/1/../bin/lava-test-case
11783 05:55:03.577544 <8>[ 50.804592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11784 05:55:03.577812 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11786 05:55:04.609979 /lava-12379433/1/../bin/lava-test-case
11787 05:55:04.633632 <8>[ 51.860490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11788 05:55:04.633924 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11790 05:55:04.649690 /lava-12379433/1/../bin/lava-test-case
11791 05:55:04.669510 <8>[ 51.896403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11792 05:55:04.669794 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11794 05:55:05.703755 /lava-12379433/1/../bin/lava-test-case
11795 05:55:05.727967 <8>[ 52.954710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11796 05:55:05.728294 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11798 05:55:05.744872 /lava-12379433/1/../bin/lava-test-case
11799 05:55:05.763411 <8>[ 52.990604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11800 05:55:05.763679 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11802 05:55:05.784524 /lava-12379433/1/../bin/lava-test-case
11803 05:55:05.805897 <8>[ 53.033030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11804 05:55:05.806223 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11806 05:55:05.828823 /lava-12379433/1/../bin/lava-test-case
11807 05:55:05.848595 <8>[ 53.075955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11808 05:55:05.848894 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11810 05:55:05.866364 /lava-12379433/1/../bin/lava-test-case
11811 05:55:05.888695 <8>[ 53.115471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11812 05:55:05.889153 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11814 05:55:05.915815 /lava-12379433/1/../bin/lava-test-case
11815 05:55:05.936143 <8>[ 53.163385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11816 05:55:05.936433 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11818 05:55:05.951346 /lava-12379433/1/../bin/lava-test-case
11819 05:55:05.970657 <8>[ 53.197834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11820 05:55:05.970932 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11822 05:55:05.995937 /lava-12379433/1/../bin/lava-test-case
11823 05:55:06.013901 <8>[ 53.241073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11824 05:55:06.014232 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11826 05:55:06.036941 /lava-12379433/1/../bin/lava-test-case
11827 05:55:06.056005 <8>[ 53.283035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11828 05:55:06.056280 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11830 05:55:06.080984 /lava-12379433/1/../bin/lava-test-case
11831 05:55:06.097884 <8>[ 53.325231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11832 05:55:06.098179 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11834 05:55:06.106013 + <8>[ 53.336463] <LAVA_SIGNAL_ENDRUN 1_bootrr 12379433_1.6.2.3.5>
11835 05:55:06.106267 Received signal: <ENDRUN> 1_bootrr 12379433_1.6.2.3.5
11836 05:55:06.106346 Ending use of test pattern.
11837 05:55:06.106411 Ending test lava.1_bootrr (12379433_1.6.2.3.5), duration 25.52
11839 05:55:06.108977 set +x
11840 05:55:06.112451 <LAVA_TEST_RUNNER EXIT>
11841 05:55:06.112700 ok: lava_test_shell seems to have completed
11842 05:55:06.113705 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11843 05:55:06.113851 end: 4.1 lava-test-shell (duration 00:00:26) [common]
11844 05:55:06.113981 end: 4 lava-test-retry (duration 00:00:26) [common]
11845 05:55:06.114074 start: 5 finalize (timeout 00:07:38) [common]
11846 05:55:06.114162 start: 5.1 power-off (timeout 00:00:30) [common]
11847 05:55:06.114313 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11848 05:55:06.188569 >> Command sent successfully.
11849 05:55:06.190875 Returned 0 in 0 seconds
11850 05:55:06.291282 end: 5.1 power-off (duration 00:00:00) [common]
11852 05:55:06.291647 start: 5.2 read-feedback (timeout 00:07:38) [common]
11853 05:55:06.291908 Listened to connection for namespace 'common' for up to 1s
11854 05:55:07.292863 Finalising connection for namespace 'common'
11855 05:55:07.293034 Disconnecting from shell: Finalise
11856 05:55:07.293115 / #
11857 05:55:07.393441 end: 5.2 read-feedback (duration 00:00:01) [common]
11858 05:55:07.393607 end: 5 finalize (duration 00:00:01) [common]
11859 05:55:07.393727 Cleaning after the job
11860 05:55:07.393826 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/ramdisk
11861 05:55:07.395856 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/kernel
11862 05:55:07.405295 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/dtb
11863 05:55:07.405480 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/nfsrootfs
11864 05:55:07.461324 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379433/tftp-deploy-cd2_bfbv/modules
11865 05:55:07.466833 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12379433
11866 05:55:07.781899 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12379433
11867 05:55:07.782075 Job finished correctly