Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 16
- Kernel Errors: 35
- Errors: 1
1 05:58:31.293441 lava-dispatcher, installed at version: 2023.10
2 05:58:31.293676 start: 0 validate
3 05:58:31.293819 Start time: 2023-12-25 05:58:31.293809+00:00 (UTC)
4 05:58:31.293940 Using caching service: 'http://localhost/cache/?uri=%s'
5 05:58:31.294075 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 05:58:31.553750 Using caching service: 'http://localhost/cache/?uri=%s'
7 05:58:31.553909 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 05:58:31.554914 Using caching service: 'http://localhost/cache/?uri=%s'
9 05:58:31.555034 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 05:58:31.821268 Using caching service: 'http://localhost/cache/?uri=%s'
11 05:58:31.821510 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 05:58:32.082963 validate duration: 0.79
14 05:58:32.083320 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:58:32.083430 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:58:32.083560 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:58:32.083770 Not decompressing ramdisk as can be used compressed.
18 05:58:32.083874 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 05:58:32.084037 saving as /var/lib/lava/dispatcher/tmp/12379461/tftp-deploy-s7pdjngo/ramdisk/rootfs.cpio.gz
20 05:58:32.084140 total size: 34390042 (32 MB)
21 05:58:32.085710 progress 0 % (0 MB)
22 05:58:32.095765 progress 5 % (1 MB)
23 05:58:32.105755 progress 10 % (3 MB)
24 05:58:32.115860 progress 15 % (4 MB)
25 05:58:32.125766 progress 20 % (6 MB)
26 05:58:32.135312 progress 25 % (8 MB)
27 05:58:32.144390 progress 30 % (9 MB)
28 05:58:32.153626 progress 35 % (11 MB)
29 05:58:32.162716 progress 40 % (13 MB)
30 05:58:32.171998 progress 45 % (14 MB)
31 05:58:32.181137 progress 50 % (16 MB)
32 05:58:32.190448 progress 55 % (18 MB)
33 05:58:32.199564 progress 60 % (19 MB)
34 05:58:32.209001 progress 65 % (21 MB)
35 05:58:32.218222 progress 70 % (22 MB)
36 05:58:32.227552 progress 75 % (24 MB)
37 05:58:32.236777 progress 80 % (26 MB)
38 05:58:32.246035 progress 85 % (27 MB)
39 05:58:32.254956 progress 90 % (29 MB)
40 05:58:32.263993 progress 95 % (31 MB)
41 05:58:32.272878 progress 100 % (32 MB)
42 05:58:32.273081 32 MB downloaded in 0.19 s (173.58 MB/s)
43 05:58:32.273262 end: 1.1.1 http-download (duration 00:00:00) [common]
45 05:58:32.273603 end: 1.1 download-retry (duration 00:00:00) [common]
46 05:58:32.273712 start: 1.2 download-retry (timeout 00:10:00) [common]
47 05:58:32.273814 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 05:58:32.273977 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 05:58:32.274079 saving as /var/lib/lava/dispatcher/tmp/12379461/tftp-deploy-s7pdjngo/kernel/Image
50 05:58:32.274179 total size: 50024960 (47 MB)
51 05:58:32.274285 No compression specified
52 05:58:32.275907 progress 0 % (0 MB)
53 05:58:32.289184 progress 5 % (2 MB)
54 05:58:32.302986 progress 10 % (4 MB)
55 05:58:32.316372 progress 15 % (7 MB)
56 05:58:32.330163 progress 20 % (9 MB)
57 05:58:32.343674 progress 25 % (11 MB)
58 05:58:32.357235 progress 30 % (14 MB)
59 05:58:32.370735 progress 35 % (16 MB)
60 05:58:32.384047 progress 40 % (19 MB)
61 05:58:32.397360 progress 45 % (21 MB)
62 05:58:32.410895 progress 50 % (23 MB)
63 05:58:32.424544 progress 55 % (26 MB)
64 05:58:32.438322 progress 60 % (28 MB)
65 05:58:32.452090 progress 65 % (31 MB)
66 05:58:32.466007 progress 70 % (33 MB)
67 05:58:32.479736 progress 75 % (35 MB)
68 05:58:32.493420 progress 80 % (38 MB)
69 05:58:32.506816 progress 85 % (40 MB)
70 05:58:32.520314 progress 90 % (42 MB)
71 05:58:32.534231 progress 95 % (45 MB)
72 05:58:32.547289 progress 100 % (47 MB)
73 05:58:32.547545 47 MB downloaded in 0.27 s (174.52 MB/s)
74 05:58:32.547708 end: 1.2.1 http-download (duration 00:00:00) [common]
76 05:58:32.547979 end: 1.2 download-retry (duration 00:00:00) [common]
77 05:58:32.548088 start: 1.3 download-retry (timeout 00:10:00) [common]
78 05:58:32.548194 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 05:58:32.548352 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 05:58:32.548431 saving as /var/lib/lava/dispatcher/tmp/12379461/tftp-deploy-s7pdjngo/dtb/mt8192-asurada-spherion-r0.dtb
81 05:58:32.548515 total size: 47278 (0 MB)
82 05:58:32.548622 No compression specified
83 05:58:32.550331 progress 69 % (0 MB)
84 05:58:32.550648 progress 100 % (0 MB)
85 05:58:32.550851 0 MB downloaded in 0.00 s (19.32 MB/s)
86 05:58:32.550998 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:58:32.551259 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:58:32.551360 start: 1.4 download-retry (timeout 00:10:00) [common]
90 05:58:32.551459 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 05:58:32.551599 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 05:58:32.551704 saving as /var/lib/lava/dispatcher/tmp/12379461/tftp-deploy-s7pdjngo/modules/modules.tar
93 05:58:32.551805 total size: 8619328 (8 MB)
94 05:58:32.551906 Using unxz to decompress xz
95 05:58:32.556523 progress 0 % (0 MB)
96 05:58:32.577793 progress 5 % (0 MB)
97 05:58:32.602254 progress 10 % (0 MB)
98 05:58:32.626612 progress 15 % (1 MB)
99 05:58:32.652082 progress 20 % (1 MB)
100 05:58:32.677602 progress 25 % (2 MB)
101 05:58:32.706086 progress 30 % (2 MB)
102 05:58:32.734701 progress 35 % (2 MB)
103 05:58:32.760838 progress 40 % (3 MB)
104 05:58:32.788499 progress 45 % (3 MB)
105 05:58:32.814997 progress 50 % (4 MB)
106 05:58:32.840758 progress 55 % (4 MB)
107 05:58:32.866092 progress 60 % (4 MB)
108 05:58:32.892229 progress 65 % (5 MB)
109 05:58:32.919709 progress 70 % (5 MB)
110 05:58:32.943898 progress 75 % (6 MB)
111 05:58:32.971613 progress 80 % (6 MB)
112 05:58:32.998280 progress 85 % (7 MB)
113 05:58:33.023989 progress 90 % (7 MB)
114 05:58:33.055125 progress 95 % (7 MB)
115 05:58:33.085909 progress 100 % (8 MB)
116 05:58:33.091011 8 MB downloaded in 0.54 s (15.24 MB/s)
117 05:58:33.091336 end: 1.4.1 http-download (duration 00:00:01) [common]
119 05:58:33.091776 end: 1.4 download-retry (duration 00:00:01) [common]
120 05:58:33.091911 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 05:58:33.092042 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 05:58:33.092166 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:58:33.092295 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 05:58:33.092576 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l
125 05:58:33.092759 makedir: /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin
126 05:58:33.092914 makedir: /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/tests
127 05:58:33.093058 makedir: /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/results
128 05:58:33.093210 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-add-keys
129 05:58:33.093408 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-add-sources
130 05:58:33.093601 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-background-process-start
131 05:58:33.093794 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-background-process-stop
132 05:58:33.093940 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-common-functions
133 05:58:33.094084 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-echo-ipv4
134 05:58:33.094240 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-install-packages
135 05:58:33.094403 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-installed-packages
136 05:58:33.094538 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-os-build
137 05:58:33.094682 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-probe-channel
138 05:58:33.094838 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-probe-ip
139 05:58:33.095009 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-target-ip
140 05:58:33.095141 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-target-mac
141 05:58:33.095282 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-target-storage
142 05:58:33.095445 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-test-case
143 05:58:33.095590 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-test-event
144 05:58:33.095722 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-test-feedback
145 05:58:33.095863 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-test-raise
146 05:58:33.096029 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-test-reference
147 05:58:33.096169 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-test-runner
148 05:58:33.096342 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-test-set
149 05:58:33.096477 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-test-shell
150 05:58:33.096646 Updating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-install-packages (oe)
151 05:58:33.096818 Updating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/bin/lava-installed-packages (oe)
152 05:58:33.096957 Creating /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/environment
153 05:58:33.097073 LAVA metadata
154 05:58:33.097174 - LAVA_JOB_ID=12379461
155 05:58:33.097242 - LAVA_DISPATCHER_IP=192.168.201.1
156 05:58:33.097360 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 05:58:33.097430 skipped lava-vland-overlay
158 05:58:33.097529 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 05:58:33.097616 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 05:58:33.097715 skipped lava-multinode-overlay
161 05:58:33.097794 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 05:58:33.097893 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 05:58:33.097978 Loading test definitions
164 05:58:33.098091 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 05:58:33.098195 Using /lava-12379461 at stage 0
166 05:58:33.098554 uuid=12379461_1.5.2.3.1 testdef=None
167 05:58:33.098652 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 05:58:33.098752 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 05:58:33.099392 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 05:58:33.099671 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 05:58:33.100569 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 05:58:33.100843 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 05:58:33.101614 runner path: /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/0/tests/0_cros-ec test_uuid 12379461_1.5.2.3.1
176 05:58:33.101804 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 05:58:33.102065 Creating lava-test-runner.conf files
179 05:58:33.102132 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379461/lava-overlay-vohvq52l/lava-12379461/0 for stage 0
180 05:58:33.102225 - 0_cros-ec
181 05:58:33.102353 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 05:58:33.102465 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 05:58:33.111252 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 05:58:33.111419 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 05:58:33.111541 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 05:58:33.111683 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 05:58:33.111806 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 05:58:34.128283 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 05:58:34.128689 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 05:58:34.128856 extracting modules file /var/lib/lava/dispatcher/tmp/12379461/tftp-deploy-s7pdjngo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379461/extract-overlay-ramdisk-hfbqs4ts/ramdisk
191 05:58:34.371415 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 05:58:34.371594 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 05:58:34.371697 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379461/compress-overlay-hc_sf6n_/overlay-1.5.2.4.tar.gz to ramdisk
194 05:58:34.371775 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379461/compress-overlay-hc_sf6n_/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12379461/extract-overlay-ramdisk-hfbqs4ts/ramdisk
195 05:58:34.378867 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 05:58:34.378996 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 05:58:34.379089 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 05:58:34.379181 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 05:58:34.379262 Building ramdisk /var/lib/lava/dispatcher/tmp/12379461/extract-overlay-ramdisk-hfbqs4ts/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12379461/extract-overlay-ramdisk-hfbqs4ts/ramdisk
200 05:58:35.116587 >> 271084 blocks
201 05:58:39.974925 rename /var/lib/lava/dispatcher/tmp/12379461/extract-overlay-ramdisk-hfbqs4ts/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12379461/tftp-deploy-s7pdjngo/ramdisk/ramdisk.cpio.gz
202 05:58:39.975424 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 05:58:39.975626 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 05:58:39.975765 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 05:58:39.975911 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12379461/tftp-deploy-s7pdjngo/kernel/Image'
206 05:58:53.249718 Returned 0 in 13 seconds
207 05:58:53.350330 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12379461/tftp-deploy-s7pdjngo/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12379461/tftp-deploy-s7pdjngo/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12379461/tftp-deploy-s7pdjngo/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12379461/tftp-deploy-s7pdjngo/kernel/image.itb
208 05:58:54.050565 output: FIT description: Kernel Image image with one or more FDT blobs
209 05:58:54.050948 output: Created: Mon Dec 25 05:58:53 2023
210 05:58:54.051027 output: Image 0 (kernel-1)
211 05:58:54.051094 output: Description:
212 05:58:54.051159 output: Created: Mon Dec 25 05:58:53 2023
213 05:58:54.051225 output: Type: Kernel Image
214 05:58:54.051287 output: Compression: lzma compressed
215 05:58:54.051349 output: Data Size: 11481830 Bytes = 11212.72 KiB = 10.95 MiB
216 05:58:54.051411 output: Architecture: AArch64
217 05:58:54.051468 output: OS: Linux
218 05:58:54.051526 output: Load Address: 0x00000000
219 05:58:54.051587 output: Entry Point: 0x00000000
220 05:58:54.051643 output: Hash algo: crc32
221 05:58:54.051700 output: Hash value: a47c00f1
222 05:58:54.051756 output: Image 1 (fdt-1)
223 05:58:54.051811 output: Description: mt8192-asurada-spherion-r0
224 05:58:54.051865 output: Created: Mon Dec 25 05:58:53 2023
225 05:58:54.051919 output: Type: Flat Device Tree
226 05:58:54.051973 output: Compression: uncompressed
227 05:58:54.052025 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 05:58:54.052079 output: Architecture: AArch64
229 05:58:54.052132 output: Hash algo: crc32
230 05:58:54.052184 output: Hash value: cc4352de
231 05:58:54.052237 output: Image 2 (ramdisk-1)
232 05:58:54.052290 output: Description: unavailable
233 05:58:54.052342 output: Created: Mon Dec 25 05:58:53 2023
234 05:58:54.052395 output: Type: RAMDisk Image
235 05:58:54.052448 output: Compression: Unknown Compression
236 05:58:54.052501 output: Data Size: 47524929 Bytes = 46411.06 KiB = 45.32 MiB
237 05:58:54.052555 output: Architecture: AArch64
238 05:58:54.052607 output: OS: Linux
239 05:58:54.052661 output: Load Address: unavailable
240 05:58:54.052713 output: Entry Point: unavailable
241 05:58:54.052766 output: Hash algo: crc32
242 05:58:54.052818 output: Hash value: a1939318
243 05:58:54.052871 output: Default Configuration: 'conf-1'
244 05:58:54.052924 output: Configuration 0 (conf-1)
245 05:58:54.052976 output: Description: mt8192-asurada-spherion-r0
246 05:58:54.053029 output: Kernel: kernel-1
247 05:58:54.053081 output: Init Ramdisk: ramdisk-1
248 05:58:54.053134 output: FDT: fdt-1
249 05:58:54.053186 output: Loadables: kernel-1
250 05:58:54.053238 output:
251 05:58:54.053434 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 05:58:54.053582 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 05:58:54.053720 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 05:58:54.053848 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 05:58:54.053929 No LXC device requested
256 05:58:54.054010 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 05:58:54.054094 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 05:58:54.054174 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 05:58:54.054248 Checking files for TFTP limit of 4294967296 bytes.
260 05:58:54.054752 end: 1 tftp-deploy (duration 00:00:22) [common]
261 05:58:54.054855 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 05:58:54.054945 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 05:58:54.055080 substitutions:
264 05:58:54.055149 - {DTB}: 12379461/tftp-deploy-s7pdjngo/dtb/mt8192-asurada-spherion-r0.dtb
265 05:58:54.055215 - {INITRD}: 12379461/tftp-deploy-s7pdjngo/ramdisk/ramdisk.cpio.gz
266 05:58:54.055274 - {KERNEL}: 12379461/tftp-deploy-s7pdjngo/kernel/Image
267 05:58:54.055332 - {LAVA_MAC}: None
268 05:58:54.055387 - {PRESEED_CONFIG}: None
269 05:58:54.055442 - {PRESEED_LOCAL}: None
270 05:58:54.055497 - {RAMDISK}: 12379461/tftp-deploy-s7pdjngo/ramdisk/ramdisk.cpio.gz
271 05:58:54.055552 - {ROOT_PART}: None
272 05:58:54.055606 - {ROOT}: None
273 05:58:54.055659 - {SERVER_IP}: 192.168.201.1
274 05:58:54.055713 - {TEE}: None
275 05:58:54.055767 Parsed boot commands:
276 05:58:54.055821 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 05:58:54.056001 Parsed boot commands: tftpboot 192.168.201.1 12379461/tftp-deploy-s7pdjngo/kernel/image.itb 12379461/tftp-deploy-s7pdjngo/kernel/cmdline
278 05:58:54.056090 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 05:58:54.056175 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 05:58:54.056270 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 05:58:54.056355 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 05:58:54.056426 Not connected, no need to disconnect.
283 05:58:54.056499 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 05:58:54.056578 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 05:58:54.056643 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 05:58:54.060608 Setting prompt string to ['lava-test: # ']
287 05:58:54.060999 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 05:58:54.061126 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 05:58:54.061226 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 05:58:54.061365 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 05:58:54.061615 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 05:58:59.189069 >> Command sent successfully.
293 05:58:59.191665 Returned 0 in 5 seconds
294 05:58:59.292053 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 05:58:59.292390 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 05:58:59.292494 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 05:58:59.292582 Setting prompt string to 'Starting depthcharge on Spherion...'
299 05:58:59.292653 Changing prompt to 'Starting depthcharge on Spherion...'
300 05:58:59.292722 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 05:58:59.293025 [Enter `^Ec?' for help]
302 05:58:59.463870
303 05:58:59.464024
304 05:58:59.464096 F0: 102B 0000
305 05:58:59.464163
306 05:58:59.464224 F3: 1001 0000 [0200]
307 05:58:59.466773
308 05:58:59.466860 F3: 1001 0000
309 05:58:59.466927
310 05:58:59.466994 F7: 102D 0000
311 05:58:59.467056
312 05:58:59.470460 F1: 0000 0000
313 05:58:59.470549
314 05:58:59.470616 V0: 0000 0000 [0001]
315 05:58:59.470681
316 05:58:59.473935 00: 0007 8000
317 05:58:59.474024
318 05:58:59.474091 01: 0000 0000
319 05:58:59.474154
320 05:58:59.476718 BP: 0C00 0209 [0000]
321 05:58:59.476802
322 05:58:59.476869 G0: 1182 0000
323 05:58:59.476931
324 05:58:59.480697 EC: 0000 0021 [4000]
325 05:58:59.480790
326 05:58:59.480857 S7: 0000 0000 [0000]
327 05:58:59.480919
328 05:58:59.484074 CC: 0000 0000 [0001]
329 05:58:59.484163
330 05:58:59.484230 T0: 0000 0040 [010F]
331 05:58:59.484293
332 05:58:59.484353 Jump to BL
333 05:58:59.487450
334 05:58:59.510700
335 05:58:59.510852
336 05:58:59.510922
337 05:58:59.517765 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 05:58:59.521379 ARM64: Exception handlers installed.
339 05:58:59.525144 ARM64: Testing exception
340 05:58:59.528368 ARM64: Done test exception
341 05:58:59.535107 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 05:58:59.545311 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 05:58:59.552223 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 05:58:59.561916 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 05:58:59.568386 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 05:58:59.578379 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 05:58:59.588925 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 05:58:59.595812 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 05:58:59.613670 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 05:58:59.617063 WDT: Last reset was cold boot
351 05:58:59.620085 SPI1(PAD0) initialized at 2873684 Hz
352 05:58:59.623500 SPI5(PAD0) initialized at 992727 Hz
353 05:58:59.627020 VBOOT: Loading verstage.
354 05:58:59.633560 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 05:58:59.636799 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 05:58:59.640358 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 05:58:59.643811 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 05:58:59.650920 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 05:58:59.658005 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 05:58:59.668919 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 05:58:59.669047
362 05:58:59.669112
363 05:58:59.678910 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 05:58:59.681752 ARM64: Exception handlers installed.
365 05:58:59.685128 ARM64: Testing exception
366 05:58:59.685239 ARM64: Done test exception
367 05:58:59.692253 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 05:58:59.695832 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 05:58:59.709643 Probing TPM: . done!
370 05:58:59.709788 TPM ready after 0 ms
371 05:58:59.716587 Connected to device vid:did:rid of 1ae0:0028:00
372 05:58:59.723635 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 05:58:59.763485 Initialized TPM device CR50 revision 0
374 05:58:59.774924 tlcl_send_startup: Startup return code is 0
375 05:58:59.775076 TPM: setup succeeded
376 05:58:59.786307 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 05:58:59.795444 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 05:58:59.806867 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 05:58:59.816674 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 05:58:59.819825 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 05:58:59.823885 in-header: 03 07 00 00 08 00 00 00
382 05:58:59.827403 in-data: aa e4 47 04 13 02 00 00
383 05:58:59.831049 Chrome EC: UHEPI supported
384 05:58:59.838246 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 05:58:59.841788 in-header: 03 9d 00 00 08 00 00 00
386 05:58:59.845345 in-data: 10 20 20 08 00 00 00 00
387 05:58:59.845430 Phase 1
388 05:58:59.848958 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 05:58:59.856391 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 05:58:59.863148 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 05:58:59.863273 Recovery requested (1009000e)
392 05:58:59.872026 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 05:58:59.877811 tlcl_extend: response is 0
394 05:58:59.885544 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 05:58:59.890834 tlcl_extend: response is 0
396 05:58:59.897357 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 05:58:59.918716 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 05:58:59.926065 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 05:58:59.926184
400 05:58:59.926252
401 05:58:59.933821 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 05:58:59.937363 ARM64: Exception handlers installed.
403 05:58:59.940902 ARM64: Testing exception
404 05:58:59.944026 ARM64: Done test exception
405 05:58:59.963686 pmic_efuse_setting: Set efuses in 11 msecs
406 05:58:59.967485 pmwrap_interface_init: Select PMIF_VLD_RDY
407 05:58:59.971582 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 05:58:59.978520 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 05:58:59.982574 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 05:58:59.986086 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 05:58:59.993286 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 05:58:59.996709 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 05:59:00.000262 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 05:59:00.007578 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 05:59:00.011028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 05:59:00.014541 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 05:59:00.020960 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 05:59:00.024529 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 05:59:00.030981 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 05:59:00.034737 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 05:59:00.041113 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 05:59:00.048076 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 05:59:00.054630 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 05:59:00.057903 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 05:59:00.065010 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 05:59:00.068481 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 05:59:00.075935 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 05:59:00.080377 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 05:59:00.086502 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 05:59:00.094019 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 05:59:00.096972 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 05:59:00.103542 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 05:59:00.107633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 05:59:00.111353 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 05:59:00.118268 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 05:59:00.121926 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 05:59:00.129058 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 05:59:00.133075 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 05:59:00.136493 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 05:59:00.144178 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 05:59:00.147820 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 05:59:00.151516 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 05:59:00.158026 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 05:59:00.161349 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 05:59:00.168235 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 05:59:00.171641 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 05:59:00.174708 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 05:59:00.181534 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 05:59:00.184727 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 05:59:00.188082 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 05:59:00.194919 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 05:59:00.198454 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 05:59:00.201369 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 05:59:00.204802 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 05:59:00.211343 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 05:59:00.214947 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 05:59:00.218398 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 05:59:00.227972 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 05:59:00.235070 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 05:59:00.238070 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 05:59:00.248157 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 05:59:00.254934 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 05:59:00.261472 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 05:59:00.264725 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 05:59:00.268077 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 05:59:00.276557 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 05:59:00.282733 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 05:59:00.286025 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 05:59:00.289650 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 05:59:00.301170 [RTC]rtc_get_frequency_meter,154: input=15, output=792
471 05:59:00.304080 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 05:59:00.311201 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 05:59:00.314172 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 05:59:00.317734 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 05:59:00.320676 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 05:59:00.324339 ADC[4]: Raw value=896300 ID=7
477 05:59:00.327819 ADC[3]: Raw value=213440 ID=1
478 05:59:00.330748 RAM Code: 0x71
479 05:59:00.334338 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 05:59:00.337774 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 05:59:00.347871 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 05:59:00.354920 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 05:59:00.358496 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 05:59:00.361767 in-header: 03 07 00 00 08 00 00 00
485 05:59:00.364951 in-data: aa e4 47 04 13 02 00 00
486 05:59:00.365043 Chrome EC: UHEPI supported
487 05:59:00.371837 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 05:59:00.375762 in-header: 03 d5 00 00 08 00 00 00
489 05:59:00.379376 in-data: 98 20 60 08 00 00 00 00
490 05:59:00.383230 MRC: failed to locate region type 0.
491 05:59:00.390601 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 05:59:00.394020 DRAM-K: Running full calibration
493 05:59:00.400707 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 05:59:00.400827 header.status = 0x0
495 05:59:00.403932 header.version = 0x6 (expected: 0x6)
496 05:59:00.407525 header.size = 0xd00 (expected: 0xd00)
497 05:59:00.410545 header.flags = 0x0
498 05:59:00.414363 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 05:59:00.433430 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
500 05:59:00.439883 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 05:59:00.443441 dram_init: ddr_geometry: 2
502 05:59:00.446409 [EMI] MDL number = 2
503 05:59:00.446498 [EMI] Get MDL freq = 0
504 05:59:00.449800 dram_init: ddr_type: 0
505 05:59:00.449887 is_discrete_lpddr4: 1
506 05:59:00.453354 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 05:59:00.453442
508 05:59:00.453519
509 05:59:00.456341 [Bian_co] ETT version 0.0.0.1
510 05:59:00.463328 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 05:59:00.463429
512 05:59:00.466783 dramc_set_vcore_voltage set vcore to 650000
513 05:59:00.466871 Read voltage for 800, 4
514 05:59:00.469958 Vio18 = 0
515 05:59:00.470046 Vcore = 650000
516 05:59:00.470113 Vdram = 0
517 05:59:00.473372 Vddq = 0
518 05:59:00.473456 Vmddr = 0
519 05:59:00.476160 dram_init: config_dvfs: 1
520 05:59:00.479615 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 05:59:00.486631 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 05:59:00.489406 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 05:59:00.492960 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 05:59:00.496197 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 05:59:00.499867 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 05:59:00.502924 MEM_TYPE=3, freq_sel=18
527 05:59:00.506494 sv_algorithm_assistance_LP4_1600
528 05:59:00.509682 ============ PULL DRAM RESETB DOWN ============
529 05:59:00.513150 ========== PULL DRAM RESETB DOWN end =========
530 05:59:00.519727 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 05:59:00.522918 ===================================
532 05:59:00.526148 LPDDR4 DRAM CONFIGURATION
533 05:59:00.530062 ===================================
534 05:59:00.530153 EX_ROW_EN[0] = 0x0
535 05:59:00.532973 EX_ROW_EN[1] = 0x0
536 05:59:00.533049 LP4Y_EN = 0x0
537 05:59:00.536516 WORK_FSP = 0x0
538 05:59:00.536598 WL = 0x2
539 05:59:00.539795 RL = 0x2
540 05:59:00.539871 BL = 0x2
541 05:59:00.542809 RPST = 0x0
542 05:59:00.542883 RD_PRE = 0x0
543 05:59:00.546255 WR_PRE = 0x1
544 05:59:00.546326 WR_PST = 0x0
545 05:59:00.549787 DBI_WR = 0x0
546 05:59:00.549869 DBI_RD = 0x0
547 05:59:00.552807 OTF = 0x1
548 05:59:00.556207 ===================================
549 05:59:00.559696 ===================================
550 05:59:00.559773 ANA top config
551 05:59:00.563242 ===================================
552 05:59:00.566144 DLL_ASYNC_EN = 0
553 05:59:00.569624 ALL_SLAVE_EN = 1
554 05:59:00.572997 NEW_RANK_MODE = 1
555 05:59:00.573076 DLL_IDLE_MODE = 1
556 05:59:00.576117 LP45_APHY_COMB_EN = 1
557 05:59:00.579363 TX_ODT_DIS = 1
558 05:59:00.582881 NEW_8X_MODE = 1
559 05:59:00.585842 ===================================
560 05:59:00.589394 ===================================
561 05:59:00.592867 data_rate = 1600
562 05:59:00.596370 CKR = 1
563 05:59:00.596461 DQ_P2S_RATIO = 8
564 05:59:00.599522 ===================================
565 05:59:00.603074 CA_P2S_RATIO = 8
566 05:59:00.606525 DQ_CA_OPEN = 0
567 05:59:00.609879 DQ_SEMI_OPEN = 0
568 05:59:00.609978 CA_SEMI_OPEN = 0
569 05:59:00.613436 CA_FULL_RATE = 0
570 05:59:00.617286 DQ_CKDIV4_EN = 1
571 05:59:00.621287 CA_CKDIV4_EN = 1
572 05:59:00.621400 CA_PREDIV_EN = 0
573 05:59:00.625112 PH8_DLY = 0
574 05:59:00.628866 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 05:59:00.632424 DQ_AAMCK_DIV = 4
576 05:59:00.632523 CA_AAMCK_DIV = 4
577 05:59:00.636572 CA_ADMCK_DIV = 4
578 05:59:00.639799 DQ_TRACK_CA_EN = 0
579 05:59:00.643661 CA_PICK = 800
580 05:59:00.643765 CA_MCKIO = 800
581 05:59:00.647428 MCKIO_SEMI = 0
582 05:59:00.651054 PLL_FREQ = 3068
583 05:59:00.654512 DQ_UI_PI_RATIO = 32
584 05:59:00.658676 CA_UI_PI_RATIO = 0
585 05:59:00.658772 ===================================
586 05:59:00.662127 ===================================
587 05:59:00.666384 memory_type:LPDDR4
588 05:59:00.666483 GP_NUM : 10
589 05:59:00.669871 SRAM_EN : 1
590 05:59:00.672861 MD32_EN : 0
591 05:59:00.672953 ===================================
592 05:59:00.676929 [ANA_INIT] >>>>>>>>>>>>>>
593 05:59:00.680460 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 05:59:00.684173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 05:59:00.687860 ===================================
596 05:59:00.687960 data_rate = 1600,PCW = 0X7600
597 05:59:00.691997 ===================================
598 05:59:00.695036 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 05:59:00.701961 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 05:59:00.708491 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 05:59:00.711878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 05:59:00.715393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 05:59:00.718895 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 05:59:00.718985 [ANA_INIT] flow start
605 05:59:00.722738 [ANA_INIT] PLL >>>>>>>>
606 05:59:00.726600 [ANA_INIT] PLL <<<<<<<<
607 05:59:00.726694 [ANA_INIT] MIDPI >>>>>>>>
608 05:59:00.729896 [ANA_INIT] MIDPI <<<<<<<<
609 05:59:00.733591 [ANA_INIT] DLL >>>>>>>>
610 05:59:00.733680 [ANA_INIT] flow end
611 05:59:00.737077 ============ LP4 DIFF to SE enter ============
612 05:59:00.740825 ============ LP4 DIFF to SE exit ============
613 05:59:00.744358 [ANA_INIT] <<<<<<<<<<<<<
614 05:59:00.747903 [Flow] Enable top DCM control >>>>>
615 05:59:00.751873 [Flow] Enable top DCM control <<<<<
616 05:59:00.755760 Enable DLL master slave shuffle
617 05:59:00.758858 ==============================================================
618 05:59:00.762391 Gating Mode config
619 05:59:00.765919 ==============================================================
620 05:59:00.768940 Config description:
621 05:59:00.778839 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 05:59:00.786025 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 05:59:00.788796 SELPH_MODE 0: By rank 1: By Phase
624 05:59:00.795801 ==============================================================
625 05:59:00.798814 GAT_TRACK_EN = 1
626 05:59:00.802572 RX_GATING_MODE = 2
627 05:59:00.805409 RX_GATING_TRACK_MODE = 2
628 05:59:00.808965 SELPH_MODE = 1
629 05:59:00.809045 PICG_EARLY_EN = 1
630 05:59:00.812215 VALID_LAT_VALUE = 1
631 05:59:00.818932 ==============================================================
632 05:59:00.822212 Enter into Gating configuration >>>>
633 05:59:00.825258 Exit from Gating configuration <<<<
634 05:59:00.828647 Enter into DVFS_PRE_config >>>>>
635 05:59:00.838569 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 05:59:00.841984 Exit from DVFS_PRE_config <<<<<
637 05:59:00.845505 Enter into PICG configuration >>>>
638 05:59:00.848633 Exit from PICG configuration <<<<
639 05:59:00.852051 [RX_INPUT] configuration >>>>>
640 05:59:00.855539 [RX_INPUT] configuration <<<<<
641 05:59:00.859045 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 05:59:00.865246 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 05:59:00.875439 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 05:59:00.878579 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 05:59:00.885815 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 05:59:00.888638 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 05:59:00.895195 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 05:59:00.898407 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 05:59:00.901950 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 05:59:00.905548 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 05:59:00.912669 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 05:59:00.916109 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 05:59:00.920107 ===================================
654 05:59:00.920225 LPDDR4 DRAM CONFIGURATION
655 05:59:00.923424 ===================================
656 05:59:00.927004 EX_ROW_EN[0] = 0x0
657 05:59:00.927098 EX_ROW_EN[1] = 0x0
658 05:59:00.931126 LP4Y_EN = 0x0
659 05:59:00.931218 WORK_FSP = 0x0
660 05:59:00.934554 WL = 0x2
661 05:59:00.934641 RL = 0x2
662 05:59:00.937962 BL = 0x2
663 05:59:00.938050 RPST = 0x0
664 05:59:00.941617 RD_PRE = 0x0
665 05:59:00.941705 WR_PRE = 0x1
666 05:59:00.945730 WR_PST = 0x0
667 05:59:00.945820 DBI_WR = 0x0
668 05:59:00.945888 DBI_RD = 0x0
669 05:59:00.948740 OTF = 0x1
670 05:59:00.952383 ===================================
671 05:59:00.956264 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 05:59:00.959662 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 05:59:00.966457 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 05:59:00.966577 ===================================
675 05:59:00.970066 LPDDR4 DRAM CONFIGURATION
676 05:59:00.973600 ===================================
677 05:59:00.977139 EX_ROW_EN[0] = 0x10
678 05:59:00.977259 EX_ROW_EN[1] = 0x0
679 05:59:00.981073 LP4Y_EN = 0x0
680 05:59:00.981277 WORK_FSP = 0x0
681 05:59:00.984767 WL = 0x2
682 05:59:00.984876 RL = 0x2
683 05:59:00.984978 BL = 0x2
684 05:59:00.988442 RPST = 0x0
685 05:59:00.988531 RD_PRE = 0x0
686 05:59:00.991862 WR_PRE = 0x1
687 05:59:00.991950 WR_PST = 0x0
688 05:59:00.996082 DBI_WR = 0x0
689 05:59:00.996171 DBI_RD = 0x0
690 05:59:00.999723 OTF = 0x1
691 05:59:01.003337 ===================================
692 05:59:01.006524 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 05:59:01.011939 nWR fixed to 40
694 05:59:01.015972 [ModeRegInit_LP4] CH0 RK0
695 05:59:01.016069 [ModeRegInit_LP4] CH0 RK1
696 05:59:01.019581 [ModeRegInit_LP4] CH1 RK0
697 05:59:01.019694 [ModeRegInit_LP4] CH1 RK1
698 05:59:01.023627 match AC timing 13
699 05:59:01.027773 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 05:59:01.031071 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 05:59:01.034814 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 05:59:01.042195 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 05:59:01.045878 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 05:59:01.046001 [EMI DOE] emi_dcm 0
705 05:59:01.050073 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 05:59:01.050170 ==
707 05:59:01.053685 Dram Type= 6, Freq= 0, CH_0, rank 0
708 05:59:01.057088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 05:59:01.057186 ==
710 05:59:01.064898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 05:59:01.071661 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 05:59:01.079883 [CA 0] Center 38 (7~69) winsize 63
713 05:59:01.083462 [CA 1] Center 37 (7~68) winsize 62
714 05:59:01.086885 [CA 2] Center 35 (5~66) winsize 62
715 05:59:01.090407 [CA 3] Center 35 (5~66) winsize 62
716 05:59:01.094363 [CA 4] Center 34 (4~65) winsize 62
717 05:59:01.098119 [CA 5] Center 34 (4~65) winsize 62
718 05:59:01.098216
719 05:59:01.101350 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 05:59:01.101465
721 05:59:01.104948 [CATrainingPosCal] consider 1 rank data
722 05:59:01.105037 u2DelayCellTimex100 = 270/100 ps
723 05:59:01.108912 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 05:59:01.112459 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 05:59:01.120139 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 05:59:01.120256 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 05:59:01.123514 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 05:59:01.127168 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 05:59:01.127261
730 05:59:01.130713 CA PerBit enable=1, Macro0, CA PI delay=34
731 05:59:01.134904
732 05:59:01.134997 [CBTSetCACLKResult] CA Dly = 34
733 05:59:01.138599 CS Dly: 6 (0~37)
734 05:59:01.138678 ==
735 05:59:01.141885 Dram Type= 6, Freq= 0, CH_0, rank 1
736 05:59:01.145944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 05:59:01.146032 ==
738 05:59:01.149757 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 05:59:01.156185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 05:59:01.165652 [CA 0] Center 38 (7~69) winsize 63
741 05:59:01.169197 [CA 1] Center 38 (7~69) winsize 63
742 05:59:01.173353 [CA 2] Center 35 (5~66) winsize 62
743 05:59:01.176887 [CA 3] Center 35 (5~66) winsize 62
744 05:59:01.180539 [CA 4] Center 34 (4~65) winsize 62
745 05:59:01.180683 [CA 5] Center 34 (4~65) winsize 62
746 05:59:01.184422
747 05:59:01.184519 [CmdBusTrainingLP45] Vref(ca) range 1: 32
748 05:59:01.188495
749 05:59:01.188587 [CATrainingPosCal] consider 2 rank data
750 05:59:01.191735 u2DelayCellTimex100 = 270/100 ps
751 05:59:01.195890 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 05:59:01.198942 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 05:59:01.203007 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 05:59:01.206343 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 05:59:01.209440 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 05:59:01.216097 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 05:59:01.216206
758 05:59:01.219674 CA PerBit enable=1, Macro0, CA PI delay=34
759 05:59:01.219751
760 05:59:01.222952 [CBTSetCACLKResult] CA Dly = 34
761 05:59:01.223034 CS Dly: 6 (0~37)
762 05:59:01.223096
763 05:59:01.225948 ----->DramcWriteLeveling(PI) begin...
764 05:59:01.226031 ==
765 05:59:01.229392 Dram Type= 6, Freq= 0, CH_0, rank 0
766 05:59:01.232927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 05:59:01.236456 ==
768 05:59:01.236540 Write leveling (Byte 0): 32 => 32
769 05:59:01.239368 Write leveling (Byte 1): 28 => 28
770 05:59:01.243032 DramcWriteLeveling(PI) end<-----
771 05:59:01.243106
772 05:59:01.243167 ==
773 05:59:01.245897 Dram Type= 6, Freq= 0, CH_0, rank 0
774 05:59:01.252506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 05:59:01.252623 ==
776 05:59:01.255906 [Gating] SW mode calibration
777 05:59:01.262493 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 05:59:01.265992 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 05:59:01.269449 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 05:59:01.276034 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 05:59:01.279631 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
782 05:59:01.282781 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 05:59:01.289447 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 05:59:01.292877 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 05:59:01.296155 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 05:59:01.302418 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 05:59:01.306026 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 05:59:01.310339 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 05:59:01.313867 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 05:59:01.321407 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 05:59:01.324753 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 05:59:01.327665 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 05:59:01.331514 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 05:59:01.338341 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 05:59:01.342028 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 05:59:01.345010 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 05:59:01.352127 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
798 05:59:01.355055 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 05:59:01.358436 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 05:59:01.361649 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 05:59:01.368576 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 05:59:01.371850 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 05:59:01.375351 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 05:59:01.381897 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 05:59:01.385446 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 05:59:01.388965 0 9 12 | B1->B0 | 2626 3333 | 1 0 | (1 1) (0 0)
807 05:59:01.395587 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 05:59:01.398926 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 05:59:01.402215 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 05:59:01.408988 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 05:59:01.411798 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 05:59:01.415385 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 05:59:01.421885 0 10 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
814 05:59:01.425419 0 10 12 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
815 05:59:01.428427 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 05:59:01.435001 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 05:59:01.438706 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 05:59:01.442088 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 05:59:01.448605 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 05:59:01.452097 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 05:59:01.455100 0 11 8 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (1 1)
822 05:59:01.458594 0 11 12 | B1->B0 | 3333 4444 | 0 1 | (0 0) (0 0)
823 05:59:01.465093 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 05:59:01.468582 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 05:59:01.471983 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 05:59:01.478391 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 05:59:01.481535 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 05:59:01.485042 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 05:59:01.492025 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 05:59:01.494939 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 05:59:01.498238 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 05:59:01.504841 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 05:59:01.508381 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 05:59:01.511675 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 05:59:01.518731 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 05:59:01.521541 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 05:59:01.525056 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 05:59:01.531532 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 05:59:01.535143 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 05:59:01.538536 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 05:59:01.545595 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 05:59:01.548302 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 05:59:01.552041 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 05:59:01.555098 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 05:59:01.561756 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
846 05:59:01.565668 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 05:59:01.568886 Total UI for P1: 0, mck2ui 16
848 05:59:01.572158 best dqsien dly found for B0: ( 0, 14, 8)
849 05:59:01.575191 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 05:59:01.578612 Total UI for P1: 0, mck2ui 16
851 05:59:01.582097 best dqsien dly found for B1: ( 0, 14, 10)
852 05:59:01.585735 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
853 05:59:01.588934 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
854 05:59:01.589024
855 05:59:01.595163 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
856 05:59:01.598678 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
857 05:59:01.598872 [Gating] SW calibration Done
858 05:59:01.602099 ==
859 05:59:01.605616 Dram Type= 6, Freq= 0, CH_0, rank 0
860 05:59:01.608731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 05:59:01.608822 ==
862 05:59:01.608889 RX Vref Scan: 0
863 05:59:01.608953
864 05:59:01.612124 RX Vref 0 -> 0, step: 1
865 05:59:01.612211
866 05:59:01.615436 RX Delay -130 -> 252, step: 16
867 05:59:01.618759 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
868 05:59:01.622413 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 05:59:01.628806 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 05:59:01.632125 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
871 05:59:01.635108 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
872 05:59:01.638656 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 05:59:01.642220 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 05:59:01.645101 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 05:59:01.652152 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 05:59:01.655061 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
877 05:59:01.658709 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 05:59:01.661658 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 05:59:01.665043 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 05:59:01.671819 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 05:59:01.675290 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 05:59:01.678655 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 05:59:01.678744 ==
884 05:59:01.681926 Dram Type= 6, Freq= 0, CH_0, rank 0
885 05:59:01.685097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 05:59:01.688589 ==
887 05:59:01.688683 DQS Delay:
888 05:59:01.688751 DQS0 = 0, DQS1 = 0
889 05:59:01.691784 DQM Delay:
890 05:59:01.691869 DQM0 = 79, DQM1 = 70
891 05:59:01.691935 DQ Delay:
892 05:59:01.695113 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
893 05:59:01.698459 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
894 05:59:01.702287 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
895 05:59:01.705218 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 05:59:01.705306
897 05:59:01.705373
898 05:59:01.708704 ==
899 05:59:01.712663 Dram Type= 6, Freq= 0, CH_0, rank 0
900 05:59:01.715864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 05:59:01.715955 ==
902 05:59:01.716022
903 05:59:01.716084
904 05:59:01.716144 TX Vref Scan disable
905 05:59:01.719616 == TX Byte 0 ==
906 05:59:01.722988 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
907 05:59:01.726388 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
908 05:59:01.729376 == TX Byte 1 ==
909 05:59:01.732847 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
910 05:59:01.736456 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
911 05:59:01.739313 ==
912 05:59:01.742811 Dram Type= 6, Freq= 0, CH_0, rank 0
913 05:59:01.745807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 05:59:01.745894 ==
915 05:59:01.758723 TX Vref=22, minBit 11, minWin=26, winSum=433
916 05:59:01.762351 TX Vref=24, minBit 0, minWin=27, winSum=438
917 05:59:01.765942 TX Vref=26, minBit 2, minWin=27, winSum=445
918 05:59:01.768792 TX Vref=28, minBit 5, minWin=27, winSum=445
919 05:59:01.772405 TX Vref=30, minBit 11, minWin=27, winSum=444
920 05:59:01.779003 TX Vref=32, minBit 4, minWin=27, winSum=442
921 05:59:01.782382 [TxChooseVref] Worse bit 2, Min win 27, Win sum 445, Final Vref 26
922 05:59:01.782485
923 05:59:01.785764 Final TX Range 1 Vref 26
924 05:59:01.785852
925 05:59:01.785918 ==
926 05:59:01.788810 Dram Type= 6, Freq= 0, CH_0, rank 0
927 05:59:01.792042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 05:59:01.792130 ==
929 05:59:01.795643
930 05:59:01.795728
931 05:59:01.795795 TX Vref Scan disable
932 05:59:01.799127 == TX Byte 0 ==
933 05:59:01.802499 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
934 05:59:01.809193 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
935 05:59:01.809294 == TX Byte 1 ==
936 05:59:01.812285 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
937 05:59:01.818935 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
938 05:59:01.819032
939 05:59:01.819100 [DATLAT]
940 05:59:01.819161 Freq=800, CH0 RK0
941 05:59:01.819221
942 05:59:01.822555 DATLAT Default: 0xa
943 05:59:01.822643 0, 0xFFFF, sum = 0
944 05:59:01.825601 1, 0xFFFF, sum = 0
945 05:59:01.825692 2, 0xFFFF, sum = 0
946 05:59:01.829070 3, 0xFFFF, sum = 0
947 05:59:01.832536 4, 0xFFFF, sum = 0
948 05:59:01.832624 5, 0xFFFF, sum = 0
949 05:59:01.835492 6, 0xFFFF, sum = 0
950 05:59:01.835577 7, 0xFFFF, sum = 0
951 05:59:01.838968 8, 0xFFFF, sum = 0
952 05:59:01.839054 9, 0x0, sum = 1
953 05:59:01.839122 10, 0x0, sum = 2
954 05:59:01.842349 11, 0x0, sum = 3
955 05:59:01.842433 12, 0x0, sum = 4
956 05:59:01.845856 best_step = 10
957 05:59:01.845940
958 05:59:01.846005 ==
959 05:59:01.848844 Dram Type= 6, Freq= 0, CH_0, rank 0
960 05:59:01.852290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 05:59:01.852375 ==
962 05:59:01.855869 RX Vref Scan: 1
963 05:59:01.855953
964 05:59:01.856019 Set Vref Range= 32 -> 127
965 05:59:01.858804
966 05:59:01.858886 RX Vref 32 -> 127, step: 1
967 05:59:01.858951
968 05:59:01.862385 RX Delay -111 -> 252, step: 8
969 05:59:01.862467
970 05:59:01.865949 Set Vref, RX VrefLevel [Byte0]: 32
971 05:59:01.868805 [Byte1]: 32
972 05:59:01.868888
973 05:59:01.872378 Set Vref, RX VrefLevel [Byte0]: 33
974 05:59:01.875292 [Byte1]: 33
975 05:59:01.879866
976 05:59:01.879953 Set Vref, RX VrefLevel [Byte0]: 34
977 05:59:01.882826 [Byte1]: 34
978 05:59:01.887004
979 05:59:01.887094 Set Vref, RX VrefLevel [Byte0]: 35
980 05:59:01.890463 [Byte1]: 35
981 05:59:01.894958
982 05:59:01.895045 Set Vref, RX VrefLevel [Byte0]: 36
983 05:59:01.897993 [Byte1]: 36
984 05:59:01.902612
985 05:59:01.902702 Set Vref, RX VrefLevel [Byte0]: 37
986 05:59:01.906074 [Byte1]: 37
987 05:59:01.910249
988 05:59:01.910337 Set Vref, RX VrefLevel [Byte0]: 38
989 05:59:01.913811 [Byte1]: 38
990 05:59:01.917820
991 05:59:01.917906 Set Vref, RX VrefLevel [Byte0]: 39
992 05:59:01.920873 [Byte1]: 39
993 05:59:01.925441
994 05:59:01.925583 Set Vref, RX VrefLevel [Byte0]: 40
995 05:59:01.928986 [Byte1]: 40
996 05:59:01.932936
997 05:59:01.933026 Set Vref, RX VrefLevel [Byte0]: 41
998 05:59:01.936348 [Byte1]: 41
999 05:59:01.940564
1000 05:59:01.940654 Set Vref, RX VrefLevel [Byte0]: 42
1001 05:59:01.944088 [Byte1]: 42
1002 05:59:01.948185
1003 05:59:01.948272 Set Vref, RX VrefLevel [Byte0]: 43
1004 05:59:01.951778 [Byte1]: 43
1005 05:59:01.955928
1006 05:59:01.956024 Set Vref, RX VrefLevel [Byte0]: 44
1007 05:59:01.959191 [Byte1]: 44
1008 05:59:01.963781
1009 05:59:01.963872 Set Vref, RX VrefLevel [Byte0]: 45
1010 05:59:01.967202 [Byte1]: 45
1011 05:59:01.971618
1012 05:59:01.971706 Set Vref, RX VrefLevel [Byte0]: 46
1013 05:59:01.974914 [Byte1]: 46
1014 05:59:01.979121
1015 05:59:01.979217 Set Vref, RX VrefLevel [Byte0]: 47
1016 05:59:01.982848 [Byte1]: 47
1017 05:59:01.986910
1018 05:59:01.987007 Set Vref, RX VrefLevel [Byte0]: 48
1019 05:59:01.989890 [Byte1]: 48
1020 05:59:01.994493
1021 05:59:01.994585 Set Vref, RX VrefLevel [Byte0]: 49
1022 05:59:01.998028 [Byte1]: 49
1023 05:59:02.002049
1024 05:59:02.002141 Set Vref, RX VrefLevel [Byte0]: 50
1025 05:59:02.005619 [Byte1]: 50
1026 05:59:02.009454
1027 05:59:02.009581 Set Vref, RX VrefLevel [Byte0]: 51
1028 05:59:02.012922 [Byte1]: 51
1029 05:59:02.017115
1030 05:59:02.017200 Set Vref, RX VrefLevel [Byte0]: 52
1031 05:59:02.020528 [Byte1]: 52
1032 05:59:02.024671
1033 05:59:02.024753 Set Vref, RX VrefLevel [Byte0]: 53
1034 05:59:02.028179 [Byte1]: 53
1035 05:59:02.032368
1036 05:59:02.032454 Set Vref, RX VrefLevel [Byte0]: 54
1037 05:59:02.035559 [Byte1]: 54
1038 05:59:02.040371
1039 05:59:02.040464 Set Vref, RX VrefLevel [Byte0]: 55
1040 05:59:02.043186 [Byte1]: 55
1041 05:59:02.048022
1042 05:59:02.048114 Set Vref, RX VrefLevel [Byte0]: 56
1043 05:59:02.050984 [Byte1]: 56
1044 05:59:02.055556
1045 05:59:02.055644 Set Vref, RX VrefLevel [Byte0]: 57
1046 05:59:02.058537 [Byte1]: 57
1047 05:59:02.062917
1048 05:59:02.063004 Set Vref, RX VrefLevel [Byte0]: 58
1049 05:59:02.066501 [Byte1]: 58
1050 05:59:02.070938
1051 05:59:02.071026 Set Vref, RX VrefLevel [Byte0]: 59
1052 05:59:02.073782 [Byte1]: 59
1053 05:59:02.078296
1054 05:59:02.078383 Set Vref, RX VrefLevel [Byte0]: 60
1055 05:59:02.081756 [Byte1]: 60
1056 05:59:02.086106
1057 05:59:02.086202 Set Vref, RX VrefLevel [Byte0]: 61
1058 05:59:02.089112 [Byte1]: 61
1059 05:59:02.093441
1060 05:59:02.093567 Set Vref, RX VrefLevel [Byte0]: 62
1061 05:59:02.096797 [Byte1]: 62
1062 05:59:02.101183
1063 05:59:02.101273 Set Vref, RX VrefLevel [Byte0]: 63
1064 05:59:02.104678 [Byte1]: 63
1065 05:59:02.108805
1066 05:59:02.108898 Set Vref, RX VrefLevel [Byte0]: 64
1067 05:59:02.112434 [Byte1]: 64
1068 05:59:02.116679
1069 05:59:02.116770 Set Vref, RX VrefLevel [Byte0]: 65
1070 05:59:02.119682 [Byte1]: 65
1071 05:59:02.124296
1072 05:59:02.124385 Set Vref, RX VrefLevel [Byte0]: 66
1073 05:59:02.127391 [Byte1]: 66
1074 05:59:02.132093
1075 05:59:02.132182 Set Vref, RX VrefLevel [Byte0]: 67
1076 05:59:02.134914 [Byte1]: 67
1077 05:59:02.139601
1078 05:59:02.139691 Set Vref, RX VrefLevel [Byte0]: 68
1079 05:59:02.142584 [Byte1]: 68
1080 05:59:02.147227
1081 05:59:02.150129 Set Vref, RX VrefLevel [Byte0]: 69
1082 05:59:02.150218 [Byte1]: 69
1083 05:59:02.154890
1084 05:59:02.154977 Set Vref, RX VrefLevel [Byte0]: 70
1085 05:59:02.157873 [Byte1]: 70
1086 05:59:02.162528
1087 05:59:02.162613 Set Vref, RX VrefLevel [Byte0]: 71
1088 05:59:02.165449 [Byte1]: 71
1089 05:59:02.170045
1090 05:59:02.170132 Set Vref, RX VrefLevel [Byte0]: 72
1091 05:59:02.173509 [Byte1]: 72
1092 05:59:02.177926
1093 05:59:02.178015 Set Vref, RX VrefLevel [Byte0]: 73
1094 05:59:02.180816 [Byte1]: 73
1095 05:59:02.185472
1096 05:59:02.185607 Set Vref, RX VrefLevel [Byte0]: 74
1097 05:59:02.188662 [Byte1]: 74
1098 05:59:02.192731
1099 05:59:02.192819 Set Vref, RX VrefLevel [Byte0]: 75
1100 05:59:02.196347 [Byte1]: 75
1101 05:59:02.200873
1102 05:59:02.200968 Set Vref, RX VrefLevel [Byte0]: 76
1103 05:59:02.204496 [Byte1]: 76
1104 05:59:02.208061
1105 05:59:02.208153 Set Vref, RX VrefLevel [Byte0]: 77
1106 05:59:02.211701 [Byte1]: 77
1107 05:59:02.215897
1108 05:59:02.215991 Set Vref, RX VrefLevel [Byte0]: 78
1109 05:59:02.219508 [Byte1]: 78
1110 05:59:02.223400
1111 05:59:02.223500 Set Vref, RX VrefLevel [Byte0]: 79
1112 05:59:02.227174 [Byte1]: 79
1113 05:59:02.231224
1114 05:59:02.231320 Final RX Vref Byte 0 = 57 to rank0
1115 05:59:02.234883 Final RX Vref Byte 1 = 59 to rank0
1116 05:59:02.237896 Final RX Vref Byte 0 = 57 to rank1
1117 05:59:02.240976 Final RX Vref Byte 1 = 59 to rank1==
1118 05:59:02.244407 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 05:59:02.251232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 05:59:02.251345 ==
1121 05:59:02.251412 DQS Delay:
1122 05:59:02.251472 DQS0 = 0, DQS1 = 0
1123 05:59:02.254888 DQM Delay:
1124 05:59:02.254976 DQM0 = 82, DQM1 = 68
1125 05:59:02.257684 DQ Delay:
1126 05:59:02.261183 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1127 05:59:02.261268 DQ4 =84, DQ5 =68, DQ6 =88, DQ7 =92
1128 05:59:02.264709 DQ8 =64, DQ9 =56, DQ10 =68, DQ11 =60
1129 05:59:02.268356 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1130 05:59:02.271103
1131 05:59:02.271189
1132 05:59:02.277920 [DQSOSCAuto] RK0, (LSB)MR18= 0x2121, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1133 05:59:02.281256 CH0 RK0: MR19=606, MR18=2121
1134 05:59:02.288173 CH0_RK0: MR19=0x606, MR18=0x2121, DQSOSC=401, MR23=63, INC=91, DEC=61
1135 05:59:02.288292
1136 05:59:02.291166 ----->DramcWriteLeveling(PI) begin...
1137 05:59:02.291251 ==
1138 05:59:02.294653 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 05:59:02.297900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 05:59:02.297989 ==
1141 05:59:02.301144 Write leveling (Byte 0): 32 => 32
1142 05:59:02.304490 Write leveling (Byte 1): 32 => 32
1143 05:59:02.308071 DramcWriteLeveling(PI) end<-----
1144 05:59:02.308167
1145 05:59:02.308233 ==
1146 05:59:02.311409 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 05:59:02.314532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 05:59:02.314626 ==
1149 05:59:02.318218 [Gating] SW mode calibration
1150 05:59:02.324702 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 05:59:02.331090 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 05:59:02.334691 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 05:59:02.337887 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1154 05:59:02.344446 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1155 05:59:02.347916 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 05:59:02.351384 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 05:59:02.358307 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 05:59:02.361222 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 05:59:02.364778 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 05:59:02.371226 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 05:59:02.374705 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 05:59:02.377613 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 05:59:02.384348 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 05:59:02.428417 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 05:59:02.428623 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 05:59:02.428726 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 05:59:02.429022 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 05:59:02.429120 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 05:59:02.429422 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1170 05:59:02.429939 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1171 05:59:02.430052 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 05:59:02.430337 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 05:59:02.430436 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 05:59:02.471823 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 05:59:02.472018 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 05:59:02.472373 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 05:59:02.472691 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 05:59:02.472791 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1179 05:59:02.472907 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1180 05:59:02.473018 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 05:59:02.473125 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 05:59:02.473218 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 05:59:02.473329 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 05:59:02.476543 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 05:59:02.479936 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
1186 05:59:02.483355 0 10 8 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)
1187 05:59:02.489702 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1188 05:59:02.493037 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 05:59:02.496666 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 05:59:02.499620 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 05:59:02.506698 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 05:59:02.509660 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 05:59:02.513183 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
1194 05:59:02.520000 0 11 8 | B1->B0 | 2a2a 3a3a | 0 1 | (0 0) (0 0)
1195 05:59:02.523249 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 05:59:02.526787 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 05:59:02.533053 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 05:59:02.536676 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 05:59:02.540200 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 05:59:02.547337 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 05:59:02.551021 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1202 05:59:02.555190 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1203 05:59:02.558736 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 05:59:02.562157 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 05:59:02.569138 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 05:59:02.572448 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 05:59:02.576336 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 05:59:02.579345 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 05:59:02.585990 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 05:59:02.589372 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 05:59:02.592676 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 05:59:02.599652 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 05:59:02.602525 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 05:59:02.606071 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 05:59:02.612401 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 05:59:02.616036 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 05:59:02.619067 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 05:59:02.626124 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 05:59:02.629486 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 05:59:02.632899 Total UI for P1: 0, mck2ui 16
1221 05:59:02.636323 best dqsien dly found for B0: ( 0, 14, 8)
1222 05:59:02.639743 Total UI for P1: 0, mck2ui 16
1223 05:59:02.642777 best dqsien dly found for B1: ( 0, 14, 8)
1224 05:59:02.646102 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1225 05:59:02.649481 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 05:59:02.649571
1227 05:59:02.653029 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 05:59:02.656591 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 05:59:02.659688 [Gating] SW calibration Done
1230 05:59:02.659774 ==
1231 05:59:02.662525 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 05:59:02.666037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 05:59:02.666127 ==
1234 05:59:02.669326 RX Vref Scan: 0
1235 05:59:02.669410
1236 05:59:02.669485 RX Vref 0 -> 0, step: 1
1237 05:59:02.672413
1238 05:59:02.672500 RX Delay -130 -> 252, step: 16
1239 05:59:02.679384 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1240 05:59:02.682758 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1241 05:59:02.685742 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1242 05:59:02.688981 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1243 05:59:02.692900 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1244 05:59:02.699007 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1245 05:59:02.702422 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1246 05:59:02.705785 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1247 05:59:02.709010 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1248 05:59:02.712494 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1249 05:59:02.718959 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1250 05:59:02.722688 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1251 05:59:02.725983 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1252 05:59:02.728942 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1253 05:59:02.732472 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1254 05:59:02.739205 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1255 05:59:02.739321 ==
1256 05:59:02.742478 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 05:59:02.746099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 05:59:02.746189 ==
1259 05:59:02.746254 DQS Delay:
1260 05:59:02.748896 DQS0 = 0, DQS1 = 0
1261 05:59:02.748978 DQM Delay:
1262 05:59:02.752515 DQM0 = 80, DQM1 = 70
1263 05:59:02.752601 DQ Delay:
1264 05:59:02.755550 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1265 05:59:02.759072 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
1266 05:59:02.762665 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1267 05:59:02.765678 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1268 05:59:02.765766
1269 05:59:02.765834
1270 05:59:02.765896 ==
1271 05:59:02.769067 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 05:59:02.772630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 05:59:02.772716 ==
1274 05:59:02.772781
1275 05:59:02.772841
1276 05:59:02.775618 TX Vref Scan disable
1277 05:59:02.779260 == TX Byte 0 ==
1278 05:59:02.782328 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1279 05:59:02.785775 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1280 05:59:02.788858 == TX Byte 1 ==
1281 05:59:02.792257 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1282 05:59:02.795660 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1283 05:59:02.795747 ==
1284 05:59:02.799319 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 05:59:02.805772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 05:59:02.805873 ==
1287 05:59:02.817171 TX Vref=22, minBit 0, minWin=27, winSum=436
1288 05:59:02.820702 TX Vref=24, minBit 1, minWin=27, winSum=440
1289 05:59:02.823734 TX Vref=26, minBit 1, minWin=27, winSum=441
1290 05:59:02.827143 TX Vref=28, minBit 1, minWin=27, winSum=443
1291 05:59:02.830820 TX Vref=30, minBit 1, minWin=27, winSum=442
1292 05:59:02.834164 TX Vref=32, minBit 1, minWin=27, winSum=440
1293 05:59:02.840650 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 28
1294 05:59:02.840774
1295 05:59:02.844215 Final TX Range 1 Vref 28
1296 05:59:02.844302
1297 05:59:02.844365 ==
1298 05:59:02.847484 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 05:59:02.851053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 05:59:02.851142 ==
1301 05:59:02.851207
1302 05:59:02.851266
1303 05:59:02.853883 TX Vref Scan disable
1304 05:59:02.857304 == TX Byte 0 ==
1305 05:59:02.861022 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1306 05:59:02.864006 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1307 05:59:02.867506 == TX Byte 1 ==
1308 05:59:02.870393 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1309 05:59:02.873848 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1310 05:59:02.873935
1311 05:59:02.877416 [DATLAT]
1312 05:59:02.877520 Freq=800, CH0 RK1
1313 05:59:02.877586
1314 05:59:02.880479 DATLAT Default: 0xa
1315 05:59:02.880563 0, 0xFFFF, sum = 0
1316 05:59:02.883882 1, 0xFFFF, sum = 0
1317 05:59:02.883967 2, 0xFFFF, sum = 0
1318 05:59:02.887654 3, 0xFFFF, sum = 0
1319 05:59:02.887745 4, 0xFFFF, sum = 0
1320 05:59:02.890723 5, 0xFFFF, sum = 0
1321 05:59:02.890808 6, 0xFFFF, sum = 0
1322 05:59:02.894171 7, 0xFFFF, sum = 0
1323 05:59:02.894255 8, 0xFFFF, sum = 0
1324 05:59:02.897626 9, 0x0, sum = 1
1325 05:59:02.897712 10, 0x0, sum = 2
1326 05:59:02.900698 11, 0x0, sum = 3
1327 05:59:02.900781 12, 0x0, sum = 4
1328 05:59:02.904038 best_step = 10
1329 05:59:02.904120
1330 05:59:02.904183 ==
1331 05:59:02.907081 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 05:59:02.910580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 05:59:02.910664 ==
1334 05:59:02.914027 RX Vref Scan: 0
1335 05:59:02.914109
1336 05:59:02.914173 RX Vref 0 -> 0, step: 1
1337 05:59:02.914233
1338 05:59:02.916808 RX Delay -111 -> 252, step: 8
1339 05:59:02.923826 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1340 05:59:02.927235 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1341 05:59:02.930497 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1342 05:59:02.934053 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1343 05:59:02.937075 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1344 05:59:02.943878 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1345 05:59:02.947130 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1346 05:59:02.950792 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1347 05:59:02.953681 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1348 05:59:02.957019 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1349 05:59:02.963630 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1350 05:59:02.967402 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1351 05:59:02.970884 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1352 05:59:02.973637 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1353 05:59:02.977254 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1354 05:59:02.983712 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1355 05:59:02.983810 ==
1356 05:59:02.987385 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 05:59:02.990318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 05:59:02.990407 ==
1359 05:59:02.990471 DQS Delay:
1360 05:59:02.993704 DQS0 = 0, DQS1 = 0
1361 05:59:02.993786 DQM Delay:
1362 05:59:02.997279 DQM0 = 78, DQM1 = 70
1363 05:59:02.997361 DQ Delay:
1364 05:59:03.000375 DQ0 =80, DQ1 =80, DQ2 =76, DQ3 =72
1365 05:59:03.003826 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1366 05:59:03.007377 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1367 05:59:03.010454 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1368 05:59:03.010540
1369 05:59:03.010605
1370 05:59:03.017451 [DQSOSCAuto] RK1, (LSB)MR18= 0x4924, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1371 05:59:03.020427 CH0 RK1: MR19=606, MR18=4924
1372 05:59:03.026934 CH0_RK1: MR19=0x606, MR18=0x4924, DQSOSC=391, MR23=63, INC=96, DEC=64
1373 05:59:03.030476 [RxdqsGatingPostProcess] freq 800
1374 05:59:03.037338 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 05:59:03.040868 Pre-setting of DQS Precalculation
1376 05:59:03.043619 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 05:59:03.043704 ==
1378 05:59:03.046922 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 05:59:03.050438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 05:59:03.050527 ==
1381 05:59:03.057206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 05:59:03.063710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 05:59:03.072287 [CA 0] Center 36 (6~66) winsize 61
1384 05:59:03.075348 [CA 1] Center 36 (6~67) winsize 62
1385 05:59:03.078975 [CA 2] Center 34 (4~64) winsize 61
1386 05:59:03.082112 [CA 3] Center 34 (4~64) winsize 61
1387 05:59:03.085541 [CA 4] Center 34 (4~65) winsize 62
1388 05:59:03.088674 [CA 5] Center 34 (4~64) winsize 61
1389 05:59:03.088763
1390 05:59:03.092160 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 05:59:03.092244
1392 05:59:03.095680 [CATrainingPosCal] consider 1 rank data
1393 05:59:03.098680 u2DelayCellTimex100 = 270/100 ps
1394 05:59:03.102238 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1395 05:59:03.108768 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 05:59:03.111762 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1397 05:59:03.115296 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1398 05:59:03.118941 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 05:59:03.121922 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 05:59:03.122008
1401 05:59:03.125445 CA PerBit enable=1, Macro0, CA PI delay=34
1402 05:59:03.125554
1403 05:59:03.128379 [CBTSetCACLKResult] CA Dly = 34
1404 05:59:03.128462 CS Dly: 5 (0~36)
1405 05:59:03.131870 ==
1406 05:59:03.131955 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 05:59:03.138429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 05:59:03.138524 ==
1409 05:59:03.141731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 05:59:03.148287 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 05:59:03.158141 [CA 0] Center 36 (6~67) winsize 62
1412 05:59:03.161530 [CA 1] Center 36 (6~67) winsize 62
1413 05:59:03.164921 [CA 2] Center 34 (4~65) winsize 62
1414 05:59:03.168286 [CA 3] Center 33 (3~64) winsize 62
1415 05:59:03.171979 [CA 4] Center 34 (4~65) winsize 62
1416 05:59:03.174783 [CA 5] Center 33 (3~64) winsize 62
1417 05:59:03.174869
1418 05:59:03.178372 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1419 05:59:03.178456
1420 05:59:03.181898 [CATrainingPosCal] consider 2 rank data
1421 05:59:03.184964 u2DelayCellTimex100 = 270/100 ps
1422 05:59:03.188255 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1423 05:59:03.191627 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 05:59:03.198582 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1425 05:59:03.201654 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 05:59:03.205153 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 05:59:03.209105 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 05:59:03.209230
1429 05:59:03.212618 CA PerBit enable=1, Macro0, CA PI delay=34
1430 05:59:03.212706
1431 05:59:03.216449 [CBTSetCACLKResult] CA Dly = 34
1432 05:59:03.216535 CS Dly: 6 (0~38)
1433 05:59:03.216599
1434 05:59:03.220087 ----->DramcWriteLeveling(PI) begin...
1435 05:59:03.220174 ==
1436 05:59:03.223502 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 05:59:03.227600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 05:59:03.227695 ==
1439 05:59:03.231093 Write leveling (Byte 0): 28 => 28
1440 05:59:03.234629 Write leveling (Byte 1): 29 => 29
1441 05:59:03.238862 DramcWriteLeveling(PI) end<-----
1442 05:59:03.238959
1443 05:59:03.239024 ==
1444 05:59:03.241795 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 05:59:03.244927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 05:59:03.245014 ==
1447 05:59:03.248636 [Gating] SW mode calibration
1448 05:59:03.255102 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 05:59:03.258500 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 05:59:03.264822 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 05:59:03.268232 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1452 05:59:03.271641 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 05:59:03.278178 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 05:59:03.281839 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 05:59:03.285180 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 05:59:03.291717 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 05:59:03.294746 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 05:59:03.298662 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 05:59:03.305025 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 05:59:03.308416 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 05:59:03.311443 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 05:59:03.317864 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 05:59:03.322025 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 05:59:03.324795 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 05:59:03.331492 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 05:59:03.334772 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 05:59:03.337914 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1468 05:59:03.345021 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1469 05:59:03.347909 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 05:59:03.351228 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 05:59:03.354703 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 05:59:03.361145 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 05:59:03.364486 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 05:59:03.367989 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 05:59:03.374434 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 05:59:03.377717 0 9 8 | B1->B0 | 2a2a 2828 | 1 0 | (1 1) (0 0)
1477 05:59:03.381247 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 05:59:03.387829 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 05:59:03.391289 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 05:59:03.394281 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 05:59:03.401288 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 05:59:03.404361 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 05:59:03.407879 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1484 05:59:03.414369 0 10 8 | B1->B0 | 2b2b 2525 | 0 1 | (0 0) (1 0)
1485 05:59:03.417935 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1486 05:59:03.421538 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 05:59:03.428251 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 05:59:03.431437 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 05:59:03.434725 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 05:59:03.441480 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 05:59:03.444825 0 11 4 | B1->B0 | 2525 2525 | 0 1 | (0 0) (0 0)
1492 05:59:03.447946 0 11 8 | B1->B0 | 3e3e 3939 | 0 0 | (0 0) (0 0)
1493 05:59:03.454785 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 05:59:03.457884 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 05:59:03.461147 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 05:59:03.464712 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 05:59:03.471029 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 05:59:03.474660 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 05:59:03.478154 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 05:59:03.484319 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1501 05:59:03.487796 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1502 05:59:03.491427 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 05:59:03.497779 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 05:59:03.501340 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 05:59:03.504153 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 05:59:03.511415 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 05:59:03.514247 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 05:59:03.517848 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 05:59:03.524287 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 05:59:03.527912 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 05:59:03.530749 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 05:59:03.537740 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 05:59:03.540836 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 05:59:03.544052 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 05:59:03.551057 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 05:59:03.554540 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 05:59:03.557649 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 05:59:03.560901 Total UI for P1: 0, mck2ui 16
1519 05:59:03.564126 best dqsien dly found for B0: ( 0, 14, 8)
1520 05:59:03.567809 Total UI for P1: 0, mck2ui 16
1521 05:59:03.570806 best dqsien dly found for B1: ( 0, 14, 8)
1522 05:59:03.574300 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1523 05:59:03.577276 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1524 05:59:03.577396
1525 05:59:03.580841 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1526 05:59:03.587727 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1527 05:59:03.587844 [Gating] SW calibration Done
1528 05:59:03.587912 ==
1529 05:59:03.590820 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 05:59:03.597978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 05:59:03.598091 ==
1532 05:59:03.598158 RX Vref Scan: 0
1533 05:59:03.598219
1534 05:59:03.600983 RX Vref 0 -> 0, step: 1
1535 05:59:03.601073
1536 05:59:03.604525 RX Delay -130 -> 252, step: 16
1537 05:59:03.607429 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1538 05:59:03.611039 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1539 05:59:03.614481 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1540 05:59:03.620956 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1541 05:59:03.624505 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1542 05:59:03.627334 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1543 05:59:03.630826 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1544 05:59:03.634379 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1545 05:59:03.637308 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1546 05:59:03.644313 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1547 05:59:03.647611 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1548 05:59:03.650919 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1549 05:59:03.654072 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1550 05:59:03.660864 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1551 05:59:03.664513 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1552 05:59:03.667417 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1553 05:59:03.667507 ==
1554 05:59:03.670948 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 05:59:03.674015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 05:59:03.674103 ==
1557 05:59:03.677439 DQS Delay:
1558 05:59:03.677567 DQS0 = 0, DQS1 = 0
1559 05:59:03.680558 DQM Delay:
1560 05:59:03.680645 DQM0 = 81, DQM1 = 76
1561 05:59:03.680711 DQ Delay:
1562 05:59:03.684067 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1563 05:59:03.687557 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1564 05:59:03.690808 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1565 05:59:03.694015 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1566 05:59:03.694103
1567 05:59:03.694168
1568 05:59:03.694227 ==
1569 05:59:03.697086 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 05:59:03.704146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 05:59:03.704253 ==
1572 05:59:03.704319
1573 05:59:03.704380
1574 05:59:03.704437 TX Vref Scan disable
1575 05:59:03.707902 == TX Byte 0 ==
1576 05:59:03.711469 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1577 05:59:03.714400 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1578 05:59:03.718204 == TX Byte 1 ==
1579 05:59:03.721073 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1580 05:59:03.724638 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1581 05:59:03.727628 ==
1582 05:59:03.731364 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 05:59:03.734247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 05:59:03.734339 ==
1585 05:59:03.746969 TX Vref=22, minBit 8, minWin=27, winSum=444
1586 05:59:03.749887 TX Vref=24, minBit 8, minWin=27, winSum=450
1587 05:59:03.753372 TX Vref=26, minBit 8, minWin=27, winSum=455
1588 05:59:03.756560 TX Vref=28, minBit 1, minWin=28, winSum=458
1589 05:59:03.759763 TX Vref=30, minBit 1, minWin=28, winSum=455
1590 05:59:03.763029 TX Vref=32, minBit 9, minWin=27, winSum=454
1591 05:59:03.770157 [TxChooseVref] Worse bit 1, Min win 28, Win sum 458, Final Vref 28
1592 05:59:03.770316
1593 05:59:03.773607 Final TX Range 1 Vref 28
1594 05:59:03.773720
1595 05:59:03.773813 ==
1596 05:59:03.776609 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 05:59:03.780156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 05:59:03.780270 ==
1599 05:59:03.780364
1600 05:59:03.783643
1601 05:59:03.783753 TX Vref Scan disable
1602 05:59:03.787502 == TX Byte 0 ==
1603 05:59:03.790985 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1604 05:59:03.794494 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1605 05:59:03.798079 == TX Byte 1 ==
1606 05:59:03.800755 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1607 05:59:03.804490 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1608 05:59:03.804622
1609 05:59:03.804716 [DATLAT]
1610 05:59:03.807847 Freq=800, CH1 RK0
1611 05:59:03.807954
1612 05:59:03.811023 DATLAT Default: 0xa
1613 05:59:03.811114 0, 0xFFFF, sum = 0
1614 05:59:03.814508 1, 0xFFFF, sum = 0
1615 05:59:03.814626 2, 0xFFFF, sum = 0
1616 05:59:03.817882 3, 0xFFFF, sum = 0
1617 05:59:03.817990 4, 0xFFFF, sum = 0
1618 05:59:03.820882 5, 0xFFFF, sum = 0
1619 05:59:03.820966 6, 0xFFFF, sum = 0
1620 05:59:03.823995 7, 0xFFFF, sum = 0
1621 05:59:03.824107 8, 0xFFFF, sum = 0
1622 05:59:03.827566 9, 0x0, sum = 1
1623 05:59:03.827655 10, 0x0, sum = 2
1624 05:59:03.831160 11, 0x0, sum = 3
1625 05:59:03.831252 12, 0x0, sum = 4
1626 05:59:03.831320 best_step = 10
1627 05:59:03.834336
1628 05:59:03.834426 ==
1629 05:59:03.837815 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 05:59:03.840859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 05:59:03.840953 ==
1632 05:59:03.841021 RX Vref Scan: 1
1633 05:59:03.841082
1634 05:59:03.844407 Set Vref Range= 32 -> 127
1635 05:59:03.844534
1636 05:59:03.847841 RX Vref 32 -> 127, step: 1
1637 05:59:03.847963
1638 05:59:03.850781 RX Delay -111 -> 252, step: 8
1639 05:59:03.850872
1640 05:59:03.854386 Set Vref, RX VrefLevel [Byte0]: 32
1641 05:59:03.857286 [Byte1]: 32
1642 05:59:03.857402
1643 05:59:03.860731 Set Vref, RX VrefLevel [Byte0]: 33
1644 05:59:03.864094 [Byte1]: 33
1645 05:59:03.864189
1646 05:59:03.867364 Set Vref, RX VrefLevel [Byte0]: 34
1647 05:59:03.871109 [Byte1]: 34
1648 05:59:03.874859
1649 05:59:03.874960 Set Vref, RX VrefLevel [Byte0]: 35
1650 05:59:03.877780 [Byte1]: 35
1651 05:59:03.882601
1652 05:59:03.882698 Set Vref, RX VrefLevel [Byte0]: 36
1653 05:59:03.885370 [Byte1]: 36
1654 05:59:03.890190
1655 05:59:03.893346 Set Vref, RX VrefLevel [Byte0]: 37
1656 05:59:03.893468 [Byte1]: 37
1657 05:59:03.897654
1658 05:59:03.897750 Set Vref, RX VrefLevel [Byte0]: 38
1659 05:59:03.901094 [Byte1]: 38
1660 05:59:03.905237
1661 05:59:03.905328 Set Vref, RX VrefLevel [Byte0]: 39
1662 05:59:03.908622 [Byte1]: 39
1663 05:59:03.912833
1664 05:59:03.912926 Set Vref, RX VrefLevel [Byte0]: 40
1665 05:59:03.916330 [Byte1]: 40
1666 05:59:03.920471
1667 05:59:03.920566 Set Vref, RX VrefLevel [Byte0]: 41
1668 05:59:03.924152 [Byte1]: 41
1669 05:59:03.928550
1670 05:59:03.928641 Set Vref, RX VrefLevel [Byte0]: 42
1671 05:59:03.931497 [Byte1]: 42
1672 05:59:03.936327
1673 05:59:03.936455 Set Vref, RX VrefLevel [Byte0]: 43
1674 05:59:03.938971 [Byte1]: 43
1675 05:59:03.943309
1676 05:59:03.943413 Set Vref, RX VrefLevel [Byte0]: 44
1677 05:59:03.946842 [Byte1]: 44
1678 05:59:03.951154
1679 05:59:03.951262 Set Vref, RX VrefLevel [Byte0]: 45
1680 05:59:03.954454 [Byte1]: 45
1681 05:59:03.959155
1682 05:59:03.959268 Set Vref, RX VrefLevel [Byte0]: 46
1683 05:59:03.962290 [Byte1]: 46
1684 05:59:03.966542
1685 05:59:03.966653 Set Vref, RX VrefLevel [Byte0]: 47
1686 05:59:03.969943 [Byte1]: 47
1687 05:59:03.973926
1688 05:59:03.974018 Set Vref, RX VrefLevel [Byte0]: 48
1689 05:59:03.977635 [Byte1]: 48
1690 05:59:03.981933
1691 05:59:03.982033 Set Vref, RX VrefLevel [Byte0]: 49
1692 05:59:03.984830 [Byte1]: 49
1693 05:59:03.989491
1694 05:59:03.992414 Set Vref, RX VrefLevel [Byte0]: 50
1695 05:59:03.992506 [Byte1]: 50
1696 05:59:03.997060
1697 05:59:03.997154 Set Vref, RX VrefLevel [Byte0]: 51
1698 05:59:04.000516 [Byte1]: 51
1699 05:59:04.004822
1700 05:59:04.004916 Set Vref, RX VrefLevel [Byte0]: 52
1701 05:59:04.008221 [Byte1]: 52
1702 05:59:04.012233
1703 05:59:04.012322 Set Vref, RX VrefLevel [Byte0]: 53
1704 05:59:04.015603 [Byte1]: 53
1705 05:59:04.019799
1706 05:59:04.019886 Set Vref, RX VrefLevel [Byte0]: 54
1707 05:59:04.023507 [Byte1]: 54
1708 05:59:04.027624
1709 05:59:04.027714 Set Vref, RX VrefLevel [Byte0]: 55
1710 05:59:04.031062 [Byte1]: 55
1711 05:59:04.035218
1712 05:59:04.035304 Set Vref, RX VrefLevel [Byte0]: 56
1713 05:59:04.038935 [Byte1]: 56
1714 05:59:04.043040
1715 05:59:04.043128 Set Vref, RX VrefLevel [Byte0]: 57
1716 05:59:04.046431 [Byte1]: 57
1717 05:59:04.050417
1718 05:59:04.050505 Set Vref, RX VrefLevel [Byte0]: 58
1719 05:59:04.053935 [Byte1]: 58
1720 05:59:04.058437
1721 05:59:04.058529 Set Vref, RX VrefLevel [Byte0]: 59
1722 05:59:04.061913 [Byte1]: 59
1723 05:59:04.065900
1724 05:59:04.065992 Set Vref, RX VrefLevel [Byte0]: 60
1725 05:59:04.068977 [Byte1]: 60
1726 05:59:04.073370
1727 05:59:04.073498 Set Vref, RX VrefLevel [Byte0]: 61
1728 05:59:04.076617 [Byte1]: 61
1729 05:59:04.081355
1730 05:59:04.081484 Set Vref, RX VrefLevel [Byte0]: 62
1731 05:59:04.084600 [Byte1]: 62
1732 05:59:04.088879
1733 05:59:04.088985 Set Vref, RX VrefLevel [Byte0]: 63
1734 05:59:04.091946 [Byte1]: 63
1735 05:59:04.096689
1736 05:59:04.096786 Set Vref, RX VrefLevel [Byte0]: 64
1737 05:59:04.099710 [Byte1]: 64
1738 05:59:04.104122
1739 05:59:04.104316 Set Vref, RX VrefLevel [Byte0]: 65
1740 05:59:04.107691 [Byte1]: 65
1741 05:59:04.112026
1742 05:59:04.112202 Set Vref, RX VrefLevel [Byte0]: 66
1743 05:59:04.115050 [Byte1]: 66
1744 05:59:04.119734
1745 05:59:04.119886 Set Vref, RX VrefLevel [Byte0]: 67
1746 05:59:04.122797 [Byte1]: 67
1747 05:59:04.127038
1748 05:59:04.127170 Set Vref, RX VrefLevel [Byte0]: 68
1749 05:59:04.130438 [Byte1]: 68
1750 05:59:04.134475
1751 05:59:04.134572 Set Vref, RX VrefLevel [Byte0]: 69
1752 05:59:04.138043 [Byte1]: 69
1753 05:59:04.142255
1754 05:59:04.142353 Set Vref, RX VrefLevel [Byte0]: 70
1755 05:59:04.145920 [Byte1]: 70
1756 05:59:04.150167
1757 05:59:04.150263 Set Vref, RX VrefLevel [Byte0]: 71
1758 05:59:04.153580 [Byte1]: 71
1759 05:59:04.157921
1760 05:59:04.158017 Set Vref, RX VrefLevel [Byte0]: 72
1761 05:59:04.160934 [Byte1]: 72
1762 05:59:04.165230
1763 05:59:04.165326 Set Vref, RX VrefLevel [Byte0]: 73
1764 05:59:04.168831 [Byte1]: 73
1765 05:59:04.172985
1766 05:59:04.173078 Set Vref, RX VrefLevel [Byte0]: 74
1767 05:59:04.176657 [Byte1]: 74
1768 05:59:04.180668
1769 05:59:04.180763 Set Vref, RX VrefLevel [Byte0]: 75
1770 05:59:04.183971 [Byte1]: 75
1771 05:59:04.188068
1772 05:59:04.188166 Set Vref, RX VrefLevel [Byte0]: 76
1773 05:59:04.191658 [Byte1]: 76
1774 05:59:04.196061
1775 05:59:04.196176 Final RX Vref Byte 0 = 55 to rank0
1776 05:59:04.199485 Final RX Vref Byte 1 = 55 to rank0
1777 05:59:04.202382 Final RX Vref Byte 0 = 55 to rank1
1778 05:59:04.205864 Final RX Vref Byte 1 = 55 to rank1==
1779 05:59:04.209262 Dram Type= 6, Freq= 0, CH_1, rank 0
1780 05:59:04.215823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 05:59:04.215937 ==
1782 05:59:04.216032 DQS Delay:
1783 05:59:04.216116 DQS0 = 0, DQS1 = 0
1784 05:59:04.219422 DQM Delay:
1785 05:59:04.219511 DQM0 = 80, DQM1 = 71
1786 05:59:04.223059 DQ Delay:
1787 05:59:04.226010 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1788 05:59:04.226102 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1789 05:59:04.229487 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1790 05:59:04.232503 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1791 05:59:04.235882
1792 05:59:04.235973
1793 05:59:04.242747 [DQSOSCAuto] RK0, (LSB)MR18= 0x101a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
1794 05:59:04.245961 CH1 RK0: MR19=606, MR18=101A
1795 05:59:04.252872 CH1_RK0: MR19=0x606, MR18=0x101A, DQSOSC=403, MR23=63, INC=90, DEC=60
1796 05:59:04.252980
1797 05:59:04.255867 ----->DramcWriteLeveling(PI) begin...
1798 05:59:04.255954 ==
1799 05:59:04.259203 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 05:59:04.262829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 05:59:04.262920 ==
1802 05:59:04.265763 Write leveling (Byte 0): 27 => 27
1803 05:59:04.269289 Write leveling (Byte 1): 30 => 30
1804 05:59:04.272834 DramcWriteLeveling(PI) end<-----
1805 05:59:04.272925
1806 05:59:04.273010 ==
1807 05:59:04.275828 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 05:59:04.279451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 05:59:04.279540 ==
1810 05:59:04.282470 [Gating] SW mode calibration
1811 05:59:04.289420 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1812 05:59:04.295839 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1813 05:59:04.299253 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1814 05:59:04.302739 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1815 05:59:04.309043 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1816 05:59:04.312857 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 05:59:04.315863 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 05:59:04.322275 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 05:59:04.326091 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 05:59:04.328937 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 05:59:04.335963 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 05:59:04.339266 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 05:59:04.342400 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 05:59:04.348964 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 05:59:04.352526 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 05:59:04.355508 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 05:59:04.362576 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 05:59:04.365462 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 05:59:04.369101 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 05:59:04.372609 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1831 05:59:04.379209 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1832 05:59:04.382867 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 05:59:04.385867 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 05:59:04.392635 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 05:59:04.395626 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 05:59:04.399246 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 05:59:04.405732 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 05:59:04.408906 0 9 4 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
1839 05:59:04.412392 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
1840 05:59:04.419129 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 05:59:04.422202 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 05:59:04.425856 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 05:59:04.432382 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 05:59:04.435972 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 05:59:04.438748 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1846 05:59:04.445553 0 10 4 | B1->B0 | 3131 2a2a | 0 0 | (0 0) (0 0)
1847 05:59:04.449086 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 05:59:04.452272 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 05:59:04.459035 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 05:59:04.462135 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 05:59:04.465936 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 05:59:04.469041 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 05:59:04.475817 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1854 05:59:04.478836 0 11 4 | B1->B0 | 2d2d 3d3d | 0 0 | (0 0) (0 0)
1855 05:59:04.482498 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1856 05:59:04.489397 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 05:59:04.492395 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 05:59:04.495404 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 05:59:04.502005 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 05:59:04.505667 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 05:59:04.508905 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 05:59:04.515399 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 05:59:04.519032 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1864 05:59:04.521972 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 05:59:04.528796 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 05:59:04.532366 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 05:59:04.535385 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 05:59:04.541964 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 05:59:04.545668 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 05:59:04.548961 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 05:59:04.555574 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 05:59:04.558601 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 05:59:04.562211 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 05:59:04.568861 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 05:59:04.572301 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 05:59:04.575452 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 05:59:04.582107 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 05:59:04.585398 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1879 05:59:04.588741 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1880 05:59:04.591985 Total UI for P1: 0, mck2ui 16
1881 05:59:04.595422 best dqsien dly found for B0: ( 0, 14, 4)
1882 05:59:04.598775 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 05:59:04.601848 Total UI for P1: 0, mck2ui 16
1884 05:59:04.605224 best dqsien dly found for B1: ( 0, 14, 6)
1885 05:59:04.608573 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1886 05:59:04.612332 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1887 05:59:04.615571
1888 05:59:04.619094 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1889 05:59:04.621981 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1890 05:59:04.622071 [Gating] SW calibration Done
1891 05:59:04.625761 ==
1892 05:59:04.628793 Dram Type= 6, Freq= 0, CH_1, rank 1
1893 05:59:04.632433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1894 05:59:04.632516 ==
1895 05:59:04.632582 RX Vref Scan: 0
1896 05:59:04.632643
1897 05:59:04.635551 RX Vref 0 -> 0, step: 1
1898 05:59:04.635633
1899 05:59:04.638542 RX Delay -130 -> 252, step: 16
1900 05:59:04.642330 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1901 05:59:04.645850 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1902 05:59:04.652236 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1903 05:59:04.655264 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1904 05:59:04.658838 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1905 05:59:04.661882 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1906 05:59:04.665520 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1907 05:59:04.672333 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1908 05:59:04.675320 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1909 05:59:04.678295 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1910 05:59:04.681641 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1911 05:59:04.685322 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1912 05:59:04.691558 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1913 05:59:04.695194 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1914 05:59:04.698282 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1915 05:59:04.701949 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1916 05:59:04.702031 ==
1917 05:59:04.704903 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 05:59:04.711787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 05:59:04.711869 ==
1920 05:59:04.711935 DQS Delay:
1921 05:59:04.711994 DQS0 = 0, DQS1 = 0
1922 05:59:04.714858 DQM Delay:
1923 05:59:04.714938 DQM0 = 80, DQM1 = 76
1924 05:59:04.718575 DQ Delay:
1925 05:59:04.721712 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1926 05:59:04.725021 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1927 05:59:04.728272 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1928 05:59:04.731449 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1929 05:59:04.731531
1930 05:59:04.731595
1931 05:59:04.731654 ==
1932 05:59:04.735078 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 05:59:04.738320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 05:59:04.738433 ==
1935 05:59:04.738525
1936 05:59:04.738613
1937 05:59:04.741314 TX Vref Scan disable
1938 05:59:04.741394 == TX Byte 0 ==
1939 05:59:04.748000 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1940 05:59:04.751641 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1941 05:59:04.751717 == TX Byte 1 ==
1942 05:59:04.758394 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1943 05:59:04.761876 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1944 05:59:04.761954 ==
1945 05:59:04.764849 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 05:59:04.768449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 05:59:04.768523 ==
1948 05:59:04.782248 TX Vref=22, minBit 9, minWin=27, winSum=450
1949 05:59:04.785705 TX Vref=24, minBit 3, minWin=28, winSum=456
1950 05:59:04.788923 TX Vref=26, minBit 3, minWin=28, winSum=456
1951 05:59:04.792374 TX Vref=28, minBit 3, minWin=28, winSum=457
1952 05:59:04.795867 TX Vref=30, minBit 8, minWin=28, winSum=460
1953 05:59:04.802582 TX Vref=32, minBit 1, minWin=28, winSum=456
1954 05:59:04.805460 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1955 05:59:04.805617
1956 05:59:04.809188 Final TX Range 1 Vref 30
1957 05:59:04.809268
1958 05:59:04.809333 ==
1959 05:59:04.812174 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 05:59:04.815317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 05:59:04.815398 ==
1962 05:59:04.818679
1963 05:59:04.818758
1964 05:59:04.818822 TX Vref Scan disable
1965 05:59:04.822324 == TX Byte 0 ==
1966 05:59:04.825354 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1967 05:59:04.828971 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1968 05:59:04.832356 == TX Byte 1 ==
1969 05:59:04.835600 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1970 05:59:04.838729 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1971 05:59:04.842535
1972 05:59:04.842635 [DATLAT]
1973 05:59:04.842700 Freq=800, CH1 RK1
1974 05:59:04.842761
1975 05:59:04.845265 DATLAT Default: 0xa
1976 05:59:04.845350 0, 0xFFFF, sum = 0
1977 05:59:04.849007 1, 0xFFFF, sum = 0
1978 05:59:04.849093 2, 0xFFFF, sum = 0
1979 05:59:04.852510 3, 0xFFFF, sum = 0
1980 05:59:04.852595 4, 0xFFFF, sum = 0
1981 05:59:04.855759 5, 0xFFFF, sum = 0
1982 05:59:04.858859 6, 0xFFFF, sum = 0
1983 05:59:04.858946 7, 0xFFFF, sum = 0
1984 05:59:04.862118 8, 0xFFFF, sum = 0
1985 05:59:04.862221 9, 0x0, sum = 1
1986 05:59:04.862308 10, 0x0, sum = 2
1987 05:59:04.865517 11, 0x0, sum = 3
1988 05:59:04.865617 12, 0x0, sum = 4
1989 05:59:04.868637 best_step = 10
1990 05:59:04.868720
1991 05:59:04.868805 ==
1992 05:59:04.872118 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 05:59:04.875309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 05:59:04.875398 ==
1995 05:59:04.878819 RX Vref Scan: 0
1996 05:59:04.878901
1997 05:59:04.878987 RX Vref 0 -> 0, step: 1
1998 05:59:04.879068
1999 05:59:04.881888 RX Delay -111 -> 252, step: 8
2000 05:59:04.889083 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2001 05:59:04.892505 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2002 05:59:04.895449 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2003 05:59:04.898841 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2004 05:59:04.902042 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2005 05:59:04.909358 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2006 05:59:04.912192 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2007 05:59:04.916018 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2008 05:59:04.919046 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2009 05:59:04.922380 iDelay=209, Bit 9, Center 60 (-63 ~ 184) 248
2010 05:59:04.929304 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2011 05:59:04.932739 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2012 05:59:04.935806 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2013 05:59:04.939297 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2014 05:59:04.942701 iDelay=209, Bit 14, Center 76 (-47 ~ 200) 248
2015 05:59:04.949193 iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248
2016 05:59:04.949305 ==
2017 05:59:04.952278 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 05:59:04.955757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 05:59:04.955867 ==
2020 05:59:04.955996 DQS Delay:
2021 05:59:04.959166 DQS0 = 0, DQS1 = 0
2022 05:59:04.959296 DQM Delay:
2023 05:59:04.962305 DQM0 = 77, DQM1 = 72
2024 05:59:04.962387 DQ Delay:
2025 05:59:04.965671 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2026 05:59:04.969214 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2027 05:59:04.972586 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
2028 05:59:04.975677 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
2029 05:59:04.975760
2030 05:59:04.975824
2031 05:59:04.982082 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
2032 05:59:04.985513 CH1 RK1: MR19=606, MR18=1E36
2033 05:59:04.992056 CH1_RK1: MR19=0x606, MR18=0x1E36, DQSOSC=396, MR23=63, INC=94, DEC=62
2034 05:59:04.995475 [RxdqsGatingPostProcess] freq 800
2035 05:59:05.002612 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2036 05:59:05.005259 Pre-setting of DQS Precalculation
2037 05:59:05.009010 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2038 05:59:05.015803 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2039 05:59:05.022417 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2040 05:59:05.022535
2041 05:59:05.022662
2042 05:59:05.025530 [Calibration Summary] 1600 Mbps
2043 05:59:05.028885 CH 0, Rank 0
2044 05:59:05.029010 SW Impedance : PASS
2045 05:59:05.032546 DUTY Scan : NO K
2046 05:59:05.035602 ZQ Calibration : PASS
2047 05:59:05.035702 Jitter Meter : NO K
2048 05:59:05.039149 CBT Training : PASS
2049 05:59:05.042078 Write leveling : PASS
2050 05:59:05.042188 RX DQS gating : PASS
2051 05:59:05.045816 RX DQ/DQS(RDDQC) : PASS
2052 05:59:05.048748 TX DQ/DQS : PASS
2053 05:59:05.048832 RX DATLAT : PASS
2054 05:59:05.052118 RX DQ/DQS(Engine): PASS
2055 05:59:05.052232 TX OE : NO K
2056 05:59:05.055787 All Pass.
2057 05:59:05.055883
2058 05:59:05.055976 CH 0, Rank 1
2059 05:59:05.058730 SW Impedance : PASS
2060 05:59:05.058814 DUTY Scan : NO K
2061 05:59:05.062196 ZQ Calibration : PASS
2062 05:59:05.065768 Jitter Meter : NO K
2063 05:59:05.065867 CBT Training : PASS
2064 05:59:05.068678 Write leveling : PASS
2065 05:59:05.072148 RX DQS gating : PASS
2066 05:59:05.072231 RX DQ/DQS(RDDQC) : PASS
2067 05:59:05.075781 TX DQ/DQS : PASS
2068 05:59:05.078825 RX DATLAT : PASS
2069 05:59:05.078922 RX DQ/DQS(Engine): PASS
2070 05:59:05.082340 TX OE : NO K
2071 05:59:05.082421 All Pass.
2072 05:59:05.082517
2073 05:59:05.085343 CH 1, Rank 0
2074 05:59:05.085449 SW Impedance : PASS
2075 05:59:05.088666 DUTY Scan : NO K
2076 05:59:05.091977 ZQ Calibration : PASS
2077 05:59:05.092127 Jitter Meter : NO K
2078 05:59:05.095742 CBT Training : PASS
2079 05:59:05.095831 Write leveling : PASS
2080 05:59:05.099080 RX DQS gating : PASS
2081 05:59:05.102062 RX DQ/DQS(RDDQC) : PASS
2082 05:59:05.102147 TX DQ/DQS : PASS
2083 05:59:05.105762 RX DATLAT : PASS
2084 05:59:05.109095 RX DQ/DQS(Engine): PASS
2085 05:59:05.109186 TX OE : NO K
2086 05:59:05.111972 All Pass.
2087 05:59:05.112047
2088 05:59:05.112109 CH 1, Rank 1
2089 05:59:05.115476 SW Impedance : PASS
2090 05:59:05.115557 DUTY Scan : NO K
2091 05:59:05.118896 ZQ Calibration : PASS
2092 05:59:05.122594 Jitter Meter : NO K
2093 05:59:05.122676 CBT Training : PASS
2094 05:59:05.125676 Write leveling : PASS
2095 05:59:05.128655 RX DQS gating : PASS
2096 05:59:05.128741 RX DQ/DQS(RDDQC) : PASS
2097 05:59:05.132134 TX DQ/DQS : PASS
2098 05:59:05.135604 RX DATLAT : PASS
2099 05:59:05.135694 RX DQ/DQS(Engine): PASS
2100 05:59:05.138619 TX OE : NO K
2101 05:59:05.138744 All Pass.
2102 05:59:05.138856
2103 05:59:05.142271 DramC Write-DBI off
2104 05:59:05.145755 PER_BANK_REFRESH: Hybrid Mode
2105 05:59:05.145865 TX_TRACKING: ON
2106 05:59:05.148698 [GetDramInforAfterCalByMRR] Vendor 6.
2107 05:59:05.152148 [GetDramInforAfterCalByMRR] Revision 606.
2108 05:59:05.155486 [GetDramInforAfterCalByMRR] Revision 2 0.
2109 05:59:05.158520 MR0 0x3b3b
2110 05:59:05.158617 MR8 0x5151
2111 05:59:05.161964 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 05:59:05.162041
2113 05:59:05.162106 MR0 0x3b3b
2114 05:59:05.165601 MR8 0x5151
2115 05:59:05.168457 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 05:59:05.168566
2117 05:59:05.175403 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2118 05:59:05.181927 [FAST_K] Save calibration result to emmc
2119 05:59:05.185399 [FAST_K] Save calibration result to emmc
2120 05:59:05.185520 dram_init: config_dvfs: 1
2121 05:59:05.188892 dramc_set_vcore_voltage set vcore to 662500
2122 05:59:05.191868 Read voltage for 1200, 2
2123 05:59:05.191975 Vio18 = 0
2124 05:59:05.195347 Vcore = 662500
2125 05:59:05.195451 Vdram = 0
2126 05:59:05.195543 Vddq = 0
2127 05:59:05.198713 Vmddr = 0
2128 05:59:05.201769 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2129 05:59:05.208759 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2130 05:59:05.208837 MEM_TYPE=3, freq_sel=15
2131 05:59:05.212052 sv_algorithm_assistance_LP4_1600
2132 05:59:05.218524 ============ PULL DRAM RESETB DOWN ============
2133 05:59:05.222029 ========== PULL DRAM RESETB DOWN end =========
2134 05:59:05.225627 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 05:59:05.228666 ===================================
2136 05:59:05.231819 LPDDR4 DRAM CONFIGURATION
2137 05:59:05.235123 ===================================
2138 05:59:05.238698 EX_ROW_EN[0] = 0x0
2139 05:59:05.238787 EX_ROW_EN[1] = 0x0
2140 05:59:05.241688 LP4Y_EN = 0x0
2141 05:59:05.241765 WORK_FSP = 0x0
2142 05:59:05.245226 WL = 0x4
2143 05:59:05.245304 RL = 0x4
2144 05:59:05.248254 BL = 0x2
2145 05:59:05.248353 RPST = 0x0
2146 05:59:05.251884 RD_PRE = 0x0
2147 05:59:05.251961 WR_PRE = 0x1
2148 05:59:05.255001 WR_PST = 0x0
2149 05:59:05.255081 DBI_WR = 0x0
2150 05:59:05.258373 DBI_RD = 0x0
2151 05:59:05.258475 OTF = 0x1
2152 05:59:05.261579 ===================================
2153 05:59:05.265322 ===================================
2154 05:59:05.268257 ANA top config
2155 05:59:05.271854 ===================================
2156 05:59:05.275468 DLL_ASYNC_EN = 0
2157 05:59:05.275548 ALL_SLAVE_EN = 0
2158 05:59:05.278854 NEW_RANK_MODE = 1
2159 05:59:05.281834 DLL_IDLE_MODE = 1
2160 05:59:05.285460 LP45_APHY_COMB_EN = 1
2161 05:59:05.285573 TX_ODT_DIS = 1
2162 05:59:05.288341 NEW_8X_MODE = 1
2163 05:59:05.291904 ===================================
2164 05:59:05.295562 ===================================
2165 05:59:05.298473 data_rate = 2400
2166 05:59:05.302066 CKR = 1
2167 05:59:05.305468 DQ_P2S_RATIO = 8
2168 05:59:05.308516 ===================================
2169 05:59:05.312083 CA_P2S_RATIO = 8
2170 05:59:05.312191 DQ_CA_OPEN = 0
2171 05:59:05.315152 DQ_SEMI_OPEN = 0
2172 05:59:05.318626 CA_SEMI_OPEN = 0
2173 05:59:05.321717 CA_FULL_RATE = 0
2174 05:59:05.325245 DQ_CKDIV4_EN = 0
2175 05:59:05.325383 CA_CKDIV4_EN = 0
2176 05:59:05.328589 CA_PREDIV_EN = 0
2177 05:59:05.331472 PH8_DLY = 17
2178 05:59:05.335230 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2179 05:59:05.338279 DQ_AAMCK_DIV = 4
2180 05:59:05.341818 CA_AAMCK_DIV = 4
2181 05:59:05.341902 CA_ADMCK_DIV = 4
2182 05:59:05.344748 DQ_TRACK_CA_EN = 0
2183 05:59:05.348367 CA_PICK = 1200
2184 05:59:05.351713 CA_MCKIO = 1200
2185 05:59:05.355298 MCKIO_SEMI = 0
2186 05:59:05.358301 PLL_FREQ = 2366
2187 05:59:05.361834 DQ_UI_PI_RATIO = 32
2188 05:59:05.364930 CA_UI_PI_RATIO = 0
2189 05:59:05.368364 ===================================
2190 05:59:05.371594 ===================================
2191 05:59:05.371703 memory_type:LPDDR4
2192 05:59:05.374788 GP_NUM : 10
2193 05:59:05.374863 SRAM_EN : 1
2194 05:59:05.378310 MD32_EN : 0
2195 05:59:05.381852 ===================================
2196 05:59:05.385118 [ANA_INIT] >>>>>>>>>>>>>>
2197 05:59:05.388203 <<<<<< [CONFIGURE PHASE]: ANA_TX
2198 05:59:05.391791 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2199 05:59:05.394720 ===================================
2200 05:59:05.394804 data_rate = 2400,PCW = 0X5b00
2201 05:59:05.398439 ===================================
2202 05:59:05.401889 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2203 05:59:05.408383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 05:59:05.414975 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 05:59:05.418581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2206 05:59:05.421523 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2207 05:59:05.425145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2208 05:59:05.428623 [ANA_INIT] flow start
2209 05:59:05.431503 [ANA_INIT] PLL >>>>>>>>
2210 05:59:05.431588 [ANA_INIT] PLL <<<<<<<<
2211 05:59:05.435253 [ANA_INIT] MIDPI >>>>>>>>
2212 05:59:05.438313 [ANA_INIT] MIDPI <<<<<<<<
2213 05:59:05.438391 [ANA_INIT] DLL >>>>>>>>
2214 05:59:05.441836 [ANA_INIT] DLL <<<<<<<<
2215 05:59:05.444920 [ANA_INIT] flow end
2216 05:59:05.448412 ============ LP4 DIFF to SE enter ============
2217 05:59:05.451724 ============ LP4 DIFF to SE exit ============
2218 05:59:05.454906 [ANA_INIT] <<<<<<<<<<<<<
2219 05:59:05.458760 [Flow] Enable top DCM control >>>>>
2220 05:59:05.461472 [Flow] Enable top DCM control <<<<<
2221 05:59:05.464853 Enable DLL master slave shuffle
2222 05:59:05.468317 ==============================================================
2223 05:59:05.471953 Gating Mode config
2224 05:59:05.474795 ==============================================================
2225 05:59:05.478627 Config description:
2226 05:59:05.488306 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2227 05:59:05.495301 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2228 05:59:05.498053 SELPH_MODE 0: By rank 1: By Phase
2229 05:59:05.505265 ==============================================================
2230 05:59:05.508150 GAT_TRACK_EN = 1
2231 05:59:05.511706 RX_GATING_MODE = 2
2232 05:59:05.515265 RX_GATING_TRACK_MODE = 2
2233 05:59:05.518232 SELPH_MODE = 1
2234 05:59:05.521326 PICG_EARLY_EN = 1
2235 05:59:05.521448 VALID_LAT_VALUE = 1
2236 05:59:05.528487 ==============================================================
2237 05:59:05.531371 Enter into Gating configuration >>>>
2238 05:59:05.535277 Exit from Gating configuration <<<<
2239 05:59:05.538149 Enter into DVFS_PRE_config >>>>>
2240 05:59:05.548180 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2241 05:59:05.551259 Exit from DVFS_PRE_config <<<<<
2242 05:59:05.554921 Enter into PICG configuration >>>>
2243 05:59:05.557938 Exit from PICG configuration <<<<
2244 05:59:05.561462 [RX_INPUT] configuration >>>>>
2245 05:59:05.564954 [RX_INPUT] configuration <<<<<
2246 05:59:05.568302 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2247 05:59:05.575019 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2248 05:59:05.581690 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 05:59:05.588317 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 05:59:05.594955 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 05:59:05.598452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 05:59:05.605051 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2253 05:59:05.608657 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2254 05:59:05.611474 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2255 05:59:05.615048 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2256 05:59:05.618619 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2257 05:59:05.624685 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 05:59:05.628245 ===================================
2259 05:59:05.631791 LPDDR4 DRAM CONFIGURATION
2260 05:59:05.634668 ===================================
2261 05:59:05.634770 EX_ROW_EN[0] = 0x0
2262 05:59:05.638318 EX_ROW_EN[1] = 0x0
2263 05:59:05.638394 LP4Y_EN = 0x0
2264 05:59:05.641768 WORK_FSP = 0x0
2265 05:59:05.641874 WL = 0x4
2266 05:59:05.644616 RL = 0x4
2267 05:59:05.644690 BL = 0x2
2268 05:59:05.648297 RPST = 0x0
2269 05:59:05.648399 RD_PRE = 0x0
2270 05:59:05.651689 WR_PRE = 0x1
2271 05:59:05.651788 WR_PST = 0x0
2272 05:59:05.654817 DBI_WR = 0x0
2273 05:59:05.654894 DBI_RD = 0x0
2274 05:59:05.658461 OTF = 0x1
2275 05:59:05.661463 ===================================
2276 05:59:05.664630 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2277 05:59:05.668118 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2278 05:59:05.674560 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 05:59:05.677980 ===================================
2280 05:59:05.678064 LPDDR4 DRAM CONFIGURATION
2281 05:59:05.681526 ===================================
2282 05:59:05.684792 EX_ROW_EN[0] = 0x10
2283 05:59:05.688156 EX_ROW_EN[1] = 0x0
2284 05:59:05.688265 LP4Y_EN = 0x0
2285 05:59:05.691650 WORK_FSP = 0x0
2286 05:59:05.691767 WL = 0x4
2287 05:59:05.694385 RL = 0x4
2288 05:59:05.694480 BL = 0x2
2289 05:59:05.698335 RPST = 0x0
2290 05:59:05.698445 RD_PRE = 0x0
2291 05:59:05.701359 WR_PRE = 0x1
2292 05:59:05.701464 WR_PST = 0x0
2293 05:59:05.704138 DBI_WR = 0x0
2294 05:59:05.704243 DBI_RD = 0x0
2295 05:59:05.708036 OTF = 0x1
2296 05:59:05.711139 ===================================
2297 05:59:05.717872 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2298 05:59:05.717970 ==
2299 05:59:05.721448 Dram Type= 6, Freq= 0, CH_0, rank 0
2300 05:59:05.724803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2301 05:59:05.724888 ==
2302 05:59:05.727770 [Duty_Offset_Calibration]
2303 05:59:05.727868 B0:2 B1:0 CA:3
2304 05:59:05.727941
2305 05:59:05.731562 [DutyScan_Calibration_Flow] k_type=0
2306 05:59:05.741684
2307 05:59:05.741800 ==CLK 0==
2308 05:59:05.745145 Final CLK duty delay cell = 0
2309 05:59:05.748179 [0] MAX Duty = 5031%(X100), DQS PI = 12
2310 05:59:05.751666 [0] MIN Duty = 4875%(X100), DQS PI = 58
2311 05:59:05.751751 [0] AVG Duty = 4953%(X100)
2312 05:59:05.755349
2313 05:59:05.758280 CH0 CLK Duty spec in!! Max-Min= 156%
2314 05:59:05.761335 [DutyScan_Calibration_Flow] ====Done====
2315 05:59:05.761439
2316 05:59:05.764916 [DutyScan_Calibration_Flow] k_type=1
2317 05:59:05.779941
2318 05:59:05.780044 ==DQS 0 ==
2319 05:59:05.783395 Final DQS duty delay cell = 0
2320 05:59:05.786869 [0] MAX Duty = 5062%(X100), DQS PI = 12
2321 05:59:05.789808 [0] MIN Duty = 4907%(X100), DQS PI = 2
2322 05:59:05.789899 [0] AVG Duty = 4984%(X100)
2323 05:59:05.793326
2324 05:59:05.793407 ==DQS 1 ==
2325 05:59:05.796531 Final DQS duty delay cell = -4
2326 05:59:05.800027 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2327 05:59:05.803050 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2328 05:59:05.806589 [-4] AVG Duty = 4922%(X100)
2329 05:59:05.806677
2330 05:59:05.810175 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2331 05:59:05.810252
2332 05:59:05.813553 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2333 05:59:05.816671 [DutyScan_Calibration_Flow] ====Done====
2334 05:59:05.816748
2335 05:59:05.819980 [DutyScan_Calibration_Flow] k_type=3
2336 05:59:05.837822
2337 05:59:05.837934 ==DQM 0 ==
2338 05:59:05.840678 Final DQM duty delay cell = 0
2339 05:59:05.844289 [0] MAX Duty = 5124%(X100), DQS PI = 28
2340 05:59:05.847609 [0] MIN Duty = 4876%(X100), DQS PI = 0
2341 05:59:05.847688 [0] AVG Duty = 5000%(X100)
2342 05:59:05.851099
2343 05:59:05.851175 ==DQM 1 ==
2344 05:59:05.854048 Final DQM duty delay cell = 4
2345 05:59:05.857660 [4] MAX Duty = 5124%(X100), DQS PI = 50
2346 05:59:05.860745 [4] MIN Duty = 5000%(X100), DQS PI = 30
2347 05:59:05.860833 [4] AVG Duty = 5062%(X100)
2348 05:59:05.864197
2349 05:59:05.867763 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2350 05:59:05.867858
2351 05:59:05.873268 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2352 05:59:05.874397 [DutyScan_Calibration_Flow] ====Done====
2353 05:59:05.874473
2354 05:59:05.877667 [DutyScan_Calibration_Flow] k_type=2
2355 05:59:05.892223
2356 05:59:05.892358 ==DQ 0 ==
2357 05:59:05.895929 Final DQ duty delay cell = -4
2358 05:59:05.899342 [-4] MAX Duty = 5000%(X100), DQS PI = 12
2359 05:59:05.902557 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2360 05:59:05.905779 [-4] AVG Duty = 4953%(X100)
2361 05:59:05.905854
2362 05:59:05.905953 ==DQ 1 ==
2363 05:59:05.909130 Final DQ duty delay cell = -4
2364 05:59:05.912744 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2365 05:59:05.915702 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2366 05:59:05.919215 [-4] AVG Duty = 4938%(X100)
2367 05:59:05.919318
2368 05:59:05.922203 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2369 05:59:05.922303
2370 05:59:05.925745 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2371 05:59:05.929002 [DutyScan_Calibration_Flow] ====Done====
2372 05:59:05.929101 ==
2373 05:59:05.932285 Dram Type= 6, Freq= 0, CH_1, rank 0
2374 05:59:05.935506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 05:59:05.935589 ==
2376 05:59:05.938862 [Duty_Offset_Calibration]
2377 05:59:05.938943 B0:1 B1:-2 CA:0
2378 05:59:05.939009
2379 05:59:05.942179 [DutyScan_Calibration_Flow] k_type=0
2380 05:59:05.953117
2381 05:59:05.953203 ==CLK 0==
2382 05:59:05.955976 Final CLK duty delay cell = 0
2383 05:59:05.959791 [0] MAX Duty = 5062%(X100), DQS PI = 30
2384 05:59:05.962782 [0] MIN Duty = 4875%(X100), DQS PI = 58
2385 05:59:05.962863 [0] AVG Duty = 4968%(X100)
2386 05:59:05.966423
2387 05:59:05.966502 CH1 CLK Duty spec in!! Max-Min= 187%
2388 05:59:05.973066 [DutyScan_Calibration_Flow] ====Done====
2389 05:59:05.973149
2390 05:59:05.975982 [DutyScan_Calibration_Flow] k_type=1
2391 05:59:05.991184
2392 05:59:05.991307 ==DQS 0 ==
2393 05:59:05.994755 Final DQS duty delay cell = -4
2394 05:59:05.998298 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2395 05:59:06.001324 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2396 05:59:06.004731 [-4] AVG Duty = 4953%(X100)
2397 05:59:06.004826
2398 05:59:06.004890 ==DQS 1 ==
2399 05:59:06.007624 Final DQS duty delay cell = 0
2400 05:59:06.010870 [0] MAX Duty = 5093%(X100), DQS PI = 0
2401 05:59:06.014525 [0] MIN Duty = 4875%(X100), DQS PI = 26
2402 05:59:06.017699 [0] AVG Duty = 4984%(X100)
2403 05:59:06.017795
2404 05:59:06.021123 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2405 05:59:06.021225
2406 05:59:06.024721 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2407 05:59:06.027750 [DutyScan_Calibration_Flow] ====Done====
2408 05:59:06.027853
2409 05:59:06.031304 [DutyScan_Calibration_Flow] k_type=3
2410 05:59:06.047745
2411 05:59:06.047870 ==DQM 0 ==
2412 05:59:06.051425 Final DQM duty delay cell = 0
2413 05:59:06.054850 [0] MAX Duty = 5000%(X100), DQS PI = 22
2414 05:59:06.057986 [0] MIN Duty = 4844%(X100), DQS PI = 52
2415 05:59:06.061352 [0] AVG Duty = 4922%(X100)
2416 05:59:06.061433
2417 05:59:06.061504 ==DQM 1 ==
2418 05:59:06.064847 Final DQM duty delay cell = 0
2419 05:59:06.067771 [0] MAX Duty = 5031%(X100), DQS PI = 36
2420 05:59:06.071168 [0] MIN Duty = 4907%(X100), DQS PI = 0
2421 05:59:06.071252 [0] AVG Duty = 4969%(X100)
2422 05:59:06.074483
2423 05:59:06.078007 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2424 05:59:06.078119
2425 05:59:06.081574 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2426 05:59:06.084433 [DutyScan_Calibration_Flow] ====Done====
2427 05:59:06.084557
2428 05:59:06.087712 [DutyScan_Calibration_Flow] k_type=2
2429 05:59:06.104073
2430 05:59:06.104169 ==DQ 0 ==
2431 05:59:06.107625 Final DQ duty delay cell = 0
2432 05:59:06.111436 [0] MAX Duty = 5062%(X100), DQS PI = 18
2433 05:59:06.114422 [0] MIN Duty = 4938%(X100), DQS PI = 54
2434 05:59:06.114507 [0] AVG Duty = 5000%(X100)
2435 05:59:06.114576
2436 05:59:06.117855 ==DQ 1 ==
2437 05:59:06.121416 Final DQ duty delay cell = 0
2438 05:59:06.124181 [0] MAX Duty = 5125%(X100), DQS PI = 34
2439 05:59:06.127932 [0] MIN Duty = 4969%(X100), DQS PI = 26
2440 05:59:06.128051 [0] AVG Duty = 5047%(X100)
2441 05:59:06.128145
2442 05:59:06.130750 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2443 05:59:06.134341
2444 05:59:06.137428 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2445 05:59:06.141031 [DutyScan_Calibration_Flow] ====Done====
2446 05:59:06.144025 nWR fixed to 30
2447 05:59:06.144110 [ModeRegInit_LP4] CH0 RK0
2448 05:59:06.147680 [ModeRegInit_LP4] CH0 RK1
2449 05:59:06.151105 [ModeRegInit_LP4] CH1 RK0
2450 05:59:06.154443 [ModeRegInit_LP4] CH1 RK1
2451 05:59:06.154530 match AC timing 7
2452 05:59:06.157517 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2453 05:59:06.164072 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2454 05:59:06.167721 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2455 05:59:06.170813 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2456 05:59:06.177387 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2457 05:59:06.177491 ==
2458 05:59:06.180702 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 05:59:06.184001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2460 05:59:06.184109 ==
2461 05:59:06.190689 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2462 05:59:06.194135 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2463 05:59:06.204428 [CA 0] Center 40 (10~71) winsize 62
2464 05:59:06.207456 [CA 1] Center 39 (9~70) winsize 62
2465 05:59:06.210955 [CA 2] Center 36 (6~66) winsize 61
2466 05:59:06.214064 [CA 3] Center 35 (5~66) winsize 62
2467 05:59:06.217680 [CA 4] Center 34 (4~65) winsize 62
2468 05:59:06.220718 [CA 5] Center 33 (3~63) winsize 61
2469 05:59:06.220827
2470 05:59:06.224409 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2471 05:59:06.224528
2472 05:59:06.228093 [CATrainingPosCal] consider 1 rank data
2473 05:59:06.230946 u2DelayCellTimex100 = 270/100 ps
2474 05:59:06.234315 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2475 05:59:06.241047 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2476 05:59:06.244205 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2477 05:59:06.247877 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2478 05:59:06.250868 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2479 05:59:06.254453 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2480 05:59:06.254565
2481 05:59:06.257989 CA PerBit enable=1, Macro0, CA PI delay=33
2482 05:59:06.258098
2483 05:59:06.261094 [CBTSetCACLKResult] CA Dly = 33
2484 05:59:06.261200 CS Dly: 7 (0~38)
2485 05:59:06.264333 ==
2486 05:59:06.264445 Dram Type= 6, Freq= 0, CH_0, rank 1
2487 05:59:06.271288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2488 05:59:06.271405 ==
2489 05:59:06.274329 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2490 05:59:06.281259 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2491 05:59:06.290683 [CA 0] Center 40 (10~71) winsize 62
2492 05:59:06.293521 [CA 1] Center 40 (10~70) winsize 61
2493 05:59:06.297301 [CA 2] Center 35 (5~66) winsize 62
2494 05:59:06.300233 [CA 3] Center 35 (5~66) winsize 62
2495 05:59:06.303711 [CA 4] Center 34 (4~65) winsize 62
2496 05:59:06.306913 [CA 5] Center 33 (3~63) winsize 61
2497 05:59:06.307024
2498 05:59:06.310476 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2499 05:59:06.310598
2500 05:59:06.313433 [CATrainingPosCal] consider 2 rank data
2501 05:59:06.317127 u2DelayCellTimex100 = 270/100 ps
2502 05:59:06.320132 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2503 05:59:06.326712 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2504 05:59:06.330380 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2505 05:59:06.333829 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 05:59:06.336943 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2507 05:59:06.340411 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2508 05:59:06.340490
2509 05:59:06.343554 CA PerBit enable=1, Macro0, CA PI delay=33
2510 05:59:06.343656
2511 05:59:06.346896 [CBTSetCACLKResult] CA Dly = 33
2512 05:59:06.350364 CS Dly: 8 (0~40)
2513 05:59:06.350466
2514 05:59:06.353912 ----->DramcWriteLeveling(PI) begin...
2515 05:59:06.354021 ==
2516 05:59:06.356966 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 05:59:06.360512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 05:59:06.360632 ==
2519 05:59:06.363396 Write leveling (Byte 0): 34 => 34
2520 05:59:06.367006 Write leveling (Byte 1): 30 => 30
2521 05:59:06.370043 DramcWriteLeveling(PI) end<-----
2522 05:59:06.370154
2523 05:59:06.370254 ==
2524 05:59:06.373671 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 05:59:06.377262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 05:59:06.377376 ==
2527 05:59:06.380367 [Gating] SW mode calibration
2528 05:59:06.387037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2529 05:59:06.393671 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2530 05:59:06.397134 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 05:59:06.400133 0 15 4 | B1->B0 | 2929 3333 | 0 1 | (1 1) (1 1)
2532 05:59:06.407234 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 05:59:06.409940 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 05:59:06.413700 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 05:59:06.420004 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 05:59:06.423480 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 05:59:06.426989 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 05:59:06.430063 1 0 0 | B1->B0 | 3030 2727 | 1 0 | (1 1) (0 1)
2539 05:59:06.436725 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2540 05:59:06.440258 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 05:59:06.443559 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 05:59:06.450392 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 05:59:06.453583 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 05:59:06.456877 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 05:59:06.463448 1 0 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2546 05:59:06.466901 1 1 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
2547 05:59:06.470538 1 1 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2548 05:59:06.477211 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 05:59:06.480204 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 05:59:06.483894 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 05:59:06.490327 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 05:59:06.493727 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 05:59:06.497071 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2554 05:59:06.503365 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2555 05:59:06.506785 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 05:59:06.510365 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 05:59:06.517058 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 05:59:06.520433 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 05:59:06.523216 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 05:59:06.530188 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 05:59:06.533445 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 05:59:06.537042 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 05:59:06.540009 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 05:59:06.546714 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 05:59:06.550328 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 05:59:06.553286 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 05:59:06.559989 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 05:59:06.563424 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 05:59:06.566958 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 05:59:06.573629 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2571 05:59:06.576586 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2572 05:59:06.580227 Total UI for P1: 0, mck2ui 16
2573 05:59:06.583293 best dqsien dly found for B0: ( 1, 4, 0)
2574 05:59:06.586767 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 05:59:06.590256 Total UI for P1: 0, mck2ui 16
2576 05:59:06.593256 best dqsien dly found for B1: ( 1, 4, 2)
2577 05:59:06.597016 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2578 05:59:06.599837 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2579 05:59:06.599961
2580 05:59:06.603215 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2581 05:59:06.610275 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2582 05:59:06.610400 [Gating] SW calibration Done
2583 05:59:06.610499 ==
2584 05:59:06.613592 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 05:59:06.620018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 05:59:06.620145 ==
2587 05:59:06.620251 RX Vref Scan: 0
2588 05:59:06.620344
2589 05:59:06.623593 RX Vref 0 -> 0, step: 1
2590 05:59:06.623670
2591 05:59:06.626481 RX Delay -40 -> 252, step: 8
2592 05:59:06.629855 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2593 05:59:06.633122 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2594 05:59:06.636821 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2595 05:59:06.643468 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2596 05:59:06.646427 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2597 05:59:06.650010 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2598 05:59:06.653541 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2599 05:59:06.656569 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2600 05:59:06.659944 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2601 05:59:06.666737 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2602 05:59:06.669898 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2603 05:59:06.673242 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2604 05:59:06.676729 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2605 05:59:06.679784 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2606 05:59:06.686431 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2607 05:59:06.689931 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2608 05:59:06.690020 ==
2609 05:59:06.693343 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 05:59:06.696306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 05:59:06.696391 ==
2612 05:59:06.699754 DQS Delay:
2613 05:59:06.699841 DQS0 = 0, DQS1 = 0
2614 05:59:06.699906 DQM Delay:
2615 05:59:06.703311 DQM0 = 112, DQM1 = 102
2616 05:59:06.703394 DQ Delay:
2617 05:59:06.706397 DQ0 =111, DQ1 =115, DQ2 =111, DQ3 =107
2618 05:59:06.709819 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2619 05:59:06.713409 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2620 05:59:06.720091 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2621 05:59:06.720187
2622 05:59:06.720253
2623 05:59:06.720314 ==
2624 05:59:06.723320 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 05:59:06.726461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 05:59:06.726547 ==
2627 05:59:06.726612
2628 05:59:06.726674
2629 05:59:06.729728 TX Vref Scan disable
2630 05:59:06.729828 == TX Byte 0 ==
2631 05:59:06.736246 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2632 05:59:06.739695 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2633 05:59:06.739799 == TX Byte 1 ==
2634 05:59:06.746460 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2635 05:59:06.749679 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2636 05:59:06.749803 ==
2637 05:59:06.753036 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 05:59:06.756547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 05:59:06.756686 ==
2640 05:59:06.769116 TX Vref=22, minBit 0, minWin=25, winSum=413
2641 05:59:06.772649 TX Vref=24, minBit 0, minWin=25, winSum=416
2642 05:59:06.775948 TX Vref=26, minBit 7, minWin=25, winSum=426
2643 05:59:06.779248 TX Vref=28, minBit 4, minWin=26, winSum=430
2644 05:59:06.782618 TX Vref=30, minBit 13, minWin=26, winSum=431
2645 05:59:06.786258 TX Vref=32, minBit 2, minWin=26, winSum=425
2646 05:59:06.792776 [TxChooseVref] Worse bit 13, Min win 26, Win sum 431, Final Vref 30
2647 05:59:06.792869
2648 05:59:06.795866 Final TX Range 1 Vref 30
2649 05:59:06.795977
2650 05:59:06.796066 ==
2651 05:59:06.799243 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 05:59:06.803090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 05:59:06.803199 ==
2654 05:59:06.806098
2655 05:59:06.806207
2656 05:59:06.806300 TX Vref Scan disable
2657 05:59:06.808918 == TX Byte 0 ==
2658 05:59:06.812474 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2659 05:59:06.815641 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2660 05:59:06.819154 == TX Byte 1 ==
2661 05:59:06.822626 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2662 05:59:06.826226 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2663 05:59:06.828960
2664 05:59:06.829067 [DATLAT]
2665 05:59:06.829163 Freq=1200, CH0 RK0
2666 05:59:06.829260
2667 05:59:06.832420 DATLAT Default: 0xd
2668 05:59:06.832527 0, 0xFFFF, sum = 0
2669 05:59:06.835728 1, 0xFFFF, sum = 0
2670 05:59:06.835807 2, 0xFFFF, sum = 0
2671 05:59:06.839376 3, 0xFFFF, sum = 0
2672 05:59:06.839457 4, 0xFFFF, sum = 0
2673 05:59:06.842582 5, 0xFFFF, sum = 0
2674 05:59:06.845981 6, 0xFFFF, sum = 0
2675 05:59:06.846069 7, 0xFFFF, sum = 0
2676 05:59:06.849604 8, 0xFFFF, sum = 0
2677 05:59:06.849691 9, 0xFFFF, sum = 0
2678 05:59:06.852318 10, 0xFFFF, sum = 0
2679 05:59:06.852421 11, 0xFFFF, sum = 0
2680 05:59:06.855725 12, 0x0, sum = 1
2681 05:59:06.855803 13, 0x0, sum = 2
2682 05:59:06.859047 14, 0x0, sum = 3
2683 05:59:06.859127 15, 0x0, sum = 4
2684 05:59:06.859192 best_step = 13
2685 05:59:06.859252
2686 05:59:06.862523 ==
2687 05:59:06.866122 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 05:59:06.869694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 05:59:06.869771 ==
2690 05:59:06.869843 RX Vref Scan: 1
2691 05:59:06.869905
2692 05:59:06.872622 Set Vref Range= 32 -> 127
2693 05:59:06.872721
2694 05:59:06.876152 RX Vref 32 -> 127, step: 1
2695 05:59:06.876251
2696 05:59:06.879109 RX Delay -37 -> 252, step: 4
2697 05:59:06.879206
2698 05:59:06.882536 Set Vref, RX VrefLevel [Byte0]: 32
2699 05:59:06.885947 [Byte1]: 32
2700 05:59:06.886030
2701 05:59:06.889391 Set Vref, RX VrefLevel [Byte0]: 33
2702 05:59:06.892153 [Byte1]: 33
2703 05:59:06.895762
2704 05:59:06.895875 Set Vref, RX VrefLevel [Byte0]: 34
2705 05:59:06.899282 [Byte1]: 34
2706 05:59:06.903881
2707 05:59:06.903992 Set Vref, RX VrefLevel [Byte0]: 35
2708 05:59:06.907434 [Byte1]: 35
2709 05:59:06.911612
2710 05:59:06.911686 Set Vref, RX VrefLevel [Byte0]: 36
2711 05:59:06.915179 [Byte1]: 36
2712 05:59:06.919903
2713 05:59:06.919976 Set Vref, RX VrefLevel [Byte0]: 37
2714 05:59:06.922860 [Byte1]: 37
2715 05:59:06.927613
2716 05:59:06.927720 Set Vref, RX VrefLevel [Byte0]: 38
2717 05:59:06.930968 [Byte1]: 38
2718 05:59:06.935757
2719 05:59:06.935867 Set Vref, RX VrefLevel [Byte0]: 39
2720 05:59:06.939284 [Byte1]: 39
2721 05:59:06.943776
2722 05:59:06.943887 Set Vref, RX VrefLevel [Byte0]: 40
2723 05:59:06.947172 [Byte1]: 40
2724 05:59:06.952133
2725 05:59:06.952242 Set Vref, RX VrefLevel [Byte0]: 41
2726 05:59:06.955311 [Byte1]: 41
2727 05:59:06.960033
2728 05:59:06.960155 Set Vref, RX VrefLevel [Byte0]: 42
2729 05:59:06.962961 [Byte1]: 42
2730 05:59:06.967928
2731 05:59:06.968041 Set Vref, RX VrefLevel [Byte0]: 43
2732 05:59:06.971229 [Byte1]: 43
2733 05:59:06.975987
2734 05:59:06.976094 Set Vref, RX VrefLevel [Byte0]: 44
2735 05:59:06.979079 [Byte1]: 44
2736 05:59:06.983941
2737 05:59:06.984051 Set Vref, RX VrefLevel [Byte0]: 45
2738 05:59:06.987084 [Byte1]: 45
2739 05:59:06.991847
2740 05:59:06.991954 Set Vref, RX VrefLevel [Byte0]: 46
2741 05:59:06.995105 [Byte1]: 46
2742 05:59:06.999899
2743 05:59:07.000007 Set Vref, RX VrefLevel [Byte0]: 47
2744 05:59:07.002999 [Byte1]: 47
2745 05:59:07.007646
2746 05:59:07.007758 Set Vref, RX VrefLevel [Byte0]: 48
2747 05:59:07.011293 [Byte1]: 48
2748 05:59:07.016119
2749 05:59:07.016225 Set Vref, RX VrefLevel [Byte0]: 49
2750 05:59:07.019005 [Byte1]: 49
2751 05:59:07.023793
2752 05:59:07.023898 Set Vref, RX VrefLevel [Byte0]: 50
2753 05:59:07.026894 [Byte1]: 50
2754 05:59:07.031622
2755 05:59:07.031702 Set Vref, RX VrefLevel [Byte0]: 51
2756 05:59:07.035335 [Byte1]: 51
2757 05:59:07.039862
2758 05:59:07.039984 Set Vref, RX VrefLevel [Byte0]: 52
2759 05:59:07.043432 [Byte1]: 52
2760 05:59:07.047808
2761 05:59:07.047933 Set Vref, RX VrefLevel [Byte0]: 53
2762 05:59:07.051495 [Byte1]: 53
2763 05:59:07.055998
2764 05:59:07.056100 Set Vref, RX VrefLevel [Byte0]: 54
2765 05:59:07.058952 [Byte1]: 54
2766 05:59:07.063586
2767 05:59:07.063678 Set Vref, RX VrefLevel [Byte0]: 55
2768 05:59:07.067519 [Byte1]: 55
2769 05:59:07.071787
2770 05:59:07.071917 Set Vref, RX VrefLevel [Byte0]: 56
2771 05:59:07.074930 [Byte1]: 56
2772 05:59:07.079755
2773 05:59:07.079857 Set Vref, RX VrefLevel [Byte0]: 57
2774 05:59:07.083320 [Byte1]: 57
2775 05:59:07.087624
2776 05:59:07.087699 Set Vref, RX VrefLevel [Byte0]: 58
2777 05:59:07.091508 [Byte1]: 58
2778 05:59:07.095663
2779 05:59:07.095786 Set Vref, RX VrefLevel [Byte0]: 59
2780 05:59:07.099214 [Byte1]: 59
2781 05:59:07.103693
2782 05:59:07.103818 Set Vref, RX VrefLevel [Byte0]: 60
2783 05:59:07.106894 [Byte1]: 60
2784 05:59:07.111566
2785 05:59:07.111688 Set Vref, RX VrefLevel [Byte0]: 61
2786 05:59:07.115112 [Byte1]: 61
2787 05:59:07.119719
2788 05:59:07.119824 Set Vref, RX VrefLevel [Byte0]: 62
2789 05:59:07.122866 [Byte1]: 62
2790 05:59:07.127938
2791 05:59:07.128047 Set Vref, RX VrefLevel [Byte0]: 63
2792 05:59:07.130899 [Byte1]: 63
2793 05:59:07.135566
2794 05:59:07.135670 Set Vref, RX VrefLevel [Byte0]: 64
2795 05:59:07.139076 [Byte1]: 64
2796 05:59:07.143671
2797 05:59:07.143785 Set Vref, RX VrefLevel [Byte0]: 65
2798 05:59:07.146993 [Byte1]: 65
2799 05:59:07.151613
2800 05:59:07.151721 Set Vref, RX VrefLevel [Byte0]: 66
2801 05:59:07.154976 [Byte1]: 66
2802 05:59:07.159683
2803 05:59:07.159799 Set Vref, RX VrefLevel [Byte0]: 67
2804 05:59:07.163256 [Byte1]: 67
2805 05:59:07.167867
2806 05:59:07.167971 Set Vref, RX VrefLevel [Byte0]: 68
2807 05:59:07.171380 [Byte1]: 68
2808 05:59:07.175819
2809 05:59:07.175936 Set Vref, RX VrefLevel [Byte0]: 69
2810 05:59:07.179104 [Byte1]: 69
2811 05:59:07.184010
2812 05:59:07.184123 Set Vref, RX VrefLevel [Byte0]: 70
2813 05:59:07.187159 [Byte1]: 70
2814 05:59:07.192033
2815 05:59:07.192138 Set Vref, RX VrefLevel [Byte0]: 71
2816 05:59:07.195247 [Byte1]: 71
2817 05:59:07.200119
2818 05:59:07.200216 Set Vref, RX VrefLevel [Byte0]: 72
2819 05:59:07.203475 [Byte1]: 72
2820 05:59:07.208186
2821 05:59:07.208274 Set Vref, RX VrefLevel [Byte0]: 73
2822 05:59:07.211438 [Byte1]: 73
2823 05:59:07.215647
2824 05:59:07.215735 Final RX Vref Byte 0 = 61 to rank0
2825 05:59:07.219511 Final RX Vref Byte 1 = 47 to rank0
2826 05:59:07.222559 Final RX Vref Byte 0 = 61 to rank1
2827 05:59:07.226155 Final RX Vref Byte 1 = 47 to rank1==
2828 05:59:07.228968 Dram Type= 6, Freq= 0, CH_0, rank 0
2829 05:59:07.236106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 05:59:07.236204 ==
2831 05:59:07.236304 DQS Delay:
2832 05:59:07.236382 DQS0 = 0, DQS1 = 0
2833 05:59:07.239188 DQM Delay:
2834 05:59:07.239300 DQM0 = 112, DQM1 = 98
2835 05:59:07.242671 DQ Delay:
2836 05:59:07.246017 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2837 05:59:07.249044 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2838 05:59:07.252419 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2839 05:59:07.256155 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =108
2840 05:59:07.256253
2841 05:59:07.256343
2842 05:59:07.262533 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdfd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2843 05:59:07.266000 CH0 RK0: MR19=303, MR18=FDFD
2844 05:59:07.272527 CH0_RK0: MR19=0x303, MR18=0xFDFD, DQSOSC=411, MR23=63, INC=38, DEC=25
2845 05:59:07.272644
2846 05:59:07.276017 ----->DramcWriteLeveling(PI) begin...
2847 05:59:07.276126 ==
2848 05:59:07.279162 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 05:59:07.282328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 05:59:07.282443 ==
2851 05:59:07.285805 Write leveling (Byte 0): 31 => 31
2852 05:59:07.289292 Write leveling (Byte 1): 31 => 31
2853 05:59:07.292873 DramcWriteLeveling(PI) end<-----
2854 05:59:07.292993
2855 05:59:07.293125 ==
2856 05:59:07.295674 Dram Type= 6, Freq= 0, CH_0, rank 1
2857 05:59:07.302354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2858 05:59:07.302445 ==
2859 05:59:07.302510 [Gating] SW mode calibration
2860 05:59:07.312389 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2861 05:59:07.315543 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2862 05:59:07.319325 0 15 0 | B1->B0 | 2928 3434 | 1 0 | (0 0) (0 0)
2863 05:59:07.325722 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 05:59:07.329092 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 05:59:07.332184 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 05:59:07.339151 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 05:59:07.342277 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 05:59:07.345733 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2869 05:59:07.352260 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
2870 05:59:07.355749 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2871 05:59:07.359156 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 05:59:07.365817 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 05:59:07.369241 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 05:59:07.372794 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 05:59:07.379159 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 05:59:07.382129 1 0 24 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
2877 05:59:07.385732 1 0 28 | B1->B0 | 2424 4141 | 0 1 | (0 0) (0 0)
2878 05:59:07.389099 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2879 05:59:07.395625 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 05:59:07.399105 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 05:59:07.402637 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 05:59:07.409071 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 05:59:07.412632 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 05:59:07.415606 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 05:59:07.422269 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2886 05:59:07.425982 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2887 05:59:07.429331 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 05:59:07.436019 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 05:59:07.438968 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 05:59:07.442623 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 05:59:07.449062 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 05:59:07.452745 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 05:59:07.455749 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 05:59:07.462221 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 05:59:07.465382 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 05:59:07.468700 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 05:59:07.475872 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 05:59:07.478971 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 05:59:07.482309 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 05:59:07.488501 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2901 05:59:07.492026 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2902 05:59:07.495662 Total UI for P1: 0, mck2ui 16
2903 05:59:07.498660 best dqsien dly found for B0: ( 1, 3, 24)
2904 05:59:07.502157 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2905 05:59:07.508585 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 05:59:07.508688 Total UI for P1: 0, mck2ui 16
2907 05:59:07.512155 best dqsien dly found for B1: ( 1, 3, 30)
2908 05:59:07.518747 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2909 05:59:07.522291 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2910 05:59:07.522376
2911 05:59:07.525276 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2912 05:59:07.528825 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2913 05:59:07.531879 [Gating] SW calibration Done
2914 05:59:07.531979 ==
2915 05:59:07.535374 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 05:59:07.538550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 05:59:07.538635 ==
2918 05:59:07.541956 RX Vref Scan: 0
2919 05:59:07.542057
2920 05:59:07.542153 RX Vref 0 -> 0, step: 1
2921 05:59:07.542227
2922 05:59:07.545267 RX Delay -40 -> 252, step: 8
2923 05:59:07.548454 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2924 05:59:07.555061 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2925 05:59:07.558463 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2926 05:59:07.561946 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2927 05:59:07.565419 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2928 05:59:07.568466 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2929 05:59:07.571998 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2930 05:59:07.578765 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2931 05:59:07.582283 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2932 05:59:07.585038 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2933 05:59:07.588906 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2934 05:59:07.592034 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2935 05:59:07.598284 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2936 05:59:07.602101 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2937 05:59:07.605013 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2938 05:59:07.608667 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2939 05:59:07.608779 ==
2940 05:59:07.612136 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 05:59:07.614998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 05:59:07.618812 ==
2943 05:59:07.618898 DQS Delay:
2944 05:59:07.618984 DQS0 = 0, DQS1 = 0
2945 05:59:07.622229 DQM Delay:
2946 05:59:07.622313 DQM0 = 111, DQM1 = 101
2947 05:59:07.625180 DQ Delay:
2948 05:59:07.628848 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2949 05:59:07.631887 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2950 05:59:07.635397 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2951 05:59:07.638559 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2952 05:59:07.638644
2953 05:59:07.638730
2954 05:59:07.638811 ==
2955 05:59:07.641893 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 05:59:07.645411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 05:59:07.645540 ==
2958 05:59:07.645627
2959 05:59:07.645708
2960 05:59:07.648740 TX Vref Scan disable
2961 05:59:07.652221 == TX Byte 0 ==
2962 05:59:07.655633 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2963 05:59:07.658530 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2964 05:59:07.662338 == TX Byte 1 ==
2965 05:59:07.665309 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2966 05:59:07.668478 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2967 05:59:07.668564 ==
2968 05:59:07.672025 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 05:59:07.675587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 05:59:07.678487 ==
2971 05:59:07.688439 TX Vref=22, minBit 2, minWin=26, winSum=423
2972 05:59:07.692060 TX Vref=24, minBit 5, minWin=26, winSum=433
2973 05:59:07.695742 TX Vref=26, minBit 1, minWin=26, winSum=436
2974 05:59:07.698500 TX Vref=28, minBit 1, minWin=27, winSum=442
2975 05:59:07.702016 TX Vref=30, minBit 5, minWin=27, winSum=441
2976 05:59:07.705370 TX Vref=32, minBit 2, minWin=27, winSum=438
2977 05:59:07.712016 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 28
2978 05:59:07.712103
2979 05:59:07.715172 Final TX Range 1 Vref 28
2980 05:59:07.715271
2981 05:59:07.715350 ==
2982 05:59:07.718783 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 05:59:07.722272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 05:59:07.722354 ==
2985 05:59:07.722449
2986 05:59:07.725262
2987 05:59:07.725343 TX Vref Scan disable
2988 05:59:07.728760 == TX Byte 0 ==
2989 05:59:07.731836 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2990 05:59:07.735425 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2991 05:59:07.738904 == TX Byte 1 ==
2992 05:59:07.741752 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2993 05:59:07.745292 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2994 05:59:07.745417
2995 05:59:07.748955 [DATLAT]
2996 05:59:07.749055 Freq=1200, CH0 RK1
2997 05:59:07.749146
2998 05:59:07.752258 DATLAT Default: 0xd
2999 05:59:07.752340 0, 0xFFFF, sum = 0
3000 05:59:07.755199 1, 0xFFFF, sum = 0
3001 05:59:07.755283 2, 0xFFFF, sum = 0
3002 05:59:07.758538 3, 0xFFFF, sum = 0
3003 05:59:07.758622 4, 0xFFFF, sum = 0
3004 05:59:07.762169 5, 0xFFFF, sum = 0
3005 05:59:07.762252 6, 0xFFFF, sum = 0
3006 05:59:07.765584 7, 0xFFFF, sum = 0
3007 05:59:07.765667 8, 0xFFFF, sum = 0
3008 05:59:07.768614 9, 0xFFFF, sum = 0
3009 05:59:07.768697 10, 0xFFFF, sum = 0
3010 05:59:07.771869 11, 0xFFFF, sum = 0
3011 05:59:07.771953 12, 0x0, sum = 1
3012 05:59:07.775593 13, 0x0, sum = 2
3013 05:59:07.775698 14, 0x0, sum = 3
3014 05:59:07.778657 15, 0x0, sum = 4
3015 05:59:07.778740 best_step = 13
3016 05:59:07.778805
3017 05:59:07.778865 ==
3018 05:59:07.782420 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 05:59:07.788665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 05:59:07.788749 ==
3021 05:59:07.788863 RX Vref Scan: 0
3022 05:59:07.788942
3023 05:59:07.792277 RX Vref 0 -> 0, step: 1
3024 05:59:07.792358
3025 05:59:07.795290 RX Delay -37 -> 252, step: 4
3026 05:59:07.798752 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3027 05:59:07.802147 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3028 05:59:07.809179 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3029 05:59:07.812313 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3030 05:59:07.815606 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3031 05:59:07.818921 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3032 05:59:07.822160 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3033 05:59:07.829203 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3034 05:59:07.832557 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3035 05:59:07.835513 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3036 05:59:07.839110 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3037 05:59:07.842085 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3038 05:59:07.845837 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3039 05:59:07.852225 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3040 05:59:07.855523 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3041 05:59:07.858796 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3042 05:59:07.858878 ==
3043 05:59:07.862764 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 05:59:07.865527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 05:59:07.869220 ==
3046 05:59:07.869301 DQS Delay:
3047 05:59:07.869366 DQS0 = 0, DQS1 = 0
3048 05:59:07.872217 DQM Delay:
3049 05:59:07.872297 DQM0 = 111, DQM1 = 100
3050 05:59:07.875729 DQ Delay:
3051 05:59:07.878856 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3052 05:59:07.882298 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3053 05:59:07.885494 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =92
3054 05:59:07.889044 DQ12 =108, DQ13 =106, DQ14 =114, DQ15 =110
3055 05:59:07.889126
3056 05:59:07.889190
3057 05:59:07.895664 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3058 05:59:07.898634 CH0 RK1: MR19=403, MR18=13FB
3059 05:59:07.905459 CH0_RK1: MR19=0x403, MR18=0x13FB, DQSOSC=402, MR23=63, INC=40, DEC=27
3060 05:59:07.909144 [RxdqsGatingPostProcess] freq 1200
3061 05:59:07.915692 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3062 05:59:07.915779 best DQS0 dly(2T, 0.5T) = (0, 12)
3063 05:59:07.918621 best DQS1 dly(2T, 0.5T) = (0, 12)
3064 05:59:07.921896 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3065 05:59:07.925401 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3066 05:59:07.928775 best DQS0 dly(2T, 0.5T) = (0, 11)
3067 05:59:07.932205 best DQS1 dly(2T, 0.5T) = (0, 11)
3068 05:59:07.935469 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3069 05:59:07.938808 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3070 05:59:07.941887 Pre-setting of DQS Precalculation
3071 05:59:07.945358 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3072 05:59:07.948967 ==
3073 05:59:07.952029 Dram Type= 6, Freq= 0, CH_1, rank 0
3074 05:59:07.955615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 05:59:07.955698 ==
3076 05:59:07.958428 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3077 05:59:07.965009 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3078 05:59:07.974527 [CA 0] Center 37 (7~67) winsize 61
3079 05:59:07.977905 [CA 1] Center 38 (8~68) winsize 61
3080 05:59:07.981589 [CA 2] Center 34 (4~64) winsize 61
3081 05:59:07.984348 [CA 3] Center 34 (4~64) winsize 61
3082 05:59:07.987998 [CA 4] Center 34 (4~64) winsize 61
3083 05:59:07.991485 [CA 5] Center 33 (3~63) winsize 61
3084 05:59:07.991569
3085 05:59:07.994440 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3086 05:59:07.994553
3087 05:59:07.997738 [CATrainingPosCal] consider 1 rank data
3088 05:59:08.001422 u2DelayCellTimex100 = 270/100 ps
3089 05:59:08.004371 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3090 05:59:08.008091 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3091 05:59:08.014424 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 05:59:08.018090 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3093 05:59:08.021574 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3094 05:59:08.024484 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3095 05:59:08.024566
3096 05:59:08.027986 CA PerBit enable=1, Macro0, CA PI delay=33
3097 05:59:08.028068
3098 05:59:08.031405 [CBTSetCACLKResult] CA Dly = 33
3099 05:59:08.031487 CS Dly: 5 (0~36)
3100 05:59:08.031567 ==
3101 05:59:08.034474 Dram Type= 6, Freq= 0, CH_1, rank 1
3102 05:59:08.041320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 05:59:08.041421 ==
3104 05:59:08.044160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3105 05:59:08.051173 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3106 05:59:08.060310 [CA 0] Center 37 (7~68) winsize 62
3107 05:59:08.063743 [CA 1] Center 37 (7~68) winsize 62
3108 05:59:08.066742 [CA 2] Center 34 (4~65) winsize 62
3109 05:59:08.070159 [CA 3] Center 33 (3~64) winsize 62
3110 05:59:08.073387 [CA 4] Center 34 (4~64) winsize 61
3111 05:59:08.076659 [CA 5] Center 33 (3~63) winsize 61
3112 05:59:08.076741
3113 05:59:08.080454 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3114 05:59:08.080536
3115 05:59:08.083702 [CATrainingPosCal] consider 2 rank data
3116 05:59:08.086737 u2DelayCellTimex100 = 270/100 ps
3117 05:59:08.090195 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3118 05:59:08.093890 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3119 05:59:08.099996 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3120 05:59:08.103613 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3121 05:59:08.107077 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 05:59:08.110021 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3123 05:59:08.110103
3124 05:59:08.113330 CA PerBit enable=1, Macro0, CA PI delay=33
3125 05:59:08.113437
3126 05:59:08.116891 [CBTSetCACLKResult] CA Dly = 33
3127 05:59:08.116973 CS Dly: 7 (0~40)
3128 05:59:08.117038
3129 05:59:08.120353 ----->DramcWriteLeveling(PI) begin...
3130 05:59:08.123607 ==
3131 05:59:08.123689 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 05:59:08.130074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 05:59:08.130190 ==
3134 05:59:08.133677 Write leveling (Byte 0): 26 => 26
3135 05:59:08.136569 Write leveling (Byte 1): 27 => 27
3136 05:59:08.140030 DramcWriteLeveling(PI) end<-----
3137 05:59:08.140112
3138 05:59:08.140176 ==
3139 05:59:08.143149 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 05:59:08.146807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 05:59:08.146889 ==
3142 05:59:08.149914 [Gating] SW mode calibration
3143 05:59:08.156624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3144 05:59:08.159702 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3145 05:59:08.166881 0 15 0 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
3146 05:59:08.169736 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 05:59:08.173352 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 05:59:08.179859 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 05:59:08.183296 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 05:59:08.186625 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 05:59:08.193408 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 05:59:08.196413 0 15 28 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 0)
3153 05:59:08.200079 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 05:59:08.206769 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 05:59:08.209749 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 05:59:08.213319 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 05:59:08.220184 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 05:59:08.223586 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 05:59:08.226585 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3160 05:59:08.233039 1 0 28 | B1->B0 | 4040 4040 | 1 0 | (0 0) (0 0)
3161 05:59:08.236642 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 05:59:08.240173 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 05:59:08.246258 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 05:59:08.249958 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 05:59:08.253200 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 05:59:08.259896 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 05:59:08.263185 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 05:59:08.266577 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3169 05:59:08.269780 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 05:59:08.276983 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 05:59:08.279912 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 05:59:08.283508 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 05:59:08.289925 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 05:59:08.293393 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 05:59:08.296707 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 05:59:08.303370 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 05:59:08.306272 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 05:59:08.309868 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 05:59:08.316509 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 05:59:08.319885 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 05:59:08.323327 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 05:59:08.329784 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 05:59:08.332716 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3184 05:59:08.336280 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3185 05:59:08.343370 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 05:59:08.343456 Total UI for P1: 0, mck2ui 16
3187 05:59:08.349850 best dqsien dly found for B0: ( 1, 3, 26)
3188 05:59:08.349951 Total UI for P1: 0, mck2ui 16
3189 05:59:08.356409 best dqsien dly found for B1: ( 1, 3, 26)
3190 05:59:08.359955 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3191 05:59:08.362947 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3192 05:59:08.363031
3193 05:59:08.366326 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3194 05:59:08.369816 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3195 05:59:08.373032 [Gating] SW calibration Done
3196 05:59:08.373113 ==
3197 05:59:08.376254 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 05:59:08.379549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 05:59:08.379634 ==
3200 05:59:08.383107 RX Vref Scan: 0
3201 05:59:08.383189
3202 05:59:08.383254 RX Vref 0 -> 0, step: 1
3203 05:59:08.383315
3204 05:59:08.386101 RX Delay -40 -> 252, step: 8
3205 05:59:08.389418 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3206 05:59:08.396341 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3207 05:59:08.399734 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3208 05:59:08.402722 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3209 05:59:08.405995 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3210 05:59:08.409773 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3211 05:59:08.412976 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3212 05:59:08.419701 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3213 05:59:08.423018 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3214 05:59:08.426035 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3215 05:59:08.429515 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3216 05:59:08.432515 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3217 05:59:08.439542 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3218 05:59:08.443099 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3219 05:59:08.446016 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3220 05:59:08.449613 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3221 05:59:08.449695 ==
3222 05:59:08.452554 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 05:59:08.459681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 05:59:08.459765 ==
3225 05:59:08.459831 DQS Delay:
3226 05:59:08.462632 DQS0 = 0, DQS1 = 0
3227 05:59:08.462714 DQM Delay:
3228 05:59:08.466239 DQM0 = 112, DQM1 = 105
3229 05:59:08.466336 DQ Delay:
3230 05:59:08.469215 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =107
3231 05:59:08.472656 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3232 05:59:08.475730 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3233 05:59:08.479321 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3234 05:59:08.479403
3235 05:59:08.479467
3236 05:59:08.479526 ==
3237 05:59:08.482994 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 05:59:08.485828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 05:59:08.489276 ==
3240 05:59:08.489357
3241 05:59:08.489421
3242 05:59:08.489504 TX Vref Scan disable
3243 05:59:08.492840 == TX Byte 0 ==
3244 05:59:08.496172 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3245 05:59:08.499201 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3246 05:59:08.502650 == TX Byte 1 ==
3247 05:59:08.505667 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3248 05:59:08.509307 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3249 05:59:08.509389 ==
3250 05:59:08.512669 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 05:59:08.519298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 05:59:08.519383 ==
3253 05:59:08.530240 TX Vref=22, minBit 10, minWin=24, winSum=405
3254 05:59:08.533145 TX Vref=24, minBit 10, minWin=24, winSum=409
3255 05:59:08.536723 TX Vref=26, minBit 9, minWin=25, winSum=419
3256 05:59:08.539791 TX Vref=28, minBit 9, minWin=25, winSum=418
3257 05:59:08.543475 TX Vref=30, minBit 9, minWin=25, winSum=421
3258 05:59:08.550005 TX Vref=32, minBit 9, minWin=24, winSum=419
3259 05:59:08.553458 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 30
3260 05:59:08.553562
3261 05:59:08.556465 Final TX Range 1 Vref 30
3262 05:59:08.556547
3263 05:59:08.556612 ==
3264 05:59:08.560062 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 05:59:08.563600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3266 05:59:08.563683 ==
3267 05:59:08.566528
3268 05:59:08.566609
3269 05:59:08.566674 TX Vref Scan disable
3270 05:59:08.570141 == TX Byte 0 ==
3271 05:59:08.573748 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3272 05:59:08.576636 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3273 05:59:08.579781 == TX Byte 1 ==
3274 05:59:08.583176 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3275 05:59:08.586758 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3276 05:59:08.590365
3277 05:59:08.590449 [DATLAT]
3278 05:59:08.590513 Freq=1200, CH1 RK0
3279 05:59:08.590574
3280 05:59:08.593202 DATLAT Default: 0xd
3281 05:59:08.593298 0, 0xFFFF, sum = 0
3282 05:59:08.596797 1, 0xFFFF, sum = 0
3283 05:59:08.596881 2, 0xFFFF, sum = 0
3284 05:59:08.599893 3, 0xFFFF, sum = 0
3285 05:59:08.599976 4, 0xFFFF, sum = 0
3286 05:59:08.603368 5, 0xFFFF, sum = 0
3287 05:59:08.606371 6, 0xFFFF, sum = 0
3288 05:59:08.606455 7, 0xFFFF, sum = 0
3289 05:59:08.609909 8, 0xFFFF, sum = 0
3290 05:59:08.609993 9, 0xFFFF, sum = 0
3291 05:59:08.613316 10, 0xFFFF, sum = 0
3292 05:59:08.613398 11, 0xFFFF, sum = 0
3293 05:59:08.616744 12, 0x0, sum = 1
3294 05:59:08.616827 13, 0x0, sum = 2
3295 05:59:08.619588 14, 0x0, sum = 3
3296 05:59:08.619671 15, 0x0, sum = 4
3297 05:59:08.619737 best_step = 13
3298 05:59:08.623121
3299 05:59:08.623201 ==
3300 05:59:08.626612 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 05:59:08.629691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3302 05:59:08.629811 ==
3303 05:59:08.629900 RX Vref Scan: 1
3304 05:59:08.629964
3305 05:59:08.632952 Set Vref Range= 32 -> 127
3306 05:59:08.633032
3307 05:59:08.636564 RX Vref 32 -> 127, step: 1
3308 05:59:08.636644
3309 05:59:08.639637 RX Delay -21 -> 252, step: 4
3310 05:59:08.639718
3311 05:59:08.643340 Set Vref, RX VrefLevel [Byte0]: 32
3312 05:59:08.646461 [Byte1]: 32
3313 05:59:08.646542
3314 05:59:08.649576 Set Vref, RX VrefLevel [Byte0]: 33
3315 05:59:08.653129 [Byte1]: 33
3316 05:59:08.656111
3317 05:59:08.656242 Set Vref, RX VrefLevel [Byte0]: 34
3318 05:59:08.659495 [Byte1]: 34
3319 05:59:08.664163
3320 05:59:08.664245 Set Vref, RX VrefLevel [Byte0]: 35
3321 05:59:08.667344 [Byte1]: 35
3322 05:59:08.672531
3323 05:59:08.672612 Set Vref, RX VrefLevel [Byte0]: 36
3324 05:59:08.675552 [Byte1]: 36
3325 05:59:08.680129
3326 05:59:08.680210 Set Vref, RX VrefLevel [Byte0]: 37
3327 05:59:08.683668 [Byte1]: 37
3328 05:59:08.687846
3329 05:59:08.687927 Set Vref, RX VrefLevel [Byte0]: 38
3330 05:59:08.691569 [Byte1]: 38
3331 05:59:08.696394
3332 05:59:08.696485 Set Vref, RX VrefLevel [Byte0]: 39
3333 05:59:08.699307 [Byte1]: 39
3334 05:59:08.703966
3335 05:59:08.704049 Set Vref, RX VrefLevel [Byte0]: 40
3336 05:59:08.707694 [Byte1]: 40
3337 05:59:08.711655
3338 05:59:08.711737 Set Vref, RX VrefLevel [Byte0]: 41
3339 05:59:08.715228 [Byte1]: 41
3340 05:59:08.719840
3341 05:59:08.719924 Set Vref, RX VrefLevel [Byte0]: 42
3342 05:59:08.722841 [Byte1]: 42
3343 05:59:08.727430
3344 05:59:08.727511 Set Vref, RX VrefLevel [Byte0]: 43
3345 05:59:08.731007 [Byte1]: 43
3346 05:59:08.735418
3347 05:59:08.735499 Set Vref, RX VrefLevel [Byte0]: 44
3348 05:59:08.742187 [Byte1]: 44
3349 05:59:08.742270
3350 05:59:08.745348 Set Vref, RX VrefLevel [Byte0]: 45
3351 05:59:08.748611 [Byte1]: 45
3352 05:59:08.748701
3353 05:59:08.752129 Set Vref, RX VrefLevel [Byte0]: 46
3354 05:59:08.755629 [Byte1]: 46
3355 05:59:08.759173
3356 05:59:08.759255 Set Vref, RX VrefLevel [Byte0]: 47
3357 05:59:08.762410 [Byte1]: 47
3358 05:59:08.767321
3359 05:59:08.767404 Set Vref, RX VrefLevel [Byte0]: 48
3360 05:59:08.770345 [Byte1]: 48
3361 05:59:08.774997
3362 05:59:08.775078 Set Vref, RX VrefLevel [Byte0]: 49
3363 05:59:08.778615 [Byte1]: 49
3364 05:59:08.782924
3365 05:59:08.783006 Set Vref, RX VrefLevel [Byte0]: 50
3366 05:59:08.786296 [Byte1]: 50
3367 05:59:08.791075
3368 05:59:08.791156 Set Vref, RX VrefLevel [Byte0]: 51
3369 05:59:08.794523 [Byte1]: 51
3370 05:59:08.798699
3371 05:59:08.798783 Set Vref, RX VrefLevel [Byte0]: 52
3372 05:59:08.802181 [Byte1]: 52
3373 05:59:08.807031
3374 05:59:08.807116 Set Vref, RX VrefLevel [Byte0]: 53
3375 05:59:08.809938 [Byte1]: 53
3376 05:59:08.814687
3377 05:59:08.814769 Set Vref, RX VrefLevel [Byte0]: 54
3378 05:59:08.818281 [Byte1]: 54
3379 05:59:08.822812
3380 05:59:08.822894 Set Vref, RX VrefLevel [Byte0]: 55
3381 05:59:08.825740 [Byte1]: 55
3382 05:59:08.830362
3383 05:59:08.830444 Set Vref, RX VrefLevel [Byte0]: 56
3384 05:59:08.833833 [Byte1]: 56
3385 05:59:08.838511
3386 05:59:08.838593 Set Vref, RX VrefLevel [Byte0]: 57
3387 05:59:08.841687 [Byte1]: 57
3388 05:59:08.846300
3389 05:59:08.846381 Set Vref, RX VrefLevel [Byte0]: 58
3390 05:59:08.849987 [Byte1]: 58
3391 05:59:08.854471
3392 05:59:08.854614 Set Vref, RX VrefLevel [Byte0]: 59
3393 05:59:08.857957 [Byte1]: 59
3394 05:59:08.862348
3395 05:59:08.862431 Set Vref, RX VrefLevel [Byte0]: 60
3396 05:59:08.865794 [Byte1]: 60
3397 05:59:08.870106
3398 05:59:08.870187 Set Vref, RX VrefLevel [Byte0]: 61
3399 05:59:08.873460 [Byte1]: 61
3400 05:59:08.877922
3401 05:59:08.878003 Set Vref, RX VrefLevel [Byte0]: 62
3402 05:59:08.881444 [Byte1]: 62
3403 05:59:08.885834
3404 05:59:08.885915 Set Vref, RX VrefLevel [Byte0]: 63
3405 05:59:08.889406 [Byte1]: 63
3406 05:59:08.893798
3407 05:59:08.893879 Set Vref, RX VrefLevel [Byte0]: 64
3408 05:59:08.897107 [Byte1]: 64
3409 05:59:08.901868
3410 05:59:08.901949 Set Vref, RX VrefLevel [Byte0]: 65
3411 05:59:08.905536 [Byte1]: 65
3412 05:59:08.910010
3413 05:59:08.910091 Set Vref, RX VrefLevel [Byte0]: 66
3414 05:59:08.912933 [Byte1]: 66
3415 05:59:08.917671
3416 05:59:08.917753 Set Vref, RX VrefLevel [Byte0]: 67
3417 05:59:08.921284 [Byte1]: 67
3418 05:59:08.925772
3419 05:59:08.925852 Set Vref, RX VrefLevel [Byte0]: 68
3420 05:59:08.929298 [Byte1]: 68
3421 05:59:08.933359
3422 05:59:08.933441 Set Vref, RX VrefLevel [Byte0]: 69
3423 05:59:08.936687 [Byte1]: 69
3424 05:59:08.941352
3425 05:59:08.941460 Set Vref, RX VrefLevel [Byte0]: 70
3426 05:59:08.944751 [Byte1]: 70
3427 05:59:08.949469
3428 05:59:08.949589 Final RX Vref Byte 0 = 59 to rank0
3429 05:59:08.953029 Final RX Vref Byte 1 = 48 to rank0
3430 05:59:08.956002 Final RX Vref Byte 0 = 59 to rank1
3431 05:59:08.959350 Final RX Vref Byte 1 = 48 to rank1==
3432 05:59:08.963049 Dram Type= 6, Freq= 0, CH_1, rank 0
3433 05:59:08.969166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 05:59:08.969252 ==
3435 05:59:08.969318 DQS Delay:
3436 05:59:08.972550 DQS0 = 0, DQS1 = 0
3437 05:59:08.972633 DQM Delay:
3438 05:59:08.972698 DQM0 = 114, DQM1 = 105
3439 05:59:08.976032 DQ Delay:
3440 05:59:08.979530 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3441 05:59:08.982461 DQ4 =112, DQ5 =122, DQ6 =124, DQ7 =112
3442 05:59:08.985922 DQ8 =92, DQ9 =98, DQ10 =104, DQ11 =100
3443 05:59:08.989291 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3444 05:59:08.989373
3445 05:59:08.989438
3446 05:59:08.998948 [DQSOSCAuto] RK0, (LSB)MR18= 0xeff6, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3447 05:59:08.999044 CH1 RK0: MR19=303, MR18=EFF6
3448 05:59:09.005831 CH1_RK0: MR19=0x303, MR18=0xEFF6, DQSOSC=414, MR23=63, INC=38, DEC=25
3449 05:59:09.005918
3450 05:59:09.009095 ----->DramcWriteLeveling(PI) begin...
3451 05:59:09.009207 ==
3452 05:59:09.012641 Dram Type= 6, Freq= 0, CH_1, rank 1
3453 05:59:09.019163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 05:59:09.019247 ==
3455 05:59:09.022780 Write leveling (Byte 0): 26 => 26
3456 05:59:09.022861 Write leveling (Byte 1): 28 => 28
3457 05:59:09.025765 DramcWriteLeveling(PI) end<-----
3458 05:59:09.025846
3459 05:59:09.025909 ==
3460 05:59:09.029076 Dram Type= 6, Freq= 0, CH_1, rank 1
3461 05:59:09.035445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 05:59:09.035529 ==
3463 05:59:09.039008 [Gating] SW mode calibration
3464 05:59:09.045939 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3465 05:59:09.048826 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3466 05:59:09.055319 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 05:59:09.058959 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 05:59:09.061990 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 05:59:09.068837 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 05:59:09.072326 0 15 16 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
3471 05:59:09.075524 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 05:59:09.082319 0 15 24 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 0)
3473 05:59:09.085590 0 15 28 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
3474 05:59:09.089019 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 05:59:09.092103 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 05:59:09.099074 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 05:59:09.102388 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 05:59:09.105900 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 05:59:09.112377 1 0 20 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
3480 05:59:09.115288 1 0 24 | B1->B0 | 2a2a 4646 | 0 0 | (1 1) (0 0)
3481 05:59:09.118694 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3482 05:59:09.125041 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 05:59:09.128781 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 05:59:09.131825 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 05:59:09.138750 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 05:59:09.141668 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 05:59:09.145088 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3488 05:59:09.151489 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3489 05:59:09.155064 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3490 05:59:09.158055 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 05:59:09.165268 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 05:59:09.168306 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 05:59:09.171871 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 05:59:09.178274 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 05:59:09.181177 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 05:59:09.184808 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 05:59:09.191702 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 05:59:09.194443 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 05:59:09.198142 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 05:59:09.204558 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 05:59:09.207821 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 05:59:09.211540 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 05:59:09.218105 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3504 05:59:09.221057 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3505 05:59:09.224373 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 05:59:09.227927 Total UI for P1: 0, mck2ui 16
3507 05:59:09.231283 best dqsien dly found for B0: ( 1, 3, 22)
3508 05:59:09.234175 Total UI for P1: 0, mck2ui 16
3509 05:59:09.237803 best dqsien dly found for B1: ( 1, 3, 24)
3510 05:59:09.241145 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3511 05:59:09.244722 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3512 05:59:09.244806
3513 05:59:09.250905 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3514 05:59:09.254562 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3515 05:59:09.257507 [Gating] SW calibration Done
3516 05:59:09.257604 ==
3517 05:59:09.261026 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 05:59:09.264657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 05:59:09.264741 ==
3520 05:59:09.264806 RX Vref Scan: 0
3521 05:59:09.264866
3522 05:59:09.267482 RX Vref 0 -> 0, step: 1
3523 05:59:09.267565
3524 05:59:09.270968 RX Delay -40 -> 252, step: 8
3525 05:59:09.273991 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
3526 05:59:09.277687 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3527 05:59:09.284100 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3528 05:59:09.287742 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3529 05:59:09.290664 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3530 05:59:09.293915 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3531 05:59:09.297088 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3532 05:59:09.303611 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3533 05:59:09.307330 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3534 05:59:09.310481 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3535 05:59:09.313627 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3536 05:59:09.317097 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3537 05:59:09.323962 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3538 05:59:09.326889 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3539 05:59:09.330268 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3540 05:59:09.333936 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3541 05:59:09.334018 ==
3542 05:59:09.336765 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 05:59:09.343268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 05:59:09.343353 ==
3545 05:59:09.343417 DQS Delay:
3546 05:59:09.343478 DQS0 = 0, DQS1 = 0
3547 05:59:09.346635 DQM Delay:
3548 05:59:09.346717 DQM0 = 109, DQM1 = 105
3549 05:59:09.350143 DQ Delay:
3550 05:59:09.353285 DQ0 =111, DQ1 =103, DQ2 =99, DQ3 =107
3551 05:59:09.356495 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3552 05:59:09.360076 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3553 05:59:09.363736 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3554 05:59:09.363845
3555 05:59:09.363912
3556 05:59:09.363975 ==
3557 05:59:09.366744 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 05:59:09.369838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 05:59:09.369956 ==
3560 05:59:09.370036
3561 05:59:09.373524
3562 05:59:09.373609 TX Vref Scan disable
3563 05:59:09.376875 == TX Byte 0 ==
3564 05:59:09.379733 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3565 05:59:09.383430 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3566 05:59:09.386252 == TX Byte 1 ==
3567 05:59:09.389787 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3568 05:59:09.393260 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3569 05:59:09.393358 ==
3570 05:59:09.396411 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 05:59:09.402964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 05:59:09.403072 ==
3573 05:59:09.413442 TX Vref=22, minBit 0, minWin=26, winSum=425
3574 05:59:09.416809 TX Vref=24, minBit 8, minWin=25, winSum=426
3575 05:59:09.420594 TX Vref=26, minBit 1, minWin=26, winSum=431
3576 05:59:09.423657 TX Vref=28, minBit 8, minWin=25, winSum=432
3577 05:59:09.427190 TX Vref=30, minBit 10, minWin=26, winSum=437
3578 05:59:09.433663 TX Vref=32, minBit 1, minWin=25, winSum=429
3579 05:59:09.437183 [TxChooseVref] Worse bit 10, Min win 26, Win sum 437, Final Vref 30
3580 05:59:09.437269
3581 05:59:09.440013 Final TX Range 1 Vref 30
3582 05:59:09.440096
3583 05:59:09.440195 ==
3584 05:59:09.443637 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 05:59:09.446530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 05:59:09.450135 ==
3587 05:59:09.450219
3588 05:59:09.450321
3589 05:59:09.450380 TX Vref Scan disable
3590 05:59:09.453900 == TX Byte 0 ==
3591 05:59:09.456694 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3592 05:59:09.463500 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3593 05:59:09.463602 == TX Byte 1 ==
3594 05:59:09.466653 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3595 05:59:09.473393 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3596 05:59:09.473499
3597 05:59:09.473581 [DATLAT]
3598 05:59:09.473641 Freq=1200, CH1 RK1
3599 05:59:09.473700
3600 05:59:09.476933 DATLAT Default: 0xd
3601 05:59:09.477013 0, 0xFFFF, sum = 0
3602 05:59:09.480317 1, 0xFFFF, sum = 0
3603 05:59:09.483772 2, 0xFFFF, sum = 0
3604 05:59:09.483872 3, 0xFFFF, sum = 0
3605 05:59:09.486573 4, 0xFFFF, sum = 0
3606 05:59:09.486656 5, 0xFFFF, sum = 0
3607 05:59:09.490214 6, 0xFFFF, sum = 0
3608 05:59:09.490296 7, 0xFFFF, sum = 0
3609 05:59:09.493722 8, 0xFFFF, sum = 0
3610 05:59:09.493823 9, 0xFFFF, sum = 0
3611 05:59:09.496738 10, 0xFFFF, sum = 0
3612 05:59:09.496837 11, 0xFFFF, sum = 0
3613 05:59:09.500387 12, 0x0, sum = 1
3614 05:59:09.500472 13, 0x0, sum = 2
3615 05:59:09.503756 14, 0x0, sum = 3
3616 05:59:09.503838 15, 0x0, sum = 4
3617 05:59:09.503903 best_step = 13
3618 05:59:09.506502
3619 05:59:09.506582 ==
3620 05:59:09.509913 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 05:59:09.513362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 05:59:09.513458 ==
3623 05:59:09.513549 RX Vref Scan: 0
3624 05:59:09.513646
3625 05:59:09.516980 RX Vref 0 -> 0, step: 1
3626 05:59:09.517059
3627 05:59:09.519814 RX Delay -21 -> 252, step: 4
3628 05:59:09.523373 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3629 05:59:09.529745 iDelay=195, Bit 1, Center 106 (39 ~ 174) 136
3630 05:59:09.533724 iDelay=195, Bit 2, Center 104 (35 ~ 174) 140
3631 05:59:09.536336 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3632 05:59:09.539837 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3633 05:59:09.542935 iDelay=195, Bit 5, Center 118 (43 ~ 194) 152
3634 05:59:09.549455 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3635 05:59:09.553000 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3636 05:59:09.556609 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3637 05:59:09.559583 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3638 05:59:09.563090 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3639 05:59:09.569794 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3640 05:59:09.572604 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3641 05:59:09.576041 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3642 05:59:09.579610 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3643 05:59:09.586254 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3644 05:59:09.586462 ==
3645 05:59:09.589776 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 05:59:09.592824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 05:59:09.592977 ==
3648 05:59:09.593055 DQS Delay:
3649 05:59:09.595905 DQS0 = 0, DQS1 = 0
3650 05:59:09.596059 DQM Delay:
3651 05:59:09.599532 DQM0 = 111, DQM1 = 108
3652 05:59:09.599717 DQ Delay:
3653 05:59:09.602574 DQ0 =114, DQ1 =106, DQ2 =104, DQ3 =108
3654 05:59:09.605948 DQ4 =108, DQ5 =118, DQ6 =122, DQ7 =110
3655 05:59:09.608973 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =102
3656 05:59:09.612732 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =116
3657 05:59:09.612961
3658 05:59:09.613082
3659 05:59:09.622323 [DQSOSCAuto] RK1, (LSB)MR18= 0xf707, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3660 05:59:09.625838 CH1 RK1: MR19=304, MR18=F707
3661 05:59:09.632098 CH1_RK1: MR19=0x304, MR18=0xF707, DQSOSC=407, MR23=63, INC=39, DEC=26
3662 05:59:09.635618 [RxdqsGatingPostProcess] freq 1200
3663 05:59:09.639166 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3664 05:59:09.642078 best DQS0 dly(2T, 0.5T) = (0, 11)
3665 05:59:09.645676 best DQS1 dly(2T, 0.5T) = (0, 11)
3666 05:59:09.648892 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3667 05:59:09.652052 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3668 05:59:09.655265 best DQS0 dly(2T, 0.5T) = (0, 11)
3669 05:59:09.658986 best DQS1 dly(2T, 0.5T) = (0, 11)
3670 05:59:09.661940 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3671 05:59:09.665499 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3672 05:59:09.668341 Pre-setting of DQS Precalculation
3673 05:59:09.671978 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3674 05:59:09.678330 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3675 05:59:09.688877 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3676 05:59:09.688986
3677 05:59:09.689053
3678 05:59:09.691591 [Calibration Summary] 2400 Mbps
3679 05:59:09.691676 CH 0, Rank 0
3680 05:59:09.695082 SW Impedance : PASS
3681 05:59:09.695196 DUTY Scan : NO K
3682 05:59:09.698591 ZQ Calibration : PASS
3683 05:59:09.701875 Jitter Meter : NO K
3684 05:59:09.701987 CBT Training : PASS
3685 05:59:09.705047 Write leveling : PASS
3686 05:59:09.708223 RX DQS gating : PASS
3687 05:59:09.708330 RX DQ/DQS(RDDQC) : PASS
3688 05:59:09.711818 TX DQ/DQS : PASS
3689 05:59:09.711931 RX DATLAT : PASS
3690 05:59:09.714691 RX DQ/DQS(Engine): PASS
3691 05:59:09.718229 TX OE : NO K
3692 05:59:09.718339 All Pass.
3693 05:59:09.718434
3694 05:59:09.718525 CH 0, Rank 1
3695 05:59:09.721454 SW Impedance : PASS
3696 05:59:09.724652 DUTY Scan : NO K
3697 05:59:09.724762 ZQ Calibration : PASS
3698 05:59:09.728104 Jitter Meter : NO K
3699 05:59:09.731526 CBT Training : PASS
3700 05:59:09.731636 Write leveling : PASS
3701 05:59:09.734523 RX DQS gating : PASS
3702 05:59:09.738061 RX DQ/DQS(RDDQC) : PASS
3703 05:59:09.738168 TX DQ/DQS : PASS
3704 05:59:09.741112 RX DATLAT : PASS
3705 05:59:09.744752 RX DQ/DQS(Engine): PASS
3706 05:59:09.744860 TX OE : NO K
3707 05:59:09.747717 All Pass.
3708 05:59:09.747822
3709 05:59:09.747915 CH 1, Rank 0
3710 05:59:09.751267 SW Impedance : PASS
3711 05:59:09.751373 DUTY Scan : NO K
3712 05:59:09.754707 ZQ Calibration : PASS
3713 05:59:09.758097 Jitter Meter : NO K
3714 05:59:09.758204 CBT Training : PASS
3715 05:59:09.761337 Write leveling : PASS
3716 05:59:09.764605 RX DQS gating : PASS
3717 05:59:09.764715 RX DQ/DQS(RDDQC) : PASS
3718 05:59:09.768038 TX DQ/DQS : PASS
3719 05:59:09.770938 RX DATLAT : PASS
3720 05:59:09.771055 RX DQ/DQS(Engine): PASS
3721 05:59:09.774436 TX OE : NO K
3722 05:59:09.774522 All Pass.
3723 05:59:09.774588
3724 05:59:09.777896 CH 1, Rank 1
3725 05:59:09.777966 SW Impedance : PASS
3726 05:59:09.781228 DUTY Scan : NO K
3727 05:59:09.781302 ZQ Calibration : PASS
3728 05:59:09.784245 Jitter Meter : NO K
3729 05:59:09.787903 CBT Training : PASS
3730 05:59:09.787974 Write leveling : PASS
3731 05:59:09.790869 RX DQS gating : PASS
3732 05:59:09.794333 RX DQ/DQS(RDDQC) : PASS
3733 05:59:09.794431 TX DQ/DQS : PASS
3734 05:59:09.797719 RX DATLAT : PASS
3735 05:59:09.800585 RX DQ/DQS(Engine): PASS
3736 05:59:09.800693 TX OE : NO K
3737 05:59:09.804123 All Pass.
3738 05:59:09.804228
3739 05:59:09.804321 DramC Write-DBI off
3740 05:59:09.807806 PER_BANK_REFRESH: Hybrid Mode
3741 05:59:09.810584 TX_TRACKING: ON
3742 05:59:09.817150 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3743 05:59:09.820645 [FAST_K] Save calibration result to emmc
3744 05:59:09.824238 dramc_set_vcore_voltage set vcore to 650000
3745 05:59:09.827331 Read voltage for 600, 5
3746 05:59:09.827439 Vio18 = 0
3747 05:59:09.830730 Vcore = 650000
3748 05:59:09.830837 Vdram = 0
3749 05:59:09.830930 Vddq = 0
3750 05:59:09.834115 Vmddr = 0
3751 05:59:09.837556 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3752 05:59:09.844229 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3753 05:59:09.844339 MEM_TYPE=3, freq_sel=19
3754 05:59:09.847027 sv_algorithm_assistance_LP4_1600
3755 05:59:09.853797 ============ PULL DRAM RESETB DOWN ============
3756 05:59:09.857223 ========== PULL DRAM RESETB DOWN end =========
3757 05:59:09.860647 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3758 05:59:09.864063 ===================================
3759 05:59:09.867301 LPDDR4 DRAM CONFIGURATION
3760 05:59:09.870669 ===================================
3761 05:59:09.870779 EX_ROW_EN[0] = 0x0
3762 05:59:09.873664 EX_ROW_EN[1] = 0x0
3763 05:59:09.876988 LP4Y_EN = 0x0
3764 05:59:09.877071 WORK_FSP = 0x0
3765 05:59:09.880478 WL = 0x2
3766 05:59:09.880550 RL = 0x2
3767 05:59:09.883946 BL = 0x2
3768 05:59:09.884018 RPST = 0x0
3769 05:59:09.887291 RD_PRE = 0x0
3770 05:59:09.887367 WR_PRE = 0x1
3771 05:59:09.890258 WR_PST = 0x0
3772 05:59:09.890333 DBI_WR = 0x0
3773 05:59:09.893756 DBI_RD = 0x0
3774 05:59:09.893826 OTF = 0x1
3775 05:59:09.897105 ===================================
3776 05:59:09.900175 ===================================
3777 05:59:09.903651 ANA top config
3778 05:59:09.907050 ===================================
3779 05:59:09.907154 DLL_ASYNC_EN = 0
3780 05:59:09.910058 ALL_SLAVE_EN = 1
3781 05:59:09.913663 NEW_RANK_MODE = 1
3782 05:59:09.917279 DLL_IDLE_MODE = 1
3783 05:59:09.920243 LP45_APHY_COMB_EN = 1
3784 05:59:09.920316 TX_ODT_DIS = 1
3785 05:59:09.923761 NEW_8X_MODE = 1
3786 05:59:09.927053 ===================================
3787 05:59:09.930116 ===================================
3788 05:59:09.933259 data_rate = 1200
3789 05:59:09.936722 CKR = 1
3790 05:59:09.940163 DQ_P2S_RATIO = 8
3791 05:59:09.943576 ===================================
3792 05:59:09.946609 CA_P2S_RATIO = 8
3793 05:59:09.946721 DQ_CA_OPEN = 0
3794 05:59:09.949883 DQ_SEMI_OPEN = 0
3795 05:59:09.953425 CA_SEMI_OPEN = 0
3796 05:59:09.956409 CA_FULL_RATE = 0
3797 05:59:09.959836 DQ_CKDIV4_EN = 1
3798 05:59:09.963335 CA_CKDIV4_EN = 1
3799 05:59:09.963453 CA_PREDIV_EN = 0
3800 05:59:09.966736 PH8_DLY = 0
3801 05:59:09.970117 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3802 05:59:09.972876 DQ_AAMCK_DIV = 4
3803 05:59:09.976517 CA_AAMCK_DIV = 4
3804 05:59:09.979980 CA_ADMCK_DIV = 4
3805 05:59:09.980086 DQ_TRACK_CA_EN = 0
3806 05:59:09.982739 CA_PICK = 600
3807 05:59:09.986306 CA_MCKIO = 600
3808 05:59:09.989835 MCKIO_SEMI = 0
3809 05:59:09.992678 PLL_FREQ = 2288
3810 05:59:09.996272 DQ_UI_PI_RATIO = 32
3811 05:59:09.999254 CA_UI_PI_RATIO = 0
3812 05:59:10.002779 ===================================
3813 05:59:10.006353 ===================================
3814 05:59:10.006430 memory_type:LPDDR4
3815 05:59:10.009093 GP_NUM : 10
3816 05:59:10.012700 SRAM_EN : 1
3817 05:59:10.012776 MD32_EN : 0
3818 05:59:10.016253 ===================================
3819 05:59:10.019050 [ANA_INIT] >>>>>>>>>>>>>>
3820 05:59:10.022615 <<<<<< [CONFIGURE PHASE]: ANA_TX
3821 05:59:10.026185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3822 05:59:10.029053 ===================================
3823 05:59:10.032812 data_rate = 1200,PCW = 0X5800
3824 05:59:10.035801 ===================================
3825 05:59:10.039207 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3826 05:59:10.042649 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3827 05:59:10.049016 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3828 05:59:10.052287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3829 05:59:10.055664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3830 05:59:10.058842 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3831 05:59:10.062659 [ANA_INIT] flow start
3832 05:59:10.065578 [ANA_INIT] PLL >>>>>>>>
3833 05:59:10.065681 [ANA_INIT] PLL <<<<<<<<
3834 05:59:10.069022 [ANA_INIT] MIDPI >>>>>>>>
3835 05:59:10.072551 [ANA_INIT] MIDPI <<<<<<<<
3836 05:59:10.075931 [ANA_INIT] DLL >>>>>>>>
3837 05:59:10.076031 [ANA_INIT] flow end
3838 05:59:10.078757 ============ LP4 DIFF to SE enter ============
3839 05:59:10.085717 ============ LP4 DIFF to SE exit ============
3840 05:59:10.085811 [ANA_INIT] <<<<<<<<<<<<<
3841 05:59:10.089188 [Flow] Enable top DCM control >>>>>
3842 05:59:10.091915 [Flow] Enable top DCM control <<<<<
3843 05:59:10.095438 Enable DLL master slave shuffle
3844 05:59:10.101945 ==============================================================
3845 05:59:10.102024 Gating Mode config
3846 05:59:10.108592 ==============================================================
3847 05:59:10.112038 Config description:
3848 05:59:10.121925 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3849 05:59:10.128558 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3850 05:59:10.131853 SELPH_MODE 0: By rank 1: By Phase
3851 05:59:10.138372 ==============================================================
3852 05:59:10.141850 GAT_TRACK_EN = 1
3853 05:59:10.144952 RX_GATING_MODE = 2
3854 05:59:10.145032 RX_GATING_TRACK_MODE = 2
3855 05:59:10.148330 SELPH_MODE = 1
3856 05:59:10.151923 PICG_EARLY_EN = 1
3857 05:59:10.154759 VALID_LAT_VALUE = 1
3858 05:59:10.161467 ==============================================================
3859 05:59:10.165286 Enter into Gating configuration >>>>
3860 05:59:10.168142 Exit from Gating configuration <<<<
3861 05:59:10.171757 Enter into DVFS_PRE_config >>>>>
3862 05:59:10.181665 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3863 05:59:10.185025 Exit from DVFS_PRE_config <<<<<
3864 05:59:10.187954 Enter into PICG configuration >>>>
3865 05:59:10.191521 Exit from PICG configuration <<<<
3866 05:59:10.194872 [RX_INPUT] configuration >>>>>
3867 05:59:10.198046 [RX_INPUT] configuration <<<<<
3868 05:59:10.201245 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3869 05:59:10.207884 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3870 05:59:10.214878 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3871 05:59:10.221207 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3872 05:59:10.224600 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3873 05:59:10.231171 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3874 05:59:10.234785 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3875 05:59:10.241372 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3876 05:59:10.244284 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3877 05:59:10.248024 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3878 05:59:10.251388 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3879 05:59:10.257865 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3880 05:59:10.261276 ===================================
3881 05:59:10.264702 LPDDR4 DRAM CONFIGURATION
3882 05:59:10.264801 ===================================
3883 05:59:10.267667 EX_ROW_EN[0] = 0x0
3884 05:59:10.271291 EX_ROW_EN[1] = 0x0
3885 05:59:10.271388 LP4Y_EN = 0x0
3886 05:59:10.274198 WORK_FSP = 0x0
3887 05:59:10.274298 WL = 0x2
3888 05:59:10.277428 RL = 0x2
3889 05:59:10.277560 BL = 0x2
3890 05:59:10.280820 RPST = 0x0
3891 05:59:10.280908 RD_PRE = 0x0
3892 05:59:10.284416 WR_PRE = 0x1
3893 05:59:10.284491 WR_PST = 0x0
3894 05:59:10.287425 DBI_WR = 0x0
3895 05:59:10.287501 DBI_RD = 0x0
3896 05:59:10.290744 OTF = 0x1
3897 05:59:10.294394 ===================================
3898 05:59:10.297282 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3899 05:59:10.300684 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3900 05:59:10.307404 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3901 05:59:10.310747 ===================================
3902 05:59:10.310848 LPDDR4 DRAM CONFIGURATION
3903 05:59:10.314245 ===================================
3904 05:59:10.317072 EX_ROW_EN[0] = 0x10
3905 05:59:10.320564 EX_ROW_EN[1] = 0x0
3906 05:59:10.320660 LP4Y_EN = 0x0
3907 05:59:10.324044 WORK_FSP = 0x0
3908 05:59:10.324169 WL = 0x2
3909 05:59:10.327066 RL = 0x2
3910 05:59:10.327140 BL = 0x2
3911 05:59:10.330395 RPST = 0x0
3912 05:59:10.330473 RD_PRE = 0x0
3913 05:59:10.333996 WR_PRE = 0x1
3914 05:59:10.334069 WR_PST = 0x0
3915 05:59:10.337309 DBI_WR = 0x0
3916 05:59:10.337405 DBI_RD = 0x0
3917 05:59:10.340231 OTF = 0x1
3918 05:59:10.343869 ===================================
3919 05:59:10.350406 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3920 05:59:10.353921 nWR fixed to 30
3921 05:59:10.356800 [ModeRegInit_LP4] CH0 RK0
3922 05:59:10.356898 [ModeRegInit_LP4] CH0 RK1
3923 05:59:10.360424 [ModeRegInit_LP4] CH1 RK0
3924 05:59:10.363393 [ModeRegInit_LP4] CH1 RK1
3925 05:59:10.363490 match AC timing 17
3926 05:59:10.370244 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3927 05:59:10.373758 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3928 05:59:10.376871 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3929 05:59:10.383680 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3930 05:59:10.386952 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3931 05:59:10.387030 ==
3932 05:59:10.389812 Dram Type= 6, Freq= 0, CH_0, rank 0
3933 05:59:10.393521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 05:59:10.393596 ==
3935 05:59:10.399860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 05:59:10.406660 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3937 05:59:10.409912 [CA 0] Center 37 (7~67) winsize 61
3938 05:59:10.413138 [CA 1] Center 37 (7~67) winsize 61
3939 05:59:10.416682 [CA 2] Center 35 (5~65) winsize 61
3940 05:59:10.419455 [CA 3] Center 35 (5~65) winsize 61
3941 05:59:10.423226 [CA 4] Center 34 (4~65) winsize 62
3942 05:59:10.426512 [CA 5] Center 34 (4~65) winsize 62
3943 05:59:10.426605
3944 05:59:10.429885 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3945 05:59:10.429959
3946 05:59:10.433010 [CATrainingPosCal] consider 1 rank data
3947 05:59:10.436106 u2DelayCellTimex100 = 270/100 ps
3948 05:59:10.439601 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3949 05:59:10.443319 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3950 05:59:10.446348 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3951 05:59:10.449730 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3952 05:59:10.452645 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3953 05:59:10.459670 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
3954 05:59:10.459754
3955 05:59:10.462643 CA PerBit enable=1, Macro0, CA PI delay=34
3956 05:59:10.462731
3957 05:59:10.466121 [CBTSetCACLKResult] CA Dly = 34
3958 05:59:10.466196 CS Dly: 6 (0~37)
3959 05:59:10.466273 ==
3960 05:59:10.469841 Dram Type= 6, Freq= 0, CH_0, rank 1
3961 05:59:10.472626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3962 05:59:10.475852 ==
3963 05:59:10.479569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3964 05:59:10.485999 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3965 05:59:10.489419 [CA 0] Center 37 (7~67) winsize 61
3966 05:59:10.492774 [CA 1] Center 37 (7~67) winsize 61
3967 05:59:10.496077 [CA 2] Center 35 (5~65) winsize 61
3968 05:59:10.499056 [CA 3] Center 35 (5~65) winsize 61
3969 05:59:10.502519 [CA 4] Center 34 (4~65) winsize 62
3970 05:59:10.505867 [CA 5] Center 34 (3~65) winsize 63
3971 05:59:10.505966
3972 05:59:10.508909 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3973 05:59:10.509007
3974 05:59:10.512501 [CATrainingPosCal] consider 2 rank data
3975 05:59:10.515741 u2DelayCellTimex100 = 270/100 ps
3976 05:59:10.518905 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3977 05:59:10.522457 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3978 05:59:10.525943 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3979 05:59:10.532532 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3980 05:59:10.535619 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3981 05:59:10.538886 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
3982 05:59:10.538958
3983 05:59:10.542308 CA PerBit enable=1, Macro0, CA PI delay=34
3984 05:59:10.542380
3985 05:59:10.545848 [CBTSetCACLKResult] CA Dly = 34
3986 05:59:10.545946 CS Dly: 6 (0~37)
3987 05:59:10.546034
3988 05:59:10.549221 ----->DramcWriteLeveling(PI) begin...
3989 05:59:10.549293 ==
3990 05:59:10.555609 Dram Type= 6, Freq= 0, CH_0, rank 0
3991 05:59:10.558766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3992 05:59:10.558839 ==
3993 05:59:10.561924 Write leveling (Byte 0): 33 => 33
3994 05:59:10.565453 Write leveling (Byte 1): 30 => 30
3995 05:59:10.569095 DramcWriteLeveling(PI) end<-----
3996 05:59:10.569167
3997 05:59:10.569229 ==
3998 05:59:10.571955 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 05:59:10.575554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 05:59:10.575650 ==
4001 05:59:10.578605 [Gating] SW mode calibration
4002 05:59:10.585611 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4003 05:59:10.591830 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4004 05:59:10.594807 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 05:59:10.598245 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 05:59:10.605448 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 05:59:10.608218 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4008 05:59:10.611548 0 9 16 | B1->B0 | 3131 2525 | 0 0 | (0 0) (0 0)
4009 05:59:10.618484 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 05:59:10.621248 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 05:59:10.624477 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 05:59:10.631308 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 05:59:10.634744 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 05:59:10.638130 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 05:59:10.644860 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4016 05:59:10.647721 0 10 16 | B1->B0 | 2e2e 4040 | 1 1 | (0 0) (0 0)
4017 05:59:10.651395 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 05:59:10.654426 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 05:59:10.661356 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 05:59:10.664292 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 05:59:10.668086 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 05:59:10.674647 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 05:59:10.678205 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 05:59:10.681059 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4025 05:59:10.687859 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 05:59:10.690672 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 05:59:10.694240 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 05:59:10.700641 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 05:59:10.704158 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 05:59:10.707695 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 05:59:10.714570 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 05:59:10.717363 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 05:59:10.720907 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 05:59:10.727261 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 05:59:10.730994 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 05:59:10.733977 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 05:59:10.740939 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 05:59:10.744076 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 05:59:10.747472 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4040 05:59:10.753800 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4041 05:59:10.753882 Total UI for P1: 0, mck2ui 16
4042 05:59:10.760825 best dqsien dly found for B0: ( 0, 13, 12)
4043 05:59:10.764118 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 05:59:10.767092 Total UI for P1: 0, mck2ui 16
4045 05:59:10.770584 best dqsien dly found for B1: ( 0, 13, 16)
4046 05:59:10.773735 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4047 05:59:10.777108 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4048 05:59:10.777180
4049 05:59:10.780410 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4050 05:59:10.783549 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4051 05:59:10.787282 [Gating] SW calibration Done
4052 05:59:10.787363 ==
4053 05:59:10.790089 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 05:59:10.796862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 05:59:10.796948 ==
4056 05:59:10.797066 RX Vref Scan: 0
4057 05:59:10.797177
4058 05:59:10.800256 RX Vref 0 -> 0, step: 1
4059 05:59:10.800379
4060 05:59:10.803885 RX Delay -230 -> 252, step: 16
4061 05:59:10.806800 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4062 05:59:10.810607 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4063 05:59:10.813774 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4064 05:59:10.820236 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4065 05:59:10.823625 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4066 05:59:10.826553 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4067 05:59:10.829982 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4068 05:59:10.833398 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4069 05:59:10.840052 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4070 05:59:10.843125 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4071 05:59:10.846546 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4072 05:59:10.849898 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4073 05:59:10.856491 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4074 05:59:10.860022 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4075 05:59:10.862984 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4076 05:59:10.866514 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4077 05:59:10.869486 ==
4078 05:59:10.872875 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 05:59:10.876539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 05:59:10.876610 ==
4081 05:59:10.876673 DQS Delay:
4082 05:59:10.879413 DQS0 = 0, DQS1 = 0
4083 05:59:10.879509 DQM Delay:
4084 05:59:10.883037 DQM0 = 38, DQM1 = 30
4085 05:59:10.883137 DQ Delay:
4086 05:59:10.886070 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4087 05:59:10.889525 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4088 05:59:10.892868 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4089 05:59:10.896215 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4090 05:59:10.896317
4091 05:59:10.896410
4092 05:59:10.896499 ==
4093 05:59:10.899337 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 05:59:10.902825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 05:59:10.902910 ==
4096 05:59:10.902976
4097 05:59:10.903037
4098 05:59:10.905771 TX Vref Scan disable
4099 05:59:10.909334 == TX Byte 0 ==
4100 05:59:10.912798 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4101 05:59:10.915688 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4102 05:59:10.919339 == TX Byte 1 ==
4103 05:59:10.922307 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4104 05:59:10.925615 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4105 05:59:10.925698 ==
4106 05:59:10.929351 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 05:59:10.935874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 05:59:10.935956 ==
4109 05:59:10.936020
4110 05:59:10.936081
4111 05:59:10.936137 TX Vref Scan disable
4112 05:59:10.940352 == TX Byte 0 ==
4113 05:59:10.943403 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4114 05:59:10.950256 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4115 05:59:10.950380 == TX Byte 1 ==
4116 05:59:10.953732 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4117 05:59:10.959981 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4118 05:59:10.960102
4119 05:59:10.960197 [DATLAT]
4120 05:59:10.960286 Freq=600, CH0 RK0
4121 05:59:10.960373
4122 05:59:10.963362 DATLAT Default: 0x9
4123 05:59:10.963437 0, 0xFFFF, sum = 0
4124 05:59:10.967040 1, 0xFFFF, sum = 0
4125 05:59:10.967155 2, 0xFFFF, sum = 0
4126 05:59:10.969893 3, 0xFFFF, sum = 0
4127 05:59:10.973419 4, 0xFFFF, sum = 0
4128 05:59:10.973546 5, 0xFFFF, sum = 0
4129 05:59:10.977029 6, 0xFFFF, sum = 0
4130 05:59:10.977128 7, 0xFFFF, sum = 0
4131 05:59:10.980136 8, 0x0, sum = 1
4132 05:59:10.980235 9, 0x0, sum = 2
4133 05:59:10.980326 10, 0x0, sum = 3
4134 05:59:10.983146 11, 0x0, sum = 4
4135 05:59:10.983244 best_step = 9
4136 05:59:10.983330
4137 05:59:10.983415 ==
4138 05:59:10.986760 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 05:59:10.993303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 05:59:10.993401 ==
4141 05:59:10.993514 RX Vref Scan: 1
4142 05:59:10.993590
4143 05:59:10.996165 RX Vref 0 -> 0, step: 1
4144 05:59:10.996260
4145 05:59:10.999628 RX Delay -195 -> 252, step: 8
4146 05:59:10.999727
4147 05:59:11.003074 Set Vref, RX VrefLevel [Byte0]: 61
4148 05:59:11.006540 [Byte1]: 47
4149 05:59:11.006637
4150 05:59:11.009686 Final RX Vref Byte 0 = 61 to rank0
4151 05:59:11.013147 Final RX Vref Byte 1 = 47 to rank0
4152 05:59:11.016211 Final RX Vref Byte 0 = 61 to rank1
4153 05:59:11.019646 Final RX Vref Byte 1 = 47 to rank1==
4154 05:59:11.022619 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 05:59:11.026246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 05:59:11.029257 ==
4157 05:59:11.029352 DQS Delay:
4158 05:59:11.029440 DQS0 = 0, DQS1 = 0
4159 05:59:11.032782 DQM Delay:
4160 05:59:11.032877 DQM0 = 33, DQM1 = 28
4161 05:59:11.036013 DQ Delay:
4162 05:59:11.036110 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =32
4163 05:59:11.039266 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4164 05:59:11.042562 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4165 05:59:11.046245 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4166 05:59:11.046341
4167 05:59:11.049655
4168 05:59:11.056181 [DQSOSCAuto] RK0, (LSB)MR18= 0x3837, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
4169 05:59:11.059153 CH0 RK0: MR19=808, MR18=3837
4170 05:59:11.065934 CH0_RK0: MR19=0x808, MR18=0x3837, DQSOSC=399, MR23=63, INC=164, DEC=109
4171 05:59:11.066031
4172 05:59:11.069103 ----->DramcWriteLeveling(PI) begin...
4173 05:59:11.069199 ==
4174 05:59:11.072467 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 05:59:11.075828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 05:59:11.075898 ==
4177 05:59:11.079496 Write leveling (Byte 0): 33 => 33
4178 05:59:11.082451 Write leveling (Byte 1): 30 => 30
4179 05:59:11.085666 DramcWriteLeveling(PI) end<-----
4180 05:59:11.085732
4181 05:59:11.085794 ==
4182 05:59:11.089205 Dram Type= 6, Freq= 0, CH_0, rank 1
4183 05:59:11.092276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 05:59:11.092345 ==
4185 05:59:11.095701 [Gating] SW mode calibration
4186 05:59:11.102279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4187 05:59:11.108808 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4188 05:59:11.112332 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 05:59:11.116477 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4190 05:59:11.122505 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 05:59:11.125578 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4192 05:59:11.129134 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
4193 05:59:11.135205 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 05:59:11.138687 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 05:59:11.141818 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 05:59:11.148410 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 05:59:11.151667 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 05:59:11.154984 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 05:59:11.161974 0 10 12 | B1->B0 | 2929 2c2c | 0 0 | (0 0) (0 0)
4200 05:59:11.165144 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4201 05:59:11.168731 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 05:59:11.175011 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 05:59:11.178287 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 05:59:11.181612 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 05:59:11.188267 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 05:59:11.191901 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 05:59:11.194822 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4208 05:59:11.201553 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4209 05:59:11.205066 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 05:59:11.208010 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 05:59:11.214661 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 05:59:11.217671 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 05:59:11.221412 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 05:59:11.227737 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 05:59:11.231057 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 05:59:11.234027 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 05:59:11.241354 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 05:59:11.244402 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 05:59:11.247355 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 05:59:11.253900 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 05:59:11.257343 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 05:59:11.260725 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 05:59:11.267622 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 05:59:11.270426 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 05:59:11.273591 Total UI for P1: 0, mck2ui 16
4226 05:59:11.277427 best dqsien dly found for B0: ( 0, 13, 14)
4227 05:59:11.280262 Total UI for P1: 0, mck2ui 16
4228 05:59:11.283735 best dqsien dly found for B1: ( 0, 13, 14)
4229 05:59:11.286889 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4230 05:59:11.290197 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4231 05:59:11.290294
4232 05:59:11.293577 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4233 05:59:11.300475 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4234 05:59:11.300602 [Gating] SW calibration Done
4235 05:59:11.300699 ==
4236 05:59:11.303448 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 05:59:11.310079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 05:59:11.310187 ==
4239 05:59:11.310268 RX Vref Scan: 0
4240 05:59:11.310331
4241 05:59:11.313644 RX Vref 0 -> 0, step: 1
4242 05:59:11.313727
4243 05:59:11.317136 RX Delay -230 -> 252, step: 16
4244 05:59:11.319995 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4245 05:59:11.323597 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4246 05:59:11.326663 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4247 05:59:11.333277 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4248 05:59:11.336758 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4249 05:59:11.340156 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4250 05:59:11.343394 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4251 05:59:11.349886 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4252 05:59:11.353190 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4253 05:59:11.356286 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4254 05:59:11.359921 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4255 05:59:11.366547 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4256 05:59:11.369694 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4257 05:59:11.373320 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4258 05:59:11.376282 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4259 05:59:11.382949 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4260 05:59:11.383030 ==
4261 05:59:11.386402 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 05:59:11.389727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 05:59:11.389825 ==
4264 05:59:11.389891 DQS Delay:
4265 05:59:11.392975 DQS0 = 0, DQS1 = 0
4266 05:59:11.393056 DQM Delay:
4267 05:59:11.396580 DQM0 = 36, DQM1 = 30
4268 05:59:11.396661 DQ Delay:
4269 05:59:11.399725 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4270 05:59:11.403031 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4271 05:59:11.405871 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4272 05:59:11.409360 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =33
4273 05:59:11.409442
4274 05:59:11.409531
4275 05:59:11.409594 ==
4276 05:59:11.413074 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 05:59:11.415859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 05:59:11.415952 ==
4279 05:59:11.416055
4280 05:59:11.419428
4281 05:59:11.419509 TX Vref Scan disable
4282 05:59:11.422412 == TX Byte 0 ==
4283 05:59:11.426032 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4284 05:59:11.429018 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4285 05:59:11.432559 == TX Byte 1 ==
4286 05:59:11.435552 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4287 05:59:11.439196 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4288 05:59:11.439277 ==
4289 05:59:11.442107 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 05:59:11.449250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 05:59:11.449331 ==
4292 05:59:11.449395
4293 05:59:11.449454
4294 05:59:11.451982 TX Vref Scan disable
4295 05:59:11.452138 == TX Byte 0 ==
4296 05:59:11.458528 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4297 05:59:11.461995 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4298 05:59:11.462126 == TX Byte 1 ==
4299 05:59:11.468566 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4300 05:59:11.472135 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4301 05:59:11.472275
4302 05:59:11.472367 [DATLAT]
4303 05:59:11.475454 Freq=600, CH0 RK1
4304 05:59:11.475534
4305 05:59:11.475597 DATLAT Default: 0x9
4306 05:59:11.478633 0, 0xFFFF, sum = 0
4307 05:59:11.478714 1, 0xFFFF, sum = 0
4308 05:59:11.481970 2, 0xFFFF, sum = 0
4309 05:59:11.485146 3, 0xFFFF, sum = 0
4310 05:59:11.485226 4, 0xFFFF, sum = 0
4311 05:59:11.488794 5, 0xFFFF, sum = 0
4312 05:59:11.488878 6, 0xFFFF, sum = 0
4313 05:59:11.491679 7, 0xFFFF, sum = 0
4314 05:59:11.491759 8, 0x0, sum = 1
4315 05:59:11.491824 9, 0x0, sum = 2
4316 05:59:11.494921 10, 0x0, sum = 3
4317 05:59:11.495006 11, 0x0, sum = 4
4318 05:59:11.498333 best_step = 9
4319 05:59:11.498412
4320 05:59:11.498475 ==
4321 05:59:11.501440 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 05:59:11.504865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 05:59:11.504945 ==
4324 05:59:11.508361 RX Vref Scan: 0
4325 05:59:11.508490
4326 05:59:11.508575 RX Vref 0 -> 0, step: 1
4327 05:59:11.508645
4328 05:59:11.511481 RX Delay -195 -> 252, step: 8
4329 05:59:11.518973 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4330 05:59:11.522619 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4331 05:59:11.525777 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4332 05:59:11.529388 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4333 05:59:11.535993 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4334 05:59:11.538953 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4335 05:59:11.542603 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4336 05:59:11.545765 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4337 05:59:11.548825 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4338 05:59:11.555366 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4339 05:59:11.559101 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4340 05:59:11.562070 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4341 05:59:11.565379 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4342 05:59:11.571977 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4343 05:59:11.575255 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4344 05:59:11.578548 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4345 05:59:11.578680 ==
4346 05:59:11.582314 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 05:59:11.589024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 05:59:11.589105 ==
4349 05:59:11.589170 DQS Delay:
4350 05:59:11.589231 DQS0 = 0, DQS1 = 0
4351 05:59:11.591771 DQM Delay:
4352 05:59:11.591859 DQM0 = 34, DQM1 = 28
4353 05:59:11.595561 DQ Delay:
4354 05:59:11.598442 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4355 05:59:11.601929 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4356 05:59:11.605379 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4357 05:59:11.608560 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4358 05:59:11.608641
4359 05:59:11.608720
4360 05:59:11.615288 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4361 05:59:11.618723 CH0 RK1: MR19=808, MR18=6D3B
4362 05:59:11.625276 CH0_RK1: MR19=0x808, MR18=0x6D3B, DQSOSC=389, MR23=63, INC=173, DEC=115
4363 05:59:11.628702 [RxdqsGatingPostProcess] freq 600
4364 05:59:11.631751 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4365 05:59:11.635329 Pre-setting of DQS Precalculation
4366 05:59:11.641878 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4367 05:59:11.641979 ==
4368 05:59:11.644909 Dram Type= 6, Freq= 0, CH_1, rank 0
4369 05:59:11.648401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 05:59:11.648473 ==
4371 05:59:11.655034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 05:59:11.661162 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4373 05:59:11.664681 [CA 0] Center 36 (6~66) winsize 61
4374 05:59:11.667860 [CA 1] Center 35 (5~66) winsize 62
4375 05:59:11.671516 [CA 2] Center 34 (4~65) winsize 62
4376 05:59:11.674474 [CA 3] Center 34 (4~65) winsize 62
4377 05:59:11.677890 [CA 4] Center 34 (4~65) winsize 62
4378 05:59:11.681304 [CA 5] Center 33 (3~64) winsize 62
4379 05:59:11.681401
4380 05:59:11.684477 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4381 05:59:11.684572
4382 05:59:11.687762 [CATrainingPosCal] consider 1 rank data
4383 05:59:11.691576 u2DelayCellTimex100 = 270/100 ps
4384 05:59:11.694257 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4385 05:59:11.697597 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4386 05:59:11.701045 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4387 05:59:11.704591 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4388 05:59:11.707510 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4389 05:59:11.711094 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4390 05:59:11.711193
4391 05:59:11.717940 CA PerBit enable=1, Macro0, CA PI delay=33
4392 05:59:11.718023
4393 05:59:11.718106 [CBTSetCACLKResult] CA Dly = 33
4394 05:59:11.720585 CS Dly: 4 (0~35)
4395 05:59:11.720674 ==
4396 05:59:11.724379 Dram Type= 6, Freq= 0, CH_1, rank 1
4397 05:59:11.727947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 05:59:11.728028 ==
4399 05:59:11.734474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4400 05:59:11.741080 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4401 05:59:11.744014 [CA 0] Center 36 (6~66) winsize 61
4402 05:59:11.747523 [CA 1] Center 35 (5~66) winsize 62
4403 05:59:11.750642 [CA 2] Center 34 (4~65) winsize 62
4404 05:59:11.754333 [CA 3] Center 34 (3~65) winsize 63
4405 05:59:11.757805 [CA 4] Center 34 (4~65) winsize 62
4406 05:59:11.760723 [CA 5] Center 33 (3~64) winsize 62
4407 05:59:11.760803
4408 05:59:11.764484 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4409 05:59:11.764562
4410 05:59:11.767449 [CATrainingPosCal] consider 2 rank data
4411 05:59:11.770880 u2DelayCellTimex100 = 270/100 ps
4412 05:59:11.773967 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4413 05:59:11.777661 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4414 05:59:11.780772 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4415 05:59:11.784350 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4416 05:59:11.787366 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4417 05:59:11.790785 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 05:59:11.790882
4419 05:59:11.797114 CA PerBit enable=1, Macro0, CA PI delay=33
4420 05:59:11.797201
4421 05:59:11.800306 [CBTSetCACLKResult] CA Dly = 33
4422 05:59:11.800408 CS Dly: 4 (0~36)
4423 05:59:11.800510
4424 05:59:11.804031 ----->DramcWriteLeveling(PI) begin...
4425 05:59:11.804148 ==
4426 05:59:11.806802 Dram Type= 6, Freq= 0, CH_1, rank 0
4427 05:59:11.810723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 05:59:11.813659 ==
4429 05:59:11.813735 Write leveling (Byte 0): 28 => 28
4430 05:59:11.817155 Write leveling (Byte 1): 29 => 29
4431 05:59:11.820646 DramcWriteLeveling(PI) end<-----
4432 05:59:11.820720
4433 05:59:11.820790 ==
4434 05:59:11.823499 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 05:59:11.830271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 05:59:11.830372 ==
4437 05:59:11.830476 [Gating] SW mode calibration
4438 05:59:11.840215 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4439 05:59:11.843503 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4440 05:59:11.847209 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4441 05:59:11.853434 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 05:59:11.857111 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4443 05:59:11.860206 0 9 12 | B1->B0 | 3333 3131 | 1 1 | (1 0) (1 1)
4444 05:59:11.866758 0 9 16 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
4445 05:59:11.869788 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 05:59:11.873411 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 05:59:11.880226 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 05:59:11.883087 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 05:59:11.886990 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 05:59:11.893316 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 05:59:11.896379 0 10 12 | B1->B0 | 3030 2a2a | 0 0 | (0 0) (0 0)
4452 05:59:11.900061 0 10 16 | B1->B0 | 4545 3f3f | 0 0 | (0 0) (0 0)
4453 05:59:11.906375 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 05:59:11.909823 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 05:59:11.913012 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 05:59:11.920133 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 05:59:11.923434 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 05:59:11.926676 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 05:59:11.932988 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4460 05:59:11.936421 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4461 05:59:11.939716 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 05:59:11.946438 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 05:59:11.949932 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 05:59:11.953442 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 05:59:11.959645 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 05:59:11.963082 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 05:59:11.966697 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 05:59:11.973291 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 05:59:11.976377 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 05:59:11.979839 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 05:59:11.986514 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 05:59:11.989625 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 05:59:11.993216 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 05:59:11.996111 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 05:59:12.002793 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4476 05:59:12.006523 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4477 05:59:12.009344 Total UI for P1: 0, mck2ui 16
4478 05:59:12.012935 best dqsien dly found for B0: ( 0, 13, 12)
4479 05:59:12.016016 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 05:59:12.019523 Total UI for P1: 0, mck2ui 16
4481 05:59:12.022779 best dqsien dly found for B1: ( 0, 13, 18)
4482 05:59:12.026217 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4483 05:59:12.032846 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4484 05:59:12.032926
4485 05:59:12.035666 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4486 05:59:12.039334 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4487 05:59:12.042718 [Gating] SW calibration Done
4488 05:59:12.042797 ==
4489 05:59:12.045559 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 05:59:12.049334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 05:59:12.049442 ==
4492 05:59:12.052624 RX Vref Scan: 0
4493 05:59:12.052703
4494 05:59:12.052777 RX Vref 0 -> 0, step: 1
4495 05:59:12.052843
4496 05:59:12.055603 RX Delay -230 -> 252, step: 16
4497 05:59:12.059259 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4498 05:59:12.065811 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4499 05:59:12.068970 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4500 05:59:12.072099 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4501 05:59:12.075592 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4502 05:59:12.082251 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4503 05:59:12.085879 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4504 05:59:12.089045 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4505 05:59:12.092018 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4506 05:59:12.095730 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4507 05:59:12.101853 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4508 05:59:12.105365 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4509 05:59:12.108927 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4510 05:59:12.111943 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4511 05:59:12.118664 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4512 05:59:12.121820 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4513 05:59:12.121906 ==
4514 05:59:12.125386 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 05:59:12.128270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 05:59:12.128358 ==
4517 05:59:12.131688 DQS Delay:
4518 05:59:12.131775 DQS0 = 0, DQS1 = 0
4519 05:59:12.134996 DQM Delay:
4520 05:59:12.135087 DQM0 = 38, DQM1 = 28
4521 05:59:12.135158 DQ Delay:
4522 05:59:12.138388 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4523 05:59:12.141507 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4524 05:59:12.144691 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4525 05:59:12.148136 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4526 05:59:12.148227
4527 05:59:12.148298
4528 05:59:12.151887 ==
4529 05:59:12.154735 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 05:59:12.158075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 05:59:12.158204 ==
4532 05:59:12.158310
4533 05:59:12.158403
4534 05:59:12.161498 TX Vref Scan disable
4535 05:59:12.161601 == TX Byte 0 ==
4536 05:59:12.168164 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4537 05:59:12.171124 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4538 05:59:12.171207 == TX Byte 1 ==
4539 05:59:12.177875 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4540 05:59:12.181300 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4541 05:59:12.181376 ==
4542 05:59:12.184571 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 05:59:12.187729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 05:59:12.187807 ==
4545 05:59:12.187871
4546 05:59:12.187930
4547 05:59:12.191199 TX Vref Scan disable
4548 05:59:12.194238 == TX Byte 0 ==
4549 05:59:12.197882 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4550 05:59:12.200920 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4551 05:59:12.204570 == TX Byte 1 ==
4552 05:59:12.207541 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4553 05:59:12.211197 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4554 05:59:12.211273
4555 05:59:12.214148 [DATLAT]
4556 05:59:12.214223 Freq=600, CH1 RK0
4557 05:59:12.214288
4558 05:59:12.217314 DATLAT Default: 0x9
4559 05:59:12.217387 0, 0xFFFF, sum = 0
4560 05:59:12.220943 1, 0xFFFF, sum = 0
4561 05:59:12.221019 2, 0xFFFF, sum = 0
4562 05:59:12.224414 3, 0xFFFF, sum = 0
4563 05:59:12.224489 4, 0xFFFF, sum = 0
4564 05:59:12.227550 5, 0xFFFF, sum = 0
4565 05:59:12.227623 6, 0xFFFF, sum = 0
4566 05:59:12.231099 7, 0xFFFF, sum = 0
4567 05:59:12.231171 8, 0x0, sum = 1
4568 05:59:12.234263 9, 0x0, sum = 2
4569 05:59:12.234338 10, 0x0, sum = 3
4570 05:59:12.237699 11, 0x0, sum = 4
4571 05:59:12.237777 best_step = 9
4572 05:59:12.237841
4573 05:59:12.237907 ==
4574 05:59:12.240736 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 05:59:12.247637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 05:59:12.247719 ==
4577 05:59:12.247784 RX Vref Scan: 1
4578 05:59:12.247845
4579 05:59:12.250489 RX Vref 0 -> 0, step: 1
4580 05:59:12.250570
4581 05:59:12.254320 RX Delay -195 -> 252, step: 8
4582 05:59:12.254399
4583 05:59:12.257550 Set Vref, RX VrefLevel [Byte0]: 59
4584 05:59:12.260585 [Byte1]: 48
4585 05:59:12.260666
4586 05:59:12.263954 Final RX Vref Byte 0 = 59 to rank0
4587 05:59:12.266909 Final RX Vref Byte 1 = 48 to rank0
4588 05:59:12.270382 Final RX Vref Byte 0 = 59 to rank1
4589 05:59:12.273439 Final RX Vref Byte 1 = 48 to rank1==
4590 05:59:12.277042 Dram Type= 6, Freq= 0, CH_1, rank 0
4591 05:59:12.280034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 05:59:12.280113 ==
4593 05:59:12.283345 DQS Delay:
4594 05:59:12.283424 DQS0 = 0, DQS1 = 0
4595 05:59:12.287329 DQM Delay:
4596 05:59:12.287416 DQM0 = 39, DQM1 = 28
4597 05:59:12.287516 DQ Delay:
4598 05:59:12.290123 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4599 05:59:12.293641 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4600 05:59:12.296877 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =20
4601 05:59:12.299802 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4602 05:59:12.299918
4603 05:59:12.300012
4604 05:59:12.310215 [DQSOSCAuto] RK0, (LSB)MR18= 0x222f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4605 05:59:12.313259 CH1 RK0: MR19=808, MR18=222F
4606 05:59:12.319738 CH1_RK0: MR19=0x808, MR18=0x222F, DQSOSC=400, MR23=63, INC=163, DEC=109
4607 05:59:12.319820
4608 05:59:12.323458 ----->DramcWriteLeveling(PI) begin...
4609 05:59:12.323554 ==
4610 05:59:12.326560 Dram Type= 6, Freq= 0, CH_1, rank 1
4611 05:59:12.330100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 05:59:12.330179 ==
4613 05:59:12.333139 Write leveling (Byte 0): 29 => 29
4614 05:59:12.336047 Write leveling (Byte 1): 33 => 33
4615 05:59:12.339764 DramcWriteLeveling(PI) end<-----
4616 05:59:12.339840
4617 05:59:12.339906 ==
4618 05:59:12.342702 Dram Type= 6, Freq= 0, CH_1, rank 1
4619 05:59:12.346250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 05:59:12.346326 ==
4621 05:59:12.349516 [Gating] SW mode calibration
4622 05:59:12.355919 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4623 05:59:12.362502 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4624 05:59:12.365754 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4625 05:59:12.368998 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4626 05:59:12.375646 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4627 05:59:12.379212 0 9 12 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
4628 05:59:12.382208 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4629 05:59:12.388906 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 05:59:12.392234 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 05:59:12.395773 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 05:59:12.402401 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 05:59:12.405519 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 05:59:12.411769 0 10 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
4635 05:59:12.415316 0 10 12 | B1->B0 | 3232 3b3b | 0 0 | (0 0) (0 0)
4636 05:59:12.418466 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
4637 05:59:12.424825 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 05:59:12.428423 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 05:59:12.431501 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 05:59:12.438199 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 05:59:12.441693 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 05:59:12.445127 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 05:59:12.451246 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4644 05:59:12.454694 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4645 05:59:12.458045 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 05:59:12.464724 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 05:59:12.468216 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 05:59:12.471152 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 05:59:12.477882 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 05:59:12.480975 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 05:59:12.484406 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 05:59:12.487866 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 05:59:12.494392 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 05:59:12.497882 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 05:59:12.504300 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 05:59:12.507766 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 05:59:12.510635 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 05:59:12.517653 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 05:59:12.520488 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4660 05:59:12.524301 Total UI for P1: 0, mck2ui 16
4661 05:59:12.527390 best dqsien dly found for B0: ( 0, 13, 10)
4662 05:59:12.530490 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4663 05:59:12.533873 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 05:59:12.537317 Total UI for P1: 0, mck2ui 16
4665 05:59:12.540335 best dqsien dly found for B1: ( 0, 13, 14)
4666 05:59:12.543818 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4667 05:59:12.550374 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4668 05:59:12.550454
4669 05:59:12.553921 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4670 05:59:12.557029 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4671 05:59:12.560644 [Gating] SW calibration Done
4672 05:59:12.560752 ==
4673 05:59:12.563510 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 05:59:12.567062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 05:59:12.567142 ==
4676 05:59:12.570312 RX Vref Scan: 0
4677 05:59:12.570411
4678 05:59:12.570487 RX Vref 0 -> 0, step: 1
4679 05:59:12.570547
4680 05:59:12.573514 RX Delay -230 -> 252, step: 16
4681 05:59:12.576919 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4682 05:59:12.583420 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4683 05:59:12.586858 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4684 05:59:12.590023 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4685 05:59:12.593309 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4686 05:59:12.600203 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4687 05:59:12.603124 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4688 05:59:12.606514 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4689 05:59:12.610080 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4690 05:59:12.616613 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4691 05:59:12.619823 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4692 05:59:12.623412 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4693 05:59:12.626394 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4694 05:59:12.632765 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4695 05:59:12.635961 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4696 05:59:12.639361 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4697 05:59:12.639486 ==
4698 05:59:12.643256 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 05:59:12.646107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 05:59:12.646191 ==
4701 05:59:12.649699 DQS Delay:
4702 05:59:12.649793 DQS0 = 0, DQS1 = 0
4703 05:59:12.652737 DQM Delay:
4704 05:59:12.652841 DQM0 = 36, DQM1 = 29
4705 05:59:12.652932 DQ Delay:
4706 05:59:12.656407 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4707 05:59:12.659328 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4708 05:59:12.662313 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4709 05:59:12.666143 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4710 05:59:12.666261
4711 05:59:12.668948
4712 05:59:12.669054 ==
4713 05:59:12.672556 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 05:59:12.675584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 05:59:12.675753 ==
4716 05:59:12.675845
4717 05:59:12.675932
4718 05:59:12.678865 TX Vref Scan disable
4719 05:59:12.679048 == TX Byte 0 ==
4720 05:59:12.685710 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4721 05:59:12.688810 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4722 05:59:12.688976 == TX Byte 1 ==
4723 05:59:12.695702 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4724 05:59:12.698789 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4725 05:59:12.698947 ==
4726 05:59:12.702060 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 05:59:12.705405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 05:59:12.705500 ==
4729 05:59:12.705577
4730 05:59:12.705636
4731 05:59:12.709000 TX Vref Scan disable
4732 05:59:12.712341 == TX Byte 0 ==
4733 05:59:12.715267 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4734 05:59:12.721821 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4735 05:59:12.721903 == TX Byte 1 ==
4736 05:59:12.725199 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4737 05:59:12.732029 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4738 05:59:12.732137
4739 05:59:12.732238 [DATLAT]
4740 05:59:12.732331 Freq=600, CH1 RK1
4741 05:59:12.732419
4742 05:59:12.735153 DATLAT Default: 0x9
4743 05:59:12.735229 0, 0xFFFF, sum = 0
4744 05:59:12.738826 1, 0xFFFF, sum = 0
4745 05:59:12.738934 2, 0xFFFF, sum = 0
4746 05:59:12.741721 3, 0xFFFF, sum = 0
4747 05:59:12.745234 4, 0xFFFF, sum = 0
4748 05:59:12.745319 5, 0xFFFF, sum = 0
4749 05:59:12.748404 6, 0xFFFF, sum = 0
4750 05:59:12.748505 7, 0xFFFF, sum = 0
4751 05:59:12.751710 8, 0x0, sum = 1
4752 05:59:12.751814 9, 0x0, sum = 2
4753 05:59:12.751907 10, 0x0, sum = 3
4754 05:59:12.755330 11, 0x0, sum = 4
4755 05:59:12.755432 best_step = 9
4756 05:59:12.755524
4757 05:59:12.755611 ==
4758 05:59:12.758378 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 05:59:12.765066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 05:59:12.765146 ==
4761 05:59:12.765214 RX Vref Scan: 0
4762 05:59:12.765305
4763 05:59:12.768044 RX Vref 0 -> 0, step: 1
4764 05:59:12.768116
4765 05:59:12.771557 RX Delay -195 -> 252, step: 8
4766 05:59:12.777943 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4767 05:59:12.781523 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4768 05:59:12.784407 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4769 05:59:12.787855 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4770 05:59:12.791213 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4771 05:59:12.797799 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4772 05:59:12.801323 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4773 05:59:12.804229 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4774 05:59:12.807705 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4775 05:59:12.814437 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4776 05:59:12.817880 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4777 05:59:12.820906 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4778 05:59:12.824631 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4779 05:59:12.830693 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4780 05:59:12.834063 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4781 05:59:12.837280 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4782 05:59:12.837389 ==
4783 05:59:12.840720 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 05:59:12.844299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 05:59:12.847198 ==
4786 05:59:12.847301 DQS Delay:
4787 05:59:12.847402 DQS0 = 0, DQS1 = 0
4788 05:59:12.850858 DQM Delay:
4789 05:59:12.850984 DQM0 = 36, DQM1 = 30
4790 05:59:12.851076 DQ Delay:
4791 05:59:12.854077 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4792 05:59:12.857485 DQ4 =32, DQ5 =44, DQ6 =48, DQ7 =36
4793 05:59:12.860360 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =20
4794 05:59:12.864034 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4795 05:59:12.864111
4796 05:59:12.866978
4797 05:59:12.873700 [DQSOSCAuto] RK1, (LSB)MR18= 0x3453, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
4798 05:59:12.877238 CH1 RK1: MR19=808, MR18=3453
4799 05:59:12.883868 CH1_RK1: MR19=0x808, MR18=0x3453, DQSOSC=394, MR23=63, INC=168, DEC=112
4800 05:59:12.886990 [RxdqsGatingPostProcess] freq 600
4801 05:59:12.890537 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4802 05:59:12.893660 Pre-setting of DQS Precalculation
4803 05:59:12.900341 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4804 05:59:12.906642 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4805 05:59:12.913201 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4806 05:59:12.913312
4807 05:59:12.913405
4808 05:59:12.916734 [Calibration Summary] 1200 Mbps
4809 05:59:12.916809 CH 0, Rank 0
4810 05:59:12.919706 SW Impedance : PASS
4811 05:59:12.923714 DUTY Scan : NO K
4812 05:59:12.923813 ZQ Calibration : PASS
4813 05:59:12.926602 Jitter Meter : NO K
4814 05:59:12.929463 CBT Training : PASS
4815 05:59:12.929569 Write leveling : PASS
4816 05:59:12.933173 RX DQS gating : PASS
4817 05:59:12.936214 RX DQ/DQS(RDDQC) : PASS
4818 05:59:12.936289 TX DQ/DQS : PASS
4819 05:59:12.939687 RX DATLAT : PASS
4820 05:59:12.943254 RX DQ/DQS(Engine): PASS
4821 05:59:12.943331 TX OE : NO K
4822 05:59:12.943396 All Pass.
4823 05:59:12.946013
4824 05:59:12.946099 CH 0, Rank 1
4825 05:59:12.949442 SW Impedance : PASS
4826 05:59:12.949524 DUTY Scan : NO K
4827 05:59:12.953164 ZQ Calibration : PASS
4828 05:59:12.953259 Jitter Meter : NO K
4829 05:59:12.956184 CBT Training : PASS
4830 05:59:12.959412 Write leveling : PASS
4831 05:59:12.959504 RX DQS gating : PASS
4832 05:59:12.962673 RX DQ/DQS(RDDQC) : PASS
4833 05:59:12.966237 TX DQ/DQS : PASS
4834 05:59:12.966318 RX DATLAT : PASS
4835 05:59:12.969288 RX DQ/DQS(Engine): PASS
4836 05:59:12.972946 TX OE : NO K
4837 05:59:12.973021 All Pass.
4838 05:59:12.973090
4839 05:59:12.973150 CH 1, Rank 0
4840 05:59:12.975986 SW Impedance : PASS
4841 05:59:12.979560 DUTY Scan : NO K
4842 05:59:12.979634 ZQ Calibration : PASS
4843 05:59:12.982498 Jitter Meter : NO K
4844 05:59:12.985975 CBT Training : PASS
4845 05:59:12.986049 Write leveling : PASS
4846 05:59:12.989187 RX DQS gating : PASS
4847 05:59:12.992717 RX DQ/DQS(RDDQC) : PASS
4848 05:59:12.992803 TX DQ/DQS : PASS
4849 05:59:12.995707 RX DATLAT : PASS
4850 05:59:12.999186 RX DQ/DQS(Engine): PASS
4851 05:59:12.999263 TX OE : NO K
4852 05:59:13.002607 All Pass.
4853 05:59:13.002720
4854 05:59:13.002822 CH 1, Rank 1
4855 05:59:13.005935 SW Impedance : PASS
4856 05:59:13.006014 DUTY Scan : NO K
4857 05:59:13.009299 ZQ Calibration : PASS
4858 05:59:13.012423 Jitter Meter : NO K
4859 05:59:13.012526 CBT Training : PASS
4860 05:59:13.015546 Write leveling : PASS
4861 05:59:13.015649 RX DQS gating : PASS
4862 05:59:13.019238 RX DQ/DQS(RDDQC) : PASS
4863 05:59:13.022599 TX DQ/DQS : PASS
4864 05:59:13.022695 RX DATLAT : PASS
4865 05:59:13.025685 RX DQ/DQS(Engine): PASS
4866 05:59:13.029289 TX OE : NO K
4867 05:59:13.029388 All Pass.
4868 05:59:13.029482
4869 05:59:13.032187 DramC Write-DBI off
4870 05:59:13.032292 PER_BANK_REFRESH: Hybrid Mode
4871 05:59:13.035430 TX_TRACKING: ON
4872 05:59:13.045354 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4873 05:59:13.048802 [FAST_K] Save calibration result to emmc
4874 05:59:13.052165 dramc_set_vcore_voltage set vcore to 662500
4875 05:59:13.052273 Read voltage for 933, 3
4876 05:59:13.055715 Vio18 = 0
4877 05:59:13.055824 Vcore = 662500
4878 05:59:13.055914 Vdram = 0
4879 05:59:13.058904 Vddq = 0
4880 05:59:13.059008 Vmddr = 0
4881 05:59:13.065201 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4882 05:59:13.068418 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4883 05:59:13.071909 MEM_TYPE=3, freq_sel=17
4884 05:59:13.075311 sv_algorithm_assistance_LP4_1600
4885 05:59:13.078397 ============ PULL DRAM RESETB DOWN ============
4886 05:59:13.081769 ========== PULL DRAM RESETB DOWN end =========
4887 05:59:13.089002 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4888 05:59:13.091952 ===================================
4889 05:59:13.092045 LPDDR4 DRAM CONFIGURATION
4890 05:59:13.094936 ===================================
4891 05:59:13.098657 EX_ROW_EN[0] = 0x0
4892 05:59:13.101794 EX_ROW_EN[1] = 0x0
4893 05:59:13.101869 LP4Y_EN = 0x0
4894 05:59:13.104867 WORK_FSP = 0x0
4895 05:59:13.104951 WL = 0x3
4896 05:59:13.108214 RL = 0x3
4897 05:59:13.108294 BL = 0x2
4898 05:59:13.111769 RPST = 0x0
4899 05:59:13.111847 RD_PRE = 0x0
4900 05:59:13.114915 WR_PRE = 0x1
4901 05:59:13.115011 WR_PST = 0x0
4902 05:59:13.118265 DBI_WR = 0x0
4903 05:59:13.118351 DBI_RD = 0x0
4904 05:59:13.121686 OTF = 0x1
4905 05:59:13.124659 ===================================
4906 05:59:13.127995 ===================================
4907 05:59:13.128078 ANA top config
4908 05:59:13.131721 ===================================
4909 05:59:13.134720 DLL_ASYNC_EN = 0
4910 05:59:13.137939 ALL_SLAVE_EN = 1
4911 05:59:13.141500 NEW_RANK_MODE = 1
4912 05:59:13.141584 DLL_IDLE_MODE = 1
4913 05:59:13.144809 LP45_APHY_COMB_EN = 1
4914 05:59:13.147884 TX_ODT_DIS = 1
4915 05:59:13.151105 NEW_8X_MODE = 1
4916 05:59:13.154835 ===================================
4917 05:59:13.158358 ===================================
4918 05:59:13.158435 data_rate = 1866
4919 05:59:13.161631 CKR = 1
4920 05:59:13.164660 DQ_P2S_RATIO = 8
4921 05:59:13.167828 ===================================
4922 05:59:13.171095 CA_P2S_RATIO = 8
4923 05:59:13.174444 DQ_CA_OPEN = 0
4924 05:59:13.177985 DQ_SEMI_OPEN = 0
4925 05:59:13.178069 CA_SEMI_OPEN = 0
4926 05:59:13.181471 CA_FULL_RATE = 0
4927 05:59:13.184499 DQ_CKDIV4_EN = 1
4928 05:59:13.188009 CA_CKDIV4_EN = 1
4929 05:59:13.191380 CA_PREDIV_EN = 0
4930 05:59:13.194398 PH8_DLY = 0
4931 05:59:13.194477 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4932 05:59:13.197949 DQ_AAMCK_DIV = 4
4933 05:59:13.200942 CA_AAMCK_DIV = 4
4934 05:59:13.204539 CA_ADMCK_DIV = 4
4935 05:59:13.207665 DQ_TRACK_CA_EN = 0
4936 05:59:13.211267 CA_PICK = 933
4937 05:59:13.214282 CA_MCKIO = 933
4938 05:59:13.214357 MCKIO_SEMI = 0
4939 05:59:13.217875 PLL_FREQ = 3732
4940 05:59:13.220666 DQ_UI_PI_RATIO = 32
4941 05:59:13.224334 CA_UI_PI_RATIO = 0
4942 05:59:13.227793 ===================================
4943 05:59:13.231124 ===================================
4944 05:59:13.234147 memory_type:LPDDR4
4945 05:59:13.234227 GP_NUM : 10
4946 05:59:13.237644 SRAM_EN : 1
4947 05:59:13.240678 MD32_EN : 0
4948 05:59:13.244212 ===================================
4949 05:59:13.244286 [ANA_INIT] >>>>>>>>>>>>>>
4950 05:59:13.247672 <<<<<< [CONFIGURE PHASE]: ANA_TX
4951 05:59:13.250691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4952 05:59:13.254277 ===================================
4953 05:59:13.257237 data_rate = 1866,PCW = 0X8f00
4954 05:59:13.260860 ===================================
4955 05:59:13.264305 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4956 05:59:13.270323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4957 05:59:13.274023 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 05:59:13.280525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4959 05:59:13.284056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4960 05:59:13.286985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4961 05:59:13.287061 [ANA_INIT] flow start
4962 05:59:13.290660 [ANA_INIT] PLL >>>>>>>>
4963 05:59:13.293652 [ANA_INIT] PLL <<<<<<<<
4964 05:59:13.297126 [ANA_INIT] MIDPI >>>>>>>>
4965 05:59:13.297214 [ANA_INIT] MIDPI <<<<<<<<
4966 05:59:13.300638 [ANA_INIT] DLL >>>>>>>>
4967 05:59:13.303899 [ANA_INIT] flow end
4968 05:59:13.306994 ============ LP4 DIFF to SE enter ============
4969 05:59:13.310594 ============ LP4 DIFF to SE exit ============
4970 05:59:13.313557 [ANA_INIT] <<<<<<<<<<<<<
4971 05:59:13.317064 [Flow] Enable top DCM control >>>>>
4972 05:59:13.320742 [Flow] Enable top DCM control <<<<<
4973 05:59:13.323700 Enable DLL master slave shuffle
4974 05:59:13.327116 ==============================================================
4975 05:59:13.330083 Gating Mode config
4976 05:59:13.333335 ==============================================================
4977 05:59:13.336793 Config description:
4978 05:59:13.346720 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4979 05:59:13.353713 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4980 05:59:13.356503 SELPH_MODE 0: By rank 1: By Phase
4981 05:59:13.363555 ==============================================================
4982 05:59:13.366611 GAT_TRACK_EN = 1
4983 05:59:13.370191 RX_GATING_MODE = 2
4984 05:59:13.373181 RX_GATING_TRACK_MODE = 2
4985 05:59:13.376345 SELPH_MODE = 1
4986 05:59:13.379766 PICG_EARLY_EN = 1
4987 05:59:13.383131 VALID_LAT_VALUE = 1
4988 05:59:13.386431 ==============================================================
4989 05:59:13.389974 Enter into Gating configuration >>>>
4990 05:59:13.393052 Exit from Gating configuration <<<<
4991 05:59:13.396355 Enter into DVFS_PRE_config >>>>>
4992 05:59:13.409494 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4993 05:59:13.409580 Exit from DVFS_PRE_config <<<<<
4994 05:59:13.413048 Enter into PICG configuration >>>>
4995 05:59:13.416011 Exit from PICG configuration <<<<
4996 05:59:13.419600 [RX_INPUT] configuration >>>>>
4997 05:59:13.422594 [RX_INPUT] configuration <<<<<
4998 05:59:13.429121 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4999 05:59:13.432461 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5000 05:59:13.439521 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5001 05:59:13.445896 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5002 05:59:13.452392 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5003 05:59:13.459553 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5004 05:59:13.462355 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5005 05:59:13.465780 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5006 05:59:13.469209 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5007 05:59:13.475824 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5008 05:59:13.478806 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5009 05:59:13.482316 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 05:59:13.485779 ===================================
5011 05:59:13.489291 LPDDR4 DRAM CONFIGURATION
5012 05:59:13.492482 ===================================
5013 05:59:13.492556 EX_ROW_EN[0] = 0x0
5014 05:59:13.495395 EX_ROW_EN[1] = 0x0
5015 05:59:13.498981 LP4Y_EN = 0x0
5016 05:59:13.499056 WORK_FSP = 0x0
5017 05:59:13.502152 WL = 0x3
5018 05:59:13.502227 RL = 0x3
5019 05:59:13.505432 BL = 0x2
5020 05:59:13.505525 RPST = 0x0
5021 05:59:13.508799 RD_PRE = 0x0
5022 05:59:13.508873 WR_PRE = 0x1
5023 05:59:13.511939 WR_PST = 0x0
5024 05:59:13.512014 DBI_WR = 0x0
5025 05:59:13.515686 DBI_RD = 0x0
5026 05:59:13.515759 OTF = 0x1
5027 05:59:13.518763 ===================================
5028 05:59:13.522335 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5029 05:59:13.529056 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5030 05:59:13.532011 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5031 05:59:13.535668 ===================================
5032 05:59:13.538536 LPDDR4 DRAM CONFIGURATION
5033 05:59:13.542400 ===================================
5034 05:59:13.542478 EX_ROW_EN[0] = 0x10
5035 05:59:13.545679 EX_ROW_EN[1] = 0x0
5036 05:59:13.549090 LP4Y_EN = 0x0
5037 05:59:13.549165 WORK_FSP = 0x0
5038 05:59:13.551979 WL = 0x3
5039 05:59:13.552061 RL = 0x3
5040 05:59:13.555322 BL = 0x2
5041 05:59:13.555397 RPST = 0x0
5042 05:59:13.558909 RD_PRE = 0x0
5043 05:59:13.559001 WR_PRE = 0x1
5044 05:59:13.562004 WR_PST = 0x0
5045 05:59:13.562074 DBI_WR = 0x0
5046 05:59:13.565431 DBI_RD = 0x0
5047 05:59:13.565547 OTF = 0x1
5048 05:59:13.568933 ===================================
5049 05:59:13.575234 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5050 05:59:13.579909 nWR fixed to 30
5051 05:59:13.582948 [ModeRegInit_LP4] CH0 RK0
5052 05:59:13.583065 [ModeRegInit_LP4] CH0 RK1
5053 05:59:13.585794 [ModeRegInit_LP4] CH1 RK0
5054 05:59:13.589247 [ModeRegInit_LP4] CH1 RK1
5055 05:59:13.589343 match AC timing 9
5056 05:59:13.595741 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5057 05:59:13.598945 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5058 05:59:13.602483 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5059 05:59:13.609312 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5060 05:59:13.612739 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5061 05:59:13.612819 ==
5062 05:59:13.615814 Dram Type= 6, Freq= 0, CH_0, rank 0
5063 05:59:13.619045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 05:59:13.619149 ==
5065 05:59:13.625954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 05:59:13.632788 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5067 05:59:13.635844 [CA 0] Center 38 (8~69) winsize 62
5068 05:59:13.638948 [CA 1] Center 38 (8~69) winsize 62
5069 05:59:13.642454 [CA 2] Center 35 (5~66) winsize 62
5070 05:59:13.645963 [CA 3] Center 35 (5~65) winsize 61
5071 05:59:13.648884 [CA 4] Center 34 (4~65) winsize 62
5072 05:59:13.652356 [CA 5] Center 33 (3~64) winsize 62
5073 05:59:13.652435
5074 05:59:13.655485 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5075 05:59:13.655557
5076 05:59:13.658963 [CATrainingPosCal] consider 1 rank data
5077 05:59:13.662368 u2DelayCellTimex100 = 270/100 ps
5078 05:59:13.665841 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5079 05:59:13.668883 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5080 05:59:13.671959 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5081 05:59:13.675518 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5082 05:59:13.681855 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5083 05:59:13.685508 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5084 05:59:13.685589
5085 05:59:13.688799 CA PerBit enable=1, Macro0, CA PI delay=33
5086 05:59:13.688868
5087 05:59:13.692326 [CBTSetCACLKResult] CA Dly = 33
5088 05:59:13.692420 CS Dly: 7 (0~38)
5089 05:59:13.692487 ==
5090 05:59:13.695225 Dram Type= 6, Freq= 0, CH_0, rank 1
5091 05:59:13.701927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 05:59:13.702043 ==
5093 05:59:13.705087 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5094 05:59:13.711625 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5095 05:59:13.715246 [CA 0] Center 38 (8~69) winsize 62
5096 05:59:13.718285 [CA 1] Center 38 (7~69) winsize 63
5097 05:59:13.721896 [CA 2] Center 35 (5~66) winsize 62
5098 05:59:13.725360 [CA 3] Center 35 (5~66) winsize 62
5099 05:59:13.728248 [CA 4] Center 34 (3~65) winsize 63
5100 05:59:13.731867 [CA 5] Center 33 (3~64) winsize 62
5101 05:59:13.731950
5102 05:59:13.734732 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5103 05:59:13.734841
5104 05:59:13.738332 [CATrainingPosCal] consider 2 rank data
5105 05:59:13.741411 u2DelayCellTimex100 = 270/100 ps
5106 05:59:13.744951 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5107 05:59:13.748037 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5108 05:59:13.755037 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5109 05:59:13.758065 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5110 05:59:13.761792 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5111 05:59:13.764875 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5112 05:59:13.764959
5113 05:59:13.768433 CA PerBit enable=1, Macro0, CA PI delay=33
5114 05:59:13.768547
5115 05:59:13.771195 [CBTSetCACLKResult] CA Dly = 33
5116 05:59:13.771311 CS Dly: 7 (0~38)
5117 05:59:13.771413
5118 05:59:13.774674 ----->DramcWriteLeveling(PI) begin...
5119 05:59:13.777823 ==
5120 05:59:13.781498 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 05:59:13.784332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 05:59:13.784442 ==
5123 05:59:13.787839 Write leveling (Byte 0): 31 => 31
5124 05:59:13.791387 Write leveling (Byte 1): 31 => 31
5125 05:59:13.794783 DramcWriteLeveling(PI) end<-----
5126 05:59:13.794896
5127 05:59:13.794997 ==
5128 05:59:13.797972 Dram Type= 6, Freq= 0, CH_0, rank 0
5129 05:59:13.801385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 05:59:13.801504 ==
5131 05:59:13.804303 [Gating] SW mode calibration
5132 05:59:13.810940 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5133 05:59:13.817961 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5134 05:59:13.820962 0 14 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5135 05:59:13.824605 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
5136 05:59:13.830637 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 05:59:13.834230 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 05:59:13.837632 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 05:59:13.843957 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 05:59:13.847363 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 05:59:13.850918 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5142 05:59:13.857329 0 15 0 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 1)
5143 05:59:13.860579 0 15 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
5144 05:59:13.864090 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 05:59:13.870129 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 05:59:13.873791 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 05:59:13.876746 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 05:59:13.883436 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 05:59:13.886967 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5150 05:59:13.890055 1 0 0 | B1->B0 | 2f2f 3a3a | 1 0 | (1 1) (0 0)
5151 05:59:13.896743 1 0 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5152 05:59:13.900384 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 05:59:13.903181 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 05:59:13.909813 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 05:59:13.913178 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 05:59:13.916476 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 05:59:13.923502 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5158 05:59:13.926509 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5159 05:59:13.930041 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 05:59:13.936504 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 05:59:13.939584 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 05:59:13.943029 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 05:59:13.949466 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 05:59:13.952756 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 05:59:13.956359 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 05:59:13.962629 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 05:59:13.966039 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 05:59:13.969397 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 05:59:13.976062 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 05:59:13.979122 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 05:59:13.982577 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 05:59:13.989247 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 05:59:13.992401 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5174 05:59:13.995852 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5175 05:59:13.999512 Total UI for P1: 0, mck2ui 16
5176 05:59:14.002429 best dqsien dly found for B0: ( 1, 2, 28)
5177 05:59:14.005600 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5178 05:59:14.012113 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 05:59:14.015540 Total UI for P1: 0, mck2ui 16
5180 05:59:14.019375 best dqsien dly found for B1: ( 1, 3, 4)
5181 05:59:14.022484 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5182 05:59:14.025731 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5183 05:59:14.025814
5184 05:59:14.028839 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5185 05:59:14.032520 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5186 05:59:14.035572 [Gating] SW calibration Done
5187 05:59:14.035646 ==
5188 05:59:14.038634 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 05:59:14.042271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 05:59:14.042342 ==
5191 05:59:14.045720 RX Vref Scan: 0
5192 05:59:14.045804
5193 05:59:14.048789 RX Vref 0 -> 0, step: 1
5194 05:59:14.048893
5195 05:59:14.048984 RX Delay -80 -> 252, step: 8
5196 05:59:14.055469 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5197 05:59:14.058439 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5198 05:59:14.061864 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5199 05:59:14.065353 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5200 05:59:14.068242 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5201 05:59:14.071527 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5202 05:59:14.078425 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5203 05:59:14.081496 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5204 05:59:14.085097 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5205 05:59:14.088256 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5206 05:59:14.091717 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5207 05:59:14.098337 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5208 05:59:14.101399 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5209 05:59:14.105108 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5210 05:59:14.108238 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5211 05:59:14.114973 iDelay=208, Bit 15, Center 87 (-16 ~ 191) 208
5212 05:59:14.115047 ==
5213 05:59:14.118072 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 05:59:14.121579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 05:59:14.121652 ==
5216 05:59:14.121712 DQS Delay:
5217 05:59:14.125057 DQS0 = 0, DQS1 = 0
5218 05:59:14.125127 DQM Delay:
5219 05:59:14.127862 DQM0 = 95, DQM1 = 82
5220 05:59:14.127959 DQ Delay:
5221 05:59:14.131224 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5222 05:59:14.134737 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5223 05:59:14.138106 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5224 05:59:14.141180 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =87
5225 05:59:14.141275
5226 05:59:14.141365
5227 05:59:14.141465 ==
5228 05:59:14.144448 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 05:59:14.148151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 05:59:14.148219 ==
5231 05:59:14.148279
5232 05:59:14.151262
5233 05:59:14.151346 TX Vref Scan disable
5234 05:59:14.154783 == TX Byte 0 ==
5235 05:59:14.157742 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5236 05:59:14.161342 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5237 05:59:14.164452 == TX Byte 1 ==
5238 05:59:14.167973 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5239 05:59:14.171330 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5240 05:59:14.171426 ==
5241 05:59:14.174738 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 05:59:14.180801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 05:59:14.180921 ==
5244 05:59:14.181053
5245 05:59:14.181137
5246 05:59:14.181211 TX Vref Scan disable
5247 05:59:14.185124 == TX Byte 0 ==
5248 05:59:14.188253 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5249 05:59:14.191800 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5250 05:59:14.195479 == TX Byte 1 ==
5251 05:59:14.198500 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5252 05:59:14.205291 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5253 05:59:14.205413
5254 05:59:14.205522 [DATLAT]
5255 05:59:14.205584 Freq=933, CH0 RK0
5256 05:59:14.205642
5257 05:59:14.208160 DATLAT Default: 0xd
5258 05:59:14.208262 0, 0xFFFF, sum = 0
5259 05:59:14.211965 1, 0xFFFF, sum = 0
5260 05:59:14.212061 2, 0xFFFF, sum = 0
5261 05:59:14.214933 3, 0xFFFF, sum = 0
5262 05:59:14.218438 4, 0xFFFF, sum = 0
5263 05:59:14.218537 5, 0xFFFF, sum = 0
5264 05:59:14.221370 6, 0xFFFF, sum = 0
5265 05:59:14.221501 7, 0xFFFF, sum = 0
5266 05:59:14.225079 8, 0xFFFF, sum = 0
5267 05:59:14.225189 9, 0xFFFF, sum = 0
5268 05:59:14.228206 10, 0x0, sum = 1
5269 05:59:14.228326 11, 0x0, sum = 2
5270 05:59:14.231508 12, 0x0, sum = 3
5271 05:59:14.231596 13, 0x0, sum = 4
5272 05:59:14.231661 best_step = 11
5273 05:59:14.231721
5274 05:59:14.235107 ==
5275 05:59:14.237935 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 05:59:14.241514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 05:59:14.241597 ==
5278 05:59:14.241663 RX Vref Scan: 1
5279 05:59:14.241725
5280 05:59:14.244972 RX Vref 0 -> 0, step: 1
5281 05:59:14.245053
5282 05:59:14.247900 RX Delay -69 -> 252, step: 4
5283 05:59:14.247974
5284 05:59:14.251314 Set Vref, RX VrefLevel [Byte0]: 61
5285 05:59:14.254419 [Byte1]: 47
5286 05:59:14.254501
5287 05:59:14.258307 Final RX Vref Byte 0 = 61 to rank0
5288 05:59:14.261395 Final RX Vref Byte 1 = 47 to rank0
5289 05:59:14.264524 Final RX Vref Byte 0 = 61 to rank1
5290 05:59:14.268238 Final RX Vref Byte 1 = 47 to rank1==
5291 05:59:14.271254 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 05:59:14.277886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 05:59:14.277992 ==
5294 05:59:14.278084 DQS Delay:
5295 05:59:14.278172 DQS0 = 0, DQS1 = 0
5296 05:59:14.281220 DQM Delay:
5297 05:59:14.281317 DQM0 = 96, DQM1 = 82
5298 05:59:14.284384 DQ Delay:
5299 05:59:14.287893 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =92
5300 05:59:14.290932 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =108
5301 05:59:14.294297 DQ8 =74, DQ9 =70, DQ10 =84, DQ11 =78
5302 05:59:14.297646 DQ12 =86, DQ13 =86, DQ14 =92, DQ15 =90
5303 05:59:14.297756
5304 05:59:14.297847
5305 05:59:14.304321 [DQSOSCAuto] RK0, (LSB)MR18= 0x1010, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5306 05:59:14.307401 CH0 RK0: MR19=505, MR18=1010
5307 05:59:14.314255 CH0_RK0: MR19=0x505, MR18=0x1010, DQSOSC=416, MR23=63, INC=62, DEC=41
5308 05:59:14.314363
5309 05:59:14.317179 ----->DramcWriteLeveling(PI) begin...
5310 05:59:14.317286 ==
5311 05:59:14.320860 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 05:59:14.323936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 05:59:14.324038 ==
5314 05:59:14.327444 Write leveling (Byte 0): 29 => 29
5315 05:59:14.330653 Write leveling (Byte 1): 28 => 28
5316 05:59:14.334082 DramcWriteLeveling(PI) end<-----
5317 05:59:14.334181
5318 05:59:14.334267 ==
5319 05:59:14.337445 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 05:59:14.340309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 05:59:14.340379 ==
5322 05:59:14.343863 [Gating] SW mode calibration
5323 05:59:14.350217 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5324 05:59:14.357334 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5325 05:59:14.360823 0 14 0 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
5326 05:59:14.367295 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 05:59:14.370098 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 05:59:14.373720 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 05:59:14.380289 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 05:59:14.383364 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 05:59:14.386862 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5332 05:59:14.393845 0 14 28 | B1->B0 | 3131 2b2b | 0 0 | (0 0) (0 0)
5333 05:59:14.397017 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5334 05:59:14.400007 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 05:59:14.406825 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 05:59:14.410014 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 05:59:14.413303 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 05:59:14.419846 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 05:59:14.423156 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 05:59:14.426726 0 15 28 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
5341 05:59:14.433313 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5342 05:59:14.436945 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 05:59:14.439899 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 05:59:14.443310 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 05:59:14.449897 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 05:59:14.453244 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 05:59:14.456791 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5348 05:59:14.463023 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5349 05:59:14.466333 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5350 05:59:14.469976 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 05:59:14.476773 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 05:59:14.479584 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 05:59:14.483454 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 05:59:14.489825 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 05:59:14.492839 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 05:59:14.496314 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 05:59:14.503104 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 05:59:14.506191 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 05:59:14.509821 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 05:59:14.516053 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 05:59:14.519754 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 05:59:14.522927 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 05:59:14.529275 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5364 05:59:14.532959 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5365 05:59:14.536208 Total UI for P1: 0, mck2ui 16
5366 05:59:14.539244 best dqsien dly found for B0: ( 1, 2, 24)
5367 05:59:14.542968 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5368 05:59:14.549411 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 05:59:14.549512 Total UI for P1: 0, mck2ui 16
5370 05:59:14.556105 best dqsien dly found for B1: ( 1, 3, 0)
5371 05:59:14.559344 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5372 05:59:14.562503 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5373 05:59:14.562593
5374 05:59:14.565702 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5375 05:59:14.569336 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5376 05:59:14.572637 [Gating] SW calibration Done
5377 05:59:14.572741 ==
5378 05:59:14.576026 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 05:59:14.579098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 05:59:14.579221 ==
5381 05:59:14.582628 RX Vref Scan: 0
5382 05:59:14.582750
5383 05:59:14.582845 RX Vref 0 -> 0, step: 1
5384 05:59:14.582935
5385 05:59:14.585833 RX Delay -80 -> 252, step: 8
5386 05:59:14.589105 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5387 05:59:14.595706 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5388 05:59:14.599141 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5389 05:59:14.602110 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5390 05:59:14.605450 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5391 05:59:14.609127 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5392 05:59:14.612156 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5393 05:59:14.619064 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5394 05:59:14.622101 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5395 05:59:14.625542 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5396 05:59:14.628892 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5397 05:59:14.632203 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5398 05:59:14.638520 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5399 05:59:14.641878 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5400 05:59:14.645069 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5401 05:59:14.648312 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5402 05:59:14.648424 ==
5403 05:59:14.651650 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 05:59:14.658345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 05:59:14.658470 ==
5406 05:59:14.658573 DQS Delay:
5407 05:59:14.661923 DQS0 = 0, DQS1 = 0
5408 05:59:14.662007 DQM Delay:
5409 05:59:14.662074 DQM0 = 91, DQM1 = 81
5410 05:59:14.665374 DQ Delay:
5411 05:59:14.668689 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5412 05:59:14.671860 DQ4 =91, DQ5 =75, DQ6 =107, DQ7 =103
5413 05:59:14.675236 DQ8 =75, DQ9 =63, DQ10 =87, DQ11 =71
5414 05:59:14.678373 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5415 05:59:14.678453
5416 05:59:14.678517
5417 05:59:14.678577 ==
5418 05:59:14.681719 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 05:59:14.685205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 05:59:14.685280 ==
5421 05:59:14.685343
5422 05:59:14.685402
5423 05:59:14.688253 TX Vref Scan disable
5424 05:59:14.688337 == TX Byte 0 ==
5425 05:59:14.694781 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5426 05:59:14.698016 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5427 05:59:14.701458 == TX Byte 1 ==
5428 05:59:14.704967 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5429 05:59:14.707923 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5430 05:59:14.708031 ==
5431 05:59:14.711668 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 05:59:14.715209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 05:59:14.715308 ==
5434 05:59:14.718124
5435 05:59:14.718213
5436 05:59:14.718281 TX Vref Scan disable
5437 05:59:14.721214 == TX Byte 0 ==
5438 05:59:14.724736 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5439 05:59:14.731388 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5440 05:59:14.731473 == TX Byte 1 ==
5441 05:59:14.734884 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5442 05:59:14.741053 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5443 05:59:14.741140
5444 05:59:14.741208 [DATLAT]
5445 05:59:14.741271 Freq=933, CH0 RK1
5446 05:59:14.741332
5447 05:59:14.744642 DATLAT Default: 0xb
5448 05:59:14.744777 0, 0xFFFF, sum = 0
5449 05:59:14.747646 1, 0xFFFF, sum = 0
5450 05:59:14.751053 2, 0xFFFF, sum = 0
5451 05:59:14.751138 3, 0xFFFF, sum = 0
5452 05:59:14.754274 4, 0xFFFF, sum = 0
5453 05:59:14.754362 5, 0xFFFF, sum = 0
5454 05:59:14.757855 6, 0xFFFF, sum = 0
5455 05:59:14.757959 7, 0xFFFF, sum = 0
5456 05:59:14.761022 8, 0xFFFF, sum = 0
5457 05:59:14.761107 9, 0xFFFF, sum = 0
5458 05:59:14.764435 10, 0x0, sum = 1
5459 05:59:14.764553 11, 0x0, sum = 2
5460 05:59:14.767456 12, 0x0, sum = 3
5461 05:59:14.767546 13, 0x0, sum = 4
5462 05:59:14.767613 best_step = 11
5463 05:59:14.771148
5464 05:59:14.771279 ==
5465 05:59:14.773923 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 05:59:14.777349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 05:59:14.777467 ==
5468 05:59:14.777573 RX Vref Scan: 0
5469 05:59:14.780429
5470 05:59:14.780539 RX Vref 0 -> 0, step: 1
5471 05:59:14.780635
5472 05:59:14.783823 RX Delay -77 -> 252, step: 4
5473 05:59:14.790567 iDelay=199, Bit 0, Center 90 (-1 ~ 182) 184
5474 05:59:14.793815 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5475 05:59:14.797134 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5476 05:59:14.800494 iDelay=199, Bit 3, Center 90 (-5 ~ 186) 192
5477 05:59:14.804037 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5478 05:59:14.810005 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5479 05:59:14.813220 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5480 05:59:14.816588 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5481 05:59:14.820333 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5482 05:59:14.823223 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5483 05:59:14.829828 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5484 05:59:14.833300 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5485 05:59:14.836482 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5486 05:59:14.840199 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5487 05:59:14.843592 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5488 05:59:14.850008 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5489 05:59:14.850108 ==
5490 05:59:14.853113 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 05:59:14.856692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 05:59:14.856776 ==
5493 05:59:14.856845 DQS Delay:
5494 05:59:14.859731 DQS0 = 0, DQS1 = 0
5495 05:59:14.859814 DQM Delay:
5496 05:59:14.863069 DQM0 = 93, DQM1 = 83
5497 05:59:14.863152 DQ Delay:
5498 05:59:14.866298 DQ0 =90, DQ1 =94, DQ2 =90, DQ3 =90
5499 05:59:14.869783 DQ4 =92, DQ5 =82, DQ6 =106, DQ7 =104
5500 05:59:14.872936 DQ8 =76, DQ9 =66, DQ10 =86, DQ11 =76
5501 05:59:14.876263 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5502 05:59:14.876347
5503 05:59:14.876415
5504 05:59:14.885969 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5505 05:59:14.886054 CH0 RK1: MR19=505, MR18=2E10
5506 05:59:14.892841 CH0_RK1: MR19=0x505, MR18=0x2E10, DQSOSC=407, MR23=63, INC=65, DEC=43
5507 05:59:14.895963 [RxdqsGatingPostProcess] freq 933
5508 05:59:14.902821 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5509 05:59:14.905628 best DQS0 dly(2T, 0.5T) = (0, 10)
5510 05:59:14.908893 best DQS1 dly(2T, 0.5T) = (0, 11)
5511 05:59:14.912324 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5512 05:59:14.915535 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5513 05:59:14.915653 best DQS0 dly(2T, 0.5T) = (0, 10)
5514 05:59:14.918921 best DQS1 dly(2T, 0.5T) = (0, 11)
5515 05:59:14.922578 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5516 05:59:14.925579 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5517 05:59:14.929199 Pre-setting of DQS Precalculation
5518 05:59:14.935689 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5519 05:59:14.935803 ==
5520 05:59:14.938596 Dram Type= 6, Freq= 0, CH_1, rank 0
5521 05:59:14.942319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 05:59:14.942406 ==
5523 05:59:14.948822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5524 05:59:14.955542 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5525 05:59:14.958588 [CA 0] Center 36 (7~66) winsize 60
5526 05:59:14.961577 [CA 1] Center 37 (7~68) winsize 62
5527 05:59:14.965120 [CA 2] Center 34 (5~64) winsize 60
5528 05:59:14.968216 [CA 3] Center 34 (5~64) winsize 60
5529 05:59:14.971871 [CA 4] Center 34 (5~64) winsize 60
5530 05:59:14.975127 [CA 5] Center 33 (4~63) winsize 60
5531 05:59:14.975250
5532 05:59:14.978271 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5533 05:59:14.978367
5534 05:59:14.981756 [CATrainingPosCal] consider 1 rank data
5535 05:59:14.984750 u2DelayCellTimex100 = 270/100 ps
5536 05:59:14.988016 CA0 delay=36 (7~66),Diff = 3 PI (18 cell)
5537 05:59:14.991422 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5538 05:59:14.994859 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5539 05:59:14.998435 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5540 05:59:15.001325 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5541 05:59:15.005021 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5542 05:59:15.005104
5543 05:59:15.011331 CA PerBit enable=1, Macro0, CA PI delay=33
5544 05:59:15.011416
5545 05:59:15.014645 [CBTSetCACLKResult] CA Dly = 33
5546 05:59:15.014728 CS Dly: 6 (0~37)
5547 05:59:15.014795 ==
5548 05:59:15.018092 Dram Type= 6, Freq= 0, CH_1, rank 1
5549 05:59:15.021513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 05:59:15.021598 ==
5551 05:59:15.028334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5552 05:59:15.034855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5553 05:59:15.037951 [CA 0] Center 38 (8~68) winsize 61
5554 05:59:15.041641 [CA 1] Center 38 (8~68) winsize 61
5555 05:59:15.044678 [CA 2] Center 35 (6~65) winsize 60
5556 05:59:15.047726 [CA 3] Center 34 (4~64) winsize 61
5557 05:59:15.051238 [CA 4] Center 35 (5~65) winsize 61
5558 05:59:15.054326 [CA 5] Center 34 (4~64) winsize 61
5559 05:59:15.054435
5560 05:59:15.057793 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5561 05:59:15.057882
5562 05:59:15.061287 [CATrainingPosCal] consider 2 rank data
5563 05:59:15.064562 u2DelayCellTimex100 = 270/100 ps
5564 05:59:15.067510 CA0 delay=37 (8~66),Diff = 4 PI (24 cell)
5565 05:59:15.071246 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5566 05:59:15.074679 CA2 delay=35 (6~64),Diff = 2 PI (12 cell)
5567 05:59:15.077782 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5568 05:59:15.084345 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5569 05:59:15.087672 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5570 05:59:15.087802
5571 05:59:15.090913 CA PerBit enable=1, Macro0, CA PI delay=33
5572 05:59:15.091005
5573 05:59:15.094040 [CBTSetCACLKResult] CA Dly = 33
5574 05:59:15.094123 CS Dly: 7 (0~39)
5575 05:59:15.094190
5576 05:59:15.097268 ----->DramcWriteLeveling(PI) begin...
5577 05:59:15.097386 ==
5578 05:59:15.100995 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 05:59:15.107536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 05:59:15.107670 ==
5581 05:59:15.110989 Write leveling (Byte 0): 26 => 26
5582 05:59:15.114002 Write leveling (Byte 1): 29 => 29
5583 05:59:15.114098 DramcWriteLeveling(PI) end<-----
5584 05:59:15.114183
5585 05:59:15.117343 ==
5586 05:59:15.120804 Dram Type= 6, Freq= 0, CH_1, rank 0
5587 05:59:15.123719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5588 05:59:15.123829 ==
5589 05:59:15.127116 [Gating] SW mode calibration
5590 05:59:15.133943 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5591 05:59:15.136786 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5592 05:59:15.143463 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5593 05:59:15.147064 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 05:59:15.150720 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 05:59:15.157317 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 05:59:15.160326 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 05:59:15.163981 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 05:59:15.170232 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 05:59:15.173436 0 14 28 | B1->B0 | 3131 3030 | 0 0 | (0 1) (0 1)
5600 05:59:15.177077 0 15 0 | B1->B0 | 2727 2929 | 0 0 | (0 0) (0 0)
5601 05:59:15.183727 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 05:59:15.186686 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 05:59:15.189878 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 05:59:15.197001 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 05:59:15.200317 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 05:59:15.203242 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 05:59:15.210119 0 15 28 | B1->B0 | 2d2d 2e2e | 0 0 | (0 0) (0 0)
5608 05:59:15.213413 1 0 0 | B1->B0 | 4444 4545 | 1 1 | (0 0) (0 0)
5609 05:59:15.216720 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 05:59:15.223317 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 05:59:15.226257 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 05:59:15.229462 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 05:59:15.236501 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 05:59:15.239853 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 05:59:15.243019 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5616 05:59:15.249333 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 05:59:15.252996 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 05:59:15.256158 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 05:59:15.262798 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 05:59:15.266303 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 05:59:15.269441 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 05:59:15.275906 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 05:59:15.279313 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 05:59:15.282667 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 05:59:15.289353 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 05:59:15.293018 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 05:59:15.295985 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 05:59:15.302575 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 05:59:15.305828 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 05:59:15.309081 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 05:59:15.312458 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5632 05:59:15.319320 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5633 05:59:15.322738 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 05:59:15.326034 Total UI for P1: 0, mck2ui 16
5635 05:59:15.329030 best dqsien dly found for B0: ( 1, 2, 30)
5636 05:59:15.332640 Total UI for P1: 0, mck2ui 16
5637 05:59:15.335561 best dqsien dly found for B1: ( 1, 2, 30)
5638 05:59:15.338993 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5639 05:59:15.342316 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5640 05:59:15.342425
5641 05:59:15.345755 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5642 05:59:15.352021 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5643 05:59:15.352126 [Gating] SW calibration Done
5644 05:59:15.352233 ==
5645 05:59:15.355657 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 05:59:15.362351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 05:59:15.362439 ==
5648 05:59:15.362541 RX Vref Scan: 0
5649 05:59:15.362640
5650 05:59:15.365331 RX Vref 0 -> 0, step: 1
5651 05:59:15.365434
5652 05:59:15.368962 RX Delay -80 -> 252, step: 8
5653 05:59:15.372012 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5654 05:59:15.375204 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5655 05:59:15.378699 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5656 05:59:15.381822 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5657 05:59:15.388446 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5658 05:59:15.392140 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5659 05:59:15.395037 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5660 05:59:15.398685 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5661 05:59:15.401706 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5662 05:59:15.408375 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5663 05:59:15.411790 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5664 05:59:15.415067 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5665 05:59:15.418223 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5666 05:59:15.421910 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5667 05:59:15.428344 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5668 05:59:15.431762 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5669 05:59:15.431868 ==
5670 05:59:15.435212 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 05:59:15.438175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 05:59:15.438253 ==
5673 05:59:15.438329 DQS Delay:
5674 05:59:15.441838 DQS0 = 0, DQS1 = 0
5675 05:59:15.441932 DQM Delay:
5676 05:59:15.444801 DQM0 = 95, DQM1 = 87
5677 05:59:15.444902 DQ Delay:
5678 05:59:15.448223 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5679 05:59:15.451766 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5680 05:59:15.455100 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5681 05:59:15.458426 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5682 05:59:15.458566
5683 05:59:15.458656
5684 05:59:15.458749 ==
5685 05:59:15.461192 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 05:59:15.467786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 05:59:15.467896 ==
5688 05:59:15.467991
5689 05:59:15.468079
5690 05:59:15.468172 TX Vref Scan disable
5691 05:59:15.471267 == TX Byte 0 ==
5692 05:59:15.474974 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5693 05:59:15.481594 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5694 05:59:15.481695 == TX Byte 1 ==
5695 05:59:15.484603 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5696 05:59:15.491102 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5697 05:59:15.491206 ==
5698 05:59:15.494493 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 05:59:15.497965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 05:59:15.498070 ==
5701 05:59:15.498178
5702 05:59:15.498279
5703 05:59:15.501589 TX Vref Scan disable
5704 05:59:15.501674 == TX Byte 0 ==
5705 05:59:15.507869 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5706 05:59:15.511409 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5707 05:59:15.511509 == TX Byte 1 ==
5708 05:59:15.518010 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5709 05:59:15.521425 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5710 05:59:15.521556
5711 05:59:15.521654 [DATLAT]
5712 05:59:15.524244 Freq=933, CH1 RK0
5713 05:59:15.524340
5714 05:59:15.524432 DATLAT Default: 0xd
5715 05:59:15.527740 0, 0xFFFF, sum = 0
5716 05:59:15.527836 1, 0xFFFF, sum = 0
5717 05:59:15.530986 2, 0xFFFF, sum = 0
5718 05:59:15.531089 3, 0xFFFF, sum = 0
5719 05:59:15.534097 4, 0xFFFF, sum = 0
5720 05:59:15.537892 5, 0xFFFF, sum = 0
5721 05:59:15.537987 6, 0xFFFF, sum = 0
5722 05:59:15.541294 7, 0xFFFF, sum = 0
5723 05:59:15.541401 8, 0xFFFF, sum = 0
5724 05:59:15.544117 9, 0xFFFF, sum = 0
5725 05:59:15.544220 10, 0x0, sum = 1
5726 05:59:15.547822 11, 0x0, sum = 2
5727 05:59:15.547958 12, 0x0, sum = 3
5728 05:59:15.548051 13, 0x0, sum = 4
5729 05:59:15.551251 best_step = 11
5730 05:59:15.551414
5731 05:59:15.551509 ==
5732 05:59:15.554207 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 05:59:15.557782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 05:59:15.557936 ==
5735 05:59:15.560763 RX Vref Scan: 1
5736 05:59:15.560848
5737 05:59:15.560909 RX Vref 0 -> 0, step: 1
5738 05:59:15.564111
5739 05:59:15.564223 RX Delay -61 -> 252, step: 4
5740 05:59:15.564310
5741 05:59:15.567447 Set Vref, RX VrefLevel [Byte0]: 59
5742 05:59:15.571446 [Byte1]: 48
5743 05:59:15.575446
5744 05:59:15.575569 Final RX Vref Byte 0 = 59 to rank0
5745 05:59:15.578372 Final RX Vref Byte 1 = 48 to rank0
5746 05:59:15.582163 Final RX Vref Byte 0 = 59 to rank1
5747 05:59:15.585294 Final RX Vref Byte 1 = 48 to rank1==
5748 05:59:15.588837 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 05:59:15.595506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 05:59:15.595610 ==
5751 05:59:15.595706 DQS Delay:
5752 05:59:15.595810 DQS0 = 0, DQS1 = 0
5753 05:59:15.598341 DQM Delay:
5754 05:59:15.598437 DQM0 = 96, DQM1 = 87
5755 05:59:15.601770 DQ Delay:
5756 05:59:15.605054 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =92
5757 05:59:15.608218 DQ4 =94, DQ5 =108, DQ6 =106, DQ7 =94
5758 05:59:15.612001 DQ8 =74, DQ9 =80, DQ10 =88, DQ11 =82
5759 05:59:15.614934 DQ12 =98, DQ13 =92, DQ14 =92, DQ15 =94
5760 05:59:15.615035
5761 05:59:15.615127
5762 05:59:15.621428 [DQSOSCAuto] RK0, (LSB)MR18= 0xff08, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5763 05:59:15.624983 CH1 RK0: MR19=405, MR18=FF08
5764 05:59:15.631372 CH1_RK0: MR19=0x405, MR18=0xFF08, DQSOSC=419, MR23=63, INC=61, DEC=41
5765 05:59:15.631483
5766 05:59:15.634988 ----->DramcWriteLeveling(PI) begin...
5767 05:59:15.635068 ==
5768 05:59:15.638464 Dram Type= 6, Freq= 0, CH_1, rank 1
5769 05:59:15.641941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 05:59:15.642020 ==
5771 05:59:15.645250 Write leveling (Byte 0): 25 => 25
5772 05:59:15.648562 Write leveling (Byte 1): 26 => 26
5773 05:59:15.651454 DramcWriteLeveling(PI) end<-----
5774 05:59:15.651553
5775 05:59:15.651643 ==
5776 05:59:15.654855 Dram Type= 6, Freq= 0, CH_1, rank 1
5777 05:59:15.657960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 05:59:15.658037 ==
5779 05:59:15.661743 [Gating] SW mode calibration
5780 05:59:15.668321 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5781 05:59:15.674763 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5782 05:59:15.678103 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5783 05:59:15.684868 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 05:59:15.687865 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 05:59:15.691439 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 05:59:15.698126 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 05:59:15.701093 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 05:59:15.704796 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5789 05:59:15.711097 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5790 05:59:15.714411 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 05:59:15.717923 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 05:59:15.724219 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 05:59:15.727623 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 05:59:15.731053 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 05:59:15.737684 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 05:59:15.740901 0 15 24 | B1->B0 | 2828 3838 | 1 0 | (0 0) (1 1)
5797 05:59:15.744214 0 15 28 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
5798 05:59:15.750751 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 05:59:15.754048 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 05:59:15.757104 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 05:59:15.763996 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 05:59:15.767406 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 05:59:15.770278 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 05:59:15.777043 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5805 05:59:15.780176 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5806 05:59:15.783582 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 05:59:15.790009 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 05:59:15.793983 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 05:59:15.796989 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 05:59:15.803478 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 05:59:15.806999 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 05:59:15.810094 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 05:59:15.816639 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 05:59:15.819789 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 05:59:15.823203 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 05:59:15.829888 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 05:59:15.833297 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 05:59:15.836697 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 05:59:15.843256 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5820 05:59:15.846369 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5821 05:59:15.849960 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5822 05:59:15.852825 Total UI for P1: 0, mck2ui 16
5823 05:59:15.856163 best dqsien dly found for B0: ( 1, 2, 22)
5824 05:59:15.859715 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 05:59:15.862806 Total UI for P1: 0, mck2ui 16
5826 05:59:15.866249 best dqsien dly found for B1: ( 1, 2, 28)
5827 05:59:15.872584 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5828 05:59:15.875992 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5829 05:59:15.876104
5830 05:59:15.879669 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5831 05:59:15.882706 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5832 05:59:15.886304 [Gating] SW calibration Done
5833 05:59:15.886411 ==
5834 05:59:15.889283 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 05:59:15.892888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 05:59:15.892987 ==
5837 05:59:15.895758 RX Vref Scan: 0
5838 05:59:15.895856
5839 05:59:15.895953 RX Vref 0 -> 0, step: 1
5840 05:59:15.896042
5841 05:59:15.899174 RX Delay -80 -> 252, step: 8
5842 05:59:15.902394 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5843 05:59:15.909560 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5844 05:59:15.912643 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5845 05:59:15.915670 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5846 05:59:15.919343 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5847 05:59:15.922268 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5848 05:59:15.925703 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5849 05:59:15.932630 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5850 05:59:15.935614 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5851 05:59:15.938975 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5852 05:59:15.942412 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5853 05:59:15.945861 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5854 05:59:15.952473 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5855 05:59:15.955305 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5856 05:59:15.958958 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5857 05:59:15.962336 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5858 05:59:15.962439 ==
5859 05:59:15.965445 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 05:59:15.968600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 05:59:15.972216 ==
5862 05:59:15.972320 DQS Delay:
5863 05:59:15.972419 DQS0 = 0, DQS1 = 0
5864 05:59:15.975378 DQM Delay:
5865 05:59:15.975487 DQM0 = 93, DQM1 = 87
5866 05:59:15.978890 DQ Delay:
5867 05:59:15.978991 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5868 05:59:15.981958 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5869 05:59:15.985437 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5870 05:59:15.988539 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5871 05:59:15.992068
5872 05:59:15.992175
5873 05:59:15.992268 ==
5874 05:59:15.995254 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 05:59:15.998399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 05:59:15.998507 ==
5877 05:59:15.998601
5878 05:59:15.998694
5879 05:59:16.002078 TX Vref Scan disable
5880 05:59:16.002191 == TX Byte 0 ==
5881 05:59:16.008302 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5882 05:59:16.012241 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5883 05:59:16.012361 == TX Byte 1 ==
5884 05:59:16.018532 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5885 05:59:16.021724 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5886 05:59:16.021804 ==
5887 05:59:16.025262 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 05:59:16.028387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 05:59:16.028486 ==
5890 05:59:16.028580
5891 05:59:16.028671
5892 05:59:16.031711 TX Vref Scan disable
5893 05:59:16.035118 == TX Byte 0 ==
5894 05:59:16.038428 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5895 05:59:16.041687 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5896 05:59:16.044770 == TX Byte 1 ==
5897 05:59:16.048426 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5898 05:59:16.051622 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5899 05:59:16.051725
5900 05:59:16.054626 [DATLAT]
5901 05:59:16.054732 Freq=933, CH1 RK1
5902 05:59:16.054831
5903 05:59:16.058289 DATLAT Default: 0xb
5904 05:59:16.058391 0, 0xFFFF, sum = 0
5905 05:59:16.061247 1, 0xFFFF, sum = 0
5906 05:59:16.061348 2, 0xFFFF, sum = 0
5907 05:59:16.064900 3, 0xFFFF, sum = 0
5908 05:59:16.065007 4, 0xFFFF, sum = 0
5909 05:59:16.067892 5, 0xFFFF, sum = 0
5910 05:59:16.068024 6, 0xFFFF, sum = 0
5911 05:59:16.071426 7, 0xFFFF, sum = 0
5912 05:59:16.071538 8, 0xFFFF, sum = 0
5913 05:59:16.074998 9, 0xFFFF, sum = 0
5914 05:59:16.075120 10, 0x0, sum = 1
5915 05:59:16.078055 11, 0x0, sum = 2
5916 05:59:16.078165 12, 0x0, sum = 3
5917 05:59:16.081093 13, 0x0, sum = 4
5918 05:59:16.081213 best_step = 11
5919 05:59:16.081321
5920 05:59:16.081418 ==
5921 05:59:16.084638 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 05:59:16.091210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 05:59:16.091320 ==
5924 05:59:16.091421 RX Vref Scan: 0
5925 05:59:16.091512
5926 05:59:16.094365 RX Vref 0 -> 0, step: 1
5927 05:59:16.094470
5928 05:59:16.097762 RX Delay -69 -> 252, step: 4
5929 05:59:16.101019 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5930 05:59:16.107874 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5931 05:59:16.110835 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5932 05:59:16.117195 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5933 05:59:16.117551 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5934 05:59:16.121060 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5935 05:59:16.124546 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5936 05:59:16.130847 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5937 05:59:16.134202 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5938 05:59:16.137487 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5939 05:59:16.140925 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5940 05:59:16.144255 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5941 05:59:16.150943 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5942 05:59:16.154294 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5943 05:59:16.157329 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5944 05:59:16.160959 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5945 05:59:16.161069 ==
5946 05:59:16.163849 Dram Type= 6, Freq= 0, CH_1, rank 1
5947 05:59:16.167569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5948 05:59:16.167692 ==
5949 05:59:16.170510 DQS Delay:
5950 05:59:16.170628 DQS0 = 0, DQS1 = 0
5951 05:59:16.174030 DQM Delay:
5952 05:59:16.174109 DQM0 = 92, DQM1 = 90
5953 05:59:16.177382 DQ Delay:
5954 05:59:16.177492 DQ0 =96, DQ1 =88, DQ2 =82, DQ3 =88
5955 05:59:16.180619 DQ4 =88, DQ5 =102, DQ6 =104, DQ7 =88
5956 05:59:16.183847 DQ8 =78, DQ9 =82, DQ10 =94, DQ11 =82
5957 05:59:16.187413 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =96
5958 05:59:16.190390
5959 05:59:16.190491
5960 05:59:16.197308 [DQSOSCAuto] RK1, (LSB)MR18= 0xb1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5961 05:59:16.200681 CH1 RK1: MR19=505, MR18=B1E
5962 05:59:16.207482 CH1_RK1: MR19=0x505, MR18=0xB1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5963 05:59:16.207588 [RxdqsGatingPostProcess] freq 933
5964 05:59:16.213432 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5965 05:59:16.217115 best DQS0 dly(2T, 0.5T) = (0, 10)
5966 05:59:16.220210 best DQS1 dly(2T, 0.5T) = (0, 10)
5967 05:59:16.223697 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5968 05:59:16.227324 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5969 05:59:16.230229 best DQS0 dly(2T, 0.5T) = (0, 10)
5970 05:59:16.233673 best DQS1 dly(2T, 0.5T) = (0, 10)
5971 05:59:16.236762 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5972 05:59:16.240368 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5973 05:59:16.243417 Pre-setting of DQS Precalculation
5974 05:59:16.246983 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5975 05:59:16.253366 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5976 05:59:16.263309 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5977 05:59:16.263421
5978 05:59:16.263516
5979 05:59:16.263609 [Calibration Summary] 1866 Mbps
5980 05:59:16.266421 CH 0, Rank 0
5981 05:59:16.269846 SW Impedance : PASS
5982 05:59:16.269950 DUTY Scan : NO K
5983 05:59:16.273314 ZQ Calibration : PASS
5984 05:59:16.273429 Jitter Meter : NO K
5985 05:59:16.276356 CBT Training : PASS
5986 05:59:16.280159 Write leveling : PASS
5987 05:59:16.280263 RX DQS gating : PASS
5988 05:59:16.282926 RX DQ/DQS(RDDQC) : PASS
5989 05:59:16.286241 TX DQ/DQS : PASS
5990 05:59:16.286354 RX DATLAT : PASS
5991 05:59:16.289532 RX DQ/DQS(Engine): PASS
5992 05:59:16.292784 TX OE : NO K
5993 05:59:16.292888 All Pass.
5994 05:59:16.292984
5995 05:59:16.293077 CH 0, Rank 1
5996 05:59:16.296217 SW Impedance : PASS
5997 05:59:16.299928 DUTY Scan : NO K
5998 05:59:16.300035 ZQ Calibration : PASS
5999 05:59:16.302906 Jitter Meter : NO K
6000 05:59:16.306590 CBT Training : PASS
6001 05:59:16.306688 Write leveling : PASS
6002 05:59:16.309433 RX DQS gating : PASS
6003 05:59:16.313168 RX DQ/DQS(RDDQC) : PASS
6004 05:59:16.313290 TX DQ/DQS : PASS
6005 05:59:16.316251 RX DATLAT : PASS
6006 05:59:16.319581 RX DQ/DQS(Engine): PASS
6007 05:59:16.319694 TX OE : NO K
6008 05:59:16.322739 All Pass.
6009 05:59:16.322856
6010 05:59:16.322930 CH 1, Rank 0
6011 05:59:16.326268 SW Impedance : PASS
6012 05:59:16.326376 DUTY Scan : NO K
6013 05:59:16.329221 ZQ Calibration : PASS
6014 05:59:16.332513 Jitter Meter : NO K
6015 05:59:16.332632 CBT Training : PASS
6016 05:59:16.335878 Write leveling : PASS
6017 05:59:16.338966 RX DQS gating : PASS
6018 05:59:16.339045 RX DQ/DQS(RDDQC) : PASS
6019 05:59:16.342746 TX DQ/DQS : PASS
6020 05:59:16.342842 RX DATLAT : PASS
6021 05:59:16.345678 RX DQ/DQS(Engine): PASS
6022 05:59:16.349322 TX OE : NO K
6023 05:59:16.349428 All Pass.
6024 05:59:16.349525
6025 05:59:16.349593 CH 1, Rank 1
6026 05:59:16.352334 SW Impedance : PASS
6027 05:59:16.356035 DUTY Scan : NO K
6028 05:59:16.356134 ZQ Calibration : PASS
6029 05:59:16.358879 Jitter Meter : NO K
6030 05:59:16.362405 CBT Training : PASS
6031 05:59:16.362486 Write leveling : PASS
6032 05:59:16.365728 RX DQS gating : PASS
6033 05:59:16.368993 RX DQ/DQS(RDDQC) : PASS
6034 05:59:16.369094 TX DQ/DQS : PASS
6035 05:59:16.372381 RX DATLAT : PASS
6036 05:59:16.375587 RX DQ/DQS(Engine): PASS
6037 05:59:16.375686 TX OE : NO K
6038 05:59:16.378733 All Pass.
6039 05:59:16.378807
6040 05:59:16.378870 DramC Write-DBI off
6041 05:59:16.382296 PER_BANK_REFRESH: Hybrid Mode
6042 05:59:16.382398 TX_TRACKING: ON
6043 05:59:16.392219 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6044 05:59:16.395600 [FAST_K] Save calibration result to emmc
6045 05:59:16.398958 dramc_set_vcore_voltage set vcore to 650000
6046 05:59:16.402173 Read voltage for 400, 6
6047 05:59:16.402287 Vio18 = 0
6048 05:59:16.405190 Vcore = 650000
6049 05:59:16.405300 Vdram = 0
6050 05:59:16.405392 Vddq = 0
6051 05:59:16.408808 Vmddr = 0
6052 05:59:16.411811 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6053 05:59:16.418819 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6054 05:59:16.418930 MEM_TYPE=3, freq_sel=20
6055 05:59:16.421868 sv_algorithm_assistance_LP4_800
6056 05:59:16.428502 ============ PULL DRAM RESETB DOWN ============
6057 05:59:16.432177 ========== PULL DRAM RESETB DOWN end =========
6058 05:59:16.435218 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6059 05:59:16.438595 ===================================
6060 05:59:16.441684 LPDDR4 DRAM CONFIGURATION
6061 05:59:16.445371 ===================================
6062 05:59:16.445481 EX_ROW_EN[0] = 0x0
6063 05:59:16.448371 EX_ROW_EN[1] = 0x0
6064 05:59:16.451778 LP4Y_EN = 0x0
6065 05:59:16.451891 WORK_FSP = 0x0
6066 05:59:16.454918 WL = 0x2
6067 05:59:16.455016 RL = 0x2
6068 05:59:16.458458 BL = 0x2
6069 05:59:16.458554 RPST = 0x0
6070 05:59:16.461455 RD_PRE = 0x0
6071 05:59:16.461555 WR_PRE = 0x1
6072 05:59:16.465059 WR_PST = 0x0
6073 05:59:16.465170 DBI_WR = 0x0
6074 05:59:16.468738 DBI_RD = 0x0
6075 05:59:16.468841 OTF = 0x1
6076 05:59:16.471605 ===================================
6077 05:59:16.474788 ===================================
6078 05:59:16.478222 ANA top config
6079 05:59:16.481866 ===================================
6080 05:59:16.481968 DLL_ASYNC_EN = 0
6081 05:59:16.484904 ALL_SLAVE_EN = 1
6082 05:59:16.488187 NEW_RANK_MODE = 1
6083 05:59:16.491671 DLL_IDLE_MODE = 1
6084 05:59:16.494721 LP45_APHY_COMB_EN = 1
6085 05:59:16.494800 TX_ODT_DIS = 1
6086 05:59:16.498225 NEW_8X_MODE = 1
6087 05:59:16.501725 ===================================
6088 05:59:16.504666 ===================================
6089 05:59:16.507933 data_rate = 800
6090 05:59:16.511235 CKR = 1
6091 05:59:16.514965 DQ_P2S_RATIO = 4
6092 05:59:16.517802 ===================================
6093 05:59:16.521321 CA_P2S_RATIO = 4
6094 05:59:16.521423 DQ_CA_OPEN = 0
6095 05:59:16.524836 DQ_SEMI_OPEN = 1
6096 05:59:16.527831 CA_SEMI_OPEN = 1
6097 05:59:16.531390 CA_FULL_RATE = 0
6098 05:59:16.534916 DQ_CKDIV4_EN = 0
6099 05:59:16.535022 CA_CKDIV4_EN = 1
6100 05:59:16.538048 CA_PREDIV_EN = 0
6101 05:59:16.541643 PH8_DLY = 0
6102 05:59:16.544653 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6103 05:59:16.548284 DQ_AAMCK_DIV = 0
6104 05:59:16.551381 CA_AAMCK_DIV = 0
6105 05:59:16.551485 CA_ADMCK_DIV = 4
6106 05:59:16.554323 DQ_TRACK_CA_EN = 0
6107 05:59:16.558070 CA_PICK = 800
6108 05:59:16.561294 CA_MCKIO = 400
6109 05:59:16.564746 MCKIO_SEMI = 400
6110 05:59:16.567926 PLL_FREQ = 3016
6111 05:59:16.571004 DQ_UI_PI_RATIO = 32
6112 05:59:16.574737 CA_UI_PI_RATIO = 32
6113 05:59:16.577858 ===================================
6114 05:59:16.581209 ===================================
6115 05:59:16.581314 memory_type:LPDDR4
6116 05:59:16.584222 GP_NUM : 10
6117 05:59:16.587550 SRAM_EN : 1
6118 05:59:16.587628 MD32_EN : 0
6119 05:59:16.591346 ===================================
6120 05:59:16.594326 [ANA_INIT] >>>>>>>>>>>>>>
6121 05:59:16.597540 <<<<<< [CONFIGURE PHASE]: ANA_TX
6122 05:59:16.600997 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6123 05:59:16.604184 ===================================
6124 05:59:16.607422 data_rate = 800,PCW = 0X7400
6125 05:59:16.610707 ===================================
6126 05:59:16.614229 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6127 05:59:16.617466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6128 05:59:16.630638 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6129 05:59:16.634219 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6130 05:59:16.637770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6131 05:59:16.640664 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6132 05:59:16.644312 [ANA_INIT] flow start
6133 05:59:16.644389 [ANA_INIT] PLL >>>>>>>>
6134 05:59:16.647481 [ANA_INIT] PLL <<<<<<<<
6135 05:59:16.651040 [ANA_INIT] MIDPI >>>>>>>>
6136 05:59:16.653999 [ANA_INIT] MIDPI <<<<<<<<
6137 05:59:16.654080 [ANA_INIT] DLL >>>>>>>>
6138 05:59:16.657600 [ANA_INIT] flow end
6139 05:59:16.660706 ============ LP4 DIFF to SE enter ============
6140 05:59:16.663773 ============ LP4 DIFF to SE exit ============
6141 05:59:16.667369 [ANA_INIT] <<<<<<<<<<<<<
6142 05:59:16.670454 [Flow] Enable top DCM control >>>>>
6143 05:59:16.674120 [Flow] Enable top DCM control <<<<<
6144 05:59:16.677248 Enable DLL master slave shuffle
6145 05:59:16.683872 ==============================================================
6146 05:59:16.683978 Gating Mode config
6147 05:59:16.690162 ==============================================================
6148 05:59:16.690241 Config description:
6149 05:59:16.700274 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6150 05:59:16.707090 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6151 05:59:16.713184 SELPH_MODE 0: By rank 1: By Phase
6152 05:59:16.716831 ==============================================================
6153 05:59:16.720172 GAT_TRACK_EN = 0
6154 05:59:16.723315 RX_GATING_MODE = 2
6155 05:59:16.726698 RX_GATING_TRACK_MODE = 2
6156 05:59:16.730072 SELPH_MODE = 1
6157 05:59:16.733314 PICG_EARLY_EN = 1
6158 05:59:16.736605 VALID_LAT_VALUE = 1
6159 05:59:16.743180 ==============================================================
6160 05:59:16.746659 Enter into Gating configuration >>>>
6161 05:59:16.750024 Exit from Gating configuration <<<<
6162 05:59:16.753159 Enter into DVFS_PRE_config >>>>>
6163 05:59:16.763249 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6164 05:59:16.766223 Exit from DVFS_PRE_config <<<<<
6165 05:59:16.769384 Enter into PICG configuration >>>>
6166 05:59:16.773109 Exit from PICG configuration <<<<
6167 05:59:16.776047 [RX_INPUT] configuration >>>>>
6168 05:59:16.776150 [RX_INPUT] configuration <<<<<
6169 05:59:16.782730 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6170 05:59:16.789377 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6171 05:59:16.792522 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6172 05:59:16.799013 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6173 05:59:16.805788 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6174 05:59:16.812572 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6175 05:59:16.816128 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6176 05:59:16.819188 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6177 05:59:16.825979 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6178 05:59:16.828925 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6179 05:59:16.832311 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6180 05:59:16.839001 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6181 05:59:16.842557 ===================================
6182 05:59:16.842667 LPDDR4 DRAM CONFIGURATION
6183 05:59:16.845911 ===================================
6184 05:59:16.849329 EX_ROW_EN[0] = 0x0
6185 05:59:16.849431 EX_ROW_EN[1] = 0x0
6186 05:59:16.852321 LP4Y_EN = 0x0
6187 05:59:16.855907 WORK_FSP = 0x0
6188 05:59:16.855983 WL = 0x2
6189 05:59:16.858826 RL = 0x2
6190 05:59:16.858897 BL = 0x2
6191 05:59:16.862491 RPST = 0x0
6192 05:59:16.862570 RD_PRE = 0x0
6193 05:59:16.865366 WR_PRE = 0x1
6194 05:59:16.865484 WR_PST = 0x0
6195 05:59:16.868741 DBI_WR = 0x0
6196 05:59:16.868854 DBI_RD = 0x0
6197 05:59:16.872204 OTF = 0x1
6198 05:59:16.875763 ===================================
6199 05:59:16.878707 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6200 05:59:16.882440 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6201 05:59:16.889012 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6202 05:59:16.892061 ===================================
6203 05:59:16.892175 LPDDR4 DRAM CONFIGURATION
6204 05:59:16.895756 ===================================
6205 05:59:16.898833 EX_ROW_EN[0] = 0x10
6206 05:59:16.898943 EX_ROW_EN[1] = 0x0
6207 05:59:16.902070 LP4Y_EN = 0x0
6208 05:59:16.902164 WORK_FSP = 0x0
6209 05:59:16.905196 WL = 0x2
6210 05:59:16.908616 RL = 0x2
6211 05:59:16.908749 BL = 0x2
6212 05:59:16.911644 RPST = 0x0
6213 05:59:16.911738 RD_PRE = 0x0
6214 05:59:16.915440 WR_PRE = 0x1
6215 05:59:16.915552 WR_PST = 0x0
6216 05:59:16.918382 DBI_WR = 0x0
6217 05:59:16.918465 DBI_RD = 0x0
6218 05:59:16.921551 OTF = 0x1
6219 05:59:16.925198 ===================================
6220 05:59:16.931910 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6221 05:59:16.934828 nWR fixed to 30
6222 05:59:16.935004 [ModeRegInit_LP4] CH0 RK0
6223 05:59:16.938490 [ModeRegInit_LP4] CH0 RK1
6224 05:59:16.941644 [ModeRegInit_LP4] CH1 RK0
6225 05:59:16.944612 [ModeRegInit_LP4] CH1 RK1
6226 05:59:16.944718 match AC timing 19
6227 05:59:16.948277 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6228 05:59:16.955041 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6229 05:59:16.958374 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6230 05:59:16.961268 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6231 05:59:16.968312 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6232 05:59:16.968398 ==
6233 05:59:16.971659 Dram Type= 6, Freq= 0, CH_0, rank 0
6234 05:59:16.974792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6235 05:59:16.974877 ==
6236 05:59:16.981645 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6237 05:59:16.987712 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6238 05:59:16.991557 [CA 0] Center 36 (8~64) winsize 57
6239 05:59:16.991641 [CA 1] Center 36 (8~64) winsize 57
6240 05:59:16.994674 [CA 2] Center 36 (8~64) winsize 57
6241 05:59:16.997826 [CA 3] Center 36 (8~64) winsize 57
6242 05:59:17.001560 [CA 4] Center 36 (8~64) winsize 57
6243 05:59:17.004560 [CA 5] Center 36 (8~64) winsize 57
6244 05:59:17.004642
6245 05:59:17.008181 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6246 05:59:17.008264
6247 05:59:17.011145 [CATrainingPosCal] consider 1 rank data
6248 05:59:17.014761 u2DelayCellTimex100 = 270/100 ps
6249 05:59:17.017728 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 05:59:17.021298 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 05:59:17.028099 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 05:59:17.031040 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 05:59:17.034176 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 05:59:17.037701 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 05:59:17.037784
6256 05:59:17.041388 CA PerBit enable=1, Macro0, CA PI delay=36
6257 05:59:17.041502
6258 05:59:17.044345 [CBTSetCACLKResult] CA Dly = 36
6259 05:59:17.044427 CS Dly: 1 (0~32)
6260 05:59:17.047439 ==
6261 05:59:17.047522 Dram Type= 6, Freq= 0, CH_0, rank 1
6262 05:59:17.054566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 05:59:17.054681 ==
6264 05:59:17.057921 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6265 05:59:17.064309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6266 05:59:17.067805 [CA 0] Center 36 (8~64) winsize 57
6267 05:59:17.070877 [CA 1] Center 36 (8~64) winsize 57
6268 05:59:17.074626 [CA 2] Center 36 (8~64) winsize 57
6269 05:59:17.077557 [CA 3] Center 36 (8~64) winsize 57
6270 05:59:17.080968 [CA 4] Center 36 (8~64) winsize 57
6271 05:59:17.084328 [CA 5] Center 36 (8~64) winsize 57
6272 05:59:17.084428
6273 05:59:17.087521 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6274 05:59:17.087604
6275 05:59:17.090891 [CATrainingPosCal] consider 2 rank data
6276 05:59:17.094382 u2DelayCellTimex100 = 270/100 ps
6277 05:59:17.097629 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 05:59:17.100833 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 05:59:17.104193 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 05:59:17.107685 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 05:59:17.113717 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 05:59:17.117320 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 05:59:17.117427
6284 05:59:17.120368 CA PerBit enable=1, Macro0, CA PI delay=36
6285 05:59:17.120469
6286 05:59:17.123676 [CBTSetCACLKResult] CA Dly = 36
6287 05:59:17.123775 CS Dly: 1 (0~32)
6288 05:59:17.123865
6289 05:59:17.127257 ----->DramcWriteLeveling(PI) begin...
6290 05:59:17.127330 ==
6291 05:59:17.130470 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 05:59:17.137098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 05:59:17.137209 ==
6294 05:59:17.140191 Write leveling (Byte 0): 40 => 8
6295 05:59:17.140293 Write leveling (Byte 1): 40 => 8
6296 05:59:17.143733 DramcWriteLeveling(PI) end<-----
6297 05:59:17.143823
6298 05:59:17.146850 ==
6299 05:59:17.146952 Dram Type= 6, Freq= 0, CH_0, rank 0
6300 05:59:17.153565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 05:59:17.153668 ==
6302 05:59:17.157116 [Gating] SW mode calibration
6303 05:59:17.163375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6304 05:59:17.166972 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6305 05:59:17.173509 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6306 05:59:17.176951 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6307 05:59:17.180234 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 05:59:17.186381 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6309 05:59:17.190153 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 05:59:17.193282 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 05:59:17.199893 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 05:59:17.203488 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 05:59:17.206340 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6314 05:59:17.210096 Total UI for P1: 0, mck2ui 16
6315 05:59:17.213218 best dqsien dly found for B0: ( 0, 14, 24)
6316 05:59:17.216105 Total UI for P1: 0, mck2ui 16
6317 05:59:17.219517 best dqsien dly found for B1: ( 0, 14, 24)
6318 05:59:17.222782 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6319 05:59:17.226195 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6320 05:59:17.226301
6321 05:59:17.233017 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6322 05:59:17.235951 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6323 05:59:17.239489 [Gating] SW calibration Done
6324 05:59:17.239611 ==
6325 05:59:17.242532 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 05:59:17.246233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 05:59:17.246315 ==
6328 05:59:17.246380 RX Vref Scan: 0
6329 05:59:17.246440
6330 05:59:17.249825 RX Vref 0 -> 0, step: 1
6331 05:59:17.249908
6332 05:59:17.252899 RX Delay -410 -> 252, step: 16
6333 05:59:17.255942 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6334 05:59:17.262816 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6335 05:59:17.265894 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6336 05:59:17.269465 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6337 05:59:17.272790 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6338 05:59:17.279116 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6339 05:59:17.282676 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6340 05:59:17.286069 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6341 05:59:17.288959 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6342 05:59:17.295822 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6343 05:59:17.299342 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6344 05:59:17.302483 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6345 05:59:17.306238 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6346 05:59:17.312635 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6347 05:59:17.315670 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6348 05:59:17.319297 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6349 05:59:17.319404 ==
6350 05:59:17.322367 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 05:59:17.326062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 05:59:17.329005 ==
6353 05:59:17.329123 DQS Delay:
6354 05:59:17.329222 DQS0 = 59, DQS1 = 59
6355 05:59:17.332415 DQM Delay:
6356 05:59:17.332517 DQM0 = 18, DQM1 = 10
6357 05:59:17.335886 DQ Delay:
6358 05:59:17.339020 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6359 05:59:17.342204 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6360 05:59:17.342314 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6361 05:59:17.345796 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6362 05:59:17.345898
6363 05:59:17.348658
6364 05:59:17.348754 ==
6365 05:59:17.352355 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 05:59:17.355421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 05:59:17.355527 ==
6368 05:59:17.355618
6369 05:59:17.355704
6370 05:59:17.359223 TX Vref Scan disable
6371 05:59:17.359326 == TX Byte 0 ==
6372 05:59:17.362300 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 05:59:17.368609 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 05:59:17.368718 == TX Byte 1 ==
6375 05:59:17.372306 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 05:59:17.379054 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 05:59:17.379184 ==
6378 05:59:17.382290 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 05:59:17.385199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 05:59:17.385299 ==
6381 05:59:17.385390
6382 05:59:17.385485
6383 05:59:17.388931 TX Vref Scan disable
6384 05:59:17.389040 == TX Byte 0 ==
6385 05:59:17.391669 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 05:59:17.398765 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 05:59:17.398873 == TX Byte 1 ==
6388 05:59:17.401750 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 05:59:17.408602 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 05:59:17.408719
6391 05:59:17.408812 [DATLAT]
6392 05:59:17.408901 Freq=400, CH0 RK0
6393 05:59:17.411627
6394 05:59:17.411750 DATLAT Default: 0xf
6395 05:59:17.415232 0, 0xFFFF, sum = 0
6396 05:59:17.415341 1, 0xFFFF, sum = 0
6397 05:59:17.418231 2, 0xFFFF, sum = 0
6398 05:59:17.418343 3, 0xFFFF, sum = 0
6399 05:59:17.421995 4, 0xFFFF, sum = 0
6400 05:59:17.422080 5, 0xFFFF, sum = 0
6401 05:59:17.425220 6, 0xFFFF, sum = 0
6402 05:59:17.425335 7, 0xFFFF, sum = 0
6403 05:59:17.428423 8, 0xFFFF, sum = 0
6404 05:59:17.428553 9, 0xFFFF, sum = 0
6405 05:59:17.431700 10, 0xFFFF, sum = 0
6406 05:59:17.431810 11, 0xFFFF, sum = 0
6407 05:59:17.435519 12, 0xFFFF, sum = 0
6408 05:59:17.435633 13, 0x0, sum = 1
6409 05:59:17.438587 14, 0x0, sum = 2
6410 05:59:17.438671 15, 0x0, sum = 3
6411 05:59:17.441440 16, 0x0, sum = 4
6412 05:59:17.441566 best_step = 14
6413 05:59:17.441660
6414 05:59:17.441750 ==
6415 05:59:17.444675 Dram Type= 6, Freq= 0, CH_0, rank 0
6416 05:59:17.451650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 05:59:17.451761 ==
6418 05:59:17.451829 RX Vref Scan: 1
6419 05:59:17.451891
6420 05:59:17.455071 RX Vref 0 -> 0, step: 1
6421 05:59:17.455141
6422 05:59:17.457944 RX Delay -359 -> 252, step: 8
6423 05:59:17.458032
6424 05:59:17.461841 Set Vref, RX VrefLevel [Byte0]: 61
6425 05:59:17.464820 [Byte1]: 47
6426 05:59:17.464928
6427 05:59:17.468069 Final RX Vref Byte 0 = 61 to rank0
6428 05:59:17.471664 Final RX Vref Byte 1 = 47 to rank0
6429 05:59:17.474713 Final RX Vref Byte 0 = 61 to rank1
6430 05:59:17.478114 Final RX Vref Byte 1 = 47 to rank1==
6431 05:59:17.481753 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 05:59:17.487909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 05:59:17.487987 ==
6434 05:59:17.488051 DQS Delay:
6435 05:59:17.491187 DQS0 = 60, DQS1 = 68
6436 05:59:17.491259 DQM Delay:
6437 05:59:17.491320 DQM0 = 14, DQM1 = 14
6438 05:59:17.494332 DQ Delay:
6439 05:59:17.497935 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6440 05:59:17.501383 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6441 05:59:17.501457 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =12
6442 05:59:17.504315 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6443 05:59:17.507862
6444 05:59:17.507943
6445 05:59:17.514491 [DQSOSCAuto] RK0, (LSB)MR18= 0x8382, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6446 05:59:17.517844 CH0 RK0: MR19=C0C, MR18=8382
6447 05:59:17.524728 CH0_RK0: MR19=0xC0C, MR18=0x8382, DQSOSC=393, MR23=63, INC=382, DEC=254
6448 05:59:17.524807 ==
6449 05:59:17.527781 Dram Type= 6, Freq= 0, CH_0, rank 1
6450 05:59:17.531415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 05:59:17.531504 ==
6452 05:59:17.534669 [Gating] SW mode calibration
6453 05:59:17.541353 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6454 05:59:17.547587 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6455 05:59:17.551000 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6456 05:59:17.554473 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6457 05:59:17.560793 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 05:59:17.564172 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6459 05:59:17.567512 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 05:59:17.574505 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 05:59:17.577665 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 05:59:17.581295 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 05:59:17.588001 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6464 05:59:17.588320 Total UI for P1: 0, mck2ui 16
6465 05:59:17.594215 best dqsien dly found for B0: ( 0, 14, 24)
6466 05:59:17.594589 Total UI for P1: 0, mck2ui 16
6467 05:59:17.597737 best dqsien dly found for B1: ( 0, 14, 24)
6468 05:59:17.604251 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6469 05:59:17.607370 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6470 05:59:17.607701
6471 05:59:17.610916 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6472 05:59:17.613918 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6473 05:59:17.617707 [Gating] SW calibration Done
6474 05:59:17.618082 ==
6475 05:59:17.620806 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 05:59:17.624119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 05:59:17.624514 ==
6478 05:59:17.627329 RX Vref Scan: 0
6479 05:59:17.627736
6480 05:59:17.628154 RX Vref 0 -> 0, step: 1
6481 05:59:17.628536
6482 05:59:17.630770 RX Delay -410 -> 252, step: 16
6483 05:59:17.637210 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6484 05:59:17.640764 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6485 05:59:17.644086 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6486 05:59:17.647031 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6487 05:59:17.653553 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6488 05:59:17.657218 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6489 05:59:17.660941 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6490 05:59:17.663969 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6491 05:59:17.670391 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6492 05:59:17.673736 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6493 05:59:17.676811 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6494 05:59:17.680170 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6495 05:59:17.686783 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6496 05:59:17.690529 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6497 05:59:17.693513 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6498 05:59:17.697064 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6499 05:59:17.700162 ==
6500 05:59:17.703659 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 05:59:17.706675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 05:59:17.707136 ==
6503 05:59:17.707499 DQS Delay:
6504 05:59:17.710245 DQS0 = 59, DQS1 = 59
6505 05:59:17.710759 DQM Delay:
6506 05:59:17.713460 DQM0 = 16, DQM1 = 10
6507 05:59:17.713813 DQ Delay:
6508 05:59:17.716536 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6509 05:59:17.720115 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6510 05:59:17.723138 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6511 05:59:17.726554 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6512 05:59:17.726869
6513 05:59:17.727122
6514 05:59:17.727356 ==
6515 05:59:17.730236 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 05:59:17.733235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 05:59:17.733576 ==
6518 05:59:17.733833
6519 05:59:17.734070
6520 05:59:17.736219 TX Vref Scan disable
6521 05:59:17.736533 == TX Byte 0 ==
6522 05:59:17.742979 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6523 05:59:17.746095 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6524 05:59:17.746420 == TX Byte 1 ==
6525 05:59:17.753070 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6526 05:59:17.756413 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6527 05:59:17.756766 ==
6528 05:59:17.759672 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 05:59:17.762831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 05:59:17.763158 ==
6531 05:59:17.763468
6532 05:59:17.763724
6533 05:59:17.766569 TX Vref Scan disable
6534 05:59:17.769449 == TX Byte 0 ==
6535 05:59:17.773118 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6536 05:59:17.776205 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6537 05:59:17.776533 == TX Byte 1 ==
6538 05:59:17.782971 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6539 05:59:17.785935 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6540 05:59:17.786016
6541 05:59:17.786081 [DATLAT]
6542 05:59:17.789097 Freq=400, CH0 RK1
6543 05:59:17.789203
6544 05:59:17.789296 DATLAT Default: 0xe
6545 05:59:17.792499 0, 0xFFFF, sum = 0
6546 05:59:17.792581 1, 0xFFFF, sum = 0
6547 05:59:17.796126 2, 0xFFFF, sum = 0
6548 05:59:17.796206 3, 0xFFFF, sum = 0
6549 05:59:17.799025 4, 0xFFFF, sum = 0
6550 05:59:17.799099 5, 0xFFFF, sum = 0
6551 05:59:17.802740 6, 0xFFFF, sum = 0
6552 05:59:17.805770 7, 0xFFFF, sum = 0
6553 05:59:17.805854 8, 0xFFFF, sum = 0
6554 05:59:17.808845 9, 0xFFFF, sum = 0
6555 05:59:17.808948 10, 0xFFFF, sum = 0
6556 05:59:17.812566 11, 0xFFFF, sum = 0
6557 05:59:17.812645 12, 0xFFFF, sum = 0
6558 05:59:17.815784 13, 0x0, sum = 1
6559 05:59:17.815864 14, 0x0, sum = 2
6560 05:59:17.818984 15, 0x0, sum = 3
6561 05:59:17.819096 16, 0x0, sum = 4
6562 05:59:17.822559 best_step = 14
6563 05:59:17.822643
6564 05:59:17.822714 ==
6565 05:59:17.825632 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 05:59:17.829126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 05:59:17.829218 ==
6568 05:59:17.829294 RX Vref Scan: 0
6569 05:59:17.829368
6570 05:59:17.832007 RX Vref 0 -> 0, step: 1
6571 05:59:17.832114
6572 05:59:17.835618 RX Delay -359 -> 252, step: 8
6573 05:59:17.842766 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6574 05:59:17.846336 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6575 05:59:17.849505 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6576 05:59:17.853206 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6577 05:59:17.859678 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6578 05:59:17.862615 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6579 05:59:17.866173 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6580 05:59:17.869384 iDelay=217, Bit 7, Center -40 (-295 ~ 216) 512
6581 05:59:17.876407 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6582 05:59:17.879386 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6583 05:59:17.882333 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6584 05:59:17.889121 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6585 05:59:17.892411 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6586 05:59:17.896096 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6587 05:59:17.899066 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6588 05:59:17.905468 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6589 05:59:17.905637 ==
6590 05:59:17.909220 Dram Type= 6, Freq= 0, CH_0, rank 1
6591 05:59:17.912643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 05:59:17.912726 ==
6593 05:59:17.912791 DQS Delay:
6594 05:59:17.915645 DQS0 = 60, DQS1 = 72
6595 05:59:17.915773 DQM Delay:
6596 05:59:17.919133 DQM0 = 11, DQM1 = 17
6597 05:59:17.919215 DQ Delay:
6598 05:59:17.922267 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6599 05:59:17.925892 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6600 05:59:17.929055 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6601 05:59:17.932115 DQ12 =24, DQ13 =28, DQ14 =24, DQ15 =24
6602 05:59:17.932196
6603 05:59:17.932302
6604 05:59:17.939349 [DQSOSCAuto] RK1, (LSB)MR18= 0xc57a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6605 05:59:17.942474 CH0 RK1: MR19=C0C, MR18=C57A
6606 05:59:17.949198 CH0_RK1: MR19=0xC0C, MR18=0xC57A, DQSOSC=385, MR23=63, INC=398, DEC=265
6607 05:59:17.952397 [RxdqsGatingPostProcess] freq 400
6608 05:59:17.958998 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6609 05:59:17.961868 best DQS0 dly(2T, 0.5T) = (0, 10)
6610 05:59:17.961951 best DQS1 dly(2T, 0.5T) = (0, 10)
6611 05:59:17.965228 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6612 05:59:17.968808 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6613 05:59:17.971918 best DQS0 dly(2T, 0.5T) = (0, 10)
6614 05:59:17.975552 best DQS1 dly(2T, 0.5T) = (0, 10)
6615 05:59:17.978448 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6616 05:59:17.981720 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6617 05:59:17.985315 Pre-setting of DQS Precalculation
6618 05:59:17.991616 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6619 05:59:17.991739 ==
6620 05:59:17.994852 Dram Type= 6, Freq= 0, CH_1, rank 0
6621 05:59:17.998626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 05:59:17.998707 ==
6623 05:59:18.004751 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6624 05:59:18.008465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6625 05:59:18.011914 [CA 0] Center 36 (8~64) winsize 57
6626 05:59:18.014998 [CA 1] Center 36 (8~64) winsize 57
6627 05:59:18.018024 [CA 2] Center 36 (8~64) winsize 57
6628 05:59:18.021598 [CA 3] Center 36 (8~64) winsize 57
6629 05:59:18.025040 [CA 4] Center 36 (8~64) winsize 57
6630 05:59:18.028335 [CA 5] Center 36 (8~64) winsize 57
6631 05:59:18.028445
6632 05:59:18.031343 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6633 05:59:18.031424
6634 05:59:18.034889 [CATrainingPosCal] consider 1 rank data
6635 05:59:18.038250 u2DelayCellTimex100 = 270/100 ps
6636 05:59:18.041383 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 05:59:18.045100 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 05:59:18.051757 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 05:59:18.054705 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 05:59:18.058485 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 05:59:18.061519 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 05:59:18.061665
6643 05:59:18.064431 CA PerBit enable=1, Macro0, CA PI delay=36
6644 05:59:18.064514
6645 05:59:18.067921 [CBTSetCACLKResult] CA Dly = 36
6646 05:59:18.068002 CS Dly: 1 (0~32)
6647 05:59:18.071543 ==
6648 05:59:18.071624 Dram Type= 6, Freq= 0, CH_1, rank 1
6649 05:59:18.077859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 05:59:18.077940 ==
6651 05:59:18.081341 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6652 05:59:18.087785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6653 05:59:18.091393 [CA 0] Center 36 (8~64) winsize 57
6654 05:59:18.094298 [CA 1] Center 36 (8~64) winsize 57
6655 05:59:18.097946 [CA 2] Center 36 (8~64) winsize 57
6656 05:59:18.101042 [CA 3] Center 36 (8~64) winsize 57
6657 05:59:18.104290 [CA 4] Center 36 (8~64) winsize 57
6658 05:59:18.107940 [CA 5] Center 36 (8~64) winsize 57
6659 05:59:18.108095
6660 05:59:18.111151 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6661 05:59:18.111289
6662 05:59:18.114288 [CATrainingPosCal] consider 2 rank data
6663 05:59:18.117956 u2DelayCellTimex100 = 270/100 ps
6664 05:59:18.121025 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 05:59:18.124187 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 05:59:18.127415 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 05:59:18.131195 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 05:59:18.134479 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 05:59:18.140867 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 05:59:18.140950
6671 05:59:18.144102 CA PerBit enable=1, Macro0, CA PI delay=36
6672 05:59:18.144185
6673 05:59:18.147545 [CBTSetCACLKResult] CA Dly = 36
6674 05:59:18.147662 CS Dly: 1 (0~32)
6675 05:59:18.147760
6676 05:59:18.150895 ----->DramcWriteLeveling(PI) begin...
6677 05:59:18.151007 ==
6678 05:59:18.153923 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 05:59:18.161213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 05:59:18.161297 ==
6681 05:59:18.164186 Write leveling (Byte 0): 40 => 8
6682 05:59:18.164268 Write leveling (Byte 1): 40 => 8
6683 05:59:18.167416 DramcWriteLeveling(PI) end<-----
6684 05:59:18.167499
6685 05:59:18.167565 ==
6686 05:59:18.170676 Dram Type= 6, Freq= 0, CH_1, rank 0
6687 05:59:18.177295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 05:59:18.177380 ==
6689 05:59:18.180855 [Gating] SW mode calibration
6690 05:59:18.187547 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6691 05:59:18.190734 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6692 05:59:18.197244 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6693 05:59:18.200871 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6694 05:59:18.204055 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 05:59:18.210937 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6696 05:59:18.214275 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 05:59:18.217232 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 05:59:18.220930 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 05:59:18.227665 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 05:59:18.230569 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6701 05:59:18.233722 Total UI for P1: 0, mck2ui 16
6702 05:59:18.237073 best dqsien dly found for B0: ( 0, 14, 24)
6703 05:59:18.240951 Total UI for P1: 0, mck2ui 16
6704 05:59:18.243799 best dqsien dly found for B1: ( 0, 14, 24)
6705 05:59:18.246914 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6706 05:59:18.250458 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6707 05:59:18.250580
6708 05:59:18.253986 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6709 05:59:18.260585 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6710 05:59:18.260754 [Gating] SW calibration Done
6711 05:59:18.260874 ==
6712 05:59:18.263566 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 05:59:18.270721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 05:59:18.270966 ==
6715 05:59:18.271163 RX Vref Scan: 0
6716 05:59:18.271350
6717 05:59:18.273673 RX Vref 0 -> 0, step: 1
6718 05:59:18.273845
6719 05:59:18.276953 RX Delay -410 -> 252, step: 16
6720 05:59:18.280074 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6721 05:59:18.283667 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6722 05:59:18.290647 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6723 05:59:18.293721 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6724 05:59:18.296837 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6725 05:59:18.300534 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6726 05:59:18.307108 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6727 05:59:18.310700 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6728 05:59:18.314110 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6729 05:59:18.317153 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6730 05:59:18.323593 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6731 05:59:18.326827 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6732 05:59:18.330558 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6733 05:59:18.333651 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6734 05:59:18.339866 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6735 05:59:18.343672 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6736 05:59:18.343909 ==
6737 05:59:18.346698 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 05:59:18.350072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 05:59:18.350307 ==
6740 05:59:18.353623 DQS Delay:
6741 05:59:18.353848 DQS0 = 51, DQS1 = 67
6742 05:59:18.356676 DQM Delay:
6743 05:59:18.356900 DQM0 = 13, DQM1 = 16
6744 05:59:18.357111 DQ Delay:
6745 05:59:18.359895 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6746 05:59:18.363351 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6747 05:59:18.366819 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6748 05:59:18.370045 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6749 05:59:18.370282
6750 05:59:18.370494
6751 05:59:18.370689 ==
6752 05:59:18.373352 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 05:59:18.379617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 05:59:18.379790 ==
6755 05:59:18.379928
6756 05:59:18.380055
6757 05:59:18.380178 TX Vref Scan disable
6758 05:59:18.383021 == TX Byte 0 ==
6759 05:59:18.386752 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 05:59:18.389528 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 05:59:18.393308 == TX Byte 1 ==
6762 05:59:18.396460 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 05:59:18.399906 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 05:59:18.400094 ==
6765 05:59:18.403219 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 05:59:18.409730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 05:59:18.409904 ==
6768 05:59:18.410046
6769 05:59:18.410175
6770 05:59:18.410296 TX Vref Scan disable
6771 05:59:18.413018 == TX Byte 0 ==
6772 05:59:18.416203 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 05:59:18.419497 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 05:59:18.422753 == TX Byte 1 ==
6775 05:59:18.426523 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 05:59:18.429960 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 05:59:18.430204
6778 05:59:18.433164 [DATLAT]
6779 05:59:18.433496 Freq=400, CH1 RK0
6780 05:59:18.433722
6781 05:59:18.436673 DATLAT Default: 0xf
6782 05:59:18.436969 0, 0xFFFF, sum = 0
6783 05:59:18.439863 1, 0xFFFF, sum = 0
6784 05:59:18.440248 2, 0xFFFF, sum = 0
6785 05:59:18.443314 3, 0xFFFF, sum = 0
6786 05:59:18.443703 4, 0xFFFF, sum = 0
6787 05:59:18.446380 5, 0xFFFF, sum = 0
6788 05:59:18.446951 6, 0xFFFF, sum = 0
6789 05:59:18.449874 7, 0xFFFF, sum = 0
6790 05:59:18.453518 8, 0xFFFF, sum = 0
6791 05:59:18.454094 9, 0xFFFF, sum = 0
6792 05:59:18.456390 10, 0xFFFF, sum = 0
6793 05:59:18.456950 11, 0xFFFF, sum = 0
6794 05:59:18.460117 12, 0xFFFF, sum = 0
6795 05:59:18.460742 13, 0x0, sum = 1
6796 05:59:18.463173 14, 0x0, sum = 2
6797 05:59:18.463667 15, 0x0, sum = 3
6798 05:59:18.466287 16, 0x0, sum = 4
6799 05:59:18.466787 best_step = 14
6800 05:59:18.467156
6801 05:59:18.467500 ==
6802 05:59:18.469424 Dram Type= 6, Freq= 0, CH_1, rank 0
6803 05:59:18.472824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 05:59:18.473286 ==
6805 05:59:18.476266 RX Vref Scan: 1
6806 05:59:18.476838
6807 05:59:18.479558 RX Vref 0 -> 0, step: 1
6808 05:59:18.480015
6809 05:59:18.480380 RX Delay -375 -> 252, step: 8
6810 05:59:18.482527
6811 05:59:18.483049 Set Vref, RX VrefLevel [Byte0]: 59
6812 05:59:18.485722 [Byte1]: 48
6813 05:59:18.491802
6814 05:59:18.492258 Final RX Vref Byte 0 = 59 to rank0
6815 05:59:18.495363 Final RX Vref Byte 1 = 48 to rank0
6816 05:59:18.498513 Final RX Vref Byte 0 = 59 to rank1
6817 05:59:18.501590 Final RX Vref Byte 1 = 48 to rank1==
6818 05:59:18.504686 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 05:59:18.511236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 05:59:18.511996 ==
6821 05:59:18.512684 DQS Delay:
6822 05:59:18.514442 DQS0 = 56, DQS1 = 68
6823 05:59:18.515057 DQM Delay:
6824 05:59:18.515621 DQM0 = 12, DQM1 = 14
6825 05:59:18.517724 DQ Delay:
6826 05:59:18.521429 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6827 05:59:18.524706 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6828 05:59:18.525164 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6829 05:59:18.528184 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6830 05:59:18.531437
6831 05:59:18.531961
6832 05:59:18.538071 [DQSOSCAuto] RK0, (LSB)MR18= 0x5669, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6833 05:59:18.541101 CH1 RK0: MR19=C0C, MR18=5669
6834 05:59:18.547652 CH1_RK0: MR19=0xC0C, MR18=0x5669, DQSOSC=396, MR23=63, INC=376, DEC=251
6835 05:59:18.548265 ==
6836 05:59:18.551003 Dram Type= 6, Freq= 0, CH_1, rank 1
6837 05:59:18.554555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 05:59:18.555150 ==
6839 05:59:18.557625 [Gating] SW mode calibration
6840 05:59:18.564277 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6841 05:59:18.570841 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6842 05:59:18.574401 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6843 05:59:18.577654 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6844 05:59:18.584190 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 05:59:18.587672 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6846 05:59:18.591039 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 05:59:18.597329 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 05:59:18.600574 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 05:59:18.604032 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 05:59:18.610660 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6851 05:59:18.611253 Total UI for P1: 0, mck2ui 16
6852 05:59:18.617279 best dqsien dly found for B0: ( 0, 14, 24)
6853 05:59:18.617735 Total UI for P1: 0, mck2ui 16
6854 05:59:18.620717 best dqsien dly found for B1: ( 0, 14, 24)
6855 05:59:18.627236 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6856 05:59:18.631164 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6857 05:59:18.631619
6858 05:59:18.633843 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6859 05:59:18.637397 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6860 05:59:18.640831 [Gating] SW calibration Done
6861 05:59:18.641248 ==
6862 05:59:18.643803 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 05:59:18.647215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 05:59:18.647633 ==
6865 05:59:18.650750 RX Vref Scan: 0
6866 05:59:18.651163
6867 05:59:18.651510 RX Vref 0 -> 0, step: 1
6868 05:59:18.651823
6869 05:59:18.653712 RX Delay -410 -> 252, step: 16
6870 05:59:18.660203 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6871 05:59:18.663881 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6872 05:59:18.667384 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6873 05:59:18.670442 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6874 05:59:18.676800 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6875 05:59:18.679912 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6876 05:59:18.683401 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6877 05:59:18.686844 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6878 05:59:18.693677 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6879 05:59:18.696568 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6880 05:59:18.700038 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6881 05:59:18.703326 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6882 05:59:18.710162 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6883 05:59:18.713272 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6884 05:59:18.716746 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6885 05:59:18.722876 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6886 05:59:18.723337 ==
6887 05:59:18.726560 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 05:59:18.730173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 05:59:18.730636 ==
6890 05:59:18.731002 DQS Delay:
6891 05:59:18.733198 DQS0 = 59, DQS1 = 59
6892 05:59:18.733694 DQM Delay:
6893 05:59:18.736756 DQM0 = 19, DQM1 = 12
6894 05:59:18.737212 DQ Delay:
6895 05:59:18.739360 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6896 05:59:18.742939 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6897 05:59:18.746194 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6898 05:59:18.749633 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6899 05:59:18.750093
6900 05:59:18.750460
6901 05:59:18.750800 ==
6902 05:59:18.752912 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 05:59:18.755848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 05:59:18.756269 ==
6905 05:59:18.756830
6906 05:59:18.757198
6907 05:59:18.759174 TX Vref Scan disable
6908 05:59:18.763074 == TX Byte 0 ==
6909 05:59:18.765859 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6910 05:59:18.769593 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6911 05:59:18.772540 == TX Byte 1 ==
6912 05:59:18.776090 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6913 05:59:18.779990 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6914 05:59:18.780560 ==
6915 05:59:18.782796 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 05:59:18.785844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 05:59:18.786307 ==
6918 05:59:18.786673
6919 05:59:18.789465
6920 05:59:18.790065 TX Vref Scan disable
6921 05:59:18.792313 == TX Byte 0 ==
6922 05:59:18.795882 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6923 05:59:18.798917 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6924 05:59:18.802466 == TX Byte 1 ==
6925 05:59:18.805462 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6926 05:59:18.809135 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6927 05:59:18.809739
6928 05:59:18.810115 [DATLAT]
6929 05:59:18.812389 Freq=400, CH1 RK1
6930 05:59:18.812850
6931 05:59:18.815835 DATLAT Default: 0xe
6932 05:59:18.816294 0, 0xFFFF, sum = 0
6933 05:59:18.819242 1, 0xFFFF, sum = 0
6934 05:59:18.819707 2, 0xFFFF, sum = 0
6935 05:59:18.822527 3, 0xFFFF, sum = 0
6936 05:59:18.823019 4, 0xFFFF, sum = 0
6937 05:59:18.825684 5, 0xFFFF, sum = 0
6938 05:59:18.826154 6, 0xFFFF, sum = 0
6939 05:59:18.828776 7, 0xFFFF, sum = 0
6940 05:59:18.829241 8, 0xFFFF, sum = 0
6941 05:59:18.832325 9, 0xFFFF, sum = 0
6942 05:59:18.832803 10, 0xFFFF, sum = 0
6943 05:59:18.835770 11, 0xFFFF, sum = 0
6944 05:59:18.836358 12, 0xFFFF, sum = 0
6945 05:59:18.839109 13, 0x0, sum = 1
6946 05:59:18.839590 14, 0x0, sum = 2
6947 05:59:18.842353 15, 0x0, sum = 3
6948 05:59:18.842976 16, 0x0, sum = 4
6949 05:59:18.845319 best_step = 14
6950 05:59:18.845826
6951 05:59:18.846217 ==
6952 05:59:18.849020 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 05:59:18.851901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 05:59:18.852363 ==
6955 05:59:18.855149 RX Vref Scan: 0
6956 05:59:18.855609
6957 05:59:18.855980 RX Vref 0 -> 0, step: 1
6958 05:59:18.856324
6959 05:59:18.858773 RX Delay -359 -> 252, step: 8
6960 05:59:18.866446 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6961 05:59:18.869719 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6962 05:59:18.873183 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6963 05:59:18.876102 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6964 05:59:18.883392 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6965 05:59:18.886323 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6966 05:59:18.889532 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6967 05:59:18.893055 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6968 05:59:18.899379 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6969 05:59:18.903242 iDelay=217, Bit 9, Center -60 (-319 ~ 200) 520
6970 05:59:18.905985 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6971 05:59:18.909600 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6972 05:59:18.916198 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6973 05:59:18.919517 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6974 05:59:18.922891 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6975 05:59:18.929754 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6976 05:59:18.930295 ==
6977 05:59:18.932463 Dram Type= 6, Freq= 0, CH_1, rank 1
6978 05:59:18.936054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 05:59:18.936624 ==
6980 05:59:18.936995 DQS Delay:
6981 05:59:18.939458 DQS0 = 60, DQS1 = 64
6982 05:59:18.939916 DQM Delay:
6983 05:59:18.942789 DQM0 = 13, DQM1 = 11
6984 05:59:18.943247 DQ Delay:
6985 05:59:18.946025 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6986 05:59:18.949045 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6987 05:59:18.952433 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6988 05:59:18.956020 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6989 05:59:18.956481
6990 05:59:18.956847
6991 05:59:18.962103 [DQSOSCAuto] RK1, (LSB)MR18= 0x75a6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6992 05:59:18.965967 CH1 RK1: MR19=C0C, MR18=75A6
6993 05:59:18.972339 CH1_RK1: MR19=0xC0C, MR18=0x75A6, DQSOSC=389, MR23=63, INC=390, DEC=260
6994 05:59:18.976116 [RxdqsGatingPostProcess] freq 400
6995 05:59:18.982516 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6996 05:59:18.985378 best DQS0 dly(2T, 0.5T) = (0, 10)
6997 05:59:18.989404 best DQS1 dly(2T, 0.5T) = (0, 10)
6998 05:59:18.990025 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6999 05:59:18.992906 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7000 05:59:18.995734 best DQS0 dly(2T, 0.5T) = (0, 10)
7001 05:59:18.998843 best DQS1 dly(2T, 0.5T) = (0, 10)
7002 05:59:19.002358 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7003 05:59:19.005375 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7004 05:59:19.008851 Pre-setting of DQS Precalculation
7005 05:59:19.015716 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7006 05:59:19.022387 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7007 05:59:19.028376 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7008 05:59:19.028867
7009 05:59:19.029269
7010 05:59:19.032362 [Calibration Summary] 800 Mbps
7011 05:59:19.032912 CH 0, Rank 0
7012 05:59:19.035895 SW Impedance : PASS
7013 05:59:19.038628 DUTY Scan : NO K
7014 05:59:19.039209 ZQ Calibration : PASS
7015 05:59:19.042214 Jitter Meter : NO K
7016 05:59:19.044878 CBT Training : PASS
7017 05:59:19.045340 Write leveling : PASS
7018 05:59:19.048248 RX DQS gating : PASS
7019 05:59:19.051968 RX DQ/DQS(RDDQC) : PASS
7020 05:59:19.052457 TX DQ/DQS : PASS
7021 05:59:19.055051 RX DATLAT : PASS
7022 05:59:19.058339 RX DQ/DQS(Engine): PASS
7023 05:59:19.058783 TX OE : NO K
7024 05:59:19.059116 All Pass.
7025 05:59:19.062099
7026 05:59:19.062619 CH 0, Rank 1
7027 05:59:19.065114 SW Impedance : PASS
7028 05:59:19.065628 DUTY Scan : NO K
7029 05:59:19.068531 ZQ Calibration : PASS
7030 05:59:19.071565 Jitter Meter : NO K
7031 05:59:19.071995 CBT Training : PASS
7032 05:59:19.074817 Write leveling : NO K
7033 05:59:19.075335 RX DQS gating : PASS
7034 05:59:19.078349 RX DQ/DQS(RDDQC) : PASS
7035 05:59:19.081340 TX DQ/DQS : PASS
7036 05:59:19.081804 RX DATLAT : PASS
7037 05:59:19.085034 RX DQ/DQS(Engine): PASS
7038 05:59:19.088463 TX OE : NO K
7039 05:59:19.088975 All Pass.
7040 05:59:19.089316
7041 05:59:19.089694 CH 1, Rank 0
7042 05:59:19.091491 SW Impedance : PASS
7043 05:59:19.094588 DUTY Scan : NO K
7044 05:59:19.095006 ZQ Calibration : PASS
7045 05:59:19.098336 Jitter Meter : NO K
7046 05:59:19.101659 CBT Training : PASS
7047 05:59:19.102176 Write leveling : PASS
7048 05:59:19.105046 RX DQS gating : PASS
7049 05:59:19.107771 RX DQ/DQS(RDDQC) : PASS
7050 05:59:19.108193 TX DQ/DQS : PASS
7051 05:59:19.111250 RX DATLAT : PASS
7052 05:59:19.114357 RX DQ/DQS(Engine): PASS
7053 05:59:19.114774 TX OE : NO K
7054 05:59:19.117961 All Pass.
7055 05:59:19.118418
7056 05:59:19.118782 CH 1, Rank 1
7057 05:59:19.121412 SW Impedance : PASS
7058 05:59:19.122004 DUTY Scan : NO K
7059 05:59:19.124495 ZQ Calibration : PASS
7060 05:59:19.127751 Jitter Meter : NO K
7061 05:59:19.128260 CBT Training : PASS
7062 05:59:19.131320 Write leveling : NO K
7063 05:59:19.131878 RX DQS gating : PASS
7064 05:59:19.134912 RX DQ/DQS(RDDQC) : PASS
7065 05:59:19.137473 TX DQ/DQS : PASS
7066 05:59:19.138067 RX DATLAT : PASS
7067 05:59:19.141073 RX DQ/DQS(Engine): PASS
7068 05:59:19.144055 TX OE : NO K
7069 05:59:19.144556 All Pass.
7070 05:59:19.144933
7071 05:59:19.147744 DramC Write-DBI off
7072 05:59:19.148203 PER_BANK_REFRESH: Hybrid Mode
7073 05:59:19.150874 TX_TRACKING: ON
7074 05:59:19.161186 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7075 05:59:19.164251 [FAST_K] Save calibration result to emmc
7076 05:59:19.167663 dramc_set_vcore_voltage set vcore to 725000
7077 05:59:19.168153 Read voltage for 1600, 0
7078 05:59:19.170641 Vio18 = 0
7079 05:59:19.171102 Vcore = 725000
7080 05:59:19.171465 Vdram = 0
7081 05:59:19.174122 Vddq = 0
7082 05:59:19.174615 Vmddr = 0
7083 05:59:19.180625 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7084 05:59:19.183823 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7085 05:59:19.187246 MEM_TYPE=3, freq_sel=13
7086 05:59:19.190577 sv_algorithm_assistance_LP4_3733
7087 05:59:19.194128 ============ PULL DRAM RESETB DOWN ============
7088 05:59:19.197561 ========== PULL DRAM RESETB DOWN end =========
7089 05:59:19.204100 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7090 05:59:19.207202 ===================================
7091 05:59:19.207622 LPDDR4 DRAM CONFIGURATION
7092 05:59:19.210635 ===================================
7093 05:59:19.213643 EX_ROW_EN[0] = 0x0
7094 05:59:19.217305 EX_ROW_EN[1] = 0x0
7095 05:59:19.217748 LP4Y_EN = 0x0
7096 05:59:19.220839 WORK_FSP = 0x1
7097 05:59:19.221253 WL = 0x5
7098 05:59:19.223899 RL = 0x5
7099 05:59:19.224319 BL = 0x2
7100 05:59:19.227060 RPST = 0x0
7101 05:59:19.227476 RD_PRE = 0x0
7102 05:59:19.230757 WR_PRE = 0x1
7103 05:59:19.231176 WR_PST = 0x1
7104 05:59:19.233790 DBI_WR = 0x0
7105 05:59:19.234204 DBI_RD = 0x0
7106 05:59:19.237401 OTF = 0x1
7107 05:59:19.240768 ===================================
7108 05:59:19.243599 ===================================
7109 05:59:19.244017 ANA top config
7110 05:59:19.246871 ===================================
7111 05:59:19.250587 DLL_ASYNC_EN = 0
7112 05:59:19.254066 ALL_SLAVE_EN = 0
7113 05:59:19.254484 NEW_RANK_MODE = 1
7114 05:59:19.257056 DLL_IDLE_MODE = 1
7115 05:59:19.260527 LP45_APHY_COMB_EN = 1
7116 05:59:19.263810 TX_ODT_DIS = 0
7117 05:59:19.267235 NEW_8X_MODE = 1
7118 05:59:19.270373 ===================================
7119 05:59:19.273789 ===================================
7120 05:59:19.276489 data_rate = 3200
7121 05:59:19.276907 CKR = 1
7122 05:59:19.280702 DQ_P2S_RATIO = 8
7123 05:59:19.283118 ===================================
7124 05:59:19.286993 CA_P2S_RATIO = 8
7125 05:59:19.289842 DQ_CA_OPEN = 0
7126 05:59:19.293159 DQ_SEMI_OPEN = 0
7127 05:59:19.296837 CA_SEMI_OPEN = 0
7128 05:59:19.297251 CA_FULL_RATE = 0
7129 05:59:19.299603 DQ_CKDIV4_EN = 0
7130 05:59:19.302934 CA_CKDIV4_EN = 0
7131 05:59:19.306770 CA_PREDIV_EN = 0
7132 05:59:19.309778 PH8_DLY = 12
7133 05:59:19.313413 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7134 05:59:19.313968 DQ_AAMCK_DIV = 4
7135 05:59:19.316206 CA_AAMCK_DIV = 4
7136 05:59:19.319822 CA_ADMCK_DIV = 4
7137 05:59:19.323354 DQ_TRACK_CA_EN = 0
7138 05:59:19.326194 CA_PICK = 1600
7139 05:59:19.330082 CA_MCKIO = 1600
7140 05:59:19.333061 MCKIO_SEMI = 0
7141 05:59:19.333538 PLL_FREQ = 3068
7142 05:59:19.336458 DQ_UI_PI_RATIO = 32
7143 05:59:19.339736 CA_UI_PI_RATIO = 0
7144 05:59:19.343341 ===================================
7145 05:59:19.346380 ===================================
7146 05:59:19.349310 memory_type:LPDDR4
7147 05:59:19.352521 GP_NUM : 10
7148 05:59:19.352935 SRAM_EN : 1
7149 05:59:19.356206 MD32_EN : 0
7150 05:59:19.359187 ===================================
7151 05:59:19.359609 [ANA_INIT] >>>>>>>>>>>>>>
7152 05:59:19.363095 <<<<<< [CONFIGURE PHASE]: ANA_TX
7153 05:59:19.366372 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7154 05:59:19.369472 ===================================
7155 05:59:19.372988 data_rate = 3200,PCW = 0X7600
7156 05:59:19.375800 ===================================
7157 05:59:19.379674 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7158 05:59:19.386126 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7159 05:59:19.389467 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7160 05:59:19.395899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7161 05:59:19.399364 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7162 05:59:19.402283 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7163 05:59:19.405458 [ANA_INIT] flow start
7164 05:59:19.406096 [ANA_INIT] PLL >>>>>>>>
7165 05:59:19.409087 [ANA_INIT] PLL <<<<<<<<
7166 05:59:19.412438 [ANA_INIT] MIDPI >>>>>>>>
7167 05:59:19.413009 [ANA_INIT] MIDPI <<<<<<<<
7168 05:59:19.415803 [ANA_INIT] DLL >>>>>>>>
7169 05:59:19.419196 [ANA_INIT] DLL <<<<<<<<
7170 05:59:19.419700 [ANA_INIT] flow end
7171 05:59:19.425576 ============ LP4 DIFF to SE enter ============
7172 05:59:19.428583 ============ LP4 DIFF to SE exit ============
7173 05:59:19.432436 [ANA_INIT] <<<<<<<<<<<<<
7174 05:59:19.435225 [Flow] Enable top DCM control >>>>>
7175 05:59:19.439224 [Flow] Enable top DCM control <<<<<
7176 05:59:19.439608 Enable DLL master slave shuffle
7177 05:59:19.445505 ==============================================================
7178 05:59:19.448529 Gating Mode config
7179 05:59:19.452144 ==============================================================
7180 05:59:19.455161 Config description:
7181 05:59:19.465099 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7182 05:59:19.471557 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7183 05:59:19.475078 SELPH_MODE 0: By rank 1: By Phase
7184 05:59:19.481557 ==============================================================
7185 05:59:19.485169 GAT_TRACK_EN = 1
7186 05:59:19.488070 RX_GATING_MODE = 2
7187 05:59:19.491470 RX_GATING_TRACK_MODE = 2
7188 05:59:19.494997 SELPH_MODE = 1
7189 05:59:19.498025 PICG_EARLY_EN = 1
7190 05:59:19.498405 VALID_LAT_VALUE = 1
7191 05:59:19.504959 ==============================================================
7192 05:59:19.508189 Enter into Gating configuration >>>>
7193 05:59:19.511911 Exit from Gating configuration <<<<
7194 05:59:19.514938 Enter into DVFS_PRE_config >>>>>
7195 05:59:19.525015 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7196 05:59:19.528121 Exit from DVFS_PRE_config <<<<<
7197 05:59:19.531557 Enter into PICG configuration >>>>
7198 05:59:19.534146 Exit from PICG configuration <<<<
7199 05:59:19.538063 [RX_INPUT] configuration >>>>>
7200 05:59:19.541036 [RX_INPUT] configuration <<<<<
7201 05:59:19.547602 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7202 05:59:19.551127 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7203 05:59:19.557843 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7204 05:59:19.564243 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7205 05:59:19.570550 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7206 05:59:19.577170 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7207 05:59:19.580733 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7208 05:59:19.584223 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7209 05:59:19.587421 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7210 05:59:19.594162 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7211 05:59:19.597408 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7212 05:59:19.600888 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7213 05:59:19.603570 ===================================
7214 05:59:19.607207 LPDDR4 DRAM CONFIGURATION
7215 05:59:19.610109 ===================================
7216 05:59:19.610663 EX_ROW_EN[0] = 0x0
7217 05:59:19.613664 EX_ROW_EN[1] = 0x0
7218 05:59:19.617308 LP4Y_EN = 0x0
7219 05:59:19.617867 WORK_FSP = 0x1
7220 05:59:19.620332 WL = 0x5
7221 05:59:19.620787 RL = 0x5
7222 05:59:19.623851 BL = 0x2
7223 05:59:19.624266 RPST = 0x0
7224 05:59:19.626877 RD_PRE = 0x0
7225 05:59:19.627287 WR_PRE = 0x1
7226 05:59:19.629957 WR_PST = 0x1
7227 05:59:19.630367 DBI_WR = 0x0
7228 05:59:19.633281 DBI_RD = 0x0
7229 05:59:19.633728 OTF = 0x1
7230 05:59:19.636611 ===================================
7231 05:59:19.643580 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7232 05:59:19.646475 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7233 05:59:19.649859 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7234 05:59:19.653389 ===================================
7235 05:59:19.656481 LPDDR4 DRAM CONFIGURATION
7236 05:59:19.660216 ===================================
7237 05:59:19.662976 EX_ROW_EN[0] = 0x10
7238 05:59:19.663385 EX_ROW_EN[1] = 0x0
7239 05:59:19.666389 LP4Y_EN = 0x0
7240 05:59:19.666988 WORK_FSP = 0x1
7241 05:59:19.669882 WL = 0x5
7242 05:59:19.670398 RL = 0x5
7243 05:59:19.672838 BL = 0x2
7244 05:59:19.673245 RPST = 0x0
7245 05:59:19.676358 RD_PRE = 0x0
7246 05:59:19.676767 WR_PRE = 0x1
7247 05:59:19.680153 WR_PST = 0x1
7248 05:59:19.680681 DBI_WR = 0x0
7249 05:59:19.683194 DBI_RD = 0x0
7250 05:59:19.683703 OTF = 0x1
7251 05:59:19.686299 ===================================
7252 05:59:19.693280 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7253 05:59:19.693868 ==
7254 05:59:19.696129 Dram Type= 6, Freq= 0, CH_0, rank 0
7255 05:59:19.702940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7256 05:59:19.703356 ==
7257 05:59:19.703777 [Duty_Offset_Calibration]
7258 05:59:19.706149 B0:2 B1:0 CA:3
7259 05:59:19.706564
7260 05:59:19.709530 [DutyScan_Calibration_Flow] k_type=0
7261 05:59:19.718667
7262 05:59:19.719199 ==CLK 0==
7263 05:59:19.722101 Final CLK duty delay cell = 0
7264 05:59:19.725002 [0] MAX Duty = 5031%(X100), DQS PI = 12
7265 05:59:19.728966 [0] MIN Duty = 4907%(X100), DQS PI = 6
7266 05:59:19.729450 [0] AVG Duty = 4969%(X100)
7267 05:59:19.731958
7268 05:59:19.735684 CH0 CLK Duty spec in!! Max-Min= 124%
7269 05:59:19.738617 [DutyScan_Calibration_Flow] ====Done====
7270 05:59:19.739125
7271 05:59:19.741907 [DutyScan_Calibration_Flow] k_type=1
7272 05:59:19.758428
7273 05:59:19.758910 ==DQS 0 ==
7274 05:59:19.762146 Final DQS duty delay cell = 0
7275 05:59:19.765911 [0] MAX Duty = 5125%(X100), DQS PI = 32
7276 05:59:19.769064 [0] MIN Duty = 4875%(X100), DQS PI = 48
7277 05:59:19.771639 [0] AVG Duty = 5000%(X100)
7278 05:59:19.772053
7279 05:59:19.772383 ==DQS 1 ==
7280 05:59:19.774836 Final DQS duty delay cell = 0
7281 05:59:19.778359 [0] MAX Duty = 5156%(X100), DQS PI = 32
7282 05:59:19.781895 [0] MIN Duty = 5031%(X100), DQS PI = 12
7283 05:59:19.784971 [0] AVG Duty = 5093%(X100)
7284 05:59:19.785380
7285 05:59:19.788794 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7286 05:59:19.789309
7287 05:59:19.792092 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7288 05:59:19.795249 [DutyScan_Calibration_Flow] ====Done====
7289 05:59:19.795757
7290 05:59:19.798319 [DutyScan_Calibration_Flow] k_type=3
7291 05:59:19.815591
7292 05:59:19.816090 ==DQM 0 ==
7293 05:59:19.819087 Final DQM duty delay cell = 0
7294 05:59:19.822509 [0] MAX Duty = 5187%(X100), DQS PI = 30
7295 05:59:19.825597 [0] MIN Duty = 4875%(X100), DQS PI = 0
7296 05:59:19.826009 [0] AVG Duty = 5031%(X100)
7297 05:59:19.829262
7298 05:59:19.829728 ==DQM 1 ==
7299 05:59:19.832313 Final DQM duty delay cell = 0
7300 05:59:19.835846 [0] MAX Duty = 4938%(X100), DQS PI = 62
7301 05:59:19.839045 [0] MIN Duty = 4813%(X100), DQS PI = 18
7302 05:59:19.842119 [0] AVG Duty = 4875%(X100)
7303 05:59:19.842627
7304 05:59:19.845580 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7305 05:59:19.845996
7306 05:59:19.849053 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7307 05:59:19.852300 [DutyScan_Calibration_Flow] ====Done====
7308 05:59:19.852712
7309 05:59:19.855286 [DutyScan_Calibration_Flow] k_type=2
7310 05:59:19.872491
7311 05:59:19.873093 ==DQ 0 ==
7312 05:59:19.875700 Final DQ duty delay cell = -4
7313 05:59:19.878451 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7314 05:59:19.881869 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7315 05:59:19.885334 [-4] AVG Duty = 4938%(X100)
7316 05:59:19.885790
7317 05:59:19.886105 ==DQ 1 ==
7318 05:59:19.888339 Final DQ duty delay cell = 0
7319 05:59:19.892023 [0] MAX Duty = 5156%(X100), DQS PI = 58
7320 05:59:19.895464 [0] MIN Duty = 5000%(X100), DQS PI = 16
7321 05:59:19.898420 [0] AVG Duty = 5078%(X100)
7322 05:59:19.898827
7323 05:59:19.902170 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7324 05:59:19.902644
7325 05:59:19.905105 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7326 05:59:19.908833 [DutyScan_Calibration_Flow] ====Done====
7327 05:59:19.909246 ==
7328 05:59:19.911696 Dram Type= 6, Freq= 0, CH_1, rank 0
7329 05:59:19.915315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7330 05:59:19.915728 ==
7331 05:59:19.918772 [Duty_Offset_Calibration]
7332 05:59:19.919179 B0:1 B1:-2 CA:1
7333 05:59:19.919509
7334 05:59:19.921364 [DutyScan_Calibration_Flow] k_type=0
7335 05:59:19.933206
7336 05:59:19.933809 ==CLK 0==
7337 05:59:19.935723 Final CLK duty delay cell = 0
7338 05:59:19.939807 [0] MAX Duty = 5031%(X100), DQS PI = 52
7339 05:59:19.942822 [0] MIN Duty = 4875%(X100), DQS PI = 26
7340 05:59:19.945692 [0] AVG Duty = 4953%(X100)
7341 05:59:19.946312
7342 05:59:19.949129 CH1 CLK Duty spec in!! Max-Min= 156%
7343 05:59:19.952871 [DutyScan_Calibration_Flow] ====Done====
7344 05:59:19.953272
7345 05:59:19.955676 [DutyScan_Calibration_Flow] k_type=1
7346 05:59:19.972705
7347 05:59:19.973199 ==DQS 0 ==
7348 05:59:19.975955 Final DQS duty delay cell = 0
7349 05:59:19.979018 [0] MAX Duty = 5156%(X100), DQS PI = 0
7350 05:59:19.982230 [0] MIN Duty = 5062%(X100), DQS PI = 14
7351 05:59:19.985700 [0] AVG Duty = 5109%(X100)
7352 05:59:19.986286
7353 05:59:19.986728 ==DQS 1 ==
7354 05:59:19.989071 Final DQS duty delay cell = 0
7355 05:59:19.992422 [0] MAX Duty = 5124%(X100), DQS PI = 28
7356 05:59:19.995484 [0] MIN Duty = 4813%(X100), DQS PI = 58
7357 05:59:19.999112 [0] AVG Duty = 4968%(X100)
7358 05:59:19.999717
7359 05:59:20.002434 CH1 DQS 0 Duty spec in!! Max-Min= 94%
7360 05:59:20.002987
7361 05:59:20.005636 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7362 05:59:20.008440 [DutyScan_Calibration_Flow] ====Done====
7363 05:59:20.008974
7364 05:59:20.012198 [DutyScan_Calibration_Flow] k_type=3
7365 05:59:20.028873
7366 05:59:20.029099 ==DQM 0 ==
7367 05:59:20.032040 Final DQM duty delay cell = 0
7368 05:59:20.035702 [0] MAX Duty = 5000%(X100), DQS PI = 0
7369 05:59:20.038792 [0] MIN Duty = 4813%(X100), DQS PI = 28
7370 05:59:20.041787 [0] AVG Duty = 4906%(X100)
7371 05:59:20.041867
7372 05:59:20.041932 ==DQM 1 ==
7373 05:59:20.045602 Final DQM duty delay cell = 0
7374 05:59:20.048703 [0] MAX Duty = 5062%(X100), DQS PI = 4
7375 05:59:20.051690 [0] MIN Duty = 4875%(X100), DQS PI = 38
7376 05:59:20.055213 [0] AVG Duty = 4968%(X100)
7377 05:59:20.055294
7378 05:59:20.058627 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7379 05:59:20.058710
7380 05:59:20.061421 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7381 05:59:20.064880 [DutyScan_Calibration_Flow] ====Done====
7382 05:59:20.064977
7383 05:59:20.068506 [DutyScan_Calibration_Flow] k_type=2
7384 05:59:20.085813
7385 05:59:20.085896 ==DQ 0 ==
7386 05:59:20.089096 Final DQ duty delay cell = 0
7387 05:59:20.091899 [0] MAX Duty = 5093%(X100), DQS PI = 60
7388 05:59:20.095611 [0] MIN Duty = 4938%(X100), DQS PI = 24
7389 05:59:20.095692 [0] AVG Duty = 5015%(X100)
7390 05:59:20.098701
7391 05:59:20.098782 ==DQ 1 ==
7392 05:59:20.101852 Final DQ duty delay cell = 0
7393 05:59:20.105666 [0] MAX Duty = 5156%(X100), DQS PI = 26
7394 05:59:20.109057 [0] MIN Duty = 4938%(X100), DQS PI = 56
7395 05:59:20.109187 [0] AVG Duty = 5047%(X100)
7396 05:59:20.109287
7397 05:59:20.115850 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7398 05:59:20.115942
7399 05:59:20.118752 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7400 05:59:20.121863 [DutyScan_Calibration_Flow] ====Done====
7401 05:59:20.125034 nWR fixed to 30
7402 05:59:20.125130 [ModeRegInit_LP4] CH0 RK0
7403 05:59:20.128761 [ModeRegInit_LP4] CH0 RK1
7404 05:59:20.131692 [ModeRegInit_LP4] CH1 RK0
7405 05:59:20.135093 [ModeRegInit_LP4] CH1 RK1
7406 05:59:20.135176 match AC timing 5
7407 05:59:20.141762 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7408 05:59:20.145333 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7409 05:59:20.148412 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7410 05:59:20.155181 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7411 05:59:20.158249 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7412 05:59:20.158355 [MiockJmeterHQA]
7413 05:59:20.158464
7414 05:59:20.161636 [DramcMiockJmeter] u1RxGatingPI = 0
7415 05:59:20.164940 0 : 4252, 4027
7416 05:59:20.165023 4 : 4253, 4026
7417 05:59:20.168739 8 : 4253, 4026
7418 05:59:20.168821 12 : 4253, 4027
7419 05:59:20.168887 16 : 4252, 4027
7420 05:59:20.171507 20 : 4253, 4026
7421 05:59:20.171589 24 : 4252, 4027
7422 05:59:20.175160 28 : 4363, 4137
7423 05:59:20.175243 32 : 4252, 4027
7424 05:59:20.178132 36 : 4252, 4027
7425 05:59:20.178215 40 : 4254, 4029
7426 05:59:20.182497 44 : 4252, 4027
7427 05:59:20.182580 48 : 4255, 4030
7428 05:59:20.182646 52 : 4363, 4137
7429 05:59:20.185256 56 : 4363, 4138
7430 05:59:20.185336 60 : 4250, 4027
7431 05:59:20.188374 64 : 4255, 4029
7432 05:59:20.188519 68 : 4252, 4027
7433 05:59:20.191620 72 : 4250, 4026
7434 05:59:20.191700 76 : 4250, 4027
7435 05:59:20.191799 80 : 4360, 4137
7436 05:59:20.194878 84 : 4250, 4026
7437 05:59:20.195010 88 : 4250, 4027
7438 05:59:20.198593 92 : 4249, 4027
7439 05:59:20.198681 96 : 4250, 4027
7440 05:59:20.201748 100 : 4249, 4027
7441 05:59:20.201901 104 : 4250, 3706
7442 05:59:20.204773 108 : 4250, 4
7443 05:59:20.204887 112 : 4250, 0
7444 05:59:20.205021 116 : 4363, 0
7445 05:59:20.208436 120 : 4250, 0
7446 05:59:20.208611 124 : 4250, 0
7447 05:59:20.208709 128 : 4249, 0
7448 05:59:20.211830 132 : 4252, 0
7449 05:59:20.212007 136 : 4250, 0
7450 05:59:20.214958 140 : 4250, 0
7451 05:59:20.215071 144 : 4250, 0
7452 05:59:20.215171 148 : 4361, 0
7453 05:59:20.218399 152 : 4360, 0
7454 05:59:20.218537 156 : 4250, 0
7455 05:59:20.221549 160 : 4250, 0
7456 05:59:20.221686 164 : 4250, 0
7457 05:59:20.221784 168 : 4250, 0
7458 05:59:20.224760 172 : 4250, 0
7459 05:59:20.224872 176 : 4250, 0
7460 05:59:20.228241 180 : 4249, 0
7461 05:59:20.228342 184 : 4252, 0
7462 05:59:20.228411 188 : 4250, 0
7463 05:59:20.231383 192 : 4251, 0
7464 05:59:20.231466 196 : 4252, 0
7465 05:59:20.235045 200 : 4361, 0
7466 05:59:20.235129 204 : 4250, 0
7467 05:59:20.235196 208 : 4250, 0
7468 05:59:20.238247 212 : 4250, 0
7469 05:59:20.238331 216 : 4250, 0
7470 05:59:20.238398 220 : 4249, 0
7471 05:59:20.241240 224 : 4250, 0
7472 05:59:20.241324 228 : 4250, 0
7473 05:59:20.244722 232 : 4249, 0
7474 05:59:20.244806 236 : 4250, 1187
7475 05:59:20.247892 240 : 4251, 4027
7476 05:59:20.247975 244 : 4361, 4137
7477 05:59:20.251475 248 : 4251, 4027
7478 05:59:20.251568 252 : 4250, 4026
7479 05:59:20.251637 256 : 4361, 4138
7480 05:59:20.254475 260 : 4251, 4027
7481 05:59:20.254560 264 : 4250, 4027
7482 05:59:20.258121 268 : 4250, 4027
7483 05:59:20.258208 272 : 4250, 4027
7484 05:59:20.261147 276 : 4250, 4027
7485 05:59:20.261263 280 : 4250, 4027
7486 05:59:20.264841 284 : 4360, 4137
7487 05:59:20.264927 288 : 4250, 4027
7488 05:59:20.267694 292 : 4249, 4027
7489 05:59:20.267777 296 : 4360, 4137
7490 05:59:20.271077 300 : 4250, 4027
7491 05:59:20.271161 304 : 4250, 4027
7492 05:59:20.274452 308 : 4361, 4138
7493 05:59:20.274536 312 : 4250, 4027
7494 05:59:20.274602 316 : 4250, 4026
7495 05:59:20.277838 320 : 4250, 4027
7496 05:59:20.277922 324 : 4250, 4027
7497 05:59:20.281062 328 : 4249, 4027
7498 05:59:20.281145 332 : 4250, 4027
7499 05:59:20.284535 336 : 4360, 4137
7500 05:59:20.284619 340 : 4250, 4027
7501 05:59:20.288069 344 : 4250, 4027
7502 05:59:20.288154 348 : 4363, 4140
7503 05:59:20.291240 352 : 4250, 4021
7504 05:59:20.291325 356 : 4250, 2981
7505 05:59:20.294237 360 : 4360, 3
7506 05:59:20.294347
7507 05:59:20.294448 MIOCK jitter meter ch=0
7508 05:59:20.294546
7509 05:59:20.297716 1T = (360-108) = 252 dly cells
7510 05:59:20.304475 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7511 05:59:20.304632 ==
7512 05:59:20.307542 Dram Type= 6, Freq= 0, CH_0, rank 0
7513 05:59:20.311249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7514 05:59:20.311373 ==
7515 05:59:20.317334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7516 05:59:20.321003 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7517 05:59:20.324240 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7518 05:59:20.330798 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7519 05:59:20.340363 [CA 0] Center 43 (13~74) winsize 62
7520 05:59:20.343741 [CA 1] Center 43 (13~74) winsize 62
7521 05:59:20.347264 [CA 2] Center 39 (10~68) winsize 59
7522 05:59:20.350304 [CA 3] Center 39 (10~68) winsize 59
7523 05:59:20.353646 [CA 4] Center 36 (7~66) winsize 60
7524 05:59:20.357360 [CA 5] Center 36 (7~66) winsize 60
7525 05:59:20.357443
7526 05:59:20.360307 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7527 05:59:20.360390
7528 05:59:20.363798 [CATrainingPosCal] consider 1 rank data
7529 05:59:20.366879 u2DelayCellTimex100 = 258/100 ps
7530 05:59:20.373452 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7531 05:59:20.376895 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7532 05:59:20.380470 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7533 05:59:20.383690 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7534 05:59:20.387108 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7535 05:59:20.390602 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7536 05:59:20.390685
7537 05:59:20.393272 CA PerBit enable=1, Macro0, CA PI delay=36
7538 05:59:20.393355
7539 05:59:20.396802 [CBTSetCACLKResult] CA Dly = 36
7540 05:59:20.400470 CS Dly: 11 (0~42)
7541 05:59:20.403545 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7542 05:59:20.406755 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7543 05:59:20.406838 ==
7544 05:59:20.410280 Dram Type= 6, Freq= 0, CH_0, rank 1
7545 05:59:20.416760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 05:59:20.416844 ==
7547 05:59:20.419737 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7548 05:59:20.426539 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7549 05:59:20.429967 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7550 05:59:20.436593 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7551 05:59:20.444305 [CA 0] Center 44 (13~75) winsize 63
7552 05:59:20.447646 [CA 1] Center 43 (13~74) winsize 62
7553 05:59:20.450930 [CA 2] Center 39 (10~69) winsize 60
7554 05:59:20.454493 [CA 3] Center 39 (10~68) winsize 59
7555 05:59:20.457429 [CA 4] Center 37 (8~67) winsize 60
7556 05:59:20.461021 [CA 5] Center 36 (7~66) winsize 60
7557 05:59:20.461102
7558 05:59:20.464175 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7559 05:59:20.464256
7560 05:59:20.470736 [CATrainingPosCal] consider 2 rank data
7561 05:59:20.470818 u2DelayCellTimex100 = 258/100 ps
7562 05:59:20.477377 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7563 05:59:20.481177 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7564 05:59:20.484170 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7565 05:59:20.487616 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7566 05:59:20.490953 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7567 05:59:20.494112 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7568 05:59:20.494193
7569 05:59:20.497137 CA PerBit enable=1, Macro0, CA PI delay=36
7570 05:59:20.497230
7571 05:59:20.500637 [CBTSetCACLKResult] CA Dly = 36
7572 05:59:20.504063 CS Dly: 11 (0~43)
7573 05:59:20.507023 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7574 05:59:20.510659 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7575 05:59:20.510734
7576 05:59:20.513686 ----->DramcWriteLeveling(PI) begin...
7577 05:59:20.517309 ==
7578 05:59:20.517421 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 05:59:20.524025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 05:59:20.524104 ==
7581 05:59:20.527107 Write leveling (Byte 0): 36 => 36
7582 05:59:20.530730 Write leveling (Byte 1): 26 => 26
7583 05:59:20.533676 DramcWriteLeveling(PI) end<-----
7584 05:59:20.533753
7585 05:59:20.533845 ==
7586 05:59:20.537139 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 05:59:20.540691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 05:59:20.540769 ==
7589 05:59:20.543816 [Gating] SW mode calibration
7590 05:59:20.550372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7591 05:59:20.557094 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7592 05:59:20.560070 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 05:59:20.563396 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 05:59:20.567152 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 05:59:20.573349 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 05:59:20.576622 1 4 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7597 05:59:20.579716 1 4 20 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
7598 05:59:20.586556 1 4 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7599 05:59:20.590349 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 05:59:20.593361 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 05:59:20.599889 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 05:59:20.603207 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7603 05:59:20.606891 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7604 05:59:20.613289 1 5 16 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
7605 05:59:20.616699 1 5 20 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
7606 05:59:20.619733 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 1) (0 0)
7607 05:59:20.626929 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7608 05:59:20.629825 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 05:59:20.633538 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 05:59:20.640047 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 05:59:20.643363 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 05:59:20.646337 1 6 16 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
7613 05:59:20.652916 1 6 20 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
7614 05:59:20.656000 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 05:59:20.659715 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 05:59:20.666263 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 05:59:20.669761 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 05:59:20.673020 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 05:59:20.679361 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 05:59:20.683061 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7621 05:59:20.685864 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7622 05:59:20.692660 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7623 05:59:20.696183 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 05:59:20.699685 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 05:59:20.706246 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 05:59:20.709339 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 05:59:20.712790 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 05:59:20.719046 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 05:59:20.722498 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 05:59:20.725947 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 05:59:20.732605 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 05:59:20.735504 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 05:59:20.739193 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 05:59:20.745425 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 05:59:20.748990 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7636 05:59:20.751970 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7637 05:59:20.758872 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7638 05:59:20.758982 Total UI for P1: 0, mck2ui 16
7639 05:59:20.765613 best dqsien dly found for B0: ( 1, 9, 14)
7640 05:59:20.768853 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7641 05:59:20.771803 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 05:59:20.775275 Total UI for P1: 0, mck2ui 16
7643 05:59:20.778670 best dqsien dly found for B1: ( 1, 9, 22)
7644 05:59:20.782056 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7645 05:59:20.785493 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7646 05:59:20.785603
7647 05:59:20.791904 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7648 05:59:20.795342 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7649 05:59:20.795451 [Gating] SW calibration Done
7650 05:59:20.798699 ==
7651 05:59:20.801967 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 05:59:20.805226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 05:59:20.805336 ==
7654 05:59:20.805435 RX Vref Scan: 0
7655 05:59:20.805538
7656 05:59:20.808359 RX Vref 0 -> 0, step: 1
7657 05:59:20.808468
7658 05:59:20.811931 RX Delay 0 -> 252, step: 8
7659 05:59:20.814945 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7660 05:59:20.818604 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7661 05:59:20.821594 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7662 05:59:20.828220 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7663 05:59:20.831821 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7664 05:59:20.835188 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7665 05:59:20.838234 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7666 05:59:20.841803 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7667 05:59:20.848450 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7668 05:59:20.851718 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7669 05:59:20.854620 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7670 05:59:20.857973 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7671 05:59:20.861609 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7672 05:59:20.868277 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7673 05:59:20.871467 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7674 05:59:20.874508 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7675 05:59:20.874619 ==
7676 05:59:20.878153 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 05:59:20.881016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 05:59:20.884704 ==
7679 05:59:20.884813 DQS Delay:
7680 05:59:20.884898 DQS0 = 0, DQS1 = 0
7681 05:59:20.888088 DQM Delay:
7682 05:59:20.888196 DQM0 = 128, DQM1 = 124
7683 05:59:20.891197 DQ Delay:
7684 05:59:20.894642 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7685 05:59:20.897596 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7686 05:59:20.901322 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7687 05:59:20.904303 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7688 05:59:20.904414
7689 05:59:20.904510
7690 05:59:20.904602 ==
7691 05:59:20.907739 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 05:59:20.911216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 05:59:20.911326 ==
7694 05:59:20.911419
7695 05:59:20.914235
7696 05:59:20.914342 TX Vref Scan disable
7697 05:59:20.917507 == TX Byte 0 ==
7698 05:59:20.921000 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7699 05:59:20.924369 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7700 05:59:20.927973 == TX Byte 1 ==
7701 05:59:20.930992 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7702 05:59:20.934138 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7703 05:59:20.934248 ==
7704 05:59:20.937636 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 05:59:20.944069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 05:59:20.944178 ==
7707 05:59:20.958348
7708 05:59:20.961958 TX Vref early break, caculate TX vref
7709 05:59:20.964954 TX Vref=16, minBit 8, minWin=21, winSum=357
7710 05:59:20.968129 TX Vref=18, minBit 11, minWin=21, winSum=369
7711 05:59:20.971703 TX Vref=20, minBit 8, minWin=21, winSum=381
7712 05:59:20.974795 TX Vref=22, minBit 8, minWin=23, winSum=390
7713 05:59:20.977867 TX Vref=24, minBit 8, minWin=23, winSum=400
7714 05:59:20.984517 TX Vref=26, minBit 8, minWin=24, winSum=408
7715 05:59:20.988165 TX Vref=28, minBit 8, minWin=24, winSum=408
7716 05:59:20.991043 TX Vref=30, minBit 8, minWin=23, winSum=402
7717 05:59:20.994544 TX Vref=32, minBit 9, minWin=22, winSum=391
7718 05:59:20.998189 TX Vref=34, minBit 8, minWin=21, winSum=387
7719 05:59:21.004289 TX Vref=36, minBit 8, minWin=21, winSum=372
7720 05:59:21.008034 [TxChooseVref] Worse bit 8, Min win 24, Win sum 408, Final Vref 26
7721 05:59:21.008175
7722 05:59:21.011219 Final TX Range 0 Vref 26
7723 05:59:21.011295
7724 05:59:21.011357 ==
7725 05:59:21.014581 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 05:59:21.017893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 05:59:21.020757 ==
7728 05:59:21.020879
7729 05:59:21.020985
7730 05:59:21.021094 TX Vref Scan disable
7731 05:59:21.027577 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7732 05:59:21.027673 == TX Byte 0 ==
7733 05:59:21.031152 u2DelayCellOfst[0]=11 cells (3 PI)
7734 05:59:21.034150 u2DelayCellOfst[1]=15 cells (4 PI)
7735 05:59:21.037562 u2DelayCellOfst[2]=7 cells (2 PI)
7736 05:59:21.041210 u2DelayCellOfst[3]=11 cells (3 PI)
7737 05:59:21.044390 u2DelayCellOfst[4]=7 cells (2 PI)
7738 05:59:21.047452 u2DelayCellOfst[5]=0 cells (0 PI)
7739 05:59:21.050723 u2DelayCellOfst[6]=15 cells (4 PI)
7740 05:59:21.054072 u2DelayCellOfst[7]=15 cells (4 PI)
7741 05:59:21.057538 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7742 05:59:21.061105 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7743 05:59:21.064147 == TX Byte 1 ==
7744 05:59:21.067244 u2DelayCellOfst[8]=0 cells (0 PI)
7745 05:59:21.070784 u2DelayCellOfst[9]=0 cells (0 PI)
7746 05:59:21.074557 u2DelayCellOfst[10]=7 cells (2 PI)
7747 05:59:21.077528 u2DelayCellOfst[11]=3 cells (1 PI)
7748 05:59:21.080703 u2DelayCellOfst[12]=11 cells (3 PI)
7749 05:59:21.080813 u2DelayCellOfst[13]=11 cells (3 PI)
7750 05:59:21.083830 u2DelayCellOfst[14]=15 cells (4 PI)
7751 05:59:21.087541 u2DelayCellOfst[15]=11 cells (3 PI)
7752 05:59:21.094069 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7753 05:59:21.097435 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7754 05:59:21.097536 DramC Write-DBI on
7755 05:59:21.100805 ==
7756 05:59:21.103714 Dram Type= 6, Freq= 0, CH_0, rank 0
7757 05:59:21.107309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7758 05:59:21.107396 ==
7759 05:59:21.107480
7760 05:59:21.107583
7761 05:59:21.110377 TX Vref Scan disable
7762 05:59:21.110482 == TX Byte 0 ==
7763 05:59:21.117089 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7764 05:59:21.117193 == TX Byte 1 ==
7765 05:59:21.120188 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7766 05:59:21.123850 DramC Write-DBI off
7767 05:59:21.123962
7768 05:59:21.124063 [DATLAT]
7769 05:59:21.126730 Freq=1600, CH0 RK0
7770 05:59:21.126843
7771 05:59:21.126944 DATLAT Default: 0xf
7772 05:59:21.130132 0, 0xFFFF, sum = 0
7773 05:59:21.130246 1, 0xFFFF, sum = 0
7774 05:59:21.133457 2, 0xFFFF, sum = 0
7775 05:59:21.133580 3, 0xFFFF, sum = 0
7776 05:59:21.137065 4, 0xFFFF, sum = 0
7777 05:59:21.140059 5, 0xFFFF, sum = 0
7778 05:59:21.140165 6, 0xFFFF, sum = 0
7779 05:59:21.143491 7, 0xFFFF, sum = 0
7780 05:59:21.143600 8, 0xFFFF, sum = 0
7781 05:59:21.146515 9, 0xFFFF, sum = 0
7782 05:59:21.146625 10, 0xFFFF, sum = 0
7783 05:59:21.150229 11, 0xFFFF, sum = 0
7784 05:59:21.150341 12, 0xFFFF, sum = 0
7785 05:59:21.153723 13, 0xFFFF, sum = 0
7786 05:59:21.153840 14, 0x0, sum = 1
7787 05:59:21.156556 15, 0x0, sum = 2
7788 05:59:21.156672 16, 0x0, sum = 3
7789 05:59:21.159933 17, 0x0, sum = 4
7790 05:59:21.160057 best_step = 15
7791 05:59:21.160169
7792 05:59:21.160259 ==
7793 05:59:21.163512 Dram Type= 6, Freq= 0, CH_0, rank 0
7794 05:59:21.166958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7795 05:59:21.169923 ==
7796 05:59:21.170002 RX Vref Scan: 1
7797 05:59:21.170071
7798 05:59:21.173573 Set Vref Range= 24 -> 127
7799 05:59:21.173685
7800 05:59:21.176417 RX Vref 24 -> 127, step: 1
7801 05:59:21.176525
7802 05:59:21.176617 RX Delay 11 -> 252, step: 4
7803 05:59:21.176709
7804 05:59:21.180177 Set Vref, RX VrefLevel [Byte0]: 24
7805 05:59:21.183187 [Byte1]: 24
7806 05:59:21.186902
7807 05:59:21.186981 Set Vref, RX VrefLevel [Byte0]: 25
7808 05:59:21.190561 [Byte1]: 25
7809 05:59:21.194559
7810 05:59:21.194663 Set Vref, RX VrefLevel [Byte0]: 26
7811 05:59:21.197750 [Byte1]: 26
7812 05:59:21.202577
7813 05:59:21.202681 Set Vref, RX VrefLevel [Byte0]: 27
7814 05:59:21.205676 [Byte1]: 27
7815 05:59:21.209786
7816 05:59:21.209896 Set Vref, RX VrefLevel [Byte0]: 28
7817 05:59:21.213214 [Byte1]: 28
7818 05:59:21.217530
7819 05:59:21.217644 Set Vref, RX VrefLevel [Byte0]: 29
7820 05:59:21.220686 [Byte1]: 29
7821 05:59:21.224770
7822 05:59:21.224850 Set Vref, RX VrefLevel [Byte0]: 30
7823 05:59:21.228589 [Byte1]: 30
7824 05:59:21.232643
7825 05:59:21.232722 Set Vref, RX VrefLevel [Byte0]: 31
7826 05:59:21.236160 [Byte1]: 31
7827 05:59:21.240081
7828 05:59:21.240197 Set Vref, RX VrefLevel [Byte0]: 32
7829 05:59:21.243561 [Byte1]: 32
7830 05:59:21.248003
7831 05:59:21.248126 Set Vref, RX VrefLevel [Byte0]: 33
7832 05:59:21.251031 [Byte1]: 33
7833 05:59:21.255329
7834 05:59:21.255438 Set Vref, RX VrefLevel [Byte0]: 34
7835 05:59:21.259162 [Byte1]: 34
7836 05:59:21.263293
7837 05:59:21.263370 Set Vref, RX VrefLevel [Byte0]: 35
7838 05:59:21.266785 [Byte1]: 35
7839 05:59:21.270677
7840 05:59:21.270755 Set Vref, RX VrefLevel [Byte0]: 36
7841 05:59:21.274180 [Byte1]: 36
7842 05:59:21.278213
7843 05:59:21.278298 Set Vref, RX VrefLevel [Byte0]: 37
7844 05:59:21.281599 [Byte1]: 37
7845 05:59:21.285746
7846 05:59:21.285828 Set Vref, RX VrefLevel [Byte0]: 38
7847 05:59:21.289413 [Byte1]: 38
7848 05:59:21.293628
7849 05:59:21.293738 Set Vref, RX VrefLevel [Byte0]: 39
7850 05:59:21.296957 [Byte1]: 39
7851 05:59:21.300962
7852 05:59:21.301078 Set Vref, RX VrefLevel [Byte0]: 40
7853 05:59:21.304172 [Byte1]: 40
7854 05:59:21.308887
7855 05:59:21.308994 Set Vref, RX VrefLevel [Byte0]: 41
7856 05:59:21.312366 [Byte1]: 41
7857 05:59:21.316157
7858 05:59:21.316263 Set Vref, RX VrefLevel [Byte0]: 42
7859 05:59:21.320025 [Byte1]: 42
7860 05:59:21.324187
7861 05:59:21.324298 Set Vref, RX VrefLevel [Byte0]: 43
7862 05:59:21.327249 [Byte1]: 43
7863 05:59:21.331548
7864 05:59:21.331654 Set Vref, RX VrefLevel [Byte0]: 44
7865 05:59:21.335075 [Byte1]: 44
7866 05:59:21.339011
7867 05:59:21.339101 Set Vref, RX VrefLevel [Byte0]: 45
7868 05:59:21.342697 [Byte1]: 45
7869 05:59:21.346600
7870 05:59:21.346677 Set Vref, RX VrefLevel [Byte0]: 46
7871 05:59:21.350278 [Byte1]: 46
7872 05:59:21.354389
7873 05:59:21.354473 Set Vref, RX VrefLevel [Byte0]: 47
7874 05:59:21.357828 [Byte1]: 47
7875 05:59:21.361932
7876 05:59:21.362015 Set Vref, RX VrefLevel [Byte0]: 48
7877 05:59:21.365585 [Byte1]: 48
7878 05:59:21.369753
7879 05:59:21.369836 Set Vref, RX VrefLevel [Byte0]: 49
7880 05:59:21.373086 [Byte1]: 49
7881 05:59:21.377085
7882 05:59:21.377194 Set Vref, RX VrefLevel [Byte0]: 50
7883 05:59:21.381224 [Byte1]: 50
7884 05:59:21.384735
7885 05:59:21.384844 Set Vref, RX VrefLevel [Byte0]: 51
7886 05:59:21.388203 [Byte1]: 51
7887 05:59:21.392931
7888 05:59:21.393034 Set Vref, RX VrefLevel [Byte0]: 52
7889 05:59:21.395960 [Byte1]: 52
7890 05:59:21.400240
7891 05:59:21.400323 Set Vref, RX VrefLevel [Byte0]: 53
7892 05:59:21.406690 [Byte1]: 53
7893 05:59:21.406774
7894 05:59:21.410228 Set Vref, RX VrefLevel [Byte0]: 54
7895 05:59:21.413380 [Byte1]: 54
7896 05:59:21.413463
7897 05:59:21.416334 Set Vref, RX VrefLevel [Byte0]: 55
7898 05:59:21.419818 [Byte1]: 55
7899 05:59:21.422811
7900 05:59:21.422930 Set Vref, RX VrefLevel [Byte0]: 56
7901 05:59:21.426173 [Byte1]: 56
7902 05:59:21.430870
7903 05:59:21.430986 Set Vref, RX VrefLevel [Byte0]: 57
7904 05:59:21.433910 [Byte1]: 57
7905 05:59:21.438235
7906 05:59:21.438356 Set Vref, RX VrefLevel [Byte0]: 58
7907 05:59:21.441694 [Byte1]: 58
7908 05:59:21.445964
7909 05:59:21.446075 Set Vref, RX VrefLevel [Byte0]: 59
7910 05:59:21.449030 [Byte1]: 59
7911 05:59:21.453258
7912 05:59:21.453354 Set Vref, RX VrefLevel [Byte0]: 60
7913 05:59:21.456928 [Byte1]: 60
7914 05:59:21.460919
7915 05:59:21.461001 Set Vref, RX VrefLevel [Byte0]: 61
7916 05:59:21.464343 [Byte1]: 61
7917 05:59:21.468508
7918 05:59:21.468615 Set Vref, RX VrefLevel [Byte0]: 62
7919 05:59:21.472308 [Byte1]: 62
7920 05:59:21.476425
7921 05:59:21.476556 Set Vref, RX VrefLevel [Byte0]: 63
7922 05:59:21.479395 [Byte1]: 63
7923 05:59:21.483937
7924 05:59:21.484089 Set Vref, RX VrefLevel [Byte0]: 64
7925 05:59:21.486989 [Byte1]: 64
7926 05:59:21.491773
7927 05:59:21.491855 Set Vref, RX VrefLevel [Byte0]: 65
7928 05:59:21.494737 [Byte1]: 65
7929 05:59:21.499124
7930 05:59:21.499204 Set Vref, RX VrefLevel [Byte0]: 66
7931 05:59:21.502558 [Byte1]: 66
7932 05:59:21.506586
7933 05:59:21.506667 Set Vref, RX VrefLevel [Byte0]: 67
7934 05:59:21.510281 [Byte1]: 67
7935 05:59:21.514444
7936 05:59:21.514524 Set Vref, RX VrefLevel [Byte0]: 68
7937 05:59:21.517591 [Byte1]: 68
7938 05:59:21.522341
7939 05:59:21.522457 Set Vref, RX VrefLevel [Byte0]: 69
7940 05:59:21.525338 [Byte1]: 69
7941 05:59:21.529436
7942 05:59:21.529549 Set Vref, RX VrefLevel [Byte0]: 70
7943 05:59:21.532838 [Byte1]: 70
7944 05:59:21.537284
7945 05:59:21.537367 Set Vref, RX VrefLevel [Byte0]: 71
7946 05:59:21.540507 [Byte1]: 71
7947 05:59:21.544924
7948 05:59:21.545006 Set Vref, RX VrefLevel [Byte0]: 72
7949 05:59:21.547926 [Byte1]: 72
7950 05:59:21.552219
7951 05:59:21.552304 Set Vref, RX VrefLevel [Byte0]: 73
7952 05:59:21.555692 [Byte1]: 73
7953 05:59:21.559932
7954 05:59:21.560014 Set Vref, RX VrefLevel [Byte0]: 74
7955 05:59:21.563373 [Byte1]: 74
7956 05:59:21.568034
7957 05:59:21.568116 Set Vref, RX VrefLevel [Byte0]: 75
7958 05:59:21.570903 [Byte1]: 75
7959 05:59:21.575357
7960 05:59:21.575439 Set Vref, RX VrefLevel [Byte0]: 76
7961 05:59:21.578290 [Byte1]: 76
7962 05:59:21.583255
7963 05:59:21.583338 Final RX Vref Byte 0 = 64 to rank0
7964 05:59:21.585995 Final RX Vref Byte 1 = 60 to rank0
7965 05:59:21.589468 Final RX Vref Byte 0 = 64 to rank1
7966 05:59:21.592730 Final RX Vref Byte 1 = 60 to rank1==
7967 05:59:21.595978 Dram Type= 6, Freq= 0, CH_0, rank 0
7968 05:59:21.602870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7969 05:59:21.602955 ==
7970 05:59:21.603043 DQS Delay:
7971 05:59:21.605889 DQS0 = 0, DQS1 = 0
7972 05:59:21.605973 DQM Delay:
7973 05:59:21.606039 DQM0 = 126, DQM1 = 119
7974 05:59:21.609276 DQ Delay:
7975 05:59:21.613000 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7976 05:59:21.615972 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7977 05:59:21.619012 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7978 05:59:21.622771 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7979 05:59:21.622854
7980 05:59:21.622919
7981 05:59:21.622981
7982 05:59:21.625711 [DramC_TX_OE_Calibration] TA2
7983 05:59:21.629327 Original DQ_B0 (3 6) =30, OEN = 27
7984 05:59:21.632341 Original DQ_B1 (3 6) =30, OEN = 27
7985 05:59:21.635796 24, 0x0, End_B0=24 End_B1=24
7986 05:59:21.635879 25, 0x0, End_B0=25 End_B1=25
7987 05:59:21.639504 26, 0x0, End_B0=26 End_B1=26
7988 05:59:21.642437 27, 0x0, End_B0=27 End_B1=27
7989 05:59:21.645797 28, 0x0, End_B0=28 End_B1=28
7990 05:59:21.649055 29, 0x0, End_B0=29 End_B1=29
7991 05:59:21.649137 30, 0x0, End_B0=30 End_B1=30
7992 05:59:21.652852 31, 0x4141, End_B0=30 End_B1=30
7993 05:59:21.655852 Byte0 end_step=30 best_step=27
7994 05:59:21.658904 Byte1 end_step=30 best_step=27
7995 05:59:21.661960 Byte0 TX OE(2T, 0.5T) = (3, 3)
7996 05:59:21.665296 Byte1 TX OE(2T, 0.5T) = (3, 3)
7997 05:59:21.665402
7998 05:59:21.665515
7999 05:59:21.672128 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
8000 05:59:21.675210 CH0 RK0: MR19=303, MR18=1111
8001 05:59:21.682174 CH0_RK0: MR19=0x303, MR18=0x1111, DQSOSC=401, MR23=63, INC=22, DEC=15
8002 05:59:21.682255
8003 05:59:21.685207 ----->DramcWriteLeveling(PI) begin...
8004 05:59:21.685289 ==
8005 05:59:21.688718 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 05:59:21.692275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 05:59:21.692357 ==
8008 05:59:21.695067 Write leveling (Byte 0): 33 => 33
8009 05:59:21.698682 Write leveling (Byte 1): 26 => 26
8010 05:59:21.701865 DramcWriteLeveling(PI) end<-----
8011 05:59:21.701946
8012 05:59:21.702010 ==
8013 05:59:21.705398 Dram Type= 6, Freq= 0, CH_0, rank 1
8014 05:59:21.708873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 05:59:21.708980 ==
8016 05:59:21.711894 [Gating] SW mode calibration
8017 05:59:21.718246 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8018 05:59:21.724876 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8019 05:59:21.728431 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 05:59:21.734945 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 05:59:21.738509 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 05:59:21.741318 1 4 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
8023 05:59:21.748134 1 4 16 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
8024 05:59:21.751517 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 05:59:21.754986 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 05:59:21.761625 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 05:59:21.764621 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 05:59:21.768113 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 05:59:21.775040 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 05:59:21.777910 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
8031 05:59:21.781435 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8032 05:59:21.788026 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8033 05:59:21.790997 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 05:59:21.794286 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 05:59:21.801238 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 05:59:21.804221 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 05:59:21.807619 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8038 05:59:21.814544 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8039 05:59:21.817946 1 6 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8040 05:59:21.821193 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8041 05:59:21.827822 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 05:59:21.830871 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 05:59:21.834317 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 05:59:21.840891 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 05:59:21.844306 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 05:59:21.847437 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 05:59:21.854229 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8048 05:59:21.857213 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8049 05:59:21.860690 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 05:59:21.864312 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 05:59:21.870660 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 05:59:21.873827 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 05:59:21.877423 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 05:59:21.883872 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 05:59:21.886902 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 05:59:21.890498 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 05:59:21.897017 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 05:59:21.900423 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 05:59:21.903708 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 05:59:21.910212 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 05:59:21.913679 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8062 05:59:21.916718 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8063 05:59:21.923536 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8064 05:59:21.926922 Total UI for P1: 0, mck2ui 16
8065 05:59:21.930062 best dqsien dly found for B0: ( 1, 9, 10)
8066 05:59:21.933673 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8067 05:59:21.936636 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 05:59:21.940368 Total UI for P1: 0, mck2ui 16
8069 05:59:21.943391 best dqsien dly found for B1: ( 1, 9, 20)
8070 05:59:21.947060 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8071 05:59:21.949964 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8072 05:59:21.953523
8073 05:59:21.956473 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8074 05:59:21.960265 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8075 05:59:21.963090 [Gating] SW calibration Done
8076 05:59:21.963170 ==
8077 05:59:21.966751 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 05:59:21.969698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 05:59:21.969781 ==
8080 05:59:21.969846 RX Vref Scan: 0
8081 05:59:21.973324
8082 05:59:21.973430 RX Vref 0 -> 0, step: 1
8083 05:59:21.973554
8084 05:59:21.976359 RX Delay 0 -> 252, step: 8
8085 05:59:21.979874 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8086 05:59:21.983353 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8087 05:59:21.989907 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8088 05:59:21.993194 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8089 05:59:21.996127 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8090 05:59:21.999850 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8091 05:59:22.002919 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8092 05:59:22.009742 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8093 05:59:22.012950 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8094 05:59:22.016211 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8095 05:59:22.019631 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8096 05:59:22.022883 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8097 05:59:22.029618 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8098 05:59:22.033034 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8099 05:59:22.036359 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8100 05:59:22.039201 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8101 05:59:22.039294 ==
8102 05:59:22.042720 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 05:59:22.049157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 05:59:22.049257 ==
8105 05:59:22.049352 DQS Delay:
8106 05:59:22.052684 DQS0 = 0, DQS1 = 0
8107 05:59:22.052766 DQM Delay:
8108 05:59:22.055755 DQM0 = 127, DQM1 = 121
8109 05:59:22.055836 DQ Delay:
8110 05:59:22.059309 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8111 05:59:22.062394 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8112 05:59:22.066040 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8113 05:59:22.069022 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8114 05:59:22.069103
8115 05:59:22.069168
8116 05:59:22.069228 ==
8117 05:59:22.072725 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 05:59:22.079111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 05:59:22.079194 ==
8120 05:59:22.079258
8121 05:59:22.079317
8122 05:59:22.079375 TX Vref Scan disable
8123 05:59:22.082665 == TX Byte 0 ==
8124 05:59:22.085702 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8125 05:59:22.092377 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8126 05:59:22.092458 == TX Byte 1 ==
8127 05:59:22.095600 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8128 05:59:22.102404 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8129 05:59:22.102486 ==
8130 05:59:22.105682 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 05:59:22.108548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 05:59:22.108629 ==
8133 05:59:22.122239
8134 05:59:22.125371 TX Vref early break, caculate TX vref
8135 05:59:22.128478 TX Vref=16, minBit 0, minWin=22, winSum=367
8136 05:59:22.131876 TX Vref=18, minBit 8, minWin=22, winSum=373
8137 05:59:22.135516 TX Vref=20, minBit 1, minWin=23, winSum=379
8138 05:59:22.138573 TX Vref=22, minBit 8, minWin=22, winSum=390
8139 05:59:22.142046 TX Vref=24, minBit 0, minWin=24, winSum=396
8140 05:59:22.148334 TX Vref=26, minBit 8, minWin=24, winSum=401
8141 05:59:22.151915 TX Vref=28, minBit 8, minWin=24, winSum=412
8142 05:59:22.154954 TX Vref=30, minBit 8, minWin=24, winSum=411
8143 05:59:22.158288 TX Vref=32, minBit 8, minWin=23, winSum=395
8144 05:59:22.161362 TX Vref=34, minBit 3, minWin=23, winSum=387
8145 05:59:22.168560 [TxChooseVref] Worse bit 8, Min win 24, Win sum 412, Final Vref 28
8146 05:59:22.168642
8147 05:59:22.171586 Final TX Range 0 Vref 28
8148 05:59:22.171687
8149 05:59:22.171781 ==
8150 05:59:22.175030 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 05:59:22.178080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 05:59:22.178163 ==
8153 05:59:22.178228
8154 05:59:22.178288
8155 05:59:22.181672 TX Vref Scan disable
8156 05:59:22.188275 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8157 05:59:22.188375 == TX Byte 0 ==
8158 05:59:22.191232 u2DelayCellOfst[0]=11 cells (3 PI)
8159 05:59:22.194801 u2DelayCellOfst[1]=18 cells (5 PI)
8160 05:59:22.198355 u2DelayCellOfst[2]=11 cells (3 PI)
8161 05:59:22.201340 u2DelayCellOfst[3]=11 cells (3 PI)
8162 05:59:22.204925 u2DelayCellOfst[4]=7 cells (2 PI)
8163 05:59:22.208364 u2DelayCellOfst[5]=0 cells (0 PI)
8164 05:59:22.211517 u2DelayCellOfst[6]=18 cells (5 PI)
8165 05:59:22.214643 u2DelayCellOfst[7]=18 cells (5 PI)
8166 05:59:22.217872 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8167 05:59:22.221548 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8168 05:59:22.224267 == TX Byte 1 ==
8169 05:59:22.227838 u2DelayCellOfst[8]=0 cells (0 PI)
8170 05:59:22.227920 u2DelayCellOfst[9]=0 cells (0 PI)
8171 05:59:22.231438 u2DelayCellOfst[10]=7 cells (2 PI)
8172 05:59:22.234317 u2DelayCellOfst[11]=7 cells (2 PI)
8173 05:59:22.237579 u2DelayCellOfst[12]=15 cells (4 PI)
8174 05:59:22.241512 u2DelayCellOfst[13]=15 cells (4 PI)
8175 05:59:22.244318 u2DelayCellOfst[14]=15 cells (4 PI)
8176 05:59:22.247690 u2DelayCellOfst[15]=11 cells (3 PI)
8177 05:59:22.251240 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8178 05:59:22.257665 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8179 05:59:22.257748 DramC Write-DBI on
8180 05:59:22.257814 ==
8181 05:59:22.261306 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 05:59:22.267857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 05:59:22.267939 ==
8184 05:59:22.268004
8185 05:59:22.268064
8186 05:59:22.268121 TX Vref Scan disable
8187 05:59:22.271389 == TX Byte 0 ==
8188 05:59:22.274938 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8189 05:59:22.278089 == TX Byte 1 ==
8190 05:59:22.281653 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8191 05:59:22.284531 DramC Write-DBI off
8192 05:59:22.284612
8193 05:59:22.284677 [DATLAT]
8194 05:59:22.284736 Freq=1600, CH0 RK1
8195 05:59:22.284794
8196 05:59:22.288139 DATLAT Default: 0xf
8197 05:59:22.291103 0, 0xFFFF, sum = 0
8198 05:59:22.291185 1, 0xFFFF, sum = 0
8199 05:59:22.294724 2, 0xFFFF, sum = 0
8200 05:59:22.294805 3, 0xFFFF, sum = 0
8201 05:59:22.297805 4, 0xFFFF, sum = 0
8202 05:59:22.297889 5, 0xFFFF, sum = 0
8203 05:59:22.301546 6, 0xFFFF, sum = 0
8204 05:59:22.301677 7, 0xFFFF, sum = 0
8205 05:59:22.304607 8, 0xFFFF, sum = 0
8206 05:59:22.304690 9, 0xFFFF, sum = 0
8207 05:59:22.307499 10, 0xFFFF, sum = 0
8208 05:59:22.307582 11, 0xFFFF, sum = 0
8209 05:59:22.311083 12, 0xFFFF, sum = 0
8210 05:59:22.311166 13, 0xCFFF, sum = 0
8211 05:59:22.314179 14, 0x0, sum = 1
8212 05:59:22.314260 15, 0x0, sum = 2
8213 05:59:22.317626 16, 0x0, sum = 3
8214 05:59:22.317709 17, 0x0, sum = 4
8215 05:59:22.320969 best_step = 15
8216 05:59:22.321049
8217 05:59:22.321114 ==
8218 05:59:22.324358 Dram Type= 6, Freq= 0, CH_0, rank 1
8219 05:59:22.327395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8220 05:59:22.327477 ==
8221 05:59:22.330843 RX Vref Scan: 0
8222 05:59:22.330924
8223 05:59:22.330990 RX Vref 0 -> 0, step: 1
8224 05:59:22.331051
8225 05:59:22.334483 RX Delay 3 -> 252, step: 4
8226 05:59:22.340747 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8227 05:59:22.344298 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8228 05:59:22.347296 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8229 05:59:22.350479 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8230 05:59:22.354382 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8231 05:59:22.360465 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8232 05:59:22.363921 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8233 05:59:22.367512 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8234 05:59:22.370469 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8235 05:59:22.374158 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8236 05:59:22.380588 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8237 05:59:22.384171 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8238 05:59:22.387232 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8239 05:59:22.390770 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8240 05:59:22.393700 iDelay=191, Bit 14, Center 126 (67 ~ 186) 120
8241 05:59:22.400237 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8242 05:59:22.400318 ==
8243 05:59:22.403930 Dram Type= 6, Freq= 0, CH_0, rank 1
8244 05:59:22.407541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8245 05:59:22.407654 ==
8246 05:59:22.407750 DQS Delay:
8247 05:59:22.410424 DQS0 = 0, DQS1 = 0
8248 05:59:22.410505 DQM Delay:
8249 05:59:22.413488 DQM0 = 124, DQM1 = 117
8250 05:59:22.413609 DQ Delay:
8251 05:59:22.417172 DQ0 =124, DQ1 =124, DQ2 =120, DQ3 =122
8252 05:59:22.420844 DQ4 =124, DQ5 =112, DQ6 =136, DQ7 =134
8253 05:59:22.423889 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8254 05:59:22.426799 DQ12 =124, DQ13 =122, DQ14 =126, DQ15 =124
8255 05:59:22.426880
8256 05:59:22.430368
8257 05:59:22.430449
8258 05:59:22.430513 [DramC_TX_OE_Calibration] TA2
8259 05:59:22.433459 Original DQ_B0 (3 6) =30, OEN = 27
8260 05:59:22.436755 Original DQ_B1 (3 6) =30, OEN = 27
8261 05:59:22.440436 24, 0x0, End_B0=24 End_B1=24
8262 05:59:22.443440 25, 0x0, End_B0=25 End_B1=25
8263 05:59:22.446932 26, 0x0, End_B0=26 End_B1=26
8264 05:59:22.447060 27, 0x0, End_B0=27 End_B1=27
8265 05:59:22.449949 28, 0x0, End_B0=28 End_B1=28
8266 05:59:22.453641 29, 0x0, End_B0=29 End_B1=29
8267 05:59:22.456743 30, 0x0, End_B0=30 End_B1=30
8268 05:59:22.459823 31, 0x4141, End_B0=30 End_B1=30
8269 05:59:22.459906 Byte0 end_step=30 best_step=27
8270 05:59:22.463186 Byte1 end_step=30 best_step=27
8271 05:59:22.466655 Byte0 TX OE(2T, 0.5T) = (3, 3)
8272 05:59:22.470268 Byte1 TX OE(2T, 0.5T) = (3, 3)
8273 05:59:22.470435
8274 05:59:22.470504
8275 05:59:22.479991 [DQSOSCAuto] RK1, (LSB)MR18= 0x2411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
8276 05:59:22.480074 CH0 RK1: MR19=303, MR18=2411
8277 05:59:22.486473 CH0_RK1: MR19=0x303, MR18=0x2411, DQSOSC=391, MR23=63, INC=24, DEC=16
8278 05:59:22.490201 [RxdqsGatingPostProcess] freq 1600
8279 05:59:22.496676 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8280 05:59:22.500363 best DQS0 dly(2T, 0.5T) = (1, 1)
8281 05:59:22.503103 best DQS1 dly(2T, 0.5T) = (1, 1)
8282 05:59:22.506339 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8283 05:59:22.506506 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8284 05:59:22.509926 best DQS0 dly(2T, 0.5T) = (1, 1)
8285 05:59:22.512991 best DQS1 dly(2T, 0.5T) = (1, 1)
8286 05:59:22.516512 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8287 05:59:22.519492 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8288 05:59:22.523082 Pre-setting of DQS Precalculation
8289 05:59:22.529666 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8290 05:59:22.529750 ==
8291 05:59:22.533302 Dram Type= 6, Freq= 0, CH_1, rank 0
8292 05:59:22.536119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 05:59:22.536200 ==
8294 05:59:22.543389 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8295 05:59:22.546307 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8296 05:59:22.549689 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8297 05:59:22.556323 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8298 05:59:22.564770 [CA 0] Center 42 (13~71) winsize 59
8299 05:59:22.567933 [CA 1] Center 42 (13~72) winsize 60
8300 05:59:22.571244 [CA 2] Center 38 (9~67) winsize 59
8301 05:59:22.574549 [CA 3] Center 37 (8~66) winsize 59
8302 05:59:22.577874 [CA 4] Center 38 (9~67) winsize 59
8303 05:59:22.581038 [CA 5] Center 36 (7~66) winsize 60
8304 05:59:22.581118
8305 05:59:22.584643 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8306 05:59:22.584724
8307 05:59:22.590961 [CATrainingPosCal] consider 1 rank data
8308 05:59:22.591041 u2DelayCellTimex100 = 258/100 ps
8309 05:59:22.597505 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8310 05:59:22.601086 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8311 05:59:22.603954 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8312 05:59:22.607695 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8313 05:59:22.610607 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8314 05:59:22.614285 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8315 05:59:22.614366
8316 05:59:22.617335 CA PerBit enable=1, Macro0, CA PI delay=36
8317 05:59:22.617415
8318 05:59:22.620919 [CBTSetCACLKResult] CA Dly = 36
8319 05:59:22.623979 CS Dly: 9 (0~40)
8320 05:59:22.627356 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8321 05:59:22.630437 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8322 05:59:22.630518 ==
8323 05:59:22.633981 Dram Type= 6, Freq= 0, CH_1, rank 1
8324 05:59:22.640696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 05:59:22.640778 ==
8326 05:59:22.643578 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8327 05:59:22.650191 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8328 05:59:22.653835 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8329 05:59:22.660228 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8330 05:59:22.667929 [CA 0] Center 42 (13~72) winsize 60
8331 05:59:22.671316 [CA 1] Center 42 (13~72) winsize 60
8332 05:59:22.674510 [CA 2] Center 38 (9~67) winsize 59
8333 05:59:22.677546 [CA 3] Center 36 (7~66) winsize 60
8334 05:59:22.680769 [CA 4] Center 38 (8~68) winsize 61
8335 05:59:22.684529 [CA 5] Center 36 (6~67) winsize 62
8336 05:59:22.684613
8337 05:59:22.687355 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8338 05:59:22.687435
8339 05:59:22.690657 [CATrainingPosCal] consider 2 rank data
8340 05:59:22.693990 u2DelayCellTimex100 = 258/100 ps
8341 05:59:22.700785 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8342 05:59:22.704168 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8343 05:59:22.707456 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8344 05:59:22.710616 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8345 05:59:22.714064 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8346 05:59:22.717427 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8347 05:59:22.717548
8348 05:59:22.720415 CA PerBit enable=1, Macro0, CA PI delay=36
8349 05:59:22.720496
8350 05:59:22.724191 [CBTSetCACLKResult] CA Dly = 36
8351 05:59:22.727176 CS Dly: 10 (0~43)
8352 05:59:22.730666 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8353 05:59:22.733782 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8354 05:59:22.733874
8355 05:59:22.737265 ----->DramcWriteLeveling(PI) begin...
8356 05:59:22.737371 ==
8357 05:59:22.740385 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 05:59:22.746950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 05:59:22.747032 ==
8360 05:59:22.750686 Write leveling (Byte 0): 24 => 24
8361 05:59:22.753597 Write leveling (Byte 1): 27 => 27
8362 05:59:22.753678 DramcWriteLeveling(PI) end<-----
8363 05:59:22.753743
8364 05:59:22.757330 ==
8365 05:59:22.760025 Dram Type= 6, Freq= 0, CH_1, rank 0
8366 05:59:22.763494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 05:59:22.763575 ==
8368 05:59:22.767078 [Gating] SW mode calibration
8369 05:59:22.773461 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8370 05:59:22.776555 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8371 05:59:22.783267 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 05:59:22.786493 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 05:59:22.790373 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 05:59:22.796400 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 05:59:22.799780 1 4 16 | B1->B0 | 3030 3131 | 0 1 | (0 0) (1 1)
8376 05:59:22.803291 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 05:59:22.810031 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 05:59:22.812948 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 05:59:22.816476 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 05:59:22.823210 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 05:59:22.826107 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 05:59:22.829843 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8383 05:59:22.836397 1 5 16 | B1->B0 | 2727 2626 | 0 0 | (1 0) (0 1)
8384 05:59:22.839360 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 05:59:22.843163 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 05:59:22.849754 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 05:59:22.852788 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 05:59:22.855814 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 05:59:22.862972 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 05:59:22.866400 1 6 12 | B1->B0 | 2828 2525 | 0 1 | (0 0) (0 0)
8391 05:59:22.869300 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (1 1)
8392 05:59:22.876099 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 05:59:22.879114 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 05:59:22.882826 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 05:59:22.888917 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 05:59:22.892333 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 05:59:22.895670 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 05:59:22.902585 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 05:59:22.905728 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8400 05:59:22.909158 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8401 05:59:22.915730 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 05:59:22.918837 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 05:59:22.921974 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 05:59:22.928863 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 05:59:22.932270 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 05:59:22.935632 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 05:59:22.942007 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 05:59:22.945609 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 05:59:22.948581 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 05:59:22.955392 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 05:59:22.958457 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 05:59:22.962065 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 05:59:22.968417 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 05:59:22.971861 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8415 05:59:22.975271 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8416 05:59:22.982125 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 05:59:22.982207 Total UI for P1: 0, mck2ui 16
8418 05:59:22.988056 best dqsien dly found for B0: ( 1, 9, 14)
8419 05:59:22.988165 Total UI for P1: 0, mck2ui 16
8420 05:59:22.991587 best dqsien dly found for B1: ( 1, 9, 14)
8421 05:59:22.998113 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8422 05:59:23.001669 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8423 05:59:23.001751
8424 05:59:23.004630 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8425 05:59:23.008170 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8426 05:59:23.011232 [Gating] SW calibration Done
8427 05:59:23.011342 ==
8428 05:59:23.014703 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 05:59:23.018236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 05:59:23.018346 ==
8431 05:59:23.021209 RX Vref Scan: 0
8432 05:59:23.021314
8433 05:59:23.021410 RX Vref 0 -> 0, step: 1
8434 05:59:23.021534
8435 05:59:23.024683 RX Delay 0 -> 252, step: 8
8436 05:59:23.027995 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8437 05:59:23.034408 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8438 05:59:23.038007 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8439 05:59:23.041222 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8440 05:59:23.044566 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8441 05:59:23.047920 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8442 05:59:23.054335 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8443 05:59:23.057937 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8444 05:59:23.060997 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8445 05:59:23.064472 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8446 05:59:23.067503 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8447 05:59:23.074472 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8448 05:59:23.077481 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8449 05:59:23.080993 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8450 05:59:23.083933 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8451 05:59:23.091180 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8452 05:59:23.091341 ==
8453 05:59:23.094196 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 05:59:23.097193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 05:59:23.097351 ==
8456 05:59:23.097502 DQS Delay:
8457 05:59:23.100710 DQS0 = 0, DQS1 = 0
8458 05:59:23.100865 DQM Delay:
8459 05:59:23.104104 DQM0 = 132, DQM1 = 126
8460 05:59:23.104262 DQ Delay:
8461 05:59:23.107543 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8462 05:59:23.110533 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8463 05:59:23.114257 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8464 05:59:23.117210 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8465 05:59:23.117317
8466 05:59:23.117383
8467 05:59:23.120662 ==
8468 05:59:23.120743 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 05:59:23.127096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 05:59:23.127211 ==
8471 05:59:23.127307
8472 05:59:23.127402
8473 05:59:23.130808 TX Vref Scan disable
8474 05:59:23.130889 == TX Byte 0 ==
8475 05:59:23.133874 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8476 05:59:23.140377 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8477 05:59:23.140458 == TX Byte 1 ==
8478 05:59:23.144155 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8479 05:59:23.150398 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8480 05:59:23.150480 ==
8481 05:59:23.153670 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 05:59:23.156786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 05:59:23.156944 ==
8484 05:59:23.170971
8485 05:59:23.174489 TX Vref early break, caculate TX vref
8486 05:59:23.177458 TX Vref=16, minBit 11, minWin=21, winSum=363
8487 05:59:23.181015 TX Vref=18, minBit 10, minWin=22, winSum=372
8488 05:59:23.184370 TX Vref=20, minBit 11, minWin=23, winSum=388
8489 05:59:23.187365 TX Vref=22, minBit 12, minWin=23, winSum=396
8490 05:59:23.194684 TX Vref=24, minBit 1, minWin=25, winSum=406
8491 05:59:23.197760 TX Vref=26, minBit 9, minWin=25, winSum=414
8492 05:59:23.200801 TX Vref=28, minBit 0, minWin=25, winSum=418
8493 05:59:23.204305 TX Vref=30, minBit 1, minWin=25, winSum=415
8494 05:59:23.207307 TX Vref=32, minBit 5, minWin=24, winSum=408
8495 05:59:23.211228 TX Vref=34, minBit 9, minWin=23, winSum=397
8496 05:59:23.217567 TX Vref=36, minBit 5, minWin=23, winSum=387
8497 05:59:23.220488 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8498 05:59:23.220569
8499 05:59:23.223984 Final TX Range 0 Vref 28
8500 05:59:23.224065
8501 05:59:23.224129 ==
8502 05:59:23.227356 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 05:59:23.230935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 05:59:23.233937 ==
8505 05:59:23.234018
8506 05:59:23.234082
8507 05:59:23.234141 TX Vref Scan disable
8508 05:59:23.240533 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8509 05:59:23.240615 == TX Byte 0 ==
8510 05:59:23.244082 u2DelayCellOfst[0]=18 cells (5 PI)
8511 05:59:23.247088 u2DelayCellOfst[1]=15 cells (4 PI)
8512 05:59:23.250541 u2DelayCellOfst[2]=0 cells (0 PI)
8513 05:59:23.254340 u2DelayCellOfst[3]=7 cells (2 PI)
8514 05:59:23.257130 u2DelayCellOfst[4]=7 cells (2 PI)
8515 05:59:23.260580 u2DelayCellOfst[5]=22 cells (6 PI)
8516 05:59:23.264042 u2DelayCellOfst[6]=22 cells (6 PI)
8517 05:59:23.267383 u2DelayCellOfst[7]=7 cells (2 PI)
8518 05:59:23.270805 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8519 05:59:23.273658 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8520 05:59:23.277061 == TX Byte 1 ==
8521 05:59:23.280563 u2DelayCellOfst[8]=0 cells (0 PI)
8522 05:59:23.283554 u2DelayCellOfst[9]=3 cells (1 PI)
8523 05:59:23.287224 u2DelayCellOfst[10]=11 cells (3 PI)
8524 05:59:23.290503 u2DelayCellOfst[11]=7 cells (2 PI)
8525 05:59:23.290619 u2DelayCellOfst[12]=15 cells (4 PI)
8526 05:59:23.293580 u2DelayCellOfst[13]=18 cells (5 PI)
8527 05:59:23.297201 u2DelayCellOfst[14]=18 cells (5 PI)
8528 05:59:23.300126 u2DelayCellOfst[15]=18 cells (5 PI)
8529 05:59:23.307096 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8530 05:59:23.310119 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8531 05:59:23.310210 DramC Write-DBI on
8532 05:59:23.313396 ==
8533 05:59:23.313470 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 05:59:23.320594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 05:59:23.320683 ==
8536 05:59:23.320745
8537 05:59:23.320804
8538 05:59:23.323637 TX Vref Scan disable
8539 05:59:23.323721 == TX Byte 0 ==
8540 05:59:23.329903 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8541 05:59:23.329981 == TX Byte 1 ==
8542 05:59:23.333544 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8543 05:59:23.336527 DramC Write-DBI off
8544 05:59:23.336598
8545 05:59:23.336660 [DATLAT]
8546 05:59:23.340070 Freq=1600, CH1 RK0
8547 05:59:23.340147
8548 05:59:23.340207 DATLAT Default: 0xf
8549 05:59:23.343065 0, 0xFFFF, sum = 0
8550 05:59:23.343136 1, 0xFFFF, sum = 0
8551 05:59:23.346580 2, 0xFFFF, sum = 0
8552 05:59:23.346651 3, 0xFFFF, sum = 0
8553 05:59:23.349504 4, 0xFFFF, sum = 0
8554 05:59:23.349574 5, 0xFFFF, sum = 0
8555 05:59:23.353155 6, 0xFFFF, sum = 0
8556 05:59:23.356502 7, 0xFFFF, sum = 0
8557 05:59:23.356611 8, 0xFFFF, sum = 0
8558 05:59:23.359456 9, 0xFFFF, sum = 0
8559 05:59:23.359542 10, 0xFFFF, sum = 0
8560 05:59:23.362994 11, 0xFFFF, sum = 0
8561 05:59:23.363066 12, 0xFFFF, sum = 0
8562 05:59:23.366289 13, 0x8FFF, sum = 0
8563 05:59:23.366365 14, 0x0, sum = 1
8564 05:59:23.369837 15, 0x0, sum = 2
8565 05:59:23.369910 16, 0x0, sum = 3
8566 05:59:23.372845 17, 0x0, sum = 4
8567 05:59:23.372916 best_step = 15
8568 05:59:23.372992
8569 05:59:23.373052 ==
8570 05:59:23.376122 Dram Type= 6, Freq= 0, CH_1, rank 0
8571 05:59:23.379457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8572 05:59:23.379530 ==
8573 05:59:23.382899 RX Vref Scan: 1
8574 05:59:23.382973
8575 05:59:23.386255 Set Vref Range= 24 -> 127
8576 05:59:23.386325
8577 05:59:23.386394 RX Vref 24 -> 127, step: 1
8578 05:59:23.389424
8579 05:59:23.389519 RX Delay 11 -> 252, step: 4
8580 05:59:23.389581
8581 05:59:23.392722 Set Vref, RX VrefLevel [Byte0]: 24
8582 05:59:23.396144 [Byte1]: 24
8583 05:59:23.399948
8584 05:59:23.400025 Set Vref, RX VrefLevel [Byte0]: 25
8585 05:59:23.402823 [Byte1]: 25
8586 05:59:23.407506
8587 05:59:23.407597 Set Vref, RX VrefLevel [Byte0]: 26
8588 05:59:23.410428 [Byte1]: 26
8589 05:59:23.415200
8590 05:59:23.415276 Set Vref, RX VrefLevel [Byte0]: 27
8591 05:59:23.418035 [Byte1]: 27
8592 05:59:23.422787
8593 05:59:23.422866 Set Vref, RX VrefLevel [Byte0]: 28
8594 05:59:23.425658 [Byte1]: 28
8595 05:59:23.430158
8596 05:59:23.430267 Set Vref, RX VrefLevel [Byte0]: 29
8597 05:59:23.433639 [Byte1]: 29
8598 05:59:23.437580
8599 05:59:23.437670 Set Vref, RX VrefLevel [Byte0]: 30
8600 05:59:23.441100 [Byte1]: 30
8601 05:59:23.445324
8602 05:59:23.445411 Set Vref, RX VrefLevel [Byte0]: 31
8603 05:59:23.448989 [Byte1]: 31
8604 05:59:23.453242
8605 05:59:23.453315 Set Vref, RX VrefLevel [Byte0]: 32
8606 05:59:23.456196 [Byte1]: 32
8607 05:59:23.460365
8608 05:59:23.460436 Set Vref, RX VrefLevel [Byte0]: 33
8609 05:59:23.463764 [Byte1]: 33
8610 05:59:23.467933
8611 05:59:23.468005 Set Vref, RX VrefLevel [Byte0]: 34
8612 05:59:23.471310 [Byte1]: 34
8613 05:59:23.475944
8614 05:59:23.476025 Set Vref, RX VrefLevel [Byte0]: 35
8615 05:59:23.478782 [Byte1]: 35
8616 05:59:23.483641
8617 05:59:23.483712 Set Vref, RX VrefLevel [Byte0]: 36
8618 05:59:23.487064 [Byte1]: 36
8619 05:59:23.491132
8620 05:59:23.491233 Set Vref, RX VrefLevel [Byte0]: 37
8621 05:59:23.494551 [Byte1]: 37
8622 05:59:23.498346
8623 05:59:23.498427 Set Vref, RX VrefLevel [Byte0]: 38
8624 05:59:23.502046 [Byte1]: 38
8625 05:59:23.506117
8626 05:59:23.506199 Set Vref, RX VrefLevel [Byte0]: 39
8627 05:59:23.509706 [Byte1]: 39
8628 05:59:23.513970
8629 05:59:23.514042 Set Vref, RX VrefLevel [Byte0]: 40
8630 05:59:23.517087 [Byte1]: 40
8631 05:59:23.521576
8632 05:59:23.521648 Set Vref, RX VrefLevel [Byte0]: 41
8633 05:59:23.524683 [Byte1]: 41
8634 05:59:23.529337
8635 05:59:23.529415 Set Vref, RX VrefLevel [Byte0]: 42
8636 05:59:23.532210 [Byte1]: 42
8637 05:59:23.536937
8638 05:59:23.537016 Set Vref, RX VrefLevel [Byte0]: 43
8639 05:59:23.539804 [Byte1]: 43
8640 05:59:23.544572
8641 05:59:23.544647 Set Vref, RX VrefLevel [Byte0]: 44
8642 05:59:23.551129 [Byte1]: 44
8643 05:59:23.551243
8644 05:59:23.554139 Set Vref, RX VrefLevel [Byte0]: 45
8645 05:59:23.557134 [Byte1]: 45
8646 05:59:23.557209
8647 05:59:23.560749 Set Vref, RX VrefLevel [Byte0]: 46
8648 05:59:23.563803 [Byte1]: 46
8649 05:59:23.567356
8650 05:59:23.567429 Set Vref, RX VrefLevel [Byte0]: 47
8651 05:59:23.570255 [Byte1]: 47
8652 05:59:23.574758
8653 05:59:23.574831 Set Vref, RX VrefLevel [Byte0]: 48
8654 05:59:23.578133 [Byte1]: 48
8655 05:59:23.582246
8656 05:59:23.582323 Set Vref, RX VrefLevel [Byte0]: 49
8657 05:59:23.585730 [Byte1]: 49
8658 05:59:23.589933
8659 05:59:23.590006 Set Vref, RX VrefLevel [Byte0]: 50
8660 05:59:23.593517 [Byte1]: 50
8661 05:59:23.597943
8662 05:59:23.598020 Set Vref, RX VrefLevel [Byte0]: 51
8663 05:59:23.601002 [Byte1]: 51
8664 05:59:23.605127
8665 05:59:23.605211 Set Vref, RX VrefLevel [Byte0]: 52
8666 05:59:23.608401 [Byte1]: 52
8667 05:59:23.612686
8668 05:59:23.612762 Set Vref, RX VrefLevel [Byte0]: 53
8669 05:59:23.615912 [Byte1]: 53
8670 05:59:23.620306
8671 05:59:23.620413 Set Vref, RX VrefLevel [Byte0]: 54
8672 05:59:23.623919 [Byte1]: 54
8673 05:59:23.628034
8674 05:59:23.628123 Set Vref, RX VrefLevel [Byte0]: 55
8675 05:59:23.631563 [Byte1]: 55
8676 05:59:23.635795
8677 05:59:23.635873 Set Vref, RX VrefLevel [Byte0]: 56
8678 05:59:23.638705 [Byte1]: 56
8679 05:59:23.643226
8680 05:59:23.643302 Set Vref, RX VrefLevel [Byte0]: 57
8681 05:59:23.646720 [Byte1]: 57
8682 05:59:23.650785
8683 05:59:23.650858 Set Vref, RX VrefLevel [Byte0]: 58
8684 05:59:23.654461 [Byte1]: 58
8685 05:59:23.658741
8686 05:59:23.658814 Set Vref, RX VrefLevel [Byte0]: 59
8687 05:59:23.661764 [Byte1]: 59
8688 05:59:23.666104
8689 05:59:23.666178 Set Vref, RX VrefLevel [Byte0]: 60
8690 05:59:23.669640 [Byte1]: 60
8691 05:59:23.673846
8692 05:59:23.673920 Set Vref, RX VrefLevel [Byte0]: 61
8693 05:59:23.676765 [Byte1]: 61
8694 05:59:23.681259
8695 05:59:23.681341 Set Vref, RX VrefLevel [Byte0]: 62
8696 05:59:23.684582 [Byte1]: 62
8697 05:59:23.688722
8698 05:59:23.688795 Set Vref, RX VrefLevel [Byte0]: 63
8699 05:59:23.692317 [Byte1]: 63
8700 05:59:23.696472
8701 05:59:23.696545 Set Vref, RX VrefLevel [Byte0]: 64
8702 05:59:23.699552 [Byte1]: 64
8703 05:59:23.704188
8704 05:59:23.704260 Set Vref, RX VrefLevel [Byte0]: 65
8705 05:59:23.707532 [Byte1]: 65
8706 05:59:23.711888
8707 05:59:23.711972 Set Vref, RX VrefLevel [Byte0]: 66
8708 05:59:23.715519 [Byte1]: 66
8709 05:59:23.719473
8710 05:59:23.719553 Set Vref, RX VrefLevel [Byte0]: 67
8711 05:59:23.722851 [Byte1]: 67
8712 05:59:23.727058
8713 05:59:23.727133 Set Vref, RX VrefLevel [Byte0]: 68
8714 05:59:23.730343 [Byte1]: 68
8715 05:59:23.734496
8716 05:59:23.734567 Set Vref, RX VrefLevel [Byte0]: 69
8717 05:59:23.737860 [Byte1]: 69
8718 05:59:23.742659
8719 05:59:23.742749 Set Vref, RX VrefLevel [Byte0]: 70
8720 05:59:23.745594 [Byte1]: 70
8721 05:59:23.749552
8722 05:59:23.749638 Set Vref, RX VrefLevel [Byte0]: 71
8723 05:59:23.753266 [Byte1]: 71
8724 05:59:23.757300
8725 05:59:23.757374 Set Vref, RX VrefLevel [Byte0]: 72
8726 05:59:23.760916 [Byte1]: 72
8727 05:59:23.765155
8728 05:59:23.765234 Final RX Vref Byte 0 = 58 to rank0
8729 05:59:23.768109 Final RX Vref Byte 1 = 56 to rank0
8730 05:59:23.771710 Final RX Vref Byte 0 = 58 to rank1
8731 05:59:23.775147 Final RX Vref Byte 1 = 56 to rank1==
8732 05:59:23.778205 Dram Type= 6, Freq= 0, CH_1, rank 0
8733 05:59:23.785080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8734 05:59:23.785157 ==
8735 05:59:23.785220 DQS Delay:
8736 05:59:23.785280 DQS0 = 0, DQS1 = 0
8737 05:59:23.788040 DQM Delay:
8738 05:59:23.788109 DQM0 = 130, DQM1 = 123
8739 05:59:23.791283 DQ Delay:
8740 05:59:23.794698 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8741 05:59:23.798367 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8742 05:59:23.801367 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8743 05:59:23.804933 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8744 05:59:23.805005
8745 05:59:23.805067
8746 05:59:23.805125
8747 05:59:23.807908 [DramC_TX_OE_Calibration] TA2
8748 05:59:23.811256 Original DQ_B0 (3 6) =30, OEN = 27
8749 05:59:23.814699 Original DQ_B1 (3 6) =30, OEN = 27
8750 05:59:23.818280 24, 0x0, End_B0=24 End_B1=24
8751 05:59:23.818359 25, 0x0, End_B0=25 End_B1=25
8752 05:59:23.821490 26, 0x0, End_B0=26 End_B1=26
8753 05:59:23.824446 27, 0x0, End_B0=27 End_B1=27
8754 05:59:23.828105 28, 0x0, End_B0=28 End_B1=28
8755 05:59:23.831466 29, 0x0, End_B0=29 End_B1=29
8756 05:59:23.831537 30, 0x0, End_B0=30 End_B1=30
8757 05:59:23.834387 31, 0x4141, End_B0=30 End_B1=30
8758 05:59:23.837902 Byte0 end_step=30 best_step=27
8759 05:59:23.841265 Byte1 end_step=30 best_step=27
8760 05:59:23.844558 Byte0 TX OE(2T, 0.5T) = (3, 3)
8761 05:59:23.847988 Byte1 TX OE(2T, 0.5T) = (3, 3)
8762 05:59:23.848095
8763 05:59:23.848158
8764 05:59:23.853862 [DQSOSCAuto] RK0, (LSB)MR18= 0x70b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
8765 05:59:23.857254 CH1 RK0: MR19=303, MR18=70B
8766 05:59:23.863948 CH1_RK0: MR19=0x303, MR18=0x70B, DQSOSC=404, MR23=63, INC=22, DEC=15
8767 05:59:23.864030
8768 05:59:23.867591 ----->DramcWriteLeveling(PI) begin...
8769 05:59:23.867680 ==
8770 05:59:23.870632 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 05:59:23.874297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 05:59:23.874381 ==
8773 05:59:23.877346 Write leveling (Byte 0): 25 => 25
8774 05:59:23.880952 Write leveling (Byte 1): 27 => 27
8775 05:59:23.883953 DramcWriteLeveling(PI) end<-----
8776 05:59:23.884026
8777 05:59:23.884102 ==
8778 05:59:23.887470 Dram Type= 6, Freq= 0, CH_1, rank 1
8779 05:59:23.890306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8780 05:59:23.890378 ==
8781 05:59:23.893822 [Gating] SW mode calibration
8782 05:59:23.900577 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8783 05:59:23.907204 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8784 05:59:23.910231 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 05:59:23.917315 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 05:59:23.920717 1 4 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
8787 05:59:23.923573 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8788 05:59:23.930578 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 05:59:23.933441 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 05:59:23.936817 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 05:59:23.944034 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 05:59:23.946844 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 05:59:23.950385 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8794 05:59:23.953421 1 5 8 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 1)
8795 05:59:23.960253 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8796 05:59:23.963845 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 05:59:23.966841 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 05:59:23.973823 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 05:59:23.976739 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 05:59:23.980376 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 05:59:23.987049 1 6 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
8802 05:59:23.989861 1 6 8 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8803 05:59:23.993342 1 6 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
8804 05:59:23.999876 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 05:59:24.003223 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 05:59:24.006502 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 05:59:24.013183 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 05:59:24.016765 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 05:59:24.019851 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 05:59:24.026319 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8811 05:59:24.029680 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8812 05:59:24.033411 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8813 05:59:24.039494 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 05:59:24.043079 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 05:59:24.046099 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 05:59:24.052846 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 05:59:24.056359 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 05:59:24.059425 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 05:59:24.066009 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 05:59:24.069622 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 05:59:24.072847 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 05:59:24.079367 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 05:59:24.083036 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 05:59:24.086012 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 05:59:24.092617 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8826 05:59:24.096320 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8827 05:59:24.099297 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8828 05:59:24.102665 Total UI for P1: 0, mck2ui 16
8829 05:59:24.106166 best dqsien dly found for B0: ( 1, 9, 6)
8830 05:59:24.112242 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 05:59:24.112325 Total UI for P1: 0, mck2ui 16
8832 05:59:24.118869 best dqsien dly found for B1: ( 1, 9, 10)
8833 05:59:24.122555 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8834 05:59:24.125388 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8835 05:59:24.125462
8836 05:59:24.129080 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8837 05:59:24.131995 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8838 05:59:24.135673 [Gating] SW calibration Done
8839 05:59:24.135753 ==
8840 05:59:24.139060 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 05:59:24.142494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 05:59:24.142567 ==
8843 05:59:24.145514 RX Vref Scan: 0
8844 05:59:24.145598
8845 05:59:24.145659 RX Vref 0 -> 0, step: 1
8846 05:59:24.145716
8847 05:59:24.148706 RX Delay 0 -> 252, step: 8
8848 05:59:24.152187 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8849 05:59:24.158845 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8850 05:59:24.162231 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8851 05:59:24.165303 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8852 05:59:24.168810 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8853 05:59:24.171946 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8854 05:59:24.178663 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8855 05:59:24.182165 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8856 05:59:24.185648 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8857 05:59:24.188758 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8858 05:59:24.191863 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8859 05:59:24.198635 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8860 05:59:24.201642 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8861 05:59:24.205203 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8862 05:59:24.208797 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8863 05:59:24.211641 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8864 05:59:24.214927 ==
8865 05:59:24.218254 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 05:59:24.221904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 05:59:24.221977 ==
8868 05:59:24.222039 DQS Delay:
8869 05:59:24.224911 DQS0 = 0, DQS1 = 0
8870 05:59:24.224979 DQM Delay:
8871 05:59:24.228488 DQM0 = 132, DQM1 = 128
8872 05:59:24.228566 DQ Delay:
8873 05:59:24.231391 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8874 05:59:24.234979 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =131
8875 05:59:24.238094 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8876 05:59:24.241567 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8877 05:59:24.241639
8878 05:59:24.241699
8879 05:59:24.244520 ==
8880 05:59:24.244597 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 05:59:24.251164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 05:59:24.251248 ==
8883 05:59:24.251315
8884 05:59:24.251383
8885 05:59:24.254488 TX Vref Scan disable
8886 05:59:24.254565 == TX Byte 0 ==
8887 05:59:24.258203 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8888 05:59:24.264349 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8889 05:59:24.264426 == TX Byte 1 ==
8890 05:59:24.268026 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8891 05:59:24.274926 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8892 05:59:24.275010 ==
8893 05:59:24.277892 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 05:59:24.281457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 05:59:24.281569 ==
8896 05:59:24.295032
8897 05:59:24.298265 TX Vref early break, caculate TX vref
8898 05:59:24.301450 TX Vref=16, minBit 0, minWin=23, winSum=389
8899 05:59:24.305333 TX Vref=18, minBit 0, minWin=23, winSum=397
8900 05:59:24.308316 TX Vref=20, minBit 0, minWin=24, winSum=406
8901 05:59:24.311850 TX Vref=22, minBit 0, minWin=24, winSum=410
8902 05:59:24.314694 TX Vref=24, minBit 0, minWin=25, winSum=417
8903 05:59:24.321513 TX Vref=26, minBit 0, minWin=25, winSum=426
8904 05:59:24.324808 TX Vref=28, minBit 1, minWin=25, winSum=427
8905 05:59:24.328439 TX Vref=30, minBit 1, minWin=25, winSum=422
8906 05:59:24.331489 TX Vref=32, minBit 1, minWin=24, winSum=415
8907 05:59:24.335000 TX Vref=34, minBit 0, minWin=24, winSum=408
8908 05:59:24.338020 TX Vref=36, minBit 1, minWin=23, winSum=400
8909 05:59:24.344644 [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 28
8910 05:59:24.344726
8911 05:59:24.348215 Final TX Range 0 Vref 28
8912 05:59:24.348288
8913 05:59:24.348348 ==
8914 05:59:24.351151 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 05:59:24.354831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 05:59:24.354904 ==
8917 05:59:24.354965
8918 05:59:24.358390
8919 05:59:24.358461 TX Vref Scan disable
8920 05:59:24.364640 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8921 05:59:24.364724 == TX Byte 0 ==
8922 05:59:24.368029 u2DelayCellOfst[0]=18 cells (5 PI)
8923 05:59:24.371534 u2DelayCellOfst[1]=11 cells (3 PI)
8924 05:59:24.374343 u2DelayCellOfst[2]=0 cells (0 PI)
8925 05:59:24.378021 u2DelayCellOfst[3]=7 cells (2 PI)
8926 05:59:24.381149 u2DelayCellOfst[4]=11 cells (3 PI)
8927 05:59:24.384449 u2DelayCellOfst[5]=22 cells (6 PI)
8928 05:59:24.387865 u2DelayCellOfst[6]=18 cells (5 PI)
8929 05:59:24.390965 u2DelayCellOfst[7]=7 cells (2 PI)
8930 05:59:24.394592 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8931 05:59:24.397593 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8932 05:59:24.401117 == TX Byte 1 ==
8933 05:59:24.404420 u2DelayCellOfst[8]=0 cells (0 PI)
8934 05:59:24.407885 u2DelayCellOfst[9]=7 cells (2 PI)
8935 05:59:24.410712 u2DelayCellOfst[10]=15 cells (4 PI)
8936 05:59:24.414041 u2DelayCellOfst[11]=7 cells (2 PI)
8937 05:59:24.414153 u2DelayCellOfst[12]=15 cells (4 PI)
8938 05:59:24.417371 u2DelayCellOfst[13]=18 cells (5 PI)
8939 05:59:24.420802 u2DelayCellOfst[14]=22 cells (6 PI)
8940 05:59:24.424247 u2DelayCellOfst[15]=22 cells (6 PI)
8941 05:59:24.430808 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8942 05:59:24.434412 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8943 05:59:24.434496 DramC Write-DBI on
8944 05:59:24.437361 ==
8945 05:59:24.437452 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 05:59:24.443895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 05:59:24.443977 ==
8948 05:59:24.444042
8949 05:59:24.444121
8950 05:59:24.447430 TX Vref Scan disable
8951 05:59:24.447512 == TX Byte 0 ==
8952 05:59:24.454066 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8953 05:59:24.454148 == TX Byte 1 ==
8954 05:59:24.457132 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8955 05:59:24.460693 DramC Write-DBI off
8956 05:59:24.460774
8957 05:59:24.460839 [DATLAT]
8958 05:59:24.464237 Freq=1600, CH1 RK1
8959 05:59:24.464319
8960 05:59:24.464383 DATLAT Default: 0xf
8961 05:59:24.467144 0, 0xFFFF, sum = 0
8962 05:59:24.467235 1, 0xFFFF, sum = 0
8963 05:59:24.470423 2, 0xFFFF, sum = 0
8964 05:59:24.470504 3, 0xFFFF, sum = 0
8965 05:59:24.473916 4, 0xFFFF, sum = 0
8966 05:59:24.473990 5, 0xFFFF, sum = 0
8967 05:59:24.477640 6, 0xFFFF, sum = 0
8968 05:59:24.477712 7, 0xFFFF, sum = 0
8969 05:59:24.480480 8, 0xFFFF, sum = 0
8970 05:59:24.480567 9, 0xFFFF, sum = 0
8971 05:59:24.483737 10, 0xFFFF, sum = 0
8972 05:59:24.487077 11, 0xFFFF, sum = 0
8973 05:59:24.487160 12, 0xFFFF, sum = 0
8974 05:59:24.490389 13, 0x8FFF, sum = 0
8975 05:59:24.490472 14, 0x0, sum = 1
8976 05:59:24.493750 15, 0x0, sum = 2
8977 05:59:24.493839 16, 0x0, sum = 3
8978 05:59:24.496699 17, 0x0, sum = 4
8979 05:59:24.496772 best_step = 15
8980 05:59:24.496842
8981 05:59:24.496902 ==
8982 05:59:24.500277 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 05:59:24.503820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 05:59:24.503890 ==
8985 05:59:24.506900 RX Vref Scan: 0
8986 05:59:24.506982
8987 05:59:24.509902 RX Vref 0 -> 0, step: 1
8988 05:59:24.509973
8989 05:59:24.510035 RX Delay 11 -> 252, step: 4
8990 05:59:24.517059 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8991 05:59:24.520616 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8992 05:59:24.524031 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8993 05:59:24.527417 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8994 05:59:24.530318 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8995 05:59:24.537440 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8996 05:59:24.540286 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8997 05:59:24.543953 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8998 05:59:24.546928 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
8999 05:59:24.550197 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9000 05:59:24.556963 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9001 05:59:24.560527 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9002 05:59:24.563565 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9003 05:59:24.566600 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9004 05:59:24.573821 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9005 05:59:24.577273 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9006 05:59:24.577354 ==
9007 05:59:24.580189 Dram Type= 6, Freq= 0, CH_1, rank 1
9008 05:59:24.583884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9009 05:59:24.583966 ==
9010 05:59:24.586733 DQS Delay:
9011 05:59:24.586837 DQS0 = 0, DQS1 = 0
9012 05:59:24.586918 DQM Delay:
9013 05:59:24.589982 DQM0 = 130, DQM1 = 125
9014 05:59:24.590053 DQ Delay:
9015 05:59:24.593404 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =128
9016 05:59:24.596858 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =128
9017 05:59:24.600192 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =120
9018 05:59:24.606785 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9019 05:59:24.606892
9020 05:59:24.606986
9021 05:59:24.607084
9022 05:59:24.609657 [DramC_TX_OE_Calibration] TA2
9023 05:59:24.613392 Original DQ_B0 (3 6) =30, OEN = 27
9024 05:59:24.613542 Original DQ_B1 (3 6) =30, OEN = 27
9025 05:59:24.616293 24, 0x0, End_B0=24 End_B1=24
9026 05:59:24.619813 25, 0x0, End_B0=25 End_B1=25
9027 05:59:24.623245 26, 0x0, End_B0=26 End_B1=26
9028 05:59:24.626162 27, 0x0, End_B0=27 End_B1=27
9029 05:59:24.626244 28, 0x0, End_B0=28 End_B1=28
9030 05:59:24.629589 29, 0x0, End_B0=29 End_B1=29
9031 05:59:24.633165 30, 0x0, End_B0=30 End_B1=30
9032 05:59:24.636635 31, 0x4141, End_B0=30 End_B1=30
9033 05:59:24.640074 Byte0 end_step=30 best_step=27
9034 05:59:24.640155 Byte1 end_step=30 best_step=27
9035 05:59:24.643406 Byte0 TX OE(2T, 0.5T) = (3, 3)
9036 05:59:24.646506 Byte1 TX OE(2T, 0.5T) = (3, 3)
9037 05:59:24.646587
9038 05:59:24.646652
9039 05:59:24.656271 [DQSOSCAuto] RK1, (LSB)MR18= 0x101b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
9040 05:59:24.656362 CH1 RK1: MR19=303, MR18=101B
9041 05:59:24.663013 CH1_RK1: MR19=0x303, MR18=0x101B, DQSOSC=396, MR23=63, INC=23, DEC=15
9042 05:59:24.666408 [RxdqsGatingPostProcess] freq 1600
9043 05:59:24.673007 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9044 05:59:24.676532 best DQS0 dly(2T, 0.5T) = (1, 1)
9045 05:59:24.679636 best DQS1 dly(2T, 0.5T) = (1, 1)
9046 05:59:24.683194 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9047 05:59:24.686213 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9048 05:59:24.686294 best DQS0 dly(2T, 0.5T) = (1, 1)
9049 05:59:24.689725 best DQS1 dly(2T, 0.5T) = (1, 1)
9050 05:59:24.693246 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9051 05:59:24.696526 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9052 05:59:24.699404 Pre-setting of DQS Precalculation
9053 05:59:24.706378 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9054 05:59:24.712991 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9055 05:59:24.719647 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9056 05:59:24.719730
9057 05:59:24.719795
9058 05:59:24.722601 [Calibration Summary] 3200 Mbps
9059 05:59:24.722683 CH 0, Rank 0
9060 05:59:24.726116 SW Impedance : PASS
9061 05:59:24.729452 DUTY Scan : NO K
9062 05:59:24.729559 ZQ Calibration : PASS
9063 05:59:24.732883 Jitter Meter : NO K
9064 05:59:24.735766 CBT Training : PASS
9065 05:59:24.735848 Write leveling : PASS
9066 05:59:24.739122 RX DQS gating : PASS
9067 05:59:24.742723 RX DQ/DQS(RDDQC) : PASS
9068 05:59:24.742804 TX DQ/DQS : PASS
9069 05:59:24.746315 RX DATLAT : PASS
9070 05:59:24.749264 RX DQ/DQS(Engine): PASS
9071 05:59:24.749345 TX OE : PASS
9072 05:59:24.749410 All Pass.
9073 05:59:24.752707
9074 05:59:24.752787 CH 0, Rank 1
9075 05:59:24.755970 SW Impedance : PASS
9076 05:59:24.756077 DUTY Scan : NO K
9077 05:59:24.759111 ZQ Calibration : PASS
9078 05:59:24.759192 Jitter Meter : NO K
9079 05:59:24.762441 CBT Training : PASS
9080 05:59:24.766172 Write leveling : PASS
9081 05:59:24.766262 RX DQS gating : PASS
9082 05:59:24.769198 RX DQ/DQS(RDDQC) : PASS
9083 05:59:24.772733 TX DQ/DQS : PASS
9084 05:59:24.772826 RX DATLAT : PASS
9085 05:59:24.776257 RX DQ/DQS(Engine): PASS
9086 05:59:24.779157 TX OE : PASS
9087 05:59:24.779272 All Pass.
9088 05:59:24.779367
9089 05:59:24.779466 CH 1, Rank 0
9090 05:59:24.782644 SW Impedance : PASS
9091 05:59:24.786188 DUTY Scan : NO K
9092 05:59:24.786297 ZQ Calibration : PASS
9093 05:59:24.788999 Jitter Meter : NO K
9094 05:59:24.792599 CBT Training : PASS
9095 05:59:24.792699 Write leveling : PASS
9096 05:59:24.795637 RX DQS gating : PASS
9097 05:59:24.799106 RX DQ/DQS(RDDQC) : PASS
9098 05:59:24.799207 TX DQ/DQS : PASS
9099 05:59:24.802536 RX DATLAT : PASS
9100 05:59:24.805983 RX DQ/DQS(Engine): PASS
9101 05:59:24.806060 TX OE : PASS
9102 05:59:24.806122 All Pass.
9103 05:59:24.806182
9104 05:59:24.808833 CH 1, Rank 1
9105 05:59:24.812188 SW Impedance : PASS
9106 05:59:24.812287 DUTY Scan : NO K
9107 05:59:24.815830 ZQ Calibration : PASS
9108 05:59:24.815905 Jitter Meter : NO K
9109 05:59:24.818777 CBT Training : PASS
9110 05:59:24.822242 Write leveling : PASS
9111 05:59:24.822343 RX DQS gating : PASS
9112 05:59:24.825332 RX DQ/DQS(RDDQC) : PASS
9113 05:59:24.828909 TX DQ/DQS : PASS
9114 05:59:24.829023 RX DATLAT : PASS
9115 05:59:24.831893 RX DQ/DQS(Engine): PASS
9116 05:59:24.835238 TX OE : PASS
9117 05:59:24.835360 All Pass.
9118 05:59:24.835461
9119 05:59:24.838669 DramC Write-DBI on
9120 05:59:24.838770 PER_BANK_REFRESH: Hybrid Mode
9121 05:59:24.841992 TX_TRACKING: ON
9122 05:59:24.852211 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9123 05:59:24.858811 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9124 05:59:24.865220 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9125 05:59:24.868407 [FAST_K] Save calibration result to emmc
9126 05:59:24.871932 sync common calibartion params.
9127 05:59:24.875052 sync cbt_mode0:1, 1:1
9128 05:59:24.875153 dram_init: ddr_geometry: 2
9129 05:59:24.878616 dram_init: ddr_geometry: 2
9130 05:59:24.881965 dram_init: ddr_geometry: 2
9131 05:59:24.885320 0:dram_rank_size:100000000
9132 05:59:24.885425 1:dram_rank_size:100000000
9133 05:59:24.891589 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9134 05:59:24.895162 DFS_SHUFFLE_HW_MODE: ON
9135 05:59:24.898696 dramc_set_vcore_voltage set vcore to 725000
9136 05:59:24.898819 Read voltage for 1600, 0
9137 05:59:24.901653 Vio18 = 0
9138 05:59:24.901757 Vcore = 725000
9139 05:59:24.901847 Vdram = 0
9140 05:59:24.905191 Vddq = 0
9141 05:59:24.905291 Vmddr = 0
9142 05:59:24.908607 switch to 3200 Mbps bootup
9143 05:59:24.908681 [DramcRunTimeConfig]
9144 05:59:24.911669 PHYPLL
9145 05:59:24.911741 DPM_CONTROL_AFTERK: ON
9146 05:59:24.915193 PER_BANK_REFRESH: ON
9147 05:59:24.918648 REFRESH_OVERHEAD_REDUCTION: ON
9148 05:59:24.918728 CMD_PICG_NEW_MODE: OFF
9149 05:59:24.921911 XRTWTW_NEW_MODE: ON
9150 05:59:24.922018 XRTRTR_NEW_MODE: ON
9151 05:59:24.925002 TX_TRACKING: ON
9152 05:59:24.925097 RDSEL_TRACKING: OFF
9153 05:59:24.928599 DQS Precalculation for DVFS: ON
9154 05:59:24.931516 RX_TRACKING: OFF
9155 05:59:24.931619 HW_GATING DBG: ON
9156 05:59:24.935155 ZQCS_ENABLE_LP4: ON
9157 05:59:24.935228 RX_PICG_NEW_MODE: ON
9158 05:59:24.938241 TX_PICG_NEW_MODE: ON
9159 05:59:24.938312 ENABLE_RX_DCM_DPHY: ON
9160 05:59:24.941721 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9161 05:59:24.945033 DUMMY_READ_FOR_TRACKING: OFF
9162 05:59:24.948307 !!! SPM_CONTROL_AFTERK: OFF
9163 05:59:24.951544 !!! SPM could not control APHY
9164 05:59:24.951671 IMPEDANCE_TRACKING: ON
9165 05:59:24.955179 TEMP_SENSOR: ON
9166 05:59:24.955277 HW_SAVE_FOR_SR: OFF
9167 05:59:24.958140 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9168 05:59:24.961224 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9169 05:59:24.964770 Read ODT Tracking: ON
9170 05:59:24.967877 Refresh Rate DeBounce: ON
9171 05:59:24.967976 DFS_NO_QUEUE_FLUSH: ON
9172 05:59:24.971561 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9173 05:59:24.975036 ENABLE_DFS_RUNTIME_MRW: OFF
9174 05:59:24.977873 DDR_RESERVE_NEW_MODE: ON
9175 05:59:24.977972 MR_CBT_SWITCH_FREQ: ON
9176 05:59:24.981193 =========================
9177 05:59:25.000045 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9178 05:59:25.003069 dram_init: ddr_geometry: 2
9179 05:59:25.021810 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9180 05:59:25.024711 dram_init: dram init end (result: 0)
9181 05:59:25.031518 DRAM-K: Full calibration passed in 24626 msecs
9182 05:59:25.035169 MRC: failed to locate region type 0.
9183 05:59:25.035271 DRAM rank0 size:0x100000000,
9184 05:59:25.038001 DRAM rank1 size=0x100000000
9185 05:59:25.048378 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9186 05:59:25.054765 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9187 05:59:25.061289 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9188 05:59:25.067717 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9189 05:59:25.071312 DRAM rank0 size:0x100000000,
9190 05:59:25.074368 DRAM rank1 size=0x100000000
9191 05:59:25.074464 CBMEM:
9192 05:59:25.077905 IMD: root @ 0xfffff000 254 entries.
9193 05:59:25.080879 IMD: root @ 0xffffec00 62 entries.
9194 05:59:25.084438 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9195 05:59:25.090766 WARNING: RO_VPD is uninitialized or empty.
9196 05:59:25.094013 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9197 05:59:25.101461 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9198 05:59:25.114262 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9199 05:59:25.125857 BS: romstage times (exec / console): total (unknown) / 24082 ms
9200 05:59:25.125940
9201 05:59:25.126035
9202 05:59:25.135839 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9203 05:59:25.138901 ARM64: Exception handlers installed.
9204 05:59:25.141886 ARM64: Testing exception
9205 05:59:25.145426 ARM64: Done test exception
9206 05:59:25.145552 Enumerating buses...
9207 05:59:25.148953 Show all devs... Before device enumeration.
9208 05:59:25.152415 Root Device: enabled 1
9209 05:59:25.155377 CPU_CLUSTER: 0: enabled 1
9210 05:59:25.155457 CPU: 00: enabled 1
9211 05:59:25.158392 Compare with tree...
9212 05:59:25.158476 Root Device: enabled 1
9213 05:59:25.161858 CPU_CLUSTER: 0: enabled 1
9214 05:59:25.165263 CPU: 00: enabled 1
9215 05:59:25.165343 Root Device scanning...
9216 05:59:25.168650 scan_static_bus for Root Device
9217 05:59:25.171884 CPU_CLUSTER: 0 enabled
9218 05:59:25.175309 scan_static_bus for Root Device done
9219 05:59:25.178236 scan_bus: bus Root Device finished in 8 msecs
9220 05:59:25.178316 done
9221 05:59:25.184860 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9222 05:59:25.188506 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9223 05:59:25.194879 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9224 05:59:25.198156 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9225 05:59:25.201536 Allocating resources...
9226 05:59:25.205206 Reading resources...
9227 05:59:25.208066 Root Device read_resources bus 0 link: 0
9228 05:59:25.211620 DRAM rank0 size:0x100000000,
9229 05:59:25.211702 DRAM rank1 size=0x100000000
9230 05:59:25.214910 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9231 05:59:25.218193 CPU: 00 missing read_resources
9232 05:59:25.224581 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9233 05:59:25.228284 Root Device read_resources bus 0 link: 0 done
9234 05:59:25.228388 Done reading resources.
9235 05:59:25.235078 Show resources in subtree (Root Device)...After reading.
9236 05:59:25.237924 Root Device child on link 0 CPU_CLUSTER: 0
9237 05:59:25.241308 CPU_CLUSTER: 0 child on link 0 CPU: 00
9238 05:59:25.251386 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9239 05:59:25.251485 CPU: 00
9240 05:59:25.254328 Root Device assign_resources, bus 0 link: 0
9241 05:59:25.257886 CPU_CLUSTER: 0 missing set_resources
9242 05:59:25.264596 Root Device assign_resources, bus 0 link: 0 done
9243 05:59:25.264681 Done setting resources.
9244 05:59:25.270998 Show resources in subtree (Root Device)...After assigning values.
9245 05:59:25.274514 Root Device child on link 0 CPU_CLUSTER: 0
9246 05:59:25.277468 CPU_CLUSTER: 0 child on link 0 CPU: 00
9247 05:59:25.287181 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9248 05:59:25.287300 CPU: 00
9249 05:59:25.290949 Done allocating resources.
9250 05:59:25.297436 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9251 05:59:25.297563 Enabling resources...
9252 05:59:25.297662 done.
9253 05:59:25.303807 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9254 05:59:25.307255 Initializing devices...
9255 05:59:25.307384 Root Device init
9256 05:59:25.310832 init hardware done!
9257 05:59:25.310917 0x00000018: ctrlr->caps
9258 05:59:25.313804 52.000 MHz: ctrlr->f_max
9259 05:59:25.317397 0.400 MHz: ctrlr->f_min
9260 05:59:25.317532 0x40ff8080: ctrlr->voltages
9261 05:59:25.320243 sclk: 390625
9262 05:59:25.320327 Bus Width = 1
9263 05:59:25.320395 sclk: 390625
9264 05:59:25.323843 Bus Width = 1
9265 05:59:25.327114 Early init status = 3
9266 05:59:25.330538 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9267 05:59:25.334404 in-header: 03 fc 00 00 01 00 00 00
9268 05:59:25.337764 in-data: 00
9269 05:59:25.341086 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9270 05:59:25.346135 in-header: 03 fd 00 00 00 00 00 00
9271 05:59:25.349739 in-data:
9272 05:59:25.353054 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9273 05:59:25.357277 in-header: 03 fc 00 00 01 00 00 00
9274 05:59:25.360692 in-data: 00
9275 05:59:25.363778 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9276 05:59:25.369678 in-header: 03 fd 00 00 00 00 00 00
9277 05:59:25.372711 in-data:
9278 05:59:25.376175 [SSUSB] Setting up USB HOST controller...
9279 05:59:25.379709 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9280 05:59:25.382603 [SSUSB] phy power-on done.
9281 05:59:25.386099 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9282 05:59:25.392810 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9283 05:59:25.395912 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9284 05:59:25.402528 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9285 05:59:25.409249 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9286 05:59:25.415718 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9287 05:59:25.422662 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9288 05:59:25.429029 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9289 05:59:25.432516 SPM: binary array size = 0x9dc
9290 05:59:25.435799 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9291 05:59:25.442336 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9292 05:59:25.448970 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9293 05:59:25.452270 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9294 05:59:25.459212 configure_display: Starting display init
9295 05:59:25.492943 anx7625_power_on_init: Init interface.
9296 05:59:25.495751 anx7625_disable_pd_protocol: Disabled PD feature.
9297 05:59:25.499329 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9298 05:59:25.527200 anx7625_start_dp_work: Secure OCM version=00
9299 05:59:25.530182 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9300 05:59:25.545092 sp_tx_get_edid_block: EDID Block = 1
9301 05:59:25.648092 Extracted contents:
9302 05:59:25.650988 header: 00 ff ff ff ff ff ff 00
9303 05:59:25.654585 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9304 05:59:25.657732 version: 01 04
9305 05:59:25.661244 basic params: 95 1f 11 78 0a
9306 05:59:25.664073 chroma info: 76 90 94 55 54 90 27 21 50 54
9307 05:59:25.667608 established: 00 00 00
9308 05:59:25.674030 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9309 05:59:25.677254 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9310 05:59:25.683856 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9311 05:59:25.690809 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9312 05:59:25.696928 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9313 05:59:25.700389 extensions: 00
9314 05:59:25.700470 checksum: fb
9315 05:59:25.700533
9316 05:59:25.703987 Manufacturer: IVO Model 57d Serial Number 0
9317 05:59:25.707206 Made week 0 of 2020
9318 05:59:25.710723 EDID version: 1.4
9319 05:59:25.710813 Digital display
9320 05:59:25.713604 6 bits per primary color channel
9321 05:59:25.713707 DisplayPort interface
9322 05:59:25.717028 Maximum image size: 31 cm x 17 cm
9323 05:59:25.720703 Gamma: 220%
9324 05:59:25.720810 Check DPMS levels
9325 05:59:25.723564 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9326 05:59:25.730488 First detailed timing is preferred timing
9327 05:59:25.730596 Established timings supported:
9328 05:59:25.733891 Standard timings supported:
9329 05:59:25.736710 Detailed timings
9330 05:59:25.740276 Hex of detail: 383680a07038204018303c0035ae10000019
9331 05:59:25.747228 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9332 05:59:25.749999 0780 0798 07c8 0820 hborder 0
9333 05:59:25.753448 0438 043b 0447 0458 vborder 0
9334 05:59:25.757225 -hsync -vsync
9335 05:59:25.757307 Did detailed timing
9336 05:59:25.763824 Hex of detail: 000000000000000000000000000000000000
9337 05:59:25.766653 Manufacturer-specified data, tag 0
9338 05:59:25.770218 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9339 05:59:25.773153 ASCII string: InfoVision
9340 05:59:25.776445 Hex of detail: 000000fe00523134304e574635205248200a
9341 05:59:25.779892 ASCII string: R140NWF5 RH
9342 05:59:25.780000 Checksum
9343 05:59:25.783234 Checksum: 0xfb (valid)
9344 05:59:25.786301 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9345 05:59:25.789437 DSI data_rate: 832800000 bps
9346 05:59:25.796437 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9347 05:59:25.799382 anx7625_parse_edid: pixelclock(138800).
9348 05:59:25.803140 hactive(1920), hsync(48), hfp(24), hbp(88)
9349 05:59:25.806218 vactive(1080), vsync(12), vfp(3), vbp(17)
9350 05:59:25.809753 anx7625_dsi_config: config dsi.
9351 05:59:25.816519 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9352 05:59:25.829628 anx7625_dsi_config: success to config DSI
9353 05:59:25.832954 anx7625_dp_start: MIPI phy setup OK.
9354 05:59:25.836616 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9355 05:59:25.839511 mtk_ddp_mode_set invalid vrefresh 60
9356 05:59:25.843082 main_disp_path_setup
9357 05:59:25.843191 ovl_layer_smi_id_en
9358 05:59:25.846261 ovl_layer_smi_id_en
9359 05:59:25.846337 ccorr_config
9360 05:59:25.846399 aal_config
9361 05:59:25.849685 gamma_config
9362 05:59:25.849757 postmask_config
9363 05:59:25.852621 dither_config
9364 05:59:25.855839 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9365 05:59:25.862621 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9366 05:59:25.866232 Root Device init finished in 555 msecs
9367 05:59:25.869133 CPU_CLUSTER: 0 init
9368 05:59:25.875614 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9369 05:59:25.882698 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9370 05:59:25.882779 APU_MBOX 0x190000b0 = 0x10001
9371 05:59:25.885556 APU_MBOX 0x190001b0 = 0x10001
9372 05:59:25.888952 APU_MBOX 0x190005b0 = 0x10001
9373 05:59:25.892270 APU_MBOX 0x190006b0 = 0x10001
9374 05:59:25.898893 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9375 05:59:25.908493 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9376 05:59:25.921276 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9377 05:59:25.927822 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9378 05:59:25.939536 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9379 05:59:25.948734 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9380 05:59:25.951623 CPU_CLUSTER: 0 init finished in 81 msecs
9381 05:59:25.954980 Devices initialized
9382 05:59:25.958433 Show all devs... After init.
9383 05:59:25.958515 Root Device: enabled 1
9384 05:59:25.961996 CPU_CLUSTER: 0: enabled 1
9385 05:59:25.964916 CPU: 00: enabled 1
9386 05:59:25.968307 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9387 05:59:25.971955 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9388 05:59:25.974777 ELOG: NV offset 0x57f000 size 0x1000
9389 05:59:25.981920 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9390 05:59:25.988772 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9391 05:59:25.991801 ELOG: Event(17) added with size 13 at 2023-12-25 05:59:25 UTC
9392 05:59:25.998019 out: cmd=0x121: 03 db 21 01 00 00 00 00
9393 05:59:26.001291 in-header: 03 21 00 00 2c 00 00 00
9394 05:59:26.011024 in-data: 3d 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9395 05:59:26.017760 ELOG: Event(A1) added with size 10 at 2023-12-25 05:59:26 UTC
9396 05:59:26.024339 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9397 05:59:26.031073 ELOG: Event(A0) added with size 9 at 2023-12-25 05:59:26 UTC
9398 05:59:26.034663 elog_add_boot_reason: Logged dev mode boot
9399 05:59:26.040981 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9400 05:59:26.041064 Finalize devices...
9401 05:59:26.044294 Devices finalized
9402 05:59:26.047520 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9403 05:59:26.050913 Writing coreboot table at 0xffe64000
9404 05:59:26.054081 0. 000000000010a000-0000000000113fff: RAMSTAGE
9405 05:59:26.061205 1. 0000000040000000-00000000400fffff: RAM
9406 05:59:26.064237 2. 0000000040100000-000000004032afff: RAMSTAGE
9407 05:59:26.067425 3. 000000004032b000-00000000545fffff: RAM
9408 05:59:26.071084 4. 0000000054600000-000000005465ffff: BL31
9409 05:59:26.074251 5. 0000000054660000-00000000ffe63fff: RAM
9410 05:59:26.080766 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9411 05:59:26.084330 7. 0000000100000000-000000023fffffff: RAM
9412 05:59:26.087850 Passing 5 GPIOs to payload:
9413 05:59:26.090669 NAME | PORT | POLARITY | VALUE
9414 05:59:26.097291 EC in RW | 0x000000aa | low | undefined
9415 05:59:26.100868 EC interrupt | 0x00000005 | low | undefined
9416 05:59:26.104290 TPM interrupt | 0x000000ab | high | undefined
9417 05:59:26.110405 SD card detect | 0x00000011 | high | undefined
9418 05:59:26.114154 speaker enable | 0x00000093 | high | undefined
9419 05:59:26.117060 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9420 05:59:26.120572 in-header: 03 f9 00 00 02 00 00 00
9421 05:59:26.123604 in-data: 02 00
9422 05:59:26.127351 ADC[4]: Raw value=894821 ID=7
9423 05:59:26.127434 ADC[3]: Raw value=212700 ID=1
9424 05:59:26.130336 RAM Code: 0x71
9425 05:59:26.133961 ADC[6]: Raw value=74722 ID=0
9426 05:59:26.134043 ADC[5]: Raw value=212330 ID=1
9427 05:59:26.136856 SKU Code: 0x1
9428 05:59:26.140462 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4d57
9429 05:59:26.144053 coreboot table: 964 bytes.
9430 05:59:26.146945 IMD ROOT 0. 0xfffff000 0x00001000
9431 05:59:26.150491 IMD SMALL 1. 0xffffe000 0x00001000
9432 05:59:26.153463 RO MCACHE 2. 0xffffc000 0x00001104
9433 05:59:26.156864 CONSOLE 3. 0xfff7c000 0x00080000
9434 05:59:26.160553 FMAP 4. 0xfff7b000 0x00000452
9435 05:59:26.163602 TIME STAMP 5. 0xfff7a000 0x00000910
9436 05:59:26.166962 VBOOT WORK 6. 0xfff66000 0x00014000
9437 05:59:26.170526 RAMOOPS 7. 0xffe66000 0x00100000
9438 05:59:26.173858 COREBOOT 8. 0xffe64000 0x00002000
9439 05:59:26.177033 IMD small region:
9440 05:59:26.180120 IMD ROOT 0. 0xffffec00 0x00000400
9441 05:59:26.183900 VPD 1. 0xffffeb80 0x0000006c
9442 05:59:26.186676 MMC STATUS 2. 0xffffeb60 0x00000004
9443 05:59:26.190216 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9444 05:59:26.193359 Probing TPM: done!
9445 05:59:26.197539 Connected to device vid:did:rid of 1ae0:0028:00
9446 05:59:26.207803 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9447 05:59:26.210690 Initialized TPM device CR50 revision 0
9448 05:59:26.214244 Checking cr50 for pending updates
9449 05:59:26.218768 Reading cr50 TPM mode
9450 05:59:26.227029 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9451 05:59:26.233658 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9452 05:59:26.273929 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9453 05:59:26.277283 Checking segment from ROM address 0x40100000
9454 05:59:26.280462 Checking segment from ROM address 0x4010001c
9455 05:59:26.287185 Loading segment from ROM address 0x40100000
9456 05:59:26.287268 code (compression=0)
9457 05:59:26.297116 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9458 05:59:26.303685 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9459 05:59:26.303784 it's not compressed!
9460 05:59:26.310254 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9461 05:59:26.313847 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9462 05:59:26.334201 Loading segment from ROM address 0x4010001c
9463 05:59:26.334286 Entry Point 0x80000000
9464 05:59:26.337523 Loaded segments
9465 05:59:26.341026 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9466 05:59:26.347615 Jumping to boot code at 0x80000000(0xffe64000)
9467 05:59:26.353693 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9468 05:59:26.360930 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9469 05:59:26.368605 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9470 05:59:26.371942 Checking segment from ROM address 0x40100000
9471 05:59:26.375532 Checking segment from ROM address 0x4010001c
9472 05:59:26.381701 Loading segment from ROM address 0x40100000
9473 05:59:26.381783 code (compression=1)
9474 05:59:26.388373 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9475 05:59:26.398278 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9476 05:59:26.398362 using LZMA
9477 05:59:26.406698 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9478 05:59:26.413408 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9479 05:59:26.417213 Loading segment from ROM address 0x4010001c
9480 05:59:26.417295 Entry Point 0x54601000
9481 05:59:26.420192 Loaded segments
9482 05:59:26.423765 NOTICE: MT8192 bl31_setup
9483 05:59:26.430280 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9484 05:59:26.434042 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9485 05:59:26.436945 WARNING: region 0:
9486 05:59:26.440319 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 05:59:26.440419 WARNING: region 1:
9488 05:59:26.446922 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9489 05:59:26.450228 WARNING: region 2:
9490 05:59:26.453661 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9491 05:59:26.457282 WARNING: region 3:
9492 05:59:26.460225 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9493 05:59:26.463858 WARNING: region 4:
9494 05:59:26.470141 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9495 05:59:26.470223 WARNING: region 5:
9496 05:59:26.473779 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 05:59:26.477196 WARNING: region 6:
9498 05:59:26.480397 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 05:59:26.483976 WARNING: region 7:
9500 05:59:26.486784 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 05:59:26.493851 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9502 05:59:26.496727 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9503 05:59:26.500373 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9504 05:59:26.507079 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9505 05:59:26.510461 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9506 05:59:26.513915 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9507 05:59:26.520344 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9508 05:59:26.523734 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9509 05:59:26.530436 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9510 05:59:26.534101 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9511 05:59:26.536939 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9512 05:59:26.543647 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9513 05:59:26.547157 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9514 05:59:26.550274 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9515 05:59:26.556722 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9516 05:59:26.560559 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9517 05:59:26.566717 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9518 05:59:26.570476 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9519 05:59:26.573549 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9520 05:59:26.580574 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9521 05:59:26.583628 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9522 05:59:26.587158 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9523 05:59:26.593710 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9524 05:59:26.597300 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9525 05:59:26.603796 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9526 05:59:26.607095 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9527 05:59:26.610455 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9528 05:59:26.617115 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9529 05:59:26.620077 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9530 05:59:26.626654 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9531 05:59:26.630301 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9532 05:59:26.633330 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9533 05:59:26.640465 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9534 05:59:26.643392 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9535 05:59:26.647033 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9536 05:59:26.650570 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9537 05:59:26.657230 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9538 05:59:26.660176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9539 05:59:26.663920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9540 05:59:26.666880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9541 05:59:26.673528 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9542 05:59:26.676894 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9543 05:59:26.679910 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9544 05:59:26.683494 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9545 05:59:26.690095 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9546 05:59:26.693429 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9547 05:59:26.697078 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9548 05:59:26.699937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9549 05:59:26.706703 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9550 05:59:26.709750 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9551 05:59:26.716628 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9552 05:59:26.719717 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9553 05:59:26.726810 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9554 05:59:26.729606 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9555 05:59:26.733048 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9556 05:59:26.739883 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9557 05:59:26.743020 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9558 05:59:26.749852 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9559 05:59:26.753425 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9560 05:59:26.759663 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9561 05:59:26.763270 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9562 05:59:26.769391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9563 05:59:26.773076 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9564 05:59:26.776146 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9565 05:59:26.783016 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9566 05:59:26.786139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9567 05:59:26.793085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9568 05:59:26.796577 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9569 05:59:26.803202 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9570 05:59:26.806211 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9571 05:59:26.809714 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9572 05:59:26.816153 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9573 05:59:26.819755 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9574 05:59:26.826374 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9575 05:59:26.829883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9576 05:59:26.836047 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9577 05:59:26.839386 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9578 05:59:26.842906 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9579 05:59:26.849887 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9580 05:59:26.852684 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9581 05:59:26.859530 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9582 05:59:26.863005 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9583 05:59:26.869876 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9584 05:59:26.872820 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9585 05:59:26.876547 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9586 05:59:26.882704 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9587 05:59:26.886173 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9588 05:59:26.892708 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9589 05:59:26.896126 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9590 05:59:26.903108 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9591 05:59:26.906049 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9592 05:59:26.909670 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9593 05:59:26.916221 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9594 05:59:26.919593 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9595 05:59:26.926214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9596 05:59:26.929654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9597 05:59:26.936423 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9598 05:59:26.939944 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9599 05:59:26.942885 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9600 05:59:26.946384 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9601 05:59:26.949669 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9602 05:59:26.956435 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9603 05:59:26.959635 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9604 05:59:26.966443 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9605 05:59:26.969625 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9606 05:59:26.973029 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9607 05:59:26.979734 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9608 05:59:26.983311 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9609 05:59:26.989803 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9610 05:59:26.992862 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9611 05:59:26.996405 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9612 05:59:27.003197 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9613 05:59:27.006211 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9614 05:59:27.013165 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9615 05:59:27.016489 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9616 05:59:27.019673 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9617 05:59:27.026231 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9618 05:59:27.029851 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9619 05:59:27.032839 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9620 05:59:27.039567 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9621 05:59:27.042992 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9622 05:59:27.046520 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9623 05:59:27.050071 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9624 05:59:27.056554 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9625 05:59:27.059456 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9626 05:59:27.063027 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9627 05:59:27.069217 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9628 05:59:27.072787 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9629 05:59:27.079724 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9630 05:59:27.082942 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9631 05:59:27.086223 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9632 05:59:27.093008 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9633 05:59:27.096152 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9634 05:59:27.099727 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9635 05:59:27.106450 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9636 05:59:27.109393 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9637 05:59:27.116144 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9638 05:59:27.119646 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9639 05:59:27.122663 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9640 05:59:27.129924 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9641 05:59:27.133118 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9642 05:59:27.139327 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9643 05:59:27.142912 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9644 05:59:27.146397 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9645 05:59:27.152813 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9646 05:59:27.156392 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9647 05:59:27.159305 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9648 05:59:27.165857 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9649 05:59:27.169554 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9650 05:59:27.176190 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9651 05:59:27.179219 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9652 05:59:27.182591 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9653 05:59:27.189423 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9654 05:59:27.192741 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9655 05:59:27.199416 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9656 05:59:27.202496 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9657 05:59:27.206209 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9658 05:59:27.212776 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9659 05:59:27.215763 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9660 05:59:27.219264 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9661 05:59:27.225980 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9662 05:59:27.229105 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9663 05:59:27.236321 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9664 05:59:27.239361 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9665 05:59:27.242705 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9666 05:59:27.249210 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9667 05:59:27.252720 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9668 05:59:27.259227 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9669 05:59:27.262273 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9670 05:59:27.265660 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9671 05:59:27.272409 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9672 05:59:27.275939 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9673 05:59:27.281913 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9674 05:59:27.285384 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9675 05:59:27.288757 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9676 05:59:27.295211 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9677 05:59:27.298871 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9678 05:59:27.305037 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9679 05:59:27.308878 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9680 05:59:27.311947 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9681 05:59:27.318523 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9682 05:59:27.321618 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9683 05:59:27.328247 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9684 05:59:27.331689 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9685 05:59:27.334732 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9686 05:59:27.341757 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9687 05:59:27.344706 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9688 05:59:27.352017 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9689 05:59:27.354985 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9690 05:59:27.357996 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9691 05:59:27.364633 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9692 05:59:27.368360 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9693 05:59:27.374743 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9694 05:59:27.378308 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9695 05:59:27.384564 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9696 05:59:27.387780 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9697 05:59:27.391574 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9698 05:59:27.397932 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9699 05:59:27.401352 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9700 05:59:27.408241 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9701 05:59:27.411127 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9702 05:59:27.414353 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9703 05:59:27.421265 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9704 05:59:27.424912 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9705 05:59:27.430949 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9706 05:59:27.434393 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9707 05:59:27.441276 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9708 05:59:27.444255 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9709 05:59:27.447759 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9710 05:59:27.454162 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9711 05:59:27.457871 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9712 05:59:27.463944 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9713 05:59:27.467454 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9714 05:59:27.474008 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9715 05:59:27.477509 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9716 05:59:27.480698 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9717 05:59:27.487453 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9718 05:59:27.490849 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9719 05:59:27.497111 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9720 05:59:27.500322 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9721 05:59:27.504239 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9722 05:59:27.510569 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9723 05:59:27.513649 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9724 05:59:27.520504 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9725 05:59:27.523840 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9726 05:59:27.530222 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9727 05:59:27.533838 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9728 05:59:27.536821 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9729 05:59:27.543483 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9730 05:59:27.547071 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9731 05:59:27.550117 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9732 05:59:27.553760 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9733 05:59:27.560212 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9734 05:59:27.563718 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9735 05:59:27.566705 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9736 05:59:27.573298 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9737 05:59:27.576814 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9738 05:59:27.583462 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9739 05:59:27.586499 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9740 05:59:27.590060 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9741 05:59:27.596746 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9742 05:59:27.599729 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9743 05:59:27.603135 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9744 05:59:27.609996 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9745 05:59:27.612885 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9746 05:59:27.616381 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9747 05:59:27.622892 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9748 05:59:27.626419 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9749 05:59:27.629850 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9750 05:59:27.636284 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9751 05:59:27.639721 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9752 05:59:27.645919 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9753 05:59:27.649611 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9754 05:59:27.652639 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9755 05:59:27.659169 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9756 05:59:27.662616 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9757 05:59:27.669321 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9758 05:59:27.672387 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9759 05:59:27.675923 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9760 05:59:27.682371 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9761 05:59:27.685891 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9762 05:59:27.689012 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9763 05:59:27.695695 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9764 05:59:27.699257 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9765 05:59:27.702133 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9766 05:59:27.709125 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9767 05:59:27.712512 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9768 05:59:27.719098 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9769 05:59:27.722372 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9770 05:59:27.725601 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9771 05:59:27.729135 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9772 05:59:27.735776 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9773 05:59:27.738790 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9774 05:59:27.742137 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9775 05:59:27.745347 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9776 05:59:27.749290 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9777 05:59:27.755565 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9778 05:59:27.758566 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9779 05:59:27.762196 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9780 05:59:27.765164 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9781 05:59:27.772216 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9782 05:59:27.775304 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9783 05:59:27.778923 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9784 05:59:27.785372 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9785 05:59:27.788448 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9786 05:59:27.794995 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9787 05:59:27.798584 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9788 05:59:27.805142 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9789 05:59:27.808568 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9790 05:59:27.811591 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9791 05:59:27.818221 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9792 05:59:27.821745 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9793 05:59:27.828834 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9794 05:59:27.831618 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9795 05:59:27.838351 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9796 05:59:27.841425 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9797 05:59:27.844943 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9798 05:59:27.851663 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9799 05:59:27.854751 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9800 05:59:27.861713 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9801 05:59:27.864956 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9802 05:59:27.868060 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9803 05:59:27.874651 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9804 05:59:27.878093 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9805 05:59:27.884652 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9806 05:59:27.888064 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9807 05:59:27.891659 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9808 05:59:27.897956 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9809 05:59:27.900992 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9810 05:59:27.907467 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9811 05:59:27.911173 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9812 05:59:27.917309 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9813 05:59:27.920844 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9814 05:59:27.924243 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9815 05:59:27.931099 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9816 05:59:27.934047 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9817 05:59:27.941068 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9818 05:59:27.943879 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9819 05:59:27.947487 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9820 05:59:27.953840 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9821 05:59:27.957611 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9822 05:59:27.964137 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9823 05:59:27.967156 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9824 05:59:27.970607 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9825 05:59:27.977224 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9826 05:59:27.980201 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9827 05:59:27.986884 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9828 05:59:27.990382 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9829 05:59:27.997269 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9830 05:59:28.000297 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9831 05:59:28.003239 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9832 05:59:28.010375 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9833 05:59:28.013450 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9834 05:59:28.020128 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9835 05:59:28.023134 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9836 05:59:28.030119 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9837 05:59:28.032917 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9838 05:59:28.036393 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9839 05:59:28.042880 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9840 05:59:28.046352 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9841 05:59:28.052741 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9842 05:59:28.056206 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9843 05:59:28.059274 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9844 05:59:28.066462 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9845 05:59:28.069339 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9846 05:59:28.075930 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9847 05:59:28.079205 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9848 05:59:28.083068 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9849 05:59:28.089368 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9850 05:59:28.092827 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9851 05:59:28.098925 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9852 05:59:28.102529 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9853 05:59:28.108875 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9854 05:59:28.112757 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9855 05:59:28.115730 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9856 05:59:28.122342 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9857 05:59:28.125914 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9858 05:59:28.132387 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9859 05:59:28.135442 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9860 05:59:28.142266 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9861 05:59:28.145755 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9862 05:59:28.148782 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9863 05:59:28.155414 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9864 05:59:28.158428 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9865 05:59:28.165532 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9866 05:59:28.168852 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9867 05:59:28.175040 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9868 05:59:28.178314 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9869 05:59:28.185030 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9870 05:59:28.188238 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9871 05:59:28.191618 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9872 05:59:28.198151 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9873 05:59:28.201511 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9874 05:59:28.208418 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9875 05:59:28.211551 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9876 05:59:28.218131 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9877 05:59:28.221160 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9878 05:59:28.224790 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9879 05:59:28.231471 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9880 05:59:28.234388 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9881 05:59:28.241000 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9882 05:59:28.244603 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9883 05:59:28.251190 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9884 05:59:28.254194 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9885 05:59:28.260771 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9886 05:59:28.264428 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9887 05:59:28.270984 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9888 05:59:28.273994 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9889 05:59:28.277635 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9890 05:59:28.284100 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9891 05:59:28.287326 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9892 05:59:28.294208 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9893 05:59:28.297317 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9894 05:59:28.303984 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9895 05:59:28.307333 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9896 05:59:28.313690 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9897 05:59:28.316910 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9898 05:59:28.320227 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9899 05:59:28.326856 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9900 05:59:28.330520 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9901 05:59:28.337147 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9902 05:59:28.340032 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9903 05:59:28.343652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9904 05:59:28.350366 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9905 05:59:28.353385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9906 05:59:28.360168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9907 05:59:28.363008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9908 05:59:28.369653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9909 05:59:28.373118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9910 05:59:28.379730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9911 05:59:28.383161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9912 05:59:28.389645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9913 05:59:28.393168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9914 05:59:28.399873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9915 05:59:28.403435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9916 05:59:28.409874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9917 05:59:28.413352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9918 05:59:28.419438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9919 05:59:28.423100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9920 05:59:28.429598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9921 05:59:28.432703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9922 05:59:28.439350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9923 05:59:28.442949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9924 05:59:28.449339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9925 05:59:28.452965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9926 05:59:28.459392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9927 05:59:28.462961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9928 05:59:28.469225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9929 05:59:28.472843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9930 05:59:28.479451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9931 05:59:28.482484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9932 05:59:28.489147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9933 05:59:28.492443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9934 05:59:28.499027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9935 05:59:28.502542 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9936 05:59:28.505931 INFO: [APUAPC] vio 0
9937 05:59:28.508982 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9938 05:59:28.515851 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9939 05:59:28.518917 INFO: [APUAPC] D0_APC_0: 0x400510
9940 05:59:28.519021 INFO: [APUAPC] D0_APC_1: 0x0
9941 05:59:28.522484 INFO: [APUAPC] D0_APC_2: 0x1540
9942 05:59:28.525365 INFO: [APUAPC] D0_APC_3: 0x0
9943 05:59:28.528727 INFO: [APUAPC] D1_APC_0: 0xffffffff
9944 05:59:28.532105 INFO: [APUAPC] D1_APC_1: 0xffffffff
9945 05:59:28.535353 INFO: [APUAPC] D1_APC_2: 0x3fffff
9946 05:59:28.538585 INFO: [APUAPC] D1_APC_3: 0x0
9947 05:59:28.541977 INFO: [APUAPC] D2_APC_0: 0xffffffff
9948 05:59:28.544878 INFO: [APUAPC] D2_APC_1: 0xffffffff
9949 05:59:28.548542 INFO: [APUAPC] D2_APC_2: 0x3fffff
9950 05:59:28.551888 INFO: [APUAPC] D2_APC_3: 0x0
9951 05:59:28.555242 INFO: [APUAPC] D3_APC_0: 0xffffffff
9952 05:59:28.558104 INFO: [APUAPC] D3_APC_1: 0xffffffff
9953 05:59:28.561788 INFO: [APUAPC] D3_APC_2: 0x3fffff
9954 05:59:28.564728 INFO: [APUAPC] D3_APC_3: 0x0
9955 05:59:28.568295 INFO: [APUAPC] D4_APC_0: 0xffffffff
9956 05:59:28.571345 INFO: [APUAPC] D4_APC_1: 0xffffffff
9957 05:59:28.574653 INFO: [APUAPC] D4_APC_2: 0x3fffff
9958 05:59:28.578110 INFO: [APUAPC] D4_APC_3: 0x0
9959 05:59:28.581569 INFO: [APUAPC] D5_APC_0: 0xffffffff
9960 05:59:28.584614 INFO: [APUAPC] D5_APC_1: 0xffffffff
9961 05:59:28.588209 INFO: [APUAPC] D5_APC_2: 0x3fffff
9962 05:59:28.591699 INFO: [APUAPC] D5_APC_3: 0x0
9963 05:59:28.594788 INFO: [APUAPC] D6_APC_0: 0xffffffff
9964 05:59:28.597730 INFO: [APUAPC] D6_APC_1: 0xffffffff
9965 05:59:28.601226 INFO: [APUAPC] D6_APC_2: 0x3fffff
9966 05:59:28.604630 INFO: [APUAPC] D6_APC_3: 0x0
9967 05:59:28.608147 INFO: [APUAPC] D7_APC_0: 0xffffffff
9968 05:59:28.610909 INFO: [APUAPC] D7_APC_1: 0xffffffff
9969 05:59:28.614623 INFO: [APUAPC] D7_APC_2: 0x3fffff
9970 05:59:28.618030 INFO: [APUAPC] D7_APC_3: 0x0
9971 05:59:28.620941 INFO: [APUAPC] D8_APC_0: 0xffffffff
9972 05:59:28.624552 INFO: [APUAPC] D8_APC_1: 0xffffffff
9973 05:59:28.628175 INFO: [APUAPC] D8_APC_2: 0x3fffff
9974 05:59:28.630942 INFO: [APUAPC] D8_APC_3: 0x0
9975 05:59:28.634441 INFO: [APUAPC] D9_APC_0: 0xffffffff
9976 05:59:28.637822 INFO: [APUAPC] D9_APC_1: 0xffffffff
9977 05:59:28.640720 INFO: [APUAPC] D9_APC_2: 0x3fffff
9978 05:59:28.644205 INFO: [APUAPC] D9_APC_3: 0x0
9979 05:59:28.647602 INFO: [APUAPC] D10_APC_0: 0xffffffff
9980 05:59:28.650536 INFO: [APUAPC] D10_APC_1: 0xffffffff
9981 05:59:28.654123 INFO: [APUAPC] D10_APC_2: 0x3fffff
9982 05:59:28.657670 INFO: [APUAPC] D10_APC_3: 0x0
9983 05:59:28.660979 INFO: [APUAPC] D11_APC_0: 0xffffffff
9984 05:59:28.664422 INFO: [APUAPC] D11_APC_1: 0xffffffff
9985 05:59:28.667661 INFO: [APUAPC] D11_APC_2: 0x3fffff
9986 05:59:28.670811 INFO: [APUAPC] D11_APC_3: 0x0
9987 05:59:28.673835 INFO: [APUAPC] D12_APC_0: 0xffffffff
9988 05:59:28.677365 INFO: [APUAPC] D12_APC_1: 0xffffffff
9989 05:59:28.680815 INFO: [APUAPC] D12_APC_2: 0x3fffff
9990 05:59:28.684233 INFO: [APUAPC] D12_APC_3: 0x0
9991 05:59:28.687739 INFO: [APUAPC] D13_APC_0: 0xffffffff
9992 05:59:28.690696 INFO: [APUAPC] D13_APC_1: 0xffffffff
9993 05:59:28.693652 INFO: [APUAPC] D13_APC_2: 0x3fffff
9994 05:59:28.697369 INFO: [APUAPC] D13_APC_3: 0x0
9995 05:59:28.700260 INFO: [APUAPC] D14_APC_0: 0xffffffff
9996 05:59:28.703772 INFO: [APUAPC] D14_APC_1: 0xffffffff
9997 05:59:28.706991 INFO: [APUAPC] D14_APC_2: 0x3fffff
9998 05:59:28.710371 INFO: [APUAPC] D14_APC_3: 0x0
9999 05:59:28.713606 INFO: [APUAPC] D15_APC_0: 0xffffffff
10000 05:59:28.717255 INFO: [APUAPC] D15_APC_1: 0xffffffff
10001 05:59:28.720203 INFO: [APUAPC] D15_APC_2: 0x3fffff
10002 05:59:28.723675 INFO: [APUAPC] D15_APC_3: 0x0
10003 05:59:28.726707 INFO: [APUAPC] APC_CON: 0x4
10004 05:59:28.730175 INFO: [NOCDAPC] D0_APC_0: 0x0
10005 05:59:28.733884 INFO: [NOCDAPC] D0_APC_1: 0x0
10006 05:59:28.733970 INFO: [NOCDAPC] D1_APC_0: 0x0
10007 05:59:28.736895 INFO: [NOCDAPC] D1_APC_1: 0xfff
10008 05:59:28.740294 INFO: [NOCDAPC] D2_APC_0: 0x0
10009 05:59:28.743591 INFO: [NOCDAPC] D2_APC_1: 0xfff
10010 05:59:28.746826 INFO: [NOCDAPC] D3_APC_0: 0x0
10011 05:59:28.750032 INFO: [NOCDAPC] D3_APC_1: 0xfff
10012 05:59:28.753464 INFO: [NOCDAPC] D4_APC_0: 0x0
10013 05:59:28.756685 INFO: [NOCDAPC] D4_APC_1: 0xfff
10014 05:59:28.760304 INFO: [NOCDAPC] D5_APC_0: 0x0
10015 05:59:28.763308 INFO: [NOCDAPC] D5_APC_1: 0xfff
10016 05:59:28.766879 INFO: [NOCDAPC] D6_APC_0: 0x0
10017 05:59:28.767006 INFO: [NOCDAPC] D6_APC_1: 0xfff
10018 05:59:28.769853 INFO: [NOCDAPC] D7_APC_0: 0x0
10019 05:59:28.773164 INFO: [NOCDAPC] D7_APC_1: 0xfff
10020 05:59:28.776420 INFO: [NOCDAPC] D8_APC_0: 0x0
10021 05:59:28.779769 INFO: [NOCDAPC] D8_APC_1: 0xfff
10022 05:59:28.783379 INFO: [NOCDAPC] D9_APC_0: 0x0
10023 05:59:28.786861 INFO: [NOCDAPC] D9_APC_1: 0xfff
10024 05:59:28.789633 INFO: [NOCDAPC] D10_APC_0: 0x0
10025 05:59:28.792881 INFO: [NOCDAPC] D10_APC_1: 0xfff
10026 05:59:28.796353 INFO: [NOCDAPC] D11_APC_0: 0x0
10027 05:59:28.800048 INFO: [NOCDAPC] D11_APC_1: 0xfff
10028 05:59:28.802891 INFO: [NOCDAPC] D12_APC_0: 0x0
10029 05:59:28.806541 INFO: [NOCDAPC] D12_APC_1: 0xfff
10030 05:59:28.806646 INFO: [NOCDAPC] D13_APC_0: 0x0
10031 05:59:28.809429 INFO: [NOCDAPC] D13_APC_1: 0xfff
10032 05:59:28.812638 INFO: [NOCDAPC] D14_APC_0: 0x0
10033 05:59:28.815994 INFO: [NOCDAPC] D14_APC_1: 0xfff
10034 05:59:28.819684 INFO: [NOCDAPC] D15_APC_0: 0x0
10035 05:59:28.822903 INFO: [NOCDAPC] D15_APC_1: 0xfff
10036 05:59:28.826288 INFO: [NOCDAPC] APC_CON: 0x4
10037 05:59:28.829283 INFO: [APUAPC] set_apusys_apc done
10038 05:59:28.832922 INFO: [DEVAPC] devapc_init done
10039 05:59:28.835915 INFO: GICv3 without legacy support detected.
10040 05:59:28.842470 INFO: ARM GICv3 driver initialized in EL3
10041 05:59:28.845980 INFO: Maximum SPI INTID supported: 639
10042 05:59:28.849278 INFO: BL31: Initializing runtime services
10043 05:59:28.855809 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10044 05:59:28.855921 INFO: SPM: enable CPC mode
10045 05:59:28.862217 INFO: mcdi ready for mcusys-off-idle and system suspend
10046 05:59:28.865691 INFO: BL31: Preparing for EL3 exit to normal world
10047 05:59:28.872204 INFO: Entry point address = 0x80000000
10048 05:59:28.872312 INFO: SPSR = 0x8
10049 05:59:28.878344
10050 05:59:28.878456
10051 05:59:28.878560
10052 05:59:28.881957 Starting depthcharge on Spherion...
10053 05:59:28.882037
10054 05:59:28.882141 Wipe memory regions:
10055 05:59:28.882242
10056 05:59:28.883081 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10057 05:59:28.883228 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10058 05:59:28.883348 Setting prompt string to ['asurada:']
10059 05:59:28.883472 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10060 05:59:28.884748 [0x00000040000000, 0x00000054600000)
10061 05:59:29.007448
10062 05:59:29.007609 [0x00000054660000, 0x00000080000000)
10063 05:59:29.268087
10064 05:59:29.268218 [0x000000821a7280, 0x000000ffe64000)
10065 05:59:30.012666
10066 05:59:30.012841 [0x00000100000000, 0x00000240000000)
10067 05:59:31.903415
10068 05:59:31.906463 Initializing XHCI USB controller at 0x11200000.
10069 05:59:32.945327
10070 05:59:32.948384 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10071 05:59:32.948475
10072 05:59:32.948560
10073 05:59:32.948641
10074 05:59:32.948943 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10076 05:59:33.049362 asurada: tftpboot 192.168.201.1 12379461/tftp-deploy-s7pdjngo/kernel/image.itb 12379461/tftp-deploy-s7pdjngo/kernel/cmdline
10077 05:59:33.049568 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10078 05:59:33.049707 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10079 05:59:33.053634 tftpboot 192.168.201.1 12379461/tftp-deploy-s7pdjngo/kernel/image.ittp-deploy-s7pdjngo/kernel/cmdline
10080 05:59:33.053756
10081 05:59:33.053842 Waiting for link
10082 05:59:33.214301
10083 05:59:33.214487 R8152: Initializing
10084 05:59:33.214581
10085 05:59:33.217355 Version 6 (ocp_data = 5c30)
10086 05:59:33.217457
10087 05:59:33.220840 R8152: Done initializing
10088 05:59:33.220960
10089 05:59:33.221061 Adding net device
10090 05:59:35.313275
10091 05:59:35.313410 done.
10092 05:59:35.313542
10093 05:59:35.313643 MAC: 00:24:32:30:78:ff
10094 05:59:35.313754
10095 05:59:35.316657 Sending DHCP discover... done.
10096 05:59:35.316736
10097 05:59:35.320472 Waiting for reply... done.
10098 05:59:35.320556
10099 05:59:35.323252 Sending DHCP request... done.
10100 05:59:35.323384
10101 05:59:35.328038 Waiting for reply... done.
10102 05:59:35.328183
10103 05:59:35.328284 My ip is 192.168.201.21
10104 05:59:35.328381
10105 05:59:35.331162 The DHCP server ip is 192.168.201.1
10106 05:59:35.331237
10107 05:59:35.337940 TFTP server IP predefined by user: 192.168.201.1
10108 05:59:35.338017
10109 05:59:35.344692 Bootfile predefined by user: 12379461/tftp-deploy-s7pdjngo/kernel/image.itb
10110 05:59:35.344793
10111 05:59:35.347751 Sending tftp read request... done.
10112 05:59:35.347861
10113 05:59:35.351394 Waiting for the transfer...
10114 05:59:35.351468
10115 05:59:35.890981 00000000 ################################################################
10116 05:59:35.891160
10117 05:59:36.434533 00080000 ################################################################
10118 05:59:36.434680
10119 05:59:36.991076 00100000 ################################################################
10120 05:59:36.991222
10121 05:59:37.580537 00180000 ################################################################
10122 05:59:37.580671
10123 05:59:38.135605 00200000 ################################################################
10124 05:59:38.135744
10125 05:59:38.709512 00280000 ################################################################
10126 05:59:38.709660
10127 05:59:39.258368 00300000 ################################################################
10128 05:59:39.258516
10129 05:59:39.813697 00380000 ################################################################
10130 05:59:39.813856
10131 05:59:40.368543 00400000 ################################################################
10132 05:59:40.368680
10133 05:59:40.908493 00480000 ################################################################
10134 05:59:40.908629
10135 05:59:41.458111 00500000 ################################################################
10136 05:59:41.458246
10137 05:59:42.103030 00580000 ################################################################
10138 05:59:42.103568
10139 05:59:42.820789 00600000 ################################################################
10140 05:59:42.820947
10141 05:59:43.453182 00680000 ################################################################
10142 05:59:43.453348
10143 05:59:44.142268 00700000 ################################################################
10144 05:59:44.142819
10145 05:59:44.789359 00780000 ################################################################
10146 05:59:44.789547
10147 05:59:45.394183 00800000 ################################################################
10148 05:59:45.394708
10149 05:59:46.131115 00880000 ################################################################
10150 05:59:46.131604
10151 05:59:46.876202 00900000 ################################################################
10152 05:59:46.876722
10153 05:59:47.608075 00980000 ################################################################
10154 05:59:47.608578
10155 05:59:48.328075 00a00000 ################################################################
10156 05:59:48.328622
10157 05:59:49.025598 00a80000 ################################################################
10158 05:59:49.025811
10159 05:59:49.758725 00b00000 ################################################################
10160 05:59:49.759280
10161 05:59:50.444282 00b80000 ################################################################
10162 05:59:50.444807
10163 05:59:51.131344 00c00000 ################################################################
10164 05:59:51.131521
10165 05:59:51.662438 00c80000 ################################################################
10166 05:59:51.662588
10167 05:59:52.270517 00d00000 ################################################################
10168 05:59:52.270738
10169 05:59:52.824162 00d80000 ################################################################
10170 05:59:52.824358
10171 05:59:53.486858 00e00000 ################################################################
10172 05:59:53.487076
10173 05:59:54.179095 00e80000 ################################################################
10174 05:59:54.179584
10175 05:59:54.802304 00f00000 ################################################################
10176 05:59:54.802511
10177 05:59:55.512864 00f80000 ################################################################
10178 05:59:55.513378
10179 05:59:56.212870 01000000 ################################################################
10180 05:59:56.213376
10181 05:59:56.820862 01080000 ################################################################
10182 05:59:56.821013
10183 05:59:57.421364 01100000 ################################################################
10184 05:59:57.421782
10185 05:59:58.021284 01180000 ################################################################
10186 05:59:58.021930
10187 05:59:58.653510 01200000 ################################################################
10188 05:59:58.653754
10189 05:59:59.282389 01280000 ################################################################
10190 05:59:59.282748
10191 05:59:59.906317 01300000 ################################################################
10192 05:59:59.906483
10193 06:00:00.570132 01380000 ################################################################
10194 06:00:00.570271
10195 06:00:01.325111 01400000 ################################################################
10196 06:00:01.325260
10197 06:00:02.031889 01480000 ################################################################
10198 06:00:02.032046
10199 06:00:02.651161 01500000 ################################################################
10200 06:00:02.651304
10201 06:00:03.321452 01580000 ################################################################
10202 06:00:03.321998
10203 06:00:04.009494 01600000 ################################################################
10204 06:00:04.009644
10205 06:00:04.687570 01680000 ################################################################
10206 06:00:04.688072
10207 06:00:05.369780 01700000 ################################################################
10208 06:00:05.370289
10209 06:00:06.075312 01780000 ################################################################
10210 06:00:06.075807
10211 06:00:06.706542 01800000 ################################################################
10212 06:00:06.707071
10213 06:00:07.455793 01880000 ################################################################
10214 06:00:07.456341
10215 06:00:08.199009 01900000 ################################################################
10216 06:00:08.199624
10217 06:00:08.933239 01980000 ################################################################
10218 06:00:08.933850
10219 06:00:09.685803 01a00000 ################################################################
10220 06:00:09.686320
10221 06:00:10.414695 01a80000 ################################################################
10222 06:00:10.415055
10223 06:00:11.135857 01b00000 ################################################################
10224 06:00:11.136351
10225 06:00:11.887416 01b80000 ################################################################
10226 06:00:11.887920
10227 06:00:12.594228 01c00000 ################################################################
10228 06:00:12.594734
10229 06:00:13.314832 01c80000 ################################################################
10230 06:00:13.315338
10231 06:00:14.044992 01d00000 ################################################################
10232 06:00:14.045550
10233 06:00:14.794738 01d80000 ################################################################
10234 06:00:14.795257
10235 06:00:15.537942 01e00000 ################################################################
10236 06:00:15.538449
10237 06:00:16.250596 01e80000 ################################################################
10238 06:00:16.251109
10239 06:00:17.001310 01f00000 ################################################################
10240 06:00:17.001949
10241 06:00:17.745922 01f80000 ################################################################
10242 06:00:17.746466
10243 06:00:18.483766 02000000 ################################################################
10244 06:00:18.484296
10245 06:00:19.216585 02080000 ################################################################
10246 06:00:19.217095
10247 06:00:19.829820 02100000 ################################################################
10248 06:00:19.829972
10249 06:00:20.497082 02180000 ################################################################
10250 06:00:20.497468
10251 06:00:21.024618 02200000 ################################################################
10252 06:00:21.024798
10253 06:00:21.757331 02280000 ################################################################
10254 06:00:21.757936
10255 06:00:22.496796 02300000 ################################################################
10256 06:00:22.497339
10257 06:00:23.229511 02380000 ################################################################
10258 06:00:23.230594
10259 06:00:23.954895 02400000 ################################################################
10260 06:00:23.955394
10261 06:00:24.695805 02480000 ################################################################
10262 06:00:24.696337
10263 06:00:25.441197 02500000 ################################################################
10264 06:00:25.441812
10265 06:00:26.171047 02580000 ################################################################
10266 06:00:26.171572
10267 06:00:26.913540 02600000 ################################################################
10268 06:00:26.914062
10269 06:00:27.623375 02680000 ################################################################
10270 06:00:27.623911
10271 06:00:28.353789 02700000 ################################################################
10272 06:00:28.354303
10273 06:00:29.068566 02780000 ################################################################
10274 06:00:29.069087
10275 06:00:29.777384 02800000 ################################################################
10276 06:00:29.777947
10277 06:00:30.464693 02880000 ################################################################
10278 06:00:30.464822
10279 06:00:31.069851 02900000 ################################################################
10280 06:00:31.070344
10281 06:00:31.791080 02980000 ################################################################
10282 06:00:31.791723
10283 06:00:32.430005 02a00000 ################################################################
10284 06:00:32.430136
10285 06:00:33.015663 02a80000 ################################################################
10286 06:00:33.015802
10287 06:00:33.605382 02b00000 ################################################################
10288 06:00:33.605568
10289 06:00:34.208223 02b80000 ################################################################
10290 06:00:34.208367
10291 06:00:34.799415 02c00000 ################################################################
10292 06:00:34.799563
10293 06:00:35.390120 02c80000 ################################################################
10294 06:00:35.390261
10295 06:00:35.980939 02d00000 ################################################################
10296 06:00:35.981085
10297 06:00:36.562006 02d80000 ################################################################
10298 06:00:36.562145
10299 06:00:37.154559 02e00000 ################################################################
10300 06:00:37.154693
10301 06:00:37.749227 02e80000 ################################################################
10302 06:00:37.749360
10303 06:00:38.338671 02f00000 ################################################################
10304 06:00:38.338801
10305 06:00:38.922245 02f80000 ################################################################
10306 06:00:38.922382
10307 06:00:39.500494 03000000 ################################################################
10308 06:00:39.500633
10309 06:00:40.087403 03080000 ################################################################
10310 06:00:40.087555
10311 06:00:40.672050 03100000 ################################################################
10312 06:00:40.672205
10313 06:00:41.246321 03180000 ################################################################
10314 06:00:41.246460
10315 06:00:41.826042 03200000 ################################################################
10316 06:00:41.826196
10317 06:00:42.397292 03280000 ################################################################
10318 06:00:42.397433
10319 06:00:42.978698 03300000 ################################################################
10320 06:00:42.978853
10321 06:00:43.567734 03380000 ################################################################
10322 06:00:43.567932
10323 06:00:44.148451 03400000 ################################################################
10324 06:00:44.148602
10325 06:00:44.731746 03480000 ################################################################
10326 06:00:44.731896
10327 06:00:45.319864 03500000 ################################################################
10328 06:00:45.320029
10329 06:00:45.914075 03580000 ################################################################
10330 06:00:45.914228
10331 06:00:46.504573 03600000 ################################################################
10332 06:00:46.504770
10333 06:00:47.095042 03680000 ################################################################
10334 06:00:47.095216
10335 06:00:47.689398 03700000 ################################################################
10336 06:00:47.689588
10337 06:00:48.296931 03780000 ################################################################
10338 06:00:48.297101
10339 06:00:48.690091 03800000 ######################################### done.
10340 06:00:48.690261
10341 06:00:48.693665 The bootfile was 59056074 bytes long.
10342 06:00:48.693772
10343 06:00:48.696764 Sending tftp read request... done.
10344 06:00:48.696867
10345 06:00:48.696964 Waiting for the transfer...
10346 06:00:48.697041
10347 06:00:48.699905 00000000 # done.
10348 06:00:48.700013
10349 06:00:48.706717 Command line loaded dynamically from TFTP file: 12379461/tftp-deploy-s7pdjngo/kernel/cmdline
10350 06:00:48.706845
10351 06:00:48.719933 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10352 06:00:48.720060
10353 06:00:48.723038 Loading FIT.
10354 06:00:48.723177
10355 06:00:48.726359 Image ramdisk-1 has 47524929 bytes.
10356 06:00:48.726475
10357 06:00:48.729684 Image fdt-1 has 47278 bytes.
10358 06:00:48.729768
10359 06:00:48.729833 Image kernel-1 has 11481830 bytes.
10360 06:00:48.729895
10361 06:00:48.739456 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10362 06:00:48.739564
10363 06:00:48.756293 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10364 06:00:48.756425
10365 06:00:48.763029 Choosing best match conf-1 for compat google,spherion-rev2.
10366 06:00:48.766952
10367 06:00:48.771904 Connected to device vid:did:rid of 1ae0:0028:00
10368 06:00:48.778262
10369 06:00:48.781741 tpm_get_response: command 0x17b, return code 0x0
10370 06:00:48.781830
10371 06:00:48.784867 ec_init: CrosEC protocol v3 supported (256, 248)
10372 06:00:48.789048
10373 06:00:48.792491 tpm_cleanup: add release locality here.
10374 06:00:48.792575
10375 06:00:48.792642 Shutting down all USB controllers.
10376 06:00:48.795526
10377 06:00:48.795609 Removing current net device
10378 06:00:48.795674
10379 06:00:48.802323 Exiting depthcharge with code 4 at timestamp: 109287970
10380 06:00:48.802407
10381 06:00:48.805578 LZMA decompressing kernel-1 to 0x821a6718
10382 06:00:48.805687
10383 06:00:48.809086 LZMA decompressing kernel-1 to 0x40000000
10384 06:00:50.246104
10385 06:00:50.246258 jumping to kernel
10386 06:00:50.246783 end: 2.2.4 bootloader-commands (duration 00:01:21) [common]
10387 06:00:50.246884 start: 2.2.5 auto-login-action (timeout 00:03:04) [common]
10388 06:00:50.246961 Setting prompt string to ['Linux version [0-9]']
10389 06:00:50.247030 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10390 06:00:50.247097 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10391 06:00:50.328770
10392 06:00:50.332223 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10393 06:00:50.335880 start: 2.2.5.1 login-action (timeout 00:03:04) [common]
10394 06:00:50.335978 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10395 06:00:50.336048 Setting prompt string to []
10396 06:00:50.336125 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10397 06:00:50.336198 Using line separator: #'\n'#
10398 06:00:50.336285 No login prompt set.
10399 06:00:50.336363 Parsing kernel messages
10400 06:00:50.336418 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10401 06:00:50.336518 [login-action] Waiting for messages, (timeout 00:03:04)
10402 06:00:50.355396 [ 0.000000] Linux version 6.1.67-cip12 (KernelCI@build-j59664-arm64-gcc-10-defconfig-arm64-chromebook-fgc24) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023
10403 06:00:50.358315 [ 0.000000] random: crng init done
10404 06:00:50.365283 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10405 06:00:50.368075 [ 0.000000] efi: UEFI not found.
10406 06:00:50.374869 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10407 06:00:50.381872 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10408 06:00:50.391614 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10409 06:00:50.401636 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10410 06:00:50.407751 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10411 06:00:50.414579 [ 0.000000] printk: bootconsole [mtk8250] enabled
10412 06:00:50.421004 [ 0.000000] NUMA: No NUMA configuration found
10413 06:00:50.427770 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10414 06:00:50.431325 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10415 06:00:50.434201 [ 0.000000] Zone ranges:
10416 06:00:50.440844 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10417 06:00:50.444605 [ 0.000000] DMA32 empty
10418 06:00:50.450745 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10419 06:00:50.454681 [ 0.000000] Movable zone start for each node
10420 06:00:50.457383 [ 0.000000] Early memory node ranges
10421 06:00:50.464231 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10422 06:00:50.471100 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10423 06:00:50.477353 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10424 06:00:50.484252 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10425 06:00:50.490699 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10426 06:00:50.497452 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10427 06:00:50.553044 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10428 06:00:50.559624 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10429 06:00:50.565919 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10430 06:00:50.569247 [ 0.000000] psci: probing for conduit method from DT.
10431 06:00:50.576439 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10432 06:00:50.579513 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10433 06:00:50.585770 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10434 06:00:50.589229 [ 0.000000] psci: SMC Calling Convention v1.2
10435 06:00:50.596270 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10436 06:00:50.599655 [ 0.000000] Detected VIPT I-cache on CPU0
10437 06:00:50.605961 [ 0.000000] CPU features: detected: GIC system register CPU interface
10438 06:00:50.612244 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10439 06:00:50.618913 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10440 06:00:50.625808 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10441 06:00:50.635504 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10442 06:00:50.642224 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10443 06:00:50.645148 [ 0.000000] alternatives: applying boot alternatives
10444 06:00:50.652042 [ 0.000000] Fallback order for Node 0: 0
10445 06:00:50.658352 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10446 06:00:50.661937 [ 0.000000] Policy zone: Normal
10447 06:00:50.675091 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10448 06:00:50.684803 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10449 06:00:50.697310 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10450 06:00:50.707377 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10451 06:00:50.714275 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10452 06:00:50.717013 <6>[ 0.000000] software IO TLB: area num 8.
10453 06:00:50.773194 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10454 06:00:50.922678 <6>[ 0.000000] Memory: 7922308K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 430460K reserved, 32768K cma-reserved)
10455 06:00:50.929247 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10456 06:00:50.935564 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10457 06:00:50.939410 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10458 06:00:50.945738 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10459 06:00:50.952558 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10460 06:00:50.955580 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10461 06:00:50.965792 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10462 06:00:50.972228 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10463 06:00:50.978510 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10464 06:00:50.984928 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10465 06:00:50.988506 <6>[ 0.000000] GICv3: 608 SPIs implemented
10466 06:00:50.991885 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10467 06:00:50.998397 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10468 06:00:51.001611 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10469 06:00:51.008542 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10470 06:00:51.021715 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10471 06:00:51.035081 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10472 06:00:51.041400 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10473 06:00:51.049012 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10474 06:00:51.062654 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10475 06:00:51.068900 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10476 06:00:51.075755 <6>[ 0.009233] Console: colour dummy device 80x25
10477 06:00:51.085396 <6>[ 0.013959] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10478 06:00:51.092312 <6>[ 0.024402] pid_max: default: 32768 minimum: 301
10479 06:00:51.095536 <6>[ 0.029273] LSM: Security Framework initializing
10480 06:00:51.102423 <6>[ 0.034210] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10481 06:00:51.112215 <6>[ 0.042023] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10482 06:00:51.118417 <6>[ 0.051436] cblist_init_generic: Setting adjustable number of callback queues.
10483 06:00:51.125160 <6>[ 0.058880] cblist_init_generic: Setting shift to 3 and lim to 1.
10484 06:00:51.135017 <6>[ 0.065218] cblist_init_generic: Setting adjustable number of callback queues.
10485 06:00:51.141951 <6>[ 0.072691] cblist_init_generic: Setting shift to 3 and lim to 1.
10486 06:00:51.145309 <6>[ 0.079093] rcu: Hierarchical SRCU implementation.
10487 06:00:51.151462 <6>[ 0.084139] rcu: Max phase no-delay instances is 1000.
10488 06:00:51.158271 <6>[ 0.091157] EFI services will not be available.
10489 06:00:51.161332 <6>[ 0.096113] smp: Bringing up secondary CPUs ...
10490 06:00:51.169655 <6>[ 0.101159] Detected VIPT I-cache on CPU1
10491 06:00:51.176408 <6>[ 0.101229] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10492 06:00:51.183411 <6>[ 0.101259] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10493 06:00:51.186166 <6>[ 0.101596] Detected VIPT I-cache on CPU2
10494 06:00:51.196599 <6>[ 0.101646] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10495 06:00:51.202743 <6>[ 0.101661] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10496 06:00:51.206286 <6>[ 0.101915] Detected VIPT I-cache on CPU3
10497 06:00:51.212705 <6>[ 0.101960] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10498 06:00:51.219458 <6>[ 0.101974] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10499 06:00:51.222909 <6>[ 0.102277] CPU features: detected: Spectre-v4
10500 06:00:51.229257 <6>[ 0.102284] CPU features: detected: Spectre-BHB
10501 06:00:51.232622 <6>[ 0.102289] Detected PIPT I-cache on CPU4
10502 06:00:51.239536 <6>[ 0.102347] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10503 06:00:51.245876 <6>[ 0.102363] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10504 06:00:51.252681 <6>[ 0.102655] Detected PIPT I-cache on CPU5
10505 06:00:51.258975 <6>[ 0.102717] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10506 06:00:51.265635 <6>[ 0.102733] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10507 06:00:51.268907 <6>[ 0.103014] Detected PIPT I-cache on CPU6
10508 06:00:51.275606 <6>[ 0.103081] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10509 06:00:51.282251 <6>[ 0.103097] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10510 06:00:51.288611 <6>[ 0.103393] Detected PIPT I-cache on CPU7
10511 06:00:51.295476 <6>[ 0.103460] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10512 06:00:51.302009 <6>[ 0.103476] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10513 06:00:51.305345 <6>[ 0.103525] smp: Brought up 1 node, 8 CPUs
10514 06:00:51.311982 <6>[ 0.244733] SMP: Total of 8 processors activated.
10515 06:00:51.315298 <6>[ 0.249654] CPU features: detected: 32-bit EL0 Support
10516 06:00:51.324963 <6>[ 0.255051] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10517 06:00:51.331897 <6>[ 0.263852] CPU features: detected: Common not Private translations
10518 06:00:51.338491 <6>[ 0.270328] CPU features: detected: CRC32 instructions
10519 06:00:51.341896 <6>[ 0.275712] CPU features: detected: RCpc load-acquire (LDAPR)
10520 06:00:51.348335 <6>[ 0.281672] CPU features: detected: LSE atomic instructions
10521 06:00:51.355143 <6>[ 0.287453] CPU features: detected: Privileged Access Never
10522 06:00:51.361395 <6>[ 0.293269] CPU features: detected: RAS Extension Support
10523 06:00:51.368109 <6>[ 0.298912] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10524 06:00:51.371085 <6>[ 0.306169] CPU: All CPU(s) started at EL2
10525 06:00:51.377960 <6>[ 0.310512] alternatives: applying system-wide alternatives
10526 06:00:51.387466 <6>[ 0.321241] devtmpfs: initialized
10527 06:00:51.402957 <6>[ 0.330119] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10528 06:00:51.409458 <6>[ 0.340083] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10529 06:00:51.416545 <6>[ 0.348306] pinctrl core: initialized pinctrl subsystem
10530 06:00:51.419908 <6>[ 0.354969] DMI not present or invalid.
10531 06:00:51.426200 <6>[ 0.359376] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10532 06:00:51.435814 <6>[ 0.366246] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10533 06:00:51.442568 <6>[ 0.373829] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10534 06:00:51.452551 <6>[ 0.382062] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10535 06:00:51.455928 <6>[ 0.390306] audit: initializing netlink subsys (disabled)
10536 06:00:51.465959 <5>[ 0.396000] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10537 06:00:51.472459 <6>[ 0.396700] thermal_sys: Registered thermal governor 'step_wise'
10538 06:00:51.478739 <6>[ 0.403967] thermal_sys: Registered thermal governor 'power_allocator'
10539 06:00:51.482121 <6>[ 0.410221] cpuidle: using governor menu
10540 06:00:51.488955 <6>[ 0.421183] NET: Registered PF_QIPCRTR protocol family
10541 06:00:51.495434 <6>[ 0.426661] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10542 06:00:51.502079 <6>[ 0.433761] ASID allocator initialised with 32768 entries
10543 06:00:51.505419 <6>[ 0.440324] Serial: AMBA PL011 UART driver
10544 06:00:51.515525 <4>[ 0.449086] Trying to register duplicate clock ID: 134
10545 06:00:51.569378 <6>[ 0.506373] KASLR enabled
10546 06:00:51.583417 <6>[ 0.514099] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10547 06:00:51.590114 <6>[ 0.521115] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10548 06:00:51.596968 <6>[ 0.527605] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10549 06:00:51.603354 <6>[ 0.534611] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10550 06:00:51.610399 <6>[ 0.541100] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10551 06:00:51.616792 <6>[ 0.548106] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10552 06:00:51.623520 <6>[ 0.554591] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10553 06:00:51.629805 <6>[ 0.561591] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10554 06:00:51.633455 <6>[ 0.569096] ACPI: Interpreter disabled.
10555 06:00:51.641711 <6>[ 0.575491] iommu: Default domain type: Translated
10556 06:00:51.648253 <6>[ 0.580604] iommu: DMA domain TLB invalidation policy: strict mode
10557 06:00:51.651288 <5>[ 0.587261] SCSI subsystem initialized
10558 06:00:51.658377 <6>[ 0.591420] usbcore: registered new interface driver usbfs
10559 06:00:51.664544 <6>[ 0.597149] usbcore: registered new interface driver hub
10560 06:00:51.668106 <6>[ 0.602700] usbcore: registered new device driver usb
10561 06:00:51.674914 <6>[ 0.608789] pps_core: LinuxPPS API ver. 1 registered
10562 06:00:51.684959 <6>[ 0.613982] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10563 06:00:51.688468 <6>[ 0.623327] PTP clock support registered
10564 06:00:51.691476 <6>[ 0.627568] EDAC MC: Ver: 3.0.0
10565 06:00:51.698885 <6>[ 0.632715] FPGA manager framework
10566 06:00:51.705858 <6>[ 0.636395] Advanced Linux Sound Architecture Driver Initialized.
10567 06:00:51.708854 <6>[ 0.643158] vgaarb: loaded
10568 06:00:51.715346 <6>[ 0.646313] clocksource: Switched to clocksource arch_sys_counter
10569 06:00:51.718829 <5>[ 0.652742] VFS: Disk quotas dquot_6.6.0
10570 06:00:51.725751 <6>[ 0.656925] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10571 06:00:51.728552 <6>[ 0.664113] pnp: PnP ACPI: disabled
10572 06:00:51.736835 <6>[ 0.670779] NET: Registered PF_INET protocol family
10573 06:00:51.746860 <6>[ 0.676365] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10574 06:00:51.758175 <6>[ 0.688674] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10575 06:00:51.767999 <6>[ 0.697486] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10576 06:00:51.775127 <6>[ 0.705456] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10577 06:00:51.781405 <6>[ 0.714157] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10578 06:00:51.793402 <6>[ 0.723898] TCP: Hash tables configured (established 65536 bind 65536)
10579 06:00:51.800369 <6>[ 0.730755] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10580 06:00:51.806587 <6>[ 0.737950] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10581 06:00:51.813454 <6>[ 0.745653] NET: Registered PF_UNIX/PF_LOCAL protocol family
10582 06:00:51.819889 <6>[ 0.751827] RPC: Registered named UNIX socket transport module.
10583 06:00:51.822831 <6>[ 0.757977] RPC: Registered udp transport module.
10584 06:00:51.829888 <6>[ 0.762910] RPC: Registered tcp transport module.
10585 06:00:51.836364 <6>[ 0.767843] RPC: Registered tcp NFSv4.1 backchannel transport module.
10586 06:00:51.839757 <6>[ 0.774510] PCI: CLS 0 bytes, default 64
10587 06:00:51.843224 <6>[ 0.778914] Unpacking initramfs...
10588 06:00:51.868008 <6>[ 0.798551] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10589 06:00:51.878071 <6>[ 0.807210] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10590 06:00:51.881139 <6>[ 0.816063] kvm [1]: IPA Size Limit: 40 bits
10591 06:00:51.887714 <6>[ 0.820590] kvm [1]: GICv3: no GICV resource entry
10592 06:00:51.891096 <6>[ 0.825609] kvm [1]: disabling GICv2 emulation
10593 06:00:51.897656 <6>[ 0.830295] kvm [1]: GIC system register CPU interface enabled
10594 06:00:51.900959 <6>[ 0.836462] kvm [1]: vgic interrupt IRQ18
10595 06:00:51.907366 <6>[ 0.840816] kvm [1]: VHE mode initialized successfully
10596 06:00:51.914393 <5>[ 0.847283] Initialise system trusted keyrings
10597 06:00:51.920682 <6>[ 0.852116] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10598 06:00:51.928330 <6>[ 0.862026] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10599 06:00:51.935193 <5>[ 0.868401] NFS: Registering the id_resolver key type
10600 06:00:51.938059 <5>[ 0.873704] Key type id_resolver registered
10601 06:00:51.945012 <5>[ 0.878118] Key type id_legacy registered
10602 06:00:51.951447 <6>[ 0.882395] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10603 06:00:51.957897 <6>[ 0.889315] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10604 06:00:51.964205 <6>[ 0.897029] 9p: Installing v9fs 9p2000 file system support
10605 06:00:52.000912 <5>[ 0.934745] Key type asymmetric registered
10606 06:00:52.004042 <5>[ 0.939076] Asymmetric key parser 'x509' registered
10607 06:00:52.014055 <6>[ 0.944220] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10608 06:00:52.017355 <6>[ 0.951832] io scheduler mq-deadline registered
10609 06:00:52.020372 <6>[ 0.956616] io scheduler kyber registered
10610 06:00:52.039821 <6>[ 0.973517] EINJ: ACPI disabled.
10611 06:00:52.071848 <4>[ 0.999094] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10612 06:00:52.081664 <4>[ 1.009725] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10613 06:00:52.097155 <6>[ 1.030930] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10614 06:00:52.105111 <6>[ 1.039055] printk: console [ttyS0] disabled
10615 06:00:52.133054 <6>[ 1.063689] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10616 06:00:52.139887 <6>[ 1.073162] printk: console [ttyS0] enabled
10617 06:00:52.143279 <6>[ 1.073162] printk: console [ttyS0] enabled
10618 06:00:52.149623 <6>[ 1.082056] printk: bootconsole [mtk8250] disabled
10619 06:00:52.153127 <6>[ 1.082056] printk: bootconsole [mtk8250] disabled
10620 06:00:52.159980 <6>[ 1.093310] SuperH (H)SCI(F) driver initialized
10621 06:00:52.162908 <6>[ 1.098608] msm_serial: driver initialized
10622 06:00:52.176849 <6>[ 1.107567] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10623 06:00:52.187265 <6>[ 1.116118] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10624 06:00:52.193799 <6>[ 1.124660] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10625 06:00:52.203556 <6>[ 1.133289] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10626 06:00:52.213836 <6>[ 1.141996] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10627 06:00:52.220006 <6>[ 1.150716] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10628 06:00:52.230032 <6>[ 1.159257] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10629 06:00:52.236725 <6>[ 1.168085] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10630 06:00:52.246499 <6>[ 1.176628] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10631 06:00:52.258324 <6>[ 1.192321] loop: module loaded
10632 06:00:52.264958 <6>[ 1.198293] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10633 06:00:52.287841 <4>[ 1.221758] mtk-pmic-keys: Failed to locate of_node [id: -1]
10634 06:00:52.294792 <6>[ 1.228613] megasas: 07.719.03.00-rc1
10635 06:00:52.304613 <6>[ 1.238350] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10636 06:00:52.311953 <6>[ 1.245687] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10637 06:00:52.329004 <6>[ 1.262385] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10638 06:00:52.385196 <6>[ 1.312217] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10639 06:00:53.885751 <6>[ 2.819660] Freeing initrd memory: 46408K
10640 06:00:53.896038 <6>[ 2.829888] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10641 06:00:53.906890 <6>[ 2.840852] tun: Universal TUN/TAP device driver, 1.6
10642 06:00:53.910292 <6>[ 2.846928] thunder_xcv, ver 1.0
10643 06:00:53.913358 <6>[ 2.850430] thunder_bgx, ver 1.0
10644 06:00:53.916765 <6>[ 2.853919] nicpf, ver 1.0
10645 06:00:53.927290 <6>[ 2.857928] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10646 06:00:53.930444 <6>[ 2.865404] hns3: Copyright (c) 2017 Huawei Corporation.
10647 06:00:53.937350 <6>[ 2.870989] hclge is initializing
10648 06:00:53.940268 <6>[ 2.874569] e1000: Intel(R) PRO/1000 Network Driver
10649 06:00:53.947262 <6>[ 2.879699] e1000: Copyright (c) 1999-2006 Intel Corporation.
10650 06:00:53.950577 <6>[ 2.885711] e1000e: Intel(R) PRO/1000 Network Driver
10651 06:00:53.956861 <6>[ 2.890927] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10652 06:00:53.963338 <6>[ 2.897114] igb: Intel(R) Gigabit Ethernet Network Driver
10653 06:00:53.970368 <6>[ 2.902764] igb: Copyright (c) 2007-2014 Intel Corporation.
10654 06:00:53.976645 <6>[ 2.908601] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10655 06:00:53.983395 <6>[ 2.915118] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10656 06:00:53.986681 <6>[ 2.921578] sky2: driver version 1.30
10657 06:00:53.993178 <6>[ 2.926574] VFIO - User Level meta-driver version: 0.3
10658 06:00:54.000846 <6>[ 2.934815] usbcore: registered new interface driver usb-storage
10659 06:00:54.007309 <6>[ 2.941253] usbcore: registered new device driver onboard-usb-hub
10660 06:00:54.016522 <6>[ 2.950391] mt6397-rtc mt6359-rtc: registered as rtc0
10661 06:00:54.026532 <6>[ 2.955854] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-25T06:00:54 UTC (1703484054)
10662 06:00:54.029285 <6>[ 2.965408] i2c_dev: i2c /dev entries driver
10663 06:00:54.046384 <6>[ 2.977069] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10664 06:00:54.065852 <6>[ 3.000058] cpu cpu0: EM: created perf domain
10665 06:00:54.069286 <6>[ 3.004986] cpu cpu4: EM: created perf domain
10666 06:00:54.076828 <6>[ 3.010584] sdhci: Secure Digital Host Controller Interface driver
10667 06:00:54.083298 <6>[ 3.017014] sdhci: Copyright(c) Pierre Ossman
10668 06:00:54.089765 <6>[ 3.021970] Synopsys Designware Multimedia Card Interface Driver
10669 06:00:54.096558 <6>[ 3.028605] sdhci-pltfm: SDHCI platform and OF driver helper
10670 06:00:54.099922 <6>[ 3.028629] mmc0: CQHCI version 5.10
10671 06:00:54.106245 <6>[ 3.038972] ledtrig-cpu: registered to indicate activity on CPUs
10672 06:00:54.113192 <6>[ 3.045991] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10673 06:00:54.119583 <6>[ 3.053044] usbcore: registered new interface driver usbhid
10674 06:00:54.123086 <6>[ 3.058865] usbhid: USB HID core driver
10675 06:00:54.129639 <6>[ 3.063076] spi_master spi0: will run message pump with realtime priority
10676 06:00:54.174393 <6>[ 3.101950] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10677 06:00:54.194032 <6>[ 3.117907] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10678 06:00:54.196897 <6>[ 3.131447] mmc0: Command Queue Engine enabled
10679 06:00:54.203884 <6>[ 3.136243] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10680 06:00:54.210440 <6>[ 3.143573] mmcblk0: mmc0:0001 DA4128 116 GiB
10681 06:00:54.213850 <6>[ 3.148500] cros-ec-spi spi0.0: Chrome EC device registered
10682 06:00:54.220466 <6>[ 3.152405] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10683 06:00:54.228310 <6>[ 3.162222] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10684 06:00:54.234948 <6>[ 3.168146] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10685 06:00:54.241550 <6>[ 3.174313] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10686 06:00:54.260543 <6>[ 3.191170] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10687 06:00:54.268137 <6>[ 3.201989] NET: Registered PF_PACKET protocol family
10688 06:00:54.271570 <6>[ 3.207381] 9pnet: Installing 9P2000 support
10689 06:00:54.277804 <5>[ 3.211947] Key type dns_resolver registered
10690 06:00:54.281274 <6>[ 3.216934] registered taskstats version 1
10691 06:00:54.287774 <5>[ 3.221325] Loading compiled-in X.509 certificates
10692 06:00:54.320022 <4>[ 3.247145] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10693 06:00:54.329402 <4>[ 3.257916] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10694 06:00:54.336021 <3>[ 3.268456] debugfs: File 'uA_load' in directory '/' already present!
10695 06:00:54.342860 <3>[ 3.275157] debugfs: File 'min_uV' in directory '/' already present!
10696 06:00:54.349264 <3>[ 3.281764] debugfs: File 'max_uV' in directory '/' already present!
10697 06:00:54.356243 <3>[ 3.288370] debugfs: File 'constraint_flags' in directory '/' already present!
10698 06:00:54.367334 <3>[ 3.298123] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10699 06:00:54.379886 <6>[ 3.314062] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10700 06:00:54.386804 <6>[ 3.320896] xhci-mtk 11200000.usb: xHCI Host Controller
10701 06:00:54.393711 <6>[ 3.326400] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10702 06:00:54.403355 <6>[ 3.334240] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10703 06:00:54.409932 <6>[ 3.343668] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10704 06:00:54.416965 <6>[ 3.349733] xhci-mtk 11200000.usb: xHCI Host Controller
10705 06:00:54.423244 <6>[ 3.355209] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10706 06:00:54.430059 <6>[ 3.362862] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10707 06:00:54.436576 <6>[ 3.370534] hub 1-0:1.0: USB hub found
10708 06:00:54.439825 <6>[ 3.374550] hub 1-0:1.0: 1 port detected
10709 06:00:54.449506 <6>[ 3.378826] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10710 06:00:54.453056 <6>[ 3.387525] hub 2-0:1.0: USB hub found
10711 06:00:54.456441 <6>[ 3.391569] hub 2-0:1.0: 1 port detected
10712 06:00:54.464187 <6>[ 3.398507] mtk-msdc 11f70000.mmc: Got CD GPIO
10713 06:00:54.477304 <6>[ 3.407910] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10714 06:00:54.484005 <6>[ 3.415946] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10715 06:00:54.493952 <4>[ 3.423851] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10716 06:00:54.503900 <6>[ 3.433390] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10717 06:00:54.510313 <6>[ 3.441469] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10718 06:00:54.516562 <6>[ 3.449490] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10719 06:00:54.526701 <6>[ 3.457420] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10720 06:00:54.533509 <6>[ 3.465244] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10721 06:00:54.543238 <6>[ 3.473061] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10722 06:00:54.553294 <6>[ 3.483598] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10723 06:00:54.559582 <6>[ 3.491966] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10724 06:00:54.569398 <6>[ 3.500312] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10725 06:00:54.579736 <6>[ 3.508651] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10726 06:00:54.586069 <6>[ 3.516991] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10727 06:00:54.595907 <6>[ 3.525330] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10728 06:00:54.602461 <6>[ 3.533669] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10729 06:00:54.612571 <6>[ 3.542008] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10730 06:00:54.618945 <6>[ 3.550346] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10731 06:00:54.628883 <6>[ 3.558685] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10732 06:00:54.635388 <6>[ 3.567024] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10733 06:00:54.645815 <6>[ 3.575362] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10734 06:00:54.651933 <6>[ 3.583701] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10735 06:00:54.662210 <6>[ 3.592039] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10736 06:00:54.668662 <6>[ 3.600378] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10737 06:00:54.675098 <6>[ 3.609086] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10738 06:00:54.682120 <6>[ 3.616215] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10739 06:00:54.688674 <6>[ 3.622971] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10740 06:00:54.698779 <6>[ 3.629724] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10741 06:00:54.705896 <6>[ 3.636658] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10742 06:00:54.712179 <6>[ 3.643497] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10743 06:00:54.722145 <6>[ 3.652628] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10744 06:00:54.731887 <6>[ 3.661747] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10745 06:00:54.741921 <6>[ 3.671043] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10746 06:00:54.751604 <6>[ 3.680516] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10747 06:00:54.758415 <6>[ 3.689985] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10748 06:00:54.768498 <6>[ 3.699104] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10749 06:00:54.778395 <6>[ 3.708573] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10750 06:00:54.788364 <6>[ 3.717691] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10751 06:00:54.798156 <6>[ 3.726984] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10752 06:00:54.807970 <6>[ 3.737145] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10753 06:00:54.818151 <6>[ 3.748766] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10754 06:00:54.867809 <6>[ 3.798581] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10755 06:00:55.022074 <6>[ 3.956238] hub 1-1:1.0: USB hub found
10756 06:00:55.025383 <6>[ 3.960744] hub 1-1:1.0: 4 ports detected
10757 06:00:55.035174 <6>[ 3.969391] hub 1-1:1.0: USB hub found
10758 06:00:55.038674 <6>[ 3.973812] hub 1-1:1.0: 4 ports detected
10759 06:00:55.148231 <6>[ 4.078951] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10760 06:00:55.174109 <6>[ 4.107900] hub 2-1:1.0: USB hub found
10761 06:00:55.177494 <6>[ 4.112473] hub 2-1:1.0: 3 ports detected
10762 06:00:55.186238 <6>[ 4.120207] hub 2-1:1.0: USB hub found
10763 06:00:55.189673 <6>[ 4.124726] hub 2-1:1.0: 3 ports detected
10764 06:00:55.363405 <6>[ 4.294562] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10765 06:00:55.495767 <6>[ 4.429735] hub 1-1.4:1.0: USB hub found
10766 06:00:55.499037 <6>[ 4.434351] hub 1-1.4:1.0: 2 ports detected
10767 06:00:55.507978 <6>[ 4.441944] hub 1-1.4:1.0: USB hub found
10768 06:00:55.511102 <6>[ 4.446573] hub 1-1.4:1.0: 2 ports detected
10769 06:00:55.579820 <6>[ 4.510824] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10770 06:00:55.807853 <6>[ 4.738625] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10771 06:00:55.999731 <6>[ 4.930667] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10772 06:01:07.109162 <6>[ 16.047597] ALSA device list:
10773 06:01:07.115678 <6>[ 16.050888] No soundcards found.
10774 06:01:07.123229 <6>[ 16.058829] Freeing unused kernel memory: 8448K
10775 06:01:07.126740 <6>[ 16.063926] Run /init as init process
10776 06:01:07.177363 <6>[ 16.112595] NET: Registered PF_INET6 protocol family
10777 06:01:07.183624 <6>[ 16.119102] Segment Routing with IPv6
10778 06:01:07.187169 <6>[ 16.123140] In-situ OAM (IOAM) with IPv6
10779 06:01:07.222122 <30>[ 16.137402] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10780 06:01:07.225075 <30>[ 16.161312] systemd[1]: Detected architecture arm64.
10781 06:01:07.228498
10782 06:01:07.231383 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10783 06:01:07.231463
10784 06:01:07.247075 <30>[ 16.182761] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10785 06:01:07.376935 <30>[ 16.309219] systemd[1]: Queued start job for default target Graphical Interface.
10786 06:01:07.404351 <30>[ 16.339550] systemd[1]: Created slice system-getty.slice.
10787 06:01:07.410685 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10788 06:01:07.427741 <30>[ 16.363267] systemd[1]: Created slice system-modprobe.slice.
10789 06:01:07.434696 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10790 06:01:07.452340 <30>[ 16.387935] systemd[1]: Created slice system-serial\x2dgetty.slice.
10791 06:01:07.462650 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10792 06:01:07.475891 <30>[ 16.411083] systemd[1]: Created slice User and Session Slice.
10793 06:01:07.482562 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10794 06:01:07.503427 <30>[ 16.435338] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10795 06:01:07.512927 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10796 06:01:07.531554 <30>[ 16.463357] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10797 06:01:07.538074 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10798 06:01:07.561751 <30>[ 16.490722] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10799 06:01:07.568556 <30>[ 16.502889] systemd[1]: Reached target Local Encrypted Volumes.
10800 06:01:07.574991 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10801 06:01:07.591847 <30>[ 16.527155] systemd[1]: Reached target Paths.
10802 06:01:07.598115 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10803 06:01:07.611248 <30>[ 16.546632] systemd[1]: Reached target Remote File Systems.
10804 06:01:07.617512 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10805 06:01:07.635503 <30>[ 16.570962] systemd[1]: Reached target Slices.
10806 06:01:07.641834 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10807 06:01:07.655498 <30>[ 16.590663] systemd[1]: Reached target Swap.
10808 06:01:07.658454 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10809 06:01:07.678988 <30>[ 16.611139] systemd[1]: Listening on initctl Compatibility Named Pipe.
10810 06:01:07.685970 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10811 06:01:07.692371 <30>[ 16.626382] systemd[1]: Listening on Journal Audit Socket.
10812 06:01:07.698665 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10813 06:01:07.712009 <30>[ 16.647119] systemd[1]: Listening on Journal Socket (/dev/log).
10814 06:01:07.718374 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10815 06:01:07.736363 <30>[ 16.671847] systemd[1]: Listening on Journal Socket.
10816 06:01:07.743053 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10817 06:01:07.759159 <30>[ 16.691311] systemd[1]: Listening on Network Service Netlink Socket.
10818 06:01:07.765453 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10819 06:01:07.779988 <30>[ 16.715188] systemd[1]: Listening on udev Control Socket.
10820 06:01:07.786350 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10821 06:01:07.804062 <30>[ 16.739667] systemd[1]: Listening on udev Kernel Socket.
10822 06:01:07.810805 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10823 06:01:07.863606 <30>[ 16.798936] systemd[1]: Mounting Huge Pages File System...
10824 06:01:07.869856 Mounting [0;1;39mHuge Pages File System[0m...
10825 06:01:07.886243 <30>[ 16.821611] systemd[1]: Mounting POSIX Message Queue File System...
10826 06:01:07.893122 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10827 06:01:07.910306 <30>[ 16.845688] systemd[1]: Mounting Kernel Debug File System...
10828 06:01:07.917284 Mounting [0;1;39mKernel Debug File System[0m...
10829 06:01:07.934883 <30>[ 16.867128] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10830 06:01:07.948286 <30>[ 16.880358] systemd[1]: Starting Create list of static device nodes for the current kernel...
10831 06:01:07.954844 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10832 06:01:07.975500 <30>[ 16.911074] systemd[1]: Starting Load Kernel Module configfs...
10833 06:01:07.982042 Starting [0;1;39mLoad Kernel Module configfs[0m...
10834 06:01:08.012029 <30>[ 16.947196] systemd[1]: Starting Load Kernel Module drm...
10835 06:01:08.018298 Starting [0;1;39mLoad Kernel Module drm[0m...
10836 06:01:08.034722 <30>[ 16.967037] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10837 06:01:08.049457 <30>[ 16.985128] systemd[1]: Starting Journal Service...
10838 06:01:08.055841 Starting [0;1;39mJournal Service[0m...
10839 06:01:08.075934 <30>[ 17.011442] systemd[1]: Starting Load Kernel Modules...
10840 06:01:08.082819 Starting [0;1;39mLoad Kernel Modules[0m...
10841 06:01:08.102973 <30>[ 17.035022] systemd[1]: Starting Remount Root and Kernel File Systems...
10842 06:01:08.109443 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10843 06:01:08.126431 <30>[ 17.061694] systemd[1]: Starting Coldplug All udev Devices...
10844 06:01:08.132696 Starting [0;1;39mColdplug All udev Devices[0m...
10845 06:01:08.150467 <30>[ 17.085840] systemd[1]: Started Journal Service.
10846 06:01:08.157132 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10847 06:01:08.174064 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10848 06:01:08.192760 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10849 06:01:08.208581 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10850 06:01:08.228651 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10851 06:01:08.245463 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10852 06:01:08.265930 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10853 06:01:08.284351 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10854 06:01:08.305647 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10855 06:01:08.319322 See 'systemctl status systemd-remount-fs.service' for details.
10856 06:01:08.372304 Mounting [0;1;39mKernel Configuration File System[0m...
10857 06:01:08.393991 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10858 06:01:08.407892 <46>[ 17.340084] systemd-journald[188]: Received client request to flush runtime journal.
10859 06:01:08.417151 Starting [0;1;39mLoad/Save Random Seed[0m...
10860 06:01:08.439207 Starting [0;1;39mApply Kernel Variables[0m...
10861 06:01:08.460632 Starting [0;1;39mCreate System Users[0m...
10862 06:01:08.479829 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10863 06:01:08.496428 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10864 06:01:08.516044 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10865 06:01:08.529268 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10866 06:01:08.544725 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10867 06:01:08.560988 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10868 06:01:08.600029 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10869 06:01:08.619461 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10870 06:01:08.635870 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10871 06:01:08.651404 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10872 06:01:08.708312 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10873 06:01:08.738418 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10874 06:01:08.755765 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10875 06:01:08.782071 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10876 06:01:08.802756 Starting [0;1;39mNetwork Service[0m...
10877 06:01:08.829383 Starting [0;1;39mNetwork Time Synchronization[0m...
10878 06:01:08.852572 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10879 06:01:08.882245 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10880 06:01:08.904367 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10881 06:01:08.953498 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10882 06:01:08.971050 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10883 06:01:08.984162 <6>[ 17.916471] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10884 06:01:08.999464 <6>[ 17.931672] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10885 06:01:09.003101 <6>[ 17.935706] remoteproc remoteproc0: scp is available
10886 06:01:09.012915 <6>[ 17.939416] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10887 06:01:09.019160 <6>[ 17.944572] remoteproc remoteproc0: powering up scp
10888 06:01:09.026083 <6>[ 17.953256] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10889 06:01:09.035934 <3>[ 17.955182] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10890 06:01:09.042528 <3>[ 17.955202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10891 06:01:09.052301 <3>[ 17.955210] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10892 06:01:09.058835 <6>[ 17.958585] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10893 06:01:09.068826 <3>[ 17.967426] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10894 06:01:09.075241 <6>[ 17.973580] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10895 06:01:09.081991 <6>[ 17.975185] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10896 06:01:09.088478 <4>[ 17.981549] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10897 06:01:09.095325 <3>[ 17.983342] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10898 06:01:09.105013 <4>[ 18.004607] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10899 06:01:09.112055 <3>[ 18.008139] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10900 06:01:09.118194 <6>[ 18.010982] usbcore: registered new interface driver r8152
10901 06:01:09.121652 <6>[ 18.018623] mc: Linux media interface: v0.10
10902 06:01:09.128518 <3>[ 18.021496] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10903 06:01:09.139006 <4>[ 18.037142] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10904 06:01:09.142110 <4>[ 18.037142] Fallback method does not support PEC.
10905 06:01:09.152436 <3>[ 18.044234] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10906 06:01:09.162207 <3>[ 18.071924] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 06:01:09.169100 <3>[ 18.092839] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10908 06:01:09.176176 <6>[ 18.100562] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10909 06:01:09.182847 <6>[ 18.106960] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10910 06:01:09.192942 <6>[ 18.109214] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10911 06:01:09.202684 <6>[ 18.110838] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10912 06:01:09.208954 <3>[ 18.111610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10913 06:01:09.215980 <3>[ 18.111619] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10914 06:01:09.225903 <3>[ 18.111622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 06:01:09.232735 <3>[ 18.113447] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10916 06:01:09.242669 <3>[ 18.113456] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 06:01:09.249254 <3>[ 18.113459] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10918 06:01:09.259183 <3>[ 18.113464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10919 06:01:09.265671 <3>[ 18.113466] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10920 06:01:09.272328 <6>[ 18.114059] videodev: Linux video capture interface: v2.00
10921 06:01:09.282535 <6>[ 18.114113] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10922 06:01:09.285762 <6>[ 18.116278] pci_bus 0000:00: root bus resource [bus 00-ff]
10923 06:01:09.295720 <3>[ 18.117669] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10924 06:01:09.302256 <6>[ 18.123234] remoteproc remoteproc0: remote processor scp is now up
10925 06:01:09.309144 <6>[ 18.129067] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10926 06:01:09.318691 <6>[ 18.132088] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10927 06:01:09.325331 <6>[ 18.147501] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10928 06:01:09.335530 <6>[ 18.150174] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10929 06:01:09.345263 <4>[ 18.178711] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10930 06:01:09.348282 <6>[ 18.182572] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10931 06:01:09.358290 <4>[ 18.190567] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10932 06:01:09.365118 <6>[ 18.198623] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10933 06:01:09.372160 <6>[ 18.201429] usbcore: registered new interface driver cdc_ether
10934 06:01:09.379115 <6>[ 18.225858] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10935 06:01:09.386361 <6>[ 18.225889] usbcore: registered new interface driver r8153_ecm
10936 06:01:09.390403 <6>[ 18.227318] pci 0000:00:00.0: supports D1 D2
10937 06:01:09.399815 <3>[ 18.228512] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 06:01:09.406895 <6>[ 18.248263] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10939 06:01:09.414342 <6>[ 18.251061] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10940 06:01:09.420526 <6>[ 18.252257] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10941 06:01:09.434077 <6>[ 18.253306] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10942 06:01:09.440830 <6>[ 18.253405] usbcore: registered new interface driver uvcvideo
10943 06:01:09.444771 <6>[ 18.254514] r8152 2-1.3:1.0 eth0: v1.12.13
10944 06:01:09.448154 <6>[ 18.261121] Bluetooth: Core ver 2.22
10945 06:01:09.454545 <6>[ 18.263575] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10946 06:01:09.461582 <3>[ 18.265316] power_supply sbs-5-000b: driver failed to report `status' property: -6
10947 06:01:09.471451 <6>[ 18.266738] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10948 06:01:09.475480 <6>[ 18.268157] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10949 06:01:09.482095 <6>[ 18.275299] NET: Registered PF_BLUETOOTH protocol family
10950 06:01:09.488362 <6>[ 18.284395] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10951 06:01:09.494975 <6>[ 18.290530] Bluetooth: HCI device and connection manager initialized
10952 06:01:09.501529 <6>[ 18.290546] Bluetooth: HCI socket layer initialized
10953 06:01:09.508272 <6>[ 18.298632] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10954 06:01:09.511996 <6>[ 18.306080] Bluetooth: L2CAP socket layer initialized
10955 06:01:09.518901 <6>[ 18.312171] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10956 06:01:09.525323 <6>[ 18.320417] Bluetooth: SCO socket layer initialized
10957 06:01:09.535236 <3>[ 18.325275] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10958 06:01:09.542025 <6>[ 18.326500] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10959 06:01:09.549414 <3>[ 18.327759] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 06:01:09.559362 <3>[ 18.328596] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 06:01:09.569752 <3>[ 18.351513] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 06:01:09.573057 <6>[ 18.355014] pci 0000:01:00.0: supports D1 D2
10963 06:01:09.580039 <3>[ 18.387685] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 06:01:09.586879 <6>[ 18.388512] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10965 06:01:09.594009 <6>[ 18.389015] usbcore: registered new interface driver btusb
10966 06:01:09.604030 <4>[ 18.390059] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10967 06:01:09.610920 <3>[ 18.390088] Bluetooth: hci0: Failed to load firmware file (-2)
10968 06:01:09.617526 <3>[ 18.390097] Bluetooth: hci0: Failed to set up firmware (-2)
10969 06:01:09.627685 <4>[ 18.390109] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10970 06:01:09.634155 <3>[ 18.414736] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 06:01:09.643994 <6>[ 18.430680] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10972 06:01:09.650860 <3>[ 18.455449] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 06:01:09.660486 <6>[ 18.461046] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10974 06:01:09.666978 <6>[ 18.599886] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10975 06:01:09.673960 <6>[ 18.599895] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10976 06:01:09.683834 <6>[ 18.599909] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10977 06:01:09.689950 <6>[ 18.599921] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10978 06:01:09.696897 <6>[ 18.599933] pci 0000:00:00.0: PCI bridge to [bus 01]
10979 06:01:09.703503 <6>[ 18.599940] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10980 06:01:09.710004 <6>[ 18.600089] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10981 06:01:09.719987 [[0;32m OK [<6>[ 18.652074] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10982 06:01:09.726621 0m] Created slic<6>[ 18.659790] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10983 06:01:09.729685 e [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10984 06:01:09.744141 <5>[ 18.676112] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10985 06:01:09.750587 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10986 06:01:09.764952 <5>[ 18.697301] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10987 06:01:09.771945 <4>[ 18.704335] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10988 06:01:09.778273 <6>[ 18.713248] cfg80211: failed to load regulatory.db
10989 06:01:09.784796 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10990 06:01:09.827456 <6>[ 18.760087] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10991 06:01:09.833963 <6>[ 18.767602] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10992 06:01:09.847328 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10993 06:01:09.858526 <6>[ 18.794325] mt7921e 0000:01:00.0: ASIC revision: 79610010
10994 06:01:09.871370 Starting [0;1;39mNetwork Name Resolution[0m...
10995 06:01:09.897538 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10996 06:01:09.947018 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10997 06:01:09.962346 <6>[ 18.894646] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10998 06:01:09.965891 <6>[ 18.894646]
10999 06:01:10.078319 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11000 06:01:10.091299 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11001 06:01:10.110204 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11002 06:01:10.123515 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11003 06:01:10.142422 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11004 06:01:10.158016 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11005 06:01:10.170878 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11006 06:01:10.190886 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11007 06:01:10.203088 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11008 06:01:10.218987 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11009 06:01:10.228818 <6>[ 19.160831] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11010 06:01:10.238657 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11011 06:01:10.288146 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11012 06:01:10.325027 Starting [0;1;39mUser Login Management[0m...
11013 06:01:10.344174 Starting [0;1;39mPermit User Sessions[0m...
11014 06:01:10.362929 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11015 06:01:10.375170 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11016 06:01:10.394999 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11017 06:01:10.411833 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11018 06:01:10.431261 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11019 06:01:10.448854 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11020 06:01:10.464027 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11021 06:01:10.481354 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11022 06:01:10.499573 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11023 06:01:10.551388 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11024 06:01:10.580322 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11025 06:01:10.631071
11026 06:01:10.631193
11027 06:01:10.634588 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11028 06:01:10.634671
11029 06:01:10.637980 debian-bullseye-arm64 login: root (automatic login)
11030 06:01:10.638062
11031 06:01:10.638127
11032 06:01:10.652903 Linux debian-bullseye-arm64 6.1.67-cip12 #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023 aarch64
11033 06:01:10.652991
11034 06:01:10.659767 The programs included with the Debian GNU/Linux system are free software;
11035 06:01:10.666054 the exact distribution terms for each program are described in the
11036 06:01:10.669516 individual files in /usr/share/doc/*/copyright.
11037 06:01:10.669599
11038 06:01:10.675987 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11039 06:01:10.679446 permitted by applicable law.
11040 06:01:10.679821 Matched prompt #10: / #
11042 06:01:10.680026 Setting prompt string to ['/ #']
11043 06:01:10.680117 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11045 06:01:10.680309 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11046 06:01:10.680398 start: 2.2.6 expect-shell-connection (timeout 00:02:43) [common]
11047 06:01:10.680467 Setting prompt string to ['/ #']
11048 06:01:10.680527 Forcing a shell prompt, looking for ['/ #']
11050 06:01:10.730773 / #
11051 06:01:10.730873 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11052 06:01:10.730950 Waiting using forced prompt support (timeout 00:02:30)
11053 06:01:10.736171
11054 06:01:10.736438 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11055 06:01:10.736530 start: 2.2.7 export-device-env (timeout 00:02:43) [common]
11056 06:01:10.736622 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11057 06:01:10.736706 end: 2.2 depthcharge-retry (duration 00:02:17) [common]
11058 06:01:10.736785 end: 2 depthcharge-action (duration 00:02:17) [common]
11059 06:01:10.736872 start: 3 lava-test-retry (timeout 00:05:00) [common]
11060 06:01:10.736954 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11061 06:01:10.737029 Using namespace: common
11063 06:01:10.837357 / # #
11064 06:01:10.837489 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11065 06:01:10.842507 #
11066 06:01:10.842772 Using /lava-12379461
11068 06:01:10.943086 / # export SHELL=/bin/sh
11069 06:01:10.948607 export SHELL=/bin/sh
11071 06:01:11.049129 / # . /lava-12379461/environment
11072 06:01:11.049305 <6>[ 19.917649] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11073 06:01:11.049379 <6>[ 19.925669] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11074 06:01:11.053811 . /lava-12379461/environment
11076 06:01:11.154350 / # /lava-12379461/bin/lava-test-runner /lava-12379461/0
11077 06:01:11.154469 Test shell timeout: 10s (minimum of the action and connection timeout)
11078 06:01:11.154788 <6>[ 20.017450] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11079 06:01:11.159937 /lava-12379461/bin/lava-test-runner /lava-12379461/0
11080 06:01:11.201678 + export TESTRUN_ID=0_cros-ec
11081 06:01:11.201832 +<8>[ 20.122071] <LAVA_SIGNAL_STARTRUN 0_cros-ec 12379461_1.5.2.3.1>
11082 06:01:11.201907 cd /lava-12379461/0/tests/0_cros-ec
11083 06:01:11.201968 + cat uuid
11084 06:01:11.202028 + UUID=12379461_1.5.2.3.1
11085 06:01:11.202092 + set +x
11086 06:01:11.202182 + python3 -m cros.runners.lava_runner -v
11087 06:01:11.202461 Received signal: <STARTRUN> 0_cros-ec 12379461_1.5.2.3.1
11088 06:01:11.202545 Starting test lava.0_cros-ec (12379461_1.5.2.3.1)
11089 06:01:11.202628 Skipping test definition patterns.
11090 06:01:11.579591 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11091 06:01:11.586072 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11092 06:01:11.589442
11093 06:01:11.592602 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11095 06:01:11.595971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11096 06:01:11.602421 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11097 06:01:11.609059 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11098 06:01:11.609141
11099 06:01:11.616146 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8
11100 06:01:11.616245 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_accel_iio_data_is_<8', 'result': 'unknown'}
11101 06:01:11.622779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8>[ 20.556977] <LAVA_SIGNAL_ENDRUN 0_cros-ec 12379461_1.5.2.3.1>
11102 06:01:11.623032 Received signal: <ENDRUN> 0_cros-ec 12379461_1.5.2.3.1
11103 06:01:11.623113 Ending use of test pattern.
11104 06:01:11.623177 Ending test lava.0_cros-ec (12379461_1.5.2.3.1), duration 0.42
11106 06:01:11.625757 valid RESULT=skip>
11107 06:01:11.629532 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11108 06:01:11.635632 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11109 06:01:11.635714
11110 06:01:11.642570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11111 06:01:11.642824 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11113 06:01:11.648843 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11114 06:01:11.655674 Checks the standard ABI for the main Embedded Controller. ... ok
11115 06:01:11.655756
11116 06:01:11.658684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11117 06:01:11.658936 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11119 06:01:11.665431 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11120 06:01:11.672350 Checks the main Embedded controller character device. ... ok
11121 06:01:11.672433
11122 06:01:11.675225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11123 06:01:11.675479 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11125 06:01:11.682354 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11126 06:01:11.688848 Checks basic comunication with the main Embedded controller. ... ok
11127 06:01:11.688930
11128 06:01:11.695272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11129 06:01:11.695525 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11131 06:01:11.698583 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11132 06:01:11.705163 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11133 06:01:11.708379
11134 06:01:11.711832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11135 06:01:11.712109 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11137 06:01:11.718300 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11138 06:01:11.724772 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11139 06:01:11.724854
11140 06:01:11.731428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11141 06:01:11.731682 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11143 06:01:11.738189 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11144 06:01:11.744764 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11145 06:01:11.744848
11146 06:01:11.751244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11147 06:01:11.751498 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11149 06:01:11.754724 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11150 06:01:11.764562 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11151 06:01:11.764670
11152 06:01:11.767925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11153 06:01:11.768181 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11155 06:01:11.774138 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11156 06:01:11.784378 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11157 06:01:11.784457
11158 06:01:11.787874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11159 06:01:11.788119 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11161 06:01:11.794017 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11162 06:01:11.801045 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11163 06:01:11.801146
11164 06:01:11.807564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11165 06:01:11.807818 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11167 06:01:11.810508 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11168 06:01:11.820349 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11169 06:01:11.820424
11170 06:01:11.827373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11171 06:01:11.827646 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11173 06:01:11.834003 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11174 06:01:11.840367 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11175 06:01:11.840448
11176 06:01:11.846898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11177 06:01:11.847153 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11179 06:01:11.853834 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11180 06:01:11.860449 Check the cros battery ABI. ... skipped 'No BAT found'
11181 06:01:11.860526
11182 06:01:11.866481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11183 06:01:11.866732 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11185 06:01:11.873065 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11186 06:01:11.879795 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11187 06:01:11.879876
11188 06:01:11.886725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11189 06:01:11.886978 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11191 06:01:11.889823 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11192 06:01:11.896621 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11193 06:01:11.896711
11194 06:01:11.902954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11195 06:01:11.903209 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11197 06:01:11.909903 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11198 06:01:11.916213 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11199 06:01:11.916290
11200 06:01:11.922924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11201 06:01:11.923004
11202 06:01:11.923245 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11204 06:01:11.929549 ----------------------------------------------------------------------
11205 06:01:11.932947 Ran 18 tests in 0.007s
11206 06:01:11.933027
11207 06:01:11.933090 OK (skipped=15)
11208 06:01:11.935939 + set +x
11209 06:01:11.936020 <LAVA_TEST_RUNNER EXIT>
11210 06:01:11.936258 ok: lava_test_shell seems to have completed
11211 06:01:11.936426 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11212 06:01:11.936525 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11213 06:01:11.936611 end: 3 lava-test-retry (duration 00:00:01) [common]
11214 06:01:11.936697 start: 4 finalize (timeout 00:07:20) [common]
11215 06:01:11.936782 start: 4.1 power-off (timeout 00:00:30) [common]
11216 06:01:11.936932 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11217 06:01:12.012683 >> Command sent successfully.
11218 06:01:12.015109 Returned 0 in 0 seconds
11219 06:01:12.115543 end: 4.1 power-off (duration 00:00:00) [common]
11221 06:01:12.115898 start: 4.2 read-feedback (timeout 00:07:20) [common]
11222 06:01:12.116165 Listened to connection for namespace 'common' for up to 1s
11223 06:01:13.116917 Finalising connection for namespace 'common'
11224 06:01:13.117080 Disconnecting from shell: Finalise
11225 06:01:13.117164 / #
11226 06:01:13.217487 end: 4.2 read-feedback (duration 00:00:01) [common]
11227 06:01:13.217642 end: 4 finalize (duration 00:00:01) [common]
11228 06:01:13.217764 Cleaning after the job
11229 06:01:13.217867 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379461/tftp-deploy-s7pdjngo/ramdisk
11230 06:01:13.224524 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379461/tftp-deploy-s7pdjngo/kernel
11231 06:01:13.233010 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379461/tftp-deploy-s7pdjngo/dtb
11232 06:01:13.233167 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379461/tftp-deploy-s7pdjngo/modules
11233 06:01:13.240442 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12379461
11234 06:01:13.360061 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12379461
11235 06:01:13.360238 Job finished correctly