Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 15
- Kernel Errors: 33
- Errors: 0
1 05:55:26.109757 lava-dispatcher, installed at version: 2023.10
2 05:55:26.110007 start: 0 validate
3 05:55:26.110182 Start time: 2023-12-25 05:55:26.110171+00:00 (UTC)
4 05:55:26.110325 Using caching service: 'http://localhost/cache/?uri=%s'
5 05:55:26.110456 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 05:55:26.382520 Using caching service: 'http://localhost/cache/?uri=%s'
7 05:55:26.382684 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 05:55:26.648480 Using caching service: 'http://localhost/cache/?uri=%s'
9 05:55:26.648650 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 05:55:26.914172 Using caching service: 'http://localhost/cache/?uri=%s'
11 05:55:26.914363 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 05:55:27.443506 validate duration: 1.33
14 05:55:27.443892 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:55:27.444033 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:55:27.444155 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:55:27.444326 Not decompressing ramdisk as can be used compressed.
18 05:55:27.444452 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 05:55:27.444527 saving as /var/lib/lava/dispatcher/tmp/12379421/tftp-deploy-gmkmbio6/ramdisk/rootfs.cpio.gz
20 05:55:27.444593 total size: 43284872 (41 MB)
21 05:55:27.445724 progress 0 % (0 MB)
22 05:55:27.458048 progress 5 % (2 MB)
23 05:55:27.469941 progress 10 % (4 MB)
24 05:55:27.481814 progress 15 % (6 MB)
25 05:55:27.493739 progress 20 % (8 MB)
26 05:55:27.506234 progress 25 % (10 MB)
27 05:55:27.518699 progress 30 % (12 MB)
28 05:55:27.531798 progress 35 % (14 MB)
29 05:55:27.544600 progress 40 % (16 MB)
30 05:55:27.557244 progress 45 % (18 MB)
31 05:55:27.570972 progress 50 % (20 MB)
32 05:55:27.584363 progress 55 % (22 MB)
33 05:55:27.597725 progress 60 % (24 MB)
34 05:55:27.611253 progress 65 % (26 MB)
35 05:55:27.624452 progress 70 % (28 MB)
36 05:55:27.636913 progress 75 % (30 MB)
37 05:55:27.649258 progress 80 % (33 MB)
38 05:55:27.660712 progress 85 % (35 MB)
39 05:55:27.672146 progress 90 % (37 MB)
40 05:55:27.683404 progress 95 % (39 MB)
41 05:55:27.695314 progress 100 % (41 MB)
42 05:55:27.695646 41 MB downloaded in 0.25 s (164.43 MB/s)
43 05:55:27.695880 end: 1.1.1 http-download (duration 00:00:00) [common]
45 05:55:27.696298 end: 1.1 download-retry (duration 00:00:00) [common]
46 05:55:27.696422 start: 1.2 download-retry (timeout 00:10:00) [common]
47 05:55:27.696551 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 05:55:27.696729 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 05:55:27.696836 saving as /var/lib/lava/dispatcher/tmp/12379421/tftp-deploy-gmkmbio6/kernel/Image
50 05:55:27.696933 total size: 50024960 (47 MB)
51 05:55:27.697037 No compression specified
52 05:55:27.698692 progress 0 % (0 MB)
53 05:55:27.712915 progress 5 % (2 MB)
54 05:55:27.727052 progress 10 % (4 MB)
55 05:55:27.741094 progress 15 % (7 MB)
56 05:55:27.755453 progress 20 % (9 MB)
57 05:55:27.769046 progress 25 % (11 MB)
58 05:55:27.782931 progress 30 % (14 MB)
59 05:55:27.796759 progress 35 % (16 MB)
60 05:55:27.810997 progress 40 % (19 MB)
61 05:55:27.825224 progress 45 % (21 MB)
62 05:55:27.839594 progress 50 % (23 MB)
63 05:55:27.853776 progress 55 % (26 MB)
64 05:55:27.867603 progress 60 % (28 MB)
65 05:55:27.881172 progress 65 % (31 MB)
66 05:55:27.894800 progress 70 % (33 MB)
67 05:55:27.908497 progress 75 % (35 MB)
68 05:55:27.922748 progress 80 % (38 MB)
69 05:55:27.936770 progress 85 % (40 MB)
70 05:55:27.950958 progress 90 % (42 MB)
71 05:55:27.965162 progress 95 % (45 MB)
72 05:55:27.978967 progress 100 % (47 MB)
73 05:55:27.979240 47 MB downloaded in 0.28 s (168.99 MB/s)
74 05:55:27.979454 end: 1.2.1 http-download (duration 00:00:00) [common]
76 05:55:27.979844 end: 1.2 download-retry (duration 00:00:00) [common]
77 05:55:27.979970 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:55:27.980100 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:55:27.980277 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 05:55:27.980386 saving as /var/lib/lava/dispatcher/tmp/12379421/tftp-deploy-gmkmbio6/dtb/mt8192-asurada-spherion-r0.dtb
81 05:55:27.980453 total size: 47278 (0 MB)
82 05:55:27.980518 No compression specified
83 05:55:27.981706 progress 69 % (0 MB)
84 05:55:27.982002 progress 100 % (0 MB)
85 05:55:27.982172 0 MB downloaded in 0.00 s (26.26 MB/s)
86 05:55:27.982305 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:55:27.982691 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:55:27.982818 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:55:27.982942 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:55:27.983097 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 05:55:27.983205 saving as /var/lib/lava/dispatcher/tmp/12379421/tftp-deploy-gmkmbio6/modules/modules.tar
93 05:55:27.983299 total size: 8619328 (8 MB)
94 05:55:27.983392 Using unxz to decompress xz
95 05:55:27.988185 progress 0 % (0 MB)
96 05:55:28.010635 progress 5 % (0 MB)
97 05:55:28.035911 progress 10 % (0 MB)
98 05:55:28.060900 progress 15 % (1 MB)
99 05:55:28.086391 progress 20 % (1 MB)
100 05:55:28.111943 progress 25 % (2 MB)
101 05:55:28.139825 progress 30 % (2 MB)
102 05:55:28.172723 progress 35 % (2 MB)
103 05:55:28.198013 progress 40 % (3 MB)
104 05:55:28.224126 progress 45 % (3 MB)
105 05:55:28.251438 progress 50 % (4 MB)
106 05:55:28.277270 progress 55 % (4 MB)
107 05:55:28.302508 progress 60 % (4 MB)
108 05:55:28.328911 progress 65 % (5 MB)
109 05:55:28.356483 progress 70 % (5 MB)
110 05:55:28.381752 progress 75 % (6 MB)
111 05:55:28.410428 progress 80 % (6 MB)
112 05:55:28.438008 progress 85 % (7 MB)
113 05:55:28.464530 progress 90 % (7 MB)
114 05:55:28.495924 progress 95 % (7 MB)
115 05:55:28.527638 progress 100 % (8 MB)
116 05:55:28.532419 8 MB downloaded in 0.55 s (14.97 MB/s)
117 05:55:28.532677 end: 1.4.1 http-download (duration 00:00:01) [common]
119 05:55:28.532955 end: 1.4 download-retry (duration 00:00:01) [common]
120 05:55:28.533050 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 05:55:28.533147 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 05:55:28.533230 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:55:28.533319 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 05:55:28.533548 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa
125 05:55:28.533697 makedir: /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin
126 05:55:28.533806 makedir: /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/tests
127 05:55:28.533910 makedir: /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/results
128 05:55:28.534029 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-add-keys
129 05:55:28.534188 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-add-sources
130 05:55:28.534327 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-background-process-start
131 05:55:28.534463 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-background-process-stop
132 05:55:28.534595 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-common-functions
133 05:55:28.534724 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-echo-ipv4
134 05:55:28.534853 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-install-packages
135 05:55:28.534981 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-installed-packages
136 05:55:28.535107 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-os-build
137 05:55:28.535235 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-probe-channel
138 05:55:28.535363 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-probe-ip
139 05:55:28.535492 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-target-ip
140 05:55:28.535620 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-target-mac
141 05:55:28.535749 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-target-storage
142 05:55:28.535883 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-test-case
143 05:55:28.536012 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-test-event
144 05:55:28.536141 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-test-feedback
145 05:55:28.536270 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-test-raise
146 05:55:28.536419 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-test-reference
147 05:55:28.536549 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-test-runner
148 05:55:28.536677 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-test-set
149 05:55:28.536806 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-test-shell
150 05:55:28.536940 Updating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-install-packages (oe)
151 05:55:28.537097 Updating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/bin/lava-installed-packages (oe)
152 05:55:28.537231 Creating /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/environment
153 05:55:28.537335 LAVA metadata
154 05:55:28.537414 - LAVA_JOB_ID=12379421
155 05:55:28.537481 - LAVA_DISPATCHER_IP=192.168.201.1
156 05:55:28.537587 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 05:55:28.537654 skipped lava-vland-overlay
158 05:55:28.537729 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 05:55:28.537809 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 05:55:28.537879 skipped lava-multinode-overlay
161 05:55:28.537957 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 05:55:28.538045 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 05:55:28.538120 Loading test definitions
164 05:55:28.538215 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 05:55:28.538291 Using /lava-12379421 at stage 0
166 05:55:28.538618 uuid=12379421_1.5.2.3.1 testdef=None
167 05:55:28.538709 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 05:55:28.538797 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 05:55:28.539336 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 05:55:28.539560 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 05:55:28.540193 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 05:55:28.540439 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 05:55:28.541056 runner path: /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/0/tests/0_igt-kms-mediatek test_uuid 12379421_1.5.2.3.1
176 05:55:28.541218 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 05:55:28.541429 Creating lava-test-runner.conf files
179 05:55:28.541497 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379421/lava-overlay-g3e3j6aa/lava-12379421/0 for stage 0
180 05:55:28.541589 - 0_igt-kms-mediatek
181 05:55:28.541690 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 05:55:28.541776 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 05:55:28.548533 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 05:55:28.548644 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 05:55:28.548736 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 05:55:28.548822 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 05:55:28.548916 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 05:55:30.054984 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 05:55:30.055405 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 05:55:30.055525 extracting modules file /var/lib/lava/dispatcher/tmp/12379421/tftp-deploy-gmkmbio6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379421/extract-overlay-ramdisk-gv2fmzwb/ramdisk
191 05:55:30.301825 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 05:55:30.301998 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 05:55:30.302099 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379421/compress-overlay-eq51n96f/overlay-1.5.2.4.tar.gz to ramdisk
194 05:55:30.302174 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379421/compress-overlay-eq51n96f/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12379421/extract-overlay-ramdisk-gv2fmzwb/ramdisk
195 05:55:30.308975 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 05:55:30.309115 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 05:55:30.309217 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 05:55:30.309318 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 05:55:30.309404 Building ramdisk /var/lib/lava/dispatcher/tmp/12379421/extract-overlay-ramdisk-gv2fmzwb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12379421/extract-overlay-ramdisk-gv2fmzwb/ramdisk
200 05:55:31.387688 >> 369994 blocks
201 05:55:37.337590 rename /var/lib/lava/dispatcher/tmp/12379421/extract-overlay-ramdisk-gv2fmzwb/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12379421/tftp-deploy-gmkmbio6/ramdisk/ramdisk.cpio.gz
202 05:55:37.338032 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 05:55:37.338163 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 05:55:37.338264 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 05:55:37.338375 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12379421/tftp-deploy-gmkmbio6/kernel/Image'
206 05:55:50.510900 Returned 0 in 13 seconds
207 05:55:50.611821 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12379421/tftp-deploy-gmkmbio6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12379421/tftp-deploy-gmkmbio6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12379421/tftp-deploy-gmkmbio6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12379421/tftp-deploy-gmkmbio6/kernel/image.itb
208 05:55:51.443305 output: FIT description: Kernel Image image with one or more FDT blobs
209 05:55:51.443675 output: Created: Mon Dec 25 05:55:51 2023
210 05:55:51.443750 output: Image 0 (kernel-1)
211 05:55:51.443818 output: Description:
212 05:55:51.443882 output: Created: Mon Dec 25 05:55:51 2023
213 05:55:51.443946 output: Type: Kernel Image
214 05:55:51.444009 output: Compression: lzma compressed
215 05:55:51.444071 output: Data Size: 11481830 Bytes = 11212.72 KiB = 10.95 MiB
216 05:55:51.444130 output: Architecture: AArch64
217 05:55:51.444190 output: OS: Linux
218 05:55:51.444249 output: Load Address: 0x00000000
219 05:55:51.444358 output: Entry Point: 0x00000000
220 05:55:51.444419 output: Hash algo: crc32
221 05:55:51.444479 output: Hash value: a47c00f1
222 05:55:51.444534 output: Image 1 (fdt-1)
223 05:55:51.444588 output: Description: mt8192-asurada-spherion-r0
224 05:55:51.444640 output: Created: Mon Dec 25 05:55:51 2023
225 05:55:51.444693 output: Type: Flat Device Tree
226 05:55:51.444747 output: Compression: uncompressed
227 05:55:51.444800 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 05:55:51.444853 output: Architecture: AArch64
229 05:55:51.444905 output: Hash algo: crc32
230 05:55:51.444958 output: Hash value: cc4352de
231 05:55:51.445011 output: Image 2 (ramdisk-1)
232 05:55:51.445064 output: Description: unavailable
233 05:55:51.445116 output: Created: Mon Dec 25 05:55:51 2023
234 05:55:51.445169 output: Type: RAMDisk Image
235 05:55:51.445222 output: Compression: Unknown Compression
236 05:55:51.445274 output: Data Size: 56435388 Bytes = 55112.68 KiB = 53.82 MiB
237 05:55:51.445326 output: Architecture: AArch64
238 05:55:51.445379 output: OS: Linux
239 05:55:51.445431 output: Load Address: unavailable
240 05:55:51.445484 output: Entry Point: unavailable
241 05:55:51.445536 output: Hash algo: crc32
242 05:55:51.445588 output: Hash value: 897a3c9b
243 05:55:51.445640 output: Default Configuration: 'conf-1'
244 05:55:51.445692 output: Configuration 0 (conf-1)
245 05:55:51.445745 output: Description: mt8192-asurada-spherion-r0
246 05:55:51.445797 output: Kernel: kernel-1
247 05:55:51.445849 output: Init Ramdisk: ramdisk-1
248 05:55:51.445901 output: FDT: fdt-1
249 05:55:51.445953 output: Loadables: kernel-1
250 05:55:51.446005 output:
251 05:55:51.446196 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 05:55:51.446294 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 05:55:51.446395 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 05:55:51.446485 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 05:55:51.446564 No LXC device requested
256 05:55:51.446644 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 05:55:51.446729 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 05:55:51.446807 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 05:55:51.446879 Checking files for TFTP limit of 4294967296 bytes.
260 05:55:51.447373 end: 1 tftp-deploy (duration 00:00:24) [common]
261 05:55:51.447479 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 05:55:51.447571 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 05:55:51.447693 substitutions:
264 05:55:51.447760 - {DTB}: 12379421/tftp-deploy-gmkmbio6/dtb/mt8192-asurada-spherion-r0.dtb
265 05:55:51.447824 - {INITRD}: 12379421/tftp-deploy-gmkmbio6/ramdisk/ramdisk.cpio.gz
266 05:55:51.447883 - {KERNEL}: 12379421/tftp-deploy-gmkmbio6/kernel/Image
267 05:55:51.447942 - {LAVA_MAC}: None
268 05:55:51.447999 - {PRESEED_CONFIG}: None
269 05:55:51.448056 - {PRESEED_LOCAL}: None
270 05:55:51.448111 - {RAMDISK}: 12379421/tftp-deploy-gmkmbio6/ramdisk/ramdisk.cpio.gz
271 05:55:51.448166 - {ROOT_PART}: None
272 05:55:51.448220 - {ROOT}: None
273 05:55:51.448274 - {SERVER_IP}: 192.168.201.1
274 05:55:51.448374 - {TEE}: None
275 05:55:51.448429 Parsed boot commands:
276 05:55:51.448483 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 05:55:51.448666 Parsed boot commands: tftpboot 192.168.201.1 12379421/tftp-deploy-gmkmbio6/kernel/image.itb 12379421/tftp-deploy-gmkmbio6/kernel/cmdline
278 05:55:51.448764 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 05:55:51.448853 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 05:55:51.448955 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 05:55:51.449045 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 05:55:51.449116 Not connected, no need to disconnect.
283 05:55:51.449190 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 05:55:51.449271 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 05:55:51.449341 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 05:55:51.453218 Setting prompt string to ['lava-test: # ']
287 05:55:51.453582 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 05:55:51.453694 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 05:55:51.453790 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 05:55:51.453886 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 05:55:51.454084 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 05:55:56.598729 >> Command sent successfully.
293 05:55:56.609332 Returned 0 in 5 seconds
294 05:55:56.710488 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 05:55:56.711831 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 05:55:56.712418 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 05:55:56.712878 Setting prompt string to 'Starting depthcharge on Spherion...'
299 05:55:56.713326 Changing prompt to 'Starting depthcharge on Spherion...'
300 05:55:56.713690 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 05:55:56.714877 [Enter `^Ec?' for help]
302 05:55:56.877397
303 05:55:56.877948
304 05:55:56.878331 F0: 102B 0000
305 05:55:56.878875
306 05:55:56.879429 F3: 1001 0000 [0200]
307 05:55:56.879779
308 05:55:56.880741 F3: 1001 0000
309 05:55:56.881173
310 05:55:56.881532 F7: 102D 0000
311 05:55:56.881859
312 05:55:56.882166 F1: 0000 0000
313 05:55:56.882471
314 05:55:56.885081 V0: 0000 0000 [0001]
315 05:55:56.885524
316 05:55:56.885875 00: 0007 8000
317 05:55:56.886219
318 05:55:56.888659 01: 0000 0000
319 05:55:56.889099
320 05:55:56.889445 BP: 0C00 0209 [0000]
321 05:55:56.889919
322 05:55:56.890355 G0: 1182 0000
323 05:55:56.891928
324 05:55:56.892399 EC: 0000 0021 [4000]
325 05:55:56.892751
326 05:55:56.895830 S7: 0000 0000 [0000]
327 05:55:56.896263
328 05:55:56.896666 CC: 0000 0000 [0001]
329 05:55:56.896991
330 05:55:56.899158 T0: 0000 0040 [010F]
331 05:55:56.899597
332 05:55:56.899935 Jump to BL
333 05:55:56.900250
334 05:55:56.923937
335 05:55:56.924413
336 05:55:56.924763
337 05:55:56.931968 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 05:55:56.935840 ARM64: Exception handlers installed.
339 05:55:56.938993 ARM64: Testing exception
340 05:55:56.939468 ARM64: Done test exception
341 05:55:56.946270 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 05:55:56.957650 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 05:55:56.965003 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 05:55:56.974783 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 05:55:56.981838 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 05:55:56.991960 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 05:55:57.002478 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 05:55:57.008506 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 05:55:57.026424 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 05:55:57.029611 WDT: Last reset was cold boot
351 05:55:57.033219 SPI1(PAD0) initialized at 2873684 Hz
352 05:55:57.036706 SPI5(PAD0) initialized at 992727 Hz
353 05:55:57.039529 VBOOT: Loading verstage.
354 05:55:57.046680 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 05:55:57.049814 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 05:55:57.054191 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 05:55:57.057650 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 05:55:57.064127 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 05:55:57.071316 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 05:55:57.081348 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 05:55:57.081591
362 05:55:57.081761
363 05:55:57.091861 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 05:55:57.095592 ARM64: Exception handlers installed.
365 05:55:57.098819 ARM64: Testing exception
366 05:55:57.099035 ARM64: Done test exception
367 05:55:57.105574 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 05:55:57.108637 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 05:55:57.123065 Probing TPM: . done!
370 05:55:57.123552 TPM ready after 0 ms
371 05:55:57.129396 Connected to device vid:did:rid of 1ae0:0028:00
372 05:55:57.136384 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 05:55:57.196326 Initialized TPM device CR50 revision 0
374 05:55:57.206937 tlcl_send_startup: Startup return code is 0
375 05:55:57.207371 TPM: setup succeeded
376 05:55:57.219119 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 05:55:57.227457 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 05:55:57.241843 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 05:55:57.248371 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 05:55:57.251345 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 05:55:57.255712 in-header: 03 07 00 00 08 00 00 00
382 05:55:57.259201 in-data: aa e4 47 04 13 02 00 00
383 05:55:57.262701 Chrome EC: UHEPI supported
384 05:55:57.269855 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 05:55:57.273207 in-header: 03 95 00 00 08 00 00 00
386 05:55:57.276864 in-data: 18 20 20 08 00 00 00 00
387 05:55:57.277294 Phase 1
388 05:55:57.280987 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 05:55:57.288076 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 05:55:57.292186 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 05:55:57.296002 Recovery requested (1009000e)
392 05:55:57.304125 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 05:55:57.309919 tlcl_extend: response is 0
394 05:55:57.318794 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 05:55:57.324275 tlcl_extend: response is 0
396 05:55:57.331813 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 05:55:57.351517 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 05:55:57.358082 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 05:55:57.358623
400 05:55:57.358972
401 05:55:57.367967 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 05:55:57.371371 ARM64: Exception handlers installed.
403 05:55:57.374769 ARM64: Testing exception
404 05:55:57.375201 ARM64: Done test exception
405 05:55:57.397279 pmic_efuse_setting: Set efuses in 11 msecs
406 05:55:57.399817 pmwrap_interface_init: Select PMIF_VLD_RDY
407 05:55:57.407194 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 05:55:57.410813 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 05:55:57.417470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 05:55:57.421554 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 05:55:57.425406 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 05:55:57.428125 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 05:55:57.435881 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 05:55:57.438873 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 05:55:57.442803 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 05:55:57.450253 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 05:55:57.453772 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 05:55:57.457147 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 05:55:57.461320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 05:55:57.469185 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 05:55:57.476351 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 05:55:57.480047 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 05:55:57.487322 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 05:55:57.491481 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 05:55:57.499437 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 05:55:57.502513 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 05:55:57.510061 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 05:55:57.513541 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 05:55:57.520711 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 05:55:57.525056 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 05:55:57.532235 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 05:55:57.535498 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 05:55:57.539637 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 05:55:57.546820 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 05:55:57.550333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 05:55:57.554243 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 05:55:57.561776 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 05:55:57.564965 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 05:55:57.572278 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 05:55:57.575922 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 05:55:57.579549 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 05:55:57.587703 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 05:55:57.591489 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 05:55:57.595418 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 05:55:57.598991 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 05:55:57.606108 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 05:55:57.609631 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 05:55:57.613373 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 05:55:57.617439 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 05:55:57.620897 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 05:55:57.628822 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 05:55:57.632279 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 05:55:57.636512 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 05:55:57.640010 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 05:55:57.643742 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 05:55:57.647469 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 05:55:57.650955 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 05:55:57.658701 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 05:55:57.669264 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 05:55:57.672873 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 05:55:57.679851 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 05:55:57.690784 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 05:55:57.695011 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 05:55:57.698457 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 05:55:57.701980 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 05:55:57.709913 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2e
467 05:55:57.714144 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 05:55:57.718543 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 05:55:57.725767 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 05:55:57.734068 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 05:55:57.744103 [RTC]rtc_get_frequency_meter,154: input=23, output=941
472 05:55:57.753652 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 05:55:57.763012 [RTC]rtc_get_frequency_meter,154: input=17, output=804
474 05:55:57.772876 [RTC]rtc_get_frequency_meter,154: input=16, output=781
475 05:55:57.781763 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 05:55:57.790920 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 05:55:57.794250 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 05:55:57.801955 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 05:55:57.805821 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 05:55:57.809620 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 05:55:57.813492 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 05:55:57.817065 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 05:55:57.821500 ADC[4]: Raw value=905834 ID=7
484 05:55:57.821862 ADC[3]: Raw value=213441 ID=1
485 05:55:57.824608 RAM Code: 0x71
486 05:55:57.828834 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 05:55:57.832318 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 05:55:57.843692 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 05:55:57.847187 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 05:55:57.850750 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 05:55:57.854468 in-header: 03 07 00 00 08 00 00 00
492 05:55:57.858230 in-data: aa e4 47 04 13 02 00 00
493 05:55:57.862543 Chrome EC: UHEPI supported
494 05:55:57.868903 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 05:55:57.872577 in-header: 03 95 00 00 08 00 00 00
496 05:55:57.876887 in-data: 18 20 20 08 00 00 00 00
497 05:55:57.877315 MRC: failed to locate region type 0.
498 05:55:57.883988 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 05:55:57.888160 DRAM-K: Running full calibration
500 05:55:57.892210 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 05:55:57.895874 header.status = 0x0
502 05:55:57.899591 header.version = 0x6 (expected: 0x6)
503 05:55:57.903481 header.size = 0xd00 (expected: 0xd00)
504 05:55:57.903910 header.flags = 0x0
505 05:55:57.910480 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 05:55:57.928895 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 05:55:57.935681 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 05:55:57.936128 dram_init: ddr_geometry: 2
509 05:55:57.939510 [EMI] MDL number = 2
510 05:55:57.943198 [EMI] Get MDL freq = 0
511 05:55:57.943832 dram_init: ddr_type: 0
512 05:55:57.947093 is_discrete_lpddr4: 1
513 05:55:57.947586 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 05:55:57.951312
515 05:55:57.951734
516 05:55:57.952071 [Bian_co] ETT version 0.0.0.1
517 05:55:57.958667 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 05:55:57.959097
519 05:55:57.962255 dramc_set_vcore_voltage set vcore to 650000
520 05:55:57.962719 Read voltage for 800, 4
521 05:55:57.963229 Vio18 = 0
522 05:55:57.965944 Vcore = 650000
523 05:55:57.966613 Vdram = 0
524 05:55:57.967170 Vddq = 0
525 05:55:57.969342 Vmddr = 0
526 05:55:57.969965 dram_init: config_dvfs: 1
527 05:55:57.977256 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 05:55:57.980758 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 05:55:57.984397 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 05:55:57.988086 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 05:55:57.992128 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 05:55:57.994890 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 05:55:57.998422 MEM_TYPE=3, freq_sel=18
534 05:55:58.001755 sv_algorithm_assistance_LP4_1600
535 05:55:58.005388 ============ PULL DRAM RESETB DOWN ============
536 05:55:58.008988 ========== PULL DRAM RESETB DOWN end =========
537 05:55:58.012203 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 05:55:58.016413 ===================================
539 05:55:58.019802 LPDDR4 DRAM CONFIGURATION
540 05:55:58.023365 ===================================
541 05:55:58.023806 EX_ROW_EN[0] = 0x0
542 05:55:58.026656 EX_ROW_EN[1] = 0x0
543 05:55:58.027108 LP4Y_EN = 0x0
544 05:55:58.030897 WORK_FSP = 0x0
545 05:55:58.031351 WL = 0x2
546 05:55:58.034407 RL = 0x2
547 05:55:58.034859 BL = 0x2
548 05:55:58.037981 RPST = 0x0
549 05:55:58.038432 RD_PRE = 0x0
550 05:55:58.041863 WR_PRE = 0x1
551 05:55:58.042316 WR_PST = 0x0
552 05:55:58.044798 DBI_WR = 0x0
553 05:55:58.045298 DBI_RD = 0x0
554 05:55:58.047758 OTF = 0x1
555 05:55:58.051263 ===================================
556 05:55:58.054804 ===================================
557 05:55:58.055313 ANA top config
558 05:55:58.058581 ===================================
559 05:55:58.061738 DLL_ASYNC_EN = 0
560 05:55:58.065652 ALL_SLAVE_EN = 1
561 05:55:58.065910 NEW_RANK_MODE = 1
562 05:55:58.068205 DLL_IDLE_MODE = 1
563 05:55:58.071688 LP45_APHY_COMB_EN = 1
564 05:55:58.075161 TX_ODT_DIS = 1
565 05:55:58.075361 NEW_8X_MODE = 1
566 05:55:58.078717 ===================================
567 05:55:58.082350 ===================================
568 05:55:58.085298 data_rate = 1600
569 05:55:58.088924 CKR = 1
570 05:55:58.092586 DQ_P2S_RATIO = 8
571 05:55:58.095308 ===================================
572 05:55:58.098763 CA_P2S_RATIO = 8
573 05:55:58.098889 DQ_CA_OPEN = 0
574 05:55:58.102297 DQ_SEMI_OPEN = 0
575 05:55:58.105121 CA_SEMI_OPEN = 0
576 05:55:58.108873 CA_FULL_RATE = 0
577 05:55:58.112170 DQ_CKDIV4_EN = 1
578 05:55:58.115698 CA_CKDIV4_EN = 1
579 05:55:58.115832 CA_PREDIV_EN = 0
580 05:55:58.119061 PH8_DLY = 0
581 05:55:58.122374 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 05:55:58.125892 DQ_AAMCK_DIV = 4
583 05:55:58.128759 CA_AAMCK_DIV = 4
584 05:55:58.128878 CA_ADMCK_DIV = 4
585 05:55:58.132540 DQ_TRACK_CA_EN = 0
586 05:55:58.136117 CA_PICK = 800
587 05:55:58.139221 CA_MCKIO = 800
588 05:55:58.143025 MCKIO_SEMI = 0
589 05:55:58.146498 PLL_FREQ = 3068
590 05:55:58.150356 DQ_UI_PI_RATIO = 32
591 05:55:58.150847 CA_UI_PI_RATIO = 0
592 05:55:58.153972 ===================================
593 05:55:58.157637 ===================================
594 05:55:58.161049 memory_type:LPDDR4
595 05:55:58.161533 GP_NUM : 10
596 05:55:58.164576 SRAM_EN : 1
597 05:55:58.165028 MD32_EN : 0
598 05:55:58.168741 ===================================
599 05:55:58.172226 [ANA_INIT] >>>>>>>>>>>>>>
600 05:55:58.176340 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 05:55:58.179692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 05:55:58.182835 ===================================
603 05:55:58.183301 data_rate = 1600,PCW = 0X7600
604 05:55:58.185896 ===================================
605 05:55:58.189752 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 05:55:58.196074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 05:55:58.202683 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 05:55:58.206193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 05:55:58.209502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 05:55:58.212991 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 05:55:58.215912 [ANA_INIT] flow start
612 05:55:58.216432 [ANA_INIT] PLL >>>>>>>>
613 05:55:58.219631 [ANA_INIT] PLL <<<<<<<<
614 05:55:58.222993 [ANA_INIT] MIDPI >>>>>>>>
615 05:55:58.226315 [ANA_INIT] MIDPI <<<<<<<<
616 05:55:58.226902 [ANA_INIT] DLL >>>>>>>>
617 05:55:58.229474 [ANA_INIT] flow end
618 05:55:58.233106 ============ LP4 DIFF to SE enter ============
619 05:55:58.236681 ============ LP4 DIFF to SE exit ============
620 05:55:58.239838 [ANA_INIT] <<<<<<<<<<<<<
621 05:55:58.242947 [Flow] Enable top DCM control >>>>>
622 05:55:58.246029 [Flow] Enable top DCM control <<<<<
623 05:55:58.249540 Enable DLL master slave shuffle
624 05:55:58.256387 ==============================================================
625 05:55:58.256910 Gating Mode config
626 05:55:58.263109 ==============================================================
627 05:55:58.263685 Config description:
628 05:55:58.273140 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 05:55:58.279460 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 05:55:58.286663 SELPH_MODE 0: By rank 1: By Phase
631 05:55:58.290082 ==============================================================
632 05:55:58.292873 GAT_TRACK_EN = 1
633 05:55:58.296247 RX_GATING_MODE = 2
634 05:55:58.299532 RX_GATING_TRACK_MODE = 2
635 05:55:58.302796 SELPH_MODE = 1
636 05:55:58.306527 PICG_EARLY_EN = 1
637 05:55:58.309983 VALID_LAT_VALUE = 1
638 05:55:58.312815 ==============================================================
639 05:55:58.316357 Enter into Gating configuration >>>>
640 05:55:58.319834 Exit from Gating configuration <<<<
641 05:55:58.322700 Enter into DVFS_PRE_config >>>>>
642 05:55:58.336697 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 05:55:58.337359 Exit from DVFS_PRE_config <<<<<
644 05:55:58.339738 Enter into PICG configuration >>>>
645 05:55:58.342959 Exit from PICG configuration <<<<
646 05:55:58.346293 [RX_INPUT] configuration >>>>>
647 05:55:58.349907 [RX_INPUT] configuration <<<<<
648 05:55:58.356715 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 05:55:58.360153 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 05:55:58.366540 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 05:55:58.373026 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 05:55:58.380201 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 05:55:58.386464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 05:55:58.390237 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 05:55:58.393185 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 05:55:58.396799 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 05:55:58.400257 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 05:55:58.406612 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 05:55:58.409818 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 05:55:58.413329 ===================================
661 05:55:58.416554 LPDDR4 DRAM CONFIGURATION
662 05:55:58.419577 ===================================
663 05:55:58.420214 EX_ROW_EN[0] = 0x0
664 05:55:58.422903 EX_ROW_EN[1] = 0x0
665 05:55:58.423495 LP4Y_EN = 0x0
666 05:55:58.426567 WORK_FSP = 0x0
667 05:55:58.427175 WL = 0x2
668 05:55:58.430322 RL = 0x2
669 05:55:58.430756 BL = 0x2
670 05:55:58.433165 RPST = 0x0
671 05:55:58.433739 RD_PRE = 0x0
672 05:55:58.436671 WR_PRE = 0x1
673 05:55:58.437108 WR_PST = 0x0
674 05:55:58.440234 DBI_WR = 0x0
675 05:55:58.443604 DBI_RD = 0x0
676 05:55:58.444037 OTF = 0x1
677 05:55:58.446465 ===================================
678 05:55:58.449941 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 05:55:58.453135 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 05:55:58.460103 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 05:55:58.463728 ===================================
682 05:55:58.464271 LPDDR4 DRAM CONFIGURATION
683 05:55:58.466837 ===================================
684 05:55:58.469964 EX_ROW_EN[0] = 0x10
685 05:55:58.473091 EX_ROW_EN[1] = 0x0
686 05:55:58.473525 LP4Y_EN = 0x0
687 05:55:58.477101 WORK_FSP = 0x0
688 05:55:58.477536 WL = 0x2
689 05:55:58.480065 RL = 0x2
690 05:55:58.480680 BL = 0x2
691 05:55:58.483653 RPST = 0x0
692 05:55:58.484096 RD_PRE = 0x0
693 05:55:58.486608 WR_PRE = 0x1
694 05:55:58.487065 WR_PST = 0x0
695 05:55:58.489986 DBI_WR = 0x0
696 05:55:58.490431 DBI_RD = 0x0
697 05:55:58.493557 OTF = 0x1
698 05:55:58.496941 ===================================
699 05:55:58.503563 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 05:55:58.506341 nWR fixed to 40
701 05:55:58.510042 [ModeRegInit_LP4] CH0 RK0
702 05:55:58.510487 [ModeRegInit_LP4] CH0 RK1
703 05:55:58.513461 [ModeRegInit_LP4] CH1 RK0
704 05:55:58.516209 [ModeRegInit_LP4] CH1 RK1
705 05:55:58.516701 match AC timing 13
706 05:55:58.523502 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 05:55:58.526804 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 05:55:58.530226 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 05:55:58.536615 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 05:55:58.539898 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 05:55:58.540383 [EMI DOE] emi_dcm 0
712 05:55:58.546891 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 05:55:58.547338 ==
714 05:55:58.549935 Dram Type= 6, Freq= 0, CH_0, rank 0
715 05:55:58.553436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 05:55:58.554013 ==
717 05:55:58.559878 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 05:55:58.563212 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 05:55:58.573934 [CA 0] Center 36 (6~67) winsize 62
720 05:55:58.577268 [CA 1] Center 36 (6~67) winsize 62
721 05:55:58.580428 [CA 2] Center 34 (4~65) winsize 62
722 05:55:58.583384 [CA 3] Center 33 (3~64) winsize 62
723 05:55:58.587138 [CA 4] Center 33 (3~64) winsize 62
724 05:55:58.590379 [CA 5] Center 32 (2~62) winsize 61
725 05:55:58.590821
726 05:55:58.593797 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 05:55:58.594334
728 05:55:58.597231 [CATrainingPosCal] consider 1 rank data
729 05:55:58.600772 u2DelayCellTimex100 = 270/100 ps
730 05:55:58.603725 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 05:55:58.607311 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 05:55:58.613718 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 05:55:58.617379 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 05:55:58.620740 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 05:55:58.623460 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 05:55:58.623931
737 05:55:58.627124 CA PerBit enable=1, Macro0, CA PI delay=32
738 05:55:58.627628
739 05:55:58.630749 [CBTSetCACLKResult] CA Dly = 32
740 05:55:58.631312 CS Dly: 5 (0~36)
741 05:55:58.631799 ==
742 05:55:58.633679 Dram Type= 6, Freq= 0, CH_0, rank 1
743 05:55:58.640789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 05:55:58.641217 ==
745 05:55:58.644253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 05:55:58.650554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 05:55:58.659846 [CA 0] Center 36 (6~67) winsize 62
748 05:55:58.663504 [CA 1] Center 36 (6~67) winsize 62
749 05:55:58.666382 [CA 2] Center 34 (4~65) winsize 62
750 05:55:58.670010 [CA 3] Center 34 (3~65) winsize 63
751 05:55:58.673495 [CA 4] Center 33 (3~63) winsize 61
752 05:55:58.676427 [CA 5] Center 32 (2~63) winsize 62
753 05:55:58.676865
754 05:55:58.680034 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 05:55:58.680571
756 05:55:58.683554 [CATrainingPosCal] consider 2 rank data
757 05:55:58.686303 u2DelayCellTimex100 = 270/100 ps
758 05:55:58.689610 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 05:55:58.692781 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 05:55:58.699911 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 05:55:58.703236 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 05:55:58.706296 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 05:55:58.710336 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 05:55:58.710773
765 05:55:58.713628 CA PerBit enable=1, Macro0, CA PI delay=32
766 05:55:58.714065
767 05:55:58.716952 [CBTSetCACLKResult] CA Dly = 32
768 05:55:58.717421 CS Dly: 5 (0~37)
769 05:55:58.717806
770 05:55:58.719737 ----->DramcWriteLeveling(PI) begin...
771 05:55:58.723571 ==
772 05:55:58.724034 Dram Type= 6, Freq= 0, CH_0, rank 0
773 05:55:58.730654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 05:55:58.731207 ==
775 05:55:58.731666 Write leveling (Byte 0): 32 => 32
776 05:55:58.734326 Write leveling (Byte 1): 30 => 30
777 05:55:58.738205 DramcWriteLeveling(PI) end<-----
778 05:55:58.738695
779 05:55:58.739108 ==
780 05:55:58.741821 Dram Type= 6, Freq= 0, CH_0, rank 0
781 05:55:58.745456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 05:55:58.745886 ==
783 05:55:58.748242 [Gating] SW mode calibration
784 05:55:58.756273 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 05:55:58.759876 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 05:55:58.766241 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 05:55:58.769543 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 05:55:58.773203 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 05:55:58.779804 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 05:55:58.782661 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 05:55:58.786074 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 05:55:58.793520 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 05:55:58.796254 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 05:55:58.799922 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 05:55:58.806743 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 05:55:58.809508 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 05:55:58.812803 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 05:55:58.819649 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 05:55:58.823056 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 05:55:58.826684 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 05:55:58.833319 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 05:55:58.836348 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 05:55:58.839705 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 05:55:58.846428 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
805 05:55:58.849837 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 05:55:58.853324 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 05:55:58.856282 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 05:55:58.863532 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 05:55:58.866579 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 05:55:58.869908 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 05:55:58.876857 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 05:55:58.879650 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
813 05:55:58.883258 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 05:55:58.889699 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 05:55:58.892903 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 05:55:58.896549 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 05:55:58.903387 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 05:55:58.906887 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 05:55:58.910122 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
820 05:55:58.916858 0 10 8 | B1->B0 | 3030 2a2a | 0 0 | (0 1) (1 0)
821 05:55:58.919609 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 05:55:58.923592 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 05:55:58.926418 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 05:55:58.933523 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 05:55:58.937088 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 05:55:58.940397 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 05:55:58.946552 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
828 05:55:58.949824 0 11 8 | B1->B0 | 2d2d 3d3d | 0 0 | (0 0) (0 0)
829 05:55:58.953357 0 11 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
830 05:55:58.960353 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 05:55:58.963188 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 05:55:58.966464 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 05:55:58.973645 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 05:55:58.977236 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 05:55:58.980257 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 05:55:58.987232 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 05:55:58.990032 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 05:55:58.993408 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 05:55:58.996818 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 05:55:59.003413 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 05:55:59.006761 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 05:55:59.010270 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 05:55:59.017091 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 05:55:59.020685 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 05:55:59.023480 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 05:55:59.030372 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 05:55:59.033572 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 05:55:59.037223 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 05:55:59.043556 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 05:55:59.046963 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 05:55:59.050657 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 05:55:59.056971 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 05:55:59.060260 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 05:55:59.063613 Total UI for P1: 0, mck2ui 16
855 05:55:59.066761 best dqsien dly found for B0: ( 0, 14, 6)
856 05:55:59.070175 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 05:55:59.073709 Total UI for P1: 0, mck2ui 16
858 05:55:59.077768 best dqsien dly found for B1: ( 0, 14, 12)
859 05:55:59.081413 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
860 05:55:59.084217 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
861 05:55:59.084485
862 05:55:59.087743 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 05:55:59.091314 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
864 05:55:59.093987 [Gating] SW calibration Done
865 05:55:59.094160 ==
866 05:55:59.097598 Dram Type= 6, Freq= 0, CH_0, rank 0
867 05:55:59.101191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 05:55:59.101404 ==
869 05:55:59.103939 RX Vref Scan: 0
870 05:55:59.104062
871 05:55:59.107438 RX Vref 0 -> 0, step: 1
872 05:55:59.107562
873 05:55:59.107672 RX Delay -130 -> 252, step: 16
874 05:55:59.114442 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
875 05:55:59.118078 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
876 05:55:59.120890 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 05:55:59.124576 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 05:55:59.127867 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
879 05:55:59.134399 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
880 05:55:59.137749 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
881 05:55:59.141006 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
882 05:55:59.144202 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
883 05:55:59.147354 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
884 05:55:59.154573 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
885 05:55:59.157570 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
886 05:55:59.160990 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
887 05:55:59.164885 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
888 05:55:59.167672 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
889 05:55:59.174453 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
890 05:55:59.174548 ==
891 05:55:59.178136 Dram Type= 6, Freq= 0, CH_0, rank 0
892 05:55:59.181488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 05:55:59.181948 ==
894 05:55:59.182358 DQS Delay:
895 05:55:59.184870 DQS0 = 0, DQS1 = 0
896 05:55:59.185315 DQM Delay:
897 05:55:59.188366 DQM0 = 90, DQM1 = 84
898 05:55:59.188845 DQ Delay:
899 05:55:59.191915 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
900 05:55:59.194944 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
901 05:55:59.198381 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
902 05:55:59.202048 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
903 05:55:59.202693
904 05:55:59.203241
905 05:55:59.203744 ==
906 05:55:59.204967 Dram Type= 6, Freq= 0, CH_0, rank 0
907 05:55:59.208459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 05:55:59.208915 ==
909 05:55:59.209261
910 05:55:59.209585
911 05:55:59.212067 TX Vref Scan disable
912 05:55:59.214818 == TX Byte 0 ==
913 05:55:59.218268 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
914 05:55:59.221566 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
915 05:55:59.225153 == TX Byte 1 ==
916 05:55:59.228846 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
917 05:55:59.231702 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
918 05:55:59.232137 ==
919 05:55:59.235253 Dram Type= 6, Freq= 0, CH_0, rank 0
920 05:55:59.238760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 05:55:59.242184 ==
922 05:55:59.253169 TX Vref=22, minBit 7, minWin=27, winSum=444
923 05:55:59.256860 TX Vref=24, minBit 10, minWin=27, winSum=453
924 05:55:59.260245 TX Vref=26, minBit 9, minWin=27, winSum=454
925 05:55:59.263078 TX Vref=28, minBit 8, minWin=28, winSum=460
926 05:55:59.266499 TX Vref=30, minBit 8, minWin=28, winSum=460
927 05:55:59.269755 TX Vref=32, minBit 11, minWin=27, winSum=458
928 05:55:59.276638 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 28
929 05:55:59.276872
930 05:55:59.280216 Final TX Range 1 Vref 28
931 05:55:59.280484
932 05:55:59.280672 ==
933 05:55:59.283096 Dram Type= 6, Freq= 0, CH_0, rank 0
934 05:55:59.286423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 05:55:59.286648 ==
936 05:55:59.286779
937 05:55:59.289650
938 05:55:59.289805 TX Vref Scan disable
939 05:55:59.293237 == TX Byte 0 ==
940 05:55:59.296433 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
941 05:55:59.299820 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
942 05:55:59.302809 == TX Byte 1 ==
943 05:55:59.306218 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
944 05:55:59.309879 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
945 05:55:59.313610
946 05:55:59.313704 [DATLAT]
947 05:55:59.313777 Freq=800, CH0 RK0
948 05:55:59.313841
949 05:55:59.316503 DATLAT Default: 0xa
950 05:55:59.316615 0, 0xFFFF, sum = 0
951 05:55:59.320063 1, 0xFFFF, sum = 0
952 05:55:59.320189 2, 0xFFFF, sum = 0
953 05:55:59.323602 3, 0xFFFF, sum = 0
954 05:55:59.323690 4, 0xFFFF, sum = 0
955 05:55:59.326419 5, 0xFFFF, sum = 0
956 05:55:59.326535 6, 0xFFFF, sum = 0
957 05:55:59.329951 7, 0xFFFF, sum = 0
958 05:55:59.330037 8, 0xFFFF, sum = 0
959 05:55:59.333630 9, 0x0, sum = 1
960 05:55:59.333739 10, 0x0, sum = 2
961 05:55:59.336545 11, 0x0, sum = 3
962 05:55:59.336630 12, 0x0, sum = 4
963 05:55:59.356773 best_step = 10
964 05:55:59.356873
965 05:55:59.356942 ==
966 05:55:59.357004 Dram Type= 6, Freq= 0, CH_0, rank 0
967 05:55:59.357063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 05:55:59.357122 ==
969 05:55:59.357180 RX Vref Scan: 1
970 05:55:59.357236
971 05:55:59.357323 Set Vref Range= 32 -> 127
972 05:55:59.357393
973 05:55:59.357448 RX Vref 32 -> 127, step: 1
974 05:55:59.357503
975 05:55:59.357557 RX Delay -95 -> 252, step: 8
976 05:55:59.357619
977 05:55:59.359759 Set Vref, RX VrefLevel [Byte0]: 32
978 05:55:59.363200 [Byte1]: 32
979 05:55:59.363282
980 05:55:59.366684 Set Vref, RX VrefLevel [Byte0]: 33
981 05:55:59.370454 [Byte1]: 33
982 05:55:59.373242
983 05:55:59.373319 Set Vref, RX VrefLevel [Byte0]: 34
984 05:55:59.377002 [Byte1]: 34
985 05:55:59.381192
986 05:55:59.381267 Set Vref, RX VrefLevel [Byte0]: 35
987 05:55:59.384724 [Byte1]: 35
988 05:55:59.388881
989 05:55:59.388970 Set Vref, RX VrefLevel [Byte0]: 36
990 05:55:59.392173 [Byte1]: 36
991 05:55:59.396272
992 05:55:59.396395 Set Vref, RX VrefLevel [Byte0]: 37
993 05:55:59.400150 [Byte1]: 37
994 05:55:59.404141
995 05:55:59.404262 Set Vref, RX VrefLevel [Byte0]: 38
996 05:55:59.407430 [Byte1]: 38
997 05:55:59.411800
998 05:55:59.411979 Set Vref, RX VrefLevel [Byte0]: 39
999 05:55:59.415017 [Byte1]: 39
1000 05:55:59.419001
1001 05:55:59.419125 Set Vref, RX VrefLevel [Byte0]: 40
1002 05:55:59.422533 [Byte1]: 40
1003 05:55:59.426753
1004 05:55:59.426915 Set Vref, RX VrefLevel [Byte0]: 41
1005 05:55:59.430461 [Byte1]: 41
1006 05:55:59.434585
1007 05:55:59.434762 Set Vref, RX VrefLevel [Byte0]: 42
1008 05:55:59.437563 [Byte1]: 42
1009 05:55:59.441957
1010 05:55:59.442203 Set Vref, RX VrefLevel [Byte0]: 43
1011 05:55:59.445455 [Byte1]: 43
1012 05:55:59.449576
1013 05:55:59.450014 Set Vref, RX VrefLevel [Byte0]: 44
1014 05:55:59.452951 [Byte1]: 44
1015 05:55:59.456886
1016 05:55:59.457187 Set Vref, RX VrefLevel [Byte0]: 45
1017 05:55:59.461040 [Byte1]: 45
1018 05:55:59.464662
1019 05:55:59.464983 Set Vref, RX VrefLevel [Byte0]: 46
1020 05:55:59.468059 [Byte1]: 46
1021 05:55:59.472130
1022 05:55:59.472636 Set Vref, RX VrefLevel [Byte0]: 47
1023 05:55:59.475849 [Byte1]: 47
1024 05:55:59.480237
1025 05:55:59.480884 Set Vref, RX VrefLevel [Byte0]: 48
1026 05:55:59.483590 [Byte1]: 48
1027 05:55:59.487942
1028 05:55:59.488589 Set Vref, RX VrefLevel [Byte0]: 49
1029 05:55:59.490755 [Byte1]: 49
1030 05:55:59.494957
1031 05:55:59.495361 Set Vref, RX VrefLevel [Byte0]: 50
1032 05:55:59.498604 [Byte1]: 50
1033 05:55:59.502497
1034 05:55:59.502776 Set Vref, RX VrefLevel [Byte0]: 51
1035 05:55:59.505901 [Byte1]: 51
1036 05:55:59.510016
1037 05:55:59.513553 Set Vref, RX VrefLevel [Byte0]: 52
1038 05:55:59.513815 [Byte1]: 52
1039 05:55:59.517973
1040 05:55:59.518279 Set Vref, RX VrefLevel [Byte0]: 53
1041 05:55:59.521406 [Byte1]: 53
1042 05:55:59.525451
1043 05:55:59.525593 Set Vref, RX VrefLevel [Byte0]: 54
1044 05:55:59.528707 [Byte1]: 54
1045 05:55:59.533155
1046 05:55:59.533267 Set Vref, RX VrefLevel [Byte0]: 55
1047 05:55:59.536409 [Byte1]: 55
1048 05:55:59.540716
1049 05:55:59.540850 Set Vref, RX VrefLevel [Byte0]: 56
1050 05:55:59.543744 [Byte1]: 56
1051 05:55:59.548185
1052 05:55:59.548277 Set Vref, RX VrefLevel [Byte0]: 57
1053 05:55:59.551800 [Byte1]: 57
1054 05:55:59.556337
1055 05:55:59.556527 Set Vref, RX VrefLevel [Byte0]: 58
1056 05:55:59.558968 [Byte1]: 58
1057 05:55:59.563645
1058 05:55:59.563840 Set Vref, RX VrefLevel [Byte0]: 59
1059 05:55:59.567039 [Byte1]: 59
1060 05:55:59.571107
1061 05:55:59.571271 Set Vref, RX VrefLevel [Byte0]: 60
1062 05:55:59.574573 [Byte1]: 60
1063 05:55:59.578906
1064 05:55:59.579123 Set Vref, RX VrefLevel [Byte0]: 61
1065 05:55:59.581996 [Byte1]: 61
1066 05:55:59.586389
1067 05:55:59.586558 Set Vref, RX VrefLevel [Byte0]: 62
1068 05:55:59.589787 [Byte1]: 62
1069 05:55:59.593881
1070 05:55:59.594077 Set Vref, RX VrefLevel [Byte0]: 63
1071 05:55:59.597331 [Byte1]: 63
1072 05:55:59.601588
1073 05:55:59.601749 Set Vref, RX VrefLevel [Byte0]: 64
1074 05:55:59.604489 [Byte1]: 64
1075 05:55:59.608887
1076 05:55:59.609053 Set Vref, RX VrefLevel [Byte0]: 65
1077 05:55:59.612269 [Byte1]: 65
1078 05:55:59.616849
1079 05:55:59.616989 Set Vref, RX VrefLevel [Byte0]: 66
1080 05:55:59.619652 [Byte1]: 66
1081 05:55:59.623904
1082 05:55:59.624038 Set Vref, RX VrefLevel [Byte0]: 67
1083 05:55:59.627540 [Byte1]: 67
1084 05:55:59.631720
1085 05:55:59.631888 Set Vref, RX VrefLevel [Byte0]: 68
1086 05:55:59.635364 [Byte1]: 68
1087 05:55:59.639561
1088 05:55:59.639761 Set Vref, RX VrefLevel [Byte0]: 69
1089 05:55:59.642976 [Byte1]: 69
1090 05:55:59.647062
1091 05:55:59.647206 Set Vref, RX VrefLevel [Byte0]: 70
1092 05:55:59.650300 [Byte1]: 70
1093 05:55:59.654778
1094 05:55:59.654923 Set Vref, RX VrefLevel [Byte0]: 71
1095 05:55:59.658042 [Byte1]: 71
1096 05:55:59.662432
1097 05:55:59.662572 Set Vref, RX VrefLevel [Byte0]: 72
1098 05:55:59.665951 [Byte1]: 72
1099 05:55:59.670120
1100 05:55:59.670215 Set Vref, RX VrefLevel [Byte0]: 73
1101 05:55:59.673480 [Byte1]: 73
1102 05:55:59.677424
1103 05:55:59.677641 Set Vref, RX VrefLevel [Byte0]: 74
1104 05:55:59.680718 [Byte1]: 74
1105 05:55:59.684737
1106 05:55:59.684827 Set Vref, RX VrefLevel [Byte0]: 75
1107 05:55:59.688107 [Byte1]: 75
1108 05:55:59.692798
1109 05:55:59.692895 Set Vref, RX VrefLevel [Byte0]: 76
1110 05:55:59.695588 [Byte1]: 76
1111 05:55:59.699931
1112 05:55:59.700045 Set Vref, RX VrefLevel [Byte0]: 77
1113 05:55:59.703515 [Byte1]: 77
1114 05:55:59.707882
1115 05:55:59.708060 Set Vref, RX VrefLevel [Byte0]: 78
1116 05:55:59.711559 [Byte1]: 78
1117 05:55:59.715467
1118 05:55:59.715624 Final RX Vref Byte 0 = 60 to rank0
1119 05:55:59.718989 Final RX Vref Byte 1 = 61 to rank0
1120 05:55:59.721792 Final RX Vref Byte 0 = 60 to rank1
1121 05:55:59.725077 Final RX Vref Byte 1 = 61 to rank1==
1122 05:55:59.728396 Dram Type= 6, Freq= 0, CH_0, rank 0
1123 05:55:59.735594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1124 05:55:59.735713 ==
1125 05:55:59.735785 DQS Delay:
1126 05:55:59.735847 DQS0 = 0, DQS1 = 0
1127 05:55:59.738468 DQM Delay:
1128 05:55:59.738551 DQM0 = 92, DQM1 = 85
1129 05:55:59.742067 DQ Delay:
1130 05:55:59.745648 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1131 05:55:59.748522 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1132 05:55:59.752189 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1133 05:55:59.755628 DQ12 =92, DQ13 =88, DQ14 =96, DQ15 =92
1134 05:55:59.755783
1135 05:55:59.755881
1136 05:55:59.762018 [DQSOSCAuto] RK0, (LSB)MR18= 0x483f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1137 05:55:59.765415 CH0 RK0: MR19=606, MR18=483F
1138 05:55:59.772073 CH0_RK0: MR19=0x606, MR18=0x483F, DQSOSC=391, MR23=63, INC=96, DEC=64
1139 05:55:59.772232
1140 05:55:59.775047 ----->DramcWriteLeveling(PI) begin...
1141 05:55:59.775184 ==
1142 05:55:59.778358 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 05:55:59.781848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 05:55:59.781968 ==
1145 05:55:59.785438 Write leveling (Byte 0): 33 => 33
1146 05:55:59.788761 Write leveling (Byte 1): 32 => 32
1147 05:55:59.792008 DramcWriteLeveling(PI) end<-----
1148 05:55:59.792154
1149 05:55:59.792251 ==
1150 05:55:59.795525 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 05:55:59.839548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 05:55:59.839695 ==
1153 05:55:59.839768 [Gating] SW mode calibration
1154 05:55:59.840025 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1155 05:55:59.840093 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1156 05:55:59.840178 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 05:55:59.840271 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1158 05:55:59.840395 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1159 05:55:59.840489 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 05:55:59.840573 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 05:55:59.840668 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 05:55:59.861486 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 05:55:59.861853 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 05:55:59.861940 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 05:55:59.862008 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 05:55:59.862070 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 05:55:59.868568 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 05:55:59.871648 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 05:55:59.875072 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 05:55:59.881579 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 05:55:59.885403 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 05:55:59.888718 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 05:55:59.895336 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1174 05:55:59.898194 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 05:55:59.901594 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 05:55:59.904864 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 05:55:59.912016 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 05:55:59.915492 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 05:55:59.918268 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 05:55:59.925136 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 05:55:59.928684 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 05:55:59.932222 0 9 8 | B1->B0 | 2b2b 2625 | 1 1 | (0 0) (0 0)
1183 05:55:59.938750 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 05:55:59.942296 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 05:55:59.946102 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 05:55:59.952084 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 05:55:59.955726 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 05:55:59.959365 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 05:55:59.966747 0 10 4 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
1190 05:55:59.969587 0 10 8 | B1->B0 | 2525 2525 | 0 1 | (1 0) (1 1)
1191 05:55:59.973047 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 05:55:59.976751 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 05:55:59.980252 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 05:55:59.987404 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 05:55:59.991090 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 05:55:59.993852 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 05:55:59.997875 0 11 4 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
1198 05:56:00.005096 0 11 8 | B1->B0 | 3c3c 4040 | 0 1 | (0 0) (0 0)
1199 05:56:00.008468 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 05:56:00.011659 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 05:56:00.017930 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 05:56:00.021872 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 05:56:00.025230 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 05:56:00.031944 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 05:56:00.034952 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 05:56:00.038298 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1207 05:56:00.041999 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 05:56:00.048810 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 05:56:00.051409 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 05:56:00.054866 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 05:56:00.061357 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 05:56:00.064751 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 05:56:00.068243 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 05:56:00.075274 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 05:56:00.078214 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 05:56:00.081629 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 05:56:00.088650 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 05:56:00.091526 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 05:56:00.095111 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 05:56:00.102244 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 05:56:00.105130 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 05:56:00.108410 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1223 05:56:00.115540 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 05:56:00.115972 Total UI for P1: 0, mck2ui 16
1225 05:56:00.118278 best dqsien dly found for B0: ( 0, 14, 8)
1226 05:56:00.122371 Total UI for P1: 0, mck2ui 16
1227 05:56:00.125500 best dqsien dly found for B1: ( 0, 14, 8)
1228 05:56:00.128895 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1229 05:56:00.135360 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1230 05:56:00.135945
1231 05:56:00.138665 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 05:56:00.141952 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1233 05:56:00.145350 [Gating] SW calibration Done
1234 05:56:00.145833 ==
1235 05:56:00.148748 Dram Type= 6, Freq= 0, CH_0, rank 1
1236 05:56:00.151895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1237 05:56:00.152368 ==
1238 05:56:00.152732 RX Vref Scan: 0
1239 05:56:00.153052
1240 05:56:00.155575 RX Vref 0 -> 0, step: 1
1241 05:56:00.156086
1242 05:56:00.158746 RX Delay -130 -> 252, step: 16
1243 05:56:00.161655 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1244 05:56:00.165053 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1245 05:56:00.171782 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1246 05:56:00.175266 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1247 05:56:00.178755 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1248 05:56:00.181612 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1249 05:56:00.185101 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1250 05:56:00.188695 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1251 05:56:00.195221 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1252 05:56:00.198083 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1253 05:56:00.201743 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1254 05:56:00.205470 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1255 05:56:00.208914 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1256 05:56:00.215209 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1257 05:56:00.218707 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1258 05:56:00.222263 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1259 05:56:00.222377 ==
1260 05:56:00.225075 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 05:56:00.228738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1262 05:56:00.231634 ==
1263 05:56:00.231717 DQS Delay:
1264 05:56:00.231781 DQS0 = 0, DQS1 = 0
1265 05:56:00.235048 DQM Delay:
1266 05:56:00.235130 DQM0 = 91, DQM1 = 82
1267 05:56:00.238495 DQ Delay:
1268 05:56:00.238577 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1269 05:56:00.241859 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1270 05:56:00.245067 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1271 05:56:00.248321 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1272 05:56:00.248418
1273 05:56:00.248483
1274 05:56:00.251602 ==
1275 05:56:00.254977 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 05:56:00.258380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 05:56:00.258462 ==
1278 05:56:00.258526
1279 05:56:00.258586
1280 05:56:00.261868 TX Vref Scan disable
1281 05:56:00.261950 == TX Byte 0 ==
1282 05:56:00.268171 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1283 05:56:00.271651 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1284 05:56:00.271762 == TX Byte 1 ==
1285 05:56:00.278278 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1286 05:56:00.281758 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1287 05:56:00.281844 ==
1288 05:56:00.285243 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 05:56:00.288644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 05:56:00.288726 ==
1291 05:56:00.301778 TX Vref=22, minBit 11, minWin=27, winSum=449
1292 05:56:00.305362 TX Vref=24, minBit 13, minWin=27, winSum=451
1293 05:56:00.308933 TX Vref=26, minBit 1, minWin=28, winSum=455
1294 05:56:00.311820 TX Vref=28, minBit 8, minWin=28, winSum=461
1295 05:56:00.315377 TX Vref=30, minBit 4, minWin=28, winSum=459
1296 05:56:00.321615 TX Vref=32, minBit 0, minWin=28, winSum=456
1297 05:56:00.325533 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 28
1298 05:56:00.325615
1299 05:56:00.328337 Final TX Range 1 Vref 28
1300 05:56:00.328419
1301 05:56:00.328483 ==
1302 05:56:00.331722 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 05:56:00.335342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 05:56:00.335446 ==
1305 05:56:00.338872
1306 05:56:00.338953
1307 05:56:00.339017 TX Vref Scan disable
1308 05:56:00.341877 == TX Byte 0 ==
1309 05:56:00.345483 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1310 05:56:00.348865 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1311 05:56:00.352427 == TX Byte 1 ==
1312 05:56:00.355579 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1313 05:56:00.358678 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1314 05:56:00.362253
1315 05:56:00.362334 [DATLAT]
1316 05:56:00.362399 Freq=800, CH0 RK1
1317 05:56:00.362459
1318 05:56:00.365317 DATLAT Default: 0xa
1319 05:56:00.365397 0, 0xFFFF, sum = 0
1320 05:56:00.369037 1, 0xFFFF, sum = 0
1321 05:56:00.369153 2, 0xFFFF, sum = 0
1322 05:56:00.372428 3, 0xFFFF, sum = 0
1323 05:56:00.372538 4, 0xFFFF, sum = 0
1324 05:56:00.375675 5, 0xFFFF, sum = 0
1325 05:56:00.375757 6, 0xFFFF, sum = 0
1326 05:56:00.378953 7, 0xFFFF, sum = 0
1327 05:56:00.381919 8, 0xFFFF, sum = 0
1328 05:56:00.382036 9, 0x0, sum = 1
1329 05:56:00.382135 10, 0x0, sum = 2
1330 05:56:00.385715 11, 0x0, sum = 3
1331 05:56:00.385818 12, 0x0, sum = 4
1332 05:56:00.388937 best_step = 10
1333 05:56:00.389018
1334 05:56:00.389081 ==
1335 05:56:00.392046 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 05:56:00.395380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 05:56:00.395463 ==
1338 05:56:00.398816 RX Vref Scan: 0
1339 05:56:00.398897
1340 05:56:00.398961 RX Vref 0 -> 0, step: 1
1341 05:56:00.399021
1342 05:56:00.402329 RX Delay -95 -> 252, step: 8
1343 05:56:00.408701 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1344 05:56:00.412362 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1345 05:56:00.415946 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1346 05:56:00.418779 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1347 05:56:00.422343 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1348 05:56:00.428715 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1349 05:56:00.432018 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1350 05:56:00.435500 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1351 05:56:00.438442 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1352 05:56:00.442099 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1353 05:56:00.448335 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1354 05:56:00.451889 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1355 05:56:00.455456 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1356 05:56:00.459042 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1357 05:56:00.461937 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1358 05:56:00.468815 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1359 05:56:00.468897 ==
1360 05:56:00.472115 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 05:56:00.475007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 05:56:00.475125 ==
1363 05:56:00.475193 DQS Delay:
1364 05:56:00.478466 DQS0 = 0, DQS1 = 0
1365 05:56:00.478547 DQM Delay:
1366 05:56:00.481777 DQM0 = 93, DQM1 = 83
1367 05:56:00.481880 DQ Delay:
1368 05:56:00.485454 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1369 05:56:00.488829 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1370 05:56:00.492260 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1371 05:56:00.495523 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1372 05:56:00.495604
1373 05:56:00.495667
1374 05:56:00.505506 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c0e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
1375 05:56:00.505591 CH0 RK1: MR19=606, MR18=3C0E
1376 05:56:00.511689 CH0_RK1: MR19=0x606, MR18=0x3C0E, DQSOSC=394, MR23=63, INC=95, DEC=63
1377 05:56:00.515358 [RxdqsGatingPostProcess] freq 800
1378 05:56:00.521614 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1379 05:56:00.525030 Pre-setting of DQS Precalculation
1380 05:56:00.528499 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1381 05:56:00.528582 ==
1382 05:56:00.531993 Dram Type= 6, Freq= 0, CH_1, rank 0
1383 05:56:00.534878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1384 05:56:00.538292 ==
1385 05:56:00.541922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1386 05:56:00.548427 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1387 05:56:00.557306 [CA 0] Center 36 (6~67) winsize 62
1388 05:56:00.560887 [CA 1] Center 36 (6~67) winsize 62
1389 05:56:00.563645 [CA 2] Center 35 (5~65) winsize 61
1390 05:56:00.567208 [CA 3] Center 34 (4~65) winsize 62
1391 05:56:00.570941 [CA 4] Center 34 (4~65) winsize 62
1392 05:56:00.573636 [CA 5] Center 34 (4~65) winsize 62
1393 05:56:00.573719
1394 05:56:00.577120 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1395 05:56:00.577204
1396 05:56:00.580622 [CATrainingPosCal] consider 1 rank data
1397 05:56:00.584212 u2DelayCellTimex100 = 270/100 ps
1398 05:56:00.587045 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 05:56:00.590509 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1400 05:56:00.593812 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1401 05:56:00.600455 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 05:56:00.604051 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1403 05:56:00.607578 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1404 05:56:00.607661
1405 05:56:00.610344 CA PerBit enable=1, Macro0, CA PI delay=34
1406 05:56:00.610494
1407 05:56:00.614064 [CBTSetCACLKResult] CA Dly = 34
1408 05:56:00.614148 CS Dly: 6 (0~37)
1409 05:56:00.614214 ==
1410 05:56:00.617534 Dram Type= 6, Freq= 0, CH_1, rank 1
1411 05:56:00.624000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 05:56:00.624118 ==
1413 05:56:00.627653 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1414 05:56:00.634838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1415 05:56:00.643965 [CA 0] Center 37 (6~68) winsize 63
1416 05:56:00.647406 [CA 1] Center 37 (6~68) winsize 63
1417 05:56:00.651195 [CA 2] Center 35 (4~66) winsize 63
1418 05:56:00.655164 [CA 3] Center 34 (4~65) winsize 62
1419 05:56:00.658916 [CA 4] Center 35 (5~66) winsize 62
1420 05:56:00.662374 [CA 5] Center 34 (4~65) winsize 62
1421 05:56:00.662451
1422 05:56:00.666088 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1423 05:56:00.666255
1424 05:56:00.668956 [CATrainingPosCal] consider 2 rank data
1425 05:56:00.669116 u2DelayCellTimex100 = 270/100 ps
1426 05:56:00.675873 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 05:56:00.679327 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1428 05:56:00.682925 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1429 05:56:00.685608 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 05:56:00.689245 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1431 05:56:00.692780 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1432 05:56:00.692872
1433 05:56:00.695717 CA PerBit enable=1, Macro0, CA PI delay=34
1434 05:56:00.695797
1435 05:56:00.699261 [CBTSetCACLKResult] CA Dly = 34
1436 05:56:00.702710 CS Dly: 6 (0~38)
1437 05:56:00.702783
1438 05:56:00.706177 ----->DramcWriteLeveling(PI) begin...
1439 05:56:00.706248 ==
1440 05:56:00.709458 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 05:56:00.712669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 05:56:00.712762 ==
1443 05:56:00.716002 Write leveling (Byte 0): 29 => 29
1444 05:56:00.719451 Write leveling (Byte 1): 29 => 29
1445 05:56:00.722228 DramcWriteLeveling(PI) end<-----
1446 05:56:00.722301
1447 05:56:00.722379 ==
1448 05:56:00.725951 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 05:56:00.728850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 05:56:00.728926 ==
1451 05:56:00.732436 [Gating] SW mode calibration
1452 05:56:00.739215 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1453 05:56:00.745568 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1454 05:56:00.748985 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1455 05:56:00.752256 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 05:56:00.758942 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 05:56:00.762330 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 05:56:00.765561 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 05:56:00.772201 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 05:56:00.775807 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 05:56:00.779490 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 05:56:00.785756 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 05:56:00.789284 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 05:56:00.792775 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 05:56:00.795582 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 05:56:00.802669 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 05:56:00.806239 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 05:56:00.809152 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 05:56:00.816226 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 05:56:00.819054 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1471 05:56:00.822371 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1472 05:56:00.828969 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1473 05:56:00.832992 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 05:56:00.835783 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 05:56:00.842908 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 05:56:00.846222 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 05:56:00.849124 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 05:56:00.856151 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 05:56:00.859094 0 9 4 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
1480 05:56:00.862574 0 9 8 | B1->B0 | 3131 3434 | 1 0 | (1 1) (0 0)
1481 05:56:00.869029 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 05:56:00.872624 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 05:56:00.875969 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 05:56:00.882490 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 05:56:00.885776 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 05:56:00.889552 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 05:56:00.892351 0 10 4 | B1->B0 | 3333 2929 | 1 1 | (0 1) (0 1)
1488 05:56:00.899463 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1489 05:56:00.902346 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 05:56:00.905870 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 05:56:00.912268 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 05:56:00.915868 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 05:56:00.919643 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 05:56:00.926007 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 05:56:00.929844 0 11 4 | B1->B0 | 2828 3535 | 0 0 | (1 1) (0 0)
1496 05:56:00.932725 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1497 05:56:00.939065 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 05:56:00.942528 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 05:56:00.945690 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 05:56:00.952949 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 05:56:00.956144 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 05:56:00.959171 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 05:56:00.966079 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1504 05:56:00.969515 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 05:56:00.972484 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 05:56:00.975893 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 05:56:00.982798 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 05:56:00.986288 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 05:56:00.989621 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 05:56:00.995988 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 05:56:00.999541 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 05:56:01.003041 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 05:56:01.009522 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 05:56:01.013021 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 05:56:01.015841 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 05:56:01.022962 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 05:56:01.025884 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 05:56:01.029466 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1519 05:56:01.035898 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1520 05:56:01.039689 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 05:56:01.042541 Total UI for P1: 0, mck2ui 16
1522 05:56:01.046078 best dqsien dly found for B0: ( 0, 14, 4)
1523 05:56:01.049583 Total UI for P1: 0, mck2ui 16
1524 05:56:01.053095 best dqsien dly found for B1: ( 0, 14, 2)
1525 05:56:01.055846 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1526 05:56:01.059546 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1527 05:56:01.059628
1528 05:56:01.062932 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1529 05:56:01.066318 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1530 05:56:01.069623 [Gating] SW calibration Done
1531 05:56:01.069704 ==
1532 05:56:01.072612 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 05:56:01.075853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 05:56:01.075936 ==
1535 05:56:01.079264 RX Vref Scan: 0
1536 05:56:01.079345
1537 05:56:01.079410 RX Vref 0 -> 0, step: 1
1538 05:56:01.082379
1539 05:56:01.082461 RX Delay -130 -> 252, step: 16
1540 05:56:01.089621 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1541 05:56:01.092624 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1542 05:56:01.095768 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1543 05:56:01.099013 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1544 05:56:01.102518 iDelay=222, Bit 4, Center 101 (-2 ~ 205) 208
1545 05:56:01.109357 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1546 05:56:01.112890 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1547 05:56:01.116252 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1548 05:56:01.119307 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1549 05:56:01.122437 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1550 05:56:01.129702 iDelay=222, Bit 10, Center 93 (-2 ~ 189) 192
1551 05:56:01.132532 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1552 05:56:01.135954 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1553 05:56:01.139517 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1554 05:56:01.142329 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1555 05:56:01.149406 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1556 05:56:01.149489 ==
1557 05:56:01.152984 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 05:56:01.155885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 05:56:01.155967 ==
1560 05:56:01.156032 DQS Delay:
1561 05:56:01.159386 DQS0 = 0, DQS1 = 0
1562 05:56:01.159467 DQM Delay:
1563 05:56:01.162889 DQM0 = 96, DQM1 = 94
1564 05:56:01.162971 DQ Delay:
1565 05:56:01.166421 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =93
1566 05:56:01.169361 DQ4 =101, DQ5 =109, DQ6 =101, DQ7 =93
1567 05:56:01.172713 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1568 05:56:01.176176 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1569 05:56:01.176258
1570 05:56:01.176384
1571 05:56:01.176474 ==
1572 05:56:01.179636 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 05:56:01.182547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 05:56:01.185929 ==
1575 05:56:01.186011
1576 05:56:01.186076
1577 05:56:01.186135 TX Vref Scan disable
1578 05:56:01.189262 == TX Byte 0 ==
1579 05:56:01.192813 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1580 05:56:01.196297 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1581 05:56:01.199545 == TX Byte 1 ==
1582 05:56:01.203050 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1583 05:56:01.206323 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1584 05:56:01.206405 ==
1585 05:56:01.209539 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 05:56:01.213964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 05:56:01.217062 ==
1588 05:56:01.227908 TX Vref=22, minBit 1, minWin=26, winSum=440
1589 05:56:01.231586 TX Vref=24, minBit 1, minWin=27, winSum=444
1590 05:56:01.234911 TX Vref=26, minBit 1, minWin=27, winSum=444
1591 05:56:01.238226 TX Vref=28, minBit 1, minWin=27, winSum=449
1592 05:56:01.241358 TX Vref=30, minBit 1, minWin=27, winSum=448
1593 05:56:01.245115 TX Vref=32, minBit 0, minWin=27, winSum=446
1594 05:56:01.251762 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 28
1595 05:56:01.251931
1596 05:56:01.255092 Final TX Range 1 Vref 28
1597 05:56:01.255195
1598 05:56:01.255282 ==
1599 05:56:01.258866 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 05:56:01.261492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 05:56:01.261649 ==
1602 05:56:01.261744
1603 05:56:01.261832
1604 05:56:01.265079 TX Vref Scan disable
1605 05:56:01.267698 == TX Byte 0 ==
1606 05:56:01.271819 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1607 05:56:01.275135 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1608 05:56:01.278524 == TX Byte 1 ==
1609 05:56:01.282120 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1610 05:56:01.285000 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1611 05:56:01.285424
1612 05:56:01.288592 [DATLAT]
1613 05:56:01.289015 Freq=800, CH1 RK0
1614 05:56:01.289355
1615 05:56:01.292057 DATLAT Default: 0xa
1616 05:56:01.292521 0, 0xFFFF, sum = 0
1617 05:56:01.294965 1, 0xFFFF, sum = 0
1618 05:56:01.295394 2, 0xFFFF, sum = 0
1619 05:56:01.298403 3, 0xFFFF, sum = 0
1620 05:56:01.298829 4, 0xFFFF, sum = 0
1621 05:56:01.301229 5, 0xFFFF, sum = 0
1622 05:56:01.301312 6, 0xFFFF, sum = 0
1623 05:56:01.305032 7, 0xFFFF, sum = 0
1624 05:56:01.305121 8, 0xFFFF, sum = 0
1625 05:56:01.308347 9, 0x0, sum = 1
1626 05:56:01.308436 10, 0x0, sum = 2
1627 05:56:01.311063 11, 0x0, sum = 3
1628 05:56:01.311145 12, 0x0, sum = 4
1629 05:56:01.314567 best_step = 10
1630 05:56:01.314648
1631 05:56:01.314713 ==
1632 05:56:01.318004 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 05:56:01.321295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 05:56:01.321377 ==
1635 05:56:01.324638 RX Vref Scan: 1
1636 05:56:01.324720
1637 05:56:01.324785 Set Vref Range= 32 -> 127
1638 05:56:01.324845
1639 05:56:01.327858 RX Vref 32 -> 127, step: 1
1640 05:56:01.327940
1641 05:56:01.331079 RX Delay -63 -> 252, step: 8
1642 05:56:01.331160
1643 05:56:01.334658 Set Vref, RX VrefLevel [Byte0]: 32
1644 05:56:01.338355 [Byte1]: 32
1645 05:56:01.338438
1646 05:56:01.341479 Set Vref, RX VrefLevel [Byte0]: 33
1647 05:56:01.344792 [Byte1]: 33
1648 05:56:01.347925
1649 05:56:01.348006 Set Vref, RX VrefLevel [Byte0]: 34
1650 05:56:01.351053 [Byte1]: 34
1651 05:56:01.355771
1652 05:56:01.355852 Set Vref, RX VrefLevel [Byte0]: 35
1653 05:56:01.359106 [Byte1]: 35
1654 05:56:01.363000
1655 05:56:01.363158 Set Vref, RX VrefLevel [Byte0]: 36
1656 05:56:01.366434 [Byte1]: 36
1657 05:56:01.370527
1658 05:56:01.370609 Set Vref, RX VrefLevel [Byte0]: 37
1659 05:56:01.373536 [Byte1]: 37
1660 05:56:01.377790
1661 05:56:01.377872 Set Vref, RX VrefLevel [Byte0]: 38
1662 05:56:01.381239 [Byte1]: 38
1663 05:56:01.385477
1664 05:56:01.385558 Set Vref, RX VrefLevel [Byte0]: 39
1665 05:56:01.388684 [Byte1]: 39
1666 05:56:01.392730
1667 05:56:01.392812 Set Vref, RX VrefLevel [Byte0]: 40
1668 05:56:01.396325 [Byte1]: 40
1669 05:56:01.400478
1670 05:56:01.400559 Set Vref, RX VrefLevel [Byte0]: 41
1671 05:56:01.404017 [Byte1]: 41
1672 05:56:01.408233
1673 05:56:01.408362 Set Vref, RX VrefLevel [Byte0]: 42
1674 05:56:01.411313 [Byte1]: 42
1675 05:56:01.415365
1676 05:56:01.415454 Set Vref, RX VrefLevel [Byte0]: 43
1677 05:56:01.418942 [Byte1]: 43
1678 05:56:01.423297
1679 05:56:01.423378 Set Vref, RX VrefLevel [Byte0]: 44
1680 05:56:01.426118 [Byte1]: 44
1681 05:56:01.430384
1682 05:56:01.430471 Set Vref, RX VrefLevel [Byte0]: 45
1683 05:56:01.434075 [Byte1]: 45
1684 05:56:01.438408
1685 05:56:01.438580 Set Vref, RX VrefLevel [Byte0]: 46
1686 05:56:01.441342 [Byte1]: 46
1687 05:56:01.445671
1688 05:56:01.445850 Set Vref, RX VrefLevel [Byte0]: 47
1689 05:56:01.448816 [Byte1]: 47
1690 05:56:01.452748
1691 05:56:01.452887 Set Vref, RX VrefLevel [Byte0]: 48
1692 05:56:01.456103 [Byte1]: 48
1693 05:56:01.460821
1694 05:56:01.461022 Set Vref, RX VrefLevel [Byte0]: 49
1695 05:56:01.464111 [Byte1]: 49
1696 05:56:01.467877
1697 05:56:01.468051 Set Vref, RX VrefLevel [Byte0]: 50
1698 05:56:01.471408 [Byte1]: 50
1699 05:56:01.475706
1700 05:56:01.475981 Set Vref, RX VrefLevel [Byte0]: 51
1701 05:56:01.478699 [Byte1]: 51
1702 05:56:01.483195
1703 05:56:01.483495 Set Vref, RX VrefLevel [Byte0]: 52
1704 05:56:01.486407 [Byte1]: 52
1705 05:56:01.490427
1706 05:56:01.490508 Set Vref, RX VrefLevel [Byte0]: 53
1707 05:56:01.493969 [Byte1]: 53
1708 05:56:01.497968
1709 05:56:01.498056 Set Vref, RX VrefLevel [Byte0]: 54
1710 05:56:01.501442 [Byte1]: 54
1711 05:56:01.505708
1712 05:56:01.505802 Set Vref, RX VrefLevel [Byte0]: 55
1713 05:56:01.509175 [Byte1]: 55
1714 05:56:01.513265
1715 05:56:01.513376 Set Vref, RX VrefLevel [Byte0]: 56
1716 05:56:01.516200 [Byte1]: 56
1717 05:56:01.520416
1718 05:56:01.520560 Set Vref, RX VrefLevel [Byte0]: 57
1719 05:56:01.523889 [Byte1]: 57
1720 05:56:01.528346
1721 05:56:01.528498 Set Vref, RX VrefLevel [Byte0]: 58
1722 05:56:01.531090 [Byte1]: 58
1723 05:56:01.535406
1724 05:56:01.535578 Set Vref, RX VrefLevel [Byte0]: 59
1725 05:56:01.539079 [Byte1]: 59
1726 05:56:01.542655
1727 05:56:01.546172 Set Vref, RX VrefLevel [Byte0]: 60
1728 05:56:01.546494 [Byte1]: 60
1729 05:56:01.550459
1730 05:56:01.550778 Set Vref, RX VrefLevel [Byte0]: 61
1731 05:56:01.553618 [Byte1]: 61
1732 05:56:01.557782
1733 05:56:01.557869 Set Vref, RX VrefLevel [Byte0]: 62
1734 05:56:01.561473 [Byte1]: 62
1735 05:56:01.565267
1736 05:56:01.565391 Set Vref, RX VrefLevel [Byte0]: 63
1737 05:56:01.568571 [Byte1]: 63
1738 05:56:01.572827
1739 05:56:01.572960 Set Vref, RX VrefLevel [Byte0]: 64
1740 05:56:01.576479 [Byte1]: 64
1741 05:56:01.580720
1742 05:56:01.580855 Set Vref, RX VrefLevel [Byte0]: 65
1743 05:56:01.583706 [Byte1]: 65
1744 05:56:01.587821
1745 05:56:01.587973 Set Vref, RX VrefLevel [Byte0]: 66
1746 05:56:01.591489 [Byte1]: 66
1747 05:56:01.595612
1748 05:56:01.595909 Set Vref, RX VrefLevel [Byte0]: 67
1749 05:56:01.598899 [Byte1]: 67
1750 05:56:01.603045
1751 05:56:01.603375 Set Vref, RX VrefLevel [Byte0]: 68
1752 05:56:01.606211 [Byte1]: 68
1753 05:56:01.610993
1754 05:56:01.611380 Set Vref, RX VrefLevel [Byte0]: 69
1755 05:56:01.613838 [Byte1]: 69
1756 05:56:01.618796
1757 05:56:01.619335 Set Vref, RX VrefLevel [Byte0]: 70
1758 05:56:01.621288 [Byte1]: 70
1759 05:56:01.625512
1760 05:56:01.625930 Set Vref, RX VrefLevel [Byte0]: 71
1761 05:56:01.629358 [Byte1]: 71
1762 05:56:01.633407
1763 05:56:01.633831 Set Vref, RX VrefLevel [Byte0]: 72
1764 05:56:01.636401 [Byte1]: 72
1765 05:56:01.640739
1766 05:56:01.641258 Set Vref, RX VrefLevel [Byte0]: 73
1767 05:56:01.644216 [Byte1]: 73
1768 05:56:01.648411
1769 05:56:01.648845 Set Vref, RX VrefLevel [Byte0]: 74
1770 05:56:01.651329 [Byte1]: 74
1771 05:56:01.655521
1772 05:56:01.655938 Set Vref, RX VrefLevel [Byte0]: 75
1773 05:56:01.659046 [Byte1]: 75
1774 05:56:01.663206
1775 05:56:01.663625 Set Vref, RX VrefLevel [Byte0]: 76
1776 05:56:01.666914 [Byte1]: 76
1777 05:56:01.671046
1778 05:56:01.671466 Final RX Vref Byte 0 = 64 to rank0
1779 05:56:01.673756 Final RX Vref Byte 1 = 55 to rank0
1780 05:56:01.677324 Final RX Vref Byte 0 = 64 to rank1
1781 05:56:01.680424 Final RX Vref Byte 1 = 55 to rank1==
1782 05:56:01.684207 Dram Type= 6, Freq= 0, CH_1, rank 0
1783 05:56:01.690598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1784 05:56:01.691024 ==
1785 05:56:01.691424 DQS Delay:
1786 05:56:01.691951 DQS0 = 0, DQS1 = 0
1787 05:56:01.694263 DQM Delay:
1788 05:56:01.694682 DQM0 = 95, DQM1 = 90
1789 05:56:01.697200 DQ Delay:
1790 05:56:01.700767 DQ0 =104, DQ1 =88, DQ2 =80, DQ3 =88
1791 05:56:01.704395 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =96
1792 05:56:01.707752 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1793 05:56:01.710517 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1794 05:56:01.710955
1795 05:56:01.711463
1796 05:56:01.717544 [DQSOSCAuto] RK0, (LSB)MR18= 0x2945, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1797 05:56:01.720536 CH1 RK0: MR19=606, MR18=2945
1798 05:56:01.727241 CH1_RK0: MR19=0x606, MR18=0x2945, DQSOSC=392, MR23=63, INC=96, DEC=64
1799 05:56:01.727894
1800 05:56:01.730761 ----->DramcWriteLeveling(PI) begin...
1801 05:56:01.731337 ==
1802 05:56:01.734061 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 05:56:01.737436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 05:56:01.738105 ==
1805 05:56:01.740440 Write leveling (Byte 0): 27 => 27
1806 05:56:01.744194 Write leveling (Byte 1): 29 => 29
1807 05:56:01.747469 DramcWriteLeveling(PI) end<-----
1808 05:56:01.747925
1809 05:56:01.748331 ==
1810 05:56:01.750647 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 05:56:01.754311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 05:56:01.754732 ==
1813 05:56:01.757070 [Gating] SW mode calibration
1814 05:56:01.764271 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1815 05:56:01.770593 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1816 05:56:01.774161 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1817 05:56:01.780740 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1818 05:56:01.783663 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 05:56:01.787067 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 05:56:01.790299 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 05:56:01.797248 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 05:56:01.800087 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 05:56:01.803404 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 05:56:01.810433 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 05:56:01.813803 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 05:56:01.817056 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 05:56:01.823528 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 05:56:01.826996 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 05:56:01.830654 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 05:56:01.837200 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 05:56:01.840718 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 05:56:01.843911 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1833 05:56:01.850254 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1834 05:56:01.853519 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1835 05:56:01.856953 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 05:56:01.863794 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 05:56:01.866924 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 05:56:01.869979 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 05:56:01.876892 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 05:56:01.880577 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 05:56:01.883375 0 9 4 | B1->B0 | 2828 2424 | 1 1 | (1 1) (0 0)
1842 05:56:01.886901 0 9 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1843 05:56:01.893287 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 05:56:01.896838 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 05:56:01.900385 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 05:56:01.907372 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 05:56:01.910738 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 05:56:01.914096 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
1849 05:56:01.920225 0 10 4 | B1->B0 | 2929 2e2e | 0 0 | (0 0) (0 0)
1850 05:56:01.923634 0 10 8 | B1->B0 | 2323 2323 | 0 1 | (1 0) (1 0)
1851 05:56:01.927071 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 05:56:01.933564 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 05:56:01.937032 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 05:56:01.940624 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 05:56:01.947472 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 05:56:01.950311 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 05:56:01.953780 0 11 4 | B1->B0 | 3a3a 2929 | 0 1 | (0 0) (0 0)
1858 05:56:01.960404 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1859 05:56:01.963613 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 05:56:01.967037 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 05:56:01.973913 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 05:56:01.976687 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 05:56:01.980262 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 05:56:01.983752 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 05:56:01.990319 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 05:56:01.994211 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 05:56:01.997255 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 05:56:02.004034 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 05:56:02.006969 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 05:56:02.010526 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 05:56:02.017556 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 05:56:02.020280 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 05:56:02.023854 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 05:56:02.030586 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 05:56:02.034217 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 05:56:02.037074 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 05:56:02.043586 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 05:56:02.047166 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 05:56:02.050489 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 05:56:02.056745 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 05:56:02.060210 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1882 05:56:02.063712 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1883 05:56:02.067139 Total UI for P1: 0, mck2ui 16
1884 05:56:02.070532 best dqsien dly found for B1: ( 0, 14, 4)
1885 05:56:02.073454 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 05:56:02.077340 Total UI for P1: 0, mck2ui 16
1887 05:56:02.080613 best dqsien dly found for B0: ( 0, 14, 6)
1888 05:56:02.083828 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1889 05:56:02.090385 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1890 05:56:02.090809
1891 05:56:02.093914 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1892 05:56:02.097218 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1893 05:56:02.100491 [Gating] SW calibration Done
1894 05:56:02.101104 ==
1895 05:56:02.103860 Dram Type= 6, Freq= 0, CH_1, rank 1
1896 05:56:02.106960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1897 05:56:02.107347 ==
1898 05:56:02.107785 RX Vref Scan: 0
1899 05:56:02.108221
1900 05:56:02.110204 RX Vref 0 -> 0, step: 1
1901 05:56:02.110537
1902 05:56:02.113209 RX Delay -130 -> 252, step: 16
1903 05:56:02.116927 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1904 05:56:02.120520 iDelay=222, Bit 1, Center 93 (-2 ~ 189) 192
1905 05:56:02.126876 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1906 05:56:02.130383 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1907 05:56:02.133675 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1908 05:56:02.137173 iDelay=222, Bit 5, Center 117 (14 ~ 221) 208
1909 05:56:02.140268 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1910 05:56:02.143839 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1911 05:56:02.150250 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1912 05:56:02.153770 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1913 05:56:02.157151 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1914 05:56:02.160066 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1915 05:56:02.163441 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1916 05:56:02.170501 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1917 05:56:02.173443 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1918 05:56:02.176996 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1919 05:56:02.177099 ==
1920 05:56:02.180572 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 05:56:02.183883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 05:56:02.183976 ==
1923 05:56:02.186746 DQS Delay:
1924 05:56:02.186830 DQS0 = 0, DQS1 = 0
1925 05:56:02.190088 DQM Delay:
1926 05:56:02.190198 DQM0 = 96, DQM1 = 91
1927 05:56:02.190310 DQ Delay:
1928 05:56:02.193442 DQ0 =101, DQ1 =93, DQ2 =77, DQ3 =93
1929 05:56:02.196785 DQ4 =85, DQ5 =117, DQ6 =101, DQ7 =101
1930 05:56:02.200392 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1931 05:56:02.207072 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1932 05:56:02.207159
1933 05:56:02.207224
1934 05:56:02.207284 ==
1935 05:56:02.210381 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 05:56:02.213882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 05:56:02.214000 ==
1938 05:56:02.214068
1939 05:56:02.214163
1940 05:56:02.217402 TX Vref Scan disable
1941 05:56:02.217486 == TX Byte 0 ==
1942 05:56:02.223643 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1943 05:56:02.226865 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1944 05:56:02.226955 == TX Byte 1 ==
1945 05:56:02.233540 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1946 05:56:02.237066 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1947 05:56:02.237149 ==
1948 05:56:02.240646 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 05:56:02.243870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 05:56:02.243952 ==
1951 05:56:02.257363 TX Vref=22, minBit 0, minWin=27, winSum=443
1952 05:56:02.260901 TX Vref=24, minBit 2, minWin=27, winSum=446
1953 05:56:02.264213 TX Vref=26, minBit 2, minWin=27, winSum=448
1954 05:56:02.267533 TX Vref=28, minBit 2, minWin=27, winSum=450
1955 05:56:02.271612 TX Vref=30, minBit 1, minWin=27, winSum=451
1956 05:56:02.274495 TX Vref=32, minBit 1, minWin=27, winSum=448
1957 05:56:02.281528 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 30
1958 05:56:02.281956
1959 05:56:02.284918 Final TX Range 1 Vref 30
1960 05:56:02.285337
1961 05:56:02.285673 ==
1962 05:56:02.287596 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 05:56:02.291037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 05:56:02.291594 ==
1965 05:56:02.292117
1966 05:56:02.292507
1967 05:56:02.294603 TX Vref Scan disable
1968 05:56:02.298244 == TX Byte 0 ==
1969 05:56:02.301101 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1970 05:56:02.304655 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1971 05:56:02.308020 == TX Byte 1 ==
1972 05:56:02.311451 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1973 05:56:02.314630 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1974 05:56:02.315047
1975 05:56:02.317711 [DATLAT]
1976 05:56:02.318127 Freq=800, CH1 RK1
1977 05:56:02.318459
1978 05:56:02.321469 DATLAT Default: 0xa
1979 05:56:02.321883 0, 0xFFFF, sum = 0
1980 05:56:02.324403 1, 0xFFFF, sum = 0
1981 05:56:02.324936 2, 0xFFFF, sum = 0
1982 05:56:02.328432 3, 0xFFFF, sum = 0
1983 05:56:02.328861 4, 0xFFFF, sum = 0
1984 05:56:02.331286 5, 0xFFFF, sum = 0
1985 05:56:02.331709 6, 0xFFFF, sum = 0
1986 05:56:02.334881 7, 0xFFFF, sum = 0
1987 05:56:02.335328 8, 0xFFFF, sum = 0
1988 05:56:02.338317 9, 0x0, sum = 1
1989 05:56:02.338740 10, 0x0, sum = 2
1990 05:56:02.341406 11, 0x0, sum = 3
1991 05:56:02.341920 12, 0x0, sum = 4
1992 05:56:02.344797 best_step = 10
1993 05:56:02.345357
1994 05:56:02.346038 ==
1995 05:56:02.347877 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 05:56:02.351363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 05:56:02.352059 ==
1998 05:56:02.354788 RX Vref Scan: 0
1999 05:56:02.355279
2000 05:56:02.355841 RX Vref 0 -> 0, step: 1
2001 05:56:02.356393
2002 05:56:02.358212 RX Delay -79 -> 252, step: 8
2003 05:56:02.361638 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2004 05:56:02.368371 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2005 05:56:02.371739 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2006 05:56:02.375073 iDelay=209, Bit 3, Center 88 (-7 ~ 184) 192
2007 05:56:02.377754 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2008 05:56:02.381314 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2009 05:56:02.384850 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2010 05:56:02.391251 iDelay=209, Bit 7, Center 92 (-7 ~ 192) 200
2011 05:56:02.394583 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2012 05:56:02.397973 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2013 05:56:02.401579 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2014 05:56:02.404317 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2015 05:56:02.411412 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2016 05:56:02.414959 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2017 05:56:02.417901 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2018 05:56:02.421531 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2019 05:56:02.421949 ==
2020 05:56:02.424345 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 05:56:02.431283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 05:56:02.431702 ==
2023 05:56:02.432077 DQS Delay:
2024 05:56:02.434530 DQS0 = 0, DQS1 = 0
2025 05:56:02.435086 DQM Delay:
2026 05:56:02.435564 DQM0 = 96, DQM1 = 91
2027 05:56:02.438005 DQ Delay:
2028 05:56:02.441231 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =88
2029 05:56:02.444282 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
2030 05:56:02.447866 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2031 05:56:02.451377 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2032 05:56:02.451788
2033 05:56:02.452114
2034 05:56:02.457976 [DQSOSCAuto] RK1, (LSB)MR18= 0x4611, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2035 05:56:02.461435 CH1 RK1: MR19=606, MR18=4611
2036 05:56:02.467482 CH1_RK1: MR19=0x606, MR18=0x4611, DQSOSC=392, MR23=63, INC=96, DEC=64
2037 05:56:02.470901 [RxdqsGatingPostProcess] freq 800
2038 05:56:02.474381 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2039 05:56:02.478063 Pre-setting of DQS Precalculation
2040 05:56:02.484280 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2041 05:56:02.491264 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2042 05:56:02.497487 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2043 05:56:02.498056
2044 05:56:02.498548
2045 05:56:02.500786 [Calibration Summary] 1600 Mbps
2046 05:56:02.501209 CH 0, Rank 0
2047 05:56:02.504181 SW Impedance : PASS
2048 05:56:02.507551 DUTY Scan : NO K
2049 05:56:02.507894 ZQ Calibration : PASS
2050 05:56:02.510904 Jitter Meter : NO K
2051 05:56:02.514526 CBT Training : PASS
2052 05:56:02.514758 Write leveling : PASS
2053 05:56:02.517247 RX DQS gating : PASS
2054 05:56:02.520759 RX DQ/DQS(RDDQC) : PASS
2055 05:56:02.521003 TX DQ/DQS : PASS
2056 05:56:02.524202 RX DATLAT : PASS
2057 05:56:02.528002 RX DQ/DQS(Engine): PASS
2058 05:56:02.528598 TX OE : NO K
2059 05:56:02.530719 All Pass.
2060 05:56:02.531079
2061 05:56:02.531398 CH 0, Rank 1
2062 05:56:02.534263 SW Impedance : PASS
2063 05:56:02.534740 DUTY Scan : NO K
2064 05:56:02.537912 ZQ Calibration : PASS
2065 05:56:02.538286 Jitter Meter : NO K
2066 05:56:02.541301 CBT Training : PASS
2067 05:56:02.544800 Write leveling : PASS
2068 05:56:02.545218 RX DQS gating : PASS
2069 05:56:02.547890 RX DQ/DQS(RDDQC) : PASS
2070 05:56:02.551193 TX DQ/DQS : PASS
2071 05:56:02.551608 RX DATLAT : PASS
2072 05:56:02.554483 RX DQ/DQS(Engine): PASS
2073 05:56:02.557857 TX OE : NO K
2074 05:56:02.558275 All Pass.
2075 05:56:02.558606
2076 05:56:02.558912 CH 1, Rank 0
2077 05:56:02.561410 SW Impedance : PASS
2078 05:56:02.564806 DUTY Scan : NO K
2079 05:56:02.565230 ZQ Calibration : PASS
2080 05:56:02.567986 Jitter Meter : NO K
2081 05:56:02.571161 CBT Training : PASS
2082 05:56:02.571576 Write leveling : PASS
2083 05:56:02.574467 RX DQS gating : PASS
2084 05:56:02.578120 RX DQ/DQS(RDDQC) : PASS
2085 05:56:02.578536 TX DQ/DQS : PASS
2086 05:56:02.580867 RX DATLAT : PASS
2087 05:56:02.581372 RX DQ/DQS(Engine): PASS
2088 05:56:02.584715 TX OE : NO K
2089 05:56:02.585141 All Pass.
2090 05:56:02.585514
2091 05:56:02.587913 CH 1, Rank 1
2092 05:56:02.588376 SW Impedance : PASS
2093 05:56:02.590953 DUTY Scan : NO K
2094 05:56:02.594136 ZQ Calibration : PASS
2095 05:56:02.594556 Jitter Meter : NO K
2096 05:56:02.597548 CBT Training : PASS
2097 05:56:02.601102 Write leveling : PASS
2098 05:56:02.601606 RX DQS gating : PASS
2099 05:56:02.604543 RX DQ/DQS(RDDQC) : PASS
2100 05:56:02.607934 TX DQ/DQS : PASS
2101 05:56:02.608549 RX DATLAT : PASS
2102 05:56:02.611368 RX DQ/DQS(Engine): PASS
2103 05:56:02.614057 TX OE : NO K
2104 05:56:02.614713 All Pass.
2105 05:56:02.615148
2106 05:56:02.615526 DramC Write-DBI off
2107 05:56:02.617361 PER_BANK_REFRESH: Hybrid Mode
2108 05:56:02.621054 TX_TRACKING: ON
2109 05:56:02.624652 [GetDramInforAfterCalByMRR] Vendor 6.
2110 05:56:02.628042 [GetDramInforAfterCalByMRR] Revision 606.
2111 05:56:02.630988 [GetDramInforAfterCalByMRR] Revision 2 0.
2112 05:56:02.631419 MR0 0x3b3b
2113 05:56:02.634492 MR8 0x5151
2114 05:56:02.637885 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 05:56:02.638189
2116 05:56:02.638430 MR0 0x3b3b
2117 05:56:02.638655 MR8 0x5151
2118 05:56:02.640719 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 05:56:02.644157
2120 05:56:02.651062 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2121 05:56:02.654507 [FAST_K] Save calibration result to emmc
2122 05:56:02.657987 [FAST_K] Save calibration result to emmc
2123 05:56:02.661414 dram_init: config_dvfs: 1
2124 05:56:02.664099 dramc_set_vcore_voltage set vcore to 662500
2125 05:56:02.667897 Read voltage for 1200, 2
2126 05:56:02.668064 Vio18 = 0
2127 05:56:02.670888 Vcore = 662500
2128 05:56:02.671041 Vdram = 0
2129 05:56:02.671163 Vddq = 0
2130 05:56:02.671277 Vmddr = 0
2131 05:56:02.677849 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2132 05:56:02.681101 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2133 05:56:02.684177 MEM_TYPE=3, freq_sel=15
2134 05:56:02.687878 sv_algorithm_assistance_LP4_1600
2135 05:56:02.691113 ============ PULL DRAM RESETB DOWN ============
2136 05:56:02.697983 ========== PULL DRAM RESETB DOWN end =========
2137 05:56:02.701188 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2138 05:56:02.704862 ===================================
2139 05:56:02.707654 LPDDR4 DRAM CONFIGURATION
2140 05:56:02.710857 ===================================
2141 05:56:02.711294 EX_ROW_EN[0] = 0x0
2142 05:56:02.714829 EX_ROW_EN[1] = 0x0
2143 05:56:02.715249 LP4Y_EN = 0x0
2144 05:56:02.718017 WORK_FSP = 0x0
2145 05:56:02.718436 WL = 0x4
2146 05:56:02.721213 RL = 0x4
2147 05:56:02.721632 BL = 0x2
2148 05:56:02.724343 RPST = 0x0
2149 05:56:02.724891 RD_PRE = 0x0
2150 05:56:02.728208 WR_PRE = 0x1
2151 05:56:02.728803 WR_PST = 0x0
2152 05:56:02.731535 DBI_WR = 0x0
2153 05:56:02.731971 DBI_RD = 0x0
2154 05:56:02.734933 OTF = 0x1
2155 05:56:02.737982 ===================================
2156 05:56:02.741465 ===================================
2157 05:56:02.741943 ANA top config
2158 05:56:02.744963 ===================================
2159 05:56:02.747770 DLL_ASYNC_EN = 0
2160 05:56:02.751337 ALL_SLAVE_EN = 0
2161 05:56:02.754874 NEW_RANK_MODE = 1
2162 05:56:02.755317 DLL_IDLE_MODE = 1
2163 05:56:02.758014 LP45_APHY_COMB_EN = 1
2164 05:56:02.761427 TX_ODT_DIS = 1
2165 05:56:02.764457 NEW_8X_MODE = 1
2166 05:56:02.767985 ===================================
2167 05:56:02.771730 ===================================
2168 05:56:02.774339 data_rate = 2400
2169 05:56:02.774653 CKR = 1
2170 05:56:02.777595 DQ_P2S_RATIO = 8
2171 05:56:02.780936 ===================================
2172 05:56:02.784528 CA_P2S_RATIO = 8
2173 05:56:02.788041 DQ_CA_OPEN = 0
2174 05:56:02.791366 DQ_SEMI_OPEN = 0
2175 05:56:02.794536 CA_SEMI_OPEN = 0
2176 05:56:02.794836 CA_FULL_RATE = 0
2177 05:56:02.797837 DQ_CKDIV4_EN = 0
2178 05:56:02.801221 CA_CKDIV4_EN = 0
2179 05:56:02.804180 CA_PREDIV_EN = 0
2180 05:56:02.807676 PH8_DLY = 17
2181 05:56:02.810897 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2182 05:56:02.811104 DQ_AAMCK_DIV = 4
2183 05:56:02.814239 CA_AAMCK_DIV = 4
2184 05:56:02.817371 CA_ADMCK_DIV = 4
2185 05:56:02.820758 DQ_TRACK_CA_EN = 0
2186 05:56:02.824575 CA_PICK = 1200
2187 05:56:02.827742 CA_MCKIO = 1200
2188 05:56:02.827878 MCKIO_SEMI = 0
2189 05:56:02.831141 PLL_FREQ = 2366
2190 05:56:02.834437 DQ_UI_PI_RATIO = 32
2191 05:56:02.837992 CA_UI_PI_RATIO = 0
2192 05:56:02.841219 ===================================
2193 05:56:02.844574 ===================================
2194 05:56:02.847924 memory_type:LPDDR4
2195 05:56:02.848367 GP_NUM : 10
2196 05:56:02.851356 SRAM_EN : 1
2197 05:56:02.854904 MD32_EN : 0
2198 05:56:02.858585 ===================================
2199 05:56:02.859170 [ANA_INIT] >>>>>>>>>>>>>>
2200 05:56:02.861266 <<<<<< [CONFIGURE PHASE]: ANA_TX
2201 05:56:02.864518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2202 05:56:02.868055 ===================================
2203 05:56:02.871568 data_rate = 2400,PCW = 0X5b00
2204 05:56:02.874484 ===================================
2205 05:56:02.877965 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2206 05:56:02.884618 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 05:56:02.887748 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 05:56:02.894642 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2209 05:56:02.898310 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2210 05:56:02.900884 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2211 05:56:02.901189 [ANA_INIT] flow start
2212 05:56:02.904434 [ANA_INIT] PLL >>>>>>>>
2213 05:56:02.907517 [ANA_INIT] PLL <<<<<<<<
2214 05:56:02.907882 [ANA_INIT] MIDPI >>>>>>>>
2215 05:56:02.911323 [ANA_INIT] MIDPI <<<<<<<<
2216 05:56:02.915182 [ANA_INIT] DLL >>>>>>>>
2217 05:56:02.915579 [ANA_INIT] DLL <<<<<<<<
2218 05:56:02.917709 [ANA_INIT] flow end
2219 05:56:02.921207 ============ LP4 DIFF to SE enter ============
2220 05:56:02.928089 ============ LP4 DIFF to SE exit ============
2221 05:56:02.928415 [ANA_INIT] <<<<<<<<<<<<<
2222 05:56:02.931566 [Flow] Enable top DCM control >>>>>
2223 05:56:02.935025 [Flow] Enable top DCM control <<<<<
2224 05:56:02.938334 Enable DLL master slave shuffle
2225 05:56:02.944849 ==============================================================
2226 05:56:02.945277 Gating Mode config
2227 05:56:02.951885 ==============================================================
2228 05:56:02.952354 Config description:
2229 05:56:02.961993 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2230 05:56:02.968233 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2231 05:56:02.975196 SELPH_MODE 0: By rank 1: By Phase
2232 05:56:02.978732 ==============================================================
2233 05:56:02.981528 GAT_TRACK_EN = 1
2234 05:56:02.985105 RX_GATING_MODE = 2
2235 05:56:02.988674 RX_GATING_TRACK_MODE = 2
2236 05:56:02.991306 SELPH_MODE = 1
2237 05:56:02.994756 PICG_EARLY_EN = 1
2238 05:56:02.997954 VALID_LAT_VALUE = 1
2239 05:56:03.004605 ==============================================================
2240 05:56:03.008263 Enter into Gating configuration >>>>
2241 05:56:03.011701 Exit from Gating configuration <<<<
2242 05:56:03.012131 Enter into DVFS_PRE_config >>>>>
2243 05:56:03.024926 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2244 05:56:03.028227 Exit from DVFS_PRE_config <<<<<
2245 05:56:03.031629 Enter into PICG configuration >>>>
2246 05:56:03.035177 Exit from PICG configuration <<<<
2247 05:56:03.035598 [RX_INPUT] configuration >>>>>
2248 05:56:03.037939 [RX_INPUT] configuration <<<<<
2249 05:56:03.044867 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2250 05:56:03.048281 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2251 05:56:03.054548 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 05:56:03.061245 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 05:56:03.068221 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 05:56:03.074547 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 05:56:03.078069 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2256 05:56:03.081588 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2257 05:56:03.085107 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2258 05:56:03.091566 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2259 05:56:03.095041 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2260 05:56:03.098699 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 05:56:03.101617 ===================================
2262 05:56:03.105085 LPDDR4 DRAM CONFIGURATION
2263 05:56:03.108558 ===================================
2264 05:56:03.108786 EX_ROW_EN[0] = 0x0
2265 05:56:03.111636 EX_ROW_EN[1] = 0x0
2266 05:56:03.115054 LP4Y_EN = 0x0
2267 05:56:03.115238 WORK_FSP = 0x0
2268 05:56:03.118735 WL = 0x4
2269 05:56:03.118972 RL = 0x4
2270 05:56:03.121539 BL = 0x2
2271 05:56:03.121717 RPST = 0x0
2272 05:56:03.125164 RD_PRE = 0x0
2273 05:56:03.125361 WR_PRE = 0x1
2274 05:56:03.127969 WR_PST = 0x0
2275 05:56:03.128166 DBI_WR = 0x0
2276 05:56:03.131344 DBI_RD = 0x0
2277 05:56:03.131576 OTF = 0x1
2278 05:56:03.134901 ===================================
2279 05:56:03.138501 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2280 05:56:03.144759 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2281 05:56:03.148610 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2282 05:56:03.151609 ===================================
2283 05:56:03.155217 LPDDR4 DRAM CONFIGURATION
2284 05:56:03.158125 ===================================
2285 05:56:03.158485 EX_ROW_EN[0] = 0x10
2286 05:56:03.162057 EX_ROW_EN[1] = 0x0
2287 05:56:03.164908 LP4Y_EN = 0x0
2288 05:56:03.165264 WORK_FSP = 0x0
2289 05:56:03.168344 WL = 0x4
2290 05:56:03.168704 RL = 0x4
2291 05:56:03.171445 BL = 0x2
2292 05:56:03.171703 RPST = 0x0
2293 05:56:03.174707 RD_PRE = 0x0
2294 05:56:03.174961 WR_PRE = 0x1
2295 05:56:03.178069 WR_PST = 0x0
2296 05:56:03.178323 DBI_WR = 0x0
2297 05:56:03.182242 DBI_RD = 0x0
2298 05:56:03.182531 OTF = 0x1
2299 05:56:03.185092 ===================================
2300 05:56:03.191515 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2301 05:56:03.191839 ==
2302 05:56:03.195123 Dram Type= 6, Freq= 0, CH_0, rank 0
2303 05:56:03.197993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2304 05:56:03.198254 ==
2305 05:56:03.201549 [Duty_Offset_Calibration]
2306 05:56:03.205191 B0:2 B1:1 CA:1
2307 05:56:03.205604
2308 05:56:03.207968 [DutyScan_Calibration_Flow] k_type=0
2309 05:56:03.216454
2310 05:56:03.216907 ==CLK 0==
2311 05:56:03.220149 Final CLK duty delay cell = 0
2312 05:56:03.223130 [0] MAX Duty = 5187%(X100), DQS PI = 24
2313 05:56:03.226505 [0] MIN Duty = 4875%(X100), DQS PI = 0
2314 05:56:03.226922 [0] AVG Duty = 5031%(X100)
2315 05:56:03.227256
2316 05:56:03.230311 CH0 CLK Duty spec in!! Max-Min= 312%
2317 05:56:03.236576 [DutyScan_Calibration_Flow] ====Done====
2318 05:56:03.236996
2319 05:56:03.240022 [DutyScan_Calibration_Flow] k_type=1
2320 05:56:03.254098
2321 05:56:03.254514 ==DQS 0 ==
2322 05:56:03.257793 Final DQS duty delay cell = -4
2323 05:56:03.261064 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2324 05:56:03.263982 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2325 05:56:03.267385 [-4] AVG Duty = 4953%(X100)
2326 05:56:03.267802
2327 05:56:03.268135 ==DQS 1 ==
2328 05:56:03.271078 Final DQS duty delay cell = -4
2329 05:56:03.274343 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2330 05:56:03.277465 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2331 05:56:03.280689 [-4] AVG Duty = 4906%(X100)
2332 05:56:03.281111
2333 05:56:03.284274 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2334 05:56:03.284875
2335 05:56:03.287634 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2336 05:56:03.290914 [DutyScan_Calibration_Flow] ====Done====
2337 05:56:03.291332
2338 05:56:03.293885 [DutyScan_Calibration_Flow] k_type=3
2339 05:56:03.311447
2340 05:56:03.311688 ==DQM 0 ==
2341 05:56:03.314277 Final DQM duty delay cell = 0
2342 05:56:03.317860 [0] MAX Duty = 5125%(X100), DQS PI = 24
2343 05:56:03.321262 [0] MIN Duty = 4875%(X100), DQS PI = 58
2344 05:56:03.321503 [0] AVG Duty = 5000%(X100)
2345 05:56:03.324649
2346 05:56:03.324870 ==DQM 1 ==
2347 05:56:03.327527 Final DQM duty delay cell = 0
2348 05:56:03.331469 [0] MAX Duty = 5093%(X100), DQS PI = 0
2349 05:56:03.334774 [0] MIN Duty = 5000%(X100), DQS PI = 18
2350 05:56:03.334995 [0] AVG Duty = 5046%(X100)
2351 05:56:03.338127
2352 05:56:03.341272 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2353 05:56:03.341638
2354 05:56:03.344817 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2355 05:56:03.348387 [DutyScan_Calibration_Flow] ====Done====
2356 05:56:03.348764
2357 05:56:03.351145 [DutyScan_Calibration_Flow] k_type=2
2358 05:56:03.367990
2359 05:56:03.368562 ==DQ 0 ==
2360 05:56:03.371144 Final DQ duty delay cell = 0
2361 05:56:03.374521 [0] MAX Duty = 5062%(X100), DQS PI = 32
2362 05:56:03.378071 [0] MIN Duty = 4875%(X100), DQS PI = 62
2363 05:56:03.378600 [0] AVG Duty = 4968%(X100)
2364 05:56:03.378942
2365 05:56:03.381221 ==DQ 1 ==
2366 05:56:03.384475 Final DQ duty delay cell = 0
2367 05:56:03.387689 [0] MAX Duty = 5093%(X100), DQS PI = 24
2368 05:56:03.391317 [0] MIN Duty = 4938%(X100), DQS PI = 36
2369 05:56:03.391744 [0] AVG Duty = 5015%(X100)
2370 05:56:03.392097
2371 05:56:03.394571 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2372 05:56:03.394998
2373 05:56:03.397739 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2374 05:56:03.404423 [DutyScan_Calibration_Flow] ====Done====
2375 05:56:03.404854 ==
2376 05:56:03.407905 Dram Type= 6, Freq= 0, CH_1, rank 0
2377 05:56:03.410786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2378 05:56:03.411248 ==
2379 05:56:03.414187 [Duty_Offset_Calibration]
2380 05:56:03.414659 B0:1 B1:0 CA:0
2381 05:56:03.415023
2382 05:56:03.417894 [DutyScan_Calibration_Flow] k_type=0
2383 05:56:03.426833
2384 05:56:03.427257 ==CLK 0==
2385 05:56:03.430294 Final CLK duty delay cell = -4
2386 05:56:03.433879 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2387 05:56:03.436654 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2388 05:56:03.439941 [-4] AVG Duty = 4953%(X100)
2389 05:56:03.440246
2390 05:56:03.443764 CH1 CLK Duty spec in!! Max-Min= 156%
2391 05:56:03.447006 [DutyScan_Calibration_Flow] ====Done====
2392 05:56:03.447308
2393 05:56:03.450474 [DutyScan_Calibration_Flow] k_type=1
2394 05:56:03.466304
2395 05:56:03.466608 ==DQS 0 ==
2396 05:56:03.469911 Final DQS duty delay cell = 0
2397 05:56:03.473488 [0] MAX Duty = 5094%(X100), DQS PI = 26
2398 05:56:03.476263 [0] MIN Duty = 4844%(X100), DQS PI = 0
2399 05:56:03.476602 [0] AVG Duty = 4969%(X100)
2400 05:56:03.479856
2401 05:56:03.480153 ==DQS 1 ==
2402 05:56:03.483387 Final DQS duty delay cell = 0
2403 05:56:03.487150 [0] MAX Duty = 5187%(X100), DQS PI = 18
2404 05:56:03.489849 [0] MIN Duty = 4969%(X100), DQS PI = 10
2405 05:56:03.490367 [0] AVG Duty = 5078%(X100)
2406 05:56:03.490809
2407 05:56:03.496839 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2408 05:56:03.497263
2409 05:56:03.500071 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2410 05:56:03.504169 [DutyScan_Calibration_Flow] ====Done====
2411 05:56:03.504647
2412 05:56:03.507068 [DutyScan_Calibration_Flow] k_type=3
2413 05:56:03.523596
2414 05:56:03.524043 ==DQM 0 ==
2415 05:56:03.526935 Final DQM duty delay cell = 0
2416 05:56:03.529674 [0] MAX Duty = 5156%(X100), DQS PI = 6
2417 05:56:03.533168 [0] MIN Duty = 5000%(X100), DQS PI = 62
2418 05:56:03.533592 [0] AVG Duty = 5078%(X100)
2419 05:56:03.536657
2420 05:56:03.537264 ==DQM 1 ==
2421 05:56:03.540102 Final DQM duty delay cell = 0
2422 05:56:03.543574 [0] MAX Duty = 5031%(X100), DQS PI = 16
2423 05:56:03.546334 [0] MIN Duty = 4875%(X100), DQS PI = 36
2424 05:56:03.549848 [0] AVG Duty = 4953%(X100)
2425 05:56:03.550323
2426 05:56:03.553309 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2427 05:56:03.553735
2428 05:56:03.556345 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2429 05:56:03.559905 [DutyScan_Calibration_Flow] ====Done====
2430 05:56:03.560359
2431 05:56:03.563394 [DutyScan_Calibration_Flow] k_type=2
2432 05:56:03.578800
2433 05:56:03.579221 ==DQ 0 ==
2434 05:56:03.582320 Final DQ duty delay cell = -4
2435 05:56:03.585882 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2436 05:56:03.589518 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2437 05:56:03.593137 [-4] AVG Duty = 5000%(X100)
2438 05:56:03.593734
2439 05:56:03.594081 ==DQ 1 ==
2440 05:56:03.595820 Final DQ duty delay cell = 0
2441 05:56:03.599565 [0] MAX Duty = 5093%(X100), DQS PI = 18
2442 05:56:03.602703 [0] MIN Duty = 4969%(X100), DQS PI = 14
2443 05:56:03.603128 [0] AVG Duty = 5031%(X100)
2444 05:56:03.606342
2445 05:56:03.609054 CH1 DQ 0 Duty spec in!! Max-Min= 188%
2446 05:56:03.609481
2447 05:56:03.612080 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2448 05:56:03.615592 [DutyScan_Calibration_Flow] ====Done====
2449 05:56:03.619073 nWR fixed to 30
2450 05:56:03.619496 [ModeRegInit_LP4] CH0 RK0
2451 05:56:03.622570 [ModeRegInit_LP4] CH0 RK1
2452 05:56:03.625992 [ModeRegInit_LP4] CH1 RK0
2453 05:56:03.628877 [ModeRegInit_LP4] CH1 RK1
2454 05:56:03.629300 match AC timing 7
2455 05:56:03.632335 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2456 05:56:03.639329 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2457 05:56:03.642652 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2458 05:56:03.645574 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2459 05:56:03.652834 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2460 05:56:03.653260 ==
2461 05:56:03.655752 Dram Type= 6, Freq= 0, CH_0, rank 0
2462 05:56:03.658988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2463 05:56:03.659413 ==
2464 05:56:03.665932 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2465 05:56:03.672027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2466 05:56:03.679372 [CA 0] Center 39 (8~70) winsize 63
2467 05:56:03.682841 [CA 1] Center 39 (8~70) winsize 63
2468 05:56:03.685817 [CA 2] Center 35 (5~66) winsize 62
2469 05:56:03.689316 [CA 3] Center 34 (4~65) winsize 62
2470 05:56:03.692674 [CA 4] Center 33 (3~64) winsize 62
2471 05:56:03.696230 [CA 5] Center 32 (3~62) winsize 60
2472 05:56:03.696572
2473 05:56:03.699118 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2474 05:56:03.699342
2475 05:56:03.702512 [CATrainingPosCal] consider 1 rank data
2476 05:56:03.705675 u2DelayCellTimex100 = 270/100 ps
2477 05:56:03.709030 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2478 05:56:03.712540 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2479 05:56:03.719702 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2480 05:56:03.722335 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2481 05:56:03.725793 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2482 05:56:03.729224 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2483 05:56:03.729446
2484 05:56:03.732803 CA PerBit enable=1, Macro0, CA PI delay=32
2485 05:56:03.733088
2486 05:56:03.736413 [CBTSetCACLKResult] CA Dly = 32
2487 05:56:03.736670 CS Dly: 6 (0~37)
2488 05:56:03.736877 ==
2489 05:56:03.739367 Dram Type= 6, Freq= 0, CH_0, rank 1
2490 05:56:03.746670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2491 05:56:03.747098 ==
2492 05:56:03.749487 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2493 05:56:03.756357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2494 05:56:03.764953 [CA 0] Center 38 (8~69) winsize 62
2495 05:56:03.768666 [CA 1] Center 38 (8~69) winsize 62
2496 05:56:03.771844 [CA 2] Center 35 (4~66) winsize 63
2497 05:56:03.775068 [CA 3] Center 34 (4~65) winsize 62
2498 05:56:03.778448 [CA 4] Center 33 (3~64) winsize 62
2499 05:56:03.781525 [CA 5] Center 32 (3~62) winsize 60
2500 05:56:03.781975
2501 05:56:03.785437 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2502 05:56:03.785855
2503 05:56:03.788413 [CATrainingPosCal] consider 2 rank data
2504 05:56:03.791597 u2DelayCellTimex100 = 270/100 ps
2505 05:56:03.795355 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2506 05:56:03.798423 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2507 05:56:03.805569 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2508 05:56:03.808465 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2509 05:56:03.811817 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2510 05:56:03.815348 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2511 05:56:03.815791
2512 05:56:03.818904 CA PerBit enable=1, Macro0, CA PI delay=32
2513 05:56:03.819320
2514 05:56:03.821744 [CBTSetCACLKResult] CA Dly = 32
2515 05:56:03.822230 CS Dly: 6 (0~38)
2516 05:56:03.822612
2517 05:56:03.824988 ----->DramcWriteLeveling(PI) begin...
2518 05:56:03.825438 ==
2519 05:56:03.829073 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 05:56:03.835625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 05:56:03.835926 ==
2522 05:56:03.838723 Write leveling (Byte 0): 34 => 34
2523 05:56:03.842087 Write leveling (Byte 1): 30 => 30
2524 05:56:03.842391 DramcWriteLeveling(PI) end<-----
2525 05:56:03.845688
2526 05:56:03.845981 ==
2527 05:56:03.848527 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 05:56:03.852029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 05:56:03.852363 ==
2530 05:56:03.855863 [Gating] SW mode calibration
2531 05:56:03.861814 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2532 05:56:03.865331 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2533 05:56:03.872227 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2534 05:56:03.875562 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2535 05:56:03.878489 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 05:56:03.885117 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 05:56:03.888704 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 05:56:03.891468 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 05:56:03.898202 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2540 05:56:03.901454 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2541 05:56:03.905024 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2542 05:56:03.911982 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 05:56:03.915171 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 05:56:03.918168 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 05:56:03.924992 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 05:56:03.928600 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 05:56:03.931526 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2548 05:56:03.934945 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2549 05:56:03.941542 1 1 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2550 05:56:03.944683 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 05:56:03.948019 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 05:56:03.954505 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 05:56:03.957978 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 05:56:03.961594 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 05:56:03.967993 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 05:56:03.971545 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2557 05:56:03.975086 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2558 05:56:03.981427 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 05:56:03.984974 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 05:56:03.988168 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 05:56:03.994889 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 05:56:03.998104 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 05:56:04.001648 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 05:56:04.008473 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 05:56:04.011739 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 05:56:04.015171 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 05:56:04.021833 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 05:56:04.025242 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 05:56:04.028018 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 05:56:04.035362 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 05:56:04.038482 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 05:56:04.042220 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2573 05:56:04.044993 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2574 05:56:04.048512 Total UI for P1: 0, mck2ui 16
2575 05:56:04.051798 best dqsien dly found for B0: ( 1, 3, 28)
2576 05:56:04.058428 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 05:56:04.061755 Total UI for P1: 0, mck2ui 16
2578 05:56:04.065210 best dqsien dly found for B1: ( 1, 4, 0)
2579 05:56:04.068824 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2580 05:56:04.071440 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2581 05:56:04.072030
2582 05:56:04.074844 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2583 05:56:04.078340 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2584 05:56:04.081804 [Gating] SW calibration Done
2585 05:56:04.082322 ==
2586 05:56:04.085390 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 05:56:04.088333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 05:56:04.088953 ==
2589 05:56:04.091860 RX Vref Scan: 0
2590 05:56:04.092281
2591 05:56:04.092675 RX Vref 0 -> 0, step: 1
2592 05:56:04.092988
2593 05:56:04.095009 RX Delay -40 -> 252, step: 8
2594 05:56:04.098425 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2595 05:56:04.105181 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2596 05:56:04.108275 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2597 05:56:04.111863 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2598 05:56:04.115097 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2599 05:56:04.118445 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2600 05:56:04.125278 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2601 05:56:04.128921 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2602 05:56:04.131687 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2603 05:56:04.135128 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2604 05:56:04.138798 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2605 05:56:04.145013 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2606 05:56:04.148609 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2607 05:56:04.152269 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2608 05:56:04.155231 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2609 05:56:04.158846 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2610 05:56:04.159294 ==
2611 05:56:04.162197 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 05:56:04.168934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 05:56:04.169507 ==
2614 05:56:04.169998 DQS Delay:
2615 05:56:04.172346 DQS0 = 0, DQS1 = 0
2616 05:56:04.172769 DQM Delay:
2617 05:56:04.175789 DQM0 = 121, DQM1 = 113
2618 05:56:04.176205 DQ Delay:
2619 05:56:04.178666 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2620 05:56:04.181932 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2621 05:56:04.185529 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2622 05:56:04.189141 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2623 05:56:04.189733
2624 05:56:04.190126
2625 05:56:04.190464 ==
2626 05:56:04.191846 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 05:56:04.195359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 05:56:04.198711 ==
2629 05:56:04.198973
2630 05:56:04.199155
2631 05:56:04.199334 TX Vref Scan disable
2632 05:56:04.202260 == TX Byte 0 ==
2633 05:56:04.205124 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2634 05:56:04.208583 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2635 05:56:04.211658 == TX Byte 1 ==
2636 05:56:04.215236 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2637 05:56:04.218601 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2638 05:56:04.222100 ==
2639 05:56:04.222379 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 05:56:04.228346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 05:56:04.228633 ==
2642 05:56:04.240114 TX Vref=22, minBit 4, minWin=24, winSum=406
2643 05:56:04.242966 TX Vref=24, minBit 4, minWin=24, winSum=412
2644 05:56:04.246418 TX Vref=26, minBit 2, minWin=25, winSum=418
2645 05:56:04.249926 TX Vref=28, minBit 15, minWin=25, winSum=421
2646 05:56:04.252751 TX Vref=30, minBit 12, minWin=25, winSum=423
2647 05:56:04.259882 TX Vref=32, minBit 1, minWin=26, winSum=425
2648 05:56:04.263291 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 32
2649 05:56:04.263646
2650 05:56:04.266573 Final TX Range 1 Vref 32
2651 05:56:04.266991
2652 05:56:04.267339 ==
2653 05:56:04.270190 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 05:56:04.273610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 05:56:04.274142 ==
2656 05:56:04.274484
2657 05:56:04.276938
2658 05:56:04.277415 TX Vref Scan disable
2659 05:56:04.280134 == TX Byte 0 ==
2660 05:56:04.283510 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2661 05:56:04.286656 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2662 05:56:04.289821 == TX Byte 1 ==
2663 05:56:04.293429 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2664 05:56:04.296889 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2665 05:56:04.297328
2666 05:56:04.300482 [DATLAT]
2667 05:56:04.300953 Freq=1200, CH0 RK0
2668 05:56:04.301326
2669 05:56:04.303196 DATLAT Default: 0xd
2670 05:56:04.303635 0, 0xFFFF, sum = 0
2671 05:56:04.306484 1, 0xFFFF, sum = 0
2672 05:56:04.306566 2, 0xFFFF, sum = 0
2673 05:56:04.309986 3, 0xFFFF, sum = 0
2674 05:56:04.310068 4, 0xFFFF, sum = 0
2675 05:56:04.313371 5, 0xFFFF, sum = 0
2676 05:56:04.313477 6, 0xFFFF, sum = 0
2677 05:56:04.316930 7, 0xFFFF, sum = 0
2678 05:56:04.317012 8, 0xFFFF, sum = 0
2679 05:56:04.319902 9, 0xFFFF, sum = 0
2680 05:56:04.320014 10, 0xFFFF, sum = 0
2681 05:56:04.323138 11, 0xFFFF, sum = 0
2682 05:56:04.323220 12, 0x0, sum = 1
2683 05:56:04.326395 13, 0x0, sum = 2
2684 05:56:04.326481 14, 0x0, sum = 3
2685 05:56:04.330072 15, 0x0, sum = 4
2686 05:56:04.330154 best_step = 13
2687 05:56:04.330218
2688 05:56:04.330278 ==
2689 05:56:04.333559 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 05:56:04.339970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 05:56:04.340078 ==
2692 05:56:04.340191 RX Vref Scan: 1
2693 05:56:04.340296
2694 05:56:04.343362 Set Vref Range= 32 -> 127
2695 05:56:04.343463
2696 05:56:04.346628 RX Vref 32 -> 127, step: 1
2697 05:56:04.346700
2698 05:56:04.346761 RX Delay -13 -> 252, step: 4
2699 05:56:04.350221
2700 05:56:04.350293 Set Vref, RX VrefLevel [Byte0]: 32
2701 05:56:04.353050 [Byte1]: 32
2702 05:56:04.358024
2703 05:56:04.358098 Set Vref, RX VrefLevel [Byte0]: 33
2704 05:56:04.360967 [Byte1]: 33
2705 05:56:04.365871
2706 05:56:04.365952 Set Vref, RX VrefLevel [Byte0]: 34
2707 05:56:04.369400 [Byte1]: 34
2708 05:56:04.373566
2709 05:56:04.373673 Set Vref, RX VrefLevel [Byte0]: 35
2710 05:56:04.377122 [Byte1]: 35
2711 05:56:04.381675
2712 05:56:04.381797 Set Vref, RX VrefLevel [Byte0]: 36
2713 05:56:04.384869 [Byte1]: 36
2714 05:56:04.389259
2715 05:56:04.389340 Set Vref, RX VrefLevel [Byte0]: 37
2716 05:56:04.392930 [Byte1]: 37
2717 05:56:04.397071
2718 05:56:04.397155 Set Vref, RX VrefLevel [Byte0]: 38
2719 05:56:04.400803 [Byte1]: 38
2720 05:56:04.405163
2721 05:56:04.405244 Set Vref, RX VrefLevel [Byte0]: 39
2722 05:56:04.408298 [Byte1]: 39
2723 05:56:04.413271
2724 05:56:04.413378 Set Vref, RX VrefLevel [Byte0]: 40
2725 05:56:04.416138 [Byte1]: 40
2726 05:56:04.421173
2727 05:56:04.421253 Set Vref, RX VrefLevel [Byte0]: 41
2728 05:56:04.424039 [Byte1]: 41
2729 05:56:04.428726
2730 05:56:04.428807 Set Vref, RX VrefLevel [Byte0]: 42
2731 05:56:04.432389 [Byte1]: 42
2732 05:56:04.437196
2733 05:56:04.437277 Set Vref, RX VrefLevel [Byte0]: 43
2734 05:56:04.440483 [Byte1]: 43
2735 05:56:04.444602
2736 05:56:04.444683 Set Vref, RX VrefLevel [Byte0]: 44
2737 05:56:04.448029 [Byte1]: 44
2738 05:56:04.452601
2739 05:56:04.452682 Set Vref, RX VrefLevel [Byte0]: 45
2740 05:56:04.455857 [Byte1]: 45
2741 05:56:04.460422
2742 05:56:04.460503 Set Vref, RX VrefLevel [Byte0]: 46
2743 05:56:04.463816 [Byte1]: 46
2744 05:56:04.468074
2745 05:56:04.468185 Set Vref, RX VrefLevel [Byte0]: 47
2746 05:56:04.471601 [Byte1]: 47
2747 05:56:04.475909
2748 05:56:04.476026 Set Vref, RX VrefLevel [Byte0]: 48
2749 05:56:04.479466 [Byte1]: 48
2750 05:56:04.484342
2751 05:56:04.484464 Set Vref, RX VrefLevel [Byte0]: 49
2752 05:56:04.487215 [Byte1]: 49
2753 05:56:04.492262
2754 05:56:04.492389 Set Vref, RX VrefLevel [Byte0]: 50
2755 05:56:04.495067 [Byte1]: 50
2756 05:56:04.499946
2757 05:56:04.500028 Set Vref, RX VrefLevel [Byte0]: 51
2758 05:56:04.503496 [Byte1]: 51
2759 05:56:04.507467
2760 05:56:04.507549 Set Vref, RX VrefLevel [Byte0]: 52
2761 05:56:04.510742 [Byte1]: 52
2762 05:56:04.515752
2763 05:56:04.515839 Set Vref, RX VrefLevel [Byte0]: 53
2764 05:56:04.518811 [Byte1]: 53
2765 05:56:04.523804
2766 05:56:04.523888 Set Vref, RX VrefLevel [Byte0]: 54
2767 05:56:04.526987 [Byte1]: 54
2768 05:56:04.531215
2769 05:56:04.531296 Set Vref, RX VrefLevel [Byte0]: 55
2770 05:56:04.534639 [Byte1]: 55
2771 05:56:04.539451
2772 05:56:04.539532 Set Vref, RX VrefLevel [Byte0]: 56
2773 05:56:04.542624 [Byte1]: 56
2774 05:56:04.547334
2775 05:56:04.547415 Set Vref, RX VrefLevel [Byte0]: 57
2776 05:56:04.550665 [Byte1]: 57
2777 05:56:04.554796
2778 05:56:04.554877 Set Vref, RX VrefLevel [Byte0]: 58
2779 05:56:04.558150 [Byte1]: 58
2780 05:56:04.562648
2781 05:56:04.562728 Set Vref, RX VrefLevel [Byte0]: 59
2782 05:56:04.566025 [Byte1]: 59
2783 05:56:04.570526
2784 05:56:04.570606 Set Vref, RX VrefLevel [Byte0]: 60
2785 05:56:04.573988 [Byte1]: 60
2786 05:56:04.578972
2787 05:56:04.579053 Set Vref, RX VrefLevel [Byte0]: 61
2788 05:56:04.581793 [Byte1]: 61
2789 05:56:04.586611
2790 05:56:04.586692 Set Vref, RX VrefLevel [Byte0]: 62
2791 05:56:04.590228 [Byte1]: 62
2792 05:56:04.594454
2793 05:56:04.594536 Set Vref, RX VrefLevel [Byte0]: 63
2794 05:56:04.597865 [Byte1]: 63
2795 05:56:04.602743
2796 05:56:04.602825 Set Vref, RX VrefLevel [Byte0]: 64
2797 05:56:04.605605 [Byte1]: 64
2798 05:56:04.610605
2799 05:56:04.610686 Set Vref, RX VrefLevel [Byte0]: 65
2800 05:56:04.613452 [Byte1]: 65
2801 05:56:04.618392
2802 05:56:04.618500 Set Vref, RX VrefLevel [Byte0]: 66
2803 05:56:04.621698 [Byte1]: 66
2804 05:56:04.625939
2805 05:56:04.626024 Set Vref, RX VrefLevel [Byte0]: 67
2806 05:56:04.629796 [Byte1]: 67
2807 05:56:04.633853
2808 05:56:04.633933 Set Vref, RX VrefLevel [Byte0]: 68
2809 05:56:04.637126 [Byte1]: 68
2810 05:56:04.641584
2811 05:56:04.641664 Set Vref, RX VrefLevel [Byte0]: 69
2812 05:56:04.645395 [Byte1]: 69
2813 05:56:04.649846
2814 05:56:04.649926 Set Vref, RX VrefLevel [Byte0]: 70
2815 05:56:04.653001 [Byte1]: 70
2816 05:56:04.657393
2817 05:56:04.657474 Set Vref, RX VrefLevel [Byte0]: 71
2818 05:56:04.660620 [Byte1]: 71
2819 05:56:04.665908
2820 05:56:04.665991 Final RX Vref Byte 0 = 54 to rank0
2821 05:56:04.668555 Final RX Vref Byte 1 = 55 to rank0
2822 05:56:04.672483 Final RX Vref Byte 0 = 54 to rank1
2823 05:56:04.675845 Final RX Vref Byte 1 = 55 to rank1==
2824 05:56:04.679064 Dram Type= 6, Freq= 0, CH_0, rank 0
2825 05:56:04.685389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 05:56:04.685472 ==
2827 05:56:04.685537 DQS Delay:
2828 05:56:04.685598 DQS0 = 0, DQS1 = 0
2829 05:56:04.688917 DQM Delay:
2830 05:56:04.688998 DQM0 = 120, DQM1 = 113
2831 05:56:04.692404 DQ Delay:
2832 05:56:04.695886 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2833 05:56:04.698738 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2834 05:56:04.702166 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
2835 05:56:04.705744 DQ12 =118, DQ13 =118, DQ14 =124, DQ15 =124
2836 05:56:04.705826
2837 05:56:04.705891
2838 05:56:04.712018 [DQSOSCAuto] RK0, (LSB)MR18= 0x120b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2839 05:56:04.715500 CH0 RK0: MR19=404, MR18=120B
2840 05:56:04.722561 CH0_RK0: MR19=0x404, MR18=0x120B, DQSOSC=403, MR23=63, INC=40, DEC=26
2841 05:56:04.722643
2842 05:56:04.726051 ----->DramcWriteLeveling(PI) begin...
2843 05:56:04.726134 ==
2844 05:56:04.729245 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 05:56:04.732114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 05:56:04.735748 ==
2847 05:56:04.735831 Write leveling (Byte 0): 34 => 34
2848 05:56:04.738668 Write leveling (Byte 1): 27 => 27
2849 05:56:04.742093 DramcWriteLeveling(PI) end<-----
2850 05:56:04.742222
2851 05:56:04.742290 ==
2852 05:56:04.745618 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 05:56:04.752266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 05:56:04.752392 ==
2855 05:56:04.752460 [Gating] SW mode calibration
2856 05:56:04.762118 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2857 05:56:04.765359 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2858 05:56:04.769155 0 15 0 | B1->B0 | 2f2f 2e2e | 1 0 | (0 0) (0 0)
2859 05:56:04.775864 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 05:56:04.779094 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 05:56:04.782434 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 05:56:04.789215 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 05:56:04.792193 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 05:56:04.795738 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 05:56:04.802281 0 15 28 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
2866 05:56:04.805710 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2867 05:56:04.809263 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 05:56:04.815631 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 05:56:04.819122 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 05:56:04.822647 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 05:56:04.829117 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 05:56:04.832543 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 05:56:04.835940 1 0 28 | B1->B0 | 3a3a 3e3d | 1 1 | (0 0) (0 0)
2874 05:56:04.842345 1 1 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
2875 05:56:04.846054 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 05:56:04.848937 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 05:56:04.852244 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 05:56:04.859205 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 05:56:04.862427 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 05:56:04.865940 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2881 05:56:04.872742 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2882 05:56:04.876039 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2883 05:56:04.879338 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 05:56:04.885755 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 05:56:04.888991 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 05:56:04.892161 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 05:56:04.899324 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 05:56:04.902496 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 05:56:04.905849 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 05:56:04.912432 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 05:56:04.916049 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 05:56:04.919136 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 05:56:04.925931 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 05:56:04.929458 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 05:56:04.932217 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 05:56:04.939453 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 05:56:04.942885 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2898 05:56:04.945554 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 05:56:04.949131 Total UI for P1: 0, mck2ui 16
2900 05:56:04.952675 best dqsien dly found for B0: ( 1, 3, 28)
2901 05:56:04.956152 Total UI for P1: 0, mck2ui 16
2902 05:56:04.959088 best dqsien dly found for B1: ( 1, 3, 28)
2903 05:56:04.962527 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2904 05:56:04.965975 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2905 05:56:04.966056
2906 05:56:04.969288 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2907 05:56:04.972559 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2908 05:56:04.976055 [Gating] SW calibration Done
2909 05:56:04.976136 ==
2910 05:56:04.978802 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 05:56:04.985661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 05:56:04.985746 ==
2913 05:56:04.985811 RX Vref Scan: 0
2914 05:56:04.985872
2915 05:56:04.989146 RX Vref 0 -> 0, step: 1
2916 05:56:04.989228
2917 05:56:04.992581 RX Delay -40 -> 252, step: 8
2918 05:56:04.995983 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2919 05:56:04.999292 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2920 05:56:05.002575 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2921 05:56:05.006252 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2922 05:56:05.012465 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2923 05:56:05.015950 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2924 05:56:05.019501 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2925 05:56:05.023048 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2926 05:56:05.025747 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2927 05:56:05.029177 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2928 05:56:05.035881 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2929 05:56:05.039125 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2930 05:56:05.042417 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2931 05:56:05.045879 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2932 05:56:05.052737 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2933 05:56:05.056345 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2934 05:56:05.056428 ==
2935 05:56:05.059066 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 05:56:05.062591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 05:56:05.062674 ==
2938 05:56:05.062740 DQS Delay:
2939 05:56:05.066105 DQS0 = 0, DQS1 = 0
2940 05:56:05.066186 DQM Delay:
2941 05:56:05.069774 DQM0 = 122, DQM1 = 113
2942 05:56:05.069855 DQ Delay:
2943 05:56:05.072444 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2944 05:56:05.075843 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2945 05:56:05.079372 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
2946 05:56:05.082802 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2947 05:56:05.082883
2948 05:56:05.086263
2949 05:56:05.086344 ==
2950 05:56:05.089498 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 05:56:05.092970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 05:56:05.093053 ==
2953 05:56:05.093118
2954 05:56:05.093178
2955 05:56:05.096473 TX Vref Scan disable
2956 05:56:05.096555 == TX Byte 0 ==
2957 05:56:05.099318 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2958 05:56:05.106341 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2959 05:56:05.106423 == TX Byte 1 ==
2960 05:56:05.109975 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2961 05:56:05.116228 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2962 05:56:05.116352 ==
2963 05:56:05.119715 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 05:56:05.122412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 05:56:05.122495 ==
2966 05:56:05.135667 TX Vref=22, minBit 1, minWin=25, winSum=413
2967 05:56:05.139035 TX Vref=24, minBit 5, minWin=25, winSum=420
2968 05:56:05.141957 TX Vref=26, minBit 1, minWin=26, winSum=422
2969 05:56:05.145408 TX Vref=28, minBit 1, minWin=26, winSum=428
2970 05:56:05.148670 TX Vref=30, minBit 5, minWin=25, winSum=427
2971 05:56:05.151913 TX Vref=32, minBit 5, minWin=25, winSum=424
2972 05:56:05.158847 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
2973 05:56:05.158931
2974 05:56:05.162546 Final TX Range 1 Vref 28
2975 05:56:05.162651
2976 05:56:05.162741 ==
2977 05:56:05.166039 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 05:56:05.168841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 05:56:05.168923 ==
2980 05:56:05.168989
2981 05:56:05.169050
2982 05:56:05.172302 TX Vref Scan disable
2983 05:56:05.175718 == TX Byte 0 ==
2984 05:56:05.179110 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2985 05:56:05.182464 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2986 05:56:05.185303 == TX Byte 1 ==
2987 05:56:05.188898 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2988 05:56:05.192525 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2989 05:56:05.192617
2990 05:56:05.195846 [DATLAT]
2991 05:56:05.195928 Freq=1200, CH0 RK1
2992 05:56:05.195993
2993 05:56:05.199061 DATLAT Default: 0xd
2994 05:56:05.199143 0, 0xFFFF, sum = 0
2995 05:56:05.202573 1, 0xFFFF, sum = 0
2996 05:56:05.202660 2, 0xFFFF, sum = 0
2997 05:56:05.206057 3, 0xFFFF, sum = 0
2998 05:56:05.206141 4, 0xFFFF, sum = 0
2999 05:56:05.208884 5, 0xFFFF, sum = 0
3000 05:56:05.208967 6, 0xFFFF, sum = 0
3001 05:56:05.212413 7, 0xFFFF, sum = 0
3002 05:56:05.212496 8, 0xFFFF, sum = 0
3003 05:56:05.215657 9, 0xFFFF, sum = 0
3004 05:56:05.215740 10, 0xFFFF, sum = 0
3005 05:56:05.218961 11, 0xFFFF, sum = 0
3006 05:56:05.219045 12, 0x0, sum = 1
3007 05:56:05.222438 13, 0x0, sum = 2
3008 05:56:05.222521 14, 0x0, sum = 3
3009 05:56:05.225877 15, 0x0, sum = 4
3010 05:56:05.225960 best_step = 13
3011 05:56:05.226025
3012 05:56:05.226086 ==
3013 05:56:05.229389 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 05:56:05.235670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 05:56:05.235765 ==
3016 05:56:05.235854 RX Vref Scan: 0
3017 05:56:05.235935
3018 05:56:05.239221 RX Vref 0 -> 0, step: 1
3019 05:56:05.239307
3020 05:56:05.242655 RX Delay -13 -> 252, step: 4
3021 05:56:05.245423 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3022 05:56:05.249052 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3023 05:56:05.256040 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3024 05:56:05.258872 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3025 05:56:05.262447 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3026 05:56:05.265827 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3027 05:56:05.269119 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3028 05:56:05.275808 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3029 05:56:05.278896 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3030 05:56:05.282313 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3031 05:56:05.285845 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3032 05:56:05.289066 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3033 05:56:05.296131 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3034 05:56:05.299716 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3035 05:56:05.302551 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3036 05:56:05.306348 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3037 05:56:05.306432 ==
3038 05:56:05.309493 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 05:56:05.312991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 05:56:05.315837 ==
3041 05:56:05.315919 DQS Delay:
3042 05:56:05.315984 DQS0 = 0, DQS1 = 0
3043 05:56:05.319365 DQM Delay:
3044 05:56:05.319447 DQM0 = 121, DQM1 = 111
3045 05:56:05.322594 DQ Delay:
3046 05:56:05.325989 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3047 05:56:05.329442 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3048 05:56:05.332849 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
3049 05:56:05.336221 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =118
3050 05:56:05.336343
3051 05:56:05.336410
3052 05:56:05.342786 [DQSOSCAuto] RK1, (LSB)MR18= 0xbec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 405 ps
3053 05:56:05.346173 CH0 RK1: MR19=403, MR18=BEC
3054 05:56:05.352841 CH0_RK1: MR19=0x403, MR18=0xBEC, DQSOSC=405, MR23=63, INC=39, DEC=26
3055 05:56:05.356205 [RxdqsGatingPostProcess] freq 1200
3056 05:56:05.362635 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3057 05:56:05.362734 best DQS0 dly(2T, 0.5T) = (0, 11)
3058 05:56:05.366152 best DQS1 dly(2T, 0.5T) = (0, 12)
3059 05:56:05.369651 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3060 05:56:05.372501 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3061 05:56:05.376079 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 05:56:05.379625 best DQS1 dly(2T, 0.5T) = (0, 11)
3063 05:56:05.382915 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 05:56:05.386205 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3065 05:56:05.389465 Pre-setting of DQS Precalculation
3066 05:56:05.392591 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3067 05:56:05.396170 ==
3068 05:56:05.396255 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 05:56:05.402911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 05:56:05.403012 ==
3071 05:56:05.405951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 05:56:05.412973 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3073 05:56:05.421645 [CA 0] Center 37 (7~68) winsize 62
3074 05:56:05.425315 [CA 1] Center 37 (7~68) winsize 62
3075 05:56:05.428056 [CA 2] Center 35 (5~65) winsize 61
3076 05:56:05.431341 [CA 3] Center 34 (4~65) winsize 62
3077 05:56:05.434677 [CA 4] Center 34 (4~64) winsize 61
3078 05:56:05.438138 [CA 5] Center 33 (3~63) winsize 61
3079 05:56:05.438222
3080 05:56:05.441776 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3081 05:56:05.441859
3082 05:56:05.445171 [CATrainingPosCal] consider 1 rank data
3083 05:56:05.447924 u2DelayCellTimex100 = 270/100 ps
3084 05:56:05.451308 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 05:56:05.454668 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 05:56:05.461724 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3087 05:56:05.464696 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3088 05:56:05.468094 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3089 05:56:05.471609 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3090 05:56:05.471692
3091 05:56:05.475131 CA PerBit enable=1, Macro0, CA PI delay=33
3092 05:56:05.475214
3093 05:56:05.477962 [CBTSetCACLKResult] CA Dly = 33
3094 05:56:05.478046 CS Dly: 8 (0~39)
3095 05:56:05.481454 ==
3096 05:56:05.481538 Dram Type= 6, Freq= 0, CH_1, rank 1
3097 05:56:05.488582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 05:56:05.488665 ==
3099 05:56:05.491495 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3100 05:56:05.498315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3101 05:56:05.507204 [CA 0] Center 37 (7~68) winsize 62
3102 05:56:05.510693 [CA 1] Center 37 (7~68) winsize 62
3103 05:56:05.513991 [CA 2] Center 35 (5~65) winsize 61
3104 05:56:05.517141 [CA 3] Center 34 (4~65) winsize 62
3105 05:56:05.520525 [CA 4] Center 34 (4~65) winsize 62
3106 05:56:05.523911 [CA 5] Center 34 (4~64) winsize 61
3107 05:56:05.524003
3108 05:56:05.527312 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3109 05:56:05.527391
3110 05:56:05.530465 [CATrainingPosCal] consider 2 rank data
3111 05:56:05.534121 u2DelayCellTimex100 = 270/100 ps
3112 05:56:05.537378 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3113 05:56:05.540519 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3114 05:56:05.547239 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3115 05:56:05.550128 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3116 05:56:05.553702 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3117 05:56:05.557225 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3118 05:56:05.557305
3119 05:56:05.560715 CA PerBit enable=1, Macro0, CA PI delay=33
3120 05:56:05.560808
3121 05:56:05.563538 [CBTSetCACLKResult] CA Dly = 33
3122 05:56:05.563623 CS Dly: 9 (0~41)
3123 05:56:05.563688
3124 05:56:05.566908 ----->DramcWriteLeveling(PI) begin...
3125 05:56:05.570313 ==
3126 05:56:05.573402 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 05:56:05.576923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 05:56:05.577003 ==
3129 05:56:05.580293 Write leveling (Byte 0): 25 => 25
3130 05:56:05.583897 Write leveling (Byte 1): 28 => 28
3131 05:56:05.586775 DramcWriteLeveling(PI) end<-----
3132 05:56:05.586851
3133 05:56:05.586915 ==
3134 05:56:05.590467 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 05:56:05.593857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 05:56:05.593934 ==
3137 05:56:05.597412 [Gating] SW mode calibration
3138 05:56:05.603754 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3139 05:56:05.607120 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3140 05:56:05.613574 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3141 05:56:05.617140 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 05:56:05.620690 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 05:56:05.626904 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 05:56:05.630457 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 05:56:05.633802 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 05:56:05.640660 0 15 24 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 1)
3147 05:56:05.643808 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3148 05:56:05.647508 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 05:56:05.654288 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 05:56:05.657193 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 05:56:05.660921 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 05:56:05.667579 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 05:56:05.671006 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 05:56:05.673920 1 0 24 | B1->B0 | 3434 4444 | 1 0 | (0 0) (0 0)
3155 05:56:05.677423 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 05:56:05.684103 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 05:56:05.687406 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 05:56:05.690896 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 05:56:05.697438 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 05:56:05.701022 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 05:56:05.704464 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 05:56:05.711043 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3163 05:56:05.714344 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3164 05:56:05.717940 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 05:56:05.724643 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 05:56:05.728185 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 05:56:05.731760 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 05:56:05.734796 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 05:56:05.741346 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 05:56:05.744897 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 05:56:05.747852 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 05:56:05.755251 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 05:56:05.758563 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 05:56:05.762051 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 05:56:05.768766 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 05:56:05.772078 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 05:56:05.775129 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3178 05:56:05.782039 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3179 05:56:05.785275 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3180 05:56:05.788340 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 05:56:05.791416 Total UI for P1: 0, mck2ui 16
3182 05:56:05.794821 best dqsien dly found for B0: ( 1, 3, 24)
3183 05:56:05.798827 Total UI for P1: 0, mck2ui 16
3184 05:56:05.801918 best dqsien dly found for B1: ( 1, 3, 26)
3185 05:56:05.805463 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3186 05:56:05.808197 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3187 05:56:05.808669
3188 05:56:05.811902 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3189 05:56:05.818688 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3190 05:56:05.819139 [Gating] SW calibration Done
3191 05:56:05.819481 ==
3192 05:56:05.821544 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 05:56:05.828511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 05:56:05.828739 ==
3195 05:56:05.828920 RX Vref Scan: 0
3196 05:56:05.829092
3197 05:56:05.831368 RX Vref 0 -> 0, step: 1
3198 05:56:05.831592
3199 05:56:05.834874 RX Delay -40 -> 252, step: 8
3200 05:56:05.838545 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3201 05:56:05.842060 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3202 05:56:05.844937 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3203 05:56:05.852004 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3204 05:56:05.854775 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3205 05:56:05.858206 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3206 05:56:05.861640 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3207 05:56:05.864782 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3208 05:56:05.868201 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
3209 05:56:05.875260 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3210 05:56:05.878009 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3211 05:56:05.881477 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3212 05:56:05.884751 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3213 05:56:05.891376 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3214 05:56:05.894706 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3215 05:56:05.898720 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3216 05:56:05.899086 ==
3217 05:56:05.901842 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 05:56:05.904913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 05:56:05.905283 ==
3220 05:56:05.908536 DQS Delay:
3221 05:56:05.909026 DQS0 = 0, DQS1 = 0
3222 05:56:05.909524 DQM Delay:
3223 05:56:05.911649 DQM0 = 120, DQM1 = 116
3224 05:56:05.912193 DQ Delay:
3225 05:56:05.915138 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3226 05:56:05.918268 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3227 05:56:05.924873 DQ8 =107, DQ9 =103, DQ10 =115, DQ11 =111
3228 05:56:05.928886 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3229 05:56:05.929311
3230 05:56:05.929784
3231 05:56:05.930144 ==
3232 05:56:05.932202 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 05:56:05.935020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 05:56:05.935536 ==
3235 05:56:05.936087
3236 05:56:05.936794
3237 05:56:05.938495 TX Vref Scan disable
3238 05:56:05.938985 == TX Byte 0 ==
3239 05:56:05.945436 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3240 05:56:05.948238 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3241 05:56:05.948648 == TX Byte 1 ==
3242 05:56:05.955186 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3243 05:56:05.958662 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3244 05:56:05.959080 ==
3245 05:56:05.962263 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 05:56:05.965117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 05:56:05.965488 ==
3248 05:56:05.977913 TX Vref=22, minBit 3, minWin=25, winSum=414
3249 05:56:05.981171 TX Vref=24, minBit 9, minWin=24, winSum=415
3250 05:56:05.984644 TX Vref=26, minBit 9, minWin=25, winSum=421
3251 05:56:05.988141 TX Vref=28, minBit 1, minWin=26, winSum=429
3252 05:56:05.991582 TX Vref=30, minBit 2, minWin=26, winSum=429
3253 05:56:05.995080 TX Vref=32, minBit 10, minWin=26, winSum=430
3254 05:56:06.001178 [TxChooseVref] Worse bit 10, Min win 26, Win sum 430, Final Vref 32
3255 05:56:06.001546
3256 05:56:06.004703 Final TX Range 1 Vref 32
3257 05:56:06.005069
3258 05:56:06.005441 ==
3259 05:56:06.008219 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 05:56:06.011767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 05:56:06.012135 ==
3262 05:56:06.015089
3263 05:56:06.015497
3264 05:56:06.015864 TX Vref Scan disable
3265 05:56:06.017887 == TX Byte 0 ==
3266 05:56:06.021259 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3267 05:56:06.024582 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3268 05:56:06.028276 == TX Byte 1 ==
3269 05:56:06.031472 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3270 05:56:06.034574 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3271 05:56:06.034955
3272 05:56:06.037979 [DATLAT]
3273 05:56:06.038346 Freq=1200, CH1 RK0
3274 05:56:06.038629
3275 05:56:06.041352 DATLAT Default: 0xd
3276 05:56:06.041920 0, 0xFFFF, sum = 0
3277 05:56:06.044557 1, 0xFFFF, sum = 0
3278 05:56:06.044989 2, 0xFFFF, sum = 0
3279 05:56:06.047840 3, 0xFFFF, sum = 0
3280 05:56:06.048454 4, 0xFFFF, sum = 0
3281 05:56:06.051394 5, 0xFFFF, sum = 0
3282 05:56:06.051942 6, 0xFFFF, sum = 0
3283 05:56:06.054724 7, 0xFFFF, sum = 0
3284 05:56:06.058118 8, 0xFFFF, sum = 0
3285 05:56:06.058641 9, 0xFFFF, sum = 0
3286 05:56:06.061106 10, 0xFFFF, sum = 0
3287 05:56:06.061724 11, 0xFFFF, sum = 0
3288 05:56:06.064537 12, 0x0, sum = 1
3289 05:56:06.065020 13, 0x0, sum = 2
3290 05:56:06.068174 14, 0x0, sum = 3
3291 05:56:06.068886 15, 0x0, sum = 4
3292 05:56:06.069514 best_step = 13
3293 05:56:06.070126
3294 05:56:06.071587 ==
3295 05:56:06.074376 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 05:56:06.078127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 05:56:06.078707 ==
3298 05:56:06.079224 RX Vref Scan: 1
3299 05:56:06.079685
3300 05:56:06.081405 Set Vref Range= 32 -> 127
3301 05:56:06.081703
3302 05:56:06.084879 RX Vref 32 -> 127, step: 1
3303 05:56:06.085322
3304 05:56:06.087482 RX Delay -5 -> 252, step: 4
3305 05:56:06.087706
3306 05:56:06.090715 Set Vref, RX VrefLevel [Byte0]: 32
3307 05:56:06.094036 [Byte1]: 32
3308 05:56:06.094331
3309 05:56:06.097203 Set Vref, RX VrefLevel [Byte0]: 33
3310 05:56:06.100787 [Byte1]: 33
3311 05:56:06.100969
3312 05:56:06.104116 Set Vref, RX VrefLevel [Byte0]: 34
3313 05:56:06.107650 [Byte1]: 34
3314 05:56:06.111877
3315 05:56:06.112057 Set Vref, RX VrefLevel [Byte0]: 35
3316 05:56:06.115314 [Byte1]: 35
3317 05:56:06.119845
3318 05:56:06.120025 Set Vref, RX VrefLevel [Byte0]: 36
3319 05:56:06.123248 [Byte1]: 36
3320 05:56:06.127413
3321 05:56:06.127682 Set Vref, RX VrefLevel [Byte0]: 37
3322 05:56:06.131215 [Byte1]: 37
3323 05:56:06.135484
3324 05:56:06.135841 Set Vref, RX VrefLevel [Byte0]: 38
3325 05:56:06.139077 [Byte1]: 38
3326 05:56:06.143366
3327 05:56:06.143837 Set Vref, RX VrefLevel [Byte0]: 39
3328 05:56:06.146754 [Byte1]: 39
3329 05:56:06.151188
3330 05:56:06.151664 Set Vref, RX VrefLevel [Byte0]: 40
3331 05:56:06.154824 [Byte1]: 40
3332 05:56:06.159158
3333 05:56:06.159573 Set Vref, RX VrefLevel [Byte0]: 41
3334 05:56:06.162805 [Byte1]: 41
3335 05:56:06.167114
3336 05:56:06.167532 Set Vref, RX VrefLevel [Byte0]: 42
3337 05:56:06.170239 [Byte1]: 42
3338 05:56:06.174505
3339 05:56:06.174922 Set Vref, RX VrefLevel [Byte0]: 43
3340 05:56:06.178307 [Byte1]: 43
3341 05:56:06.182877
3342 05:56:06.183292 Set Vref, RX VrefLevel [Byte0]: 44
3343 05:56:06.185757 [Byte1]: 44
3344 05:56:06.190575
3345 05:56:06.190998 Set Vref, RX VrefLevel [Byte0]: 45
3346 05:56:06.194050 [Byte1]: 45
3347 05:56:06.198075
3348 05:56:06.198529 Set Vref, RX VrefLevel [Byte0]: 46
3349 05:56:06.201348 [Byte1]: 46
3350 05:56:06.206005
3351 05:56:06.206570 Set Vref, RX VrefLevel [Byte0]: 47
3352 05:56:06.209581 [Byte1]: 47
3353 05:56:06.214177
3354 05:56:06.214595 Set Vref, RX VrefLevel [Byte0]: 48
3355 05:56:06.216892 [Byte1]: 48
3356 05:56:06.221678
3357 05:56:06.221855 Set Vref, RX VrefLevel [Byte0]: 49
3358 05:56:06.225380 [Byte1]: 49
3359 05:56:06.229435
3360 05:56:06.229612 Set Vref, RX VrefLevel [Byte0]: 50
3361 05:56:06.232968 [Byte1]: 50
3362 05:56:06.237094
3363 05:56:06.237271 Set Vref, RX VrefLevel [Byte0]: 51
3364 05:56:06.240634 [Byte1]: 51
3365 05:56:06.244970
3366 05:56:06.245156 Set Vref, RX VrefLevel [Byte0]: 52
3367 05:56:06.248473 [Byte1]: 52
3368 05:56:06.253516
3369 05:56:06.253706 Set Vref, RX VrefLevel [Byte0]: 53
3370 05:56:06.256531 [Byte1]: 53
3371 05:56:06.261266
3372 05:56:06.261764 Set Vref, RX VrefLevel [Byte0]: 54
3373 05:56:06.264693 [Byte1]: 54
3374 05:56:06.268807
3375 05:56:06.269243 Set Vref, RX VrefLevel [Byte0]: 55
3376 05:56:06.272175 [Byte1]: 55
3377 05:56:06.276816
3378 05:56:06.277292 Set Vref, RX VrefLevel [Byte0]: 56
3379 05:56:06.280461 [Byte1]: 56
3380 05:56:06.284923
3381 05:56:06.285340 Set Vref, RX VrefLevel [Byte0]: 57
3382 05:56:06.288099 [Byte1]: 57
3383 05:56:06.292370
3384 05:56:06.292934 Set Vref, RX VrefLevel [Byte0]: 58
3385 05:56:06.296112 [Byte1]: 58
3386 05:56:06.300804
3387 05:56:06.301234 Set Vref, RX VrefLevel [Byte0]: 59
3388 05:56:06.304325 [Byte1]: 59
3389 05:56:06.308695
3390 05:56:06.309114 Set Vref, RX VrefLevel [Byte0]: 60
3391 05:56:06.311866 [Byte1]: 60
3392 05:56:06.316120
3393 05:56:06.316602 Set Vref, RX VrefLevel [Byte0]: 61
3394 05:56:06.319306 [Byte1]: 61
3395 05:56:06.323821
3396 05:56:06.324464 Set Vref, RX VrefLevel [Byte0]: 62
3397 05:56:06.327248 [Byte1]: 62
3398 05:56:06.331601
3399 05:56:06.332057 Set Vref, RX VrefLevel [Byte0]: 63
3400 05:56:06.335066 [Byte1]: 63
3401 05:56:06.339694
3402 05:56:06.340168 Set Vref, RX VrefLevel [Byte0]: 64
3403 05:56:06.343207 [Byte1]: 64
3404 05:56:06.347338
3405 05:56:06.347649 Set Vref, RX VrefLevel [Byte0]: 65
3406 05:56:06.350849 [Byte1]: 65
3407 05:56:06.355009
3408 05:56:06.355235 Set Vref, RX VrefLevel [Byte0]: 66
3409 05:56:06.358541 [Byte1]: 66
3410 05:56:06.362811
3411 05:56:06.362963 Set Vref, RX VrefLevel [Byte0]: 67
3412 05:56:06.366301 [Byte1]: 67
3413 05:56:06.370568
3414 05:56:06.370718 Set Vref, RX VrefLevel [Byte0]: 68
3415 05:56:06.374089 [Byte1]: 68
3416 05:56:06.378970
3417 05:56:06.379122 Set Vref, RX VrefLevel [Byte0]: 69
3418 05:56:06.381865 [Byte1]: 69
3419 05:56:06.386930
3420 05:56:06.387081 Final RX Vref Byte 0 = 53 to rank0
3421 05:56:06.389715 Final RX Vref Byte 1 = 53 to rank0
3422 05:56:06.393195 Final RX Vref Byte 0 = 53 to rank1
3423 05:56:06.396643 Final RX Vref Byte 1 = 53 to rank1==
3424 05:56:06.400175 Dram Type= 6, Freq= 0, CH_1, rank 0
3425 05:56:06.406531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3426 05:56:06.406794 ==
3427 05:56:06.406985 DQS Delay:
3428 05:56:06.407165 DQS0 = 0, DQS1 = 0
3429 05:56:06.410234 DQM Delay:
3430 05:56:06.410546 DQM0 = 120, DQM1 = 117
3431 05:56:06.413580 DQ Delay:
3432 05:56:06.417008 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3433 05:56:06.420250 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3434 05:56:06.423489 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3435 05:56:06.426607 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3436 05:56:06.427031
3437 05:56:06.427368
3438 05:56:06.433403 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3439 05:56:06.436893 CH1 RK0: MR19=304, MR18=FF12
3440 05:56:06.443599 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3441 05:56:06.444055
3442 05:56:06.446643 ----->DramcWriteLeveling(PI) begin...
3443 05:56:06.447068 ==
3444 05:56:06.450369 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 05:56:06.453872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3446 05:56:06.456632 ==
3447 05:56:06.457056 Write leveling (Byte 0): 25 => 25
3448 05:56:06.460208 Write leveling (Byte 1): 27 => 27
3449 05:56:06.463753 DramcWriteLeveling(PI) end<-----
3450 05:56:06.464176
3451 05:56:06.464663 ==
3452 05:56:06.467209 Dram Type= 6, Freq= 0, CH_1, rank 1
3453 05:56:06.473329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3454 05:56:06.473887 ==
3455 05:56:06.474376 [Gating] SW mode calibration
3456 05:56:06.483209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3457 05:56:06.486535 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3458 05:56:06.490026 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 05:56:06.497046 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 05:56:06.499875 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 05:56:06.503299 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 05:56:06.509734 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 05:56:06.513175 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3464 05:56:06.516486 0 15 24 | B1->B0 | 2828 3434 | 1 0 | (1 0) (0 0)
3465 05:56:06.522993 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
3466 05:56:06.526765 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 05:56:06.530161 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 05:56:06.536251 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 05:56:06.540027 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 05:56:06.543524 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 05:56:06.550071 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3472 05:56:06.553447 1 0 24 | B1->B0 | 4444 2a2a | 0 0 | (0 0) (0 0)
3473 05:56:06.556923 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3474 05:56:06.563309 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 05:56:06.566942 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 05:56:06.569758 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 05:56:06.576634 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 05:56:06.580089 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 05:56:06.583076 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3480 05:56:06.590175 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3481 05:56:06.593492 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3482 05:56:06.596829 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 05:56:06.603033 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 05:56:06.606749 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 05:56:06.609563 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 05:56:06.616311 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 05:56:06.619326 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 05:56:06.622725 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 05:56:06.626198 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 05:56:06.633062 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 05:56:06.636242 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 05:56:06.639669 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 05:56:06.645809 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 05:56:06.649268 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 05:56:06.652611 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3496 05:56:06.659237 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3497 05:56:06.662744 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3498 05:56:06.665775 Total UI for P1: 0, mck2ui 16
3499 05:56:06.669044 best dqsien dly found for B1: ( 1, 3, 22)
3500 05:56:06.672566 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 05:56:06.675797 Total UI for P1: 0, mck2ui 16
3502 05:56:06.679472 best dqsien dly found for B0: ( 1, 3, 28)
3503 05:56:06.682471 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3504 05:56:06.686038 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3505 05:56:06.686498
3506 05:56:06.693121 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3507 05:56:06.695911 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3508 05:56:06.699350 [Gating] SW calibration Done
3509 05:56:06.699848 ==
3510 05:56:06.702847 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 05:56:06.706130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 05:56:06.706717 ==
3513 05:56:06.707238 RX Vref Scan: 0
3514 05:56:06.707672
3515 05:56:06.709600 RX Vref 0 -> 0, step: 1
3516 05:56:06.710189
3517 05:56:06.712515 RX Delay -40 -> 252, step: 8
3518 05:56:06.716003 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3519 05:56:06.719495 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3520 05:56:06.725963 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3521 05:56:06.729418 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3522 05:56:06.732140 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3523 05:56:06.735539 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3524 05:56:06.738907 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3525 05:56:06.745688 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3526 05:56:06.748865 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3527 05:56:06.752244 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3528 05:56:06.756032 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3529 05:56:06.758667 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3530 05:56:06.765687 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3531 05:56:06.769035 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3532 05:56:06.772019 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3533 05:56:06.775599 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3534 05:56:06.775863 ==
3535 05:56:06.779109 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 05:56:06.785387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 05:56:06.785688 ==
3538 05:56:06.785922 DQS Delay:
3539 05:56:06.788889 DQS0 = 0, DQS1 = 0
3540 05:56:06.789074 DQM Delay:
3541 05:56:06.789286 DQM0 = 120, DQM1 = 117
3542 05:56:06.792161 DQ Delay:
3543 05:56:06.795463 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3544 05:56:06.798593 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3545 05:56:06.801600 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3546 05:56:06.805212 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3547 05:56:06.805490
3548 05:56:06.805789
3549 05:56:06.806079 ==
3550 05:56:06.808737 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 05:56:06.811970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 05:56:06.815226 ==
3553 05:56:06.815560
3554 05:56:06.815859
3555 05:56:06.816172 TX Vref Scan disable
3556 05:56:06.818437 == TX Byte 0 ==
3557 05:56:06.821877 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3558 05:56:06.825370 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3559 05:56:06.828251 == TX Byte 1 ==
3560 05:56:06.831706 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3561 05:56:06.835245 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3562 05:56:06.838813 ==
3563 05:56:06.839149 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 05:56:06.845029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 05:56:06.845382 ==
3566 05:56:06.856008 TX Vref=22, minBit 9, minWin=25, winSum=420
3567 05:56:06.859136 TX Vref=24, minBit 10, minWin=25, winSum=423
3568 05:56:06.862428 TX Vref=26, minBit 9, minWin=26, winSum=431
3569 05:56:06.866011 TX Vref=28, minBit 9, minWin=26, winSum=434
3570 05:56:06.868619 TX Vref=30, minBit 9, minWin=26, winSum=435
3571 05:56:06.875892 TX Vref=32, minBit 9, minWin=26, winSum=432
3572 05:56:06.879066 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3573 05:56:06.879151
3574 05:56:06.882554 Final TX Range 1 Vref 30
3575 05:56:06.882637
3576 05:56:06.882702 ==
3577 05:56:06.885491 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 05:56:06.888886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 05:56:06.891788 ==
3580 05:56:06.891882
3581 05:56:06.891997
3582 05:56:06.892101 TX Vref Scan disable
3583 05:56:06.895472 == TX Byte 0 ==
3584 05:56:06.898908 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3585 05:56:06.905252 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3586 05:56:06.905393 == TX Byte 1 ==
3587 05:56:06.908812 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3588 05:56:06.915685 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3589 05:56:06.915839
3590 05:56:06.916026 [DATLAT]
3591 05:56:06.916195 Freq=1200, CH1 RK1
3592 05:56:06.916371
3593 05:56:06.919021 DATLAT Default: 0xd
3594 05:56:06.919178 0, 0xFFFF, sum = 0
3595 05:56:06.922087 1, 0xFFFF, sum = 0
3596 05:56:06.925620 2, 0xFFFF, sum = 0
3597 05:56:06.925825 3, 0xFFFF, sum = 0
3598 05:56:06.928707 4, 0xFFFF, sum = 0
3599 05:56:06.928958 5, 0xFFFF, sum = 0
3600 05:56:06.932307 6, 0xFFFF, sum = 0
3601 05:56:06.932556 7, 0xFFFF, sum = 0
3602 05:56:06.935483 8, 0xFFFF, sum = 0
3603 05:56:06.935782 9, 0xFFFF, sum = 0
3604 05:56:06.938647 10, 0xFFFF, sum = 0
3605 05:56:06.938974 11, 0xFFFF, sum = 0
3606 05:56:06.942270 12, 0x0, sum = 1
3607 05:56:06.942818 13, 0x0, sum = 2
3608 05:56:06.945850 14, 0x0, sum = 3
3609 05:56:06.946314 15, 0x0, sum = 4
3610 05:56:06.949308 best_step = 13
3611 05:56:06.949797
3612 05:56:06.950274 ==
3613 05:56:06.952079 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 05:56:06.955834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 05:56:06.956322 ==
3616 05:56:06.956682 RX Vref Scan: 0
3617 05:56:06.957057
3618 05:56:06.959226 RX Vref 0 -> 0, step: 1
3619 05:56:06.959867
3620 05:56:06.961982 RX Delay -5 -> 252, step: 4
3621 05:56:06.965432 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3622 05:56:06.972126 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3623 05:56:06.975714 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3624 05:56:06.979710 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3625 05:56:06.982028 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3626 05:56:06.985176 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3627 05:56:06.992014 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3628 05:56:06.995837 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3629 05:56:06.998894 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3630 05:56:07.002262 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3631 05:56:07.005786 iDelay=195, Bit 10, Center 120 (59 ~ 182) 124
3632 05:56:07.012015 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3633 05:56:07.015485 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3634 05:56:07.018902 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3635 05:56:07.021631 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3636 05:56:07.025199 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3637 05:56:07.028608 ==
3638 05:56:07.032025 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 05:56:07.034823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 05:56:07.035006 ==
3641 05:56:07.035178 DQS Delay:
3642 05:56:07.038020 DQS0 = 0, DQS1 = 0
3643 05:56:07.038091 DQM Delay:
3644 05:56:07.041487 DQM0 = 120, DQM1 = 118
3645 05:56:07.041568 DQ Delay:
3646 05:56:07.045148 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3647 05:56:07.048532 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3648 05:56:07.051773 DQ8 =106, DQ9 =108, DQ10 =120, DQ11 =112
3649 05:56:07.054939 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3650 05:56:07.055020
3651 05:56:07.055086
3652 05:56:07.065056 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3653 05:56:07.068693 CH1 RK1: MR19=403, MR18=11EE
3654 05:56:07.071453 CH1_RK1: MR19=0x403, MR18=0x11EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3655 05:56:07.074695 [RxdqsGatingPostProcess] freq 1200
3656 05:56:07.081573 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3657 05:56:07.085193 best DQS0 dly(2T, 0.5T) = (0, 11)
3658 05:56:07.088535 best DQS1 dly(2T, 0.5T) = (0, 11)
3659 05:56:07.091362 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3660 05:56:07.094954 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3661 05:56:07.098380 best DQS0 dly(2T, 0.5T) = (0, 11)
3662 05:56:07.101582 best DQS1 dly(2T, 0.5T) = (0, 11)
3663 05:56:07.104756 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3664 05:56:07.108035 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3665 05:56:07.110894 Pre-setting of DQS Precalculation
3666 05:56:07.114410 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3667 05:56:07.120809 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3668 05:56:07.127344 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3669 05:56:07.130878
3670 05:56:07.130954
3671 05:56:07.131016 [Calibration Summary] 2400 Mbps
3672 05:56:07.134371 CH 0, Rank 0
3673 05:56:07.134453 SW Impedance : PASS
3674 05:56:07.137651 DUTY Scan : NO K
3675 05:56:07.141224 ZQ Calibration : PASS
3676 05:56:07.141304 Jitter Meter : NO K
3677 05:56:07.144117 CBT Training : PASS
3678 05:56:07.147617 Write leveling : PASS
3679 05:56:07.147721 RX DQS gating : PASS
3680 05:56:07.150894 RX DQ/DQS(RDDQC) : PASS
3681 05:56:07.154536 TX DQ/DQS : PASS
3682 05:56:07.154610 RX DATLAT : PASS
3683 05:56:07.157369 RX DQ/DQS(Engine): PASS
3684 05:56:07.160903 TX OE : NO K
3685 05:56:07.161033 All Pass.
3686 05:56:07.161127
3687 05:56:07.161207 CH 0, Rank 1
3688 05:56:07.164354 SW Impedance : PASS
3689 05:56:07.167631 DUTY Scan : NO K
3690 05:56:07.167712 ZQ Calibration : PASS
3691 05:56:07.171071 Jitter Meter : NO K
3692 05:56:07.174422 CBT Training : PASS
3693 05:56:07.174503 Write leveling : PASS
3694 05:56:07.177558 RX DQS gating : PASS
3695 05:56:07.177646 RX DQ/DQS(RDDQC) : PASS
3696 05:56:07.181049 TX DQ/DQS : PASS
3697 05:56:07.184148 RX DATLAT : PASS
3698 05:56:07.184243 RX DQ/DQS(Engine): PASS
3699 05:56:07.187480 TX OE : NO K
3700 05:56:07.187582 All Pass.
3701 05:56:07.187663
3702 05:56:07.190781 CH 1, Rank 0
3703 05:56:07.190891 SW Impedance : PASS
3704 05:56:07.194134 DUTY Scan : NO K
3705 05:56:07.197994 ZQ Calibration : PASS
3706 05:56:07.198650 Jitter Meter : NO K
3707 05:56:07.200788 CBT Training : PASS
3708 05:56:07.204358 Write leveling : PASS
3709 05:56:07.204822 RX DQS gating : PASS
3710 05:56:07.207922 RX DQ/DQS(RDDQC) : PASS
3711 05:56:07.211276 TX DQ/DQS : PASS
3712 05:56:07.211697 RX DATLAT : PASS
3713 05:56:07.214572 RX DQ/DQS(Engine): PASS
3714 05:56:07.217909 TX OE : NO K
3715 05:56:07.218346 All Pass.
3716 05:56:07.218724
3717 05:56:07.219036 CH 1, Rank 1
3718 05:56:07.221122 SW Impedance : PASS
3719 05:56:07.224603 DUTY Scan : NO K
3720 05:56:07.225040 ZQ Calibration : PASS
3721 05:56:07.227570 Jitter Meter : NO K
3722 05:56:07.228000 CBT Training : PASS
3723 05:56:07.230995 Write leveling : PASS
3724 05:56:07.234604 RX DQS gating : PASS
3725 05:56:07.235178 RX DQ/DQS(RDDQC) : PASS
3726 05:56:07.237861 TX DQ/DQS : PASS
3727 05:56:07.241441 RX DATLAT : PASS
3728 05:56:07.242036 RX DQ/DQS(Engine): PASS
3729 05:56:07.244066 TX OE : NO K
3730 05:56:07.244584 All Pass.
3731 05:56:07.244953
3732 05:56:07.247466 DramC Write-DBI off
3733 05:56:07.251099 PER_BANK_REFRESH: Hybrid Mode
3734 05:56:07.251562 TX_TRACKING: ON
3735 05:56:07.261129 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3736 05:56:07.264447 [FAST_K] Save calibration result to emmc
3737 05:56:07.267273 dramc_set_vcore_voltage set vcore to 650000
3738 05:56:07.270638 Read voltage for 600, 5
3739 05:56:07.270943 Vio18 = 0
3740 05:56:07.271198 Vcore = 650000
3741 05:56:07.274188 Vdram = 0
3742 05:56:07.274615 Vddq = 0
3743 05:56:07.275011 Vmddr = 0
3744 05:56:07.280186 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3745 05:56:07.283582 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3746 05:56:07.287590 MEM_TYPE=3, freq_sel=19
3747 05:56:07.290815 sv_algorithm_assistance_LP4_1600
3748 05:56:07.293992 ============ PULL DRAM RESETB DOWN ============
3749 05:56:07.297269 ========== PULL DRAM RESETB DOWN end =========
3750 05:56:07.303609 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3751 05:56:07.306946 ===================================
3752 05:56:07.310706 LPDDR4 DRAM CONFIGURATION
3753 05:56:07.313632 ===================================
3754 05:56:07.313785 EX_ROW_EN[0] = 0x0
3755 05:56:07.317207 EX_ROW_EN[1] = 0x0
3756 05:56:07.317360 LP4Y_EN = 0x0
3757 05:56:07.320568 WORK_FSP = 0x0
3758 05:56:07.320766 WL = 0x2
3759 05:56:07.323445 RL = 0x2
3760 05:56:07.323659 BL = 0x2
3761 05:56:07.327218 RPST = 0x0
3762 05:56:07.327436 RD_PRE = 0x0
3763 05:56:07.330345 WR_PRE = 0x1
3764 05:56:07.330564 WR_PST = 0x0
3765 05:56:07.333829 DBI_WR = 0x0
3766 05:56:07.334092 DBI_RD = 0x0
3767 05:56:07.336785 OTF = 0x1
3768 05:56:07.340371 ===================================
3769 05:56:07.343987 ===================================
3770 05:56:07.344422 ANA top config
3771 05:56:07.346999 ===================================
3772 05:56:07.350397 DLL_ASYNC_EN = 0
3773 05:56:07.353824 ALL_SLAVE_EN = 1
3774 05:56:07.357325 NEW_RANK_MODE = 1
3775 05:56:07.357716 DLL_IDLE_MODE = 1
3776 05:56:07.360855 LP45_APHY_COMB_EN = 1
3777 05:56:07.363626 TX_ODT_DIS = 1
3778 05:56:07.367056 NEW_8X_MODE = 1
3779 05:56:07.370274 ===================================
3780 05:56:07.373519 ===================================
3781 05:56:07.377419 data_rate = 1200
3782 05:56:07.377880 CKR = 1
3783 05:56:07.380246 DQ_P2S_RATIO = 8
3784 05:56:07.383853 ===================================
3785 05:56:07.387420 CA_P2S_RATIO = 8
3786 05:56:07.390203 DQ_CA_OPEN = 0
3787 05:56:07.393512 DQ_SEMI_OPEN = 0
3788 05:56:07.396907 CA_SEMI_OPEN = 0
3789 05:56:07.397295 CA_FULL_RATE = 0
3790 05:56:07.400496 DQ_CKDIV4_EN = 1
3791 05:56:07.403947 CA_CKDIV4_EN = 1
3792 05:56:07.407207 CA_PREDIV_EN = 0
3793 05:56:07.410758 PH8_DLY = 0
3794 05:56:07.413959 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3795 05:56:07.414351 DQ_AAMCK_DIV = 4
3796 05:56:07.417000 CA_AAMCK_DIV = 4
3797 05:56:07.420195 CA_ADMCK_DIV = 4
3798 05:56:07.423903 DQ_TRACK_CA_EN = 0
3799 05:56:07.427393 CA_PICK = 600
3800 05:56:07.430222 CA_MCKIO = 600
3801 05:56:07.430672 MCKIO_SEMI = 0
3802 05:56:07.433784 PLL_FREQ = 2288
3803 05:56:07.437102 DQ_UI_PI_RATIO = 32
3804 05:56:07.440524 CA_UI_PI_RATIO = 0
3805 05:56:07.443696 ===================================
3806 05:56:07.447384 ===================================
3807 05:56:07.450299 memory_type:LPDDR4
3808 05:56:07.450771 GP_NUM : 10
3809 05:56:07.453758 SRAM_EN : 1
3810 05:56:07.456740 MD32_EN : 0
3811 05:56:07.460128 ===================================
3812 05:56:07.460563 [ANA_INIT] >>>>>>>>>>>>>>
3813 05:56:07.463707 <<<<<< [CONFIGURE PHASE]: ANA_TX
3814 05:56:07.467131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3815 05:56:07.470139 ===================================
3816 05:56:07.473735 data_rate = 1200,PCW = 0X5800
3817 05:56:07.477184 ===================================
3818 05:56:07.480688 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3819 05:56:07.487360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3820 05:56:07.490695 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3821 05:56:07.496775 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3822 05:56:07.500152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3823 05:56:07.503491 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3824 05:56:07.503893 [ANA_INIT] flow start
3825 05:56:07.506837 [ANA_INIT] PLL >>>>>>>>
3826 05:56:07.510350 [ANA_INIT] PLL <<<<<<<<
3827 05:56:07.510917 [ANA_INIT] MIDPI >>>>>>>>
3828 05:56:07.513931 [ANA_INIT] MIDPI <<<<<<<<
3829 05:56:07.516759 [ANA_INIT] DLL >>>>>>>>
3830 05:56:07.517236 [ANA_INIT] flow end
3831 05:56:07.523365 ============ LP4 DIFF to SE enter ============
3832 05:56:07.526617 ============ LP4 DIFF to SE exit ============
3833 05:56:07.529801 [ANA_INIT] <<<<<<<<<<<<<
3834 05:56:07.533528 [Flow] Enable top DCM control >>>>>
3835 05:56:07.536401 [Flow] Enable top DCM control <<<<<
3836 05:56:07.539887 Enable DLL master slave shuffle
3837 05:56:07.543520 ==============================================================
3838 05:56:07.546281 Gating Mode config
3839 05:56:07.549354 ==============================================================
3840 05:56:07.553274 Config description:
3841 05:56:07.562877 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3842 05:56:07.569863 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3843 05:56:07.572716 SELPH_MODE 0: By rank 1: By Phase
3844 05:56:07.579210 ==============================================================
3845 05:56:07.582734 GAT_TRACK_EN = 1
3846 05:56:07.586518 RX_GATING_MODE = 2
3847 05:56:07.590058 RX_GATING_TRACK_MODE = 2
3848 05:56:07.593431 SELPH_MODE = 1
3849 05:56:07.596065 PICG_EARLY_EN = 1
3850 05:56:07.599421 VALID_LAT_VALUE = 1
3851 05:56:07.602783 ==============================================================
3852 05:56:07.606100 Enter into Gating configuration >>>>
3853 05:56:07.609412 Exit from Gating configuration <<<<
3854 05:56:07.612879 Enter into DVFS_PRE_config >>>>>
3855 05:56:07.622830 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3856 05:56:07.626214 Exit from DVFS_PRE_config <<<<<
3857 05:56:07.629663 Enter into PICG configuration >>>>
3858 05:56:07.632475 Exit from PICG configuration <<<<
3859 05:56:07.635943 [RX_INPUT] configuration >>>>>
3860 05:56:07.639308 [RX_INPUT] configuration <<<<<
3861 05:56:07.645968 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3862 05:56:07.649499 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3863 05:56:07.655650 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3864 05:56:07.662330 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3865 05:56:07.668866 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3866 05:56:07.675580 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3867 05:56:07.679295 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3868 05:56:07.681956 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3869 05:56:07.685614 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3870 05:56:07.692068 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3871 05:56:07.695558 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3872 05:56:07.698631 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 05:56:07.702069 ===================================
3874 05:56:07.705647 LPDDR4 DRAM CONFIGURATION
3875 05:56:07.708937 ===================================
3876 05:56:07.709092 EX_ROW_EN[0] = 0x0
3877 05:56:07.712193 EX_ROW_EN[1] = 0x0
3878 05:56:07.715378 LP4Y_EN = 0x0
3879 05:56:07.715553 WORK_FSP = 0x0
3880 05:56:07.718677 WL = 0x2
3881 05:56:07.718854 RL = 0x2
3882 05:56:07.721931 BL = 0x2
3883 05:56:07.722133 RPST = 0x0
3884 05:56:07.725670 RD_PRE = 0x0
3885 05:56:07.725999 WR_PRE = 0x1
3886 05:56:07.729071 WR_PST = 0x0
3887 05:56:07.729322 DBI_WR = 0x0
3888 05:56:07.732511 DBI_RD = 0x0
3889 05:56:07.732813 OTF = 0x1
3890 05:56:07.735400 ===================================
3891 05:56:07.738952 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3892 05:56:07.746083 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3893 05:56:07.748955 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3894 05:56:07.752361 ===================================
3895 05:56:07.755775 LPDDR4 DRAM CONFIGURATION
3896 05:56:07.758920 ===================================
3897 05:56:07.759340 EX_ROW_EN[0] = 0x10
3898 05:56:07.762685 EX_ROW_EN[1] = 0x0
3899 05:56:07.763130 LP4Y_EN = 0x0
3900 05:56:07.765450 WORK_FSP = 0x0
3901 05:56:07.765879 WL = 0x2
3902 05:56:07.768884 RL = 0x2
3903 05:56:07.769308 BL = 0x2
3904 05:56:07.772575 RPST = 0x0
3905 05:56:07.773152 RD_PRE = 0x0
3906 05:56:07.775788 WR_PRE = 0x1
3907 05:56:07.779072 WR_PST = 0x0
3908 05:56:07.779487 DBI_WR = 0x0
3909 05:56:07.782323 DBI_RD = 0x0
3910 05:56:07.782940 OTF = 0x1
3911 05:56:07.785724 ===================================
3912 05:56:07.792522 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3913 05:56:07.795930 nWR fixed to 30
3914 05:56:07.799266 [ModeRegInit_LP4] CH0 RK0
3915 05:56:07.799783 [ModeRegInit_LP4] CH0 RK1
3916 05:56:07.802728 [ModeRegInit_LP4] CH1 RK0
3917 05:56:07.805466 [ModeRegInit_LP4] CH1 RK1
3918 05:56:07.805752 match AC timing 17
3919 05:56:07.812377 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3920 05:56:07.816047 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3921 05:56:07.818818 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3922 05:56:07.825859 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3923 05:56:07.829160 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3924 05:56:07.829631 ==
3925 05:56:07.832231 Dram Type= 6, Freq= 0, CH_0, rank 0
3926 05:56:07.836178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3927 05:56:07.836659 ==
3928 05:56:07.842211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3929 05:56:07.849315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3930 05:56:07.852811 [CA 0] Center 35 (5~66) winsize 62
3931 05:56:07.855518 [CA 1] Center 35 (5~66) winsize 62
3932 05:56:07.859057 [CA 2] Center 33 (3~64) winsize 62
3933 05:56:07.862458 [CA 3] Center 33 (2~64) winsize 63
3934 05:56:07.865453 [CA 4] Center 33 (2~64) winsize 63
3935 05:56:07.868794 [CA 5] Center 32 (2~63) winsize 62
3936 05:56:07.869307
3937 05:56:07.872007 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3938 05:56:07.872514
3939 05:56:07.875419 [CATrainingPosCal] consider 1 rank data
3940 05:56:07.879281 u2DelayCellTimex100 = 270/100 ps
3941 05:56:07.882395 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3942 05:56:07.885966 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3943 05:56:07.888687 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3944 05:56:07.892036 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3945 05:56:07.895398 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3946 05:56:07.899214 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3947 05:56:07.902087
3948 05:56:07.905621 CA PerBit enable=1, Macro0, CA PI delay=32
3949 05:56:07.906184
3950 05:56:07.908870 [CBTSetCACLKResult] CA Dly = 32
3951 05:56:07.909300 CS Dly: 5 (0~36)
3952 05:56:07.909639 ==
3953 05:56:07.912567 Dram Type= 6, Freq= 0, CH_0, rank 1
3954 05:56:07.916054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 05:56:07.916558 ==
3956 05:56:07.922267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3957 05:56:07.929296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3958 05:56:07.932001 [CA 0] Center 35 (5~66) winsize 62
3959 05:56:07.935393 [CA 1] Center 35 (5~66) winsize 62
3960 05:56:07.938829 [CA 2] Center 33 (3~64) winsize 62
3961 05:56:07.941412 [CA 3] Center 33 (3~64) winsize 62
3962 05:56:07.945428 [CA 4] Center 33 (2~64) winsize 63
3963 05:56:07.948203 [CA 5] Center 32 (2~63) winsize 62
3964 05:56:07.948418
3965 05:56:07.951495 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3966 05:56:07.951677
3967 05:56:07.955042 [CATrainingPosCal] consider 2 rank data
3968 05:56:07.958513 u2DelayCellTimex100 = 270/100 ps
3969 05:56:07.962094 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3970 05:56:07.964941 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3971 05:56:07.968488 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3972 05:56:07.971135 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3973 05:56:07.978234 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3974 05:56:07.981204 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3975 05:56:07.981449
3976 05:56:07.984613 CA PerBit enable=1, Macro0, CA PI delay=32
3977 05:56:07.984886
3978 05:56:07.988579 [CBTSetCACLKResult] CA Dly = 32
3979 05:56:07.988919 CS Dly: 5 (0~36)
3980 05:56:07.989187
3981 05:56:07.991618 ----->DramcWriteLeveling(PI) begin...
3982 05:56:07.991946 ==
3983 05:56:07.994845 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 05:56:08.001917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 05:56:08.002249 ==
3986 05:56:08.004750 Write leveling (Byte 0): 35 => 35
3987 05:56:08.008253 Write leveling (Byte 1): 32 => 32
3988 05:56:08.008658 DramcWriteLeveling(PI) end<-----
3989 05:56:08.008921
3990 05:56:08.011617 ==
3991 05:56:08.014805 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 05:56:08.018028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 05:56:08.018421 ==
3994 05:56:08.021505 [Gating] SW mode calibration
3995 05:56:08.028203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3996 05:56:08.031532 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3997 05:56:08.037799 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 05:56:08.041259 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 05:56:08.044836 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 05:56:08.051771 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 1)
4001 05:56:08.055125 0 9 16 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
4002 05:56:08.058216 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 05:56:08.064909 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 05:56:08.068194 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 05:56:08.071794 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 05:56:08.078016 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 05:56:08.081550 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 05:56:08.084694 0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
4009 05:56:08.091564 0 10 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
4010 05:56:08.094493 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 05:56:08.097852 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 05:56:08.101012 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 05:56:08.108145 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 05:56:08.111052 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 05:56:08.114513 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 05:56:08.121289 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 05:56:08.124733 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4018 05:56:08.128021 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 05:56:08.134611 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 05:56:08.137850 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 05:56:08.140961 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 05:56:08.147796 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 05:56:08.150723 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 05:56:08.154075 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 05:56:08.161075 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 05:56:08.164590 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 05:56:08.167895 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 05:56:08.173863 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 05:56:08.177761 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 05:56:08.180933 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 05:56:08.187189 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 05:56:08.190710 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4033 05:56:08.194112 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4034 05:56:08.197675 Total UI for P1: 0, mck2ui 16
4035 05:56:08.200379 best dqsien dly found for B0: ( 0, 13, 12)
4036 05:56:08.207603 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 05:56:08.208087 Total UI for P1: 0, mck2ui 16
4038 05:56:08.214017 best dqsien dly found for B1: ( 0, 13, 16)
4039 05:56:08.217145 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4040 05:56:08.220387 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4041 05:56:08.220970
4042 05:56:08.224206 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4043 05:56:08.227100 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4044 05:56:08.230773 [Gating] SW calibration Done
4045 05:56:08.231192 ==
4046 05:56:08.234120 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 05:56:08.237613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 05:56:08.238037 ==
4049 05:56:08.240520 RX Vref Scan: 0
4050 05:56:08.241011
4051 05:56:08.241417 RX Vref 0 -> 0, step: 1
4052 05:56:08.241774
4053 05:56:08.243907 RX Delay -230 -> 252, step: 16
4054 05:56:08.250918 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4055 05:56:08.254224 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4056 05:56:08.256975 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4057 05:56:08.260258 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4058 05:56:08.263944 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4059 05:56:08.270312 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4060 05:56:08.273599 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4061 05:56:08.277045 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4062 05:56:08.280625 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4063 05:56:08.286914 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4064 05:56:08.290150 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4065 05:56:08.293637 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4066 05:56:08.297323 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4067 05:56:08.300255 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4068 05:56:08.306591 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4069 05:56:08.310148 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4070 05:56:08.310629 ==
4071 05:56:08.313684 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 05:56:08.317237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 05:56:08.317823 ==
4074 05:56:08.320207 DQS Delay:
4075 05:56:08.320791 DQS0 = 0, DQS1 = 0
4076 05:56:08.323496 DQM Delay:
4077 05:56:08.324133 DQM0 = 53, DQM1 = 46
4078 05:56:08.324601 DQ Delay:
4079 05:56:08.327023 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4080 05:56:08.329936 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4081 05:56:08.333636 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4082 05:56:08.336722 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =49
4083 05:56:08.337099
4084 05:56:08.337435
4085 05:56:08.337769 ==
4086 05:56:08.339646 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 05:56:08.346647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 05:56:08.346878 ==
4089 05:56:08.347061
4090 05:56:08.347229
4091 05:56:08.347387 TX Vref Scan disable
4092 05:56:08.350829 == TX Byte 0 ==
4093 05:56:08.354153 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4094 05:56:08.356852 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4095 05:56:08.360306 == TX Byte 1 ==
4096 05:56:08.363967 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4097 05:56:08.370196 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4098 05:56:08.370426 ==
4099 05:56:08.373877 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 05:56:08.376611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 05:56:08.376838 ==
4102 05:56:08.377017
4103 05:56:08.377184
4104 05:56:08.379660 TX Vref Scan disable
4105 05:56:08.383589 == TX Byte 0 ==
4106 05:56:08.386761 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4107 05:56:08.389780 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4108 05:56:08.393542 == TX Byte 1 ==
4109 05:56:08.396175 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4110 05:56:08.399553 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4111 05:56:08.399635
4112 05:56:08.399710 [DATLAT]
4113 05:56:08.403100 Freq=600, CH0 RK0
4114 05:56:08.403195
4115 05:56:08.406743 DATLAT Default: 0x9
4116 05:56:08.406825 0, 0xFFFF, sum = 0
4117 05:56:08.409491 1, 0xFFFF, sum = 0
4118 05:56:08.409574 2, 0xFFFF, sum = 0
4119 05:56:08.413141 3, 0xFFFF, sum = 0
4120 05:56:08.413223 4, 0xFFFF, sum = 0
4121 05:56:08.416735 5, 0xFFFF, sum = 0
4122 05:56:08.416817 6, 0xFFFF, sum = 0
4123 05:56:08.419663 7, 0xFFFF, sum = 0
4124 05:56:08.419745 8, 0x0, sum = 1
4125 05:56:08.423106 9, 0x0, sum = 2
4126 05:56:08.423189 10, 0x0, sum = 3
4127 05:56:08.423255 11, 0x0, sum = 4
4128 05:56:08.426726 best_step = 9
4129 05:56:08.426807
4130 05:56:08.426871 ==
4131 05:56:08.429485 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 05:56:08.432957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 05:56:08.433042 ==
4134 05:56:08.436468 RX Vref Scan: 1
4135 05:56:08.436549
4136 05:56:08.439947 RX Vref 0 -> 0, step: 1
4137 05:56:08.440029
4138 05:56:08.440097 RX Delay -163 -> 252, step: 8
4139 05:56:08.440159
4140 05:56:08.442598 Set Vref, RX VrefLevel [Byte0]: 54
4141 05:56:08.446054 [Byte1]: 55
4142 05:56:08.450355
4143 05:56:08.450431 Final RX Vref Byte 0 = 54 to rank0
4144 05:56:08.454053 Final RX Vref Byte 1 = 55 to rank0
4145 05:56:08.457010 Final RX Vref Byte 0 = 54 to rank1
4146 05:56:08.460619 Final RX Vref Byte 1 = 55 to rank1==
4147 05:56:08.464141 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 05:56:08.470451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 05:56:08.470561 ==
4150 05:56:08.470628 DQS Delay:
4151 05:56:08.470688 DQS0 = 0, DQS1 = 0
4152 05:56:08.473688 DQM Delay:
4153 05:56:08.473775 DQM0 = 53, DQM1 = 46
4154 05:56:08.477102 DQ Delay:
4155 05:56:08.480541 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4156 05:56:08.480617 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4157 05:56:08.484157 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4158 05:56:08.487591 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4159 05:56:08.490443
4160 05:56:08.490516
4161 05:56:08.497281 [DQSOSCAuto] RK0, (LSB)MR18= 0x7164, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4162 05:56:08.500412 CH0 RK0: MR19=808, MR18=7164
4163 05:56:08.507054 CH0_RK0: MR19=0x808, MR18=0x7164, DQSOSC=388, MR23=63, INC=174, DEC=116
4164 05:56:08.507147
4165 05:56:08.510354 ----->DramcWriteLeveling(PI) begin...
4166 05:56:08.510428 ==
4167 05:56:08.513696 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 05:56:08.517164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 05:56:08.517243 ==
4170 05:56:08.520943 Write leveling (Byte 0): 34 => 34
4171 05:56:08.523739 Write leveling (Byte 1): 32 => 32
4172 05:56:08.527384 DramcWriteLeveling(PI) end<-----
4173 05:56:08.527457
4174 05:56:08.527517 ==
4175 05:56:08.530197 Dram Type= 6, Freq= 0, CH_0, rank 1
4176 05:56:08.533687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 05:56:08.533759 ==
4178 05:56:08.537182 [Gating] SW mode calibration
4179 05:56:08.544218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4180 05:56:08.550513 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4181 05:56:08.554050 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4182 05:56:08.556931 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 05:56:08.563937 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 05:56:08.567257 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4185 05:56:08.570569 0 9 16 | B1->B0 | 2a2a 2626 | 1 0 | (1 0) (0 0)
4186 05:56:08.576782 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 05:56:08.580623 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 05:56:08.583991 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 05:56:08.590297 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 05:56:08.593799 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 05:56:08.597108 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 05:56:08.603436 0 10 12 | B1->B0 | 2424 2323 | 0 1 | (0 0) (0 0)
4193 05:56:08.606847 0 10 16 | B1->B0 | 3c3c 4444 | 1 0 | (0 0) (0 0)
4194 05:56:08.610162 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 05:56:08.617633 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 05:56:08.620587 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 05:56:08.623946 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 05:56:08.630512 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 05:56:08.634102 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 05:56:08.637523 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4201 05:56:08.644142 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4202 05:56:08.647570 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 05:56:08.650546 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 05:56:08.656946 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 05:56:08.660591 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 05:56:08.663557 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 05:56:08.670810 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 05:56:08.673513 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 05:56:08.676910 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 05:56:08.680646 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 05:56:08.687293 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 05:56:08.690748 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 05:56:08.693625 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 05:56:08.700533 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 05:56:08.703968 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 05:56:08.707321 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4217 05:56:08.713294 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 05:56:08.716681 Total UI for P1: 0, mck2ui 16
4219 05:56:08.720003 best dqsien dly found for B0: ( 0, 13, 12)
4220 05:56:08.720680 Total UI for P1: 0, mck2ui 16
4221 05:56:08.726371 best dqsien dly found for B1: ( 0, 13, 14)
4222 05:56:08.730275 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4223 05:56:08.733144 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4224 05:56:08.733566
4225 05:56:08.736802 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4226 05:56:08.740172 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4227 05:56:08.743436 [Gating] SW calibration Done
4228 05:56:08.744003 ==
4229 05:56:08.746796 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 05:56:08.749961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 05:56:08.750637 ==
4232 05:56:08.753244 RX Vref Scan: 0
4233 05:56:08.753801
4234 05:56:08.756410 RX Vref 0 -> 0, step: 1
4235 05:56:08.756914
4236 05:56:08.757326 RX Delay -230 -> 252, step: 16
4237 05:56:08.763442 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4238 05:56:08.766383 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4239 05:56:08.770104 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4240 05:56:08.772970 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4241 05:56:08.780214 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4242 05:56:08.783136 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4243 05:56:08.786620 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4244 05:56:08.790085 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4245 05:56:08.792781 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4246 05:56:08.799608 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4247 05:56:08.803075 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4248 05:56:08.806622 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4249 05:56:08.809515 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4250 05:56:08.816781 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4251 05:56:08.819376 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4252 05:56:08.822910 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4253 05:56:08.823338 ==
4254 05:56:08.826277 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 05:56:08.829906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 05:56:08.832829 ==
4257 05:56:08.833251 DQS Delay:
4258 05:56:08.833713 DQS0 = 0, DQS1 = 0
4259 05:56:08.836362 DQM Delay:
4260 05:56:08.836902 DQM0 = 51, DQM1 = 44
4261 05:56:08.839930 DQ Delay:
4262 05:56:08.840419 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4263 05:56:08.842883 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4264 05:56:08.846134 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4265 05:56:08.849422 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4266 05:56:08.850034
4267 05:56:08.853018
4268 05:56:08.853542 ==
4269 05:56:08.855745 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 05:56:08.859571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 05:56:08.859990 ==
4272 05:56:08.860367
4273 05:56:08.860923
4274 05:56:08.863222 TX Vref Scan disable
4275 05:56:08.863640 == TX Byte 0 ==
4276 05:56:08.870082 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4277 05:56:08.872979 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4278 05:56:08.873422 == TX Byte 1 ==
4279 05:56:08.879327 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4280 05:56:08.882940 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4281 05:56:08.883444 ==
4282 05:56:08.886492 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 05:56:08.889343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 05:56:08.889762 ==
4285 05:56:08.890335
4286 05:56:08.890890
4287 05:56:08.892674 TX Vref Scan disable
4288 05:56:08.895685 == TX Byte 0 ==
4289 05:56:08.899377 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4290 05:56:08.902629 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4291 05:56:08.905821 == TX Byte 1 ==
4292 05:56:08.909113 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4293 05:56:08.912319 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4294 05:56:08.912734
4295 05:56:08.915924 [DATLAT]
4296 05:56:08.916383 Freq=600, CH0 RK1
4297 05:56:08.916724
4298 05:56:08.919414 DATLAT Default: 0x9
4299 05:56:08.919831 0, 0xFFFF, sum = 0
4300 05:56:08.922753 1, 0xFFFF, sum = 0
4301 05:56:08.923176 2, 0xFFFF, sum = 0
4302 05:56:08.925701 3, 0xFFFF, sum = 0
4303 05:56:08.926270 4, 0xFFFF, sum = 0
4304 05:56:08.929267 5, 0xFFFF, sum = 0
4305 05:56:08.929703 6, 0xFFFF, sum = 0
4306 05:56:08.932395 7, 0xFFFF, sum = 0
4307 05:56:08.932827 8, 0x0, sum = 1
4308 05:56:08.935876 9, 0x0, sum = 2
4309 05:56:08.936364 10, 0x0, sum = 3
4310 05:56:08.939499 11, 0x0, sum = 4
4311 05:56:08.939927 best_step = 9
4312 05:56:08.940264
4313 05:56:08.940636 ==
4314 05:56:08.942246 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 05:56:08.949368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 05:56:08.949793 ==
4317 05:56:08.950131 RX Vref Scan: 0
4318 05:56:08.950447
4319 05:56:08.952253 RX Vref 0 -> 0, step: 1
4320 05:56:08.952709
4321 05:56:08.955765 RX Delay -163 -> 252, step: 8
4322 05:56:08.959057 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4323 05:56:08.962474 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4324 05:56:08.969176 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4325 05:56:08.972261 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4326 05:56:08.975846 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4327 05:56:08.979446 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4328 05:56:08.982128 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4329 05:56:08.989011 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4330 05:56:08.992370 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4331 05:56:08.995545 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4332 05:56:08.998729 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4333 05:56:09.005789 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4334 05:56:09.008542 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4335 05:56:09.012255 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4336 05:56:09.015117 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4337 05:56:09.018584 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4338 05:56:09.019210 ==
4339 05:56:09.021780 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 05:56:09.028867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 05:56:09.029284 ==
4342 05:56:09.029613 DQS Delay:
4343 05:56:09.031676 DQS0 = 0, DQS1 = 0
4344 05:56:09.032089 DQM Delay:
4345 05:56:09.035151 DQM0 = 53, DQM1 = 46
4346 05:56:09.035668 DQ Delay:
4347 05:56:09.038484 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4348 05:56:09.041735 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =56
4349 05:56:09.045125 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4350 05:56:09.048625 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4351 05:56:09.049043
4352 05:56:09.049359
4353 05:56:09.054977 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f1f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
4354 05:56:09.058458 CH0 RK1: MR19=808, MR18=5F1F
4355 05:56:09.064913 CH0_RK1: MR19=0x808, MR18=0x5F1F, DQSOSC=391, MR23=63, INC=171, DEC=114
4356 05:56:09.068251 [RxdqsGatingPostProcess] freq 600
4357 05:56:09.075293 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4358 05:56:09.075751 Pre-setting of DQS Precalculation
4359 05:56:09.082148 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4360 05:56:09.082601 ==
4361 05:56:09.085193 Dram Type= 6, Freq= 0, CH_1, rank 0
4362 05:56:09.088874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 05:56:09.089432 ==
4364 05:56:09.094805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4365 05:56:09.102034 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4366 05:56:09.105175 [CA 0] Center 35 (5~66) winsize 62
4367 05:56:09.108269 [CA 1] Center 36 (5~67) winsize 63
4368 05:56:09.111313 [CA 2] Center 35 (4~66) winsize 63
4369 05:56:09.114919 [CA 3] Center 34 (4~65) winsize 62
4370 05:56:09.117991 [CA 4] Center 34 (4~65) winsize 62
4371 05:56:09.121639 [CA 5] Center 34 (3~65) winsize 63
4372 05:56:09.122176
4373 05:56:09.125215 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4374 05:56:09.125639
4375 05:56:09.128483 [CATrainingPosCal] consider 1 rank data
4376 05:56:09.131697 u2DelayCellTimex100 = 270/100 ps
4377 05:56:09.135036 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4378 05:56:09.138308 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4379 05:56:09.141571 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4380 05:56:09.145033 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4381 05:56:09.148202 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4382 05:56:09.151440 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4383 05:56:09.151858
4384 05:56:09.157851 CA PerBit enable=1, Macro0, CA PI delay=34
4385 05:56:09.158285
4386 05:56:09.158694 [CBTSetCACLKResult] CA Dly = 34
4387 05:56:09.161484 CS Dly: 5 (0~36)
4388 05:56:09.161899 ==
4389 05:56:09.165106 Dram Type= 6, Freq= 0, CH_1, rank 1
4390 05:56:09.167903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 05:56:09.168465 ==
4392 05:56:09.174519 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4393 05:56:09.181445 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4394 05:56:09.184345 [CA 0] Center 36 (5~67) winsize 63
4395 05:56:09.188102 [CA 1] Center 36 (5~67) winsize 63
4396 05:56:09.191237 [CA 2] Center 35 (4~66) winsize 63
4397 05:56:09.194670 [CA 3] Center 34 (3~65) winsize 63
4398 05:56:09.197721 [CA 4] Center 34 (4~65) winsize 62
4399 05:56:09.201251 [CA 5] Center 34 (3~65) winsize 63
4400 05:56:09.201408
4401 05:56:09.204185 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4402 05:56:09.204365
4403 05:56:09.207716 [CATrainingPosCal] consider 2 rank data
4404 05:56:09.211200 u2DelayCellTimex100 = 270/100 ps
4405 05:56:09.214695 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4406 05:56:09.217659 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4407 05:56:09.221111 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4408 05:56:09.224483 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4409 05:56:09.227897 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4410 05:56:09.231167 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4411 05:56:09.231465
4412 05:56:09.237736 CA PerBit enable=1, Macro0, CA PI delay=34
4413 05:56:09.238131
4414 05:56:09.241403 [CBTSetCACLKResult] CA Dly = 34
4415 05:56:09.241834 CS Dly: 6 (0~38)
4416 05:56:09.242238
4417 05:56:09.244420 ----->DramcWriteLeveling(PI) begin...
4418 05:56:09.244856 ==
4419 05:56:09.247469 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 05:56:09.250758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 05:56:09.251186 ==
4422 05:56:09.254490 Write leveling (Byte 0): 28 => 28
4423 05:56:09.258095 Write leveling (Byte 1): 33 => 33
4424 05:56:09.261175 DramcWriteLeveling(PI) end<-----
4425 05:56:09.261599
4426 05:56:09.261934 ==
4427 05:56:09.264588 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 05:56:09.270719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 05:56:09.271149 ==
4430 05:56:09.271488 [Gating] SW mode calibration
4431 05:56:09.281372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4432 05:56:09.283986 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4433 05:56:09.287548 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4434 05:56:09.294124 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 05:56:09.297687 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4436 05:56:09.300515 0 9 12 | B1->B0 | 3030 2e2e | 1 1 | (1 0) (1 0)
4437 05:56:09.307463 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 05:56:09.310830 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 05:56:09.314037 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 05:56:09.320885 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 05:56:09.324204 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 05:56:09.327659 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 05:56:09.334119 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 05:56:09.337490 0 10 12 | B1->B0 | 3232 3a3a | 0 0 | (0 0) (0 0)
4445 05:56:09.340585 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 05:56:09.347274 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 05:56:09.350651 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 05:56:09.354066 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 05:56:09.361086 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 05:56:09.364009 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 05:56:09.367267 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 05:56:09.374311 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4453 05:56:09.377272 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 05:56:09.380277 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 05:56:09.387126 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 05:56:09.390514 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 05:56:09.393347 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 05:56:09.400336 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 05:56:09.403227 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 05:56:09.406781 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 05:56:09.413120 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 05:56:09.416682 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 05:56:09.420194 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 05:56:09.426594 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 05:56:09.430368 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 05:56:09.433709 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 05:56:09.436769 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 05:56:09.443936 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4469 05:56:09.446649 Total UI for P1: 0, mck2ui 16
4470 05:56:09.450191 best dqsien dly found for B1: ( 0, 13, 10)
4471 05:56:09.453914 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 05:56:09.456400 Total UI for P1: 0, mck2ui 16
4473 05:56:09.459926 best dqsien dly found for B0: ( 0, 13, 12)
4474 05:56:09.463747 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4475 05:56:09.466847 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4476 05:56:09.467279
4477 05:56:09.470637 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4478 05:56:09.473415 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4479 05:56:09.477248 [Gating] SW calibration Done
4480 05:56:09.477678 ==
4481 05:56:09.480771 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 05:56:09.487087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 05:56:09.487509 ==
4484 05:56:09.487852 RX Vref Scan: 0
4485 05:56:09.488220
4486 05:56:09.490043 RX Vref 0 -> 0, step: 1
4487 05:56:09.490458
4488 05:56:09.493650 RX Delay -230 -> 252, step: 16
4489 05:56:09.496590 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4490 05:56:09.500406 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4491 05:56:09.503875 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4492 05:56:09.510282 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4493 05:56:09.513983 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4494 05:56:09.516667 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4495 05:56:09.520186 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4496 05:56:09.523505 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4497 05:56:09.529885 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4498 05:56:09.533396 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4499 05:56:09.536738 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4500 05:56:09.540377 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4501 05:56:09.546265 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4502 05:56:09.549870 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4503 05:56:09.553119 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4504 05:56:09.556799 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4505 05:56:09.556929 ==
4506 05:56:09.559715 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 05:56:09.566277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 05:56:09.566414 ==
4509 05:56:09.566522 DQS Delay:
4510 05:56:09.570114 DQS0 = 0, DQS1 = 0
4511 05:56:09.570328 DQM Delay:
4512 05:56:09.570448 DQM0 = 49, DQM1 = 46
4513 05:56:09.573318 DQ Delay:
4514 05:56:09.576786 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =49
4515 05:56:09.579879 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4516 05:56:09.583269 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4517 05:56:09.586794 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4518 05:56:09.586957
4519 05:56:09.587090
4520 05:56:09.587200 ==
4521 05:56:09.590098 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 05:56:09.593355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 05:56:09.593525 ==
4524 05:56:09.593687
4525 05:56:09.593819
4526 05:56:09.596141 TX Vref Scan disable
4527 05:56:09.599767 == TX Byte 0 ==
4528 05:56:09.603151 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4529 05:56:09.606391 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4530 05:56:09.610160 == TX Byte 1 ==
4531 05:56:09.613247 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4532 05:56:09.616907 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4533 05:56:09.617401 ==
4534 05:56:09.619592 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 05:56:09.623212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 05:56:09.626623 ==
4537 05:56:09.627207
4538 05:56:09.627565
4539 05:56:09.627885 TX Vref Scan disable
4540 05:56:09.630375 == TX Byte 0 ==
4541 05:56:09.633886 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4542 05:56:09.640263 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4543 05:56:09.640751 == TX Byte 1 ==
4544 05:56:09.643532 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4545 05:56:09.650654 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4546 05:56:09.651082
4547 05:56:09.651509 [DATLAT]
4548 05:56:09.651903 Freq=600, CH1 RK0
4549 05:56:09.652221
4550 05:56:09.653411 DATLAT Default: 0x9
4551 05:56:09.653833 0, 0xFFFF, sum = 0
4552 05:56:09.657042 1, 0xFFFF, sum = 0
4553 05:56:09.657470 2, 0xFFFF, sum = 0
4554 05:56:09.660498 3, 0xFFFF, sum = 0
4555 05:56:09.663351 4, 0xFFFF, sum = 0
4556 05:56:09.663814 5, 0xFFFF, sum = 0
4557 05:56:09.666874 6, 0xFFFF, sum = 0
4558 05:56:09.667309 7, 0xFFFF, sum = 0
4559 05:56:09.670670 8, 0x0, sum = 1
4560 05:56:09.671195 9, 0x0, sum = 2
4561 05:56:09.671546 10, 0x0, sum = 3
4562 05:56:09.673603 11, 0x0, sum = 4
4563 05:56:09.674084 best_step = 9
4564 05:56:09.674472
4565 05:56:09.674792 ==
4566 05:56:09.676830 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 05:56:09.683493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 05:56:09.683944 ==
4569 05:56:09.684492 RX Vref Scan: 1
4570 05:56:09.684888
4571 05:56:09.686665 RX Vref 0 -> 0, step: 1
4572 05:56:09.687127
4573 05:56:09.690004 RX Delay -163 -> 252, step: 8
4574 05:56:09.690553
4575 05:56:09.693591 Set Vref, RX VrefLevel [Byte0]: 53
4576 05:56:09.696745 [Byte1]: 53
4577 05:56:09.697244
4578 05:56:09.699908 Final RX Vref Byte 0 = 53 to rank0
4579 05:56:09.703557 Final RX Vref Byte 1 = 53 to rank0
4580 05:56:09.706492 Final RX Vref Byte 0 = 53 to rank1
4581 05:56:09.710040 Final RX Vref Byte 1 = 53 to rank1==
4582 05:56:09.713441 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 05:56:09.717058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 05:56:09.717498 ==
4585 05:56:09.720282 DQS Delay:
4586 05:56:09.720769 DQS0 = 0, DQS1 = 0
4587 05:56:09.721203 DQM Delay:
4588 05:56:09.723509 DQM0 = 48, DQM1 = 45
4589 05:56:09.723942 DQ Delay:
4590 05:56:09.727106 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4591 05:56:09.730213 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4592 05:56:09.733720 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4593 05:56:09.736564 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4594 05:56:09.736993
4595 05:56:09.737428
4596 05:56:09.747045 [DQSOSCAuto] RK0, (LSB)MR18= 0x496f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4597 05:56:09.750071 CH1 RK0: MR19=808, MR18=496F
4598 05:56:09.753235 CH1_RK0: MR19=0x808, MR18=0x496F, DQSOSC=389, MR23=63, INC=173, DEC=115
4599 05:56:09.753672
4600 05:56:09.757024 ----->DramcWriteLeveling(PI) begin...
4601 05:56:09.759882 ==
4602 05:56:09.763266 Dram Type= 6, Freq= 0, CH_1, rank 1
4603 05:56:09.766799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 05:56:09.767453 ==
4605 05:56:09.770097 Write leveling (Byte 0): 30 => 30
4606 05:56:09.773235 Write leveling (Byte 1): 31 => 31
4607 05:56:09.776757 DramcWriteLeveling(PI) end<-----
4608 05:56:09.777185
4609 05:56:09.777521 ==
4610 05:56:09.779660 Dram Type= 6, Freq= 0, CH_1, rank 1
4611 05:56:09.783017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 05:56:09.783448 ==
4613 05:56:09.786428 [Gating] SW mode calibration
4614 05:56:09.792677 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4615 05:56:09.799870 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4616 05:56:09.802981 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4617 05:56:09.806112 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4618 05:56:09.809526 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4619 05:56:09.816212 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 1)
4620 05:56:09.819906 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 05:56:09.822941 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 05:56:09.829279 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 05:56:09.832973 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 05:56:09.836179 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 05:56:09.843249 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 05:56:09.846283 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 05:56:09.849838 0 10 12 | B1->B0 | 3434 3232 | 1 0 | (0 0) (0 0)
4628 05:56:09.856273 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 05:56:09.859421 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 05:56:09.863042 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 05:56:09.869481 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 05:56:09.872913 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 05:56:09.876401 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 05:56:09.882932 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4635 05:56:09.886417 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 05:56:09.890399 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4637 05:56:09.896251 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 05:56:09.899941 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 05:56:09.902782 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 05:56:09.909642 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 05:56:09.913019 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 05:56:09.916318 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 05:56:09.922761 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 05:56:09.926149 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 05:56:09.929514 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 05:56:09.936057 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 05:56:09.939166 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 05:56:09.943015 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 05:56:09.946231 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 05:56:09.952728 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 05:56:09.956218 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4652 05:56:09.959846 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 05:56:09.963120 Total UI for P1: 0, mck2ui 16
4654 05:56:09.966183 best dqsien dly found for B0: ( 0, 13, 14)
4655 05:56:09.969597 Total UI for P1: 0, mck2ui 16
4656 05:56:09.972816 best dqsien dly found for B1: ( 0, 13, 12)
4657 05:56:09.975944 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4658 05:56:09.982989 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4659 05:56:09.983509
4660 05:56:09.985459 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4661 05:56:09.988948 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4662 05:56:09.992379 [Gating] SW calibration Done
4663 05:56:09.992830 ==
4664 05:56:09.995848 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 05:56:09.999655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 05:56:10.000377 ==
4667 05:56:10.002319 RX Vref Scan: 0
4668 05:56:10.002837
4669 05:56:10.003173 RX Vref 0 -> 0, step: 1
4670 05:56:10.003485
4671 05:56:10.005936 RX Delay -230 -> 252, step: 16
4672 05:56:10.008780 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4673 05:56:10.015872 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4674 05:56:10.019338 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4675 05:56:10.022807 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4676 05:56:10.025523 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4677 05:56:10.028814 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4678 05:56:10.035824 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4679 05:56:10.039250 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4680 05:56:10.042572 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4681 05:56:10.046058 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4682 05:56:10.051990 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4683 05:56:10.055364 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4684 05:56:10.059330 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4685 05:56:10.062096 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4686 05:56:10.065951 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4687 05:56:10.072370 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4688 05:56:10.072806 ==
4689 05:56:10.075726 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 05:56:10.078865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 05:56:10.079435 ==
4692 05:56:10.079954 DQS Delay:
4693 05:56:10.082679 DQS0 = 0, DQS1 = 0
4694 05:56:10.083111 DQM Delay:
4695 05:56:10.085649 DQM0 = 49, DQM1 = 48
4696 05:56:10.086019 DQ Delay:
4697 05:56:10.088959 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4698 05:56:10.092122 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4699 05:56:10.095304 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4700 05:56:10.098686 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4701 05:56:10.098948
4702 05:56:10.099180
4703 05:56:10.099347 ==
4704 05:56:10.102100 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 05:56:10.105007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 05:56:10.108508 ==
4707 05:56:10.108692
4708 05:56:10.108829
4709 05:56:10.108977 TX Vref Scan disable
4710 05:56:10.112111 == TX Byte 0 ==
4711 05:56:10.114899 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4712 05:56:10.118541 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4713 05:56:10.122077 == TX Byte 1 ==
4714 05:56:10.124897 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4715 05:56:10.128483 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4716 05:56:10.132025 ==
4717 05:56:10.132129 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 05:56:10.138385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 05:56:10.138562 ==
4720 05:56:10.138631
4721 05:56:10.138693
4722 05:56:10.141667 TX Vref Scan disable
4723 05:56:10.141754 == TX Byte 0 ==
4724 05:56:10.148037 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4725 05:56:10.151115 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4726 05:56:10.151238 == TX Byte 1 ==
4727 05:56:10.158408 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4728 05:56:10.161085 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4729 05:56:10.161167
4730 05:56:10.161233 [DATLAT]
4731 05:56:10.164416 Freq=600, CH1 RK1
4732 05:56:10.164498
4733 05:56:10.164563 DATLAT Default: 0x9
4734 05:56:10.167826 0, 0xFFFF, sum = 0
4735 05:56:10.167909 1, 0xFFFF, sum = 0
4736 05:56:10.171270 2, 0xFFFF, sum = 0
4737 05:56:10.174785 3, 0xFFFF, sum = 0
4738 05:56:10.174868 4, 0xFFFF, sum = 0
4739 05:56:10.178186 5, 0xFFFF, sum = 0
4740 05:56:10.178268 6, 0xFFFF, sum = 0
4741 05:56:10.181555 7, 0xFFFF, sum = 0
4742 05:56:10.181684 8, 0x0, sum = 1
4743 05:56:10.181756 9, 0x0, sum = 2
4744 05:56:10.184585 10, 0x0, sum = 3
4745 05:56:10.184745 11, 0x0, sum = 4
4746 05:56:10.187873 best_step = 9
4747 05:56:10.187974
4748 05:56:10.188070 ==
4749 05:56:10.191415 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 05:56:10.194307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 05:56:10.194412 ==
4752 05:56:10.197563 RX Vref Scan: 0
4753 05:56:10.197667
4754 05:56:10.197762 RX Vref 0 -> 0, step: 1
4755 05:56:10.197854
4756 05:56:10.200947 RX Delay -163 -> 252, step: 8
4757 05:56:10.208452 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4758 05:56:10.211755 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4759 05:56:10.215287 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4760 05:56:10.218085 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4761 05:56:10.225078 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4762 05:56:10.228601 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4763 05:56:10.231521 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4764 05:56:10.235012 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4765 05:56:10.238565 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4766 05:56:10.242090 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4767 05:56:10.248543 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4768 05:56:10.251988 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4769 05:56:10.255297 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4770 05:56:10.259173 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4771 05:56:10.265420 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4772 05:56:10.268383 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4773 05:56:10.268463 ==
4774 05:56:10.271985 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 05:56:10.275190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 05:56:10.275301 ==
4777 05:56:10.275367 DQS Delay:
4778 05:56:10.278443 DQS0 = 0, DQS1 = 0
4779 05:56:10.278517 DQM Delay:
4780 05:56:10.281863 DQM0 = 49, DQM1 = 46
4781 05:56:10.281951 DQ Delay:
4782 05:56:10.285412 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4783 05:56:10.288141 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4784 05:56:10.291586 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4785 05:56:10.294901 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4786 05:56:10.295015
4787 05:56:10.295086
4788 05:56:10.304914 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4789 05:56:10.305059 CH1 RK1: MR19=808, MR18=6A22
4790 05:56:10.311994 CH1_RK1: MR19=0x808, MR18=0x6A22, DQSOSC=389, MR23=63, INC=173, DEC=115
4791 05:56:10.315332 [RxdqsGatingPostProcess] freq 600
4792 05:56:10.321555 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4793 05:56:10.324757 Pre-setting of DQS Precalculation
4794 05:56:10.328065 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4795 05:56:10.335027 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4796 05:56:10.345142 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4797 05:56:10.345299
4798 05:56:10.345396
4799 05:56:10.345478 [Calibration Summary] 1200 Mbps
4800 05:56:10.347966 CH 0, Rank 0
4801 05:56:10.351539 SW Impedance : PASS
4802 05:56:10.351624 DUTY Scan : NO K
4803 05:56:10.354945 ZQ Calibration : PASS
4804 05:56:10.355054 Jitter Meter : NO K
4805 05:56:10.357740 CBT Training : PASS
4806 05:56:10.361304 Write leveling : PASS
4807 05:56:10.361390 RX DQS gating : PASS
4808 05:56:10.364822 RX DQ/DQS(RDDQC) : PASS
4809 05:56:10.368225 TX DQ/DQS : PASS
4810 05:56:10.368353 RX DATLAT : PASS
4811 05:56:10.371093 RX DQ/DQS(Engine): PASS
4812 05:56:10.374563 TX OE : NO K
4813 05:56:10.374648 All Pass.
4814 05:56:10.374734
4815 05:56:10.374814 CH 0, Rank 1
4816 05:56:10.377740 SW Impedance : PASS
4817 05:56:10.380969 DUTY Scan : NO K
4818 05:56:10.381089 ZQ Calibration : PASS
4819 05:56:10.384825 Jitter Meter : NO K
4820 05:56:10.387824 CBT Training : PASS
4821 05:56:10.387936 Write leveling : PASS
4822 05:56:10.391002 RX DQS gating : PASS
4823 05:56:10.394103 RX DQ/DQS(RDDQC) : PASS
4824 05:56:10.394251 TX DQ/DQS : PASS
4825 05:56:10.398005 RX DATLAT : PASS
4826 05:56:10.400809 RX DQ/DQS(Engine): PASS
4827 05:56:10.400931 TX OE : NO K
4828 05:56:10.401053 All Pass.
4829 05:56:10.404227
4830 05:56:10.404368 CH 1, Rank 0
4831 05:56:10.407637 SW Impedance : PASS
4832 05:56:10.407737 DUTY Scan : NO K
4833 05:56:10.410806 ZQ Calibration : PASS
4834 05:56:10.410914 Jitter Meter : NO K
4835 05:56:10.414566 CBT Training : PASS
4836 05:56:10.417832 Write leveling : PASS
4837 05:56:10.417950 RX DQS gating : PASS
4838 05:56:10.421368 RX DQ/DQS(RDDQC) : PASS
4839 05:56:10.424050 TX DQ/DQS : PASS
4840 05:56:10.424169 RX DATLAT : PASS
4841 05:56:10.427763 RX DQ/DQS(Engine): PASS
4842 05:56:10.431306 TX OE : NO K
4843 05:56:10.431403 All Pass.
4844 05:56:10.431496
4845 05:56:10.431596 CH 1, Rank 1
4846 05:56:10.434611 SW Impedance : PASS
4847 05:56:10.437735 DUTY Scan : NO K
4848 05:56:10.437851 ZQ Calibration : PASS
4849 05:56:10.441055 Jitter Meter : NO K
4850 05:56:10.444502 CBT Training : PASS
4851 05:56:10.444603 Write leveling : PASS
4852 05:56:10.447909 RX DQS gating : PASS
4853 05:56:10.448009 RX DQ/DQS(RDDQC) : PASS
4854 05:56:10.451467 TX DQ/DQS : PASS
4855 05:56:10.454320 RX DATLAT : PASS
4856 05:56:10.454426 RX DQ/DQS(Engine): PASS
4857 05:56:10.457844 TX OE : NO K
4858 05:56:10.457963 All Pass.
4859 05:56:10.458064
4860 05:56:10.461104 DramC Write-DBI off
4861 05:56:10.464838 PER_BANK_REFRESH: Hybrid Mode
4862 05:56:10.464965 TX_TRACKING: ON
4863 05:56:10.474656 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4864 05:56:10.477532 [FAST_K] Save calibration result to emmc
4865 05:56:10.481040 dramc_set_vcore_voltage set vcore to 662500
4866 05:56:10.484388 Read voltage for 933, 3
4867 05:56:10.484520 Vio18 = 0
4868 05:56:10.484592 Vcore = 662500
4869 05:56:10.487784 Vdram = 0
4870 05:56:10.487887 Vddq = 0
4871 05:56:10.487959 Vmddr = 0
4872 05:56:10.494107 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4873 05:56:10.497480 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4874 05:56:10.500817 MEM_TYPE=3, freq_sel=17
4875 05:56:10.503949 sv_algorithm_assistance_LP4_1600
4876 05:56:10.507194 ============ PULL DRAM RESETB DOWN ============
4877 05:56:10.513800 ========== PULL DRAM RESETB DOWN end =========
4878 05:56:10.517203 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4879 05:56:10.520634 ===================================
4880 05:56:10.523836 LPDDR4 DRAM CONFIGURATION
4881 05:56:10.527053 ===================================
4882 05:56:10.527217 EX_ROW_EN[0] = 0x0
4883 05:56:10.530836 EX_ROW_EN[1] = 0x0
4884 05:56:10.530942 LP4Y_EN = 0x0
4885 05:56:10.534111 WORK_FSP = 0x0
4886 05:56:10.534218 WL = 0x3
4887 05:56:10.537555 RL = 0x3
4888 05:56:10.537662 BL = 0x2
4889 05:56:10.540437 RPST = 0x0
4890 05:56:10.540539 RD_PRE = 0x0
4891 05:56:10.543903 WR_PRE = 0x1
4892 05:56:10.544021 WR_PST = 0x0
4893 05:56:10.547222 DBI_WR = 0x0
4894 05:56:10.550453 DBI_RD = 0x0
4895 05:56:10.550557 OTF = 0x1
4896 05:56:10.553709 ===================================
4897 05:56:10.557208 ===================================
4898 05:56:10.557320 ANA top config
4899 05:56:10.560826 ===================================
4900 05:56:10.564147 DLL_ASYNC_EN = 0
4901 05:56:10.566863 ALL_SLAVE_EN = 1
4902 05:56:10.570523 NEW_RANK_MODE = 1
4903 05:56:10.574087 DLL_IDLE_MODE = 1
4904 05:56:10.574176 LP45_APHY_COMB_EN = 1
4905 05:56:10.577653 TX_ODT_DIS = 1
4906 05:56:10.580574 NEW_8X_MODE = 1
4907 05:56:10.584056 ===================================
4908 05:56:10.587389 ===================================
4909 05:56:10.590774 data_rate = 1866
4910 05:56:10.594195 CKR = 1
4911 05:56:10.594363 DQ_P2S_RATIO = 8
4912 05:56:10.597072 ===================================
4913 05:56:10.600765 CA_P2S_RATIO = 8
4914 05:56:10.603970 DQ_CA_OPEN = 0
4915 05:56:10.607473 DQ_SEMI_OPEN = 0
4916 05:56:10.610292 CA_SEMI_OPEN = 0
4917 05:56:10.613805 CA_FULL_RATE = 0
4918 05:56:10.613886 DQ_CKDIV4_EN = 1
4919 05:56:10.617123 CA_CKDIV4_EN = 1
4920 05:56:10.620343 CA_PREDIV_EN = 0
4921 05:56:10.623462 PH8_DLY = 0
4922 05:56:10.627084 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4923 05:56:10.630503 DQ_AAMCK_DIV = 4
4924 05:56:10.630588 CA_AAMCK_DIV = 4
4925 05:56:10.633335 CA_ADMCK_DIV = 4
4926 05:56:10.636766 DQ_TRACK_CA_EN = 0
4927 05:56:10.640669 CA_PICK = 933
4928 05:56:10.643531 CA_MCKIO = 933
4929 05:56:10.647063 MCKIO_SEMI = 0
4930 05:56:10.647146 PLL_FREQ = 3732
4931 05:56:10.650097 DQ_UI_PI_RATIO = 32
4932 05:56:10.653995 CA_UI_PI_RATIO = 0
4933 05:56:10.656847 ===================================
4934 05:56:10.660101 ===================================
4935 05:56:10.664201 memory_type:LPDDR4
4936 05:56:10.664291 GP_NUM : 10
4937 05:56:10.666804 SRAM_EN : 1
4938 05:56:10.670364 MD32_EN : 0
4939 05:56:10.673756 ===================================
4940 05:56:10.673840 [ANA_INIT] >>>>>>>>>>>>>>
4941 05:56:10.676751 <<<<<< [CONFIGURE PHASE]: ANA_TX
4942 05:56:10.680281 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4943 05:56:10.683188 ===================================
4944 05:56:10.686734 data_rate = 1866,PCW = 0X8f00
4945 05:56:10.690312 ===================================
4946 05:56:10.693011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4947 05:56:10.699907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4948 05:56:10.706329 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4949 05:56:10.709780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4950 05:56:10.713143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4951 05:56:10.716654 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4952 05:56:10.720139 [ANA_INIT] flow start
4953 05:56:10.720223 [ANA_INIT] PLL >>>>>>>>
4954 05:56:10.722975 [ANA_INIT] PLL <<<<<<<<
4955 05:56:10.726441 [ANA_INIT] MIDPI >>>>>>>>
4956 05:56:10.726524 [ANA_INIT] MIDPI <<<<<<<<
4957 05:56:10.730054 [ANA_INIT] DLL >>>>>>>>
4958 05:56:10.733317 [ANA_INIT] flow end
4959 05:56:10.736668 ============ LP4 DIFF to SE enter ============
4960 05:56:10.740164 ============ LP4 DIFF to SE exit ============
4961 05:56:10.743615 [ANA_INIT] <<<<<<<<<<<<<
4962 05:56:10.746427 [Flow] Enable top DCM control >>>>>
4963 05:56:10.749999 [Flow] Enable top DCM control <<<<<
4964 05:56:10.753420 Enable DLL master slave shuffle
4965 05:56:10.756728 ==============================================================
4966 05:56:10.759930 Gating Mode config
4967 05:56:10.766788 ==============================================================
4968 05:56:10.766877 Config description:
4969 05:56:10.776265 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4970 05:56:10.782908 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4971 05:56:10.786770 SELPH_MODE 0: By rank 1: By Phase
4972 05:56:10.793028 ==============================================================
4973 05:56:10.796694 GAT_TRACK_EN = 1
4974 05:56:10.799491 RX_GATING_MODE = 2
4975 05:56:10.803030 RX_GATING_TRACK_MODE = 2
4976 05:56:10.806511 SELPH_MODE = 1
4977 05:56:10.809921 PICG_EARLY_EN = 1
4978 05:56:10.813327 VALID_LAT_VALUE = 1
4979 05:56:10.816118 ==============================================================
4980 05:56:10.819433 Enter into Gating configuration >>>>
4981 05:56:10.823020 Exit from Gating configuration <<<<
4982 05:56:10.826494 Enter into DVFS_PRE_config >>>>>
4983 05:56:10.836501 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4984 05:56:10.839341 Exit from DVFS_PRE_config <<<<<
4985 05:56:10.843366 Enter into PICG configuration >>>>
4986 05:56:10.846078 Exit from PICG configuration <<<<
4987 05:56:10.849333 [RX_INPUT] configuration >>>>>
4988 05:56:10.853189 [RX_INPUT] configuration <<<<<
4989 05:56:10.859804 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4990 05:56:10.863247 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4991 05:56:10.869625 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4992 05:56:10.876263 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4993 05:56:10.883070 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4994 05:56:10.889761 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4995 05:56:10.893163 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4996 05:56:10.896570 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4997 05:56:10.899585 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4998 05:56:10.906230 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4999 05:56:10.909673 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5000 05:56:10.912868 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 05:56:10.916252 ===================================
5002 05:56:10.919761 LPDDR4 DRAM CONFIGURATION
5003 05:56:10.922495 ===================================
5004 05:56:10.922578 EX_ROW_EN[0] = 0x0
5005 05:56:10.925889 EX_ROW_EN[1] = 0x0
5006 05:56:10.925972 LP4Y_EN = 0x0
5007 05:56:10.929149 WORK_FSP = 0x0
5008 05:56:10.932726 WL = 0x3
5009 05:56:10.932810 RL = 0x3
5010 05:56:10.936255 BL = 0x2
5011 05:56:10.936375 RPST = 0x0
5012 05:56:10.939852 RD_PRE = 0x0
5013 05:56:10.939934 WR_PRE = 0x1
5014 05:56:10.942689 WR_PST = 0x0
5015 05:56:10.942771 DBI_WR = 0x0
5016 05:56:10.946165 DBI_RD = 0x0
5017 05:56:10.946247 OTF = 0x1
5018 05:56:10.949766 ===================================
5019 05:56:10.952473 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5020 05:56:10.959339 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5021 05:56:10.962744 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5022 05:56:10.966005 ===================================
5023 05:56:10.969655 LPDDR4 DRAM CONFIGURATION
5024 05:56:10.972830 ===================================
5025 05:56:10.972917 EX_ROW_EN[0] = 0x10
5026 05:56:10.975663 EX_ROW_EN[1] = 0x0
5027 05:56:10.975759 LP4Y_EN = 0x0
5028 05:56:10.979074 WORK_FSP = 0x0
5029 05:56:10.979204 WL = 0x3
5030 05:56:10.982548 RL = 0x3
5031 05:56:10.982629 BL = 0x2
5032 05:56:10.985854 RPST = 0x0
5033 05:56:10.989079 RD_PRE = 0x0
5034 05:56:10.989255 WR_PRE = 0x1
5035 05:56:10.992735 WR_PST = 0x0
5036 05:56:10.992870 DBI_WR = 0x0
5037 05:56:10.995520 DBI_RD = 0x0
5038 05:56:10.995611 OTF = 0x1
5039 05:56:10.999016 ===================================
5040 05:56:11.005889 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5041 05:56:11.009768 nWR fixed to 30
5042 05:56:11.012971 [ModeRegInit_LP4] CH0 RK0
5043 05:56:11.013092 [ModeRegInit_LP4] CH0 RK1
5044 05:56:11.016102 [ModeRegInit_LP4] CH1 RK0
5045 05:56:11.019374 [ModeRegInit_LP4] CH1 RK1
5046 05:56:11.019470 match AC timing 9
5047 05:56:11.025863 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5048 05:56:11.029058 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5049 05:56:11.032659 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5050 05:56:11.039403 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5051 05:56:11.042758 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5052 05:56:11.042841 ==
5053 05:56:11.045567 Dram Type= 6, Freq= 0, CH_0, rank 0
5054 05:56:11.049009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5055 05:56:11.049092 ==
5056 05:56:11.055907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5057 05:56:11.062154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5058 05:56:11.065779 [CA 0] Center 37 (6~68) winsize 63
5059 05:56:11.069270 [CA 1] Center 37 (7~68) winsize 62
5060 05:56:11.072099 [CA 2] Center 34 (4~65) winsize 62
5061 05:56:11.075430 [CA 3] Center 34 (3~65) winsize 63
5062 05:56:11.078716 [CA 4] Center 33 (3~64) winsize 62
5063 05:56:11.082400 [CA 5] Center 32 (2~62) winsize 61
5064 05:56:11.082517
5065 05:56:11.085349 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5066 05:56:11.085432
5067 05:56:11.089084 [CATrainingPosCal] consider 1 rank data
5068 05:56:11.092476 u2DelayCellTimex100 = 270/100 ps
5069 05:56:11.095332 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5070 05:56:11.098732 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5071 05:56:11.102326 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5072 05:56:11.105586 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5073 05:56:11.108475 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5074 05:56:11.115637 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5075 05:56:11.115727
5076 05:56:11.118491 CA PerBit enable=1, Macro0, CA PI delay=32
5077 05:56:11.118594
5078 05:56:11.121820 [CBTSetCACLKResult] CA Dly = 32
5079 05:56:11.121904 CS Dly: 5 (0~36)
5080 05:56:11.121999 ==
5081 05:56:11.125206 Dram Type= 6, Freq= 0, CH_0, rank 1
5082 05:56:11.128452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 05:56:11.132033 ==
5084 05:56:11.135573 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5085 05:56:11.141707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5086 05:56:11.145134 [CA 0] Center 37 (6~68) winsize 63
5087 05:56:11.148342 [CA 1] Center 37 (6~68) winsize 63
5088 05:56:11.152088 [CA 2] Center 34 (4~65) winsize 62
5089 05:56:11.154968 [CA 3] Center 34 (3~65) winsize 63
5090 05:56:11.158344 [CA 4] Center 33 (3~63) winsize 61
5091 05:56:11.161818 [CA 5] Center 32 (2~63) winsize 62
5092 05:56:11.161913
5093 05:56:11.165605 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5094 05:56:11.165715
5095 05:56:11.169217 [CATrainingPosCal] consider 2 rank data
5096 05:56:11.172060 u2DelayCellTimex100 = 270/100 ps
5097 05:56:11.175620 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5098 05:56:11.178452 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5099 05:56:11.182043 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5100 05:56:11.185583 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5101 05:56:11.192444 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5102 05:56:11.195055 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5103 05:56:11.195196
5104 05:56:11.198887 CA PerBit enable=1, Macro0, CA PI delay=32
5105 05:56:11.199026
5106 05:56:11.201957 [CBTSetCACLKResult] CA Dly = 32
5107 05:56:11.202098 CS Dly: 5 (0~37)
5108 05:56:11.202227
5109 05:56:11.205151 ----->DramcWriteLeveling(PI) begin...
5110 05:56:11.205288 ==
5111 05:56:11.246410 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 05:56:11.246593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 05:56:11.246741 ==
5114 05:56:11.246935 Write leveling (Byte 0): 33 => 33
5115 05:56:11.247071 Write leveling (Byte 1): 31 => 31
5116 05:56:11.247215 DramcWriteLeveling(PI) end<-----
5117 05:56:11.247398
5118 05:56:11.247561 ==
5119 05:56:11.247693 Dram Type= 6, Freq= 0, CH_0, rank 0
5120 05:56:11.247853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 05:56:11.248009 ==
5122 05:56:11.248184 [Gating] SW mode calibration
5123 05:56:11.248366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5124 05:56:11.248515 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5125 05:56:11.251983 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
5126 05:56:11.255484 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 05:56:11.258888 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 05:56:11.265087 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 05:56:11.268308 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 05:56:11.272070 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 05:56:11.278672 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5132 05:56:11.281740 0 14 28 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 1)
5133 05:56:11.284938 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5134 05:56:11.291696 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5135 05:56:11.295129 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 05:56:11.298649 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 05:56:11.305045 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 05:56:11.308660 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 05:56:11.311363 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5140 05:56:11.315317 0 15 28 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
5141 05:56:11.321510 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5142 05:56:11.325098 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 05:56:11.328163 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 05:56:11.335095 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 05:56:11.338571 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 05:56:11.341978 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 05:56:11.348524 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5148 05:56:11.352006 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5149 05:56:11.354826 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 05:56:11.361977 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 05:56:11.364831 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 05:56:11.368439 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 05:56:11.374822 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 05:56:11.378422 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 05:56:11.381820 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 05:56:11.388318 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 05:56:11.391931 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 05:56:11.395588 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 05:56:11.402229 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 05:56:11.405222 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 05:56:11.408843 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 05:56:11.411955 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 05:56:11.418680 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 05:56:11.421511 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5165 05:56:11.425114 Total UI for P1: 0, mck2ui 16
5166 05:56:11.428415 best dqsien dly found for B0: ( 1, 2, 26)
5167 05:56:11.431184 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 05:56:11.434943 Total UI for P1: 0, mck2ui 16
5169 05:56:11.438285 best dqsien dly found for B1: ( 1, 2, 28)
5170 05:56:11.441368 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5171 05:56:11.447919 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5172 05:56:11.448057
5173 05:56:11.451411 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5174 05:56:11.454668 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5175 05:56:11.457986 [Gating] SW calibration Done
5176 05:56:11.458112 ==
5177 05:56:11.461495 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 05:56:11.464217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 05:56:11.464385 ==
5180 05:56:11.467665 RX Vref Scan: 0
5181 05:56:11.467823
5182 05:56:11.467954 RX Vref 0 -> 0, step: 1
5183 05:56:11.468080
5184 05:56:11.471096 RX Delay -80 -> 252, step: 8
5185 05:56:11.474593 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5186 05:56:11.481043 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5187 05:56:11.484462 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5188 05:56:11.487998 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5189 05:56:11.490842 iDelay=208, Bit 4, Center 111 (24 ~ 199) 176
5190 05:56:11.494278 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5191 05:56:11.497853 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5192 05:56:11.504022 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5193 05:56:11.507410 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5194 05:56:11.511451 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5195 05:56:11.514604 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5196 05:56:11.517435 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5197 05:56:11.520767 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5198 05:56:11.527276 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5199 05:56:11.530553 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5200 05:56:11.533972 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5201 05:56:11.534075 ==
5202 05:56:11.537424 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 05:56:11.540707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 05:56:11.544384 ==
5205 05:56:11.544470 DQS Delay:
5206 05:56:11.544539 DQS0 = 0, DQS1 = 0
5207 05:56:11.547133 DQM Delay:
5208 05:56:11.547217 DQM0 = 107, DQM1 = 94
5209 05:56:11.550380 DQ Delay:
5210 05:56:11.554193 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5211 05:56:11.557432 DQ4 =111, DQ5 =95, DQ6 =115, DQ7 =115
5212 05:56:11.560520 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5213 05:56:11.563825 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5214 05:56:11.563910
5215 05:56:11.563978
5216 05:56:11.564042 ==
5217 05:56:11.567052 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 05:56:11.570275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 05:56:11.570360 ==
5220 05:56:11.570427
5221 05:56:11.570488
5222 05:56:11.574166 TX Vref Scan disable
5223 05:56:11.577004 == TX Byte 0 ==
5224 05:56:11.580621 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5225 05:56:11.584185 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5226 05:56:11.587039 == TX Byte 1 ==
5227 05:56:11.590489 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5228 05:56:11.594025 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5229 05:56:11.594109 ==
5230 05:56:11.597653 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 05:56:11.600536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 05:56:11.600621 ==
5233 05:56:11.600701
5234 05:56:11.604143
5235 05:56:11.604227 TX Vref Scan disable
5236 05:56:11.607624 == TX Byte 0 ==
5237 05:56:11.610415 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5238 05:56:11.613964 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5239 05:56:11.617390 == TX Byte 1 ==
5240 05:56:11.620658 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5241 05:56:11.624004 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5242 05:56:11.624098
5243 05:56:11.627657 [DATLAT]
5244 05:56:11.627740 Freq=933, CH0 RK0
5245 05:56:11.627806
5246 05:56:11.630465 DATLAT Default: 0xd
5247 05:56:11.630565 0, 0xFFFF, sum = 0
5248 05:56:11.633923 1, 0xFFFF, sum = 0
5249 05:56:11.634008 2, 0xFFFF, sum = 0
5250 05:56:11.637451 3, 0xFFFF, sum = 0
5251 05:56:11.637536 4, 0xFFFF, sum = 0
5252 05:56:11.640929 5, 0xFFFF, sum = 0
5253 05:56:11.641013 6, 0xFFFF, sum = 0
5254 05:56:11.644280 7, 0xFFFF, sum = 0
5255 05:56:11.644401 8, 0xFFFF, sum = 0
5256 05:56:11.647576 9, 0xFFFF, sum = 0
5257 05:56:11.647673 10, 0x0, sum = 1
5258 05:56:11.650840 11, 0x0, sum = 2
5259 05:56:11.650924 12, 0x0, sum = 3
5260 05:56:11.654135 13, 0x0, sum = 4
5261 05:56:11.654221 best_step = 11
5262 05:56:11.654287
5263 05:56:11.654348 ==
5264 05:56:11.656927 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 05:56:11.663758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 05:56:11.663844 ==
5267 05:56:11.663926 RX Vref Scan: 1
5268 05:56:11.664019
5269 05:56:11.666958 RX Vref 0 -> 0, step: 1
5270 05:56:11.667096
5271 05:56:11.670388 RX Delay -53 -> 252, step: 4
5272 05:56:11.670518
5273 05:56:11.673637 Set Vref, RX VrefLevel [Byte0]: 54
5274 05:56:11.676963 [Byte1]: 55
5275 05:56:11.677047
5276 05:56:11.680179 Final RX Vref Byte 0 = 54 to rank0
5277 05:56:11.684084 Final RX Vref Byte 1 = 55 to rank0
5278 05:56:11.686989 Final RX Vref Byte 0 = 54 to rank1
5279 05:56:11.690561 Final RX Vref Byte 1 = 55 to rank1==
5280 05:56:11.693984 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 05:56:11.696850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 05:56:11.696965 ==
5283 05:56:11.700418 DQS Delay:
5284 05:56:11.700530 DQS0 = 0, DQS1 = 0
5285 05:56:11.703844 DQM Delay:
5286 05:56:11.703952 DQM0 = 104, DQM1 = 97
5287 05:56:11.704053 DQ Delay:
5288 05:56:11.706859 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5289 05:56:11.710203 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5290 05:56:11.713661 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =92
5291 05:56:11.720033 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =104
5292 05:56:11.720146
5293 05:56:11.720242
5294 05:56:11.726976 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
5295 05:56:11.730396 CH0 RK0: MR19=505, MR18=2C24
5296 05:56:11.737418 CH0_RK0: MR19=0x505, MR18=0x2C24, DQSOSC=408, MR23=63, INC=65, DEC=43
5297 05:56:11.737503
5298 05:56:11.740174 ----->DramcWriteLeveling(PI) begin...
5299 05:56:11.740261 ==
5300 05:56:11.743779 Dram Type= 6, Freq= 0, CH_0, rank 1
5301 05:56:11.746727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 05:56:11.746810 ==
5303 05:56:11.750446 Write leveling (Byte 0): 32 => 32
5304 05:56:11.753283 Write leveling (Byte 1): 31 => 31
5305 05:56:11.756713 DramcWriteLeveling(PI) end<-----
5306 05:56:11.756796
5307 05:56:11.756860 ==
5308 05:56:11.760032 Dram Type= 6, Freq= 0, CH_0, rank 1
5309 05:56:11.763477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 05:56:11.763560 ==
5311 05:56:11.766733 [Gating] SW mode calibration
5312 05:56:11.773310 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5313 05:56:11.780075 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5314 05:56:11.783676 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5315 05:56:11.790007 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 05:56:11.793485 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 05:56:11.796776 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 05:56:11.803597 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 05:56:11.806471 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 05:56:11.810220 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 05:56:11.813111 0 14 28 | B1->B0 | 2a2a 2c2c | 1 1 | (1 1) (1 1)
5322 05:56:11.820123 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 05:56:11.823039 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 05:56:11.826614 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 05:56:11.833248 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 05:56:11.836746 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 05:56:11.840020 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 05:56:11.846879 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 05:56:11.849815 0 15 28 | B1->B0 | 3838 3131 | 0 0 | (0 0) (0 0)
5330 05:56:11.853380 1 0 0 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
5331 05:56:11.859853 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 05:56:11.863423 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 05:56:11.866067 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 05:56:11.873069 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 05:56:11.876352 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 05:56:11.879536 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 05:56:11.886302 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5338 05:56:11.889703 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 05:56:11.892924 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 05:56:11.899219 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 05:56:11.902716 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 05:56:11.906226 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 05:56:11.912957 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 05:56:11.916321 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 05:56:11.919646 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 05:56:11.925832 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 05:56:11.929088 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 05:56:11.932560 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 05:56:11.938740 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 05:56:11.942191 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 05:56:11.945404 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 05:56:11.952190 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 05:56:11.955661 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5354 05:56:11.958451 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 05:56:11.962121 Total UI for P1: 0, mck2ui 16
5356 05:56:11.965658 best dqsien dly found for B0: ( 1, 2, 28)
5357 05:56:11.968599 Total UI for P1: 0, mck2ui 16
5358 05:56:11.972017 best dqsien dly found for B1: ( 1, 2, 28)
5359 05:56:11.975583 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5360 05:56:11.978387 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5361 05:56:11.978468
5362 05:56:11.985451 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5363 05:56:11.988921 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5364 05:56:11.992064 [Gating] SW calibration Done
5365 05:56:11.992150 ==
5366 05:56:11.995424 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 05:56:11.998649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 05:56:11.998731 ==
5369 05:56:11.998823 RX Vref Scan: 0
5370 05:56:11.998903
5371 05:56:12.001902 RX Vref 0 -> 0, step: 1
5372 05:56:12.001992
5373 05:56:12.005046 RX Delay -80 -> 252, step: 8
5374 05:56:12.008472 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5375 05:56:12.011799 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5376 05:56:12.018276 iDelay=208, Bit 2, Center 107 (16 ~ 199) 184
5377 05:56:12.021666 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5378 05:56:12.024724 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5379 05:56:12.028169 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5380 05:56:12.031709 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5381 05:56:12.034945 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5382 05:56:12.041282 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5383 05:56:12.044658 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5384 05:56:12.047851 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5385 05:56:12.051320 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5386 05:56:12.054565 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5387 05:56:12.061340 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5388 05:56:12.064950 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5389 05:56:12.067784 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5390 05:56:12.067863 ==
5391 05:56:12.071409 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 05:56:12.074349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 05:56:12.074431 ==
5394 05:56:12.077812 DQS Delay:
5395 05:56:12.077889 DQS0 = 0, DQS1 = 0
5396 05:56:12.077954 DQM Delay:
5397 05:56:12.081334 DQM0 = 105, DQM1 = 95
5398 05:56:12.081405 DQ Delay:
5399 05:56:12.084898 DQ0 =107, DQ1 =107, DQ2 =107, DQ3 =99
5400 05:56:12.087739 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5401 05:56:12.091405 DQ8 =87, DQ9 =87, DQ10 =91, DQ11 =87
5402 05:56:12.097559 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =103
5403 05:56:12.097641
5404 05:56:12.097736
5405 05:56:12.097796 ==
5406 05:56:12.101026 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 05:56:12.104674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 05:56:12.104757 ==
5409 05:56:12.104823
5410 05:56:12.104894
5411 05:56:12.108116 TX Vref Scan disable
5412 05:56:12.108199 == TX Byte 0 ==
5413 05:56:12.114608 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5414 05:56:12.117819 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5415 05:56:12.117897 == TX Byte 1 ==
5416 05:56:12.124544 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5417 05:56:12.127834 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5418 05:56:12.127931 ==
5419 05:56:12.130783 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 05:56:12.134477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 05:56:12.134556 ==
5422 05:56:12.134621
5423 05:56:12.134682
5424 05:56:12.138031 TX Vref Scan disable
5425 05:56:12.140803 == TX Byte 0 ==
5426 05:56:12.144429 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5427 05:56:12.147634 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5428 05:56:12.150922 == TX Byte 1 ==
5429 05:56:12.154178 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5430 05:56:12.157479 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5431 05:56:12.157563
5432 05:56:12.160729 [DATLAT]
5433 05:56:12.160816 Freq=933, CH0 RK1
5434 05:56:12.160887
5435 05:56:12.164039 DATLAT Default: 0xb
5436 05:56:12.164168 0, 0xFFFF, sum = 0
5437 05:56:12.167370 1, 0xFFFF, sum = 0
5438 05:56:12.167445 2, 0xFFFF, sum = 0
5439 05:56:12.170730 3, 0xFFFF, sum = 0
5440 05:56:12.170812 4, 0xFFFF, sum = 0
5441 05:56:12.174179 5, 0xFFFF, sum = 0
5442 05:56:12.174256 6, 0xFFFF, sum = 0
5443 05:56:12.177822 7, 0xFFFF, sum = 0
5444 05:56:12.177929 8, 0xFFFF, sum = 0
5445 05:56:12.181305 9, 0xFFFF, sum = 0
5446 05:56:12.181401 10, 0x0, sum = 1
5447 05:56:12.184076 11, 0x0, sum = 2
5448 05:56:12.184154 12, 0x0, sum = 3
5449 05:56:12.187665 13, 0x0, sum = 4
5450 05:56:12.187738 best_step = 11
5451 05:56:12.187806
5452 05:56:12.187868 ==
5453 05:56:12.191269 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 05:56:12.197634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 05:56:12.197717 ==
5456 05:56:12.197785 RX Vref Scan: 0
5457 05:56:12.197878
5458 05:56:12.201070 RX Vref 0 -> 0, step: 1
5459 05:56:12.201183
5460 05:56:12.204378 RX Delay -45 -> 252, step: 4
5461 05:56:12.207311 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5462 05:56:12.210806 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5463 05:56:12.217784 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5464 05:56:12.220574 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5465 05:56:12.224171 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5466 05:56:12.227455 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5467 05:56:12.230721 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5468 05:56:12.237764 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5469 05:56:12.240777 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5470 05:56:12.244027 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5471 05:56:12.247529 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5472 05:56:12.250302 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5473 05:56:12.253740 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5474 05:56:12.260606 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5475 05:56:12.264103 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5476 05:56:12.267432 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5477 05:56:12.267541 ==
5478 05:56:12.270684 Dram Type= 6, Freq= 0, CH_0, rank 1
5479 05:56:12.274103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5480 05:56:12.276879 ==
5481 05:56:12.276960 DQS Delay:
5482 05:56:12.277027 DQS0 = 0, DQS1 = 0
5483 05:56:12.280185 DQM Delay:
5484 05:56:12.280319 DQM0 = 104, DQM1 = 95
5485 05:56:12.283655 DQ Delay:
5486 05:56:12.287315 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5487 05:56:12.290100 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5488 05:56:12.293700 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =90
5489 05:56:12.296739 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5490 05:56:12.296822
5491 05:56:12.296884
5492 05:56:12.303827 [DQSOSCAuto] RK1, (LSB)MR18= 0x25fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5493 05:56:12.306553 CH0 RK1: MR19=504, MR18=25FE
5494 05:56:12.313467 CH0_RK1: MR19=0x504, MR18=0x25FE, DQSOSC=410, MR23=63, INC=64, DEC=42
5495 05:56:12.317035 [RxdqsGatingPostProcess] freq 933
5496 05:56:12.323443 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5497 05:56:12.323566 best DQS0 dly(2T, 0.5T) = (0, 10)
5498 05:56:12.326876 best DQS1 dly(2T, 0.5T) = (0, 10)
5499 05:56:12.329823 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5500 05:56:12.333430 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5501 05:56:12.336951 best DQS0 dly(2T, 0.5T) = (0, 10)
5502 05:56:12.340252 best DQS1 dly(2T, 0.5T) = (0, 10)
5503 05:56:12.343141 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5504 05:56:12.346631 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5505 05:56:12.350029 Pre-setting of DQS Precalculation
5506 05:56:12.356452 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5507 05:56:12.356561 ==
5508 05:56:12.360364 Dram Type= 6, Freq= 0, CH_1, rank 0
5509 05:56:12.363327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 05:56:12.363410 ==
5511 05:56:12.369705 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5512 05:56:12.373054 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5513 05:56:12.377384 [CA 0] Center 36 (6~67) winsize 62
5514 05:56:12.380637 [CA 1] Center 37 (6~68) winsize 63
5515 05:56:12.383649 [CA 2] Center 34 (4~65) winsize 62
5516 05:56:12.387443 [CA 3] Center 34 (4~65) winsize 62
5517 05:56:12.390620 [CA 4] Center 34 (4~65) winsize 62
5518 05:56:12.393889 [CA 5] Center 33 (3~64) winsize 62
5519 05:56:12.393976
5520 05:56:12.397332 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5521 05:56:12.397406
5522 05:56:12.400870 [CATrainingPosCal] consider 1 rank data
5523 05:56:12.403667 u2DelayCellTimex100 = 270/100 ps
5524 05:56:12.407328 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5525 05:56:12.410114 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5526 05:56:12.417037 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5527 05:56:12.420604 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5528 05:56:12.423501 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5529 05:56:12.426910 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5530 05:56:12.426997
5531 05:56:12.430415 CA PerBit enable=1, Macro0, CA PI delay=33
5532 05:56:12.430498
5533 05:56:12.434118 [CBTSetCACLKResult] CA Dly = 33
5534 05:56:12.434190 CS Dly: 7 (0~38)
5535 05:56:12.436895 ==
5536 05:56:12.436972 Dram Type= 6, Freq= 0, CH_1, rank 1
5537 05:56:12.443826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 05:56:12.443909 ==
5539 05:56:12.446686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5540 05:56:12.453895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5541 05:56:12.457364 [CA 0] Center 36 (6~67) winsize 62
5542 05:56:12.460110 [CA 1] Center 37 (6~68) winsize 63
5543 05:56:12.463668 [CA 2] Center 35 (5~66) winsize 62
5544 05:56:12.467055 [CA 3] Center 34 (4~65) winsize 62
5545 05:56:12.470479 [CA 4] Center 34 (4~65) winsize 62
5546 05:56:12.473906 [CA 5] Center 34 (4~64) winsize 61
5547 05:56:12.473991
5548 05:56:12.477184 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5549 05:56:12.477271
5550 05:56:12.480429 [CATrainingPosCal] consider 2 rank data
5551 05:56:12.483517 u2DelayCellTimex100 = 270/100 ps
5552 05:56:12.486760 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5553 05:56:12.490551 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5554 05:56:12.496725 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5555 05:56:12.499991 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5556 05:56:12.503653 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5557 05:56:12.506862 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5558 05:56:12.506946
5559 05:56:12.509976 CA PerBit enable=1, Macro0, CA PI delay=34
5560 05:56:12.510050
5561 05:56:12.513317 [CBTSetCACLKResult] CA Dly = 34
5562 05:56:12.513395 CS Dly: 8 (0~40)
5563 05:56:12.513459
5564 05:56:12.516872 ----->DramcWriteLeveling(PI) begin...
5565 05:56:12.520370 ==
5566 05:56:12.523682 Dram Type= 6, Freq= 0, CH_1, rank 0
5567 05:56:12.526608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 05:56:12.526685 ==
5569 05:56:12.530164 Write leveling (Byte 0): 24 => 24
5570 05:56:12.533687 Write leveling (Byte 1): 26 => 26
5571 05:56:12.536612 DramcWriteLeveling(PI) end<-----
5572 05:56:12.536691
5573 05:56:12.536754 ==
5574 05:56:12.540063 Dram Type= 6, Freq= 0, CH_1, rank 0
5575 05:56:12.543773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5576 05:56:12.543852 ==
5577 05:56:12.546567 [Gating] SW mode calibration
5578 05:56:12.553593 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5579 05:56:12.559985 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5580 05:56:12.563305 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 05:56:12.566784 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 05:56:12.573358 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 05:56:12.576736 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 05:56:12.579561 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 05:56:12.586522 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 05:56:12.589863 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5587 05:56:12.593039 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5588 05:56:12.599442 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 05:56:12.603356 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 05:56:12.606619 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 05:56:12.609862 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 05:56:12.616143 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 05:56:12.620014 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 05:56:12.623316 0 15 24 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
5595 05:56:12.629950 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5596 05:56:12.633321 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 05:56:12.635953 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 05:56:12.642750 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 05:56:12.646398 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 05:56:12.649799 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 05:56:12.656233 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 05:56:12.659626 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5603 05:56:12.663291 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5604 05:56:12.669558 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 05:56:12.673111 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 05:56:12.675901 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 05:56:12.682811 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 05:56:12.686266 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 05:56:12.689937 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 05:56:12.696169 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 05:56:12.699792 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 05:56:12.703049 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 05:56:12.709185 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 05:56:12.712482 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 05:56:12.716247 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 05:56:12.719501 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 05:56:12.726450 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5618 05:56:12.729313 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5619 05:56:12.732668 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 05:56:12.736032 Total UI for P1: 0, mck2ui 16
5621 05:56:12.739319 best dqsien dly found for B0: ( 1, 2, 22)
5622 05:56:12.742406 Total UI for P1: 0, mck2ui 16
5623 05:56:12.746196 best dqsien dly found for B1: ( 1, 2, 24)
5624 05:56:12.749130 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5625 05:56:12.755794 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5626 05:56:12.755914
5627 05:56:12.759427 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5628 05:56:12.762180 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5629 05:56:12.765701 [Gating] SW calibration Done
5630 05:56:12.765818 ==
5631 05:56:12.769210 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 05:56:12.772580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 05:56:12.772682 ==
5634 05:56:12.772788 RX Vref Scan: 0
5635 05:56:12.775556
5636 05:56:12.775665 RX Vref 0 -> 0, step: 1
5637 05:56:12.775763
5638 05:56:12.779089 RX Delay -80 -> 252, step: 8
5639 05:56:12.782716 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5640 05:56:12.786327 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5641 05:56:12.792540 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5642 05:56:12.796027 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5643 05:56:12.799586 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5644 05:56:12.802402 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5645 05:56:12.805890 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5646 05:56:12.809453 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5647 05:56:12.816049 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5648 05:56:12.818960 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5649 05:56:12.822275 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5650 05:56:12.825398 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5651 05:56:12.829332 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5652 05:56:12.832375 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5653 05:56:12.838720 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5654 05:56:12.842312 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5655 05:56:12.842459 ==
5656 05:56:12.845766 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 05:56:12.848550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 05:56:12.848682 ==
5659 05:56:12.852080 DQS Delay:
5660 05:56:12.852270 DQS0 = 0, DQS1 = 0
5661 05:56:12.855564 DQM Delay:
5662 05:56:12.855727 DQM0 = 102, DQM1 = 98
5663 05:56:12.855857 DQ Delay:
5664 05:56:12.858755 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5665 05:56:12.861872 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5666 05:56:12.865633 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5667 05:56:12.871825 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5668 05:56:12.872147
5669 05:56:12.872464
5670 05:56:12.872667 ==
5671 05:56:12.875223 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 05:56:12.878452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 05:56:12.878768 ==
5674 05:56:12.879092
5675 05:56:12.879394
5676 05:56:12.881938 TX Vref Scan disable
5677 05:56:12.882252 == TX Byte 0 ==
5678 05:56:12.888032 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5679 05:56:12.891681 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5680 05:56:12.891762 == TX Byte 1 ==
5681 05:56:12.897865 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5682 05:56:12.901412 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5683 05:56:12.901493 ==
5684 05:56:12.904945 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 05:56:12.908464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 05:56:12.908542 ==
5687 05:56:12.908607
5688 05:56:12.908673
5689 05:56:12.911214 TX Vref Scan disable
5690 05:56:12.914869 == TX Byte 0 ==
5691 05:56:12.917676 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5692 05:56:12.921320 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5693 05:56:12.924691 == TX Byte 1 ==
5694 05:56:12.928108 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5695 05:56:12.931056 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5696 05:56:12.934517
5697 05:56:12.934590 [DATLAT]
5698 05:56:12.934658 Freq=933, CH1 RK0
5699 05:56:12.934721
5700 05:56:12.938018 DATLAT Default: 0xd
5701 05:56:12.938095 0, 0xFFFF, sum = 0
5702 05:56:12.941388 1, 0xFFFF, sum = 0
5703 05:56:12.941497 2, 0xFFFF, sum = 0
5704 05:56:12.944514 3, 0xFFFF, sum = 0
5705 05:56:12.944585 4, 0xFFFF, sum = 0
5706 05:56:12.947485 5, 0xFFFF, sum = 0
5707 05:56:12.950952 6, 0xFFFF, sum = 0
5708 05:56:12.951030 7, 0xFFFF, sum = 0
5709 05:56:12.954578 8, 0xFFFF, sum = 0
5710 05:56:12.954665 9, 0xFFFF, sum = 0
5711 05:56:12.957694 10, 0x0, sum = 1
5712 05:56:12.957776 11, 0x0, sum = 2
5713 05:56:12.957842 12, 0x0, sum = 3
5714 05:56:12.960946 13, 0x0, sum = 4
5715 05:56:12.961027 best_step = 11
5716 05:56:12.961092
5717 05:56:12.964520 ==
5718 05:56:12.964601 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 05:56:12.970804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 05:56:12.970886 ==
5721 05:56:12.970951 RX Vref Scan: 1
5722 05:56:12.971011
5723 05:56:12.974267 RX Vref 0 -> 0, step: 1
5724 05:56:12.974348
5725 05:56:12.977545 RX Delay -45 -> 252, step: 4
5726 05:56:12.977625
5727 05:56:12.980807 Set Vref, RX VrefLevel [Byte0]: 53
5728 05:56:12.983932 [Byte1]: 53
5729 05:56:12.984013
5730 05:56:12.987461 Final RX Vref Byte 0 = 53 to rank0
5731 05:56:12.990802 Final RX Vref Byte 1 = 53 to rank0
5732 05:56:12.994105 Final RX Vref Byte 0 = 53 to rank1
5733 05:56:12.997444 Final RX Vref Byte 1 = 53 to rank1==
5734 05:56:13.000531 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 05:56:13.003910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 05:56:13.007429 ==
5737 05:56:13.007510 DQS Delay:
5738 05:56:13.007574 DQS0 = 0, DQS1 = 0
5739 05:56:13.010948 DQM Delay:
5740 05:56:13.011029 DQM0 = 103, DQM1 = 98
5741 05:56:13.013763 DQ Delay:
5742 05:56:13.017408 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5743 05:56:13.020215 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5744 05:56:13.023704 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5745 05:56:13.027367 DQ12 =104, DQ13 =102, DQ14 =106, DQ15 =104
5746 05:56:13.027441
5747 05:56:13.027508
5748 05:56:13.033739 [DQSOSCAuto] RK0, (LSB)MR18= 0x162e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5749 05:56:13.037401 CH1 RK0: MR19=505, MR18=162E
5750 05:56:13.043782 CH1_RK0: MR19=0x505, MR18=0x162E, DQSOSC=407, MR23=63, INC=65, DEC=43
5751 05:56:13.043861
5752 05:56:13.047415 ----->DramcWriteLeveling(PI) begin...
5753 05:56:13.047494 ==
5754 05:56:13.050298 Dram Type= 6, Freq= 0, CH_1, rank 1
5755 05:56:13.053603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 05:56:13.053681 ==
5757 05:56:13.057177 Write leveling (Byte 0): 28 => 28
5758 05:56:13.060560 Write leveling (Byte 1): 27 => 27
5759 05:56:13.063799 DramcWriteLeveling(PI) end<-----
5760 05:56:13.063879
5761 05:56:13.063945 ==
5762 05:56:13.066772 Dram Type= 6, Freq= 0, CH_1, rank 1
5763 05:56:13.070445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 05:56:13.070529 ==
5765 05:56:13.073440 [Gating] SW mode calibration
5766 05:56:13.080839 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5767 05:56:13.087301 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5768 05:56:13.090784 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 05:56:13.096814 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 05:56:13.100622 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5771 05:56:13.103679 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 05:56:13.110695 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 05:56:13.113880 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 05:56:13.117180 0 14 24 | B1->B0 | 2e2e 3232 | 1 0 | (1 0) (0 0)
5775 05:56:13.123626 0 14 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5776 05:56:13.127087 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 05:56:13.130591 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 05:56:13.133501 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 05:56:13.140543 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 05:56:13.143378 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 05:56:13.146856 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 05:56:13.153391 0 15 24 | B1->B0 | 3232 2626 | 0 1 | (0 0) (0 0)
5783 05:56:13.156755 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (1 1)
5784 05:56:13.160488 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 05:56:13.166851 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 05:56:13.170297 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 05:56:13.173171 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 05:56:13.180224 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 05:56:13.183023 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5790 05:56:13.186340 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 05:56:13.193156 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5792 05:56:13.196483 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 05:56:13.200038 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 05:56:13.206981 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 05:56:13.209752 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 05:56:13.213637 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 05:56:13.220110 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 05:56:13.223313 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 05:56:13.226567 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 05:56:13.233671 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 05:56:13.236217 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 05:56:13.240067 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 05:56:13.246252 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 05:56:13.249727 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 05:56:13.253146 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 05:56:13.260247 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5807 05:56:13.263130 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 05:56:13.266621 Total UI for P1: 0, mck2ui 16
5809 05:56:13.270256 best dqsien dly found for B0: ( 1, 2, 24)
5810 05:56:13.273016 Total UI for P1: 0, mck2ui 16
5811 05:56:13.276401 best dqsien dly found for B1: ( 1, 2, 24)
5812 05:56:13.279695 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5813 05:56:13.283404 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5814 05:56:13.283476
5815 05:56:13.286235 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5816 05:56:13.289851 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5817 05:56:13.293416 [Gating] SW calibration Done
5818 05:56:13.293534 ==
5819 05:56:13.296241 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 05:56:13.299595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 05:56:13.299669 ==
5822 05:56:13.302917 RX Vref Scan: 0
5823 05:56:13.302994
5824 05:56:13.306587 RX Vref 0 -> 0, step: 1
5825 05:56:13.306660
5826 05:56:13.306722 RX Delay -80 -> 252, step: 8
5827 05:56:13.312879 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5828 05:56:13.316416 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5829 05:56:13.319843 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5830 05:56:13.323077 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5831 05:56:13.326443 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5832 05:56:13.329769 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5833 05:56:13.336262 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5834 05:56:13.339606 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5835 05:56:13.342894 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5836 05:56:13.346210 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5837 05:56:13.349605 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5838 05:56:13.352998 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5839 05:56:13.359904 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5840 05:56:13.363185 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5841 05:56:13.366075 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5842 05:56:13.369497 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5843 05:56:13.369587 ==
5844 05:56:13.373033 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 05:56:13.379414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 05:56:13.379488 ==
5847 05:56:13.379554 DQS Delay:
5848 05:56:13.379613 DQS0 = 0, DQS1 = 0
5849 05:56:13.382896 DQM Delay:
5850 05:56:13.382964 DQM0 = 102, DQM1 = 99
5851 05:56:13.386372 DQ Delay:
5852 05:56:13.389765 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5853 05:56:13.393227 DQ4 =95, DQ5 =119, DQ6 =111, DQ7 =99
5854 05:56:13.396014 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5855 05:56:13.399500 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5856 05:56:13.399573
5857 05:56:13.399640
5858 05:56:13.399700 ==
5859 05:56:13.403020 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 05:56:13.405797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 05:56:13.405868 ==
5862 05:56:13.405935
5863 05:56:13.405996
5864 05:56:13.409362 TX Vref Scan disable
5865 05:56:13.412671 == TX Byte 0 ==
5866 05:56:13.415844 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5867 05:56:13.419120 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5868 05:56:13.422401 == TX Byte 1 ==
5869 05:56:13.426217 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5870 05:56:13.429382 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5871 05:56:13.429461 ==
5872 05:56:13.432878 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 05:56:13.436098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 05:56:13.436202 ==
5875 05:56:13.439394
5876 05:56:13.439471
5877 05:56:13.439536 TX Vref Scan disable
5878 05:56:13.442677 == TX Byte 0 ==
5879 05:56:13.446122 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5880 05:56:13.452795 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5881 05:56:13.452873 == TX Byte 1 ==
5882 05:56:13.456037 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5883 05:56:13.462789 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5884 05:56:13.462870
5885 05:56:13.462933 [DATLAT]
5886 05:56:13.463001 Freq=933, CH1 RK1
5887 05:56:13.463063
5888 05:56:13.465605 DATLAT Default: 0xb
5889 05:56:13.465682 0, 0xFFFF, sum = 0
5890 05:56:13.468996 1, 0xFFFF, sum = 0
5891 05:56:13.469073 2, 0xFFFF, sum = 0
5892 05:56:13.472756 3, 0xFFFF, sum = 0
5893 05:56:13.475972 4, 0xFFFF, sum = 0
5894 05:56:13.476055 5, 0xFFFF, sum = 0
5895 05:56:13.479428 6, 0xFFFF, sum = 0
5896 05:56:13.479531 7, 0xFFFF, sum = 0
5897 05:56:13.482363 8, 0xFFFF, sum = 0
5898 05:56:13.482461 9, 0xFFFF, sum = 0
5899 05:56:13.485742 10, 0x0, sum = 1
5900 05:56:13.485841 11, 0x0, sum = 2
5901 05:56:13.489210 12, 0x0, sum = 3
5902 05:56:13.489294 13, 0x0, sum = 4
5903 05:56:13.489389 best_step = 11
5904 05:56:13.489476
5905 05:56:13.492587 ==
5906 05:56:13.495975 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 05:56:13.499382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 05:56:13.499484 ==
5909 05:56:13.499574 RX Vref Scan: 0
5910 05:56:13.499663
5911 05:56:13.502824 RX Vref 0 -> 0, step: 1
5912 05:56:13.502921
5913 05:56:13.505642 RX Delay -45 -> 252, step: 4
5914 05:56:13.509163 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5915 05:56:13.515617 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5916 05:56:13.519095 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5917 05:56:13.522464 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5918 05:56:13.525453 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5919 05:56:13.528700 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5920 05:56:13.535812 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5921 05:56:13.539136 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5922 05:56:13.542488 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5923 05:56:13.545860 iDelay=203, Bit 9, Center 88 (-1 ~ 178) 180
5924 05:56:13.549215 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5925 05:56:13.552621 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5926 05:56:13.559310 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5927 05:56:13.562597 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5928 05:56:13.565936 iDelay=203, Bit 14, Center 104 (19 ~ 190) 172
5929 05:56:13.569384 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5930 05:56:13.569485 ==
5931 05:56:13.572740 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 05:56:13.578892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 05:56:13.578994 ==
5934 05:56:13.579084 DQS Delay:
5935 05:56:13.579185 DQS0 = 0, DQS1 = 0
5936 05:56:13.582766 DQM Delay:
5937 05:56:13.582836 DQM0 = 104, DQM1 = 98
5938 05:56:13.585989 DQ Delay:
5939 05:56:13.589108 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5940 05:56:13.592635 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5941 05:56:13.596029 DQ8 =90, DQ9 =88, DQ10 =98, DQ11 =92
5942 05:56:13.599533 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =106
5943 05:56:13.599631
5944 05:56:13.599729
5945 05:56:13.605923 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5946 05:56:13.609482 CH1 RK1: MR19=504, MR18=2BFF
5947 05:56:13.615932 CH1_RK1: MR19=0x504, MR18=0x2BFF, DQSOSC=408, MR23=63, INC=65, DEC=43
5948 05:56:13.618766 [RxdqsGatingPostProcess] freq 933
5949 05:56:13.625704 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5950 05:56:13.625809 best DQS0 dly(2T, 0.5T) = (0, 10)
5951 05:56:13.629176 best DQS1 dly(2T, 0.5T) = (0, 10)
5952 05:56:13.631970 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5953 05:56:13.635507 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5954 05:56:13.638796 best DQS0 dly(2T, 0.5T) = (0, 10)
5955 05:56:13.642012 best DQS1 dly(2T, 0.5T) = (0, 10)
5956 05:56:13.645215 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5957 05:56:13.648628 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5958 05:56:13.651968 Pre-setting of DQS Precalculation
5959 05:56:13.658645 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5960 05:56:13.665268 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5961 05:56:13.672329 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5962 05:56:13.672414
5963 05:56:13.672480
5964 05:56:13.675587 [Calibration Summary] 1866 Mbps
5965 05:56:13.675687 CH 0, Rank 0
5966 05:56:13.678399 SW Impedance : PASS
5967 05:56:13.682140 DUTY Scan : NO K
5968 05:56:13.682221 ZQ Calibration : PASS
5969 05:56:13.684923 Jitter Meter : NO K
5970 05:56:13.684997 CBT Training : PASS
5971 05:56:13.688550 Write leveling : PASS
5972 05:56:13.691977 RX DQS gating : PASS
5973 05:56:13.692082 RX DQ/DQS(RDDQC) : PASS
5974 05:56:13.695380 TX DQ/DQS : PASS
5975 05:56:13.698537 RX DATLAT : PASS
5976 05:56:13.698636 RX DQ/DQS(Engine): PASS
5977 05:56:13.702186 TX OE : NO K
5978 05:56:13.702290 All Pass.
5979 05:56:13.702381
5980 05:56:13.705361 CH 0, Rank 1
5981 05:56:13.705468 SW Impedance : PASS
5982 05:56:13.708379 DUTY Scan : NO K
5983 05:56:13.711965 ZQ Calibration : PASS
5984 05:56:13.712066 Jitter Meter : NO K
5985 05:56:13.715413 CBT Training : PASS
5986 05:56:13.718908 Write leveling : PASS
5987 05:56:13.719011 RX DQS gating : PASS
5988 05:56:13.721756 RX DQ/DQS(RDDQC) : PASS
5989 05:56:13.725482 TX DQ/DQS : PASS
5990 05:56:13.725584 RX DATLAT : PASS
5991 05:56:13.728859 RX DQ/DQS(Engine): PASS
5992 05:56:13.728937 TX OE : NO K
5993 05:56:13.731652 All Pass.
5994 05:56:13.731751
5995 05:56:13.731818 CH 1, Rank 0
5996 05:56:13.735141 SW Impedance : PASS
5997 05:56:13.735243 DUTY Scan : NO K
5998 05:56:13.742560 ZQ Calibration : PASS
5999 05:56:13.742665 Jitter Meter : NO K
6000 05:56:13.742758 CBT Training : PASS
6001 05:56:13.745062 Write leveling : PASS
6002 05:56:13.748430 RX DQS gating : PASS
6003 05:56:13.748506 RX DQ/DQS(RDDQC) : PASS
6004 05:56:13.751692 TX DQ/DQS : PASS
6005 05:56:13.754856 RX DATLAT : PASS
6006 05:56:13.754958 RX DQ/DQS(Engine): PASS
6007 05:56:13.758771 TX OE : NO K
6008 05:56:13.758875 All Pass.
6009 05:56:13.758965
6010 05:56:13.761987 CH 1, Rank 1
6011 05:56:13.762075 SW Impedance : PASS
6012 05:56:13.765215 DUTY Scan : NO K
6013 05:56:13.768437 ZQ Calibration : PASS
6014 05:56:13.768541 Jitter Meter : NO K
6015 05:56:13.771670 CBT Training : PASS
6016 05:56:13.774862 Write leveling : PASS
6017 05:56:13.774940 RX DQS gating : PASS
6018 05:56:13.778215 RX DQ/DQS(RDDQC) : PASS
6019 05:56:13.778295 TX DQ/DQS : PASS
6020 05:56:13.781628 RX DATLAT : PASS
6021 05:56:13.784939 RX DQ/DQS(Engine): PASS
6022 05:56:13.785034 TX OE : NO K
6023 05:56:13.788227 All Pass.
6024 05:56:13.788350
6025 05:56:13.788436 DramC Write-DBI off
6026 05:56:13.791420 PER_BANK_REFRESH: Hybrid Mode
6027 05:56:13.795318 TX_TRACKING: ON
6028 05:56:13.802176 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6029 05:56:13.804911 [FAST_K] Save calibration result to emmc
6030 05:56:13.808199 dramc_set_vcore_voltage set vcore to 650000
6031 05:56:13.811543 Read voltage for 400, 6
6032 05:56:13.811624 Vio18 = 0
6033 05:56:13.814811 Vcore = 650000
6034 05:56:13.814892 Vdram = 0
6035 05:56:13.814957 Vddq = 0
6036 05:56:13.818502 Vmddr = 0
6037 05:56:13.821595 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6038 05:56:13.828571 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6039 05:56:13.828654 MEM_TYPE=3, freq_sel=20
6040 05:56:13.831314 sv_algorithm_assistance_LP4_800
6041 05:56:13.838074 ============ PULL DRAM RESETB DOWN ============
6042 05:56:13.841664 ========== PULL DRAM RESETB DOWN end =========
6043 05:56:13.844775 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6044 05:56:13.848117 ===================================
6045 05:56:13.851685 LPDDR4 DRAM CONFIGURATION
6046 05:56:13.855117 ===================================
6047 05:56:13.858405 EX_ROW_EN[0] = 0x0
6048 05:56:13.858487 EX_ROW_EN[1] = 0x0
6049 05:56:13.861195 LP4Y_EN = 0x0
6050 05:56:13.861276 WORK_FSP = 0x0
6051 05:56:13.864520 WL = 0x2
6052 05:56:13.864603 RL = 0x2
6053 05:56:13.868189 BL = 0x2
6054 05:56:13.868272 RPST = 0x0
6055 05:56:13.871378 RD_PRE = 0x0
6056 05:56:13.871458 WR_PRE = 0x1
6057 05:56:13.874784 WR_PST = 0x0
6058 05:56:13.874866 DBI_WR = 0x0
6059 05:56:13.878208 DBI_RD = 0x0
6060 05:56:13.878306 OTF = 0x1
6061 05:56:13.881535 ===================================
6062 05:56:13.884826 ===================================
6063 05:56:13.887752 ANA top config
6064 05:56:13.891121 ===================================
6065 05:56:13.894515 DLL_ASYNC_EN = 0
6066 05:56:13.894594 ALL_SLAVE_EN = 1
6067 05:56:13.897818 NEW_RANK_MODE = 1
6068 05:56:13.901204 DLL_IDLE_MODE = 1
6069 05:56:13.904558 LP45_APHY_COMB_EN = 1
6070 05:56:13.904641 TX_ODT_DIS = 1
6071 05:56:13.908163 NEW_8X_MODE = 1
6072 05:56:13.911395 ===================================
6073 05:56:13.914680 ===================================
6074 05:56:13.918011 data_rate = 800
6075 05:56:13.920838 CKR = 1
6076 05:56:13.924720 DQ_P2S_RATIO = 4
6077 05:56:13.928046 ===================================
6078 05:56:13.931063 CA_P2S_RATIO = 4
6079 05:56:13.931147 DQ_CA_OPEN = 0
6080 05:56:13.934372 DQ_SEMI_OPEN = 1
6081 05:56:13.937733 CA_SEMI_OPEN = 1
6082 05:56:13.941173 CA_FULL_RATE = 0
6083 05:56:13.944708 DQ_CKDIV4_EN = 0
6084 05:56:13.948203 CA_CKDIV4_EN = 1
6085 05:56:13.948346 CA_PREDIV_EN = 0
6086 05:56:13.951084 PH8_DLY = 0
6087 05:56:13.954561 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6088 05:56:13.957908 DQ_AAMCK_DIV = 0
6089 05:56:13.961326 CA_AAMCK_DIV = 0
6090 05:56:13.961413 CA_ADMCK_DIV = 4
6091 05:56:13.964713 DQ_TRACK_CA_EN = 0
6092 05:56:13.968015 CA_PICK = 800
6093 05:56:13.971369 CA_MCKIO = 400
6094 05:56:13.974633 MCKIO_SEMI = 400
6095 05:56:13.977579 PLL_FREQ = 3016
6096 05:56:13.980905 DQ_UI_PI_RATIO = 32
6097 05:56:13.984430 CA_UI_PI_RATIO = 32
6098 05:56:13.987960 ===================================
6099 05:56:13.991244 ===================================
6100 05:56:13.991328 memory_type:LPDDR4
6101 05:56:13.994624 GP_NUM : 10
6102 05:56:13.997709 SRAM_EN : 1
6103 05:56:13.997795 MD32_EN : 0
6104 05:56:14.000972 ===================================
6105 05:56:14.004429 [ANA_INIT] >>>>>>>>>>>>>>
6106 05:56:14.007683 <<<<<< [CONFIGURE PHASE]: ANA_TX
6107 05:56:14.011464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6108 05:56:14.013953 ===================================
6109 05:56:14.014036 data_rate = 800,PCW = 0X7400
6110 05:56:14.017883 ===================================
6111 05:56:14.024213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6112 05:56:14.027779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6113 05:56:14.041079 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6114 05:56:14.044450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6115 05:56:14.047645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6116 05:56:14.050425 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6117 05:56:14.053884 [ANA_INIT] flow start
6118 05:56:14.053971 [ANA_INIT] PLL >>>>>>>>
6119 05:56:14.057359 [ANA_INIT] PLL <<<<<<<<
6120 05:56:14.060810 [ANA_INIT] MIDPI >>>>>>>>
6121 05:56:14.064361 [ANA_INIT] MIDPI <<<<<<<<
6122 05:56:14.064446 [ANA_INIT] DLL >>>>>>>>
6123 05:56:14.066947 [ANA_INIT] flow end
6124 05:56:14.071021 ============ LP4 DIFF to SE enter ============
6125 05:56:14.074214 ============ LP4 DIFF to SE exit ============
6126 05:56:14.076993 [ANA_INIT] <<<<<<<<<<<<<
6127 05:56:14.080417 [Flow] Enable top DCM control >>>>>
6128 05:56:14.083840 [Flow] Enable top DCM control <<<<<
6129 05:56:14.087354 Enable DLL master slave shuffle
6130 05:56:14.090747 ==============================================================
6131 05:56:14.094375 Gating Mode config
6132 05:56:14.100488 ==============================================================
6133 05:56:14.100576 Config description:
6134 05:56:14.110847 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6135 05:56:14.117387 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6136 05:56:14.124112 SELPH_MODE 0: By rank 1: By Phase
6137 05:56:14.127453 ==============================================================
6138 05:56:14.130774 GAT_TRACK_EN = 0
6139 05:56:14.134080 RX_GATING_MODE = 2
6140 05:56:14.137416 RX_GATING_TRACK_MODE = 2
6141 05:56:14.140756 SELPH_MODE = 1
6142 05:56:14.144076 PICG_EARLY_EN = 1
6143 05:56:14.147408 VALID_LAT_VALUE = 1
6144 05:56:14.150927 ==============================================================
6145 05:56:14.154194 Enter into Gating configuration >>>>
6146 05:56:14.157459 Exit from Gating configuration <<<<
6147 05:56:14.160223 Enter into DVFS_PRE_config >>>>>
6148 05:56:14.174090 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6149 05:56:14.177349 Exit from DVFS_PRE_config <<<<<
6150 05:56:14.177436 Enter into PICG configuration >>>>
6151 05:56:14.180537 Exit from PICG configuration <<<<
6152 05:56:14.183920 [RX_INPUT] configuration >>>>>
6153 05:56:14.187332 [RX_INPUT] configuration <<<<<
6154 05:56:14.193614 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6155 05:56:14.197032 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6156 05:56:14.203397 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6157 05:56:14.210203 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6158 05:56:14.216892 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6159 05:56:14.223539 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6160 05:56:14.226734 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6161 05:56:14.230373 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6162 05:56:14.233564 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6163 05:56:14.240020 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6164 05:56:14.243348 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6165 05:56:14.246371 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6166 05:56:14.250018 ===================================
6167 05:56:14.253474 LPDDR4 DRAM CONFIGURATION
6168 05:56:14.256592 ===================================
6169 05:56:14.259778 EX_ROW_EN[0] = 0x0
6170 05:56:14.259862 EX_ROW_EN[1] = 0x0
6171 05:56:14.262962 LP4Y_EN = 0x0
6172 05:56:14.263046 WORK_FSP = 0x0
6173 05:56:14.266876 WL = 0x2
6174 05:56:14.266959 RL = 0x2
6175 05:56:14.269656 BL = 0x2
6176 05:56:14.269740 RPST = 0x0
6177 05:56:14.273190 RD_PRE = 0x0
6178 05:56:14.273313 WR_PRE = 0x1
6179 05:56:14.276609 WR_PST = 0x0
6180 05:56:14.276691 DBI_WR = 0x0
6181 05:56:14.280080 DBI_RD = 0x0
6182 05:56:14.280161 OTF = 0x1
6183 05:56:14.283436 ===================================
6184 05:56:14.289872 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6185 05:56:14.293276 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6186 05:56:14.296729 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6187 05:56:14.299471 ===================================
6188 05:56:14.302929 LPDDR4 DRAM CONFIGURATION
6189 05:56:14.306396 ===================================
6190 05:56:14.306479 EX_ROW_EN[0] = 0x10
6191 05:56:14.309852 EX_ROW_EN[1] = 0x0
6192 05:56:14.313309 LP4Y_EN = 0x0
6193 05:56:14.313391 WORK_FSP = 0x0
6194 05:56:14.316778 WL = 0x2
6195 05:56:14.316860 RL = 0x2
6196 05:56:14.319551 BL = 0x2
6197 05:56:14.319664 RPST = 0x0
6198 05:56:14.323151 RD_PRE = 0x0
6199 05:56:14.323253 WR_PRE = 0x1
6200 05:56:14.326691 WR_PST = 0x0
6201 05:56:14.326774 DBI_WR = 0x0
6202 05:56:14.329549 DBI_RD = 0x0
6203 05:56:14.329630 OTF = 0x1
6204 05:56:14.332881 ===================================
6205 05:56:14.339418 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6206 05:56:14.343877 nWR fixed to 30
6207 05:56:14.347196 [ModeRegInit_LP4] CH0 RK0
6208 05:56:14.347278 [ModeRegInit_LP4] CH0 RK1
6209 05:56:14.350448 [ModeRegInit_LP4] CH1 RK0
6210 05:56:14.353809 [ModeRegInit_LP4] CH1 RK1
6211 05:56:14.353891 match AC timing 19
6212 05:56:14.360436 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6213 05:56:14.364221 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6214 05:56:14.367164 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6215 05:56:14.373701 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6216 05:56:14.377309 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6217 05:56:14.377393 ==
6218 05:56:14.380692 Dram Type= 6, Freq= 0, CH_0, rank 0
6219 05:56:14.383858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6220 05:56:14.383940 ==
6221 05:56:14.390648 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6222 05:56:14.397405 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6223 05:56:14.400498 [CA 0] Center 36 (8~64) winsize 57
6224 05:56:14.403769 [CA 1] Center 36 (8~64) winsize 57
6225 05:56:14.407160 [CA 2] Center 36 (8~64) winsize 57
6226 05:56:14.410725 [CA 3] Center 36 (8~64) winsize 57
6227 05:56:14.410808 [CA 4] Center 36 (8~64) winsize 57
6228 05:56:14.414122 [CA 5] Center 36 (8~64) winsize 57
6229 05:56:14.414206
6230 05:56:14.420294 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6231 05:56:14.420413
6232 05:56:14.423715 [CATrainingPosCal] consider 1 rank data
6233 05:56:14.427258 u2DelayCellTimex100 = 270/100 ps
6234 05:56:14.430779 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 05:56:14.434107 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 05:56:14.436897 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 05:56:14.440533 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 05:56:14.443969 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 05:56:14.447297 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 05:56:14.447400
6241 05:56:14.450708 CA PerBit enable=1, Macro0, CA PI delay=36
6242 05:56:14.450791
6243 05:56:14.453832 [CBTSetCACLKResult] CA Dly = 36
6244 05:56:14.457017 CS Dly: 1 (0~32)
6245 05:56:14.457117 ==
6246 05:56:14.460283 Dram Type= 6, Freq= 0, CH_0, rank 1
6247 05:56:14.463584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 05:56:14.463700 ==
6249 05:56:14.470472 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6250 05:56:14.473981 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6251 05:56:14.477321 [CA 0] Center 36 (8~64) winsize 57
6252 05:56:14.480579 [CA 1] Center 36 (8~64) winsize 57
6253 05:56:14.483596 [CA 2] Center 36 (8~64) winsize 57
6254 05:56:14.487262 [CA 3] Center 36 (8~64) winsize 57
6255 05:56:14.490096 [CA 4] Center 36 (8~64) winsize 57
6256 05:56:14.493514 [CA 5] Center 36 (8~64) winsize 57
6257 05:56:14.493652
6258 05:56:14.496728 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6259 05:56:14.496825
6260 05:56:14.499954 [CATrainingPosCal] consider 2 rank data
6261 05:56:14.503506 u2DelayCellTimex100 = 270/100 ps
6262 05:56:14.506650 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 05:56:14.510457 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 05:56:14.513461 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 05:56:14.519899 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 05:56:14.523861 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 05:56:14.526590 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 05:56:14.526672
6269 05:56:14.529968 CA PerBit enable=1, Macro0, CA PI delay=36
6270 05:56:14.530050
6271 05:56:14.533515 [CBTSetCACLKResult] CA Dly = 36
6272 05:56:14.533596 CS Dly: 1 (0~32)
6273 05:56:14.533662
6274 05:56:14.536828 ----->DramcWriteLeveling(PI) begin...
6275 05:56:14.536914 ==
6276 05:56:14.540477 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 05:56:14.546629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 05:56:14.546718 ==
6279 05:56:14.550008 Write leveling (Byte 0): 40 => 8
6280 05:56:14.550107 Write leveling (Byte 1): 40 => 8
6281 05:56:14.553470 DramcWriteLeveling(PI) end<-----
6282 05:56:14.553607
6283 05:56:14.556926 ==
6284 05:56:14.557011 Dram Type= 6, Freq= 0, CH_0, rank 0
6285 05:56:14.563580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 05:56:14.563667 ==
6287 05:56:14.566957 [Gating] SW mode calibration
6288 05:56:14.573483 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6289 05:56:14.576693 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6290 05:56:14.583537 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6291 05:56:14.586924 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6292 05:56:14.589859 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6293 05:56:14.596855 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6294 05:56:14.600338 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6295 05:56:14.602893 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6296 05:56:14.609750 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 05:56:14.613348 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 05:56:14.616235 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 05:56:14.619976 Total UI for P1: 0, mck2ui 16
6300 05:56:14.623094 best dqsien dly found for B0: ( 0, 14, 24)
6301 05:56:14.626223 Total UI for P1: 0, mck2ui 16
6302 05:56:14.629867 best dqsien dly found for B1: ( 0, 14, 24)
6303 05:56:14.633276 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6304 05:56:14.636274 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6305 05:56:14.636399
6306 05:56:14.643217 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6307 05:56:14.646181 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6308 05:56:14.646265 [Gating] SW calibration Done
6309 05:56:14.649655 ==
6310 05:56:14.653091 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 05:56:14.656462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 05:56:14.656549 ==
6313 05:56:14.656644 RX Vref Scan: 0
6314 05:56:14.656733
6315 05:56:14.659926 RX Vref 0 -> 0, step: 1
6316 05:56:14.660023
6317 05:56:14.662826 RX Delay -410 -> 252, step: 16
6318 05:56:14.666146 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6319 05:56:14.672870 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6320 05:56:14.676464 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6321 05:56:14.679874 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6322 05:56:14.683127 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6323 05:56:14.685848 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6324 05:56:14.692761 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6325 05:56:14.696255 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6326 05:56:14.699743 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6327 05:56:14.702526 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6328 05:56:14.709418 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6329 05:56:14.712743 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6330 05:56:14.716171 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6331 05:56:14.722518 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6332 05:56:14.725798 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6333 05:56:14.729605 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6334 05:56:14.729717 ==
6335 05:56:14.732788 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 05:56:14.735974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 05:56:14.736057 ==
6338 05:56:14.739297 DQS Delay:
6339 05:56:14.739379 DQS0 = 27, DQS1 = 35
6340 05:56:14.742656 DQM Delay:
6341 05:56:14.742738 DQM0 = 9, DQM1 = 11
6342 05:56:14.745915 DQ Delay:
6343 05:56:14.745996 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6344 05:56:14.749286 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6345 05:56:14.752598 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6346 05:56:14.755785 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6347 05:56:14.755868
6348 05:56:14.755933
6349 05:56:14.755994 ==
6350 05:56:14.759332 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 05:56:14.765516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 05:56:14.765599 ==
6353 05:56:14.765684
6354 05:56:14.765761
6355 05:56:14.765820 TX Vref Scan disable
6356 05:56:14.769152 == TX Byte 0 ==
6357 05:56:14.772507 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6358 05:56:14.775875 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6359 05:56:14.778726 == TX Byte 1 ==
6360 05:56:14.782080 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 05:56:14.785560 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 05:56:14.788803 ==
6363 05:56:14.792431 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 05:56:14.795095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 05:56:14.795178 ==
6366 05:56:14.795244
6367 05:56:14.795305
6368 05:56:14.798601 TX Vref Scan disable
6369 05:56:14.798684 == TX Byte 0 ==
6370 05:56:14.802185 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6371 05:56:14.808366 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6372 05:56:14.808450 == TX Byte 1 ==
6373 05:56:14.811597 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6374 05:56:14.818417 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6375 05:56:14.818500
6376 05:56:14.818566 [DATLAT]
6377 05:56:14.818627 Freq=400, CH0 RK0
6378 05:56:14.818687
6379 05:56:14.821769 DATLAT Default: 0xf
6380 05:56:14.821851 0, 0xFFFF, sum = 0
6381 05:56:14.825225 1, 0xFFFF, sum = 0
6382 05:56:14.825309 2, 0xFFFF, sum = 0
6383 05:56:14.828681 3, 0xFFFF, sum = 0
6384 05:56:14.828764 4, 0xFFFF, sum = 0
6385 05:56:14.832091 5, 0xFFFF, sum = 0
6386 05:56:14.835616 6, 0xFFFF, sum = 0
6387 05:56:14.835700 7, 0xFFFF, sum = 0
6388 05:56:14.838937 8, 0xFFFF, sum = 0
6389 05:56:14.839038 9, 0xFFFF, sum = 0
6390 05:56:14.842152 10, 0xFFFF, sum = 0
6391 05:56:14.842245 11, 0xFFFF, sum = 0
6392 05:56:14.845278 12, 0xFFFF, sum = 0
6393 05:56:14.845362 13, 0x0, sum = 1
6394 05:56:14.848296 14, 0x0, sum = 2
6395 05:56:14.848414 15, 0x0, sum = 3
6396 05:56:14.852055 16, 0x0, sum = 4
6397 05:56:14.852138 best_step = 14
6398 05:56:14.852203
6399 05:56:14.852264 ==
6400 05:56:14.855526 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 05:56:14.858377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 05:56:14.858461 ==
6403 05:56:14.861859 RX Vref Scan: 1
6404 05:56:14.861942
6405 05:56:14.865266 RX Vref 0 -> 0, step: 1
6406 05:56:14.865349
6407 05:56:14.865416 RX Delay -311 -> 252, step: 8
6408 05:56:14.865477
6409 05:56:14.868280 Set Vref, RX VrefLevel [Byte0]: 54
6410 05:56:14.871633 [Byte1]: 55
6411 05:56:14.877347
6412 05:56:14.877440 Final RX Vref Byte 0 = 54 to rank0
6413 05:56:14.880519 Final RX Vref Byte 1 = 55 to rank0
6414 05:56:14.884031 Final RX Vref Byte 0 = 54 to rank1
6415 05:56:14.887266 Final RX Vref Byte 1 = 55 to rank1==
6416 05:56:14.890852 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 05:56:14.897506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 05:56:14.897591 ==
6419 05:56:14.897658 DQS Delay:
6420 05:56:14.900660 DQS0 = 28, DQS1 = 36
6421 05:56:14.900774 DQM Delay:
6422 05:56:14.900869 DQM0 = 11, DQM1 = 12
6423 05:56:14.903765 DQ Delay:
6424 05:56:14.907196 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6425 05:56:14.907280 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6426 05:56:14.910677 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6427 05:56:14.913518 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6428 05:56:14.913608
6429 05:56:14.916909
6430 05:56:14.923816 [DQSOSCAuto] RK0, (LSB)MR18= 0xc3b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6431 05:56:14.927371 CH0 RK0: MR19=C0C, MR18=C3B0
6432 05:56:14.933489 CH0_RK0: MR19=0xC0C, MR18=0xC3B0, DQSOSC=385, MR23=63, INC=398, DEC=265
6433 05:56:14.933572 ==
6434 05:56:14.936969 Dram Type= 6, Freq= 0, CH_0, rank 1
6435 05:56:14.940424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 05:56:14.940508 ==
6437 05:56:14.943786 [Gating] SW mode calibration
6438 05:56:14.950582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6439 05:56:14.957644 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6440 05:56:14.960827 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6441 05:56:14.964052 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6442 05:56:14.970468 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 05:56:14.973865 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6444 05:56:14.977358 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 05:56:14.980635 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 05:56:14.986602 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 05:56:14.990109 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 05:56:14.993418 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 05:56:14.996612 Total UI for P1: 0, mck2ui 16
6450 05:56:14.999974 best dqsien dly found for B0: ( 0, 14, 24)
6451 05:56:15.003191 Total UI for P1: 0, mck2ui 16
6452 05:56:15.007231 best dqsien dly found for B1: ( 0, 14, 24)
6453 05:56:15.010313 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6454 05:56:15.016548 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6455 05:56:15.016634
6456 05:56:15.020256 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6457 05:56:15.023080 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6458 05:56:15.026291 [Gating] SW calibration Done
6459 05:56:15.026380 ==
6460 05:56:15.029832 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 05:56:15.033394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 05:56:15.033524 ==
6463 05:56:15.036895 RX Vref Scan: 0
6464 05:56:15.036997
6465 05:56:15.037079 RX Vref 0 -> 0, step: 1
6466 05:56:15.037158
6467 05:56:15.039761 RX Delay -410 -> 252, step: 16
6468 05:56:15.043004 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6469 05:56:15.049921 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6470 05:56:15.053567 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6471 05:56:15.056535 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6472 05:56:15.060008 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6473 05:56:15.066963 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6474 05:56:15.070307 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6475 05:56:15.073277 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6476 05:56:15.077072 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6477 05:56:15.083519 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6478 05:56:15.087068 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6479 05:56:15.090444 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6480 05:56:15.093914 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6481 05:56:15.100569 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6482 05:56:15.104054 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6483 05:56:15.106823 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6484 05:56:15.107246 ==
6485 05:56:15.110275 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 05:56:15.113765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 05:56:15.117148 ==
6488 05:56:15.117570 DQS Delay:
6489 05:56:15.117906 DQS0 = 27, DQS1 = 35
6490 05:56:15.119991 DQM Delay:
6491 05:56:15.120460 DQM0 = 12, DQM1 = 11
6492 05:56:15.123122 DQ Delay:
6493 05:56:15.123542 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6494 05:56:15.126973 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6495 05:56:15.130070 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6496 05:56:15.133564 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6497 05:56:15.133987
6498 05:56:15.134319
6499 05:56:15.136724 ==
6500 05:56:15.137178 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 05:56:15.143450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 05:56:15.143873 ==
6503 05:56:15.144210
6504 05:56:15.144558
6505 05:56:15.146804 TX Vref Scan disable
6506 05:56:15.147224 == TX Byte 0 ==
6507 05:56:15.150283 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6508 05:56:15.156470 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6509 05:56:15.156893 == TX Byte 1 ==
6510 05:56:15.160062 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6511 05:56:15.163412 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6512 05:56:15.166947 ==
6513 05:56:15.170361 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 05:56:15.173154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 05:56:15.173578 ==
6516 05:56:15.173915
6517 05:56:15.174224
6518 05:56:15.176608 TX Vref Scan disable
6519 05:56:15.177030 == TX Byte 0 ==
6520 05:56:15.179909 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6521 05:56:15.186365 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6522 05:56:15.186787 == TX Byte 1 ==
6523 05:56:15.189725 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6524 05:56:15.193410 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6525 05:56:15.196588
6526 05:56:15.197005 [DATLAT]
6527 05:56:15.197341 Freq=400, CH0 RK1
6528 05:56:15.197657
6529 05:56:15.200000 DATLAT Default: 0xe
6530 05:56:15.200495 0, 0xFFFF, sum = 0
6531 05:56:15.202731 1, 0xFFFF, sum = 0
6532 05:56:15.203170 2, 0xFFFF, sum = 0
6533 05:56:15.206297 3, 0xFFFF, sum = 0
6534 05:56:15.209626 4, 0xFFFF, sum = 0
6535 05:56:15.210053 5, 0xFFFF, sum = 0
6536 05:56:15.213227 6, 0xFFFF, sum = 0
6537 05:56:15.213738 7, 0xFFFF, sum = 0
6538 05:56:15.216812 8, 0xFFFF, sum = 0
6539 05:56:15.217363 9, 0xFFFF, sum = 0
6540 05:56:15.219378 10, 0xFFFF, sum = 0
6541 05:56:15.219839 11, 0xFFFF, sum = 0
6542 05:56:15.222786 12, 0xFFFF, sum = 0
6543 05:56:15.223304 13, 0x0, sum = 1
6544 05:56:15.226287 14, 0x0, sum = 2
6545 05:56:15.226891 15, 0x0, sum = 3
6546 05:56:15.229775 16, 0x0, sum = 4
6547 05:56:15.230297 best_step = 14
6548 05:56:15.230878
6549 05:56:15.231436 ==
6550 05:56:15.233164 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 05:56:15.236574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 05:56:15.239749 ==
6553 05:56:15.240253 RX Vref Scan: 0
6554 05:56:15.240812
6555 05:56:15.243152 RX Vref 0 -> 0, step: 1
6556 05:56:15.243545
6557 05:56:15.244071 RX Delay -311 -> 252, step: 8
6558 05:56:15.251789 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6559 05:56:15.255005 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6560 05:56:15.258527 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6561 05:56:15.261979 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6562 05:56:15.268221 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6563 05:56:15.271680 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6564 05:56:15.275124 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6565 05:56:15.278690 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6566 05:56:15.284995 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6567 05:56:15.288528 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6568 05:56:15.291825 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6569 05:56:15.295338 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6570 05:56:15.301319 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6571 05:56:15.305181 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6572 05:56:15.308481 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6573 05:56:15.311691 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6574 05:56:15.315039 ==
6575 05:56:15.318430 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 05:56:15.321616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 05:56:15.322040 ==
6578 05:56:15.322380 DQS Delay:
6579 05:56:15.325136 DQS0 = 24, DQS1 = 32
6580 05:56:15.325560 DQM Delay:
6581 05:56:15.328054 DQM0 = 8, DQM1 = 10
6582 05:56:15.328524 DQ Delay:
6583 05:56:15.331416 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6584 05:56:15.334901 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6585 05:56:15.338475 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6586 05:56:15.341692 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6587 05:56:15.342113
6588 05:56:15.342446
6589 05:56:15.347957 [DQSOSCAuto] RK1, (LSB)MR18= 0xb153, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6590 05:56:15.351435 CH0 RK1: MR19=C0C, MR18=B153
6591 05:56:15.357818 CH0_RK1: MR19=0xC0C, MR18=0xB153, DQSOSC=387, MR23=63, INC=394, DEC=262
6592 05:56:15.361115 [RxdqsGatingPostProcess] freq 400
6593 05:56:15.364459 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6594 05:56:15.367842 best DQS0 dly(2T, 0.5T) = (0, 10)
6595 05:56:15.370995 best DQS1 dly(2T, 0.5T) = (0, 10)
6596 05:56:15.374669 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6597 05:56:15.377923 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6598 05:56:15.381596 best DQS0 dly(2T, 0.5T) = (0, 10)
6599 05:56:15.384878 best DQS1 dly(2T, 0.5T) = (0, 10)
6600 05:56:15.387698 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6601 05:56:15.391221 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6602 05:56:15.394649 Pre-setting of DQS Precalculation
6603 05:56:15.398076 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6604 05:56:15.398157 ==
6605 05:56:15.400810 Dram Type= 6, Freq= 0, CH_1, rank 0
6606 05:56:15.407423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 05:56:15.407505 ==
6608 05:56:15.411226 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6609 05:56:15.417419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6610 05:56:15.421266 [CA 0] Center 36 (8~64) winsize 57
6611 05:56:15.424545 [CA 1] Center 36 (8~64) winsize 57
6612 05:56:15.427711 [CA 2] Center 36 (8~64) winsize 57
6613 05:56:15.431023 [CA 3] Center 36 (8~64) winsize 57
6614 05:56:15.434483 [CA 4] Center 36 (8~64) winsize 57
6615 05:56:15.437827 [CA 5] Center 36 (8~64) winsize 57
6616 05:56:15.437936
6617 05:56:15.440613 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6618 05:56:15.440697
6619 05:56:15.444045 [CATrainingPosCal] consider 1 rank data
6620 05:56:15.447545 u2DelayCellTimex100 = 270/100 ps
6621 05:56:15.450825 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 05:56:15.453968 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 05:56:15.457422 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 05:56:15.460928 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 05:56:15.464422 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 05:56:15.467859 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 05:56:15.470557
6628 05:56:15.474191 CA PerBit enable=1, Macro0, CA PI delay=36
6629 05:56:15.474276
6630 05:56:15.477648 [CBTSetCACLKResult] CA Dly = 36
6631 05:56:15.477733 CS Dly: 1 (0~32)
6632 05:56:15.477818 ==
6633 05:56:15.480981 Dram Type= 6, Freq= 0, CH_1, rank 1
6634 05:56:15.483830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 05:56:15.483915 ==
6636 05:56:15.490874 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6637 05:56:15.497801 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6638 05:56:15.500494 [CA 0] Center 36 (8~64) winsize 57
6639 05:56:15.504084 [CA 1] Center 36 (8~64) winsize 57
6640 05:56:15.507539 [CA 2] Center 36 (8~64) winsize 57
6641 05:56:15.510393 [CA 3] Center 36 (8~64) winsize 57
6642 05:56:15.513783 [CA 4] Center 36 (8~64) winsize 57
6643 05:56:15.513867 [CA 5] Center 36 (8~64) winsize 57
6644 05:56:15.517067
6645 05:56:15.520859 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6646 05:56:15.520946
6647 05:56:15.524086 [CATrainingPosCal] consider 2 rank data
6648 05:56:15.527416 u2DelayCellTimex100 = 270/100 ps
6649 05:56:15.530675 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 05:56:15.533703 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 05:56:15.537630 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 05:56:15.540857 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 05:56:15.544111 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 05:56:15.547329 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 05:56:15.547412
6656 05:56:15.550731 CA PerBit enable=1, Macro0, CA PI delay=36
6657 05:56:15.550814
6658 05:56:15.554231 [CBTSetCACLKResult] CA Dly = 36
6659 05:56:15.556878 CS Dly: 1 (0~32)
6660 05:56:15.556961
6661 05:56:15.560770 ----->DramcWriteLeveling(PI) begin...
6662 05:56:15.560853 ==
6663 05:56:15.563853 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 05:56:15.567366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 05:56:15.567449 ==
6666 05:56:15.570734 Write leveling (Byte 0): 40 => 8
6667 05:56:15.573543 Write leveling (Byte 1): 40 => 8
6668 05:56:15.576906 DramcWriteLeveling(PI) end<-----
6669 05:56:15.577019
6670 05:56:15.577083 ==
6671 05:56:15.580423 Dram Type= 6, Freq= 0, CH_1, rank 0
6672 05:56:15.583722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 05:56:15.583817 ==
6674 05:56:15.587169 [Gating] SW mode calibration
6675 05:56:15.593516 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6676 05:56:15.600057 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6677 05:56:15.603287 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6678 05:56:15.606814 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6679 05:56:15.613494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6680 05:56:15.616846 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6681 05:56:15.620277 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 05:56:15.627057 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6683 05:56:15.630489 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 05:56:15.633913 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 05:56:15.639783 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 05:56:15.643539 Total UI for P1: 0, mck2ui 16
6687 05:56:15.646868 best dqsien dly found for B0: ( 0, 14, 24)
6688 05:56:15.646951 Total UI for P1: 0, mck2ui 16
6689 05:56:15.653476 best dqsien dly found for B1: ( 0, 14, 24)
6690 05:56:15.656653 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6691 05:56:15.660085 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6692 05:56:15.660167
6693 05:56:15.663425 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6694 05:56:15.666781 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6695 05:56:15.670083 [Gating] SW calibration Done
6696 05:56:15.670164 ==
6697 05:56:15.673505 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 05:56:15.676906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 05:56:15.676988 ==
6700 05:56:15.679694 RX Vref Scan: 0
6701 05:56:15.679776
6702 05:56:15.683060 RX Vref 0 -> 0, step: 1
6703 05:56:15.683141
6704 05:56:15.683206 RX Delay -410 -> 252, step: 16
6705 05:56:15.689984 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6706 05:56:15.692709 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6707 05:56:15.696184 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6708 05:56:15.699697 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6709 05:56:15.706464 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6710 05:56:15.709856 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6711 05:56:15.713358 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6712 05:56:15.716090 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6713 05:56:15.722679 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6714 05:56:15.726548 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6715 05:56:15.729691 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6716 05:56:15.732650 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6717 05:56:15.739721 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6718 05:56:15.742846 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6719 05:56:15.745989 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6720 05:56:15.752546 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6721 05:56:15.752628 ==
6722 05:56:15.755944 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 05:56:15.759479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 05:56:15.759561 ==
6725 05:56:15.759626 DQS Delay:
6726 05:56:15.762830 DQS0 = 27, DQS1 = 27
6727 05:56:15.762925 DQM Delay:
6728 05:56:15.766188 DQM0 = 11, DQM1 = 8
6729 05:56:15.766270 DQ Delay:
6730 05:56:15.769137 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6731 05:56:15.773031 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6732 05:56:15.776188 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6733 05:56:15.779558 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16
6734 05:56:15.779640
6735 05:56:15.779704
6736 05:56:15.779764 ==
6737 05:56:15.782883 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 05:56:15.785695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 05:56:15.785777 ==
6740 05:56:15.785843
6741 05:56:15.785903
6742 05:56:15.789049 TX Vref Scan disable
6743 05:56:15.789130 == TX Byte 0 ==
6744 05:56:15.795980 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 05:56:15.798875 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 05:56:15.798963 == TX Byte 1 ==
6747 05:56:15.805869 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 05:56:15.809415 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 05:56:15.809522 ==
6750 05:56:15.812188 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 05:56:15.815552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 05:56:15.815679 ==
6753 05:56:15.815778
6754 05:56:15.815868
6755 05:56:15.819093 TX Vref Scan disable
6756 05:56:15.819215 == TX Byte 0 ==
6757 05:56:15.826003 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 05:56:15.828777 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 05:56:15.828928 == TX Byte 1 ==
6760 05:56:15.835726 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 05:56:15.839212 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 05:56:15.839414
6763 05:56:15.839574 [DATLAT]
6764 05:56:15.842591 Freq=400, CH1 RK0
6765 05:56:15.842833
6766 05:56:15.843026 DATLAT Default: 0xf
6767 05:56:15.845716 0, 0xFFFF, sum = 0
6768 05:56:15.846017 1, 0xFFFF, sum = 0
6769 05:56:15.849255 2, 0xFFFF, sum = 0
6770 05:56:15.849555 3, 0xFFFF, sum = 0
6771 05:56:15.852679 4, 0xFFFF, sum = 0
6772 05:56:15.853195 5, 0xFFFF, sum = 0
6773 05:56:15.856366 6, 0xFFFF, sum = 0
6774 05:56:15.856793 7, 0xFFFF, sum = 0
6775 05:56:15.859761 8, 0xFFFF, sum = 0
6776 05:56:15.860213 9, 0xFFFF, sum = 0
6777 05:56:15.862957 10, 0xFFFF, sum = 0
6778 05:56:15.866075 11, 0xFFFF, sum = 0
6779 05:56:15.866502 12, 0xFFFF, sum = 0
6780 05:56:15.869210 13, 0x0, sum = 1
6781 05:56:15.869799 14, 0x0, sum = 2
6782 05:56:15.870183 15, 0x0, sum = 3
6783 05:56:15.872566 16, 0x0, sum = 4
6784 05:56:15.872976 best_step = 14
6785 05:56:15.873295
6786 05:56:15.875919 ==
6787 05:56:15.876466 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 05:56:15.882233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 05:56:15.882728 ==
6790 05:56:15.883175 RX Vref Scan: 1
6791 05:56:15.883565
6792 05:56:15.885888 RX Vref 0 -> 0, step: 1
6793 05:56:15.886321
6794 05:56:15.889147 RX Delay -295 -> 252, step: 8
6795 05:56:15.889717
6796 05:56:15.892434 Set Vref, RX VrefLevel [Byte0]: 53
6797 05:56:15.895829 [Byte1]: 53
6798 05:56:15.899103
6799 05:56:15.899879 Final RX Vref Byte 0 = 53 to rank0
6800 05:56:15.902482 Final RX Vref Byte 1 = 53 to rank0
6801 05:56:15.906010 Final RX Vref Byte 0 = 53 to rank1
6802 05:56:15.909482 Final RX Vref Byte 1 = 53 to rank1==
6803 05:56:15.912220 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 05:56:15.919282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 05:56:15.919834 ==
6806 05:56:15.920420 DQS Delay:
6807 05:56:15.922129 DQS0 = 32, DQS1 = 32
6808 05:56:15.922689 DQM Delay:
6809 05:56:15.923032 DQM0 = 13, DQM1 = 10
6810 05:56:15.925410 DQ Delay:
6811 05:56:15.928921 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6812 05:56:15.932553 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6813 05:56:15.932974 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6814 05:56:15.935295 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =20
6815 05:56:15.935715
6816 05:56:15.938716
6817 05:56:15.945534 [DQSOSCAuto] RK0, (LSB)MR18= 0x89c1, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6818 05:56:15.949092 CH1 RK0: MR19=C0C, MR18=89C1
6819 05:56:15.955247 CH1_RK0: MR19=0xC0C, MR18=0x89C1, DQSOSC=385, MR23=63, INC=398, DEC=265
6820 05:56:15.955668 ==
6821 05:56:15.958679 Dram Type= 6, Freq= 0, CH_1, rank 1
6822 05:56:15.961945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 05:56:15.962377 ==
6824 05:56:15.965128 [Gating] SW mode calibration
6825 05:56:15.971839 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6826 05:56:15.978449 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6827 05:56:15.981573 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6828 05:56:15.985250 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6829 05:56:15.991654 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6830 05:56:15.995174 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6831 05:56:15.997996 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6832 05:56:16.005072 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6833 05:56:16.007997 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 05:56:16.011705 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 05:56:16.014687 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 05:56:16.018408 Total UI for P1: 0, mck2ui 16
6837 05:56:16.021198 best dqsien dly found for B0: ( 0, 14, 24)
6838 05:56:16.024674 Total UI for P1: 0, mck2ui 16
6839 05:56:16.028072 best dqsien dly found for B1: ( 0, 14, 24)
6840 05:56:16.034490 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6841 05:56:16.037992 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6842 05:56:16.038073
6843 05:56:16.041402 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6844 05:56:16.044764 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6845 05:56:16.048396 [Gating] SW calibration Done
6846 05:56:16.048478 ==
6847 05:56:16.051076 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 05:56:16.054552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 05:56:16.054635 ==
6850 05:56:16.058157 RX Vref Scan: 0
6851 05:56:16.058239
6852 05:56:16.058304 RX Vref 0 -> 0, step: 1
6853 05:56:16.058364
6854 05:56:16.061696 RX Delay -410 -> 252, step: 16
6855 05:56:16.064459 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6856 05:56:16.071464 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6857 05:56:16.074259 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6858 05:56:16.077703 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6859 05:56:16.081227 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6860 05:56:16.088022 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6861 05:56:16.091198 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6862 05:56:16.094144 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6863 05:56:16.097986 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6864 05:56:16.104470 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6865 05:56:16.107951 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6866 05:56:16.111133 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6867 05:56:16.114465 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6868 05:56:16.120701 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6869 05:56:16.124174 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6870 05:56:16.127689 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6871 05:56:16.127771 ==
6872 05:56:16.130617 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 05:56:16.137139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 05:56:16.137222 ==
6875 05:56:16.137287 DQS Delay:
6876 05:56:16.140553 DQS0 = 35, DQS1 = 35
6877 05:56:16.140635 DQM Delay:
6878 05:56:16.140701 DQM0 = 18, DQM1 = 14
6879 05:56:16.143859 DQ Delay:
6880 05:56:16.147734 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6881 05:56:16.150437 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6882 05:56:16.153864 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6883 05:56:16.157344 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6884 05:56:16.157426
6885 05:56:16.157491
6886 05:56:16.157551 ==
6887 05:56:16.160867 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 05:56:16.164415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 05:56:16.164498 ==
6890 05:56:16.164563
6891 05:56:16.164622
6892 05:56:16.167206 TX Vref Scan disable
6893 05:56:16.167288 == TX Byte 0 ==
6894 05:56:16.170762 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6895 05:56:16.177054 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6896 05:56:16.177136 == TX Byte 1 ==
6897 05:56:16.180405 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6898 05:56:16.187364 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6899 05:56:16.187447 ==
6900 05:56:16.190860 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 05:56:16.193584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 05:56:16.193666 ==
6903 05:56:16.193731
6904 05:56:16.193791
6905 05:56:16.196939 TX Vref Scan disable
6906 05:56:16.197021 == TX Byte 0 ==
6907 05:56:16.203582 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6908 05:56:16.207377 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6909 05:56:16.207460 == TX Byte 1 ==
6910 05:56:16.213621 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6911 05:56:16.217064 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6912 05:56:16.217146
6913 05:56:16.217211 [DATLAT]
6914 05:56:16.220617 Freq=400, CH1 RK1
6915 05:56:16.220700
6916 05:56:16.220765 DATLAT Default: 0xe
6917 05:56:16.223413 0, 0xFFFF, sum = 0
6918 05:56:16.223497 1, 0xFFFF, sum = 0
6919 05:56:16.226958 2, 0xFFFF, sum = 0
6920 05:56:16.227041 3, 0xFFFF, sum = 0
6921 05:56:16.230510 4, 0xFFFF, sum = 0
6922 05:56:16.230593 5, 0xFFFF, sum = 0
6923 05:56:16.233754 6, 0xFFFF, sum = 0
6924 05:56:16.233837 7, 0xFFFF, sum = 0
6925 05:56:16.237003 8, 0xFFFF, sum = 0
6926 05:56:16.237086 9, 0xFFFF, sum = 0
6927 05:56:16.240170 10, 0xFFFF, sum = 0
6928 05:56:16.240253 11, 0xFFFF, sum = 0
6929 05:56:16.243943 12, 0xFFFF, sum = 0
6930 05:56:16.244025 13, 0x0, sum = 1
6931 05:56:16.247087 14, 0x0, sum = 2
6932 05:56:16.247170 15, 0x0, sum = 3
6933 05:56:16.250216 16, 0x0, sum = 4
6934 05:56:16.250300 best_step = 14
6935 05:56:16.250364
6936 05:56:16.250427 ==
6937 05:56:16.253723 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 05:56:16.260054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 05:56:16.260136 ==
6940 05:56:16.260201 RX Vref Scan: 0
6941 05:56:16.260261
6942 05:56:16.263815 RX Vref 0 -> 0, step: 1
6943 05:56:16.263897
6944 05:56:16.266835 RX Delay -311 -> 252, step: 8
6945 05:56:16.273552 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6946 05:56:16.276782 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6947 05:56:16.280080 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6948 05:56:16.283650 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6949 05:56:16.289849 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6950 05:56:16.293361 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6951 05:56:16.296863 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6952 05:56:16.300300 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6953 05:56:16.306718 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6954 05:56:16.310358 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6955 05:56:16.313069 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6956 05:56:16.316502 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6957 05:56:16.323207 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6958 05:56:16.326572 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6959 05:56:16.330019 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6960 05:56:16.333449 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6961 05:56:16.336924 ==
6962 05:56:16.339705 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 05:56:16.343204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 05:56:16.343401 ==
6965 05:56:16.343524 DQS Delay:
6966 05:56:16.346801 DQS0 = 28, DQS1 = 36
6967 05:56:16.346966 DQM Delay:
6968 05:56:16.350363 DQM0 = 9, DQM1 = 14
6969 05:56:16.350633 DQ Delay:
6970 05:56:16.352945 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6971 05:56:16.356439 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6972 05:56:16.359968 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6973 05:56:16.363444 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6974 05:56:16.363743
6975 05:56:16.363982
6976 05:56:16.369761 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc4d, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6977 05:56:16.373769 CH1 RK1: MR19=C0C, MR18=BC4D
6978 05:56:16.379876 CH1_RK1: MR19=0xC0C, MR18=0xBC4D, DQSOSC=386, MR23=63, INC=396, DEC=264
6979 05:56:16.383566 [RxdqsGatingPostProcess] freq 400
6980 05:56:16.386707 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6981 05:56:16.389945 best DQS0 dly(2T, 0.5T) = (0, 10)
6982 05:56:16.393186 best DQS1 dly(2T, 0.5T) = (0, 10)
6983 05:56:16.396398 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6984 05:56:16.399717 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6985 05:56:16.403417 best DQS0 dly(2T, 0.5T) = (0, 10)
6986 05:56:16.406657 best DQS1 dly(2T, 0.5T) = (0, 10)
6987 05:56:16.409755 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6988 05:56:16.413286 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6989 05:56:16.416617 Pre-setting of DQS Precalculation
6990 05:56:16.420008 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6991 05:56:16.429623 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6992 05:56:16.436874 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6993 05:56:16.437295
6994 05:56:16.437629
6995 05:56:16.439872 [Calibration Summary] 800 Mbps
6996 05:56:16.440328 CH 0, Rank 0
6997 05:56:16.442950 SW Impedance : PASS
6998 05:56:16.443366 DUTY Scan : NO K
6999 05:56:16.446277 ZQ Calibration : PASS
7000 05:56:16.449750 Jitter Meter : NO K
7001 05:56:16.450171 CBT Training : PASS
7002 05:56:16.453291 Write leveling : PASS
7003 05:56:16.456662 RX DQS gating : PASS
7004 05:56:16.457125 RX DQ/DQS(RDDQC) : PASS
7005 05:56:16.459971 TX DQ/DQS : PASS
7006 05:56:16.460430 RX DATLAT : PASS
7007 05:56:16.463471 RX DQ/DQS(Engine): PASS
7008 05:56:16.466285 TX OE : NO K
7009 05:56:16.466702 All Pass.
7010 05:56:16.467028
7011 05:56:16.467336 CH 0, Rank 1
7012 05:56:16.469837 SW Impedance : PASS
7013 05:56:16.473299 DUTY Scan : NO K
7014 05:56:16.473881 ZQ Calibration : PASS
7015 05:56:16.476037 Jitter Meter : NO K
7016 05:56:16.479486 CBT Training : PASS
7017 05:56:16.479902 Write leveling : NO K
7018 05:56:16.483059 RX DQS gating : PASS
7019 05:56:16.486625 RX DQ/DQS(RDDQC) : PASS
7020 05:56:16.487040 TX DQ/DQS : PASS
7021 05:56:16.489408 RX DATLAT : PASS
7022 05:56:16.492868 RX DQ/DQS(Engine): PASS
7023 05:56:16.493285 TX OE : NO K
7024 05:56:16.496250 All Pass.
7025 05:56:16.496711
7026 05:56:16.497068 CH 1, Rank 0
7027 05:56:16.499733 SW Impedance : PASS
7028 05:56:16.500214 DUTY Scan : NO K
7029 05:56:16.503106 ZQ Calibration : PASS
7030 05:56:16.506240 Jitter Meter : NO K
7031 05:56:16.506660 CBT Training : PASS
7032 05:56:16.509681 Write leveling : PASS
7033 05:56:16.513055 RX DQS gating : PASS
7034 05:56:16.513476 RX DQ/DQS(RDDQC) : PASS
7035 05:56:16.516004 TX DQ/DQS : PASS
7036 05:56:16.516461 RX DATLAT : PASS
7037 05:56:16.519660 RX DQ/DQS(Engine): PASS
7038 05:56:16.522970 TX OE : NO K
7039 05:56:16.523528 All Pass.
7040 05:56:16.523982
7041 05:56:16.524511 CH 1, Rank 1
7042 05:56:16.525734 SW Impedance : PASS
7043 05:56:16.529224 DUTY Scan : NO K
7044 05:56:16.529654 ZQ Calibration : PASS
7045 05:56:16.532846 Jitter Meter : NO K
7046 05:56:16.535893 CBT Training : PASS
7047 05:56:16.536359 Write leveling : NO K
7048 05:56:16.539388 RX DQS gating : PASS
7049 05:56:16.542736 RX DQ/DQS(RDDQC) : PASS
7050 05:56:16.543231 TX DQ/DQS : PASS
7051 05:56:16.545985 RX DATLAT : PASS
7052 05:56:16.549162 RX DQ/DQS(Engine): PASS
7053 05:56:16.549578 TX OE : NO K
7054 05:56:16.552666 All Pass.
7055 05:56:16.553088
7056 05:56:16.553422 DramC Write-DBI off
7057 05:56:16.555731 PER_BANK_REFRESH: Hybrid Mode
7058 05:56:16.556150 TX_TRACKING: ON
7059 05:56:16.565945 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7060 05:56:16.569448 [FAST_K] Save calibration result to emmc
7061 05:56:16.573042 dramc_set_vcore_voltage set vcore to 725000
7062 05:56:16.575769 Read voltage for 1600, 0
7063 05:56:16.576186 Vio18 = 0
7064 05:56:16.579280 Vcore = 725000
7065 05:56:16.579699 Vdram = 0
7066 05:56:16.580035 Vddq = 0
7067 05:56:16.582727 Vmddr = 0
7068 05:56:16.585531 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7069 05:56:16.592559 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7070 05:56:16.593176 MEM_TYPE=3, freq_sel=13
7071 05:56:16.595994 sv_algorithm_assistance_LP4_3733
7072 05:56:16.602157 ============ PULL DRAM RESETB DOWN ============
7073 05:56:16.605673 ========== PULL DRAM RESETB DOWN end =========
7074 05:56:16.609004 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7075 05:56:16.612457 ===================================
7076 05:56:16.615287 LPDDR4 DRAM CONFIGURATION
7077 05:56:16.618976 ===================================
7078 05:56:16.619402 EX_ROW_EN[0] = 0x0
7079 05:56:16.622467 EX_ROW_EN[1] = 0x0
7080 05:56:16.625789 LP4Y_EN = 0x0
7081 05:56:16.626428 WORK_FSP = 0x1
7082 05:56:16.629147 WL = 0x5
7083 05:56:16.629833 RL = 0x5
7084 05:56:16.632541 BL = 0x2
7085 05:56:16.633470 RPST = 0x0
7086 05:56:16.635427 RD_PRE = 0x0
7087 05:56:16.636186 WR_PRE = 0x1
7088 05:56:16.639029 WR_PST = 0x1
7089 05:56:16.639669 DBI_WR = 0x0
7090 05:56:16.642454 DBI_RD = 0x0
7091 05:56:16.642920 OTF = 0x1
7092 05:56:16.645382 ===================================
7093 05:56:16.648890 ===================================
7094 05:56:16.652411 ANA top config
7095 05:56:16.655363 ===================================
7096 05:56:16.655790 DLL_ASYNC_EN = 0
7097 05:56:16.658839 ALL_SLAVE_EN = 0
7098 05:56:16.661953 NEW_RANK_MODE = 1
7099 05:56:16.665259 DLL_IDLE_MODE = 1
7100 05:56:16.668599 LP45_APHY_COMB_EN = 1
7101 05:56:16.669490 TX_ODT_DIS = 0
7102 05:56:16.671776 NEW_8X_MODE = 1
7103 05:56:16.675312 ===================================
7104 05:56:16.678543 ===================================
7105 05:56:16.681895 data_rate = 3200
7106 05:56:16.685018 CKR = 1
7107 05:56:16.688250 DQ_P2S_RATIO = 8
7108 05:56:16.691569 ===================================
7109 05:56:16.691877 CA_P2S_RATIO = 8
7110 05:56:16.695034 DQ_CA_OPEN = 0
7111 05:56:16.698563 DQ_SEMI_OPEN = 0
7112 05:56:16.701980 CA_SEMI_OPEN = 0
7113 05:56:16.705393 CA_FULL_RATE = 0
7114 05:56:16.708115 DQ_CKDIV4_EN = 0
7115 05:56:16.708537 CA_CKDIV4_EN = 0
7116 05:56:16.711539 CA_PREDIV_EN = 0
7117 05:56:16.714825 PH8_DLY = 12
7118 05:56:16.718356 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7119 05:56:16.721988 DQ_AAMCK_DIV = 4
7120 05:56:16.725233 CA_AAMCK_DIV = 4
7121 05:56:16.725462 CA_ADMCK_DIV = 4
7122 05:56:16.727989 DQ_TRACK_CA_EN = 0
7123 05:56:16.731327 CA_PICK = 1600
7124 05:56:16.734890 CA_MCKIO = 1600
7125 05:56:16.738281 MCKIO_SEMI = 0
7126 05:56:16.741151 PLL_FREQ = 3068
7127 05:56:16.744621 DQ_UI_PI_RATIO = 32
7128 05:56:16.748013 CA_UI_PI_RATIO = 0
7129 05:56:16.748251 ===================================
7130 05:56:16.751510 ===================================
7131 05:56:16.755065 memory_type:LPDDR4
7132 05:56:16.758526 GP_NUM : 10
7133 05:56:16.758713 SRAM_EN : 1
7134 05:56:16.761308 MD32_EN : 0
7135 05:56:16.764810 ===================================
7136 05:56:16.768224 [ANA_INIT] >>>>>>>>>>>>>>
7137 05:56:16.771681 <<<<<< [CONFIGURE PHASE]: ANA_TX
7138 05:56:16.775012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7139 05:56:16.778188 ===================================
7140 05:56:16.778369 data_rate = 3200,PCW = 0X7600
7141 05:56:16.781128 ===================================
7142 05:56:16.784705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7143 05:56:16.791443 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7144 05:56:16.797800 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7145 05:56:16.801419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7146 05:56:16.804397 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7147 05:56:16.807745 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7148 05:56:16.811514 [ANA_INIT] flow start
7149 05:56:16.814460 [ANA_INIT] PLL >>>>>>>>
7150 05:56:16.814641 [ANA_INIT] PLL <<<<<<<<
7151 05:56:16.818002 [ANA_INIT] MIDPI >>>>>>>>
7152 05:56:16.821358 [ANA_INIT] MIDPI <<<<<<<<
7153 05:56:16.821540 [ANA_INIT] DLL >>>>>>>>
7154 05:56:16.824235 [ANA_INIT] DLL <<<<<<<<
7155 05:56:16.827592 [ANA_INIT] flow end
7156 05:56:16.831501 ============ LP4 DIFF to SE enter ============
7157 05:56:16.834917 ============ LP4 DIFF to SE exit ============
7158 05:56:16.837669 [ANA_INIT] <<<<<<<<<<<<<
7159 05:56:16.840944 [Flow] Enable top DCM control >>>>>
7160 05:56:16.844320 [Flow] Enable top DCM control <<<<<
7161 05:56:16.847908 Enable DLL master slave shuffle
7162 05:56:16.851342 ==============================================================
7163 05:56:16.854083 Gating Mode config
7164 05:56:16.861221 ==============================================================
7165 05:56:16.861340 Config description:
7166 05:56:16.870927 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7167 05:56:16.877993 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7168 05:56:16.880787 SELPH_MODE 0: By rank 1: By Phase
7169 05:56:16.887497 ==============================================================
7170 05:56:16.891051 GAT_TRACK_EN = 1
7171 05:56:16.893978 RX_GATING_MODE = 2
7172 05:56:16.897983 RX_GATING_TRACK_MODE = 2
7173 05:56:16.901334 SELPH_MODE = 1
7174 05:56:16.904210 PICG_EARLY_EN = 1
7175 05:56:16.907753 VALID_LAT_VALUE = 1
7176 05:56:16.911291 ==============================================================
7177 05:56:16.915045 Enter into Gating configuration >>>>
7178 05:56:16.917574 Exit from Gating configuration <<<<
7179 05:56:16.921233 Enter into DVFS_PRE_config >>>>>
7180 05:56:16.931214 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7181 05:56:16.934531 Exit from DVFS_PRE_config <<<<<
7182 05:56:16.937614 Enter into PICG configuration >>>>
7183 05:56:16.940758 Exit from PICG configuration <<<<
7184 05:56:16.944242 [RX_INPUT] configuration >>>>>
7185 05:56:16.947183 [RX_INPUT] configuration <<<<<
7186 05:56:16.954078 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7187 05:56:16.957478 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7188 05:56:16.964277 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7189 05:56:16.970646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7190 05:56:16.977621 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7191 05:56:16.984131 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7192 05:56:16.987658 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7193 05:56:16.990304 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7194 05:56:16.993941 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7195 05:56:17.000591 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7196 05:56:17.003696 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7197 05:56:17.007315 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7198 05:56:17.010344 ===================================
7199 05:56:17.013910 LPDDR4 DRAM CONFIGURATION
7200 05:56:17.017321 ===================================
7201 05:56:17.017681 EX_ROW_EN[0] = 0x0
7202 05:56:17.020680 EX_ROW_EN[1] = 0x0
7203 05:56:17.021021 LP4Y_EN = 0x0
7204 05:56:17.024042 WORK_FSP = 0x1
7205 05:56:17.026788 WL = 0x5
7206 05:56:17.027118 RL = 0x5
7207 05:56:17.030813 BL = 0x2
7208 05:56:17.031064 RPST = 0x0
7209 05:56:17.033558 RD_PRE = 0x0
7210 05:56:17.033817 WR_PRE = 0x1
7211 05:56:17.036873 WR_PST = 0x1
7212 05:56:17.037098 DBI_WR = 0x0
7213 05:56:17.040362 DBI_RD = 0x0
7214 05:56:17.040650 OTF = 0x1
7215 05:56:17.043758 ===================================
7216 05:56:17.047253 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7217 05:56:17.053987 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7218 05:56:17.056877 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7219 05:56:17.060028 ===================================
7220 05:56:17.063516 LPDDR4 DRAM CONFIGURATION
7221 05:56:17.066746 ===================================
7222 05:56:17.067047 EX_ROW_EN[0] = 0x10
7223 05:56:17.070241 EX_ROW_EN[1] = 0x0
7224 05:56:17.070538 LP4Y_EN = 0x0
7225 05:56:17.073877 WORK_FSP = 0x1
7226 05:56:17.074104 WL = 0x5
7227 05:56:17.077076 RL = 0x5
7228 05:56:17.077388 BL = 0x2
7229 05:56:17.079910 RPST = 0x0
7230 05:56:17.083316 RD_PRE = 0x0
7231 05:56:17.083602 WR_PRE = 0x1
7232 05:56:17.087201 WR_PST = 0x1
7233 05:56:17.087513 DBI_WR = 0x0
7234 05:56:17.089800 DBI_RD = 0x0
7235 05:56:17.089900 OTF = 0x1
7236 05:56:17.093267 ===================================
7237 05:56:17.100298 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7238 05:56:17.100421 ==
7239 05:56:17.103026 Dram Type= 6, Freq= 0, CH_0, rank 0
7240 05:56:17.106469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7241 05:56:17.106580 ==
7242 05:56:17.109696 [Duty_Offset_Calibration]
7243 05:56:17.112928 B0:2 B1:1 CA:1
7244 05:56:17.113035
7245 05:56:17.116671 [DutyScan_Calibration_Flow] k_type=0
7246 05:56:17.124757
7247 05:56:17.124877 ==CLK 0==
7248 05:56:17.128194 Final CLK duty delay cell = 0
7249 05:56:17.131696 [0] MAX Duty = 5156%(X100), DQS PI = 22
7250 05:56:17.135033 [0] MIN Duty = 4907%(X100), DQS PI = 0
7251 05:56:17.135168 [0] AVG Duty = 5031%(X100)
7252 05:56:17.138413
7253 05:56:17.141643 CH0 CLK Duty spec in!! Max-Min= 249%
7254 05:56:17.144640 [DutyScan_Calibration_Flow] ====Done====
7255 05:56:17.144735
7256 05:56:17.148089 [DutyScan_Calibration_Flow] k_type=1
7257 05:56:17.163907
7258 05:56:17.164060 ==DQS 0 ==
7259 05:56:17.167353 Final DQS duty delay cell = -4
7260 05:56:17.170796 [-4] MAX Duty = 5094%(X100), DQS PI = 24
7261 05:56:17.174203 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7262 05:56:17.176998 [-4] AVG Duty = 4875%(X100)
7263 05:56:17.177085
7264 05:56:17.177153 ==DQS 1 ==
7265 05:56:17.180432 Final DQS duty delay cell = 0
7266 05:56:17.183750 [0] MAX Duty = 5187%(X100), DQS PI = 10
7267 05:56:17.187152 [0] MIN Duty = 5031%(X100), DQS PI = 52
7268 05:56:17.190342 [0] AVG Duty = 5109%(X100)
7269 05:56:17.190435
7270 05:56:17.193579 CH0 DQS 0 Duty spec in!! Max-Min= 437%
7271 05:56:17.193667
7272 05:56:17.196845 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7273 05:56:17.199899 [DutyScan_Calibration_Flow] ====Done====
7274 05:56:17.200008
7275 05:56:17.203633 [DutyScan_Calibration_Flow] k_type=3
7276 05:56:17.221560
7277 05:56:17.221729 ==DQM 0 ==
7278 05:56:17.224918 Final DQM duty delay cell = 0
7279 05:56:17.227711 [0] MAX Duty = 5218%(X100), DQS PI = 34
7280 05:56:17.231454 [0] MIN Duty = 4907%(X100), DQS PI = 54
7281 05:56:17.234631 [0] AVG Duty = 5062%(X100)
7282 05:56:17.234867
7283 05:56:17.234951 ==DQM 1 ==
7284 05:56:17.237792 Final DQM duty delay cell = 0
7285 05:56:17.241697 [0] MAX Duty = 5187%(X100), DQS PI = 4
7286 05:56:17.244845 [0] MIN Duty = 5031%(X100), DQS PI = 48
7287 05:56:17.248123 [0] AVG Duty = 5109%(X100)
7288 05:56:17.248260
7289 05:56:17.251410 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7290 05:56:17.251499
7291 05:56:17.254821 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7292 05:56:17.258243 [DutyScan_Calibration_Flow] ====Done====
7293 05:56:17.258336
7294 05:56:17.260996 [DutyScan_Calibration_Flow] k_type=2
7295 05:56:17.278687
7296 05:56:17.278828 ==DQ 0 ==
7297 05:56:17.282050 Final DQ duty delay cell = 0
7298 05:56:17.285522 [0] MAX Duty = 5062%(X100), DQS PI = 26
7299 05:56:17.288845 [0] MIN Duty = 4907%(X100), DQS PI = 0
7300 05:56:17.288927 [0] AVG Duty = 4984%(X100)
7301 05:56:17.292191
7302 05:56:17.292331 ==DQ 1 ==
7303 05:56:17.295112 Final DQ duty delay cell = 0
7304 05:56:17.298494 [0] MAX Duty = 5156%(X100), DQS PI = 22
7305 05:56:17.301993 [0] MIN Duty = 4907%(X100), DQS PI = 34
7306 05:56:17.302075 [0] AVG Duty = 5031%(X100)
7307 05:56:17.302141
7308 05:56:17.308369 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7309 05:56:17.308452
7310 05:56:17.311784 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7311 05:56:17.315052 [DutyScan_Calibration_Flow] ====Done====
7312 05:56:17.315133 ==
7313 05:56:17.318313 Dram Type= 6, Freq= 0, CH_1, rank 0
7314 05:56:17.322063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7315 05:56:17.322166 ==
7316 05:56:17.324919 [Duty_Offset_Calibration]
7317 05:56:17.325001 B0:1 B1:0 CA:0
7318 05:56:17.325066
7319 05:56:17.328427 [DutyScan_Calibration_Flow] k_type=0
7320 05:56:17.338165
7321 05:56:17.338252 ==CLK 0==
7322 05:56:17.341626 Final CLK duty delay cell = -4
7323 05:56:17.344781 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7324 05:56:17.347814 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7325 05:56:17.351173 [-4] AVG Duty = 4922%(X100)
7326 05:56:17.351255
7327 05:56:17.354394 CH1 CLK Duty spec in!! Max-Min= 156%
7328 05:56:17.357670 [DutyScan_Calibration_Flow] ====Done====
7329 05:56:17.357752
7330 05:56:17.360991 [DutyScan_Calibration_Flow] k_type=1
7331 05:56:17.377868
7332 05:56:17.377956 ==DQS 0 ==
7333 05:56:17.381444 Final DQS duty delay cell = 0
7334 05:56:17.384854 [0] MAX Duty = 5094%(X100), DQS PI = 30
7335 05:56:17.388422 [0] MIN Duty = 4844%(X100), DQS PI = 0
7336 05:56:17.388506 [0] AVG Duty = 4969%(X100)
7337 05:56:17.391073
7338 05:56:17.391154 ==DQS 1 ==
7339 05:56:17.394536 Final DQS duty delay cell = 0
7340 05:56:17.397981 [0] MAX Duty = 5249%(X100), DQS PI = 16
7341 05:56:17.401453 [0] MIN Duty = 4938%(X100), DQS PI = 8
7342 05:56:17.401535 [0] AVG Duty = 5093%(X100)
7343 05:56:17.405000
7344 05:56:17.407749 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7345 05:56:17.407831
7346 05:56:17.411200 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7347 05:56:17.414594 [DutyScan_Calibration_Flow] ====Done====
7348 05:56:17.414682
7349 05:56:17.418142 [DutyScan_Calibration_Flow] k_type=3
7350 05:56:17.435095
7351 05:56:17.435298 ==DQM 0 ==
7352 05:56:17.438246 Final DQM duty delay cell = 0
7353 05:56:17.441366 [0] MAX Duty = 5187%(X100), DQS PI = 8
7354 05:56:17.445046 [0] MIN Duty = 4969%(X100), DQS PI = 48
7355 05:56:17.448164 [0] AVG Duty = 5078%(X100)
7356 05:56:17.448370
7357 05:56:17.448590 ==DQM 1 ==
7358 05:56:17.451434 Final DQM duty delay cell = 0
7359 05:56:17.454991 [0] MAX Duty = 5093%(X100), DQS PI = 16
7360 05:56:17.457911 [0] MIN Duty = 4907%(X100), DQS PI = 34
7361 05:56:17.461481 [0] AVG Duty = 5000%(X100)
7362 05:56:17.461735
7363 05:56:17.464769 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7364 05:56:17.465082
7365 05:56:17.468434 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7366 05:56:17.471656 [DutyScan_Calibration_Flow] ====Done====
7367 05:56:17.472073
7368 05:56:17.474544 [DutyScan_Calibration_Flow] k_type=2
7369 05:56:17.491454
7370 05:56:17.491875 ==DQ 0 ==
7371 05:56:17.494978 Final DQ duty delay cell = -4
7372 05:56:17.498333 [-4] MAX Duty = 5031%(X100), DQS PI = 8
7373 05:56:17.501082 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7374 05:56:17.504557 [-4] AVG Duty = 4953%(X100)
7375 05:56:17.504982
7376 05:56:17.505318 ==DQ 1 ==
7377 05:56:17.508053 Final DQ duty delay cell = 0
7378 05:56:17.511504 [0] MAX Duty = 5124%(X100), DQS PI = 16
7379 05:56:17.514224 [0] MIN Duty = 4938%(X100), DQS PI = 10
7380 05:56:17.517669 [0] AVG Duty = 5031%(X100)
7381 05:56:17.518089
7382 05:56:17.521104 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7383 05:56:17.521524
7384 05:56:17.524500 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7385 05:56:17.527850 [DutyScan_Calibration_Flow] ====Done====
7386 05:56:17.531302 nWR fixed to 30
7387 05:56:17.531725 [ModeRegInit_LP4] CH0 RK0
7388 05:56:17.534745 [ModeRegInit_LP4] CH0 RK1
7389 05:56:17.538243 [ModeRegInit_LP4] CH1 RK0
7390 05:56:17.541031 [ModeRegInit_LP4] CH1 RK1
7391 05:56:17.541452 match AC timing 5
7392 05:56:17.547964 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7393 05:56:17.550857 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7394 05:56:17.554218 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7395 05:56:17.560872 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7396 05:56:17.564119 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7397 05:56:17.564626 [MiockJmeterHQA]
7398 05:56:17.565071
7399 05:56:17.567311 [DramcMiockJmeter] u1RxGatingPI = 0
7400 05:56:17.570953 0 : 4255, 4030
7401 05:56:17.571398 4 : 4363, 4137
7402 05:56:17.573966 8 : 4252, 4027
7403 05:56:17.574444 12 : 4368, 4140
7404 05:56:17.574888 16 : 4252, 4027
7405 05:56:17.577359 20 : 4258, 4030
7406 05:56:17.577803 24 : 4253, 4026
7407 05:56:17.580568 28 : 4363, 4138
7408 05:56:17.581014 32 : 4363, 4137
7409 05:56:17.584103 36 : 4252, 4027
7410 05:56:17.584625 40 : 4253, 4027
7411 05:56:17.587647 44 : 4253, 4026
7412 05:56:17.588091 48 : 4252, 4027
7413 05:56:17.588614 52 : 4254, 4029
7414 05:56:17.590861 56 : 4363, 4138
7415 05:56:17.591308 60 : 4252, 4027
7416 05:56:17.593916 64 : 4252, 4027
7417 05:56:17.594362 68 : 4250, 4027
7418 05:56:17.597031 72 : 4252, 4029
7419 05:56:17.597476 76 : 4250, 4027
7420 05:56:17.600692 80 : 4360, 4138
7421 05:56:17.601140 84 : 4360, 4137
7422 05:56:17.601596 88 : 4250, 79
7423 05:56:17.603685 92 : 4361, 0
7424 05:56:17.604129 96 : 4249, 0
7425 05:56:17.607499 100 : 4250, 0
7426 05:56:17.607943 104 : 4250, 0
7427 05:56:17.608510 108 : 4250, 0
7428 05:56:17.610654 112 : 4252, 0
7429 05:56:17.611102 116 : 4250, 0
7430 05:56:17.611558 120 : 4250, 0
7431 05:56:17.613727 124 : 4252, 0
7432 05:56:17.614173 128 : 4250, 0
7433 05:56:17.617334 132 : 4361, 0
7434 05:56:17.617783 136 : 4250, 0
7435 05:56:17.618243 140 : 4361, 0
7436 05:56:17.620370 144 : 4360, 0
7437 05:56:17.620984 148 : 4250, 0
7438 05:56:17.623906 152 : 4250, 0
7439 05:56:17.624706 156 : 4250, 0
7440 05:56:17.625354 160 : 4250, 0
7441 05:56:17.627226 164 : 4252, 0
7442 05:56:17.627878 168 : 4252, 0
7443 05:56:17.629985 172 : 4250, 0
7444 05:56:17.630412 176 : 4252, 0
7445 05:56:17.630988 180 : 4250, 0
7446 05:56:17.633545 184 : 4361, 0
7447 05:56:17.634037 188 : 4360, 0
7448 05:56:17.636945 192 : 4250, 0
7449 05:56:17.637490 196 : 4360, 0
7450 05:56:17.637851 200 : 4250, 0
7451 05:56:17.640208 204 : 4250, 1104
7452 05:56:17.640660 208 : 4363, 4064
7453 05:56:17.643673 212 : 4250, 4026
7454 05:56:17.643934 216 : 4250, 4027
7455 05:56:17.646602 220 : 4250, 4027
7456 05:56:17.646834 224 : 4252, 4029
7457 05:56:17.650104 228 : 4250, 4026
7458 05:56:17.650290 232 : 4250, 4027
7459 05:56:17.653579 236 : 4360, 4138
7460 05:56:17.653737 240 : 4250, 4027
7461 05:56:17.653880 244 : 4250, 4026
7462 05:56:17.656457 248 : 4361, 4137
7463 05:56:17.656614 252 : 4250, 4027
7464 05:56:17.659950 256 : 4249, 4027
7465 05:56:17.660126 260 : 4363, 4140
7466 05:56:17.663206 264 : 4250, 4026
7467 05:56:17.663346 268 : 4250, 4027
7468 05:56:17.666691 272 : 4250, 4027
7469 05:56:17.666841 276 : 4249, 4027
7470 05:56:17.670214 280 : 4250, 4026
7471 05:56:17.670365 284 : 4250, 4027
7472 05:56:17.672914 288 : 4360, 4138
7473 05:56:17.673065 292 : 4250, 4027
7474 05:56:17.676279 296 : 4250, 4026
7475 05:56:17.676451 300 : 4361, 4137
7476 05:56:17.676571 304 : 4250, 4027
7477 05:56:17.679820 308 : 4249, 3981
7478 05:56:17.679974 312 : 4363, 2034
7479 05:56:17.680110
7480 05:56:17.682907 MIOCK jitter meter ch=0
7481 05:56:17.683143
7482 05:56:17.686127 1T = (312-88) = 224 dly cells
7483 05:56:17.693291 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7484 05:56:17.693412 ==
7485 05:56:17.696344 Dram Type= 6, Freq= 0, CH_0, rank 0
7486 05:56:17.699405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7487 05:56:17.699493 ==
7488 05:56:17.706268 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7489 05:56:17.709696 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7490 05:56:17.712955 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7491 05:56:17.719678 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7492 05:56:17.729071 [CA 0] Center 43 (13~73) winsize 61
7493 05:56:17.732122 [CA 1] Center 43 (13~73) winsize 61
7494 05:56:17.735560 [CA 2] Center 38 (8~68) winsize 61
7495 05:56:17.738437 [CA 3] Center 38 (9~67) winsize 59
7496 05:56:17.742066 [CA 4] Center 36 (7~66) winsize 60
7497 05:56:17.745553 [CA 5] Center 35 (6~65) winsize 60
7498 05:56:17.745975
7499 05:56:17.749053 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7500 05:56:17.749471
7501 05:56:17.751808 [CATrainingPosCal] consider 1 rank data
7502 05:56:17.755275 u2DelayCellTimex100 = 290/100 ps
7503 05:56:17.758759 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7504 05:56:17.765173 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7505 05:56:17.768441 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7506 05:56:17.771778 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7507 05:56:17.775396 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7508 05:56:17.778293 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7509 05:56:17.778714
7510 05:56:17.781643 CA PerBit enable=1, Macro0, CA PI delay=35
7511 05:56:17.782063
7512 05:56:17.785231 [CBTSetCACLKResult] CA Dly = 35
7513 05:56:17.788511 CS Dly: 9 (0~40)
7514 05:56:17.791793 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7515 05:56:17.795130 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7516 05:56:17.795551 ==
7517 05:56:17.798457 Dram Type= 6, Freq= 0, CH_0, rank 1
7518 05:56:17.802112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7519 05:56:17.805027 ==
7520 05:56:17.808370 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7521 05:56:17.811507 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7522 05:56:17.818197 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7523 05:56:17.824983 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7524 05:56:17.832111 [CA 0] Center 42 (12~73) winsize 62
7525 05:56:17.835719 [CA 1] Center 42 (12~73) winsize 62
7526 05:56:17.838536 [CA 2] Center 38 (8~68) winsize 61
7527 05:56:17.842002 [CA 3] Center 38 (8~68) winsize 61
7528 05:56:17.845485 [CA 4] Center 36 (6~66) winsize 61
7529 05:56:17.848821 [CA 5] Center 35 (5~65) winsize 61
7530 05:56:17.849243
7531 05:56:17.851989 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7532 05:56:17.852459
7533 05:56:17.855095 [CATrainingPosCal] consider 2 rank data
7534 05:56:17.858844 u2DelayCellTimex100 = 290/100 ps
7535 05:56:17.861804 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7536 05:56:17.868737 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7537 05:56:17.872123 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7538 05:56:17.875403 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7539 05:56:17.878574 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7540 05:56:17.882164 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7541 05:56:17.882547
7542 05:56:17.884931 CA PerBit enable=1, Macro0, CA PI delay=35
7543 05:56:17.885246
7544 05:56:17.888277 [CBTSetCACLKResult] CA Dly = 35
7545 05:56:17.891842 CS Dly: 10 (0~42)
7546 05:56:17.895247 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7547 05:56:17.898716 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7548 05:56:17.899140
7549 05:56:17.902125 ----->DramcWriteLeveling(PI) begin...
7550 05:56:17.902687 ==
7551 05:56:17.905342 Dram Type= 6, Freq= 0, CH_0, rank 0
7552 05:56:17.912153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 05:56:17.912762 ==
7554 05:56:17.915499 Write leveling (Byte 0): 35 => 35
7555 05:56:17.916188 Write leveling (Byte 1): 27 => 27
7556 05:56:17.918285 DramcWriteLeveling(PI) end<-----
7557 05:56:17.918830
7558 05:56:17.919254 ==
7559 05:56:17.921719 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 05:56:17.928168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 05:56:17.928834 ==
7562 05:56:17.932133 [Gating] SW mode calibration
7563 05:56:17.938692 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7564 05:56:17.942097 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7565 05:56:17.948187 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7566 05:56:17.951626 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 05:56:17.955031 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 05:56:17.961757 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7569 05:56:17.965084 1 4 16 | B1->B0 | 2424 3535 | 0 1 | (0 0) (1 1)
7570 05:56:17.968230 1 4 20 | B1->B0 | 3333 3737 | 1 0 | (1 1) (0 0)
7571 05:56:17.975150 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7572 05:56:17.978293 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 05:56:17.981835 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7574 05:56:17.988199 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7575 05:56:17.991553 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7576 05:56:17.995069 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
7577 05:56:17.998474 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 1)
7578 05:56:18.004877 1 5 20 | B1->B0 | 2727 2423 | 0 1 | (1 0) (0 0)
7579 05:56:18.008081 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (1 0) (1 1)
7580 05:56:18.011495 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 05:56:18.018011 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 05:56:18.021413 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7583 05:56:18.024813 1 6 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
7584 05:56:18.031486 1 6 12 | B1->B0 | 2323 4544 | 0 1 | (0 0) (0 0)
7585 05:56:18.034743 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (1 1) (0 0)
7586 05:56:18.038105 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7587 05:56:18.044860 1 6 24 | B1->B0 | 4646 4646 | 0 1 | (0 0) (0 0)
7588 05:56:18.047923 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 05:56:18.051274 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 05:56:18.057970 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 05:56:18.061482 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7592 05:56:18.064889 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7593 05:56:18.071050 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7594 05:56:18.074772 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7595 05:56:18.078178 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 05:56:18.084833 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 05:56:18.087887 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 05:56:18.091456 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 05:56:18.098208 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 05:56:18.100947 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 05:56:18.104491 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 05:56:18.107909 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 05:56:18.114667 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 05:56:18.118049 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 05:56:18.121208 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 05:56:18.127572 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 05:56:18.130915 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 05:56:18.134505 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7609 05:56:18.141201 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7610 05:56:18.144373 Total UI for P1: 0, mck2ui 16
7611 05:56:18.147975 best dqsien dly found for B0: ( 1, 9, 12)
7612 05:56:18.150618 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7613 05:56:18.153942 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7614 05:56:18.160642 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 05:56:18.164445 Total UI for P1: 0, mck2ui 16
7616 05:56:18.167664 best dqsien dly found for B1: ( 1, 9, 22)
7617 05:56:18.170968 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7618 05:56:18.174276 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7619 05:56:18.174575
7620 05:56:18.177671 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7621 05:56:18.181230 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7622 05:56:18.184095 [Gating] SW calibration Done
7623 05:56:18.184420 ==
7624 05:56:18.187407 Dram Type= 6, Freq= 0, CH_0, rank 0
7625 05:56:18.190998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7626 05:56:18.191299 ==
7627 05:56:18.194341 RX Vref Scan: 0
7628 05:56:18.194639
7629 05:56:18.194877 RX Vref 0 -> 0, step: 1
7630 05:56:18.197729
7631 05:56:18.198120 RX Delay 0 -> 252, step: 8
7632 05:56:18.200800 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7633 05:56:18.207725 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7634 05:56:18.211182 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7635 05:56:18.214608 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7636 05:56:18.217443 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7637 05:56:18.220877 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7638 05:56:18.227494 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7639 05:56:18.231014 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7640 05:56:18.234232 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7641 05:56:18.238705 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7642 05:56:18.240671 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7643 05:56:18.247070 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7644 05:56:18.250376 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7645 05:56:18.253688 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7646 05:56:18.256984 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7647 05:56:18.260500 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7648 05:56:18.263971 ==
7649 05:56:18.267435 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 05:56:18.270813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 05:56:18.271110 ==
7652 05:56:18.271352 DQS Delay:
7653 05:56:18.274188 DQS0 = 0, DQS1 = 0
7654 05:56:18.274501 DQM Delay:
7655 05:56:18.277507 DQM0 = 136, DQM1 = 130
7656 05:56:18.277920 DQ Delay:
7657 05:56:18.280266 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7658 05:56:18.283961 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7659 05:56:18.286958 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7660 05:56:18.290231 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7661 05:56:18.290545
7662 05:56:18.290866
7663 05:56:18.291167 ==
7664 05:56:18.293862 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 05:56:18.300523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 05:56:18.300610 ==
7667 05:56:18.300698
7668 05:56:18.300780
7669 05:56:18.300860 TX Vref Scan disable
7670 05:56:18.303988 == TX Byte 0 ==
7671 05:56:18.307383 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7672 05:56:18.314111 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7673 05:56:18.314197 == TX Byte 1 ==
7674 05:56:18.317138 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7675 05:56:18.323800 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7676 05:56:18.323889 ==
7677 05:56:18.327065 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 05:56:18.330373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 05:56:18.330484 ==
7680 05:56:18.343598
7681 05:56:18.346957 TX Vref early break, caculate TX vref
7682 05:56:18.350310 TX Vref=16, minBit 7, minWin=22, winSum=378
7683 05:56:18.353956 TX Vref=18, minBit 4, minWin=23, winSum=387
7684 05:56:18.357197 TX Vref=20, minBit 0, minWin=24, winSum=399
7685 05:56:18.360452 TX Vref=22, minBit 1, minWin=24, winSum=405
7686 05:56:18.363788 TX Vref=24, minBit 7, minWin=24, winSum=416
7687 05:56:18.370052 TX Vref=26, minBit 2, minWin=25, winSum=422
7688 05:56:18.373568 TX Vref=28, minBit 1, minWin=25, winSum=423
7689 05:56:18.377228 TX Vref=30, minBit 6, minWin=24, winSum=415
7690 05:56:18.380650 TX Vref=32, minBit 1, minWin=24, winSum=405
7691 05:56:18.383373 TX Vref=34, minBit 6, minWin=23, winSum=392
7692 05:56:18.390153 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 28
7693 05:56:18.390237
7694 05:56:18.393359 Final TX Range 0 Vref 28
7695 05:56:18.393441
7696 05:56:18.393509 ==
7697 05:56:18.397360 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 05:56:18.400734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 05:56:18.400818 ==
7700 05:56:18.400883
7701 05:56:18.400944
7702 05:56:18.403560 TX Vref Scan disable
7703 05:56:18.410569 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7704 05:56:18.410706 == TX Byte 0 ==
7705 05:56:18.413745 u2DelayCellOfst[0]=10 cells (3 PI)
7706 05:56:18.416664 u2DelayCellOfst[1]=16 cells (5 PI)
7707 05:56:18.420121 u2DelayCellOfst[2]=10 cells (3 PI)
7708 05:56:18.423559 u2DelayCellOfst[3]=10 cells (3 PI)
7709 05:56:18.426885 u2DelayCellOfst[4]=6 cells (2 PI)
7710 05:56:18.430147 u2DelayCellOfst[5]=0 cells (0 PI)
7711 05:56:18.433279 u2DelayCellOfst[6]=16 cells (5 PI)
7712 05:56:18.433401 u2DelayCellOfst[7]=13 cells (4 PI)
7713 05:56:18.440004 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7714 05:56:18.443499 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7715 05:56:18.443609 == TX Byte 1 ==
7716 05:56:18.446837 u2DelayCellOfst[8]=0 cells (0 PI)
7717 05:56:18.450311 u2DelayCellOfst[9]=0 cells (0 PI)
7718 05:56:18.453154 u2DelayCellOfst[10]=6 cells (2 PI)
7719 05:56:18.456999 u2DelayCellOfst[11]=3 cells (1 PI)
7720 05:56:18.460187 u2DelayCellOfst[12]=6 cells (2 PI)
7721 05:56:18.463363 u2DelayCellOfst[13]=6 cells (2 PI)
7722 05:56:18.466691 u2DelayCellOfst[14]=10 cells (3 PI)
7723 05:56:18.469900 u2DelayCellOfst[15]=6 cells (2 PI)
7724 05:56:18.473641 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7725 05:56:18.477133 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7726 05:56:18.479858 DramC Write-DBI on
7727 05:56:18.479972 ==
7728 05:56:18.483293 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 05:56:18.486661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 05:56:18.486748 ==
7731 05:56:18.486821
7732 05:56:18.486896
7733 05:56:18.490116 TX Vref Scan disable
7734 05:56:18.493529 == TX Byte 0 ==
7735 05:56:18.497021 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7736 05:56:18.500341 == TX Byte 1 ==
7737 05:56:18.503144 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7738 05:56:18.503251 DramC Write-DBI off
7739 05:56:18.503356
7740 05:56:18.506725 [DATLAT]
7741 05:56:18.506847 Freq=1600, CH0 RK0
7742 05:56:18.506941
7743 05:56:18.509998 DATLAT Default: 0xf
7744 05:56:18.510107 0, 0xFFFF, sum = 0
7745 05:56:18.513415 1, 0xFFFF, sum = 0
7746 05:56:18.513501 2, 0xFFFF, sum = 0
7747 05:56:18.516466 3, 0xFFFF, sum = 0
7748 05:56:18.516547 4, 0xFFFF, sum = 0
7749 05:56:18.519938 5, 0xFFFF, sum = 0
7750 05:56:18.520056 6, 0xFFFF, sum = 0
7751 05:56:18.523360 7, 0xFFFF, sum = 0
7752 05:56:18.523469 8, 0xFFFF, sum = 0
7753 05:56:18.526830 9, 0xFFFF, sum = 0
7754 05:56:18.529643 10, 0xFFFF, sum = 0
7755 05:56:18.529754 11, 0xFFFF, sum = 0
7756 05:56:18.533174 12, 0xFFFF, sum = 0
7757 05:56:18.533291 13, 0xFFFF, sum = 0
7758 05:56:18.536581 14, 0x0, sum = 1
7759 05:56:18.536688 15, 0x0, sum = 2
7760 05:56:18.539851 16, 0x0, sum = 3
7761 05:56:18.539967 17, 0x0, sum = 4
7762 05:56:18.540067 best_step = 15
7763 05:56:18.543171
7764 05:56:18.543285 ==
7765 05:56:18.546272 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 05:56:18.549694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 05:56:18.549777 ==
7768 05:56:18.549863 RX Vref Scan: 1
7769 05:56:18.549944
7770 05:56:18.553207 Set Vref Range= 24 -> 127
7771 05:56:18.553300
7772 05:56:18.556463 RX Vref 24 -> 127, step: 1
7773 05:56:18.556547
7774 05:56:18.559848 RX Delay 19 -> 252, step: 4
7775 05:56:18.559939
7776 05:56:18.562561 Set Vref, RX VrefLevel [Byte0]: 24
7777 05:56:18.566031 [Byte1]: 24
7778 05:56:18.566113
7779 05:56:18.569279 Set Vref, RX VrefLevel [Byte0]: 25
7780 05:56:18.572968 [Byte1]: 25
7781 05:56:18.573051
7782 05:56:18.576255 Set Vref, RX VrefLevel [Byte0]: 26
7783 05:56:18.579533 [Byte1]: 26
7784 05:56:18.582865
7785 05:56:18.582947 Set Vref, RX VrefLevel [Byte0]: 27
7786 05:56:18.586307 [Byte1]: 27
7787 05:56:18.590470
7788 05:56:18.590552 Set Vref, RX VrefLevel [Byte0]: 28
7789 05:56:18.593825 [Byte1]: 28
7790 05:56:18.598068
7791 05:56:18.598150 Set Vref, RX VrefLevel [Byte0]: 29
7792 05:56:18.601537 [Byte1]: 29
7793 05:56:18.605675
7794 05:56:18.605758 Set Vref, RX VrefLevel [Byte0]: 30
7795 05:56:18.609181 [Byte1]: 30
7796 05:56:18.613356
7797 05:56:18.613440 Set Vref, RX VrefLevel [Byte0]: 31
7798 05:56:18.616997 [Byte1]: 31
7799 05:56:18.621134
7800 05:56:18.621215 Set Vref, RX VrefLevel [Byte0]: 32
7801 05:56:18.624489 [Byte1]: 32
7802 05:56:18.628350
7803 05:56:18.628445 Set Vref, RX VrefLevel [Byte0]: 33
7804 05:56:18.632092 [Byte1]: 33
7805 05:56:18.636052
7806 05:56:18.636134 Set Vref, RX VrefLevel [Byte0]: 34
7807 05:56:18.639655 [Byte1]: 34
7808 05:56:18.643747
7809 05:56:18.643828 Set Vref, RX VrefLevel [Byte0]: 35
7810 05:56:18.647152 [Byte1]: 35
7811 05:56:18.651259
7812 05:56:18.651344 Set Vref, RX VrefLevel [Byte0]: 36
7813 05:56:18.654797 [Byte1]: 36
7814 05:56:18.658700
7815 05:56:18.658809 Set Vref, RX VrefLevel [Byte0]: 37
7816 05:56:18.662261 [Byte1]: 37
7817 05:56:18.666487
7818 05:56:18.666605 Set Vref, RX VrefLevel [Byte0]: 38
7819 05:56:18.669577 [Byte1]: 38
7820 05:56:18.673888
7821 05:56:18.673978 Set Vref, RX VrefLevel [Byte0]: 39
7822 05:56:18.677354 [Byte1]: 39
7823 05:56:18.681361
7824 05:56:18.681469 Set Vref, RX VrefLevel [Byte0]: 40
7825 05:56:18.684985 [Byte1]: 40
7826 05:56:18.689024
7827 05:56:18.689107 Set Vref, RX VrefLevel [Byte0]: 41
7828 05:56:18.692158 [Byte1]: 41
7829 05:56:18.696798
7830 05:56:18.696895 Set Vref, RX VrefLevel [Byte0]: 42
7831 05:56:18.700393 [Byte1]: 42
7832 05:56:18.704460
7833 05:56:18.704566 Set Vref, RX VrefLevel [Byte0]: 43
7834 05:56:18.707292 [Byte1]: 43
7835 05:56:18.712112
7836 05:56:18.712215 Set Vref, RX VrefLevel [Byte0]: 44
7837 05:56:18.714906 [Byte1]: 44
7838 05:56:18.719763
7839 05:56:18.719847 Set Vref, RX VrefLevel [Byte0]: 45
7840 05:56:18.722517 [Byte1]: 45
7841 05:56:18.726728
7842 05:56:18.726814 Set Vref, RX VrefLevel [Byte0]: 46
7843 05:56:18.730225 [Byte1]: 46
7844 05:56:18.734418
7845 05:56:18.734532 Set Vref, RX VrefLevel [Byte0]: 47
7846 05:56:18.738628 [Byte1]: 47
7847 05:56:18.742234
7848 05:56:18.742330 Set Vref, RX VrefLevel [Byte0]: 48
7849 05:56:18.745285 [Byte1]: 48
7850 05:56:18.749580
7851 05:56:18.749678 Set Vref, RX VrefLevel [Byte0]: 49
7852 05:56:18.752939 [Byte1]: 49
7853 05:56:18.757080
7854 05:56:18.757164 Set Vref, RX VrefLevel [Byte0]: 50
7855 05:56:18.760505 [Byte1]: 50
7856 05:56:18.764785
7857 05:56:18.764870 Set Vref, RX VrefLevel [Byte0]: 51
7858 05:56:18.768171 [Byte1]: 51
7859 05:56:18.772257
7860 05:56:18.772355 Set Vref, RX VrefLevel [Byte0]: 52
7861 05:56:18.775526 [Byte1]: 52
7862 05:56:18.779859
7863 05:56:18.779942 Set Vref, RX VrefLevel [Byte0]: 53
7864 05:56:18.783728 [Byte1]: 53
7865 05:56:18.787408
7866 05:56:18.787492 Set Vref, RX VrefLevel [Byte0]: 54
7867 05:56:18.790682 [Byte1]: 54
7868 05:56:18.795520
7869 05:56:18.795604 Set Vref, RX VrefLevel [Byte0]: 55
7870 05:56:18.798623 [Byte1]: 55
7871 05:56:18.802410
7872 05:56:18.802496 Set Vref, RX VrefLevel [Byte0]: 56
7873 05:56:18.806128 [Byte1]: 56
7874 05:56:18.810523
7875 05:56:18.810613 Set Vref, RX VrefLevel [Byte0]: 57
7876 05:56:18.813809 [Byte1]: 57
7877 05:56:18.817636
7878 05:56:18.817721 Set Vref, RX VrefLevel [Byte0]: 58
7879 05:56:18.820990 [Byte1]: 58
7880 05:56:18.825100
7881 05:56:18.825190 Set Vref, RX VrefLevel [Byte0]: 59
7882 05:56:18.828894 [Byte1]: 59
7883 05:56:18.833068
7884 05:56:18.833152 Set Vref, RX VrefLevel [Byte0]: 60
7885 05:56:18.836567 [Byte1]: 60
7886 05:56:18.840582
7887 05:56:18.840665 Set Vref, RX VrefLevel [Byte0]: 61
7888 05:56:18.844039 [Byte1]: 61
7889 05:56:18.848085
7890 05:56:18.848185 Set Vref, RX VrefLevel [Byte0]: 62
7891 05:56:18.851600 [Byte1]: 62
7892 05:56:18.855643
7893 05:56:18.855725 Set Vref, RX VrefLevel [Byte0]: 63
7894 05:56:18.858683 [Byte1]: 63
7895 05:56:18.863205
7896 05:56:18.863346 Set Vref, RX VrefLevel [Byte0]: 64
7897 05:56:18.866672 [Byte1]: 64
7898 05:56:18.870832
7899 05:56:18.870914 Set Vref, RX VrefLevel [Byte0]: 65
7900 05:56:18.874214 [Byte1]: 65
7901 05:56:18.878080
7902 05:56:18.878162 Set Vref, RX VrefLevel [Byte0]: 66
7903 05:56:18.881568 [Byte1]: 66
7904 05:56:18.886293
7905 05:56:18.886412 Set Vref, RX VrefLevel [Byte0]: 67
7906 05:56:18.889645 [Byte1]: 67
7907 05:56:18.893764
7908 05:56:18.893850 Set Vref, RX VrefLevel [Byte0]: 68
7909 05:56:18.897064 [Byte1]: 68
7910 05:56:18.901133
7911 05:56:18.901215 Set Vref, RX VrefLevel [Byte0]: 69
7912 05:56:18.904438 [Byte1]: 69
7913 05:56:18.908507
7914 05:56:18.911695 Set Vref, RX VrefLevel [Byte0]: 70
7915 05:56:18.915241 [Byte1]: 70
7916 05:56:18.915323
7917 05:56:18.918432 Set Vref, RX VrefLevel [Byte0]: 71
7918 05:56:18.921729 [Byte1]: 71
7919 05:56:18.921828
7920 05:56:18.925176 Set Vref, RX VrefLevel [Byte0]: 72
7921 05:56:18.928207 [Byte1]: 72
7922 05:56:18.928315
7923 05:56:18.931469 Set Vref, RX VrefLevel [Byte0]: 73
7924 05:56:18.934904 [Byte1]: 73
7925 05:56:18.939081
7926 05:56:18.939173 Set Vref, RX VrefLevel [Byte0]: 74
7927 05:56:18.942600 [Byte1]: 74
7928 05:56:18.946845
7929 05:56:18.946929 Set Vref, RX VrefLevel [Byte0]: 75
7930 05:56:18.949646 [Byte1]: 75
7931 05:56:18.954458
7932 05:56:18.954540 Set Vref, RX VrefLevel [Byte0]: 76
7933 05:56:18.957364 [Byte1]: 76
7934 05:56:18.961506
7935 05:56:18.961589 Set Vref, RX VrefLevel [Byte0]: 77
7936 05:56:18.964897 [Byte1]: 77
7937 05:56:18.969565
7938 05:56:18.969648 Final RX Vref Byte 0 = 57 to rank0
7939 05:56:18.972790 Final RX Vref Byte 1 = 60 to rank0
7940 05:56:18.976091 Final RX Vref Byte 0 = 57 to rank1
7941 05:56:18.979081 Final RX Vref Byte 1 = 60 to rank1==
7942 05:56:18.982394 Dram Type= 6, Freq= 0, CH_0, rank 0
7943 05:56:18.989307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7944 05:56:18.989392 ==
7945 05:56:18.989459 DQS Delay:
7946 05:56:18.989520 DQS0 = 0, DQS1 = 0
7947 05:56:18.992715 DQM Delay:
7948 05:56:18.992827 DQM0 = 133, DQM1 = 127
7949 05:56:18.996151 DQ Delay:
7950 05:56:18.998860 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
7951 05:56:19.002887 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138
7952 05:56:19.006122 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7953 05:56:19.009577 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
7954 05:56:19.009679
7955 05:56:19.009777
7956 05:56:19.009866
7957 05:56:19.012450 [DramC_TX_OE_Calibration] TA2
7958 05:56:19.015836 Original DQ_B0 (3 6) =30, OEN = 27
7959 05:56:19.019266 Original DQ_B1 (3 6) =30, OEN = 27
7960 05:56:19.022428 24, 0x0, End_B0=24 End_B1=24
7961 05:56:19.022530 25, 0x0, End_B0=25 End_B1=25
7962 05:56:19.026121 26, 0x0, End_B0=26 End_B1=26
7963 05:56:19.029554 27, 0x0, End_B0=27 End_B1=27
7964 05:56:19.032811 28, 0x0, End_B0=28 End_B1=28
7965 05:56:19.032893 29, 0x0, End_B0=29 End_B1=29
7966 05:56:19.035489 30, 0x0, End_B0=30 End_B1=30
7967 05:56:19.039066 31, 0x4141, End_B0=30 End_B1=30
7968 05:56:19.042245 Byte0 end_step=30 best_step=27
7969 05:56:19.045505 Byte1 end_step=30 best_step=27
7970 05:56:19.049007 Byte0 TX OE(2T, 0.5T) = (3, 3)
7971 05:56:19.049089 Byte1 TX OE(2T, 0.5T) = (3, 3)
7972 05:56:19.052542
7973 05:56:19.052624
7974 05:56:19.059555 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
7975 05:56:19.062478 CH0 RK0: MR19=303, MR18=241F
7976 05:56:19.069340 CH0_RK0: MR19=0x303, MR18=0x241F, DQSOSC=391, MR23=63, INC=24, DEC=16
7977 05:56:19.069441
7978 05:56:19.072799 ----->DramcWriteLeveling(PI) begin...
7979 05:56:19.072873 ==
7980 05:56:19.075569 Dram Type= 6, Freq= 0, CH_0, rank 1
7981 05:56:19.078951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7982 05:56:19.079035 ==
7983 05:56:19.082438 Write leveling (Byte 0): 35 => 35
7984 05:56:19.085679 Write leveling (Byte 1): 29 => 29
7985 05:56:19.088910 DramcWriteLeveling(PI) end<-----
7986 05:56:19.089000
7987 05:56:19.089095 ==
7988 05:56:19.092104 Dram Type= 6, Freq= 0, CH_0, rank 1
7989 05:56:19.095967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 05:56:19.096052 ==
7991 05:56:19.099039 [Gating] SW mode calibration
7992 05:56:19.105488 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7993 05:56:19.111984 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7994 05:56:19.115356 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 05:56:19.118695 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 05:56:19.125697 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 05:56:19.129102 1 4 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7998 05:56:19.132238 1 4 16 | B1->B0 | 2c2c 3636 | 0 0 | (0 0) (0 0)
7999 05:56:19.138843 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 05:56:19.142383 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8001 05:56:19.145846 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8002 05:56:19.152310 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8003 05:56:19.155687 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8004 05:56:19.158462 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8005 05:56:19.165308 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
8006 05:56:19.168699 1 5 16 | B1->B0 | 2f2f 2525 | 1 0 | (0 0) (0 0)
8007 05:56:19.172208 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8008 05:56:19.178990 1 5 24 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8009 05:56:19.181763 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 05:56:19.185126 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8011 05:56:19.192143 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8012 05:56:19.195572 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 05:56:19.198827 1 6 12 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
8014 05:56:19.205144 1 6 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8015 05:56:19.208441 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8016 05:56:19.211851 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 05:56:19.214988 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8018 05:56:19.222013 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 05:56:19.225285 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 05:56:19.228541 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 05:56:19.235486 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8022 05:56:19.238149 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8023 05:56:19.242078 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 05:56:19.248172 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 05:56:19.251899 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 05:56:19.255351 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 05:56:19.261814 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 05:56:19.265080 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 05:56:19.268412 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 05:56:19.275283 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 05:56:19.278088 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 05:56:19.281414 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 05:56:19.288254 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 05:56:19.291699 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 05:56:19.295117 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 05:56:19.301445 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 05:56:19.304778 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8038 05:56:19.308064 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8039 05:56:19.314623 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 05:56:19.314730 Total UI for P1: 0, mck2ui 16
8041 05:56:19.321818 best dqsien dly found for B0: ( 1, 9, 14)
8042 05:56:19.321931 Total UI for P1: 0, mck2ui 16
8043 05:56:19.324912 best dqsien dly found for B1: ( 1, 9, 14)
8044 05:56:19.331626 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8045 05:56:19.334976 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8046 05:56:19.335081
8047 05:56:19.338157 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8048 05:56:19.341539 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8049 05:56:19.344735 [Gating] SW calibration Done
8050 05:56:19.344836 ==
8051 05:56:19.348151 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 05:56:19.351618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 05:56:19.351723 ==
8054 05:56:19.354937 RX Vref Scan: 0
8055 05:56:19.355036
8056 05:56:19.355130 RX Vref 0 -> 0, step: 1
8057 05:56:19.355222
8058 05:56:19.358428 RX Delay 0 -> 252, step: 8
8059 05:56:19.361227 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8060 05:56:19.368033 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8061 05:56:19.371396 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8062 05:56:19.374657 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8063 05:56:19.378027 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8064 05:56:19.381450 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8065 05:56:19.387701 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8066 05:56:19.390970 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8067 05:56:19.394542 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8068 05:56:19.397985 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8069 05:56:19.401407 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8070 05:56:19.407691 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8071 05:56:19.410971 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8072 05:56:19.414454 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8073 05:56:19.417606 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8074 05:56:19.421528 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8075 05:56:19.421632 ==
8076 05:56:19.424816 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 05:56:19.430996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 05:56:19.431102 ==
8079 05:56:19.431198 DQS Delay:
8080 05:56:19.434313 DQS0 = 0, DQS1 = 0
8081 05:56:19.434415 DQM Delay:
8082 05:56:19.437714 DQM0 = 136, DQM1 = 129
8083 05:56:19.437819 DQ Delay:
8084 05:56:19.441191 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8085 05:56:19.444669 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8086 05:56:19.447878 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8087 05:56:19.451032 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8088 05:56:19.451132
8089 05:56:19.451227
8090 05:56:19.451316 ==
8091 05:56:19.454563 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 05:56:19.461101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 05:56:19.461211 ==
8094 05:56:19.461312
8095 05:56:19.461403
8096 05:56:19.461493 TX Vref Scan disable
8097 05:56:19.464362 == TX Byte 0 ==
8098 05:56:19.467905 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8099 05:56:19.474086 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8100 05:56:19.474189 == TX Byte 1 ==
8101 05:56:19.477431 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8102 05:56:19.484139 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8103 05:56:19.484244 ==
8104 05:56:19.487298 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 05:56:19.490784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 05:56:19.490890 ==
8107 05:56:19.503917
8108 05:56:19.507480 TX Vref early break, caculate TX vref
8109 05:56:19.510824 TX Vref=16, minBit 1, minWin=22, winSum=386
8110 05:56:19.514318 TX Vref=18, minBit 1, minWin=22, winSum=396
8111 05:56:19.517206 TX Vref=20, minBit 1, minWin=23, winSum=408
8112 05:56:19.520733 TX Vref=22, minBit 0, minWin=24, winSum=412
8113 05:56:19.523926 TX Vref=24, minBit 1, minWin=24, winSum=419
8114 05:56:19.530425 TX Vref=26, minBit 1, minWin=25, winSum=430
8115 05:56:19.533819 TX Vref=28, minBit 1, minWin=25, winSum=422
8116 05:56:19.537222 TX Vref=30, minBit 4, minWin=25, winSum=418
8117 05:56:19.540584 TX Vref=32, minBit 7, minWin=24, winSum=410
8118 05:56:19.544140 TX Vref=34, minBit 0, minWin=23, winSum=397
8119 05:56:19.551043 [TxChooseVref] Worse bit 1, Min win 25, Win sum 430, Final Vref 26
8120 05:56:19.551127
8121 05:56:19.553731 Final TX Range 0 Vref 26
8122 05:56:19.553814
8123 05:56:19.553880 ==
8124 05:56:19.557319 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 05:56:19.560725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 05:56:19.560808 ==
8127 05:56:19.560874
8128 05:56:19.560935
8129 05:56:19.563982 TX Vref Scan disable
8130 05:56:19.571018 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8131 05:56:19.571100 == TX Byte 0 ==
8132 05:56:19.574037 u2DelayCellOfst[0]=10 cells (3 PI)
8133 05:56:19.577582 u2DelayCellOfst[1]=13 cells (4 PI)
8134 05:56:19.580567 u2DelayCellOfst[2]=10 cells (3 PI)
8135 05:56:19.584168 u2DelayCellOfst[3]=10 cells (3 PI)
8136 05:56:19.587222 u2DelayCellOfst[4]=6 cells (2 PI)
8137 05:56:19.590884 u2DelayCellOfst[5]=0 cells (0 PI)
8138 05:56:19.590967 u2DelayCellOfst[6]=13 cells (4 PI)
8139 05:56:19.594320 u2DelayCellOfst[7]=13 cells (4 PI)
8140 05:56:19.600699 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8141 05:56:19.603599 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8142 05:56:19.603682 == TX Byte 1 ==
8143 05:56:19.606942 u2DelayCellOfst[8]=3 cells (1 PI)
8144 05:56:19.610508 u2DelayCellOfst[9]=0 cells (0 PI)
8145 05:56:19.613910 u2DelayCellOfst[10]=6 cells (2 PI)
8146 05:56:19.617378 u2DelayCellOfst[11]=6 cells (2 PI)
8147 05:56:19.620121 u2DelayCellOfst[12]=10 cells (3 PI)
8148 05:56:19.623688 u2DelayCellOfst[13]=10 cells (3 PI)
8149 05:56:19.627091 u2DelayCellOfst[14]=13 cells (4 PI)
8150 05:56:19.630458 u2DelayCellOfst[15]=10 cells (3 PI)
8151 05:56:19.633760 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8152 05:56:19.640788 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8153 05:56:19.640884 DramC Write-DBI on
8154 05:56:19.640964 ==
8155 05:56:19.643981 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 05:56:19.647330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 05:56:19.647410 ==
8158 05:56:19.650545
8159 05:56:19.650652
8160 05:56:19.650747 TX Vref Scan disable
8161 05:56:19.653956 == TX Byte 0 ==
8162 05:56:19.656755 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8163 05:56:19.660300 == TX Byte 1 ==
8164 05:56:19.663788 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8165 05:56:19.663888 DramC Write-DBI off
8166 05:56:19.666547
8167 05:56:19.666647 [DATLAT]
8168 05:56:19.666739 Freq=1600, CH0 RK1
8169 05:56:19.666809
8170 05:56:19.670084 DATLAT Default: 0xf
8171 05:56:19.670158 0, 0xFFFF, sum = 0
8172 05:56:19.673602 1, 0xFFFF, sum = 0
8173 05:56:19.673699 2, 0xFFFF, sum = 0
8174 05:56:19.676960 3, 0xFFFF, sum = 0
8175 05:56:19.680412 4, 0xFFFF, sum = 0
8176 05:56:19.680517 5, 0xFFFF, sum = 0
8177 05:56:19.683329 6, 0xFFFF, sum = 0
8178 05:56:19.683438 7, 0xFFFF, sum = 0
8179 05:56:19.687167 8, 0xFFFF, sum = 0
8180 05:56:19.687302 9, 0xFFFF, sum = 0
8181 05:56:19.689872 10, 0xFFFF, sum = 0
8182 05:56:19.689973 11, 0xFFFF, sum = 0
8183 05:56:19.693854 12, 0xFFFF, sum = 0
8184 05:56:19.693956 13, 0xFFFF, sum = 0
8185 05:56:19.696833 14, 0x0, sum = 1
8186 05:56:19.696936 15, 0x0, sum = 2
8187 05:56:19.700051 16, 0x0, sum = 3
8188 05:56:19.700157 17, 0x0, sum = 4
8189 05:56:19.703691 best_step = 15
8190 05:56:19.703789
8191 05:56:19.703878 ==
8192 05:56:19.706693 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 05:56:19.710119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 05:56:19.710222 ==
8195 05:56:19.710318 RX Vref Scan: 0
8196 05:56:19.713062
8197 05:56:19.713159 RX Vref 0 -> 0, step: 1
8198 05:56:19.713248
8199 05:56:19.716677 RX Delay 19 -> 252, step: 4
8200 05:56:19.719971 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8201 05:56:19.726751 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8202 05:56:19.730358 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8203 05:56:19.733235 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8204 05:56:19.736693 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8205 05:56:19.740105 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8206 05:56:19.746825 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8207 05:56:19.750058 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8208 05:56:19.753314 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8209 05:56:19.756487 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8210 05:56:19.760160 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8211 05:56:19.763543 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8212 05:56:19.769888 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8213 05:56:19.773241 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8214 05:56:19.776766 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8215 05:56:19.780123 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8216 05:56:19.780225 ==
8217 05:56:19.783760 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 05:56:19.789887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 05:56:19.789996 ==
8220 05:56:19.790091 DQS Delay:
8221 05:56:19.793513 DQS0 = 0, DQS1 = 0
8222 05:56:19.793594 DQM Delay:
8223 05:56:19.796822 DQM0 = 135, DQM1 = 127
8224 05:56:19.796896 DQ Delay:
8225 05:56:19.800292 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8226 05:56:19.803007 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =142
8227 05:56:19.806476 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8228 05:56:19.809991 DQ12 =134, DQ13 =132, DQ14 =136, DQ15 =134
8229 05:56:19.810098
8230 05:56:19.810190
8231 05:56:19.810282
8232 05:56:19.813423 [DramC_TX_OE_Calibration] TA2
8233 05:56:19.816821 Original DQ_B0 (3 6) =30, OEN = 27
8234 05:56:19.820123 Original DQ_B1 (3 6) =30, OEN = 27
8235 05:56:19.823420 24, 0x0, End_B0=24 End_B1=24
8236 05:56:19.823546 25, 0x0, End_B0=25 End_B1=25
8237 05:56:19.826796 26, 0x0, End_B0=26 End_B1=26
8238 05:56:19.829754 27, 0x0, End_B0=27 End_B1=27
8239 05:56:19.833277 28, 0x0, End_B0=28 End_B1=28
8240 05:56:19.836650 29, 0x0, End_B0=29 End_B1=29
8241 05:56:19.836755 30, 0x0, End_B0=30 End_B1=30
8242 05:56:19.839782 31, 0x4141, End_B0=30 End_B1=30
8243 05:56:19.842892 Byte0 end_step=30 best_step=27
8244 05:56:19.846795 Byte1 end_step=30 best_step=27
8245 05:56:19.849560 Byte0 TX OE(2T, 0.5T) = (3, 3)
8246 05:56:19.853117 Byte1 TX OE(2T, 0.5T) = (3, 3)
8247 05:56:19.853193
8248 05:56:19.853258
8249 05:56:19.859996 [DQSOSCAuto] RK1, (LSB)MR18= 0x210a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
8250 05:56:19.863178 CH0 RK1: MR19=303, MR18=210A
8251 05:56:19.869626 CH0_RK1: MR19=0x303, MR18=0x210A, DQSOSC=393, MR23=63, INC=23, DEC=15
8252 05:56:19.872953 [RxdqsGatingPostProcess] freq 1600
8253 05:56:19.876432 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8254 05:56:19.880019 best DQS0 dly(2T, 0.5T) = (1, 1)
8255 05:56:19.882694 best DQS1 dly(2T, 0.5T) = (1, 1)
8256 05:56:19.886180 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8257 05:56:19.889747 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8258 05:56:19.893344 best DQS0 dly(2T, 0.5T) = (1, 1)
8259 05:56:19.896065 best DQS1 dly(2T, 0.5T) = (1, 1)
8260 05:56:19.899512 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8261 05:56:19.902994 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8262 05:56:19.906517 Pre-setting of DQS Precalculation
8263 05:56:19.909756 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8264 05:56:19.909840 ==
8265 05:56:19.912606 Dram Type= 6, Freq= 0, CH_1, rank 0
8266 05:56:19.916053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8267 05:56:19.919369 ==
8268 05:56:19.922737 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8269 05:56:19.926232 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8270 05:56:19.933196 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8271 05:56:19.936045 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8272 05:56:19.946250 [CA 0] Center 41 (12~71) winsize 60
8273 05:56:19.949636 [CA 1] Center 42 (13~71) winsize 59
8274 05:56:19.953433 [CA 2] Center 38 (9~68) winsize 60
8275 05:56:19.956553 [CA 3] Center 37 (9~66) winsize 58
8276 05:56:19.959664 [CA 4] Center 37 (8~67) winsize 60
8277 05:56:19.963292 [CA 5] Center 37 (8~66) winsize 59
8278 05:56:19.963376
8279 05:56:19.966824 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8280 05:56:19.966908
8281 05:56:19.969638 [CATrainingPosCal] consider 1 rank data
8282 05:56:19.972917 u2DelayCellTimex100 = 290/100 ps
8283 05:56:19.976645 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8284 05:56:19.983599 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8285 05:56:19.986508 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8286 05:56:19.989598 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8287 05:56:19.993037 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8288 05:56:19.996556 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8289 05:56:19.996641
8290 05:56:20.000008 CA PerBit enable=1, Macro0, CA PI delay=37
8291 05:56:20.000092
8292 05:56:20.003438 [CBTSetCACLKResult] CA Dly = 37
8293 05:56:20.003528 CS Dly: 11 (0~42)
8294 05:56:20.009684 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8295 05:56:20.013130 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8296 05:56:20.013215 ==
8297 05:56:20.016499 Dram Type= 6, Freq= 0, CH_1, rank 1
8298 05:56:20.019970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8299 05:56:20.020077 ==
8300 05:56:20.026722 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8301 05:56:20.030170 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8302 05:56:20.036527 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8303 05:56:20.039983 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8304 05:56:20.049532 [CA 0] Center 42 (13~72) winsize 60
8305 05:56:20.053113 [CA 1] Center 42 (13~72) winsize 60
8306 05:56:20.056511 [CA 2] Center 39 (9~69) winsize 61
8307 05:56:20.059834 [CA 3] Center 38 (9~68) winsize 60
8308 05:56:20.062680 [CA 4] Center 39 (9~69) winsize 61
8309 05:56:20.066347 [CA 5] Center 37 (8~67) winsize 60
8310 05:56:20.066460
8311 05:56:20.069825 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8312 05:56:20.069901
8313 05:56:20.073134 [CATrainingPosCal] consider 2 rank data
8314 05:56:20.076431 u2DelayCellTimex100 = 290/100 ps
8315 05:56:20.079552 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8316 05:56:20.086594 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8317 05:56:20.089809 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8318 05:56:20.092845 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8319 05:56:20.096241 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8320 05:56:20.099636 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8321 05:56:20.099741
8322 05:56:20.102877 CA PerBit enable=1, Macro0, CA PI delay=37
8323 05:56:20.102980
8324 05:56:20.106167 [CBTSetCACLKResult] CA Dly = 37
8325 05:56:20.109651 CS Dly: 12 (0~45)
8326 05:56:20.112772 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8327 05:56:20.116223 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8328 05:56:20.116357
8329 05:56:20.119609 ----->DramcWriteLeveling(PI) begin...
8330 05:56:20.119709 ==
8331 05:56:20.122889 Dram Type= 6, Freq= 0, CH_1, rank 0
8332 05:56:20.126123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8333 05:56:20.129423 ==
8334 05:56:20.129526 Write leveling (Byte 0): 25 => 25
8335 05:56:20.132865 Write leveling (Byte 1): 28 => 28
8336 05:56:20.136249 DramcWriteLeveling(PI) end<-----
8337 05:56:20.136377
8338 05:56:20.136442 ==
8339 05:56:20.139688 Dram Type= 6, Freq= 0, CH_1, rank 0
8340 05:56:20.145841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 05:56:20.145927 ==
8342 05:56:20.145991 [Gating] SW mode calibration
8343 05:56:20.156121 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8344 05:56:20.159790 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8345 05:56:20.163147 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 05:56:20.169379 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 05:56:20.172883 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8348 05:56:20.176303 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8349 05:56:20.182684 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 05:56:20.186335 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 05:56:20.189591 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 05:56:20.195779 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 05:56:20.199401 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 05:56:20.202766 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 05:56:20.209424 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
8356 05:56:20.212533 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
8357 05:56:20.215642 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 05:56:20.222771 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 05:56:20.225689 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 05:56:20.229185 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 05:56:20.235781 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 05:56:20.239031 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 05:56:20.242518 1 6 8 | B1->B0 | 2323 3131 | 1 0 | (0 0) (0 0)
8364 05:56:20.249282 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 05:56:20.252404 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 05:56:20.255750 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 05:56:20.262702 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 05:56:20.266197 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 05:56:20.269003 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 05:56:20.275753 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 05:56:20.279293 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8372 05:56:20.282800 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8373 05:56:20.286264 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 05:56:20.292402 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 05:56:20.295676 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 05:56:20.299130 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 05:56:20.305565 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 05:56:20.308990 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 05:56:20.312402 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 05:56:20.318746 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 05:56:20.322102 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 05:56:20.325568 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 05:56:20.332228 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 05:56:20.335678 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 05:56:20.339141 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 05:56:20.345743 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 05:56:20.349042 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8388 05:56:20.352205 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8389 05:56:20.358771 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 05:56:20.358855 Total UI for P1: 0, mck2ui 16
8391 05:56:20.365089 best dqsien dly found for B0: ( 1, 9, 10)
8392 05:56:20.365173 Total UI for P1: 0, mck2ui 16
8393 05:56:20.372259 best dqsien dly found for B1: ( 1, 9, 10)
8394 05:56:20.375519 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8395 05:56:20.378884 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8396 05:56:20.378966
8397 05:56:20.381816 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8398 05:56:20.385417 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8399 05:56:20.388580 [Gating] SW calibration Done
8400 05:56:20.388684 ==
8401 05:56:20.391866 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 05:56:20.395311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 05:56:20.395415 ==
8404 05:56:20.398803 RX Vref Scan: 0
8405 05:56:20.398881
8406 05:56:20.398945 RX Vref 0 -> 0, step: 1
8407 05:56:20.399006
8408 05:56:20.402037 RX Delay 0 -> 252, step: 8
8409 05:56:20.405507 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8410 05:56:20.411866 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8411 05:56:20.415381 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8412 05:56:20.418154 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8413 05:56:20.421613 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8414 05:56:20.425023 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8415 05:56:20.431723 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8416 05:56:20.435017 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8417 05:56:20.438308 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8418 05:56:20.441673 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8419 05:56:20.445090 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8420 05:56:20.452007 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8421 05:56:20.455379 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8422 05:56:20.458599 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8423 05:56:20.461814 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8424 05:56:20.465281 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8425 05:56:20.468707 ==
8426 05:56:20.468784 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 05:56:20.474962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 05:56:20.475071 ==
8429 05:56:20.475157 DQS Delay:
8430 05:56:20.478418 DQS0 = 0, DQS1 = 0
8431 05:56:20.478527 DQM Delay:
8432 05:56:20.481854 DQM0 = 136, DQM1 = 132
8433 05:56:20.481939 DQ Delay:
8434 05:56:20.485260 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8435 05:56:20.488741 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8436 05:56:20.491805 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8437 05:56:20.494895 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8438 05:56:20.494978
8439 05:56:20.495044
8440 05:56:20.495104 ==
8441 05:56:20.499151 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 05:56:20.504902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 05:56:20.504985 ==
8444 05:56:20.505051
8445 05:56:20.505112
8446 05:56:20.505171 TX Vref Scan disable
8447 05:56:20.508453 == TX Byte 0 ==
8448 05:56:20.512010 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8449 05:56:20.518641 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8450 05:56:20.518725 == TX Byte 1 ==
8451 05:56:20.521959 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8452 05:56:20.528175 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8453 05:56:20.528258 ==
8454 05:56:20.531637 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 05:56:20.535046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 05:56:20.535156 ==
8457 05:56:20.547262
8458 05:56:20.550716 TX Vref early break, caculate TX vref
8459 05:56:20.553590 TX Vref=16, minBit 9, minWin=22, winSum=378
8460 05:56:20.556984 TX Vref=18, minBit 1, minWin=23, winSum=384
8461 05:56:20.560425 TX Vref=20, minBit 1, minWin=23, winSum=395
8462 05:56:20.563883 TX Vref=22, minBit 6, minWin=24, winSum=406
8463 05:56:20.567203 TX Vref=24, minBit 0, minWin=25, winSum=415
8464 05:56:20.573718 TX Vref=26, minBit 0, minWin=25, winSum=421
8465 05:56:20.577117 TX Vref=28, minBit 0, minWin=25, winSum=426
8466 05:56:20.580714 TX Vref=30, minBit 0, minWin=25, winSum=418
8467 05:56:20.583978 TX Vref=32, minBit 2, minWin=24, winSum=410
8468 05:56:20.587449 TX Vref=34, minBit 0, minWin=24, winSum=401
8469 05:56:20.593662 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8470 05:56:20.593745
8471 05:56:20.597213 Final TX Range 0 Vref 28
8472 05:56:20.597296
8473 05:56:20.597361 ==
8474 05:56:20.599974 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 05:56:20.603503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 05:56:20.603586 ==
8477 05:56:20.603652
8478 05:56:20.603748
8479 05:56:20.606787 TX Vref Scan disable
8480 05:56:20.613638 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8481 05:56:20.613723 == TX Byte 0 ==
8482 05:56:20.616543 u2DelayCellOfst[0]=16 cells (5 PI)
8483 05:56:20.620432 u2DelayCellOfst[1]=10 cells (3 PI)
8484 05:56:20.623594 u2DelayCellOfst[2]=0 cells (0 PI)
8485 05:56:20.626635 u2DelayCellOfst[3]=3 cells (1 PI)
8486 05:56:20.630580 u2DelayCellOfst[4]=10 cells (3 PI)
8487 05:56:20.633663 u2DelayCellOfst[5]=16 cells (5 PI)
8488 05:56:20.636800 u2DelayCellOfst[6]=16 cells (5 PI)
8489 05:56:20.636883 u2DelayCellOfst[7]=3 cells (1 PI)
8490 05:56:20.643785 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8491 05:56:20.647346 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8492 05:56:20.647430 == TX Byte 1 ==
8493 05:56:20.650605 u2DelayCellOfst[8]=0 cells (0 PI)
8494 05:56:20.653804 u2DelayCellOfst[9]=0 cells (0 PI)
8495 05:56:20.656671 u2DelayCellOfst[10]=10 cells (3 PI)
8496 05:56:20.660048 u2DelayCellOfst[11]=0 cells (0 PI)
8497 05:56:20.663299 u2DelayCellOfst[12]=10 cells (3 PI)
8498 05:56:20.666767 u2DelayCellOfst[13]=13 cells (4 PI)
8499 05:56:20.670297 u2DelayCellOfst[14]=13 cells (4 PI)
8500 05:56:20.673629 u2DelayCellOfst[15]=13 cells (4 PI)
8501 05:56:20.676973 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8502 05:56:20.683618 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8503 05:56:20.683697 DramC Write-DBI on
8504 05:56:20.683793 ==
8505 05:56:20.686357 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 05:56:20.689816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 05:56:20.693321 ==
8508 05:56:20.693403
8509 05:56:20.693468
8510 05:56:20.693528 TX Vref Scan disable
8511 05:56:20.696853 == TX Byte 0 ==
8512 05:56:20.700426 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8513 05:56:20.703292 == TX Byte 1 ==
8514 05:56:20.706737 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8515 05:56:20.706824 DramC Write-DBI off
8516 05:56:20.710177
8517 05:56:20.710270 [DATLAT]
8518 05:56:20.710337 Freq=1600, CH1 RK0
8519 05:56:20.710401
8520 05:56:20.713061 DATLAT Default: 0xf
8521 05:56:20.713144 0, 0xFFFF, sum = 0
8522 05:56:20.716539 1, 0xFFFF, sum = 0
8523 05:56:20.716623 2, 0xFFFF, sum = 0
8524 05:56:20.720059 3, 0xFFFF, sum = 0
8525 05:56:20.723565 4, 0xFFFF, sum = 0
8526 05:56:20.723653 5, 0xFFFF, sum = 0
8527 05:56:20.726286 6, 0xFFFF, sum = 0
8528 05:56:20.726370 7, 0xFFFF, sum = 0
8529 05:56:20.729721 8, 0xFFFF, sum = 0
8530 05:56:20.729804 9, 0xFFFF, sum = 0
8531 05:56:20.733074 10, 0xFFFF, sum = 0
8532 05:56:20.733159 11, 0xFFFF, sum = 0
8533 05:56:20.736342 12, 0xFFFF, sum = 0
8534 05:56:20.736489 13, 0xFFFF, sum = 0
8535 05:56:20.739793 14, 0x0, sum = 1
8536 05:56:20.739869 15, 0x0, sum = 2
8537 05:56:20.743460 16, 0x0, sum = 3
8538 05:56:20.743543 17, 0x0, sum = 4
8539 05:56:20.746744 best_step = 15
8540 05:56:20.746826
8541 05:56:20.746891 ==
8542 05:56:20.749896 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 05:56:20.753031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 05:56:20.753114 ==
8545 05:56:20.753180 RX Vref Scan: 1
8546 05:56:20.756600
8547 05:56:20.756681 Set Vref Range= 24 -> 127
8548 05:56:20.756747
8549 05:56:20.759581 RX Vref 24 -> 127, step: 1
8550 05:56:20.759662
8551 05:56:20.763168 RX Delay 27 -> 252, step: 4
8552 05:56:20.763275
8553 05:56:20.766451 Set Vref, RX VrefLevel [Byte0]: 24
8554 05:56:20.769595 [Byte1]: 24
8555 05:56:20.769677
8556 05:56:20.773432 Set Vref, RX VrefLevel [Byte0]: 25
8557 05:56:20.776458 [Byte1]: 25
8558 05:56:20.776541
8559 05:56:20.779912 Set Vref, RX VrefLevel [Byte0]: 26
8560 05:56:20.782780 [Byte1]: 26
8561 05:56:20.786750
8562 05:56:20.786832 Set Vref, RX VrefLevel [Byte0]: 27
8563 05:56:20.789969 [Byte1]: 27
8564 05:56:20.793994
8565 05:56:20.794076 Set Vref, RX VrefLevel [Byte0]: 28
8566 05:56:20.797469 [Byte1]: 28
8567 05:56:20.802094
8568 05:56:20.802176 Set Vref, RX VrefLevel [Byte0]: 29
8569 05:56:20.804898 [Byte1]: 29
8570 05:56:20.809659
8571 05:56:20.809740 Set Vref, RX VrefLevel [Byte0]: 30
8572 05:56:20.812464 [Byte1]: 30
8573 05:56:20.816584
8574 05:56:20.816684 Set Vref, RX VrefLevel [Byte0]: 31
8575 05:56:20.823622 [Byte1]: 31
8576 05:56:20.823704
8577 05:56:20.826295 Set Vref, RX VrefLevel [Byte0]: 32
8578 05:56:20.829900 [Byte1]: 32
8579 05:56:20.829982
8580 05:56:20.833388 Set Vref, RX VrefLevel [Byte0]: 33
8581 05:56:20.836192 [Byte1]: 33
8582 05:56:20.836274
8583 05:56:20.840074 Set Vref, RX VrefLevel [Byte0]: 34
8584 05:56:20.843502 [Byte1]: 34
8585 05:56:20.847026
8586 05:56:20.847108 Set Vref, RX VrefLevel [Byte0]: 35
8587 05:56:20.850527 [Byte1]: 35
8588 05:56:20.854584
8589 05:56:20.854667 Set Vref, RX VrefLevel [Byte0]: 36
8590 05:56:20.858122 [Byte1]: 36
8591 05:56:20.862141
8592 05:56:20.862223 Set Vref, RX VrefLevel [Byte0]: 37
8593 05:56:20.865504 [Byte1]: 37
8594 05:56:20.869512
8595 05:56:20.869597 Set Vref, RX VrefLevel [Byte0]: 38
8596 05:56:20.873233 [Byte1]: 38
8597 05:56:20.877147
8598 05:56:20.877229 Set Vref, RX VrefLevel [Byte0]: 39
8599 05:56:20.880412 [Byte1]: 39
8600 05:56:20.884473
8601 05:56:20.884555 Set Vref, RX VrefLevel [Byte0]: 40
8602 05:56:20.887687 [Byte1]: 40
8603 05:56:20.891853
8604 05:56:20.891936 Set Vref, RX VrefLevel [Byte0]: 41
8605 05:56:20.895315 [Byte1]: 41
8606 05:56:20.899831
8607 05:56:20.899913 Set Vref, RX VrefLevel [Byte0]: 42
8608 05:56:20.903092 [Byte1]: 42
8609 05:56:20.907314
8610 05:56:20.907397 Set Vref, RX VrefLevel [Byte0]: 43
8611 05:56:20.910559 [Byte1]: 43
8612 05:56:20.914584
8613 05:56:20.914667 Set Vref, RX VrefLevel [Byte0]: 44
8614 05:56:20.918052 [Byte1]: 44
8615 05:56:20.922082
8616 05:56:20.922194 Set Vref, RX VrefLevel [Byte0]: 45
8617 05:56:20.925623 [Byte1]: 45
8618 05:56:20.929832
8619 05:56:20.929914 Set Vref, RX VrefLevel [Byte0]: 46
8620 05:56:20.933247 [Byte1]: 46
8621 05:56:20.937496
8622 05:56:20.937579 Set Vref, RX VrefLevel [Byte0]: 47
8623 05:56:20.940891 [Byte1]: 47
8624 05:56:20.944932
8625 05:56:20.945015 Set Vref, RX VrefLevel [Byte0]: 48
8626 05:56:20.948241 [Byte1]: 48
8627 05:56:20.952536
8628 05:56:20.952618 Set Vref, RX VrefLevel [Byte0]: 49
8629 05:56:20.955907 [Byte1]: 49
8630 05:56:20.960089
8631 05:56:20.960171 Set Vref, RX VrefLevel [Byte0]: 50
8632 05:56:20.962908 [Byte1]: 50
8633 05:56:20.967553
8634 05:56:20.967635 Set Vref, RX VrefLevel [Byte0]: 51
8635 05:56:20.970884 [Byte1]: 51
8636 05:56:20.975090
8637 05:56:20.975171 Set Vref, RX VrefLevel [Byte0]: 52
8638 05:56:20.978441 [Byte1]: 52
8639 05:56:20.982294
8640 05:56:20.982376 Set Vref, RX VrefLevel [Byte0]: 53
8641 05:56:20.985614 [Byte1]: 53
8642 05:56:20.990467
8643 05:56:20.990548 Set Vref, RX VrefLevel [Byte0]: 54
8644 05:56:20.993123 [Byte1]: 54
8645 05:56:20.997635
8646 05:56:20.997717 Set Vref, RX VrefLevel [Byte0]: 55
8647 05:56:21.000926 [Byte1]: 55
8648 05:56:21.005159
8649 05:56:21.005241 Set Vref, RX VrefLevel [Byte0]: 56
8650 05:56:21.008600 [Byte1]: 56
8651 05:56:21.012730
8652 05:56:21.012876 Set Vref, RX VrefLevel [Byte0]: 57
8653 05:56:21.016430 [Byte1]: 57
8654 05:56:21.020549
8655 05:56:21.020631 Set Vref, RX VrefLevel [Byte0]: 58
8656 05:56:21.023473 [Byte1]: 58
8657 05:56:21.027894
8658 05:56:21.027980 Set Vref, RX VrefLevel [Byte0]: 59
8659 05:56:21.031181 [Byte1]: 59
8660 05:56:21.035429
8661 05:56:21.035512 Set Vref, RX VrefLevel [Byte0]: 60
8662 05:56:21.038828 [Byte1]: 60
8663 05:56:21.043032
8664 05:56:21.043115 Set Vref, RX VrefLevel [Byte0]: 61
8665 05:56:21.045902 [Byte1]: 61
8666 05:56:21.050557
8667 05:56:21.050640 Set Vref, RX VrefLevel [Byte0]: 62
8668 05:56:21.053926 [Byte1]: 62
8669 05:56:21.058046
8670 05:56:21.058128 Set Vref, RX VrefLevel [Byte0]: 63
8671 05:56:21.061568 [Byte1]: 63
8672 05:56:21.065874
8673 05:56:21.065956 Set Vref, RX VrefLevel [Byte0]: 64
8674 05:56:21.068574 [Byte1]: 64
8675 05:56:21.072731
8676 05:56:21.072813 Set Vref, RX VrefLevel [Byte0]: 65
8677 05:56:21.076039 [Byte1]: 65
8678 05:56:21.080191
8679 05:56:21.080297 Set Vref, RX VrefLevel [Byte0]: 66
8680 05:56:21.083787 [Byte1]: 66
8681 05:56:21.088353
8682 05:56:21.088434 Set Vref, RX VrefLevel [Byte0]: 67
8683 05:56:21.091530 [Byte1]: 67
8684 05:56:21.095482
8685 05:56:21.095564 Set Vref, RX VrefLevel [Byte0]: 68
8686 05:56:21.098938 [Byte1]: 68
8687 05:56:21.103123
8688 05:56:21.103205 Set Vref, RX VrefLevel [Byte0]: 69
8689 05:56:21.106561 [Byte1]: 69
8690 05:56:21.110405
8691 05:56:21.110487 Set Vref, RX VrefLevel [Byte0]: 70
8692 05:56:21.113607 [Byte1]: 70
8693 05:56:21.117976
8694 05:56:21.118058 Set Vref, RX VrefLevel [Byte0]: 71
8695 05:56:21.121267 [Byte1]: 71
8696 05:56:21.125845
8697 05:56:21.125927 Set Vref, RX VrefLevel [Byte0]: 72
8698 05:56:21.129084 [Byte1]: 72
8699 05:56:21.133484
8700 05:56:21.133565 Set Vref, RX VrefLevel [Byte0]: 73
8701 05:56:21.136525 [Byte1]: 73
8702 05:56:21.140925
8703 05:56:21.141008 Set Vref, RX VrefLevel [Byte0]: 74
8704 05:56:21.143719 [Byte1]: 74
8705 05:56:21.148573
8706 05:56:21.148655 Set Vref, RX VrefLevel [Byte0]: 75
8707 05:56:21.151942 [Byte1]: 75
8708 05:56:21.155996
8709 05:56:21.156078 Set Vref, RX VrefLevel [Byte0]: 76
8710 05:56:21.158793 [Byte1]: 76
8711 05:56:21.163530
8712 05:56:21.163612 Final RX Vref Byte 0 = 59 to rank0
8713 05:56:21.166850 Final RX Vref Byte 1 = 56 to rank0
8714 05:56:21.170347 Final RX Vref Byte 0 = 59 to rank1
8715 05:56:21.173148 Final RX Vref Byte 1 = 56 to rank1==
8716 05:56:21.176656 Dram Type= 6, Freq= 0, CH_1, rank 0
8717 05:56:21.183493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 05:56:21.183577 ==
8719 05:56:21.183643 DQS Delay:
8720 05:56:21.183703 DQS0 = 0, DQS1 = 0
8721 05:56:21.186989 DQM Delay:
8722 05:56:21.187071 DQM0 = 134, DQM1 = 131
8723 05:56:21.189863 DQ Delay:
8724 05:56:21.193127 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8725 05:56:21.196533 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
8726 05:56:21.199760 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8727 05:56:21.202981 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8728 05:56:21.203064
8729 05:56:21.203129
8730 05:56:21.203189
8731 05:56:21.206446 [DramC_TX_OE_Calibration] TA2
8732 05:56:21.209843 Original DQ_B0 (3 6) =30, OEN = 27
8733 05:56:21.213340 Original DQ_B1 (3 6) =30, OEN = 27
8734 05:56:21.216626 24, 0x0, End_B0=24 End_B1=24
8735 05:56:21.216711 25, 0x0, End_B0=25 End_B1=25
8736 05:56:21.219890 26, 0x0, End_B0=26 End_B1=26
8737 05:56:21.223141 27, 0x0, End_B0=27 End_B1=27
8738 05:56:21.226499 28, 0x0, End_B0=28 End_B1=28
8739 05:56:21.226582 29, 0x0, End_B0=29 End_B1=29
8740 05:56:21.229746 30, 0x0, End_B0=30 End_B1=30
8741 05:56:21.232934 31, 0x4141, End_B0=30 End_B1=30
8742 05:56:21.236196 Byte0 end_step=30 best_step=27
8743 05:56:21.239640 Byte1 end_step=30 best_step=27
8744 05:56:21.242956 Byte0 TX OE(2T, 0.5T) = (3, 3)
8745 05:56:21.246232 Byte1 TX OE(2T, 0.5T) = (3, 3)
8746 05:56:21.246315
8747 05:56:21.246380
8748 05:56:21.252952 [DQSOSCAuto] RK0, (LSB)MR18= 0x1421, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
8749 05:56:21.256291 CH1 RK0: MR19=303, MR18=1421
8750 05:56:21.263167 CH1_RK0: MR19=0x303, MR18=0x1421, DQSOSC=393, MR23=63, INC=23, DEC=15
8751 05:56:21.263251
8752 05:56:21.266636 ----->DramcWriteLeveling(PI) begin...
8753 05:56:21.266719 ==
8754 05:56:21.269978 Dram Type= 6, Freq= 0, CH_1, rank 1
8755 05:56:21.272688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8756 05:56:21.272772 ==
8757 05:56:21.277072 Write leveling (Byte 0): 27 => 27
8758 05:56:21.279602 Write leveling (Byte 1): 28 => 28
8759 05:56:21.283132 DramcWriteLeveling(PI) end<-----
8760 05:56:21.283214
8761 05:56:21.283279 ==
8762 05:56:21.286395 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 05:56:21.289967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 05:56:21.290050 ==
8765 05:56:21.292799 [Gating] SW mode calibration
8766 05:56:21.299757 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8767 05:56:21.305964 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8768 05:56:21.309865 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 05:56:21.313167 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 05:56:21.319219 1 4 8 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
8771 05:56:21.322659 1 4 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8772 05:56:21.325940 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 05:56:21.332752 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 05:56:21.336191 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 05:56:21.339531 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 05:56:21.346105 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 05:56:21.349298 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8778 05:56:21.352710 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (0 1) (1 0)
8779 05:56:21.359380 1 5 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8780 05:56:21.363113 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 05:56:21.366322 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 05:56:21.372794 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 05:56:21.376204 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 05:56:21.379562 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 05:56:21.385870 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 05:56:21.389362 1 6 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
8787 05:56:21.392651 1 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8788 05:56:21.399424 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 05:56:21.402832 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 05:56:21.406210 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 05:56:21.408991 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 05:56:21.415919 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 05:56:21.419198 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8794 05:56:21.422436 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8795 05:56:21.429621 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8796 05:56:21.432278 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8797 05:56:21.435757 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 05:56:21.442634 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 05:56:21.446149 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 05:56:21.449593 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 05:56:21.456178 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 05:56:21.458876 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 05:56:21.462296 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 05:56:21.469144 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 05:56:21.472447 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 05:56:21.475854 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 05:56:21.482425 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 05:56:21.485636 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 05:56:21.488898 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8810 05:56:21.495711 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8811 05:56:21.499011 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8812 05:56:21.502377 Total UI for P1: 0, mck2ui 16
8813 05:56:21.505833 best dqsien dly found for B1: ( 1, 9, 6)
8814 05:56:21.508696 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8815 05:56:21.515710 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 05:56:21.515794 Total UI for P1: 0, mck2ui 16
8817 05:56:21.522031 best dqsien dly found for B0: ( 1, 9, 14)
8818 05:56:21.525480 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8819 05:56:21.528806 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8820 05:56:21.528888
8821 05:56:21.532043 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8822 05:56:21.535279 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8823 05:56:21.538508 [Gating] SW calibration Done
8824 05:56:21.538591 ==
8825 05:56:21.542430 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 05:56:21.545190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 05:56:21.545273 ==
8828 05:56:21.548690 RX Vref Scan: 0
8829 05:56:21.548773
8830 05:56:21.548838 RX Vref 0 -> 0, step: 1
8831 05:56:21.548899
8832 05:56:21.551977 RX Delay 0 -> 252, step: 8
8833 05:56:21.555455 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8834 05:56:21.561508 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8835 05:56:21.565321 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8836 05:56:21.568601 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8837 05:56:21.571502 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8838 05:56:21.574827 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8839 05:56:21.581854 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8840 05:56:21.584658 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8841 05:56:21.588058 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8842 05:56:21.591407 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8843 05:56:21.594656 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8844 05:56:21.601884 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8845 05:56:21.604589 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8846 05:56:21.608411 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8847 05:56:21.611746 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8848 05:56:21.615088 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8849 05:56:21.617957 ==
8850 05:56:21.621504 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 05:56:21.624999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 05:56:21.625085 ==
8853 05:56:21.625151 DQS Delay:
8854 05:56:21.627785 DQS0 = 0, DQS1 = 0
8855 05:56:21.627868 DQM Delay:
8856 05:56:21.631327 DQM0 = 135, DQM1 = 133
8857 05:56:21.631408 DQ Delay:
8858 05:56:21.634715 DQ0 =139, DQ1 =135, DQ2 =119, DQ3 =131
8859 05:56:21.638102 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8860 05:56:21.641542 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8861 05:56:21.644648 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8862 05:56:21.644730
8863 05:56:21.644796
8864 05:56:21.644857 ==
8865 05:56:21.647825 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 05:56:21.654351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 05:56:21.654434 ==
8868 05:56:21.654500
8869 05:56:21.654560
8870 05:56:21.654618 TX Vref Scan disable
8871 05:56:21.658151 == TX Byte 0 ==
8872 05:56:21.661522 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8873 05:56:21.665039 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8874 05:56:21.668474 == TX Byte 1 ==
8875 05:56:21.671726 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8876 05:56:21.678148 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8877 05:56:21.678231 ==
8878 05:56:21.681612 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 05:56:21.685125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 05:56:21.685207 ==
8881 05:56:21.698189
8882 05:56:21.701579 TX Vref early break, caculate TX vref
8883 05:56:21.704946 TX Vref=16, minBit 0, minWin=22, winSum=380
8884 05:56:21.708206 TX Vref=18, minBit 1, minWin=23, winSum=394
8885 05:56:21.711713 TX Vref=20, minBit 9, minWin=24, winSum=405
8886 05:56:21.714389 TX Vref=22, minBit 0, minWin=24, winSum=408
8887 05:56:21.717702 TX Vref=24, minBit 0, minWin=25, winSum=419
8888 05:56:21.724927 TX Vref=26, minBit 0, minWin=25, winSum=419
8889 05:56:21.727740 TX Vref=28, minBit 0, minWin=26, winSum=428
8890 05:56:21.731300 TX Vref=30, minBit 6, minWin=25, winSum=424
8891 05:56:21.734813 TX Vref=32, minBit 0, minWin=25, winSum=412
8892 05:56:21.738183 TX Vref=34, minBit 0, minWin=25, winSum=407
8893 05:56:21.741020 TX Vref=36, minBit 0, minWin=24, winSum=395
8894 05:56:21.748113 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8895 05:56:21.748223
8896 05:56:21.751548 Final TX Range 0 Vref 28
8897 05:56:21.751656
8898 05:56:21.751749 ==
8899 05:56:21.754896 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 05:56:21.758037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 05:56:21.758162 ==
8902 05:56:21.758256
8903 05:56:21.758345
8904 05:56:21.761126 TX Vref Scan disable
8905 05:56:21.767901 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8906 05:56:21.767984 == TX Byte 0 ==
8907 05:56:21.771157 u2DelayCellOfst[0]=16 cells (5 PI)
8908 05:56:21.774719 u2DelayCellOfst[1]=10 cells (3 PI)
8909 05:56:21.778050 u2DelayCellOfst[2]=0 cells (0 PI)
8910 05:56:21.781183 u2DelayCellOfst[3]=6 cells (2 PI)
8911 05:56:21.784463 u2DelayCellOfst[4]=6 cells (2 PI)
8912 05:56:21.787556 u2DelayCellOfst[5]=16 cells (5 PI)
8913 05:56:21.790766 u2DelayCellOfst[6]=16 cells (5 PI)
8914 05:56:21.794172 u2DelayCellOfst[7]=6 cells (2 PI)
8915 05:56:21.797802 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8916 05:56:21.801157 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8917 05:56:21.804655 == TX Byte 1 ==
8918 05:56:21.804738 u2DelayCellOfst[8]=0 cells (0 PI)
8919 05:56:21.808261 u2DelayCellOfst[9]=3 cells (1 PI)
8920 05:56:21.810984 u2DelayCellOfst[10]=10 cells (3 PI)
8921 05:56:21.814399 u2DelayCellOfst[11]=6 cells (2 PI)
8922 05:56:21.818148 u2DelayCellOfst[12]=13 cells (4 PI)
8923 05:56:21.821547 u2DelayCellOfst[13]=16 cells (5 PI)
8924 05:56:21.824206 u2DelayCellOfst[14]=16 cells (5 PI)
8925 05:56:21.827543 u2DelayCellOfst[15]=16 cells (5 PI)
8926 05:56:21.831416 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8927 05:56:21.837508 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8928 05:56:21.837592 DramC Write-DBI on
8929 05:56:21.837658 ==
8930 05:56:21.840960 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 05:56:21.844551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 05:56:21.847405 ==
8933 05:56:21.847487
8934 05:56:21.847552
8935 05:56:21.847612 TX Vref Scan disable
8936 05:56:21.850879 == TX Byte 0 ==
8937 05:56:21.854431 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8938 05:56:21.857895 == TX Byte 1 ==
8939 05:56:21.861239 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8940 05:56:21.864449 DramC Write-DBI off
8941 05:56:21.864531
8942 05:56:21.864596 [DATLAT]
8943 05:56:21.864656 Freq=1600, CH1 RK1
8944 05:56:21.864717
8945 05:56:21.867775 DATLAT Default: 0xf
8946 05:56:21.870808 0, 0xFFFF, sum = 0
8947 05:56:21.870892 1, 0xFFFF, sum = 0
8948 05:56:21.874009 2, 0xFFFF, sum = 0
8949 05:56:21.874093 3, 0xFFFF, sum = 0
8950 05:56:21.877393 4, 0xFFFF, sum = 0
8951 05:56:21.877476 5, 0xFFFF, sum = 0
8952 05:56:21.880781 6, 0xFFFF, sum = 0
8953 05:56:21.880864 7, 0xFFFF, sum = 0
8954 05:56:21.884005 8, 0xFFFF, sum = 0
8955 05:56:21.884089 9, 0xFFFF, sum = 0
8956 05:56:21.887319 10, 0xFFFF, sum = 0
8957 05:56:21.887403 11, 0xFFFF, sum = 0
8958 05:56:21.890675 12, 0xFFFF, sum = 0
8959 05:56:21.890759 13, 0xFFFF, sum = 0
8960 05:56:21.894053 14, 0x0, sum = 1
8961 05:56:21.894136 15, 0x0, sum = 2
8962 05:56:21.897347 16, 0x0, sum = 3
8963 05:56:21.897430 17, 0x0, sum = 4
8964 05:56:21.900488 best_step = 15
8965 05:56:21.900570
8966 05:56:21.900635 ==
8967 05:56:21.903916 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 05:56:21.907489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 05:56:21.907572 ==
8970 05:56:21.911092 RX Vref Scan: 0
8971 05:56:21.911189
8972 05:56:21.911256 RX Vref 0 -> 0, step: 1
8973 05:56:21.911318
8974 05:56:21.914479 RX Delay 19 -> 252, step: 4
8975 05:56:21.917365 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8976 05:56:21.924135 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8977 05:56:21.927392 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8978 05:56:21.930809 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8979 05:56:21.934138 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8980 05:56:21.937460 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8981 05:56:21.943750 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8982 05:56:21.947181 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8983 05:56:21.950585 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8984 05:56:21.954103 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8985 05:56:21.956845 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8986 05:56:21.963823 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8987 05:56:21.967375 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8988 05:56:21.970693 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8989 05:56:21.973438 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8990 05:56:21.980133 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8991 05:56:21.980215 ==
8992 05:56:21.983873 Dram Type= 6, Freq= 0, CH_1, rank 1
8993 05:56:21.987015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8994 05:56:21.987098 ==
8995 05:56:21.987164 DQS Delay:
8996 05:56:21.990444 DQS0 = 0, DQS1 = 0
8997 05:56:21.990526 DQM Delay:
8998 05:56:21.993485 DQM0 = 134, DQM1 = 130
8999 05:56:21.993567 DQ Delay:
9000 05:56:21.996737 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9001 05:56:21.999959 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9002 05:56:22.003859 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9003 05:56:22.006976 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9004 05:56:22.007058
9005 05:56:22.007123
9006 05:56:22.007184
9007 05:56:22.010122 [DramC_TX_OE_Calibration] TA2
9008 05:56:22.013385 Original DQ_B0 (3 6) =30, OEN = 27
9009 05:56:22.017252 Original DQ_B1 (3 6) =30, OEN = 27
9010 05:56:22.020078 24, 0x0, End_B0=24 End_B1=24
9011 05:56:22.023490 25, 0x0, End_B0=25 End_B1=25
9012 05:56:22.023574 26, 0x0, End_B0=26 End_B1=26
9013 05:56:22.026853 27, 0x0, End_B0=27 End_B1=27
9014 05:56:22.030308 28, 0x0, End_B0=28 End_B1=28
9015 05:56:22.033714 29, 0x0, End_B0=29 End_B1=29
9016 05:56:22.033797 30, 0x0, End_B0=30 End_B1=30
9017 05:56:22.036971 31, 0x4545, End_B0=30 End_B1=30
9018 05:56:22.040319 Byte0 end_step=30 best_step=27
9019 05:56:22.043792 Byte1 end_step=30 best_step=27
9020 05:56:22.046551 Byte0 TX OE(2T, 0.5T) = (3, 3)
9021 05:56:22.049811 Byte1 TX OE(2T, 0.5T) = (3, 3)
9022 05:56:22.049893
9023 05:56:22.049958
9024 05:56:22.056484 [DQSOSCAuto] RK1, (LSB)MR18= 0x2208, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9025 05:56:22.059951 CH1 RK1: MR19=303, MR18=2208
9026 05:56:22.066684 CH1_RK1: MR19=0x303, MR18=0x2208, DQSOSC=392, MR23=63, INC=24, DEC=16
9027 05:56:22.070098 [RxdqsGatingPostProcess] freq 1600
9028 05:56:22.076922 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9029 05:56:22.077007 best DQS0 dly(2T, 0.5T) = (1, 1)
9030 05:56:22.079728 best DQS1 dly(2T, 0.5T) = (1, 1)
9031 05:56:22.083380 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9032 05:56:22.086557 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9033 05:56:22.090043 best DQS0 dly(2T, 0.5T) = (1, 1)
9034 05:56:22.093494 best DQS1 dly(2T, 0.5T) = (1, 1)
9035 05:56:22.096727 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9036 05:56:22.099999 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9037 05:56:22.103329 Pre-setting of DQS Precalculation
9038 05:56:22.106625 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9039 05:56:22.113284 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9040 05:56:22.123032 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9041 05:56:22.123116
9042 05:56:22.123182
9043 05:56:22.126814 [Calibration Summary] 3200 Mbps
9044 05:56:22.126897 CH 0, Rank 0
9045 05:56:22.130178 SW Impedance : PASS
9046 05:56:22.130260 DUTY Scan : NO K
9047 05:56:22.133642 ZQ Calibration : PASS
9048 05:56:22.136359 Jitter Meter : NO K
9049 05:56:22.136442 CBT Training : PASS
9050 05:56:22.139800 Write leveling : PASS
9051 05:56:22.139882 RX DQS gating : PASS
9052 05:56:22.143105 RX DQ/DQS(RDDQC) : PASS
9053 05:56:22.146531 TX DQ/DQS : PASS
9054 05:56:22.146614 RX DATLAT : PASS
9055 05:56:22.149905 RX DQ/DQS(Engine): PASS
9056 05:56:22.153184 TX OE : PASS
9057 05:56:22.153267 All Pass.
9058 05:56:22.153332
9059 05:56:22.153393 CH 0, Rank 1
9060 05:56:22.156635 SW Impedance : PASS
9061 05:56:22.159958 DUTY Scan : NO K
9062 05:56:22.160040 ZQ Calibration : PASS
9063 05:56:22.163173 Jitter Meter : NO K
9064 05:56:22.166439 CBT Training : PASS
9065 05:56:22.166521 Write leveling : PASS
9066 05:56:22.169713 RX DQS gating : PASS
9067 05:56:22.173099 RX DQ/DQS(RDDQC) : PASS
9068 05:56:22.173181 TX DQ/DQS : PASS
9069 05:56:22.176769 RX DATLAT : PASS
9070 05:56:22.180164 RX DQ/DQS(Engine): PASS
9071 05:56:22.180246 TX OE : PASS
9072 05:56:22.180352 All Pass.
9073 05:56:22.183050
9074 05:56:22.183133 CH 1, Rank 0
9075 05:56:22.183198 SW Impedance : PASS
9076 05:56:22.186535 DUTY Scan : NO K
9077 05:56:22.189880 ZQ Calibration : PASS
9078 05:56:22.189962 Jitter Meter : NO K
9079 05:56:22.193426 CBT Training : PASS
9080 05:56:22.196824 Write leveling : PASS
9081 05:56:22.196906 RX DQS gating : PASS
9082 05:56:22.199658 RX DQ/DQS(RDDQC) : PASS
9083 05:56:22.203323 TX DQ/DQS : PASS
9084 05:56:22.203406 RX DATLAT : PASS
9085 05:56:22.206613 RX DQ/DQS(Engine): PASS
9086 05:56:22.210125 TX OE : PASS
9087 05:56:22.210234 All Pass.
9088 05:56:22.210327
9089 05:56:22.210402 CH 1, Rank 1
9090 05:56:22.213333 SW Impedance : PASS
9091 05:56:22.216607 DUTY Scan : NO K
9092 05:56:22.216716 ZQ Calibration : PASS
9093 05:56:22.219637 Jitter Meter : NO K
9094 05:56:22.223631 CBT Training : PASS
9095 05:56:22.223714 Write leveling : PASS
9096 05:56:22.226814 RX DQS gating : PASS
9097 05:56:22.226896 RX DQ/DQS(RDDQC) : PASS
9098 05:56:22.230035 TX DQ/DQS : PASS
9099 05:56:22.233407 RX DATLAT : PASS
9100 05:56:22.233490 RX DQ/DQS(Engine): PASS
9101 05:56:22.236408 TX OE : PASS
9102 05:56:22.236491 All Pass.
9103 05:56:22.236556
9104 05:56:22.239621 DramC Write-DBI on
9105 05:56:22.243632 PER_BANK_REFRESH: Hybrid Mode
9106 05:56:22.243715 TX_TRACKING: ON
9107 05:56:22.253569 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9108 05:56:22.259813 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9109 05:56:22.266749 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9110 05:56:22.270242 [FAST_K] Save calibration result to emmc
9111 05:56:22.273421 sync common calibartion params.
9112 05:56:22.276640 sync cbt_mode0:1, 1:1
9113 05:56:22.280205 dram_init: ddr_geometry: 2
9114 05:56:22.280341 dram_init: ddr_geometry: 2
9115 05:56:22.283812 dram_init: ddr_geometry: 2
9116 05:56:22.286590 0:dram_rank_size:100000000
9117 05:56:22.290000 1:dram_rank_size:100000000
9118 05:56:22.293439 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9119 05:56:22.296892 DFS_SHUFFLE_HW_MODE: ON
9120 05:56:22.299748 dramc_set_vcore_voltage set vcore to 725000
9121 05:56:22.303182 Read voltage for 1600, 0
9122 05:56:22.303264 Vio18 = 0
9123 05:56:22.303330 Vcore = 725000
9124 05:56:22.306520 Vdram = 0
9125 05:56:22.306602 Vddq = 0
9126 05:56:22.306686 Vmddr = 0
9127 05:56:22.309955 switch to 3200 Mbps bootup
9128 05:56:22.313326 [DramcRunTimeConfig]
9129 05:56:22.313407 PHYPLL
9130 05:56:22.313472 DPM_CONTROL_AFTERK: ON
9131 05:56:22.316753 PER_BANK_REFRESH: ON
9132 05:56:22.319545 REFRESH_OVERHEAD_REDUCTION: ON
9133 05:56:22.319651 CMD_PICG_NEW_MODE: OFF
9134 05:56:22.322848 XRTWTW_NEW_MODE: ON
9135 05:56:22.326751 XRTRTR_NEW_MODE: ON
9136 05:56:22.326834 TX_TRACKING: ON
9137 05:56:22.329857 RDSEL_TRACKING: OFF
9138 05:56:22.329940 DQS Precalculation for DVFS: ON
9139 05:56:22.333266 RX_TRACKING: OFF
9140 05:56:22.333349 HW_GATING DBG: ON
9141 05:56:22.336468 ZQCS_ENABLE_LP4: ON
9142 05:56:22.336550 RX_PICG_NEW_MODE: ON
9143 05:56:22.339848 TX_PICG_NEW_MODE: ON
9144 05:56:22.343140 ENABLE_RX_DCM_DPHY: ON
9145 05:56:22.346419 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9146 05:56:22.346501 DUMMY_READ_FOR_TRACKING: OFF
9147 05:56:22.349474 !!! SPM_CONTROL_AFTERK: OFF
9148 05:56:22.352600 !!! SPM could not control APHY
9149 05:56:22.356476 IMPEDANCE_TRACKING: ON
9150 05:56:22.356558 TEMP_SENSOR: ON
9151 05:56:22.359691 HW_SAVE_FOR_SR: OFF
9152 05:56:22.359773 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9153 05:56:22.366341 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9154 05:56:22.366424 Read ODT Tracking: ON
9155 05:56:22.369289 Refresh Rate DeBounce: ON
9156 05:56:22.372758 DFS_NO_QUEUE_FLUSH: ON
9157 05:56:22.376035 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9158 05:56:22.376117 ENABLE_DFS_RUNTIME_MRW: OFF
9159 05:56:22.379555 DDR_RESERVE_NEW_MODE: ON
9160 05:56:22.382947 MR_CBT_SWITCH_FREQ: ON
9161 05:56:22.383029 =========================
9162 05:56:22.402125 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9163 05:56:22.405714 dram_init: ddr_geometry: 2
9164 05:56:22.424133 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9165 05:56:22.427514 dram_init: dram init end (result: 0)
9166 05:56:22.433543 DRAM-K: Full calibration passed in 24534 msecs
9167 05:56:22.437330 MRC: failed to locate region type 0.
9168 05:56:22.437436 DRAM rank0 size:0x100000000,
9169 05:56:22.440596 DRAM rank1 size=0x100000000
9170 05:56:22.450189 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9171 05:56:22.456729 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9172 05:56:22.464001 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9173 05:56:22.470820 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9174 05:56:22.473883 DRAM rank0 size:0x100000000,
9175 05:56:22.477084 DRAM rank1 size=0x100000000
9176 05:56:22.477166 CBMEM:
9177 05:56:22.480595 IMD: root @ 0xfffff000 254 entries.
9178 05:56:22.483807 IMD: root @ 0xffffec00 62 entries.
9179 05:56:22.486631 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9180 05:56:22.490134 WARNING: RO_VPD is uninitialized or empty.
9181 05:56:22.497016 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9182 05:56:22.503998 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9183 05:56:22.516581 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9184 05:56:22.528109 BS: romstage times (exec / console): total (unknown) / 24054 ms
9185 05:56:22.528195
9186 05:56:22.528261
9187 05:56:22.537793 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9188 05:56:22.541174 ARM64: Exception handlers installed.
9189 05:56:22.544580 ARM64: Testing exception
9190 05:56:22.547843 ARM64: Done test exception
9191 05:56:22.547925 Enumerating buses...
9192 05:56:22.551108 Show all devs... Before device enumeration.
9193 05:56:22.554600 Root Device: enabled 1
9194 05:56:22.557937 CPU_CLUSTER: 0: enabled 1
9195 05:56:22.558043 CPU: 00: enabled 1
9196 05:56:22.561328 Compare with tree...
9197 05:56:22.561410 Root Device: enabled 1
9198 05:56:22.564604 CPU_CLUSTER: 0: enabled 1
9199 05:56:22.567901 CPU: 00: enabled 1
9200 05:56:22.567983 Root Device scanning...
9201 05:56:22.571449 scan_static_bus for Root Device
9202 05:56:22.574193 CPU_CLUSTER: 0 enabled
9203 05:56:22.577673 scan_static_bus for Root Device done
9204 05:56:22.580882 scan_bus: bus Root Device finished in 8 msecs
9205 05:56:22.580964 done
9206 05:56:22.587895 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9207 05:56:22.591256 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9208 05:56:22.597588 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9209 05:56:22.600852 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9210 05:56:22.604431 Allocating resources...
9211 05:56:22.607875 Reading resources...
9212 05:56:22.611372 Root Device read_resources bus 0 link: 0
9213 05:56:22.611455 DRAM rank0 size:0x100000000,
9214 05:56:22.614527 DRAM rank1 size=0x100000000
9215 05:56:22.617583 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9216 05:56:22.621213 CPU: 00 missing read_resources
9217 05:56:22.624540 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9218 05:56:22.630638 Root Device read_resources bus 0 link: 0 done
9219 05:56:22.630721 Done reading resources.
9220 05:56:22.637407 Show resources in subtree (Root Device)...After reading.
9221 05:56:22.640948 Root Device child on link 0 CPU_CLUSTER: 0
9222 05:56:22.644332 CPU_CLUSTER: 0 child on link 0 CPU: 00
9223 05:56:22.653752 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9224 05:56:22.653836 CPU: 00
9225 05:56:22.657075 Root Device assign_resources, bus 0 link: 0
9226 05:56:22.660493 CPU_CLUSTER: 0 missing set_resources
9227 05:56:22.667469 Root Device assign_resources, bus 0 link: 0 done
9228 05:56:22.667551 Done setting resources.
9229 05:56:22.673886 Show resources in subtree (Root Device)...After assigning values.
9230 05:56:22.677389 Root Device child on link 0 CPU_CLUSTER: 0
9231 05:56:22.680807 CPU_CLUSTER: 0 child on link 0 CPU: 00
9232 05:56:22.690324 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9233 05:56:22.690438 CPU: 00
9234 05:56:22.693599 Done allocating resources.
9235 05:56:22.697571 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9236 05:56:22.700899 Enabling resources...
9237 05:56:22.700976 done.
9238 05:56:22.707295 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9239 05:56:22.707405 Initializing devices...
9240 05:56:22.710628 Root Device init
9241 05:56:22.710728 init hardware done!
9242 05:56:22.714132 0x00000018: ctrlr->caps
9243 05:56:22.716954 52.000 MHz: ctrlr->f_max
9244 05:56:22.717039 0.400 MHz: ctrlr->f_min
9245 05:56:22.720489 0x40ff8080: ctrlr->voltages
9246 05:56:22.720604 sclk: 390625
9247 05:56:22.723862 Bus Width = 1
9248 05:56:22.723971 sclk: 390625
9249 05:56:22.726998 Bus Width = 1
9250 05:56:22.727108 Early init status = 3
9251 05:56:22.733851 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9252 05:56:22.736932 in-header: 03 fc 00 00 01 00 00 00
9253 05:56:22.737036 in-data: 00
9254 05:56:22.743222 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9255 05:56:22.746492 in-header: 03 fd 00 00 00 00 00 00
9256 05:56:22.749874 in-data:
9257 05:56:22.753346 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9258 05:56:22.756587 in-header: 03 fc 00 00 01 00 00 00
9259 05:56:22.760061 in-data: 00
9260 05:56:22.763476 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9261 05:56:22.768980 in-header: 03 fd 00 00 00 00 00 00
9262 05:56:22.772490 in-data:
9263 05:56:22.775764 [SSUSB] Setting up USB HOST controller...
9264 05:56:22.778926 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9265 05:56:22.782530 [SSUSB] phy power-on done.
9266 05:56:22.785892 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9267 05:56:22.792201 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9268 05:56:22.795692 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9269 05:56:22.802606 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9270 05:56:22.808608 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9271 05:56:22.815674 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9272 05:56:22.821974 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9273 05:56:22.828907 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9274 05:56:22.829011 SPM: binary array size = 0x9dc
9275 05:56:22.835601 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9276 05:56:22.842265 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9277 05:56:22.848617 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9278 05:56:22.851828 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9279 05:56:22.858903 configure_display: Starting display init
9280 05:56:22.892283 anx7625_power_on_init: Init interface.
9281 05:56:22.895753 anx7625_disable_pd_protocol: Disabled PD feature.
9282 05:56:22.898578 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9283 05:56:22.926769 anx7625_start_dp_work: Secure OCM version=00
9284 05:56:22.929603 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9285 05:56:22.944600 sp_tx_get_edid_block: EDID Block = 1
9286 05:56:23.047252 Extracted contents:
9287 05:56:23.050701 header: 00 ff ff ff ff ff ff 00
9288 05:56:23.054068 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9289 05:56:23.057450 version: 01 04
9290 05:56:23.060787 basic params: 95 1f 11 78 0a
9291 05:56:23.063536 chroma info: 76 90 94 55 54 90 27 21 50 54
9292 05:56:23.066808 established: 00 00 00
9293 05:56:23.073622 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9294 05:56:23.077026 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9295 05:56:23.084159 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9296 05:56:23.090386 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9297 05:56:23.097317 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9298 05:56:23.100662 extensions: 00
9299 05:56:23.100743 checksum: fb
9300 05:56:23.100809
9301 05:56:23.103843 Manufacturer: IVO Model 57d Serial Number 0
9302 05:56:23.107322 Made week 0 of 2020
9303 05:56:23.107403 EDID version: 1.4
9304 05:56:23.110512 Digital display
9305 05:56:23.113614 6 bits per primary color channel
9306 05:56:23.113697 DisplayPort interface
9307 05:56:23.116665 Maximum image size: 31 cm x 17 cm
9308 05:56:23.120346 Gamma: 220%
9309 05:56:23.120428 Check DPMS levels
9310 05:56:23.123619 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9311 05:56:23.127094 First detailed timing is preferred timing
9312 05:56:23.130226 Established timings supported:
9313 05:56:23.133378 Standard timings supported:
9314 05:56:23.133460 Detailed timings
9315 05:56:23.140128 Hex of detail: 383680a07038204018303c0035ae10000019
9316 05:56:23.143381 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9317 05:56:23.150126 0780 0798 07c8 0820 hborder 0
9318 05:56:23.153620 0438 043b 0447 0458 vborder 0
9319 05:56:23.157143 -hsync -vsync
9320 05:56:23.157224 Did detailed timing
9321 05:56:23.159890 Hex of detail: 000000000000000000000000000000000000
9322 05:56:23.163799 Manufacturer-specified data, tag 0
9323 05:56:23.169806 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9324 05:56:23.169888 ASCII string: InfoVision
9325 05:56:23.176486 Hex of detail: 000000fe00523134304e574635205248200a
9326 05:56:23.179906 ASCII string: R140NWF5 RH
9327 05:56:23.179988 Checksum
9328 05:56:23.180062 Checksum: 0xfb (valid)
9329 05:56:23.186855 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9330 05:56:23.189558 DSI data_rate: 832800000 bps
9331 05:56:23.196465 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9332 05:56:23.199881 anx7625_parse_edid: pixelclock(138800).
9333 05:56:23.203376 hactive(1920), hsync(48), hfp(24), hbp(88)
9334 05:56:23.206036 vactive(1080), vsync(12), vfp(3), vbp(17)
9335 05:56:23.209385 anx7625_dsi_config: config dsi.
9336 05:56:23.216124 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9337 05:56:23.229636 anx7625_dsi_config: success to config DSI
9338 05:56:23.232650 anx7625_dp_start: MIPI phy setup OK.
9339 05:56:23.235799 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9340 05:56:23.238989 mtk_ddp_mode_set invalid vrefresh 60
9341 05:56:23.242384 main_disp_path_setup
9342 05:56:23.242470 ovl_layer_smi_id_en
9343 05:56:23.245620 ovl_layer_smi_id_en
9344 05:56:23.245702 ccorr_config
9345 05:56:23.245767 aal_config
9346 05:56:23.248793 gamma_config
9347 05:56:23.248874 postmask_config
9348 05:56:23.252546 dither_config
9349 05:56:23.255375 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9350 05:56:23.262646 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9351 05:56:23.265802 Root Device init finished in 552 msecs
9352 05:56:23.269075 CPU_CLUSTER: 0 init
9353 05:56:23.275833 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9354 05:56:23.278625 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9355 05:56:23.282448 APU_MBOX 0x190000b0 = 0x10001
9356 05:56:23.285844 APU_MBOX 0x190001b0 = 0x10001
9357 05:56:23.288612 APU_MBOX 0x190005b0 = 0x10001
9358 05:56:23.292040 APU_MBOX 0x190006b0 = 0x10001
9359 05:56:23.295541 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9360 05:56:23.307999 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9361 05:56:23.320900 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9362 05:56:23.327146 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9363 05:56:23.338621 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9364 05:56:23.347855 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9365 05:56:23.351381 CPU_CLUSTER: 0 init finished in 81 msecs
9366 05:56:23.354849 Devices initialized
9367 05:56:23.358346 Show all devs... After init.
9368 05:56:23.358429 Root Device: enabled 1
9369 05:56:23.361012 CPU_CLUSTER: 0: enabled 1
9370 05:56:23.364816 CPU: 00: enabled 1
9371 05:56:23.368021 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9372 05:56:23.371108 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9373 05:56:23.374821 ELOG: NV offset 0x57f000 size 0x1000
9374 05:56:23.381160 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9375 05:56:23.387957 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9376 05:56:23.390921 ELOG: Event(17) added with size 13 at 2023-12-25 05:53:48 UTC
9377 05:56:23.394368 out: cmd=0x121: 03 db 21 01 00 00 00 00
9378 05:56:23.398275 in-header: 03 8d 00 00 2c 00 00 00
9379 05:56:23.411564 in-data: d2 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9380 05:56:23.418571 ELOG: Event(A1) added with size 10 at 2023-12-25 05:53:48 UTC
9381 05:56:23.424627 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9382 05:56:23.431261 ELOG: Event(A0) added with size 9 at 2023-12-25 05:53:48 UTC
9383 05:56:23.434664 elog_add_boot_reason: Logged dev mode boot
9384 05:56:23.438149 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9385 05:56:23.441696 Finalize devices...
9386 05:56:23.441779 Devices finalized
9387 05:56:23.448448 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9388 05:56:23.451785 Writing coreboot table at 0xffe64000
9389 05:56:23.455157 0. 000000000010a000-0000000000113fff: RAMSTAGE
9390 05:56:23.457924 1. 0000000040000000-00000000400fffff: RAM
9391 05:56:23.461481 2. 0000000040100000-000000004032afff: RAMSTAGE
9392 05:56:23.468520 3. 000000004032b000-00000000545fffff: RAM
9393 05:56:23.471858 4. 0000000054600000-000000005465ffff: BL31
9394 05:56:23.475151 5. 0000000054660000-00000000ffe63fff: RAM
9395 05:56:23.477795 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9396 05:56:23.484991 7. 0000000100000000-000000023fffffff: RAM
9397 05:56:23.485074 Passing 5 GPIOs to payload:
9398 05:56:23.491782 NAME | PORT | POLARITY | VALUE
9399 05:56:23.494574 EC in RW | 0x000000aa | low | undefined
9400 05:56:23.501177 EC interrupt | 0x00000005 | low | undefined
9401 05:56:23.504542 TPM interrupt | 0x000000ab | high | undefined
9402 05:56:23.508338 SD card detect | 0x00000011 | high | undefined
9403 05:56:23.514922 speaker enable | 0x00000093 | high | undefined
9404 05:56:23.517931 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9405 05:56:23.520972 in-header: 03 f9 00 00 02 00 00 00
9406 05:56:23.521056 in-data: 02 00
9407 05:56:23.524542 ADC[4]: Raw value=903988 ID=7
9408 05:56:23.527903 ADC[3]: Raw value=213441 ID=1
9409 05:56:23.527986 RAM Code: 0x71
9410 05:56:23.531159 ADC[6]: Raw value=75701 ID=0
9411 05:56:23.534498 ADC[5]: Raw value=212703 ID=1
9412 05:56:23.534581 SKU Code: 0x1
9413 05:56:23.541109 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5137
9414 05:56:23.544493 coreboot table: 964 bytes.
9415 05:56:23.548098 IMD ROOT 0. 0xfffff000 0x00001000
9416 05:56:23.550904 IMD SMALL 1. 0xffffe000 0x00001000
9417 05:56:23.554218 RO MCACHE 2. 0xffffc000 0x00001104
9418 05:56:23.557597 CONSOLE 3. 0xfff7c000 0x00080000
9419 05:56:23.560991 FMAP 4. 0xfff7b000 0x00000452
9420 05:56:23.564652 TIME STAMP 5. 0xfff7a000 0x00000910
9421 05:56:23.567401 VBOOT WORK 6. 0xfff66000 0x00014000
9422 05:56:23.570836 RAMOOPS 7. 0xffe66000 0x00100000
9423 05:56:23.574411 COREBOOT 8. 0xffe64000 0x00002000
9424 05:56:23.574494 IMD small region:
9425 05:56:23.577865 IMD ROOT 0. 0xffffec00 0x00000400
9426 05:56:23.581344 VPD 1. 0xffffeb80 0x0000006c
9427 05:56:23.584554 MMC STATUS 2. 0xffffeb60 0x00000004
9428 05:56:23.591645 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9429 05:56:23.591733 Probing TPM: done!
9430 05:56:23.598318 Connected to device vid:did:rid of 1ae0:0028:00
9431 05:56:23.605008 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9432 05:56:23.608445 Initialized TPM device CR50 revision 0
9433 05:56:23.611891 Checking cr50 for pending updates
9434 05:56:23.617552 Reading cr50 TPM mode
9435 05:56:23.626215 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9436 05:56:23.633215 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9437 05:56:23.673346 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9438 05:56:23.676152 Checking segment from ROM address 0x40100000
9439 05:56:23.679707 Checking segment from ROM address 0x4010001c
9440 05:56:23.686718 Loading segment from ROM address 0x40100000
9441 05:56:23.686801 code (compression=0)
9442 05:56:23.693500 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9443 05:56:23.703407 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9444 05:56:23.703491 it's not compressed!
9445 05:56:23.709564 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9446 05:56:23.713241 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9447 05:56:23.733458 Loading segment from ROM address 0x4010001c
9448 05:56:23.733569 Entry Point 0x80000000
9449 05:56:23.736903 Loaded segments
9450 05:56:23.740384 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9451 05:56:23.746631 Jumping to boot code at 0x80000000(0xffe64000)
9452 05:56:23.753324 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9453 05:56:23.759722 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9454 05:56:23.768132 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9455 05:56:23.771400 Checking segment from ROM address 0x40100000
9456 05:56:23.774455 Checking segment from ROM address 0x4010001c
9457 05:56:23.781341 Loading segment from ROM address 0x40100000
9458 05:56:23.781424 code (compression=1)
9459 05:56:23.788043 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9460 05:56:23.797651 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9461 05:56:23.797735 using LZMA
9462 05:56:23.806136 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9463 05:56:23.812851 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9464 05:56:23.816505 Loading segment from ROM address 0x4010001c
9465 05:56:23.816589 Entry Point 0x54601000
9466 05:56:23.819712 Loaded segments
9467 05:56:23.823118 NOTICE: MT8192 bl31_setup
9468 05:56:23.830316 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9469 05:56:23.833632 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9470 05:56:23.836453 WARNING: region 0:
9471 05:56:23.839690 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 05:56:23.839773 WARNING: region 1:
9473 05:56:23.846655 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9474 05:56:23.849992 WARNING: region 2:
9475 05:56:23.853629 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9476 05:56:23.856209 WARNING: region 3:
9477 05:56:23.859848 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9478 05:56:23.863292 WARNING: region 4:
9479 05:56:23.870049 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9480 05:56:23.870132 WARNING: region 5:
9481 05:56:23.873551 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 05:56:23.876906 WARNING: region 6:
9483 05:56:23.880200 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 05:56:23.880282 WARNING: region 7:
9485 05:56:23.886546 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 05:56:23.893118 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9487 05:56:23.896292 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9488 05:56:23.899679 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9489 05:56:23.906681 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9490 05:56:23.910083 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9491 05:56:23.913529 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9492 05:56:23.919965 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9493 05:56:23.923764 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9494 05:56:23.926800 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9495 05:56:23.933167 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9496 05:56:23.936674 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9497 05:56:23.943688 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9498 05:56:23.946931 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9499 05:56:23.949712 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9500 05:56:23.956641 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9501 05:56:23.960122 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9502 05:56:23.963541 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9503 05:56:23.970508 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9504 05:56:23.973654 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9505 05:56:23.977102 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9506 05:56:23.983379 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9507 05:56:23.986842 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9508 05:56:23.993710 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9509 05:56:23.997194 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9510 05:56:24.000115 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9511 05:56:24.006783 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9512 05:56:24.010095 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9513 05:56:24.017488 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9514 05:56:24.020202 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9515 05:56:24.023561 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9516 05:56:24.030168 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9517 05:56:24.033939 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9518 05:56:24.036834 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9519 05:56:24.043928 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9520 05:56:24.047004 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9521 05:56:24.050213 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9522 05:56:24.053643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9523 05:56:24.060585 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9524 05:56:24.063904 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9525 05:56:24.067354 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9526 05:56:24.070151 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9527 05:56:24.076965 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9528 05:56:24.080320 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9529 05:56:24.083790 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9530 05:56:24.087230 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9531 05:56:24.094208 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9532 05:56:24.097055 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9533 05:56:24.100462 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9534 05:56:24.107339 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9535 05:56:24.110669 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9536 05:56:24.113474 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9537 05:56:24.120828 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9538 05:56:24.123598 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9539 05:56:24.130592 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9540 05:56:24.134076 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9541 05:56:24.140363 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9542 05:56:24.143721 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9543 05:56:24.147077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9544 05:56:24.153948 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9545 05:56:24.157395 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9546 05:56:24.164025 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9547 05:56:24.167672 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9548 05:56:24.173599 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9549 05:56:24.177234 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9550 05:56:24.180678 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9551 05:56:24.187602 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9552 05:56:24.190624 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9553 05:56:24.197545 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9554 05:56:24.200822 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9555 05:56:24.204169 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9556 05:56:24.210623 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9557 05:56:24.214073 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9558 05:56:24.220992 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9559 05:56:24.224237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9560 05:56:24.230570 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9561 05:56:24.234006 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9562 05:56:24.237464 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9563 05:56:24.244328 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9564 05:56:24.247844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9565 05:56:24.254647 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9566 05:56:24.257405 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9567 05:56:24.264410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9568 05:56:24.267922 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9569 05:56:24.271300 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9570 05:56:24.278140 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9571 05:56:24.281475 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9572 05:56:24.288123 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9573 05:56:24.291349 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9574 05:56:24.294785 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9575 05:56:24.301302 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9576 05:56:24.304398 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9577 05:56:24.311195 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9578 05:56:24.314641 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9579 05:56:24.321431 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9580 05:56:24.324438 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9581 05:56:24.331056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9582 05:56:24.334889 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9583 05:56:24.338395 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9584 05:56:24.341108 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9585 05:56:24.347837 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9586 05:56:24.351437 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9587 05:56:24.354696 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9588 05:56:24.361600 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9589 05:56:24.364976 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9590 05:56:24.367894 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9591 05:56:24.374756 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9592 05:56:24.378298 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9593 05:56:24.384447 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9594 05:56:24.387755 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9595 05:56:24.391240 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9596 05:56:24.398209 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9597 05:56:24.401625 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9598 05:56:24.407781 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9599 05:56:24.411208 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9600 05:56:24.414618 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9601 05:56:24.421581 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9602 05:56:24.424315 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9603 05:56:24.428223 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9604 05:56:24.434606 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9605 05:56:24.437887 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9606 05:56:24.441432 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9607 05:56:24.444156 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9608 05:56:24.451138 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9609 05:56:24.454333 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9610 05:56:24.457558 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9611 05:56:24.464443 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9612 05:56:24.467575 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9613 05:56:24.471202 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9614 05:56:24.477892 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9615 05:56:24.480904 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9616 05:56:24.487703 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9617 05:56:24.491030 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9618 05:56:24.494288 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9619 05:56:24.501080 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9620 05:56:24.504424 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9621 05:56:24.511319 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9622 05:56:24.514146 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9623 05:56:24.517595 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9624 05:56:24.524581 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9625 05:56:24.527921 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9626 05:56:24.530846 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9627 05:56:24.537612 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9628 05:56:24.541084 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9629 05:56:24.547379 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9630 05:56:24.550902 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9631 05:56:24.554435 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9632 05:56:24.560729 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9633 05:56:24.564664 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9634 05:56:24.571313 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9635 05:56:24.574677 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9636 05:56:24.577880 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9637 05:56:24.584130 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9638 05:56:24.587885 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9639 05:56:24.591284 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9640 05:56:24.597379 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9641 05:56:24.601023 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9642 05:56:24.607538 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9643 05:56:24.611201 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9644 05:56:24.614269 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9645 05:56:24.621011 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9646 05:56:24.623934 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9647 05:56:24.630738 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9648 05:56:24.634206 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9649 05:56:24.637679 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9650 05:56:24.643936 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9651 05:56:24.647410 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9652 05:56:24.654325 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9653 05:56:24.657107 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9654 05:56:24.660581 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9655 05:56:24.667457 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9656 05:56:24.670818 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9657 05:56:24.677347 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9658 05:56:24.680811 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9659 05:56:24.684097 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9660 05:56:24.690400 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9661 05:56:24.693921 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9662 05:56:24.697362 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9663 05:56:24.704265 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9664 05:56:24.706955 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9665 05:56:24.713615 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9666 05:56:24.717295 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9667 05:56:24.720292 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9668 05:56:24.727048 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9669 05:56:24.730520 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9670 05:56:24.736913 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9671 05:56:24.740409 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9672 05:56:24.743423 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9673 05:56:24.750188 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9674 05:56:24.753652 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9675 05:56:24.760459 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9676 05:56:24.763294 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9677 05:56:24.766596 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9678 05:56:24.773474 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9679 05:56:24.776991 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9680 05:56:24.783527 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9681 05:56:24.786667 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9682 05:56:24.793655 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9683 05:56:24.796340 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9684 05:56:24.799729 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9685 05:56:24.806660 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9686 05:56:24.809964 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9687 05:56:24.816270 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9688 05:56:24.819658 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9689 05:56:24.826577 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9690 05:56:24.830071 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9691 05:56:24.832832 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9692 05:56:24.840201 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9693 05:56:24.843021 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9694 05:56:24.849707 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9695 05:56:24.853501 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9696 05:56:24.856809 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9697 05:56:24.863230 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9698 05:56:24.866230 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9699 05:56:24.872815 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9700 05:56:24.876214 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9701 05:56:24.879421 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9702 05:56:24.886095 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9703 05:56:24.889348 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9704 05:56:24.895989 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9705 05:56:24.899755 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9706 05:56:24.905854 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9707 05:56:24.909320 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9708 05:56:24.912805 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9709 05:56:24.919155 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9710 05:56:24.922691 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9711 05:56:24.929695 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9712 05:56:24.932555 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9713 05:56:24.939459 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9714 05:56:24.942756 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9715 05:56:24.946211 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9716 05:56:24.949650 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9717 05:56:24.955897 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9718 05:56:24.959452 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9719 05:56:24.962933 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9720 05:56:24.966429 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9721 05:56:24.972740 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9722 05:56:24.976130 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9723 05:56:24.982774 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9724 05:56:24.986255 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9725 05:56:24.988918 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9726 05:56:24.995666 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9727 05:56:24.999013 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9728 05:56:25.002198 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9729 05:56:25.008875 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9730 05:56:25.012816 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9731 05:56:25.015887 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9732 05:56:25.022399 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9733 05:56:25.025540 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9734 05:56:25.029113 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9735 05:56:25.035435 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9736 05:56:25.038923 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9737 05:56:25.045359 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9738 05:56:25.048795 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9739 05:56:25.052059 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9740 05:56:25.058996 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9741 05:56:25.062439 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9742 05:56:25.065371 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9743 05:56:25.072171 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9744 05:56:25.075678 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9745 05:56:25.078550 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9746 05:56:25.085624 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9747 05:56:25.088951 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9748 05:56:25.095799 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9749 05:56:25.098945 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9750 05:56:25.102494 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9751 05:56:25.108714 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9752 05:56:25.112261 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9753 05:56:25.118446 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9754 05:56:25.121852 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9755 05:56:25.125254 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9756 05:56:25.128424 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9757 05:56:25.131872 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9758 05:56:25.138901 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9759 05:56:25.142073 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9760 05:56:25.145635 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9761 05:56:25.148416 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9762 05:56:25.155071 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9763 05:56:25.158502 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9764 05:56:25.161501 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9765 05:56:25.164856 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9766 05:56:25.172007 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9767 05:56:25.174811 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9768 05:56:25.178361 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9769 05:56:25.185258 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9770 05:56:25.188607 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9771 05:56:25.194755 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9772 05:56:25.197963 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9773 05:56:25.204813 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9774 05:56:25.208252 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9775 05:56:25.211778 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9776 05:56:25.218211 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9777 05:56:25.221625 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9778 05:56:25.227953 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9779 05:56:25.231295 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9780 05:56:25.234565 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9781 05:56:25.241638 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9782 05:56:25.244428 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9783 05:56:25.251307 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9784 05:56:25.254591 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9785 05:56:25.258027 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9786 05:56:25.264603 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9787 05:56:25.267737 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9788 05:56:25.274725 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9789 05:56:25.277754 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9790 05:56:25.281291 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9791 05:56:25.287933 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9792 05:56:25.291476 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9793 05:56:25.297633 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9794 05:56:25.301059 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9795 05:56:25.304501 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9796 05:56:25.311289 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9797 05:56:25.314520 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9798 05:56:25.320681 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9799 05:56:25.324155 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9800 05:56:25.327410 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9801 05:56:25.334497 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9802 05:56:25.337933 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9803 05:56:25.344037 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9804 05:56:25.347462 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9805 05:56:25.354501 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9806 05:56:25.357812 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9807 05:56:25.361373 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9808 05:56:25.367476 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9809 05:56:25.370854 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9810 05:56:25.377748 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9811 05:56:25.381181 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9812 05:56:25.384001 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9813 05:56:25.390790 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9814 05:56:25.394090 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9815 05:56:25.400700 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9816 05:56:25.403984 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9817 05:56:25.407689 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9818 05:56:25.414275 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9819 05:56:25.417589 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9820 05:56:25.424067 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9821 05:56:25.427511 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9822 05:56:25.434356 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9823 05:56:25.437070 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9824 05:56:25.440472 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9825 05:56:25.447014 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9826 05:56:25.450590 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9827 05:56:25.456901 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9828 05:56:25.460216 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9829 05:56:25.463689 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9830 05:56:25.470693 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9831 05:56:25.473533 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9832 05:56:25.480249 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9833 05:56:25.483839 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9834 05:56:25.487381 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9835 05:56:25.493616 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9836 05:56:25.497080 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9837 05:56:25.503703 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9838 05:56:25.506992 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9839 05:56:25.510509 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9840 05:56:25.516608 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9841 05:56:25.520088 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9842 05:56:25.527018 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9843 05:56:25.530402 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9844 05:56:25.537363 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9845 05:56:25.539900 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9846 05:56:25.546696 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9847 05:56:25.550131 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9848 05:56:25.553333 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9849 05:56:25.559953 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9850 05:56:25.563351 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9851 05:56:25.569919 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9852 05:56:25.573293 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9853 05:56:25.579856 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9854 05:56:25.583224 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9855 05:56:25.586534 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9856 05:56:25.593540 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9857 05:56:25.596407 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9858 05:56:25.603601 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9859 05:56:25.606411 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9860 05:56:25.613138 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9861 05:56:25.616358 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9862 05:56:25.619767 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9863 05:56:25.626646 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9864 05:56:25.630105 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9865 05:56:25.636850 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9866 05:56:25.639638 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9867 05:56:25.646824 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9868 05:56:25.649668 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9869 05:56:25.653063 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9870 05:56:25.659895 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9871 05:56:25.663429 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9872 05:56:25.670115 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9873 05:56:25.673172 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9874 05:56:25.679575 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9875 05:56:25.683213 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9876 05:56:25.686329 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9877 05:56:25.692910 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9878 05:56:25.696181 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9879 05:56:25.703137 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9880 05:56:25.706303 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9881 05:56:25.713046 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9882 05:56:25.716243 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9883 05:56:25.719703 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9884 05:56:25.726499 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9885 05:56:25.729295 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9886 05:56:25.736042 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9887 05:56:25.739497 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9888 05:56:25.742763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9889 05:56:25.749733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9890 05:56:25.753274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9891 05:56:25.759586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9892 05:56:25.762845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9893 05:56:25.769735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9894 05:56:25.773236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9895 05:56:25.779409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9896 05:56:25.782799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9897 05:56:25.789876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9898 05:56:25.793158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9899 05:56:25.799511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9900 05:56:25.803014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9901 05:56:25.809494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9902 05:56:25.812983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9903 05:56:25.819021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9904 05:56:25.822712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9905 05:56:25.829111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9906 05:56:25.832819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9907 05:56:25.836454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9908 05:56:25.842737 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9909 05:56:25.849277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9910 05:56:25.852814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9911 05:56:25.859257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9912 05:56:25.862653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9913 05:56:25.868820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9914 05:56:25.872389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9915 05:56:25.878975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9916 05:56:25.882404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9917 05:56:25.888590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9918 05:56:25.892081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9919 05:56:25.899019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9920 05:56:25.902518 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9921 05:56:25.902645 INFO: [APUAPC] vio 0
9922 05:56:25.909413 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9923 05:56:25.912819 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9924 05:56:25.916134 INFO: [APUAPC] D0_APC_0: 0x400510
9925 05:56:25.919710 INFO: [APUAPC] D0_APC_1: 0x0
9926 05:56:25.922562 INFO: [APUAPC] D0_APC_2: 0x1540
9927 05:56:25.926070 INFO: [APUAPC] D0_APC_3: 0x0
9928 05:56:25.929486 INFO: [APUAPC] D1_APC_0: 0xffffffff
9929 05:56:25.932963 INFO: [APUAPC] D1_APC_1: 0xffffffff
9930 05:56:25.935799 INFO: [APUAPC] D1_APC_2: 0x3fffff
9931 05:56:25.939461 INFO: [APUAPC] D1_APC_3: 0x0
9932 05:56:25.942862 INFO: [APUAPC] D2_APC_0: 0xffffffff
9933 05:56:25.945670 INFO: [APUAPC] D2_APC_1: 0xffffffff
9934 05:56:25.949317 INFO: [APUAPC] D2_APC_2: 0x3fffff
9935 05:56:25.952726 INFO: [APUAPC] D2_APC_3: 0x0
9936 05:56:25.956056 INFO: [APUAPC] D3_APC_0: 0xffffffff
9937 05:56:25.959359 INFO: [APUAPC] D3_APC_1: 0xffffffff
9938 05:56:25.962842 INFO: [APUAPC] D3_APC_2: 0x3fffff
9939 05:56:25.965458 INFO: [APUAPC] D3_APC_3: 0x0
9940 05:56:25.969066 INFO: [APUAPC] D4_APC_0: 0xffffffff
9941 05:56:25.972221 INFO: [APUAPC] D4_APC_1: 0xffffffff
9942 05:56:25.975691 INFO: [APUAPC] D4_APC_2: 0x3fffff
9943 05:56:25.978982 INFO: [APUAPC] D4_APC_3: 0x0
9944 05:56:25.982340 INFO: [APUAPC] D5_APC_0: 0xffffffff
9945 05:56:25.985782 INFO: [APUAPC] D5_APC_1: 0xffffffff
9946 05:56:25.988752 INFO: [APUAPC] D5_APC_2: 0x3fffff
9947 05:56:25.988848 INFO: [APUAPC] D5_APC_3: 0x0
9948 05:56:25.992073 INFO: [APUAPC] D6_APC_0: 0xffffffff
9949 05:56:25.999013 INFO: [APUAPC] D6_APC_1: 0xffffffff
9950 05:56:25.999120 INFO: [APUAPC] D6_APC_2: 0x3fffff
9951 05:56:26.002188 INFO: [APUAPC] D6_APC_3: 0x0
9952 05:56:26.005384 INFO: [APUAPC] D7_APC_0: 0xffffffff
9953 05:56:26.009106 INFO: [APUAPC] D7_APC_1: 0xffffffff
9954 05:56:26.012528 INFO: [APUAPC] D7_APC_2: 0x3fffff
9955 05:56:26.015225 INFO: [APUAPC] D7_APC_3: 0x0
9956 05:56:26.019296 INFO: [APUAPC] D8_APC_0: 0xffffffff
9957 05:56:26.022048 INFO: [APUAPC] D8_APC_1: 0xffffffff
9958 05:56:26.025503 INFO: [APUAPC] D8_APC_2: 0x3fffff
9959 05:56:26.028923 INFO: [APUAPC] D8_APC_3: 0x0
9960 05:56:26.031735 INFO: [APUAPC] D9_APC_0: 0xffffffff
9961 05:56:26.035182 INFO: [APUAPC] D9_APC_1: 0xffffffff
9962 05:56:26.038666 INFO: [APUAPC] D9_APC_2: 0x3fffff
9963 05:56:26.042108 INFO: [APUAPC] D9_APC_3: 0x0
9964 05:56:26.044934 INFO: [APUAPC] D10_APC_0: 0xffffffff
9965 05:56:26.048366 INFO: [APUAPC] D10_APC_1: 0xffffffff
9966 05:56:26.051902 INFO: [APUAPC] D10_APC_2: 0x3fffff
9967 05:56:26.055385 INFO: [APUAPC] D10_APC_3: 0x0
9968 05:56:26.058785 INFO: [APUAPC] D11_APC_0: 0xffffffff
9969 05:56:26.061536 INFO: [APUAPC] D11_APC_1: 0xffffffff
9970 05:56:26.065035 INFO: [APUAPC] D11_APC_2: 0x3fffff
9971 05:56:26.068520 INFO: [APUAPC] D11_APC_3: 0x0
9972 05:56:26.071925 INFO: [APUAPC] D12_APC_0: 0xffffffff
9973 05:56:26.074717 INFO: [APUAPC] D12_APC_1: 0xffffffff
9974 05:56:26.078336 INFO: [APUAPC] D12_APC_2: 0x3fffff
9975 05:56:26.081883 INFO: [APUAPC] D12_APC_3: 0x0
9976 05:56:26.084699 INFO: [APUAPC] D13_APC_0: 0xffffffff
9977 05:56:26.088096 INFO: [APUAPC] D13_APC_1: 0xffffffff
9978 05:56:26.091515 INFO: [APUAPC] D13_APC_2: 0x3fffff
9979 05:56:26.094710 INFO: [APUAPC] D13_APC_3: 0x0
9980 05:56:26.097947 INFO: [APUAPC] D14_APC_0: 0xffffffff
9981 05:56:26.101406 INFO: [APUAPC] D14_APC_1: 0xffffffff
9982 05:56:26.104648 INFO: [APUAPC] D14_APC_2: 0x3fffff
9983 05:56:26.108033 INFO: [APUAPC] D14_APC_3: 0x0
9984 05:56:26.111103 INFO: [APUAPC] D15_APC_0: 0xffffffff
9985 05:56:26.114976 INFO: [APUAPC] D15_APC_1: 0xffffffff
9986 05:56:26.121397 INFO: [APUAPC] D15_APC_2: 0x3fffff
9987 05:56:26.121527 INFO: [APUAPC] D15_APC_3: 0x0
9988 05:56:26.124358 INFO: [APUAPC] APC_CON: 0x4
9989 05:56:26.128083 INFO: [NOCDAPC] D0_APC_0: 0x0
9990 05:56:26.131239 INFO: [NOCDAPC] D0_APC_1: 0x0
9991 05:56:26.134251 INFO: [NOCDAPC] D1_APC_0: 0x0
9992 05:56:26.137957 INFO: [NOCDAPC] D1_APC_1: 0xfff
9993 05:56:26.140966 INFO: [NOCDAPC] D2_APC_0: 0x0
9994 05:56:26.144450 INFO: [NOCDAPC] D2_APC_1: 0xfff
9995 05:56:26.147529 INFO: [NOCDAPC] D3_APC_0: 0x0
9996 05:56:26.147674 INFO: [NOCDAPC] D3_APC_1: 0xfff
9997 05:56:26.150977 INFO: [NOCDAPC] D4_APC_0: 0x0
9998 05:56:26.154393 INFO: [NOCDAPC] D4_APC_1: 0xfff
9999 05:56:26.157793 INFO: [NOCDAPC] D5_APC_0: 0x0
10000 05:56:26.161145 INFO: [NOCDAPC] D5_APC_1: 0xfff
10001 05:56:26.164636 INFO: [NOCDAPC] D6_APC_0: 0x0
10002 05:56:26.168017 INFO: [NOCDAPC] D6_APC_1: 0xfff
10003 05:56:26.170878 INFO: [NOCDAPC] D7_APC_0: 0x0
10004 05:56:26.174658 INFO: [NOCDAPC] D7_APC_1: 0xfff
10005 05:56:26.178053 INFO: [NOCDAPC] D8_APC_0: 0x0
10006 05:56:26.180898 INFO: [NOCDAPC] D8_APC_1: 0xfff
10007 05:56:26.180984 INFO: [NOCDAPC] D9_APC_0: 0x0
10008 05:56:26.184256 INFO: [NOCDAPC] D9_APC_1: 0xfff
10009 05:56:26.187783 INFO: [NOCDAPC] D10_APC_0: 0x0
10010 05:56:26.191423 INFO: [NOCDAPC] D10_APC_1: 0xfff
10011 05:56:26.194094 INFO: [NOCDAPC] D11_APC_0: 0x0
10012 05:56:26.197587 INFO: [NOCDAPC] D11_APC_1: 0xfff
10013 05:56:26.200913 INFO: [NOCDAPC] D12_APC_0: 0x0
10014 05:56:26.204249 INFO: [NOCDAPC] D12_APC_1: 0xfff
10015 05:56:26.207591 INFO: [NOCDAPC] D13_APC_0: 0x0
10016 05:56:26.210951 INFO: [NOCDAPC] D13_APC_1: 0xfff
10017 05:56:26.214495 INFO: [NOCDAPC] D14_APC_0: 0x0
10018 05:56:26.217241 INFO: [NOCDAPC] D14_APC_1: 0xfff
10019 05:56:26.220778 INFO: [NOCDAPC] D15_APC_0: 0x0
10020 05:56:26.224177 INFO: [NOCDAPC] D15_APC_1: 0xfff
10021 05:56:26.224324 INFO: [NOCDAPC] APC_CON: 0x4
10022 05:56:26.227574 INFO: [APUAPC] set_apusys_apc done
10023 05:56:26.230971 INFO: [DEVAPC] devapc_init done
10024 05:56:26.237275 INFO: GICv3 without legacy support detected.
10025 05:56:26.240716 INFO: ARM GICv3 driver initialized in EL3
10026 05:56:26.244060 INFO: Maximum SPI INTID supported: 639
10027 05:56:26.247385 INFO: BL31: Initializing runtime services
10028 05:56:26.254254 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10029 05:56:26.257380 INFO: SPM: enable CPC mode
10030 05:56:26.260653 INFO: mcdi ready for mcusys-off-idle and system suspend
10031 05:56:26.267110 INFO: BL31: Preparing for EL3 exit to normal world
10032 05:56:26.270508 INFO: Entry point address = 0x80000000
10033 05:56:26.270590 INFO: SPSR = 0x8
10034 05:56:26.277432
10035 05:56:26.277514
10036 05:56:26.277580
10037 05:56:26.281083 Starting depthcharge on Spherion...
10038 05:56:26.281201
10039 05:56:26.281268 Wipe memory regions:
10040 05:56:26.281329
10041 05:56:26.282001 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10042 05:56:26.282101 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10043 05:56:26.282179 Setting prompt string to ['asurada:']
10044 05:56:26.282254 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10045 05:56:26.283998 [0x00000040000000, 0x00000054600000)
10046 05:56:26.406714
10047 05:56:26.406849 [0x00000054660000, 0x00000080000000)
10048 05:56:26.666960
10049 05:56:26.667098 [0x000000821a7280, 0x000000ffe64000)
10050 05:56:27.411961
10051 05:56:27.412100 [0x00000100000000, 0x00000240000000)
10052 05:56:29.302327
10053 05:56:29.305742 Initializing XHCI USB controller at 0x11200000.
10054 05:56:30.343638
10055 05:56:30.347090 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10056 05:56:30.347209
10057 05:56:30.347302
10058 05:56:30.347390
10059 05:56:30.347700 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10061 05:56:30.448090 asurada: tftpboot 192.168.201.1 12379421/tftp-deploy-gmkmbio6/kernel/image.itb 12379421/tftp-deploy-gmkmbio6/kernel/cmdline
10062 05:56:30.448261 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 05:56:30.448457 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10064 05:56:30.453536 tftpboot 192.168.201.1 12379421/tftp-deploy-gmkmbio6/kernel/image.itp-deploy-gmkmbio6/kernel/cmdline
10065 05:56:30.453633
10066 05:56:30.453702 Waiting for link
10067 05:56:30.611306
10068 05:56:30.611436 R8152: Initializing
10069 05:56:30.611507
10070 05:56:30.614436 Version 9 (ocp_data = 6010)
10071 05:56:30.614514
10072 05:56:30.617625 R8152: Done initializing
10073 05:56:30.617702
10074 05:56:30.617764 Adding net device
10075 05:56:32.565814
10076 05:56:32.565946 done.
10077 05:56:32.566013
10078 05:56:32.566074 MAC: 00:e0:4c:78:7a:aa
10079 05:56:32.566132
10080 05:56:32.569128 Sending DHCP discover... done.
10081 05:56:32.569213
10082 05:56:32.571794 Waiting for reply... done.
10083 05:56:32.571876
10084 05:56:32.575232 Sending DHCP request... done.
10085 05:56:32.575316
10086 05:56:32.587814 Waiting for reply... done.
10087 05:56:32.587916
10088 05:56:32.588001 My ip is 192.168.201.12
10089 05:56:32.588065
10090 05:56:32.591051 The DHCP server ip is 192.168.201.1
10091 05:56:32.591160
10092 05:56:32.597592 TFTP server IP predefined by user: 192.168.201.1
10093 05:56:32.597678
10094 05:56:32.604420 Bootfile predefined by user: 12379421/tftp-deploy-gmkmbio6/kernel/image.itb
10095 05:56:32.604504
10096 05:56:32.607446 Sending tftp read request... done.
10097 05:56:32.607530
10098 05:56:32.611243 Waiting for the transfer...
10099 05:56:32.611325
10100 05:56:32.872458 00000000 ################################################################
10101 05:56:32.872599
10102 05:56:33.133001 00080000 ################################################################
10103 05:56:33.133176
10104 05:56:33.393894 00100000 ################################################################
10105 05:56:33.394063
10106 05:56:33.651028 00180000 ################################################################
10107 05:56:33.651198
10108 05:56:33.910912 00200000 ################################################################
10109 05:56:33.911082
10110 05:56:34.170907 00280000 ################################################################
10111 05:56:34.171059
10112 05:56:34.423599 00300000 ################################################################
10113 05:56:34.423745
10114 05:56:34.697539 00380000 ################################################################
10115 05:56:34.697676
10116 05:56:34.963507 00400000 ################################################################
10117 05:56:34.963671
10118 05:56:35.217376 00480000 ################################################################
10119 05:56:35.217511
10120 05:56:35.472297 00500000 ################################################################
10121 05:56:35.472434
10122 05:56:35.726792 00580000 ################################################################
10123 05:56:35.726982
10124 05:56:35.991669 00600000 ################################################################
10125 05:56:35.991836
10126 05:56:36.246119 00680000 ################################################################
10127 05:56:36.246287
10128 05:56:36.507566 00700000 ################################################################
10129 05:56:36.507776
10130 05:56:36.758666 00780000 ################################################################
10131 05:56:36.758806
10132 05:56:37.036274 00800000 ################################################################
10133 05:56:37.036548
10134 05:56:37.296319 00880000 ################################################################
10135 05:56:37.296471
10136 05:56:37.559811 00900000 ################################################################
10137 05:56:37.560041
10138 05:56:37.826664 00980000 ################################################################
10139 05:56:37.826802
10140 05:56:38.080241 00a00000 ################################################################
10141 05:56:38.080413
10142 05:56:38.349080 00a80000 ################################################################
10143 05:56:38.349310
10144 05:56:38.608434 00b00000 ################################################################
10145 05:56:38.608587
10146 05:56:38.866652 00b80000 ################################################################
10147 05:56:38.866803
10148 05:56:39.125403 00c00000 ################################################################
10149 05:56:39.125554
10150 05:56:39.377574 00c80000 ################################################################
10151 05:56:39.377733
10152 05:56:39.637104 00d00000 ################################################################
10153 05:56:39.637254
10154 05:56:39.893125 00d80000 ################################################################
10155 05:56:39.893296
10156 05:56:40.155382 00e00000 ################################################################
10157 05:56:40.155524
10158 05:56:40.419671 00e80000 ################################################################
10159 05:56:40.419810
10160 05:56:40.680015 00f00000 ################################################################
10161 05:56:40.680165
10162 05:56:40.941103 00f80000 ################################################################
10163 05:56:40.941295
10164 05:56:41.194993 01000000 ################################################################
10165 05:56:41.195136
10166 05:56:41.449134 01080000 ################################################################
10167 05:56:41.449320
10168 05:56:41.708802 01100000 ################################################################
10169 05:56:41.709005
10170 05:56:41.986053 01180000 ################################################################
10171 05:56:41.986259
10172 05:56:42.262819 01200000 ################################################################
10173 05:56:42.263009
10174 05:56:42.530447 01280000 ################################################################
10175 05:56:42.530626
10176 05:56:42.795541 01300000 ################################################################
10177 05:56:42.795722
10178 05:56:43.051530 01380000 ################################################################
10179 05:56:43.051712
10180 05:56:43.301217 01400000 ################################################################
10181 05:56:43.301419
10182 05:56:43.554892 01480000 ################################################################
10183 05:56:43.555092
10184 05:56:43.817996 01500000 ################################################################
10185 05:56:43.818197
10186 05:56:44.076336 01580000 ################################################################
10187 05:56:44.076538
10188 05:56:44.325470 01600000 ################################################################
10189 05:56:44.325650
10190 05:56:44.579925 01680000 ################################################################
10191 05:56:44.580097
10192 05:56:44.834380 01700000 ################################################################
10193 05:56:44.834558
10194 05:56:45.081635 01780000 ################################################################
10195 05:56:45.081815
10196 05:56:45.346667 01800000 ################################################################
10197 05:56:45.346818
10198 05:56:45.604618 01880000 ################################################################
10199 05:56:45.604781
10200 05:56:45.859599 01900000 ################################################################
10201 05:56:45.859771
10202 05:56:46.111057 01980000 ################################################################
10203 05:56:46.111251
10204 05:56:46.374531 01a00000 ################################################################
10205 05:56:46.374793
10206 05:56:46.636259 01a80000 ################################################################
10207 05:56:46.636478
10208 05:56:46.896844 01b00000 ################################################################
10209 05:56:46.897044
10210 05:56:47.165289 01b80000 ################################################################
10211 05:56:47.165486
10212 05:56:47.426715 01c00000 ################################################################
10213 05:56:47.426893
10214 05:56:47.686013 01c80000 ################################################################
10215 05:56:47.686172
10216 05:56:47.944178 01d00000 ################################################################
10217 05:56:47.944376
10218 05:56:48.206106 01d80000 ################################################################
10219 05:56:48.206235
10220 05:56:48.457754 01e00000 ################################################################
10221 05:56:48.457900
10222 05:56:48.723273 01e80000 ################################################################
10223 05:56:48.723421
10224 05:56:48.975470 01f00000 ################################################################
10225 05:56:48.975647
10226 05:56:49.238431 01f80000 ################################################################
10227 05:56:49.238582
10228 05:56:49.509087 02000000 ################################################################
10229 05:56:49.509265
10230 05:56:49.768819 02080000 ################################################################
10231 05:56:49.769000
10232 05:56:50.021334 02100000 ################################################################
10233 05:56:50.021537
10234 05:56:50.282727 02180000 ################################################################
10235 05:56:50.282874
10236 05:56:50.542963 02200000 ################################################################
10237 05:56:50.543142
10238 05:56:50.822596 02280000 ################################################################
10239 05:56:50.822734
10240 05:56:51.111741 02300000 ################################################################
10241 05:56:51.111896
10242 05:56:51.392672 02380000 ################################################################
10243 05:56:51.392830
10244 05:56:51.665049 02400000 ################################################################
10245 05:56:51.665245
10246 05:56:51.933501 02480000 ################################################################
10247 05:56:51.933700
10248 05:56:52.214424 02500000 ################################################################
10249 05:56:52.214561
10250 05:56:52.476273 02580000 ################################################################
10251 05:56:52.476488
10252 05:56:52.746652 02600000 ################################################################
10253 05:56:52.746815
10254 05:56:53.015030 02680000 ################################################################
10255 05:56:53.015198
10256 05:56:53.281725 02700000 ################################################################
10257 05:56:53.281907
10258 05:56:53.551572 02780000 ################################################################
10259 05:56:53.551799
10260 05:56:53.818817 02800000 ################################################################
10261 05:56:53.818977
10262 05:56:54.091620 02880000 ################################################################
10263 05:56:54.091828
10264 05:56:54.353826 02900000 ################################################################
10265 05:56:54.353977
10266 05:56:54.622583 02980000 ################################################################
10267 05:56:54.622726
10268 05:56:54.888309 02a00000 ################################################################
10269 05:56:54.888444
10270 05:56:55.181223 02a80000 ################################################################
10271 05:56:55.181360
10272 05:56:55.478572 02b00000 ################################################################
10273 05:56:55.478735
10274 05:56:55.765948 02b80000 ################################################################
10275 05:56:55.766091
10276 05:56:56.060241 02c00000 ################################################################
10277 05:56:56.060385
10278 05:56:56.353435 02c80000 ################################################################
10279 05:56:56.353589
10280 05:56:56.623279 02d00000 ################################################################
10281 05:56:56.623420
10282 05:56:56.905972 02d80000 ################################################################
10283 05:56:56.906109
10284 05:56:57.168440 02e00000 ################################################################
10285 05:56:57.168578
10286 05:56:57.437403 02e80000 ################################################################
10287 05:56:57.437540
10288 05:56:57.694240 02f00000 ################################################################
10289 05:56:57.694382
10290 05:56:57.992126 02f80000 ################################################################
10291 05:56:57.992266
10292 05:56:58.263943 03000000 ################################################################
10293 05:56:58.264082
10294 05:56:58.541788 03080000 ################################################################
10295 05:56:58.541924
10296 05:56:58.816906 03100000 ################################################################
10297 05:56:58.817052
10298 05:56:59.095292 03180000 ################################################################
10299 05:56:59.095510
10300 05:56:59.386113 03200000 ################################################################
10301 05:56:59.386261
10302 05:56:59.682406 03280000 ################################################################
10303 05:56:59.682567
10304 05:56:59.965749 03300000 ################################################################
10305 05:56:59.965913
10306 05:57:00.247142 03380000 ################################################################
10307 05:57:00.247295
10308 05:57:00.501028 03400000 ################################################################
10309 05:57:00.501178
10310 05:57:00.756010 03480000 ################################################################
10311 05:57:00.756196
10312 05:57:01.006547 03500000 ################################################################
10313 05:57:01.006739
10314 05:57:01.254266 03580000 ################################################################
10315 05:57:01.254396
10316 05:57:01.505700 03600000 ################################################################
10317 05:57:01.505840
10318 05:57:01.754803 03680000 ################################################################
10319 05:57:01.754942
10320 05:57:02.003688 03700000 ################################################################
10321 05:57:02.003840
10322 05:57:02.256046 03780000 ################################################################
10323 05:57:02.256214
10324 05:57:02.506493 03800000 ################################################################
10325 05:57:02.506635
10326 05:57:02.757647 03880000 ################################################################
10327 05:57:02.757786
10328 05:57:03.006963 03900000 ################################################################
10329 05:57:03.007103
10330 05:57:03.256906 03980000 ################################################################
10331 05:57:03.257041
10332 05:57:03.510212 03a00000 ################################################################
10333 05:57:03.510371
10334 05:57:03.759177 03a80000 ################################################################
10335 05:57:03.759314
10336 05:57:04.007817 03b00000 ################################################################
10337 05:57:04.007962
10338 05:57:04.284996 03b80000 ################################################################
10339 05:57:04.285162
10340 05:57:04.514518 03c00000 ################################################################
10341 05:57:04.514678
10342 05:57:04.777723 03c80000 ################################################################
10343 05:57:04.777861
10344 05:57:05.042581 03d00000 ################################################################
10345 05:57:05.042714
10346 05:57:05.299823 03d80000 ################################################################
10347 05:57:05.299963
10348 05:57:05.559098 03e00000 ################################################################
10349 05:57:05.559239
10350 05:57:05.817076 03e80000 ################################################################
10351 05:57:05.817213
10352 05:57:06.073695 03f00000 ################################################################
10353 05:57:06.073829
10354 05:57:06.330615 03f80000 ################################################################
10355 05:57:06.330758
10356 05:57:06.588613 04000000 ################################################################
10357 05:57:06.588745
10358 05:57:06.753357 04080000 ######################################### done.
10359 05:57:06.753498
10360 05:57:06.756946 The bootfile was 67966530 bytes long.
10361 05:57:06.757035
10362 05:57:06.757103 Sending tftp read request... done.
10363 05:57:06.757166
10364 05:57:06.760517 Waiting for the transfer...
10365 05:57:06.760603
10366 05:57:06.763642 00000000 # done.
10367 05:57:06.763729
10368 05:57:06.769957 Command line loaded dynamically from TFTP file: 12379421/tftp-deploy-gmkmbio6/kernel/cmdline
10369 05:57:06.770044
10370 05:57:06.783588 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10371 05:57:06.783675
10372 05:57:06.787116 Loading FIT.
10373 05:57:06.787200
10374 05:57:06.789968 Image ramdisk-1 has 56435388 bytes.
10375 05:57:06.790053
10376 05:57:06.790119 Image fdt-1 has 47278 bytes.
10377 05:57:06.790182
10378 05:57:06.793390 Image kernel-1 has 11481830 bytes.
10379 05:57:06.793474
10380 05:57:06.803226 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10381 05:57:06.803311
10382 05:57:06.820049 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10383 05:57:06.820173
10384 05:57:06.827000 Choosing best match conf-1 for compat google,spherion-rev2.
10385 05:57:06.830528
10386 05:57:06.834697 Connected to device vid:did:rid of 1ae0:0028:00
10387 05:57:06.843029
10388 05:57:06.846600 tpm_get_response: command 0x17b, return code 0x0
10389 05:57:06.846679
10390 05:57:06.849406 ec_init: CrosEC protocol v3 supported (256, 248)
10391 05:57:06.853515
10392 05:57:06.856864 tpm_cleanup: add release locality here.
10393 05:57:06.856947
10394 05:57:06.857012 Shutting down all USB controllers.
10395 05:57:06.860186
10396 05:57:06.860269 Removing current net device
10397 05:57:06.860360
10398 05:57:06.866661 Exiting depthcharge with code 4 at timestamp: 69939594
10399 05:57:06.866743
10400 05:57:06.870549 LZMA decompressing kernel-1 to 0x821a6718
10401 05:57:06.870632
10402 05:57:06.873755 LZMA decompressing kernel-1 to 0x40000000
10403 05:57:08.310687
10404 05:57:08.310830 jumping to kernel
10405 05:57:08.311370 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10406 05:57:08.311470 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10407 05:57:08.311548 Setting prompt string to ['Linux version [0-9]']
10408 05:57:08.311618 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10409 05:57:08.311686 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10410 05:57:08.392541
10411 05:57:08.395997 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10412 05:57:08.399736 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10413 05:57:08.399829 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10414 05:57:08.399901 Setting prompt string to []
10415 05:57:08.399984 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10416 05:57:08.400058 Using line separator: #'\n'#
10417 05:57:08.400118 No login prompt set.
10418 05:57:08.400181 Parsing kernel messages
10419 05:57:08.400237 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10420 05:57:08.400380 [login-action] Waiting for messages, (timeout 00:03:43)
10421 05:57:08.419400 [ 0.000000] Linux version 6.1.67-cip12 (KernelCI@build-j59664-arm64-gcc-10-defconfig-arm64-chromebook-fgc24) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023
10422 05:57:08.422888 [ 0.000000] random: crng init done
10423 05:57:08.429419 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10424 05:57:08.429502 [ 0.000000] efi: UEFI not found.
10425 05:57:08.439042 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10426 05:57:08.446124 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10427 05:57:08.455626 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10428 05:57:08.465823 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10429 05:57:08.472449 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10430 05:57:08.475989 [ 0.000000] printk: bootconsole [mtk8250] enabled
10431 05:57:08.484781 [ 0.000000] NUMA: No NUMA configuration found
10432 05:57:08.491018 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10433 05:57:08.497884 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10434 05:57:08.497972 [ 0.000000] Zone ranges:
10435 05:57:08.504409 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10436 05:57:08.507840 [ 0.000000] DMA32 empty
10437 05:57:08.514894 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10438 05:57:08.517725 [ 0.000000] Movable zone start for each node
10439 05:57:08.521341 [ 0.000000] Early memory node ranges
10440 05:57:08.528206 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10441 05:57:08.534541 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10442 05:57:08.541084 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10443 05:57:08.547649 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10444 05:57:08.554777 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10445 05:57:08.561128 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10446 05:57:08.617416 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10447 05:57:08.623687 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10448 05:57:08.630881 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10449 05:57:08.633605 [ 0.000000] psci: probing for conduit method from DT.
10450 05:57:08.640013 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10451 05:57:08.643600 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10452 05:57:08.650026 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10453 05:57:08.653580 [ 0.000000] psci: SMC Calling Convention v1.2
10454 05:57:08.660147 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10455 05:57:08.663557 [ 0.000000] Detected VIPT I-cache on CPU0
10456 05:57:08.670361 [ 0.000000] CPU features: detected: GIC system register CPU interface
10457 05:57:08.676798 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10458 05:57:08.683199 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10459 05:57:08.690270 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10460 05:57:08.696644 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10461 05:57:08.706557 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10462 05:57:08.709811 [ 0.000000] alternatives: applying boot alternatives
10463 05:57:08.716505 [ 0.000000] Fallback order for Node 0: 0
10464 05:57:08.723227 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10465 05:57:08.726446 [ 0.000000] Policy zone: Normal
10466 05:57:08.739713 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10467 05:57:08.750153 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10468 05:57:08.760105 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10469 05:57:08.770199 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10470 05:57:08.776913 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10471 05:57:08.780523 <6>[ 0.000000] software IO TLB: area num 8.
10472 05:57:08.837024 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10473 05:57:08.985987 <6>[ 0.000000] Memory: 7913604K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 439164K reserved, 32768K cma-reserved)
10474 05:57:08.992960 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10475 05:57:08.999295 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10476 05:57:09.002918 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10477 05:57:09.009295 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10478 05:57:09.015986 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10479 05:57:09.019550 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10480 05:57:09.028860 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10481 05:57:09.035763 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10482 05:57:09.038928 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10483 05:57:09.046572 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10484 05:57:09.050368 <6>[ 0.000000] GICv3: 608 SPIs implemented
10485 05:57:09.057057 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10486 05:57:09.060276 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10487 05:57:09.063663 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10488 05:57:09.073626 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10489 05:57:09.083297 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10490 05:57:09.096601 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10491 05:57:09.103346 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10492 05:57:09.111958 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10493 05:57:09.125739 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10494 05:57:09.132195 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10495 05:57:09.138723 <6>[ 0.009231] Console: colour dummy device 80x25
10496 05:57:09.149027 <6>[ 0.013985] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10497 05:57:09.155569 <6>[ 0.024427] pid_max: default: 32768 minimum: 301
10498 05:57:09.158412 <6>[ 0.029291] LSM: Security Framework initializing
10499 05:57:09.165738 <6>[ 0.034231] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10500 05:57:09.175455 <6>[ 0.042045] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10501 05:57:09.181854 <6>[ 0.051509] cblist_init_generic: Setting adjustable number of callback queues.
10502 05:57:09.188930 <6>[ 0.058953] cblist_init_generic: Setting shift to 3 and lim to 1.
10503 05:57:09.195954 <6>[ 0.065291] cblist_init_generic: Setting adjustable number of callback queues.
10504 05:57:09.201929 <6>[ 0.072718] cblist_init_generic: Setting shift to 3 and lim to 1.
10505 05:57:09.209071 <6>[ 0.079119] rcu: Hierarchical SRCU implementation.
10506 05:57:09.215742 <6>[ 0.084135] rcu: Max phase no-delay instances is 1000.
10507 05:57:09.218693 <6>[ 0.091187] EFI services will not be available.
10508 05:57:09.225539 <6>[ 0.096142] smp: Bringing up secondary CPUs ...
10509 05:57:09.232956 <6>[ 0.101190] Detected VIPT I-cache on CPU1
10510 05:57:09.239542 <6>[ 0.101259] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10511 05:57:09.246637 <6>[ 0.101289] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10512 05:57:09.250077 <6>[ 0.101618] Detected VIPT I-cache on CPU2
10513 05:57:09.256704 <6>[ 0.101666] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10514 05:57:09.266239 <6>[ 0.101682] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10515 05:57:09.269475 <6>[ 0.101937] Detected VIPT I-cache on CPU3
10516 05:57:09.276134 <6>[ 0.101984] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10517 05:57:09.283021 <6>[ 0.101998] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10518 05:57:09.285871 <6>[ 0.102300] CPU features: detected: Spectre-v4
10519 05:57:09.292857 <6>[ 0.102307] CPU features: detected: Spectre-BHB
10520 05:57:09.295722 <6>[ 0.102311] Detected PIPT I-cache on CPU4
10521 05:57:09.302653 <6>[ 0.102368] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10522 05:57:09.309173 <6>[ 0.102385] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10523 05:57:09.315915 <6>[ 0.102678] Detected PIPT I-cache on CPU5
10524 05:57:09.322619 <6>[ 0.102740] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10525 05:57:09.329099 <6>[ 0.102756] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10526 05:57:09.332619 <6>[ 0.103036] Detected PIPT I-cache on CPU6
10527 05:57:09.339324 <6>[ 0.103099] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10528 05:57:09.345584 <6>[ 0.103115] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10529 05:57:09.352528 <6>[ 0.103409] Detected PIPT I-cache on CPU7
10530 05:57:09.359448 <6>[ 0.103475] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10531 05:57:09.365659 <6>[ 0.103491] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10532 05:57:09.369018 <6>[ 0.103538] smp: Brought up 1 node, 8 CPUs
10533 05:57:09.375781 <6>[ 0.244934] SMP: Total of 8 processors activated.
10534 05:57:09.379280 <6>[ 0.249855] CPU features: detected: 32-bit EL0 Support
10535 05:57:09.388923 <6>[ 0.255251] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10536 05:57:09.395860 <6>[ 0.264106] CPU features: detected: Common not Private translations
10537 05:57:09.398793 <6>[ 0.270582] CPU features: detected: CRC32 instructions
10538 05:57:09.405801 <6>[ 0.275933] CPU features: detected: RCpc load-acquire (LDAPR)
10539 05:57:09.412189 <6>[ 0.281930] CPU features: detected: LSE atomic instructions
10540 05:57:09.418662 <6>[ 0.287747] CPU features: detected: Privileged Access Never
10541 05:57:09.422227 <6>[ 0.293563] CPU features: detected: RAS Extension Support
10542 05:57:09.432157 <6>[ 0.299171] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10543 05:57:09.435514 <6>[ 0.306435] CPU: All CPU(s) started at EL2
10544 05:57:09.442307 <6>[ 0.310778] alternatives: applying system-wide alternatives
10545 05:57:09.451195 <6>[ 0.321507] devtmpfs: initialized
10546 05:57:09.462908 <6>[ 0.330397] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10547 05:57:09.473469 <6>[ 0.340358] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10548 05:57:09.476061 <6>[ 0.348002] pinctrl core: initialized pinctrl subsystem
10549 05:57:09.484386 <6>[ 0.354666] DMI not present or invalid.
10550 05:57:09.491309 <6>[ 0.359079] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10551 05:57:09.497786 <6>[ 0.365948] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10552 05:57:09.507697 <6>[ 0.373529] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10553 05:57:09.513922 <6>[ 0.381755] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10554 05:57:09.520424 <6>[ 0.389996] audit: initializing netlink subsys (disabled)
10555 05:57:09.527650 <5>[ 0.395689] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10556 05:57:09.534502 <6>[ 0.396394] thermal_sys: Registered thermal governor 'step_wise'
10557 05:57:09.540594 <6>[ 0.403658] thermal_sys: Registered thermal governor 'power_allocator'
10558 05:57:09.544052 <6>[ 0.409910] cpuidle: using governor menu
10559 05:57:09.550570 <6>[ 0.420866] NET: Registered PF_QIPCRTR protocol family
10560 05:57:09.557720 <6>[ 0.426348] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10561 05:57:09.564098 <6>[ 0.433448] ASID allocator initialised with 32768 entries
10562 05:57:09.567493 <6>[ 0.440019] Serial: AMBA PL011 UART driver
10563 05:57:09.578372 <4>[ 0.448805] Trying to register duplicate clock ID: 134
10564 05:57:09.632166 <6>[ 0.506201] KASLR enabled
10565 05:57:09.646943 <6>[ 0.513927] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10566 05:57:09.652927 <6>[ 0.520942] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10567 05:57:09.659851 <6>[ 0.527430] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10568 05:57:09.666669 <6>[ 0.534435] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10569 05:57:09.672839 <6>[ 0.540924] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10570 05:57:09.679900 <6>[ 0.547927] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10571 05:57:09.686547 <6>[ 0.554415] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10572 05:57:09.693331 <6>[ 0.561419] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10573 05:57:09.696134 <6>[ 0.568921] ACPI: Interpreter disabled.
10574 05:57:09.704668 <6>[ 0.575322] iommu: Default domain type: Translated
10575 05:57:09.711748 <6>[ 0.580434] iommu: DMA domain TLB invalidation policy: strict mode
10576 05:57:09.714666 <5>[ 0.587093] SCSI subsystem initialized
10577 05:57:09.721616 <6>[ 0.591252] usbcore: registered new interface driver usbfs
10578 05:57:09.728542 <6>[ 0.596982] usbcore: registered new interface driver hub
10579 05:57:09.731400 <6>[ 0.602534] usbcore: registered new device driver usb
10580 05:57:09.737815 <6>[ 0.608626] pps_core: LinuxPPS API ver. 1 registered
10581 05:57:09.748453 <6>[ 0.613821] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10582 05:57:09.751806 <6>[ 0.623168] PTP clock support registered
10583 05:57:09.754571 <6>[ 0.627410] EDAC MC: Ver: 3.0.0
10584 05:57:09.762251 <6>[ 0.632552] FPGA manager framework
10585 05:57:09.768232 <6>[ 0.636230] Advanced Linux Sound Architecture Driver Initialized.
10586 05:57:09.771537 <6>[ 0.643001] vgaarb: loaded
10587 05:57:09.778869 <6>[ 0.646147] clocksource: Switched to clocksource arch_sys_counter
10588 05:57:09.782119 <5>[ 0.652580] VFS: Disk quotas dquot_6.6.0
10589 05:57:09.788577 <6>[ 0.656766] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10590 05:57:09.791927 <6>[ 0.663954] pnp: PnP ACPI: disabled
10591 05:57:09.800013 <6>[ 0.670647] NET: Registered PF_INET protocol family
10592 05:57:09.806630 <6>[ 0.676233] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10593 05:57:09.821093 <6>[ 0.688555] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10594 05:57:09.831226 <6>[ 0.697374] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10595 05:57:09.838110 <6>[ 0.705339] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10596 05:57:09.844570 <6>[ 0.714041] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10597 05:57:09.856744 <6>[ 0.723799] TCP: Hash tables configured (established 65536 bind 65536)
10598 05:57:09.863277 <6>[ 0.730660] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10599 05:57:09.869639 <6>[ 0.737857] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10600 05:57:09.876640 <6>[ 0.745556] NET: Registered PF_UNIX/PF_LOCAL protocol family
10601 05:57:09.882690 <6>[ 0.751695] RPC: Registered named UNIX socket transport module.
10602 05:57:09.886253 <6>[ 0.757850] RPC: Registered udp transport module.
10603 05:57:09.892776 <6>[ 0.762785] RPC: Registered tcp transport module.
10604 05:57:09.899633 <6>[ 0.767715] RPC: Registered tcp NFSv4.1 backchannel transport module.
10605 05:57:09.902935 <6>[ 0.774377] PCI: CLS 0 bytes, default 64
10606 05:57:09.905903 <6>[ 0.778772] Unpacking initramfs...
10607 05:57:09.915645 <6>[ 0.782497] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10608 05:57:09.922825 <6>[ 0.791137] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10609 05:57:09.929407 <6>[ 0.799981] kvm [1]: IPA Size Limit: 40 bits
10610 05:57:09.932936 <6>[ 0.804510] kvm [1]: GICv3: no GICV resource entry
10611 05:57:09.939393 <6>[ 0.809529] kvm [1]: disabling GICv2 emulation
10612 05:57:09.945816 <6>[ 0.814213] kvm [1]: GIC system register CPU interface enabled
10613 05:57:09.949531 <6>[ 0.820383] kvm [1]: vgic interrupt IRQ18
10614 05:57:09.955993 <6>[ 0.826204] kvm [1]: VHE mode initialized successfully
10615 05:57:09.962608 <5>[ 0.832605] Initialise system trusted keyrings
10616 05:57:09.968862 <6>[ 0.837409] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10617 05:57:09.976747 <6>[ 0.847364] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10618 05:57:09.983653 <5>[ 0.853731] NFS: Registering the id_resolver key type
10619 05:57:09.986967 <5>[ 0.859029] Key type id_resolver registered
10620 05:57:09.993305 <5>[ 0.863443] Key type id_legacy registered
10621 05:57:09.999745 <6>[ 0.867725] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10622 05:57:10.006593 <6>[ 0.874650] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10623 05:57:10.013118 <6>[ 0.882383] 9p: Installing v9fs 9p2000 file system support
10624 05:57:10.050377 <5>[ 0.920711] Key type asymmetric registered
10625 05:57:10.053147 <5>[ 0.925040] Asymmetric key parser 'x509' registered
10626 05:57:10.063301 <6>[ 0.930177] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10627 05:57:10.066722 <6>[ 0.937789] io scheduler mq-deadline registered
10628 05:57:10.070120 <6>[ 0.942560] io scheduler kyber registered
10629 05:57:10.088818 <6>[ 0.959503] EINJ: ACPI disabled.
10630 05:57:10.120827 <4>[ 0.984732] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10631 05:57:10.130910 <4>[ 0.995370] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10632 05:57:10.145156 <6>[ 1.015777] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10633 05:57:10.152955 <6>[ 1.023640] printk: console [ttyS0] disabled
10634 05:57:10.181209 <6>[ 1.048290] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10635 05:57:10.187964 <6>[ 1.057781] printk: console [ttyS0] enabled
10636 05:57:10.190641 <6>[ 1.057781] printk: console [ttyS0] enabled
10637 05:57:10.197555 <6>[ 1.066676] printk: bootconsole [mtk8250] disabled
10638 05:57:10.200898 <6>[ 1.066676] printk: bootconsole [mtk8250] disabled
10639 05:57:10.207364 <6>[ 1.077708] SuperH (H)SCI(F) driver initialized
10640 05:57:10.210904 <6>[ 1.082989] msm_serial: driver initialized
10641 05:57:10.225051 <6>[ 1.091948] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10642 05:57:10.234418 <6>[ 1.100496] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10643 05:57:10.241273 <6>[ 1.109038] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10644 05:57:10.251703 <6>[ 1.117666] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10645 05:57:10.258563 <6>[ 1.126372] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10646 05:57:10.268368 <6>[ 1.135086] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10647 05:57:10.278004 <6>[ 1.143625] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10648 05:57:10.284660 <6>[ 1.152416] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10649 05:57:10.294285 <6>[ 1.160958] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10650 05:57:10.305606 <6>[ 1.176470] loop: module loaded
10651 05:57:10.312680 <6>[ 1.182458] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10652 05:57:10.335007 <4>[ 1.205600] mtk-pmic-keys: Failed to locate of_node [id: -1]
10653 05:57:10.341814 <6>[ 1.212421] megasas: 07.719.03.00-rc1
10654 05:57:10.350940 <6>[ 1.221802] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10655 05:57:10.358813 <6>[ 1.229559] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10656 05:57:10.374957 <6>[ 1.245528] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10657 05:57:10.430950 <6>[ 1.294909] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10658 05:57:12.298833 <6>[ 3.169300] Freeing initrd memory: 55112K
10659 05:57:12.308669 <6>[ 3.179633] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10660 05:57:12.319560 <6>[ 3.190568] tun: Universal TUN/TAP device driver, 1.6
10661 05:57:12.322939 <6>[ 3.196619] thunder_xcv, ver 1.0
10662 05:57:12.326595 <6>[ 3.200124] thunder_bgx, ver 1.0
10663 05:57:12.329298 <6>[ 3.203621] nicpf, ver 1.0
10664 05:57:12.340345 <6>[ 3.207624] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10665 05:57:12.343532 <6>[ 3.215100] hns3: Copyright (c) 2017 Huawei Corporation.
10666 05:57:12.350186 <6>[ 3.220686] hclge is initializing
10667 05:57:12.353155 <6>[ 3.224266] e1000: Intel(R) PRO/1000 Network Driver
10668 05:57:12.360061 <6>[ 3.229396] e1000: Copyright (c) 1999-2006 Intel Corporation.
10669 05:57:12.363629 <6>[ 3.235411] e1000e: Intel(R) PRO/1000 Network Driver
10670 05:57:12.369695 <6>[ 3.240626] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10671 05:57:12.376256 <6>[ 3.246811] igb: Intel(R) Gigabit Ethernet Network Driver
10672 05:57:12.383508 <6>[ 3.252460] igb: Copyright (c) 2007-2014 Intel Corporation.
10673 05:57:12.389765 <6>[ 3.258295] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10674 05:57:12.396048 <6>[ 3.264813] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10675 05:57:12.399706 <6>[ 3.271276] sky2: driver version 1.30
10676 05:57:12.406357 <6>[ 3.276264] VFIO - User Level meta-driver version: 0.3
10677 05:57:12.414146 <6>[ 3.284529] usbcore: registered new interface driver usb-storage
10678 05:57:12.420474 <6>[ 3.290970] usbcore: registered new device driver onboard-usb-hub
10679 05:57:12.429192 <6>[ 3.300084] mt6397-rtc mt6359-rtc: registered as rtc0
10680 05:57:12.439181 <6>[ 3.305547] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-25T05:54:37 UTC (1703483677)
10681 05:57:12.442720 <6>[ 3.315108] i2c_dev: i2c /dev entries driver
10682 05:57:12.459176 <6>[ 3.326911] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10683 05:57:12.478900 <6>[ 3.349908] cpu cpu0: EM: created perf domain
10684 05:57:12.482408 <6>[ 3.354830] cpu cpu4: EM: created perf domain
10685 05:57:12.489432 <6>[ 3.360394] sdhci: Secure Digital Host Controller Interface driver
10686 05:57:12.495841 <6>[ 3.366825] sdhci: Copyright(c) Pierre Ossman
10687 05:57:12.502842 <6>[ 3.371780] Synopsys Designware Multimedia Card Interface Driver
10688 05:57:12.509466 <6>[ 3.378441] sdhci-pltfm: SDHCI platform and OF driver helper
10689 05:57:12.512632 <6>[ 3.378489] mmc0: CQHCI version 5.10
10690 05:57:12.519465 <6>[ 3.388615] ledtrig-cpu: registered to indicate activity on CPUs
10691 05:57:12.526185 <6>[ 3.395711] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10692 05:57:12.532412 <6>[ 3.402768] usbcore: registered new interface driver usbhid
10693 05:57:12.535926 <6>[ 3.408590] usbhid: USB HID core driver
10694 05:57:12.542818 <6>[ 3.412778] spi_master spi0: will run message pump with realtime priority
10695 05:57:12.586413 <6>[ 3.450347] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10696 05:57:12.605418 <6>[ 3.466023] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10697 05:57:12.612685 <6>[ 3.481871] cros-ec-spi spi0.0: Chrome EC device registered
10698 05:57:12.615630 <6>[ 3.488003] mmc0: Command Queue Engine enabled
10699 05:57:12.622004 <6>[ 3.492759] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10700 05:57:12.629658 <6>[ 3.500388] mmcblk0: mmc0:0001 DA4128 116 GiB
10701 05:57:12.639809 <6>[ 3.510861] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10702 05:57:12.650153 <6>[ 3.515645] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10703 05:57:12.656119 <6>[ 3.517972] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10704 05:57:12.659660 <6>[ 3.527330] NET: Registered PF_PACKET protocol family
10705 05:57:12.666695 <6>[ 3.531990] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10706 05:57:12.669494 <6>[ 3.536734] 9pnet: Installing 9P2000 support
10707 05:57:12.676669 <6>[ 3.542646] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10708 05:57:12.682652 <5>[ 3.546408] Key type dns_resolver registered
10709 05:57:12.686395 <6>[ 3.557843] registered taskstats version 1
10710 05:57:12.693022 <5>[ 3.562220] Loading compiled-in X.509 certificates
10711 05:57:12.720141 <4>[ 3.584300] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10712 05:57:12.730295 <4>[ 3.595235] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10713 05:57:12.736675 <3>[ 3.605803] debugfs: File 'uA_load' in directory '/' already present!
10714 05:57:12.743011 <3>[ 3.612523] debugfs: File 'min_uV' in directory '/' already present!
10715 05:57:12.749587 <3>[ 3.619195] debugfs: File 'max_uV' in directory '/' already present!
10716 05:57:12.756474 <3>[ 3.625823] debugfs: File 'constraint_flags' in directory '/' already present!
10717 05:57:12.767973 <3>[ 3.635837] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10718 05:57:12.777263 <6>[ 3.648254] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10719 05:57:12.784331 <6>[ 3.655053] xhci-mtk 11200000.usb: xHCI Host Controller
10720 05:57:12.791115 <6>[ 3.660546] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10721 05:57:12.800564 <6>[ 3.668422] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10722 05:57:12.807314 <6>[ 3.677846] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10723 05:57:12.814315 <6>[ 3.683895] xhci-mtk 11200000.usb: xHCI Host Controller
10724 05:57:12.821038 <6>[ 3.689369] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10725 05:57:12.828138 <6>[ 3.697015] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10726 05:57:12.834724 <6>[ 3.704659] hub 1-0:1.0: USB hub found
10727 05:57:12.837573 <6>[ 3.708671] hub 1-0:1.0: 1 port detected
10728 05:57:12.844825 <6>[ 3.712930] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10729 05:57:12.851159 <6>[ 3.721491] hub 2-0:1.0: USB hub found
10730 05:57:12.854694 <6>[ 3.725494] hub 2-0:1.0: 1 port detected
10731 05:57:12.863020 <6>[ 3.733881] mtk-msdc 11f70000.mmc: Got CD GPIO
10732 05:57:12.873347 <6>[ 3.740357] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10733 05:57:12.879733 <6>[ 3.748390] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10734 05:57:12.889969 <4>[ 3.756304] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10735 05:57:12.899922 <6>[ 3.765828] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10736 05:57:12.906492 <6>[ 3.773904] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10737 05:57:12.913012 <6>[ 3.782003] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10738 05:57:12.923065 <6>[ 3.790001] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10739 05:57:12.929304 <6>[ 3.797830] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10740 05:57:12.939580 <6>[ 3.805668] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10741 05:57:12.949259 <6>[ 3.816152] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10742 05:57:12.956163 <6>[ 3.824543] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10743 05:57:12.965623 <6>[ 3.832885] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10744 05:57:12.972915 <6>[ 3.841236] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10745 05:57:12.982705 <6>[ 3.849576] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10746 05:57:12.989065 <6>[ 3.857927] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10747 05:57:12.998997 <6>[ 3.866267] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10748 05:57:13.005367 <6>[ 3.874618] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10749 05:57:13.015229 <6>[ 3.882959] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10750 05:57:13.025159 <6>[ 3.891320] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10751 05:57:13.032014 <6>[ 3.899660] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10752 05:57:13.038991 <6>[ 3.908000] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10753 05:57:13.048933 <6>[ 3.916339] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10754 05:57:13.058530 <6>[ 3.924678] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10755 05:57:13.065663 <6>[ 3.933016] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10756 05:57:13.071965 <6>[ 3.941787] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10757 05:57:13.078361 <6>[ 3.948971] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10758 05:57:13.085440 <6>[ 3.955731] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10759 05:57:13.091797 <6>[ 3.962484] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10760 05:57:13.101810 <6>[ 3.969412] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10761 05:57:13.108356 <6>[ 3.976261] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10762 05:57:13.118133 <6>[ 3.985388] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10763 05:57:13.128131 <6>[ 3.994509] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10764 05:57:13.138514 <6>[ 4.003830] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10765 05:57:13.148154 <6>[ 4.013306] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10766 05:57:13.155040 <6>[ 4.022778] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10767 05:57:13.164396 <6>[ 4.031901] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10768 05:57:13.174443 <6>[ 4.041369] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10769 05:57:13.184799 <6>[ 4.050487] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10770 05:57:13.194479 <6>[ 4.059781] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10771 05:57:13.204546 <6>[ 4.069940] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10772 05:57:13.214511 <6>[ 4.081467] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10773 05:57:13.242898 <6>[ 4.110728] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10774 05:57:13.270408 <6>[ 4.141393] hub 2-1:1.0: USB hub found
10775 05:57:13.273733 <6>[ 4.145837] hub 2-1:1.0: 3 ports detected
10776 05:57:13.282313 <6>[ 4.152904] hub 2-1:1.0: USB hub found
10777 05:57:13.285595 <6>[ 4.157295] hub 2-1:1.0: 3 ports detected
10778 05:57:13.395036 <6>[ 4.262449] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10779 05:57:13.549145 <6>[ 4.420072] hub 1-1:1.0: USB hub found
10780 05:57:13.552697 <6>[ 4.424628] hub 1-1:1.0: 4 ports detected
10781 05:57:13.562579 <6>[ 4.433177] hub 1-1:1.0: USB hub found
10782 05:57:13.565179 <6>[ 4.437544] hub 1-1:1.0: 4 ports detected
10783 05:57:13.634558 <6>[ 4.502511] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10784 05:57:13.886890 <6>[ 4.754469] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10785 05:57:14.019236 <6>[ 4.890397] hub 1-1.4:1.0: USB hub found
10786 05:57:14.023110 <6>[ 4.895091] hub 1-1.4:1.0: 2 ports detected
10787 05:57:14.032844 <6>[ 4.903575] hub 1-1.4:1.0: USB hub found
10788 05:57:14.035605 <6>[ 4.908114] hub 1-1.4:1.0: 2 ports detected
10789 05:57:14.330396 <6>[ 5.198442] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10790 05:57:14.522578 <6>[ 5.390442] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10791 05:57:25.492566 <6>[ 16.367506] ALSA device list:
10792 05:57:25.498687 <6>[ 16.370800] No soundcards found.
10793 05:57:25.506766 <6>[ 16.378939] Freeing unused kernel memory: 8448K
10794 05:57:25.510214 <6>[ 16.384047] Run /init as init process
10795 05:57:25.563334 <6>[ 16.435791] NET: Registered PF_INET6 protocol family
10796 05:57:25.569857 <6>[ 16.442000] Segment Routing with IPv6
10797 05:57:25.573266 <6>[ 16.445940] In-situ OAM (IOAM) with IPv6
10798 05:57:25.610900 <30>[ 16.463343] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10799 05:57:25.614337 <30>[ 16.487160] systemd[1]: Detected architecture arm64.
10800 05:57:25.614419
10801 05:57:25.620988 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10802 05:57:25.621090
10803 05:57:25.633992 <30>[ 16.506341] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10804 05:57:25.796722 <30>[ 16.665445] systemd[1]: Queued start job for default target Graphical Interface.
10805 05:57:25.843002 <30>[ 16.715348] systemd[1]: Created slice system-getty.slice.
10806 05:57:25.849455 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10807 05:57:25.867175 <30>[ 16.739112] systemd[1]: Created slice system-modprobe.slice.
10808 05:57:25.873285 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10809 05:57:25.894964 <30>[ 16.767483] systemd[1]: Created slice system-serial\x2dgetty.slice.
10810 05:57:25.905408 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10811 05:57:25.922128 <30>[ 16.794744] systemd[1]: Created slice User and Session Slice.
10812 05:57:25.929113 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10813 05:57:25.949703 <30>[ 16.818955] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10814 05:57:25.960060 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10815 05:57:25.977811 <30>[ 16.846935] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10816 05:57:25.984463 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10817 05:57:26.004843 <30>[ 16.870491] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10818 05:57:26.011828 <30>[ 16.882605] systemd[1]: Reached target Local Encrypted Volumes.
10819 05:57:26.017892 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10820 05:57:26.034702 <30>[ 16.906859] systemd[1]: Reached target Paths.
10821 05:57:26.037606 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10822 05:57:26.054141 <30>[ 16.926447] systemd[1]: Reached target Remote File Systems.
10823 05:57:26.061162 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10824 05:57:26.078759 <30>[ 16.950816] systemd[1]: Reached target Slices.
10825 05:57:26.085182 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10826 05:57:26.098567 <30>[ 16.970480] systemd[1]: Reached target Swap.
10827 05:57:26.101482 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10828 05:57:26.122175 <30>[ 16.991002] systemd[1]: Listening on initctl Compatibility Named Pipe.
10829 05:57:26.128598 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10830 05:57:26.135259 <30>[ 17.006325] systemd[1]: Listening on Journal Audit Socket.
10831 05:57:26.141418 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10832 05:57:26.155139 <30>[ 17.027003] systemd[1]: Listening on Journal Socket (/dev/log).
10833 05:57:26.161460 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10834 05:57:26.179728 <30>[ 17.051754] systemd[1]: Listening on Journal Socket.
10835 05:57:26.186090 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10836 05:57:26.198898 <30>[ 17.071095] systemd[1]: Listening on udev Control Socket.
10837 05:57:26.205167 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10838 05:57:26.222897 <30>[ 17.095547] systemd[1]: Listening on udev Kernel Socket.
10839 05:57:26.229642 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10840 05:57:26.270338 <30>[ 17.142516] systemd[1]: Mounting Huge Pages File System...
10841 05:57:26.276625 Mounting [0;1;39mHuge Pages File System[0m...
10842 05:57:26.294249 <30>[ 17.166732] systemd[1]: Mounting POSIX Message Queue File System...
10843 05:57:26.301523 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10844 05:57:26.319753 <30>[ 17.192149] systemd[1]: Mounting Kernel Debug File System...
10845 05:57:26.326222 Mounting [0;1;39mKernel Debug File System[0m...
10846 05:57:26.345560 <30>[ 17.214589] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10847 05:57:26.356501 <30>[ 17.225411] systemd[1]: Starting Create list of static device nodes for the current kernel...
10848 05:57:26.362940 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10849 05:57:26.381344 <30>[ 17.253861] systemd[1]: Starting Load Kernel Module configfs...
10850 05:57:26.387962 Starting [0;1;39mLoad Kernel Module configfs[0m...
10851 05:57:26.405752 <30>[ 17.278180] systemd[1]: Starting Load Kernel Module drm...
10852 05:57:26.412720 Starting [0;1;39mLoad Kernel Module drm[0m...
10853 05:57:26.434001 <30>[ 17.302788] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10854 05:57:26.448182 <30>[ 17.320245] systemd[1]: Starting Journal Service...
10855 05:57:26.451043 Starting [0;1;39mJournal Service[0m...
10856 05:57:26.468938 <30>[ 17.341351] systemd[1]: Starting Load Kernel Modules...
10857 05:57:26.475391 Starting [0;1;39mLoad Kernel Modules[0m...
10858 05:57:26.501942 <30>[ 17.371320] systemd[1]: Starting Remount Root and Kernel File Systems...
10859 05:57:26.509176 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10860 05:57:26.529119 <30>[ 17.401747] systemd[1]: Starting Coldplug All udev Devices...
10861 05:57:26.535740 Starting [0;1;39mColdplug All udev Devices[0m...
10862 05:57:26.558787 <30>[ 17.431065] systemd[1]: Started Journal Service.
10863 05:57:26.565160 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10864 05:57:26.581063 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10865 05:57:26.598747 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10866 05:57:26.618993 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10867 05:57:26.639595 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10868 05:57:26.656262 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10869 05:57:26.676349 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10870 05:57:26.690929 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10871 05:57:26.712283 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10872 05:57:26.726232 See 'systemctl status systemd-remount-fs.service' for details.
10873 05:57:26.787535 Mounting [0;1;39mKernel Configuration File System[0m...
10874 05:57:26.807592 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10875 05:57:26.829786 Startin<46>[ 17.699642] systemd-journald[180]: Received client request to flush runtime journal.
10876 05:57:26.833184 g [0;1;39mLoad/Save Random Seed[0m...
10877 05:57:26.854883 Starting [0;1;39mApply Kernel Variables[0m...
10878 05:57:26.876138 Starting [0;1;39mCreate System Users[0m...
10879 05:57:26.897070 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10880 05:57:26.915127 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10881 05:57:26.935166 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10882 05:57:26.947889 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10883 05:57:26.964385 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10884 05:57:26.971852 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10885 05:57:27.014553 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10886 05:57:27.037033 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10887 05:57:27.050561 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10888 05:57:27.066272 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10889 05:57:27.106792 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10890 05:57:27.131430 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10891 05:57:27.159373 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10892 05:57:27.181990 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10893 05:57:27.228589 Starting [0;1;39mNetwork Time Synchronization[0m...
10894 05:57:27.251634 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10895 05:57:27.286149 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10896 05:57:27.308950 <6>[ 18.178093] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10897 05:57:27.323257 [[0;32m OK [0m] Started [0;<6>[ 18.191199] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10898 05:57:27.333376 1;39mNetwork Tim<6>[ 18.200961] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10899 05:57:27.335958 e Synchronization[0m.
10900 05:57:27.353098 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10901 05:57:27.370326 <3>[ 18.239597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10902 05:57:27.376848 <3>[ 18.247912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10903 05:57:27.386939 <3>[ 18.256137] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10904 05:57:27.393320 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10905 05:57:27.405223 <3>[ 18.274068] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10906 05:57:27.411400 <4>[ 18.280769] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10907 05:57:27.421410 <3>[ 18.282191] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10908 05:57:27.428314 <3>[ 18.282196] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10909 05:57:27.434541 <3>[ 18.282204] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10910 05:57:27.445072 <3>[ 18.282209] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10911 05:57:27.451565 <3>[ 18.298638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10912 05:57:27.458018 <6>[ 18.308056] mc: Linux media interface: v0.10
10913 05:57:27.464890 <4>[ 18.314257] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10914 05:57:27.471441 <3>[ 18.322098] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 05:57:27.478206 <6>[ 18.328007] usbcore: registered new interface driver r8152
10916 05:57:27.484318 <6>[ 18.339250] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10917 05:57:27.494553 <3>[ 18.342299] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10918 05:57:27.498064 <6>[ 18.350653] pci_bus 0000:00: root bus resource [bus 00-ff]
10919 05:57:27.508081 <3>[ 18.356150] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10920 05:57:27.514296 <6>[ 18.363019] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10921 05:57:27.520753 <6>[ 18.366203] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10922 05:57:27.530779 <3>[ 18.380284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10923 05:57:27.541306 <6>[ 18.385230] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10924 05:57:27.547705 <6>[ 18.391123] videodev: Linux video capture interface: v2.00
10925 05:57:27.553944 <3>[ 18.392192] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10926 05:57:27.564037 <3>[ 18.392197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10927 05:57:27.570640 <3>[ 18.392202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10928 05:57:27.577761 <3>[ 18.392206] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10929 05:57:27.587295 <3>[ 18.392292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10930 05:57:27.593842 [[0;32m OK [<6>[ 18.465159] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10931 05:57:27.607000 0m] Reached targ<6>[ 18.466321] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10932 05:57:27.617337 et [0;1;39mSyst<6>[ 18.468202] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10933 05:57:27.623538 <6>[ 18.472926] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10934 05:57:27.633980 em Time Set[0m.<6>[ 18.495357] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10935 05:57:27.636876
10936 05:57:27.640434 <6>[ 18.503287] pci 0000:00:00.0: supports D1 D2
10937 05:57:27.646947 <6>[ 18.517561] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10938 05:57:27.656724 [[0;32m OK [<6>[ 18.525543] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10939 05:57:27.666783 0m] Reached targ<6>[ 18.526467] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10940 05:57:27.673377 et [0;1;39mSyst<6>[ 18.537436] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10941 05:57:27.683552 em Time Synchron<4>[ 18.543514] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10942 05:57:27.690067 <4>[ 18.543514] Fallback method does not support PEC.
10943 05:57:27.690179 ized[0m.
10944 05:57:27.697032 <6>[ 18.544227] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10945 05:57:27.703423 <6>[ 18.544275] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10946 05:57:27.713200 <6>[ 18.544312] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10947 05:57:27.719738 <6>[ 18.544327] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10948 05:57:27.722888 <6>[ 18.544531] pci 0000:01:00.0: supports D1 D2
10949 05:57:27.729870 <6>[ 18.544547] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10950 05:57:27.736512 <6>[ 18.554335] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10951 05:57:27.742872 <6>[ 18.554984] remoteproc remoteproc0: scp is available
10952 05:57:27.746602 <6>[ 18.555049] remoteproc remoteproc0: powering up scp
10953 05:57:27.757004 <6>[ 18.555054] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10954 05:57:27.764049 <6>[ 18.555069] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10955 05:57:27.771301 <4>[ 18.557631] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10956 05:57:27.778459 <4>[ 18.557640] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10957 05:57:27.781266 <6>[ 18.575313] Bluetooth: Core ver 2.22
10958 05:57:27.791362 <6>[ 18.582018] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10959 05:57:27.798484 <6>[ 18.582403] usbcore: registered new interface driver cdc_ether
10960 05:57:27.801912 <6>[ 18.589510] NET: Registered PF_BLUETOOTH protocol family
10961 05:57:27.811913 <6>[ 18.596929] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10962 05:57:27.818319 <6>[ 18.598101] usbcore: registered new interface driver r8153_ecm
10963 05:57:27.825403 <6>[ 18.601451] Bluetooth: HCI device and connection manager initialized
10964 05:57:27.828564 <6>[ 18.601465] Bluetooth: HCI socket layer initialized
10965 05:57:27.834859 <6>[ 18.608341] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10966 05:57:27.845015 <6>[ 18.609564] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10967 05:57:27.854845 <6>[ 18.610796] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10968 05:57:27.861593 <6>[ 18.610968] usbcore: registered new interface driver uvcvideo
10969 05:57:27.867937 <6>[ 18.615218] Bluetooth: L2CAP socket layer initialized
10970 05:57:27.871271 <6>[ 18.618250] r8152 2-1.3:1.0 eth0: v1.12.13
10971 05:57:27.881621 <6>[ 18.620429] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10972 05:57:27.884396 <6>[ 18.625558] Bluetooth: SCO socket layer initialized
10973 05:57:27.891409 <6>[ 18.626088] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10974 05:57:27.898092 <6>[ 18.633980] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10975 05:57:27.904251 <6>[ 18.634619] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10976 05:57:27.914525 <3>[ 18.646248] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 05:57:27.920748 <3>[ 18.647084] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10978 05:57:27.927789 <6>[ 18.648660] pci 0000:00:00.0: PCI bridge to [bus 01]
10979 05:57:27.937420 <3>[ 18.653258] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 05:57:27.944426 <3>[ 18.678388] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 05:57:27.953959 <6>[ 18.680279] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10982 05:57:27.960581 <6>[ 18.680685] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10983 05:57:27.967756 <6>[ 18.680733] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10984 05:57:27.973944 <6>[ 18.680739] remoteproc remoteproc0: remote processor scp is now up
10985 05:57:27.980586 <6>[ 18.688934] usbcore: registered new interface driver btusb
10986 05:57:27.990653 <6>[ 18.689633] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10987 05:57:28.000642 <4>[ 18.689843] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10988 05:57:28.007397 <3>[ 18.689857] Bluetooth: hci0: Failed to load firmware file (-2)
10989 05:57:28.010833 <3>[ 18.689863] Bluetooth: hci0: Failed to set up firmware (-2)
10990 05:57:28.020150 <4>[ 18.689870] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10991 05:57:28.030059 <6>[ 18.691363] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10992 05:57:28.037259 <6>[ 18.694539] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10993 05:57:28.043493 <6>[ 18.914570] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10994 05:57:28.050192 <6>[ 18.921251] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10995 05:57:28.067839 <5>[ 18.937196] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10996 05:57:28.074626 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10997 05:57:28.088715 <5>[ 18.958023] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10998 05:57:28.095716 <4>[ 18.965383] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10999 05:57:28.101947 <6>[ 18.974369] cfg80211: failed to load regulatory.db
11000 05:57:28.115731 [[0;32m OK [0m] Finished [0;1;39mLoad/Save <3>[ 18.982929] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 05:57:28.118915 Screen …s of leds:white:kbd_backlight[0m.
11002 05:57:28.148305 <3>[ 19.017129] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11003 05:57:28.158990 <6>[ 19.028036] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11004 05:57:28.165294 <6>[ 19.035547] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11005 05:57:28.179704 <3>[ 19.048719] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11006 05:57:28.189655 <6>[ 19.062215] mt7921e 0000:01:00.0: ASIC revision: 79610010
11007 05:57:28.208765 <3>[ 19.077570] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11008 05:57:28.244726 <3>[ 19.113574] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11009 05:57:28.257215 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11010 05:57:28.273989 [[0;32m OK [<3>[ 19.142633] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 05:57:28.280312 0m] Reached target [0;1;39mSystem Initialization[0m.
11012 05:57:28.299214 [[0;32m OK [<6>[ 19.167681] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11013 05:57:28.302776 <6>[ 19.167681]
11014 05:57:28.305591 0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11015 05:57:28.325592 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11016 05:57:28.338379 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11017 05:57:28.357959 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11018 05:57:28.369702 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11019 05:57:28.386141 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11020 05:57:28.410226 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11021 05:57:28.458719 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11022 05:57:28.526739 Starting [0;1;39mUser Login Management[0m...
11023 05:57:28.547436 Starting [0;1;39mPermit User Sessions[0m...
11024 05:57:28.569436 <6>[ 19.438967] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11025 05:57:28.576520 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11026 05:57:28.619186 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11027 05:57:28.637617 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11028 05:57:28.654438 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11029 05:57:28.674056 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11030 05:57:28.692059 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11031 05:57:28.710925 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11032 05:57:28.727523 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11033 05:57:28.742267 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11034 05:57:28.794923 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11035 05:57:28.830398 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11036 05:57:28.875120
11037 05:57:28.875282
11038 05:57:28.878600 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11039 05:57:28.878716
11040 05:57:28.881751 debian-bullseye-arm64 login: root (automatic login)
11041 05:57:28.881830
11042 05:57:28.881894
11043 05:57:28.899353 Linux debian-bullseye-arm64 6.1.67-cip12 #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023 aarch64
11044 05:57:28.899498
11045 05:57:28.905908 The programs included with the Debian GNU/Linux system are free software;
11046 05:57:28.912770 the exact distribution terms for each program are described in the
11047 05:57:28.915847 individual files in /usr/share/doc/*/copyright.
11048 05:57:28.915954
11049 05:57:28.922102 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11050 05:57:28.925941 permitted by applicable law.
11051 05:57:28.926570 Matched prompt #10: / #
11053 05:57:28.926891 Setting prompt string to ['/ #']
11054 05:57:28.927018 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11056 05:57:28.927331 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11057 05:57:28.927449 start: 2.2.6 expect-shell-connection (timeout 00:03:23) [common]
11058 05:57:28.927526 Setting prompt string to ['/ #']
11059 05:57:28.927591 Forcing a shell prompt, looking for ['/ #']
11061 05:57:28.977821 / #
11062 05:57:28.978019 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11063 05:57:28.978130 Waiting using forced prompt support (timeout 00:02:30)
11064 05:57:28.983294
11065 05:57:28.983601 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11066 05:57:28.983732 start: 2.2.7 export-device-env (timeout 00:03:22) [common]
11067 05:57:28.983858 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11068 05:57:28.983977 end: 2.2 depthcharge-retry (duration 00:01:38) [common]
11069 05:57:28.984096 end: 2 depthcharge-action (duration 00:01:38) [common]
11070 05:57:28.984218 start: 3 lava-test-retry (timeout 00:07:58) [common]
11071 05:57:28.984349 start: 3.1 lava-test-shell (timeout 00:07:58) [common]
11072 05:57:28.984453 Using namespace: common
11074 05:57:29.084811 / # #
11075 05:57:29.085014 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11076 05:57:29.090421 #
11077 05:57:29.090736 Using /lava-12379421
11079 05:57:29.191050 / # export SHELL=/bin/sh
11080 05:57:29.196082 export SHELL=/bin/sh
11082 05:57:29.296648 / # . /lava-12379421/environment
11083 05:57:29.302024 . /lava-12379421/environment
11085 05:57:29.402557 / # /lava-12379421/bin/lava-test-runner /lava-12379421/0
11086 05:57:29.402717 Test shell timeout: 10s (minimum of the action and connection timeout)
11087 05:57:29.407648 /lava-12379421/bin/lava-test-runner /lava-12379421/0
11088 05:57:29.422747 <6>[ 20.295466] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11089 05:57:29.434844 + export TESTRUN_ID=0_igt-kms-me<8>[ 20.305638] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 12379421_1.5.2.3.1>
11090 05:57:29.435165 Received signal: <STARTRUN> 0_igt-kms-mediatek 12379421_1.5.2.3.1
11091 05:57:29.435254 Starting test lava.0_igt-kms-mediatek (12379421_1.5.2.3.1)
11092 05:57:29.435344 Skipping test definition patterns.
11093 05:57:29.438041 diatek
11094 05:57:29.441353 + cd /lava-12379421/0/tests/0_igt-kms-mediatek
11095 05:57:29.441442 + cat uuid
11096 05:57:29.444439 + UUID=12379421_1.5.2.3.1
11097 05:57:29.444526 + set +x
11098 05:57:29.457753 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversi<8>[ 20.330756] <LAVA_SIGNAL_TESTSET START core_auth>
11099 05:57:29.458049 Received signal: <TESTSET> START core_auth
11100 05:57:29.458144 Starting test_set core_auth
11101 05:57:29.470955 on core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11102 05:57:29.478038 <14>[ 20.350577] [IGT] core_auth: executing
11103 05:57:29.484351 IGT-Version: 1.2<14>[ 20.355041] [IGT] core_auth: starting subtest getclient-simple
11104 05:57:29.494572 7.1-g621c2d3 (aa<14>[ 20.362663] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11105 05:57:29.497981 rch64) (Linux: 6<14>[ 20.371096] [IGT] core_auth: exiting, ret=0
11106 05:57:29.501459 .1.67-cip12 aarch64)
11107 05:57:29.504275 Starting subtest: getclient-simple
11108 05:57:29.511517 Opened<8>[ 20.381700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11109 05:57:29.511812 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11111 05:57:29.514397 device: /dev/dri/card0
11112 05:57:29.517944 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11113 05:57:29.529393 <14>[ 20.402205] [IGT] core_auth: executing
11114 05:57:29.536549 IGT-Version: 1.2<14>[ 20.406540] [IGT] core_auth: starting subtest getclient-master-drop
11115 05:57:29.546411 7.1-g621c2d3 (aa<14>[ 20.414599] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11116 05:57:29.552809 rch64) (Linux: 6<14>[ 20.423338] [IGT] core_auth: exiting, ret=0
11117 05:57:29.552909 .1.67-cip12 aarch64)
11118 05:57:29.556328 Starting subtest: getclient-master-drop
11119 05:57:29.565741 O<8>[ 20.433570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11120 05:57:29.565845 pened device: /dev/dri/card0
11121 05:57:29.566098 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11123 05:57:29.572712 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11124 05:57:29.582283 <14>[ 20.454770] [IGT] core_auth: executing
11125 05:57:29.588937 IGT-Version: 1.2<14>[ 20.459169] [IGT] core_auth: starting subtest basic-auth
11126 05:57:29.595316 7.1-g621c2d3 (aa<14>[ 20.466262] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11127 05:57:29.601976 <14>[ 20.473969] [IGT] core_auth: exiting, ret=0
11128 05:57:29.605640 rch64) (Linux: 6.1.67-cip12 aarch64)
11129 05:57:29.612089 Opened device: /dev/dri/ca<8>[ 20.483103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11130 05:57:29.612322 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11132 05:57:29.615354 rd0
11133 05:57:29.615434 Starting subtest: basic-auth
11134 05:57:29.621481 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11135 05:57:29.630237 <14>[ 20.503216] [IGT] core_auth: executing
11136 05:57:29.637443 IGT-Version: 1.2<14>[ 20.507660] [IGT] core_auth: starting subtest many-magics
11137 05:57:29.640240 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11138 05:57:29.643711 Opened device: /dev/dri/card0
11139 05:57:29.650225 Starting su<14>[ 20.521610] [IGT] core_auth: finished subtest many-magics, SUCCESS
11140 05:57:29.656893 btest: many-magi<14>[ 20.529661] [IGT] core_auth: exiting, ret=0
11141 05:57:29.656982 cs
11142 05:57:29.660518 Reopening device failed after 1020 opens
11143 05:57:29.670281 [1mSubtest many-m<8>[ 20.539809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11144 05:57:29.670563 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11146 05:57:29.673558 agics: SUCCESS (0.007s)[0m
11147 05:57:29.676782 <8>[ 20.549439] <LAVA_SIGNAL_TESTSET STOP>
11148 05:57:29.677036 Received signal: <TESTSET> STOP
11149 05:57:29.677129 Closing test_set core_auth
11150 05:57:29.707750 <14>[ 20.580324] [IGT] core_getclient: executing
11151 05:57:29.714261 IGT-Version: 1.2<14>[ 20.585160] [IGT] core_getclient: exiting, ret=0
11152 05:57:29.717689 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11153 05:57:29.727275 Opened dev<8>[ 20.596121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11154 05:57:29.727378 ice: /dev/dri/card0
11155 05:57:29.727624 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11157 05:57:29.730994 SUCCESS (0.006s)
11158 05:57:29.759903 <14>[ 20.632697] [IGT] core_getstats: executing
11159 05:57:29.766435 IGT-Version: 1.2<14>[ 20.637435] [IGT] core_getstats: exiting, ret=0
11160 05:57:29.769867 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11161 05:57:29.779529 Opened dev<8>[ 20.648411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11162 05:57:29.779616 ice: /dev/dri/card0
11163 05:57:29.779857 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11165 05:57:29.782833 SUCCESS (0.006s)
11166 05:57:29.811837 <14>[ 20.684900] [IGT] core_getversion: executing
11167 05:57:29.818949 IGT-Version: 1.2<14>[ 20.689817] [IGT] core_getversion: exiting, ret=0
11168 05:57:29.821838 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11169 05:57:29.831607 Opened dev<8>[ 20.700611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11170 05:57:29.831733 ice: /dev/dri/card0
11171 05:57:29.831973 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11173 05:57:29.835084 SUCCESS (0.006s)
11174 05:57:29.864593 <14>[ 20.737559] [IGT] core_setmaster_vs_auth: executing
11175 05:57:29.871218 IGT-Version: 1.2<14>[ 20.743195] [IGT] core_setmaster_vs_auth: exiting, ret=0
11176 05:57:29.878346 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11177 05:57:29.884746 Opened dev<8>[ 20.754921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11178 05:57:29.885025 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11180 05:57:29.888038 ice: /dev/dri/card0
11181 05:57:29.888121 SUCCESS (0.007s)
11182 05:57:29.905335 <8>[ 20.778039] <LAVA_SIGNAL_TESTSET START drm_read>
11183 05:57:29.905623 Received signal: <TESTSET> START drm_read
11184 05:57:29.905696 Starting test_set drm_read
11185 05:57:29.924415 <14>[ 20.797038] [IGT] drm_read: executing
11186 05:57:29.930795 IGT-Version: 1.2<14>[ 20.801696] [IGT] drm_read: exiting, ret=77
11187 05:57:29.934272 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11188 05:57:29.940803 Opened dev<8>[ 20.811822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11189 05:57:29.941060 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11191 05:57:29.944513 ice: /dev/dri/card0
11192 05:57:29.947791 No KMS driver or no outputs, pipes: 8, outputs: 0
11193 05:57:29.954067 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11194 05:57:29.957711 <14>[ 20.831837] [IGT] drm_read: executing
11195 05:57:29.964054 IGT-Version: 1.2<14>[ 20.836288] [IGT] drm_read: exiting, ret=77
11196 05:57:29.967655 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11197 05:57:29.977477 Opened dev<8>[ 20.846695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11198 05:57:29.977600 ice: /dev/dri/card0
11199 05:57:29.977879 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11201 05:57:29.983885 No KMS driver or no outputs, pipes: 8, outputs: 0
11202 05:57:29.987796 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11203 05:57:29.994333 <14>[ 20.867045] [IGT] drm_read: executing
11204 05:57:30.001382 IGT-Version: 1.2<14>[ 20.871492] [IGT] drm_read: exiting, ret=77
11205 05:57:30.004709 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11206 05:57:30.010824 Opened dev<8>[ 20.881673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11207 05:57:30.011089 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11209 05:57:30.014583 ice: /dev/dri/card0
11210 05:57:30.017285 No KMS driver or no outputs, pipes: 8, outputs: 0
11211 05:57:30.021109 [1mSubtest empty-block: SKIP (0.000s)[0m
11212 05:57:30.029540 <14>[ 20.901997] [IGT] drm_read: executing
11213 05:57:30.036188 IGT-Version: 1.2<14>[ 20.906578] [IGT] drm_read: exiting, ret=77
11214 05:57:30.039012 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11215 05:57:30.045617 Opened dev<8>[ 20.916604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11216 05:57:30.045880 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11218 05:57:30.049146 ice: /dev/dri/card0
11219 05:57:30.052563 No KMS driver or no outputs, pipes: 8, outputs: 0
11220 05:57:30.058882 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11221 05:57:30.062317 <14>[ 20.937610] [IGT] drm_read: executing
11222 05:57:30.069376 IGT-Version: 1.2<14>[ 20.942049] [IGT] drm_read: exiting, ret=77
11223 05:57:30.075771 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11224 05:57:30.082235 Opened dev<8>[ 20.952308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11225 05:57:30.082507 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11227 05:57:30.085788 ice: /dev/dri/card0
11228 05:57:30.088761 No KMS driver or no outputs, pipes: 8, outputs: 0
11229 05:57:30.092231 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11230 05:57:30.100217 <14>[ 20.972848] [IGT] drm_read: executing
11231 05:57:30.106500 IGT-Version: 1.2<14>[ 20.977289] [IGT] drm_read: exiting, ret=77
11232 05:57:30.109944 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11233 05:57:30.119587 Opened dev<8>[ 20.987530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11234 05:57:30.119709 ice: /dev/dri/card0
11235 05:57:30.119986 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11237 05:57:30.123072 No KMS driver or no outputs, pipes: 8, outputs: 0
11238 05:57:30.130206 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11239 05:57:30.133109 <14>[ 21.008334] [IGT] drm_read: executing
11240 05:57:30.139693 IGT-Version: 1.2<14>[ 21.012789] [IGT] drm_read: exiting, ret=77
11241 05:57:30.146128 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11242 05:57:30.153398 Opened dev<8>[ 21.023113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11243 05:57:30.153710 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11245 05:57:30.156175 ice: /dev/dri/card0
11246 05:57:30.159831 No KMS driv<8>[ 21.033080] <LAVA_SIGNAL_TESTSET STOP>
11247 05:57:30.160087 Received signal: <TESTSET> STOP
11248 05:57:30.160159 Closing test_set drm_read
11249 05:57:30.162651 er or no outputs, pipes: 8, outputs: 0
11250 05:57:30.169418 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11251 05:57:30.181127 <8>[ 21.053961] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11252 05:57:30.181405 Received signal: <TESTSET> START kms_addfb_basic
11253 05:57:30.181481 Starting test_set kms_addfb_basic
11254 05:57:30.201818 <14>[ 21.074526] [IGT] kms_addfb_basic: executing
11255 05:57:30.214716 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarc<14>[ 21.083597] [IGT] kms_addfb_basic: starting subtest unused-handle
11256 05:57:30.214825 h64)
11257 05:57:30.221571 Opened dev<14>[ 21.091404] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11258 05:57:30.224890 ice: /dev/dri/card0
11259 05:57:30.228305 Starting subtest: unused-handle
11260 05:57:30.234852 [1mSubtest unused-handle: SUCCESS (0.000s<14>[ 21.108088] [IGT] kms_addfb_basic: exiting, ret=0
11261 05:57:30.234966 )[0m
11262 05:57:30.248156 Test requirement not met in function igt_require_i915, fi<8>[ 21.118244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11263 05:57:30.248437 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11265 05:57:30.251281 le ../lib/drmtest.c:720:
11266 05:57:30.254744 Test requirement: is_i915_device(fd)
11267 05:57:30.264897 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<14>[ 21.138046] [IGT] kms_addfb_basic: executing
11268 05:57:30.264995 :
11269 05:57:30.268303 Test requirement: is_i915_device(fd)
11270 05:57:30.278258 No KMS driver or no out<14>[ 21.147740] [IGT] kms_addfb_basic: starting subtest unused-pitches
11271 05:57:30.288121 puts, pipes: 8, <14>[ 21.155573] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11272 05:57:30.288250 outputs: 0
11273 05:57:30.294716 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11274 05:57:30.300988 Opened device:<14>[ 21.172196] [IGT] kms_addfb_basic: exiting, ret=0
11275 05:57:30.301114 /dev/dri/card0
11276 05:57:30.304623 Starting subtest: unused-pitches
11277 05:57:30.314373 [1mSubtest unused-pitches: S<8>[ 21.183884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11278 05:57:30.314460 UCCESS (0.000s)[0m
11279 05:57:30.314703 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11281 05:57:30.324612 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11282 05:57:30.327439 Test requirement: is_i915_device(fd)
11283 05:57:30.330659 Te<14>[ 21.204213] [IGT] kms_addfb_basic: executing
11284 05:57:30.344270 st requirement not met in function igt_require_i915, file ../lib<14>[ 21.213391] [IGT] kms_addfb_basic: starting subtest unused-offsets
11285 05:57:30.344371 /drmtest.c:720:
11286 05:57:30.351019 <14>[ 21.221264] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11287 05:57:30.351111
11288 05:57:30.354355 Test requirement: is_i915_device(fd)
11289 05:57:30.360374 No KMS driver or no outputs, pipes: 8, outputs: 0
11290 05:57:30.367485 IGT-Ve<14>[ 21.238094] [IGT] kms_addfb_basic: exiting, ret=0
11291 05:57:30.370360 rsion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11292 05:57:30.377647 <8>[ 21.248101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11293 05:57:30.377915 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11295 05:57:30.380422 Opened device: /dev/dri/card0
11296 05:57:30.383878 Starting subtest: unused-offsets
11297 05:57:30.387198 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11298 05:57:30.396680 Test requirement not met in f<14>[ 21.268263] [IGT] kms_addfb_basic: executing
11299 05:57:30.400392 unction igt_require_i915, file ../lib/drmtest.c:720:
11300 05:57:30.406794 Test requi<14>[ 21.277598] [IGT] kms_addfb_basic: starting subtest unused-modifier
11301 05:57:30.416678 rement: is_i915_<14>[ 21.285744] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11302 05:57:30.416802 device(fd)
11303 05:57:30.423769 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11304 05:57:30.429783 T<14>[ 21.302515] [IGT] kms_addfb_basic: exiting, ret=0
11305 05:57:30.433800 est requirement: is_i915_device(fd)
11306 05:57:30.443542 No KMS driver or no outputs, pipes: 8, outp<8>[ 21.313636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11307 05:57:30.443840 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11309 05:57:30.446919 uts: 0
11310 05:57:30.449757 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11311 05:57:30.453310 Opened device: /dev/dri/card0
11312 05:57:30.456633 Starting subtest: unused-modifier
11313 05:57:30.463429 [1mSubtest unus<14>[ 21.334817] [IGT] kms_addfb_basic: executing
11314 05:57:30.466623 ed-modifier: SUCCESS (0.000s)[0m
11315 05:57:30.476302 Test requirement not met in f<14>[ 21.345000] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11316 05:57:30.483553 unction igt_requ<14>[ 21.353345] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11317 05:57:30.486415 ire_i915, file ../lib/drmtest.c:720:
11318 05:57:30.489946 Test requirement: is_i915_device(fd)
11319 05:57:30.496300 Test requirement not<14>[ 21.370493] [IGT] kms_addfb_basic: exiting, ret=77
11320 05:57:30.503162 met in function igt_require_i915, file ../lib/drmtest.c:720:
11321 05:57:30.513244 Test requirement:<8>[ 21.381499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11322 05:57:30.513336 is_i915_device(fd)
11323 05:57:30.513589 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11325 05:57:30.519695 No KMS driver or no outputs, pipes: 8, outputs: 0
11326 05:57:30.526317 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11327 05:57:30.532643 Opened device: /de<14>[ 21.403186] [IGT] kms_addfb_basic: executing
11328 05:57:30.532730 v/dri/card0
11329 05:57:30.536031 Starting subtest: clobberred-modifier
11330 05:57:30.545883 Test require<14>[ 21.413237] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11331 05:57:30.552176 ment not met in <14>[ 21.422398] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11332 05:57:30.559145 function igt_require_i915, file ../lib/drmtest.c:720:
11333 05:57:30.562354 Test requirement: is_i915_device(fd)
11334 05:57:30.568965 [1<14>[ 21.439996] [IGT] kms_addfb_basic: exiting, ret=77
11335 05:57:30.572460 mSubtest clobberred-modifier: SKIP (0.000s)[0m
11336 05:57:30.582015 Test requirement not met in fun<8>[ 21.451163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11337 05:57:30.582355 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11339 05:57:30.588946 ction igt_require_i915, file ../lib/drmtest.c:720:
11340 05:57:30.592666 Test requirement: is_i915_device(fd)
11341 05:57:30.602044 Test requirement not met in function igt_require_i915, file ../lib/drm<14>[ 21.473393] [IGT] kms_addfb_basic: executing
11342 05:57:30.602160 test.c:720:
11343 05:57:30.605555 Test requirement: is_i915_device(fd)
11344 05:57:30.611936 No KMS driver<14>[ 21.483567] [IGT] kms_addfb_basic: starting subtest legacy-format
11345 05:57:30.615072 or no outputs, pipes: 8, outputs: 0
11346 05:57:30.628735 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Li<14>[ 21.497451] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11347 05:57:30.628840 nux: 6.1.67-cip12 aarch64)
11348 05:57:30.631609 Opened device: /dev/dri/card0
11349 05:57:30.641620 Starting subtest: invalid-smem-bo-on-<14>[ 21.513467] [IGT] kms_addfb_basic: exiting, ret=0
11350 05:57:30.641752 discrete
11351 05:57:30.655388 Test requirement not met in function igt_require_intel, file ../lib/dr<8>[ 21.524538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11352 05:57:30.655506 mtest.c:715:
11353 05:57:30.655781 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11355 05:57:30.658323 Test requirement: is_intel_device(fd)
11356 05:57:30.664778 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11357 05:57:30.674809 Test requirement not met in function igt_requir<14>[ 21.545532] [IGT] kms_addfb_basic: executing
11358 05:57:30.677864 e_i915, file ../lib/drmtest.c:720:
11359 05:57:30.681404 Test requirement: is_i915_device(fd)
11360 05:57:30.687958 Test r<14>[ 21.558103] [IGT] kms_addfb_basic: starting subtest no-handle
11361 05:57:30.694816 equirement not m<14>[ 21.564715] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11362 05:57:30.701629 et in function igt_require_i915, file ../lib/drmtest.c:720:
11363 05:57:30.707648 Test requirement: i<14>[ 21.578873] [IGT] kms_addfb_basic: exiting, ret=0
11364 05:57:30.707731 s_i915_device(fd)
11365 05:57:30.714629 No KMS driver or no outputs, pipes: 8, outputs: 0
11366 05:57:30.721285 IGT-Versio<8>[ 21.590899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11367 05:57:30.721559 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11369 05:57:30.727705 n: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11370 05:57:30.727793 Opened device: /dev/dri/card0
11371 05:57:30.731478 Starting subtest: legacy-format
11372 05:57:30.741045 Successfully fuzzed 10000 {bpp, dept<14>[ 21.611594] [IGT] kms_addfb_basic: executing
11373 05:57:30.741129 h} variations
11374 05:57:30.744009 [1mSubtest legacy-format: SUCCESS (0.006s)[0m
11375 05:57:30.751254 Test requirement<14>[ 21.623934] [IGT] kms_addfb_basic: starting subtest basic
11376 05:57:30.760790 not met in func<14>[ 21.630205] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11377 05:57:30.764386 tion igt_require_i915, file ../lib/drmtest.c:720:
11378 05:57:30.771034 Test requirement: is_i915_dev<14>[ 21.643968] [IGT] kms_addfb_basic: exiting, ret=0
11379 05:57:30.774388 ice(fd)
11380 05:57:30.784083 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11382 05:57:30.787621 Test requirement not met in function igt_require_i915, file ../lib/drmt<8>[ 21.655897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11383 05:57:30.787708 est.c:720:
11384 05:57:30.790451 Test requirement: is_i915_device(fd)
11385 05:57:30.794115 No KMS driver or no outputs, pipes: 8, outputs: 0
11386 05:57:30.803692 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12<14>[ 21.676218] [IGT] kms_addfb_basic: executing
11387 05:57:30.803780 aarch64)
11388 05:57:30.807325 Opened device: /dev/dri/card0
11389 05:57:30.810265 Starting subtest: no-handle
11390 05:57:30.817248 [1mSubte<14>[ 21.688704] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11391 05:57:30.826810 st no-handle: SU<14>[ 21.695589] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11392 05:57:30.826902 CCESS (0.000s)[0m
11393 05:57:30.837392 Test requirement not met in function igt_require_i915, file <14>[ 21.709799] [IGT] kms_addfb_basic: exiting, ret=0
11394 05:57:30.840308 ../lib/drmtest.c:720:
11395 05:57:30.844006 Test requirement: is_i915_device(fd)
11396 05:57:30.850793 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11398 05:57:30.853382 Test requirement no<8>[ 21.721747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11399 05:57:30.856985 t met in function igt_require_i915, file ../lib/drmtest.c:720:
11400 05:57:30.859932 Test requirement: is_i915_device(fd)
11401 05:57:30.870187 No KMS driver or no outputs, pipes: 8, out<14>[ 21.742133] [IGT] kms_addfb_basic: executing
11402 05:57:30.870303 puts: 0
11403 05:57:30.876543 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11404 05:57:30.883230 O<14>[ 21.753548] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11405 05:57:30.890014 pened device: /d<14>[ 21.760552] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11406 05:57:30.893446 ev/dri/card0
11407 05:57:30.893556 Starting subtest: basic
11408 05:57:30.897134 [1mSubtest basic: SUCCESS (0.000s)[0m
11409 05:57:30.903096 <14>[ 21.774961] [IGT] kms_addfb_basic: exiting, ret=0
11410 05:57:30.916907 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<8>[ 21.787194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11411 05:57:30.917001 :
11412 05:57:30.917267 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11414 05:57:30.919866 Test requirement: is_i915_device(fd)
11415 05:57:30.926726 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11416 05:57:30.936401 Test requirement: is_i915_device(fd)<14>[ 21.807909] [IGT] kms_addfb_basic: executing
11417 05:57:30.936489
11418 05:57:30.939834 No KMS driver or no outputs, pipes: 8, outputs: 0
11419 05:57:30.949677 IGT-Version: 1.27.1-g621c2d<14>[ 21.820075] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11420 05:57:30.956394 3 (aarch64) (Lin<14>[ 21.827145] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11421 05:57:30.959859 ux: 6.1.67-cip12 aarch64)
11422 05:57:30.962902 Opened device: /dev/dri/card0
11423 05:57:30.969646 Starting subtest: bad-<14>[ 21.841459] [IGT] kms_addfb_basic: exiting, ret=0
11424 05:57:30.969756 pitch-0
11425 05:57:30.976184 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11426 05:57:30.982837 Test requirement not met<8>[ 21.853315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11427 05:57:30.983131 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11429 05:57:30.989434 in function igt_require_i915, file ../lib/drmtest.c:720:
11430 05:57:30.993165 Test requirement: is_i915_device(fd)
11431 05:57:31.003083 Test requirement not met in function igt_require_i915, file ../<14>[ 21.874556] [IGT] kms_addfb_basic: executing
11432 05:57:31.003200 lib/drmtest.c:720:
11433 05:57:31.006007 Test requirement: is_i915_device(fd)
11434 05:57:31.015445 No KMS driver or no ou<14>[ 21.886780] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11435 05:57:31.025672 tputs, pipes: 8,<14>[ 21.893817] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11436 05:57:31.025786 outputs: 0
11437 05:57:31.035253 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64<14>[ 21.908298] [IGT] kms_addfb_basic: exiting, ret=0
11438 05:57:31.035369 )
11439 05:57:31.038843 Opened device: /dev/dri/card0
11440 05:57:31.042419 Starting subtest: bad-pitch-32
11441 05:57:31.048898 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11443 05:57:31.051926 [1mSubtest ba<8>[ 21.920128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11444 05:57:31.052030 d-pitch-32: SUCCESS (0.000s)[0m
11445 05:57:31.062170 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11446 05:57:31.065597 Test requirement: is_i915_device(fd)
11447 05:57:31.068294 Test <14>[ 21.941128] [IGT] kms_addfb_basic: executing
11448 05:57:31.074907 requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11449 05:57:31.081477 Te<14>[ 21.953483] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11450 05:57:31.091930 st requirement: <14>[ 21.960698] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11451 05:57:31.092048 is_i915_device(fd)
11452 05:57:31.098477 No KMS driver or no outputs, pipes: 8, outputs: 0
11453 05:57:31.104901 IGT-Versi<14>[ 21.975071] [IGT] kms_addfb_basic: exiting, ret=0
11454 05:57:31.108177 on: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11455 05:57:31.118251 Opened device: /dev<8>[ 21.986931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11456 05:57:31.118359 /dri/card0
11457 05:57:31.118636 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11459 05:57:31.121294 Starting subtest: bad-pitch-63
11460 05:57:31.124920 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11461 05:57:31.134788 Test requirement not met in function igt_require_i915, file ../lib/d<14>[ 22.007868] [IGT] kms_addfb_basic: executing
11462 05:57:31.138348 rmtest.c:720:
11463 05:57:31.141217 Test requirement: is_i915_device(fd)
11464 05:57:31.147696 Test requirement not met in<14>[ 22.020303] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11465 05:57:31.157869 function igt_re<14>[ 22.027547] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11466 05:57:31.161469 quire_i915, file ../lib/drmtest.c:720:
11467 05:57:31.164955 Test requirement: is_i915_device(fd)
11468 05:57:31.170948 No<14>[ 22.042048] [IGT] kms_addfb_basic: exiting, ret=0
11469 05:57:31.174386 KMS driver or no outputs, pipes: 8, outputs: 0
11470 05:57:31.184169 IGT-Version: 1.<8>[ 22.053779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11471 05:57:31.184503 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11473 05:57:31.187791 27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11474 05:57:31.190874 Opened device: /dev/dri/card0
11475 05:57:31.194360 Starting subtest: bad-pitch-128
11476 05:57:31.201116 [1mSubtest bad-pitch-128: SUCCESS (0.000<14>[ 22.073527] [IGT] kms_addfb_basic: executing
11477 05:57:31.201237 s)[0m
11478 05:57:31.214176 Test requirement not met in function igt_require_i915, file ../lib/drmte<14>[ 22.086100] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11479 05:57:31.217440 st.c:720:
11480 05:57:31.224341 Test <14>[ 22.093192] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11481 05:57:31.227861 requirement: is_i915_device(fd)
11482 05:57:31.234327 Test requirement not met in function igt_requir<14>[ 22.107673] [IGT] kms_addfb_basic: exiting, ret=0
11483 05:57:31.237356 e_i915, file ../lib/drmtest.c:720:
11484 05:57:31.241011 Test requirement: is_i915_device(fd)
11485 05:57:31.250487 No KMS<8>[ 22.119705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11486 05:57:31.250804 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11488 05:57:31.254102 driver or no outputs, pipes: 8, outputs: 0
11489 05:57:31.260770 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11490 05:57:31.267370 Opened device: /dev/dri/card0<14>[ 22.140330] [IGT] kms_addfb_basic: executing
11491 05:57:31.267485
11492 05:57:31.270886 Starting subtest: bad-pitch-256
11493 05:57:31.280242 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[<14>[ 22.151634] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11494 05:57:31.280367 0m
11495 05:57:31.290281 Test require<14>[ 22.158778] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11496 05:57:31.296883 ment not met in function igt_require_i915, file ../lib/drmtest.c:720:
11497 05:57:31.300263 Test requ<14>[ 22.173302] [IGT] kms_addfb_basic: exiting, ret=0
11498 05:57:31.303533 irement: is_i915_device(fd)
11499 05:57:31.316701 Test requirement not met in function igt_require_i9<8>[ 22.185266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11500 05:57:31.316999 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11502 05:57:31.320380 15, file ../lib/drmtest.c:720:
11503 05:57:31.323366 Test requirement: is_i915_device(fd)
11504 05:57:31.326676 No KMS driver or no outputs, pipes: 8, outputs: 0
11505 05:57:31.333690 IGT-Version: 1.27.1-g621c2d3 (aarch64) <14>[ 22.206568] [IGT] kms_addfb_basic: executing
11506 05:57:31.336529 (Linux: 6.1.67-cip12 aarch64)
11507 05:57:31.340032 Opened device: /dev/dri/card0
11508 05:57:31.343789 Starting subtest: bad-pitch-1024
11509 05:57:31.350245 [1mSubtest bad-<14>[ 22.220887] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11510 05:57:31.360316 pitch-1024: SUCC<14>[ 22.229393] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11511 05:57:31.363239 ESS (0.000s)[0m
11512 05:57:31.369848 Test requirement not met in fu<14>[ 22.242482] [IGT] kms_addfb_basic: exiting, ret=0
11513 05:57:31.373499 nction igt_require_i915, file ../lib/drmtest.c:720:
11514 05:57:31.383125 Test requir<8>[ 22.253346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11515 05:57:31.383438 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11517 05:57:31.386918 ement: is_i915_device(fd)
11518 05:57:31.393591 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11519 05:57:31.400196 Test requirement: is_i915_device(f<14>[ 22.273557] [IGT] kms_addfb_basic: executing
11520 05:57:31.400318 d)
11521 05:57:31.406499 No KMS driver or no outputs, pipes: 8, outputs: 0
11522 05:57:31.416329 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip<14>[ 22.286821] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11523 05:57:31.416417 12 aarch64)
11524 05:57:31.426638 Ope<14>[ 22.294816] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11525 05:57:31.426769 ned device: /dev/dri/card0
11526 05:57:31.436305 Starting subtest: ba<14>[ 22.307579] [IGT] kms_addfb_basic: exiting, ret=0
11527 05:57:31.436478 d-pitch-999
11528 05:57:31.439731 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11529 05:57:31.449816 Test requirement n<8>[ 22.318742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11530 05:57:31.450145 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11532 05:57:31.456369 ot met in function igt_require_i915, file ../lib/drmtest.c:720:
11533 05:57:31.460111 Test requirement: is_i915_device(fd)
11534 05:57:31.466699 Test requirement not met in function igt_require_i915, fi<14>[ 22.339790] [IGT] kms_addfb_basic: executing
11535 05:57:31.469715 le ../lib/drmtest.c:720:
11536 05:57:31.473393 Test requirement: is_i915_device(fd)
11537 05:57:31.485902 No KMS driver or no outputs, pipes: 8, outputs: <14>[ 22.354412] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11538 05:57:31.486026 0
11539 05:57:31.493094 IGT-Version: <14>[ 22.362696] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11540 05:57:31.502656 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 a<14>[ 22.375955] [IGT] kms_addfb_basic: exiting, ret=0
11541 05:57:31.502776 arch64)
11542 05:57:31.505733 Opened device: /dev/dri/card0
11543 05:57:31.515992 Starting subtest: bad-pi<8>[ 22.385680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11544 05:57:31.516307 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11546 05:57:31.519501 tch-65536
11547 05:57:31.522422 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11548 05:57:31.528892 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11549 05:57:31.532362 <14>[ 22.406845] [IGT] kms_addfb_basic: executing
11550 05:57:31.532476
11551 05:57:31.535750 Test requirement: is_i915_device(fd)
11552 05:57:31.549120 Test requirement not met in function igt_require_i915, file ../lib/drmtes<14>[ 22.420124] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11553 05:57:31.552236 t.c:720:
11554 05:57:31.559166 Test r<14>[ 22.428187] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11555 05:57:31.562244 equirement: is_i915_device(fd)
11556 05:57:31.568915 No KMS driver or<14>[ 22.441120] [IGT] kms_addfb_basic: exiting, ret=0
11557 05:57:31.572581 no outputs, pipes: 8, outputs: 0
11558 05:57:31.582309 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux<8>[ 22.452001] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11559 05:57:31.582607 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11561 05:57:31.585380 : 6.1.67-cip12 aarch64)
11562 05:57:31.588367 Opened device: /dev/dri/card0
11563 05:57:31.591834 Starting subtest: invalid-get-prop-any
11564 05:57:31.595157 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11565 05:57:31.601961 Test req<14>[ 22.473317] [IGT] kms_addfb_basic: executing
11566 05:57:31.608612 uirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11567 05:57:31.611503 Test requirement: is_i915_device(fd)
11568 05:57:31.618251 Test requiremen<14>[ 22.489555] [IGT] kms_addfb_basic: starting subtest master-rmfb
11569 05:57:31.628115 t not met in fun<14>[ 22.496862] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11570 05:57:31.634747 ction igt_require_i915, file ../<14>[ 22.507233] [IGT] kms_addfb_basic: exiting, ret=0
11571 05:57:31.638499 lib/drmtest.c:720:
11572 05:57:31.641384 Test requirement: is_i915_device(fd)
11573 05:57:31.648539 No KMS driver or no ou<8>[ 22.518998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11574 05:57:31.648807 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11576 05:57:31.651100 tputs, pipes: 8, outputs: 0
11577 05:57:31.658347 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11578 05:57:31.664951 Opened device: /dev/dri/card0<14>[ 22.537918] [IGT] kms_addfb_basic: executing
11579 05:57:31.665064
11580 05:57:31.668146 Starting subtest: invalid-get-prop
11581 05:57:31.671247 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11582 05:57:31.684364 Test requirement not met in function igt_require_i915,<14>[ 22.555019] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11583 05:57:31.694292 file ../lib/drm<14>[ 22.562874] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11584 05:57:31.694419 test.c:720:
11585 05:57:31.701240 Tes<14>[ 22.572630] [IGT] kms_addfb_basic: exiting, ret=0
11586 05:57:31.704874 t requirement: is_i915_device(fd)
11587 05:57:31.714477 Test requirement not met in function igt_requ<8>[ 22.584534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11588 05:57:31.714786 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11590 05:57:31.717447 ire_i915, file ../lib/drmtest.c:720:
11591 05:57:31.721150 Test requirement: is_i915_device(fd)
11592 05:57:31.727867 No KMS driver or no outputs, pipes: 8, outputs: 0
11593 05:57:31.734121 IGT-Version: 1.27.1-g621c2d3 (aar<14>[ 22.606523] [IGT] kms_addfb_basic: executing
11594 05:57:31.737727 ch64) (Linux: 6.1.67-cip12 aarch64)
11595 05:57:31.740799 Opened device: /dev/dri/card0
11596 05:57:31.744461 Starting subtest: invalid-set-prop-any
11597 05:57:31.754134 [1mSubtest invalid-set-prop-any: SU<14>[ 22.624704] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11598 05:57:31.757099 CCESS (0.000s)[0m
11599 05:57:31.767083 Test requirement not met in function igt_req<14>[ 22.637451] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11600 05:57:31.773628 uire_i915, file <14>[ 22.645426] [IGT] kms_addfb_basic: exiting, ret=98
11601 05:57:31.777011 ../lib/drmtest.c:720:
11602 05:57:31.780356 Test requirement: is_i915_device(fd)
11603 05:57:31.787008 Tes<8>[ 22.656394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11604 05:57:31.787304 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11606 05:57:31.793748 t requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11607 05:57:31.796654 Test requirement: is_i915_device(fd)
11608 05:57:31.807014 No KMS driver or no outputs, pipes: 8, out<14>[ 22.677917] [IGT] kms_addfb_basic: executing
11609 05:57:31.807106 puts: 0
11610 05:57:31.813233 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11611 05:57:31.816997 Opened device: /dev/dri/card0
11612 05:57:31.817082 Starting subtest: invalid-set-prop
11613 05:57:31.823664 [1mSubtest in<14>[ 22.696417] [IGT] kms_addfb_basic: exiting, ret=77
11614 05:57:31.826590 valid-set-prop: SUCCESS (0.000s)[0m
11615 05:57:31.839940 Test requirement not met i<8>[ 22.707339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11616 05:57:31.840247 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11618 05:57:31.843521 n function igt_require_i915, file ../lib/drmtest.c:720:
11619 05:57:31.846533 Test requirement: is_i915_device(fd)
11620 05:57:31.856995 Test requirement not met in function igt_require_<14>[ 22.728962] [IGT] kms_addfb_basic: executing
11621 05:57:31.859840 i915, file ../lib/drmtest.c:720:
11622 05:57:31.862833 Test requirement: is_i915_device(fd)
11623 05:57:31.866569 No KMS driver or no outputs, pipes: 8, outputs: 0
11624 05:57:31.876170 IGT-Version: 1.27.1-g621c2d3 (aarch64<14>[ 22.746811] [IGT] kms_addfb_basic: exiting, ret=77
11625 05:57:31.879912 ) (Linux: 6.1.67-cip12 aarch64)
11626 05:57:31.880020 Opened device: /dev/dri/card0
11627 05:57:31.889220 <8>[ 22.757720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11628 05:57:31.889525 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11630 05:57:31.892863 Starting subtest: master-rmfb
11631 05:57:31.896326 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11632 05:57:31.906529 Test requirement not met in function igt_require_i915, file ../lib<14>[ 22.778827] [IGT] kms_addfb_basic: executing
11633 05:57:31.906648 /drmtest.c:720:
11634 05:57:31.909799 Test requirement: is_i915_device(fd)
11635 05:57:31.919515 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11636 05:57:31.922709 Test requirement: is_i915_device(fd)
11637 05:57:31.925989 No KMS driver or no outputs, pipes: 8, outputs: 0
11638 05:57:31.932869 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11639 05:57:31.935726 Opened device: /dev/dri/card0
11640 05:57:31.939435 Starting subtest: addfb25-modifier-no-flag
11641 05:57:31.942840 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11642 05:57:31.949591 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11643 05:57:31.952392 Test requirement: is_i915_device(fd)
11644 05:57:31.962776 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11645 05:57:31.965855 Test requirement: is_i915_device(fd)
11646 05:57:31.969599 No KMS driver or no outputs, pipes: 8, outputs: 0
11647 05:57:31.975576 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11648 05:57:31.979278 Opened device: /dev/dri/card0
11649 05:57:31.982309 Starting subtest: addfb25-bad-modifier
11650 05:57:31.992252 (kms_addfb_basic:431) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11651 05:57:32.009378 (kms_addfb_basic:431) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11652 05:57:32.012300 (kms_addfb_basic:431) CRITICAL: error: 0 != -1
11653 05:57:32.015567 Stack trace:
11654 05:57:32.019022 #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11655 05:57:32.022633 #1 [<unknown>+0xc90b47e0]
11656 05:57:32.025495 #2 [<unknown>+0xc90b6278]
11657 05:57:32.025614 #3 [<unknown>+0xc90b167c]
11658 05:57:32.029021 #4 [__libc_start_main+0xe8]
11659 05:57:32.032602 #5 [<unknown>+0xc90b16b4]
11660 05:57:32.035898 #6 [<unknown>+0xc90b16b4]
11661 05:57:32.039401 Subtest addfb25-bad-modifier failed.
11662 05:57:32.039515 **** DEBUG ****
11663 05:57:32.048747 (kms_addfb_basic:431) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11664 05:57:32.058944 (kms_addfb_basic:431) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11665 05:57:32.075277 (kms_addfb_basic:431) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11666 05:57:32.078415 (kms_addfb_basic:431) CRITICAL: error: 0 != -1
11667 05:57:32.085034 (kms_addfb_basic:431) igt_core-INFO: Stack trace:
11668 05:57:32.091687 (kms_addfb_basic:431) igt_core-INFO: #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11669 05:57:32.098401 (kms_addfb_basic:431) igt_core-INFO: #1 [<unknown>+0xc90b47e0]
11670 05:57:32.101962 (kms_addfb_basic:431) igt_core-INFO: #2 [<unknown>+0xc90b6278]
11671 05:57:32.108290 (kms_addfb_basic:431) igt_core-INFO: #3 [<unknown>+0xc90b167c]
11672 05:57:32.114587 (kms_addfb_basic:431) igt_core-INFO: #4 [__libc_start_main+0xe8]
11673 05:57:32.121163 (kms_addfb_basic:431) igt_core-INFO: #5 [<unknown>+0xc90b16b4]
11674 05:57:32.124932 (kms_addfb_basic:431) igt_core-INFO: #6 [<unknown>+0xc90b16b4]
11675 05:57:32.128280 **** END ****
11676 05:57:32.131139 [1mSubtest addfb25-bad-modifier: FAIL (0.005s)[0m
11677 05:57:32.137782 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11678 05:57:32.141597 Test requirement: is_i915_device(fd)
11679 05:57:32.151262 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11680 05:57:32.154278 Test requirement: is_i915_device(fd)
11681 05:57:32.157708 No KMS driver or no outputs, pipes: 8, outputs: 0
11682 05:57:32.164646 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11683 05:57:32.167417 Opened device: /dev/dri/card0
11684 05:57:32.173988 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11685 05:57:32.177600 Test requirement: is_i915_device(fd)
11686 05:57:32.180817 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11687 05:57:32.190742 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11688 05:57:32.194298 Test requirement: is_i915_device(fd)
11689 05:57:32.197244 No KMS driver or no outputs, pipes: 8, outputs: 0
11690 05:57:32.204033 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11691 05:57:32.207031 Opened device: /dev/dri/card0
11692 05:57:32.214241 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11693 05:57:32.217568 Test requirement: is_i915_device(fd)
11694 05:57:32.220189 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11695 05:57:32.227448 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11696 05:57:32.230694 Test requirement: is_i915_device(fd)
11697 05:57:32.236878 No KMS driver or no outputs, pipes: 8, outputs: 0
11698 05:57:32.243889 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11699 05:57:32.243975 Opened device: /dev/dri/card0
11700 05:57:32.256835 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:<14>[ 23.129052] [IGT] kms_addfb_basic: exiting, ret=77
11701 05:57:32.256924
11702 05:57:32.260367 Test requirement: is_i915_device(fd)
11703 05:57:32.269849 [1mSubtest addfb25-fram<8>[ 23.139925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11704 05:57:32.270117 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11706 05:57:32.276979 ebuffer-vs-set-tiling: SKIP (0.000s)[0m
11707 05:57:32.283559 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11708 05:57:32.290301 Test requirement: i<14>[ 23.161523] [IGT] kms_addfb_basic: executing
11709 05:57:32.290444 s_i915_device(fd)
11710 05:57:32.293489 No KMS driver or no outputs, pipes: 8, outputs: 0
11711 05:57:32.300041 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11712 05:57:32.306560 Opened device: /dev/<14>[ 23.179455] [IGT] kms_addfb_basic: exiting, ret=77
11713 05:57:32.309633 dri/card0
11714 05:57:32.319656 Test requirement not met in function igt_require_i915<8>[ 23.190723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11715 05:57:32.320015 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11717 05:57:32.323411 , file ../lib/drmtest.c:720:
11718 05:57:32.326264 Test requirement: is_i915_device(fd)
11719 05:57:32.339840 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c<14>[ 23.211257] [IGT] kms_addfb_basic: executing
11720 05:57:32.340014 :720:
11721 05:57:32.342960 Test requirement: is_i915_device(fd)
11722 05:57:32.346584 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11723 05:57:32.352822 No KMS driver or no outputs, pipes: 8, outputs: 0
11724 05:57:32.356087 IGT-Version<14>[ 23.229098] [IGT] kms_addfb_basic: exiting, ret=77
11725 05:57:32.363219 : 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11726 05:57:32.369608 Opene<8>[ 23.239987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11727 05:57:32.369970 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11729 05:57:32.373205 d device: /dev/dri/card0
11730 05:57:32.379857 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11731 05:57:32.389936 Test requirement: is_i915_device(fd<14>[ 23.261144] [IGT] kms_addfb_basic: executing
11732 05:57:32.390125 )
11733 05:57:32.396408 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11734 05:57:32.399301 Test requirement: is_i915_device(fd)
11735 05:57:32.406167 [1mSubtest framebuf<14>[ 23.278870] [IGT] kms_addfb_basic: exiting, ret=77
11736 05:57:32.409119 fer-vs-set-tiling: SKIP (0.000s)[0m
11737 05:57:32.419178 No KMS driver or no output<8>[ 23.288553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11738 05:57:32.419476 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11740 05:57:32.422727 s, pipes: 8, outputs: 0
11741 05:57:32.425990 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11742 05:57:32.429442 Opened device: /dev/dri/card0
11743 05:57:32.436169 Test requirement n<14>[ 23.309548] [IGT] kms_addfb_basic: executing
11744 05:57:32.442568 ot met in function igt_require_i915, file ../lib/drmtest.c:720:
11745 05:57:32.446064 Test requirement: is_i915_device(fd)
11746 05:57:32.455695 Test requirement not met in function igt_require_i915, fi<14>[ 23.327188] [IGT] kms_addfb_basic: exiting, ret=77
11747 05:57:32.459425 le ../lib/drmtest.c:720:
11748 05:57:32.462506 Test requirement: is_i915_device(fd)
11749 05:57:32.469350 <8>[ 23.338063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11750 05:57:32.469605 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11752 05:57:32.472269 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11753 05:57:32.479605 No KMS driver or no outputs, pipes: 8, outputs: 0
11754 05:57:32.486027 IGT-Version: 1.27.1-g621c2d3 (aarch64) (L<14>[ 23.358843] [IGT] kms_addfb_basic: executing
11755 05:57:32.488894 inux: 6.1.67-cip12 aarch64)
11756 05:57:32.492438 Opened device: /dev/dri/card0
11757 05:57:32.498992 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11758 05:57:32.505475 Test requirement:<14>[ 23.376859] [IGT] kms_addfb_basic: exiting, ret=77
11759 05:57:32.505600 is_i915_device(fd)
11760 05:57:32.518809 Test requirement not met in function igt_re<8>[ 23.387737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11761 05:57:32.519131 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11763 05:57:32.522330 quire_i915, file ../lib/drmtest.c:720:
11764 05:57:32.525273 Test requirement: is_i915_device(fd)
11765 05:57:32.528957 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11766 05:57:32.535324 No KMS driver<14>[ 23.407452] [IGT] kms_addfb_basic: executing
11767 05:57:32.538613 or no outputs, pipes: 8, outputs: 0
11768 05:57:32.545468 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11769 05:57:32.545583 Opened device: /dev/dri/card0
11770 05:57:32.555041 Test requirement not <14>[ 23.425242] [IGT] kms_addfb_basic: exiting, ret=77
11771 05:57:32.558776 met in function igt_require_i915, file ../lib/drmtest.c:720:
11772 05:57:32.565207 Te<8>[ 23.436530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11773 05:57:32.565473 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11775 05:57:32.568775 st requirement: is_i915_device(fd)
11776 05:57:32.575306 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11777 05:57:32.581892 Test requirement: is_i915<14>[ 23.456052] [IGT] kms_addfb_basic: executing
11778 05:57:32.585147 _device(fd)
11779 05:57:32.588799 No KMS driver or no outputs, pipes: 8, outputs: 0
11780 05:57:32.591769 [1mSubtest size-max: SKIP (0.000s)[0m
11781 05:57:32.602527 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-c<14>[ 23.473810] [IGT] kms_addfb_basic: exiting, ret=77
11782 05:57:32.602665 ip12 aarch64)
11783 05:57:32.605363 Opened device: /dev/dri/card0
11784 05:57:32.615310 Test requirement n<8>[ 23.485021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11785 05:57:32.615619 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11787 05:57:32.618839 ot met in function igt_require_i915, file ../lib/drmtest.c:720:
11788 05:57:32.622216 Test requirement: is_i915_device(fd)
11789 05:57:32.632299 Test requirement not met in function igt_<14>[ 23.504498] [IGT] kms_addfb_basic: executing
11790 05:57:32.635061 require_i915, file ../lib/drmtest.c:720:
11791 05:57:32.638620 Test requirement: is_i915_device(fd)
11792 05:57:32.641517 No KMS driver or no outputs, pipes: 8, outputs: 0
11793 05:57:32.652138 [1mSubtest too-wide: SKIP (0<14>[ 23.522508] [IGT] kms_addfb_basic: exiting, ret=77
11794 05:57:32.652233 .000s)[0m
11795 05:57:32.665015 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.6<8>[ 23.533327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11796 05:57:32.665108 7-cip12 aarch64)
11797 05:57:32.665355 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11799 05:57:32.668209 Opened device: /dev/dri/card0
11800 05:57:32.675213 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11801 05:57:32.681656 Test require<14>[ 23.553723] [IGT] kms_addfb_basic: executing
11802 05:57:32.681742 ment: is_i915_device(fd)
11803 05:57:32.691632 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11804 05:57:32.694524 Test requirement: is_i915_device(fd)
11805 05:57:32.701202 No KMS driver<14>[ 23.571239] [IGT] kms_addfb_basic: exiting, ret=77
11806 05:57:32.704424 or no outputs, pipes: 8, outputs: 0
11807 05:57:32.710875 [1mSubtest too-high: SKIP<8>[ 23.582223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11808 05:57:32.711136 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11810 05:57:32.714094 (0.000s)[0m
11811 05:57:32.718291 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11812 05:57:32.721294 Opened device: /dev/dri/card0
11813 05:57:32.727452 Test requirement not met in <14>[ 23.601490] [IGT] kms_addfb_basic: executing
11814 05:57:32.734798 function igt_require_i915, file ../lib/drmtest.c:720:
11815 05:57:32.737713 Test requirement: is_i915_device(fd)
11816 05:57:32.747304 Test requirement not met in function igt_require_i9<14>[ 23.619605] [IGT] kms_addfb_basic: exiting, ret=77
11817 05:57:32.751066 15, file ../lib/drmtest.c:720:
11818 05:57:32.760640 Test requirement: is_i915_device<8>[ 23.629914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11819 05:57:32.760819 (fd)
11820 05:57:32.761103 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11822 05:57:32.764169 No KMS driver or no outputs, pipes: 8, outputs: 0
11823 05:57:32.770548 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11824 05:57:32.777548 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Li<14>[ 23.650949] [IGT] kms_addfb_basic: executing
11825 05:57:32.780927 nux: 6.1.67-cip12 aarch64)
11826 05:57:32.784214 Opened device: /dev/dri/card0
11827 05:57:32.790364 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11828 05:57:32.794044 Te<14>[ 23.668260] [IGT] kms_addfb_basic: exiting, ret=77
11829 05:57:32.796941 st requirement: is_i915_device(fd)
11830 05:57:32.807515 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11832 05:57:32.810753 Test requirement not met in <8>[ 23.678196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11833 05:57:32.814200 function igt_require_i915, file ../lib/drmtest.c:720:
11834 05:57:32.816845 Test requirement: is_i915_device(fd)
11835 05:57:32.820201 No KMS driver or no outputs, pipes: 8, outputs: 0
11836 05:57:32.827454 <14>[ 23.699017] [IGT] kms_addfb_basic: executing
11837 05:57:32.830637 [1mSubtest small-bo: SKIP (0.000s)[0m
11838 05:57:32.837152 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11839 05:57:32.837238 Opened device: /dev/dri/card0
11840 05:57:32.844088 Te<14>[ 23.716640] [IGT] kms_addfb_basic: exiting, ret=77
11841 05:57:32.857050 st requirement not met in function igt_require_i915, file ../lib<8>[ 23.726624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11842 05:57:32.857320 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11844 05:57:32.860679 /drmtest.c:720:
11845 05:57:32.864097 Test requirement: is_i915_device(fd)
11846 05:57:32.870655 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11847 05:57:32.873599 Test r<14>[ 23.747420] [IGT] kms_addfb_basic: executing
11848 05:57:32.877056 equirement: is_i915_device(fd)
11849 05:57:32.880596 No KMS driver or no outputs, pipes: 8, outputs: 0
11850 05:57:32.887026 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11851 05:57:32.893724 IGT-Version: 1.27.<14>[ 23.765203] [IGT] kms_addfb_basic: exiting, ret=77
11852 05:57:32.896904 1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11853 05:57:32.906983 Opened devic<8>[ 23.776513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11854 05:57:32.907247 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11856 05:57:32.909918 e: /dev/dri/card0
11857 05:57:32.917038 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11858 05:57:32.919951 Test requirement: is_i915_device(fd)
11859 05:57:32.923188 Test<14>[ 23.797392] [IGT] kms_addfb_basic: executing
11860 05:57:32.933177 requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11861 05:57:32.936641 Test requirement: is_i915_device(fd)
11862 05:57:32.943659 No KMS driver or no outputs, pipes: 8, outp<14>[ 23.815629] [IGT] kms_addfb_basic: exiting, ret=77
11863 05:57:32.943744 uts: 0
11864 05:57:32.950011 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11865 05:57:32.956481 I<8>[ 23.826767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11866 05:57:32.956740 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11868 05:57:32.963485 GT-Version: 1.27.1-g621c2d3 (aar<8>[ 23.836395] <LAVA_SIGNAL_TESTSET STOP>
11869 05:57:32.963759 Received signal: <TESTSET> STOP
11870 05:57:32.963831 Closing test_set kms_addfb_basic
11871 05:57:32.966267 ch64) (Linux: 6.1.67-cip12 aarch64)
11872 05:57:32.969930 Opened device: /dev/dri/card0
11873 05:57:32.976438 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11874 05:57:32.979274 Test requirement: is_i915_device(fd)
11875 05:57:32.986519 Tes<8>[ 23.857988] <LAVA_SIGNAL_TESTSET START kms_atomic>
11876 05:57:32.986793 Received signal: <TESTSET> START kms_atomic
11877 05:57:32.986867 Starting test_set kms_atomic
11878 05:57:32.993104 t requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11879 05:57:32.996150 Test requirement: is_i915_device(fd)
11880 05:57:33.002658 No KMS driver or no output<14>[ 23.875593] [IGT] kms_atomic: executing
11881 05:57:33.009669 s, pipes: 8, out<14>[ 23.880661] [IGT] kms_atomic: exiting, ret=77
11882 05:57:33.009795 puts: 0
11883 05:57:33.013026 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11884 05:57:33.022822 <8>[ 23.891007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11885 05:57:33.022955
11886 05:57:33.023228 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11888 05:57:33.029246 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11889 05:57:33.029367 Opened device: /dev/dri/card0
11890 05:57:33.039390 Test requirement not met in function igt_require_i915, fil<14>[ 23.912630] [IGT] kms_atomic: executing
11891 05:57:33.045998 e ../lib/drmtest<14>[ 23.918056] [IGT] kms_atomic: exiting, ret=77
11892 05:57:33.046114 .c:720:
11893 05:57:33.048929 Test requirement: is_i915_device(fd)
11894 05:57:33.058733 Test requirement <8>[ 23.928483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11895 05:57:33.059024 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11897 05:57:33.065788 not met in function igt_require_i915, file ../lib/drmtest.c:720:
11898 05:57:33.069247 Test requirement: is_i915_device(fd)
11899 05:57:33.071841 No KMS driver or no outputs, pipes: 8, outputs: 0
11900 05:57:33.075243 [1mS<14>[ 23.949978] [IGT] kms_atomic: executing
11901 05:57:33.081889 ubtest addfb25-y<14>[ 23.955569] [IGT] kms_atomic: exiting, ret=77
11902 05:57:33.085514 -tiled-small-legacy: SKIP (0.000s)[0m
11903 05:57:33.098760 IGT-Version: 1.27.1-g621<8>[ 23.965928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11904 05:57:33.099022 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11906 05:57:33.102595 c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11907 05:57:33.105730 Opened device: /dev/dri/card0
11908 05:57:33.115083 Test requirement not met in function igt_require_i915, file ../lib/<14>[ 23.987889] [IGT] kms_atomic: executing
11909 05:57:33.115169 drmtest.c:720:
11910 05:57:33.122280 <14>[ 23.992951] [IGT] kms_atomic: exiting, ret=77
11911 05:57:33.125226 Test requirement: is_i915_device(fd)
11912 05:57:33.135229 Test requirement not met i<8>[ 24.003196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11913 05:57:33.135490 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11915 05:57:33.138158 n function igt_require_i915, file ../lib/drmtest.c:720:
11916 05:57:33.141709 Test requirement: is_i915_device(fd)
11917 05:57:33.151550 No KMS driver or no outputs, pipes: 8, outputs: 0<14>[ 24.024223] [IGT] kms_atomic: executing
11918 05:57:33.151646
11919 05:57:33.158272 [1mSubtest ad<14>[ 24.029067] [IGT] kms_atomic: exiting, ret=77
11920 05:57:33.158378 dfb25-4-tiled: SKIP (0.000s)[0m
11921 05:57:33.167869 IGT-Version: 1.27.1-g621c2d3 (<8>[ 24.039269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11922 05:57:33.168183 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11924 05:57:33.171517 aarch64) (Linux: 6.1.67-cip12 aarch64)
11925 05:57:33.174583 Opened device: /dev/dri/card0
11926 05:57:33.181597 No KMS driver or no outputs, pipes: 8, outputs: 0
11927 05:57:33.187993 [1mSubtest plane-overlay-legacy: SKIP<14>[ 24.059924] [IGT] kms_atomic: executing
11928 05:57:33.188120 (0.000s)[0m
11929 05:57:33.194861 I<14>[ 24.065665] [IGT] kms_atomic: exiting, ret=77
11930 05:57:33.208222 GT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch<8>[ 24.075886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11931 05:57:33.208345 64)
11932 05:57:33.208591 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11934 05:57:33.211139 Opened device: /dev/dri/card0
11935 05:57:33.214204 No KMS driver or no outputs, pipes: 8, outputs: 0
11936 05:57:33.217872 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
11937 05:57:33.224527 IGT-<14>[ 24.096648] [IGT] kms_atomic: executing
11938 05:57:33.227499 Version: 1.27.1-<14>[ 24.101705] [IGT] kms_atomic: exiting, ret=77
11939 05:57:33.234197 g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11940 05:57:33.240792 Opened device:<8>[ 24.111885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11941 05:57:33.241082 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11943 05:57:33.244278 /dev/dri/card0
11944 05:57:33.247867 No KMS driver or no outputs, pipes: 8, outputs: 0
11945 05:57:33.254416 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
11946 05:57:33.260792 IGT-Versi<14>[ 24.132910] [IGT] kms_atomic: executing
11947 05:57:33.264201 on: 1.27.1-g621c<14>[ 24.137848] [IGT] kms_atomic: exiting, ret=77
11948 05:57:33.271049 2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11949 05:57:33.280782 Opened device: /dev<8>[ 24.148081] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11950 05:57:33.280874 /dri/card0
11951 05:57:33.281114 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11953 05:57:33.283905 No KMS driver or no outputs, pipes: 8, outputs: 0
11954 05:57:33.290524 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
11955 05:57:33.297186 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linu<14>[ 24.170306] [IGT] kms_atomic: executing
11956 05:57:33.303654 x: 6.1.67-cip12 <14>[ 24.175936] [IGT] kms_atomic: exiting, ret=77
11957 05:57:33.303739 aarch64)
11958 05:57:33.307272 Opened device: /dev/dri/card0
11959 05:57:33.317547 No KMS driver or no out<8>[ 24.186089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11960 05:57:33.317810 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11962 05:57:33.320615 puts, pipes: 8, outputs: 0
11963 05:57:33.323902 [1mSubtest test-only: SKIP (0.000s)[0m
11964 05:57:33.330128 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11965 05:57:33.334085 Open<14>[ 24.207341] [IGT] kms_atomic: executing
11966 05:57:33.340651 ed device: /dev/<14>[ 24.211967] [IGT] kms_atomic: exiting, ret=77
11967 05:57:33.340768 dri/card0
11968 05:57:33.344039 No KMS driver or no outputs, pipes: 8, outputs: 0
11969 05:57:33.353723 [<8>[ 24.222208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11970 05:57:33.354030 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11972 05:57:33.356726 1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11973 05:57:33.363377 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11974 05:57:33.370283 Opened device: /dev/dri/<14>[ 24.243630] [IGT] kms_atomic: executing
11975 05:57:33.370391 card0
11976 05:57:33.376899 No KMS dr<14>[ 24.248619] [IGT] kms_atomic: exiting, ret=77
11977 05:57:33.380098 iver or no outputs, pipes: 8, outputs: 0
11978 05:57:33.389951 [1mSubtest plane-inva<8>[ 24.258915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11979 05:57:33.390243 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11981 05:57:33.393334 lid-params: SKIP (0.000s)[0m
11982 05:57:33.396981 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11983 05:57:33.400026 Opened device: /dev/dri/card0
11984 05:57:33.406729 No KMS drive<14>[ 24.279821] [IGT] kms_atomic: executing
11985 05:57:33.413427 r or no outputs,<14>[ 24.284812] [IGT] kms_atomic: exiting, ret=77
11986 05:57:33.413513 pipes: 8, outputs: 0
11987 05:57:33.426319 [1mSubtest plane-invalid-params-fence: S<8>[ 24.295054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
11988 05:57:33.426610 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
11990 05:57:33.429570 KIP (0.000s)[0m<8>[ 24.305137] <LAVA_SIGNAL_TESTSET STOP>
11991 05:57:33.429649
11992 05:57:33.429884 Received signal: <TESTSET> STOP
11993 05:57:33.429952 Closing test_set kms_atomic
11994 05:57:33.436678 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11995 05:57:33.440111 Opened device: /dev/dri/card0
11996 05:57:33.442983 No KMS driver or no outputs, pipes: 8, outputs: 0
11997 05:57:33.453009 [1mSubtest crtc-inval<8>[ 24.323682] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
11998 05:57:33.453299 Received signal: <TESTSET> START kms_flip_event_leak
11999 05:57:33.453401 Starting test_set kms_flip_event_leak
12000 05:57:33.456671 id-params: SKIP (0.000s)[0m
12001 05:57:33.459638 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12002 05:57:33.463375 Opened device: /dev/dri/card0
12003 05:57:33.469352 No KMS driver or no outputs, <14>[ 24.343860] [IGT] kms_flip_event_leak: executing
12004 05:57:33.479855 pipes: 8, output<14>[ 24.349739] [IGT] kms_flip_event_leak: exiting, ret=77
12005 05:57:33.479940 s: 0
12006 05:57:33.482749 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
12007 05:57:33.489668 <8>[ 24.361117] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12008 05:57:33.489924 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12010 05:57:33.496426 IGT-Version: 1.27.1-g621c2d3 (aa<8>[ 24.369822] <LAVA_SIGNAL_TESTSET STOP>
12011 05:57:33.496679 Received signal: <TESTSET> STOP
12012 05:57:33.496750 Closing test_set kms_flip_event_leak
12013 05:57:33.499190 rch64) (Linux: 6.1.67-cip12 aarch64)
12014 05:57:33.502907 Opened device: /dev/dri/card0
12015 05:57:33.506199 No KMS driver or no outputs, pipes: 8, outputs: 0
12016 05:57:33.512459 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
12017 05:57:33.519593 IGT-Version: 1.27.<8>[ 24.390549] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12018 05:57:33.519848 Received signal: <TESTSET> START kms_prop_blob
12019 05:57:33.519954 Starting test_set kms_prop_blob
12020 05:57:33.522434 1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12021 05:57:33.526272 Opened device: /dev/dri/card0
12022 05:57:33.529190 No KMS driver or no outputs, pipes: 8, outputs: 0
12023 05:57:33.535789 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
12024 05:57:33.539341 IGT-Ve<14>[ 24.412719] [IGT] kms_prop_blob: executing
12025 05:57:33.546106 rsion: 1.27.1-g6<14>[ 24.418773] [IGT] kms_prop_blob: starting subtest basic
12026 05:57:33.555539 21c2d3 (aarch64)<14>[ 24.425370] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12027 05:57:33.559348 <14>[ 24.433150] [IGT] kms_prop_blob: exiting, ret=0
12028 05:57:33.562311 (Linux: 6.1.67-cip12 aarch64)
12029 05:57:33.565598 Opened device: /dev/dri/card0
12030 05:57:33.572208 N<8>[ 24.442557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12031 05:57:33.572496 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12033 05:57:33.575190 o KMS driver or no outputs, pipes: 8, outputs: 0
12034 05:57:33.579046 [1mSubtest basic: SKIP (0.000s)[0m
12035 05:57:33.588625 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-ci<14>[ 24.461669] [IGT] kms_prop_blob: executing
12036 05:57:33.588707 p12 aarch64)
12037 05:57:33.595174 Op<14>[ 24.467366] [IGT] kms_prop_blob: starting subtest blob-prop-core
12038 05:57:33.605420 ened device: /de<14>[ 24.474928] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12039 05:57:33.611773 <14>[ 24.483487] [IGT] kms_prop_blob: exiting, ret=0
12040 05:57:33.611855 v/dri/card0
12041 05:57:33.615402 Starting subtest: basic
12042 05:57:33.621430 [1mSubtest basic: SUCCESS<8>[ 24.492741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12043 05:57:33.621712 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12045 05:57:33.625410 (0.000s)[0m
12046 05:57:33.631953 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12047 05:57:33.632064 Opened device: /dev/dri/card0
12048 05:57:33.638564 Starting subtest: blob-prop-<14>[ 24.513564] [IGT] kms_prop_blob: executing
12049 05:57:33.641563 core
12050 05:57:33.648226 [1mSubtes<14>[ 24.518539] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12051 05:57:33.658292 t blob-prop-core<14>[ 24.526441] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12052 05:57:33.661815 <14>[ 24.535283] [IGT] kms_prop_blob: exiting, ret=0
12053 05:57:33.664665 : SUCCESS (0.000s)[0m
12054 05:57:33.674875 IGT-Version: 1.27.1-g621c2d3 (aarch64) (<8>[ 24.544725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12055 05:57:33.675180 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12057 05:57:33.678087 Linux: 6.1.67-cip12 aarch64)
12058 05:57:33.681308 Opened device: /dev/dri/card0
12059 05:57:33.684684 Starting subtest: blob-prop-validate
12060 05:57:33.691084 [1mSubtest blob-prop-validate: SUCCESS (0.00<14>[ 24.565678] [IGT] kms_prop_blob: executing
12061 05:57:33.691201 0s)[0m
12062 05:57:33.697922 <14>[ 24.570669] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12063 05:57:33.708190 IGT-Version: 1.2<14>[ 24.577942] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12064 05:57:33.715285 7.1-g621c2d3 (aa<14>[ 24.586817] [IGT] kms_prop_blob: exiting, ret=0
12065 05:57:33.718230 rch64) (Linux: 6.1.67-cip12 aarch64)
12066 05:57:33.727782 Opened device: /dev/dri/ca<8>[ 24.597475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12067 05:57:33.727872 rd0
12068 05:57:33.728147 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12070 05:57:33.730953 Starting subtest: blob-prop-lifetime
12071 05:57:33.737913 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12072 05:57:33.745638 <14>[ 24.618335] [IGT] kms_prop_blob: executing
12073 05:57:33.751637 IGT-Version: 1.2<14>[ 24.623166] [IGT] kms_prop_blob: starting subtest blob-multiple
12074 05:57:33.761963 7.1-g621c2d3 (aa<14>[ 24.630783] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12075 05:57:33.764797 <14>[ 24.639182] [IGT] kms_prop_blob: exiting, ret=0
12076 05:57:33.768539 rch64) (Linux: 6.1.67-cip12 aarch64)
12077 05:57:33.771435 Opened device: /dev/dri/card0
12078 05:57:33.778750 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12080 05:57:33.781456 Starting su<8>[ 24.649702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12081 05:57:33.781533 btest: blob-multiple
12082 05:57:33.785016 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12083 05:57:33.797404 <14>[ 24.670782] [IGT] kms_prop_blob: executing
12084 05:57:33.804158 IGT-Version: 1.2<14>[ 24.675523] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12085 05:57:33.813814 7.1-g621c2d3 (aa<14>[ 24.683691] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12086 05:57:33.820965 <14>[ 24.692759] [IGT] kms_prop_blob: exiting, ret=0
12087 05:57:33.824066 rch64) (Linux: 6.1.67-cip12 aarch64)
12088 05:57:33.830881 Opened dev<8>[ 24.701803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12089 05:57:33.831169 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12091 05:57:33.833754 ice: /dev/dri/card0
12092 05:57:33.837389 Starting subtest: invalid-get-prop-any
12093 05:57:33.840254 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12094 05:57:33.848729 <14>[ 24.721726] [IGT] kms_prop_blob: executing
12095 05:57:33.855358 IGT-Version: 1.2<14>[ 24.726574] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12096 05:57:33.864899 7.1-g621c2d3 (aa<14>[ 24.734307] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12097 05:57:33.868425 <14>[ 24.743023] [IGT] kms_prop_blob: exiting, ret=0
12098 05:57:33.871980 rch64) (Linux: 6.1.67-cip12 aarch64)
12099 05:57:33.881783 Opened device: /dev/dri/ca<8>[ 24.752321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12100 05:57:33.881869 rd0
12101 05:57:33.882129 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12103 05:57:33.884679 Starting subtest: invalid-get-prop
12104 05:57:33.891289 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12105 05:57:33.900099 <14>[ 24.772823] [IGT] kms_prop_blob: executing
12106 05:57:33.906432 IGT-Version: 1.2<14>[ 24.777590] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12107 05:57:33.916212 7.1-g621c2d3 (aa<14>[ 24.785730] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12108 05:57:33.922635 <14>[ 24.794807] [IGT] kms_prop_blob: exiting, ret=0
12109 05:57:33.925990 rch64) (Linux: 6.1.67-cip12 aarch64)
12110 05:57:33.935678 Opened device: /dev/dri/ca<8>[ 24.804183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12111 05:57:33.935806 rd0
12112 05:57:33.936094 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12114 05:57:33.939404 Starting subtest: invalid-set-prop-any
12115 05:57:33.942293 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12116 05:57:33.952193 <14>[ 24.825375] [IGT] kms_prop_blob: executing
12117 05:57:33.958847 IGT-Version: 1.2<14>[ 24.830134] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12118 05:57:33.969159 7.1-g621c2d3 (aa<14>[ 24.838012] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12119 05:57:33.975470 rch64) (Linux: 6<14>[ 24.846674] [IGT] kms_prop_blob: exiting, ret=0
12120 05:57:33.975585 .1.67-cip12 aarch64)
12121 05:57:33.978291 Opened device: /dev/dri/card0
12122 05:57:33.988426 Starting su<8>[ 24.857204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12123 05:57:33.988549 btest: invalid-set-prop
12124 05:57:33.988829 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12126 05:57:33.995153 [1mSub<8>[ 24.867407] <LAVA_SIGNAL_TESTSET STOP>
12127 05:57:33.995441 Received signal: <TESTSET> STOP
12128 05:57:33.995544 Closing test_set kms_prop_blob
12129 05:57:33.998913 test invalid-set-prop: SUCCESS (0.000s)[0m
12130 05:57:34.014706 <8>[ 24.887926] <LAVA_SIGNAL_TESTSET START kms_setmode>
12131 05:57:34.014966 Received signal: <TESTSET> START kms_setmode
12132 05:57:34.015044 Starting test_set kms_setmode
12133 05:57:34.032259 <14>[ 24.905312] [IGT] kms_setmode: executing
12134 05:57:34.038394 IGT-Version: 1.2<14>[ 24.910051] [IGT] kms_setmode: starting subtest basic
12135 05:57:34.045661 7.1-g621c2d3 (aa<14>[ 24.916689] [IGT] kms_setmode: finished subtest basic, SKIP
12136 05:57:34.052094 rch64) (Linux: 6<14>[ 24.924201] [IGT] kms_setmode: exiting, ret=77
12137 05:57:34.055534 .1.67-cip12 aarch64)
12138 05:57:34.055620 Opened device: /dev/dri/card0
12139 05:57:34.065276 Starting su<8>[ 24.934598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12140 05:57:34.065362 btest: basic
12141 05:57:34.065605 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12143 05:57:34.068279 No dynamic tests executed.
12144 05:57:34.071895 [1mSubtest basic: SKIP (0.000s)[0m
12145 05:57:34.081143 <14>[ 24.953946] [IGT] kms_setmode: executing
12146 05:57:34.087351 IGT-Version: 1.2<14>[ 24.958666] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12147 05:57:34.097484 7.1-g621c2d3 (aa<14>[ 24.966849] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12148 05:57:34.103900 <14>[ 24.975756] [IGT] kms_setmode: exiting, ret=77
12149 05:57:34.107524 rch64) (Linux: 6.1.67-cip12 aarch64)
12150 05:57:34.114348 Opened dev<8>[ 24.984710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12151 05:57:34.114609 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12153 05:57:34.117394 ice: /dev/dri/card0
12154 05:57:34.120406 Starting subtest: basic-clone-single-crtc
12155 05:57:34.123875 No dynamic tests executed.
12156 05:57:34.127579 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12157 05:57:34.130396 <14>[ 25.005357] [IGT] kms_setmode: executing
12158 05:57:34.140763 IGT-Version: 1.2<14>[ 25.010262] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12159 05:57:34.150414 7.1-g621c2d3 (aa<14>[ 25.018565] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12160 05:57:34.153729 <14>[ 25.027627] [IGT] kms_setmode: exiting, ret=77
12161 05:57:34.157168 rch64) (Linux: 6.1.67-cip12 aarch64)
12162 05:57:34.167076 Opened device: /dev/dri/ca<8>[ 25.036726] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12163 05:57:34.167162 rd0
12164 05:57:34.167404 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12166 05:57:34.173633 Starting subtest: invalid-clone-single-crtc
12167 05:57:34.173767 No dynamic tests executed.
12168 05:57:34.180125 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12169 05:57:34.183094 <14>[ 25.058491] [IGT] kms_setmode: executing
12170 05:57:34.193644 IGT-Version: 1.2<14>[ 25.063105] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12171 05:57:34.203003 7.1-g621c2d3 (aa<14>[ 25.071733] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12172 05:57:34.206289 <14>[ 25.081073] [IGT] kms_setmode: exiting, ret=77
12173 05:57:34.209598 rch64) (Linux: 6.1.67-cip12 aarch64)
12174 05:57:34.223031 Opened device: /dev/dri/ca<8>[ 25.090325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12175 05:57:34.223118 rd0
12176 05:57:34.223360 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12178 05:57:34.226530 Starting subtest: invalid-clone-exclusive-crtc
12179 05:57:34.230082 No dynamic tests executed.
12180 05:57:34.233600 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12181 05:57:34.239975 <14>[ 25.111836] [IGT] kms_setmode: executing
12182 05:57:34.246616 IGT-Version: 1.2<14>[ 25.116845] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12183 05:57:34.256120 7.1-g621c2d3 (aa<14>[ 25.124771] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12184 05:57:34.259817 <14>[ 25.133421] [IGT] kms_setmode: exiting, ret=77
12185 05:57:34.262703 rch64) (Linux: 6.1.67-cip12 aarch64)
12186 05:57:34.273053 Opened device: /dev/dri/ca<8>[ 25.142535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12187 05:57:34.273155 rd0
12188 05:57:34.273430 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12190 05:57:34.276518 Starting subtest: clone-exclusive-crtc
12191 05:57:34.279819 No dynamic tests executed.
12192 05:57:34.283053 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12193 05:57:34.291399 <14>[ 25.164208] [IGT] kms_setmode: executing
12194 05:57:34.300932 IGT-Version: 1.2<14>[ 25.168835] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12195 05:57:34.311340 7.1-g621c2d3 (aa<14>[ 25.177991] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12196 05:57:34.314815 <14>[ 25.187849] [IGT] kms_setmode: exiting, ret=77
12197 05:57:34.317518 rch64) (Linux: 6.1.67-cip12 aarch64)
12198 05:57:34.328049 Opened device: /dev/dri/ca<8>[ 25.197071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12199 05:57:34.328328 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12201 05:57:34.331298 rd0
12202 05:57:34.334507 Starting su<8>[ 25.208530] <LAVA_SIGNAL_TESTSET STOP>
12203 05:57:34.334769 Received signal: <TESTSET> STOP
12204 05:57:34.334843 Closing test_set kms_setmode
12205 05:57:34.337407 btest: invalid-clone-single-crtc-stealing
12206 05:57:34.340889 No dynamic tests executed.
12207 05:57:34.347866 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12208 05:57:34.354214 <8>[ 25.227775] <LAVA_SIGNAL_TESTSET START kms_vblank>
12209 05:57:34.354480 Received signal: <TESTSET> START kms_vblank
12210 05:57:34.354556 Starting test_set kms_vblank
12211 05:57:34.372618 <14>[ 25.245934] [IGT] kms_vblank: executing
12212 05:57:34.379676 IGT-Version: 1.2<14>[ 25.250873] [IGT] kms_vblank: exiting, ret=77
12213 05:57:34.382663 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12214 05:57:34.389395 Opened dev<8>[ 25.261176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12215 05:57:34.389652 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12217 05:57:34.392620 ice: /dev/dri/card0
12218 05:57:34.395958 No KMS driver or no outputs, pipes: 8, outputs: 0
12219 05:57:34.399423 [1mSubtest invalid: SKIP (0.000s)[0m
12220 05:57:34.407382 <14>[ 25.280888] [IGT] kms_vblank: executing
12221 05:57:34.414616 IGT-Version: 1.2<14>[ 25.285597] [IGT] kms_vblank: exiting, ret=77
12222 05:57:34.417343 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12223 05:57:34.424282 Opened dev<8>[ 25.295818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12224 05:57:34.424581 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12226 05:57:34.427412 ice: /dev/dri/card0
12227 05:57:34.430964 No KMS driver or no outputs, pipes: 8, outputs: 0
12228 05:57:34.433735 [1mSubtest crtc-id: SKIP (0.000s)[0m
12229 05:57:34.443801 <14>[ 25.317118] [IGT] kms_vblank: executing
12230 05:57:34.450220 IGT-Version: 1.2<14>[ 25.321865] [IGT] kms_vblank: exiting, ret=77
12231 05:57:34.454074 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12232 05:57:34.464078 Opened dev<8>[ 25.332283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12233 05:57:34.464163 ice: /dev/dri/card0
12234 05:57:34.464404 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12236 05:57:34.470670 No KMS driver or no outputs, pipes: 8, outputs: 0
12237 05:57:34.473604 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12238 05:57:34.480609 <14>[ 25.352899] [IGT] kms_vblank: executing
12239 05:57:34.483469 IGT-Version: 1.2<14>[ 25.357658] [IGT] kms_vblank: exiting, ret=77
12240 05:57:34.490764 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12241 05:57:34.497213 Opened dev<8>[ 25.367949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12242 05:57:34.497470 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12244 05:57:34.500669 ice: /dev/dri/card0
12245 05:57:34.503565 No KMS driver or no outputs, pipes: 8, outputs: 0
12246 05:57:34.510590 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12247 05:57:34.513566 <14>[ 25.388357] [IGT] kms_vblank: executing
12248 05:57:34.520082 IGT-Version: 1.2<14>[ 25.393078] [IGT] kms_vblank: exiting, ret=77
12249 05:57:34.526700 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12250 05:57:34.533473 Opened dev<8>[ 25.403329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12251 05:57:34.533730 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12253 05:57:34.536560 ice: /dev/dri/card0
12254 05:57:34.539880 No KMS driver or no outputs, pipes: 8, outputs: 0
12255 05:57:34.546935 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12256 05:57:34.549818 <14>[ 25.424235] [IGT] kms_vblank: executing
12257 05:57:34.556839 IGT-Version: 1.2<14>[ 25.428967] [IGT] kms_vblank: exiting, ret=77
12258 05:57:34.559588 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12259 05:57:34.569898 Opened dev<8>[ 25.439242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12260 05:57:34.570159 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12262 05:57:34.573149 ice: /dev/dri/card0
12263 05:57:34.576070 No KMS driver or no outputs, pipes: 8, outputs: 0
12264 05:57:34.579829 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12265 05:57:34.586851 <14>[ 25.459897] [IGT] kms_vblank: executing
12266 05:57:34.593594 IGT-Version: 1.2<14>[ 25.464631] [IGT] kms_vblank: exiting, ret=77
12267 05:57:34.596467 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12268 05:57:34.606267 Opened dev<8>[ 25.475035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12269 05:57:34.606355 ice: /dev/dri/card0
12270 05:57:34.606595 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12272 05:57:34.612967 No KMS driver or no outputs, pipes: 8, outputs: 0
12273 05:57:34.616670 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12274 05:57:34.623156 <14>[ 25.495818] [IGT] kms_vblank: executing
12275 05:57:34.626818 IGT-Version: 1.2<14>[ 25.500560] [IGT] kms_vblank: exiting, ret=77
12276 05:57:34.632893 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12277 05:57:34.639684 Opened dev<8>[ 25.511064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12278 05:57:34.639943 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12280 05:57:34.643098 ice: /dev/dri/card0
12281 05:57:34.646564 No KMS driver or no outputs, pipes: 8, outputs: 0
12282 05:57:34.653018 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12283 05:57:34.656627 <14>[ 25.531660] [IGT] kms_vblank: executing
12284 05:57:34.663340 IGT-Version: 1.2<14>[ 25.536457] [IGT] kms_vblank: exiting, ret=77
12285 05:57:34.669446 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12286 05:57:34.676556 Opened dev<8>[ 25.546945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12287 05:57:34.676848 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12289 05:57:34.679244 ice: /dev/dri/card0
12290 05:57:34.682651 No KMS driver or no outputs, pipes: 8, outputs: 0
12291 05:57:34.689479 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12292 05:57:34.692934 <14>[ 25.567374] [IGT] kms_vblank: executing
12293 05:57:34.699496 IGT-Version: 1.2<14>[ 25.572119] [IGT] kms_vblank: exiting, ret=77
12294 05:57:34.705542 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12295 05:57:34.712552 Opened dev<8>[ 25.582436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12296 05:57:34.712863 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12298 05:57:34.715672 ice: /dev/dri/card0
12299 05:57:34.719473 No KMS driver or no outputs, pipes: 8, outputs: 0
12300 05:57:34.725532 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12301 05:57:34.729031 <14>[ 25.603649] [IGT] kms_vblank: executing
12302 05:57:34.735687 IGT-Version: 1.2<14>[ 25.608436] [IGT] kms_vblank: exiting, ret=77
12303 05:57:34.741931 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12304 05:57:34.748606 Opened dev<8>[ 25.618798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12305 05:57:34.748864 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12307 05:57:34.752178 ice: /dev/dri/card0
12308 05:57:34.755786 No KMS driver or no outputs, pipes: 8, outputs: 0
12309 05:57:34.762168 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12310 05:57:34.765446 <14>[ 25.640375] [IGT] kms_vblank: executing
12311 05:57:34.771859 IGT-Version: 1.2<14>[ 25.645094] [IGT] kms_vblank: exiting, ret=77
12312 05:57:34.778677 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12313 05:57:34.785282 Opened dev<8>[ 25.655234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12314 05:57:34.785558 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12316 05:57:34.789107 ice: /dev/dri/card0
12317 05:57:34.792022 No KMS driver or no outputs, pipes: 8, outputs: 0
12318 05:57:34.795709 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12319 05:57:34.802340 <14>[ 25.675690] [IGT] kms_vblank: executing
12320 05:57:34.809128 IGT-Version: 1.2<14>[ 25.680427] [IGT] kms_vblank: exiting, ret=77
12321 05:57:34.812419 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12322 05:57:34.822681 Opened dev<8>[ 25.691015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12323 05:57:34.822812 ice: /dev/dri/card0
12324 05:57:34.823086 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12326 05:57:34.828984 No KMS driver or no outputs, pipes: 8, outputs: 0
12327 05:57:34.832649 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12328 05:57:34.839285 <14>[ 25.711805] [IGT] kms_vblank: executing
12329 05:57:34.845898 IGT-Version: 1.2<14>[ 25.716619] [IGT] kms_vblank: exiting, ret=77
12330 05:57:34.848743 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12331 05:57:34.855165 Opened dev<8>[ 25.726910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12332 05:57:34.855483 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12334 05:57:34.858539 ice: /dev/dri/card0
12335 05:57:34.862164 No KMS driver or no outputs, pipes: 8, outputs: 0
12336 05:57:34.868954 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12337 05:57:34.872346 <14>[ 25.747482] [IGT] kms_vblank: executing
12338 05:57:34.878833 IGT-Version: 1.2<14>[ 25.752197] [IGT] kms_vblank: exiting, ret=77
12339 05:57:34.885429 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12340 05:57:34.891700 Opened dev<8>[ 25.762533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12341 05:57:34.891979 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12343 05:57:34.895466 ice: /dev/dri/card0
12344 05:57:34.899233 No KMS driver or no outputs, pipes: 8, outputs: 0
12345 05:57:34.905227 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12346 05:57:34.908982 <14>[ 25.783351] [IGT] kms_vblank: executing
12347 05:57:34.915643 IGT-Version: 1.2<14>[ 25.788167] [IGT] kms_vblank: exiting, ret=77
12348 05:57:34.921955 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12349 05:57:34.928675 Opened dev<8>[ 25.798401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12350 05:57:34.928933 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12352 05:57:34.931866 ice: /dev/dri/card0
12353 05:57:34.935077 No KMS driver or no outputs, pipes: 8, outputs: 0
12354 05:57:34.938290 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12355 05:57:34.945551 <14>[ 25.819023] [IGT] kms_vblank: executing
12356 05:57:34.952779 IGT-Version: 1.2<14>[ 25.823765] [IGT] kms_vblank: exiting, ret=77
12357 05:57:34.955727 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12358 05:57:34.965855 Opened dev<8>[ 25.833937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12359 05:57:34.965968 ice: /dev/dri/card0
12360 05:57:34.966238 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12362 05:57:34.972842 No KMS driver or no outputs, pipes: 8, outputs: 0
12363 05:57:34.975860 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12364 05:57:34.982553 <14>[ 25.855062] [IGT] kms_vblank: executing
12365 05:57:34.986100 IGT-Version: 1.2<14>[ 25.859812] [IGT] kms_vblank: exiting, ret=77
12366 05:57:34.992428 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12367 05:57:34.999405 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12369 05:57:35.002071 Opened dev<8>[ 25.870023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12370 05:57:35.002183 ice: /dev/dri/card0
12371 05:57:35.005998 No KMS driver or no outputs, pipes: 8, outputs: 0
12372 05:57:35.012576 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12373 05:57:35.019006 <14>[ 25.891357] [IGT] kms_vblank: executing
12374 05:57:35.021950 IGT-Version: 1.2<14>[ 25.896081] [IGT] kms_vblank: exiting, ret=77
12375 05:57:35.028818 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12376 05:57:35.038332 Opened dev<8>[ 25.906627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12377 05:57:35.038422 ice: /dev/dri/card0
12378 05:57:35.038662 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12380 05:57:35.045148 No KMS driver or no outputs, pipes: 8, outputs: 0
12381 05:57:35.048291 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12382 05:57:35.055248 <14>[ 25.927951] [IGT] kms_vblank: executing
12383 05:57:35.058729 IGT-Version: 1.2<14>[ 25.932670] [IGT] kms_vblank: exiting, ret=77
12384 05:57:35.065146 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12385 05:57:35.075498 Opened dev<8>[ 25.943088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12386 05:57:35.075603 ice: /dev/dri/card0
12387 05:57:35.075846 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12389 05:57:35.081774 No KMS driver or no outputs, pipes: 8, outputs: 0
12390 05:57:35.085130 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12391 05:57:35.092082 <14>[ 25.964246] [IGT] kms_vblank: executing
12392 05:57:35.095059 IGT-Version: 1.2<14>[ 25.969102] [IGT] kms_vblank: exiting, ret=77
12393 05:57:35.102046 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12394 05:57:35.111912 Opened dev<8>[ 25.979259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12395 05:57:35.111997 ice: /dev/dri/card0
12396 05:57:35.112234 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12398 05:57:35.118167 No KMS driver or no outputs, pipes: 8, outputs: 0
12399 05:57:35.121717 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12400 05:57:35.128114 <14>[ 26.000971] [IGT] kms_vblank: executing
12401 05:57:35.135296 IGT-Version: 1.2<14>[ 26.005823] [IGT] kms_vblank: exiting, ret=77
12402 05:57:35.138137 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12403 05:57:35.148078 Opened dev<8>[ 26.015962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12404 05:57:35.148179 ice: /dev/dri/card0
12405 05:57:35.148418 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12407 05:57:35.154579 No KMS driver or no outputs, pipes: 8, outputs: 0
12408 05:57:35.158009 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12409 05:57:35.164772 <14>[ 26.037597] [IGT] kms_vblank: executing
12410 05:57:35.171525 IGT-Version: 1.2<14>[ 26.042523] [IGT] kms_vblank: exiting, ret=77
12411 05:57:35.174718 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12412 05:57:35.185126 Opened dev<8>[ 26.052594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12413 05:57:35.185212 ice: /dev/dri/card0
12414 05:57:35.185451 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12416 05:57:35.191354 No KMS driver or no outputs, pipes: 8, outputs: 0
12417 05:57:35.198077 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12418 05:57:35.200851 <14>[ 26.074813] [IGT] kms_vblank: executing
12419 05:57:35.208127 IGT-Version: 1.2<14>[ 26.079716] [IGT] kms_vblank: exiting, ret=77
12420 05:57:35.211084 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12421 05:57:35.221103 Opened dev<8>[ 26.089853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12422 05:57:35.221360 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12424 05:57:35.224527 ice: /dev/dri/card0
12425 05:57:35.228028 No KMS driver or no outputs, pipes: 8, outputs: 0
12426 05:57:35.234366 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12427 05:57:35.237537 <14>[ 26.111599] [IGT] kms_vblank: executing
12428 05:57:35.244278 IGT-Version: 1.2<14>[ 26.116312] [IGT] kms_vblank: exiting, ret=77
12429 05:57:35.247978 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12430 05:57:35.257666 Opened dev<8>[ 26.126658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12431 05:57:35.257948 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12433 05:57:35.261185 ice: /dev/dri/card0
12434 05:57:35.264725 No KMS driver or no outputs, pipes: 8, outputs: 0
12435 05:57:35.271317 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12436 05:57:35.274157 <14>[ 26.148199] [IGT] kms_vblank: executing
12437 05:57:35.280953 IGT-Version: 1.2<14>[ 26.152927] [IGT] kms_vblank: exiting, ret=77
12438 05:57:35.284263 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12439 05:57:35.294322 Opened dev<8>[ 26.163075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12440 05:57:35.294635 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12442 05:57:35.297588 ice: /dev/dri/card0
12443 05:57:35.300633 No KMS driver or no outputs, pipes: 8, outputs: 0
12444 05:57:35.307398 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12445 05:57:35.310848 <14>[ 26.185126] [IGT] kms_vblank: executing
12446 05:57:35.317410 IGT-Version: 1.2<14>[ 26.190156] [IGT] kms_vblank: exiting, ret=77
12447 05:57:35.323918 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12448 05:57:35.330633 Opened dev<8>[ 26.200297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12449 05:57:35.330909 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12451 05:57:35.334181 ice: /dev/dri/card0
12452 05:57:35.337096 No KMS driver or no outputs, pipes: 8, outputs: 0
12453 05:57:35.343531 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12454 05:57:35.347000 <14>[ 26.222054] [IGT] kms_vblank: executing
12455 05:57:35.353505 IGT-Version: 1.2<14>[ 26.227155] [IGT] kms_vblank: exiting, ret=77
12456 05:57:35.360016 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12457 05:57:35.366942 Opened dev<8>[ 26.237350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12458 05:57:35.367250 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12460 05:57:35.370532 ice: /dev/dri/card0
12461 05:57:35.373399 No KMS driver or no outputs, pipes: 8, outputs: 0
12462 05:57:35.379875 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12463 05:57:35.383419 <14>[ 26.258013] [IGT] kms_vblank: executing
12464 05:57:35.389783 IGT-Version: 1.2<14>[ 26.262842] [IGT] kms_vblank: exiting, ret=77
12465 05:57:35.393382 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12466 05:57:35.403495 Opened dev<8>[ 26.272920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12467 05:57:35.403783 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12469 05:57:35.406322 ice: /dev/dri/card0
12470 05:57:35.409582 No KMS driver or no outputs, pipes: 8, outputs: 0
12471 05:57:35.413056 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12472 05:57:35.420926 <14>[ 26.293933] [IGT] kms_vblank: executing
12473 05:57:35.427476 IGT-Version: 1.2<14>[ 26.298820] [IGT] kms_vblank: exiting, ret=77
12474 05:57:35.430955 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12475 05:57:35.441133 Opened dev<8>[ 26.308840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12476 05:57:35.441253 ice: /dev/dri/card0
12477 05:57:35.441499 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12479 05:57:35.447716 No KMS driver or no outputs, pipes: 8, outputs: 0
12480 05:57:35.450792 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12481 05:57:35.457205 <14>[ 26.329806] [IGT] kms_vblank: executing
12482 05:57:35.460780 IGT-Version: 1.2<14>[ 26.334705] [IGT] kms_vblank: exiting, ret=77
12483 05:57:35.467072 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12484 05:57:35.473690 Opened dev<8>[ 26.344739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12485 05:57:35.473974 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12487 05:57:35.477032 ice: /dev/dri/card0
12488 05:57:35.480266 No KMS driver or no outputs, pipes: 8, outputs: 0
12489 05:57:35.487484 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12490 05:57:35.490746 <14>[ 26.365717] [IGT] kms_vblank: executing
12491 05:57:35.496898 IGT-Version: 1.2<14>[ 26.370569] [IGT] kms_vblank: exiting, ret=77
12492 05:57:35.503850 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12493 05:57:35.510349 Opened dev<8>[ 26.380693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12494 05:57:35.510689 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12496 05:57:35.513286 ice: /dev/dri/card0
12497 05:57:35.516882 No KMS driver or no outputs, pipes: 8, outputs: 0
12498 05:57:35.523249 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12499 05:57:35.526674 <14>[ 26.401369] [IGT] kms_vblank: executing
12500 05:57:35.533351 IGT-Version: 1.2<14>[ 26.406073] [IGT] kms_vblank: exiting, ret=77
12501 05:57:35.536703 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12502 05:57:35.546751 Opened dev<8>[ 26.416520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12503 05:57:35.547064 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12505 05:57:35.550257 ice: /dev/dri/card0
12506 05:57:35.553133 No KMS driver or no outputs, pipes: 8, outputs: 0
12507 05:57:35.556597 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12508 05:57:35.563880 <14>[ 26.436814] [IGT] kms_vblank: executing
12509 05:57:35.570420 IGT-Version: 1.2<14>[ 26.441549] [IGT] kms_vblank: exiting, ret=77
12510 05:57:35.573342 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12511 05:57:35.583469 Opened dev<8>[ 26.451676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12512 05:57:35.583582 ice: /dev/dri/card0
12513 05:57:35.583828 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12515 05:57:35.589758 No KMS driver or no outputs, pipes: 8, outputs: 0
12516 05:57:35.593010 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12517 05:57:35.599879 <14>[ 26.472745] [IGT] kms_vblank: executing
12518 05:57:35.603209 IGT-Version: 1.2<14>[ 26.477445] [IGT] kms_vblank: exiting, ret=77
12519 05:57:35.610007 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12520 05:57:35.620049 Opened dev<8>[ 26.487606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12521 05:57:35.620199 ice: /dev/dri/card0
12522 05:57:35.620481 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12524 05:57:35.622906 No KMS driver or no outputs, pipes: 8, outputs: 0
12525 05:57:35.629942 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12526 05:57:35.632829 <14>[ 26.508713] [IGT] kms_vblank: executing
12527 05:57:35.639850 IGT-Version: 1.2<14>[ 26.513559] [IGT] kms_vblank: exiting, ret=77
12528 05:57:35.646347 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12529 05:57:35.653750 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12531 05:57:35.656433 Opened dev<8>[ 26.523698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12532 05:57:35.656521 ice: /dev/dri/card0
12533 05:57:35.659977 No KMS driver or no outputs, pipes: 8, outputs: 0
12534 05:57:35.666410 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12535 05:57:35.675812 <14>[ 26.549076] [IGT] kms_vblank: executing
12536 05:57:35.682311 IGT-Version: 1.2<14>[ 26.553891] [IGT] kms_vblank: exiting, ret=77
12537 05:57:35.685984 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12538 05:57:35.692376 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12540 05:57:35.695814 Opened dev<8>[ 26.564187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12541 05:57:35.695906 ice: /dev/dri/card0
12542 05:57:35.699384 No KMS driver or no outputs, pipes: 8, outputs: 0
12543 05:57:35.705796 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12544 05:57:35.712252 <14>[ 26.585036] [IGT] kms_vblank: executing
12545 05:57:35.715684 IGT-Version: 1.2<14>[ 26.589770] [IGT] kms_vblank: exiting, ret=77
12546 05:57:35.722254 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12547 05:57:35.728913 Opened dev<8>[ 26.600077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12548 05:57:35.729206 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12550 05:57:35.732398 ice: /dev/dri/card0
12551 05:57:35.735345 No KMS driver or no outputs, pipes: 8, outputs: 0
12552 05:57:35.742155 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12553 05:57:35.745677 <14>[ 26.620849] [IGT] kms_vblank: executing
12554 05:57:35.752202 IGT-Version: 1.2<14>[ 26.625577] [IGT] kms_vblank: exiting, ret=77
12555 05:57:35.758769 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12556 05:57:35.765442 Opened dev<8>[ 26.635694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12557 05:57:35.765745 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12559 05:57:35.768470 ice: /dev/dri/card0
12560 05:57:35.772190 No KMS driver or no outputs, pipes: 8, outputs: 0
12561 05:57:35.775101 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12562 05:57:35.783027 <14>[ 26.656516] [IGT] kms_vblank: executing
12563 05:57:35.790175 IGT-Version: 1.2<14>[ 26.661252] [IGT] kms_vblank: exiting, ret=77
12564 05:57:35.793056 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12565 05:57:35.803510 Opened dev<8>[ 26.671390] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12566 05:57:35.803639 ice: /dev/dri/card0
12567 05:57:35.803917 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12569 05:57:35.809824 No KMS driver or no outputs, pipes: 8, outputs: 0
12570 05:57:35.813419 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12571 05:57:35.820074 <14>[ 26.693330] [IGT] kms_vblank: executing
12572 05:57:35.826766 IGT-Version: 1.2<14>[ 26.698115] [IGT] kms_vblank: exiting, ret=77
12573 05:57:35.829805 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12574 05:57:35.839952 Opened dev<8>[ 26.708348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12575 05:57:35.840113 ice: /dev/dri/card0
12576 05:57:35.840396 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12578 05:57:35.842905 No KMS driver or no outputs, pipes: 8, outputs: 0
12579 05:57:35.849724 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12580 05:57:35.852985 <14>[ 26.728693] [IGT] kms_vblank: executing
12581 05:57:35.859647 IGT-Version: 1.2<14>[ 26.733432] [IGT] kms_vblank: exiting, ret=77
12582 05:57:35.866344 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12583 05:57:35.872717 Opened dev<8>[ 26.743679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12584 05:57:35.873026 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12586 05:57:35.876080 ice: /dev/dri/card0
12587 05:57:35.879446 No KMS driver or no outputs, pipes: 8, outputs: 0
12588 05:57:35.886491 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12589 05:57:35.889782 <14>[ 26.764489] [IGT] kms_vblank: executing
12590 05:57:35.896009 IGT-Version: 1.2<14>[ 26.769231] [IGT] kms_vblank: exiting, ret=77
12591 05:57:35.903101 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12592 05:57:35.909440 Opened dev<8>[ 26.779380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12593 05:57:35.909736 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12595 05:57:35.913049 ice: /dev/dri/card0
12596 05:57:35.915941 No KMS driver or no outputs, pipes: 8, outputs: 0
12597 05:57:35.922333 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12598 05:57:35.925856 <14>[ 26.800722] [IGT] kms_vblank: executing
12599 05:57:35.932548 IGT-Version: 1.2<14>[ 26.805466] [IGT] kms_vblank: exiting, ret=77
12600 05:57:35.939026 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12601 05:57:35.945986 Opened dev<8>[ 26.815604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12602 05:57:35.946295 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12604 05:57:35.949503 ice: /dev/dri/card0
12605 05:57:35.952442 No KMS driver or no outputs, pipes: 8, outputs: 0
12606 05:57:35.958950 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12607 05:57:35.962420 <14>[ 26.837559] [IGT] kms_vblank: executing
12608 05:57:35.969297 IGT-Version: 1.2<14>[ 26.842334] [IGT] kms_vblank: exiting, ret=77
12609 05:57:35.975715 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12610 05:57:35.982065 Opened dev<8>[ 26.852475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12611 05:57:35.982375 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12613 05:57:35.985283 ice: /dev/dri/card0
12614 05:57:35.989381 No KMS driver or no outputs, pipes: 8, outputs: 0
12615 05:57:35.995559 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12616 05:57:35.998894 <14>[ 26.873592] [IGT] kms_vblank: executing
12617 05:57:36.005608 IGT-Version: 1.2<14>[ 26.878337] [IGT] kms_vblank: exiting, ret=77
12618 05:57:36.008663 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12619 05:57:36.019407 Opened dev<8>[ 26.888771] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12620 05:57:36.019719 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12622 05:57:36.022100 ice: /dev/dri/card0
12623 05:57:36.025763 No KMS driver or no outputs, pipes: 8, outputs: 0
12624 05:57:36.032358 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12625 05:57:36.035240 <14>[ 26.910086] [IGT] kms_vblank: executing
12626 05:57:36.042331 IGT-Version: 1.2<14>[ 26.915017] [IGT] kms_vblank: exiting, ret=77
12627 05:57:36.048688 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12628 05:57:36.055605 Opened dev<8>[ 26.925425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12629 05:57:36.055909 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12631 05:57:36.058503 ice: /dev/dri/card0
12632 05:57:36.062100 No KMS driver or no outputs, pipes: 8, outputs: 0
12633 05:57:36.068848 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12634 05:57:36.077031 <14>[ 26.950507] [IGT] kms_vblank: executing
12635 05:57:36.083691 IGT-Version: 1.2<14>[ 26.955341] [IGT] kms_vblank: exiting, ret=77
12636 05:57:36.087316 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12637 05:57:36.096902 Opened dev<8>[ 26.965514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12638 05:57:36.097213 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12640 05:57:36.100232 ice: /dev/dri/card0
12641 05:57:36.103672 No KMS driver or no outputs, pipes: 8, outputs: 0
12642 05:57:36.110057 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12643 05:57:36.113918 <14>[ 26.988156] [IGT] kms_vblank: executing
12644 05:57:36.120253 IGT-Version: 1.2<14>[ 26.992889] [IGT] kms_vblank: exiting, ret=77
12645 05:57:36.123565 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12646 05:57:36.133545 Opened dev<8>[ 27.003059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12647 05:57:36.133864 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12649 05:57:36.136580 ice: /dev/dri/card0
12650 05:57:36.139820 No KMS driver or no outputs, pipes: 8, outputs: 0
12651 05:57:36.146812 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12652 05:57:36.150354 <14>[ 27.024409] [IGT] kms_vblank: executing
12653 05:57:36.156948 IGT-Version: 1.2<14>[ 27.029372] [IGT] kms_vblank: exiting, ret=77
12654 05:57:36.159720 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12655 05:57:36.169955 Opened dev<8>[ 27.039440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12656 05:57:36.170263 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12658 05:57:36.172928 ice: /dev/dri/card0
12659 05:57:36.176363 No KMS driver or no outputs, pipes: 8, outputs: 0
12660 05:57:36.183071 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12661 05:57:36.186617 <14>[ 27.061038] [IGT] kms_vblank: executing
12662 05:57:36.193202 IGT-Version: 1.2<14>[ 27.065778] [IGT] kms_vblank: exiting, ret=77
12663 05:57:36.196219 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12664 05:57:36.206194 Opened dev<8>[ 27.075985] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12665 05:57:36.206498 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12667 05:57:36.209515 ice: /dev/dri/card0
12668 05:57:36.212912 No KMS driver or no outputs, pipes: 8, outputs: 0
12669 05:57:36.219550 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12670 05:57:36.222886 <14>[ 27.097755] [IGT] kms_vblank: executing
12671 05:57:36.229860 IGT-Version: 1.2<14>[ 27.103148] [IGT] kms_vblank: exiting, ret=77
12672 05:57:36.236260 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12673 05:57:36.245940 Opened dev<8>[ 27.113341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12674 05:57:36.246070 ice: /dev/dri/card0
12675 05:57:36.246344 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12677 05:57:36.252637 No KMS driver or no outputs, pipes: 8, outputs: 0
12678 05:57:36.255960 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12679 05:57:36.262753 <14>[ 27.135395] [IGT] kms_vblank: executing
12680 05:57:36.266502 IGT-Version: 1.2<14>[ 27.140219] [IGT] kms_vblank: exiting, ret=77
12681 05:57:36.272801 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12682 05:57:36.279545 Opened dev<8>[ 27.150566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12683 05:57:36.279868 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12685 05:57:36.283220 ice: /dev/dri/card0
12686 05:57:36.286298 No KMS driver or no outputs, pipes: 8, outputs: 0
12687 05:57:36.292854 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12688 05:57:36.296256 <14>[ 27.171329] [IGT] kms_vblank: executing
12689 05:57:36.302818 IGT-Version: 1.2<14>[ 27.176052] [IGT] kms_vblank: exiting, ret=77
12690 05:57:36.309413 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12691 05:57:36.315991 Opened dev<8>[ 27.186260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12692 05:57:36.316301 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12694 05:57:36.319642 ice: /dev/dri/card0
12695 05:57:36.322497 No KMS driver or no outputs, pipes: 8, outputs: 0
12696 05:57:36.325976 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12697 05:57:36.333662 <14>[ 27.206850] [IGT] kms_vblank: executing
12698 05:57:36.340026 IGT-Version: 1.2<14>[ 27.211577] [IGT] kms_vblank: exiting, ret=77
12699 05:57:36.343042 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12700 05:57:36.353056 Opened dev<8>[ 27.221643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12701 05:57:36.353218 ice: /dev/dri/card0
12702 05:57:36.353499 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12704 05:57:36.360207 No KMS driver or no outputs, pipes: 8, outputs: 0
12705 05:57:36.363008 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12706 05:57:36.369956 <14>[ 27.242800] [IGT] kms_vblank: executing
12707 05:57:36.376391 IGT-Version: 1.2<14>[ 27.247519] [IGT] kms_vblank: exiting, ret=77
12708 05:57:36.379629 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12709 05:57:36.386648 Opened dev<8>[ 27.257698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12710 05:57:36.386989 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12712 05:57:36.389446 ice: /dev/dri/card0
12713 05:57:36.393141 No KMS driver or no outputs, pipes: 8, outputs: 0
12714 05:57:36.399653 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12715 05:57:36.403296 <14>[ 27.278607] [IGT] kms_vblank: executing
12716 05:57:36.409673 IGT-Version: 1.2<14>[ 27.283525] [IGT] kms_vblank: exiting, ret=77
12717 05:57:36.416804 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12718 05:57:36.423336 Opened dev<8>[ 27.293787] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12719 05:57:36.423669 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12721 05:57:36.426173 ice: /dev/dri/card0
12722 05:57:36.429910 No KMS driver or no outputs, pipes: 8, outputs: 0
12723 05:57:36.436310 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12724 05:57:36.439317 <14>[ 27.314864] [IGT] kms_vblank: executing
12725 05:57:36.446430 IGT-Version: 1.2<14>[ 27.319634] [IGT] kms_vblank: exiting, ret=77
12726 05:57:36.452955 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12727 05:57:36.459852 Opened dev<8>[ 27.329742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12728 05:57:36.460165 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12730 05:57:36.462586 ice: /dev/dri/card0
12731 05:57:36.466301 No KMS driver or no outputs, pipes: 8, outputs: 0
12732 05:57:36.469265 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12733 05:57:36.477374 <14>[ 27.350432] [IGT] kms_vblank: executing
12734 05:57:36.483780 IGT-Version: 1.2<14>[ 27.355168] [IGT] kms_vblank: exiting, ret=77
12735 05:57:36.487155 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12736 05:57:36.496769 Opened dev<8>[ 27.365250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12737 05:57:36.496931 ice: /dev/dri/card0
12738 05:57:36.497209 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12740 05:57:36.503272 No KMS driver or no outputs, pipes: 8, outputs: 0
12741 05:57:36.506980 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12742 05:57:36.513626 <14>[ 27.386616] [IGT] kms_vblank: executing
12743 05:57:36.517352 IGT-Version: 1.2<14>[ 27.391342] [IGT] kms_vblank: exiting, ret=77
12744 05:57:36.523565 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12745 05:57:36.533814 Opened dev<8>[ 27.401404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12746 05:57:36.533945 ice: /dev/dri/card0
12747 05:57:36.534191 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12749 05:57:36.537382 No KMS driver or no outputs, pipes: 8, outputs: 0
12750 05:57:36.543725 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12751 05:57:36.546825 <14>[ 27.422798] [IGT] kms_vblank: executing
12752 05:57:36.553426 IGT-Version: 1.2<14>[ 27.427525] [IGT] kms_vblank: exiting, ret=77
12753 05:57:36.560718 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12754 05:57:36.570128 Opened dev<8>[ 27.437698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12755 05:57:36.570264 ice: /dev/dri/card0
12756 05:57:36.570531 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12758 05:57:36.573375 No KMS driver or no outputs, pipes: 8, outputs: 0
12759 05:57:36.580083 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12760 05:57:36.583754 <14>[ 27.459362] [IGT] kms_vblank: executing
12761 05:57:36.590224 IGT-Version: 1.2<14>[ 27.464090] [IGT] kms_vblank: exiting, ret=77
12762 05:57:36.597204 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12763 05:57:36.603745 Opened dev<8>[ 27.474325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12764 05:57:36.604046 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12766 05:57:36.607268 ice: /dev/dri/card0
12767 05:57:36.609960 No KMS driver or no outputs, pipes: 8, outputs: 0
12768 05:57:36.613254 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12769 05:57:36.621839 <14>[ 27.494964] [IGT] kms_vblank: executing
12770 05:57:36.628389 IGT-Version: 1.2<14>[ 27.499695] [IGT] kms_vblank: exiting, ret=77
12771 05:57:36.631786 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12772 05:57:36.641547 Opened dev<8>[ 27.509856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12773 05:57:36.641741 ice: /dev/dri/card0
12774 05:57:36.642003 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12776 05:57:36.647921 No KMS driver or no outputs, pipes: 8, outputs: 0
12777 05:57:36.651450 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12778 05:57:36.658075 <14>[ 27.530895] [IGT] kms_vblank: executing
12779 05:57:36.664905 IGT-Version: 1.2<14>[ 27.535758] [IGT] kms_vblank: exiting, ret=77
12780 05:57:36.667756 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12781 05:57:36.674204 Opened dev<8>[ 27.545865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12782 05:57:36.674506 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12784 05:57:36.677643 ice: /dev/dri/card0
12785 05:57:36.680944 No KMS driver or no outputs, pipes: 8, outputs: 0
12786 05:57:36.687660 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12787 05:57:36.691301 <14>[ 27.566516] [IGT] kms_vblank: executing
12788 05:57:36.697864 IGT-Version: 1.2<14>[ 27.571303] [IGT] kms_vblank: exiting, ret=77
12789 05:57:36.704504 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12790 05:57:36.711231 Opened dev<8>[ 27.581457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12791 05:57:36.711568 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12793 05:57:36.713951 ice: /dev/dri/card0
12794 05:57:36.717494 No KMS driver or no outputs, pipes: 8, outputs: 0
12795 05:57:36.724412 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12796 05:57:36.727862 <14>[ 27.602750] [IGT] kms_vblank: executing
12797 05:57:36.734216 IGT-Version: 1.2<14>[ 27.607455] [IGT] kms_vblank: exiting, ret=77
12798 05:57:36.740615 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12799 05:57:36.747368 Opened dev<8>[ 27.617672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12800 05:57:36.747732 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12802 05:57:36.750914 ice: /dev/dri/card0
12803 05:57:36.754380 No KMS driver or no outputs, pipes: 8, outputs: 0
12804 05:57:36.757349 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12805 05:57:36.765002 <14>[ 27.638168] [IGT] kms_vblank: executing
12806 05:57:36.771482 IGT-Version: 1.2<14>[ 27.642905] [IGT] kms_vblank: exiting, ret=77
12807 05:57:36.775033 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12808 05:57:36.784806 Opened dev<8>[ 27.653053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12809 05:57:36.784937 ice: /dev/dri/card0
12810 05:57:36.785184 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12812 05:57:36.791337 No KMS driver or no outputs, pipes: 8, outputs: 0
12813 05:57:36.795063 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12814 05:57:36.801325 <14>[ 27.674507] [IGT] kms_vblank: executing
12815 05:57:36.807952 IGT-Version: 1.2<14>[ 27.679298] [IGT] kms_vblank: exiting, ret=77
12816 05:57:36.811314 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12817 05:57:36.821307 Opened dev<8>[ 27.689377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12818 05:57:36.821479 ice: /dev/dri/card0
12819 05:57:36.821749 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12821 05:57:36.827995 No KMS driver or no outputs, pipes: 8, outputs: 0
12822 05:57:36.830720 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12823 05:57:36.837638 <14>[ 27.710896] [IGT] kms_vblank: executing
12824 05:57:36.843878 IGT-Version: 1.2<14>[ 27.715633] [IGT] kms_vblank: exiting, ret=77
12825 05:57:36.847312 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12826 05:57:36.857293 Opened dev<8>[ 27.725789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12827 05:57:36.857453 ice: /dev/dri/card0
12828 05:57:36.857772 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12830 05:57:36.864755 No KMS driver or no outputs, pipes: 8, outputs: 0
12831 05:57:36.867611 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12832 05:57:36.874271 <14>[ 27.747287] [IGT] kms_vblank: executing
12833 05:57:36.881029 IGT-Version: 1.2<14>[ 27.752062] [IGT] kms_vblank: exiting, ret=77
12834 05:57:36.884070 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12835 05:57:36.894284 Opened dev<8>[ 27.762249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12836 05:57:36.894462 ice: /dev/dri/card0
12837 05:57:36.894751 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12839 05:57:36.901042 No KMS driver or no outputs, pipes: 8, outputs: 0
12840 05:57:36.904030 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12841 05:57:36.910647 <14>[ 27.783546] [IGT] kms_vblank: executing
12842 05:57:36.913662 IGT-Version: 1.2<14>[ 27.788277] [IGT] kms_vblank: exiting, ret=77
12843 05:57:36.920486 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12844 05:57:36.930209 Opened dev<8>[ 27.798601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12845 05:57:36.930377 ice: /dev/dri/card0
12846 05:57:36.930660 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12848 05:57:36.936860 No KMS driver or no outputs, pipes: 8, outputs: 0
12849 05:57:36.940200 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12850 05:57:36.947389 <14>[ 27.820264] [IGT] kms_vblank: executing
12851 05:57:36.953671 IGT-Version: 1.2<14>[ 27.825004] [IGT] kms_vblank: exiting, ret=77
12852 05:57:36.957093 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12853 05:57:36.966451 Opened dev<8>[ 27.835269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12854 05:57:36.966615 ice: /dev/dri/card0
12855 05:57:36.966900 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12857 05:57:36.973714 No KMS driver or no outputs, pipes: 8, outputs: 0
12858 05:57:36.976558 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12859 05:57:36.987506 <14>[ 27.861139] [IGT] kms_vblank: executing
12860 05:57:36.994193 IGT-Version: 1.2<14>[ 27.865862] [IGT] kms_vblank: exiting, ret=77
12861 05:57:36.997276 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12862 05:57:37.007555 Opened dev<8>[ 27.876093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12863 05:57:37.007868 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12865 05:57:37.011312 ice: /dev/dri/card0
12866 05:57:37.014286 No KMS driver or no outputs, pipes: 8, outputs: 0
12867 05:57:37.020951 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12868 05:57:37.023852 <14>[ 27.897879] [IGT] kms_vblank: executing
12869 05:57:37.030476 IGT-Version: 1.2<14>[ 27.903241] [IGT] kms_vblank: exiting, ret=77
12870 05:57:37.034088 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12871 05:57:37.044217 Opened dev<8>[ 27.913266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12872 05:57:37.044579 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12874 05:57:37.047481 ice: /dev/dri/card0
12875 05:57:37.050561 No KMS driver or no outputs, pipes: 8, outputs: 0
12876 05:57:37.057361 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12877 05:57:37.060661 <14>[ 27.935200] [IGT] kms_vblank: executing
12878 05:57:37.067468 IGT-Version: 1.2<14>[ 27.939933] [IGT] kms_vblank: exiting, ret=77
12879 05:57:37.070352 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12880 05:57:37.080833 Opened dev<8>[ 27.950068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12881 05:57:37.081157 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12883 05:57:37.084217 ice: /dev/dri/card0
12884 05:57:37.086938 No KMS driver or no outputs, pipes: 8, outputs: 0
12885 05:57:37.094431 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12886 05:57:37.097462 <14>[ 27.971859] [IGT] kms_vblank: executing
12887 05:57:37.104090 IGT-Version: 1.2<14>[ 27.976576] [IGT] kms_vblank: exiting, ret=77
12888 05:57:37.107412 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12889 05:57:37.117070 Opened dev<8>[ 27.986772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12890 05:57:37.117424 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12892 05:57:37.120738 ice: /dev/dri/card0
12893 05:57:37.123731 No KMS driver or no outputs, pipes: 8, outputs: 0
12894 05:57:37.130466 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12895 05:57:37.133908 <14>[ 28.008735] [IGT] kms_vblank: executing
12896 05:57:37.140451 IGT-Version: 1.2<14>[ 28.013946] [IGT] kms_vblank: exiting, ret=77
12897 05:57:37.147159 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12898 05:57:37.156788 Opened dev<8>[ 28.024086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12899 05:57:37.156964 ice: /dev/dri/card0
12900 05:57:37.157256 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12902 05:57:37.160082 No KMS driver or no outputs, pipes: 8, outputs: 0
12903 05:57:37.166919 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12904 05:57:37.173537 <14>[ 28.045856] [IGT] kms_vblank: executing
12905 05:57:37.176999 IGT-Version: 1.2<14>[ 28.051042] [IGT] kms_vblank: exiting, ret=77
12906 05:57:37.183595 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12907 05:57:37.190410 Opened dev<8>[ 28.061180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12908 05:57:37.190731 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12910 05:57:37.193283 ice: /dev/dri/card0
12911 05:57:37.196444 No KMS driver or no outputs, pipes: 8, outputs: 0
12912 05:57:37.203643 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12913 05:57:37.206425 <14>[ 28.081873] [IGT] kms_vblank: executing
12914 05:57:37.213683 IGT-Version: 1.2<14>[ 28.086700] [IGT] kms_vblank: exiting, ret=77
12915 05:57:37.220259 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12916 05:57:37.226987 Opened dev<8>[ 28.096868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12917 05:57:37.227329 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12919 05:57:37.229927 ice: /dev/dri/card0
12920 05:57:37.233422 No KMS driver or no outputs, pipes: 8, outputs: 0
12921 05:57:37.236569 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12922 05:57:37.243673 <14>[ 28.117386] [IGT] kms_vblank: executing
12923 05:57:37.250407 IGT-Version: 1.2<14>[ 28.122173] [IGT] kms_vblank: exiting, ret=77
12924 05:57:37.253903 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12925 05:57:37.263524 Opened dev<8>[ 28.132522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12926 05:57:37.263661 ice: /dev/dri/card0
12927 05:57:37.263909 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12929 05:57:37.270721 No KMS driver or no outputs, pipes: 8, outputs: 0
12930 05:57:37.273414 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12931 05:57:37.280407 <14>[ 28.154008] [IGT] kms_vblank: executing
12932 05:57:37.287469 IGT-Version: 1.2<14>[ 28.158819] [IGT] kms_vblank: exiting, ret=77
12933 05:57:37.290283 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12934 05:57:37.300087 Opened dev<8>[ 28.169173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12935 05:57:37.300230 ice: /dev/dri/card0
12936 05:57:37.300530 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12938 05:57:37.307175 No KMS driver or no outputs, pipes: 8, outputs: 0
12939 05:57:37.310232 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12940 05:57:37.313673 <14>[ 28.189283] [IGT] kms_vblank: executing
12941 05:57:37.320176 IGT-Version: 1.2<14>[ 28.194018] [IGT] kms_vblank: exiting, ret=77
12942 05:57:37.326531 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12943 05:57:37.333864 Opened dev<8>[ 28.204385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12944 05:57:37.334170 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12946 05:57:37.336706 ice: /dev/dri/card0
12947 05:57:37.339721 No KMS driver or no outputs, pipes: 8, outputs: 0
12948 05:57:37.346305 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12949 05:57:37.349996 <14>[ 28.225300] [IGT] kms_vblank: executing
12950 05:57:37.356779 IGT-Version: 1.2<14>[ 28.230043] [IGT] kms_vblank: exiting, ret=77
12951 05:57:37.363088 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12952 05:57:37.370225 Opened dev<8>[ 28.240434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12953 05:57:37.370530 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12955 05:57:37.373134 ice: /dev/dri/card0
12956 05:57:37.376794 No KMS driver or no outputs, pipes: 8, outputs: 0
12957 05:57:37.379653 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12958 05:57:37.388223 <14>[ 28.261483] [IGT] kms_vblank: executing
12959 05:57:37.394771 IGT-Version: 1.2<14>[ 28.266259] [IGT] kms_vblank: exiting, ret=77
12960 05:57:37.398179 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12961 05:57:37.407834 Opened device: /dev/dri/ca<8>[ 28.277835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12962 05:57:37.407996 rd0
12963 05:57:37.408293 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12965 05:57:37.414333 No KMS driver or no outputs, pipes: 8, outputs: 0
12966 05:57:37.417964 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12967 05:57:37.425748 <14>[ 28.299352] [IGT] kms_vblank: executing
12968 05:57:37.432826 IGT-Version: 1.2<14>[ 28.304074] [IGT] kms_vblank: exiting, ret=77
12969 05:57:37.436138 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12970 05:57:37.446126 Opened dev<8>[ 28.314674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12971 05:57:37.446265 ice: /dev/dri/card0
12972 05:57:37.446539 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12974 05:57:37.452726 No KMS driver or no outputs, pipes: 8, outputs: 0
12975 05:57:37.455487 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
12976 05:57:37.462007 <14>[ 28.335802] [IGT] kms_vblank: executing
12977 05:57:37.468918 IGT-Version: 1.2<14>[ 28.340534] [IGT] kms_vblank: exiting, ret=77
12978 05:57:37.472592 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12979 05:57:37.482351 Opened dev<8>[ 28.351003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
12980 05:57:37.482502 ice: /dev/dri/card0
12981 05:57:37.482787 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
12983 05:57:37.489235 No KMS driver or no outputs, pipes: 8, outputs: 0
12984 05:57:37.492037 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
12985 05:57:37.499689 <14>[ 28.372812] [IGT] kms_vblank: executing
12986 05:57:37.505635 IGT-Version: 1.2<14>[ 28.377530] [IGT] kms_vblank: exiting, ret=77
12987 05:57:37.509219 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12988 05:57:37.515532 Opened dev<8>[ 28.387705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
12989 05:57:37.515858 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
12991 05:57:37.519116 ice: /dev/dri/card0
12992 05:57:37.522754 No KMS driver or no outputs, pipes: 8, outputs: 0
12993 05:57:37.529513 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
12994 05:57:37.532501 <14>[ 28.408284] [IGT] kms_vblank: executing
12995 05:57:37.539402 IGT-Version: 1.2<14>[ 28.413035] [IGT] kms_vblank: exiting, ret=77
12996 05:57:37.545912 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
12997 05:57:37.553014 Opened dev<8>[ 28.423268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
12998 05:57:37.553349 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
13000 05:57:37.555918 ice: /dev/dri/card0
13001 05:57:37.559583 No KMS driver or no outputs, pipes: 8, outputs: 0
13002 05:57:37.565581 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
13003 05:57:37.569217 <14>[ 28.444157] [IGT] kms_vblank: executing
13004 05:57:37.575762 IGT-Version: 1.2<14>[ 28.448886] [IGT] kms_vblank: exiting, ret=77
13005 05:57:37.578982 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13006 05:57:37.589302 Opened dev<8>[ 28.459121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
13007 05:57:37.589634 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
13009 05:57:37.592330 ice: /dev/dri/card0
13010 05:57:37.595309 No KMS driver or no outputs, pipes: 8, outputs: 0
13011 05:57:37.598903 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
13012 05:57:37.606256 <14>[ 28.479825] [IGT] kms_vblank: executing
13013 05:57:37.613185 IGT-Version: 1.2<14>[ 28.484535] [IGT] kms_vblank: exiting, ret=77
13014 05:57:37.616222 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13015 05:57:37.626119 Opened dev<8>[ 28.494950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
13016 05:57:37.626252 ice: /dev/dri/card0
13017 05:57:37.626506 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
13019 05:57:37.632780 No KMS driver or no outputs, pipes: 8, outputs: 0
13020 05:57:37.635849 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
13021 05:57:37.642809 <14>[ 28.515754] [IGT] kms_vblank: executing
13022 05:57:37.649414 IGT-Version: 1.2<14>[ 28.520570] [IGT] kms_vblank: exiting, ret=77
13023 05:57:37.652423 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13024 05:57:37.659436 Opened dev<8>[ 28.531032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
13025 05:57:37.659811 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
13027 05:57:37.662958 ice: /dev/dri/card0
13028 05:57:37.665822 No KMS driver or no outputs, pipes: 8, outputs: 0
13029 05:57:37.672982 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
13030 05:57:37.675837 <14>[ 28.551412] [IGT] kms_vblank: executing
13031 05:57:37.682439 IGT-Version: 1.2<14>[ 28.556260] [IGT] kms_vblank: exiting, ret=77
13032 05:57:37.688855 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13033 05:57:37.695693 Opened dev<8>[ 28.566730] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
13034 05:57:37.696017 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
13036 05:57:37.699278 ice: /dev/dri/card0
13037 05:57:37.702888 No KMS driver or no outputs, pipes: 8, outputs: 0
13038 05:57:37.708924 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
13039 05:57:37.712555 <14>[ 28.587466] [IGT] kms_vblank: executing
13040 05:57:37.718835 IGT-Version: 1.2<14>[ 28.592263] [IGT] kms_vblank: exiting, ret=77
13041 05:57:37.725437 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13042 05:57:37.732567 Opened dev<8>[ 28.602645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
13043 05:57:37.732896 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
13045 05:57:37.735921 ice: /dev/dri/card0
13046 05:57:37.739102 No KMS driver or no outputs, pipes: 8, outputs: 0
13047 05:57:37.745266 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
13048 05:57:37.748458 <14>[ 28.623579] [IGT] kms_vblank: executing
13049 05:57:37.755524 IGT-Version: 1.2<14>[ 28.628301] [IGT] kms_vblank: exiting, ret=77
13050 05:57:37.758418 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13051 05:57:37.768686 Opened dev<8>[ 28.638907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
13052 05:57:37.769047 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
13054 05:57:37.772033 ice: /dev/dri/card0
13055 05:57:37.775366 No KMS driver or no outputs, pipes: 8, outputs: 0
13056 05:57:37.782074 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
13057 05:57:37.785260 <14>[ 28.659947] [IGT] kms_vblank: executing
13058 05:57:37.791699 IGT-Version: 1.2<14>[ 28.664744] [IGT] kms_vblank: exiting, ret=77
13059 05:57:37.795332 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13060 05:57:37.804968 Opened dev<8>[ 28.675117] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
13061 05:57:37.805288 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
13063 05:57:37.807960 ice: /dev/dri/card0
13064 05:57:37.811390 No KMS driver or no outputs, pipes: 8, outputs: 0
13065 05:57:37.817834 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
13066 05:57:37.821402 <14>[ 28.696310] [IGT] kms_vblank: executing
13067 05:57:37.827960 IGT-Version: 1.2<14>[ 28.701063] [IGT] kms_vblank: exiting, ret=77
13068 05:57:37.831412 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13069 05:57:37.841689 Opened dev<8>[ 28.711215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
13070 05:57:37.842031 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
13072 05:57:37.844739 ice: /dev/dri/card0
13073 05:57:37.847879 No KMS driver or no outputs, pipes: 8, outputs: 0
13074 05:57:37.854837 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
13075 05:57:37.857967 <14>[ 28.733037] [IGT] kms_vblank: executing
13076 05:57:37.864874 IGT-Version: 1.2<14>[ 28.737755] [IGT] kms_vblank: exiting, ret=77
13077 05:57:37.867972 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13078 05:57:37.878335 Opened dev<8>[ 28.747867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
13079 05:57:37.878667 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
13081 05:57:37.881669 ice: /dev/dri/card0
13082 05:57:37.884498 No KMS driver or no outputs, pipes: 8, outputs: 0
13083 05:57:37.891306 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13084 05:57:37.894762 <14>[ 28.769211] [IGT] kms_vblank: executing
13085 05:57:37.901773 IGT-Version: 1.2<14>[ 28.774415] [IGT] kms_vblank: exiting, ret=77
13086 05:57:37.904643 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13087 05:57:37.914944 Opened dev<8>[ 28.784594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13088 05:57:37.915261 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13090 05:57:37.917745 ice: /dev/dri/card0
13091 05:57:37.921251 No KMS driver or no outputs, pipes: 8, outputs: 0
13092 05:57:37.927707 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13093 05:57:37.931224 <14>[ 28.806513] [IGT] kms_vblank: executing
13094 05:57:37.937895 IGT-Version: 1.2<14>[ 28.811642] [IGT] kms_vblank: exiting, ret=77
13095 05:57:37.944536 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13096 05:57:37.954368 Opened dev<8>[ 28.821715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13097 05:57:37.954512 ice: /dev/dri/card0
13098 05:57:37.954789 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13100 05:57:37.960811 No KMS driver or no outputs, pipes: 8, outputs: 0
13101 05:57:37.965083 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13102 05:57:37.967894 <14>[ 28.843415] [IGT] kms_vblank: executing
13103 05:57:37.974240 IGT-Version: 1.2<14>[ 28.848156] [IGT] kms_vblank: exiting, ret=77
13104 05:57:37.980777 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13105 05:57:37.990600 Opened dev<8>[ 28.858368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13106 05:57:37.990735 ice: /dev/dri/card0
13107 05:57:37.990981 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13109 05:57:37.997044 No KMS driver or no outputs, pipes: 8, outputs: 0
13110 05:57:38.000801 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13111 05:57:38.007188 <14>[ 28.880092] [IGT] kms_vblank: executing
13112 05:57:38.010641 IGT-Version: 1.2<14>[ 28.884859] [IGT] kms_vblank: exiting, ret=77
13113 05:57:38.017469 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13114 05:57:38.026767 Opened dev<8>[ 28.895034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13115 05:57:38.026898 ice: /dev/dri/card0
13116 05:57:38.027171 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13118 05:57:38.033924 No KMS driver or no outputs, pipes: 8, outputs: 0
13119 05:57:38.040193 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13120 05:57:38.043572 <14>[ 28.916971] [IGT] kms_vblank: executing
13121 05:57:38.050295 IGT-Version: 1.2<14>[ 28.922101] [IGT] kms_vblank: exiting, ret=77
13122 05:57:38.053724 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13123 05:57:38.063571 Opened dev<8>[ 28.932368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13124 05:57:38.063888 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13126 05:57:38.066475 ice: /dev/dri/card0
13127 05:57:38.069996 No KMS driver or no outputs, pipes: 8, outputs: 0
13128 05:57:38.076511 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13129 05:57:38.080029 <14>[ 28.954367] [IGT] kms_vblank: executing
13130 05:57:38.086381 IGT-Version: 1.2<14>[ 28.959175] [IGT] kms_vblank: exiting, ret=77
13131 05:57:38.089914 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13132 05:57:38.099594 Opened dev<8>[ 28.969308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13133 05:57:38.099948 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13135 05:57:38.103215 ice: /dev/dri/card0
13136 05:57:38.106010 No KMS driver or no outputs, pipes: 8, outputs: 0
13137 05:57:38.109550 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13138 05:57:38.116194 <14>[ 28.990085] [IGT] kms_vblank: executing
13139 05:57:38.122777 IGT-Version: 1.2<14>[ 28.994857] [IGT] kms_vblank: exiting, ret=77
13140 05:57:38.126564 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13141 05:57:38.136418 Opened dev<8>[ 29.004986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13142 05:57:38.136562 ice: /dev/dri/card0
13143 05:57:38.136832 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13145 05:57:38.139383 No KMS driver or no outputs, pipes: 8, outputs: 0
13146 05:57:38.146472 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13147 05:57:38.149839 <14>[ 29.025578] [IGT] kms_vblank: executing
13148 05:57:38.156192 IGT-Version: 1.2<14>[ 29.030385] [IGT] kms_vblank: exiting, ret=77
13149 05:57:38.162933 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13150 05:57:38.169730 Opened dev<8>[ 29.040537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13151 05:57:38.170052 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13153 05:57:38.173188 ice: /dev/dri/card0
13154 05:57:38.175994 No KMS driver or no outputs, pipes: 8, outputs: 0
13155 05:57:38.183270 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13156 05:57:38.186097 <14>[ 29.061798] [IGT] kms_vblank: executing
13157 05:57:38.193090 IGT-Version: 1.2<14>[ 29.066676] [IGT] kms_vblank: exiting, ret=77
13158 05:57:38.199682 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13159 05:57:38.205859 Opened dev<8>[ 29.076754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13160 05:57:38.206163 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13162 05:57:38.209234 ice: /dev/dri/card0
13163 05:57:38.212759 No KMS driver or no outputs, pipes: 8, outputs: 0
13164 05:57:38.218994 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13165 05:57:38.222533 <14>[ 29.097270] [IGT] kms_vblank: executing
13166 05:57:38.229015 IGT-Version: 1.2<14>[ 29.102002] [IGT] kms_vblank: exiting, ret=77
13167 05:57:38.232530 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13168 05:57:38.242646 Opened dev<8>[ 29.112240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13169 05:57:38.242992 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13171 05:57:38.245914 ice: /dev/dri/card0
13172 05:57:38.249297 No KMS driver or no outputs, pipes: 8, outputs: 0
13173 05:57:38.252435 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13174 05:57:38.260622 <14>[ 29.134085] [IGT] kms_vblank: executing
13175 05:57:38.267160 IGT-Version: 1.2<14>[ 29.138825] [IGT] kms_vblank: exiting, ret=77
13176 05:57:38.270421 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13177 05:57:38.277345 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13179 05:57:38.280834 Opened dev<8>[ 29.149040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13180 05:57:38.280932 ice: /dev/dri/card0
13181 05:57:38.283629 No KMS driver or no outputs, pipes: 8, outputs: 0
13182 05:57:38.290380 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13183 05:57:38.293428 <14>[ 29.169456] [IGT] kms_vblank: executing
13184 05:57:38.299951 IGT-Version: 1.2<14>[ 29.174335] [IGT] kms_vblank: exiting, ret=77
13185 05:57:38.307120 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13186 05:57:38.313283 Opened dev<8>[ 29.184389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13187 05:57:38.313582 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13189 05:57:38.316642 ice: /dev/dri/card0
13190 05:57:38.320002 No KMS driver or no outputs, pipes: 8, outputs: 0
13191 05:57:38.326231 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13192 05:57:38.329846 <14>[ 29.205528] [IGT] kms_vblank: executing
13193 05:57:38.336459 IGT-Version: 1.2<14>[ 29.210347] [IGT] kms_vblank: exiting, ret=77
13194 05:57:38.343125 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13195 05:57:38.349383 Opened dev<8>[ 29.220446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13196 05:57:38.349681 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13198 05:57:38.353162 ice: /dev/dri/card0
13199 05:57:38.356524 No KMS driver or no outputs, pipes: 8, outputs: 0
13200 05:57:38.362946 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13201 05:57:38.366244 <14>[ 29.241252] [IGT] kms_vblank: executing
13202 05:57:38.372786 IGT-Version: 1.2<14>[ 29.246073] [IGT] kms_vblank: exiting, ret=77
13203 05:57:38.376126 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13204 05:57:38.386189 Opened dev<8>[ 29.256236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13205 05:57:38.386505 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13207 05:57:38.389617 ice: /dev/dri/card0
13208 05:57:38.393284 No KMS driver or no outputs, pipes: 8, outputs: 0
13209 05:57:38.399224 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13210 05:57:38.402990 <14>[ 29.277661] [IGT] kms_vblank: executing
13211 05:57:38.409413 IGT-Version: 1.2<14>[ 29.282474] [IGT] kms_vblank: exiting, ret=77
13212 05:57:38.413218 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13213 05:57:38.423013 Opened dev<8>[ 29.292669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13214 05:57:38.423175 ice: /dev/dri/card0
13215 05:57:38.423428 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13217 05:57:38.429536 No KMS driver or no outputs, pipes: 8, outputs: 0
13218 05:57:38.432485 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13219 05:57:38.440516 <14>[ 29.313951] [IGT] kms_vblank: executing
13220 05:57:38.447215 IGT-Version: 1.2<14>[ 29.318750] [IGT] kms_vblank: exiting, ret=77
13221 05:57:38.450083 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13222 05:57:38.460314 Opened dev<8>[ 29.328880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13223 05:57:38.460455 ice: /dev/dri/card0
13224 05:57:38.460706 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13226 05:57:38.467044 No KMS driver or no outputs, pipes: 8, outputs: 0
13227 05:57:38.470505 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13228 05:57:38.476963 <14>[ 29.349910] [IGT] kms_vblank: executing
13229 05:57:38.480358 IGT-Version: 1.2<14>[ 29.354752] [IGT] kms_vblank: exiting, ret=77
13230 05:57:38.486647 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13231 05:57:38.493000 Opened dev<8>[ 29.364775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13232 05:57:38.493301 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13234 05:57:38.496792 ice: /dev/dri/card0
13235 05:57:38.499861 No KMS driver or no outputs, pipes: 8, outputs: 0
13236 05:57:38.506471 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13237 05:57:38.509643 <14>[ 29.385665] [IGT] kms_vblank: executing
13238 05:57:38.516502 IGT-Version: 1.2<14>[ 29.390532] [IGT] kms_vblank: exiting, ret=77
13239 05:57:38.523450 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13240 05:57:38.529980 Opened dev<8>[ 29.400623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13241 05:57:38.530291 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13243 05:57:38.532758 ice: /dev/dri/card0
13244 05:57:38.536263 No KMS driver or no outputs, pipes: 8, outputs: 0
13245 05:57:38.542933 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13246 05:57:38.546674 <14>[ 29.421500] [IGT] kms_vblank: executing
13247 05:57:38.552712 IGT-Version: 1.2<14>[ 29.426372] [IGT] kms_vblank: exiting, ret=77
13248 05:57:38.559830 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13249 05:57:38.566513 Opened dev<8>[ 29.436550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13250 05:57:38.566854 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13252 05:57:38.569466 ice: /dev/dri/card0
13253 05:57:38.573133 No KMS driver or no outputs, pipes: 8, outputs: 0
13254 05:57:38.575944 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13255 05:57:38.583637 <14>[ 29.457510] [IGT] kms_vblank: executing
13256 05:57:38.590287 IGT-Version: 1.2<14>[ 29.462459] [IGT] kms_vblank: exiting, ret=77
13257 05:57:38.593972 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13258 05:57:38.604019 Opened dev<8>[ 29.472555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13259 05:57:38.604176 ice: /dev/dri/card0
13260 05:57:38.604454 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13262 05:57:38.610348 No KMS driver or no outputs, pipes: 8, outputs: 0
13263 05:57:38.613845 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13264 05:57:38.620408 <14>[ 29.493920] [IGT] kms_vblank: executing
13265 05:57:38.626985 IGT-Version: 1.2<14>[ 29.498829] [IGT] kms_vblank: exiting, ret=77
13266 05:57:38.630556 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13267 05:57:38.639837 Opened dev<8>[ 29.508913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13268 05:57:38.639975 ice: /dev/dri/card0
13269 05:57:38.640224 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13271 05:57:38.646833 No KMS driver or no outputs, pipes: 8, outputs: 0
13272 05:57:38.649964 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13273 05:57:38.653763 <14>[ 29.529618] [IGT] kms_vblank: executing
13274 05:57:38.660167 IGT-Version: 1.2<14>[ 29.534450] [IGT] kms_vblank: exiting, ret=77
13275 05:57:38.666928 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13276 05:57:38.673786 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13278 05:57:38.676434 Opened dev<8>[ 29.544748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13279 05:57:38.676553 ice: /dev/dri/card0
13280 05:57:38.680197 No KMS driver or no outputs, pipes: 8, outputs: 0
13281 05:57:38.686889 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13282 05:57:38.689839 <14>[ 29.565833] [IGT] kms_vblank: executing
13283 05:57:38.696552 IGT-Version: 1.2<14>[ 29.570688] [IGT] kms_vblank: exiting, ret=77
13284 05:57:38.703837 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13285 05:57:38.710391 Opened dev<8>[ 29.581018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13286 05:57:38.710698 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13288 05:57:38.713015 ice: /dev/dri/card0
13289 05:57:38.716678 No KMS driver or no outputs, pipes: 8, outputs: 0
13290 05:57:38.723325 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13291 05:57:38.726761 <14>[ 29.602408] [IGT] kms_vblank: executing
13292 05:57:38.733357 IGT-Version: 1.2<14>[ 29.607148] [IGT] kms_vblank: exiting, ret=77
13293 05:57:38.740150 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13294 05:57:38.749636 Opened dev<8>[ 29.617635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13295 05:57:38.749766 ice: /dev/dri/card0
13296 05:57:38.750015 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13298 05:57:38.753163 No KMS driver or no outputs, pipes: 8, outputs: 0
13299 05:57:38.759510 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13300 05:57:38.763227 <14>[ 29.639247] [IGT] kms_vblank: executing
13301 05:57:38.769924 IGT-Version: 1.2<14>[ 29.643997] [IGT] kms_vblank: exiting, ret=77
13302 05:57:38.776867 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13303 05:57:38.786422 Opened dev<8>[ 29.654637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13304 05:57:38.786608 ice: /dev/dri/card0
13305 05:57:38.786898 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13307 05:57:38.793187 No KMS driver or no outputs, pipes: 8, outputs: 0
13308 05:57:38.796499 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13309 05:57:38.803087 <14>[ 29.676013] [IGT] kms_vblank: executing
13310 05:57:38.806691 IGT-Version: 1.2<14>[ 29.680774] [IGT] kms_vblank: exiting, ret=77
13311 05:57:38.813314 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13312 05:57:38.823106 Opened dev<8>[ 29.691165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13313 05:57:38.823236 ice: /dev/dri/card0
13314 05:57:38.823484 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13316 05:57:38.829778 No KMS driver or no outputs, pipes: 8, outputs: 0
13317 05:57:38.833121 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13318 05:57:38.839444 <14>[ 29.712883] [IGT] kms_vblank: executing
13319 05:57:38.846460 IGT-Version: 1.2<14>[ 29.718046] [IGT] kms_vblank: exiting, ret=77
13320 05:57:38.849422 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13321 05:57:38.859636 Opened dev<8>[ 29.728603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13322 05:57:38.859778 ice: /dev/dri/card0
13323 05:57:38.860022 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13325 05:57:38.866074 No KMS driver or no outputs, pipes: 8, outputs: 0
13326 05:57:38.869744 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13327 05:57:38.876472 <14>[ 29.750118] [IGT] kms_vblank: executing
13328 05:57:38.882995 IGT-Version: 1.2<14>[ 29.754841] [IGT] kms_vblank: exiting, ret=77
13329 05:57:38.886222 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13330 05:57:38.896180 Opened dev<8>[ 29.765031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13331 05:57:38.896550 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13333 05:57:38.899712 ice: /dev/dri/card0
13334 05:57:38.903065 No KMS driver or no outputs, pipes: 8, outputs: 0
13335 05:57:38.909224 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13336 05:57:38.912406 <14>[ 29.787242] [IGT] kms_vblank: executing
13337 05:57:38.918986 IGT-Version: 1.2<14>[ 29.792006] [IGT] kms_vblank: exiting, ret=77
13338 05:57:38.922281 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13339 05:57:38.932474 Opened dev<8>[ 29.802626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13340 05:57:38.932796 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13342 05:57:38.935662 ice: /dev/dri/card0
13343 05:57:38.938939 No KMS driver or no outputs, pipes: 8, outputs: 0
13344 05:57:38.945643 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13345 05:57:38.949069 <14>[ 29.824526] [IGT] kms_vblank: executing
13346 05:57:38.955156 IGT-Version: 1.2<14>[ 29.829258] [IGT] kms_vblank: exiting, ret=77
13347 05:57:38.962421 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13348 05:57:38.971920 Opened dev<8>[ 29.839473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13349 05:57:38.972062 ice: /dev/dri/card0
13350 05:57:38.972317 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13352 05:57:38.978634 No KMS driver or no outputs, pipes: 8, outputs: 0
13353 05:57:38.981523 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13354 05:57:38.988232 <14>[ 29.861300] [IGT] kms_vblank: executing
13355 05:57:38.991245 IGT-Version: 1.2<14>[ 29.866279] [IGT] kms_vblank: exiting, ret=77
13356 05:57:38.998434 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13357 05:57:39.004968 Opened dev<8>[ 29.876737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13358 05:57:39.005261 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13360 05:57:39.007994 ice: /dev/dri/card0
13361 05:57:39.011202 No KMS driver or no outputs, pipes: 8, outputs: 0
13362 05:57:39.017921 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13363 05:57:39.024592 <14>[ 29.897668] [IGT] kms_vblank: executing
13364 05:57:39.027965 IGT-Version: 1.2<14>[ 29.902540] [IGT] kms_vblank: exiting, ret=77
13365 05:57:39.034193 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13366 05:57:39.041547 Opened dev<8>[ 29.912657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13367 05:57:39.041841 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13369 05:57:39.044662 ice: /dev/dri/card0
13370 05:57:39.047925 No KMS driver or no outputs, pipes: 8, outputs: 0
13371 05:57:39.054295 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13372 05:57:39.057824 <14>[ 29.933117] [IGT] kms_vblank: executing
13373 05:57:39.064391 IGT-Version: 1.2<14>[ 29.937932] [IGT] kms_vblank: exiting, ret=77
13374 05:57:39.070630 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13375 05:57:39.077223 Opened dev<8>[ 29.948253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13376 05:57:39.077517 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13378 05:57:39.080579 ice: /dev/dri/card0
13379 05:57:39.084011 No KMS driver or no outputs, pipes: 8, outputs: 0
13380 05:57:39.090662 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13381 05:57:39.106733 <14>[ 29.980372] [IGT] kms_vblank: executing
13382 05:57:39.113370 IGT-Version: 1.2<14>[ 29.985515] [IGT] kms_vblank: exiting, ret=77
13383 05:57:39.116358 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13384 05:57:39.126556 Opened device: /dev/dri/ca<8>[ 29.996723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13385 05:57:39.126708 rd0
13386 05:57:39.126992 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13388 05:57:39.133110 No KMS driver or no outputs, pipes: 8, outputs: 0
13389 05:57:39.136771 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13390 05:57:39.143946 <14>[ 30.017971] [IGT] kms_vblank: executing
13391 05:57:39.151087 IGT-Version: 1.2<14>[ 30.022770] [IGT] kms_vblank: exiting, ret=77
13392 05:57:39.153985 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13393 05:57:39.164016 Opened dev<8>[ 30.032845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13394 05:57:39.164146 ice: /dev/dri/card0
13395 05:57:39.164425 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13397 05:57:39.171267 No KMS driver or no outputs, pipes: 8, outputs: 0
13398 05:57:39.173962 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13399 05:57:39.180474 <14>[ 30.054074] [IGT] kms_vblank: executing
13400 05:57:39.187394 IGT-Version: 1.2<14>[ 30.058845] [IGT] kms_vblank: exiting, ret=77
13401 05:57:39.190531 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13402 05:57:39.197166 Opened dev<8>[ 30.069015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13403 05:57:39.197475 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13405 05:57:39.200236 ice: /dev/dri/card0
13406 05:57:39.204012 No KMS driver or no outputs, pipes: 8, outputs: 0
13407 05:57:39.210364 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13408 05:57:39.213538 <14>[ 30.089931] [IGT] kms_vblank: executing
13409 05:57:39.220407 IGT-Version: 1.2<14>[ 30.094844] [IGT] kms_vblank: exiting, ret=77
13410 05:57:39.227023 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13411 05:57:39.233478 Opened dev<8>[ 30.104772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13412 05:57:39.233815 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13414 05:57:39.237049 ice: /dev/dri/card0
13415 05:57:39.240748 No KMS driver or no outputs, pipes: 8, outputs: 0
13416 05:57:39.247244 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13417 05:57:39.250573 <14>[ 30.125551] [IGT] kms_vblank: executing
13418 05:57:39.256811 IGT-Version: 1.2<14>[ 30.130352] [IGT] kms_vblank: exiting, ret=77
13419 05:57:39.263890 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13420 05:57:39.270528 Opened dev<8>[ 30.140418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13421 05:57:39.270822 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13423 05:57:39.273385 ice: /dev/dri/card0
13424 05:57:39.276718 No KMS driver or no outputs, pipes: 8, outputs: 0
13425 05:57:39.283206 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13426 05:57:39.286775 <14>[ 30.161534] [IGT] kms_vblank: executing
13427 05:57:39.293397 IGT-Version: 1.2<14>[ 30.166338] [IGT] kms_vblank: exiting, ret=77
13428 05:57:39.296854 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13429 05:57:39.307035 Opened dev<8>[ 30.176532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13430 05:57:39.307345 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13432 05:57:39.309839 ice: /dev/dri/card0
13433 05:57:39.313220 No KMS driver or no outputs, pipes: 8, outputs: 0
13434 05:57:39.319680 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13435 05:57:39.323292 <14>[ 30.197767] [IGT] kms_vblank: executing
13436 05:57:39.330154 IGT-Version: 1.2<14>[ 30.202644] [IGT] kms_vblank: exiting, ret=77
13437 05:57:39.333656 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13438 05:57:39.342854 Opened dev<8>[ 30.212829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13439 05:57:39.342978 ice: /dev/dri/card0
13440 05:57:39.343231 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13442 05:57:39.349605 No KMS driver or no outputs, pipes: 8, outputs: 0
13443 05:57:39.353191 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13444 05:57:39.359813 <14>[ 30.233512] [IGT] kms_vblank: executing
13445 05:57:39.366207 IGT-Version: 1.2<14>[ 30.238284] [IGT] kms_vblank: exiting, ret=77
13446 05:57:39.369936 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13447 05:57:39.379347 Opened dev<8>[ 30.248702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13448 05:57:39.379475 ice: /dev/dri/card0
13449 05:57:39.379724 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13451 05:57:39.386205 No KMS driver or no outputs, pipes: 8, outputs: 0
13452 05:57:39.389605 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13453 05:57:39.393141 <14>[ 30.269128] [IGT] kms_vblank: executing
13454 05:57:39.399807 IGT-Version: 1.2<14>[ 30.273823] [IGT] kms_vblank: exiting, ret=77
13455 05:57:39.406443 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13456 05:57:39.412839 Opened dev<8>[ 30.284403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13457 05:57:39.413134 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13459 05:57:39.416297 ice: /dev/dri/card0
13460 05:57:39.419728 No KMS driver or no outputs, pipes: 8, outputs: 0
13461 05:57:39.426315 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13462 05:57:39.429274 <14>[ 30.305232] [IGT] kms_vblank: executing
13463 05:57:39.435972 IGT-Version: 1.2<14>[ 30.309981] [IGT] kms_vblank: exiting, ret=77
13464 05:57:39.442560 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13465 05:57:39.449386 Opened dev<8>[ 30.320416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13466 05:57:39.449698 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13468 05:57:39.452543 ice: /dev/dri/card0
13469 05:57:39.456018 No KMS driver or no outputs, pipes: 8, outputs: 0
13470 05:57:39.462390 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13471 05:57:39.466138 <14>[ 30.341185] [IGT] kms_vblank: executing
13472 05:57:39.472377 IGT-Version: 1.2<14>[ 30.345885] [IGT] kms_vblank: exiting, ret=77
13473 05:57:39.476119 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13474 05:57:39.486329 Opened dev<8>[ 30.356248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13475 05:57:39.486661 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13477 05:57:39.489149 ice: /dev/dri/card0
13478 05:57:39.492416 No KMS driver or no outputs, pipes: 8, outputs: 0
13479 05:57:39.495932 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13480 05:57:39.503230 <14>[ 30.376999] [IGT] kms_vblank: executing
13481 05:57:39.509635 IGT-Version: 1.2<14>[ 30.381739] [IGT] kms_vblank: exiting, ret=77
13482 05:57:39.513306 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13483 05:57:39.523526 Opened dev<8>[ 30.392060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13484 05:57:39.523653 ice: /dev/dri/card0
13485 05:57:39.523899 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13487 05:57:39.529492 No KMS driver or no outputs, pipes: 8, outputs: 0
13488 05:57:39.532877 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13489 05:57:39.540278 <14>[ 30.413937] [IGT] kms_vblank: executing
13490 05:57:39.546881 IGT-Version: 1.2<14>[ 30.418832] [IGT] kms_vblank: exiting, ret=77
13491 05:57:39.549865 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13492 05:57:39.560168 Opened dev<8>[ 30.428884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13493 05:57:39.560343 ice: /dev/dri/card0
13494 05:57:39.560596 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13496 05:57:39.566693 No KMS driver or no outputs, pipes: 8, outputs: 0
13497 05:57:39.570318 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13498 05:57:39.579563 <14>[ 30.453235] [IGT] kms_vblank: executing
13499 05:57:39.586007 IGT-Version: 1.2<14>[ 30.458042] [IGT] kms_vblank: exiting, ret=77
13500 05:57:39.589291 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13501 05:57:39.599359 Opened dev<8>[ 30.468384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13502 05:57:39.599490 ice: /dev/dri/card0
13503 05:57:39.599739 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13505 05:57:39.605897 No KMS driver or no outputs, pipes: 8, outputs: 0
13506 05:57:39.608928 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13507 05:57:39.616254 <14>[ 30.489881] [IGT] kms_vblank: executing
13508 05:57:39.622618 IGT-Version: 1.2<14>[ 30.494807] [IGT] kms_vblank: exiting, ret=77
13509 05:57:39.626244 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13510 05:57:39.635816 Opened dev<8>[ 30.504838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13511 05:57:39.635998 ice: /dev/dri/card0
13512 05:57:39.636249 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13514 05:57:39.642732 No KMS driver or no outputs, pipes: 8, outputs: 0
13515 05:57:39.645795 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13516 05:57:39.652712 <14>[ 30.526395] [IGT] kms_vblank: executing
13517 05:57:39.659122 IGT-Version: 1.2<14>[ 30.531116] [IGT] kms_vblank: exiting, ret=77
13518 05:57:39.662825 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13519 05:57:39.672175 Opened dev<8>[ 30.541471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13520 05:57:39.672502 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13522 05:57:39.675712 ice: /dev/dri/card0
13523 05:57:39.679331 No KMS driver or no outputs, pipes: 8, outputs: 0
13524 05:57:39.685729 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13525 05:57:39.689305 <14>[ 30.563065] [IGT] kms_vblank: executing
13526 05:57:39.695684 IGT-Version: 1.2<14>[ 30.567824] [IGT] kms_vblank: exiting, ret=77
13527 05:57:39.699321 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13528 05:57:39.708580 Opened dev<8>[ 30.578106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13529 05:57:39.708890 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13531 05:57:39.712272 ice: /dev/dri/card0
13532 05:57:39.715212 No KMS driver or no outputs, pipes: 8, outputs: 0
13533 05:57:39.722283 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13534 05:57:39.725695 <14>[ 30.599574] [IGT] kms_vblank: executing
13535 05:57:39.731757 IGT-Version: 1.2<14>[ 30.604409] [IGT] kms_vblank: exiting, ret=77
13536 05:57:39.735188 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13537 05:57:39.745132 Opened dev<8>[ 30.615009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13538 05:57:39.745443 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13540 05:57:39.748241 ice: /dev/dri/card0
13541 05:57:39.751936 No KMS driver or no outputs, pipes: 8, outputs: 0
13542 05:57:39.758728 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13543 05:57:39.761751 <14>[ 30.636737] [IGT] kms_vblank: executing
13544 05:57:39.768760 IGT-Version: 1.2<14>[ 30.641607] [IGT] kms_vblank: exiting, ret=77
13545 05:57:39.771387 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13546 05:57:39.782072 Opened dev<8>[ 30.651785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13547 05:57:39.782413 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13549 05:57:39.784815 ice: /dev/dri/card0
13550 05:57:39.788508 No KMS driver or no outputs, pipes: 8, outputs: 0
13551 05:57:39.795002 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13552 05:57:39.798510 <14>[ 30.673200] [IGT] kms_vblank: executing
13553 05:57:39.804988 IGT-Version: 1.2<14>[ 30.677939] [IGT] kms_vblank: exiting, ret=77
13554 05:57:39.808509 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13555 05:57:39.818639 Opened dev<8>[ 30.688190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13556 05:57:39.819005 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13558 05:57:39.821405 ice: /dev/dri/card0
13559 05:57:39.825136 No KMS driver or no outputs, pipes: 8, outputs: 0
13560 05:57:39.831703 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13561 05:57:39.835072 <14>[ 30.709775] [IGT] kms_vblank: executing
13562 05:57:39.841678 IGT-Version: 1.2<14>[ 30.714631] [IGT] kms_vblank: exiting, ret=77
13563 05:57:39.844591 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13564 05:57:39.854756 Opened dev<8>[ 30.724786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13565 05:57:39.855080 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13567 05:57:39.857716 ice: /dev/dri/card0
13568 05:57:39.861312 No KMS driver or no outputs, pipes: 8, outputs: 0
13569 05:57:39.867669 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13570 05:57:39.870955 <14>[ 30.746822] [IGT] kms_vblank: executing
13571 05:57:39.877570 IGT-Version: 1.2<14>[ 30.751691] [IGT] kms_vblank: exiting, ret=77
13572 05:57:39.884386 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13573 05:57:39.891564 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13575 05:57:39.894356 Opened dev<8>[ 30.762051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13576 05:57:39.894449 ice: /dev/dri/card0
13577 05:57:39.897803 No KMS driver or no outputs, pipes: 8, outputs: 0
13578 05:57:39.904227 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13579 05:57:39.907410 <14>[ 30.783886] [IGT] kms_vblank: executing
13580 05:57:39.914385 IGT-Version: 1.2<14>[ 30.788686] [IGT] kms_vblank: exiting, ret=77
13581 05:57:39.921137 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13582 05:57:39.927785 Opened dev<8>[ 30.798977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13583 05:57:39.928111 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13585 05:57:39.931364 ice: /dev/dri/card0
13586 05:57:39.934391 No KMS driver or no outputs, pipes: 8, outputs: 0
13587 05:57:39.941345 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13588 05:57:39.944694 <14>[ 30.819769] [IGT] kms_vblank: executing
13589 05:57:39.951193 IGT-Version: 1.2<14>[ 30.824506] [IGT] kms_vblank: exiting, ret=77
13590 05:57:39.957528 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13591 05:57:39.963858 Opened dev<8>[ 30.834976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13592 05:57:39.964159 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13594 05:57:39.967462 ice: /dev/dri/card0
13595 05:57:39.970787 No KMS driver or no outputs, pipes: 8, outputs: 0
13596 05:57:39.974470 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13597 05:57:39.981444 <14>[ 30.855597] [IGT] kms_vblank: executing
13598 05:57:39.988072 IGT-Version: 1.2<14>[ 30.860350] [IGT] kms_vblank: exiting, ret=77
13599 05:57:39.991681 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13600 05:57:40.001848 Opened dev<8>[ 30.870784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13601 05:57:40.002023 ice: /dev/dri/card0
13602 05:57:40.002302 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13604 05:57:40.007895 No KMS driver or no outputs, pipes: 8, outputs: 0
13605 05:57:40.011297 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13606 05:57:40.018201 <14>[ 30.891422] [IGT] kms_vblank: executing
13607 05:57:40.024701 IGT-Version: 1.2<14>[ 30.896278] [IGT] kms_vblank: exiting, ret=77
13608 05:57:40.027834 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13609 05:57:40.034744 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13611 05:57:40.037370 Opened dev<8>[ 30.906769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13612 05:57:40.037478 ice: /dev/dri/card0
13613 05:57:40.040736 No KMS driver or no outputs, pipes: 8, outputs: 0
13614 05:57:40.047487 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13615 05:57:40.054116 <14>[ 30.927329] [IGT] kms_vblank: executing
13616 05:57:40.057568 IGT-Version: 1.2<14>[ 30.932067] [IGT] kms_vblank: exiting, ret=77
13617 05:57:40.063909 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13618 05:57:40.070578 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13620 05:57:40.074096 Opened dev<8>[ 30.942275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13621 05:57:40.074224 ice: /dev/dri/card0
13622 05:57:40.077797 No KMS driver or no outputs, pipes: 8, outputs: 0
13623 05:57:40.084443 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13624 05:57:40.087283 <14>[ 30.963434] [IGT] kms_vblank: executing
13625 05:57:40.093756 IGT-Version: 1.2<14>[ 30.968239] [IGT] kms_vblank: exiting, ret=77
13626 05:57:40.100572 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13627 05:57:40.107172 Opened dev<8>[ 30.978663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13628 05:57:40.107471 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13630 05:57:40.110820 ice: /dev/dri/card0
13631 05:57:40.114257 No KMS driver or no outputs, pipes: 8, outputs: 0
13632 05:57:40.116932 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13633 05:57:40.125020 <14>[ 30.998902] [IGT] kms_vblank: executing
13634 05:57:40.131607 IGT-Version: 1.2<14>[ 31.003649] [IGT] kms_vblank: exiting, ret=77
13635 05:57:40.135094 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13636 05:57:40.145046 Opened dev<8>[ 31.013853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13637 05:57:40.145191 ice: /dev/dri/card0
13638 05:57:40.145440 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13640 05:57:40.151640 No KMS driver or no outputs, pipes: 8, outputs: 0
13641 05:57:40.154942 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13642 05:57:40.161331 <14>[ 31.034762] [IGT] kms_vblank: executing
13643 05:57:40.164748 IGT-Version: 1.2<14>[ 31.039490] [IGT] kms_vblank: exiting, ret=77
13644 05:57:40.171717 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13645 05:57:40.181585 Opened dev<8>[ 31.049656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13646 05:57:40.181720 ice: /dev/dri/card0
13647 05:57:40.181970 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13649 05:57:40.184351 No KMS driver or no outputs, pipes: 8, outputs: 0
13650 05:57:40.191007 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13651 05:57:40.194493 <14>[ 31.070954] [IGT] kms_vblank: executing
13652 05:57:40.201408 IGT-Version: 1.2<14>[ 31.075687] [IGT] kms_vblank: exiting, ret=77
13653 05:57:40.208162 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13654 05:57:40.217766 Opened dev<8>[ 31.085868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13655 05:57:40.217903 ice: /dev/dri/card0
13656 05:57:40.218162 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13658 05:57:40.221205 No KMS driver or no outputs, pipes: 8, outputs: 0
13659 05:57:40.227976 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13660 05:57:40.231012 <14>[ 31.107519] [IGT] kms_vblank: executing
13661 05:57:40.238361 IGT-Version: 1.2<14>[ 31.112289] [IGT] kms_vblank: exiting, ret=77
13662 05:57:40.244887 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13663 05:57:40.251431 Opened dev<8>[ 31.122698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13664 05:57:40.251734 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13666 05:57:40.254493 ice: /dev/dri/card0
13667 05:57:40.258171 No KMS driver or no outputs, pipes: 8, outputs: 0
13668 05:57:40.261013 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13669 05:57:40.269486 <14>[ 31.143277] [IGT] kms_vblank: executing
13670 05:57:40.276115 IGT-Version: 1.2<14>[ 31.148065] [IGT] kms_vblank: exiting, ret=77
13671 05:57:40.279665 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13672 05:57:40.289718 Opened dev<8>[ 31.158379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13673 05:57:40.289845 ice: /dev/dri/card0
13674 05:57:40.290095 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13676 05:57:40.296212 No KMS driver or no outputs, pipes: 8, outputs: 0
13677 05:57:40.299636 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13678 05:57:40.305595 <14>[ 31.179242] [IGT] kms_vblank: executing
13679 05:57:40.309577 IGT-Version: 1.2<14>[ 31.183954] [IGT] kms_vblank: exiting, ret=77
13680 05:57:40.315963 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13681 05:57:40.322328 Opened dev<8>[ 31.194391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13682 05:57:40.322632 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13684 05:57:40.325968 ice: /dev/dri/card0
13685 05:57:40.328824 No KMS driver or no outputs, pipes: 8, outputs: 0
13686 05:57:40.335927 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13687 05:57:40.339196 <14>[ 31.214925] [IGT] kms_vblank: executing
13688 05:57:40.345524 IGT-Version: 1.2<14>[ 31.219673] [IGT] kms_vblank: exiting, ret=77
13689 05:57:40.352743 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13690 05:57:40.358857 Opened dev<8>[ 31.229861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13691 05:57:40.359155 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13693 05:57:40.362505 ice: /dev/dri/card0
13694 05:57:40.365244 No KMS driver or no outputs, pipes: 8, outputs: 0
13695 05:57:40.372215 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13696 05:57:40.375866 <14>[ 31.250967] [IGT] kms_vblank: executing
13697 05:57:40.382548 IGT-Version: 1.2<14>[ 31.255697] [IGT] kms_vblank: exiting, ret=77
13698 05:57:40.389039 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13699 05:57:40.395661 Opened dev<8>[ 31.265798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13700 05:57:40.395961 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13702 05:57:40.398390 ice: /dev/dri/card0
13703 05:57:40.401985 No KMS driver or no outputs, pipes: 8, outputs: 0
13704 05:57:40.405549 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13705 05:57:40.412882 <14>[ 31.286543] [IGT] kms_vblank: executing
13706 05:57:40.419454 IGT-Version: 1.2<14>[ 31.291265] [IGT] kms_vblank: exiting, ret=77
13707 05:57:40.422955 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13708 05:57:40.432418 Opened dev<8>[ 31.301683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13709 05:57:40.432549 ice: /dev/dri/card0
13710 05:57:40.432797 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13712 05:57:40.439719 No KMS driver or no outputs, pipes: 8, outputs: 0
13713 05:57:40.442336 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13714 05:57:40.445699 <14>[ 31.322282] [IGT] kms_vblank: executing
13715 05:57:40.452739 IGT-Version: 1.2<14>[ 31.327096] [IGT] kms_vblank: exiting, ret=77
13716 05:57:40.459338 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13717 05:57:40.465839 Opened dev<8>[ 31.337306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13718 05:57:40.466182 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13720 05:57:40.469589 ice: /dev/dri/card0
13721 05:57:40.472348 No KMS driver or no outputs, pipes: 8, outputs: 0
13722 05:57:40.479225 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13723 05:57:40.482254 <14>[ 31.358560] [IGT] kms_vblank: executing
13724 05:57:40.489515 IGT-Version: 1.2<14>[ 31.363302] [IGT] kms_vblank: exiting, ret=77
13725 05:57:40.495948 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13726 05:57:40.502540 Opened dev<8>[ 31.373535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13727 05:57:40.502868 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13729 05:57:40.505455 ice: /dev/dri/card0
13730 05:57:40.509019 No KMS driver or no outputs, pipes: 8, outputs: 0
13731 05:57:40.515634 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13732 05:57:40.519272 <14>[ 31.394991] [IGT] kms_vblank: executing
13733 05:57:40.526001 IGT-Version: 1.2<14>[ 31.399826] [IGT] kms_vblank: exiting, ret=77
13734 05:57:40.532402 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13735 05:57:40.538669 Opened dev<8>[ 31.410006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13736 05:57:40.538960 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13738 05:57:40.542197 ice: /dev/dri/card0
13739 05:57:40.545272 No KMS driver or no outputs, pipes: 8, outputs: 0
13740 05:57:40.552413 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13741 05:57:40.555249 <14>[ 31.431562] [IGT] kms_vblank: executing
13742 05:57:40.561831 IGT-Version: 1.2<14>[ 31.436296] [IGT] kms_vblank: exiting, ret=77
13743 05:57:40.568501 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13744 05:57:40.578422 Opened dev<8>[ 31.446782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13745 05:57:40.578584 ice: /dev/dri/card0
13746 05:57:40.578869 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13748 05:57:40.585609 No KMS driver or no outputs, pipes: 8, outputs: 0
13749 05:57:40.588429 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13750 05:57:40.594877 <14>[ 31.468257] [IGT] kms_vblank: executing
13751 05:57:40.598460 IGT-Version: 1.2<14>[ 31.473110] [IGT] kms_vblank: exiting, ret=77
13752 05:57:40.605406 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13753 05:57:40.615183 Opened dev<8>[ 31.483210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13754 05:57:40.615343 ice: /dev/dri/card0
13755 05:57:40.615618 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13757 05:57:40.621365 No KMS driver or no outputs, pipes: 8, outputs: 0
13758 05:57:40.624999 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13759 05:57:40.631574 <14>[ 31.505012] [IGT] kms_vblank: executing
13760 05:57:40.635156 IGT-Version: 1.2<14>[ 31.509739] [IGT] kms_vblank: exiting, ret=77
13761 05:57:40.641663 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13762 05:57:40.651562 Opened dev<8>[ 31.519982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13763 05:57:40.651695 ice: /dev/dri/card0
13764 05:57:40.651943 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13766 05:57:40.658123 No KMS driver or no outputs, pipes: 8, outputs: 0
13767 05:57:40.664556 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13768 05:57:40.668257 <14>[ 31.541985] [IGT] kms_vblank: executing
13769 05:57:40.674365 IGT-Version: 1.2<14>[ 31.547026] [IGT] kms_vblank: exiting, ret=77
13770 05:57:40.677893 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13771 05:57:40.687810 Opened dev<8>[ 31.557224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13772 05:57:40.688151 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13774 05:57:40.691352 ice: /dev/dri/card0
13775 05:57:40.694815 No KMS driver or no outputs, pipes: 8, outputs: 0
13776 05:57:40.701076 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13777 05:57:40.704707 <14>[ 31.579008] [IGT] kms_vblank: executing
13778 05:57:40.710929 IGT-Version: 1.2<14>[ 31.583741] [IGT] kms_vblank: exiting, ret=77
13779 05:57:40.714236 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13780 05:57:40.724636 Opened dev<8>[ 31.593906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13781 05:57:40.724950 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13783 05:57:40.727435 ice: /dev/dri/card0
13784 05:57:40.730759 No KMS driver or no outputs, pipes: 8, outputs: 0
13785 05:57:40.737831 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13786 05:57:40.741009 <14>[ 31.615611] [IGT] kms_vblank: executing
13787 05:57:40.747383 IGT-Version: 1.2<14>[ 31.620465] [IGT] kms_vblank: exiting, ret=77
13788 05:57:40.750874 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13789 05:57:40.760615 Opened dev<8>[ 31.630804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13790 05:57:40.760928 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13792 05:57:40.764264 ice: /dev/dri/card0
13793 05:57:40.767926 No KMS driver or no outputs, pipes: 8, outputs: 0
13794 05:57:40.774288 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13795 05:57:40.777740 <14>[ 31.652749] [IGT] kms_vblank: executing
13796 05:57:40.784018 IGT-Version: 1.2<14>[ 31.657664] [IGT] kms_vblank: exiting, ret=77
13797 05:57:40.790521 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13798 05:57:40.797203 Opened dev<8>[ 31.667882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13799 05:57:40.797531 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13801 05:57:40.800752 ice: /dev/dri/card0
13802 05:57:40.804248 No KMS driver or no outputs, pipes: 8, outputs: 0
13803 05:57:40.810750 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13804 05:57:40.814372 <14>[ 31.689490] [IGT] kms_vblank: executing
13805 05:57:40.820921 IGT-Version: 1.2<14>[ 31.694849] [IGT] kms_vblank: exiting, ret=77
13806 05:57:40.827277 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13807 05:57:40.833829 Opened dev<8>[ 31.705190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13808 05:57:40.834134 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13810 05:57:40.837446 ice: /dev/dri/card0
13811 05:57:40.840716 No KMS driver or no outputs, pipes: 8, outputs: 0
13812 05:57:40.847186 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13813 05:57:40.850432 <14>[ 31.725925] [IGT] kms_vblank: executing
13814 05:57:40.856996 IGT-Version: 1.2<14>[ 31.730791] [IGT] kms_vblank: exiting, ret=77
13815 05:57:40.863377 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13816 05:57:40.870127 Opened dev<8>[ 31.740944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13817 05:57:40.870431 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13819 05:57:40.873250 ice: /dev/dri/card0
13820 05:57:40.877163 No KMS driver or no outputs, pipes: 8, outputs: 0
13821 05:57:40.879900 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13822 05:57:40.888090 <14>[ 31.761749] [IGT] kms_vblank: executing
13823 05:57:40.894457 IGT-Version: 1.2<14>[ 31.766661] [IGT] kms_vblank: exiting, ret=77
13824 05:57:40.897473 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13825 05:57:40.907579 Opened dev<8>[ 31.776831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13826 05:57:40.907735 ice: /dev/dri/card0
13827 05:57:40.908017 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13829 05:57:40.914192 No KMS driver or no outputs, pipes: 8, outputs: 0
13830 05:57:40.917965 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13831 05:57:40.920823 <14>[ 31.797395] [IGT] kms_vblank: executing
13832 05:57:40.928062 IGT-Version: 1.2<14>[ 31.802082] [IGT] kms_vblank: exiting, ret=77
13833 05:57:40.934565 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13834 05:57:40.941240 Opened dev<8>[ 31.812471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13835 05:57:40.941560 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13837 05:57:40.944270 ice: /dev/dri/card0
13838 05:57:40.947303 No KMS driver or no outputs, pipes: 8, outputs: 0
13839 05:57:40.954483 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13840 05:57:40.957317 <14>[ 31.832993] [IGT] kms_vblank: executing
13841 05:57:40.964333 IGT-Version: 1.2<14>[ 31.837717] [IGT] kms_vblank: exiting, ret=77
13842 05:57:40.970564 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13843 05:57:40.977521 Opened dev<8>[ 31.848160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13844 05:57:40.977880 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13846 05:57:40.980525 ice: /dev/dri/card0
13847 05:57:40.984009 No KMS driver or no outputs, pipes: 8, outputs: 0
13848 05:57:40.990177 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13849 05:57:40.994070 <14>[ 31.869115] [IGT] kms_vblank: executing
13850 05:57:41.000450 IGT-Version: 1.2<14>[ 31.873825] [IGT] kms_vblank: exiting, ret=77
13851 05:57:41.003952 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13852 05:57:41.013466 Opened dev<8>[ 31.884122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13853 05:57:41.013808 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13855 05:57:41.016959 ice: /dev/dri/card0
13856 05:57:41.020456 No KMS driver or no outputs, pipes: 8, outputs: 0
13857 05:57:41.023794 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13858 05:57:41.031449 <14>[ 31.904922] [IGT] kms_vblank: executing
13859 05:57:41.037311 IGT-Version: 1.2<14>[ 31.909665] [IGT] kms_vblank: exiting, ret=77
13860 05:57:41.040862 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13861 05:57:41.051229 Opened dev<8>[ 31.919876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13862 05:57:41.051376 ice: /dev/dri/card0
13863 05:57:41.051652 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13865 05:57:41.057822 No KMS driver or no outputs, pipes: 8, outputs: 0
13866 05:57:41.060680 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13867 05:57:41.067727 <14>[ 31.940737] [IGT] kms_vblank: executing
13868 05:57:41.070572 IGT-Version: 1.2<14>[ 31.945474] [IGT] kms_vblank: exiting, ret=77
13869 05:57:41.077843 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13870 05:57:41.083883 Opened dev<8>[ 31.955822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13871 05:57:41.084196 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13873 05:57:41.087274 ice: /dev/dri/card0
13874 05:57:41.090689 No KMS driver or no outputs, pipes: 8, outputs: 0
13875 05:57:41.097817 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13876 05:57:41.100737 <14>[ 31.976860] [IGT] kms_vblank: executing
13877 05:57:41.107961 IGT-Version: 1.2<14>[ 31.981585] [IGT] kms_vblank: exiting, ret=77
13878 05:57:41.114349 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13879 05:57:41.120889 Opened dev<8>[ 31.991996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13880 05:57:41.121257 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13882 05:57:41.124189 ice: /dev/dri/card0
13883 05:57:41.127353 No KMS driver or no outputs, pipes: 8, outputs: 0
13884 05:57:41.133836 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13885 05:57:41.137018 <14>[ 32.013134] [IGT] kms_vblank: executing
13886 05:57:41.143870 IGT-Version: 1.2<14>[ 32.017846] [IGT] kms_vblank: exiting, ret=77
13887 05:57:41.150284 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13888 05:57:41.157309 Opened dev<8>[ 32.028068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13889 05:57:41.157633 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13891 05:57:41.160188 ice: /dev/dri/card0
13892 05:57:41.164019 No KMS driver or no outputs, pipes: 8, outputs: 0
13893 05:57:41.166923 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13894 05:57:41.174555 <14>[ 32.048530] [IGT] kms_vblank: executing
13895 05:57:41.181191 IGT-Version: 1.2<14>[ 32.053281] [IGT] kms_vblank: exiting, ret=77
13896 05:57:41.184197 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13897 05:57:41.194160 Opened dev<8>[ 32.063438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13898 05:57:41.194330 ice: /dev/dri/card0
13899 05:57:41.194615 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13901 05:57:41.200735 No KMS driver or no outputs, pipes: 8, outputs: 0
13902 05:57:41.204438 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13903 05:57:41.210785 <14>[ 32.084378] [IGT] kms_vblank: executing
13904 05:57:41.214430 IGT-Version: 1.2<14>[ 32.089084] [IGT] kms_vblank: exiting, ret=77
13905 05:57:41.221154 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13906 05:57:41.227549 Opened dev<8>[ 32.099248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13907 05:57:41.227844 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13909 05:57:41.231086 ice: /dev/dri/card0
13910 05:57:41.233883 No KMS driver or no outputs, pipes: 8, outputs: 0
13911 05:57:41.241046 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13912 05:57:41.243993 <14>[ 32.119930] [IGT] kms_vblank: executing
13913 05:57:41.250967 IGT-Version: 1.2<14>[ 32.124662] [IGT] kms_vblank: exiting, ret=77
13914 05:57:41.257318 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13915 05:57:41.263780 Opened dev<8>[ 32.134979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13916 05:57:41.264098 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13918 05:57:41.267002 ice: /dev/dri/card0
13919 05:57:41.270282 No KMS driver or no outputs, pipes: 8, outputs: 0
13920 05:57:41.277261 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13921 05:57:41.280660 <14>[ 32.156168] [IGT] kms_vblank: executing
13922 05:57:41.287254 IGT-Version: 1.2<14>[ 32.160886] [IGT] kms_vblank: exiting, ret=77
13923 05:57:41.293631 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13924 05:57:41.300243 Opened dev<8>[ 32.171006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13925 05:57:41.300567 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13927 05:57:41.303903 ice: /dev/dri/card0
13928 05:57:41.306644 No KMS driver or no outputs, pipes: 8, outputs: 0
13929 05:57:41.309943 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13930 05:57:41.317870 <14>[ 32.191753] [IGT] kms_vblank: executing
13931 05:57:41.324414 IGT-Version: 1.2<14>[ 32.196484] [IGT] kms_vblank: exiting, ret=77
13932 05:57:41.327964 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13933 05:57:41.337332 Opened dev<8>[ 32.206890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13934 05:57:41.337496 ice: /dev/dri/card0
13935 05:57:41.337795 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13937 05:57:41.344382 No KMS driver or no outputs, pipes: 8, outputs: 0
13938 05:57:41.347242 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13939 05:57:41.354079 <14>[ 32.227753] [IGT] kms_vblank: executing
13940 05:57:41.357784 IGT-Version: 1.2<14>[ 32.232483] [IGT] kms_vblank: exiting, ret=77
13941 05:57:41.364368 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13942 05:57:41.374316 Opened dev<8>[ 32.242792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13943 05:57:41.374478 ice: /dev/dri/card0
13944 05:57:41.374756 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13946 05:57:41.377863 No KMS driver or no outputs, pipes: 8, outputs: 0
13947 05:57:41.384251 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13948 05:57:41.387663 <14>[ 32.263724] [IGT] kms_vblank: executing
13949 05:57:41.394543 IGT-Version: 1.2<14>[ 32.268541] [IGT] kms_vblank: exiting, ret=77
13950 05:57:41.400906 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13951 05:57:41.410480 Opened dev<8>[ 32.278802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13952 05:57:41.410612 ice: /dev/dri/card0
13953 05:57:41.410860 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13955 05:57:41.414039 No KMS driver or no outputs, pipes: 8, outputs: 0
13956 05:57:41.420383 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13957 05:57:41.423564 <14>[ 32.300138] [IGT] kms_vblank: executing
13958 05:57:41.430703 IGT-Version: 1.2<14>[ 32.304866] [IGT] kms_vblank: exiting, ret=77
13959 05:57:41.437359 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13960 05:57:41.444320 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13962 05:57:41.446910 Opened dev<8>[ 32.315029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13963 05:57:41.446995 ice: /dev/dri/card0
13964 05:57:41.450359 No KMS driver or no outputs, pipes: 8, outputs: 0
13965 05:57:41.457078 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13966 05:57:41.460001 <14>[ 32.336596] [IGT] kms_vblank: executing
13967 05:57:41.466853 IGT-Version: 1.2<14>[ 32.341343] [IGT] kms_vblank: exiting, ret=77
13968 05:57:41.473300 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13969 05:57:41.483406 Opened dev<8>[ 32.351515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13970 05:57:41.483563 ice: /dev/dri/card0
13971 05:57:41.483846 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
13973 05:57:41.490098 No KMS driver or no outputs, pipes: 8, outputs: 0
13974 05:57:41.493029 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
13975 05:57:41.500003 <14>[ 32.373466] [IGT] kms_vblank: executing
13976 05:57:41.506517 IGT-Version: 1.2<14>[ 32.378203] [IGT] kms_vblank: exiting, ret=77
13977 05:57:41.509571 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13978 05:57:41.520127 Opened dev<8>[ 32.388401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
13979 05:57:41.520266 ice: /dev/dri/card0
13980 05:57:41.520564 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
13982 05:57:41.526769 No KMS driver or no outputs, pipes: 8, outputs: 0
13983 05:57:41.529735 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13984 05:57:41.535999 <14>[ 32.410015] [IGT] kms_vblank: executing
13985 05:57:41.543086 IGT-Version: 1.2<14>[ 32.414837] [IGT] kms_vblank: exiting, ret=77
13986 05:57:41.546372 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13987 05:57:41.556178 Opened dev<8>[ 32.425003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
13988 05:57:41.556393 ice: /dev/dri/card0
13989 05:57:41.556687 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
13991 05:57:41.563225 No KMS driver or no outputs, pipes: 8, outputs: 0
13992 05:57:41.569635 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13993 05:57:41.573197 <14>[ 32.447034] [IGT] kms_vblank: executing
13994 05:57:41.579832 IGT-Version: 1.2<14>[ 32.452030] [IGT] kms_vblank: exiting, ret=77
13995 05:57:41.582657 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
13996 05:57:41.593093 Opened dev<8>[ 32.462377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
13997 05:57:41.593434 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
13999 05:57:41.595953 ice: /dev/dri/card0
14000 05:57:41.599683 No KMS driver or no outputs, pipes: 8, outputs: 0
14001 05:57:41.606286 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
14002 05:57:41.609341 <14>[ 32.484021] [IGT] kms_vblank: executing
14003 05:57:41.616313 IGT-Version: 1.2<14>[ 32.488765] [IGT] kms_vblank: exiting, ret=77
14004 05:57:41.619130 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
14005 05:57:41.629313 Opened dev<8>[ 32.498891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
14006 05:57:41.629635 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
14008 05:57:41.632465 ice: /dev/dri/card0
14009 05:57:41.635706 No KMS driver or no outputs, pipes: 8, outputs: 0
14010 05:57:41.642273 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
14011 05:57:41.645711 <14>[ 32.520671] [IGT] kms_vblank: executing
14012 05:57:41.652630 IGT-Version: 1.2<14>[ 32.525416] [IGT] kms_vblank: exiting, ret=77
14013 05:57:41.655421 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
14014 05:57:41.665747 Opened dev<8>[ 32.535499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
14015 05:57:41.666099 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
14017 05:57:41.668677 ice: /dev/dri/card0
14018 05:57:41.672124 No KMS driver or no outputs, pipes: 8, outputs: 0
14019 05:57:41.678668 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
14020 05:57:41.682374 <14>[ 32.557435] [IGT] kms_vblank: executing
14021 05:57:41.688596 IGT-Version: 1.2<14>[ 32.562823] [IGT] kms_vblank: exiting, ret=77
14022 05:57:41.695768 7.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
14023 05:57:41.702425 Opened dev<8>[ 32.572840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
14024 05:57:41.702729 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
14026 05:57:41.705438 ice: /dev/dri/card0
14027 05:57:41.709281 Received signal: <TESTSET> STOP
14028 05:57:41.709401 Closing test_set kms_vblank
14029 05:57:41.712096 No KMS driv<8>[ 32.584236] <LAVA_SIGNAL_TESTSET STOP>
14030 05:57:41.718820 er or no outputs, pipes: 8, outp<8>[ 32.591248] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 12379421_1.5.2.3.1>
14031 05:57:41.719115 Received signal: <ENDRUN> 0_igt-kms-mediatek 12379421_1.5.2.3.1
14032 05:57:41.719235 Ending use of test pattern.
14033 05:57:41.719330 Ending test lava.0_igt-kms-mediatek (12379421_1.5.2.3.1), duration 12.28
14035 05:57:41.722486 uts: 0
14036 05:57:41.725458 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
14037 05:57:41.729208 + set +x
14038 05:57:41.729307 <LAVA_TEST_RUNNER EXIT>
14039 05:57:41.729553 ok: lava_test_shell seems to have completed
14040 05:57:41.733512 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
14041 05:57:41.733763 end: 3.1 lava-test-shell (duration 00:00:13) [common]
14042 05:57:41.733859 end: 3 lava-test-retry (duration 00:00:13) [common]
14043 05:57:41.733951 start: 4 finalize (timeout 00:07:46) [common]
14044 05:57:41.734046 start: 4.1 power-off (timeout 00:00:30) [common]
14045 05:57:41.734200 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
14046 05:57:41.807463 >> Command sent successfully.
14047 05:57:41.810410 Returned 0 in 0 seconds
14048 05:57:41.910843 end: 4.1 power-off (duration 00:00:00) [common]
14050 05:57:41.911326 start: 4.2 read-feedback (timeout 00:07:46) [common]
14051 05:57:41.911662 Listened to connection for namespace 'common' for up to 1s
14052 05:57:42.912348 Finalising connection for namespace 'common'
14053 05:57:42.912513 Disconnecting from shell: Finalise
14054 05:57:42.912597 / #
14055 05:57:43.012906 end: 4.2 read-feedback (duration 00:00:01) [common]
14056 05:57:43.013112 end: 4 finalize (duration 00:00:01) [common]
14057 05:57:43.013264 Cleaning after the job
14058 05:57:43.013402 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379421/tftp-deploy-gmkmbio6/ramdisk
14059 05:57:43.020999 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379421/tftp-deploy-gmkmbio6/kernel
14060 05:57:43.029878 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379421/tftp-deploy-gmkmbio6/dtb
14061 05:57:43.030095 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379421/tftp-deploy-gmkmbio6/modules
14062 05:57:43.037574 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12379421
14063 05:57:43.159099 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12379421
14064 05:57:43.159268 Job finished correctly