Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 17
- Kernel Errors: 38
- Errors: 0
1 05:57:52.171445 lava-dispatcher, installed at version: 2023.10
2 05:57:52.171664 start: 0 validate
3 05:57:52.171815 Start time: 2023-12-25 05:57:52.171806+00:00 (UTC)
4 05:57:52.171946 Using caching service: 'http://localhost/cache/?uri=%s'
5 05:57:52.172070 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 05:57:52.445846 Using caching service: 'http://localhost/cache/?uri=%s'
7 05:57:52.446019 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 05:57:52.704185 Using caching service: 'http://localhost/cache/?uri=%s'
9 05:57:52.704406 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 05:57:52.970462 Using caching service: 'http://localhost/cache/?uri=%s'
11 05:57:52.970720 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:57:53.241965 Using caching service: 'http://localhost/cache/?uri=%s'
13 05:57:53.242670 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 05:57:53.511020 validate duration: 1.34
16 05:57:53.512237 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:57:53.512802 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:57:53.513290 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:57:53.513889 Not decompressing ramdisk as can be used compressed.
20 05:57:53.514350 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 05:57:53.514702 saving as /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/ramdisk/initrd.cpio.gz
22 05:57:53.515061 total size: 4665395 (4 MB)
23 05:57:53.520610 progress 0 % (0 MB)
24 05:57:53.529203 progress 5 % (0 MB)
25 05:57:53.534998 progress 10 % (0 MB)
26 05:57:53.539143 progress 15 % (0 MB)
27 05:57:53.542615 progress 20 % (0 MB)
28 05:57:53.545468 progress 25 % (1 MB)
29 05:57:53.548115 progress 30 % (1 MB)
30 05:57:53.550480 progress 35 % (1 MB)
31 05:57:53.552729 progress 40 % (1 MB)
32 05:57:53.555006 progress 45 % (2 MB)
33 05:57:53.557026 progress 50 % (2 MB)
34 05:57:53.558795 progress 55 % (2 MB)
35 05:57:53.560552 progress 60 % (2 MB)
36 05:57:53.562292 progress 65 % (2 MB)
37 05:57:53.563847 progress 70 % (3 MB)
38 05:57:53.565406 progress 75 % (3 MB)
39 05:57:53.566956 progress 80 % (3 MB)
40 05:57:53.568569 progress 85 % (3 MB)
41 05:57:53.569974 progress 90 % (4 MB)
42 05:57:53.571374 progress 95 % (4 MB)
43 05:57:53.572735 progress 100 % (4 MB)
44 05:57:53.572892 4 MB downloaded in 0.06 s (76.90 MB/s)
45 05:57:53.573051 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:57:53.573293 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:57:53.573380 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:57:53.573465 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:57:53.573600 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 05:57:53.573669 saving as /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/kernel/Image
52 05:57:53.573731 total size: 50024960 (47 MB)
53 05:57:53.573793 No compression specified
54 05:57:53.574874 progress 0 % (0 MB)
55 05:57:53.587841 progress 5 % (2 MB)
56 05:57:53.600684 progress 10 % (4 MB)
57 05:57:53.613571 progress 15 % (7 MB)
58 05:57:53.626749 progress 20 % (9 MB)
59 05:57:53.639626 progress 25 % (11 MB)
60 05:57:53.652609 progress 30 % (14 MB)
61 05:57:53.665548 progress 35 % (16 MB)
62 05:57:53.678370 progress 40 % (19 MB)
63 05:57:53.691236 progress 45 % (21 MB)
64 05:57:53.704260 progress 50 % (23 MB)
65 05:57:53.717186 progress 55 % (26 MB)
66 05:57:53.730155 progress 60 % (28 MB)
67 05:57:53.743266 progress 65 % (31 MB)
68 05:57:53.756172 progress 70 % (33 MB)
69 05:57:53.769008 progress 75 % (35 MB)
70 05:57:53.781952 progress 80 % (38 MB)
71 05:57:53.794757 progress 85 % (40 MB)
72 05:57:53.807685 progress 90 % (42 MB)
73 05:57:53.820766 progress 95 % (45 MB)
74 05:57:53.833447 progress 100 % (47 MB)
75 05:57:53.833663 47 MB downloaded in 0.26 s (183.54 MB/s)
76 05:57:53.833810 end: 1.2.1 http-download (duration 00:00:00) [common]
78 05:57:53.834039 end: 1.2 download-retry (duration 00:00:00) [common]
79 05:57:53.834125 start: 1.3 download-retry (timeout 00:10:00) [common]
80 05:57:53.834211 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 05:57:53.834340 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 05:57:53.834410 saving as /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/dtb/mt8192-asurada-spherion-r0.dtb
83 05:57:53.834470 total size: 47278 (0 MB)
84 05:57:53.834530 No compression specified
85 05:57:53.835673 progress 69 % (0 MB)
86 05:57:53.835964 progress 100 % (0 MB)
87 05:57:53.836121 0 MB downloaded in 0.00 s (27.34 MB/s)
88 05:57:53.836244 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:57:53.836459 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:57:53.836557 start: 1.4 download-retry (timeout 00:10:00) [common]
92 05:57:53.836684 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 05:57:53.837444 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 05:57:53.837510 saving as /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/nfsrootfs/full.rootfs.tar
95 05:57:53.837568 total size: 200813988 (191 MB)
96 05:57:53.837655 Using unxz to decompress xz
97 05:57:53.842171 progress 0 % (0 MB)
98 05:57:54.369125 progress 5 % (9 MB)
99 05:57:54.880304 progress 10 % (19 MB)
100 05:57:55.463377 progress 15 % (28 MB)
101 05:57:55.833661 progress 20 % (38 MB)
102 05:57:56.156159 progress 25 % (47 MB)
103 05:57:56.742659 progress 30 % (57 MB)
104 05:57:57.287760 progress 35 % (67 MB)
105 05:57:57.873545 progress 40 % (76 MB)
106 05:57:58.427037 progress 45 % (86 MB)
107 05:57:59.004972 progress 50 % (95 MB)
108 05:57:59.630043 progress 55 % (105 MB)
109 05:58:00.288354 progress 60 % (114 MB)
110 05:58:00.404843 progress 65 % (124 MB)
111 05:58:00.542793 progress 70 % (134 MB)
112 05:58:00.637610 progress 75 % (143 MB)
113 05:58:00.707882 progress 80 % (153 MB)
114 05:58:00.776807 progress 85 % (162 MB)
115 05:58:00.876360 progress 90 % (172 MB)
116 05:58:01.149740 progress 95 % (181 MB)
117 05:58:01.722546 progress 100 % (191 MB)
118 05:58:01.727613 191 MB downloaded in 7.89 s (24.27 MB/s)
119 05:58:01.727871 end: 1.4.1 http-download (duration 00:00:08) [common]
121 05:58:01.728146 end: 1.4 download-retry (duration 00:00:08) [common]
122 05:58:01.728234 start: 1.5 download-retry (timeout 00:09:52) [common]
123 05:58:01.728320 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 05:58:01.728480 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 05:58:01.728548 saving as /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/modules/modules.tar
126 05:58:01.728608 total size: 8619328 (8 MB)
127 05:58:01.728671 Using unxz to decompress xz
128 05:58:01.733054 progress 0 % (0 MB)
129 05:58:01.753975 progress 5 % (0 MB)
130 05:58:01.777237 progress 10 % (0 MB)
131 05:58:01.800217 progress 15 % (1 MB)
132 05:58:01.823114 progress 20 % (1 MB)
133 05:58:01.847021 progress 25 % (2 MB)
134 05:58:01.872444 progress 30 % (2 MB)
135 05:58:01.898089 progress 35 % (2 MB)
136 05:58:01.920890 progress 40 % (3 MB)
137 05:58:01.944807 progress 45 % (3 MB)
138 05:58:01.969761 progress 50 % (4 MB)
139 05:58:01.993582 progress 55 % (4 MB)
140 05:58:02.017886 progress 60 % (4 MB)
141 05:58:02.043073 progress 65 % (5 MB)
142 05:58:02.069501 progress 70 % (5 MB)
143 05:58:02.092626 progress 75 % (6 MB)
144 05:58:02.119511 progress 80 % (6 MB)
145 05:58:02.144577 progress 85 % (7 MB)
146 05:58:02.168751 progress 90 % (7 MB)
147 05:58:02.197827 progress 95 % (7 MB)
148 05:58:02.227269 progress 100 % (8 MB)
149 05:58:02.231911 8 MB downloaded in 0.50 s (16.33 MB/s)
150 05:58:02.232157 end: 1.5.1 http-download (duration 00:00:01) [common]
152 05:58:02.232425 end: 1.5 download-retry (duration 00:00:01) [common]
153 05:58:02.232562 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 05:58:02.232686 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 05:58:05.775672 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12379454/extract-nfsrootfs-ytmy4fkh
156 05:58:05.775874 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 05:58:05.775971 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 05:58:05.776134 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb
159 05:58:05.776264 makedir: /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin
160 05:58:05.776365 makedir: /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/tests
161 05:58:05.776461 makedir: /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/results
162 05:58:05.776559 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-add-keys
163 05:58:05.776698 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-add-sources
164 05:58:05.776904 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-background-process-start
165 05:58:05.777038 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-background-process-stop
166 05:58:05.777163 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-common-functions
167 05:58:05.777287 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-echo-ipv4
168 05:58:05.777441 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-install-packages
169 05:58:05.777564 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-installed-packages
170 05:58:05.777687 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-os-build
171 05:58:05.777852 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-probe-channel
172 05:58:05.778023 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-probe-ip
173 05:58:05.778147 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-target-ip
174 05:58:05.778271 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-target-mac
175 05:58:05.778394 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-target-storage
176 05:58:05.778520 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-test-case
177 05:58:05.778645 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-test-event
178 05:58:05.778768 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-test-feedback
179 05:58:05.778890 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-test-raise
180 05:58:05.779012 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-test-reference
181 05:58:05.779140 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-test-runner
182 05:58:05.779263 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-test-set
183 05:58:05.779386 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-test-shell
184 05:58:05.779510 Updating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-add-keys (debian)
185 05:58:05.779659 Updating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-add-sources (debian)
186 05:58:05.779796 Updating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-install-packages (debian)
187 05:58:05.779932 Updating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-installed-packages (debian)
188 05:58:05.780067 Updating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/bin/lava-os-build (debian)
189 05:58:05.780186 Creating /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/environment
190 05:58:05.780279 LAVA metadata
191 05:58:05.780347 - LAVA_JOB_ID=12379454
192 05:58:05.780408 - LAVA_DISPATCHER_IP=192.168.201.1
193 05:58:05.780505 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 05:58:05.780569 skipped lava-vland-overlay
195 05:58:05.780640 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 05:58:05.780720 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 05:58:05.780828 skipped lava-multinode-overlay
198 05:58:05.780898 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 05:58:05.780974 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 05:58:05.781044 Loading test definitions
201 05:58:05.781133 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 05:58:05.781201 Using /lava-12379454 at stage 0
203 05:58:05.781482 uuid=12379454_1.6.2.3.1 testdef=None
204 05:58:05.781567 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 05:58:05.781648 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 05:58:05.782086 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 05:58:05.782298 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 05:58:05.782840 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 05:58:05.783064 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 05:58:05.783591 runner path: /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/0/tests/0_timesync-off test_uuid 12379454_1.6.2.3.1
213 05:58:05.783740 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 05:58:05.783957 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 05:58:05.784027 Using /lava-12379454 at stage 0
217 05:58:05.784120 Fetching tests from https://github.com/kernelci/test-definitions.git
218 05:58:05.784195 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/0/tests/1_kselftest-tpm2'
219 05:58:10.113746 Running '/usr/bin/git checkout kernelci.org
220 05:58:10.204163 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 05:58:10.204907 uuid=12379454_1.6.2.3.5 testdef=None
222 05:58:10.205062 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 05:58:10.205330 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 05:58:10.206069 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 05:58:10.206304 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 05:58:10.207275 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 05:58:10.207507 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 05:58:10.208466 runner path: /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/0/tests/1_kselftest-tpm2 test_uuid 12379454_1.6.2.3.5
232 05:58:10.208560 BOARD='mt8192-asurada-spherion-r0'
233 05:58:10.208624 BRANCH='cip'
234 05:58:10.208683 SKIPFILE='/dev/null'
235 05:58:10.208783 SKIP_INSTALL='True'
236 05:58:10.208838 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 05:58:10.208897 TST_CASENAME=''
238 05:58:10.208952 TST_CMDFILES='tpm2'
239 05:58:10.209094 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 05:58:10.209294 Creating lava-test-runner.conf files
242 05:58:10.209356 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379454/lava-overlay-rvz5yreb/lava-12379454/0 for stage 0
243 05:58:10.209449 - 0_timesync-off
244 05:58:10.209518 - 1_kselftest-tpm2
245 05:58:10.209614 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 05:58:10.209739 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 05:58:17.673774 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 05:58:17.673932 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 05:58:17.674023 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 05:58:17.674122 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 05:58:17.674209 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 05:58:17.794398 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 05:58:17.794807 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 05:58:17.794920 extracting modules file /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379454/extract-nfsrootfs-ytmy4fkh
255 05:58:18.016217 extracting modules file /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379454/extract-overlay-ramdisk-8426yuok/ramdisk
256 05:58:18.239619 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 05:58:18.239797 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 05:58:18.239905 [common] Applying overlay to NFS
259 05:58:18.239985 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379454/compress-overlay-cuzn_f6_/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12379454/extract-nfsrootfs-ytmy4fkh
260 05:58:19.165500 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 05:58:19.165678 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 05:58:19.165791 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 05:58:19.165899 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 05:58:19.165995 Building ramdisk /var/lib/lava/dispatcher/tmp/12379454/extract-overlay-ramdisk-8426yuok/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12379454/extract-overlay-ramdisk-8426yuok/ramdisk
265 05:58:19.507674 >> 119415 blocks
266 05:58:21.471642 rename /var/lib/lava/dispatcher/tmp/12379454/extract-overlay-ramdisk-8426yuok/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/ramdisk/ramdisk.cpio.gz
267 05:58:21.472101 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 05:58:21.472234 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 05:58:21.472336 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 05:58:21.472447 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/kernel/Image'
271 05:58:33.819657 Returned 0 in 12 seconds
272 05:58:33.920675 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/kernel/image.itb
273 05:58:34.273282 output: FIT description: Kernel Image image with one or more FDT blobs
274 05:58:34.273672 output: Created: Mon Dec 25 05:58:34 2023
275 05:58:34.273749 output: Image 0 (kernel-1)
276 05:58:34.273814 output: Description:
277 05:58:34.273875 output: Created: Mon Dec 25 05:58:34 2023
278 05:58:34.273936 output: Type: Kernel Image
279 05:58:34.273997 output: Compression: lzma compressed
280 05:58:34.274058 output: Data Size: 11481830 Bytes = 11212.72 KiB = 10.95 MiB
281 05:58:34.274120 output: Architecture: AArch64
282 05:58:34.274175 output: OS: Linux
283 05:58:34.274232 output: Load Address: 0x00000000
284 05:58:34.274291 output: Entry Point: 0x00000000
285 05:58:34.274351 output: Hash algo: crc32
286 05:58:34.274407 output: Hash value: a47c00f1
287 05:58:34.274463 output: Image 1 (fdt-1)
288 05:58:34.274515 output: Description: mt8192-asurada-spherion-r0
289 05:58:34.274567 output: Created: Mon Dec 25 05:58:34 2023
290 05:58:34.274620 output: Type: Flat Device Tree
291 05:58:34.274672 output: Compression: uncompressed
292 05:58:34.274725 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 05:58:34.274777 output: Architecture: AArch64
294 05:58:34.274829 output: Hash algo: crc32
295 05:58:34.274881 output: Hash value: cc4352de
296 05:58:34.274932 output: Image 2 (ramdisk-1)
297 05:58:34.274984 output: Description: unavailable
298 05:58:34.275036 output: Created: Mon Dec 25 05:58:34 2023
299 05:58:34.275088 output: Type: RAMDisk Image
300 05:58:34.275139 output: Compression: Unknown Compression
301 05:58:34.275201 output: Data Size: 17797414 Bytes = 17380.29 KiB = 16.97 MiB
302 05:58:34.275255 output: Architecture: AArch64
303 05:58:34.275307 output: OS: Linux
304 05:58:34.275358 output: Load Address: unavailable
305 05:58:34.275410 output: Entry Point: unavailable
306 05:58:34.275462 output: Hash algo: crc32
307 05:58:34.275513 output: Hash value: 4e4a58e3
308 05:58:34.275565 output: Default Configuration: 'conf-1'
309 05:58:34.275617 output: Configuration 0 (conf-1)
310 05:58:34.275669 output: Description: mt8192-asurada-spherion-r0
311 05:58:34.275720 output: Kernel: kernel-1
312 05:58:34.275772 output: Init Ramdisk: ramdisk-1
313 05:58:34.275823 output: FDT: fdt-1
314 05:58:34.275875 output: Loadables: kernel-1
315 05:58:34.275925 output:
316 05:58:34.276133 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 05:58:34.276229 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 05:58:34.276328 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 05:58:34.276420 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 05:58:34.276499 No LXC device requested
321 05:58:34.276576 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 05:58:34.276658 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 05:58:34.276761 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 05:58:34.276845 Checking files for TFTP limit of 4294967296 bytes.
325 05:58:34.277357 end: 1 tftp-deploy (duration 00:00:41) [common]
326 05:58:34.277459 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 05:58:34.277547 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 05:58:34.277684 substitutions:
329 05:58:34.277751 - {DTB}: 12379454/tftp-deploy-batrup0z/dtb/mt8192-asurada-spherion-r0.dtb
330 05:58:34.277815 - {INITRD}: 12379454/tftp-deploy-batrup0z/ramdisk/ramdisk.cpio.gz
331 05:58:34.277872 - {KERNEL}: 12379454/tftp-deploy-batrup0z/kernel/Image
332 05:58:34.277929 - {LAVA_MAC}: None
333 05:58:34.277983 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12379454/extract-nfsrootfs-ytmy4fkh
334 05:58:34.278038 - {NFS_SERVER_IP}: 192.168.201.1
335 05:58:34.278092 - {PRESEED_CONFIG}: None
336 05:58:34.278146 - {PRESEED_LOCAL}: None
337 05:58:34.278200 - {RAMDISK}: 12379454/tftp-deploy-batrup0z/ramdisk/ramdisk.cpio.gz
338 05:58:34.278252 - {ROOT_PART}: None
339 05:58:34.278305 - {ROOT}: None
340 05:58:34.278361 - {SERVER_IP}: 192.168.201.1
341 05:58:34.278413 - {TEE}: None
342 05:58:34.278467 Parsed boot commands:
343 05:58:34.278520 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 05:58:34.278706 Parsed boot commands: tftpboot 192.168.201.1 12379454/tftp-deploy-batrup0z/kernel/image.itb 12379454/tftp-deploy-batrup0z/kernel/cmdline
345 05:58:34.278792 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 05:58:34.278874 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 05:58:34.278964 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 05:58:34.279051 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 05:58:34.279120 Not connected, no need to disconnect.
350 05:58:34.279192 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 05:58:34.279271 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 05:58:34.279338 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 05:58:34.283459 Setting prompt string to ['lava-test: # ']
354 05:58:34.283868 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 05:58:34.283973 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 05:58:34.284094 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 05:58:34.284211 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 05:58:34.284450 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 05:58:39.432898 >> Command sent successfully.
360 05:58:39.444417 Returned 0 in 5 seconds
361 05:58:39.545995 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 05:58:39.547536 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 05:58:39.548084 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 05:58:39.548590 Setting prompt string to 'Starting depthcharge on Spherion...'
366 05:58:39.549036 Changing prompt to 'Starting depthcharge on Spherion...'
367 05:58:39.549564 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 05:58:39.551054 [Enter `^Ec?' for help]
369 05:58:39.718014
370 05:58:39.718736
371 05:58:39.719227 F0: 102B 0000
372 05:58:39.719721
373 05:58:39.720183 F3: 1001 0000 [0200]
374 05:58:39.720637
375 05:58:39.721647 F3: 1001 0000
376 05:58:39.722170
377 05:58:39.722645 F7: 102D 0000
378 05:58:39.723097
379 05:58:39.723551 F1: 0000 0000
380 05:58:39.723996
381 05:58:39.725104 V0: 0000 0000 [0001]
382 05:58:39.725630
383 05:58:39.726087 00: 0007 8000
384 05:58:39.726569
385 05:58:39.728654 01: 0000 0000
386 05:58:39.728985
387 05:58:39.729224 BP: 0C00 0209 [0000]
388 05:58:39.729447
389 05:58:39.729655 G0: 1182 0000
390 05:58:39.732195
391 05:58:39.732558 EC: 0000 0021 [4000]
392 05:58:39.732826
393 05:58:39.737285 S7: 0000 0000 [0000]
394 05:58:39.737656
395 05:58:39.737898 CC: 0000 0000 [0001]
396 05:58:39.738123
397 05:58:39.738339 T0: 0000 0040 [010F]
398 05:58:39.738546
399 05:58:39.740511 Jump to BL
400 05:58:39.740943
401 05:58:39.764203
402 05:58:39.764527
403 05:58:39.764762
404 05:58:39.770917 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 05:58:39.774407 ARM64: Exception handlers installed.
406 05:58:39.777923 ARM64: Testing exception
407 05:58:39.781508 ARM64: Done test exception
408 05:58:39.788288 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 05:58:39.797816 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 05:58:39.804827 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 05:58:39.815039 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 05:58:39.822344 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 05:58:39.832198 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 05:58:39.842577 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 05:58:39.849014 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 05:58:39.867443 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 05:58:39.870892 WDT: Last reset was cold boot
418 05:58:39.873996 SPI1(PAD0) initialized at 2873684 Hz
419 05:58:39.877361 SPI5(PAD0) initialized at 992727 Hz
420 05:58:39.880950 VBOOT: Loading verstage.
421 05:58:39.887498 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 05:58:39.890858 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 05:58:39.893843 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 05:58:39.897446 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 05:58:39.904748 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 05:58:39.911434 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 05:58:39.922284 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 05:58:39.922856
429 05:58:39.923226
430 05:58:39.932222 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 05:58:39.935486 ARM64: Exception handlers installed.
432 05:58:39.938809 ARM64: Testing exception
433 05:58:39.939380 ARM64: Done test exception
434 05:58:39.945668 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 05:58:39.948862 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 05:58:39.963448 Probing TPM: . done!
437 05:58:39.964182 TPM ready after 0 ms
438 05:58:39.970094 Connected to device vid:did:rid of 1ae0:0028:00
439 05:58:39.976312 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 05:58:40.019013 Initialized TPM device CR50 revision 0
441 05:58:40.031003 tlcl_send_startup: Startup return code is 0
442 05:58:40.031724 TPM: setup succeeded
443 05:58:40.042344 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 05:58:40.051071 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 05:58:40.061115 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 05:58:40.070445 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 05:58:40.073200 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 05:58:40.076788 in-header: 03 07 00 00 08 00 00 00
449 05:58:40.080078 in-data: aa e4 47 04 13 02 00 00
450 05:58:40.083358 Chrome EC: UHEPI supported
451 05:58:40.089888 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 05:58:40.093223 in-header: 03 9d 00 00 08 00 00 00
453 05:58:40.096865 in-data: 10 20 20 08 00 00 00 00
454 05:58:40.097333 Phase 1
455 05:58:40.103024 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 05:58:40.106608 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 05:58:40.113259 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 05:58:40.116565 Recovery requested (1009000e)
459 05:58:40.121281 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 05:58:40.129189 tlcl_extend: response is 0
461 05:58:40.137218 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 05:58:40.143356 tlcl_extend: response is 0
463 05:58:40.149616 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 05:58:40.171420 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 05:58:40.177610 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 05:58:40.178185
467 05:58:40.178558
468 05:58:40.187317 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 05:58:40.190985 ARM64: Exception handlers installed.
470 05:58:40.191556 ARM64: Testing exception
471 05:58:40.194043 ARM64: Done test exception
472 05:58:40.216391 pmic_efuse_setting: Set efuses in 11 msecs
473 05:58:40.220099 pmwrap_interface_init: Select PMIF_VLD_RDY
474 05:58:40.225728 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 05:58:40.229851 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 05:58:40.233057 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 05:58:40.240117 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 05:58:40.243705 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 05:58:40.247577 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 05:58:40.254221 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 05:58:40.257825 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 05:58:40.264614 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 05:58:40.267498 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 05:58:40.271143 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 05:58:40.277680 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 05:58:40.281088 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 05:58:40.287960 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 05:58:40.294237 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 05:58:40.297895 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 05:58:40.304843 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 05:58:40.312177 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 05:58:40.315664 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 05:58:40.322301 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 05:58:40.325713 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 05:58:40.332522 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 05:58:40.339260 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 05:58:40.345568 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 05:58:40.348829 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 05:58:40.355982 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 05:58:40.359183 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 05:58:40.365624 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 05:58:40.368499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 05:58:40.375188 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 05:58:40.378357 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 05:58:40.384792 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 05:58:40.388536 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 05:58:40.394947 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 05:58:40.398426 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 05:58:40.405337 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 05:58:40.409088 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 05:58:40.415203 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 05:58:40.418127 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 05:58:40.424742 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 05:58:40.428331 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 05:58:40.431507 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 05:58:40.438398 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 05:58:40.441538 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 05:58:40.444791 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 05:58:40.448126 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 05:58:40.454802 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 05:58:40.457843 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 05:58:40.461412 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 05:58:40.468550 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 05:58:40.471491 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 05:58:40.478258 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 05:58:40.488940 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 05:58:40.491599 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 05:58:40.498112 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 05:58:40.508519 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 05:58:40.511431 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 05:58:40.517923 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 05:58:40.521156 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 05:58:40.528149 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 05:58:40.534913 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 05:58:40.538070 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 05:58:40.541656 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 05:58:40.552931 [RTC]rtc_get_frequency_meter,154: input=15, output=764
538 05:58:40.562188 [RTC]rtc_get_frequency_meter,154: input=23, output=949
539 05:58:40.571826 [RTC]rtc_get_frequency_meter,154: input=19, output=857
540 05:58:40.581599 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 05:58:40.590870 [RTC]rtc_get_frequency_meter,154: input=16, output=786
542 05:58:40.601096 [RTC]rtc_get_frequency_meter,154: input=16, output=787
543 05:58:40.609876 [RTC]rtc_get_frequency_meter,154: input=17, output=811
544 05:58:40.613328 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 05:58:40.620510 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 05:58:40.623833 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 05:58:40.627016 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 05:58:40.633497 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 05:58:40.637027 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 05:58:40.640386 ADC[4]: Raw value=670432 ID=5
551 05:58:40.640908 ADC[3]: Raw value=212917 ID=1
552 05:58:40.643430 RAM Code: 0x51
553 05:58:40.647121 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 05:58:40.653901 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 05:58:40.660228 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 05:58:40.667176 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 05:58:40.670169 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 05:58:40.674143 in-header: 03 07 00 00 08 00 00 00
559 05:58:40.676858 in-data: aa e4 47 04 13 02 00 00
560 05:58:40.680286 Chrome EC: UHEPI supported
561 05:58:40.687140 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 05:58:40.690356 in-header: 03 d5 00 00 08 00 00 00
563 05:58:40.693744 in-data: 98 20 60 08 00 00 00 00
564 05:58:40.697159 MRC: failed to locate region type 0.
565 05:58:40.700639 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 05:58:40.703830 DRAM-K: Running full calibration
567 05:58:40.710320 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 05:58:40.713762 header.status = 0x0
569 05:58:40.717027 header.version = 0x6 (expected: 0x6)
570 05:58:40.720312 header.size = 0xd00 (expected: 0xd00)
571 05:58:40.720839 header.flags = 0x0
572 05:58:40.727264 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 05:58:40.744956 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 05:58:40.752017 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 05:58:40.755530 dram_init: ddr_geometry: 0
576 05:58:40.756147 [EMI] MDL number = 0
577 05:58:40.758732 [EMI] Get MDL freq = 0
578 05:58:40.761938 dram_init: ddr_type: 0
579 05:58:40.762409 is_discrete_lpddr4: 1
580 05:58:40.765073 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 05:58:40.765545
582 05:58:40.765916
583 05:58:40.768835 [Bian_co] ETT version 0.0.0.1
584 05:58:40.772326 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 05:58:40.772842
586 05:58:40.778782 dramc_set_vcore_voltage set vcore to 650000
587 05:58:40.779292 Read voltage for 800, 4
588 05:58:40.782029 Vio18 = 0
589 05:58:40.782494 Vcore = 650000
590 05:58:40.782863 Vdram = 0
591 05:58:40.783205 Vddq = 0
592 05:58:40.785672 Vmddr = 0
593 05:58:40.786138 dram_init: config_dvfs: 1
594 05:58:40.792253 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 05:58:40.798739 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 05:58:40.802372 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 05:58:40.805521 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 05:58:40.809039 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 05:58:40.812362 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 05:58:40.815572 MEM_TYPE=3, freq_sel=18
601 05:58:40.818636 sv_algorithm_assistance_LP4_1600
602 05:58:40.822172 ============ PULL DRAM RESETB DOWN ============
603 05:58:40.825479 ========== PULL DRAM RESETB DOWN end =========
604 05:58:40.832455 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 05:58:40.835504 ===================================
606 05:58:40.835981 LPDDR4 DRAM CONFIGURATION
607 05:58:40.839350 ===================================
608 05:58:40.842394 EX_ROW_EN[0] = 0x0
609 05:58:40.842969 EX_ROW_EN[1] = 0x0
610 05:58:40.845699 LP4Y_EN = 0x0
611 05:58:40.846169 WORK_FSP = 0x0
612 05:58:40.848945 WL = 0x2
613 05:58:40.852359 RL = 0x2
614 05:58:40.852985 BL = 0x2
615 05:58:40.855681 RPST = 0x0
616 05:58:40.856258 RD_PRE = 0x0
617 05:58:40.859136 WR_PRE = 0x1
618 05:58:40.859717 WR_PST = 0x0
619 05:58:40.862252 DBI_WR = 0x0
620 05:58:40.862663 DBI_RD = 0x0
621 05:58:40.865420 OTF = 0x1
622 05:58:40.868792 ===================================
623 05:58:40.872515 ===================================
624 05:58:40.873164 ANA top config
625 05:58:40.875652 ===================================
626 05:58:40.879142 DLL_ASYNC_EN = 0
627 05:58:40.882341 ALL_SLAVE_EN = 1
628 05:58:40.882913 NEW_RANK_MODE = 1
629 05:58:40.885427 DLL_IDLE_MODE = 1
630 05:58:40.889045 LP45_APHY_COMB_EN = 1
631 05:58:40.892169 TX_ODT_DIS = 1
632 05:58:40.892649 NEW_8X_MODE = 1
633 05:58:40.895503 ===================================
634 05:58:40.898871 ===================================
635 05:58:40.902281 data_rate = 1600
636 05:58:40.905699 CKR = 1
637 05:58:40.908638 DQ_P2S_RATIO = 8
638 05:58:40.912307 ===================================
639 05:58:40.915594 CA_P2S_RATIO = 8
640 05:58:40.918918 DQ_CA_OPEN = 0
641 05:58:40.919387 DQ_SEMI_OPEN = 0
642 05:58:40.921869 CA_SEMI_OPEN = 0
643 05:58:40.925520 CA_FULL_RATE = 0
644 05:58:40.928805 DQ_CKDIV4_EN = 1
645 05:58:40.932003 CA_CKDIV4_EN = 1
646 05:58:40.935304 CA_PREDIV_EN = 0
647 05:58:40.935763 PH8_DLY = 0
648 05:58:40.938984 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 05:58:40.941991 DQ_AAMCK_DIV = 4
650 05:58:40.945234 CA_AAMCK_DIV = 4
651 05:58:40.949027 CA_ADMCK_DIV = 4
652 05:58:40.952149 DQ_TRACK_CA_EN = 0
653 05:58:40.952563 CA_PICK = 800
654 05:58:40.955528 CA_MCKIO = 800
655 05:58:40.958925 MCKIO_SEMI = 0
656 05:58:40.962437 PLL_FREQ = 3068
657 05:58:40.965366 DQ_UI_PI_RATIO = 32
658 05:58:40.969190 CA_UI_PI_RATIO = 0
659 05:58:40.971959 ===================================
660 05:58:40.975522 ===================================
661 05:58:40.976180 memory_type:LPDDR4
662 05:58:40.979292 GP_NUM : 10
663 05:58:40.982152 SRAM_EN : 1
664 05:58:40.982650 MD32_EN : 0
665 05:58:40.985577 ===================================
666 05:58:40.988792 [ANA_INIT] >>>>>>>>>>>>>>
667 05:58:40.992039 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 05:58:40.995432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 05:58:40.998638 ===================================
670 05:58:41.002353 data_rate = 1600,PCW = 0X7600
671 05:58:41.005485 ===================================
672 05:58:41.008759 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 05:58:41.012328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 05:58:41.018970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 05:58:41.022245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 05:58:41.025484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 05:58:41.028464 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 05:58:41.032118 [ANA_INIT] flow start
679 05:58:41.035529 [ANA_INIT] PLL >>>>>>>>
680 05:58:41.036177 [ANA_INIT] PLL <<<<<<<<
681 05:58:41.038464 [ANA_INIT] MIDPI >>>>>>>>
682 05:58:41.042154 [ANA_INIT] MIDPI <<<<<<<<
683 05:58:41.045159 [ANA_INIT] DLL >>>>>>>>
684 05:58:41.045794 [ANA_INIT] flow end
685 05:58:41.048784 ============ LP4 DIFF to SE enter ============
686 05:58:41.055226 ============ LP4 DIFF to SE exit ============
687 05:58:41.055657 [ANA_INIT] <<<<<<<<<<<<<
688 05:58:41.058665 [Flow] Enable top DCM control >>>>>
689 05:58:41.061573 [Flow] Enable top DCM control <<<<<
690 05:58:41.064958 Enable DLL master slave shuffle
691 05:58:41.071733 ==============================================================
692 05:58:41.072052 Gating Mode config
693 05:58:41.078505 ==============================================================
694 05:58:41.081664 Config description:
695 05:58:41.088480 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 05:58:41.094920 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 05:58:41.101744 SELPH_MODE 0: By rank 1: By Phase
698 05:58:41.108519 ==============================================================
699 05:58:41.109180 GAT_TRACK_EN = 1
700 05:58:41.112012 RX_GATING_MODE = 2
701 05:58:41.115452 RX_GATING_TRACK_MODE = 2
702 05:58:41.118690 SELPH_MODE = 1
703 05:58:41.121892 PICG_EARLY_EN = 1
704 05:58:41.125161 VALID_LAT_VALUE = 1
705 05:58:41.131990 ==============================================================
706 05:58:41.135341 Enter into Gating configuration >>>>
707 05:58:41.138228 Exit from Gating configuration <<<<
708 05:58:41.141681 Enter into DVFS_PRE_config >>>>>
709 05:58:41.151833 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 05:58:41.155057 Exit from DVFS_PRE_config <<<<<
711 05:58:41.158753 Enter into PICG configuration >>>>
712 05:58:41.162095 Exit from PICG configuration <<<<
713 05:58:41.165090 [RX_INPUT] configuration >>>>>
714 05:58:41.165562 [RX_INPUT] configuration <<<<<
715 05:58:41.171663 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 05:58:41.178749 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 05:58:41.182031 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 05:58:41.188318 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 05:58:41.195100 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 05:58:41.202146 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 05:58:41.205361 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 05:58:41.208586 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 05:58:41.215285 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 05:58:41.218873 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 05:58:41.221720 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 05:58:41.228603 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 05:58:41.232088 ===================================
728 05:58:41.232668 LPDDR4 DRAM CONFIGURATION
729 05:58:41.235293 ===================================
730 05:58:41.238121 EX_ROW_EN[0] = 0x0
731 05:58:41.238615 EX_ROW_EN[1] = 0x0
732 05:58:41.241955 LP4Y_EN = 0x0
733 05:58:41.242530 WORK_FSP = 0x0
734 05:58:41.245144 WL = 0x2
735 05:58:41.245612 RL = 0x2
736 05:58:41.248265 BL = 0x2
737 05:58:41.251810 RPST = 0x0
738 05:58:41.252384 RD_PRE = 0x0
739 05:58:41.254803 WR_PRE = 0x1
740 05:58:41.255289 WR_PST = 0x0
741 05:58:41.258840 DBI_WR = 0x0
742 05:58:41.259452 DBI_RD = 0x0
743 05:58:41.261496 OTF = 0x1
744 05:58:41.265027 ===================================
745 05:58:41.268349 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 05:58:41.271628 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 05:58:41.275308 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 05:58:41.278352 ===================================
749 05:58:41.281518 LPDDR4 DRAM CONFIGURATION
750 05:58:41.285206 ===================================
751 05:58:41.288096 EX_ROW_EN[0] = 0x10
752 05:58:41.288564 EX_ROW_EN[1] = 0x0
753 05:58:41.291358 LP4Y_EN = 0x0
754 05:58:41.291830 WORK_FSP = 0x0
755 05:58:41.294975 WL = 0x2
756 05:58:41.295449 RL = 0x2
757 05:58:41.298079 BL = 0x2
758 05:58:41.298685 RPST = 0x0
759 05:58:41.301614 RD_PRE = 0x0
760 05:58:41.302087 WR_PRE = 0x1
761 05:58:41.304973 WR_PST = 0x0
762 05:58:41.305519 DBI_WR = 0x0
763 05:58:41.308081 DBI_RD = 0x0
764 05:58:41.311148 OTF = 0x1
765 05:58:41.311620 ===================================
766 05:58:41.317796 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 05:58:41.323013 nWR fixed to 40
768 05:58:41.326544 [ModeRegInit_LP4] CH0 RK0
769 05:58:41.326986 [ModeRegInit_LP4] CH0 RK1
770 05:58:41.329440 [ModeRegInit_LP4] CH1 RK0
771 05:58:41.333059 [ModeRegInit_LP4] CH1 RK1
772 05:58:41.333509 match AC timing 12
773 05:58:41.339918 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 05:58:41.343289 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 05:58:41.346796 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 05:58:41.353129 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 05:58:41.356439 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 05:58:41.356911 [EMI DOE] emi_dcm 0
779 05:58:41.363133 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 05:58:41.363654 ==
781 05:58:41.366243 Dram Type= 6, Freq= 0, CH_0, rank 0
782 05:58:41.369664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 05:58:41.370087 ==
784 05:58:41.376243 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 05:58:41.382951 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 05:58:41.390918 [CA 0] Center 37 (7~68) winsize 62
787 05:58:41.394080 [CA 1] Center 37 (7~68) winsize 62
788 05:58:41.397368 [CA 2] Center 35 (5~66) winsize 62
789 05:58:41.400406 [CA 3] Center 35 (4~66) winsize 63
790 05:58:41.403807 [CA 4] Center 34 (4~65) winsize 62
791 05:58:41.406973 [CA 5] Center 33 (3~64) winsize 62
792 05:58:41.407464
793 05:58:41.410757 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 05:58:41.411355
795 05:58:41.413904 [CATrainingPosCal] consider 1 rank data
796 05:58:41.417074 u2DelayCellTimex100 = 270/100 ps
797 05:58:41.420690 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 05:58:41.423678 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 05:58:41.430427 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 05:58:41.433844 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 05:58:41.436974 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
802 05:58:41.440292 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 05:58:41.440852
804 05:58:41.443526 CA PerBit enable=1, Macro0, CA PI delay=33
805 05:58:41.444020
806 05:58:41.446938 [CBTSetCACLKResult] CA Dly = 33
807 05:58:41.447428 CS Dly: 6 (0~37)
808 05:58:41.450676 ==
809 05:58:41.451166 Dram Type= 6, Freq= 0, CH_0, rank 1
810 05:58:41.457145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 05:58:41.457596 ==
812 05:58:41.460181 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 05:58:41.466858 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 05:58:41.476602 [CA 0] Center 37 (7~68) winsize 62
815 05:58:41.479853 [CA 1] Center 37 (6~68) winsize 63
816 05:58:41.483432 [CA 2] Center 35 (4~66) winsize 63
817 05:58:41.486457 [CA 3] Center 35 (4~66) winsize 63
818 05:58:41.490385 [CA 4] Center 33 (3~64) winsize 62
819 05:58:41.493168 [CA 5] Center 33 (3~64) winsize 62
820 05:58:41.493739
821 05:58:41.496487 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 05:58:41.497032
823 05:58:41.500202 [CATrainingPosCal] consider 2 rank data
824 05:58:41.503501 u2DelayCellTimex100 = 270/100 ps
825 05:58:41.506422 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 05:58:41.510104 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 05:58:41.516819 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 05:58:41.520113 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
829 05:58:41.523588 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
830 05:58:41.526372 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 05:58:41.526851
832 05:58:41.529631 CA PerBit enable=1, Macro0, CA PI delay=33
833 05:58:41.530097
834 05:58:41.533185 [CBTSetCACLKResult] CA Dly = 33
835 05:58:41.533651 CS Dly: 6 (0~37)
836 05:58:41.534100
837 05:58:41.536298 ----->DramcWriteLeveling(PI) begin...
838 05:58:41.539641 ==
839 05:58:41.542731 Dram Type= 6, Freq= 0, CH_0, rank 0
840 05:58:41.546492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 05:58:41.547003 ==
842 05:58:41.549619 Write leveling (Byte 0): 32 => 32
843 05:58:41.552763 Write leveling (Byte 1): 27 => 27
844 05:58:41.556368 DramcWriteLeveling(PI) end<-----
845 05:58:41.556992
846 05:58:41.557366 ==
847 05:58:41.559999 Dram Type= 6, Freq= 0, CH_0, rank 0
848 05:58:41.562984 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 05:58:41.563639 ==
850 05:58:41.566288 [Gating] SW mode calibration
851 05:58:41.573004 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 05:58:41.576571 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 05:58:41.583589 0 6 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
854 05:58:41.586435 0 6 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
855 05:58:41.589886 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 05:58:41.596496 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 05:58:41.599818 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 05:58:41.603070 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 05:58:41.609807 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 05:58:41.613403 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 05:58:41.616773 0 7 0 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (0 0)
862 05:58:41.623176 0 7 4 | B1->B0 | 3a3a 3f3f | 1 0 | (0 0) (0 0)
863 05:58:41.626419 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 05:58:41.629388 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 05:58:41.636178 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 05:58:41.639990 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 05:58:41.642865 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 05:58:41.649738 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 05:58:41.652837 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
870 05:58:41.656575 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 05:58:41.663394 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 05:58:41.666502 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 05:58:41.669690 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 05:58:41.676444 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 05:58:41.680014 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 05:58:41.683183 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 05:58:41.686449 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 05:58:41.693344 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 05:58:41.696678 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 05:58:41.699917 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 05:58:41.705770 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 05:58:41.709276 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 05:58:41.712621 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 05:58:41.719526 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 05:58:41.722682 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
886 05:58:41.725795 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 05:58:41.729490 Total UI for P1: 0, mck2ui 16
888 05:58:41.732565 best dqsien dly found for B0: ( 0, 10, 2)
889 05:58:41.736003 Total UI for P1: 0, mck2ui 16
890 05:58:41.739156 best dqsien dly found for B1: ( 0, 10, 0)
891 05:58:41.742742 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
892 05:58:41.746006 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
893 05:58:41.749223
894 05:58:41.752658 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
895 05:58:41.755838 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
896 05:58:41.759633 [Gating] SW calibration Done
897 05:58:41.760162 ==
898 05:58:41.763176 Dram Type= 6, Freq= 0, CH_0, rank 0
899 05:58:41.766376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 05:58:41.766818 ==
901 05:58:41.767227 RX Vref Scan: 0
902 05:58:41.767555
903 05:58:41.769811 RX Vref 0 -> 0, step: 1
904 05:58:41.770269
905 05:58:41.773529 RX Delay -130 -> 252, step: 16
906 05:58:41.776495 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 05:58:41.780252 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 05:58:41.783482 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 05:58:41.789906 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 05:58:41.793708 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 05:58:41.796754 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 05:58:41.799888 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 05:58:41.803882 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 05:58:41.806528 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
915 05:58:41.813454 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 05:58:41.816758 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 05:58:41.819941 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 05:58:41.823768 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 05:58:41.826873 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 05:58:41.833707 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 05:58:41.836616 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 05:58:41.837141 ==
923 05:58:41.840039 Dram Type= 6, Freq= 0, CH_0, rank 0
924 05:58:41.843454 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 05:58:41.844055 ==
926 05:58:41.846734 DQS Delay:
927 05:58:41.847257 DQS0 = 0, DQS1 = 0
928 05:58:41.847747 DQM Delay:
929 05:58:41.850395 DQM0 = 82, DQM1 = 74
930 05:58:41.850936 DQ Delay:
931 05:58:41.853220 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
932 05:58:41.856419 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
933 05:58:41.859969 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
934 05:58:41.863068 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 05:58:41.863340
936 05:58:41.863508
937 05:58:41.863642 ==
938 05:58:41.866774 Dram Type= 6, Freq= 0, CH_0, rank 0
939 05:58:41.873360 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 05:58:41.873641 ==
941 05:58:41.873799
942 05:58:41.873940
943 05:58:41.874074 TX Vref Scan disable
944 05:58:41.876980 == TX Byte 0 ==
945 05:58:41.880278 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
946 05:58:41.887187 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
947 05:58:41.887473 == TX Byte 1 ==
948 05:58:41.890398 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
949 05:58:41.897004 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
950 05:58:41.897582 ==
951 05:58:41.900670 Dram Type= 6, Freq= 0, CH_0, rank 0
952 05:58:41.903613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 05:58:41.904194 ==
954 05:58:41.916809 TX Vref=22, minBit 5, minWin=27, winSum=443
955 05:58:41.919719 TX Vref=24, minBit 11, minWin=27, winSum=451
956 05:58:41.923087 TX Vref=26, minBit 11, minWin=27, winSum=452
957 05:58:41.926363 TX Vref=28, minBit 11, minWin=27, winSum=453
958 05:58:41.929851 TX Vref=30, minBit 0, minWin=28, winSum=452
959 05:58:41.936582 TX Vref=32, minBit 0, minWin=28, winSum=451
960 05:58:41.939663 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
961 05:58:41.940136
962 05:58:41.943330 Final TX Range 1 Vref 30
963 05:58:41.944031
964 05:58:41.944414 ==
965 05:58:41.946842 Dram Type= 6, Freq= 0, CH_0, rank 0
966 05:58:41.949802 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 05:58:41.950281 ==
968 05:58:41.953706
969 05:58:41.954463
970 05:58:41.954973 TX Vref Scan disable
971 05:58:41.956700 == TX Byte 0 ==
972 05:58:41.960421 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
973 05:58:41.963287 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
974 05:58:41.967187 == TX Byte 1 ==
975 05:58:41.970081 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
976 05:58:41.973423 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
977 05:58:41.976840
978 05:58:41.977451 [DATLAT]
979 05:58:41.977989 Freq=800, CH0 RK0
980 05:58:41.978525
981 05:58:41.980280 DATLAT Default: 0xa
982 05:58:41.980909 0, 0xFFFF, sum = 0
983 05:58:41.983341 1, 0xFFFF, sum = 0
984 05:58:41.983758 2, 0xFFFF, sum = 0
985 05:58:41.986422 3, 0xFFFF, sum = 0
986 05:58:41.986819 4, 0xFFFF, sum = 0
987 05:58:41.990006 5, 0xFFFF, sum = 0
988 05:58:41.990304 6, 0xFFFF, sum = 0
989 05:58:41.993324 7, 0xFFFF, sum = 0
990 05:58:41.993586 8, 0x0, sum = 1
991 05:58:41.996566 9, 0x0, sum = 2
992 05:58:41.996776 10, 0x0, sum = 3
993 05:58:41.999739 11, 0x0, sum = 4
994 05:58:41.999987 best_step = 9
995 05:58:42.000141
996 05:58:42.000299 ==
997 05:58:42.003351 Dram Type= 6, Freq= 0, CH_0, rank 0
998 05:58:42.010382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 05:58:42.010627 ==
1000 05:58:42.010763 RX Vref Scan: 1
1001 05:58:42.010885
1002 05:58:42.013286 Set Vref Range= 32 -> 127
1003 05:58:42.013526
1004 05:58:42.016824 RX Vref 32 -> 127, step: 1
1005 05:58:42.017065
1006 05:58:42.019816 RX Delay -111 -> 252, step: 8
1007 05:58:42.020066
1008 05:58:42.020192 Set Vref, RX VrefLevel [Byte0]: 32
1009 05:58:42.023118 [Byte1]: 32
1010 05:58:42.027423
1011 05:58:42.027602 Set Vref, RX VrefLevel [Byte0]: 33
1012 05:58:42.030956 [Byte1]: 33
1013 05:58:42.035032
1014 05:58:42.035183 Set Vref, RX VrefLevel [Byte0]: 34
1015 05:58:42.038104 [Byte1]: 34
1016 05:58:42.043004
1017 05:58:42.043262 Set Vref, RX VrefLevel [Byte0]: 35
1018 05:58:42.045987 [Byte1]: 35
1019 05:58:42.050504
1020 05:58:42.050834 Set Vref, RX VrefLevel [Byte0]: 36
1021 05:58:42.054242 [Byte1]: 36
1022 05:58:42.058075
1023 05:58:42.058423 Set Vref, RX VrefLevel [Byte0]: 37
1024 05:58:42.061739 [Byte1]: 37
1025 05:58:42.065943
1026 05:58:42.066416 Set Vref, RX VrefLevel [Byte0]: 38
1027 05:58:42.069245 [Byte1]: 38
1028 05:58:42.073583
1029 05:58:42.074153 Set Vref, RX VrefLevel [Byte0]: 39
1030 05:58:42.077050 [Byte1]: 39
1031 05:58:42.081345
1032 05:58:42.082006 Set Vref, RX VrefLevel [Byte0]: 40
1033 05:58:42.084684 [Byte1]: 40
1034 05:58:42.088815
1035 05:58:42.089274 Set Vref, RX VrefLevel [Byte0]: 41
1036 05:58:42.092481 [Byte1]: 41
1037 05:58:42.097060
1038 05:58:42.097610 Set Vref, RX VrefLevel [Byte0]: 42
1039 05:58:42.103139 [Byte1]: 42
1040 05:58:42.103697
1041 05:58:42.106817 Set Vref, RX VrefLevel [Byte0]: 43
1042 05:58:42.109618 [Byte1]: 43
1043 05:58:42.110077
1044 05:58:42.113080 Set Vref, RX VrefLevel [Byte0]: 44
1045 05:58:42.116166 [Byte1]: 44
1046 05:58:42.116829
1047 05:58:42.119835 Set Vref, RX VrefLevel [Byte0]: 45
1048 05:58:42.123294 [Byte1]: 45
1049 05:58:42.127315
1050 05:58:42.127911 Set Vref, RX VrefLevel [Byte0]: 46
1051 05:58:42.130454 [Byte1]: 46
1052 05:58:42.134960
1053 05:58:42.135420 Set Vref, RX VrefLevel [Byte0]: 47
1054 05:58:42.138129 [Byte1]: 47
1055 05:58:42.142854
1056 05:58:42.143314 Set Vref, RX VrefLevel [Byte0]: 48
1057 05:58:42.146020 [Byte1]: 48
1058 05:58:42.150360
1059 05:58:42.150942 Set Vref, RX VrefLevel [Byte0]: 49
1060 05:58:42.153380 [Byte1]: 49
1061 05:58:42.157978
1062 05:58:42.158443 Set Vref, RX VrefLevel [Byte0]: 50
1063 05:58:42.161115 [Byte1]: 50
1064 05:58:42.165288
1065 05:58:42.168446 Set Vref, RX VrefLevel [Byte0]: 51
1066 05:58:42.172027 [Byte1]: 51
1067 05:58:42.172591
1068 05:58:42.175317 Set Vref, RX VrefLevel [Byte0]: 52
1069 05:58:42.178700 [Byte1]: 52
1070 05:58:42.179165
1071 05:58:42.182006 Set Vref, RX VrefLevel [Byte0]: 53
1072 05:58:42.185319 [Byte1]: 53
1073 05:58:42.188351
1074 05:58:42.188852 Set Vref, RX VrefLevel [Byte0]: 54
1075 05:58:42.191818 [Byte1]: 54
1076 05:58:42.195757
1077 05:58:42.196219 Set Vref, RX VrefLevel [Byte0]: 55
1078 05:58:42.199209 [Byte1]: 55
1079 05:58:42.203712
1080 05:58:42.204423 Set Vref, RX VrefLevel [Byte0]: 56
1081 05:58:42.206751 [Byte1]: 56
1082 05:58:42.211533
1083 05:58:42.212097 Set Vref, RX VrefLevel [Byte0]: 57
1084 05:58:42.214489 [Byte1]: 57
1085 05:58:42.219123
1086 05:58:42.219859 Set Vref, RX VrefLevel [Byte0]: 58
1087 05:58:42.222287 [Byte1]: 58
1088 05:58:42.226822
1089 05:58:42.227393 Set Vref, RX VrefLevel [Byte0]: 59
1090 05:58:42.230068 [Byte1]: 59
1091 05:58:42.234201
1092 05:58:42.234663 Set Vref, RX VrefLevel [Byte0]: 60
1093 05:58:42.238001 [Byte1]: 60
1094 05:58:42.241826
1095 05:58:42.242396 Set Vref, RX VrefLevel [Byte0]: 61
1096 05:58:42.245010 [Byte1]: 61
1097 05:58:42.249459
1098 05:58:42.249871 Set Vref, RX VrefLevel [Byte0]: 62
1099 05:58:42.252253 [Byte1]: 62
1100 05:58:42.256650
1101 05:58:42.256978 Set Vref, RX VrefLevel [Byte0]: 63
1102 05:58:42.260177 [Byte1]: 63
1103 05:58:42.264450
1104 05:58:42.268091 Set Vref, RX VrefLevel [Byte0]: 64
1105 05:58:42.270778 [Byte1]: 64
1106 05:58:42.270972
1107 05:58:42.274479 Set Vref, RX VrefLevel [Byte0]: 65
1108 05:58:42.277762 [Byte1]: 65
1109 05:58:42.278045
1110 05:58:42.280816 Set Vref, RX VrefLevel [Byte0]: 66
1111 05:58:42.284103 [Byte1]: 66
1112 05:58:42.287494
1113 05:58:42.287725 Set Vref, RX VrefLevel [Byte0]: 67
1114 05:58:42.291000 [Byte1]: 67
1115 05:58:42.294929
1116 05:58:42.295120 Set Vref, RX VrefLevel [Byte0]: 68
1117 05:58:42.298567 [Byte1]: 68
1118 05:58:42.302619
1119 05:58:42.302824 Set Vref, RX VrefLevel [Byte0]: 69
1120 05:58:42.306397 [Byte1]: 69
1121 05:58:42.310840
1122 05:58:42.311159 Set Vref, RX VrefLevel [Byte0]: 70
1123 05:58:42.313723 [Byte1]: 70
1124 05:58:42.318009
1125 05:58:42.318418 Set Vref, RX VrefLevel [Byte0]: 71
1126 05:58:42.321337 [Byte1]: 71
1127 05:58:42.326198
1128 05:58:42.326767 Set Vref, RX VrefLevel [Byte0]: 72
1129 05:58:42.329323 [Byte1]: 72
1130 05:58:42.333967
1131 05:58:42.334530 Final RX Vref Byte 0 = 52 to rank0
1132 05:58:42.336783 Final RX Vref Byte 1 = 56 to rank0
1133 05:58:42.340164 Final RX Vref Byte 0 = 52 to rank1
1134 05:58:42.343631 Final RX Vref Byte 1 = 56 to rank1==
1135 05:58:42.347263 Dram Type= 6, Freq= 0, CH_0, rank 0
1136 05:58:42.353711 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1137 05:58:42.354279 ==
1138 05:58:42.354645 DQS Delay:
1139 05:58:42.354982 DQS0 = 0, DQS1 = 0
1140 05:58:42.357126 DQM Delay:
1141 05:58:42.357712 DQM0 = 83, DQM1 = 72
1142 05:58:42.360182 DQ Delay:
1143 05:58:42.363105 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1144 05:58:42.366452 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1145 05:58:42.370176 DQ8 =60, DQ9 =56, DQ10 =76, DQ11 =64
1146 05:58:42.373429 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1147 05:58:42.374064
1148 05:58:42.374569
1149 05:58:42.380010 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f2f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1150 05:58:42.383504 CH0 RK0: MR19=606, MR18=2F2F
1151 05:58:42.390115 CH0_RK0: MR19=0x606, MR18=0x2F2F, DQSOSC=397, MR23=63, INC=93, DEC=62
1152 05:58:42.390439
1153 05:58:42.393154 ----->DramcWriteLeveling(PI) begin...
1154 05:58:42.393544 ==
1155 05:58:42.396288 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 05:58:42.399887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1157 05:58:42.400173 ==
1158 05:58:42.403616 Write leveling (Byte 0): 29 => 29
1159 05:58:42.406723 Write leveling (Byte 1): 29 => 29
1160 05:58:42.409737 DramcWriteLeveling(PI) end<-----
1161 05:58:42.410023
1162 05:58:42.410190 ==
1163 05:58:42.412911 Dram Type= 6, Freq= 0, CH_0, rank 1
1164 05:58:42.416408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1165 05:58:42.416688 ==
1166 05:58:42.419377 [Gating] SW mode calibration
1167 05:58:42.426150 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1168 05:58:42.432603 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1169 05:58:42.436270 0 6 0 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1170 05:58:42.439818 0 6 4 | B1->B0 | 2929 2525 | 0 0 | (0 0) (1 0)
1171 05:58:42.446518 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 05:58:42.449766 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 05:58:42.453368 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 05:58:42.459816 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 05:58:42.462787 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 05:58:42.466265 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 05:58:42.473518 0 7 0 | B1->B0 | 2e2e 3131 | 0 0 | (0 0) (0 0)
1178 05:58:42.476240 0 7 4 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
1179 05:58:42.479911 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1180 05:58:42.486837 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1181 05:58:42.489522 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1182 05:58:42.493116 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 05:58:42.499844 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 05:58:42.503014 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 05:58:42.506968 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 05:58:42.513100 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1187 05:58:42.515992 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1188 05:58:42.519386 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1189 05:58:42.526198 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 05:58:42.529287 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 05:58:42.532924 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 05:58:42.539636 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 05:58:42.543084 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 05:58:42.546515 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 05:58:42.549192 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 05:58:42.556391 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 05:58:42.559650 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 05:58:42.563029 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 05:58:42.569752 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 05:58:42.572965 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 05:58:42.576555 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1202 05:58:42.582612 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 05:58:42.586512 Total UI for P1: 0, mck2ui 16
1204 05:58:42.589347 best dqsien dly found for B0: ( 0, 10, 0)
1205 05:58:42.589778 Total UI for P1: 0, mck2ui 16
1206 05:58:42.596017 best dqsien dly found for B1: ( 0, 10, 2)
1207 05:58:42.599547 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1208 05:58:42.602654 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1209 05:58:42.602984
1210 05:58:42.605964 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1211 05:58:42.609312 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1212 05:58:42.612788 [Gating] SW calibration Done
1213 05:58:42.613219 ==
1214 05:58:42.615741 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 05:58:42.619528 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1216 05:58:42.619971 ==
1217 05:58:42.622552 RX Vref Scan: 0
1218 05:58:42.622878
1219 05:58:42.623132 RX Vref 0 -> 0, step: 1
1220 05:58:42.623374
1221 05:58:42.625743 RX Delay -130 -> 252, step: 16
1222 05:58:42.632530 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1223 05:58:42.636241 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1224 05:58:42.639077 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1225 05:58:42.683537 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1226 05:58:42.684143 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1227 05:58:42.684517 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1228 05:58:42.685252 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1229 05:58:42.685617 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1230 05:58:42.685946 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1231 05:58:42.686263 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1232 05:58:42.686571 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1233 05:58:42.686876 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1234 05:58:42.687176 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1235 05:58:42.687475 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1236 05:58:42.716502 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1237 05:58:42.717162 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1238 05:58:42.717758 ==
1239 05:58:42.718310 Dram Type= 6, Freq= 0, CH_0, rank 1
1240 05:58:42.718674 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1241 05:58:42.719009 ==
1242 05:58:42.719333 DQS Delay:
1243 05:58:42.720014 DQS0 = 0, DQS1 = 0
1244 05:58:42.720377 DQM Delay:
1245 05:58:42.720694 DQM0 = 82, DQM1 = 73
1246 05:58:42.721046 DQ Delay:
1247 05:58:42.721353 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1248 05:58:42.721659 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1249 05:58:42.721960 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69
1250 05:58:42.722319 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1251 05:58:42.722635
1252 05:58:42.722935
1253 05:58:42.723229 ==
1254 05:58:42.723876 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 05:58:42.727289 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1256 05:58:42.727752 ==
1257 05:58:42.728114
1258 05:58:42.728445
1259 05:58:42.730465 TX Vref Scan disable
1260 05:58:42.730921 == TX Byte 0 ==
1261 05:58:42.733821 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1262 05:58:42.740585 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1263 05:58:42.741189 == TX Byte 1 ==
1264 05:58:42.744057 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1265 05:58:42.750385 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1266 05:58:42.750942 ==
1267 05:58:42.753700 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 05:58:42.757024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1269 05:58:42.757599 ==
1270 05:58:42.770710 TX Vref=22, minBit 0, minWin=27, winSum=445
1271 05:58:42.773691 TX Vref=24, minBit 0, minWin=27, winSum=450
1272 05:58:42.776661 TX Vref=26, minBit 2, minWin=28, winSum=457
1273 05:58:42.780114 TX Vref=28, minBit 2, minWin=28, winSum=459
1274 05:58:42.783530 TX Vref=30, minBit 0, minWin=28, winSum=458
1275 05:58:42.786499 TX Vref=32, minBit 2, minWin=28, winSum=458
1276 05:58:42.793356 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 28
1277 05:58:42.793797
1278 05:58:42.797152 Final TX Range 1 Vref 28
1279 05:58:42.797586
1280 05:58:42.797850 ==
1281 05:58:42.799961 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 05:58:42.803494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1283 05:58:42.803830 ==
1284 05:58:42.806598
1285 05:58:42.806934
1286 05:58:42.807134 TX Vref Scan disable
1287 05:58:42.810439 == TX Byte 0 ==
1288 05:58:42.813248 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1289 05:58:42.819777 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1290 05:58:42.820055 == TX Byte 1 ==
1291 05:58:42.823304 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1292 05:58:42.829931 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1293 05:58:42.830185
1294 05:58:42.830377 [DATLAT]
1295 05:58:42.830554 Freq=800, CH0 RK1
1296 05:58:42.830726
1297 05:58:42.833045 DATLAT Default: 0x9
1298 05:58:42.833286 0, 0xFFFF, sum = 0
1299 05:58:42.836438 1, 0xFFFF, sum = 0
1300 05:58:42.836683 2, 0xFFFF, sum = 0
1301 05:58:42.839701 3, 0xFFFF, sum = 0
1302 05:58:42.843240 4, 0xFFFF, sum = 0
1303 05:58:42.843486 5, 0xFFFF, sum = 0
1304 05:58:42.846319 6, 0xFFFF, sum = 0
1305 05:58:42.846662 7, 0xFFFF, sum = 0
1306 05:58:42.850027 8, 0x0, sum = 1
1307 05:58:42.850298 9, 0x0, sum = 2
1308 05:58:42.850494 10, 0x0, sum = 3
1309 05:58:42.853250 11, 0x0, sum = 4
1310 05:58:42.853554 best_step = 9
1311 05:58:42.853790
1312 05:58:42.854010 ==
1313 05:58:42.856949 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 05:58:42.863425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1315 05:58:42.863992 ==
1316 05:58:42.864362 RX Vref Scan: 0
1317 05:58:42.864732
1318 05:58:42.867049 RX Vref 0 -> 0, step: 1
1319 05:58:42.867512
1320 05:58:42.869825 RX Delay -111 -> 252, step: 8
1321 05:58:42.873396 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1322 05:58:42.876939 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1323 05:58:42.883120 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1324 05:58:42.886529 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1325 05:58:42.890109 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1326 05:58:42.893141 iDelay=217, Bit 5, Center 72 (-47 ~ 192) 240
1327 05:58:42.896450 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1328 05:58:42.903446 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1329 05:58:42.906963 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1330 05:58:42.909978 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1331 05:58:42.912965 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1332 05:58:42.916232 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1333 05:58:42.922730 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1334 05:58:42.926323 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1335 05:58:42.929546 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1336 05:58:42.932914 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1337 05:58:42.933232 ==
1338 05:58:42.936476 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 05:58:42.943247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1340 05:58:42.943565 ==
1341 05:58:42.943754 DQS Delay:
1342 05:58:42.943923 DQS0 = 0, DQS1 = 0
1343 05:58:42.945923 DQM Delay:
1344 05:58:42.946146 DQM0 = 85, DQM1 = 74
1345 05:58:42.949578 DQ Delay:
1346 05:58:42.952874 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1347 05:58:42.956054 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =96
1348 05:58:42.959424 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1349 05:58:42.963270 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1350 05:58:42.963648
1351 05:58:42.963940
1352 05:58:42.969998 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1353 05:58:42.973039 CH0 RK1: MR19=606, MR18=3A3A
1354 05:58:42.979955 CH0_RK1: MR19=0x606, MR18=0x3A3A, DQSOSC=395, MR23=63, INC=94, DEC=63
1355 05:58:42.983055 [RxdqsGatingPostProcess] freq 800
1356 05:58:42.986629 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1357 05:58:42.989566 Pre-setting of DQS Precalculation
1358 05:58:42.996471 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1359 05:58:42.997107 ==
1360 05:58:42.999557 Dram Type= 6, Freq= 0, CH_1, rank 0
1361 05:58:43.002758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1362 05:58:43.003261 ==
1363 05:58:43.009954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1364 05:58:43.012619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1365 05:58:43.022616 [CA 0] Center 37 (6~68) winsize 63
1366 05:58:43.025872 [CA 1] Center 37 (6~68) winsize 63
1367 05:58:43.029504 [CA 2] Center 34 (4~65) winsize 62
1368 05:58:43.033023 [CA 3] Center 34 (4~65) winsize 62
1369 05:58:43.036064 [CA 4] Center 33 (3~64) winsize 62
1370 05:58:43.039401 [CA 5] Center 33 (3~64) winsize 62
1371 05:58:43.039765
1372 05:58:43.042581 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1373 05:58:43.042899
1374 05:58:43.045788 [CATrainingPosCal] consider 1 rank data
1375 05:58:43.049355 u2DelayCellTimex100 = 270/100 ps
1376 05:58:43.052650 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1377 05:58:43.055917 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1378 05:58:43.062985 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1379 05:58:43.065660 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1380 05:58:43.069159 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1381 05:58:43.072450 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1382 05:58:43.072910
1383 05:58:43.075868 CA PerBit enable=1, Macro0, CA PI delay=33
1384 05:58:43.076335
1385 05:58:43.079369 [CBTSetCACLKResult] CA Dly = 33
1386 05:58:43.079801 CS Dly: 4 (0~35)
1387 05:58:43.082799 ==
1388 05:58:43.083217 Dram Type= 6, Freq= 0, CH_1, rank 1
1389 05:58:43.089672 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1390 05:58:43.090237 ==
1391 05:58:43.092656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1392 05:58:43.099504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1393 05:58:43.108784 [CA 0] Center 36 (6~67) winsize 62
1394 05:58:43.112484 [CA 1] Center 37 (6~68) winsize 63
1395 05:58:43.115363 [CA 2] Center 34 (4~65) winsize 62
1396 05:58:43.118797 [CA 3] Center 34 (4~65) winsize 62
1397 05:58:43.122488 [CA 4] Center 33 (3~64) winsize 62
1398 05:58:43.125389 [CA 5] Center 33 (3~64) winsize 62
1399 05:58:43.125856
1400 05:58:43.128753 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1401 05:58:43.129214
1402 05:58:43.132322 [CATrainingPosCal] consider 2 rank data
1403 05:58:43.135350 u2DelayCellTimex100 = 270/100 ps
1404 05:58:43.139080 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1405 05:58:43.142112 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1406 05:58:43.149012 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1407 05:58:43.152224 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1408 05:58:43.155798 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1409 05:58:43.158973 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1410 05:58:43.159546
1411 05:58:43.162123 CA PerBit enable=1, Macro0, CA PI delay=33
1412 05:58:43.162690
1413 05:58:43.165366 [CBTSetCACLKResult] CA Dly = 33
1414 05:58:43.165894 CS Dly: 4 (0~36)
1415 05:58:43.166261
1416 05:58:43.168983 ----->DramcWriteLeveling(PI) begin...
1417 05:58:43.169449 ==
1418 05:58:43.171980 Dram Type= 6, Freq= 0, CH_1, rank 0
1419 05:58:43.178991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1420 05:58:43.179687 ==
1421 05:58:43.182254 Write leveling (Byte 0): 24 => 24
1422 05:58:43.185716 Write leveling (Byte 1): 26 => 26
1423 05:58:43.186172 DramcWriteLeveling(PI) end<-----
1424 05:58:43.188792
1425 05:58:43.189393 ==
1426 05:58:43.192409 Dram Type= 6, Freq= 0, CH_1, rank 0
1427 05:58:43.195381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1428 05:58:43.196073 ==
1429 05:58:43.198784 [Gating] SW mode calibration
1430 05:58:43.205267 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1431 05:58:43.208861 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1432 05:58:43.215426 0 6 0 | B1->B0 | 3030 2525 | 0 0 | (1 1) (1 0)
1433 05:58:43.218830 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1434 05:58:43.222230 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1435 05:58:43.229171 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1436 05:58:43.232221 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1437 05:58:43.235340 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1438 05:58:43.242321 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 05:58:43.245888 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 05:58:43.248687 0 7 0 | B1->B0 | 2c2c 3d3d | 0 0 | (0 0) (0 0)
1441 05:58:43.255830 0 7 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1442 05:58:43.259007 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1443 05:58:43.262222 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1444 05:58:43.269025 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1445 05:58:43.272078 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1446 05:58:43.275538 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1447 05:58:43.279236 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 05:58:43.285617 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1449 05:58:43.288935 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1450 05:58:43.291920 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1451 05:58:43.298862 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1452 05:58:43.301845 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1453 05:58:43.305214 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 05:58:43.312189 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 05:58:43.315542 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 05:58:43.318515 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 05:58:43.325550 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 05:58:43.328321 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 05:58:43.331822 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 05:58:43.338736 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 05:58:43.341613 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 05:58:43.345501 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 05:58:43.351869 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1464 05:58:43.355262 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1465 05:58:43.358511 Total UI for P1: 0, mck2ui 16
1466 05:58:43.362194 best dqsien dly found for B0: ( 0, 9, 28)
1467 05:58:43.365023 Total UI for P1: 0, mck2ui 16
1468 05:58:43.369281 best dqsien dly found for B1: ( 0, 9, 30)
1469 05:58:43.372426 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1470 05:58:43.375568 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1471 05:58:43.376077
1472 05:58:43.378639 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1473 05:58:43.382433 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1474 05:58:43.385525 [Gating] SW calibration Done
1475 05:58:43.386091 ==
1476 05:58:43.388873 Dram Type= 6, Freq= 0, CH_1, rank 0
1477 05:58:43.392287 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1478 05:58:43.392800 ==
1479 05:58:43.395549 RX Vref Scan: 0
1480 05:58:43.396112
1481 05:58:43.398888 RX Vref 0 -> 0, step: 1
1482 05:58:43.399454
1483 05:58:43.402281 RX Delay -130 -> 252, step: 16
1484 05:58:43.405554 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1485 05:58:43.408878 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1486 05:58:43.412119 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1487 05:58:43.415231 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1488 05:58:43.421955 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1489 05:58:43.424961 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1490 05:58:43.428440 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1491 05:58:43.432134 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1492 05:58:43.435074 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1493 05:58:43.441428 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1494 05:58:43.444773 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1495 05:58:43.448234 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1496 05:58:43.451726 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1497 05:58:43.454648 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1498 05:58:43.461789 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1499 05:58:43.464693 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1500 05:58:43.465203 ==
1501 05:58:43.468235 Dram Type= 6, Freq= 0, CH_1, rank 0
1502 05:58:43.471444 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1503 05:58:43.471909 ==
1504 05:58:43.474955 DQS Delay:
1505 05:58:43.475412 DQS0 = 0, DQS1 = 0
1506 05:58:43.475770 DQM Delay:
1507 05:58:43.478114 DQM0 = 84, DQM1 = 75
1508 05:58:43.478573 DQ Delay:
1509 05:58:43.481553 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1510 05:58:43.484866 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =85
1511 05:58:43.488533 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1512 05:58:43.491654 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1513 05:58:43.492152
1514 05:58:43.492516
1515 05:58:43.492910 ==
1516 05:58:43.495202 Dram Type= 6, Freq= 0, CH_1, rank 0
1517 05:58:43.498585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1518 05:58:43.501789 ==
1519 05:58:43.502349
1520 05:58:43.502710
1521 05:58:43.503044 TX Vref Scan disable
1522 05:58:43.505060 == TX Byte 0 ==
1523 05:58:43.508665 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1524 05:58:43.511848 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1525 05:58:43.515312 == TX Byte 1 ==
1526 05:58:43.518187 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1527 05:58:43.521372 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1528 05:58:43.525155 ==
1529 05:58:43.528063 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 05:58:43.531746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1531 05:58:43.532323 ==
1532 05:58:43.544407 TX Vref=22, minBit 3, minWin=27, winSum=445
1533 05:58:43.547775 TX Vref=24, minBit 3, minWin=27, winSum=451
1534 05:58:43.551006 TX Vref=26, minBit 3, minWin=27, winSum=450
1535 05:58:43.554085 TX Vref=28, minBit 0, minWin=28, winSum=454
1536 05:58:43.557178 TX Vref=30, minBit 3, minWin=28, winSum=460
1537 05:58:43.560930 TX Vref=32, minBit 0, minWin=28, winSum=456
1538 05:58:43.567337 [TxChooseVref] Worse bit 3, Min win 28, Win sum 460, Final Vref 30
1539 05:58:43.567809
1540 05:58:43.570422 Final TX Range 1 Vref 30
1541 05:58:43.570918
1542 05:58:43.571282 ==
1543 05:58:43.573919 Dram Type= 6, Freq= 0, CH_1, rank 0
1544 05:58:43.577108 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1545 05:58:43.577573 ==
1546 05:58:43.577935
1547 05:58:43.580502
1548 05:58:43.580997 TX Vref Scan disable
1549 05:58:43.583822 == TX Byte 0 ==
1550 05:58:43.587477 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1551 05:58:43.593717 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1552 05:58:43.594039 == TX Byte 1 ==
1553 05:58:43.597319 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1554 05:58:43.603938 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1555 05:58:43.604368
1556 05:58:43.604748 [DATLAT]
1557 05:58:43.605005 Freq=800, CH1 RK0
1558 05:58:43.605285
1559 05:58:43.607569 DATLAT Default: 0xa
1560 05:58:43.607991 0, 0xFFFF, sum = 0
1561 05:58:43.610682 1, 0xFFFF, sum = 0
1562 05:58:43.611137 2, 0xFFFF, sum = 0
1563 05:58:43.613844 3, 0xFFFF, sum = 0
1564 05:58:43.617111 4, 0xFFFF, sum = 0
1565 05:58:43.617535 5, 0xFFFF, sum = 0
1566 05:58:43.620315 6, 0xFFFF, sum = 0
1567 05:58:43.620643 7, 0xFFFF, sum = 0
1568 05:58:43.620947 8, 0x0, sum = 1
1569 05:58:43.624125 9, 0x0, sum = 2
1570 05:58:43.624549 10, 0x0, sum = 3
1571 05:58:43.627556 11, 0x0, sum = 4
1572 05:58:43.627988 best_step = 9
1573 05:58:43.628259
1574 05:58:43.628494 ==
1575 05:58:43.630823 Dram Type= 6, Freq= 0, CH_1, rank 0
1576 05:58:43.637077 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1577 05:58:43.637402 ==
1578 05:58:43.637668 RX Vref Scan: 1
1579 05:58:43.638042
1580 05:58:43.640315 Set Vref Range= 32 -> 127
1581 05:58:43.640636
1582 05:58:43.643867 RX Vref 32 -> 127, step: 1
1583 05:58:43.644309
1584 05:58:43.647482 RX Delay -111 -> 252, step: 8
1585 05:58:43.647804
1586 05:58:43.650261 Set Vref, RX VrefLevel [Byte0]: 32
1587 05:58:43.650632 [Byte1]: 32
1588 05:58:43.655003
1589 05:58:43.655454 Set Vref, RX VrefLevel [Byte0]: 33
1590 05:58:43.658074 [Byte1]: 33
1591 05:58:43.662862
1592 05:58:43.663409 Set Vref, RX VrefLevel [Byte0]: 34
1593 05:58:43.665888 [Byte1]: 34
1594 05:58:43.669950
1595 05:58:43.670267 Set Vref, RX VrefLevel [Byte0]: 35
1596 05:58:43.673320 [Byte1]: 35
1597 05:58:43.677652
1598 05:58:43.677972 Set Vref, RX VrefLevel [Byte0]: 36
1599 05:58:43.681144 [Byte1]: 36
1600 05:58:43.685334
1601 05:58:43.685653 Set Vref, RX VrefLevel [Byte0]: 37
1602 05:58:43.688754 [Byte1]: 37
1603 05:58:43.693291
1604 05:58:43.693862 Set Vref, RX VrefLevel [Byte0]: 38
1605 05:58:43.696672 [Byte1]: 38
1606 05:58:43.700450
1607 05:58:43.700904 Set Vref, RX VrefLevel [Byte0]: 39
1608 05:58:43.703918 [Byte1]: 39
1609 05:58:43.708223
1610 05:58:43.708673 Set Vref, RX VrefLevel [Byte0]: 40
1611 05:58:43.711463 [Byte1]: 40
1612 05:58:43.715934
1613 05:58:43.716346 Set Vref, RX VrefLevel [Byte0]: 41
1614 05:58:43.719130 [Byte1]: 41
1615 05:58:43.723696
1616 05:58:43.724110 Set Vref, RX VrefLevel [Byte0]: 42
1617 05:58:43.726879 [Byte1]: 42
1618 05:58:43.731634
1619 05:58:43.732152 Set Vref, RX VrefLevel [Byte0]: 43
1620 05:58:43.734478 [Byte1]: 43
1621 05:58:43.738865
1622 05:58:43.739294 Set Vref, RX VrefLevel [Byte0]: 44
1623 05:58:43.742528 [Byte1]: 44
1624 05:58:43.746460
1625 05:58:43.746873 Set Vref, RX VrefLevel [Byte0]: 45
1626 05:58:43.750227 [Byte1]: 45
1627 05:58:43.754498
1628 05:58:43.755059 Set Vref, RX VrefLevel [Byte0]: 46
1629 05:58:43.757808 [Byte1]: 46
1630 05:58:43.761905
1631 05:58:43.762318 Set Vref, RX VrefLevel [Byte0]: 47
1632 05:58:43.765259 [Byte1]: 47
1633 05:58:43.769600
1634 05:58:43.770127 Set Vref, RX VrefLevel [Byte0]: 48
1635 05:58:43.772747 [Byte1]: 48
1636 05:58:43.777625
1637 05:58:43.778038 Set Vref, RX VrefLevel [Byte0]: 49
1638 05:58:43.780520 [Byte1]: 49
1639 05:58:43.785159
1640 05:58:43.785678 Set Vref, RX VrefLevel [Byte0]: 50
1641 05:58:43.788389 [Byte1]: 50
1642 05:58:43.792372
1643 05:58:43.792819 Set Vref, RX VrefLevel [Byte0]: 51
1644 05:58:43.796025 [Byte1]: 51
1645 05:58:43.800409
1646 05:58:43.800980 Set Vref, RX VrefLevel [Byte0]: 52
1647 05:58:43.803565 [Byte1]: 52
1648 05:58:43.808136
1649 05:58:43.808761 Set Vref, RX VrefLevel [Byte0]: 53
1650 05:58:43.810963 [Byte1]: 53
1651 05:58:43.815942
1652 05:58:43.816477 Set Vref, RX VrefLevel [Byte0]: 54
1653 05:58:43.818946 [Byte1]: 54
1654 05:58:43.823247
1655 05:58:43.823659 Set Vref, RX VrefLevel [Byte0]: 55
1656 05:58:43.826327 [Byte1]: 55
1657 05:58:43.830947
1658 05:58:43.831369 Set Vref, RX VrefLevel [Byte0]: 56
1659 05:58:43.834065 [Byte1]: 56
1660 05:58:43.838220
1661 05:58:43.838635 Set Vref, RX VrefLevel [Byte0]: 57
1662 05:58:43.841576 [Byte1]: 57
1663 05:58:43.845727
1664 05:58:43.846143 Set Vref, RX VrefLevel [Byte0]: 58
1665 05:58:43.849199 [Byte1]: 58
1666 05:58:43.853643
1667 05:58:43.854054 Set Vref, RX VrefLevel [Byte0]: 59
1668 05:58:43.856956 [Byte1]: 59
1669 05:58:43.861547
1670 05:58:43.861886 Set Vref, RX VrefLevel [Byte0]: 60
1671 05:58:43.864676 [Byte1]: 60
1672 05:58:43.869154
1673 05:58:43.869545 Set Vref, RX VrefLevel [Byte0]: 61
1674 05:58:43.872272 [Byte1]: 61
1675 05:58:43.876634
1676 05:58:43.877140 Set Vref, RX VrefLevel [Byte0]: 62
1677 05:58:43.880008 [Byte1]: 62
1678 05:58:43.883905
1679 05:58:43.884300 Set Vref, RX VrefLevel [Byte0]: 63
1680 05:58:43.887923 [Byte1]: 63
1681 05:58:43.891786
1682 05:58:43.892199 Set Vref, RX VrefLevel [Byte0]: 64
1683 05:58:43.895573 [Byte1]: 64
1684 05:58:43.900139
1685 05:58:43.900743 Set Vref, RX VrefLevel [Byte0]: 65
1686 05:58:43.902782 [Byte1]: 65
1687 05:58:43.907413
1688 05:58:43.907872 Set Vref, RX VrefLevel [Byte0]: 66
1689 05:58:43.910418 [Byte1]: 66
1690 05:58:43.914925
1691 05:58:43.915475 Set Vref, RX VrefLevel [Byte0]: 67
1692 05:58:43.918248 [Byte1]: 67
1693 05:58:43.922956
1694 05:58:43.923509 Set Vref, RX VrefLevel [Byte0]: 68
1695 05:58:43.926113 [Byte1]: 68
1696 05:58:43.930134
1697 05:58:43.930691 Set Vref, RX VrefLevel [Byte0]: 69
1698 05:58:43.933680 [Byte1]: 69
1699 05:58:43.938162
1700 05:58:43.938623 Set Vref, RX VrefLevel [Byte0]: 70
1701 05:58:43.941111 [Byte1]: 70
1702 05:58:43.945447
1703 05:58:43.946003 Set Vref, RX VrefLevel [Byte0]: 71
1704 05:58:43.948655 [Byte1]: 71
1705 05:58:43.953187
1706 05:58:43.953648 Set Vref, RX VrefLevel [Byte0]: 72
1707 05:58:43.956539 [Byte1]: 72
1708 05:58:43.960858
1709 05:58:43.961407 Set Vref, RX VrefLevel [Byte0]: 73
1710 05:58:43.964269 [Byte1]: 73
1711 05:58:43.968213
1712 05:58:43.968908 Set Vref, RX VrefLevel [Byte0]: 74
1713 05:58:43.971650 [Byte1]: 74
1714 05:58:43.976031
1715 05:58:43.976488 Set Vref, RX VrefLevel [Byte0]: 75
1716 05:58:43.979296 [Byte1]: 75
1717 05:58:43.983798
1718 05:58:43.984381 Set Vref, RX VrefLevel [Byte0]: 76
1719 05:58:43.986724 [Byte1]: 76
1720 05:58:43.991357
1721 05:58:43.991815 Final RX Vref Byte 0 = 58 to rank0
1722 05:58:43.994479 Final RX Vref Byte 1 = 53 to rank0
1723 05:58:43.998162 Final RX Vref Byte 0 = 58 to rank1
1724 05:58:44.001471 Final RX Vref Byte 1 = 53 to rank1==
1725 05:58:44.004489 Dram Type= 6, Freq= 0, CH_1, rank 0
1726 05:58:44.011351 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1727 05:58:44.011781 ==
1728 05:58:44.012064 DQS Delay:
1729 05:58:44.012339 DQS0 = 0, DQS1 = 0
1730 05:58:44.014377 DQM Delay:
1731 05:58:44.014700 DQM0 = 81, DQM1 = 75
1732 05:58:44.017840 DQ Delay:
1733 05:58:44.021627 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1734 05:58:44.021949 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1735 05:58:44.024600 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1736 05:58:44.027908 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1737 05:58:44.031400
1738 05:58:44.031913
1739 05:58:44.038250 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e4e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1740 05:58:44.041381 CH1 RK0: MR19=606, MR18=4E4E
1741 05:58:44.048039 CH1_RK0: MR19=0x606, MR18=0x4E4E, DQSOSC=390, MR23=63, INC=97, DEC=64
1742 05:58:44.048582
1743 05:58:44.051421 ----->DramcWriteLeveling(PI) begin...
1744 05:58:44.051843 ==
1745 05:58:44.054906 Dram Type= 6, Freq= 0, CH_1, rank 1
1746 05:58:44.058141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1747 05:58:44.058672 ==
1748 05:58:44.061824 Write leveling (Byte 0): 26 => 26
1749 05:58:44.064811 Write leveling (Byte 1): 26 => 26
1750 05:58:44.068323 DramcWriteLeveling(PI) end<-----
1751 05:58:44.068784
1752 05:58:44.069122 ==
1753 05:58:44.071204 Dram Type= 6, Freq= 0, CH_1, rank 1
1754 05:58:44.074547 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1755 05:58:44.074975 ==
1756 05:58:44.077734 [Gating] SW mode calibration
1757 05:58:44.084254 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1758 05:58:44.091729 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1759 05:58:44.094286 0 6 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
1760 05:58:44.097861 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1761 05:58:44.104154 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1762 05:58:44.107331 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1763 05:58:44.110534 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1764 05:58:44.116942 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1765 05:58:44.120423 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1766 05:58:44.123589 0 6 28 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
1767 05:58:44.130794 0 7 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1768 05:58:44.134429 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1769 05:58:44.137147 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1770 05:58:44.143714 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1771 05:58:44.146734 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1772 05:58:44.150517 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1773 05:58:44.157329 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1774 05:58:44.160412 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1775 05:58:44.163842 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1776 05:58:44.170322 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1777 05:58:44.173608 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1778 05:58:44.176984 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1779 05:58:44.183748 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1780 05:58:44.187245 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 05:58:44.190445 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 05:58:44.197167 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 05:58:44.200496 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 05:58:44.203721 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 05:58:44.210460 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 05:58:44.213563 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 05:58:44.217063 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 05:58:44.224095 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 05:58:44.227244 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 05:58:44.230399 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1791 05:58:44.233923 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1792 05:58:44.237062 Total UI for P1: 0, mck2ui 16
1793 05:58:44.240250 best dqsien dly found for B0: ( 0, 9, 28)
1794 05:58:44.246844 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1795 05:58:44.250526 Total UI for P1: 0, mck2ui 16
1796 05:58:44.253691 best dqsien dly found for B1: ( 0, 9, 30)
1797 05:58:44.256858 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1798 05:58:44.260612 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1799 05:58:44.261227
1800 05:58:44.264278 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1801 05:58:44.267263 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1802 05:58:44.270354 [Gating] SW calibration Done
1803 05:58:44.270815 ==
1804 05:58:44.273893 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 05:58:44.277081 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1806 05:58:44.277656 ==
1807 05:58:44.280404 RX Vref Scan: 0
1808 05:58:44.280899
1809 05:58:44.283629 RX Vref 0 -> 0, step: 1
1810 05:58:44.284087
1811 05:58:44.284443 RX Delay -130 -> 252, step: 16
1812 05:58:44.290416 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1813 05:58:44.293417 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1814 05:58:44.296894 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1815 05:58:44.300510 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1816 05:58:44.303429 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1817 05:58:44.310750 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1818 05:58:44.313491 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1819 05:58:44.317100 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1820 05:58:44.320293 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1821 05:58:44.323971 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1822 05:58:44.330211 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1823 05:58:44.333480 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1824 05:58:44.337115 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1825 05:58:44.339938 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1826 05:58:44.343142 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1827 05:58:44.349856 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1828 05:58:44.350320 ==
1829 05:58:44.353092 Dram Type= 6, Freq= 0, CH_1, rank 1
1830 05:58:44.356635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1831 05:58:44.357147 ==
1832 05:58:44.357513 DQS Delay:
1833 05:58:44.359803 DQS0 = 0, DQS1 = 0
1834 05:58:44.360261 DQM Delay:
1835 05:58:44.363162 DQM0 = 86, DQM1 = 76
1836 05:58:44.363623 DQ Delay:
1837 05:58:44.366590 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1838 05:58:44.369812 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1839 05:58:44.373268 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1840 05:58:44.377211 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1841 05:58:44.377775
1842 05:58:44.378220
1843 05:58:44.378595 ==
1844 05:58:44.379883 Dram Type= 6, Freq= 0, CH_1, rank 1
1845 05:58:44.382973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1846 05:58:44.386273 ==
1847 05:58:44.386737
1848 05:58:44.387146
1849 05:58:44.387618 TX Vref Scan disable
1850 05:58:44.389754 == TX Byte 0 ==
1851 05:58:44.393352 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1852 05:58:44.396467 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1853 05:58:44.399886 == TX Byte 1 ==
1854 05:58:44.402955 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1855 05:58:44.406255 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1856 05:58:44.409883 ==
1857 05:58:44.412838 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 05:58:44.416527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1859 05:58:44.417090 ==
1860 05:58:44.428465 TX Vref=22, minBit 0, minWin=27, winSum=448
1861 05:58:44.431493 TX Vref=24, minBit 8, minWin=27, winSum=451
1862 05:58:44.434995 TX Vref=26, minBit 9, minWin=27, winSum=454
1863 05:58:44.437935 TX Vref=28, minBit 0, minWin=28, winSum=455
1864 05:58:44.441782 TX Vref=30, minBit 9, minWin=27, winSum=457
1865 05:58:44.448145 TX Vref=32, minBit 9, minWin=27, winSum=452
1866 05:58:44.451247 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 28
1867 05:58:44.451711
1868 05:58:44.454842 Final TX Range 1 Vref 28
1869 05:58:44.455325
1870 05:58:44.455684 ==
1871 05:58:44.458016 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 05:58:44.461389 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1873 05:58:44.464820 ==
1874 05:58:44.465276
1875 05:58:44.465632
1876 05:58:44.465962 TX Vref Scan disable
1877 05:58:44.468180 == TX Byte 0 ==
1878 05:58:44.471681 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1879 05:58:44.475053 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1880 05:58:44.478438 == TX Byte 1 ==
1881 05:58:44.481755 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1882 05:58:44.488649 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1883 05:58:44.489262
1884 05:58:44.489623 [DATLAT]
1885 05:58:44.489962 Freq=800, CH1 RK1
1886 05:58:44.490288
1887 05:58:44.491295 DATLAT Default: 0x9
1888 05:58:44.491671 0, 0xFFFF, sum = 0
1889 05:58:44.494759 1, 0xFFFF, sum = 0
1890 05:58:44.495312 2, 0xFFFF, sum = 0
1891 05:58:44.497992 3, 0xFFFF, sum = 0
1892 05:58:44.501742 4, 0xFFFF, sum = 0
1893 05:58:44.502302 5, 0xFFFF, sum = 0
1894 05:58:44.504947 6, 0xFFFF, sum = 0
1895 05:58:44.505410 7, 0xFFFF, sum = 0
1896 05:58:44.505775 8, 0x0, sum = 1
1897 05:58:44.508469 9, 0x0, sum = 2
1898 05:58:44.509070 10, 0x0, sum = 3
1899 05:58:44.511238 11, 0x0, sum = 4
1900 05:58:44.511699 best_step = 9
1901 05:58:44.512055
1902 05:58:44.512388 ==
1903 05:58:44.514854 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 05:58:44.521651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1905 05:58:44.522109 ==
1906 05:58:44.522473 RX Vref Scan: 0
1907 05:58:44.522811
1908 05:58:44.524857 RX Vref 0 -> 0, step: 1
1909 05:58:44.525385
1910 05:58:44.528038 RX Delay -95 -> 252, step: 8
1911 05:58:44.531634 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1912 05:58:44.534741 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
1913 05:58:44.541492 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1914 05:58:44.545016 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1915 05:58:44.548242 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1916 05:58:44.551598 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1917 05:58:44.554795 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1918 05:58:44.558447 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
1919 05:58:44.564883 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1920 05:58:44.568466 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1921 05:58:44.571527 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1922 05:58:44.574871 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1923 05:58:44.578265 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1924 05:58:44.585085 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1925 05:58:44.588483 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1926 05:58:44.591341 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1927 05:58:44.591804 ==
1928 05:58:44.594770 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 05:58:44.598189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1930 05:58:44.601365 ==
1931 05:58:44.601821 DQS Delay:
1932 05:58:44.602179 DQS0 = 0, DQS1 = 0
1933 05:58:44.605035 DQM Delay:
1934 05:58:44.605586 DQM0 = 85, DQM1 = 74
1935 05:58:44.608267 DQ Delay:
1936 05:58:44.608863 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84
1937 05:58:44.611832 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
1938 05:58:44.615035 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =68
1939 05:58:44.618365 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1940 05:58:44.618920
1941 05:58:44.621667
1942 05:58:44.628041 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1943 05:58:44.631287 CH1 RK1: MR19=606, MR18=3A3A
1944 05:58:44.638216 CH1_RK1: MR19=0x606, MR18=0x3A3A, DQSOSC=395, MR23=63, INC=94, DEC=63
1945 05:58:44.641670 [RxdqsGatingPostProcess] freq 800
1946 05:58:44.644491 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1947 05:58:44.647823 Pre-setting of DQS Precalculation
1948 05:58:44.651272 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1949 05:58:44.661182 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1950 05:58:44.668137 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1951 05:58:44.668603
1952 05:58:44.669013
1953 05:58:44.671504 [Calibration Summary] 1600 Mbps
1954 05:58:44.672063 CH 0, Rank 0
1955 05:58:44.674940 SW Impedance : PASS
1956 05:58:44.675403 DUTY Scan : NO K
1957 05:58:44.677767 ZQ Calibration : PASS
1958 05:58:44.681056 Jitter Meter : NO K
1959 05:58:44.681588 CBT Training : PASS
1960 05:58:44.684487 Write leveling : PASS
1961 05:58:44.687836 RX DQS gating : PASS
1962 05:58:44.688294 RX DQ/DQS(RDDQC) : PASS
1963 05:58:44.691464 TX DQ/DQS : PASS
1964 05:58:44.694474 RX DATLAT : PASS
1965 05:58:44.694935 RX DQ/DQS(Engine): PASS
1966 05:58:44.697909 TX OE : NO K
1967 05:58:44.698369 All Pass.
1968 05:58:44.698849
1969 05:58:44.701659 CH 0, Rank 1
1970 05:58:44.702116 SW Impedance : PASS
1971 05:58:44.704461 DUTY Scan : NO K
1972 05:58:44.708245 ZQ Calibration : PASS
1973 05:58:44.708733 Jitter Meter : NO K
1974 05:58:44.711125 CBT Training : PASS
1975 05:58:44.711537 Write leveling : PASS
1976 05:58:44.714637 RX DQS gating : PASS
1977 05:58:44.717795 RX DQ/DQS(RDDQC) : PASS
1978 05:58:44.718091 TX DQ/DQS : PASS
1979 05:58:44.721025 RX DATLAT : PASS
1980 05:58:44.724356 RX DQ/DQS(Engine): PASS
1981 05:58:44.724535 TX OE : NO K
1982 05:58:44.727678 All Pass.
1983 05:58:44.727941
1984 05:58:44.728090 CH 1, Rank 0
1985 05:58:44.730702 SW Impedance : PASS
1986 05:58:44.730855 DUTY Scan : NO K
1987 05:58:44.734389 ZQ Calibration : PASS
1988 05:58:44.737968 Jitter Meter : NO K
1989 05:58:44.738199 CBT Training : PASS
1990 05:58:44.740739 Write leveling : PASS
1991 05:58:44.744519 RX DQS gating : PASS
1992 05:58:44.744679 RX DQ/DQS(RDDQC) : PASS
1993 05:58:44.747795 TX DQ/DQS : PASS
1994 05:58:44.750718 RX DATLAT : PASS
1995 05:58:44.750917 RX DQ/DQS(Engine): PASS
1996 05:58:44.754539 TX OE : NO K
1997 05:58:44.754776 All Pass.
1998 05:58:44.754915
1999 05:58:44.757366 CH 1, Rank 1
2000 05:58:44.757531 SW Impedance : PASS
2001 05:58:44.760598 DUTY Scan : NO K
2002 05:58:44.760761 ZQ Calibration : PASS
2003 05:58:44.763994 Jitter Meter : NO K
2004 05:58:44.767459 CBT Training : PASS
2005 05:58:44.767609 Write leveling : PASS
2006 05:58:44.770669 RX DQS gating : PASS
2007 05:58:44.774284 RX DQ/DQS(RDDQC) : PASS
2008 05:58:44.774465 TX DQ/DQS : PASS
2009 05:58:44.777550 RX DATLAT : PASS
2010 05:58:44.780782 RX DQ/DQS(Engine): PASS
2011 05:58:44.780954 TX OE : NO K
2012 05:58:44.783942 All Pass.
2013 05:58:44.784176
2014 05:58:44.784319 DramC Write-DBI off
2015 05:58:44.787264 PER_BANK_REFRESH: Hybrid Mode
2016 05:58:44.787437 TX_TRACKING: ON
2017 05:58:44.790880 [GetDramInforAfterCalByMRR] Vendor 6.
2018 05:58:44.797469 [GetDramInforAfterCalByMRR] Revision 606.
2019 05:58:44.801105 [GetDramInforAfterCalByMRR] Revision 2 0.
2020 05:58:44.801442 MR0 0x3939
2021 05:58:44.801650 MR8 0x1111
2022 05:58:44.803975 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2023 05:58:44.807639
2024 05:58:44.807931 MR0 0x3939
2025 05:58:44.808162 MR8 0x1111
2026 05:58:44.810827 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2027 05:58:44.811207
2028 05:58:44.821441 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2029 05:58:44.824426 [FAST_K] Save calibration result to emmc
2030 05:58:44.828214 [FAST_K] Save calibration result to emmc
2031 05:58:44.830501 dram_init: config_dvfs: 1
2032 05:58:44.834080 dramc_set_vcore_voltage set vcore to 662500
2033 05:58:44.837652 Read voltage for 1200, 2
2034 05:58:44.838209 Vio18 = 0
2035 05:58:44.838566 Vcore = 662500
2036 05:58:44.841040 Vdram = 0
2037 05:58:44.841499 Vddq = 0
2038 05:58:44.841858 Vmddr = 0
2039 05:58:44.847615 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2040 05:58:44.850737 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2041 05:58:44.853958 MEM_TYPE=3, freq_sel=15
2042 05:58:44.857595 sv_algorithm_assistance_LP4_1600
2043 05:58:44.860801 ============ PULL DRAM RESETB DOWN ============
2044 05:58:44.864335 ========== PULL DRAM RESETB DOWN end =========
2045 05:58:44.870632 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2046 05:58:44.873993 ===================================
2047 05:58:44.877626 LPDDR4 DRAM CONFIGURATION
2048 05:58:44.880975 ===================================
2049 05:58:44.881529 EX_ROW_EN[0] = 0x0
2050 05:58:44.883933 EX_ROW_EN[1] = 0x0
2051 05:58:44.884482 LP4Y_EN = 0x0
2052 05:58:44.887583 WORK_FSP = 0x0
2053 05:58:44.888149 WL = 0x4
2054 05:58:44.890811 RL = 0x4
2055 05:58:44.891359 BL = 0x2
2056 05:58:44.894066 RPST = 0x0
2057 05:58:44.894522 RD_PRE = 0x0
2058 05:58:44.897133 WR_PRE = 0x1
2059 05:58:44.897590 WR_PST = 0x0
2060 05:58:44.900822 DBI_WR = 0x0
2061 05:58:44.901281 DBI_RD = 0x0
2062 05:58:44.903783 OTF = 0x1
2063 05:58:44.907781 ===================================
2064 05:58:44.910461 ===================================
2065 05:58:44.911100 ANA top config
2066 05:58:44.913856 ===================================
2067 05:58:44.917152 DLL_ASYNC_EN = 0
2068 05:58:44.920545 ALL_SLAVE_EN = 0
2069 05:58:44.923849 NEW_RANK_MODE = 1
2070 05:58:44.924508 DLL_IDLE_MODE = 1
2071 05:58:44.927490 LP45_APHY_COMB_EN = 1
2072 05:58:44.930415 TX_ODT_DIS = 1
2073 05:58:44.933921 NEW_8X_MODE = 1
2074 05:58:44.937188 ===================================
2075 05:58:44.940339 ===================================
2076 05:58:44.943850 data_rate = 2400
2077 05:58:44.944363 CKR = 1
2078 05:58:44.947006 DQ_P2S_RATIO = 8
2079 05:58:44.950611 ===================================
2080 05:58:44.954145 CA_P2S_RATIO = 8
2081 05:58:44.957051 DQ_CA_OPEN = 0
2082 05:58:44.960583 DQ_SEMI_OPEN = 0
2083 05:58:44.963897 CA_SEMI_OPEN = 0
2084 05:58:44.964364 CA_FULL_RATE = 0
2085 05:58:44.967208 DQ_CKDIV4_EN = 0
2086 05:58:44.971009 CA_CKDIV4_EN = 0
2087 05:58:44.973975 CA_PREDIV_EN = 0
2088 05:58:44.976971 PH8_DLY = 17
2089 05:58:44.980620 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2090 05:58:44.981234 DQ_AAMCK_DIV = 4
2091 05:58:44.984467 CA_AAMCK_DIV = 4
2092 05:58:44.986975 CA_ADMCK_DIV = 4
2093 05:58:44.990666 DQ_TRACK_CA_EN = 0
2094 05:58:44.993820 CA_PICK = 1200
2095 05:58:44.997302 CA_MCKIO = 1200
2096 05:58:44.997866 MCKIO_SEMI = 0
2097 05:58:45.001098 PLL_FREQ = 2366
2098 05:58:45.003640 DQ_UI_PI_RATIO = 32
2099 05:58:45.007148 CA_UI_PI_RATIO = 0
2100 05:58:45.010518 ===================================
2101 05:58:45.013563 ===================================
2102 05:58:45.017072 memory_type:LPDDR4
2103 05:58:45.017629 GP_NUM : 10
2104 05:58:45.020272 SRAM_EN : 1
2105 05:58:45.023468 MD32_EN : 0
2106 05:58:45.026825 ===================================
2107 05:58:45.027286 [ANA_INIT] >>>>>>>>>>>>>>
2108 05:58:45.030202 <<<<<< [CONFIGURE PHASE]: ANA_TX
2109 05:58:45.033542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2110 05:58:45.037109 ===================================
2111 05:58:45.040295 data_rate = 2400,PCW = 0X5b00
2112 05:58:45.043943 ===================================
2113 05:58:45.047005 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2114 05:58:45.053466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2115 05:58:45.056664 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2116 05:58:45.063423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2117 05:58:45.067000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2118 05:58:45.070682 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2119 05:58:45.071263 [ANA_INIT] flow start
2120 05:58:45.073364 [ANA_INIT] PLL >>>>>>>>
2121 05:58:45.076741 [ANA_INIT] PLL <<<<<<<<
2122 05:58:45.080127 [ANA_INIT] MIDPI >>>>>>>>
2123 05:58:45.080639 [ANA_INIT] MIDPI <<<<<<<<
2124 05:58:45.083547 [ANA_INIT] DLL >>>>>>>>
2125 05:58:45.086787 [ANA_INIT] DLL <<<<<<<<
2126 05:58:45.087248 [ANA_INIT] flow end
2127 05:58:45.090583 ============ LP4 DIFF to SE enter ============
2128 05:58:45.096898 ============ LP4 DIFF to SE exit ============
2129 05:58:45.097374 [ANA_INIT] <<<<<<<<<<<<<
2130 05:58:45.100500 [Flow] Enable top DCM control >>>>>
2131 05:58:45.103732 [Flow] Enable top DCM control <<<<<
2132 05:58:45.107325 Enable DLL master slave shuffle
2133 05:58:45.113396 ==============================================================
2134 05:58:45.114093 Gating Mode config
2135 05:58:45.120227 ==============================================================
2136 05:58:45.123444 Config description:
2137 05:58:45.133359 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2138 05:58:45.140239 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2139 05:58:45.143585 SELPH_MODE 0: By rank 1: By Phase
2140 05:58:45.150661 ==============================================================
2141 05:58:45.153590 GAT_TRACK_EN = 1
2142 05:58:45.154220 RX_GATING_MODE = 2
2143 05:58:45.156925 RX_GATING_TRACK_MODE = 2
2144 05:58:45.159781 SELPH_MODE = 1
2145 05:58:45.163298 PICG_EARLY_EN = 1
2146 05:58:45.166843 VALID_LAT_VALUE = 1
2147 05:58:45.173411 ==============================================================
2148 05:58:45.176443 Enter into Gating configuration >>>>
2149 05:58:45.179980 Exit from Gating configuration <<<<
2150 05:58:45.183539 Enter into DVFS_PRE_config >>>>>
2151 05:58:45.193324 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2152 05:58:45.197150 Exit from DVFS_PRE_config <<<<<
2153 05:58:45.200659 Enter into PICG configuration >>>>
2154 05:58:45.203632 Exit from PICG configuration <<<<
2155 05:58:45.207311 [RX_INPUT] configuration >>>>>
2156 05:58:45.207825 [RX_INPUT] configuration <<<<<
2157 05:58:45.213484 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2158 05:58:45.220552 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2159 05:58:45.223732 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2160 05:58:45.230063 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2161 05:58:45.237093 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2162 05:58:45.243116 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2163 05:58:45.246688 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2164 05:58:45.249926 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2165 05:58:45.256650 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2166 05:58:45.259984 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2167 05:58:45.263426 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2168 05:58:45.270344 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2169 05:58:45.272977 ===================================
2170 05:58:45.273439 LPDDR4 DRAM CONFIGURATION
2171 05:58:45.276806 ===================================
2172 05:58:45.279844 EX_ROW_EN[0] = 0x0
2173 05:58:45.280304 EX_ROW_EN[1] = 0x0
2174 05:58:45.283205 LP4Y_EN = 0x0
2175 05:58:45.286342 WORK_FSP = 0x0
2176 05:58:45.286800 WL = 0x4
2177 05:58:45.289476 RL = 0x4
2178 05:58:45.289974 BL = 0x2
2179 05:58:45.292592 RPST = 0x0
2180 05:58:45.293239 RD_PRE = 0x0
2181 05:58:45.295907 WR_PRE = 0x1
2182 05:58:45.296365 WR_PST = 0x0
2183 05:58:45.299691 DBI_WR = 0x0
2184 05:58:45.300306 DBI_RD = 0x0
2185 05:58:45.302900 OTF = 0x1
2186 05:58:45.306289 ===================================
2187 05:58:45.309316 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2188 05:58:45.312520 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2189 05:58:45.319191 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2190 05:58:45.322528 ===================================
2191 05:58:45.322946 LPDDR4 DRAM CONFIGURATION
2192 05:58:45.325796 ===================================
2193 05:58:45.329256 EX_ROW_EN[0] = 0x10
2194 05:58:45.329645 EX_ROW_EN[1] = 0x0
2195 05:58:45.332281 LP4Y_EN = 0x0
2196 05:58:45.335721 WORK_FSP = 0x0
2197 05:58:45.336017 WL = 0x4
2198 05:58:45.339281 RL = 0x4
2199 05:58:45.339669 BL = 0x2
2200 05:58:45.342668 RPST = 0x0
2201 05:58:45.342964 RD_PRE = 0x0
2202 05:58:45.345914 WR_PRE = 0x1
2203 05:58:45.346423 WR_PST = 0x0
2204 05:58:45.349413 DBI_WR = 0x0
2205 05:58:45.349866 DBI_RD = 0x0
2206 05:58:45.352629 OTF = 0x1
2207 05:58:45.355939 ===================================
2208 05:58:45.362376 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2209 05:58:45.362940 ==
2210 05:58:45.365547 Dram Type= 6, Freq= 0, CH_0, rank 0
2211 05:58:45.368695 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2212 05:58:45.369221 ==
2213 05:58:45.372496 [Duty_Offset_Calibration]
2214 05:58:45.373014 B0:0 B1:2 CA:1
2215 05:58:45.373373
2216 05:58:45.375574 [DutyScan_Calibration_Flow] k_type=0
2217 05:58:45.385475
2218 05:58:45.386035 ==CLK 0==
2219 05:58:45.388577 Final CLK duty delay cell = 0
2220 05:58:45.392328 [0] MAX Duty = 5093%(X100), DQS PI = 12
2221 05:58:45.395442 [0] MIN Duty = 4938%(X100), DQS PI = 52
2222 05:58:45.398698 [0] AVG Duty = 5015%(X100)
2223 05:58:45.399157
2224 05:58:45.402040 CH0 CLK Duty spec in!! Max-Min= 155%
2225 05:58:45.405224 [DutyScan_Calibration_Flow] ====Done====
2226 05:58:45.405698
2227 05:58:45.408847 [DutyScan_Calibration_Flow] k_type=1
2228 05:58:45.424815
2229 05:58:45.425465 ==DQS 0 ==
2230 05:58:45.427879 Final DQS duty delay cell = 0
2231 05:58:45.431564 [0] MAX Duty = 5125%(X100), DQS PI = 30
2232 05:58:45.434879 [0] MIN Duty = 5031%(X100), DQS PI = 4
2233 05:58:45.435457 [0] AVG Duty = 5078%(X100)
2234 05:58:45.437923
2235 05:58:45.438396 ==DQS 1 ==
2236 05:58:45.441245 Final DQS duty delay cell = 0
2237 05:58:45.444504 [0] MAX Duty = 5062%(X100), DQS PI = 58
2238 05:58:45.447972 [0] MIN Duty = 4906%(X100), DQS PI = 16
2239 05:58:45.451514 [0] AVG Duty = 4984%(X100)
2240 05:58:45.452172
2241 05:58:45.454737 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2242 05:58:45.455193
2243 05:58:45.457722 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2244 05:58:45.461089 [DutyScan_Calibration_Flow] ====Done====
2245 05:58:45.461547
2246 05:58:45.464647 [DutyScan_Calibration_Flow] k_type=3
2247 05:58:45.481461
2248 05:58:45.482007 ==DQM 0 ==
2249 05:58:45.484681 Final DQM duty delay cell = 0
2250 05:58:45.487775 [0] MAX Duty = 5156%(X100), DQS PI = 22
2251 05:58:45.491201 [0] MIN Duty = 4969%(X100), DQS PI = 40
2252 05:58:45.494371 [0] AVG Duty = 5062%(X100)
2253 05:58:45.494830
2254 05:58:45.495185 ==DQM 1 ==
2255 05:58:45.497572 Final DQM duty delay cell = 0
2256 05:58:45.501345 [0] MAX Duty = 5000%(X100), DQS PI = 56
2257 05:58:45.504469 [0] MIN Duty = 4844%(X100), DQS PI = 0
2258 05:58:45.507831 [0] AVG Duty = 4922%(X100)
2259 05:58:45.508385
2260 05:58:45.511356 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2261 05:58:45.511910
2262 05:58:45.514523 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2263 05:58:45.518063 [DutyScan_Calibration_Flow] ====Done====
2264 05:58:45.518617
2265 05:58:45.520892 [DutyScan_Calibration_Flow] k_type=2
2266 05:58:45.536738
2267 05:58:45.537296 ==DQ 0 ==
2268 05:58:45.539647 Final DQ duty delay cell = -4
2269 05:58:45.542827 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2270 05:58:45.545944 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2271 05:58:45.549167 [-4] AVG Duty = 4937%(X100)
2272 05:58:45.549625
2273 05:58:45.549987 ==DQ 1 ==
2274 05:58:45.552942 Final DQ duty delay cell = -4
2275 05:58:45.556538 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2276 05:58:45.559293 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2277 05:58:45.562388 [-4] AVG Duty = 4969%(X100)
2278 05:58:45.562850
2279 05:58:45.565921 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2280 05:58:45.566378
2281 05:58:45.569341 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2282 05:58:45.572517 [DutyScan_Calibration_Flow] ====Done====
2283 05:58:45.573286 ==
2284 05:58:45.575713 Dram Type= 6, Freq= 0, CH_1, rank 0
2285 05:58:45.579347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2286 05:58:45.579969 ==
2287 05:58:45.582450 [Duty_Offset_Calibration]
2288 05:58:45.582989 B0:0 B1:5 CA:-5
2289 05:58:45.583384
2290 05:58:45.586009 [DutyScan_Calibration_Flow] k_type=0
2291 05:58:45.597272
2292 05:58:45.597715 ==CLK 0==
2293 05:58:45.600129 Final CLK duty delay cell = 0
2294 05:58:45.603369 [0] MAX Duty = 5094%(X100), DQS PI = 24
2295 05:58:45.606504 [0] MIN Duty = 4907%(X100), DQS PI = 44
2296 05:58:45.606844 [0] AVG Duty = 5000%(X100)
2297 05:58:45.610492
2298 05:58:45.613490 CH1 CLK Duty spec in!! Max-Min= 187%
2299 05:58:45.616578 [DutyScan_Calibration_Flow] ====Done====
2300 05:58:45.616925
2301 05:58:45.620239 [DutyScan_Calibration_Flow] k_type=1
2302 05:58:45.635128
2303 05:58:45.635709 ==DQS 0 ==
2304 05:58:45.638594 Final DQS duty delay cell = 0
2305 05:58:45.641771 [0] MAX Duty = 5125%(X100), DQS PI = 16
2306 05:58:45.645037 [0] MIN Duty = 4875%(X100), DQS PI = 40
2307 05:58:45.648587 [0] AVG Duty = 5000%(X100)
2308 05:58:45.649093
2309 05:58:45.649456 ==DQS 1 ==
2310 05:58:45.652104 Final DQS duty delay cell = -4
2311 05:58:45.655368 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2312 05:58:45.658773 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2313 05:58:45.661854 [-4] AVG Duty = 4953%(X100)
2314 05:58:45.662325
2315 05:58:45.665319 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2316 05:58:45.665790
2317 05:58:45.668592 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2318 05:58:45.672224 [DutyScan_Calibration_Flow] ====Done====
2319 05:58:45.672845
2320 05:58:45.675104 [DutyScan_Calibration_Flow] k_type=3
2321 05:58:45.690380
2322 05:58:45.690946 ==DQM 0 ==
2323 05:58:45.693797 Final DQM duty delay cell = -4
2324 05:58:45.696849 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2325 05:58:45.700468 [-4] MIN Duty = 4875%(X100), DQS PI = 38
2326 05:58:45.703627 [-4] AVG Duty = 4968%(X100)
2327 05:58:45.704103
2328 05:58:45.704577 ==DQM 1 ==
2329 05:58:45.706591 Final DQM duty delay cell = -4
2330 05:58:45.710000 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2331 05:58:45.713418 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2332 05:58:45.716475 [-4] AVG Duty = 5000%(X100)
2333 05:58:45.717009
2334 05:58:45.719977 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2335 05:58:45.720431
2336 05:58:45.723165 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2337 05:58:45.726666 [DutyScan_Calibration_Flow] ====Done====
2338 05:58:45.727122
2339 05:58:45.729890 [DutyScan_Calibration_Flow] k_type=2
2340 05:58:45.747534
2341 05:58:45.748216 ==DQ 0 ==
2342 05:58:45.750519 Final DQ duty delay cell = 0
2343 05:58:45.754029 [0] MAX Duty = 5062%(X100), DQS PI = 0
2344 05:58:45.757267 [0] MIN Duty = 4969%(X100), DQS PI = 44
2345 05:58:45.757726 [0] AVG Duty = 5015%(X100)
2346 05:58:45.760908
2347 05:58:45.761362 ==DQ 1 ==
2348 05:58:45.764277 Final DQ duty delay cell = 0
2349 05:58:45.767705 [0] MAX Duty = 5000%(X100), DQS PI = 6
2350 05:58:45.771210 [0] MIN Duty = 4875%(X100), DQS PI = 46
2351 05:58:45.771769 [0] AVG Duty = 4937%(X100)
2352 05:58:45.772132
2353 05:58:45.773907 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2354 05:58:45.774361
2355 05:58:45.780813 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2356 05:58:45.784152 [DutyScan_Calibration_Flow] ====Done====
2357 05:58:45.787214 nWR fixed to 30
2358 05:58:45.787771 [ModeRegInit_LP4] CH0 RK0
2359 05:58:45.790726 [ModeRegInit_LP4] CH0 RK1
2360 05:58:45.793757 [ModeRegInit_LP4] CH1 RK0
2361 05:58:45.794207 [ModeRegInit_LP4] CH1 RK1
2362 05:58:45.797248 match AC timing 6
2363 05:58:45.800263 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2364 05:58:45.804046 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2365 05:58:45.810375 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2366 05:58:45.813599 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2367 05:58:45.820258 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2368 05:58:45.820592 ==
2369 05:58:45.823307 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 05:58:45.826377 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2371 05:58:45.826672 ==
2372 05:58:45.833341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2373 05:58:45.839954 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2374 05:58:45.846576 [CA 0] Center 39 (9~70) winsize 62
2375 05:58:45.850246 [CA 1] Center 39 (8~70) winsize 63
2376 05:58:45.853306 [CA 2] Center 36 (5~67) winsize 63
2377 05:58:45.856470 [CA 3] Center 35 (5~66) winsize 62
2378 05:58:45.860348 [CA 4] Center 34 (3~65) winsize 63
2379 05:58:45.863784 [CA 5] Center 33 (3~64) winsize 62
2380 05:58:45.864337
2381 05:58:45.866974 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2382 05:58:45.867427
2383 05:58:45.870582 [CATrainingPosCal] consider 1 rank data
2384 05:58:45.874026 u2DelayCellTimex100 = 270/100 ps
2385 05:58:45.877233 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2386 05:58:45.884077 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2387 05:58:45.887133 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2388 05:58:45.890288 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2389 05:58:45.893872 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2390 05:58:45.897146 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2391 05:58:45.897700
2392 05:58:45.900852 CA PerBit enable=1, Macro0, CA PI delay=33
2393 05:58:45.901412
2394 05:58:45.903993 [CBTSetCACLKResult] CA Dly = 33
2395 05:58:45.904544 CS Dly: 7 (0~38)
2396 05:58:45.907219 ==
2397 05:58:45.910243 Dram Type= 6, Freq= 0, CH_0, rank 1
2398 05:58:45.914105 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2399 05:58:45.914672 ==
2400 05:58:45.917169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2401 05:58:45.924069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2402 05:58:45.932966 [CA 0] Center 39 (8~70) winsize 63
2403 05:58:45.936072 [CA 1] Center 39 (8~70) winsize 63
2404 05:58:45.939659 [CA 2] Center 36 (5~67) winsize 63
2405 05:58:45.942427 [CA 3] Center 35 (4~66) winsize 63
2406 05:58:45.946363 [CA 4] Center 33 (3~64) winsize 62
2407 05:58:45.949741 [CA 5] Center 34 (3~65) winsize 63
2408 05:58:45.950198
2409 05:58:45.952301 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2410 05:58:45.952805
2411 05:58:45.955681 [CATrainingPosCal] consider 2 rank data
2412 05:58:45.958983 u2DelayCellTimex100 = 270/100 ps
2413 05:58:45.962438 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2414 05:58:45.968736 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2415 05:58:45.972276 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2416 05:58:45.975507 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2417 05:58:45.978809 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2418 05:58:45.982122 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2419 05:58:45.982637
2420 05:58:45.985333 CA PerBit enable=1, Macro0, CA PI delay=33
2421 05:58:45.985789
2422 05:58:45.988643 [CBTSetCACLKResult] CA Dly = 33
2423 05:58:45.989142 CS Dly: 7 (0~39)
2424 05:58:45.992040
2425 05:58:45.995538 ----->DramcWriteLeveling(PI) begin...
2426 05:58:45.996000 ==
2427 05:58:45.998752 Dram Type= 6, Freq= 0, CH_0, rank 0
2428 05:58:46.002440 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2429 05:58:46.003011 ==
2430 05:58:46.005409 Write leveling (Byte 0): 27 => 27
2431 05:58:46.008826 Write leveling (Byte 1): 26 => 26
2432 05:58:46.012494 DramcWriteLeveling(PI) end<-----
2433 05:58:46.013113
2434 05:58:46.013527 ==
2435 05:58:46.015293 Dram Type= 6, Freq= 0, CH_0, rank 0
2436 05:58:46.019491 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2437 05:58:46.020049 ==
2438 05:58:46.022404 [Gating] SW mode calibration
2439 05:58:46.028890 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2440 05:58:46.035683 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2441 05:58:46.038983 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2442 05:58:46.042127 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2443 05:58:46.048885 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2444 05:58:46.052137 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2445 05:58:46.055429 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2446 05:58:46.062025 0 11 20 | B1->B0 | 2f2f 2c2c | 0 0 | (0 1) (1 0)
2447 05:58:46.065183 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2448 05:58:46.068851 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2449 05:58:46.072096 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2450 05:58:46.078946 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2451 05:58:46.082356 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2452 05:58:46.085494 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2453 05:58:46.091795 0 12 16 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
2454 05:58:46.095191 0 12 20 | B1->B0 | 3a3a 3f3f | 0 0 | (0 0) (0 0)
2455 05:58:46.098887 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2456 05:58:46.105391 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2457 05:58:46.108349 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2458 05:58:46.112079 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2459 05:58:46.118649 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2460 05:58:46.121695 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2461 05:58:46.125235 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2462 05:58:46.132212 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2463 05:58:46.135523 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2464 05:58:46.139115 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2465 05:58:46.145563 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2466 05:58:46.148626 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2467 05:58:46.152137 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 05:58:46.158489 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 05:58:46.162254 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 05:58:46.164960 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 05:58:46.172011 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 05:58:46.175134 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 05:58:46.178586 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 05:58:46.185071 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 05:58:46.188381 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 05:58:46.191830 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 05:58:46.195061 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 05:58:46.201672 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2479 05:58:46.205048 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2480 05:58:46.208301 Total UI for P1: 0, mck2ui 16
2481 05:58:46.211801 best dqsien dly found for B0: ( 0, 15, 20)
2482 05:58:46.215405 Total UI for P1: 0, mck2ui 16
2483 05:58:46.218312 best dqsien dly found for B1: ( 0, 15, 20)
2484 05:58:46.221800 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2485 05:58:46.224808 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2486 05:58:46.225380
2487 05:58:46.228192 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2488 05:58:46.231955 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2489 05:58:46.235419 [Gating] SW calibration Done
2490 05:58:46.235886 ==
2491 05:58:46.238123 Dram Type= 6, Freq= 0, CH_0, rank 0
2492 05:58:46.244649 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2493 05:58:46.245161 ==
2494 05:58:46.245592 RX Vref Scan: 0
2495 05:58:46.245994
2496 05:58:46.248360 RX Vref 0 -> 0, step: 1
2497 05:58:46.248829
2498 05:58:46.251449 RX Delay -40 -> 252, step: 8
2499 05:58:46.255098 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2500 05:58:46.258813 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2501 05:58:46.261685 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2502 05:58:46.265048 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2503 05:58:46.271499 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2504 05:58:46.274981 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2505 05:58:46.278094 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2506 05:58:46.281728 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2507 05:58:46.285279 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2508 05:58:46.292015 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2509 05:58:46.295113 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2510 05:58:46.298088 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2511 05:58:46.302104 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2512 05:58:46.305575 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2513 05:58:46.311520 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2514 05:58:46.315171 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2515 05:58:46.315703 ==
2516 05:58:46.318681 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 05:58:46.321331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2518 05:58:46.321769 ==
2519 05:58:46.324815 DQS Delay:
2520 05:58:46.325285 DQS0 = 0, DQS1 = 0
2521 05:58:46.325714 DQM Delay:
2522 05:58:46.328499 DQM0 = 115, DQM1 = 106
2523 05:58:46.329085 DQ Delay:
2524 05:58:46.331854 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2525 05:58:46.335171 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2526 05:58:46.338220 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2527 05:58:46.345115 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2528 05:58:46.345664
2529 05:58:46.346100
2530 05:58:46.346501 ==
2531 05:58:46.348255 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 05:58:46.351433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2533 05:58:46.351861 ==
2534 05:58:46.352285
2535 05:58:46.352813
2536 05:58:46.354796 TX Vref Scan disable
2537 05:58:46.355221 == TX Byte 0 ==
2538 05:58:46.361245 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2539 05:58:46.365020 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2540 05:58:46.365465 == TX Byte 1 ==
2541 05:58:46.371419 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2542 05:58:46.374764 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2543 05:58:46.375304 ==
2544 05:58:46.377909 Dram Type= 6, Freq= 0, CH_0, rank 0
2545 05:58:46.380973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2546 05:58:46.381512 ==
2547 05:58:46.394071 TX Vref=22, minBit 8, minWin=25, winSum=415
2548 05:58:46.397639 TX Vref=24, minBit 8, minWin=26, winSum=426
2549 05:58:46.400928 TX Vref=26, minBit 10, minWin=25, winSum=427
2550 05:58:46.404028 TX Vref=28, minBit 9, minWin=26, winSum=433
2551 05:58:46.407811 TX Vref=30, minBit 9, minWin=26, winSum=432
2552 05:58:46.410568 TX Vref=32, minBit 8, minWin=26, winSum=432
2553 05:58:46.417762 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 28
2554 05:58:46.418289
2555 05:58:46.421061 Final TX Range 1 Vref 28
2556 05:58:46.421484
2557 05:58:46.421812 ==
2558 05:58:46.423949 Dram Type= 6, Freq= 0, CH_0, rank 0
2559 05:58:46.427575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2560 05:58:46.428105 ==
2561 05:58:46.428435
2562 05:58:46.431267
2563 05:58:46.431950 TX Vref Scan disable
2564 05:58:46.434092 == TX Byte 0 ==
2565 05:58:46.437799 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2566 05:58:46.440869 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2567 05:58:46.444243 == TX Byte 1 ==
2568 05:58:46.447029 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2569 05:58:46.450563 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2570 05:58:46.454122
2571 05:58:46.454540 [DATLAT]
2572 05:58:46.454867 Freq=1200, CH0 RK0
2573 05:58:46.455173
2574 05:58:46.457217 DATLAT Default: 0xd
2575 05:58:46.457705 0, 0xFFFF, sum = 0
2576 05:58:46.460244 1, 0xFFFF, sum = 0
2577 05:58:46.460743 2, 0xFFFF, sum = 0
2578 05:58:46.464107 3, 0xFFFF, sum = 0
2579 05:58:46.464592 4, 0xFFFF, sum = 0
2580 05:58:46.466959 5, 0xFFFF, sum = 0
2581 05:58:46.467430 6, 0xFFFF, sum = 0
2582 05:58:46.470337 7, 0xFFFF, sum = 0
2583 05:58:46.474057 8, 0xFFFF, sum = 0
2584 05:58:46.474621 9, 0xFFFF, sum = 0
2585 05:58:46.477230 10, 0xFFFF, sum = 0
2586 05:58:46.477701 11, 0x0, sum = 1
2587 05:58:46.480640 12, 0x0, sum = 2
2588 05:58:46.481299 13, 0x0, sum = 3
2589 05:58:46.481673 14, 0x0, sum = 4
2590 05:58:46.483894 best_step = 12
2591 05:58:46.484453
2592 05:58:46.484880 ==
2593 05:58:46.487575 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 05:58:46.490535 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2595 05:58:46.491005 ==
2596 05:58:46.493785 RX Vref Scan: 1
2597 05:58:46.494246
2598 05:58:46.497225 Set Vref Range= 32 -> 127
2599 05:58:46.497831
2600 05:58:46.498356 RX Vref 32 -> 127, step: 1
2601 05:58:46.498877
2602 05:58:46.500623 RX Delay -21 -> 252, step: 4
2603 05:58:46.501124
2604 05:58:46.503793 Set Vref, RX VrefLevel [Byte0]: 32
2605 05:58:46.506788 [Byte1]: 32
2606 05:58:46.510659
2607 05:58:46.511191 Set Vref, RX VrefLevel [Byte0]: 33
2608 05:58:46.513993 [Byte1]: 33
2609 05:58:46.518274
2610 05:58:46.518744 Set Vref, RX VrefLevel [Byte0]: 34
2611 05:58:46.521664 [Byte1]: 34
2612 05:58:46.526150
2613 05:58:46.526568 Set Vref, RX VrefLevel [Byte0]: 35
2614 05:58:46.529668 [Byte1]: 35
2615 05:58:46.534360
2616 05:58:46.534882 Set Vref, RX VrefLevel [Byte0]: 36
2617 05:58:46.538048 [Byte1]: 36
2618 05:58:46.542432
2619 05:58:46.542943 Set Vref, RX VrefLevel [Byte0]: 37
2620 05:58:46.545831 [Byte1]: 37
2621 05:58:46.550518
2622 05:58:46.550936 Set Vref, RX VrefLevel [Byte0]: 38
2623 05:58:46.553381 [Byte1]: 38
2624 05:58:46.558077
2625 05:58:46.558596 Set Vref, RX VrefLevel [Byte0]: 39
2626 05:58:46.561328 [Byte1]: 39
2627 05:58:46.566016
2628 05:58:46.566435 Set Vref, RX VrefLevel [Byte0]: 40
2629 05:58:46.569049 [Byte1]: 40
2630 05:58:46.574373
2631 05:58:46.574897 Set Vref, RX VrefLevel [Byte0]: 41
2632 05:58:46.577050 [Byte1]: 41
2633 05:58:46.581858
2634 05:58:46.582302 Set Vref, RX VrefLevel [Byte0]: 42
2635 05:58:46.584773 [Byte1]: 42
2636 05:58:46.590069
2637 05:58:46.590601 Set Vref, RX VrefLevel [Byte0]: 43
2638 05:58:46.593255 [Byte1]: 43
2639 05:58:46.597567
2640 05:58:46.598102 Set Vref, RX VrefLevel [Byte0]: 44
2641 05:58:46.600658 [Byte1]: 44
2642 05:58:46.605637
2643 05:58:46.606161 Set Vref, RX VrefLevel [Byte0]: 45
2644 05:58:46.609076 [Byte1]: 45
2645 05:58:46.613628
2646 05:58:46.614152 Set Vref, RX VrefLevel [Byte0]: 46
2647 05:58:46.617052 [Byte1]: 46
2648 05:58:46.621236
2649 05:58:46.621655 Set Vref, RX VrefLevel [Byte0]: 47
2650 05:58:46.624814 [Byte1]: 47
2651 05:58:46.629451
2652 05:58:46.630052 Set Vref, RX VrefLevel [Byte0]: 48
2653 05:58:46.632359 [Byte1]: 48
2654 05:58:46.637194
2655 05:58:46.637756 Set Vref, RX VrefLevel [Byte0]: 49
2656 05:58:46.640280 [Byte1]: 49
2657 05:58:46.644936
2658 05:58:46.645452 Set Vref, RX VrefLevel [Byte0]: 50
2659 05:58:46.648239 [Byte1]: 50
2660 05:58:46.653241
2661 05:58:46.653660 Set Vref, RX VrefLevel [Byte0]: 51
2662 05:58:46.656546 [Byte1]: 51
2663 05:58:46.661071
2664 05:58:46.661489 Set Vref, RX VrefLevel [Byte0]: 52
2665 05:58:46.664192 [Byte1]: 52
2666 05:58:46.668924
2667 05:58:46.669342 Set Vref, RX VrefLevel [Byte0]: 53
2668 05:58:46.672325 [Byte1]: 53
2669 05:58:46.676877
2670 05:58:46.677296 Set Vref, RX VrefLevel [Byte0]: 54
2671 05:58:46.680204 [Byte1]: 54
2672 05:58:46.685001
2673 05:58:46.685531 Set Vref, RX VrefLevel [Byte0]: 55
2674 05:58:46.687832 [Byte1]: 55
2675 05:58:46.692611
2676 05:58:46.693180 Set Vref, RX VrefLevel [Byte0]: 56
2677 05:58:46.696117 [Byte1]: 56
2678 05:58:46.700551
2679 05:58:46.701004 Set Vref, RX VrefLevel [Byte0]: 57
2680 05:58:46.704091 [Byte1]: 57
2681 05:58:46.708670
2682 05:58:46.709240 Set Vref, RX VrefLevel [Byte0]: 58
2683 05:58:46.712003 [Byte1]: 58
2684 05:58:46.716594
2685 05:58:46.717162 Set Vref, RX VrefLevel [Byte0]: 59
2686 05:58:46.719969 [Byte1]: 59
2687 05:58:46.724496
2688 05:58:46.725070 Set Vref, RX VrefLevel [Byte0]: 60
2689 05:58:46.727853 [Byte1]: 60
2690 05:58:46.732624
2691 05:58:46.733188 Set Vref, RX VrefLevel [Byte0]: 61
2692 05:58:46.735626 [Byte1]: 61
2693 05:58:46.740445
2694 05:58:46.740996 Set Vref, RX VrefLevel [Byte0]: 62
2695 05:58:46.744024 [Byte1]: 62
2696 05:58:46.748146
2697 05:58:46.748754 Set Vref, RX VrefLevel [Byte0]: 63
2698 05:58:46.751458 [Byte1]: 63
2699 05:58:46.756193
2700 05:58:46.756911 Set Vref, RX VrefLevel [Byte0]: 64
2701 05:58:46.759307 [Byte1]: 64
2702 05:58:46.764071
2703 05:58:46.764762 Set Vref, RX VrefLevel [Byte0]: 65
2704 05:58:46.767415 [Byte1]: 65
2705 05:58:46.771959
2706 05:58:46.772551 Set Vref, RX VrefLevel [Byte0]: 66
2707 05:58:46.774894 [Byte1]: 66
2708 05:58:46.779906
2709 05:58:46.780471 Final RX Vref Byte 0 = 55 to rank0
2710 05:58:46.782923 Final RX Vref Byte 1 = 49 to rank0
2711 05:58:46.786528 Final RX Vref Byte 0 = 55 to rank1
2712 05:58:46.790160 Final RX Vref Byte 1 = 49 to rank1==
2713 05:58:46.793115 Dram Type= 6, Freq= 0, CH_0, rank 0
2714 05:58:46.799509 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2715 05:58:46.799944 ==
2716 05:58:46.800214 DQS Delay:
2717 05:58:46.800455 DQS0 = 0, DQS1 = 0
2718 05:58:46.803445 DQM Delay:
2719 05:58:46.803891 DQM0 = 114, DQM1 = 105
2720 05:58:46.806305 DQ Delay:
2721 05:58:46.809691 DQ0 =112, DQ1 =114, DQ2 =112, DQ3 =110
2722 05:58:46.813274 DQ4 =118, DQ5 =106, DQ6 =122, DQ7 =120
2723 05:58:46.816652 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2724 05:58:46.820110 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2725 05:58:46.820862
2726 05:58:46.821373
2727 05:58:46.827072 [DQSOSCAuto] RK0, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2728 05:58:46.829970 CH0 RK0: MR19=404, MR18=707
2729 05:58:46.836662 CH0_RK0: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
2730 05:58:46.837277
2731 05:58:46.839894 ----->DramcWriteLeveling(PI) begin...
2732 05:58:46.840467 ==
2733 05:58:46.843209 Dram Type= 6, Freq= 0, CH_0, rank 1
2734 05:58:46.846538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2735 05:58:46.847125 ==
2736 05:58:46.849549 Write leveling (Byte 0): 27 => 27
2737 05:58:46.852894 Write leveling (Byte 1): 24 => 24
2738 05:58:46.856301 DramcWriteLeveling(PI) end<-----
2739 05:58:46.856926
2740 05:58:46.857299 ==
2741 05:58:46.859867 Dram Type= 6, Freq= 0, CH_0, rank 1
2742 05:58:46.866150 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2743 05:58:46.866619 ==
2744 05:58:46.866983 [Gating] SW mode calibration
2745 05:58:46.876564 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2746 05:58:46.879440 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2747 05:58:46.883098 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2748 05:58:46.889434 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2749 05:58:46.892551 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2750 05:58:46.895897 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2751 05:58:46.903084 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2752 05:58:46.905925 0 11 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2753 05:58:46.909069 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2754 05:58:46.915935 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2755 05:58:46.919422 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2756 05:58:46.922295 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2757 05:58:46.929384 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2758 05:58:46.932785 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2759 05:58:46.935805 0 12 16 | B1->B0 | 2525 2f2f | 1 1 | (0 0) (0 0)
2760 05:58:46.942367 0 12 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2761 05:58:46.946231 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2762 05:58:46.949299 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2763 05:58:46.956092 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2764 05:58:46.959081 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2765 05:58:46.962350 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2766 05:58:46.969010 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2767 05:58:46.972773 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2768 05:58:46.975730 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2769 05:58:46.982373 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2770 05:58:46.985484 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2771 05:58:46.988821 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2772 05:58:46.995762 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2773 05:58:46.998773 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 05:58:47.002968 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 05:58:47.009399 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 05:58:47.012453 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 05:58:47.015826 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 05:58:47.018852 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 05:58:47.025986 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 05:58:47.028798 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 05:58:47.032031 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 05:58:47.039211 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 05:58:47.042104 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2784 05:58:47.045357 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2785 05:58:47.051763 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2786 05:58:47.055404 Total UI for P1: 0, mck2ui 16
2787 05:58:47.058454 best dqsien dly found for B0: ( 0, 15, 18)
2788 05:58:47.058755 Total UI for P1: 0, mck2ui 16
2789 05:58:47.064980 best dqsien dly found for B1: ( 0, 15, 20)
2790 05:58:47.068464 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2791 05:58:47.072136 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2792 05:58:47.072522
2793 05:58:47.075573 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2794 05:58:47.078455 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2795 05:58:47.081934 [Gating] SW calibration Done
2796 05:58:47.082331 ==
2797 05:58:47.085225 Dram Type= 6, Freq= 0, CH_0, rank 1
2798 05:58:47.088945 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2799 05:58:47.089425 ==
2800 05:58:47.091883 RX Vref Scan: 0
2801 05:58:47.092345
2802 05:58:47.092703 RX Vref 0 -> 0, step: 1
2803 05:58:47.095684
2804 05:58:47.096234 RX Delay -40 -> 252, step: 8
2805 05:58:47.102020 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2806 05:58:47.105278 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2807 05:58:47.108555 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2808 05:58:47.112005 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2809 05:58:47.115238 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2810 05:58:47.118597 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2811 05:58:47.125115 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2812 05:58:47.128645 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2813 05:58:47.132319 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2814 05:58:47.135244 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2815 05:58:47.138624 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2816 05:58:47.145283 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2817 05:58:47.148472 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2818 05:58:47.151685 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2819 05:58:47.155197 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2820 05:58:47.158783 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2821 05:58:47.161758 ==
2822 05:58:47.165176 Dram Type= 6, Freq= 0, CH_0, rank 1
2823 05:58:47.168514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2824 05:58:47.169055 ==
2825 05:58:47.169424 DQS Delay:
2826 05:58:47.171895 DQS0 = 0, DQS1 = 0
2827 05:58:47.172357 DQM Delay:
2828 05:58:47.174982 DQM0 = 115, DQM1 = 106
2829 05:58:47.175441 DQ Delay:
2830 05:58:47.178455 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2831 05:58:47.181747 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2832 05:58:47.185344 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2833 05:58:47.188288 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2834 05:58:47.188610
2835 05:58:47.188891
2836 05:58:47.189127 ==
2837 05:58:47.191695 Dram Type= 6, Freq= 0, CH_0, rank 1
2838 05:58:47.198320 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2839 05:58:47.198745 ==
2840 05:58:47.199002
2841 05:58:47.199238
2842 05:58:47.199465 TX Vref Scan disable
2843 05:58:47.201981 == TX Byte 0 ==
2844 05:58:47.205070 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2845 05:58:47.211984 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2846 05:58:47.212405 == TX Byte 1 ==
2847 05:58:47.215059 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2848 05:58:47.221816 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2849 05:58:47.222236 ==
2850 05:58:47.224953 Dram Type= 6, Freq= 0, CH_0, rank 1
2851 05:58:47.228288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2852 05:58:47.228814 ==
2853 05:58:47.239721 TX Vref=22, minBit 8, minWin=25, winSum=418
2854 05:58:47.243220 TX Vref=24, minBit 8, minWin=25, winSum=423
2855 05:58:47.246398 TX Vref=26, minBit 9, minWin=25, winSum=426
2856 05:58:47.249740 TX Vref=28, minBit 8, minWin=26, winSum=432
2857 05:58:47.253512 TX Vref=30, minBit 9, minWin=26, winSum=430
2858 05:58:47.256871 TX Vref=32, minBit 8, minWin=26, winSum=432
2859 05:58:47.263213 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 28
2860 05:58:47.263754
2861 05:58:47.266233 Final TX Range 1 Vref 28
2862 05:58:47.266884
2863 05:58:47.267272 ==
2864 05:58:47.269910 Dram Type= 6, Freq= 0, CH_0, rank 1
2865 05:58:47.273338 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2866 05:58:47.273806 ==
2867 05:58:47.274172
2868 05:58:47.276538
2869 05:58:47.277041 TX Vref Scan disable
2870 05:58:47.279677 == TX Byte 0 ==
2871 05:58:47.283224 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2872 05:58:47.286959 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2873 05:58:47.289657 == TX Byte 1 ==
2874 05:58:47.293188 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2875 05:58:47.296564 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2876 05:58:47.297080
2877 05:58:47.299849 [DATLAT]
2878 05:58:47.300307 Freq=1200, CH0 RK1
2879 05:58:47.300770
2880 05:58:47.302842 DATLAT Default: 0xc
2881 05:58:47.303290 0, 0xFFFF, sum = 0
2882 05:58:47.306300 1, 0xFFFF, sum = 0
2883 05:58:47.306721 2, 0xFFFF, sum = 0
2884 05:58:47.309899 3, 0xFFFF, sum = 0
2885 05:58:47.310321 4, 0xFFFF, sum = 0
2886 05:58:47.313097 5, 0xFFFF, sum = 0
2887 05:58:47.313590 6, 0xFFFF, sum = 0
2888 05:58:47.316293 7, 0xFFFF, sum = 0
2889 05:58:47.319421 8, 0xFFFF, sum = 0
2890 05:58:47.319968 9, 0xFFFF, sum = 0
2891 05:58:47.322964 10, 0xFFFF, sum = 0
2892 05:58:47.323482 11, 0x0, sum = 1
2893 05:58:47.326255 12, 0x0, sum = 2
2894 05:58:47.326674 13, 0x0, sum = 3
2895 05:58:47.327003 14, 0x0, sum = 4
2896 05:58:47.329864 best_step = 12
2897 05:58:47.330276
2898 05:58:47.330601 ==
2899 05:58:47.332940 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 05:58:47.336467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2901 05:58:47.337051 ==
2902 05:58:47.339475 RX Vref Scan: 0
2903 05:58:47.339890
2904 05:58:47.340214 RX Vref 0 -> 0, step: 1
2905 05:58:47.342923
2906 05:58:47.343427 RX Delay -21 -> 252, step: 4
2907 05:58:47.349863 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2908 05:58:47.353375 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2909 05:58:47.356582 iDelay=199, Bit 2, Center 112 (43 ~ 182) 140
2910 05:58:47.360289 iDelay=199, Bit 3, Center 110 (39 ~ 182) 144
2911 05:58:47.363396 iDelay=199, Bit 4, Center 118 (43 ~ 194) 152
2912 05:58:47.369912 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2913 05:58:47.373244 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2914 05:58:47.377322 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2915 05:58:47.379946 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2916 05:58:47.383559 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2917 05:58:47.390087 iDelay=199, Bit 10, Center 108 (43 ~ 174) 132
2918 05:58:47.393304 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2919 05:58:47.397021 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2920 05:58:47.400304 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2921 05:58:47.403905 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2922 05:58:47.409947 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2923 05:58:47.410506 ==
2924 05:58:47.413615 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 05:58:47.416916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2926 05:58:47.417472 ==
2927 05:58:47.417838 DQS Delay:
2928 05:58:47.419918 DQS0 = 0, DQS1 = 0
2929 05:58:47.420380 DQM Delay:
2930 05:58:47.423755 DQM0 = 115, DQM1 = 105
2931 05:58:47.424312 DQ Delay:
2932 05:58:47.426540 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =110
2933 05:58:47.430210 DQ4 =118, DQ5 =108, DQ6 =122, DQ7 =124
2934 05:58:47.433354 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =96
2935 05:58:47.436471 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2936 05:58:47.436969
2937 05:58:47.437326
2938 05:58:47.446786 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2939 05:58:47.449935 CH0 RK1: MR19=404, MR18=C0C
2940 05:58:47.453283 CH0_RK1: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
2941 05:58:47.456628 [RxdqsGatingPostProcess] freq 1200
2942 05:58:47.463041 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2943 05:58:47.466796 Pre-setting of DQS Precalculation
2944 05:58:47.469965 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2945 05:58:47.470530 ==
2946 05:58:47.473465 Dram Type= 6, Freq= 0, CH_1, rank 0
2947 05:58:47.479788 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2948 05:58:47.480330 ==
2949 05:58:47.483072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2950 05:58:47.490487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2951 05:58:47.498491 [CA 0] Center 37 (7~68) winsize 62
2952 05:58:47.501847 [CA 1] Center 37 (7~68) winsize 62
2953 05:58:47.505515 [CA 2] Center 34 (4~65) winsize 62
2954 05:58:47.508837 [CA 3] Center 33 (3~64) winsize 62
2955 05:58:47.511965 [CA 4] Center 32 (2~63) winsize 62
2956 05:58:47.515365 [CA 5] Center 32 (2~63) winsize 62
2957 05:58:47.515921
2958 05:58:47.518739 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2959 05:58:47.519312
2960 05:58:47.521933 [CATrainingPosCal] consider 1 rank data
2961 05:58:47.525285 u2DelayCellTimex100 = 270/100 ps
2962 05:58:47.528457 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2963 05:58:47.531800 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2964 05:58:47.538526 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2965 05:58:47.541639 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2966 05:58:47.545080 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2967 05:58:47.548904 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2968 05:58:47.549478
2969 05:58:47.551925 CA PerBit enable=1, Macro0, CA PI delay=32
2970 05:58:47.552448
2971 05:58:47.554811 [CBTSetCACLKResult] CA Dly = 32
2972 05:58:47.555420 CS Dly: 6 (0~37)
2973 05:58:47.558128 ==
2974 05:58:47.558586 Dram Type= 6, Freq= 0, CH_1, rank 1
2975 05:58:47.564812 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2976 05:58:47.565343 ==
2977 05:58:47.568549 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2978 05:58:47.574755 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2979 05:58:47.583782 [CA 0] Center 37 (6~68) winsize 63
2980 05:58:47.587076 [CA 1] Center 37 (7~68) winsize 62
2981 05:58:47.590739 [CA 2] Center 33 (3~64) winsize 62
2982 05:58:47.593404 [CA 3] Center 34 (4~64) winsize 61
2983 05:58:47.597169 [CA 4] Center 32 (2~63) winsize 62
2984 05:58:47.600210 [CA 5] Center 32 (2~62) winsize 61
2985 05:58:47.600665
2986 05:58:47.603624 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2987 05:58:47.604212
2988 05:58:47.606792 [CATrainingPosCal] consider 2 rank data
2989 05:58:47.609975 u2DelayCellTimex100 = 270/100 ps
2990 05:58:47.613519 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2991 05:58:47.620342 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2992 05:58:47.623666 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2993 05:58:47.627154 CA3 delay=34 (4~64),Diff = 2 PI (9 cell)
2994 05:58:47.629955 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2995 05:58:47.633516 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2996 05:58:47.633980
2997 05:58:47.636579 CA PerBit enable=1, Macro0, CA PI delay=32
2998 05:58:47.637104
2999 05:58:47.639825 [CBTSetCACLKResult] CA Dly = 32
3000 05:58:47.640283 CS Dly: 6 (0~38)
3001 05:58:47.640645
3002 05:58:47.643368 ----->DramcWriteLeveling(PI) begin...
3003 05:58:47.646615 ==
3004 05:58:47.649735 Dram Type= 6, Freq= 0, CH_1, rank 0
3005 05:58:47.653132 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3006 05:58:47.653374 ==
3007 05:58:47.656592 Write leveling (Byte 0): 22 => 22
3008 05:58:47.659866 Write leveling (Byte 1): 22 => 22
3009 05:58:47.662863 DramcWriteLeveling(PI) end<-----
3010 05:58:47.663023
3011 05:58:47.663220 ==
3012 05:58:47.666485 Dram Type= 6, Freq= 0, CH_1, rank 0
3013 05:58:47.670007 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3014 05:58:47.670157 ==
3015 05:58:47.673027 [Gating] SW mode calibration
3016 05:58:47.680064 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3017 05:58:47.683513 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3018 05:58:47.689932 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3019 05:58:47.693306 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3020 05:58:47.696528 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3021 05:58:47.702865 0 11 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3022 05:58:47.706076 0 11 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (1 0)
3023 05:58:47.709552 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3024 05:58:47.716074 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3025 05:58:47.719469 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3026 05:58:47.722958 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3027 05:58:47.729378 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3028 05:58:47.732932 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3029 05:58:47.736093 0 12 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
3030 05:58:47.743183 0 12 16 | B1->B0 | 3333 4444 | 0 0 | (0 0) (0 0)
3031 05:58:47.746400 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3032 05:58:47.749524 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3033 05:58:47.756284 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3034 05:58:47.759754 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3035 05:58:47.762928 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3036 05:58:47.769519 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3037 05:58:47.773054 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3038 05:58:47.776621 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3039 05:58:47.783154 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3040 05:58:47.786484 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3041 05:58:47.789697 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3042 05:58:47.796997 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3043 05:58:47.800082 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 05:58:47.803247 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 05:58:47.809922 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 05:58:47.813334 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 05:58:47.816293 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 05:58:47.819845 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 05:58:47.826530 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 05:58:47.829910 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 05:58:47.833058 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 05:58:47.839587 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 05:58:47.843039 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 05:58:47.846277 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3055 05:58:47.852639 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3056 05:58:47.855985 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3057 05:58:47.859523 Total UI for P1: 0, mck2ui 16
3058 05:58:47.862757 best dqsien dly found for B0: ( 0, 15, 18)
3059 05:58:47.865793 Total UI for P1: 0, mck2ui 16
3060 05:58:47.869390 best dqsien dly found for B1: ( 0, 15, 20)
3061 05:58:47.872489 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
3062 05:58:47.876246 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3063 05:58:47.876379
3064 05:58:47.879241 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
3065 05:58:47.882333 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3066 05:58:47.885956 [Gating] SW calibration Done
3067 05:58:47.886081 ==
3068 05:58:47.889208 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 05:58:47.892537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3070 05:58:47.895776 ==
3071 05:58:47.895875 RX Vref Scan: 0
3072 05:58:47.895947
3073 05:58:47.899967 RX Vref 0 -> 0, step: 1
3074 05:58:47.900140
3075 05:58:47.902716 RX Delay -40 -> 252, step: 8
3076 05:58:47.906375 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3077 05:58:47.909141 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3078 05:58:47.912675 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3079 05:58:47.915897 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3080 05:58:47.922406 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3081 05:58:47.926005 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3082 05:58:47.929294 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3083 05:58:47.932774 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3084 05:58:47.936231 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3085 05:58:47.943196 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3086 05:58:47.946687 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3087 05:58:47.949804 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3088 05:58:47.953006 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3089 05:58:47.956744 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3090 05:58:47.963090 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3091 05:58:47.966190 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3092 05:58:47.966749 ==
3093 05:58:47.969402 Dram Type= 6, Freq= 0, CH_1, rank 0
3094 05:58:47.972913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3095 05:58:47.973372 ==
3096 05:58:47.976148 DQS Delay:
3097 05:58:47.976604 DQS0 = 0, DQS1 = 0
3098 05:58:47.977025 DQM Delay:
3099 05:58:47.979423 DQM0 = 116, DQM1 = 109
3100 05:58:47.979874 DQ Delay:
3101 05:58:47.982761 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3102 05:58:47.986039 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3103 05:58:47.989371 DQ8 =87, DQ9 =99, DQ10 =111, DQ11 =99
3104 05:58:47.992450 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3105 05:58:47.995971
3106 05:58:47.996424
3107 05:58:47.996856 ==
3108 05:58:47.999670 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 05:58:48.002786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3110 05:58:48.003244 ==
3111 05:58:48.003597
3112 05:58:48.003921
3113 05:58:48.005718 TX Vref Scan disable
3114 05:58:48.006172 == TX Byte 0 ==
3115 05:58:48.012647 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3116 05:58:48.016529 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3117 05:58:48.017061 == TX Byte 1 ==
3118 05:58:48.022821 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3119 05:58:48.026026 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3120 05:58:48.026490 ==
3121 05:58:48.029070 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 05:58:48.032238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3123 05:58:48.032700 ==
3124 05:58:48.044817 TX Vref=22, minBit 0, minWin=25, winSum=413
3125 05:58:48.048332 TX Vref=24, minBit 9, minWin=25, winSum=423
3126 05:58:48.051497 TX Vref=26, minBit 1, minWin=26, winSum=427
3127 05:58:48.054911 TX Vref=28, minBit 8, minWin=26, winSum=431
3128 05:58:48.058164 TX Vref=30, minBit 8, minWin=26, winSum=432
3129 05:58:48.061279 TX Vref=32, minBit 9, minWin=25, winSum=431
3130 05:58:48.068283 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 30
3131 05:58:48.068877
3132 05:58:48.071248 Final TX Range 1 Vref 30
3133 05:58:48.071810
3134 05:58:48.072173 ==
3135 05:58:48.074565 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 05:58:48.078258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3137 05:58:48.078819 ==
3138 05:58:48.079180
3139 05:58:48.081294
3140 05:58:48.081870 TX Vref Scan disable
3141 05:58:48.084547 == TX Byte 0 ==
3142 05:58:48.087751 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3143 05:58:48.091452 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3144 05:58:48.094693 == TX Byte 1 ==
3145 05:58:48.097892 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3146 05:58:48.101184 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3147 05:58:48.101644
3148 05:58:48.104826 [DATLAT]
3149 05:58:48.105284 Freq=1200, CH1 RK0
3150 05:58:48.105644
3151 05:58:48.108080 DATLAT Default: 0xd
3152 05:58:48.108537 0, 0xFFFF, sum = 0
3153 05:58:48.111403 1, 0xFFFF, sum = 0
3154 05:58:48.111871 2, 0xFFFF, sum = 0
3155 05:58:48.114492 3, 0xFFFF, sum = 0
3156 05:58:48.114908 4, 0xFFFF, sum = 0
3157 05:58:48.118268 5, 0xFFFF, sum = 0
3158 05:58:48.118793 6, 0xFFFF, sum = 0
3159 05:58:48.121898 7, 0xFFFF, sum = 0
3160 05:58:48.122416 8, 0xFFFF, sum = 0
3161 05:58:48.125254 9, 0xFFFF, sum = 0
3162 05:58:48.127981 10, 0xFFFF, sum = 0
3163 05:58:48.128405 11, 0x0, sum = 1
3164 05:58:48.128784 12, 0x0, sum = 2
3165 05:58:48.131258 13, 0x0, sum = 3
3166 05:58:48.131683 14, 0x0, sum = 4
3167 05:58:48.135064 best_step = 12
3168 05:58:48.135705
3169 05:58:48.136283 ==
3170 05:58:48.137770 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 05:58:48.141042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3172 05:58:48.141465 ==
3173 05:58:48.144650 RX Vref Scan: 1
3174 05:58:48.145114
3175 05:58:48.145473 Set Vref Range= 32 -> 127
3176 05:58:48.147798
3177 05:58:48.148209 RX Vref 32 -> 127, step: 1
3178 05:58:48.148534
3179 05:58:48.151292 RX Delay -29 -> 252, step: 4
3180 05:58:48.151706
3181 05:58:48.154918 Set Vref, RX VrefLevel [Byte0]: 32
3182 05:58:48.157830 [Byte1]: 32
3183 05:58:48.158349
3184 05:58:48.161210 Set Vref, RX VrefLevel [Byte0]: 33
3185 05:58:48.164790 [Byte1]: 33
3186 05:58:48.169301
3187 05:58:48.169715 Set Vref, RX VrefLevel [Byte0]: 34
3188 05:58:48.172372 [Byte1]: 34
3189 05:58:48.177093
3190 05:58:48.177605 Set Vref, RX VrefLevel [Byte0]: 35
3191 05:58:48.180764 [Byte1]: 35
3192 05:58:48.184902
3193 05:58:48.185317 Set Vref, RX VrefLevel [Byte0]: 36
3194 05:58:48.188665 [Byte1]: 36
3195 05:58:48.193097
3196 05:58:48.193613 Set Vref, RX VrefLevel [Byte0]: 37
3197 05:58:48.196196 [Byte1]: 37
3198 05:58:48.200861
3199 05:58:48.201366 Set Vref, RX VrefLevel [Byte0]: 38
3200 05:58:48.204183 [Byte1]: 38
3201 05:58:48.209305
3202 05:58:48.209816 Set Vref, RX VrefLevel [Byte0]: 39
3203 05:58:48.212092 [Byte1]: 39
3204 05:58:48.216667
3205 05:58:48.217156 Set Vref, RX VrefLevel [Byte0]: 40
3206 05:58:48.219950 [Byte1]: 40
3207 05:58:48.225233
3208 05:58:48.225788 Set Vref, RX VrefLevel [Byte0]: 41
3209 05:58:48.228549 [Byte1]: 41
3210 05:58:48.232947
3211 05:58:48.233402 Set Vref, RX VrefLevel [Byte0]: 42
3212 05:58:48.236161 [Byte1]: 42
3213 05:58:48.240473
3214 05:58:48.240993 Set Vref, RX VrefLevel [Byte0]: 43
3215 05:58:48.244172 [Byte1]: 43
3216 05:58:48.248897
3217 05:58:48.249488 Set Vref, RX VrefLevel [Byte0]: 44
3218 05:58:48.251817 [Byte1]: 44
3219 05:58:48.256896
3220 05:58:48.257449 Set Vref, RX VrefLevel [Byte0]: 45
3221 05:58:48.259697 [Byte1]: 45
3222 05:58:48.264300
3223 05:58:48.264806 Set Vref, RX VrefLevel [Byte0]: 46
3224 05:58:48.267793 [Byte1]: 46
3225 05:58:48.272600
3226 05:58:48.273206 Set Vref, RX VrefLevel [Byte0]: 47
3227 05:58:48.275816 [Byte1]: 47
3228 05:58:48.280434
3229 05:58:48.281054 Set Vref, RX VrefLevel [Byte0]: 48
3230 05:58:48.284028 [Byte1]: 48
3231 05:58:48.288693
3232 05:58:48.289313 Set Vref, RX VrefLevel [Byte0]: 49
3233 05:58:48.292263 [Byte1]: 49
3234 05:58:48.296488
3235 05:58:48.296982 Set Vref, RX VrefLevel [Byte0]: 50
3236 05:58:48.299610 [Byte1]: 50
3237 05:58:48.304519
3238 05:58:48.305124 Set Vref, RX VrefLevel [Byte0]: 51
3239 05:58:48.307948 [Byte1]: 51
3240 05:58:48.312445
3241 05:58:48.313049 Set Vref, RX VrefLevel [Byte0]: 52
3242 05:58:48.315671 [Byte1]: 52
3243 05:58:48.320282
3244 05:58:48.320883 Set Vref, RX VrefLevel [Byte0]: 53
3245 05:58:48.323790 [Byte1]: 53
3246 05:58:48.328130
3247 05:58:48.328682 Set Vref, RX VrefLevel [Byte0]: 54
3248 05:58:48.331812 [Byte1]: 54
3249 05:58:48.336478
3250 05:58:48.337171 Set Vref, RX VrefLevel [Byte0]: 55
3251 05:58:48.339549 [Byte1]: 55
3252 05:58:48.344265
3253 05:58:48.344887 Set Vref, RX VrefLevel [Byte0]: 56
3254 05:58:48.347791 [Byte1]: 56
3255 05:58:48.351907
3256 05:58:48.352364 Set Vref, RX VrefLevel [Byte0]: 57
3257 05:58:48.355364 [Byte1]: 57
3258 05:58:48.360160
3259 05:58:48.360619 Set Vref, RX VrefLevel [Byte0]: 58
3260 05:58:48.363156 [Byte1]: 58
3261 05:58:48.368488
3262 05:58:48.369113 Set Vref, RX VrefLevel [Byte0]: 59
3263 05:58:48.371402 [Byte1]: 59
3264 05:58:48.376088
3265 05:58:48.376915 Set Vref, RX VrefLevel [Byte0]: 60
3266 05:58:48.379603 [Byte1]: 60
3267 05:58:48.384318
3268 05:58:48.384933 Set Vref, RX VrefLevel [Byte0]: 61
3269 05:58:48.387444 [Byte1]: 61
3270 05:58:48.392222
3271 05:58:48.392839 Set Vref, RX VrefLevel [Byte0]: 62
3272 05:58:48.395360 [Byte1]: 62
3273 05:58:48.399924
3274 05:58:48.400523 Set Vref, RX VrefLevel [Byte0]: 63
3275 05:58:48.403000 [Byte1]: 63
3276 05:58:48.408042
3277 05:58:48.408497 Set Vref, RX VrefLevel [Byte0]: 64
3278 05:58:48.411234 [Byte1]: 64
3279 05:58:48.415984
3280 05:58:48.416552 Set Vref, RX VrefLevel [Byte0]: 65
3281 05:58:48.419252 [Byte1]: 65
3282 05:58:48.424226
3283 05:58:48.424825 Set Vref, RX VrefLevel [Byte0]: 66
3284 05:58:48.426849 [Byte1]: 66
3285 05:58:48.431916
3286 05:58:48.432470 Set Vref, RX VrefLevel [Byte0]: 67
3287 05:58:48.434814 [Byte1]: 67
3288 05:58:48.440343
3289 05:58:48.440926 Final RX Vref Byte 0 = 52 to rank0
3290 05:58:48.442982 Final RX Vref Byte 1 = 50 to rank0
3291 05:58:48.446450 Final RX Vref Byte 0 = 52 to rank1
3292 05:58:48.449648 Final RX Vref Byte 1 = 50 to rank1==
3293 05:58:48.452838 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 05:58:48.459545 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3295 05:58:48.460031 ==
3296 05:58:48.460451 DQS Delay:
3297 05:58:48.460852 DQS0 = 0, DQS1 = 0
3298 05:58:48.462694 DQM Delay:
3299 05:58:48.463188 DQM0 = 115, DQM1 = 106
3300 05:58:48.466186 DQ Delay:
3301 05:58:48.469615 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3302 05:58:48.473300 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =112
3303 05:58:48.476596 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3304 05:58:48.479448 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3305 05:58:48.479910
3306 05:58:48.480266
3307 05:58:48.486083 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3308 05:58:48.489561 CH1 RK0: MR19=404, MR18=1717
3309 05:58:48.496869 CH1_RK0: MR19=0x404, MR18=0x1717, DQSOSC=401, MR23=63, INC=40, DEC=27
3310 05:58:48.497426
3311 05:58:48.499707 ----->DramcWriteLeveling(PI) begin...
3312 05:58:48.500262 ==
3313 05:58:48.503129 Dram Type= 6, Freq= 0, CH_1, rank 1
3314 05:58:48.506652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3315 05:58:48.507209 ==
3316 05:58:48.509958 Write leveling (Byte 0): 21 => 21
3317 05:58:48.513134 Write leveling (Byte 1): 21 => 21
3318 05:58:48.516486 DramcWriteLeveling(PI) end<-----
3319 05:58:48.517100
3320 05:58:48.517465 ==
3321 05:58:48.519884 Dram Type= 6, Freq= 0, CH_1, rank 1
3322 05:58:48.526253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3323 05:58:48.526813 ==
3324 05:58:48.527173 [Gating] SW mode calibration
3325 05:58:48.536814 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3326 05:58:48.539878 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3327 05:58:48.542940 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3328 05:58:48.549515 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3329 05:58:48.552817 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3330 05:58:48.556330 0 11 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
3331 05:58:48.562680 0 11 16 | B1->B0 | 3333 2323 | 0 0 | (1 0) (0 0)
3332 05:58:48.566189 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3333 05:58:48.569534 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3334 05:58:48.575590 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3335 05:58:48.579603 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3336 05:58:48.582623 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3337 05:58:48.589404 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3338 05:58:48.592764 0 12 12 | B1->B0 | 2424 3c3c | 0 0 | (0 0) (0 0)
3339 05:58:48.596146 0 12 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
3340 05:58:48.602634 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3341 05:58:48.605982 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3342 05:58:48.609471 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3343 05:58:48.616466 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3344 05:58:48.619139 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3345 05:58:48.623028 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3346 05:58:48.629659 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3347 05:58:48.633413 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3348 05:58:48.636054 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3349 05:58:48.642973 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 05:58:48.646499 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 05:58:48.649502 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 05:58:48.652573 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 05:58:48.658918 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 05:58:48.662446 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 05:58:48.665833 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 05:58:48.672897 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 05:58:48.675860 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 05:58:48.679290 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 05:58:48.685659 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 05:58:48.689034 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 05:58:48.692674 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 05:58:48.699087 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3363 05:58:48.702494 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3364 05:58:48.705881 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3365 05:58:48.709298 Total UI for P1: 0, mck2ui 16
3366 05:58:48.712294 best dqsien dly found for B0: ( 0, 15, 14)
3367 05:58:48.719038 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3368 05:58:48.719583 Total UI for P1: 0, mck2ui 16
3369 05:58:48.725665 best dqsien dly found for B1: ( 0, 15, 18)
3370 05:58:48.729492 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3371 05:58:48.732381 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3372 05:58:48.732943
3373 05:58:48.735697 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3374 05:58:48.739436 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3375 05:58:48.742607 [Gating] SW calibration Done
3376 05:58:48.743039 ==
3377 05:58:48.745628 Dram Type= 6, Freq= 0, CH_1, rank 1
3378 05:58:48.748797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3379 05:58:48.749210 ==
3380 05:58:48.752399 RX Vref Scan: 0
3381 05:58:48.752852
3382 05:58:48.753178 RX Vref 0 -> 0, step: 1
3383 05:58:48.753477
3384 05:58:48.755562 RX Delay -40 -> 252, step: 8
3385 05:58:48.759177 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3386 05:58:48.765477 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3387 05:58:48.768800 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3388 05:58:48.772421 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3389 05:58:48.775483 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3390 05:58:48.779078 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3391 05:58:48.785610 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3392 05:58:48.788979 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3393 05:58:48.792795 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3394 05:58:48.796057 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
3395 05:58:48.799523 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3396 05:58:48.805454 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3397 05:58:48.808889 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3398 05:58:48.812345 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3399 05:58:48.816030 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3400 05:58:48.819064 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3401 05:58:48.819624 ==
3402 05:58:48.822099 Dram Type= 6, Freq= 0, CH_1, rank 1
3403 05:58:48.829559 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3404 05:58:48.830115 ==
3405 05:58:48.830471 DQS Delay:
3406 05:58:48.832288 DQS0 = 0, DQS1 = 0
3407 05:58:48.832880 DQM Delay:
3408 05:58:48.835706 DQM0 = 116, DQM1 = 104
3409 05:58:48.836260 DQ Delay:
3410 05:58:48.838759 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3411 05:58:48.842211 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3412 05:58:48.845452 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
3413 05:58:48.849041 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3414 05:58:48.849588
3415 05:58:48.849940
3416 05:58:48.850264 ==
3417 05:58:48.852503 Dram Type= 6, Freq= 0, CH_1, rank 1
3418 05:58:48.858556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3419 05:58:48.859110 ==
3420 05:58:48.859467
3421 05:58:48.859792
3422 05:58:48.860105 TX Vref Scan disable
3423 05:58:48.861921 == TX Byte 0 ==
3424 05:58:48.865238 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3425 05:58:48.868594 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3426 05:58:48.871986 == TX Byte 1 ==
3427 05:58:48.875580 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3428 05:58:48.879015 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3429 05:58:48.881857 ==
3430 05:58:48.885550 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 05:58:48.888991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3432 05:58:48.889541 ==
3433 05:58:48.899807 TX Vref=22, minBit 1, minWin=25, winSum=420
3434 05:58:48.902752 TX Vref=24, minBit 9, minWin=25, winSum=424
3435 05:58:48.906391 TX Vref=26, minBit 11, minWin=25, winSum=429
3436 05:58:48.909540 TX Vref=28, minBit 8, minWin=26, winSum=433
3437 05:58:48.912645 TX Vref=30, minBit 9, minWin=26, winSum=431
3438 05:58:48.919617 TX Vref=32, minBit 0, minWin=26, winSum=434
3439 05:58:48.922860 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 32
3440 05:58:48.923415
3441 05:58:48.926500 Final TX Range 1 Vref 32
3442 05:58:48.927051
3443 05:58:48.927406 ==
3444 05:58:48.929911 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 05:58:48.933012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3446 05:58:48.933563 ==
3447 05:58:48.933923
3448 05:58:48.936025
3449 05:58:48.936476 TX Vref Scan disable
3450 05:58:48.939308 == TX Byte 0 ==
3451 05:58:48.942516 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3452 05:58:48.945997 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3453 05:58:48.949358 == TX Byte 1 ==
3454 05:58:48.952761 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3455 05:58:48.955867 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3456 05:58:48.956331
3457 05:58:48.959430 [DATLAT]
3458 05:58:48.959891 Freq=1200, CH1 RK1
3459 05:58:48.960252
3460 05:58:48.962528 DATLAT Default: 0xc
3461 05:58:48.962990 0, 0xFFFF, sum = 0
3462 05:58:48.966191 1, 0xFFFF, sum = 0
3463 05:58:48.966658 2, 0xFFFF, sum = 0
3464 05:58:48.969381 3, 0xFFFF, sum = 0
3465 05:58:48.969845 4, 0xFFFF, sum = 0
3466 05:58:48.972639 5, 0xFFFF, sum = 0
3467 05:58:48.973139 6, 0xFFFF, sum = 0
3468 05:58:48.976429 7, 0xFFFF, sum = 0
3469 05:58:48.976962 8, 0xFFFF, sum = 0
3470 05:58:48.979874 9, 0xFFFF, sum = 0
3471 05:58:48.982856 10, 0xFFFF, sum = 0
3472 05:58:48.983392 11, 0x0, sum = 1
3473 05:58:48.983759 12, 0x0, sum = 2
3474 05:58:48.986026 13, 0x0, sum = 3
3475 05:58:48.986491 14, 0x0, sum = 4
3476 05:58:48.989422 best_step = 12
3477 05:58:48.989879
3478 05:58:48.990237 ==
3479 05:58:48.993158 Dram Type= 6, Freq= 0, CH_1, rank 1
3480 05:58:48.996329 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3481 05:58:48.996937 ==
3482 05:58:48.999552 RX Vref Scan: 0
3483 05:58:49.000108
3484 05:58:49.000466 RX Vref 0 -> 0, step: 1
3485 05:58:49.000881
3486 05:58:49.002860 RX Delay -29 -> 252, step: 4
3487 05:58:49.009814 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3488 05:58:49.013426 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3489 05:58:49.016557 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3490 05:58:49.019923 iDelay=199, Bit 3, Center 110 (43 ~ 178) 136
3491 05:58:49.023385 iDelay=199, Bit 4, Center 112 (43 ~ 182) 140
3492 05:58:49.029765 iDelay=199, Bit 5, Center 126 (55 ~ 198) 144
3493 05:58:49.032987 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3494 05:58:49.036429 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3495 05:58:49.040330 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3496 05:58:49.043439 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3497 05:58:49.049780 iDelay=199, Bit 10, Center 108 (43 ~ 174) 132
3498 05:58:49.053049 iDelay=199, Bit 11, Center 96 (31 ~ 162) 132
3499 05:58:49.056675 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3500 05:58:49.059698 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3501 05:58:49.063246 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3502 05:58:49.069878 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3503 05:58:49.070421 ==
3504 05:58:49.073179 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 05:58:49.076418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3506 05:58:49.076921 ==
3507 05:58:49.077286 DQS Delay:
3508 05:58:49.079972 DQS0 = 0, DQS1 = 0
3509 05:58:49.080531 DQM Delay:
3510 05:58:49.083075 DQM0 = 114, DQM1 = 103
3511 05:58:49.083613 DQ Delay:
3512 05:58:49.086154 DQ0 =114, DQ1 =110, DQ2 =108, DQ3 =110
3513 05:58:49.089839 DQ4 =112, DQ5 =126, DQ6 =122, DQ7 =112
3514 05:58:49.093367 DQ8 =86, DQ9 =92, DQ10 =108, DQ11 =96
3515 05:58:49.096631 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3516 05:58:49.097245
3517 05:58:49.097614
3518 05:58:49.106557 [DQSOSCAuto] RK1, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3519 05:58:49.110162 CH1 RK1: MR19=404, MR18=808
3520 05:58:49.113516 CH1_RK1: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
3521 05:58:49.116195 [RxdqsGatingPostProcess] freq 1200
3522 05:58:49.123052 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3523 05:58:49.126861 Pre-setting of DQS Precalculation
3524 05:58:49.129621 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3525 05:58:49.139972 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3526 05:58:49.146659 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3527 05:58:49.147234
3528 05:58:49.147596
3529 05:58:49.149430 [Calibration Summary] 2400 Mbps
3530 05:58:49.149896 CH 0, Rank 0
3531 05:58:49.152930 SW Impedance : PASS
3532 05:58:49.153537 DUTY Scan : NO K
3533 05:58:49.155993 ZQ Calibration : PASS
3534 05:58:49.159627 Jitter Meter : NO K
3535 05:58:49.160089 CBT Training : PASS
3536 05:58:49.162528 Write leveling : PASS
3537 05:58:49.166389 RX DQS gating : PASS
3538 05:58:49.166979 RX DQ/DQS(RDDQC) : PASS
3539 05:58:49.169280 TX DQ/DQS : PASS
3540 05:58:49.173285 RX DATLAT : PASS
3541 05:58:49.173968 RX DQ/DQS(Engine): PASS
3542 05:58:49.176339 TX OE : NO K
3543 05:58:49.176999 All Pass.
3544 05:58:49.177373
3545 05:58:49.179557 CH 0, Rank 1
3546 05:58:49.180015 SW Impedance : PASS
3547 05:58:49.182925 DUTY Scan : NO K
3548 05:58:49.185724 ZQ Calibration : PASS
3549 05:58:49.186188 Jitter Meter : NO K
3550 05:58:49.189186 CBT Training : PASS
3551 05:58:49.189680 Write leveling : PASS
3552 05:58:49.192583 RX DQS gating : PASS
3553 05:58:49.195990 RX DQ/DQS(RDDQC) : PASS
3554 05:58:49.196599 TX DQ/DQS : PASS
3555 05:58:49.199207 RX DATLAT : PASS
3556 05:58:49.202598 RX DQ/DQS(Engine): PASS
3557 05:58:49.203157 TX OE : NO K
3558 05:58:49.205983 All Pass.
3559 05:58:49.206538
3560 05:58:49.206898 CH 1, Rank 0
3561 05:58:49.209036 SW Impedance : PASS
3562 05:58:49.209499 DUTY Scan : NO K
3563 05:58:49.212377 ZQ Calibration : PASS
3564 05:58:49.215767 Jitter Meter : NO K
3565 05:58:49.216322 CBT Training : PASS
3566 05:58:49.219225 Write leveling : PASS
3567 05:58:49.222600 RX DQS gating : PASS
3568 05:58:49.223065 RX DQ/DQS(RDDQC) : PASS
3569 05:58:49.225757 TX DQ/DQS : PASS
3570 05:58:49.228988 RX DATLAT : PASS
3571 05:58:49.229454 RX DQ/DQS(Engine): PASS
3572 05:58:49.232852 TX OE : NO K
3573 05:58:49.233401 All Pass.
3574 05:58:49.233764
3575 05:58:49.235589 CH 1, Rank 1
3576 05:58:49.236051 SW Impedance : PASS
3577 05:58:49.238968 DUTY Scan : NO K
3578 05:58:49.242362 ZQ Calibration : PASS
3579 05:58:49.242824 Jitter Meter : NO K
3580 05:58:49.246261 CBT Training : PASS
3581 05:58:49.246821 Write leveling : PASS
3582 05:58:49.249063 RX DQS gating : PASS
3583 05:58:49.252440 RX DQ/DQS(RDDQC) : PASS
3584 05:58:49.253118 TX DQ/DQS : PASS
3585 05:58:49.255720 RX DATLAT : PASS
3586 05:58:49.258840 RX DQ/DQS(Engine): PASS
3587 05:58:49.259304 TX OE : NO K
3588 05:58:49.262189 All Pass.
3589 05:58:49.262652
3590 05:58:49.263008 DramC Write-DBI off
3591 05:58:49.265365 PER_BANK_REFRESH: Hybrid Mode
3592 05:58:49.265827 TX_TRACKING: ON
3593 05:58:49.275680 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3594 05:58:49.279052 [FAST_K] Save calibration result to emmc
3595 05:58:49.282272 dramc_set_vcore_voltage set vcore to 650000
3596 05:58:49.285658 Read voltage for 600, 5
3597 05:58:49.286191 Vio18 = 0
3598 05:58:49.288927 Vcore = 650000
3599 05:58:49.289389 Vdram = 0
3600 05:58:49.289750 Vddq = 0
3601 05:58:49.292522 Vmddr = 0
3602 05:58:49.295635 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3603 05:58:49.302139 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3604 05:58:49.302602 MEM_TYPE=3, freq_sel=19
3605 05:58:49.305745 sv_algorithm_assistance_LP4_1600
3606 05:58:49.308968 ============ PULL DRAM RESETB DOWN ============
3607 05:58:49.315467 ========== PULL DRAM RESETB DOWN end =========
3608 05:58:49.319014 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3609 05:58:49.322546 ===================================
3610 05:58:49.325501 LPDDR4 DRAM CONFIGURATION
3611 05:58:49.328945 ===================================
3612 05:58:49.329566 EX_ROW_EN[0] = 0x0
3613 05:58:49.332347 EX_ROW_EN[1] = 0x0
3614 05:58:49.335596 LP4Y_EN = 0x0
3615 05:58:49.336155 WORK_FSP = 0x0
3616 05:58:49.339099 WL = 0x2
3617 05:58:49.339661 RL = 0x2
3618 05:58:49.342589 BL = 0x2
3619 05:58:49.343054 RPST = 0x0
3620 05:58:49.345607 RD_PRE = 0x0
3621 05:58:49.346083 WR_PRE = 0x1
3622 05:58:49.348689 WR_PST = 0x0
3623 05:58:49.349187 DBI_WR = 0x0
3624 05:58:49.351974 DBI_RD = 0x0
3625 05:58:49.352495 OTF = 0x1
3626 05:58:49.355604 ===================================
3627 05:58:49.358633 ===================================
3628 05:58:49.361719 ANA top config
3629 05:58:49.365430 ===================================
3630 05:58:49.365950 DLL_ASYNC_EN = 0
3631 05:58:49.368515 ALL_SLAVE_EN = 1
3632 05:58:49.372302 NEW_RANK_MODE = 1
3633 05:58:49.375589 DLL_IDLE_MODE = 1
3634 05:58:49.378807 LP45_APHY_COMB_EN = 1
3635 05:58:49.379274 TX_ODT_DIS = 1
3636 05:58:49.381788 NEW_8X_MODE = 1
3637 05:58:49.384984 ===================================
3638 05:58:49.388190 ===================================
3639 05:58:49.391622 data_rate = 1200
3640 05:58:49.395195 CKR = 1
3641 05:58:49.398259 DQ_P2S_RATIO = 8
3642 05:58:49.401775 ===================================
3643 05:58:49.402240 CA_P2S_RATIO = 8
3644 05:58:49.405159 DQ_CA_OPEN = 0
3645 05:58:49.408341 DQ_SEMI_OPEN = 0
3646 05:58:49.411595 CA_SEMI_OPEN = 0
3647 05:58:49.415033 CA_FULL_RATE = 0
3648 05:58:49.418265 DQ_CKDIV4_EN = 1
3649 05:58:49.418729 CA_CKDIV4_EN = 1
3650 05:58:49.421579 CA_PREDIV_EN = 0
3651 05:58:49.425123 PH8_DLY = 0
3652 05:58:49.428486 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3653 05:58:49.431809 DQ_AAMCK_DIV = 4
3654 05:58:49.434837 CA_AAMCK_DIV = 4
3655 05:58:49.435415 CA_ADMCK_DIV = 4
3656 05:58:49.437829 DQ_TRACK_CA_EN = 0
3657 05:58:49.441353 CA_PICK = 600
3658 05:58:49.444579 CA_MCKIO = 600
3659 05:58:49.447789 MCKIO_SEMI = 0
3660 05:58:49.451525 PLL_FREQ = 2288
3661 05:58:49.454215 DQ_UI_PI_RATIO = 32
3662 05:58:49.457769 CA_UI_PI_RATIO = 0
3663 05:58:49.461039 ===================================
3664 05:58:49.464646 ===================================
3665 05:58:49.465175 memory_type:LPDDR4
3666 05:58:49.467783 GP_NUM : 10
3667 05:58:49.468264 SRAM_EN : 1
3668 05:58:49.471110 MD32_EN : 0
3669 05:58:49.474598 ===================================
3670 05:58:49.477843 [ANA_INIT] >>>>>>>>>>>>>>
3671 05:58:49.481665 <<<<<< [CONFIGURE PHASE]: ANA_TX
3672 05:58:49.484356 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3673 05:58:49.487818 ===================================
3674 05:58:49.491230 data_rate = 1200,PCW = 0X5800
3675 05:58:49.494245 ===================================
3676 05:58:49.497393 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3677 05:58:49.500822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3678 05:58:49.507397 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3679 05:58:49.510813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3680 05:58:49.513855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3681 05:58:49.517579 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3682 05:58:49.520953 [ANA_INIT] flow start
3683 05:58:49.523798 [ANA_INIT] PLL >>>>>>>>
3684 05:58:49.524362 [ANA_INIT] PLL <<<<<<<<
3685 05:58:49.527402 [ANA_INIT] MIDPI >>>>>>>>
3686 05:58:49.530514 [ANA_INIT] MIDPI <<<<<<<<
3687 05:58:49.534226 [ANA_INIT] DLL >>>>>>>>
3688 05:58:49.534802 [ANA_INIT] flow end
3689 05:58:49.537133 ============ LP4 DIFF to SE enter ============
3690 05:58:49.543557 ============ LP4 DIFF to SE exit ============
3691 05:58:49.544115 [ANA_INIT] <<<<<<<<<<<<<
3692 05:58:49.547403 [Flow] Enable top DCM control >>>>>
3693 05:58:49.550332 [Flow] Enable top DCM control <<<<<
3694 05:58:49.553419 Enable DLL master slave shuffle
3695 05:58:49.560094 ==============================================================
3696 05:58:49.560563 Gating Mode config
3697 05:58:49.567002 ==============================================================
3698 05:58:49.570674 Config description:
3699 05:58:49.576892 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3700 05:58:49.586898 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3701 05:58:49.590526 SELPH_MODE 0: By rank 1: By Phase
3702 05:58:49.596988 ==============================================================
3703 05:58:49.600286 GAT_TRACK_EN = 1
3704 05:58:49.600907 RX_GATING_MODE = 2
3705 05:58:49.603650 RX_GATING_TRACK_MODE = 2
3706 05:58:49.606722 SELPH_MODE = 1
3707 05:58:49.610076 PICG_EARLY_EN = 1
3708 05:58:49.613440 VALID_LAT_VALUE = 1
3709 05:58:49.619940 ==============================================================
3710 05:58:49.623527 Enter into Gating configuration >>>>
3711 05:58:49.626502 Exit from Gating configuration <<<<
3712 05:58:49.629910 Enter into DVFS_PRE_config >>>>>
3713 05:58:49.639844 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3714 05:58:49.643269 Exit from DVFS_PRE_config <<<<<
3715 05:58:49.646350 Enter into PICG configuration >>>>
3716 05:58:49.649458 Exit from PICG configuration <<<<
3717 05:58:49.653147 [RX_INPUT] configuration >>>>>
3718 05:58:49.656348 [RX_INPUT] configuration <<<<<
3719 05:58:49.660045 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3720 05:58:49.666234 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3721 05:58:49.672802 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3722 05:58:49.679180 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3723 05:58:49.682784 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3724 05:58:49.689272 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3725 05:58:49.692689 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3726 05:58:49.699407 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3727 05:58:49.702735 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3728 05:58:49.705784 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3729 05:58:49.709030 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3730 05:58:49.715872 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3731 05:58:49.719130 ===================================
3732 05:58:49.722501 LPDDR4 DRAM CONFIGURATION
3733 05:58:49.725660 ===================================
3734 05:58:49.726121 EX_ROW_EN[0] = 0x0
3735 05:58:49.729159 EX_ROW_EN[1] = 0x0
3736 05:58:49.729714 LP4Y_EN = 0x0
3737 05:58:49.732383 WORK_FSP = 0x0
3738 05:58:49.732986 WL = 0x2
3739 05:58:49.735901 RL = 0x2
3740 05:58:49.736471 BL = 0x2
3741 05:58:49.739210 RPST = 0x0
3742 05:58:49.739762 RD_PRE = 0x0
3743 05:58:49.742467 WR_PRE = 0x1
3744 05:58:49.743019 WR_PST = 0x0
3745 05:58:49.745532 DBI_WR = 0x0
3746 05:58:49.745992 DBI_RD = 0x0
3747 05:58:49.749425 OTF = 0x1
3748 05:58:49.752069 ===================================
3749 05:58:49.755222 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3750 05:58:49.759015 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3751 05:58:49.765315 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3752 05:58:49.768855 ===================================
3753 05:58:49.769321 LPDDR4 DRAM CONFIGURATION
3754 05:58:49.771909 ===================================
3755 05:58:49.775319 EX_ROW_EN[0] = 0x10
3756 05:58:49.778832 EX_ROW_EN[1] = 0x0
3757 05:58:49.779293 LP4Y_EN = 0x0
3758 05:58:49.781667 WORK_FSP = 0x0
3759 05:58:49.781989 WL = 0x2
3760 05:58:49.785034 RL = 0x2
3761 05:58:49.785359 BL = 0x2
3762 05:58:49.788733 RPST = 0x0
3763 05:58:49.789165 RD_PRE = 0x0
3764 05:58:49.791821 WR_PRE = 0x1
3765 05:58:49.792170 WR_PST = 0x0
3766 05:58:49.795386 DBI_WR = 0x0
3767 05:58:49.795819 DBI_RD = 0x0
3768 05:58:49.798344 OTF = 0x1
3769 05:58:49.801706 ===================================
3770 05:58:49.808430 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3771 05:58:49.811769 nWR fixed to 30
3772 05:58:49.815182 [ModeRegInit_LP4] CH0 RK0
3773 05:58:49.815602 [ModeRegInit_LP4] CH0 RK1
3774 05:58:49.818020 [ModeRegInit_LP4] CH1 RK0
3775 05:58:49.821724 [ModeRegInit_LP4] CH1 RK1
3776 05:58:49.822147 match AC timing 16
3777 05:58:49.828165 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3778 05:58:49.831811 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3779 05:58:49.834960 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3780 05:58:49.841380 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3781 05:58:49.844943 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3782 05:58:49.845501 ==
3783 05:58:49.848196 Dram Type= 6, Freq= 0, CH_0, rank 0
3784 05:58:49.851619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3785 05:58:49.852172 ==
3786 05:58:49.857917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3787 05:58:49.864515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3788 05:58:49.868355 [CA 0] Center 36 (6~66) winsize 61
3789 05:58:49.871163 [CA 1] Center 35 (5~66) winsize 62
3790 05:58:49.874735 [CA 2] Center 34 (4~65) winsize 62
3791 05:58:49.878161 [CA 3] Center 34 (4~65) winsize 62
3792 05:58:49.880942 [CA 4] Center 33 (3~64) winsize 62
3793 05:58:49.884431 [CA 5] Center 33 (3~64) winsize 62
3794 05:58:49.884941
3795 05:58:49.887249 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3796 05:58:49.887710
3797 05:58:49.890886 [CATrainingPosCal] consider 1 rank data
3798 05:58:49.894556 u2DelayCellTimex100 = 270/100 ps
3799 05:58:49.898172 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3800 05:58:49.900953 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3801 05:58:49.904255 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3802 05:58:49.907441 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3803 05:58:49.913804 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3804 05:58:49.917093 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3805 05:58:49.917555
3806 05:58:49.920999 CA PerBit enable=1, Macro0, CA PI delay=33
3807 05:58:49.921560
3808 05:58:49.923843 [CBTSetCACLKResult] CA Dly = 33
3809 05:58:49.924400 CS Dly: 5 (0~36)
3810 05:58:49.924802 ==
3811 05:58:49.926957 Dram Type= 6, Freq= 0, CH_0, rank 1
3812 05:58:49.933820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3813 05:58:49.934379 ==
3814 05:58:49.937513 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3815 05:58:49.943714 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3816 05:58:49.947311 [CA 0] Center 36 (6~66) winsize 61
3817 05:58:49.950318 [CA 1] Center 35 (5~66) winsize 62
3818 05:58:49.953336 [CA 2] Center 34 (4~65) winsize 62
3819 05:58:49.956805 [CA 3] Center 34 (4~65) winsize 62
3820 05:58:49.960360 [CA 4] Center 33 (3~64) winsize 62
3821 05:58:49.963504 [CA 5] Center 33 (3~64) winsize 62
3822 05:58:49.964069
3823 05:58:49.966551 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3824 05:58:49.967016
3825 05:58:49.969852 [CATrainingPosCal] consider 2 rank data
3826 05:58:49.973393 u2DelayCellTimex100 = 270/100 ps
3827 05:58:49.976491 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3828 05:58:49.983251 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3829 05:58:49.986573 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3830 05:58:49.989670 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3831 05:58:49.993693 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3832 05:58:49.996450 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3833 05:58:49.996957
3834 05:58:49.999670 CA PerBit enable=1, Macro0, CA PI delay=33
3835 05:58:50.000132
3836 05:58:50.003105 [CBTSetCACLKResult] CA Dly = 33
3837 05:58:50.003569 CS Dly: 5 (0~37)
3838 05:58:50.006237
3839 05:58:50.009696 ----->DramcWriteLeveling(PI) begin...
3840 05:58:50.010251 ==
3841 05:58:50.013008 Dram Type= 6, Freq= 0, CH_0, rank 0
3842 05:58:50.016817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3843 05:58:50.017386 ==
3844 05:58:50.019871 Write leveling (Byte 0): 30 => 30
3845 05:58:50.022969 Write leveling (Byte 1): 30 => 30
3846 05:58:50.026312 DramcWriteLeveling(PI) end<-----
3847 05:58:50.026915
3848 05:58:50.027290 ==
3849 05:58:50.029419 Dram Type= 6, Freq= 0, CH_0, rank 0
3850 05:58:50.032791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3851 05:58:50.033440 ==
3852 05:58:50.036221 [Gating] SW mode calibration
3853 05:58:50.043438 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3854 05:58:50.049441 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3855 05:58:50.052563 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3856 05:58:50.056263 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3857 05:58:50.062454 0 5 8 | B1->B0 | 3232 3030 | 0 0 | (0 1) (0 1)
3858 05:58:50.065951 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3859 05:58:50.069064 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3860 05:58:50.076041 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3861 05:58:50.079038 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3862 05:58:50.082486 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3863 05:58:50.088883 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3864 05:58:50.092548 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3865 05:58:50.095493 0 6 8 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
3866 05:58:50.102572 0 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3867 05:58:50.105430 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3868 05:58:50.109274 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3869 05:58:50.115635 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3870 05:58:50.118897 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3871 05:58:50.122021 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3872 05:58:50.128916 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3873 05:58:50.132090 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3874 05:58:50.135537 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3875 05:58:50.142112 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 05:58:50.145657 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 05:58:50.148602 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 05:58:50.155072 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 05:58:50.158370 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 05:58:50.162089 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 05:58:50.167929 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 05:58:50.171495 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 05:58:50.174729 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 05:58:50.181425 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 05:58:50.185114 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 05:58:50.187791 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 05:58:50.194431 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 05:58:50.198107 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 05:58:50.201175 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3890 05:58:50.207831 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3891 05:58:50.208392 Total UI for P1: 0, mck2ui 16
3892 05:58:50.214788 best dqsien dly found for B0: ( 0, 9, 10)
3893 05:58:50.215344 Total UI for P1: 0, mck2ui 16
3894 05:58:50.217759 best dqsien dly found for B1: ( 0, 9, 10)
3895 05:58:50.221469 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3896 05:58:50.228437 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3897 05:58:50.229036
3898 05:58:50.231704 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3899 05:58:50.234543 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3900 05:58:50.237615 [Gating] SW calibration Done
3901 05:58:50.238172 ==
3902 05:58:50.240870 Dram Type= 6, Freq= 0, CH_0, rank 0
3903 05:58:50.244351 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3904 05:58:50.245053 ==
3905 05:58:50.248080 RX Vref Scan: 0
3906 05:58:50.248634
3907 05:58:50.249035 RX Vref 0 -> 0, step: 1
3908 05:58:50.249370
3909 05:58:50.250731 RX Delay -230 -> 252, step: 16
3910 05:58:50.254055 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3911 05:58:50.261447 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3912 05:58:50.264495 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3913 05:58:50.267685 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3914 05:58:50.270698 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3915 05:58:50.277173 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3916 05:58:50.281151 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3917 05:58:50.284063 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3918 05:58:50.287242 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3919 05:58:50.293635 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3920 05:58:50.297287 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3921 05:58:50.300415 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3922 05:58:50.303960 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3923 05:58:50.310836 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3924 05:58:50.314080 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3925 05:58:50.317156 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3926 05:58:50.317617 ==
3927 05:58:50.320228 Dram Type= 6, Freq= 0, CH_0, rank 0
3928 05:58:50.323697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3929 05:58:50.324264 ==
3930 05:58:50.327050 DQS Delay:
3931 05:58:50.327603 DQS0 = 0, DQS1 = 0
3932 05:58:50.330442 DQM Delay:
3933 05:58:50.330996 DQM0 = 38, DQM1 = 33
3934 05:58:50.331363 DQ Delay:
3935 05:58:50.334076 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3936 05:58:50.337089 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3937 05:58:50.340601 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3938 05:58:50.344108 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3939 05:58:50.344665
3940 05:58:50.345223
3941 05:58:50.346852 ==
3942 05:58:50.350270 Dram Type= 6, Freq= 0, CH_0, rank 0
3943 05:58:50.353531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3944 05:58:50.353996 ==
3945 05:58:50.354356
3946 05:58:50.354685
3947 05:58:50.357148 TX Vref Scan disable
3948 05:58:50.357726 == TX Byte 0 ==
3949 05:58:50.363092 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3950 05:58:50.366942 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3951 05:58:50.367501 == TX Byte 1 ==
3952 05:58:50.373153 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3953 05:58:50.376680 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3954 05:58:50.377274 ==
3955 05:58:50.379832 Dram Type= 6, Freq= 0, CH_0, rank 0
3956 05:58:50.382872 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3957 05:58:50.383334 ==
3958 05:58:50.383693
3959 05:58:50.384019
3960 05:58:50.386258 TX Vref Scan disable
3961 05:58:50.389464 == TX Byte 0 ==
3962 05:58:50.392784 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3963 05:58:50.396386 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3964 05:58:50.399263 == TX Byte 1 ==
3965 05:58:50.403017 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3966 05:58:50.405928 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3967 05:58:50.406392
3968 05:58:50.409431 [DATLAT]
3969 05:58:50.409983 Freq=600, CH0 RK0
3970 05:58:50.410346
3971 05:58:50.412619 DATLAT Default: 0x9
3972 05:58:50.413113 0, 0xFFFF, sum = 0
3973 05:58:50.415771 1, 0xFFFF, sum = 0
3974 05:58:50.416237 2, 0xFFFF, sum = 0
3975 05:58:50.419892 3, 0xFFFF, sum = 0
3976 05:58:50.420458 4, 0xFFFF, sum = 0
3977 05:58:50.422471 5, 0xFFFF, sum = 0
3978 05:58:50.422938 6, 0xFFFF, sum = 0
3979 05:58:50.425919 7, 0x0, sum = 1
3980 05:58:50.426483 8, 0x0, sum = 2
3981 05:58:50.429446 9, 0x0, sum = 3
3982 05:58:50.430003 10, 0x0, sum = 4
3983 05:58:50.432602 best_step = 8
3984 05:58:50.433230
3985 05:58:50.433621 ==
3986 05:58:50.436108 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 05:58:50.439642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3988 05:58:50.440106 ==
3989 05:58:50.442541 RX Vref Scan: 1
3990 05:58:50.442999
3991 05:58:50.443356 RX Vref 0 -> 0, step: 1
3992 05:58:50.443690
3993 05:58:50.445748 RX Delay -195 -> 252, step: 8
3994 05:58:50.446206
3995 05:58:50.449164 Set Vref, RX VrefLevel [Byte0]: 55
3996 05:58:50.452625 [Byte1]: 49
3997 05:58:50.456049
3998 05:58:50.456505 Final RX Vref Byte 0 = 55 to rank0
3999 05:58:50.459583 Final RX Vref Byte 1 = 49 to rank0
4000 05:58:50.462560 Final RX Vref Byte 0 = 55 to rank1
4001 05:58:50.465887 Final RX Vref Byte 1 = 49 to rank1==
4002 05:58:50.469434 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 05:58:50.476256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4004 05:58:50.476861 ==
4005 05:58:50.477230 DQS Delay:
4006 05:58:50.479618 DQS0 = 0, DQS1 = 0
4007 05:58:50.480171 DQM Delay:
4008 05:58:50.480530 DQM0 = 39, DQM1 = 30
4009 05:58:50.482905 DQ Delay:
4010 05:58:50.486221 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4011 05:58:50.489303 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4012 05:58:50.492540 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4013 05:58:50.495913 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4014 05:58:50.496374
4015 05:58:50.496772
4016 05:58:50.502765 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a4a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
4017 05:58:50.505957 CH0 RK0: MR19=808, MR18=4A4A
4018 05:58:50.512675 CH0_RK0: MR19=0x808, MR18=0x4A4A, DQSOSC=395, MR23=63, INC=168, DEC=112
4019 05:58:50.513288
4020 05:58:50.515645 ----->DramcWriteLeveling(PI) begin...
4021 05:58:50.516204 ==
4022 05:58:50.518863 Dram Type= 6, Freq= 0, CH_0, rank 1
4023 05:58:50.522235 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4024 05:58:50.522698 ==
4025 05:58:50.525666 Write leveling (Byte 0): 30 => 30
4026 05:58:50.529161 Write leveling (Byte 1): 30 => 30
4027 05:58:50.532264 DramcWriteLeveling(PI) end<-----
4028 05:58:50.532907
4029 05:58:50.533331 ==
4030 05:58:50.535466 Dram Type= 6, Freq= 0, CH_0, rank 1
4031 05:58:50.538462 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4032 05:58:50.541882 ==
4033 05:58:50.542342 [Gating] SW mode calibration
4034 05:58:50.551994 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4035 05:58:50.555170 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4036 05:58:50.558497 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 05:58:50.564978 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 05:58:50.568586 0 5 8 | B1->B0 | 3434 3030 | 0 1 | (0 0) (0 0)
4039 05:58:50.571760 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4040 05:58:50.578459 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 05:58:50.581355 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 05:58:50.584984 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 05:58:50.591683 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 05:58:50.594851 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 05:58:50.598246 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 05:58:50.605223 0 6 8 | B1->B0 | 2e2e 3131 | 1 1 | (0 0) (0 0)
4047 05:58:50.608055 0 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4048 05:58:50.611706 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 05:58:50.618273 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 05:58:50.621310 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 05:58:50.625043 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 05:58:50.631374 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 05:58:50.635127 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 05:58:50.637775 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4055 05:58:50.644594 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 05:58:50.648163 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 05:58:50.651313 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 05:58:50.657853 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 05:58:50.661042 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 05:58:50.664444 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 05:58:50.670745 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 05:58:50.674325 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 05:58:50.677530 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 05:58:50.684363 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 05:58:50.687618 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 05:58:50.690800 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 05:58:50.697300 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 05:58:50.700765 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 05:58:50.704370 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 05:58:50.710663 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4071 05:58:50.714629 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 05:58:50.717746 Total UI for P1: 0, mck2ui 16
4073 05:58:50.720739 best dqsien dly found for B0: ( 0, 9, 8)
4074 05:58:50.724203 Total UI for P1: 0, mck2ui 16
4075 05:58:50.727318 best dqsien dly found for B1: ( 0, 9, 8)
4076 05:58:50.730416 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4077 05:58:50.733924 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4078 05:58:50.734382
4079 05:58:50.736970 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4080 05:58:50.740483 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4081 05:58:50.743688 [Gating] SW calibration Done
4082 05:58:50.744244 ==
4083 05:58:50.747167 Dram Type= 6, Freq= 0, CH_0, rank 1
4084 05:58:50.750516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4085 05:58:50.751093 ==
4086 05:58:50.753462 RX Vref Scan: 0
4087 05:58:50.753920
4088 05:58:50.757302 RX Vref 0 -> 0, step: 1
4089 05:58:50.757888
4090 05:58:50.758244 RX Delay -230 -> 252, step: 16
4091 05:58:50.763837 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4092 05:58:50.766762 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4093 05:58:50.770412 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4094 05:58:50.773385 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4095 05:58:50.780259 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4096 05:58:50.783529 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4097 05:58:50.786936 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4098 05:58:50.789877 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4099 05:58:50.793295 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4100 05:58:50.799954 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4101 05:58:50.803404 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4102 05:58:50.806840 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4103 05:58:50.810229 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4104 05:58:50.816690 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4105 05:58:50.820503 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4106 05:58:50.823358 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4107 05:58:50.823923 ==
4108 05:58:50.826274 Dram Type= 6, Freq= 0, CH_0, rank 1
4109 05:58:50.833155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4110 05:58:50.833726 ==
4111 05:58:50.834091 DQS Delay:
4112 05:58:50.834425 DQS0 = 0, DQS1 = 0
4113 05:58:50.836531 DQM Delay:
4114 05:58:50.837125 DQM0 = 41, DQM1 = 33
4115 05:58:50.839955 DQ Delay:
4116 05:58:50.842981 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4117 05:58:50.846135 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4118 05:58:50.849548 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4119 05:58:50.853041 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4120 05:58:50.853616
4121 05:58:50.853977
4122 05:58:50.854307 ==
4123 05:58:50.856428 Dram Type= 6, Freq= 0, CH_0, rank 1
4124 05:58:50.859494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4125 05:58:50.860060 ==
4126 05:58:50.860421
4127 05:58:50.860818
4128 05:58:50.862961 TX Vref Scan disable
4129 05:58:50.863521 == TX Byte 0 ==
4130 05:58:50.869234 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4131 05:58:50.872961 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4132 05:58:50.875973 == TX Byte 1 ==
4133 05:58:50.879424 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4134 05:58:50.882413 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4135 05:58:50.882872 ==
4136 05:58:50.885745 Dram Type= 6, Freq= 0, CH_0, rank 1
4137 05:58:50.889311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4138 05:58:50.889885 ==
4139 05:58:50.892969
4140 05:58:50.893522
4141 05:58:50.893878 TX Vref Scan disable
4142 05:58:50.895908 == TX Byte 0 ==
4143 05:58:50.899700 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4144 05:58:50.905882 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4145 05:58:50.906463 == TX Byte 1 ==
4146 05:58:50.909084 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4147 05:58:50.916221 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4148 05:58:50.916875
4149 05:58:50.917249 [DATLAT]
4150 05:58:50.917583 Freq=600, CH0 RK1
4151 05:58:50.917905
4152 05:58:50.919237 DATLAT Default: 0x8
4153 05:58:50.919690 0, 0xFFFF, sum = 0
4154 05:58:50.922816 1, 0xFFFF, sum = 0
4155 05:58:50.925541 2, 0xFFFF, sum = 0
4156 05:58:50.926004 3, 0xFFFF, sum = 0
4157 05:58:50.929367 4, 0xFFFF, sum = 0
4158 05:58:50.929933 5, 0xFFFF, sum = 0
4159 05:58:50.932447 6, 0xFFFF, sum = 0
4160 05:58:50.933055 7, 0x0, sum = 1
4161 05:58:50.935766 8, 0x0, sum = 2
4162 05:58:50.936325 9, 0x0, sum = 3
4163 05:58:50.936689 10, 0x0, sum = 4
4164 05:58:50.938972 best_step = 8
4165 05:58:50.939527
4166 05:58:50.939885 ==
4167 05:58:50.942426 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 05:58:50.945482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4169 05:58:50.946042 ==
4170 05:58:50.949409 RX Vref Scan: 0
4171 05:58:50.949968
4172 05:58:50.950327 RX Vref 0 -> 0, step: 1
4173 05:58:50.950658
4174 05:58:50.951933 RX Delay -195 -> 252, step: 8
4175 05:58:50.959500 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4176 05:58:50.963489 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4177 05:58:50.966498 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4178 05:58:50.969891 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4179 05:58:50.976107 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4180 05:58:50.979760 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4181 05:58:50.982609 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4182 05:58:50.985783 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4183 05:58:50.992332 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4184 05:58:50.996492 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4185 05:58:50.999462 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4186 05:58:51.002711 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4187 05:58:51.009387 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4188 05:58:51.013191 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4189 05:58:51.016406 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4190 05:58:51.019350 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4191 05:58:51.019911 ==
4192 05:58:51.022532 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 05:58:51.029164 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4194 05:58:51.029740 ==
4195 05:58:51.030096 DQS Delay:
4196 05:58:51.032378 DQS0 = 0, DQS1 = 0
4197 05:58:51.032969 DQM Delay:
4198 05:58:51.033330 DQM0 = 40, DQM1 = 32
4199 05:58:51.035864 DQ Delay:
4200 05:58:51.039091 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4201 05:58:51.042465 DQ4 =48, DQ5 =28, DQ6 =48, DQ7 =48
4202 05:58:51.045620 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4203 05:58:51.048908 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4204 05:58:51.049361
4205 05:58:51.049714
4206 05:58:51.055903 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4207 05:58:51.058693 CH0 RK1: MR19=808, MR18=5F5F
4208 05:58:51.065440 CH0_RK1: MR19=0x808, MR18=0x5F5F, DQSOSC=391, MR23=63, INC=171, DEC=114
4209 05:58:51.068673 [RxdqsGatingPostProcess] freq 600
4210 05:58:51.072356 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4211 05:58:51.075414 Pre-setting of DQS Precalculation
4212 05:58:51.081915 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4213 05:58:51.082484 ==
4214 05:58:51.085583 Dram Type= 6, Freq= 0, CH_1, rank 0
4215 05:58:51.088506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4216 05:58:51.089094 ==
4217 05:58:51.095264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4218 05:58:51.101761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4219 05:58:51.105027 [CA 0] Center 35 (5~66) winsize 62
4220 05:58:51.108450 [CA 1] Center 35 (5~66) winsize 62
4221 05:58:51.111756 [CA 2] Center 33 (3~64) winsize 62
4222 05:58:51.115083 [CA 3] Center 33 (3~64) winsize 62
4223 05:58:51.118408 [CA 4] Center 33 (2~64) winsize 63
4224 05:58:51.121711 [CA 5] Center 33 (2~64) winsize 63
4225 05:58:51.122170
4226 05:58:51.124811 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4227 05:58:51.125282
4228 05:58:51.128307 [CATrainingPosCal] consider 1 rank data
4229 05:58:51.132020 u2DelayCellTimex100 = 270/100 ps
4230 05:58:51.134779 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4231 05:58:51.138272 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4232 05:58:51.141797 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4233 05:58:51.145050 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4234 05:58:51.148278 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4235 05:58:51.151963 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4236 05:58:51.152522
4237 05:58:51.157939 CA PerBit enable=1, Macro0, CA PI delay=33
4238 05:58:51.158504
4239 05:58:51.158864 [CBTSetCACLKResult] CA Dly = 33
4240 05:58:51.161640 CS Dly: 4 (0~35)
4241 05:58:51.162200 ==
4242 05:58:51.164864 Dram Type= 6, Freq= 0, CH_1, rank 1
4243 05:58:51.167945 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4244 05:58:51.168503 ==
4245 05:58:51.174313 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4246 05:58:51.180940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4247 05:58:51.184395 [CA 0] Center 35 (5~66) winsize 62
4248 05:58:51.187758 [CA 1] Center 35 (5~65) winsize 61
4249 05:58:51.191511 [CA 2] Center 33 (2~64) winsize 63
4250 05:58:51.194655 [CA 3] Center 33 (2~64) winsize 63
4251 05:58:51.198542 [CA 4] Center 32 (2~63) winsize 62
4252 05:58:51.201425 [CA 5] Center 32 (2~63) winsize 62
4253 05:58:51.201884
4254 05:58:51.204488 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4255 05:58:51.204983
4256 05:58:51.207893 [CATrainingPosCal] consider 2 rank data
4257 05:58:51.211153 u2DelayCellTimex100 = 270/100 ps
4258 05:58:51.214638 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4259 05:58:51.217778 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4260 05:58:51.221090 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4261 05:58:51.224381 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4262 05:58:51.227407 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4263 05:58:51.234208 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4264 05:58:51.234775
4265 05:58:51.237717 CA PerBit enable=1, Macro0, CA PI delay=32
4266 05:58:51.238313
4267 05:58:51.240662 [CBTSetCACLKResult] CA Dly = 32
4268 05:58:51.241160 CS Dly: 4 (0~36)
4269 05:58:51.241517
4270 05:58:51.244284 ----->DramcWriteLeveling(PI) begin...
4271 05:58:51.244927 ==
4272 05:58:51.247554 Dram Type= 6, Freq= 0, CH_1, rank 0
4273 05:58:51.251081 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4274 05:58:51.254300 ==
4275 05:58:51.254755 Write leveling (Byte 0): 29 => 29
4276 05:58:51.257409 Write leveling (Byte 1): 28 => 28
4277 05:58:51.260637 DramcWriteLeveling(PI) end<-----
4278 05:58:51.261124
4279 05:58:51.261481 ==
4280 05:58:51.264248 Dram Type= 6, Freq= 0, CH_1, rank 0
4281 05:58:51.270911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4282 05:58:51.271471 ==
4283 05:58:51.274090 [Gating] SW mode calibration
4284 05:58:51.280508 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4285 05:58:51.284248 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4286 05:58:51.290630 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4287 05:58:51.293790 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4288 05:58:51.296840 0 5 8 | B1->B0 | 2f2f 2828 | 1 1 | (1 1) (0 0)
4289 05:58:51.303760 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4290 05:58:51.306949 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4291 05:58:51.310396 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4292 05:58:51.317521 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4293 05:58:51.320620 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4294 05:58:51.323570 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4295 05:58:51.330473 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4296 05:58:51.333717 0 6 8 | B1->B0 | 3434 3b3b | 1 1 | (0 0) (0 0)
4297 05:58:51.336887 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 05:58:51.343532 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 05:58:51.346638 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 05:58:51.349854 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4301 05:58:51.356831 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4302 05:58:51.359854 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4303 05:58:51.363266 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4304 05:58:51.369917 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4305 05:58:51.372803 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 05:58:51.376476 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 05:58:51.379740 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 05:58:51.386340 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 05:58:51.389882 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 05:58:51.393494 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 05:58:51.399594 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 05:58:51.402865 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 05:58:51.406187 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 05:58:51.412647 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 05:58:51.416047 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 05:58:51.419593 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 05:58:51.426522 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 05:58:51.429312 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 05:58:51.432870 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 05:58:51.439306 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4321 05:58:51.442451 Total UI for P1: 0, mck2ui 16
4322 05:58:51.446503 best dqsien dly found for B0: ( 0, 9, 6)
4323 05:58:51.447061 Total UI for P1: 0, mck2ui 16
4324 05:58:51.452702 best dqsien dly found for B1: ( 0, 9, 6)
4325 05:58:51.455997 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4326 05:58:51.459135 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4327 05:58:51.459594
4328 05:58:51.462711 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4329 05:58:51.465777 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4330 05:58:51.469425 [Gating] SW calibration Done
4331 05:58:51.469996 ==
4332 05:58:51.472602 Dram Type= 6, Freq= 0, CH_1, rank 0
4333 05:58:51.476121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4334 05:58:51.476802 ==
4335 05:58:51.479104 RX Vref Scan: 0
4336 05:58:51.479583
4337 05:58:51.479948 RX Vref 0 -> 0, step: 1
4338 05:58:51.480352
4339 05:58:51.482729 RX Delay -230 -> 252, step: 16
4340 05:58:51.489262 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4341 05:58:51.492564 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4342 05:58:51.495972 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4343 05:58:51.499675 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4344 05:58:51.502301 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4345 05:58:51.509083 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4346 05:58:51.512784 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4347 05:58:51.515576 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4348 05:58:51.518978 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4349 05:58:51.525887 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4350 05:58:51.528668 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4351 05:58:51.532121 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4352 05:58:51.535409 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4353 05:58:51.542173 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4354 05:58:51.545394 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4355 05:58:51.549018 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4356 05:58:51.549573 ==
4357 05:58:51.551804 Dram Type= 6, Freq= 0, CH_1, rank 0
4358 05:58:51.555504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4359 05:58:51.558656 ==
4360 05:58:51.559109 DQS Delay:
4361 05:58:51.559464 DQS0 = 0, DQS1 = 0
4362 05:58:51.561709 DQM Delay:
4363 05:58:51.562158 DQM0 = 39, DQM1 = 33
4364 05:58:51.562510 DQ Delay:
4365 05:58:51.565374 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4366 05:58:51.568317 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4367 05:58:51.571655 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4368 05:58:51.574861 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4369 05:58:51.575311
4370 05:58:51.578290
4371 05:58:51.578736 ==
4372 05:58:51.581710 Dram Type= 6, Freq= 0, CH_1, rank 0
4373 05:58:51.584957 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4374 05:58:51.585413 ==
4375 05:58:51.585764
4376 05:58:51.586088
4377 05:58:51.587976 TX Vref Scan disable
4378 05:58:51.588345 == TX Byte 0 ==
4379 05:58:51.594851 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4380 05:58:51.598140 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4381 05:58:51.598638 == TX Byte 1 ==
4382 05:58:51.604732 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4383 05:58:51.608591 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4384 05:58:51.609211 ==
4385 05:58:51.611631 Dram Type= 6, Freq= 0, CH_1, rank 0
4386 05:58:51.615424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4387 05:58:51.615981 ==
4388 05:58:51.616333
4389 05:58:51.616657
4390 05:58:51.617998 TX Vref Scan disable
4391 05:58:51.621464 == TX Byte 0 ==
4392 05:58:51.624944 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4393 05:58:51.627797 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4394 05:58:51.631373 == TX Byte 1 ==
4395 05:58:51.634507 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4396 05:58:51.637939 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4397 05:58:51.638494
4398 05:58:51.641244 [DATLAT]
4399 05:58:51.641995 Freq=600, CH1 RK0
4400 05:58:51.642372
4401 05:58:51.644334 DATLAT Default: 0x9
4402 05:58:51.644923 0, 0xFFFF, sum = 0
4403 05:58:51.647744 1, 0xFFFF, sum = 0
4404 05:58:51.648207 2, 0xFFFF, sum = 0
4405 05:58:51.651434 3, 0xFFFF, sum = 0
4406 05:58:51.651962 4, 0xFFFF, sum = 0
4407 05:58:51.654236 5, 0xFFFF, sum = 0
4408 05:58:51.654690 6, 0xFFFF, sum = 0
4409 05:58:51.657728 7, 0x0, sum = 1
4410 05:58:51.658185 8, 0x0, sum = 2
4411 05:58:51.660891 9, 0x0, sum = 3
4412 05:58:51.661350 10, 0x0, sum = 4
4413 05:58:51.664102 best_step = 8
4414 05:58:51.664554
4415 05:58:51.664948 ==
4416 05:58:51.667596 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 05:58:51.671158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4418 05:58:51.671616 ==
4419 05:58:51.675002 RX Vref Scan: 1
4420 05:58:51.675453
4421 05:58:51.675803 RX Vref 0 -> 0, step: 1
4422 05:58:51.676131
4423 05:58:51.677498 RX Delay -195 -> 252, step: 8
4424 05:58:51.678103
4425 05:58:51.680989 Set Vref, RX VrefLevel [Byte0]: 52
4426 05:58:51.684238 [Byte1]: 50
4427 05:58:51.687927
4428 05:58:51.688481 Final RX Vref Byte 0 = 52 to rank0
4429 05:58:51.691450 Final RX Vref Byte 1 = 50 to rank0
4430 05:58:51.694661 Final RX Vref Byte 0 = 52 to rank1
4431 05:58:51.697808 Final RX Vref Byte 1 = 50 to rank1==
4432 05:58:51.700921 Dram Type= 6, Freq= 0, CH_1, rank 0
4433 05:58:51.707855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4434 05:58:51.708309 ==
4435 05:58:51.708658 DQS Delay:
4436 05:58:51.711338 DQS0 = 0, DQS1 = 0
4437 05:58:51.711891 DQM Delay:
4438 05:58:51.712243 DQM0 = 38, DQM1 = 31
4439 05:58:51.714802 DQ Delay:
4440 05:58:51.717549 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4441 05:58:51.720925 DQ4 =36, DQ5 =52, DQ6 =44, DQ7 =36
4442 05:58:51.724779 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4443 05:58:51.727822 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4444 05:58:51.728384
4445 05:58:51.728786
4446 05:58:51.734424 [DQSOSCAuto] RK0, (LSB)MR18= 0x7979, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4447 05:58:51.737332 CH1 RK0: MR19=808, MR18=7979
4448 05:58:51.743986 CH1_RK0: MR19=0x808, MR18=0x7979, DQSOSC=387, MR23=63, INC=175, DEC=116
4449 05:58:51.744564
4450 05:58:51.747142 ----->DramcWriteLeveling(PI) begin...
4451 05:58:51.747603 ==
4452 05:58:51.750524 Dram Type= 6, Freq= 0, CH_1, rank 1
4453 05:58:51.754087 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4454 05:58:51.754549 ==
4455 05:58:51.757392 Write leveling (Byte 0): 26 => 26
4456 05:58:51.761329 Write leveling (Byte 1): 26 => 26
4457 05:58:51.763804 DramcWriteLeveling(PI) end<-----
4458 05:58:51.764264
4459 05:58:51.764626 ==
4460 05:58:51.767296 Dram Type= 6, Freq= 0, CH_1, rank 1
4461 05:58:51.770690 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4462 05:58:51.774006 ==
4463 05:58:51.774572 [Gating] SW mode calibration
4464 05:58:51.780922 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4465 05:58:51.787318 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4466 05:58:51.790397 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 05:58:51.797229 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4468 05:58:51.800462 0 5 8 | B1->B0 | 3131 2727 | 0 0 | (1 1) (1 1)
4469 05:58:51.803944 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 05:58:51.810223 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 05:58:51.813672 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 05:58:51.817100 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 05:58:51.823705 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 05:58:51.827157 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 05:58:51.830330 0 6 4 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
4476 05:58:51.837348 0 6 8 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
4477 05:58:51.840291 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 05:58:51.843708 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 05:58:51.850150 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 05:58:51.853630 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 05:58:51.856932 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 05:58:51.863433 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 05:58:51.866152 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4484 05:58:51.870287 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4485 05:58:51.876329 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 05:58:51.879560 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 05:58:51.882801 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 05:58:51.889498 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 05:58:51.892796 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 05:58:51.896009 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 05:58:51.902635 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 05:58:51.906208 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 05:58:51.909045 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 05:58:51.915501 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 05:58:51.919135 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 05:58:51.922205 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 05:58:51.928868 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 05:58:51.932897 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4499 05:58:51.935612 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4500 05:58:51.942326 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 05:58:51.942957 Total UI for P1: 0, mck2ui 16
4502 05:58:51.945637 best dqsien dly found for B0: ( 0, 9, 2)
4503 05:58:51.949104 Total UI for P1: 0, mck2ui 16
4504 05:58:51.952261 best dqsien dly found for B1: ( 0, 9, 6)
4505 05:58:51.956014 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4506 05:58:51.962235 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4507 05:58:51.962651
4508 05:58:51.965444 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4509 05:58:51.968786 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4510 05:58:51.971991 [Gating] SW calibration Done
4511 05:58:51.972599 ==
4512 05:58:51.975619 Dram Type= 6, Freq= 0, CH_1, rank 1
4513 05:58:51.978722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4514 05:58:51.979345 ==
4515 05:58:51.979913 RX Vref Scan: 0
4516 05:58:51.982200
4517 05:58:51.982615 RX Vref 0 -> 0, step: 1
4518 05:58:51.982941
4519 05:58:51.985227 RX Delay -230 -> 252, step: 16
4520 05:58:51.988850 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4521 05:58:51.995234 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4522 05:58:51.998308 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4523 05:58:52.001591 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4524 05:58:52.005265 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4525 05:58:52.008586 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4526 05:58:52.014951 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4527 05:58:52.018366 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4528 05:58:52.021561 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4529 05:58:52.024877 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4530 05:58:52.031681 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4531 05:58:52.034654 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4532 05:58:52.038307 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4533 05:58:52.041267 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4534 05:58:52.048156 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4535 05:58:52.051112 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4536 05:58:52.051530 ==
4537 05:58:52.054569 Dram Type= 6, Freq= 0, CH_1, rank 1
4538 05:58:52.057964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4539 05:58:52.058387 ==
4540 05:58:52.061319 DQS Delay:
4541 05:58:52.061731 DQS0 = 0, DQS1 = 0
4542 05:58:52.062053 DQM Delay:
4543 05:58:52.064463 DQM0 = 40, DQM1 = 33
4544 05:58:52.064867 DQ Delay:
4545 05:58:52.067896 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4546 05:58:52.071446 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4547 05:58:52.074477 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4548 05:58:52.077703 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4549 05:58:52.078138
4550 05:58:52.078571
4551 05:58:52.078987 ==
4552 05:58:52.081265 Dram Type= 6, Freq= 0, CH_1, rank 1
4553 05:58:52.087831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4554 05:58:52.088226 ==
4555 05:58:52.088549
4556 05:58:52.088905
4557 05:58:52.089223 TX Vref Scan disable
4558 05:58:52.091732 == TX Byte 0 ==
4559 05:58:52.094845 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4560 05:58:52.101342 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4561 05:58:52.101762 == TX Byte 1 ==
4562 05:58:52.104980 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4563 05:58:52.111573 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4564 05:58:52.111994 ==
4565 05:58:52.114813 Dram Type= 6, Freq= 0, CH_1, rank 1
4566 05:58:52.118298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4567 05:58:52.118740 ==
4568 05:58:52.119070
4569 05:58:52.119374
4570 05:58:52.121252 TX Vref Scan disable
4571 05:58:52.125149 == TX Byte 0 ==
4572 05:58:52.128067 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4573 05:58:52.131660 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4574 05:58:52.134805 == TX Byte 1 ==
4575 05:58:52.138271 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4576 05:58:52.141381 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4577 05:58:52.141926
4578 05:58:52.142259 [DATLAT]
4579 05:58:52.144965 Freq=600, CH1 RK1
4580 05:58:52.145379
4581 05:58:52.145701 DATLAT Default: 0x8
4582 05:58:52.148042 0, 0xFFFF, sum = 0
4583 05:58:52.151557 1, 0xFFFF, sum = 0
4584 05:58:52.151978 2, 0xFFFF, sum = 0
4585 05:58:52.154886 3, 0xFFFF, sum = 0
4586 05:58:52.155306 4, 0xFFFF, sum = 0
4587 05:58:52.157621 5, 0xFFFF, sum = 0
4588 05:58:52.158045 6, 0xFFFF, sum = 0
4589 05:58:52.160955 7, 0x0, sum = 1
4590 05:58:52.161373 8, 0x0, sum = 2
4591 05:58:52.161918 9, 0x0, sum = 3
4592 05:58:52.164556 10, 0x0, sum = 4
4593 05:58:52.165001 best_step = 8
4594 05:58:52.165324
4595 05:58:52.165624 ==
4596 05:58:52.167649 Dram Type= 6, Freq= 0, CH_1, rank 1
4597 05:58:52.174335 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4598 05:58:52.174898 ==
4599 05:58:52.175234 RX Vref Scan: 0
4600 05:58:52.175540
4601 05:58:52.178265 RX Vref 0 -> 0, step: 1
4602 05:58:52.178679
4603 05:58:52.180865 RX Delay -195 -> 252, step: 8
4604 05:58:52.184244 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4605 05:58:52.190847 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4606 05:58:52.194314 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4607 05:58:52.197656 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4608 05:58:52.200858 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4609 05:58:52.208030 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4610 05:58:52.210638 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4611 05:58:52.214188 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4612 05:58:52.217527 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4613 05:58:52.220886 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4614 05:58:52.227122 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4615 05:58:52.230729 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4616 05:58:52.234031 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4617 05:58:52.240909 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4618 05:58:52.244049 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4619 05:58:52.247420 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4620 05:58:52.247834 ==
4621 05:58:52.250509 Dram Type= 6, Freq= 0, CH_1, rank 1
4622 05:58:52.254344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4623 05:58:52.254936 ==
4624 05:58:52.257587 DQS Delay:
4625 05:58:52.258155 DQS0 = 0, DQS1 = 0
4626 05:58:52.260604 DQM Delay:
4627 05:58:52.261069 DQM0 = 37, DQM1 = 28
4628 05:58:52.261400 DQ Delay:
4629 05:58:52.263720 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4630 05:58:52.266840 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4631 05:58:52.270585 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4632 05:58:52.273706 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4633 05:58:52.274496
4634 05:58:52.275031
4635 05:58:52.283451 [DQSOSCAuto] RK1, (LSB)MR18= 0x5353, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
4636 05:58:52.286950 CH1 RK1: MR19=808, MR18=5353
4637 05:58:52.293625 CH1_RK1: MR19=0x808, MR18=0x5353, DQSOSC=394, MR23=63, INC=168, DEC=112
4638 05:58:52.294045 [RxdqsGatingPostProcess] freq 600
4639 05:58:52.300118 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4640 05:58:52.303573 Pre-setting of DQS Precalculation
4641 05:58:52.306650 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4642 05:58:52.316650 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4643 05:58:52.323257 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4644 05:58:52.323692
4645 05:58:52.324016
4646 05:58:52.326532 [Calibration Summary] 1200 Mbps
4647 05:58:52.327216 CH 0, Rank 0
4648 05:58:52.330029 SW Impedance : PASS
4649 05:58:52.330446 DUTY Scan : NO K
4650 05:58:52.333520 ZQ Calibration : PASS
4651 05:58:52.336380 Jitter Meter : NO K
4652 05:58:52.337122 CBT Training : PASS
4653 05:58:52.339634 Write leveling : PASS
4654 05:58:52.343314 RX DQS gating : PASS
4655 05:58:52.343943 RX DQ/DQS(RDDQC) : PASS
4656 05:58:52.346305 TX DQ/DQS : PASS
4657 05:58:52.349983 RX DATLAT : PASS
4658 05:58:52.350548 RX DQ/DQS(Engine): PASS
4659 05:58:52.353102 TX OE : NO K
4660 05:58:52.353696 All Pass.
4661 05:58:52.354040
4662 05:58:52.356254 CH 0, Rank 1
4663 05:58:52.356609 SW Impedance : PASS
4664 05:58:52.359703 DUTY Scan : NO K
4665 05:58:52.363150 ZQ Calibration : PASS
4666 05:58:52.363680 Jitter Meter : NO K
4667 05:58:52.366798 CBT Training : PASS
4668 05:58:52.370009 Write leveling : PASS
4669 05:58:52.370420 RX DQS gating : PASS
4670 05:58:52.373293 RX DQ/DQS(RDDQC) : PASS
4671 05:58:52.376263 TX DQ/DQS : PASS
4672 05:58:52.376862 RX DATLAT : PASS
4673 05:58:52.379423 RX DQ/DQS(Engine): PASS
4674 05:58:52.379938 TX OE : NO K
4675 05:58:52.383107 All Pass.
4676 05:58:52.383723
4677 05:58:52.384168 CH 1, Rank 0
4678 05:58:52.386299 SW Impedance : PASS
4679 05:58:52.386711 DUTY Scan : NO K
4680 05:58:52.389655 ZQ Calibration : PASS
4681 05:58:52.393278 Jitter Meter : NO K
4682 05:58:52.393829 CBT Training : PASS
4683 05:58:52.396611 Write leveling : PASS
4684 05:58:52.399982 RX DQS gating : PASS
4685 05:58:52.400392 RX DQ/DQS(RDDQC) : PASS
4686 05:58:52.402975 TX DQ/DQS : PASS
4687 05:58:52.406092 RX DATLAT : PASS
4688 05:58:52.406674 RX DQ/DQS(Engine): PASS
4689 05:58:52.409734 TX OE : NO K
4690 05:58:52.410148 All Pass.
4691 05:58:52.410468
4692 05:58:52.413000 CH 1, Rank 1
4693 05:58:52.413611 SW Impedance : PASS
4694 05:58:52.416655 DUTY Scan : NO K
4695 05:58:52.419565 ZQ Calibration : PASS
4696 05:58:52.419976 Jitter Meter : NO K
4697 05:58:52.422690 CBT Training : PASS
4698 05:58:52.426209 Write leveling : PASS
4699 05:58:52.426741 RX DQS gating : PASS
4700 05:58:52.429305 RX DQ/DQS(RDDQC) : PASS
4701 05:58:52.432399 TX DQ/DQS : PASS
4702 05:58:52.433023 RX DATLAT : PASS
4703 05:58:52.436050 RX DQ/DQS(Engine): PASS
4704 05:58:52.436546 TX OE : NO K
4705 05:58:52.439238 All Pass.
4706 05:58:52.439716
4707 05:58:52.440223 DramC Write-DBI off
4708 05:58:52.443147 PER_BANK_REFRESH: Hybrid Mode
4709 05:58:52.446381 TX_TRACKING: ON
4710 05:58:52.452400 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4711 05:58:52.455836 [FAST_K] Save calibration result to emmc
4712 05:58:52.462367 dramc_set_vcore_voltage set vcore to 662500
4713 05:58:52.462826 Read voltage for 933, 3
4714 05:58:52.463152 Vio18 = 0
4715 05:58:52.465921 Vcore = 662500
4716 05:58:52.466332 Vdram = 0
4717 05:58:52.466711 Vddq = 0
4718 05:58:52.468841 Vmddr = 0
4719 05:58:52.472669 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4720 05:58:52.479002 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4721 05:58:52.482147 MEM_TYPE=3, freq_sel=17
4722 05:58:52.482559 sv_algorithm_assistance_LP4_1600
4723 05:58:52.489216 ============ PULL DRAM RESETB DOWN ============
4724 05:58:52.492507 ========== PULL DRAM RESETB DOWN end =========
4725 05:58:52.495603 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4726 05:58:52.499192 ===================================
4727 05:58:52.502351 LPDDR4 DRAM CONFIGURATION
4728 05:58:52.505496 ===================================
4729 05:58:52.509193 EX_ROW_EN[0] = 0x0
4730 05:58:52.509604 EX_ROW_EN[1] = 0x0
4731 05:58:52.511908 LP4Y_EN = 0x0
4732 05:58:52.512316 WORK_FSP = 0x0
4733 05:58:52.515442 WL = 0x3
4734 05:58:52.516073 RL = 0x3
4735 05:58:52.519147 BL = 0x2
4736 05:58:52.519657 RPST = 0x0
4737 05:58:52.521980 RD_PRE = 0x0
4738 05:58:52.522392 WR_PRE = 0x1
4739 05:58:52.525222 WR_PST = 0x0
4740 05:58:52.525636 DBI_WR = 0x0
4741 05:58:52.528765 DBI_RD = 0x0
4742 05:58:52.529177 OTF = 0x1
4743 05:58:52.532059 ===================================
4744 05:58:52.535692 ===================================
4745 05:58:52.539006 ANA top config
4746 05:58:52.542182 ===================================
4747 05:58:52.545288 DLL_ASYNC_EN = 0
4748 05:58:52.545803 ALL_SLAVE_EN = 1
4749 05:58:52.548440 NEW_RANK_MODE = 1
4750 05:58:52.551815 DLL_IDLE_MODE = 1
4751 05:58:52.555337 LP45_APHY_COMB_EN = 1
4752 05:58:52.558636 TX_ODT_DIS = 1
4753 05:58:52.559152 NEW_8X_MODE = 1
4754 05:58:52.561626 ===================================
4755 05:58:52.564919 ===================================
4756 05:58:52.568412 data_rate = 1866
4757 05:58:52.571813 CKR = 1
4758 05:58:52.575201 DQ_P2S_RATIO = 8
4759 05:58:52.578655 ===================================
4760 05:58:52.581440 CA_P2S_RATIO = 8
4761 05:58:52.585046 DQ_CA_OPEN = 0
4762 05:58:52.585461 DQ_SEMI_OPEN = 0
4763 05:58:52.588140 CA_SEMI_OPEN = 0
4764 05:58:52.591411 CA_FULL_RATE = 0
4765 05:58:52.594489 DQ_CKDIV4_EN = 1
4766 05:58:52.598141 CA_CKDIV4_EN = 1
4767 05:58:52.601293 CA_PREDIV_EN = 0
4768 05:58:52.601754 PH8_DLY = 0
4769 05:58:52.604918 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4770 05:58:52.608257 DQ_AAMCK_DIV = 4
4771 05:58:52.611179 CA_AAMCK_DIV = 4
4772 05:58:52.614790 CA_ADMCK_DIV = 4
4773 05:58:52.617612 DQ_TRACK_CA_EN = 0
4774 05:58:52.621119 CA_PICK = 933
4775 05:58:52.621681 CA_MCKIO = 933
4776 05:58:52.624346 MCKIO_SEMI = 0
4777 05:58:52.627802 PLL_FREQ = 3732
4778 05:58:52.631203 DQ_UI_PI_RATIO = 32
4779 05:58:52.634644 CA_UI_PI_RATIO = 0
4780 05:58:52.637784 ===================================
4781 05:58:52.641048 ===================================
4782 05:58:52.644487 memory_type:LPDDR4
4783 05:58:52.645182 GP_NUM : 10
4784 05:58:52.647253 SRAM_EN : 1
4785 05:58:52.647704 MD32_EN : 0
4786 05:58:52.651275 ===================================
4787 05:58:52.654333 [ANA_INIT] >>>>>>>>>>>>>>
4788 05:58:52.657377 <<<<<< [CONFIGURE PHASE]: ANA_TX
4789 05:58:52.660876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4790 05:58:52.663917 ===================================
4791 05:58:52.667506 data_rate = 1866,PCW = 0X8f00
4792 05:58:52.670837 ===================================
4793 05:58:52.673788 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4794 05:58:52.680538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4795 05:58:52.683623 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4796 05:58:52.690259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4797 05:58:52.693595 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4798 05:58:52.697159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4799 05:58:52.697619 [ANA_INIT] flow start
4800 05:58:52.700396 [ANA_INIT] PLL >>>>>>>>
4801 05:58:52.703585 [ANA_INIT] PLL <<<<<<<<
4802 05:58:52.704038 [ANA_INIT] MIDPI >>>>>>>>
4803 05:58:52.706801 [ANA_INIT] MIDPI <<<<<<<<
4804 05:58:52.710159 [ANA_INIT] DLL >>>>>>>>
4805 05:58:52.710609 [ANA_INIT] flow end
4806 05:58:52.716649 ============ LP4 DIFF to SE enter ============
4807 05:58:52.720017 ============ LP4 DIFF to SE exit ============
4808 05:58:52.723533 [ANA_INIT] <<<<<<<<<<<<<
4809 05:58:52.726581 [Flow] Enable top DCM control >>>>>
4810 05:58:52.729797 [Flow] Enable top DCM control <<<<<
4811 05:58:52.733181 Enable DLL master slave shuffle
4812 05:58:52.736431 ==============================================================
4813 05:58:52.739720 Gating Mode config
4814 05:58:52.743184 ==============================================================
4815 05:58:52.746752 Config description:
4816 05:58:52.756168 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4817 05:58:52.762986 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4818 05:58:52.766685 SELPH_MODE 0: By rank 1: By Phase
4819 05:58:52.772770 ==============================================================
4820 05:58:52.775851 GAT_TRACK_EN = 1
4821 05:58:52.779595 RX_GATING_MODE = 2
4822 05:58:52.782741 RX_GATING_TRACK_MODE = 2
4823 05:58:52.785913 SELPH_MODE = 1
4824 05:58:52.789291 PICG_EARLY_EN = 1
4825 05:58:52.792500 VALID_LAT_VALUE = 1
4826 05:58:52.795729 ==============================================================
4827 05:58:52.798875 Enter into Gating configuration >>>>
4828 05:58:52.802538 Exit from Gating configuration <<<<
4829 05:58:52.805879 Enter into DVFS_PRE_config >>>>>
4830 05:58:52.818708 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4831 05:58:52.821940 Exit from DVFS_PRE_config <<<<<
4832 05:58:52.822419 Enter into PICG configuration >>>>
4833 05:58:52.825620 Exit from PICG configuration <<<<
4834 05:58:52.828899 [RX_INPUT] configuration >>>>>
4835 05:58:52.832055 [RX_INPUT] configuration <<<<<
4836 05:58:52.838615 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4837 05:58:52.841742 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4838 05:58:52.848413 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4839 05:58:52.855118 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4840 05:58:52.861650 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4841 05:58:52.868897 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4842 05:58:52.871520 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4843 05:58:52.875584 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4844 05:58:52.881640 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4845 05:58:52.885188 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4846 05:58:52.888002 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4847 05:58:52.891317 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4848 05:58:52.894562 ===================================
4849 05:58:52.898238 LPDDR4 DRAM CONFIGURATION
4850 05:58:52.901805 ===================================
4851 05:58:52.905014 EX_ROW_EN[0] = 0x0
4852 05:58:52.905593 EX_ROW_EN[1] = 0x0
4853 05:58:52.908107 LP4Y_EN = 0x0
4854 05:58:52.908584 WORK_FSP = 0x0
4855 05:58:52.911074 WL = 0x3
4856 05:58:52.911804 RL = 0x3
4857 05:58:52.915056 BL = 0x2
4858 05:58:52.915627 RPST = 0x0
4859 05:58:52.918042 RD_PRE = 0x0
4860 05:58:52.918600 WR_PRE = 0x1
4861 05:58:52.921115 WR_PST = 0x0
4862 05:58:52.921576 DBI_WR = 0x0
4863 05:58:52.924343 DBI_RD = 0x0
4864 05:58:52.928189 OTF = 0x1
4865 05:58:52.928821 ===================================
4866 05:58:52.934542 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4867 05:58:52.937817 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4868 05:58:52.941093 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4869 05:58:52.944389 ===================================
4870 05:58:52.947745 LPDDR4 DRAM CONFIGURATION
4871 05:58:52.951001 ===================================
4872 05:58:52.954672 EX_ROW_EN[0] = 0x10
4873 05:58:52.955253 EX_ROW_EN[1] = 0x0
4874 05:58:52.957333 LP4Y_EN = 0x0
4875 05:58:52.957810 WORK_FSP = 0x0
4876 05:58:52.960835 WL = 0x3
4877 05:58:52.961314 RL = 0x3
4878 05:58:52.964034 BL = 0x2
4879 05:58:52.964512 RPST = 0x0
4880 05:58:52.967444 RD_PRE = 0x0
4881 05:58:52.967921 WR_PRE = 0x1
4882 05:58:52.971083 WR_PST = 0x0
4883 05:58:52.973811 DBI_WR = 0x0
4884 05:58:52.974292 DBI_RD = 0x0
4885 05:58:52.977265 OTF = 0x1
4886 05:58:52.980805 ===================================
4887 05:58:52.983973 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4888 05:58:52.989252 nWR fixed to 30
4889 05:58:52.992478 [ModeRegInit_LP4] CH0 RK0
4890 05:58:52.993054 [ModeRegInit_LP4] CH0 RK1
4891 05:58:52.996143 [ModeRegInit_LP4] CH1 RK0
4892 05:58:52.998902 [ModeRegInit_LP4] CH1 RK1
4893 05:58:52.999367 match AC timing 8
4894 05:58:53.005584 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4895 05:58:53.008900 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4896 05:58:53.012858 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4897 05:58:53.019033 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4898 05:58:53.021972 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4899 05:58:53.022524 ==
4900 05:58:53.025577 Dram Type= 6, Freq= 0, CH_0, rank 0
4901 05:58:53.028529 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4902 05:58:53.029023 ==
4903 05:58:53.035356 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4904 05:58:53.041818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4905 05:58:53.045364 [CA 0] Center 38 (8~69) winsize 62
4906 05:58:53.048527 [CA 1] Center 38 (8~69) winsize 62
4907 05:58:53.052098 [CA 2] Center 36 (6~67) winsize 62
4908 05:58:53.055121 [CA 3] Center 36 (5~67) winsize 63
4909 05:58:53.058473 [CA 4] Center 34 (4~65) winsize 62
4910 05:58:53.061935 [CA 5] Center 34 (4~65) winsize 62
4911 05:58:53.062391
4912 05:58:53.065233 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4913 05:58:53.065693
4914 05:58:53.068516 [CATrainingPosCal] consider 1 rank data
4915 05:58:53.071734 u2DelayCellTimex100 = 270/100 ps
4916 05:58:53.075156 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4917 05:58:53.078552 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4918 05:58:53.081839 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4919 05:58:53.085166 CA3 delay=36 (5~67),Diff = 2 PI (12 cell)
4920 05:58:53.088574 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4921 05:58:53.094859 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4922 05:58:53.095324
4923 05:58:53.098249 CA PerBit enable=1, Macro0, CA PI delay=34
4924 05:58:53.098714
4925 05:58:53.102062 [CBTSetCACLKResult] CA Dly = 34
4926 05:58:53.102627 CS Dly: 7 (0~38)
4927 05:58:53.102994 ==
4928 05:58:53.104827 Dram Type= 6, Freq= 0, CH_0, rank 1
4929 05:58:53.108172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4930 05:58:53.111561 ==
4931 05:58:53.114801 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4932 05:58:53.121401 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4933 05:58:53.124805 [CA 0] Center 38 (8~69) winsize 62
4934 05:58:53.128115 [CA 1] Center 38 (8~69) winsize 62
4935 05:58:53.131564 [CA 2] Center 36 (5~67) winsize 63
4936 05:58:53.135144 [CA 3] Center 35 (5~66) winsize 62
4937 05:58:53.138192 [CA 4] Center 34 (4~64) winsize 61
4938 05:58:53.141409 [CA 5] Center 34 (4~65) winsize 62
4939 05:58:53.141872
4940 05:58:53.144601 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4941 05:58:53.145174
4942 05:58:53.147946 [CATrainingPosCal] consider 2 rank data
4943 05:58:53.151203 u2DelayCellTimex100 = 270/100 ps
4944 05:58:53.154672 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4945 05:58:53.158055 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4946 05:58:53.161155 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4947 05:58:53.167575 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4948 05:58:53.170912 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4949 05:58:53.174394 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4950 05:58:53.174967
4951 05:58:53.177689 CA PerBit enable=1, Macro0, CA PI delay=34
4952 05:58:53.178152
4953 05:58:53.180802 [CBTSetCACLKResult] CA Dly = 34
4954 05:58:53.181265 CS Dly: 7 (0~39)
4955 05:58:53.181627
4956 05:58:53.184288 ----->DramcWriteLeveling(PI) begin...
4957 05:58:53.187548 ==
4958 05:58:53.188012 Dram Type= 6, Freq= 0, CH_0, rank 0
4959 05:58:53.194374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4960 05:58:53.194966 ==
4961 05:58:53.197420 Write leveling (Byte 0): 28 => 28
4962 05:58:53.200937 Write leveling (Byte 1): 27 => 27
4963 05:58:53.203901 DramcWriteLeveling(PI) end<-----
4964 05:58:53.204364
4965 05:58:53.204759 ==
4966 05:58:53.207216 Dram Type= 6, Freq= 0, CH_0, rank 0
4967 05:58:53.210866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4968 05:58:53.211335 ==
4969 05:58:53.213823 [Gating] SW mode calibration
4970 05:58:53.221173 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4971 05:58:53.227343 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4972 05:58:53.230484 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4973 05:58:53.233865 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4974 05:58:53.240927 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4975 05:58:53.244059 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4976 05:58:53.247009 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4977 05:58:53.250650 0 10 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4978 05:58:53.256937 0 10 24 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (1 0)
4979 05:58:53.260452 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4980 05:58:53.264036 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4981 05:58:53.270570 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4982 05:58:53.274036 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4983 05:58:53.276931 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4984 05:58:53.283453 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4985 05:58:53.287066 0 11 20 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (1 1)
4986 05:58:53.290133 0 11 24 | B1->B0 | 3636 4343 | 1 1 | (0 0) (0 0)
4987 05:58:53.297018 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4988 05:58:53.299879 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4989 05:58:53.303376 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4990 05:58:53.309874 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4991 05:58:53.314058 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4992 05:58:53.316280 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4993 05:58:53.323109 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4994 05:58:53.326560 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4995 05:58:53.329686 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4996 05:58:53.336902 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 05:58:53.340121 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 05:58:53.343843 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 05:58:53.349880 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 05:58:53.353103 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 05:58:53.356518 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 05:58:53.363390 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 05:58:53.366639 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 05:58:53.369716 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 05:58:53.376260 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 05:58:53.379568 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 05:58:53.383091 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 05:58:53.389472 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 05:58:53.393036 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 05:58:53.396260 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5011 05:58:53.399489 Total UI for P1: 0, mck2ui 16
5012 05:58:53.402608 best dqsien dly found for B0: ( 0, 14, 22)
5013 05:58:53.405960 Total UI for P1: 0, mck2ui 16
5014 05:58:53.409193 best dqsien dly found for B1: ( 0, 14, 22)
5015 05:58:53.412696 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5016 05:58:53.416166 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5017 05:58:53.416859
5018 05:58:53.422664 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5019 05:58:53.425879 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5020 05:58:53.428961 [Gating] SW calibration Done
5021 05:58:53.429427 ==
5022 05:58:53.432332 Dram Type= 6, Freq= 0, CH_0, rank 0
5023 05:58:53.435702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5024 05:58:53.436168 ==
5025 05:58:53.436527 RX Vref Scan: 0
5026 05:58:53.438914
5027 05:58:53.439372 RX Vref 0 -> 0, step: 1
5028 05:58:53.439737
5029 05:58:53.442683 RX Delay -80 -> 252, step: 8
5030 05:58:53.445533 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5031 05:58:53.449058 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5032 05:58:53.452434 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5033 05:58:53.459119 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5034 05:58:53.462275 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5035 05:58:53.465354 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5036 05:58:53.468792 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5037 05:58:53.471831 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5038 05:58:53.478692 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5039 05:58:53.481715 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5040 05:58:53.484914 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5041 05:58:53.488092 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5042 05:58:53.491558 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5043 05:58:53.498013 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5044 05:58:53.501508 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5045 05:58:53.505083 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5046 05:58:53.505654 ==
5047 05:58:53.508079 Dram Type= 6, Freq= 0, CH_0, rank 0
5048 05:58:53.511390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5049 05:58:53.511856 ==
5050 05:58:53.514891 DQS Delay:
5051 05:58:53.515354 DQS0 = 0, DQS1 = 0
5052 05:58:53.518240 DQM Delay:
5053 05:58:53.518701 DQM0 = 96, DQM1 = 85
5054 05:58:53.519064 DQ Delay:
5055 05:58:53.521491 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5056 05:58:53.524531 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5057 05:58:53.528099 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5058 05:58:53.531632 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5059 05:58:53.532110
5060 05:58:53.532588
5061 05:58:53.534448 ==
5062 05:58:53.537728 Dram Type= 6, Freq= 0, CH_0, rank 0
5063 05:58:53.541201 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5064 05:58:53.541683 ==
5065 05:58:53.542180
5066 05:58:53.542629
5067 05:58:53.544376 TX Vref Scan disable
5068 05:58:53.544909 == TX Byte 0 ==
5069 05:58:53.550853 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5070 05:58:53.554596 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5071 05:58:53.555079 == TX Byte 1 ==
5072 05:58:53.561090 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5073 05:58:53.564441 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5074 05:58:53.565094 ==
5075 05:58:53.567870 Dram Type= 6, Freq= 0, CH_0, rank 0
5076 05:58:53.570934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5077 05:58:53.571530 ==
5078 05:58:53.572024
5079 05:58:53.572479
5080 05:58:53.573969 TX Vref Scan disable
5081 05:58:53.577525 == TX Byte 0 ==
5082 05:58:53.580684 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5083 05:58:53.584356 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5084 05:58:53.587183 == TX Byte 1 ==
5085 05:58:53.590529 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5086 05:58:53.594132 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5087 05:58:53.594593
5088 05:58:53.597085 [DATLAT]
5089 05:58:53.597543 Freq=933, CH0 RK0
5090 05:58:53.597903
5091 05:58:53.600844 DATLAT Default: 0xd
5092 05:58:53.601299 0, 0xFFFF, sum = 0
5093 05:58:53.603940 1, 0xFFFF, sum = 0
5094 05:58:53.604401 2, 0xFFFF, sum = 0
5095 05:58:53.607113 3, 0xFFFF, sum = 0
5096 05:58:53.607578 4, 0xFFFF, sum = 0
5097 05:58:53.610750 5, 0xFFFF, sum = 0
5098 05:58:53.611215 6, 0xFFFF, sum = 0
5099 05:58:53.613971 7, 0xFFFF, sum = 0
5100 05:58:53.614436 8, 0xFFFF, sum = 0
5101 05:58:53.616842 9, 0xFFFF, sum = 0
5102 05:58:53.617305 10, 0x0, sum = 1
5103 05:58:53.620614 11, 0x0, sum = 2
5104 05:58:53.621229 12, 0x0, sum = 3
5105 05:58:53.624030 13, 0x0, sum = 4
5106 05:58:53.624557 best_step = 11
5107 05:58:53.624979
5108 05:58:53.625320 ==
5109 05:58:53.627103 Dram Type= 6, Freq= 0, CH_0, rank 0
5110 05:58:53.633562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5111 05:58:53.634025 ==
5112 05:58:53.634383 RX Vref Scan: 1
5113 05:58:53.634713
5114 05:58:53.637075 RX Vref 0 -> 0, step: 1
5115 05:58:53.637628
5116 05:58:53.640403 RX Delay -69 -> 252, step: 4
5117 05:58:53.640986
5118 05:58:53.643664 Set Vref, RX VrefLevel [Byte0]: 55
5119 05:58:53.646826 [Byte1]: 49
5120 05:58:53.647285
5121 05:58:53.650651 Final RX Vref Byte 0 = 55 to rank0
5122 05:58:53.653394 Final RX Vref Byte 1 = 49 to rank0
5123 05:58:53.657335 Final RX Vref Byte 0 = 55 to rank1
5124 05:58:53.659943 Final RX Vref Byte 1 = 49 to rank1==
5125 05:58:53.663228 Dram Type= 6, Freq= 0, CH_0, rank 0
5126 05:58:53.666596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5127 05:58:53.667100 ==
5128 05:58:53.669806 DQS Delay:
5129 05:58:53.670282 DQS0 = 0, DQS1 = 0
5130 05:58:53.673425 DQM Delay:
5131 05:58:53.674010 DQM0 = 96, DQM1 = 87
5132 05:58:53.674502 DQ Delay:
5133 05:58:53.676889 DQ0 =90, DQ1 =98, DQ2 =96, DQ3 =94
5134 05:58:53.679996 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5135 05:58:53.683118 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =80
5136 05:58:53.686472 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5137 05:58:53.686954
5138 05:58:53.689624
5139 05:58:53.696346 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5140 05:58:53.699859 CH0 RK0: MR19=505, MR18=1D1D
5141 05:58:53.706405 CH0_RK0: MR19=0x505, MR18=0x1D1D, DQSOSC=412, MR23=63, INC=63, DEC=42
5142 05:58:53.706974
5143 05:58:53.709896 ----->DramcWriteLeveling(PI) begin...
5144 05:58:53.710485 ==
5145 05:58:53.712835 Dram Type= 6, Freq= 0, CH_0, rank 1
5146 05:58:53.716531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5147 05:58:53.717227 ==
5148 05:58:53.719629 Write leveling (Byte 0): 31 => 31
5149 05:58:53.722907 Write leveling (Byte 1): 27 => 27
5150 05:58:53.726065 DramcWriteLeveling(PI) end<-----
5151 05:58:53.726544
5152 05:58:53.727024 ==
5153 05:58:53.729300 Dram Type= 6, Freq= 0, CH_0, rank 1
5154 05:58:53.732830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5155 05:58:53.733316 ==
5156 05:58:53.736382 [Gating] SW mode calibration
5157 05:58:53.742355 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5158 05:58:53.749256 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5159 05:58:53.752550 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 05:58:53.758918 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 05:58:53.762632 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 05:58:53.765771 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 05:58:53.772094 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 05:58:53.776291 0 10 20 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 1)
5165 05:58:53.779362 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5166 05:58:53.782339 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 05:58:53.788943 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 05:58:53.792230 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 05:58:53.795788 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 05:58:53.802030 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 05:58:53.805622 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 05:58:53.808604 0 11 20 | B1->B0 | 2929 3131 | 0 0 | (0 0) (0 0)
5173 05:58:53.815790 0 11 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5174 05:58:53.818765 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 05:58:53.822133 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 05:58:53.828808 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 05:58:53.832784 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 05:58:53.835356 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 05:58:53.842098 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 05:58:53.845305 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5181 05:58:53.848325 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5182 05:58:53.855479 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 05:58:53.858444 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 05:58:53.861431 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 05:58:53.868257 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 05:58:53.871609 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 05:58:53.875009 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 05:58:53.881270 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 05:58:53.884780 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 05:58:53.887974 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 05:58:53.894545 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 05:58:53.897936 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 05:58:53.901267 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 05:58:53.907733 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 05:58:53.910930 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 05:58:53.914915 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5197 05:58:53.921276 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5198 05:58:53.924089 Total UI for P1: 0, mck2ui 16
5199 05:58:53.927670 best dqsien dly found for B1: ( 0, 14, 20)
5200 05:58:53.930850 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 05:58:53.934370 Total UI for P1: 0, mck2ui 16
5202 05:58:53.937582 best dqsien dly found for B0: ( 0, 14, 22)
5203 05:58:53.940679 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5204 05:58:53.944448 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5205 05:58:53.944955
5206 05:58:53.947227 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5207 05:58:53.954000 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5208 05:58:53.954606 [Gating] SW calibration Done
5209 05:58:53.954982 ==
5210 05:58:53.957380 Dram Type= 6, Freq= 0, CH_0, rank 1
5211 05:58:53.963830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5212 05:58:53.964301 ==
5213 05:58:53.964665 RX Vref Scan: 0
5214 05:58:53.965058
5215 05:58:53.967141 RX Vref 0 -> 0, step: 1
5216 05:58:53.967664
5217 05:58:53.970448 RX Delay -80 -> 252, step: 8
5218 05:58:53.973618 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5219 05:58:53.977676 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5220 05:58:53.980600 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5221 05:58:53.984214 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5222 05:58:53.990692 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5223 05:58:53.994091 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5224 05:58:53.997246 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5225 05:58:54.000641 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5226 05:58:54.004116 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5227 05:58:54.007435 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5228 05:58:54.013986 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5229 05:58:54.017264 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5230 05:58:54.020609 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5231 05:58:54.024123 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5232 05:58:54.027042 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5233 05:58:54.033700 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5234 05:58:54.034266 ==
5235 05:58:54.037102 Dram Type= 6, Freq= 0, CH_0, rank 1
5236 05:58:54.040237 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5237 05:58:54.040867 ==
5238 05:58:54.041362 DQS Delay:
5239 05:58:54.043860 DQS0 = 0, DQS1 = 0
5240 05:58:54.044431 DQM Delay:
5241 05:58:54.046688 DQM0 = 96, DQM1 = 85
5242 05:58:54.047165 DQ Delay:
5243 05:58:54.050090 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5244 05:58:54.053640 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5245 05:58:54.056755 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5246 05:58:54.060429 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5247 05:58:54.061046
5248 05:58:54.061539
5249 05:58:54.062000 ==
5250 05:58:54.063531 Dram Type= 6, Freq= 0, CH_0, rank 1
5251 05:58:54.066931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5252 05:58:54.069845 ==
5253 05:58:54.070324
5254 05:58:54.070806
5255 05:58:54.071262 TX Vref Scan disable
5256 05:58:54.073242 == TX Byte 0 ==
5257 05:58:54.076745 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5258 05:58:54.079778 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5259 05:58:54.082973 == TX Byte 1 ==
5260 05:58:54.086413 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5261 05:58:54.089826 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5262 05:58:54.093355 ==
5263 05:58:54.093824 Dram Type= 6, Freq= 0, CH_0, rank 1
5264 05:58:54.099922 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5265 05:58:54.100385 ==
5266 05:58:54.100784
5267 05:58:54.101131
5268 05:58:54.102856 TX Vref Scan disable
5269 05:58:54.103318 == TX Byte 0 ==
5270 05:58:54.109571 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5271 05:58:54.113116 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5272 05:58:54.113580 == TX Byte 1 ==
5273 05:58:54.120014 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5274 05:58:54.123274 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5275 05:58:54.123912
5276 05:58:54.124283 [DATLAT]
5277 05:58:54.125999 Freq=933, CH0 RK1
5278 05:58:54.126476
5279 05:58:54.126841 DATLAT Default: 0xb
5280 05:58:54.129381 0, 0xFFFF, sum = 0
5281 05:58:54.129888 1, 0xFFFF, sum = 0
5282 05:58:54.132403 2, 0xFFFF, sum = 0
5283 05:58:54.135638 3, 0xFFFF, sum = 0
5284 05:58:54.136107 4, 0xFFFF, sum = 0
5285 05:58:54.139016 5, 0xFFFF, sum = 0
5286 05:58:54.139520 6, 0xFFFF, sum = 0
5287 05:58:54.142344 7, 0xFFFF, sum = 0
5288 05:58:54.142904 8, 0xFFFF, sum = 0
5289 05:58:54.145885 9, 0xFFFF, sum = 0
5290 05:58:54.146356 10, 0x0, sum = 1
5291 05:58:54.148852 11, 0x0, sum = 2
5292 05:58:54.149320 12, 0x0, sum = 3
5293 05:58:54.152450 13, 0x0, sum = 4
5294 05:58:54.153052 best_step = 11
5295 05:58:54.153420
5296 05:58:54.153758 ==
5297 05:58:54.156063 Dram Type= 6, Freq= 0, CH_0, rank 1
5298 05:58:54.159146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5299 05:58:54.159708 ==
5300 05:58:54.162210 RX Vref Scan: 0
5301 05:58:54.162673
5302 05:58:54.165296 RX Vref 0 -> 0, step: 1
5303 05:58:54.165777
5304 05:58:54.166257 RX Delay -69 -> 252, step: 4
5305 05:58:54.173387 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5306 05:58:54.176936 iDelay=203, Bit 1, Center 100 (7 ~ 194) 188
5307 05:58:54.180404 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5308 05:58:54.183274 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5309 05:58:54.186374 iDelay=203, Bit 4, Center 100 (7 ~ 194) 188
5310 05:58:54.190059 iDelay=203, Bit 5, Center 88 (-1 ~ 178) 180
5311 05:58:54.196401 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5312 05:58:54.199865 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5313 05:58:54.203175 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5314 05:58:54.206537 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5315 05:58:54.212960 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5316 05:58:54.216798 iDelay=203, Bit 11, Center 80 (-5 ~ 166) 172
5317 05:58:54.219765 iDelay=203, Bit 12, Center 92 (3 ~ 182) 180
5318 05:58:54.222989 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5319 05:58:54.226105 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5320 05:58:54.229835 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5321 05:58:54.232731 ==
5322 05:58:54.236048 Dram Type= 6, Freq= 0, CH_0, rank 1
5323 05:58:54.239352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5324 05:58:54.239930 ==
5325 05:58:54.240306 DQS Delay:
5326 05:58:54.243039 DQS0 = 0, DQS1 = 0
5327 05:58:54.243595 DQM Delay:
5328 05:58:54.246191 DQM0 = 97, DQM1 = 86
5329 05:58:54.246801 DQ Delay:
5330 05:58:54.249298 DQ0 =92, DQ1 =100, DQ2 =96, DQ3 =92
5331 05:58:54.252336 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =108
5332 05:58:54.256172 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =80
5333 05:58:54.259240 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =94
5334 05:58:54.259936
5335 05:58:54.260308
5336 05:58:54.265807 [DQSOSCAuto] RK1, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5337 05:58:54.269310 CH0 RK1: MR19=505, MR18=2424
5338 05:58:54.275679 CH0_RK1: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42
5339 05:58:54.278743 [RxdqsGatingPostProcess] freq 933
5340 05:58:54.285394 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5341 05:58:54.289168 Pre-setting of DQS Precalculation
5342 05:58:54.291914 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5343 05:58:54.292422 ==
5344 05:58:54.295652 Dram Type= 6, Freq= 0, CH_1, rank 0
5345 05:58:54.298772 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5346 05:58:54.299239 ==
5347 05:58:54.305615 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5348 05:58:54.312257 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5349 05:58:54.315483 [CA 0] Center 37 (7~68) winsize 62
5350 05:58:54.318811 [CA 1] Center 37 (6~68) winsize 63
5351 05:58:54.321886 [CA 2] Center 35 (5~65) winsize 61
5352 05:58:54.325200 [CA 3] Center 34 (4~65) winsize 62
5353 05:58:54.328487 [CA 4] Center 33 (2~64) winsize 63
5354 05:58:54.332046 [CA 5] Center 33 (3~64) winsize 62
5355 05:58:54.332619
5356 05:58:54.335393 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5357 05:58:54.335962
5358 05:58:54.338479 [CATrainingPosCal] consider 1 rank data
5359 05:58:54.341570 u2DelayCellTimex100 = 270/100 ps
5360 05:58:54.344934 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5361 05:58:54.348828 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5362 05:58:54.351663 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5363 05:58:54.358137 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5364 05:58:54.361445 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5365 05:58:54.364740 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5366 05:58:54.365212
5367 05:58:54.368489 CA PerBit enable=1, Macro0, CA PI delay=33
5368 05:58:54.369104
5369 05:58:54.371248 [CBTSetCACLKResult] CA Dly = 33
5370 05:58:54.371709 CS Dly: 5 (0~36)
5371 05:58:54.372067 ==
5372 05:58:54.374497 Dram Type= 6, Freq= 0, CH_1, rank 1
5373 05:58:54.381234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5374 05:58:54.381786 ==
5375 05:58:54.384449 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5376 05:58:54.391379 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5377 05:58:54.394740 [CA 0] Center 37 (7~68) winsize 62
5378 05:58:54.397821 [CA 1] Center 37 (6~68) winsize 63
5379 05:58:54.401434 [CA 2] Center 34 (4~65) winsize 62
5380 05:58:54.404532 [CA 3] Center 34 (4~64) winsize 61
5381 05:58:54.407535 [CA 4] Center 33 (3~64) winsize 62
5382 05:58:54.411285 [CA 5] Center 33 (3~63) winsize 61
5383 05:58:54.411742
5384 05:58:54.414350 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5385 05:58:54.414809
5386 05:58:54.417406 [CATrainingPosCal] consider 2 rank data
5387 05:58:54.420858 u2DelayCellTimex100 = 270/100 ps
5388 05:58:54.424686 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5389 05:58:54.430575 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5390 05:58:54.434079 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5391 05:58:54.437552 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5392 05:58:54.440898 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5393 05:58:54.444181 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5394 05:58:54.444798
5395 05:58:54.447494 CA PerBit enable=1, Macro0, CA PI delay=33
5396 05:58:54.448048
5397 05:58:54.450605 [CBTSetCACLKResult] CA Dly = 33
5398 05:58:54.453894 CS Dly: 5 (0~37)
5399 05:58:54.454588
5400 05:58:54.457323 ----->DramcWriteLeveling(PI) begin...
5401 05:58:54.457900 ==
5402 05:58:54.460771 Dram Type= 6, Freq= 0, CH_1, rank 0
5403 05:58:54.464238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5404 05:58:54.464846 ==
5405 05:58:54.467368 Write leveling (Byte 0): 23 => 23
5406 05:58:54.470537 Write leveling (Byte 1): 22 => 22
5407 05:58:54.474165 DramcWriteLeveling(PI) end<-----
5408 05:58:54.474717
5409 05:58:54.475077 ==
5410 05:58:54.477465 Dram Type= 6, Freq= 0, CH_1, rank 0
5411 05:58:54.480509 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5412 05:58:54.481099 ==
5413 05:58:54.483506 [Gating] SW mode calibration
5414 05:58:54.490497 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5415 05:58:54.496592 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5416 05:58:54.500365 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5417 05:58:54.503354 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5418 05:58:54.510047 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5419 05:58:54.513405 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5420 05:58:54.516820 0 10 16 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5421 05:58:54.523373 0 10 20 | B1->B0 | 3131 2525 | 1 0 | (1 0) (0 0)
5422 05:58:54.526623 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5423 05:58:54.529734 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5424 05:58:54.536971 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5425 05:58:54.539798 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5426 05:58:54.543559 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5427 05:58:54.550120 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5428 05:58:54.553573 0 11 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5429 05:58:54.556527 0 11 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
5430 05:58:54.563564 0 11 24 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5431 05:58:54.566620 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 05:58:54.570005 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 05:58:54.577130 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 05:58:54.579741 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5435 05:58:54.583179 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5436 05:58:54.589600 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5437 05:58:54.593116 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5438 05:58:54.596441 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 05:58:54.603004 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 05:58:54.606586 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 05:58:54.609568 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 05:58:54.616454 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 05:58:54.619577 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 05:58:54.622925 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 05:58:54.626332 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 05:58:54.632839 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 05:58:54.636289 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 05:58:54.639540 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 05:58:54.646494 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 05:58:54.649595 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 05:58:54.652597 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 05:58:54.659499 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5453 05:58:54.662623 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5454 05:58:54.665757 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5455 05:58:54.669361 Total UI for P1: 0, mck2ui 16
5456 05:58:54.672537 best dqsien dly found for B0: ( 0, 14, 18)
5457 05:58:54.676033 Total UI for P1: 0, mck2ui 16
5458 05:58:54.679454 best dqsien dly found for B1: ( 0, 14, 20)
5459 05:58:54.682350 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5460 05:58:54.689103 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5461 05:58:54.689664
5462 05:58:54.692373 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5463 05:58:54.695340 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5464 05:58:54.698856 [Gating] SW calibration Done
5465 05:58:54.699318 ==
5466 05:58:54.702139 Dram Type= 6, Freq= 0, CH_1, rank 0
5467 05:58:54.705387 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5468 05:58:54.705899 ==
5469 05:58:54.708678 RX Vref Scan: 0
5470 05:58:54.709186
5471 05:58:54.709548 RX Vref 0 -> 0, step: 1
5472 05:58:54.709887
5473 05:58:54.712304 RX Delay -80 -> 252, step: 8
5474 05:58:54.715667 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5475 05:58:54.722448 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5476 05:58:54.725201 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5477 05:58:54.728595 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5478 05:58:54.731764 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5479 05:58:54.735860 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5480 05:58:54.738666 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5481 05:58:54.745208 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5482 05:58:54.748891 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5483 05:58:54.751878 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5484 05:58:54.754977 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5485 05:58:54.758601 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5486 05:58:54.764760 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5487 05:58:54.768141 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5488 05:58:54.771951 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5489 05:58:54.775077 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5490 05:58:54.775636 ==
5491 05:58:54.778309 Dram Type= 6, Freq= 0, CH_1, rank 0
5492 05:58:54.784749 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5493 05:58:54.785223 ==
5494 05:58:54.785586 DQS Delay:
5495 05:58:54.785921 DQS0 = 0, DQS1 = 0
5496 05:58:54.788203 DQM Delay:
5497 05:58:54.788802 DQM0 = 94, DQM1 = 88
5498 05:58:54.791274 DQ Delay:
5499 05:58:54.794878 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5500 05:58:54.798128 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5501 05:58:54.801322 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5502 05:58:54.804303 DQ12 =99, DQ13 =103, DQ14 =91, DQ15 =95
5503 05:58:54.804796
5504 05:58:54.805159
5505 05:58:54.805491 ==
5506 05:58:54.807495 Dram Type= 6, Freq= 0, CH_1, rank 0
5507 05:58:54.811165 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5508 05:58:54.811725 ==
5509 05:58:54.812091
5510 05:58:54.812422
5511 05:58:54.814242 TX Vref Scan disable
5512 05:58:54.814699 == TX Byte 0 ==
5513 05:58:54.821121 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5514 05:58:54.824460 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5515 05:58:54.824968 == TX Byte 1 ==
5516 05:58:54.831179 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5517 05:58:54.834551 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5518 05:58:54.835279 ==
5519 05:58:54.837550 Dram Type= 6, Freq= 0, CH_1, rank 0
5520 05:58:54.841323 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5521 05:58:54.841805 ==
5522 05:58:54.842163
5523 05:58:54.844770
5524 05:58:54.845384 TX Vref Scan disable
5525 05:58:54.847518 == TX Byte 0 ==
5526 05:58:54.850835 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5527 05:58:54.854165 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5528 05:58:54.857769 == TX Byte 1 ==
5529 05:58:54.860847 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5530 05:58:54.864326 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5531 05:58:54.867551
5532 05:58:54.868006 [DATLAT]
5533 05:58:54.868363 Freq=933, CH1 RK0
5534 05:58:54.868699
5535 05:58:54.870912 DATLAT Default: 0xd
5536 05:58:54.871471 0, 0xFFFF, sum = 0
5537 05:58:54.873945 1, 0xFFFF, sum = 0
5538 05:58:54.874415 2, 0xFFFF, sum = 0
5539 05:58:54.877267 3, 0xFFFF, sum = 0
5540 05:58:54.880671 4, 0xFFFF, sum = 0
5541 05:58:54.881246 5, 0xFFFF, sum = 0
5542 05:58:54.883773 6, 0xFFFF, sum = 0
5543 05:58:54.884242 7, 0xFFFF, sum = 0
5544 05:58:54.887327 8, 0xFFFF, sum = 0
5545 05:58:54.887909 9, 0xFFFF, sum = 0
5546 05:58:54.890784 10, 0x0, sum = 1
5547 05:58:54.891338 11, 0x0, sum = 2
5548 05:58:54.893711 12, 0x0, sum = 3
5549 05:58:54.894181 13, 0x0, sum = 4
5550 05:58:54.894546 best_step = 11
5551 05:58:54.894884
5552 05:58:54.897052 ==
5553 05:58:54.900440 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 05:58:54.903748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5555 05:58:54.904214 ==
5556 05:58:54.904579 RX Vref Scan: 1
5557 05:58:54.904983
5558 05:58:54.907023 RX Vref 0 -> 0, step: 1
5559 05:58:54.907486
5560 05:58:54.910732 RX Delay -69 -> 252, step: 4
5561 05:58:54.911292
5562 05:58:54.913483 Set Vref, RX VrefLevel [Byte0]: 52
5563 05:58:54.917019 [Byte1]: 50
5564 05:58:54.917479
5565 05:58:54.920523 Final RX Vref Byte 0 = 52 to rank0
5566 05:58:54.923415 Final RX Vref Byte 1 = 50 to rank0
5567 05:58:54.927128 Final RX Vref Byte 0 = 52 to rank1
5568 05:58:54.930382 Final RX Vref Byte 1 = 50 to rank1==
5569 05:58:54.933474 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 05:58:54.936804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5571 05:58:54.939984 ==
5572 05:58:54.940557 DQS Delay:
5573 05:58:54.941133 DQS0 = 0, DQS1 = 0
5574 05:58:54.943863 DQM Delay:
5575 05:58:54.944324 DQM0 = 94, DQM1 = 88
5576 05:58:54.946775 DQ Delay:
5577 05:58:54.950702 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =90
5578 05:58:54.953541 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5579 05:58:54.956473 DQ8 =72, DQ9 =78, DQ10 =90, DQ11 =80
5580 05:58:54.960160 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5581 05:58:54.960761
5582 05:58:54.961138
5583 05:58:54.966550 [DQSOSCAuto] RK0, (LSB)MR18= 0x3434, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5584 05:58:54.969658 CH1 RK0: MR19=505, MR18=3434
5585 05:58:54.976848 CH1_RK0: MR19=0x505, MR18=0x3434, DQSOSC=405, MR23=63, INC=66, DEC=44
5586 05:58:54.977397
5587 05:58:54.979896 ----->DramcWriteLeveling(PI) begin...
5588 05:58:54.980365 ==
5589 05:58:54.982902 Dram Type= 6, Freq= 0, CH_1, rank 1
5590 05:58:54.986188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5591 05:58:54.986654 ==
5592 05:58:54.990052 Write leveling (Byte 0): 22 => 22
5593 05:58:54.992926 Write leveling (Byte 1): 24 => 24
5594 05:58:54.995975 DramcWriteLeveling(PI) end<-----
5595 05:58:54.996570
5596 05:58:54.997001 ==
5597 05:58:54.999487 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 05:58:55.002779 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5599 05:58:55.003246 ==
5600 05:58:55.006229 [Gating] SW mode calibration
5601 05:58:55.012824 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5602 05:58:55.019317 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5603 05:58:55.023164 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 05:58:55.029303 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 05:58:55.032437 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 05:58:55.035798 0 10 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5607 05:58:55.043023 0 10 16 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (1 1)
5608 05:58:55.045737 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5609 05:58:55.049502 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 05:58:55.055988 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 05:58:55.059228 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 05:58:55.062673 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 05:58:55.068804 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 05:58:55.072255 0 11 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5615 05:58:55.075867 0 11 16 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
5616 05:58:55.082139 0 11 20 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
5617 05:58:55.085451 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 05:58:55.088928 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 05:58:55.095686 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 05:58:55.098932 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 05:58:55.101781 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 05:58:55.108470 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 05:58:55.112092 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5624 05:58:55.115277 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 05:58:55.121507 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 05:58:55.124868 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 05:58:55.128116 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 05:58:55.134795 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 05:58:55.138517 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 05:58:55.141416 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 05:58:55.148155 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 05:58:55.152070 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 05:58:55.154526 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 05:58:55.161593 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 05:58:55.164471 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 05:58:55.167986 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 05:58:55.174415 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 05:58:55.178005 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 05:58:55.181076 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5640 05:58:55.187768 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5641 05:58:55.188317 Total UI for P1: 0, mck2ui 16
5642 05:58:55.194262 best dqsien dly found for B0: ( 0, 14, 16)
5643 05:58:55.197419 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 05:58:55.201035 Total UI for P1: 0, mck2ui 16
5645 05:58:55.204134 best dqsien dly found for B1: ( 0, 14, 20)
5646 05:58:55.207475 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5647 05:58:55.210846 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5648 05:58:55.211407
5649 05:58:55.214183 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5650 05:58:55.217320 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5651 05:58:55.221248 [Gating] SW calibration Done
5652 05:58:55.221811 ==
5653 05:58:55.223881 Dram Type= 6, Freq= 0, CH_1, rank 1
5654 05:58:55.227161 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5655 05:58:55.230863 ==
5656 05:58:55.231325 RX Vref Scan: 0
5657 05:58:55.231764
5658 05:58:55.234046 RX Vref 0 -> 0, step: 1
5659 05:58:55.234601
5660 05:58:55.237202 RX Delay -80 -> 252, step: 8
5661 05:58:55.240693 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5662 05:58:55.243749 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5663 05:58:55.247308 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5664 05:58:55.251010 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5665 05:58:55.253898 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5666 05:58:55.260348 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5667 05:58:55.264167 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5668 05:58:55.266942 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5669 05:58:55.270348 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5670 05:58:55.273440 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5671 05:58:55.280430 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5672 05:58:55.283760 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5673 05:58:55.286796 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5674 05:58:55.290212 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5675 05:58:55.293683 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5676 05:58:55.296664 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5677 05:58:55.300052 ==
5678 05:58:55.303420 Dram Type= 6, Freq= 0, CH_1, rank 1
5679 05:58:55.307209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5680 05:58:55.307768 ==
5681 05:58:55.308133 DQS Delay:
5682 05:58:55.310036 DQS0 = 0, DQS1 = 0
5683 05:58:55.310503 DQM Delay:
5684 05:58:55.313417 DQM0 = 95, DQM1 = 86
5685 05:58:55.313980 DQ Delay:
5686 05:58:55.316995 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =91
5687 05:58:55.319858 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5688 05:58:55.323370 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =79
5689 05:58:55.326372 DQ12 =91, DQ13 =99, DQ14 =95, DQ15 =95
5690 05:58:55.326839
5691 05:58:55.327199
5692 05:58:55.327531 ==
5693 05:58:55.329867 Dram Type= 6, Freq= 0, CH_1, rank 1
5694 05:58:55.333291 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5695 05:58:55.333757 ==
5696 05:58:55.334117
5697 05:58:55.334450
5698 05:58:55.336811 TX Vref Scan disable
5699 05:58:55.339808 == TX Byte 0 ==
5700 05:58:55.343383 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5701 05:58:55.346579 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5702 05:58:55.349898 == TX Byte 1 ==
5703 05:58:55.353048 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5704 05:58:55.356308 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5705 05:58:55.356796 ==
5706 05:58:55.359511 Dram Type= 6, Freq= 0, CH_1, rank 1
5707 05:58:55.365816 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5708 05:58:55.366285 ==
5709 05:58:55.366648
5710 05:58:55.366979
5711 05:58:55.367301 TX Vref Scan disable
5712 05:58:55.370235 == TX Byte 0 ==
5713 05:58:55.373559 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5714 05:58:55.380620 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5715 05:58:55.381198 == TX Byte 1 ==
5716 05:58:55.383447 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5717 05:58:55.390548 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5718 05:58:55.391107
5719 05:58:55.391473 [DATLAT]
5720 05:58:55.391809 Freq=933, CH1 RK1
5721 05:58:55.392136
5722 05:58:55.393553 DATLAT Default: 0xb
5723 05:58:55.394016 0, 0xFFFF, sum = 0
5724 05:58:55.396828 1, 0xFFFF, sum = 0
5725 05:58:55.399870 2, 0xFFFF, sum = 0
5726 05:58:55.400342 3, 0xFFFF, sum = 0
5727 05:58:55.403286 4, 0xFFFF, sum = 0
5728 05:58:55.403760 5, 0xFFFF, sum = 0
5729 05:58:55.407213 6, 0xFFFF, sum = 0
5730 05:58:55.407775 7, 0xFFFF, sum = 0
5731 05:58:55.410205 8, 0xFFFF, sum = 0
5732 05:58:55.410697 9, 0xFFFF, sum = 0
5733 05:58:55.413574 10, 0x0, sum = 1
5734 05:58:55.414040 11, 0x0, sum = 2
5735 05:58:55.416553 12, 0x0, sum = 3
5736 05:58:55.417069 13, 0x0, sum = 4
5737 05:58:55.417441 best_step = 11
5738 05:58:55.420080
5739 05:58:55.420539 ==
5740 05:58:55.423138 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 05:58:55.426453 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5742 05:58:55.426921 ==
5743 05:58:55.427283 RX Vref Scan: 0
5744 05:58:55.427620
5745 05:58:55.429688 RX Vref 0 -> 0, step: 1
5746 05:58:55.430210
5747 05:58:55.433508 RX Delay -77 -> 252, step: 4
5748 05:58:55.439757 iDelay=203, Bit 0, Center 96 (7 ~ 186) 180
5749 05:58:55.443367 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5750 05:58:55.446243 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5751 05:58:55.449760 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5752 05:58:55.453213 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5753 05:58:55.456153 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5754 05:58:55.463289 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5755 05:58:55.466217 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5756 05:58:55.469462 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5757 05:58:55.473142 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5758 05:58:55.476666 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5759 05:58:55.479911 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5760 05:58:55.486640 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5761 05:58:55.490208 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5762 05:58:55.492880 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5763 05:58:55.496410 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5764 05:58:55.497021 ==
5765 05:58:55.499673 Dram Type= 6, Freq= 0, CH_1, rank 1
5766 05:58:55.506074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5767 05:58:55.506645 ==
5768 05:58:55.507015 DQS Delay:
5769 05:58:55.507353 DQS0 = 0, DQS1 = 0
5770 05:58:55.509605 DQM Delay:
5771 05:58:55.510182 DQM0 = 95, DQM1 = 87
5772 05:58:55.512506 DQ Delay:
5773 05:58:55.515703 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =92
5774 05:58:55.519622 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5775 05:58:55.522595 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5776 05:58:55.525817 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5777 05:58:55.526352
5778 05:58:55.526728
5779 05:58:55.532645 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5780 05:58:55.535854 CH1 RK1: MR19=505, MR18=2222
5781 05:58:55.542478 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5782 05:58:55.546182 [RxdqsGatingPostProcess] freq 933
5783 05:58:55.549697 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5784 05:58:55.552274 Pre-setting of DQS Precalculation
5785 05:58:55.558883 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5786 05:58:55.565498 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5787 05:58:55.572110 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5788 05:58:55.572580
5789 05:58:55.572977
5790 05:58:55.575530 [Calibration Summary] 1866 Mbps
5791 05:58:55.575992 CH 0, Rank 0
5792 05:58:55.579054 SW Impedance : PASS
5793 05:58:55.582341 DUTY Scan : NO K
5794 05:58:55.582811 ZQ Calibration : PASS
5795 05:58:55.585801 Jitter Meter : NO K
5796 05:58:55.588747 CBT Training : PASS
5797 05:58:55.589214 Write leveling : PASS
5798 05:58:55.592293 RX DQS gating : PASS
5799 05:58:55.595358 RX DQ/DQS(RDDQC) : PASS
5800 05:58:55.595817 TX DQ/DQS : PASS
5801 05:58:55.598997 RX DATLAT : PASS
5802 05:58:55.601940 RX DQ/DQS(Engine): PASS
5803 05:58:55.602403 TX OE : NO K
5804 05:58:55.605459 All Pass.
5805 05:58:55.605918
5806 05:58:55.606280 CH 0, Rank 1
5807 05:58:55.608574 SW Impedance : PASS
5808 05:58:55.609075 DUTY Scan : NO K
5809 05:58:55.611579 ZQ Calibration : PASS
5810 05:58:55.615106 Jitter Meter : NO K
5811 05:58:55.615671 CBT Training : PASS
5812 05:58:55.619051 Write leveling : PASS
5813 05:58:55.622053 RX DQS gating : PASS
5814 05:58:55.622617 RX DQ/DQS(RDDQC) : PASS
5815 05:58:55.625126 TX DQ/DQS : PASS
5816 05:58:55.625591 RX DATLAT : PASS
5817 05:58:55.628232 RX DQ/DQS(Engine): PASS
5818 05:58:55.632153 TX OE : NO K
5819 05:58:55.632815 All Pass.
5820 05:58:55.633194
5821 05:58:55.633531 CH 1, Rank 0
5822 05:58:55.634753 SW Impedance : PASS
5823 05:58:55.638143 DUTY Scan : NO K
5824 05:58:55.638603 ZQ Calibration : PASS
5825 05:58:55.641669 Jitter Meter : NO K
5826 05:58:55.644806 CBT Training : PASS
5827 05:58:55.645338 Write leveling : PASS
5828 05:58:55.648470 RX DQS gating : PASS
5829 05:58:55.651527 RX DQ/DQS(RDDQC) : PASS
5830 05:58:55.652082 TX DQ/DQS : PASS
5831 05:58:55.655180 RX DATLAT : PASS
5832 05:58:55.657818 RX DQ/DQS(Engine): PASS
5833 05:58:55.658283 TX OE : NO K
5834 05:58:55.661489 All Pass.
5835 05:58:55.661946
5836 05:58:55.662304 CH 1, Rank 1
5837 05:58:55.664648 SW Impedance : PASS
5838 05:58:55.665153 DUTY Scan : NO K
5839 05:58:55.668211 ZQ Calibration : PASS
5840 05:58:55.671157 Jitter Meter : NO K
5841 05:58:55.671624 CBT Training : PASS
5842 05:58:55.674515 Write leveling : PASS
5843 05:58:55.677921 RX DQS gating : PASS
5844 05:58:55.678385 RX DQ/DQS(RDDQC) : PASS
5845 05:58:55.681125 TX DQ/DQS : PASS
5846 05:58:55.684485 RX DATLAT : PASS
5847 05:58:55.685106 RX DQ/DQS(Engine): PASS
5848 05:58:55.687820 TX OE : NO K
5849 05:58:55.688312 All Pass.
5850 05:58:55.688676
5851 05:58:55.690935 DramC Write-DBI off
5852 05:58:55.694417 PER_BANK_REFRESH: Hybrid Mode
5853 05:58:55.694967 TX_TRACKING: ON
5854 05:58:55.704244 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5855 05:58:55.707693 [FAST_K] Save calibration result to emmc
5856 05:58:55.710745 dramc_set_vcore_voltage set vcore to 650000
5857 05:58:55.714206 Read voltage for 400, 6
5858 05:58:55.714765 Vio18 = 0
5859 05:58:55.715124 Vcore = 650000
5860 05:58:55.717535 Vdram = 0
5861 05:58:55.717994 Vddq = 0
5862 05:58:55.718351 Vmddr = 0
5863 05:58:55.724076 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5864 05:58:55.727298 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5865 05:58:55.730313 MEM_TYPE=3, freq_sel=20
5866 05:58:55.733899 sv_algorithm_assistance_LP4_800
5867 05:58:55.737236 ============ PULL DRAM RESETB DOWN ============
5868 05:58:55.740512 ========== PULL DRAM RESETB DOWN end =========
5869 05:58:55.747633 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5870 05:58:55.750570 ===================================
5871 05:58:55.753519 LPDDR4 DRAM CONFIGURATION
5872 05:58:55.756863 ===================================
5873 05:58:55.757370 EX_ROW_EN[0] = 0x0
5874 05:58:55.760278 EX_ROW_EN[1] = 0x0
5875 05:58:55.760869 LP4Y_EN = 0x0
5876 05:58:55.763606 WORK_FSP = 0x0
5877 05:58:55.764161 WL = 0x2
5878 05:58:55.767025 RL = 0x2
5879 05:58:55.767487 BL = 0x2
5880 05:58:55.770195 RPST = 0x0
5881 05:58:55.770657 RD_PRE = 0x0
5882 05:58:55.773264 WR_PRE = 0x1
5883 05:58:55.773788 WR_PST = 0x0
5884 05:58:55.776871 DBI_WR = 0x0
5885 05:58:55.777422 DBI_RD = 0x0
5886 05:58:55.780031 OTF = 0x1
5887 05:58:55.783652 ===================================
5888 05:58:55.786508 ===================================
5889 05:58:55.786973 ANA top config
5890 05:58:55.789733 ===================================
5891 05:58:55.793337 DLL_ASYNC_EN = 0
5892 05:58:55.796509 ALL_SLAVE_EN = 1
5893 05:58:55.799707 NEW_RANK_MODE = 1
5894 05:58:55.803334 DLL_IDLE_MODE = 1
5895 05:58:55.803797 LP45_APHY_COMB_EN = 1
5896 05:58:55.806696 TX_ODT_DIS = 1
5897 05:58:55.809953 NEW_8X_MODE = 1
5898 05:58:55.812840 ===================================
5899 05:58:55.816182 ===================================
5900 05:58:55.819550 data_rate = 800
5901 05:58:55.823214 CKR = 1
5902 05:58:55.823772 DQ_P2S_RATIO = 4
5903 05:58:55.826056 ===================================
5904 05:58:55.829346 CA_P2S_RATIO = 4
5905 05:58:55.832859 DQ_CA_OPEN = 0
5906 05:58:55.835944 DQ_SEMI_OPEN = 1
5907 05:58:55.839712 CA_SEMI_OPEN = 1
5908 05:58:55.843155 CA_FULL_RATE = 0
5909 05:58:55.843728 DQ_CKDIV4_EN = 0
5910 05:58:55.846107 CA_CKDIV4_EN = 1
5911 05:58:55.849548 CA_PREDIV_EN = 0
5912 05:58:55.852909 PH8_DLY = 0
5913 05:58:55.856117 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5914 05:58:55.859323 DQ_AAMCK_DIV = 0
5915 05:58:55.859786 CA_AAMCK_DIV = 0
5916 05:58:55.862563 CA_ADMCK_DIV = 4
5917 05:58:55.866047 DQ_TRACK_CA_EN = 0
5918 05:58:55.869033 CA_PICK = 800
5919 05:58:55.872460 CA_MCKIO = 400
5920 05:58:55.875629 MCKIO_SEMI = 400
5921 05:58:55.879160 PLL_FREQ = 3016
5922 05:58:55.882422 DQ_UI_PI_RATIO = 32
5923 05:58:55.883014 CA_UI_PI_RATIO = 32
5924 05:58:55.885673 ===================================
5925 05:58:55.888802 ===================================
5926 05:58:55.892914 memory_type:LPDDR4
5927 05:58:55.895562 GP_NUM : 10
5928 05:58:55.896090 SRAM_EN : 1
5929 05:58:55.899267 MD32_EN : 0
5930 05:58:55.902229 ===================================
5931 05:58:55.905825 [ANA_INIT] >>>>>>>>>>>>>>
5932 05:58:55.908643 <<<<<< [CONFIGURE PHASE]: ANA_TX
5933 05:58:55.912444 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5934 05:58:55.916000 ===================================
5935 05:58:55.916566 data_rate = 800,PCW = 0X7400
5936 05:58:55.918977 ===================================
5937 05:58:55.922470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5938 05:58:55.928768 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5939 05:58:55.941948 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5940 05:58:55.945487 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5941 05:58:55.948672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5942 05:58:55.951998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5943 05:58:55.955479 [ANA_INIT] flow start
5944 05:58:55.956045 [ANA_INIT] PLL >>>>>>>>
5945 05:58:55.958371 [ANA_INIT] PLL <<<<<<<<
5946 05:58:55.962315 [ANA_INIT] MIDPI >>>>>>>>
5947 05:58:55.962878 [ANA_INIT] MIDPI <<<<<<<<
5948 05:58:55.965344 [ANA_INIT] DLL >>>>>>>>
5949 05:58:55.968410 [ANA_INIT] flow end
5950 05:58:55.972353 ============ LP4 DIFF to SE enter ============
5951 05:58:55.975260 ============ LP4 DIFF to SE exit ============
5952 05:58:55.978527 [ANA_INIT] <<<<<<<<<<<<<
5953 05:58:55.981546 [Flow] Enable top DCM control >>>>>
5954 05:58:55.984895 [Flow] Enable top DCM control <<<<<
5955 05:58:55.988663 Enable DLL master slave shuffle
5956 05:58:55.991879 ==============================================================
5957 05:58:55.995505 Gating Mode config
5958 05:58:56.002065 ==============================================================
5959 05:58:56.002574 Config description:
5960 05:58:56.011722 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5961 05:58:56.017995 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5962 05:58:56.021628 SELPH_MODE 0: By rank 1: By Phase
5963 05:58:56.028432 ==============================================================
5964 05:58:56.031498 GAT_TRACK_EN = 0
5965 05:58:56.035152 RX_GATING_MODE = 2
5966 05:58:56.038207 RX_GATING_TRACK_MODE = 2
5967 05:58:56.041501 SELPH_MODE = 1
5968 05:58:56.044611 PICG_EARLY_EN = 1
5969 05:58:56.048044 VALID_LAT_VALUE = 1
5970 05:58:56.052036 ==============================================================
5971 05:58:56.054434 Enter into Gating configuration >>>>
5972 05:58:56.058044 Exit from Gating configuration <<<<
5973 05:58:56.061400 Enter into DVFS_PRE_config >>>>>
5974 05:58:56.074388 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5975 05:58:56.078039 Exit from DVFS_PRE_config <<<<<
5976 05:58:56.081304 Enter into PICG configuration >>>>
5977 05:58:56.081766 Exit from PICG configuration <<<<
5978 05:58:56.084789 [RX_INPUT] configuration >>>>>
5979 05:58:56.088217 [RX_INPUT] configuration <<<<<
5980 05:58:56.094461 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5981 05:58:56.097525 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5982 05:58:56.104332 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5983 05:58:56.111120 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5984 05:58:56.117521 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5985 05:58:56.124102 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5986 05:58:56.127750 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5987 05:58:56.131033 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5988 05:58:56.133970 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5989 05:58:56.140968 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5990 05:58:56.143727 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5991 05:58:56.147129 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5992 05:58:56.150707 ===================================
5993 05:58:56.153784 LPDDR4 DRAM CONFIGURATION
5994 05:58:56.157188 ===================================
5995 05:58:56.160889 EX_ROW_EN[0] = 0x0
5996 05:58:56.161316 EX_ROW_EN[1] = 0x0
5997 05:58:56.163740 LP4Y_EN = 0x0
5998 05:58:56.164287 WORK_FSP = 0x0
5999 05:58:56.167218 WL = 0x2
6000 05:58:56.167679 RL = 0x2
6001 05:58:56.170553 BL = 0x2
6002 05:58:56.171010 RPST = 0x0
6003 05:58:56.174073 RD_PRE = 0x0
6004 05:58:56.174532 WR_PRE = 0x1
6005 05:58:56.177186 WR_PST = 0x0
6006 05:58:56.177644 DBI_WR = 0x0
6007 05:58:56.180362 DBI_RD = 0x0
6008 05:58:56.180966 OTF = 0x1
6009 05:58:56.183475 ===================================
6010 05:58:56.190060 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6011 05:58:56.193703 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6012 05:58:56.196952 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6013 05:58:56.200273 ===================================
6014 05:58:56.203280 LPDDR4 DRAM CONFIGURATION
6015 05:58:56.206772 ===================================
6016 05:58:56.209983 EX_ROW_EN[0] = 0x10
6017 05:58:56.210538 EX_ROW_EN[1] = 0x0
6018 05:58:56.213299 LP4Y_EN = 0x0
6019 05:58:56.213762 WORK_FSP = 0x0
6020 05:58:56.216929 WL = 0x2
6021 05:58:56.217483 RL = 0x2
6022 05:58:56.219932 BL = 0x2
6023 05:58:56.220392 RPST = 0x0
6024 05:58:56.223534 RD_PRE = 0x0
6025 05:58:56.224083 WR_PRE = 0x1
6026 05:58:56.226579 WR_PST = 0x0
6027 05:58:56.227041 DBI_WR = 0x0
6028 05:58:56.229915 DBI_RD = 0x0
6029 05:58:56.233355 OTF = 0x1
6030 05:58:56.233834 ===================================
6031 05:58:56.239921 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6032 05:58:56.245382 nWR fixed to 30
6033 05:58:56.248520 [ModeRegInit_LP4] CH0 RK0
6034 05:58:56.249129 [ModeRegInit_LP4] CH0 RK1
6035 05:58:56.251914 [ModeRegInit_LP4] CH1 RK0
6036 05:58:56.254616 [ModeRegInit_LP4] CH1 RK1
6037 05:58:56.255079 match AC timing 18
6038 05:58:56.261402 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6039 05:58:56.264915 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6040 05:58:56.268290 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6041 05:58:56.274429 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6042 05:58:56.277703 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6043 05:58:56.278161 ==
6044 05:58:56.281083 Dram Type= 6, Freq= 0, CH_0, rank 0
6045 05:58:56.284403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6046 05:58:56.284902 ==
6047 05:58:56.291411 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6048 05:58:56.298141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6049 05:58:56.301134 [CA 0] Center 36 (8~64) winsize 57
6050 05:58:56.304484 [CA 1] Center 36 (8~64) winsize 57
6051 05:58:56.307850 [CA 2] Center 36 (8~64) winsize 57
6052 05:58:56.311417 [CA 3] Center 36 (8~64) winsize 57
6053 05:58:56.311976 [CA 4] Center 36 (8~64) winsize 57
6054 05:58:56.314251 [CA 5] Center 36 (8~64) winsize 57
6055 05:58:56.314711
6056 05:58:56.321765 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6057 05:58:56.322225
6058 05:58:56.324793 [CATrainingPosCal] consider 1 rank data
6059 05:58:56.327774 u2DelayCellTimex100 = 270/100 ps
6060 05:58:56.331023 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6061 05:58:56.333918 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6062 05:58:56.337560 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6063 05:58:56.340631 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6064 05:58:56.344140 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6065 05:58:56.347648 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6066 05:58:56.348210
6067 05:58:56.350785 CA PerBit enable=1, Macro0, CA PI delay=36
6068 05:58:56.351348
6069 05:58:56.354197 [CBTSetCACLKResult] CA Dly = 36
6070 05:58:56.357679 CS Dly: 1 (0~32)
6071 05:58:56.358236 ==
6072 05:58:56.360779 Dram Type= 6, Freq= 0, CH_0, rank 1
6073 05:58:56.364262 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6074 05:58:56.364857 ==
6075 05:58:56.370468 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6076 05:58:56.377068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6077 05:58:56.380519 [CA 0] Center 36 (8~64) winsize 57
6078 05:58:56.381125 [CA 1] Center 36 (8~64) winsize 57
6079 05:58:56.383846 [CA 2] Center 36 (8~64) winsize 57
6080 05:58:56.387207 [CA 3] Center 36 (8~64) winsize 57
6081 05:58:56.390403 [CA 4] Center 36 (8~64) winsize 57
6082 05:58:56.393824 [CA 5] Center 36 (8~64) winsize 57
6083 05:58:56.394388
6084 05:58:56.397174 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6085 05:58:56.397635
6086 05:58:56.403676 [CATrainingPosCal] consider 2 rank data
6087 05:58:56.404145 u2DelayCellTimex100 = 270/100 ps
6088 05:58:56.410964 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6089 05:58:56.413909 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6090 05:58:56.417033 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6091 05:58:56.420497 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6092 05:58:56.423768 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6093 05:58:56.427489 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6094 05:58:56.428095
6095 05:58:56.430460 CA PerBit enable=1, Macro0, CA PI delay=36
6096 05:58:56.431035
6097 05:58:56.433798 [CBTSetCACLKResult] CA Dly = 36
6098 05:58:56.437430 CS Dly: 1 (0~32)
6099 05:58:56.437990
6100 05:58:56.440390 ----->DramcWriteLeveling(PI) begin...
6101 05:58:56.440992 ==
6102 05:58:56.443322 Dram Type= 6, Freq= 0, CH_0, rank 0
6103 05:58:56.446789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6104 05:58:56.447351 ==
6105 05:58:56.449832 Write leveling (Byte 0): 32 => 0
6106 05:58:56.453369 Write leveling (Byte 1): 32 => 0
6107 05:58:56.456590 DramcWriteLeveling(PI) end<-----
6108 05:58:56.457108
6109 05:58:56.457474 ==
6110 05:58:56.459881 Dram Type= 6, Freq= 0, CH_0, rank 0
6111 05:58:56.463280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6112 05:58:56.463859 ==
6113 05:58:56.466891 [Gating] SW mode calibration
6114 05:58:56.472881 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6115 05:58:56.479553 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6116 05:58:56.483471 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6117 05:58:56.486514 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6118 05:58:56.493015 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6119 05:58:56.496086 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6120 05:58:56.499421 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6121 05:58:56.505885 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6122 05:58:56.509497 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6123 05:58:56.512589 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6124 05:58:56.519198 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6125 05:58:56.519668 Total UI for P1: 0, mck2ui 16
6126 05:58:56.525732 best dqsien dly found for B0: ( 0, 10, 16)
6127 05:58:56.526331 Total UI for P1: 0, mck2ui 16
6128 05:58:56.532505 best dqsien dly found for B1: ( 0, 10, 24)
6129 05:58:56.535919 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6130 05:58:56.538749 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6131 05:58:56.539213
6132 05:58:56.542510 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6133 05:58:56.545705 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6134 05:58:56.549482 [Gating] SW calibration Done
6135 05:58:56.550038 ==
6136 05:58:56.552261 Dram Type= 6, Freq= 0, CH_0, rank 0
6137 05:58:56.555493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6138 05:58:56.555958 ==
6139 05:58:56.559051 RX Vref Scan: 0
6140 05:58:56.559606
6141 05:58:56.562275 RX Vref 0 -> 0, step: 1
6142 05:58:56.562829
6143 05:58:56.563208 RX Delay -410 -> 252, step: 16
6144 05:58:56.568610 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6145 05:58:56.572360 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6146 05:58:56.575102 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6147 05:58:56.582227 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6148 05:58:56.585262 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6149 05:58:56.588775 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6150 05:58:56.591682 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6151 05:58:56.598693 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6152 05:58:56.601891 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6153 05:58:56.604913 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6154 05:58:56.608571 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6155 05:58:56.614847 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6156 05:58:56.617711 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6157 05:58:56.621388 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6158 05:58:56.624407 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6159 05:58:56.631658 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6160 05:58:56.632221 ==
6161 05:58:56.634575 Dram Type= 6, Freq= 0, CH_0, rank 0
6162 05:58:56.637678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6163 05:58:56.638143 ==
6164 05:58:56.641101 DQS Delay:
6165 05:58:56.641563 DQS0 = 51, DQS1 = 59
6166 05:58:56.641926 DQM Delay:
6167 05:58:56.645077 DQM0 = 12, DQM1 = 16
6168 05:58:56.645636 DQ Delay:
6169 05:58:56.647529 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6170 05:58:56.650946 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6171 05:58:56.654777 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6172 05:58:56.657575 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6173 05:58:56.658039
6174 05:58:56.658397
6175 05:58:56.658728 ==
6176 05:58:56.660919 Dram Type= 6, Freq= 0, CH_0, rank 0
6177 05:58:56.664221 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6178 05:58:56.664831 ==
6179 05:58:56.667818
6180 05:58:56.668367
6181 05:58:56.668779 TX Vref Scan disable
6182 05:58:56.670785 == TX Byte 0 ==
6183 05:58:56.674015 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6184 05:58:56.677532 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6185 05:58:56.680926 == TX Byte 1 ==
6186 05:58:56.684160 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6187 05:58:56.687735 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6188 05:58:56.688296 ==
6189 05:58:56.690758 Dram Type= 6, Freq= 0, CH_0, rank 0
6190 05:58:56.697105 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6191 05:58:56.697649 ==
6192 05:58:56.698018
6193 05:58:56.698358
6194 05:58:56.698680 TX Vref Scan disable
6195 05:58:56.700350 == TX Byte 0 ==
6196 05:58:56.703674 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6197 05:58:56.707484 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6198 05:58:56.710732 == TX Byte 1 ==
6199 05:58:56.713689 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6200 05:58:56.717187 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6201 05:58:56.720601
6202 05:58:56.721093 [DATLAT]
6203 05:58:56.721455 Freq=400, CH0 RK0
6204 05:58:56.721792
6205 05:58:56.723972 DATLAT Default: 0xf
6206 05:58:56.724427 0, 0xFFFF, sum = 0
6207 05:58:56.727302 1, 0xFFFF, sum = 0
6208 05:58:56.727868 2, 0xFFFF, sum = 0
6209 05:58:56.730203 3, 0xFFFF, sum = 0
6210 05:58:56.730667 4, 0xFFFF, sum = 0
6211 05:58:56.733609 5, 0xFFFF, sum = 0
6212 05:58:56.734074 6, 0xFFFF, sum = 0
6213 05:58:56.736936 7, 0xFFFF, sum = 0
6214 05:58:56.740181 8, 0xFFFF, sum = 0
6215 05:58:56.740645 9, 0xFFFF, sum = 0
6216 05:58:56.743922 10, 0xFFFF, sum = 0
6217 05:58:56.744385 11, 0xFFFF, sum = 0
6218 05:58:56.747129 12, 0x0, sum = 1
6219 05:58:56.747691 13, 0x0, sum = 2
6220 05:58:56.750642 14, 0x0, sum = 3
6221 05:58:56.751203 15, 0x0, sum = 4
6222 05:58:56.751575 best_step = 13
6223 05:58:56.751912
6224 05:58:56.753663 ==
6225 05:58:56.756900 Dram Type= 6, Freq= 0, CH_0, rank 0
6226 05:58:56.760649 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6227 05:58:56.761254 ==
6228 05:58:56.761620 RX Vref Scan: 1
6229 05:58:56.761954
6230 05:58:56.763300 RX Vref 0 -> 0, step: 1
6231 05:58:56.763757
6232 05:58:56.767069 RX Delay -359 -> 252, step: 8
6233 05:58:56.767526
6234 05:58:56.769956 Set Vref, RX VrefLevel [Byte0]: 55
6235 05:58:56.773542 [Byte1]: 49
6236 05:58:56.777137
6237 05:58:56.777594 Final RX Vref Byte 0 = 55 to rank0
6238 05:58:56.780830 Final RX Vref Byte 1 = 49 to rank0
6239 05:58:56.783802 Final RX Vref Byte 0 = 55 to rank1
6240 05:58:56.787326 Final RX Vref Byte 1 = 49 to rank1==
6241 05:58:56.790436 Dram Type= 6, Freq= 0, CH_0, rank 0
6242 05:58:56.797138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6243 05:58:56.797704 ==
6244 05:58:56.798158 DQS Delay:
6245 05:58:56.800467 DQS0 = 56, DQS1 = 68
6246 05:58:56.800962 DQM Delay:
6247 05:58:56.801328 DQM0 = 13, DQM1 = 16
6248 05:58:56.803988 DQ Delay:
6249 05:58:56.806726 DQ0 =8, DQ1 =12, DQ2 =12, DQ3 =8
6250 05:58:56.810446 DQ4 =20, DQ5 =0, DQ6 =20, DQ7 =24
6251 05:58:56.811004 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6252 05:58:56.816899 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6253 05:58:56.817360
6254 05:58:56.817886
6255 05:58:56.823400 [DQSOSCAuto] RK0, (LSB)MR18= 0xa3a3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6256 05:58:56.827234 CH0 RK0: MR19=C0C, MR18=A3A3
6257 05:58:56.833485 CH0_RK0: MR19=0xC0C, MR18=0xA3A3, DQSOSC=389, MR23=63, INC=390, DEC=260
6258 05:58:56.834029 ==
6259 05:58:56.836581 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 05:58:56.840257 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6261 05:58:56.840891 ==
6262 05:58:56.843469 [Gating] SW mode calibration
6263 05:58:56.850197 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6264 05:58:56.857014 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6265 05:58:56.860264 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6266 05:58:56.863521 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6267 05:58:56.869983 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6268 05:58:56.873018 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6269 05:58:56.876455 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 05:58:56.883039 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 05:58:56.886536 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 05:58:56.889559 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6273 05:58:56.896676 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 05:58:56.897268 Total UI for P1: 0, mck2ui 16
6275 05:58:56.903321 best dqsien dly found for B0: ( 0, 10, 16)
6276 05:58:56.903902 Total UI for P1: 0, mck2ui 16
6277 05:58:56.906720 best dqsien dly found for B1: ( 0, 10, 24)
6278 05:58:56.912900 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6279 05:58:56.916368 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6280 05:58:56.916878
6281 05:58:56.919412 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6282 05:58:56.922624 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6283 05:58:56.925929 [Gating] SW calibration Done
6284 05:58:56.926394 ==
6285 05:58:56.929312 Dram Type= 6, Freq= 0, CH_0, rank 1
6286 05:58:56.932623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6287 05:58:56.933124 ==
6288 05:58:56.936164 RX Vref Scan: 0
6289 05:58:56.936631
6290 05:58:56.937185 RX Vref 0 -> 0, step: 1
6291 05:58:56.937644
6292 05:58:56.939443 RX Delay -410 -> 252, step: 16
6293 05:58:56.946167 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6294 05:58:56.949244 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6295 05:58:56.952839 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6296 05:58:56.956040 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6297 05:58:56.962308 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6298 05:58:56.965831 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6299 05:58:56.968884 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6300 05:58:56.972163 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6301 05:58:56.978731 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6302 05:58:56.982232 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6303 05:58:56.985552 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6304 05:58:56.989178 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6305 05:58:56.995743 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6306 05:58:56.998767 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6307 05:58:57.002328 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6308 05:58:57.008632 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6309 05:58:57.009127 ==
6310 05:58:57.012003 Dram Type= 6, Freq= 0, CH_0, rank 1
6311 05:58:57.014999 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6312 05:58:57.015494 ==
6313 05:58:57.015920 DQS Delay:
6314 05:58:57.018565 DQS0 = 43, DQS1 = 59
6315 05:58:57.019025 DQM Delay:
6316 05:58:57.021829 DQM0 = 6, DQM1 = 15
6317 05:58:57.022331 DQ Delay:
6318 05:58:57.025045 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6319 05:58:57.028295 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6320 05:58:57.031860 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6321 05:58:57.035538 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6322 05:58:57.035999
6323 05:58:57.036362
6324 05:58:57.036697 ==
6325 05:58:57.038072 Dram Type= 6, Freq= 0, CH_0, rank 1
6326 05:58:57.041647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6327 05:58:57.042111 ==
6328 05:58:57.042471
6329 05:58:57.042806
6330 05:58:57.045216 TX Vref Scan disable
6331 05:58:57.045794 == TX Byte 0 ==
6332 05:58:57.052063 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6333 05:58:57.054950 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6334 05:58:57.055417 == TX Byte 1 ==
6335 05:58:57.061535 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6336 05:58:57.064620 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6337 05:58:57.065131 ==
6338 05:58:57.068100 Dram Type= 6, Freq= 0, CH_0, rank 1
6339 05:58:57.071356 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6340 05:58:57.071822 ==
6341 05:58:57.072184
6342 05:58:57.072517
6343 05:58:57.075032 TX Vref Scan disable
6344 05:58:57.075492 == TX Byte 0 ==
6345 05:58:57.081597 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6346 05:58:57.085511 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6347 05:58:57.085979 == TX Byte 1 ==
6348 05:58:57.091355 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6349 05:58:57.094834 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6350 05:58:57.095394
6351 05:58:57.095756 [DATLAT]
6352 05:58:57.097922 Freq=400, CH0 RK1
6353 05:58:57.098388
6354 05:58:57.098746 DATLAT Default: 0xd
6355 05:58:57.101268 0, 0xFFFF, sum = 0
6356 05:58:57.101740 1, 0xFFFF, sum = 0
6357 05:58:57.104686 2, 0xFFFF, sum = 0
6358 05:58:57.105292 3, 0xFFFF, sum = 0
6359 05:58:57.107926 4, 0xFFFF, sum = 0
6360 05:58:57.108389 5, 0xFFFF, sum = 0
6361 05:58:57.111276 6, 0xFFFF, sum = 0
6362 05:58:57.114556 7, 0xFFFF, sum = 0
6363 05:58:57.115020 8, 0xFFFF, sum = 0
6364 05:58:57.118076 9, 0xFFFF, sum = 0
6365 05:58:57.118544 10, 0xFFFF, sum = 0
6366 05:58:57.121021 11, 0xFFFF, sum = 0
6367 05:58:57.121488 12, 0x0, sum = 1
6368 05:58:57.124328 13, 0x0, sum = 2
6369 05:58:57.124839 14, 0x0, sum = 3
6370 05:58:57.127864 15, 0x0, sum = 4
6371 05:58:57.128327 best_step = 13
6372 05:58:57.128680
6373 05:58:57.129227 ==
6374 05:58:57.130762 Dram Type= 6, Freq= 0, CH_0, rank 1
6375 05:58:57.134137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6376 05:58:57.134496 ==
6377 05:58:57.137838 RX Vref Scan: 0
6378 05:58:57.138252
6379 05:58:57.140962 RX Vref 0 -> 0, step: 1
6380 05:58:57.141374
6381 05:58:57.141632 RX Delay -359 -> 252, step: 8
6382 05:58:57.149502 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6383 05:58:57.153027 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6384 05:58:57.156382 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6385 05:58:57.159731 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6386 05:58:57.166464 iDelay=217, Bit 4, Center -40 (-295 ~ 216) 512
6387 05:58:57.169912 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6388 05:58:57.173034 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6389 05:58:57.176133 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6390 05:58:57.183092 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6391 05:58:57.186433 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6392 05:58:57.189901 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6393 05:58:57.196580 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6394 05:58:57.199659 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6395 05:58:57.202944 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6396 05:58:57.206012 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6397 05:58:57.213018 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6398 05:58:57.213572 ==
6399 05:58:57.215932 Dram Type= 6, Freq= 0, CH_0, rank 1
6400 05:58:57.219299 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6401 05:58:57.219759 ==
6402 05:58:57.220121 DQS Delay:
6403 05:58:57.223053 DQS0 = 52, DQS1 = 64
6404 05:58:57.223604 DQM Delay:
6405 05:58:57.226349 DQM0 = 8, DQM1 = 14
6406 05:58:57.226899 DQ Delay:
6407 05:58:57.229572 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6408 05:58:57.232600 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6409 05:58:57.235926 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6410 05:58:57.239515 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6411 05:58:57.240062
6412 05:58:57.240504
6413 05:58:57.246168 [DQSOSCAuto] RK1, (LSB)MR18= 0xbaba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6414 05:58:57.248924 CH0 RK1: MR19=C0C, MR18=BABA
6415 05:58:57.256207 CH0_RK1: MR19=0xC0C, MR18=0xBABA, DQSOSC=386, MR23=63, INC=396, DEC=264
6416 05:58:57.258997 [RxdqsGatingPostProcess] freq 400
6417 05:58:57.265612 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6418 05:58:57.269231 Pre-setting of DQS Precalculation
6419 05:58:57.272162 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6420 05:58:57.272614 ==
6421 05:58:57.275741 Dram Type= 6, Freq= 0, CH_1, rank 0
6422 05:58:57.279225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6423 05:58:57.279680 ==
6424 05:58:57.285384 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6425 05:58:57.291874 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6426 05:58:57.295399 [CA 0] Center 36 (8~64) winsize 57
6427 05:58:57.298643 [CA 1] Center 36 (8~64) winsize 57
6428 05:58:57.301849 [CA 2] Center 36 (8~64) winsize 57
6429 05:58:57.305402 [CA 3] Center 36 (8~64) winsize 57
6430 05:58:57.308611 [CA 4] Center 36 (8~64) winsize 57
6431 05:58:57.309341 [CA 5] Center 36 (8~64) winsize 57
6432 05:58:57.312382
6433 05:58:57.315393 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6434 05:58:57.315849
6435 05:58:57.318538 [CATrainingPosCal] consider 1 rank data
6436 05:58:57.321781 u2DelayCellTimex100 = 270/100 ps
6437 05:58:57.324914 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6438 05:58:57.328451 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6439 05:58:57.331759 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6440 05:58:57.335623 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6441 05:58:57.338788 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6442 05:58:57.342138 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6443 05:58:57.342705
6444 05:58:57.345056 CA PerBit enable=1, Macro0, CA PI delay=36
6445 05:58:57.345542
6446 05:58:57.348410 [CBTSetCACLKResult] CA Dly = 36
6447 05:58:57.351722 CS Dly: 1 (0~32)
6448 05:58:57.352187 ==
6449 05:58:57.355568 Dram Type= 6, Freq= 0, CH_1, rank 1
6450 05:58:57.358406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6451 05:58:57.358873 ==
6452 05:58:57.365310 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6453 05:58:57.371761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6454 05:58:57.374861 [CA 0] Center 36 (8~64) winsize 57
6455 05:58:57.375331 [CA 1] Center 36 (8~64) winsize 57
6456 05:58:57.378414 [CA 2] Center 36 (8~64) winsize 57
6457 05:58:57.381657 [CA 3] Center 36 (8~64) winsize 57
6458 05:58:57.384842 [CA 4] Center 32 (8~56) winsize 49
6459 05:58:57.388107 [CA 5] Center 36 (8~64) winsize 57
6460 05:58:57.388585
6461 05:58:57.391773 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6462 05:58:57.392344
6463 05:58:57.398198 [CATrainingPosCal] consider 2 rank data
6464 05:58:57.398801 u2DelayCellTimex100 = 270/100 ps
6465 05:58:57.405079 CA0 delay=36 (8~64),Diff = 4 PI (57 cell)
6466 05:58:57.407838 CA1 delay=36 (8~64),Diff = 4 PI (57 cell)
6467 05:58:57.411432 CA2 delay=36 (8~64),Diff = 4 PI (57 cell)
6468 05:58:57.414364 CA3 delay=36 (8~64),Diff = 4 PI (57 cell)
6469 05:58:57.417741 CA4 delay=32 (8~56),Diff = 0 PI (0 cell)
6470 05:58:57.421310 CA5 delay=36 (8~64),Diff = 4 PI (57 cell)
6471 05:58:57.421772
6472 05:58:57.424691 CA PerBit enable=1, Macro0, CA PI delay=32
6473 05:58:57.425290
6474 05:58:57.427966 [CBTSetCACLKResult] CA Dly = 32
6475 05:58:57.431265 CS Dly: 1 (0~32)
6476 05:58:57.431772
6477 05:58:57.434312 ----->DramcWriteLeveling(PI) begin...
6478 05:58:57.434829 ==
6479 05:58:57.437621 Dram Type= 6, Freq= 0, CH_1, rank 0
6480 05:58:57.440950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6481 05:58:57.441502 ==
6482 05:58:57.444119 Write leveling (Byte 0): 32 => 0
6483 05:58:57.447142 Write leveling (Byte 1): 32 => 0
6484 05:58:57.450832 DramcWriteLeveling(PI) end<-----
6485 05:58:57.451295
6486 05:58:57.451654 ==
6487 05:58:57.453844 Dram Type= 6, Freq= 0, CH_1, rank 0
6488 05:58:57.457706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6489 05:58:57.458173 ==
6490 05:58:57.460607 [Gating] SW mode calibration
6491 05:58:57.467445 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6492 05:58:57.474014 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6493 05:58:57.477437 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6494 05:58:57.483824 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 05:58:57.487140 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 05:58:57.490387 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6497 05:58:57.494071 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 05:58:57.501077 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 05:58:57.503748 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 05:58:57.506909 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6501 05:58:57.513859 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 05:58:57.516660 Total UI for P1: 0, mck2ui 16
6503 05:58:57.520084 best dqsien dly found for B0: ( 0, 10, 16)
6504 05:58:57.523644 Total UI for P1: 0, mck2ui 16
6505 05:58:57.526950 best dqsien dly found for B1: ( 0, 10, 16)
6506 05:58:57.530044 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6507 05:58:57.533353 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6508 05:58:57.533818
6509 05:58:57.536858 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6510 05:58:57.540300 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6511 05:58:57.543357 [Gating] SW calibration Done
6512 05:58:57.543904 ==
6513 05:58:57.546997 Dram Type= 6, Freq= 0, CH_1, rank 0
6514 05:58:57.549683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6515 05:58:57.553518 ==
6516 05:58:57.553981 RX Vref Scan: 0
6517 05:58:57.554348
6518 05:58:57.556299 RX Vref 0 -> 0, step: 1
6519 05:58:57.556691
6520 05:58:57.559318 RX Delay -410 -> 252, step: 16
6521 05:58:57.562863 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6522 05:58:57.566106 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6523 05:58:57.569509 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6524 05:58:57.576209 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6525 05:58:57.579684 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6526 05:58:57.583306 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6527 05:58:57.586351 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6528 05:58:57.592881 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6529 05:58:57.595724 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6530 05:58:57.598965 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6531 05:58:57.605971 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6532 05:58:57.609187 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6533 05:58:57.612134 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6534 05:58:57.615510 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6535 05:58:57.622264 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6536 05:58:57.625626 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6537 05:58:57.626190 ==
6538 05:58:57.628566 Dram Type= 6, Freq= 0, CH_1, rank 0
6539 05:58:57.632096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6540 05:58:57.632767 ==
6541 05:58:57.635290 DQS Delay:
6542 05:58:57.635661 DQS0 = 43, DQS1 = 59
6543 05:58:57.639240 DQM Delay:
6544 05:58:57.639658 DQM0 = 6, DQM1 = 16
6545 05:58:57.640000 DQ Delay:
6546 05:58:57.641957 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6547 05:58:57.645589 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6548 05:58:57.648475 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6549 05:58:57.651906 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6550 05:58:57.652332
6551 05:58:57.652658
6552 05:58:57.653076 ==
6553 05:58:57.655207 Dram Type= 6, Freq= 0, CH_1, rank 0
6554 05:58:57.658641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6555 05:58:57.662071 ==
6556 05:58:57.662490
6557 05:58:57.662817
6558 05:58:57.663124 TX Vref Scan disable
6559 05:58:57.665212 == TX Byte 0 ==
6560 05:58:57.668376 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6561 05:58:57.672221 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6562 05:58:57.675091 == TX Byte 1 ==
6563 05:58:57.678552 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6564 05:58:57.681642 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6565 05:58:57.682063 ==
6566 05:58:57.684876 Dram Type= 6, Freq= 0, CH_1, rank 0
6567 05:58:57.691918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6568 05:58:57.692340 ==
6569 05:58:57.692671
6570 05:58:57.693031
6571 05:58:57.693328 TX Vref Scan disable
6572 05:58:57.695047 == TX Byte 0 ==
6573 05:58:57.698218 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6574 05:58:57.704683 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6575 05:58:57.705144 == TX Byte 1 ==
6576 05:58:57.707909 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6577 05:58:57.714581 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6578 05:58:57.715171
6579 05:58:57.715658 [DATLAT]
6580 05:58:57.716177 Freq=400, CH1 RK0
6581 05:58:57.716756
6582 05:58:57.718275 DATLAT Default: 0xf
6583 05:58:57.718841 0, 0xFFFF, sum = 0
6584 05:58:57.721338 1, 0xFFFF, sum = 0
6585 05:58:57.724834 2, 0xFFFF, sum = 0
6586 05:58:57.725389 3, 0xFFFF, sum = 0
6587 05:58:57.727952 4, 0xFFFF, sum = 0
6588 05:58:57.728592 5, 0xFFFF, sum = 0
6589 05:58:57.731163 6, 0xFFFF, sum = 0
6590 05:58:57.731737 7, 0xFFFF, sum = 0
6591 05:58:57.734719 8, 0xFFFF, sum = 0
6592 05:58:57.735524 9, 0xFFFF, sum = 0
6593 05:58:57.737729 10, 0xFFFF, sum = 0
6594 05:58:57.738082 11, 0xFFFF, sum = 0
6595 05:58:57.741039 12, 0x0, sum = 1
6596 05:58:57.741416 13, 0x0, sum = 2
6597 05:58:57.744694 14, 0x0, sum = 3
6598 05:58:57.745338 15, 0x0, sum = 4
6599 05:58:57.747767 best_step = 13
6600 05:58:57.748101
6601 05:58:57.748378 ==
6602 05:58:57.750969 Dram Type= 6, Freq= 0, CH_1, rank 0
6603 05:58:57.754032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6604 05:58:57.754307 ==
6605 05:58:57.754542 RX Vref Scan: 1
6606 05:58:57.757428
6607 05:58:57.757779 RX Vref 0 -> 0, step: 1
6608 05:58:57.758065
6609 05:58:57.761168 RX Delay -359 -> 252, step: 8
6610 05:58:57.761427
6611 05:58:57.764502 Set Vref, RX VrefLevel [Byte0]: 52
6612 05:58:57.767441 [Byte1]: 50
6613 05:58:57.771765
6614 05:58:57.772029 Final RX Vref Byte 0 = 52 to rank0
6615 05:58:57.774795 Final RX Vref Byte 1 = 50 to rank0
6616 05:58:57.778223 Final RX Vref Byte 0 = 52 to rank1
6617 05:58:57.781694 Final RX Vref Byte 1 = 50 to rank1==
6618 05:58:57.785415 Dram Type= 6, Freq= 0, CH_1, rank 0
6619 05:58:57.791494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6620 05:58:57.791806 ==
6621 05:58:57.792079 DQS Delay:
6622 05:58:57.794887 DQS0 = 48, DQS1 = 64
6623 05:58:57.795173 DQM Delay:
6624 05:58:57.795426 DQM0 = 9, DQM1 = 16
6625 05:58:57.798072 DQ Delay:
6626 05:58:57.801378 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =8
6627 05:58:57.801489 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6628 05:58:57.804390 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6629 05:58:57.807694 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6630 05:58:57.807797
6631 05:58:57.811314
6632 05:58:57.817736 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbcb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6633 05:58:57.821102 CH1 RK0: MR19=C0C, MR18=CBCB
6634 05:58:57.827399 CH1_RK0: MR19=0xC0C, MR18=0xCBCB, DQSOSC=384, MR23=63, INC=400, DEC=267
6635 05:58:57.827501 ==
6636 05:58:57.830715 Dram Type= 6, Freq= 0, CH_1, rank 1
6637 05:58:57.834225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6638 05:58:57.834308 ==
6639 05:58:57.837858 [Gating] SW mode calibration
6640 05:58:57.844302 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6641 05:58:57.850699 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6642 05:58:57.854310 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6643 05:58:57.857609 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6644 05:58:57.864030 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6645 05:58:57.867234 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6646 05:58:57.870388 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6647 05:58:57.877496 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6648 05:58:57.880508 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6649 05:58:57.883915 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6650 05:58:57.890611 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6651 05:58:57.890693 Total UI for P1: 0, mck2ui 16
6652 05:58:57.893670 best dqsien dly found for B0: ( 0, 10, 16)
6653 05:58:57.897373 Total UI for P1: 0, mck2ui 16
6654 05:58:57.900563 best dqsien dly found for B1: ( 0, 10, 16)
6655 05:58:57.907381 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6656 05:58:57.910227 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6657 05:58:57.910309
6658 05:58:57.913505 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6659 05:58:57.916922 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6660 05:58:57.920416 [Gating] SW calibration Done
6661 05:58:57.920497 ==
6662 05:58:57.923895 Dram Type= 6, Freq= 0, CH_1, rank 1
6663 05:58:57.927154 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6664 05:58:57.927236 ==
6665 05:58:57.930255 RX Vref Scan: 0
6666 05:58:57.930337
6667 05:58:57.930401 RX Vref 0 -> 0, step: 1
6668 05:58:57.930461
6669 05:58:57.933423 RX Delay -410 -> 252, step: 16
6670 05:58:57.940080 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6671 05:58:57.943353 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6672 05:58:57.946739 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6673 05:58:57.950063 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6674 05:58:57.956568 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6675 05:58:57.959832 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6676 05:58:57.963191 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6677 05:58:57.966503 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6678 05:58:57.973278 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6679 05:58:57.976571 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6680 05:58:57.979523 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6681 05:58:57.983098 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6682 05:58:57.989694 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6683 05:58:57.993130 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6684 05:58:57.996111 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6685 05:58:58.002624 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6686 05:58:58.002706 ==
6687 05:58:58.005946 Dram Type= 6, Freq= 0, CH_1, rank 1
6688 05:58:58.009158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6689 05:58:58.009240 ==
6690 05:58:58.009304 DQS Delay:
6691 05:58:58.012720 DQS0 = 35, DQS1 = 59
6692 05:58:58.012817 DQM Delay:
6693 05:58:58.015739 DQM0 = 2, DQM1 = 17
6694 05:58:58.015824 DQ Delay:
6695 05:58:58.019205 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6696 05:58:58.022808 DQ4 =0, DQ5 =8, DQ6 =8, DQ7 =0
6697 05:58:58.025924 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6698 05:58:58.029564 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6699 05:58:58.029647
6700 05:58:58.029711
6701 05:58:58.029770 ==
6702 05:58:58.032730 Dram Type= 6, Freq= 0, CH_1, rank 1
6703 05:58:58.035791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6704 05:58:58.035880 ==
6705 05:58:58.035949
6706 05:58:58.036011
6707 05:58:58.039201 TX Vref Scan disable
6708 05:58:58.039289 == TX Byte 0 ==
6709 05:58:58.045785 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6710 05:58:58.049434 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6711 05:58:58.049540 == TX Byte 1 ==
6712 05:58:58.055965 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6713 05:58:58.058989 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6714 05:58:58.059122 ==
6715 05:58:58.062975 Dram Type= 6, Freq= 0, CH_1, rank 1
6716 05:58:58.065646 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6717 05:58:58.065781 ==
6718 05:58:58.065858
6719 05:58:58.065926
6720 05:58:58.068853 TX Vref Scan disable
6721 05:58:58.068968 == TX Byte 0 ==
6722 05:58:58.075457 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6723 05:58:58.079029 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6724 05:58:58.079150 == TX Byte 1 ==
6725 05:58:58.085650 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6726 05:58:58.088655 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6727 05:58:58.088790
6728 05:58:58.088871 [DATLAT]
6729 05:58:58.092145 Freq=400, CH1 RK1
6730 05:58:58.092278
6731 05:58:58.092360 DATLAT Default: 0xd
6732 05:58:58.095833 0, 0xFFFF, sum = 0
6733 05:58:58.095941 1, 0xFFFF, sum = 0
6734 05:58:58.098692 2, 0xFFFF, sum = 0
6735 05:58:58.098795 3, 0xFFFF, sum = 0
6736 05:58:58.102113 4, 0xFFFF, sum = 0
6737 05:58:58.102208 5, 0xFFFF, sum = 0
6738 05:58:58.105370 6, 0xFFFF, sum = 0
6739 05:58:58.105483 7, 0xFFFF, sum = 0
6740 05:58:58.108570 8, 0xFFFF, sum = 0
6741 05:58:58.112023 9, 0xFFFF, sum = 0
6742 05:58:58.112207 10, 0xFFFF, sum = 0
6743 05:58:58.115357 11, 0xFFFF, sum = 0
6744 05:58:58.115628 12, 0x0, sum = 1
6745 05:58:58.118511 13, 0x0, sum = 2
6746 05:58:58.118602 14, 0x0, sum = 3
6747 05:58:58.118688 15, 0x0, sum = 4
6748 05:58:58.121666 best_step = 13
6749 05:58:58.121847
6750 05:58:58.121975 ==
6751 05:58:58.124990 Dram Type= 6, Freq= 0, CH_1, rank 1
6752 05:58:58.128591 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6753 05:58:58.128773 ==
6754 05:58:58.131492 RX Vref Scan: 0
6755 05:58:58.131615
6756 05:58:58.135224 RX Vref 0 -> 0, step: 1
6757 05:58:58.135336
6758 05:58:58.135404 RX Delay -359 -> 252, step: 8
6759 05:58:58.143852 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6760 05:58:58.146798 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6761 05:58:58.150431 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6762 05:58:58.156879 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6763 05:58:58.160333 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6764 05:58:58.163310 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6765 05:58:58.166698 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6766 05:58:58.173252 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6767 05:58:58.176436 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6768 05:58:58.179894 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6769 05:58:58.183238 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6770 05:58:58.189476 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6771 05:58:58.193086 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6772 05:58:58.196699 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6773 05:58:58.203401 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6774 05:58:58.206115 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6775 05:58:58.206546 ==
6776 05:58:58.209852 Dram Type= 6, Freq= 0, CH_1, rank 1
6777 05:58:58.213297 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6778 05:58:58.213860 ==
6779 05:58:58.216405 DQS Delay:
6780 05:58:58.216927 DQS0 = 48, DQS1 = 64
6781 05:58:58.217296 DQM Delay:
6782 05:58:58.219707 DQM0 = 9, DQM1 = 15
6783 05:58:58.220126 DQ Delay:
6784 05:58:58.222741 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6785 05:58:58.226736 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6786 05:58:58.229690 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6787 05:58:58.232972 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6788 05:58:58.233436
6789 05:58:58.233796
6790 05:58:58.243379 [DQSOSCAuto] RK1, (LSB)MR18= 0xa7a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6791 05:58:58.243955 CH1 RK1: MR19=C0C, MR18=A7A7
6792 05:58:58.249476 CH1_RK1: MR19=0xC0C, MR18=0xA7A7, DQSOSC=389, MR23=63, INC=390, DEC=260
6793 05:58:58.253178 [RxdqsGatingPostProcess] freq 400
6794 05:58:58.259352 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6795 05:58:58.262812 Pre-setting of DQS Precalculation
6796 05:58:58.266288 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6797 05:58:58.272601 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6798 05:58:58.282302 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6799 05:58:58.282858
6800 05:58:58.283219
6801 05:58:58.285508 [Calibration Summary] 800 Mbps
6802 05:58:58.285590 CH 0, Rank 0
6803 05:58:58.288974 SW Impedance : PASS
6804 05:58:58.289056 DUTY Scan : NO K
6805 05:58:58.292482 ZQ Calibration : PASS
6806 05:58:58.293003 Jitter Meter : NO K
6807 05:58:58.295865 CBT Training : PASS
6808 05:58:58.299135 Write leveling : PASS
6809 05:58:58.299586 RX DQS gating : PASS
6810 05:58:58.302192 RX DQ/DQS(RDDQC) : PASS
6811 05:58:58.305864 TX DQ/DQS : PASS
6812 05:58:58.306329 RX DATLAT : PASS
6813 05:58:58.309204 RX DQ/DQS(Engine): PASS
6814 05:58:58.312024 TX OE : NO K
6815 05:58:58.312489 All Pass.
6816 05:58:58.312905
6817 05:58:58.313461 CH 0, Rank 1
6818 05:58:58.315614 SW Impedance : PASS
6819 05:58:58.319231 DUTY Scan : NO K
6820 05:58:58.319689 ZQ Calibration : PASS
6821 05:58:58.321822 Jitter Meter : NO K
6822 05:58:58.325413 CBT Training : PASS
6823 05:58:58.325833 Write leveling : NO K
6824 05:58:58.328897 RX DQS gating : PASS
6825 05:58:58.332021 RX DQ/DQS(RDDQC) : PASS
6826 05:58:58.332438 TX DQ/DQS : PASS
6827 05:58:58.335225 RX DATLAT : PASS
6828 05:58:58.338454 RX DQ/DQS(Engine): PASS
6829 05:58:58.338873 TX OE : NO K
6830 05:58:58.339203 All Pass.
6831 05:58:58.341794
6832 05:58:58.342211 CH 1, Rank 0
6833 05:58:58.345290 SW Impedance : PASS
6834 05:58:58.345711 DUTY Scan : NO K
6835 05:58:58.348603 ZQ Calibration : PASS
6836 05:58:58.349059 Jitter Meter : NO K
6837 05:58:58.351969 CBT Training : PASS
6838 05:58:58.355116 Write leveling : PASS
6839 05:58:58.355535 RX DQS gating : PASS
6840 05:58:58.358366 RX DQ/DQS(RDDQC) : PASS
6841 05:58:58.361787 TX DQ/DQS : PASS
6842 05:58:58.362202 RX DATLAT : PASS
6843 05:58:58.365253 RX DQ/DQS(Engine): PASS
6844 05:58:58.368217 TX OE : NO K
6845 05:58:58.368632 All Pass.
6846 05:58:58.369020
6847 05:58:58.369357 CH 1, Rank 1
6848 05:58:58.371573 SW Impedance : PASS
6849 05:58:58.375041 DUTY Scan : NO K
6850 05:58:58.375484 ZQ Calibration : PASS
6851 05:58:58.378464 Jitter Meter : NO K
6852 05:58:58.381581 CBT Training : PASS
6853 05:58:58.382011 Write leveling : NO K
6854 05:58:58.384931 RX DQS gating : PASS
6855 05:58:58.388198 RX DQ/DQS(RDDQC) : PASS
6856 05:58:58.388627 TX DQ/DQS : PASS
6857 05:58:58.391406 RX DATLAT : PASS
6858 05:58:58.394885 RX DQ/DQS(Engine): PASS
6859 05:58:58.395314 TX OE : NO K
6860 05:58:58.398070 All Pass.
6861 05:58:58.398497
6862 05:58:58.398925 DramC Write-DBI off
6863 05:58:58.401335 PER_BANK_REFRESH: Hybrid Mode
6864 05:58:58.401763 TX_TRACKING: ON
6865 05:58:58.411166 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6866 05:58:58.414887 [FAST_K] Save calibration result to emmc
6867 05:58:58.418001 dramc_set_vcore_voltage set vcore to 725000
6868 05:58:58.421595 Read voltage for 1600, 0
6869 05:58:58.422036 Vio18 = 0
6870 05:58:58.424542 Vcore = 725000
6871 05:58:58.425007 Vdram = 0
6872 05:58:58.425334 Vddq = 0
6873 05:58:58.427628 Vmddr = 0
6874 05:58:58.431140 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6875 05:58:58.437656 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6876 05:58:58.438074 MEM_TYPE=3, freq_sel=13
6877 05:58:58.441229 sv_algorithm_assistance_LP4_3733
6878 05:58:58.448363 ============ PULL DRAM RESETB DOWN ============
6879 05:58:58.451152 ========== PULL DRAM RESETB DOWN end =========
6880 05:58:58.454118 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6881 05:58:58.457557 ===================================
6882 05:58:58.461082 LPDDR4 DRAM CONFIGURATION
6883 05:58:58.464364 ===================================
6884 05:58:58.467892 EX_ROW_EN[0] = 0x0
6885 05:58:58.468491 EX_ROW_EN[1] = 0x0
6886 05:58:58.471182 LP4Y_EN = 0x0
6887 05:58:58.471806 WORK_FSP = 0x1
6888 05:58:58.474112 WL = 0x5
6889 05:58:58.474686 RL = 0x5
6890 05:58:58.477242 BL = 0x2
6891 05:58:58.477701 RPST = 0x0
6892 05:58:58.480943 RD_PRE = 0x0
6893 05:58:58.481501 WR_PRE = 0x1
6894 05:58:58.484081 WR_PST = 0x1
6895 05:58:58.484538 DBI_WR = 0x0
6896 05:58:58.487619 DBI_RD = 0x0
6897 05:58:58.488262 OTF = 0x1
6898 05:58:58.490450 ===================================
6899 05:58:58.493670 ===================================
6900 05:58:58.497177 ANA top config
6901 05:58:58.500660 ===================================
6902 05:58:58.503854 DLL_ASYNC_EN = 0
6903 05:58:58.504319 ALL_SLAVE_EN = 0
6904 05:58:58.507215 NEW_RANK_MODE = 1
6905 05:58:58.510551 DLL_IDLE_MODE = 1
6906 05:58:58.513789 LP45_APHY_COMB_EN = 1
6907 05:58:58.514456 TX_ODT_DIS = 0
6908 05:58:58.517071 NEW_8X_MODE = 1
6909 05:58:58.520424 ===================================
6910 05:58:58.523809 ===================================
6911 05:58:58.527285 data_rate = 3200
6912 05:58:58.530419 CKR = 1
6913 05:58:58.533424 DQ_P2S_RATIO = 8
6914 05:58:58.536879 ===================================
6915 05:58:58.540268 CA_P2S_RATIO = 8
6916 05:58:58.544055 DQ_CA_OPEN = 0
6917 05:58:58.544641 DQ_SEMI_OPEN = 0
6918 05:58:58.546988 CA_SEMI_OPEN = 0
6919 05:58:58.550326 CA_FULL_RATE = 0
6920 05:58:58.553523 DQ_CKDIV4_EN = 0
6921 05:58:58.556601 CA_CKDIV4_EN = 0
6922 05:58:58.559732 CA_PREDIV_EN = 0
6923 05:58:58.560206 PH8_DLY = 12
6924 05:58:58.563263 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6925 05:58:58.566681 DQ_AAMCK_DIV = 4
6926 05:58:58.570077 CA_AAMCK_DIV = 4
6927 05:58:58.573193 CA_ADMCK_DIV = 4
6928 05:58:58.576687 DQ_TRACK_CA_EN = 0
6929 05:58:58.577187 CA_PICK = 1600
6930 05:58:58.580436 CA_MCKIO = 1600
6931 05:58:58.583074 MCKIO_SEMI = 0
6932 05:58:58.585852 PLL_FREQ = 3068
6933 05:58:58.589480 DQ_UI_PI_RATIO = 32
6934 05:58:58.592733 CA_UI_PI_RATIO = 0
6935 05:58:58.595814 ===================================
6936 05:58:58.599088 ===================================
6937 05:58:58.602292 memory_type:LPDDR4
6938 05:58:58.602371 GP_NUM : 10
6939 05:58:58.605675 SRAM_EN : 1
6940 05:58:58.605750 MD32_EN : 0
6941 05:58:58.608863 ===================================
6942 05:58:58.612156 [ANA_INIT] >>>>>>>>>>>>>>
6943 05:58:58.615517 <<<<<< [CONFIGURE PHASE]: ANA_TX
6944 05:58:58.619042 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6945 05:58:58.622344 ===================================
6946 05:58:58.625652 data_rate = 3200,PCW = 0X7600
6947 05:58:58.628508 ===================================
6948 05:58:58.631939 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6949 05:58:58.638610 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6950 05:58:58.641829 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6951 05:58:58.648406 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6952 05:58:58.651579 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6953 05:58:58.655102 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6954 05:58:58.655176 [ANA_INIT] flow start
6955 05:58:58.658209 [ANA_INIT] PLL >>>>>>>>
6956 05:58:58.661660 [ANA_INIT] PLL <<<<<<<<
6957 05:58:58.661732 [ANA_INIT] MIDPI >>>>>>>>
6958 05:58:58.665221 [ANA_INIT] MIDPI <<<<<<<<
6959 05:58:58.668057 [ANA_INIT] DLL >>>>>>>>
6960 05:58:58.671640 [ANA_INIT] DLL <<<<<<<<
6961 05:58:58.671729 [ANA_INIT] flow end
6962 05:58:58.674677 ============ LP4 DIFF to SE enter ============
6963 05:58:58.681412 ============ LP4 DIFF to SE exit ============
6964 05:58:58.681500 [ANA_INIT] <<<<<<<<<<<<<
6965 05:58:58.684529 [Flow] Enable top DCM control >>>>>
6966 05:58:58.688283 [Flow] Enable top DCM control <<<<<
6967 05:58:58.691218 Enable DLL master slave shuffle
6968 05:58:58.697796 ==============================================================
6969 05:58:58.697883 Gating Mode config
6970 05:58:58.704701 ==============================================================
6971 05:58:58.707855 Config description:
6972 05:58:58.717977 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6973 05:58:58.724029 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6974 05:58:58.727480 SELPH_MODE 0: By rank 1: By Phase
6975 05:58:58.734250 ==============================================================
6976 05:58:58.737707 GAT_TRACK_EN = 1
6977 05:58:58.740952 RX_GATING_MODE = 2
6978 05:58:58.741036 RX_GATING_TRACK_MODE = 2
6979 05:58:58.744263 SELPH_MODE = 1
6980 05:58:58.747475 PICG_EARLY_EN = 1
6981 05:58:58.750646 VALID_LAT_VALUE = 1
6982 05:58:58.757222 ==============================================================
6983 05:58:58.760594 Enter into Gating configuration >>>>
6984 05:58:58.763760 Exit from Gating configuration <<<<
6985 05:58:58.767312 Enter into DVFS_PRE_config >>>>>
6986 05:58:58.777224 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6987 05:58:58.780580 Exit from DVFS_PRE_config <<<<<
6988 05:58:58.784056 Enter into PICG configuration >>>>
6989 05:58:58.786952 Exit from PICG configuration <<<<
6990 05:58:58.790267 [RX_INPUT] configuration >>>>>
6991 05:58:58.793532 [RX_INPUT] configuration <<<<<
6992 05:58:58.797179 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6993 05:58:58.803796 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6994 05:58:58.810085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6995 05:58:58.816853 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6996 05:58:58.823365 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6997 05:58:58.826769 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6998 05:58:58.833644 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6999 05:58:58.836451 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7000 05:58:58.839807 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7001 05:58:58.843259 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7002 05:58:58.849976 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7003 05:58:58.853301 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7004 05:58:58.856577 ===================================
7005 05:58:58.859670 LPDDR4 DRAM CONFIGURATION
7006 05:58:58.863156 ===================================
7007 05:58:58.863240 EX_ROW_EN[0] = 0x0
7008 05:58:58.866265 EX_ROW_EN[1] = 0x0
7009 05:58:58.866347 LP4Y_EN = 0x0
7010 05:58:58.869759 WORK_FSP = 0x1
7011 05:58:58.869843 WL = 0x5
7012 05:58:58.873239 RL = 0x5
7013 05:58:58.873322 BL = 0x2
7014 05:58:58.876697 RPST = 0x0
7015 05:58:58.876819 RD_PRE = 0x0
7016 05:58:58.879647 WR_PRE = 0x1
7017 05:58:58.882983 WR_PST = 0x1
7018 05:58:58.883066 DBI_WR = 0x0
7019 05:58:58.885862 DBI_RD = 0x0
7020 05:58:58.885946 OTF = 0x1
7021 05:58:58.890312 ===================================
7022 05:58:58.892575 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7023 05:58:58.899333 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7024 05:58:58.902573 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7025 05:58:58.905937 ===================================
7026 05:58:58.909400 LPDDR4 DRAM CONFIGURATION
7027 05:58:58.912657 ===================================
7028 05:58:58.912810 EX_ROW_EN[0] = 0x10
7029 05:58:58.915825 EX_ROW_EN[1] = 0x0
7030 05:58:58.915937 LP4Y_EN = 0x0
7031 05:58:58.919157 WORK_FSP = 0x1
7032 05:58:58.919241 WL = 0x5
7033 05:58:58.922522 RL = 0x5
7034 05:58:58.922634 BL = 0x2
7035 05:58:58.926045 RPST = 0x0
7036 05:58:58.929200 RD_PRE = 0x0
7037 05:58:58.929281 WR_PRE = 0x1
7038 05:58:58.932163 WR_PST = 0x1
7039 05:58:58.932243 DBI_WR = 0x0
7040 05:58:58.935474 DBI_RD = 0x0
7041 05:58:58.935554 OTF = 0x1
7042 05:58:58.938991 ===================================
7043 05:58:58.945424 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7044 05:58:58.945534 ==
7045 05:58:58.948541 Dram Type= 6, Freq= 0, CH_0, rank 0
7046 05:58:58.952045 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7047 05:58:58.952153 ==
7048 05:58:58.955393 [Duty_Offset_Calibration]
7049 05:58:58.958491 B0:0 B1:2 CA:1
7050 05:58:58.958571
7051 05:58:58.961795 [DutyScan_Calibration_Flow] k_type=0
7052 05:58:58.970278
7053 05:58:58.970357 ==CLK 0==
7054 05:58:58.973471 Final CLK duty delay cell = 0
7055 05:58:58.976960 [0] MAX Duty = 5156%(X100), DQS PI = 22
7056 05:58:58.980116 [0] MIN Duty = 4938%(X100), DQS PI = 50
7057 05:58:58.983614 [0] AVG Duty = 5047%(X100)
7058 05:58:58.983695
7059 05:58:58.987038 CH0 CLK Duty spec in!! Max-Min= 218%
7060 05:58:58.990098 [DutyScan_Calibration_Flow] ====Done====
7061 05:58:58.990181
7062 05:58:58.993378 [DutyScan_Calibration_Flow] k_type=1
7063 05:58:59.010580
7064 05:58:59.010660 ==DQS 0 ==
7065 05:58:59.013611 Final DQS duty delay cell = 0
7066 05:58:59.016909 [0] MAX Duty = 5156%(X100), DQS PI = 34
7067 05:58:59.020621 [0] MIN Duty = 5031%(X100), DQS PI = 14
7068 05:58:59.023469 [0] AVG Duty = 5093%(X100)
7069 05:58:59.023549
7070 05:58:59.023650 ==DQS 1 ==
7071 05:58:59.026740 Final DQS duty delay cell = 0
7072 05:58:59.030610 [0] MAX Duty = 5031%(X100), DQS PI = 2
7073 05:58:59.033754 [0] MIN Duty = 4876%(X100), DQS PI = 16
7074 05:58:59.037013 [0] AVG Duty = 4953%(X100)
7075 05:58:59.037094
7076 05:58:59.039987 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7077 05:58:59.040067
7078 05:58:59.043427 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7079 05:58:59.046737 [DutyScan_Calibration_Flow] ====Done====
7080 05:58:59.046817
7081 05:58:59.049977 [DutyScan_Calibration_Flow] k_type=3
7082 05:58:59.067953
7083 05:58:59.068050 ==DQM 0 ==
7084 05:58:59.070827 Final DQM duty delay cell = 0
7085 05:58:59.074127 [0] MAX Duty = 5187%(X100), DQS PI = 22
7086 05:58:59.077722 [0] MIN Duty = 4907%(X100), DQS PI = 42
7087 05:58:59.080974 [0] AVG Duty = 5047%(X100)
7088 05:58:59.081075
7089 05:58:59.081186 ==DQM 1 ==
7090 05:58:59.084088 Final DQM duty delay cell = 0
7091 05:58:59.087487 [0] MAX Duty = 5000%(X100), DQS PI = 4
7092 05:58:59.090825 [0] MIN Duty = 4782%(X100), DQS PI = 14
7093 05:58:59.095009 [0] AVG Duty = 4891%(X100)
7094 05:58:59.095093
7095 05:58:59.097349 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7096 05:58:59.097431
7097 05:58:59.100575 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7098 05:58:59.104018 [DutyScan_Calibration_Flow] ====Done====
7099 05:58:59.104104
7100 05:58:59.107482 [DutyScan_Calibration_Flow] k_type=2
7101 05:58:59.124398
7102 05:58:59.125036 ==DQ 0 ==
7103 05:58:59.127897 Final DQ duty delay cell = 0
7104 05:58:59.131394 [0] MAX Duty = 5218%(X100), DQS PI = 18
7105 05:58:59.133891 [0] MIN Duty = 4938%(X100), DQS PI = 56
7106 05:58:59.134024 [0] AVG Duty = 5078%(X100)
7107 05:58:59.137127
7108 05:58:59.137213 ==DQ 1 ==
7109 05:58:59.140606 Final DQ duty delay cell = -4
7110 05:58:59.143838 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7111 05:58:59.147204 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7112 05:58:59.150613 [-4] AVG Duty = 4969%(X100)
7113 05:58:59.150785
7114 05:58:59.153809 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7115 05:58:59.153980
7116 05:58:59.157202 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7117 05:58:59.160377 [DutyScan_Calibration_Flow] ====Done====
7118 05:58:59.160511 ==
7119 05:58:59.163786 Dram Type= 6, Freq= 0, CH_1, rank 0
7120 05:58:59.167070 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7121 05:58:59.167221 ==
7122 05:58:59.170484 [Duty_Offset_Calibration]
7123 05:58:59.170654 B0:0 B1:4 CA:-5
7124 05:58:59.170788
7125 05:58:59.173938 [DutyScan_Calibration_Flow] k_type=0
7126 05:58:59.184747
7127 05:58:59.185078 ==CLK 0==
7128 05:58:59.188451 Final CLK duty delay cell = 0
7129 05:58:59.191615 [0] MAX Duty = 5156%(X100), DQS PI = 20
7130 05:58:59.194840 [0] MIN Duty = 4875%(X100), DQS PI = 50
7131 05:58:59.195218 [0] AVG Duty = 5015%(X100)
7132 05:58:59.198628
7133 05:58:59.201992 CH1 CLK Duty spec in!! Max-Min= 281%
7134 05:58:59.204796 [DutyScan_Calibration_Flow] ====Done====
7135 05:58:59.205251
7136 05:58:59.208442 [DutyScan_Calibration_Flow] k_type=1
7137 05:58:59.223772
7138 05:58:59.224241 ==DQS 0 ==
7139 05:58:59.227345 Final DQS duty delay cell = 0
7140 05:58:59.230613 [0] MAX Duty = 5156%(X100), DQS PI = 18
7141 05:58:59.233671 [0] MIN Duty = 4876%(X100), DQS PI = 44
7142 05:58:59.237176 [0] AVG Duty = 5016%(X100)
7143 05:58:59.237644
7144 05:58:59.237996 ==DQS 1 ==
7145 05:58:59.240563 Final DQS duty delay cell = -4
7146 05:58:59.244270 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7147 05:58:59.247093 [-4] MIN Duty = 4875%(X100), DQS PI = 38
7148 05:58:59.250218 [-4] AVG Duty = 4937%(X100)
7149 05:58:59.250689
7150 05:58:59.253752 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7151 05:58:59.254227
7152 05:58:59.257175 CH1 DQS 1 Duty spec in!! Max-Min= 125%
7153 05:58:59.260835 [DutyScan_Calibration_Flow] ====Done====
7154 05:58:59.261385
7155 05:58:59.263978 [DutyScan_Calibration_Flow] k_type=3
7156 05:58:59.279383
7157 05:58:59.279938 ==DQM 0 ==
7158 05:58:59.282651 Final DQM duty delay cell = -4
7159 05:58:59.285944 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7160 05:58:59.289470 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7161 05:58:59.293202 [-4] AVG Duty = 4937%(X100)
7162 05:58:59.293757
7163 05:58:59.294121 ==DQM 1 ==
7164 05:58:59.296138 Final DQM duty delay cell = -4
7165 05:58:59.299715 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7166 05:58:59.302873 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7167 05:58:59.306347 [-4] AVG Duty = 5000%(X100)
7168 05:58:59.306833
7169 05:58:59.310035 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7170 05:58:59.310651
7171 05:58:59.312892 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7172 05:58:59.316245 [DutyScan_Calibration_Flow] ====Done====
7173 05:58:59.316702
7174 05:58:59.319381 [DutyScan_Calibration_Flow] k_type=2
7175 05:58:59.337354
7176 05:58:59.337933 ==DQ 0 ==
7177 05:58:59.340835 Final DQ duty delay cell = 0
7178 05:58:59.344221 [0] MAX Duty = 5093%(X100), DQS PI = 20
7179 05:58:59.347666 [0] MIN Duty = 4969%(X100), DQS PI = 44
7180 05:58:59.350219 [0] AVG Duty = 5031%(X100)
7181 05:58:59.350676
7182 05:58:59.351095 ==DQ 1 ==
7183 05:58:59.354190 Final DQ duty delay cell = 0
7184 05:58:59.357052 [0] MAX Duty = 5031%(X100), DQS PI = 4
7185 05:58:59.360626 [0] MIN Duty = 4876%(X100), DQS PI = 28
7186 05:58:59.361313 [0] AVG Duty = 4953%(X100)
7187 05:58:59.363495
7188 05:58:59.366908 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7189 05:58:59.367394
7190 05:58:59.370319 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7191 05:58:59.373357 [DutyScan_Calibration_Flow] ====Done====
7192 05:58:59.376876 nWR fixed to 30
7193 05:58:59.380141 [ModeRegInit_LP4] CH0 RK0
7194 05:58:59.380759 [ModeRegInit_LP4] CH0 RK1
7195 05:58:59.383696 [ModeRegInit_LP4] CH1 RK0
7196 05:58:59.386904 [ModeRegInit_LP4] CH1 RK1
7197 05:58:59.387367 match AC timing 4
7198 05:58:59.393261 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7199 05:58:59.396456 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7200 05:58:59.400432 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7201 05:58:59.406760 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7202 05:58:59.410172 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7203 05:58:59.410727 [MiockJmeterHQA]
7204 05:58:59.411085
7205 05:58:59.413450 [DramcMiockJmeter] u1RxGatingPI = 0
7206 05:58:59.416480 0 : 4258, 4029
7207 05:58:59.417101 4 : 4252, 4027
7208 05:58:59.419944 8 : 4363, 4137
7209 05:58:59.420520 12 : 4363, 4137
7210 05:58:59.420963 16 : 4250, 4024
7211 05:58:59.423255 20 : 4363, 4138
7212 05:58:59.423738 24 : 4253, 4026
7213 05:58:59.426697 28 : 4253, 4027
7214 05:58:59.427160 32 : 4253, 4027
7215 05:58:59.429655 36 : 4255, 4029
7216 05:58:59.430123 40 : 4361, 4137
7217 05:58:59.433097 44 : 4250, 4026
7218 05:58:59.433564 48 : 4360, 4138
7219 05:58:59.433929 52 : 4249, 4027
7220 05:58:59.436341 56 : 4250, 4026
7221 05:58:59.436848 60 : 4249, 4027
7222 05:58:59.439449 64 : 4360, 4137
7223 05:58:59.439912 68 : 4250, 4026
7224 05:58:59.442690 72 : 4360, 4138
7225 05:58:59.443185 76 : 4250, 4026
7226 05:58:59.446607 80 : 4250, 4027
7227 05:58:59.447176 84 : 4249, 4027
7228 05:58:59.447545 88 : 4253, 4029
7229 05:58:59.449556 92 : 4360, 4137
7230 05:58:59.450019 96 : 4253, 4026
7231 05:58:59.453062 100 : 4360, 1756
7232 05:58:59.453878 104 : 4253, 0
7233 05:58:59.455965 108 : 4252, 0
7234 05:58:59.456509 112 : 4361, 0
7235 05:58:59.456925 116 : 4360, 0
7236 05:58:59.459764 120 : 4363, 0
7237 05:58:59.460256 124 : 4250, 0
7238 05:58:59.462701 128 : 4360, 0
7239 05:58:59.463189 132 : 4249, 0
7240 05:58:59.463569 136 : 4250, 0
7241 05:58:59.466291 140 : 4249, 0
7242 05:58:59.466752 144 : 4249, 0
7243 05:58:59.467115 148 : 4253, 0
7244 05:58:59.469642 152 : 4360, 0
7245 05:58:59.470379 156 : 4249, 0
7246 05:58:59.472564 160 : 4250, 0
7247 05:58:59.473077 164 : 4250, 0
7248 05:58:59.473442 168 : 4360, 0
7249 05:58:59.476303 172 : 4360, 0
7250 05:58:59.476813 176 : 4250, 0
7251 05:58:59.479016 180 : 4249, 0
7252 05:58:59.479477 184 : 4363, 0
7253 05:58:59.479856 188 : 4250, 0
7254 05:58:59.482702 192 : 4250, 0
7255 05:58:59.483268 196 : 4249, 0
7256 05:58:59.486059 200 : 4253, 0
7257 05:58:59.486518 204 : 4360, 0
7258 05:58:59.486966 208 : 4249, 0
7259 05:58:59.489279 212 : 4250, 0
7260 05:58:59.489781 216 : 4361, 0
7261 05:58:59.492687 220 : 4360, 778
7262 05:58:59.493306 224 : 4253, 4017
7263 05:58:59.495898 228 : 4250, 4026
7264 05:58:59.496356 232 : 4253, 4029
7265 05:58:59.496758 236 : 4249, 4027
7266 05:58:59.498978 240 : 4252, 4029
7267 05:58:59.499439 244 : 4253, 4029
7268 05:58:59.502420 248 : 4250, 4027
7269 05:58:59.502883 252 : 4361, 4137
7270 05:58:59.505620 256 : 4363, 4140
7271 05:58:59.506108 260 : 4250, 4026
7272 05:58:59.508985 264 : 4250, 4027
7273 05:58:59.509483 268 : 4361, 4137
7274 05:58:59.512446 272 : 4252, 4029
7275 05:58:59.512965 276 : 4250, 4026
7276 05:58:59.515687 280 : 4250, 4026
7277 05:58:59.516206 284 : 4250, 4027
7278 05:58:59.518713 288 : 4249, 4027
7279 05:58:59.519175 292 : 4250, 4026
7280 05:58:59.522185 296 : 4250, 4026
7281 05:58:59.522679 300 : 4250, 4027
7282 05:58:59.523045 304 : 4360, 4137
7283 05:58:59.525368 308 : 4360, 4137
7284 05:58:59.525905 312 : 4250, 4026
7285 05:58:59.529067 316 : 4363, 4140
7286 05:58:59.529528 320 : 4361, 4137
7287 05:58:59.532181 324 : 4249, 4027
7288 05:58:59.532660 328 : 4250, 4026
7289 05:58:59.535928 332 : 4250, 4026
7290 05:58:59.536478 336 : 4250, 3952
7291 05:58:59.538898 340 : 4249, 1834
7292 05:58:59.539454
7293 05:58:59.539815 MIOCK jitter meter ch=0
7294 05:58:59.540144
7295 05:58:59.542348 1T = (340-100) = 240 dly cells
7296 05:58:59.548554 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7297 05:58:59.549191 ==
7298 05:58:59.551728 Dram Type= 6, Freq= 0, CH_0, rank 0
7299 05:58:59.555287 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7300 05:58:59.555828 ==
7301 05:58:59.561735 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7302 05:58:59.565246 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7303 05:58:59.571968 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7304 05:58:59.575117 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7305 05:58:59.584834 [CA 0] Center 42 (12~73) winsize 62
7306 05:58:59.587828 [CA 1] Center 42 (12~73) winsize 62
7307 05:58:59.591241 [CA 2] Center 39 (9~69) winsize 61
7308 05:58:59.594687 [CA 3] Center 38 (9~68) winsize 60
7309 05:58:59.597649 [CA 4] Center 37 (7~67) winsize 61
7310 05:58:59.601249 [CA 5] Center 36 (6~66) winsize 61
7311 05:58:59.601809
7312 05:58:59.604999 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7313 05:58:59.605457
7314 05:58:59.607378 [CATrainingPosCal] consider 1 rank data
7315 05:58:59.610721 u2DelayCellTimex100 = 271/100 ps
7316 05:58:59.617716 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7317 05:58:59.620864 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7318 05:58:59.624056 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7319 05:58:59.627487 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7320 05:58:59.631307 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7321 05:58:59.634609 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7322 05:58:59.635069
7323 05:58:59.637543 CA PerBit enable=1, Macro0, CA PI delay=36
7324 05:58:59.638015
7325 05:58:59.640698 [CBTSetCACLKResult] CA Dly = 36
7326 05:58:59.643815 CS Dly: 10 (0~41)
7327 05:58:59.647419 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7328 05:58:59.650422 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7329 05:58:59.650881 ==
7330 05:58:59.653945 Dram Type= 6, Freq= 0, CH_0, rank 1
7331 05:58:59.660700 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7332 05:58:59.661457 ==
7333 05:58:59.664355 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7334 05:58:59.667486 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7335 05:58:59.674038 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7336 05:58:59.680487 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7337 05:58:59.687608 [CA 0] Center 42 (12~73) winsize 62
7338 05:58:59.690674 [CA 1] Center 42 (12~73) winsize 62
7339 05:58:59.693755 [CA 2] Center 38 (9~68) winsize 60
7340 05:58:59.697193 [CA 3] Center 37 (8~67) winsize 60
7341 05:58:59.700813 [CA 4] Center 36 (6~66) winsize 61
7342 05:58:59.703787 [CA 5] Center 36 (6~66) winsize 61
7343 05:58:59.704350
7344 05:58:59.706865 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7345 05:58:59.707344
7346 05:58:59.710306 [CATrainingPosCal] consider 2 rank data
7347 05:58:59.713846 u2DelayCellTimex100 = 271/100 ps
7348 05:58:59.717298 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7349 05:58:59.724091 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7350 05:58:59.726933 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7351 05:58:59.730161 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7352 05:58:59.733770 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7353 05:58:59.736961 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7354 05:58:59.737521
7355 05:58:59.740173 CA PerBit enable=1, Macro0, CA PI delay=36
7356 05:58:59.740629
7357 05:58:59.743484 [CBTSetCACLKResult] CA Dly = 36
7358 05:58:59.746625 CS Dly: 10 (0~42)
7359 05:58:59.750414 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7360 05:58:59.753136 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7361 05:58:59.753742
7362 05:58:59.756875 ----->DramcWriteLeveling(PI) begin...
7363 05:58:59.757459 ==
7364 05:58:59.759790 Dram Type= 6, Freq= 0, CH_0, rank 0
7365 05:58:59.766566 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7366 05:58:59.767151 ==
7367 05:58:59.769787 Write leveling (Byte 0): 29 => 29
7368 05:58:59.773043 Write leveling (Byte 1): 27 => 27
7369 05:58:59.773446 DramcWriteLeveling(PI) end<-----
7370 05:58:59.773809
7371 05:58:59.776330 ==
7372 05:58:59.779431 Dram Type= 6, Freq= 0, CH_0, rank 0
7373 05:58:59.782797 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7374 05:58:59.783027 ==
7375 05:58:59.785954 [Gating] SW mode calibration
7376 05:58:59.792539 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7377 05:58:59.795936 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7378 05:58:59.802499 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7379 05:58:59.806209 0 12 4 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7380 05:58:59.809550 0 12 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
7381 05:58:59.816345 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7382 05:58:59.819366 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7383 05:58:59.822481 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7384 05:58:59.829720 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7385 05:58:59.832746 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7386 05:58:59.836154 0 13 0 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
7387 05:58:59.842279 0 13 4 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7388 05:58:59.845718 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7389 05:58:59.848832 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7390 05:58:59.855876 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7391 05:58:59.859157 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7392 05:58:59.862283 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7393 05:58:59.868906 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7394 05:58:59.872350 0 14 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7395 05:58:59.875599 0 14 4 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7396 05:58:59.882553 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7397 05:58:59.885732 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7398 05:58:59.889319 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7399 05:58:59.895472 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7400 05:58:59.898881 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7401 05:58:59.902202 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7402 05:58:59.908761 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7403 05:58:59.912127 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7404 05:58:59.915248 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7405 05:58:59.922183 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 05:58:59.925083 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7407 05:58:59.928675 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7408 05:58:59.935478 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7409 05:58:59.938634 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 05:58:59.941765 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7411 05:58:59.948319 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7412 05:58:59.951437 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 05:58:59.954782 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7414 05:58:59.961741 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 05:58:59.964494 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 05:58:59.968112 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 05:58:59.975165 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7418 05:58:59.977961 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7419 05:58:59.981628 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7420 05:58:59.988039 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7421 05:58:59.988470 Total UI for P1: 0, mck2ui 16
7422 05:58:59.994540 best dqsien dly found for B0: ( 1, 1, 2)
7423 05:58:59.994963 Total UI for P1: 0, mck2ui 16
7424 05:58:59.997803 best dqsien dly found for B1: ( 1, 1, 4)
7425 05:59:00.004437 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7426 05:59:00.007868 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7427 05:59:00.008285
7428 05:59:00.011037 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7429 05:59:00.014729 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7430 05:59:00.017851 [Gating] SW calibration Done
7431 05:59:00.018270 ==
7432 05:59:00.020970 Dram Type= 6, Freq= 0, CH_0, rank 0
7433 05:59:00.024155 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7434 05:59:00.024576 ==
7435 05:59:00.024966 RX Vref Scan: 0
7436 05:59:00.027389
7437 05:59:00.027805 RX Vref 0 -> 0, step: 1
7438 05:59:00.028133
7439 05:59:00.030714 RX Delay 0 -> 252, step: 8
7440 05:59:00.034255 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7441 05:59:00.037591 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7442 05:59:00.043998 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7443 05:59:00.047454 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7444 05:59:00.050928 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7445 05:59:00.054229 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7446 05:59:00.057253 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7447 05:59:00.064021 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7448 05:59:00.067641 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7449 05:59:00.070460 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7450 05:59:00.074182 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7451 05:59:00.076986 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7452 05:59:00.083792 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7453 05:59:00.087259 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7454 05:59:00.090174 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7455 05:59:00.093623 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7456 05:59:00.094045 ==
7457 05:59:00.097278 Dram Type= 6, Freq= 0, CH_0, rank 0
7458 05:59:00.103581 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7459 05:59:00.104001 ==
7460 05:59:00.104329 DQS Delay:
7461 05:59:00.107130 DQS0 = 0, DQS1 = 0
7462 05:59:00.107547 DQM Delay:
7463 05:59:00.110212 DQM0 = 129, DQM1 = 124
7464 05:59:00.110630 DQ Delay:
7465 05:59:00.113686 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7466 05:59:00.116764 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7467 05:59:00.120084 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7468 05:59:00.123454 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7469 05:59:00.123873
7470 05:59:00.124197
7471 05:59:00.124500 ==
7472 05:59:00.127164 Dram Type= 6, Freq= 0, CH_0, rank 0
7473 05:59:00.133434 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7474 05:59:00.133911 ==
7475 05:59:00.134243
7476 05:59:00.134553
7477 05:59:00.134849 TX Vref Scan disable
7478 05:59:00.136511 == TX Byte 0 ==
7479 05:59:00.139807 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7480 05:59:00.146855 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7481 05:59:00.147358 == TX Byte 1 ==
7482 05:59:00.149922 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7483 05:59:00.156385 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7484 05:59:00.156894 ==
7485 05:59:00.159835 Dram Type= 6, Freq= 0, CH_0, rank 0
7486 05:59:00.163115 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7487 05:59:00.163582 ==
7488 05:59:00.175807
7489 05:59:00.178830 TX Vref early break, caculate TX vref
7490 05:59:00.182245 TX Vref=16, minBit 8, minWin=22, winSum=373
7491 05:59:00.185562 TX Vref=18, minBit 8, minWin=23, winSum=385
7492 05:59:00.188834 TX Vref=20, minBit 9, minWin=22, winSum=391
7493 05:59:00.192147 TX Vref=22, minBit 8, minWin=23, winSum=396
7494 05:59:00.195488 TX Vref=24, minBit 9, minWin=23, winSum=405
7495 05:59:00.202576 TX Vref=26, minBit 8, minWin=24, winSum=412
7496 05:59:00.205544 TX Vref=28, minBit 8, minWin=24, winSum=415
7497 05:59:00.208921 TX Vref=30, minBit 3, minWin=24, winSum=406
7498 05:59:00.211946 TX Vref=32, minBit 1, minWin=24, winSum=400
7499 05:59:00.215518 TX Vref=34, minBit 6, minWin=23, winSum=392
7500 05:59:00.222438 [TxChooseVref] Worse bit 8, Min win 24, Win sum 415, Final Vref 28
7501 05:59:00.223001
7502 05:59:00.225286 Final TX Range 0 Vref 28
7503 05:59:00.225753
7504 05:59:00.226114 ==
7505 05:59:00.228542 Dram Type= 6, Freq= 0, CH_0, rank 0
7506 05:59:00.231787 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7507 05:59:00.232252 ==
7508 05:59:00.232610
7509 05:59:00.233008
7510 05:59:00.235349 TX Vref Scan disable
7511 05:59:00.241880 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7512 05:59:00.242340 == TX Byte 0 ==
7513 05:59:00.245269 u2DelayCellOfst[0]=14 cells (4 PI)
7514 05:59:00.248425 u2DelayCellOfst[1]=18 cells (5 PI)
7515 05:59:00.251650 u2DelayCellOfst[2]=14 cells (4 PI)
7516 05:59:00.255710 u2DelayCellOfst[3]=10 cells (3 PI)
7517 05:59:00.258462 u2DelayCellOfst[4]=7 cells (2 PI)
7518 05:59:00.261827 u2DelayCellOfst[5]=0 cells (0 PI)
7519 05:59:00.264984 u2DelayCellOfst[6]=18 cells (5 PI)
7520 05:59:00.268807 u2DelayCellOfst[7]=21 cells (6 PI)
7521 05:59:00.271597 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7522 05:59:00.274849 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7523 05:59:00.278176 == TX Byte 1 ==
7524 05:59:00.278636 u2DelayCellOfst[8]=3 cells (1 PI)
7525 05:59:00.281537 u2DelayCellOfst[9]=0 cells (0 PI)
7526 05:59:00.284883 u2DelayCellOfst[10]=10 cells (3 PI)
7527 05:59:00.288285 u2DelayCellOfst[11]=7 cells (2 PI)
7528 05:59:00.291747 u2DelayCellOfst[12]=18 cells (5 PI)
7529 05:59:00.294885 u2DelayCellOfst[13]=18 cells (5 PI)
7530 05:59:00.298104 u2DelayCellOfst[14]=18 cells (5 PI)
7531 05:59:00.301457 u2DelayCellOfst[15]=18 cells (5 PI)
7532 05:59:00.304784 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7533 05:59:00.311188 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7534 05:59:00.311652 DramC Write-DBI on
7535 05:59:00.312015 ==
7536 05:59:00.315169 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 05:59:00.320887 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7538 05:59:00.321691 ==
7539 05:59:00.322184
7540 05:59:00.322637
7541 05:59:00.323080 TX Vref Scan disable
7542 05:59:00.325045 == TX Byte 0 ==
7543 05:59:00.328508 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7544 05:59:00.331720 == TX Byte 1 ==
7545 05:59:00.334710 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7546 05:59:00.338231 DramC Write-DBI off
7547 05:59:00.338707
7548 05:59:00.339187 [DATLAT]
7549 05:59:00.339637 Freq=1600, CH0 RK0
7550 05:59:00.340183
7551 05:59:00.341867 DATLAT Default: 0xf
7552 05:59:00.344973 0, 0xFFFF, sum = 0
7553 05:59:00.345456 1, 0xFFFF, sum = 0
7554 05:59:00.348063 2, 0xFFFF, sum = 0
7555 05:59:00.348546 3, 0xFFFF, sum = 0
7556 05:59:00.351654 4, 0xFFFF, sum = 0
7557 05:59:00.352137 5, 0xFFFF, sum = 0
7558 05:59:00.354721 6, 0xFFFF, sum = 0
7559 05:59:00.355304 7, 0xFFFF, sum = 0
7560 05:59:00.357768 8, 0xFFFF, sum = 0
7561 05:59:00.358298 9, 0xFFFF, sum = 0
7562 05:59:00.361340 10, 0xFFFF, sum = 0
7563 05:59:00.361826 11, 0xFFFF, sum = 0
7564 05:59:00.365024 12, 0xFFF, sum = 0
7565 05:59:00.365510 13, 0x0, sum = 1
7566 05:59:00.367847 14, 0x0, sum = 2
7567 05:59:00.368426 15, 0x0, sum = 3
7568 05:59:00.370994 16, 0x0, sum = 4
7569 05:59:00.371475 best_step = 14
7570 05:59:00.371953
7571 05:59:00.372406 ==
7572 05:59:00.374891 Dram Type= 6, Freq= 0, CH_0, rank 0
7573 05:59:00.380961 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7574 05:59:00.381423 ==
7575 05:59:00.381781 RX Vref Scan: 1
7576 05:59:00.382116
7577 05:59:00.384354 Set Vref Range= 24 -> 127
7578 05:59:00.384872
7579 05:59:00.387927 RX Vref 24 -> 127, step: 1
7580 05:59:00.388455
7581 05:59:00.388884 RX Delay 11 -> 252, step: 4
7582 05:59:00.389235
7583 05:59:00.390908 Set Vref, RX VrefLevel [Byte0]: 24
7584 05:59:00.394026 [Byte1]: 24
7585 05:59:00.398197
7586 05:59:00.398656 Set Vref, RX VrefLevel [Byte0]: 25
7587 05:59:00.401527 [Byte1]: 25
7588 05:59:00.405809
7589 05:59:00.406267 Set Vref, RX VrefLevel [Byte0]: 26
7590 05:59:00.409434 [Byte1]: 26
7591 05:59:00.413434
7592 05:59:00.413892 Set Vref, RX VrefLevel [Byte0]: 27
7593 05:59:00.417023 [Byte1]: 27
7594 05:59:00.421052
7595 05:59:00.421592 Set Vref, RX VrefLevel [Byte0]: 28
7596 05:59:00.424497 [Byte1]: 28
7597 05:59:00.429003
7598 05:59:00.429574 Set Vref, RX VrefLevel [Byte0]: 29
7599 05:59:00.431870 [Byte1]: 29
7600 05:59:00.436690
7601 05:59:00.437314 Set Vref, RX VrefLevel [Byte0]: 30
7602 05:59:00.439750 [Byte1]: 30
7603 05:59:00.444271
7604 05:59:00.444890 Set Vref, RX VrefLevel [Byte0]: 31
7605 05:59:00.447384 [Byte1]: 31
7606 05:59:00.451800
7607 05:59:00.452367 Set Vref, RX VrefLevel [Byte0]: 32
7608 05:59:00.455054 [Byte1]: 32
7609 05:59:00.459047
7610 05:59:00.459523 Set Vref, RX VrefLevel [Byte0]: 33
7611 05:59:00.462417 [Byte1]: 33
7612 05:59:00.466514
7613 05:59:00.469962 Set Vref, RX VrefLevel [Byte0]: 34
7614 05:59:00.473515 [Byte1]: 34
7615 05:59:00.473992
7616 05:59:00.476868 Set Vref, RX VrefLevel [Byte0]: 35
7617 05:59:00.479849 [Byte1]: 35
7618 05:59:00.480310
7619 05:59:00.483104 Set Vref, RX VrefLevel [Byte0]: 36
7620 05:59:00.486540 [Byte1]: 36
7621 05:59:00.489634
7622 05:59:00.490177 Set Vref, RX VrefLevel [Byte0]: 37
7623 05:59:00.493036 [Byte1]: 37
7624 05:59:00.497077
7625 05:59:00.497537 Set Vref, RX VrefLevel [Byte0]: 38
7626 05:59:00.500361 [Byte1]: 38
7627 05:59:00.504901
7628 05:59:00.505452 Set Vref, RX VrefLevel [Byte0]: 39
7629 05:59:00.508045 [Byte1]: 39
7630 05:59:00.512164
7631 05:59:00.512622 Set Vref, RX VrefLevel [Byte0]: 40
7632 05:59:00.515995 [Byte1]: 40
7633 05:59:00.520250
7634 05:59:00.521130 Set Vref, RX VrefLevel [Byte0]: 41
7635 05:59:00.523338 [Byte1]: 41
7636 05:59:00.527672
7637 05:59:00.528144 Set Vref, RX VrefLevel [Byte0]: 42
7638 05:59:00.530938 [Byte1]: 42
7639 05:59:00.535221
7640 05:59:00.535678 Set Vref, RX VrefLevel [Byte0]: 43
7641 05:59:00.538715 [Byte1]: 43
7642 05:59:00.543077
7643 05:59:00.543612 Set Vref, RX VrefLevel [Byte0]: 44
7644 05:59:00.546609 [Byte1]: 44
7645 05:59:00.550519
7646 05:59:00.551066 Set Vref, RX VrefLevel [Byte0]: 45
7647 05:59:00.553801 [Byte1]: 45
7648 05:59:00.557996
7649 05:59:00.558460 Set Vref, RX VrefLevel [Byte0]: 46
7650 05:59:00.561422 [Byte1]: 46
7651 05:59:00.565569
7652 05:59:00.566030 Set Vref, RX VrefLevel [Byte0]: 47
7653 05:59:00.569134 [Byte1]: 47
7654 05:59:00.573521
7655 05:59:00.574082 Set Vref, RX VrefLevel [Byte0]: 48
7656 05:59:00.576413 [Byte1]: 48
7657 05:59:00.581118
7658 05:59:00.581679 Set Vref, RX VrefLevel [Byte0]: 49
7659 05:59:00.584093 [Byte1]: 49
7660 05:59:00.588597
7661 05:59:00.589114 Set Vref, RX VrefLevel [Byte0]: 50
7662 05:59:00.591969 [Byte1]: 50
7663 05:59:00.596209
7664 05:59:00.596849 Set Vref, RX VrefLevel [Byte0]: 51
7665 05:59:00.599644 [Byte1]: 51
7666 05:59:00.603838
7667 05:59:00.604395 Set Vref, RX VrefLevel [Byte0]: 52
7668 05:59:00.607137 [Byte1]: 52
7669 05:59:00.611652
7670 05:59:00.612112 Set Vref, RX VrefLevel [Byte0]: 53
7671 05:59:00.615343 [Byte1]: 53
7672 05:59:00.618961
7673 05:59:00.619423 Set Vref, RX VrefLevel [Byte0]: 54
7674 05:59:00.622573 [Byte1]: 54
7675 05:59:00.626639
7676 05:59:00.627096 Set Vref, RX VrefLevel [Byte0]: 55
7677 05:59:00.630195 [Byte1]: 55
7678 05:59:00.634217
7679 05:59:00.634838 Set Vref, RX VrefLevel [Byte0]: 56
7680 05:59:00.637290 [Byte1]: 56
7681 05:59:00.642128
7682 05:59:00.642586 Set Vref, RX VrefLevel [Byte0]: 57
7683 05:59:00.645392 [Byte1]: 57
7684 05:59:00.649502
7685 05:59:00.649974 Set Vref, RX VrefLevel [Byte0]: 58
7686 05:59:00.652981 [Byte1]: 58
7687 05:59:00.657120
7688 05:59:00.657673 Set Vref, RX VrefLevel [Byte0]: 59
7689 05:59:00.660431 [Byte1]: 59
7690 05:59:00.664872
7691 05:59:00.665424 Set Vref, RX VrefLevel [Byte0]: 60
7692 05:59:00.668143 [Byte1]: 60
7693 05:59:00.672287
7694 05:59:00.672882 Set Vref, RX VrefLevel [Byte0]: 61
7695 05:59:00.675720 [Byte1]: 61
7696 05:59:00.679966
7697 05:59:00.680527 Set Vref, RX VrefLevel [Byte0]: 62
7698 05:59:00.683489 [Byte1]: 62
7699 05:59:00.687586
7700 05:59:00.688140 Set Vref, RX VrefLevel [Byte0]: 63
7701 05:59:00.690772 [Byte1]: 63
7702 05:59:00.695406
7703 05:59:00.695959 Set Vref, RX VrefLevel [Byte0]: 64
7704 05:59:00.698379 [Byte1]: 64
7705 05:59:00.702871
7706 05:59:00.703430 Set Vref, RX VrefLevel [Byte0]: 65
7707 05:59:00.706254 [Byte1]: 65
7708 05:59:00.710369
7709 05:59:00.710828 Set Vref, RX VrefLevel [Byte0]: 66
7710 05:59:00.713780 [Byte1]: 66
7711 05:59:00.717738
7712 05:59:00.718195 Set Vref, RX VrefLevel [Byte0]: 67
7713 05:59:00.721152 [Byte1]: 67
7714 05:59:00.725532
7715 05:59:00.725991 Set Vref, RX VrefLevel [Byte0]: 68
7716 05:59:00.728844 [Byte1]: 68
7717 05:59:00.733540
7718 05:59:00.734090 Set Vref, RX VrefLevel [Byte0]: 69
7719 05:59:00.736428 [Byte1]: 69
7720 05:59:00.740627
7721 05:59:00.741259 Set Vref, RX VrefLevel [Byte0]: 70
7722 05:59:00.744289 [Byte1]: 70
7723 05:59:00.748604
7724 05:59:00.749203 Set Vref, RX VrefLevel [Byte0]: 71
7725 05:59:00.751915 [Byte1]: 71
7726 05:59:00.756581
7727 05:59:00.757204 Set Vref, RX VrefLevel [Byte0]: 72
7728 05:59:00.759126 [Byte1]: 72
7729 05:59:00.763812
7730 05:59:00.766805 Final RX Vref Byte 0 = 53 to rank0
7731 05:59:00.767367 Final RX Vref Byte 1 = 58 to rank0
7732 05:59:00.770254 Final RX Vref Byte 0 = 53 to rank1
7733 05:59:00.773389 Final RX Vref Byte 1 = 58 to rank1==
7734 05:59:00.777055 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 05:59:00.783786 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7736 05:59:00.784330 ==
7737 05:59:00.784695 DQS Delay:
7738 05:59:00.785069 DQS0 = 0, DQS1 = 0
7739 05:59:00.786746 DQM Delay:
7740 05:59:00.787203 DQM0 = 126, DQM1 = 121
7741 05:59:00.790469 DQ Delay:
7742 05:59:00.793527 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7743 05:59:00.796872 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7744 05:59:00.800157 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112
7745 05:59:00.803557 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7746 05:59:00.804113
7747 05:59:00.804475
7748 05:59:00.804845
7749 05:59:00.806667 [DramC_TX_OE_Calibration] TA2
7750 05:59:00.810167 Original DQ_B0 (3 6) =30, OEN = 27
7751 05:59:00.813032 Original DQ_B1 (3 6) =30, OEN = 27
7752 05:59:00.816462 24, 0x0, End_B0=24 End_B1=24
7753 05:59:00.817160 25, 0x0, End_B0=25 End_B1=25
7754 05:59:00.819919 26, 0x0, End_B0=26 End_B1=26
7755 05:59:00.823252 27, 0x0, End_B0=27 End_B1=27
7756 05:59:00.826699 28, 0x0, End_B0=28 End_B1=28
7757 05:59:00.829872 29, 0x0, End_B0=29 End_B1=29
7758 05:59:00.830433 30, 0x0, End_B0=30 End_B1=30
7759 05:59:00.833227 31, 0x4141, End_B0=30 End_B1=30
7760 05:59:00.836147 Byte0 end_step=30 best_step=27
7761 05:59:00.839487 Byte1 end_step=30 best_step=27
7762 05:59:00.842930 Byte0 TX OE(2T, 0.5T) = (3, 3)
7763 05:59:00.845995 Byte1 TX OE(2T, 0.5T) = (3, 3)
7764 05:59:00.846456
7765 05:59:00.846816
7766 05:59:00.852919 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
7767 05:59:00.856506 CH0 RK0: MR19=303, MR18=1919
7768 05:59:00.863043 CH0_RK0: MR19=0x303, MR18=0x1919, DQSOSC=397, MR23=63, INC=23, DEC=15
7769 05:59:00.863616
7770 05:59:00.866094 ----->DramcWriteLeveling(PI) begin...
7771 05:59:00.866654 ==
7772 05:59:00.869576 Dram Type= 6, Freq= 0, CH_0, rank 1
7773 05:59:00.873012 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7774 05:59:00.873574 ==
7775 05:59:00.876194 Write leveling (Byte 0): 31 => 31
7776 05:59:00.879470 Write leveling (Byte 1): 28 => 28
7777 05:59:00.882807 DramcWriteLeveling(PI) end<-----
7778 05:59:00.883270
7779 05:59:00.883632 ==
7780 05:59:00.885819 Dram Type= 6, Freq= 0, CH_0, rank 1
7781 05:59:00.889445 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7782 05:59:00.889997 ==
7783 05:59:00.892638 [Gating] SW mode calibration
7784 05:59:00.899418 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7785 05:59:00.905672 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7786 05:59:00.908964 0 12 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
7787 05:59:00.915590 0 12 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7788 05:59:00.918955 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7789 05:59:00.922135 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7790 05:59:00.928798 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7791 05:59:00.932526 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7792 05:59:00.935623 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7793 05:59:00.941971 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7794 05:59:00.945241 0 13 0 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
7795 05:59:00.948932 0 13 4 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
7796 05:59:00.955221 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7797 05:59:00.958813 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7798 05:59:00.961687 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7799 05:59:00.968442 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7800 05:59:00.971588 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7801 05:59:00.975077 0 13 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7802 05:59:00.981540 0 14 0 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7803 05:59:00.985221 0 14 4 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7804 05:59:00.988271 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7805 05:59:00.994800 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7806 05:59:00.998180 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7807 05:59:01.001539 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7808 05:59:01.007781 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7809 05:59:01.011724 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7810 05:59:01.015185 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7811 05:59:01.021587 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7812 05:59:01.024875 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7813 05:59:01.028062 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7814 05:59:01.034452 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7815 05:59:01.037607 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 05:59:01.041278 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 05:59:01.047588 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 05:59:01.051079 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 05:59:01.054149 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7820 05:59:01.061040 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7821 05:59:01.064175 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 05:59:01.067344 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 05:59:01.073917 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 05:59:01.076995 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7825 05:59:01.080211 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7826 05:59:01.087558 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7827 05:59:01.090709 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7828 05:59:01.093612 Total UI for P1: 0, mck2ui 16
7829 05:59:01.096784 best dqsien dly found for B0: ( 1, 0, 28)
7830 05:59:01.100024 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7831 05:59:01.106656 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7832 05:59:01.107195 Total UI for P1: 0, mck2ui 16
7833 05:59:01.113760 best dqsien dly found for B1: ( 1, 1, 4)
7834 05:59:01.116393 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7835 05:59:01.120030 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7836 05:59:01.120614
7837 05:59:01.123472 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7838 05:59:01.126387 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7839 05:59:01.129880 [Gating] SW calibration Done
7840 05:59:01.130338 ==
7841 05:59:01.133031 Dram Type= 6, Freq= 0, CH_0, rank 1
7842 05:59:01.136381 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7843 05:59:01.136894 ==
7844 05:59:01.139935 RX Vref Scan: 0
7845 05:59:01.140491
7846 05:59:01.140900 RX Vref 0 -> 0, step: 1
7847 05:59:01.141247
7848 05:59:01.142940 RX Delay 0 -> 252, step: 8
7849 05:59:01.146385 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7850 05:59:01.152811 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7851 05:59:01.156271 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7852 05:59:01.159259 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7853 05:59:01.163086 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7854 05:59:01.166017 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7855 05:59:01.172602 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7856 05:59:01.175945 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7857 05:59:01.179133 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7858 05:59:01.182281 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7859 05:59:01.188823 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7860 05:59:01.192446 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7861 05:59:01.195759 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7862 05:59:01.198695 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7863 05:59:01.202591 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7864 05:59:01.209041 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7865 05:59:01.209503 ==
7866 05:59:01.212324 Dram Type= 6, Freq= 0, CH_0, rank 1
7867 05:59:01.215983 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7868 05:59:01.216662 ==
7869 05:59:01.217240 DQS Delay:
7870 05:59:01.218742 DQS0 = 0, DQS1 = 0
7871 05:59:01.219199 DQM Delay:
7872 05:59:01.222619 DQM0 = 130, DQM1 = 124
7873 05:59:01.223182 DQ Delay:
7874 05:59:01.225801 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7875 05:59:01.228925 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7876 05:59:01.232449 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7877 05:59:01.235543 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7878 05:59:01.236215
7879 05:59:01.238876
7880 05:59:01.239428 ==
7881 05:59:01.241812 Dram Type= 6, Freq= 0, CH_0, rank 1
7882 05:59:01.245306 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7883 05:59:01.245770 ==
7884 05:59:01.246131
7885 05:59:01.246463
7886 05:59:01.248549 TX Vref Scan disable
7887 05:59:01.249057 == TX Byte 0 ==
7888 05:59:01.255631 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7889 05:59:01.258651 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7890 05:59:01.259218 == TX Byte 1 ==
7891 05:59:01.265121 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7892 05:59:01.269023 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7893 05:59:01.269582 ==
7894 05:59:01.271855 Dram Type= 6, Freq= 0, CH_0, rank 1
7895 05:59:01.275299 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7896 05:59:01.275857 ==
7897 05:59:01.289644
7898 05:59:01.293178 TX Vref early break, caculate TX vref
7899 05:59:01.296287 TX Vref=16, minBit 9, minWin=22, winSum=376
7900 05:59:01.299734 TX Vref=18, minBit 8, minWin=22, winSum=386
7901 05:59:01.303169 TX Vref=20, minBit 1, minWin=24, winSum=395
7902 05:59:01.306238 TX Vref=22, minBit 1, minWin=24, winSum=402
7903 05:59:01.309719 TX Vref=24, minBit 0, minWin=25, winSum=409
7904 05:59:01.316634 TX Vref=26, minBit 0, minWin=25, winSum=415
7905 05:59:01.319895 TX Vref=28, minBit 6, minWin=25, winSum=418
7906 05:59:01.323072 TX Vref=30, minBit 6, minWin=25, winSum=419
7907 05:59:01.326407 TX Vref=32, minBit 8, minWin=24, winSum=407
7908 05:59:01.329272 TX Vref=34, minBit 0, minWin=24, winSum=400
7909 05:59:01.333296 TX Vref=36, minBit 1, minWin=23, winSum=394
7910 05:59:01.339988 [TxChooseVref] Worse bit 6, Min win 25, Win sum 419, Final Vref 30
7911 05:59:01.340541
7912 05:59:01.342702 Final TX Range 0 Vref 30
7913 05:59:01.343165
7914 05:59:01.343550 ==
7915 05:59:01.346118 Dram Type= 6, Freq= 0, CH_0, rank 1
7916 05:59:01.349664 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7917 05:59:01.350225 ==
7918 05:59:01.350587
7919 05:59:01.352697
7920 05:59:01.353273 TX Vref Scan disable
7921 05:59:01.359439 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7922 05:59:01.360007 == TX Byte 0 ==
7923 05:59:01.362842 u2DelayCellOfst[0]=10 cells (3 PI)
7924 05:59:01.366208 u2DelayCellOfst[1]=14 cells (4 PI)
7925 05:59:01.369051 u2DelayCellOfst[2]=10 cells (3 PI)
7926 05:59:01.372610 u2DelayCellOfst[3]=10 cells (3 PI)
7927 05:59:01.375725 u2DelayCellOfst[4]=7 cells (2 PI)
7928 05:59:01.379258 u2DelayCellOfst[5]=0 cells (0 PI)
7929 05:59:01.382460 u2DelayCellOfst[6]=18 cells (5 PI)
7930 05:59:01.385936 u2DelayCellOfst[7]=14 cells (4 PI)
7931 05:59:01.389172 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7932 05:59:01.392380 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7933 05:59:01.395918 == TX Byte 1 ==
7934 05:59:01.398797 u2DelayCellOfst[8]=3 cells (1 PI)
7935 05:59:01.402426 u2DelayCellOfst[9]=0 cells (0 PI)
7936 05:59:01.405660 u2DelayCellOfst[10]=10 cells (3 PI)
7937 05:59:01.409118 u2DelayCellOfst[11]=7 cells (2 PI)
7938 05:59:01.411950 u2DelayCellOfst[12]=14 cells (4 PI)
7939 05:59:01.412412 u2DelayCellOfst[13]=14 cells (4 PI)
7940 05:59:01.415587 u2DelayCellOfst[14]=21 cells (6 PI)
7941 05:59:01.419203 u2DelayCellOfst[15]=14 cells (4 PI)
7942 05:59:01.425462 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7943 05:59:01.428316 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7944 05:59:01.428829 DramC Write-DBI on
7945 05:59:01.432132 ==
7946 05:59:01.435065 Dram Type= 6, Freq= 0, CH_0, rank 1
7947 05:59:01.438662 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7948 05:59:01.439224 ==
7949 05:59:01.439589
7950 05:59:01.439923
7951 05:59:01.441493 TX Vref Scan disable
7952 05:59:01.442120 == TX Byte 0 ==
7953 05:59:01.448346 Update DQM dly =730 (2 ,6, 26) DQM OEN =(3 ,3)
7954 05:59:01.448971 == TX Byte 1 ==
7955 05:59:01.451874 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7956 05:59:01.454905 DramC Write-DBI off
7957 05:59:01.455365
7958 05:59:01.455720 [DATLAT]
7959 05:59:01.457963 Freq=1600, CH0 RK1
7960 05:59:01.458421
7961 05:59:01.458782 DATLAT Default: 0xe
7962 05:59:01.461308 0, 0xFFFF, sum = 0
7963 05:59:01.461777 1, 0xFFFF, sum = 0
7964 05:59:01.465117 2, 0xFFFF, sum = 0
7965 05:59:01.465583 3, 0xFFFF, sum = 0
7966 05:59:01.468432 4, 0xFFFF, sum = 0
7967 05:59:01.471597 5, 0xFFFF, sum = 0
7968 05:59:01.472189 6, 0xFFFF, sum = 0
7969 05:59:01.474902 7, 0xFFFF, sum = 0
7970 05:59:01.475368 8, 0xFFFF, sum = 0
7971 05:59:01.478128 9, 0xFFFF, sum = 0
7972 05:59:01.478593 10, 0xFFFF, sum = 0
7973 05:59:01.481293 11, 0xFFFF, sum = 0
7974 05:59:01.481757 12, 0x8FFF, sum = 0
7975 05:59:01.485012 13, 0x0, sum = 1
7976 05:59:01.485570 14, 0x0, sum = 2
7977 05:59:01.488448 15, 0x0, sum = 3
7978 05:59:01.489045 16, 0x0, sum = 4
7979 05:59:01.491449 best_step = 14
7980 05:59:01.491995
7981 05:59:01.492353 ==
7982 05:59:01.494844 Dram Type= 6, Freq= 0, CH_0, rank 1
7983 05:59:01.497872 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7984 05:59:01.498337 ==
7985 05:59:01.498696 RX Vref Scan: 0
7986 05:59:01.501572
7987 05:59:01.502121 RX Vref 0 -> 0, step: 1
7988 05:59:01.502486
7989 05:59:01.504860 RX Delay 11 -> 252, step: 4
7990 05:59:01.507824 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7991 05:59:01.514449 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7992 05:59:01.517900 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7993 05:59:01.521450 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7994 05:59:01.524740 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7995 05:59:01.527878 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7996 05:59:01.534215 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7997 05:59:01.537871 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7998 05:59:01.541017 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
7999 05:59:01.544114 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
8000 05:59:01.547748 iDelay=195, Bit 10, Center 120 (67 ~ 174) 108
8001 05:59:01.554472 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8002 05:59:01.557536 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8003 05:59:01.560945 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8004 05:59:01.564031 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8005 05:59:01.567861 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8006 05:59:01.571144 ==
8007 05:59:01.574228 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 05:59:01.577487 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8009 05:59:01.578056 ==
8010 05:59:01.578560 DQS Delay:
8011 05:59:01.580761 DQS0 = 0, DQS1 = 0
8012 05:59:01.581216 DQM Delay:
8013 05:59:01.584153 DQM0 = 128, DQM1 = 120
8014 05:59:01.584604 DQ Delay:
8015 05:59:01.587609 DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =124
8016 05:59:01.591127 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
8017 05:59:01.594156 DQ8 =110, DQ9 =106, DQ10 =120, DQ11 =112
8018 05:59:01.597599 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =132
8019 05:59:01.598056
8020 05:59:01.598424
8021 05:59:01.598793
8022 05:59:01.600683 [DramC_TX_OE_Calibration] TA2
8023 05:59:01.604196 Original DQ_B0 (3 6) =30, OEN = 27
8024 05:59:01.607455 Original DQ_B1 (3 6) =30, OEN = 27
8025 05:59:01.610809 24, 0x0, End_B0=24 End_B1=24
8026 05:59:01.613572 25, 0x0, End_B0=25 End_B1=25
8027 05:59:01.614035 26, 0x0, End_B0=26 End_B1=26
8028 05:59:01.617324 27, 0x0, End_B0=27 End_B1=27
8029 05:59:01.620807 28, 0x0, End_B0=28 End_B1=28
8030 05:59:01.623518 29, 0x0, End_B0=29 End_B1=29
8031 05:59:01.627045 30, 0x0, End_B0=30 End_B1=30
8032 05:59:01.627584 31, 0x4545, End_B0=30 End_B1=30
8033 05:59:01.630703 Byte0 end_step=30 best_step=27
8034 05:59:01.633388 Byte1 end_step=30 best_step=27
8035 05:59:01.637107 Byte0 TX OE(2T, 0.5T) = (3, 3)
8036 05:59:01.640321 Byte1 TX OE(2T, 0.5T) = (3, 3)
8037 05:59:01.640890
8038 05:59:01.641607
8039 05:59:01.646747 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8040 05:59:01.649985 CH0 RK1: MR19=303, MR18=2121
8041 05:59:01.656511 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
8042 05:59:01.659911 [RxdqsGatingPostProcess] freq 1600
8043 05:59:01.666492 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8044 05:59:01.669833 Pre-setting of DQS Precalculation
8045 05:59:01.673036 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8046 05:59:01.673457 ==
8047 05:59:01.676794 Dram Type= 6, Freq= 0, CH_1, rank 0
8048 05:59:01.680168 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8049 05:59:01.680782 ==
8050 05:59:01.686697 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8051 05:59:01.689871 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8052 05:59:01.697044 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8053 05:59:01.699931 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8054 05:59:01.709171 [CA 0] Center 41 (11~71) winsize 61
8055 05:59:01.712229 [CA 1] Center 40 (10~71) winsize 62
8056 05:59:01.715494 [CA 2] Center 36 (7~66) winsize 60
8057 05:59:01.719641 [CA 3] Center 35 (6~65) winsize 60
8058 05:59:01.722701 [CA 4] Center 33 (4~63) winsize 60
8059 05:59:01.725828 [CA 5] Center 33 (4~63) winsize 60
8060 05:59:01.726381
8061 05:59:01.728830 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8062 05:59:01.729289
8063 05:59:01.733259 [CATrainingPosCal] consider 1 rank data
8064 05:59:01.736037 u2DelayCellTimex100 = 271/100 ps
8065 05:59:01.742303 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8066 05:59:01.745802 CA1 delay=40 (10~71),Diff = 7 PI (25 cell)
8067 05:59:01.748669 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8068 05:59:01.752302 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8069 05:59:01.755487 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8070 05:59:01.758513 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8071 05:59:01.759027
8072 05:59:01.762171 CA PerBit enable=1, Macro0, CA PI delay=33
8073 05:59:01.762729
8074 05:59:01.765136 [CBTSetCACLKResult] CA Dly = 33
8075 05:59:01.768586 CS Dly: 9 (0~40)
8076 05:59:01.771845 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8077 05:59:01.775172 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8078 05:59:01.775628 ==
8079 05:59:01.778404 Dram Type= 6, Freq= 0, CH_1, rank 1
8080 05:59:01.785487 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8081 05:59:01.786042 ==
8082 05:59:01.788226 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8083 05:59:01.794923 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8084 05:59:01.798110 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8085 05:59:01.804785 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8086 05:59:01.811762 [CA 0] Center 40 (10~70) winsize 61
8087 05:59:01.814756 [CA 1] Center 39 (9~70) winsize 62
8088 05:59:01.818245 [CA 2] Center 35 (6~65) winsize 60
8089 05:59:01.821517 [CA 3] Center 35 (6~65) winsize 60
8090 05:59:01.825071 [CA 4] Center 33 (4~62) winsize 59
8091 05:59:01.827979 [CA 5] Center 33 (4~63) winsize 60
8092 05:59:01.828436
8093 05:59:01.831330 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8094 05:59:01.831782
8095 05:59:01.834788 [CATrainingPosCal] consider 2 rank data
8096 05:59:01.838070 u2DelayCellTimex100 = 271/100 ps
8097 05:59:01.841284 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8098 05:59:01.847622 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8099 05:59:01.851579 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8100 05:59:01.854421 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8101 05:59:01.857957 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8102 05:59:01.861092 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8103 05:59:01.861606
8104 05:59:01.864348 CA PerBit enable=1, Macro0, CA PI delay=33
8105 05:59:01.864857
8106 05:59:01.867612 [CBTSetCACLKResult] CA Dly = 33
8107 05:59:01.871029 CS Dly: 9 (0~41)
8108 05:59:01.874317 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8109 05:59:01.877811 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8110 05:59:01.878268
8111 05:59:01.881019 ----->DramcWriteLeveling(PI) begin...
8112 05:59:01.881477 ==
8113 05:59:01.884534 Dram Type= 6, Freq= 0, CH_1, rank 0
8114 05:59:01.891083 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8115 05:59:01.891701 ==
8116 05:59:01.894246 Write leveling (Byte 0): 21 => 21
8117 05:59:01.897472 Write leveling (Byte 1): 21 => 21
8118 05:59:01.897969 DramcWriteLeveling(PI) end<-----
8119 05:59:01.898337
8120 05:59:01.900849 ==
8121 05:59:01.904249 Dram Type= 6, Freq= 0, CH_1, rank 0
8122 05:59:01.907159 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8123 05:59:01.907615 ==
8124 05:59:01.910683 [Gating] SW mode calibration
8125 05:59:01.916802 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8126 05:59:01.920169 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8127 05:59:01.927035 0 12 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8128 05:59:01.930150 0 12 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8129 05:59:01.933562 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8130 05:59:01.940073 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8131 05:59:01.943504 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8132 05:59:01.947174 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8133 05:59:01.953679 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8134 05:59:01.956964 0 12 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
8135 05:59:01.960193 0 13 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
8136 05:59:01.966968 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8137 05:59:01.970186 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8138 05:59:01.973805 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8139 05:59:01.980140 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8140 05:59:01.983200 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8141 05:59:01.986888 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8142 05:59:01.992938 0 13 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8143 05:59:01.996588 0 14 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8144 05:59:01.999936 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8145 05:59:02.006344 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8146 05:59:02.009344 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8147 05:59:02.013288 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8148 05:59:02.019982 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8149 05:59:02.023034 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8150 05:59:02.026049 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8151 05:59:02.032824 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8152 05:59:02.036205 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8153 05:59:02.039313 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 05:59:02.045934 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 05:59:02.049678 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 05:59:02.052855 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 05:59:02.059277 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 05:59:02.062914 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8159 05:59:02.066196 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8160 05:59:02.072543 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 05:59:02.075910 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 05:59:02.079179 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 05:59:02.085873 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8164 05:59:02.089023 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8165 05:59:02.092871 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8166 05:59:02.098882 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8167 05:59:02.102255 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8168 05:59:02.105589 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8169 05:59:02.108639 Total UI for P1: 0, mck2ui 16
8170 05:59:02.112095 best dqsien dly found for B0: ( 1, 0, 28)
8171 05:59:02.118956 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8172 05:59:02.119514 Total UI for P1: 0, mck2ui 16
8173 05:59:02.122218 best dqsien dly found for B1: ( 1, 1, 4)
8174 05:59:02.128482 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8175 05:59:02.131738 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
8176 05:59:02.132238
8177 05:59:02.135135 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8178 05:59:02.138617 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
8179 05:59:02.142010 [Gating] SW calibration Done
8180 05:59:02.142472 ==
8181 05:59:02.145068 Dram Type= 6, Freq= 0, CH_1, rank 0
8182 05:59:02.148358 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8183 05:59:02.148968 ==
8184 05:59:02.151406 RX Vref Scan: 0
8185 05:59:02.151863
8186 05:59:02.152225 RX Vref 0 -> 0, step: 1
8187 05:59:02.152563
8188 05:59:02.155011 RX Delay 0 -> 252, step: 8
8189 05:59:02.158303 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8190 05:59:02.161909 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8191 05:59:02.168182 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8192 05:59:02.171578 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8193 05:59:02.174675 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8194 05:59:02.178324 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8195 05:59:02.181742 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8196 05:59:02.188473 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8197 05:59:02.191447 iDelay=200, Bit 8, Center 107 (56 ~ 159) 104
8198 05:59:02.194845 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8199 05:59:02.197964 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8200 05:59:02.205082 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8201 05:59:02.208093 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8202 05:59:02.211256 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8203 05:59:02.214352 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8204 05:59:02.218175 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8205 05:59:02.221318 ==
8206 05:59:02.224798 Dram Type= 6, Freq= 0, CH_1, rank 0
8207 05:59:02.227988 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8208 05:59:02.228452 ==
8209 05:59:02.228943 DQS Delay:
8210 05:59:02.230908 DQS0 = 0, DQS1 = 0
8211 05:59:02.231367 DQM Delay:
8212 05:59:02.234243 DQM0 = 129, DQM1 = 125
8213 05:59:02.234840 DQ Delay:
8214 05:59:02.237748 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8215 05:59:02.240823 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8216 05:59:02.244434 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8217 05:59:02.247700 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8218 05:59:02.248262
8219 05:59:02.248623
8220 05:59:02.249031 ==
8221 05:59:02.250905 Dram Type= 6, Freq= 0, CH_1, rank 0
8222 05:59:02.257803 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8223 05:59:02.258368 ==
8224 05:59:02.258734
8225 05:59:02.259065
8226 05:59:02.259382 TX Vref Scan disable
8227 05:59:02.260957 == TX Byte 0 ==
8228 05:59:02.264614 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8229 05:59:02.271278 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8230 05:59:02.271830 == TX Byte 1 ==
8231 05:59:02.274474 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8232 05:59:02.281160 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8233 05:59:02.281716 ==
8234 05:59:02.284408 Dram Type= 6, Freq= 0, CH_1, rank 0
8235 05:59:02.287856 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8236 05:59:02.288417 ==
8237 05:59:02.299995
8238 05:59:02.302682 TX Vref early break, caculate TX vref
8239 05:59:02.305988 TX Vref=16, minBit 3, minWin=21, winSum=369
8240 05:59:02.309760 TX Vref=18, minBit 1, minWin=22, winSum=378
8241 05:59:02.312761 TX Vref=20, minBit 3, minWin=22, winSum=384
8242 05:59:02.316183 TX Vref=22, minBit 3, minWin=23, winSum=394
8243 05:59:02.319244 TX Vref=24, minBit 3, minWin=23, winSum=402
8244 05:59:02.325886 TX Vref=26, minBit 0, minWin=24, winSum=410
8245 05:59:02.329746 TX Vref=28, minBit 0, minWin=25, winSum=413
8246 05:59:02.332365 TX Vref=30, minBit 3, minWin=24, winSum=403
8247 05:59:02.336115 TX Vref=32, minBit 1, minWin=23, winSum=394
8248 05:59:02.339451 TX Vref=34, minBit 1, minWin=23, winSum=387
8249 05:59:02.346200 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
8250 05:59:02.346756
8251 05:59:02.349491 Final TX Range 0 Vref 28
8252 05:59:02.349952
8253 05:59:02.350312 ==
8254 05:59:02.352425 Dram Type= 6, Freq= 0, CH_1, rank 0
8255 05:59:02.356058 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8256 05:59:02.356616 ==
8257 05:59:02.357046
8258 05:59:02.357385
8259 05:59:02.359033 TX Vref Scan disable
8260 05:59:02.365712 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8261 05:59:02.366270 == TX Byte 0 ==
8262 05:59:02.368833 u2DelayCellOfst[0]=14 cells (4 PI)
8263 05:59:02.371877 u2DelayCellOfst[1]=10 cells (3 PI)
8264 05:59:02.375555 u2DelayCellOfst[2]=0 cells (0 PI)
8265 05:59:02.378820 u2DelayCellOfst[3]=7 cells (2 PI)
8266 05:59:02.382072 u2DelayCellOfst[4]=7 cells (2 PI)
8267 05:59:02.385345 u2DelayCellOfst[5]=14 cells (4 PI)
8268 05:59:02.388658 u2DelayCellOfst[6]=14 cells (4 PI)
8269 05:59:02.391752 u2DelayCellOfst[7]=7 cells (2 PI)
8270 05:59:02.395581 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8271 05:59:02.398477 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8272 05:59:02.402021 == TX Byte 1 ==
8273 05:59:02.402573 u2DelayCellOfst[8]=0 cells (0 PI)
8274 05:59:02.405764 u2DelayCellOfst[9]=3 cells (1 PI)
8275 05:59:02.408790 u2DelayCellOfst[10]=7 cells (2 PI)
8276 05:59:02.411955 u2DelayCellOfst[11]=0 cells (0 PI)
8277 05:59:02.415015 u2DelayCellOfst[12]=14 cells (4 PI)
8278 05:59:02.418873 u2DelayCellOfst[13]=18 cells (5 PI)
8279 05:59:02.421948 u2DelayCellOfst[14]=18 cells (5 PI)
8280 05:59:02.425100 u2DelayCellOfst[15]=18 cells (5 PI)
8281 05:59:02.428682 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8282 05:59:02.435223 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8283 05:59:02.435774 DramC Write-DBI on
8284 05:59:02.436138 ==
8285 05:59:02.438172 Dram Type= 6, Freq= 0, CH_1, rank 0
8286 05:59:02.445040 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8287 05:59:02.445505 ==
8288 05:59:02.445867
8289 05:59:02.446201
8290 05:59:02.446521 TX Vref Scan disable
8291 05:59:02.448524 == TX Byte 0 ==
8292 05:59:02.451995 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8293 05:59:02.455086 == TX Byte 1 ==
8294 05:59:02.458777 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8295 05:59:02.461587 DramC Write-DBI off
8296 05:59:02.462074
8297 05:59:02.462444 [DATLAT]
8298 05:59:02.462780 Freq=1600, CH1 RK0
8299 05:59:02.463107
8300 05:59:02.464805 DATLAT Default: 0xf
8301 05:59:02.465265 0, 0xFFFF, sum = 0
8302 05:59:02.468063 1, 0xFFFF, sum = 0
8303 05:59:02.471361 2, 0xFFFF, sum = 0
8304 05:59:02.471828 3, 0xFFFF, sum = 0
8305 05:59:02.474982 4, 0xFFFF, sum = 0
8306 05:59:02.475449 5, 0xFFFF, sum = 0
8307 05:59:02.477947 6, 0xFFFF, sum = 0
8308 05:59:02.478416 7, 0xFFFF, sum = 0
8309 05:59:02.481905 8, 0xFFFF, sum = 0
8310 05:59:02.482504 9, 0xFFFF, sum = 0
8311 05:59:02.484757 10, 0xFFFF, sum = 0
8312 05:59:02.485230 11, 0xFFFF, sum = 0
8313 05:59:02.487836 12, 0xF7F, sum = 0
8314 05:59:02.488306 13, 0x0, sum = 1
8315 05:59:02.491822 14, 0x0, sum = 2
8316 05:59:02.492389 15, 0x0, sum = 3
8317 05:59:02.494839 16, 0x0, sum = 4
8318 05:59:02.495406 best_step = 14
8319 05:59:02.495769
8320 05:59:02.496106 ==
8321 05:59:02.497982 Dram Type= 6, Freq= 0, CH_1, rank 0
8322 05:59:02.501311 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8323 05:59:02.504868 ==
8324 05:59:02.505329 RX Vref Scan: 1
8325 05:59:02.505689
8326 05:59:02.508155 Set Vref Range= 24 -> 127
8327 05:59:02.508770
8328 05:59:02.511242 RX Vref 24 -> 127, step: 1
8329 05:59:02.511703
8330 05:59:02.512060 RX Delay 11 -> 252, step: 4
8331 05:59:02.512393
8332 05:59:02.514407 Set Vref, RX VrefLevel [Byte0]: 24
8333 05:59:02.517708 [Byte1]: 24
8334 05:59:02.521817
8335 05:59:02.522408 Set Vref, RX VrefLevel [Byte0]: 25
8336 05:59:02.524840 [Byte1]: 25
8337 05:59:02.529636
8338 05:59:02.530196 Set Vref, RX VrefLevel [Byte0]: 26
8339 05:59:02.532480 [Byte1]: 26
8340 05:59:02.537097
8341 05:59:02.537643 Set Vref, RX VrefLevel [Byte0]: 27
8342 05:59:02.540935 [Byte1]: 27
8343 05:59:02.545256
8344 05:59:02.545810 Set Vref, RX VrefLevel [Byte0]: 28
8345 05:59:02.548159 [Byte1]: 28
8346 05:59:02.552771
8347 05:59:02.553336 Set Vref, RX VrefLevel [Byte0]: 29
8348 05:59:02.555606 [Byte1]: 29
8349 05:59:02.560016
8350 05:59:02.560572 Set Vref, RX VrefLevel [Byte0]: 30
8351 05:59:02.562991 [Byte1]: 30
8352 05:59:02.567474
8353 05:59:02.568031 Set Vref, RX VrefLevel [Byte0]: 31
8354 05:59:02.570928 [Byte1]: 31
8355 05:59:02.575003
8356 05:59:02.575564 Set Vref, RX VrefLevel [Byte0]: 32
8357 05:59:02.578480 [Byte1]: 32
8358 05:59:02.583023
8359 05:59:02.583583 Set Vref, RX VrefLevel [Byte0]: 33
8360 05:59:02.585957 [Byte1]: 33
8361 05:59:02.590386
8362 05:59:02.590887 Set Vref, RX VrefLevel [Byte0]: 34
8363 05:59:02.593488 [Byte1]: 34
8364 05:59:02.597766
8365 05:59:02.598221 Set Vref, RX VrefLevel [Byte0]: 35
8366 05:59:02.601214 [Byte1]: 35
8367 05:59:02.605540
8368 05:59:02.605995 Set Vref, RX VrefLevel [Byte0]: 36
8369 05:59:02.608789 [Byte1]: 36
8370 05:59:02.612933
8371 05:59:02.613389 Set Vref, RX VrefLevel [Byte0]: 37
8372 05:59:02.616452 [Byte1]: 37
8373 05:59:02.621241
8374 05:59:02.621791 Set Vref, RX VrefLevel [Byte0]: 38
8375 05:59:02.624611 [Byte1]: 38
8376 05:59:02.628439
8377 05:59:02.629185 Set Vref, RX VrefLevel [Byte0]: 39
8378 05:59:02.631710 [Byte1]: 39
8379 05:59:02.635743
8380 05:59:02.636201 Set Vref, RX VrefLevel [Byte0]: 40
8381 05:59:02.639353 [Byte1]: 40
8382 05:59:02.643566
8383 05:59:02.644130 Set Vref, RX VrefLevel [Byte0]: 41
8384 05:59:02.646797 [Byte1]: 41
8385 05:59:02.651049
8386 05:59:02.651510 Set Vref, RX VrefLevel [Byte0]: 42
8387 05:59:02.654806 [Byte1]: 42
8388 05:59:02.658947
8389 05:59:02.659498 Set Vref, RX VrefLevel [Byte0]: 43
8390 05:59:02.662321 [Byte1]: 43
8391 05:59:02.666516
8392 05:59:02.667065 Set Vref, RX VrefLevel [Byte0]: 44
8393 05:59:02.670394 [Byte1]: 44
8394 05:59:02.673997
8395 05:59:02.674488 Set Vref, RX VrefLevel [Byte0]: 45
8396 05:59:02.677295 [Byte1]: 45
8397 05:59:02.681616
8398 05:59:02.682176 Set Vref, RX VrefLevel [Byte0]: 46
8399 05:59:02.684929 [Byte1]: 46
8400 05:59:02.689587
8401 05:59:02.690154 Set Vref, RX VrefLevel [Byte0]: 47
8402 05:59:02.692546 [Byte1]: 47
8403 05:59:02.697279
8404 05:59:02.697950 Set Vref, RX VrefLevel [Byte0]: 48
8405 05:59:02.699937 [Byte1]: 48
8406 05:59:02.704241
8407 05:59:02.704697 Set Vref, RX VrefLevel [Byte0]: 49
8408 05:59:02.707953 [Byte1]: 49
8409 05:59:02.711962
8410 05:59:02.712416 Set Vref, RX VrefLevel [Byte0]: 50
8411 05:59:02.715900 [Byte1]: 50
8412 05:59:02.719704
8413 05:59:02.720162 Set Vref, RX VrefLevel [Byte0]: 51
8414 05:59:02.723064 [Byte1]: 51
8415 05:59:02.727843
8416 05:59:02.728303 Set Vref, RX VrefLevel [Byte0]: 52
8417 05:59:02.730754 [Byte1]: 52
8418 05:59:02.734847
8419 05:59:02.735396 Set Vref, RX VrefLevel [Byte0]: 53
8420 05:59:02.738757 [Byte1]: 53
8421 05:59:02.742893
8422 05:59:02.743440 Set Vref, RX VrefLevel [Byte0]: 54
8423 05:59:02.745862 [Byte1]: 54
8424 05:59:02.750286
8425 05:59:02.750827 Set Vref, RX VrefLevel [Byte0]: 55
8426 05:59:02.753367 [Byte1]: 55
8427 05:59:02.757442
8428 05:59:02.758045 Set Vref, RX VrefLevel [Byte0]: 56
8429 05:59:02.760877 [Byte1]: 56
8430 05:59:02.765353
8431 05:59:02.765804 Set Vref, RX VrefLevel [Byte0]: 57
8432 05:59:02.768882 [Byte1]: 57
8433 05:59:02.773215
8434 05:59:02.773771 Set Vref, RX VrefLevel [Byte0]: 58
8435 05:59:02.776353 [Byte1]: 58
8436 05:59:02.780680
8437 05:59:02.781287 Set Vref, RX VrefLevel [Byte0]: 59
8438 05:59:02.783906 [Byte1]: 59
8439 05:59:02.788619
8440 05:59:02.789229 Set Vref, RX VrefLevel [Byte0]: 60
8441 05:59:02.791651 [Byte1]: 60
8442 05:59:02.795853
8443 05:59:02.796430 Set Vref, RX VrefLevel [Byte0]: 61
8444 05:59:02.799200 [Byte1]: 61
8445 05:59:02.803851
8446 05:59:02.804407 Set Vref, RX VrefLevel [Byte0]: 62
8447 05:59:02.806936 [Byte1]: 62
8448 05:59:02.810996
8449 05:59:02.811558 Set Vref, RX VrefLevel [Byte0]: 63
8450 05:59:02.814292 [Byte1]: 63
8451 05:59:02.818670
8452 05:59:02.819224 Set Vref, RX VrefLevel [Byte0]: 64
8453 05:59:02.822074 [Byte1]: 64
8454 05:59:02.826338
8455 05:59:02.826900 Set Vref, RX VrefLevel [Byte0]: 65
8456 05:59:02.829773 [Byte1]: 65
8457 05:59:02.833784
8458 05:59:02.834360 Set Vref, RX VrefLevel [Byte0]: 66
8459 05:59:02.836997 [Byte1]: 66
8460 05:59:02.841486
8461 05:59:02.841958 Set Vref, RX VrefLevel [Byte0]: 67
8462 05:59:02.844699 [Byte1]: 67
8463 05:59:02.849342
8464 05:59:02.849892 Set Vref, RX VrefLevel [Byte0]: 68
8465 05:59:02.852448 [Byte1]: 68
8466 05:59:02.856637
8467 05:59:02.857142 Set Vref, RX VrefLevel [Byte0]: 69
8468 05:59:02.860210 [Byte1]: 69
8469 05:59:02.864439
8470 05:59:02.865190 Set Vref, RX VrefLevel [Byte0]: 70
8471 05:59:02.867768 [Byte1]: 70
8472 05:59:02.872073
8473 05:59:02.872626 Set Vref, RX VrefLevel [Byte0]: 71
8474 05:59:02.875539 [Byte1]: 71
8475 05:59:02.880043
8476 05:59:02.880593 Set Vref, RX VrefLevel [Byte0]: 72
8477 05:59:02.882974 [Byte1]: 72
8478 05:59:02.887736
8479 05:59:02.888287 Set Vref, RX VrefLevel [Byte0]: 73
8480 05:59:02.890543 [Byte1]: 73
8481 05:59:02.894754
8482 05:59:02.895305 Set Vref, RX VrefLevel [Byte0]: 74
8483 05:59:02.898592 [Byte1]: 74
8484 05:59:02.902640
8485 05:59:02.903193 Set Vref, RX VrefLevel [Byte0]: 75
8486 05:59:02.905472 [Byte1]: 75
8487 05:59:02.909976
8488 05:59:02.910434 Set Vref, RX VrefLevel [Byte0]: 76
8489 05:59:02.913563 [Byte1]: 76
8490 05:59:02.918097
8491 05:59:02.918654 Final RX Vref Byte 0 = 61 to rank0
8492 05:59:02.921098 Final RX Vref Byte 1 = 54 to rank0
8493 05:59:02.924619 Final RX Vref Byte 0 = 61 to rank1
8494 05:59:02.927685 Final RX Vref Byte 1 = 54 to rank1==
8495 05:59:02.930475 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 05:59:02.937263 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8497 05:59:02.937789 ==
8498 05:59:02.938153 DQS Delay:
8499 05:59:02.940840 DQS0 = 0, DQS1 = 0
8500 05:59:02.941298 DQM Delay:
8501 05:59:02.941653 DQM0 = 128, DQM1 = 124
8502 05:59:02.944056 DQ Delay:
8503 05:59:02.947474 DQ0 =134, DQ1 =122, DQ2 =116, DQ3 =126
8504 05:59:02.950671 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =126
8505 05:59:02.953959 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8506 05:59:02.957228 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8507 05:59:02.957781
8508 05:59:02.958138
8509 05:59:02.958471
8510 05:59:02.960572 [DramC_TX_OE_Calibration] TA2
8511 05:59:02.963659 Original DQ_B0 (3 6) =30, OEN = 27
8512 05:59:02.967430 Original DQ_B1 (3 6) =30, OEN = 27
8513 05:59:02.970482 24, 0x0, End_B0=24 End_B1=24
8514 05:59:02.973778 25, 0x0, End_B0=25 End_B1=25
8515 05:59:02.974247 26, 0x0, End_B0=26 End_B1=26
8516 05:59:02.977082 27, 0x0, End_B0=27 End_B1=27
8517 05:59:02.980050 28, 0x0, End_B0=28 End_B1=28
8518 05:59:02.983911 29, 0x0, End_B0=29 End_B1=29
8519 05:59:02.984479 30, 0x0, End_B0=30 End_B1=30
8520 05:59:02.986773 31, 0x4141, End_B0=30 End_B1=30
8521 05:59:02.990164 Byte0 end_step=30 best_step=27
8522 05:59:02.993584 Byte1 end_step=30 best_step=27
8523 05:59:02.996938 Byte0 TX OE(2T, 0.5T) = (3, 3)
8524 05:59:02.999988 Byte1 TX OE(2T, 0.5T) = (3, 3)
8525 05:59:03.000448
8526 05:59:03.000859
8527 05:59:03.006798 [DQSOSCAuto] RK0, (LSB)MR18= 0x2727, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8528 05:59:03.010328 CH1 RK0: MR19=303, MR18=2727
8529 05:59:03.016861 CH1_RK0: MR19=0x303, MR18=0x2727, DQSOSC=390, MR23=63, INC=24, DEC=16
8530 05:59:03.017415
8531 05:59:03.020048 ----->DramcWriteLeveling(PI) begin...
8532 05:59:03.020762 ==
8533 05:59:03.023567 Dram Type= 6, Freq= 0, CH_1, rank 1
8534 05:59:03.026852 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8535 05:59:03.027473 ==
8536 05:59:03.029876 Write leveling (Byte 0): 22 => 22
8537 05:59:03.033371 Write leveling (Byte 1): 23 => 23
8538 05:59:03.036519 DramcWriteLeveling(PI) end<-----
8539 05:59:03.037041
8540 05:59:03.037428 ==
8541 05:59:03.039793 Dram Type= 6, Freq= 0, CH_1, rank 1
8542 05:59:03.043345 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8543 05:59:03.046224 ==
8544 05:59:03.046694 [Gating] SW mode calibration
8545 05:59:03.053171 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8546 05:59:03.059734 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8547 05:59:03.062948 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
8548 05:59:03.069438 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8549 05:59:03.072937 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8550 05:59:03.076182 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8551 05:59:03.082539 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8552 05:59:03.085895 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8553 05:59:03.089651 0 12 24 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)
8554 05:59:03.096065 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8555 05:59:03.099681 0 13 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8556 05:59:03.102758 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8557 05:59:03.109507 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8558 05:59:03.112634 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8559 05:59:03.115748 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8560 05:59:03.122412 0 13 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8561 05:59:03.125940 0 13 24 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
8562 05:59:03.129311 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8563 05:59:03.135575 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8564 05:59:03.138807 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8565 05:59:03.142317 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8566 05:59:03.148972 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8567 05:59:03.152464 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8568 05:59:03.155979 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8569 05:59:03.162139 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8570 05:59:03.165952 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8571 05:59:03.168871 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8572 05:59:03.175324 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8573 05:59:03.178708 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8574 05:59:03.181732 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8575 05:59:03.188557 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8576 05:59:03.191951 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8577 05:59:03.195501 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8578 05:59:03.201830 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8579 05:59:03.205284 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8580 05:59:03.208622 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8581 05:59:03.212375 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8582 05:59:03.219182 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8583 05:59:03.221878 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8584 05:59:03.225852 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8585 05:59:03.231583 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8586 05:59:03.235280 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8587 05:59:03.238913 Total UI for P1: 0, mck2ui 16
8588 05:59:03.241516 best dqsien dly found for B0: ( 1, 0, 22)
8589 05:59:03.245046 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8590 05:59:03.251992 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8591 05:59:03.255307 Total UI for P1: 0, mck2ui 16
8592 05:59:03.258273 best dqsien dly found for B1: ( 1, 0, 30)
8593 05:59:03.261716 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8594 05:59:03.264841 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8595 05:59:03.265307
8596 05:59:03.268198 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8597 05:59:03.271570 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8598 05:59:03.274999 [Gating] SW calibration Done
8599 05:59:03.275563 ==
8600 05:59:03.278456 Dram Type= 6, Freq= 0, CH_1, rank 1
8601 05:59:03.281433 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8602 05:59:03.281901 ==
8603 05:59:03.284848 RX Vref Scan: 0
8604 05:59:03.285393
8605 05:59:03.288370 RX Vref 0 -> 0, step: 1
8606 05:59:03.288982
8607 05:59:03.289356 RX Delay 0 -> 252, step: 8
8608 05:59:03.294855 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8609 05:59:03.297820 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8610 05:59:03.301320 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8611 05:59:03.304634 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8612 05:59:03.308395 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8613 05:59:03.314592 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8614 05:59:03.317714 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8615 05:59:03.321176 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8616 05:59:03.324457 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8617 05:59:03.327502 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8618 05:59:03.334462 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8619 05:59:03.338149 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8620 05:59:03.340655 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8621 05:59:03.343913 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8622 05:59:03.347211 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8623 05:59:03.354292 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8624 05:59:03.355029 ==
8625 05:59:03.357328 Dram Type= 6, Freq= 0, CH_1, rank 1
8626 05:59:03.360816 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8627 05:59:03.361386 ==
8628 05:59:03.361753 DQS Delay:
8629 05:59:03.364322 DQS0 = 0, DQS1 = 0
8630 05:59:03.364929 DQM Delay:
8631 05:59:03.367458 DQM0 = 131, DQM1 = 125
8632 05:59:03.368028 DQ Delay:
8633 05:59:03.370604 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8634 05:59:03.374182 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8635 05:59:03.377455 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8636 05:59:03.383943 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8637 05:59:03.384519
8638 05:59:03.384953
8639 05:59:03.385295 ==
8640 05:59:03.387257 Dram Type= 6, Freq= 0, CH_1, rank 1
8641 05:59:03.390161 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8642 05:59:03.390622 ==
8643 05:59:03.391057
8644 05:59:03.391396
8645 05:59:03.393759 TX Vref Scan disable
8646 05:59:03.394226 == TX Byte 0 ==
8647 05:59:03.400537 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8648 05:59:03.403634 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8649 05:59:03.404214 == TX Byte 1 ==
8650 05:59:03.410297 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8651 05:59:03.413299 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8652 05:59:03.413760 ==
8653 05:59:03.416854 Dram Type= 6, Freq= 0, CH_1, rank 1
8654 05:59:03.420016 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8655 05:59:03.420480 ==
8656 05:59:03.433792
8657 05:59:03.437169 TX Vref early break, caculate TX vref
8658 05:59:03.440100 TX Vref=16, minBit 1, minWin=22, winSum=371
8659 05:59:03.443785 TX Vref=18, minBit 0, minWin=23, winSum=381
8660 05:59:03.446977 TX Vref=20, minBit 0, minWin=23, winSum=392
8661 05:59:03.450151 TX Vref=22, minBit 2, minWin=24, winSum=399
8662 05:59:03.453178 TX Vref=24, minBit 2, minWin=24, winSum=408
8663 05:59:03.459930 TX Vref=26, minBit 0, minWin=25, winSum=420
8664 05:59:03.463069 TX Vref=28, minBit 0, minWin=25, winSum=416
8665 05:59:03.466436 TX Vref=30, minBit 0, minWin=24, winSum=412
8666 05:59:03.469853 TX Vref=32, minBit 0, minWin=24, winSum=402
8667 05:59:03.473404 TX Vref=34, minBit 0, minWin=22, winSum=394
8668 05:59:03.479899 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 26
8669 05:59:03.480500
8670 05:59:03.483278 Final TX Range 0 Vref 26
8671 05:59:03.483755
8672 05:59:03.484235 ==
8673 05:59:03.486179 Dram Type= 6, Freq= 0, CH_1, rank 1
8674 05:59:03.489953 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8675 05:59:03.490547 ==
8676 05:59:03.491037
8677 05:59:03.491485
8678 05:59:03.493327 TX Vref Scan disable
8679 05:59:03.500387 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8680 05:59:03.501016 == TX Byte 0 ==
8681 05:59:03.502482 u2DelayCellOfst[0]=14 cells (4 PI)
8682 05:59:03.506576 u2DelayCellOfst[1]=7 cells (2 PI)
8683 05:59:03.509641 u2DelayCellOfst[2]=0 cells (0 PI)
8684 05:59:03.512911 u2DelayCellOfst[3]=7 cells (2 PI)
8685 05:59:03.516412 u2DelayCellOfst[4]=7 cells (2 PI)
8686 05:59:03.519530 u2DelayCellOfst[5]=14 cells (4 PI)
8687 05:59:03.523083 u2DelayCellOfst[6]=14 cells (4 PI)
8688 05:59:03.526399 u2DelayCellOfst[7]=3 cells (1 PI)
8689 05:59:03.529613 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8690 05:59:03.532902 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8691 05:59:03.536468 == TX Byte 1 ==
8692 05:59:03.537068 u2DelayCellOfst[8]=0 cells (0 PI)
8693 05:59:03.539059 u2DelayCellOfst[9]=7 cells (2 PI)
8694 05:59:03.542680 u2DelayCellOfst[10]=14 cells (4 PI)
8695 05:59:03.545968 u2DelayCellOfst[11]=7 cells (2 PI)
8696 05:59:03.549329 u2DelayCellOfst[12]=18 cells (5 PI)
8697 05:59:03.552428 u2DelayCellOfst[13]=21 cells (6 PI)
8698 05:59:03.556011 u2DelayCellOfst[14]=21 cells (6 PI)
8699 05:59:03.559050 u2DelayCellOfst[15]=21 cells (6 PI)
8700 05:59:03.562176 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8701 05:59:03.568788 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8702 05:59:03.569328 DramC Write-DBI on
8703 05:59:03.569690 ==
8704 05:59:03.572473 Dram Type= 6, Freq= 0, CH_1, rank 1
8705 05:59:03.579102 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8706 05:59:03.579661 ==
8707 05:59:03.580025
8708 05:59:03.580353
8709 05:59:03.580670 TX Vref Scan disable
8710 05:59:03.582636 == TX Byte 0 ==
8711 05:59:03.586122 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8712 05:59:03.589304 == TX Byte 1 ==
8713 05:59:03.592586 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8714 05:59:03.595894 DramC Write-DBI off
8715 05:59:03.596447
8716 05:59:03.596839 [DATLAT]
8717 05:59:03.597181 Freq=1600, CH1 RK1
8718 05:59:03.597508
8719 05:59:03.599400 DATLAT Default: 0xe
8720 05:59:03.602326 0, 0xFFFF, sum = 0
8721 05:59:03.602855 1, 0xFFFF, sum = 0
8722 05:59:03.605990 2, 0xFFFF, sum = 0
8723 05:59:03.606549 3, 0xFFFF, sum = 0
8724 05:59:03.609428 4, 0xFFFF, sum = 0
8725 05:59:03.609991 5, 0xFFFF, sum = 0
8726 05:59:03.612480 6, 0xFFFF, sum = 0
8727 05:59:03.613073 7, 0xFFFF, sum = 0
8728 05:59:03.615834 8, 0xFFFF, sum = 0
8729 05:59:03.616396 9, 0xFFFF, sum = 0
8730 05:59:03.618704 10, 0xFFFF, sum = 0
8731 05:59:03.619170 11, 0xFFFF, sum = 0
8732 05:59:03.622884 12, 0xF7F, sum = 0
8733 05:59:03.623449 13, 0x0, sum = 1
8734 05:59:03.625556 14, 0x0, sum = 2
8735 05:59:03.626019 15, 0x0, sum = 3
8736 05:59:03.628692 16, 0x0, sum = 4
8737 05:59:03.629194 best_step = 14
8738 05:59:03.629555
8739 05:59:03.629889 ==
8740 05:59:03.631983 Dram Type= 6, Freq= 0, CH_1, rank 1
8741 05:59:03.638916 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8742 05:59:03.639474 ==
8743 05:59:03.639838 RX Vref Scan: 0
8744 05:59:03.640172
8745 05:59:03.642220 RX Vref 0 -> 0, step: 1
8746 05:59:03.642775
8747 05:59:03.645683 RX Delay 3 -> 252, step: 4
8748 05:59:03.648765 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8749 05:59:03.652093 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8750 05:59:03.655276 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8751 05:59:03.662342 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8752 05:59:03.665484 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8753 05:59:03.668821 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8754 05:59:03.671546 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8755 05:59:03.674963 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8756 05:59:03.681778 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8757 05:59:03.685175 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8758 05:59:03.687992 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8759 05:59:03.691521 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8760 05:59:03.694727 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8761 05:59:03.701817 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8762 05:59:03.704798 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8763 05:59:03.708246 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8764 05:59:03.708854 ==
8765 05:59:03.711878 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 05:59:03.715054 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8767 05:59:03.717847 ==
8768 05:59:03.718306 DQS Delay:
8769 05:59:03.718682 DQS0 = 0, DQS1 = 0
8770 05:59:03.721459 DQM Delay:
8771 05:59:03.722018 DQM0 = 126, DQM1 = 122
8772 05:59:03.724405 DQ Delay:
8773 05:59:03.728251 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =122
8774 05:59:03.731486 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8775 05:59:03.734569 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8776 05:59:03.737846 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8777 05:59:03.738361
8778 05:59:03.738729
8779 05:59:03.739063
8780 05:59:03.741036 [DramC_TX_OE_Calibration] TA2
8781 05:59:03.745032 Original DQ_B0 (3 6) =30, OEN = 27
8782 05:59:03.747857 Original DQ_B1 (3 6) =30, OEN = 27
8783 05:59:03.751051 24, 0x0, End_B0=24 End_B1=24
8784 05:59:03.751522 25, 0x0, End_B0=25 End_B1=25
8785 05:59:03.754705 26, 0x0, End_B0=26 End_B1=26
8786 05:59:03.758045 27, 0x0, End_B0=27 End_B1=27
8787 05:59:03.760997 28, 0x0, End_B0=28 End_B1=28
8788 05:59:03.761471 29, 0x0, End_B0=29 End_B1=29
8789 05:59:03.764536 30, 0x0, End_B0=30 End_B1=30
8790 05:59:03.768292 31, 0x4141, End_B0=30 End_B1=30
8791 05:59:03.771162 Byte0 end_step=30 best_step=27
8792 05:59:03.774746 Byte1 end_step=30 best_step=27
8793 05:59:03.777833 Byte0 TX OE(2T, 0.5T) = (3, 3)
8794 05:59:03.778292 Byte1 TX OE(2T, 0.5T) = (3, 3)
8795 05:59:03.778648
8796 05:59:03.781304
8797 05:59:03.787985 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8798 05:59:03.790909 CH1 RK1: MR19=303, MR18=1B1B
8799 05:59:03.797646 CH1_RK1: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8800 05:59:03.800526 [RxdqsGatingPostProcess] freq 1600
8801 05:59:03.804100 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8802 05:59:03.807296 Pre-setting of DQS Precalculation
8803 05:59:03.814266 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8804 05:59:03.820523 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8805 05:59:03.827494 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8806 05:59:03.828058
8807 05:59:03.828422
8808 05:59:03.830715 [Calibration Summary] 3200 Mbps
8809 05:59:03.831176 CH 0, Rank 0
8810 05:59:03.834433 SW Impedance : PASS
8811 05:59:03.837379 DUTY Scan : NO K
8812 05:59:03.838050 ZQ Calibration : PASS
8813 05:59:03.840284 Jitter Meter : NO K
8814 05:59:03.844113 CBT Training : PASS
8815 05:59:03.844766 Write leveling : PASS
8816 05:59:03.847015 RX DQS gating : PASS
8817 05:59:03.850377 RX DQ/DQS(RDDQC) : PASS
8818 05:59:03.850849 TX DQ/DQS : PASS
8819 05:59:03.853469 RX DATLAT : PASS
8820 05:59:03.857335 RX DQ/DQS(Engine): PASS
8821 05:59:03.857890 TX OE : PASS
8822 05:59:03.858253 All Pass.
8823 05:59:03.860503
8824 05:59:03.861008 CH 0, Rank 1
8825 05:59:03.863647 SW Impedance : PASS
8826 05:59:03.864207 DUTY Scan : NO K
8827 05:59:03.867517 ZQ Calibration : PASS
8828 05:59:03.868071 Jitter Meter : NO K
8829 05:59:03.870254 CBT Training : PASS
8830 05:59:03.873434 Write leveling : PASS
8831 05:59:03.873892 RX DQS gating : PASS
8832 05:59:03.877298 RX DQ/DQS(RDDQC) : PASS
8833 05:59:03.880523 TX DQ/DQS : PASS
8834 05:59:03.881141 RX DATLAT : PASS
8835 05:59:03.883855 RX DQ/DQS(Engine): PASS
8836 05:59:03.886869 TX OE : PASS
8837 05:59:03.887427 All Pass.
8838 05:59:03.887792
8839 05:59:03.888141 CH 1, Rank 0
8840 05:59:03.890089 SW Impedance : PASS
8841 05:59:03.893409 DUTY Scan : NO K
8842 05:59:03.893871 ZQ Calibration : PASS
8843 05:59:03.896499 Jitter Meter : NO K
8844 05:59:03.900178 CBT Training : PASS
8845 05:59:03.900779 Write leveling : PASS
8846 05:59:03.903560 RX DQS gating : PASS
8847 05:59:03.906881 RX DQ/DQS(RDDQC) : PASS
8848 05:59:03.907339 TX DQ/DQS : PASS
8849 05:59:03.910082 RX DATLAT : PASS
8850 05:59:03.913278 RX DQ/DQS(Engine): PASS
8851 05:59:03.913741 TX OE : PASS
8852 05:59:03.916906 All Pass.
8853 05:59:03.917369
8854 05:59:03.917727 CH 1, Rank 1
8855 05:59:03.919606 SW Impedance : PASS
8856 05:59:03.920067 DUTY Scan : NO K
8857 05:59:03.923528 ZQ Calibration : PASS
8858 05:59:03.926691 Jitter Meter : NO K
8859 05:59:03.927250 CBT Training : PASS
8860 05:59:03.929555 Write leveling : PASS
8861 05:59:03.932885 RX DQS gating : PASS
8862 05:59:03.933347 RX DQ/DQS(RDDQC) : PASS
8863 05:59:03.936766 TX DQ/DQS : PASS
8864 05:59:03.937340 RX DATLAT : PASS
8865 05:59:03.940074 RX DQ/DQS(Engine): PASS
8866 05:59:03.943037 TX OE : PASS
8867 05:59:03.943499 All Pass.
8868 05:59:03.943855
8869 05:59:03.946555 DramC Write-DBI on
8870 05:59:03.947111 PER_BANK_REFRESH: Hybrid Mode
8871 05:59:03.949615 TX_TRACKING: ON
8872 05:59:03.959991 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8873 05:59:03.966532 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8874 05:59:03.973043 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8875 05:59:03.976463 [FAST_K] Save calibration result to emmc
8876 05:59:03.979066 sync common calibartion params.
8877 05:59:03.982419 sync cbt_mode0:0, 1:0
8878 05:59:03.982876 dram_init: ddr_geometry: 0
8879 05:59:03.986046 dram_init: ddr_geometry: 0
8880 05:59:03.989639 dram_init: ddr_geometry: 0
8881 05:59:03.992550 0:dram_rank_size:80000000
8882 05:59:03.993044 1:dram_rank_size:80000000
8883 05:59:03.999356 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8884 05:59:04.002556 DFS_SHUFFLE_HW_MODE: ON
8885 05:59:04.006334 dramc_set_vcore_voltage set vcore to 725000
8886 05:59:04.006893 Read voltage for 1600, 0
8887 05:59:04.009424 Vio18 = 0
8888 05:59:04.009976 Vcore = 725000
8889 05:59:04.010341 Vdram = 0
8890 05:59:04.012671 Vddq = 0
8891 05:59:04.013270 Vmddr = 0
8892 05:59:04.015718 switch to 3200 Mbps bootup
8893 05:59:04.016177 [DramcRunTimeConfig]
8894 05:59:04.018905 PHYPLL
8895 05:59:04.019361 DPM_CONTROL_AFTERK: ON
8896 05:59:04.022020 PER_BANK_REFRESH: ON
8897 05:59:04.025657 REFRESH_OVERHEAD_REDUCTION: ON
8898 05:59:04.026213 CMD_PICG_NEW_MODE: OFF
8899 05:59:04.028724 XRTWTW_NEW_MODE: ON
8900 05:59:04.029187 XRTRTR_NEW_MODE: ON
8901 05:59:04.032048 TX_TRACKING: ON
8902 05:59:04.032506 RDSEL_TRACKING: OFF
8903 05:59:04.035696 DQS Precalculation for DVFS: ON
8904 05:59:04.039094 RX_TRACKING: OFF
8905 05:59:04.039648 HW_GATING DBG: ON
8906 05:59:04.042043 ZQCS_ENABLE_LP4: ON
8907 05:59:04.042560 RX_PICG_NEW_MODE: ON
8908 05:59:04.045402 TX_PICG_NEW_MODE: ON
8909 05:59:04.045865 ENABLE_RX_DCM_DPHY: ON
8910 05:59:04.048906 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8911 05:59:04.052072 DUMMY_READ_FOR_TRACKING: OFF
8912 05:59:04.055754 !!! SPM_CONTROL_AFTERK: OFF
8913 05:59:04.058758 !!! SPM could not control APHY
8914 05:59:04.059320 IMPEDANCE_TRACKING: ON
8915 05:59:04.062061 TEMP_SENSOR: ON
8916 05:59:04.062527 HW_SAVE_FOR_SR: OFF
8917 05:59:04.065082 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8918 05:59:04.069236 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8919 05:59:04.071993 Read ODT Tracking: ON
8920 05:59:04.076105 Refresh Rate DeBounce: ON
8921 05:59:04.076663 DFS_NO_QUEUE_FLUSH: ON
8922 05:59:04.078481 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8923 05:59:04.081766 ENABLE_DFS_RUNTIME_MRW: OFF
8924 05:59:04.085415 DDR_RESERVE_NEW_MODE: ON
8925 05:59:04.085977 MR_CBT_SWITCH_FREQ: ON
8926 05:59:04.088357 =========================
8927 05:59:04.107496 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8928 05:59:04.110780 dram_init: ddr_geometry: 0
8929 05:59:04.128770 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8930 05:59:04.131944 dram_init: dram init end (result: 0)
8931 05:59:04.138177 DRAM-K: Full calibration passed in 23422 msecs
8932 05:59:04.141499 MRC: failed to locate region type 0.
8933 05:59:04.141966 DRAM rank0 size:0x80000000,
8934 05:59:04.145028 DRAM rank1 size=0x80000000
8935 05:59:04.155281 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8936 05:59:04.161429 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8937 05:59:04.168181 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8938 05:59:04.174733 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8939 05:59:04.177702 DRAM rank0 size:0x80000000,
8940 05:59:04.181294 DRAM rank1 size=0x80000000
8941 05:59:04.181753 CBMEM:
8942 05:59:04.185003 IMD: root @ 0xfffff000 254 entries.
8943 05:59:04.187883 IMD: root @ 0xffffec00 62 entries.
8944 05:59:04.191738 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8945 05:59:04.194200 WARNING: RO_VPD is uninitialized or empty.
8946 05:59:04.201143 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8947 05:59:04.208423 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8948 05:59:04.221036 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8949 05:59:04.232399 BS: romstage times (exec / console): total (unknown) / 22961 ms
8950 05:59:04.233059
8951 05:59:04.233432
8952 05:59:04.242803 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8953 05:59:04.245497 ARM64: Exception handlers installed.
8954 05:59:04.249054 ARM64: Testing exception
8955 05:59:04.252061 ARM64: Done test exception
8956 05:59:04.252637 Enumerating buses...
8957 05:59:04.255711 Show all devs... Before device enumeration.
8958 05:59:04.258928 Root Device: enabled 1
8959 05:59:04.262311 CPU_CLUSTER: 0: enabled 1
8960 05:59:04.262880 CPU: 00: enabled 1
8961 05:59:04.265074 Compare with tree...
8962 05:59:04.265534 Root Device: enabled 1
8963 05:59:04.269135 CPU_CLUSTER: 0: enabled 1
8964 05:59:04.272065 CPU: 00: enabled 1
8965 05:59:04.272622 Root Device scanning...
8966 05:59:04.275881 scan_static_bus for Root Device
8967 05:59:04.278348 CPU_CLUSTER: 0 enabled
8968 05:59:04.281641 scan_static_bus for Root Device done
8969 05:59:04.285467 scan_bus: bus Root Device finished in 8 msecs
8970 05:59:04.286219 done
8971 05:59:04.292282 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8972 05:59:04.294769 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8973 05:59:04.301713 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8974 05:59:04.304861 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8975 05:59:04.308241 Allocating resources...
8976 05:59:04.311778 Reading resources...
8977 05:59:04.314893 Root Device read_resources bus 0 link: 0
8978 05:59:04.318054 DRAM rank0 size:0x80000000,
8979 05:59:04.318612 DRAM rank1 size=0x80000000
8980 05:59:04.321326 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8981 05:59:04.324834 CPU: 00 missing read_resources
8982 05:59:04.331125 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8983 05:59:04.334670 Root Device read_resources bus 0 link: 0 done
8984 05:59:04.335280 Done reading resources.
8985 05:59:04.341184 Show resources in subtree (Root Device)...After reading.
8986 05:59:04.344323 Root Device child on link 0 CPU_CLUSTER: 0
8987 05:59:04.348164 CPU_CLUSTER: 0 child on link 0 CPU: 00
8988 05:59:04.357861 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8989 05:59:04.358423 CPU: 00
8990 05:59:04.360926 Root Device assign_resources, bus 0 link: 0
8991 05:59:04.364634 CPU_CLUSTER: 0 missing set_resources
8992 05:59:04.371285 Root Device assign_resources, bus 0 link: 0 done
8993 05:59:04.371847 Done setting resources.
8994 05:59:04.377498 Show resources in subtree (Root Device)...After assigning values.
8995 05:59:04.380761 Root Device child on link 0 CPU_CLUSTER: 0
8996 05:59:04.384117 CPU_CLUSTER: 0 child on link 0 CPU: 00
8997 05:59:04.394057 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8998 05:59:04.394599 CPU: 00
8999 05:59:04.397058 Done allocating resources.
9000 05:59:04.403828 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9001 05:59:04.404378 Enabling resources...
9002 05:59:04.404779 done.
9003 05:59:04.410622 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9004 05:59:04.414419 Initializing devices...
9005 05:59:04.414974 Root Device init
9006 05:59:04.417423 init hardware done!
9007 05:59:04.417981 0x00000018: ctrlr->caps
9008 05:59:04.420354 52.000 MHz: ctrlr->f_max
9009 05:59:04.424429 0.400 MHz: ctrlr->f_min
9010 05:59:04.425056 0x40ff8080: ctrlr->voltages
9011 05:59:04.427204 sclk: 390625
9012 05:59:04.427664 Bus Width = 1
9013 05:59:04.428026 sclk: 390625
9014 05:59:04.430721 Bus Width = 1
9015 05:59:04.431181 Early init status = 3
9016 05:59:04.437466 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9017 05:59:04.440362 in-header: 03 fc 00 00 01 00 00 00
9018 05:59:04.443596 in-data: 00
9019 05:59:04.447011 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9020 05:59:04.452131 in-header: 03 fd 00 00 00 00 00 00
9021 05:59:04.455074 in-data:
9022 05:59:04.458406 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9023 05:59:04.461658 in-header: 03 fc 00 00 01 00 00 00
9024 05:59:04.465332 in-data: 00
9025 05:59:04.468526 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9026 05:59:04.473436 in-header: 03 fd 00 00 00 00 00 00
9027 05:59:04.476513 in-data:
9028 05:59:04.479966 [SSUSB] Setting up USB HOST controller...
9029 05:59:04.483431 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9030 05:59:04.486626 [SSUSB] phy power-on done.
9031 05:59:04.489725 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9032 05:59:04.496484 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9033 05:59:04.499843 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9034 05:59:04.506717 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9035 05:59:04.513276 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9036 05:59:04.519512 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9037 05:59:04.526584 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9038 05:59:04.533196 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9039 05:59:04.536641 SPM: binary array size = 0x9dc
9040 05:59:04.540132 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9041 05:59:04.545978 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9042 05:59:04.553011 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9043 05:59:04.560008 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9044 05:59:04.563031 configure_display: Starting display init
9045 05:59:04.596682 anx7625_power_on_init: Init interface.
9046 05:59:04.600504 anx7625_disable_pd_protocol: Disabled PD feature.
9047 05:59:04.603978 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9048 05:59:04.631707 anx7625_start_dp_work: Secure OCM version=00
9049 05:59:04.634374 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9050 05:59:04.649309 sp_tx_get_edid_block: EDID Block = 1
9051 05:59:04.751898 Extracted contents:
9052 05:59:04.755470 header: 00 ff ff ff ff ff ff 00
9053 05:59:04.758345 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9054 05:59:04.762072 version: 01 04
9055 05:59:04.765203 basic params: 95 1f 11 78 0a
9056 05:59:04.768973 chroma info: 76 90 94 55 54 90 27 21 50 54
9057 05:59:04.771766 established: 00 00 00
9058 05:59:04.778693 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9059 05:59:04.781630 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9060 05:59:04.788403 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9061 05:59:04.795057 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9062 05:59:04.801549 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9063 05:59:04.804847 extensions: 00
9064 05:59:04.805320 checksum: fb
9065 05:59:04.805676
9066 05:59:04.808078 Manufacturer: IVO Model 57d Serial Number 0
9067 05:59:04.811234 Made week 0 of 2020
9068 05:59:04.815016 EDID version: 1.4
9069 05:59:04.815584 Digital display
9070 05:59:04.817727 6 bits per primary color channel
9071 05:59:04.818192 DisplayPort interface
9072 05:59:04.820899 Maximum image size: 31 cm x 17 cm
9073 05:59:04.824807 Gamma: 220%
9074 05:59:04.825366 Check DPMS levels
9075 05:59:04.828095 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9076 05:59:04.834494 First detailed timing is preferred timing
9077 05:59:04.834953 Established timings supported:
9078 05:59:04.837956 Standard timings supported:
9079 05:59:04.840979 Detailed timings
9080 05:59:04.844828 Hex of detail: 383680a07038204018303c0035ae10000019
9081 05:59:04.850824 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9082 05:59:04.854125 0780 0798 07c8 0820 hborder 0
9083 05:59:04.857379 0438 043b 0447 0458 vborder 0
9084 05:59:04.860745 -hsync -vsync
9085 05:59:04.861234 Did detailed timing
9086 05:59:04.867377 Hex of detail: 000000000000000000000000000000000000
9087 05:59:04.870843 Manufacturer-specified data, tag 0
9088 05:59:04.874032 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9089 05:59:04.877396 ASCII string: InfoVision
9090 05:59:04.880278 Hex of detail: 000000fe00523134304e574635205248200a
9091 05:59:04.883885 ASCII string: R140NWF5 RH
9092 05:59:04.884441 Checksum
9093 05:59:04.887442 Checksum: 0xfb (valid)
9094 05:59:04.890439 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9095 05:59:04.894376 DSI data_rate: 832800000 bps
9096 05:59:04.900399 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9097 05:59:04.903894 anx7625_parse_edid: pixelclock(138800).
9098 05:59:04.907342 hactive(1920), hsync(48), hfp(24), hbp(88)
9099 05:59:04.910528 vactive(1080), vsync(12), vfp(3), vbp(17)
9100 05:59:04.913636 anx7625_dsi_config: config dsi.
9101 05:59:04.920370 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9102 05:59:04.933886 anx7625_dsi_config: success to config DSI
9103 05:59:04.937378 anx7625_dp_start: MIPI phy setup OK.
9104 05:59:04.940429 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9105 05:59:04.943710 mtk_ddp_mode_set invalid vrefresh 60
9106 05:59:04.946908 main_disp_path_setup
9107 05:59:04.947406 ovl_layer_smi_id_en
9108 05:59:04.950134 ovl_layer_smi_id_en
9109 05:59:04.950681 ccorr_config
9110 05:59:04.951051 aal_config
9111 05:59:04.953480 gamma_config
9112 05:59:04.953941 postmask_config
9113 05:59:04.956981 dither_config
9114 05:59:04.960134 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9115 05:59:04.966449 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9116 05:59:04.970007 Root Device init finished in 552 msecs
9117 05:59:04.973617 CPU_CLUSTER: 0 init
9118 05:59:04.980398 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9119 05:59:04.986781 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9120 05:59:04.987331 APU_MBOX 0x190000b0 = 0x10001
9121 05:59:04.989849 APU_MBOX 0x190001b0 = 0x10001
9122 05:59:04.992991 APU_MBOX 0x190005b0 = 0x10001
9123 05:59:04.996781 APU_MBOX 0x190006b0 = 0x10001
9124 05:59:05.002822 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9125 05:59:05.013224 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9126 05:59:05.025044 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9127 05:59:05.031787 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9128 05:59:05.043058 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9129 05:59:05.052171 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9130 05:59:05.055821 CPU_CLUSTER: 0 init finished in 81 msecs
9131 05:59:05.059415 Devices initialized
9132 05:59:05.062322 Show all devs... After init.
9133 05:59:05.062784 Root Device: enabled 1
9134 05:59:05.065563 CPU_CLUSTER: 0: enabled 1
9135 05:59:05.068930 CPU: 00: enabled 1
9136 05:59:05.072747 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9137 05:59:05.075858 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9138 05:59:05.079056 ELOG: NV offset 0x57f000 size 0x1000
9139 05:59:05.085626 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9140 05:59:05.092253 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9141 05:59:05.095609 ELOG: Event(17) added with size 13 at 2023-12-25 05:59:04 UTC
9142 05:59:05.102309 out: cmd=0x121: 03 db 21 01 00 00 00 00
9143 05:59:05.105358 in-header: 03 fa 00 00 2c 00 00 00
9144 05:59:05.115624 in-data: 69 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9145 05:59:05.122177 ELOG: Event(A1) added with size 10 at 2023-12-25 05:59:04 UTC
9146 05:59:05.128747 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9147 05:59:05.135212 ELOG: Event(A0) added with size 9 at 2023-12-25 05:59:04 UTC
9148 05:59:05.138666 elog_add_boot_reason: Logged dev mode boot
9149 05:59:05.145014 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9150 05:59:05.145727 Finalize devices...
9151 05:59:05.148300 Devices finalized
9152 05:59:05.151666 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9153 05:59:05.155169 Writing coreboot table at 0xffe64000
9154 05:59:05.158175 0. 000000000010a000-0000000000113fff: RAMSTAGE
9155 05:59:05.164658 1. 0000000040000000-00000000400fffff: RAM
9156 05:59:05.168086 2. 0000000040100000-000000004032afff: RAMSTAGE
9157 05:59:05.171219 3. 000000004032b000-00000000545fffff: RAM
9158 05:59:05.174980 4. 0000000054600000-000000005465ffff: BL31
9159 05:59:05.177888 5. 0000000054660000-00000000ffe63fff: RAM
9160 05:59:05.184531 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9161 05:59:05.188054 7. 0000000100000000-000000013fffffff: RAM
9162 05:59:05.190886 Passing 5 GPIOs to payload:
9163 05:59:05.194425 NAME | PORT | POLARITY | VALUE
9164 05:59:05.201076 EC in RW | 0x000000aa | low | undefined
9165 05:59:05.204144 EC interrupt | 0x00000005 | low | undefined
9166 05:59:05.211065 TPM interrupt | 0x000000ab | high | undefined
9167 05:59:05.214114 SD card detect | 0x00000011 | high | undefined
9168 05:59:05.217292 speaker enable | 0x00000093 | high | undefined
9169 05:59:05.220866 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9170 05:59:05.224454 in-header: 03 f8 00 00 02 00 00 00
9171 05:59:05.227805 in-data: 03 00
9172 05:59:05.231100 ADC[4]: Raw value=669327 ID=5
9173 05:59:05.234250 ADC[3]: Raw value=212549 ID=1
9174 05:59:05.234705 RAM Code: 0x51
9175 05:59:05.237207 ADC[6]: Raw value=74410 ID=0
9176 05:59:05.240856 ADC[5]: Raw value=211444 ID=1
9177 05:59:05.241410 SKU Code: 0x1
9178 05:59:05.247219 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 97e2
9179 05:59:05.247768 coreboot table: 964 bytes.
9180 05:59:05.250458 IMD ROOT 0. 0xfffff000 0x00001000
9181 05:59:05.253868 IMD SMALL 1. 0xffffe000 0x00001000
9182 05:59:05.257481 RO MCACHE 2. 0xffffc000 0x00001104
9183 05:59:05.260869 CONSOLE 3. 0xfff7c000 0x00080000
9184 05:59:05.264262 FMAP 4. 0xfff7b000 0x00000452
9185 05:59:05.267087 TIME STAMP 5. 0xfff7a000 0x00000910
9186 05:59:05.270611 VBOOT WORK 6. 0xfff66000 0x00014000
9187 05:59:05.273814 RAMOOPS 7. 0xffe66000 0x00100000
9188 05:59:05.276991 COREBOOT 8. 0xffe64000 0x00002000
9189 05:59:05.280531 IMD small region:
9190 05:59:05.283820 IMD ROOT 0. 0xffffec00 0x00000400
9191 05:59:05.286815 VPD 1. 0xffffeb80 0x0000006c
9192 05:59:05.290125 MMC STATUS 2. 0xffffeb60 0x00000004
9193 05:59:05.296876 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9194 05:59:05.297438 Probing TPM: done!
9195 05:59:05.303890 Connected to device vid:did:rid of 1ae0:0028:00
9196 05:59:05.310153 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9197 05:59:05.313929 Initialized TPM device CR50 revision 0
9198 05:59:05.316785 Checking cr50 for pending updates
9199 05:59:05.322869 Reading cr50 TPM mode
9200 05:59:05.331363 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9201 05:59:05.337478 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9202 05:59:05.377817 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9203 05:59:05.381454 Checking segment from ROM address 0x40100000
9204 05:59:05.384832 Checking segment from ROM address 0x4010001c
9205 05:59:05.390714 Loading segment from ROM address 0x40100000
9206 05:59:05.391173 code (compression=0)
9207 05:59:05.400998 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9208 05:59:05.407457 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9209 05:59:05.408022 it's not compressed!
9210 05:59:05.414124 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9211 05:59:05.417382 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9212 05:59:05.437972 Loading segment from ROM address 0x4010001c
9213 05:59:05.438530 Entry Point 0x80000000
9214 05:59:05.441307 Loaded segments
9215 05:59:05.444772 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9216 05:59:05.451123 Jumping to boot code at 0x80000000(0xffe64000)
9217 05:59:05.458022 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9218 05:59:05.464334 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9219 05:59:05.472353 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9220 05:59:05.475852 Checking segment from ROM address 0x40100000
9221 05:59:05.479428 Checking segment from ROM address 0x4010001c
9222 05:59:05.485963 Loading segment from ROM address 0x40100000
9223 05:59:05.486544 code (compression=1)
9224 05:59:05.492549 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9225 05:59:05.502532 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9226 05:59:05.503124 using LZMA
9227 05:59:05.510393 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9228 05:59:05.517406 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9229 05:59:05.520855 Loading segment from ROM address 0x4010001c
9230 05:59:05.521315 Entry Point 0x54601000
9231 05:59:05.524058 Loaded segments
9232 05:59:05.527001 NOTICE: MT8192 bl31_setup
9233 05:59:05.534174 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9234 05:59:05.537841 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9235 05:59:05.541318 WARNING: region 0:
9236 05:59:05.544685 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9237 05:59:05.545298 WARNING: region 1:
9238 05:59:05.551017 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9239 05:59:05.554364 WARNING: region 2:
9240 05:59:05.557506 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9241 05:59:05.561007 WARNING: region 3:
9242 05:59:05.564138 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9243 05:59:05.567956 WARNING: region 4:
9244 05:59:05.574728 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9245 05:59:05.575294 WARNING: region 5:
9246 05:59:05.577978 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9247 05:59:05.581053 WARNING: region 6:
9248 05:59:05.584248 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9249 05:59:05.588023 WARNING: region 7:
9250 05:59:05.590767 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9251 05:59:05.597609 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9252 05:59:05.601657 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9253 05:59:05.604605 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9254 05:59:05.611036 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9255 05:59:05.613996 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9256 05:59:05.617633 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9257 05:59:05.624024 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9258 05:59:05.628022 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9259 05:59:05.634247 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9260 05:59:05.637311 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9261 05:59:05.641166 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9262 05:59:05.647269 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9263 05:59:05.650851 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9264 05:59:05.654085 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9265 05:59:05.660693 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9266 05:59:05.664174 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9267 05:59:05.671261 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9268 05:59:05.674587 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9269 05:59:05.677245 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9270 05:59:05.684846 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9271 05:59:05.687284 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9272 05:59:05.690920 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9273 05:59:05.697615 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9274 05:59:05.701252 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9275 05:59:05.707328 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9276 05:59:05.710857 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9277 05:59:05.714489 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9278 05:59:05.720946 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9279 05:59:05.724144 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9280 05:59:05.731269 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9281 05:59:05.734106 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9282 05:59:05.737775 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9283 05:59:05.744260 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9284 05:59:05.748076 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9285 05:59:05.750683 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9286 05:59:05.754015 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9287 05:59:05.760847 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9288 05:59:05.764057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9289 05:59:05.767852 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9290 05:59:05.771055 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9291 05:59:05.774680 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9292 05:59:05.781174 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9293 05:59:05.784130 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9294 05:59:05.787778 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9295 05:59:05.794153 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9296 05:59:05.797674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9297 05:59:05.801478 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9298 05:59:05.804315 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9299 05:59:05.811191 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9300 05:59:05.814232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9301 05:59:05.821078 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9302 05:59:05.824282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9303 05:59:05.827743 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9304 05:59:05.834577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9305 05:59:05.837665 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9306 05:59:05.844269 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9307 05:59:05.847678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9308 05:59:05.854374 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9309 05:59:05.857466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9310 05:59:05.860532 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9311 05:59:05.867658 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9312 05:59:05.870759 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9313 05:59:05.877721 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9314 05:59:05.881153 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9315 05:59:05.887696 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9316 05:59:05.890666 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9317 05:59:05.897524 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9318 05:59:05.901109 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9319 05:59:05.904034 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9320 05:59:05.910768 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9321 05:59:05.914104 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9322 05:59:05.920458 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9323 05:59:05.923819 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9324 05:59:05.930827 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9325 05:59:05.933832 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9326 05:59:05.937084 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9327 05:59:05.944150 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9328 05:59:05.947219 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9329 05:59:05.953750 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9330 05:59:05.957285 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9331 05:59:05.963878 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9332 05:59:05.967350 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9333 05:59:05.973699 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9334 05:59:05.977038 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9335 05:59:05.980515 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9336 05:59:05.987408 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9337 05:59:05.990678 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9338 05:59:05.997109 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9339 05:59:06.000845 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9340 05:59:06.004232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9341 05:59:06.010456 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9342 05:59:06.013456 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9343 05:59:06.019977 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9344 05:59:06.023485 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9345 05:59:06.030392 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9346 05:59:06.033540 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9347 05:59:06.036950 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9348 05:59:06.043481 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9349 05:59:06.046622 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9350 05:59:06.049941 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9351 05:59:06.053360 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9352 05:59:06.060113 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9353 05:59:06.063836 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9354 05:59:06.069667 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9355 05:59:06.073639 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9356 05:59:06.076794 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9357 05:59:06.083147 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9358 05:59:06.086288 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9359 05:59:06.092976 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9360 05:59:06.096269 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9361 05:59:06.100023 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9362 05:59:06.106212 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9363 05:59:06.109937 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9364 05:59:06.116336 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9365 05:59:06.119937 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9366 05:59:06.122987 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9367 05:59:06.129418 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9368 05:59:06.133217 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9369 05:59:06.136799 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9370 05:59:06.142835 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9371 05:59:06.146131 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9372 05:59:06.149277 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9373 05:59:06.152661 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9374 05:59:06.160101 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9375 05:59:06.163026 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9376 05:59:06.166433 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9377 05:59:06.173186 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9378 05:59:06.175985 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9379 05:59:06.182630 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9380 05:59:06.186118 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9381 05:59:06.189719 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9382 05:59:06.196000 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9383 05:59:06.199572 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9384 05:59:06.206179 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9385 05:59:06.209501 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9386 05:59:06.212442 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9387 05:59:06.219333 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9388 05:59:06.223107 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9389 05:59:06.229145 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9390 05:59:06.232875 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9391 05:59:06.236332 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9392 05:59:06.242552 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9393 05:59:06.246197 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9394 05:59:06.252413 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9395 05:59:06.255823 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9396 05:59:06.259302 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9397 05:59:06.266484 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9398 05:59:06.269254 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9399 05:59:06.272253 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9400 05:59:06.279324 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9401 05:59:06.282578 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9402 05:59:06.289339 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9403 05:59:06.292187 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9404 05:59:06.295559 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9405 05:59:06.302526 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9406 05:59:06.306056 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9407 05:59:06.312370 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9408 05:59:06.316086 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9409 05:59:06.319557 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9410 05:59:06.326288 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9411 05:59:06.328973 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9412 05:59:06.332113 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9413 05:59:06.339152 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9414 05:59:06.342427 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9415 05:59:06.348757 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9416 05:59:06.352351 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9417 05:59:06.355713 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9418 05:59:06.361964 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9419 05:59:06.365612 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9420 05:59:06.372551 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9421 05:59:06.375578 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9422 05:59:06.379121 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9423 05:59:06.385223 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9424 05:59:06.388580 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9425 05:59:06.395740 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9426 05:59:06.398808 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9427 05:59:06.401961 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9428 05:59:06.408779 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9429 05:59:06.411632 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9430 05:59:06.418467 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9431 05:59:06.421779 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9432 05:59:06.425166 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9433 05:59:06.431707 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9434 05:59:06.435111 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9435 05:59:06.441835 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9436 05:59:06.445231 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9437 05:59:06.448868 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9438 05:59:06.454708 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9439 05:59:06.457785 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9440 05:59:06.464478 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9441 05:59:06.467994 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9442 05:59:06.474289 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9443 05:59:06.477639 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9444 05:59:06.481261 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9445 05:59:06.487718 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9446 05:59:06.491298 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9447 05:59:06.497979 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9448 05:59:06.501296 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9449 05:59:06.504565 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9450 05:59:06.511324 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9451 05:59:06.514183 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9452 05:59:06.520866 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9453 05:59:06.524189 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9454 05:59:06.530624 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9455 05:59:06.534206 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9456 05:59:06.536966 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9457 05:59:06.544098 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9458 05:59:06.547208 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9459 05:59:06.553771 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9460 05:59:06.557067 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9461 05:59:06.563644 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9462 05:59:06.567452 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9463 05:59:06.570502 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9464 05:59:06.577187 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9465 05:59:06.580255 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9466 05:59:06.587436 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9467 05:59:06.590306 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9468 05:59:06.593508 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9469 05:59:06.600130 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9470 05:59:06.603924 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9471 05:59:06.610003 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9472 05:59:06.613700 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9473 05:59:06.620059 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9474 05:59:06.623401 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9475 05:59:06.626492 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9476 05:59:06.633197 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9477 05:59:06.636737 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9478 05:59:06.643485 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9479 05:59:06.646703 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9480 05:59:06.649955 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9481 05:59:06.653035 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9482 05:59:06.660120 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9483 05:59:06.663504 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9484 05:59:06.666527 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9485 05:59:06.672930 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9486 05:59:06.676654 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9487 05:59:06.679350 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9488 05:59:06.686143 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9489 05:59:06.689227 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9490 05:59:06.692766 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9491 05:59:06.699294 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9492 05:59:06.702758 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9493 05:59:06.709437 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9494 05:59:06.712769 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9495 05:59:06.715683 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9496 05:59:06.723043 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9497 05:59:06.725582 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9498 05:59:06.732753 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9499 05:59:06.735900 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9500 05:59:06.738872 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9501 05:59:06.745710 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9502 05:59:06.749295 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9503 05:59:06.752395 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9504 05:59:06.758672 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9505 05:59:06.762470 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9506 05:59:06.765711 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9507 05:59:06.772357 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9508 05:59:06.775469 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9509 05:59:06.778525 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9510 05:59:06.785172 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9511 05:59:06.788779 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9512 05:59:06.795185 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9513 05:59:06.798523 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9514 05:59:06.801795 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9515 05:59:06.808673 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9516 05:59:06.811697 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9517 05:59:06.818656 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9518 05:59:06.821838 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9519 05:59:06.825012 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9520 05:59:06.828103 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9521 05:59:06.834993 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9522 05:59:06.838174 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9523 05:59:06.841666 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9524 05:59:06.844948 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9525 05:59:06.851801 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9526 05:59:06.855098 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9527 05:59:06.858086 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9528 05:59:06.861534 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9529 05:59:06.868524 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9530 05:59:06.871736 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9531 05:59:06.874627 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9532 05:59:06.878058 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9533 05:59:06.884947 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9534 05:59:06.888302 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9535 05:59:06.894398 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9536 05:59:06.897584 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9537 05:59:06.904587 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9538 05:59:06.908069 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9539 05:59:06.914618 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9540 05:59:06.917448 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9541 05:59:06.920966 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9542 05:59:06.927614 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9543 05:59:06.931066 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9544 05:59:06.937569 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9545 05:59:06.940554 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9546 05:59:06.943915 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9547 05:59:06.950726 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9548 05:59:06.954038 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9549 05:59:06.960346 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9550 05:59:06.963628 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9551 05:59:06.966592 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9552 05:59:06.973492 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9553 05:59:06.976918 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9554 05:59:06.983684 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9555 05:59:06.986415 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9556 05:59:06.993283 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9557 05:59:06.996678 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9558 05:59:07.000007 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9559 05:59:07.006455 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9560 05:59:07.009610 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9561 05:59:07.016556 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9562 05:59:07.019712 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9563 05:59:07.025856 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9564 05:59:07.029594 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9565 05:59:07.032610 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9566 05:59:07.039258 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9567 05:59:07.042630 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9568 05:59:07.049299 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9569 05:59:07.052642 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9570 05:59:07.055967 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9571 05:59:07.062726 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9572 05:59:07.065642 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9573 05:59:07.072481 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9574 05:59:07.075559 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9575 05:59:07.078921 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9576 05:59:07.085308 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9577 05:59:07.089164 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9578 05:59:07.095499 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9579 05:59:07.099073 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9580 05:59:07.102535 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9581 05:59:07.109173 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9582 05:59:07.112273 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9583 05:59:07.119250 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9584 05:59:07.122845 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9585 05:59:07.129440 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9586 05:59:07.132438 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9587 05:59:07.135836 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9588 05:59:07.142426 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9589 05:59:07.145104 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9590 05:59:07.152066 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9591 05:59:07.155156 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9592 05:59:07.158607 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9593 05:59:07.165112 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9594 05:59:07.168582 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9595 05:59:07.174680 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9596 05:59:07.178225 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9597 05:59:07.181459 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9598 05:59:07.188309 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9599 05:59:07.191487 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9600 05:59:07.197785 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9601 05:59:07.201406 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9602 05:59:07.208281 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9603 05:59:07.211669 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9604 05:59:07.214874 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9605 05:59:07.221153 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9606 05:59:07.224875 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9607 05:59:07.231775 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9608 05:59:07.234371 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9609 05:59:07.241689 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9610 05:59:07.244516 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9611 05:59:07.251365 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9612 05:59:07.254558 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9613 05:59:07.257702 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9614 05:59:07.264219 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9615 05:59:07.267395 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9616 05:59:07.274178 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9617 05:59:07.277230 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9618 05:59:07.283728 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9619 05:59:07.287325 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9620 05:59:07.291043 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9621 05:59:07.296873 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9622 05:59:07.300546 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9623 05:59:07.307272 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9624 05:59:07.310145 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9625 05:59:07.316882 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9626 05:59:07.320008 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9627 05:59:07.326987 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9628 05:59:07.329727 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9629 05:59:07.336928 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9630 05:59:07.339759 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9631 05:59:07.343209 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9632 05:59:07.350057 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9633 05:59:07.353368 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9634 05:59:07.359987 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9635 05:59:07.363576 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9636 05:59:07.369513 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9637 05:59:07.372813 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9638 05:59:07.379627 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9639 05:59:07.382830 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9640 05:59:07.385987 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9641 05:59:07.392975 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9642 05:59:07.396149 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9643 05:59:07.402780 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9644 05:59:07.405833 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9645 05:59:07.412741 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9646 05:59:07.416113 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9647 05:59:07.419351 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9648 05:59:07.425744 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9649 05:59:07.429619 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9650 05:59:07.435661 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9651 05:59:07.438811 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9652 05:59:07.446152 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9653 05:59:07.449419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9654 05:59:07.452560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9655 05:59:07.459056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9656 05:59:07.462356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9657 05:59:07.468677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9658 05:59:07.472215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9659 05:59:07.478676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9660 05:59:07.481931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9661 05:59:07.488909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9662 05:59:07.492334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9663 05:59:07.498480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9664 05:59:07.501716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9665 05:59:07.508815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9666 05:59:07.511513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9667 05:59:07.518491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9668 05:59:07.521362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9669 05:59:07.528192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9670 05:59:07.531345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9671 05:59:07.537855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9672 05:59:07.541174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9673 05:59:07.547944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9674 05:59:07.550952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9675 05:59:07.557912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9676 05:59:07.561060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9677 05:59:07.567966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9678 05:59:07.571345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9679 05:59:07.577687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9680 05:59:07.581176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9681 05:59:07.587700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9682 05:59:07.591248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9683 05:59:07.597643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9684 05:59:07.600938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9685 05:59:07.607193 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9686 05:59:07.607608 INFO: [APUAPC] vio 0
9687 05:59:07.613834 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9688 05:59:07.617243 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9689 05:59:07.620795 INFO: [APUAPC] D0_APC_0: 0x400510
9690 05:59:07.623980 INFO: [APUAPC] D0_APC_1: 0x0
9691 05:59:07.627203 INFO: [APUAPC] D0_APC_2: 0x1540
9692 05:59:07.630633 INFO: [APUAPC] D0_APC_3: 0x0
9693 05:59:07.633513 INFO: [APUAPC] D1_APC_0: 0xffffffff
9694 05:59:07.637108 INFO: [APUAPC] D1_APC_1: 0xffffffff
9695 05:59:07.641105 INFO: [APUAPC] D1_APC_2: 0x3fffff
9696 05:59:07.643665 INFO: [APUAPC] D1_APC_3: 0x0
9697 05:59:07.646867 INFO: [APUAPC] D2_APC_0: 0xffffffff
9698 05:59:07.650384 INFO: [APUAPC] D2_APC_1: 0xffffffff
9699 05:59:07.654251 INFO: [APUAPC] D2_APC_2: 0x3fffff
9700 05:59:07.657214 INFO: [APUAPC] D2_APC_3: 0x0
9701 05:59:07.660455 INFO: [APUAPC] D3_APC_0: 0xffffffff
9702 05:59:07.663483 INFO: [APUAPC] D3_APC_1: 0xffffffff
9703 05:59:07.667082 INFO: [APUAPC] D3_APC_2: 0x3fffff
9704 05:59:07.670249 INFO: [APUAPC] D3_APC_3: 0x0
9705 05:59:07.673389 INFO: [APUAPC] D4_APC_0: 0xffffffff
9706 05:59:07.676661 INFO: [APUAPC] D4_APC_1: 0xffffffff
9707 05:59:07.679990 INFO: [APUAPC] D4_APC_2: 0x3fffff
9708 05:59:07.683744 INFO: [APUAPC] D4_APC_3: 0x0
9709 05:59:07.687198 INFO: [APUAPC] D5_APC_0: 0xffffffff
9710 05:59:07.690048 INFO: [APUAPC] D5_APC_1: 0xffffffff
9711 05:59:07.693374 INFO: [APUAPC] D5_APC_2: 0x3fffff
9712 05:59:07.696183 INFO: [APUAPC] D5_APC_3: 0x0
9713 05:59:07.699919 INFO: [APUAPC] D6_APC_0: 0xffffffff
9714 05:59:07.703158 INFO: [APUAPC] D6_APC_1: 0xffffffff
9715 05:59:07.706343 INFO: [APUAPC] D6_APC_2: 0x3fffff
9716 05:59:07.706864 INFO: [APUAPC] D6_APC_3: 0x0
9717 05:59:07.713079 INFO: [APUAPC] D7_APC_0: 0xffffffff
9718 05:59:07.716359 INFO: [APUAPC] D7_APC_1: 0xffffffff
9719 05:59:07.719894 INFO: [APUAPC] D7_APC_2: 0x3fffff
9720 05:59:07.720490 INFO: [APUAPC] D7_APC_3: 0x0
9721 05:59:07.722834 INFO: [APUAPC] D8_APC_0: 0xffffffff
9722 05:59:07.729560 INFO: [APUAPC] D8_APC_1: 0xffffffff
9723 05:59:07.732642 INFO: [APUAPC] D8_APC_2: 0x3fffff
9724 05:59:07.733135 INFO: [APUAPC] D8_APC_3: 0x0
9725 05:59:07.735799 INFO: [APUAPC] D9_APC_0: 0xffffffff
9726 05:59:07.739271 INFO: [APUAPC] D9_APC_1: 0xffffffff
9727 05:59:07.742512 INFO: [APUAPC] D9_APC_2: 0x3fffff
9728 05:59:07.745564 INFO: [APUAPC] D9_APC_3: 0x0
9729 05:59:07.749181 INFO: [APUAPC] D10_APC_0: 0xffffffff
9730 05:59:07.752517 INFO: [APUAPC] D10_APC_1: 0xffffffff
9731 05:59:07.756164 INFO: [APUAPC] D10_APC_2: 0x3fffff
9732 05:59:07.759183 INFO: [APUAPC] D10_APC_3: 0x0
9733 05:59:07.762483 INFO: [APUAPC] D11_APC_0: 0xffffffff
9734 05:59:07.765884 INFO: [APUAPC] D11_APC_1: 0xffffffff
9735 05:59:07.769073 INFO: [APUAPC] D11_APC_2: 0x3fffff
9736 05:59:07.772560 INFO: [APUAPC] D11_APC_3: 0x0
9737 05:59:07.776025 INFO: [APUAPC] D12_APC_0: 0xffffffff
9738 05:59:07.782772 INFO: [APUAPC] D12_APC_1: 0xffffffff
9739 05:59:07.785451 INFO: [APUAPC] D12_APC_2: 0x3fffff
9740 05:59:07.785909 INFO: [APUAPC] D12_APC_3: 0x0
9741 05:59:07.788608 INFO: [APUAPC] D13_APC_0: 0xffffffff
9742 05:59:07.795771 INFO: [APUAPC] D13_APC_1: 0xffffffff
9743 05:59:07.799018 INFO: [APUAPC] D13_APC_2: 0x3fffff
9744 05:59:07.799606 INFO: [APUAPC] D13_APC_3: 0x0
9745 05:59:07.805721 INFO: [APUAPC] D14_APC_0: 0xffffffff
9746 05:59:07.808678 INFO: [APUAPC] D14_APC_1: 0xffffffff
9747 05:59:07.812189 INFO: [APUAPC] D14_APC_2: 0x3fffff
9748 05:59:07.812785 INFO: [APUAPC] D14_APC_3: 0x0
9749 05:59:07.818801 INFO: [APUAPC] D15_APC_0: 0xffffffff
9750 05:59:07.821964 INFO: [APUAPC] D15_APC_1: 0xffffffff
9751 05:59:07.825462 INFO: [APUAPC] D15_APC_2: 0x3fffff
9752 05:59:07.828403 INFO: [APUAPC] D15_APC_3: 0x0
9753 05:59:07.828895 INFO: [APUAPC] APC_CON: 0x4
9754 05:59:07.832167 INFO: [NOCDAPC] D0_APC_0: 0x0
9755 05:59:07.835001 INFO: [NOCDAPC] D0_APC_1: 0x0
9756 05:59:07.838314 INFO: [NOCDAPC] D1_APC_0: 0x0
9757 05:59:07.841640 INFO: [NOCDAPC] D1_APC_1: 0xfff
9758 05:59:07.844824 INFO: [NOCDAPC] D2_APC_0: 0x0
9759 05:59:07.848505 INFO: [NOCDAPC] D2_APC_1: 0xfff
9760 05:59:07.851747 INFO: [NOCDAPC] D3_APC_0: 0x0
9761 05:59:07.854902 INFO: [NOCDAPC] D3_APC_1: 0xfff
9762 05:59:07.858298 INFO: [NOCDAPC] D4_APC_0: 0x0
9763 05:59:07.858759 INFO: [NOCDAPC] D4_APC_1: 0xfff
9764 05:59:07.861628 INFO: [NOCDAPC] D5_APC_0: 0x0
9765 05:59:07.865117 INFO: [NOCDAPC] D5_APC_1: 0xfff
9766 05:59:07.868241 INFO: [NOCDAPC] D6_APC_0: 0x0
9767 05:59:07.871416 INFO: [NOCDAPC] D6_APC_1: 0xfff
9768 05:59:07.874666 INFO: [NOCDAPC] D7_APC_0: 0x0
9769 05:59:07.878265 INFO: [NOCDAPC] D7_APC_1: 0xfff
9770 05:59:07.881045 INFO: [NOCDAPC] D8_APC_0: 0x0
9771 05:59:07.884767 INFO: [NOCDAPC] D8_APC_1: 0xfff
9772 05:59:07.888101 INFO: [NOCDAPC] D9_APC_0: 0x0
9773 05:59:07.891270 INFO: [NOCDAPC] D9_APC_1: 0xfff
9774 05:59:07.894461 INFO: [NOCDAPC] D10_APC_0: 0x0
9775 05:59:07.894787 INFO: [NOCDAPC] D10_APC_1: 0xfff
9776 05:59:07.897614 INFO: [NOCDAPC] D11_APC_0: 0x0
9777 05:59:07.901359 INFO: [NOCDAPC] D11_APC_1: 0xfff
9778 05:59:07.904656 INFO: [NOCDAPC] D12_APC_0: 0x0
9779 05:59:07.907876 INFO: [NOCDAPC] D12_APC_1: 0xfff
9780 05:59:07.911110 INFO: [NOCDAPC] D13_APC_0: 0x0
9781 05:59:07.914126 INFO: [NOCDAPC] D13_APC_1: 0xfff
9782 05:59:07.917968 INFO: [NOCDAPC] D14_APC_0: 0x0
9783 05:59:07.921371 INFO: [NOCDAPC] D14_APC_1: 0xfff
9784 05:59:07.924414 INFO: [NOCDAPC] D15_APC_0: 0x0
9785 05:59:07.927445 INFO: [NOCDAPC] D15_APC_1: 0xfff
9786 05:59:07.930978 INFO: [NOCDAPC] APC_CON: 0x4
9787 05:59:07.934153 INFO: [APUAPC] set_apusys_apc done
9788 05:59:07.937900 INFO: [DEVAPC] devapc_init done
9789 05:59:07.940896 INFO: GICv3 without legacy support detected.
9790 05:59:07.944221 INFO: ARM GICv3 driver initialized in EL3
9791 05:59:07.947479 INFO: Maximum SPI INTID supported: 639
9792 05:59:07.953841 INFO: BL31: Initializing runtime services
9793 05:59:07.957451 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9794 05:59:07.960742 INFO: SPM: enable CPC mode
9795 05:59:07.967204 INFO: mcdi ready for mcusys-off-idle and system suspend
9796 05:59:07.970586 INFO: BL31: Preparing for EL3 exit to normal world
9797 05:59:07.973744 INFO: Entry point address = 0x80000000
9798 05:59:07.977095 INFO: SPSR = 0x8
9799 05:59:07.982360
9800 05:59:07.982847
9801 05:59:07.983213
9802 05:59:07.985431 Starting depthcharge on Spherion...
9803 05:59:07.985891
9804 05:59:07.986448 Wipe memory regions:
9805 05:59:07.986819
9806 05:59:07.989569 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9807 05:59:07.990136 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9808 05:59:07.990581 Setting prompt string to ['asurada:']
9809 05:59:07.991012 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9810 05:59:07.991734 [0x00000040000000, 0x00000054600000)
9811 05:59:08.111326
9812 05:59:08.111910 [0x00000054660000, 0x00000080000000)
9813 05:59:08.371271
9814 05:59:08.371833 [0x000000821a7280, 0x000000ffe64000)
9815 05:59:09.115739
9816 05:59:09.116293 [0x00000100000000, 0x00000140000000)
9817 05:59:09.495560
9818 05:59:09.498940 Initializing XHCI USB controller at 0x11200000.
9819 05:59:10.536431
9820 05:59:10.540323 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9821 05:59:10.540831
9822 05:59:10.541198
9823 05:59:10.541527
9824 05:59:10.542339 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9826 05:59:10.643608 asurada: tftpboot 192.168.201.1 12379454/tftp-deploy-batrup0z/kernel/image.itb 12379454/tftp-deploy-batrup0z/kernel/cmdline
9827 05:59:10.644363 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9828 05:59:10.644939 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9829 05:59:10.649156 tftpboot 192.168.201.1 12379454/tftp-deploy-batrup0z/kernel/image.ittp-deploy-batrup0z/kernel/cmdline
9830 05:59:10.649623
9831 05:59:10.649979 Waiting for link
9832 05:59:10.810064
9833 05:59:10.810625 R8152: Initializing
9834 05:59:10.810986
9835 05:59:10.812866 Version 9 (ocp_data = 6010)
9836 05:59:10.813324
9837 05:59:10.816460 R8152: Done initializing
9838 05:59:10.817078
9839 05:59:10.817625 Adding net device
9840 05:59:12.823986
9841 05:59:12.824548 done.
9842 05:59:12.824975
9843 05:59:12.825320 MAC: 00:e0:4c:68:03:bd
9844 05:59:12.825641
9845 05:59:12.826924 Sending DHCP discover... done.
9846 05:59:12.827375
9847 05:59:22.553614 Waiting for reply... R8152: Bulk read error 0xffffffbf
9848 05:59:22.554219
9849 05:59:22.556380 Receive failed.
9850 05:59:22.556890
9851 05:59:22.557284 done.
9852 05:59:22.557724
9853 05:59:22.559881 Sending DHCP request... done.
9854 05:59:22.560359
9855 05:59:22.563022 Waiting for reply... done.
9856 05:59:22.563475
9857 05:59:22.566933 My ip is 192.168.201.16
9858 05:59:22.567498
9859 05:59:22.569856 The DHCP server ip is 192.168.201.1
9860 05:59:22.570312
9861 05:59:22.572820 TFTP server IP predefined by user: 192.168.201.1
9862 05:59:22.573276
9863 05:59:22.579813 Bootfile predefined by user: 12379454/tftp-deploy-batrup0z/kernel/image.itb
9864 05:59:22.580370
9865 05:59:22.583011 Sending tftp read request... done.
9866 05:59:22.583555
9867 05:59:22.590698 Waiting for the transfer...
9868 05:59:22.591205
9869 05:59:22.908565 00000000 ################################################################
9870 05:59:22.908714
9871 05:59:23.193526 00080000 ################################################################
9872 05:59:23.193669
9873 05:59:23.488729 00100000 ################################################################
9874 05:59:23.488872
9875 05:59:23.776988 00180000 ################################################################
9876 05:59:23.777130
9877 05:59:24.072114 00200000 ################################################################
9878 05:59:24.072251
9879 05:59:24.379104 00280000 ################################################################
9880 05:59:24.379756
9881 05:59:24.798368 00300000 ################################################################
9882 05:59:24.798540
9883 05:59:25.080266 00380000 ################################################################
9884 05:59:25.080400
9885 05:59:25.418255 00400000 ################################################################
9886 05:59:25.418869
9887 05:59:25.804468 00480000 ################################################################
9888 05:59:25.805166
9889 05:59:26.183363 00500000 ################################################################
9890 05:59:26.184083
9891 05:59:26.577832 00580000 ################################################################
9892 05:59:26.578354
9893 05:59:26.877917 00600000 ################################################################
9894 05:59:26.878062
9895 05:59:27.167744 00680000 ################################################################
9896 05:59:27.167885
9897 05:59:27.451872 00700000 ################################################################
9898 05:59:27.452015
9899 05:59:27.752083 00780000 ################################################################
9900 05:59:27.752228
9901 05:59:28.049888 00800000 ################################################################
9902 05:59:28.050037
9903 05:59:28.340032 00880000 ################################################################
9904 05:59:28.340167
9905 05:59:28.641648 00900000 ################################################################
9906 05:59:28.641796
9907 05:59:28.940992 00980000 ################################################################
9908 05:59:28.941134
9909 05:59:29.241205 00a00000 ################################################################
9910 05:59:29.241348
9911 05:59:29.540345 00a80000 ################################################################
9912 05:59:29.540480
9913 05:59:29.828253 00b00000 ################################################################
9914 05:59:29.828385
9915 05:59:30.128381 00b80000 ################################################################
9916 05:59:30.128522
9917 05:59:30.419604 00c00000 ################################################################
9918 05:59:30.419741
9919 05:59:30.721529 00c80000 ################################################################
9920 05:59:30.721676
9921 05:59:31.022233 00d00000 ################################################################
9922 05:59:31.022372
9923 05:59:31.324434 00d80000 ################################################################
9924 05:59:31.324579
9925 05:59:31.624993 00e00000 ################################################################
9926 05:59:31.625146
9927 05:59:31.926902 00e80000 ################################################################
9928 05:59:31.927046
9929 05:59:32.227586 00f00000 ################################################################
9930 05:59:32.227723
9931 05:59:32.519852 00f80000 ################################################################
9932 05:59:32.520000
9933 05:59:32.810767 01000000 ################################################################
9934 05:59:32.810910
9935 05:59:33.122184 01080000 ################################################################
9936 05:59:33.122325
9937 05:59:33.390622 01100000 ################################################################
9938 05:59:33.390761
9939 05:59:33.669824 01180000 ################################################################
9940 05:59:33.669969
9941 05:59:33.958150 01200000 ################################################################
9942 05:59:33.958291
9943 05:59:34.254219 01280000 ################################################################
9944 05:59:34.254361
9945 05:59:34.542688 01300000 ################################################################
9946 05:59:34.542824
9947 05:59:34.818919 01380000 ################################################################
9948 05:59:34.819061
9949 05:59:35.119383 01400000 ################################################################
9950 05:59:35.119543
9951 05:59:35.421140 01480000 ################################################################
9952 05:59:35.421280
9953 05:59:35.719827 01500000 ################################################################
9954 05:59:35.719973
9955 05:59:36.004907 01580000 ################################################################
9956 05:59:36.005074
9957 05:59:36.307689 01600000 ################################################################
9958 05:59:36.307840
9959 05:59:36.606162 01680000 ################################################################
9960 05:59:36.606303
9961 05:59:36.904539 01700000 ################################################################
9962 05:59:36.904711
9963 05:59:37.204911 01780000 ################################################################
9964 05:59:37.205048
9965 05:59:37.506885 01800000 ################################################################
9966 05:59:37.507023
9967 05:59:37.803683 01880000 ################################################################
9968 05:59:37.803822
9969 05:59:38.102807 01900000 ################################################################
9970 05:59:38.102964
9971 05:59:38.401924 01980000 ################################################################
9972 05:59:38.402061
9973 05:59:38.698252 01a00000 ################################################################
9974 05:59:38.698392
9975 05:59:38.997820 01a80000 ################################################################
9976 05:59:38.997950
9977 05:59:39.268815 01b00000 ################################################################
9978 05:59:39.268953
9979 05:59:39.508371 01b80000 ############################################################# done.
9980 05:59:39.508507
9981 05:59:39.511660 The bootfile was 29328558 bytes long.
9982 05:59:39.511748
9983 05:59:39.515260 Sending tftp read request... done.
9984 05:59:39.515708
9985 05:59:39.518579 Waiting for the transfer...
9986 05:59:39.518994
9987 05:59:39.519314 00000000 # done.
9988 05:59:39.519622
9989 05:59:39.528533 Command line loaded dynamically from TFTP file: 12379454/tftp-deploy-batrup0z/kernel/cmdline
9990 05:59:39.528997
9991 05:59:39.548671 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12379454/extract-nfsrootfs-ytmy4fkh,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9992 05:59:39.549267
9993 05:59:39.549630 Loading FIT.
9994 05:59:39.551760
9995 05:59:39.552214 Image ramdisk-1 has 17797414 bytes.
9996 05:59:39.554802
9997 05:59:39.555257 Image fdt-1 has 47278 bytes.
9998 05:59:39.555616
9999 05:59:39.558621 Image kernel-1 has 11481830 bytes.
10000 05:59:39.559183
10001 05:59:39.568769 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10002 05:59:39.569335
10003 05:59:39.584870 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10004 05:59:39.585434
10005 05:59:39.591358 Choosing best match conf-1 for compat google,spherion-rev3.
10006 05:59:39.595115
10007 05:59:39.599587 Connected to device vid:did:rid of 1ae0:0028:00
10008 05:59:39.607164
10009 05:59:39.609705 tpm_get_response: command 0x17b, return code 0x0
10010 05:59:39.610163
10011 05:59:39.612896 ec_init: CrosEC protocol v3 supported (256, 248)
10012 05:59:39.617727
10013 05:59:39.620399 tpm_cleanup: add release locality here.
10014 05:59:39.620910
10015 05:59:39.621273 Shutting down all USB controllers.
10016 05:59:39.623553
10017 05:59:39.624001 Removing current net device
10018 05:59:39.624357
10019 05:59:39.630628 Exiting depthcharge with code 4 at timestamp: 59862508
10020 05:59:39.631377
10021 05:59:39.633558 LZMA decompressing kernel-1 to 0x821a6718
10022 05:59:39.633953
10023 05:59:39.637231 LZMA decompressing kernel-1 to 0x40000000
10024 05:59:41.073329
10025 05:59:41.073885 jumping to kernel
10026 05:59:41.076056 end: 2.2.4 bootloader-commands (duration 00:00:33) [common]
10027 05:59:41.076573 start: 2.2.5 auto-login-action (timeout 00:03:53) [common]
10028 05:59:41.077013 Setting prompt string to ['Linux version [0-9]']
10029 05:59:41.077380 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10030 05:59:41.077747 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10031 05:59:41.124438
10032 05:59:41.127971 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10033 05:59:41.131405 start: 2.2.5.1 login-action (timeout 00:03:53) [common]
10034 05:59:41.131976 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10035 05:59:41.132436 Setting prompt string to []
10036 05:59:41.132887 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10037 05:59:41.133272 Using line separator: #'\n'#
10038 05:59:41.133648 No login prompt set.
10039 05:59:41.133994 Parsing kernel messages
10040 05:59:41.134363 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10041 05:59:41.134923 [login-action] Waiting for messages, (timeout 00:03:53)
10042 05:59:41.150744 [ 0.000000] Linux version 6.1.67-cip12 (KernelCI@build-j59664-arm64-gcc-10-defconfig-arm64-chromebook-fgc24) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023
10043 05:59:41.154101 [ 0.000000] random: crng init done
10044 05:59:41.160827 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10045 05:59:41.164054 [ 0.000000] efi: UEFI not found.
10046 05:59:41.170900 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10047 05:59:41.176801 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10048 05:59:41.187039 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10049 05:59:41.196825 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10050 05:59:41.203681 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10051 05:59:41.210067 [ 0.000000] printk: bootconsole [mtk8250] enabled
10052 05:59:41.216848 [ 0.000000] NUMA: No NUMA configuration found
10053 05:59:41.223195 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10054 05:59:41.226661 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d2a00-0x13f7d4fff]
10055 05:59:41.229999 [ 0.000000] Zone ranges:
10056 05:59:41.236868 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10057 05:59:41.240104 [ 0.000000] DMA32 empty
10058 05:59:41.246545 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10059 05:59:41.249932 [ 0.000000] Movable zone start for each node
10060 05:59:41.253191 [ 0.000000] Early memory node ranges
10061 05:59:41.259643 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10062 05:59:41.266158 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10063 05:59:41.272693 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10064 05:59:41.279440 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10065 05:59:41.286081 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10066 05:59:41.292416 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10067 05:59:41.322888 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10068 05:59:41.329327 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10069 05:59:41.336290 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10070 05:59:41.339332 [ 0.000000] psci: probing for conduit method from DT.
10071 05:59:41.346563 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10072 05:59:41.349657 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10073 05:59:41.356082 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10074 05:59:41.359021 [ 0.000000] psci: SMC Calling Convention v1.2
10075 05:59:41.365838 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10076 05:59:41.369043 [ 0.000000] Detected VIPT I-cache on CPU0
10077 05:59:41.376179 [ 0.000000] CPU features: detected: GIC system register CPU interface
10078 05:59:41.382248 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10079 05:59:41.388602 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10080 05:59:41.395461 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10081 05:59:41.405162 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10082 05:59:41.411938 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10083 05:59:41.415310 [ 0.000000] alternatives: applying boot alternatives
10084 05:59:41.422374 [ 0.000000] Fallback order for Node 0: 0
10085 05:59:41.428920 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10086 05:59:41.432094 [ 0.000000] Policy zone: Normal
10087 05:59:41.455064 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12379454/extract-nfsrootfs-ytmy4fkh,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10088 05:59:41.464849 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10089 05:59:41.474834 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10090 05:59:41.481444 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10091 05:59:41.487916 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10092 05:59:41.494088 <6>[ 0.000000] software IO TLB: area num 8.
10093 05:59:41.549817 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10094 05:59:41.629950 <6>[ 0.000000] Memory: 3836924K/4191232K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 321540K reserved, 32768K cma-reserved)
10095 05:59:41.636882 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10096 05:59:41.643776 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10097 05:59:41.646775 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10098 05:59:41.653056 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10099 05:59:41.660098 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10100 05:59:41.663068 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10101 05:59:41.672857 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10102 05:59:41.679542 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10103 05:59:41.686180 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10104 05:59:41.693043 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10105 05:59:41.696061 <6>[ 0.000000] GICv3: 608 SPIs implemented
10106 05:59:41.699158 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10107 05:59:41.705745 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10108 05:59:41.708894 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10109 05:59:41.715944 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10110 05:59:41.729028 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10111 05:59:41.742596 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10112 05:59:41.748421 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10113 05:59:41.756873 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10114 05:59:41.770189 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10115 05:59:41.776628 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10116 05:59:41.782847 <6>[ 0.009179] Console: colour dummy device 80x25
10117 05:59:41.793145 <6>[ 0.013935] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10118 05:59:41.799424 <6>[ 0.024376] pid_max: default: 32768 minimum: 301
10119 05:59:41.802870 <6>[ 0.029246] LSM: Security Framework initializing
10120 05:59:41.809994 <6>[ 0.034159] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10121 05:59:41.819911 <6>[ 0.041813] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10122 05:59:41.826307 <6>[ 0.051099] cblist_init_generic: Setting adjustable number of callback queues.
10123 05:59:41.832860 <6>[ 0.058541] cblist_init_generic: Setting shift to 3 and lim to 1.
10124 05:59:41.842971 <6>[ 0.064917] cblist_init_generic: Setting adjustable number of callback queues.
10125 05:59:41.845856 <6>[ 0.072343] cblist_init_generic: Setting shift to 3 and lim to 1.
10126 05:59:41.852498 <6>[ 0.078743] rcu: Hierarchical SRCU implementation.
10127 05:59:41.859571 <6>[ 0.083758] rcu: Max phase no-delay instances is 1000.
10128 05:59:41.865915 <6>[ 0.090780] EFI services will not be available.
10129 05:59:41.869202 <6>[ 0.095733] smp: Bringing up secondary CPUs ...
10130 05:59:41.877043 <6>[ 0.100777] Detected VIPT I-cache on CPU1
10131 05:59:41.884023 <6>[ 0.100847] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10132 05:59:41.889944 <6>[ 0.100877] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10133 05:59:41.893405 <6>[ 0.101202] Detected VIPT I-cache on CPU2
10134 05:59:41.900533 <6>[ 0.101251] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10135 05:59:41.910264 <6>[ 0.101267] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10136 05:59:41.913357 <6>[ 0.101521] Detected VIPT I-cache on CPU3
10137 05:59:41.919876 <6>[ 0.101566] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10138 05:59:41.926612 <6>[ 0.101580] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10139 05:59:41.929985 <6>[ 0.101880] CPU features: detected: Spectre-v4
10140 05:59:41.936778 <6>[ 0.101886] CPU features: detected: Spectre-BHB
10141 05:59:41.939939 <6>[ 0.101891] Detected PIPT I-cache on CPU4
10142 05:59:41.946296 <6>[ 0.101948] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10143 05:59:41.953074 <6>[ 0.101964] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10144 05:59:41.959766 <6>[ 0.102253] Detected PIPT I-cache on CPU5
10145 05:59:41.966371 <6>[ 0.102314] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10146 05:59:41.973544 <6>[ 0.102331] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10147 05:59:41.976446 <6>[ 0.102609] Detected PIPT I-cache on CPU6
10148 05:59:41.982717 <6>[ 0.102671] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10149 05:59:41.989422 <6>[ 0.102687] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10150 05:59:41.995760 <6>[ 0.102985] Detected PIPT I-cache on CPU7
10151 05:59:42.002637 <6>[ 0.103049] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10152 05:59:42.009190 <6>[ 0.103065] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10153 05:59:42.012478 <6>[ 0.103112] smp: Brought up 1 node, 8 CPUs
10154 05:59:42.019234 <6>[ 0.244467] SMP: Total of 8 processors activated.
10155 05:59:42.022205 <6>[ 0.249419] CPU features: detected: 32-bit EL0 Support
10156 05:59:42.031996 <6>[ 0.254781] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10157 05:59:42.038718 <6>[ 0.263582] CPU features: detected: Common not Private translations
10158 05:59:42.045314 <6>[ 0.270098] CPU features: detected: CRC32 instructions
10159 05:59:42.051674 <6>[ 0.275483] CPU features: detected: RCpc load-acquire (LDAPR)
10160 05:59:42.054957 <6>[ 0.281443] CPU features: detected: LSE atomic instructions
10161 05:59:42.061844 <6>[ 0.287225] CPU features: detected: Privileged Access Never
10162 05:59:42.068384 <6>[ 0.293005] CPU features: detected: RAS Extension Support
10163 05:59:42.075041 <6>[ 0.298614] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10164 05:59:42.078342 <6>[ 0.305833] CPU: All CPU(s) started at EL2
10165 05:59:42.085100 <6>[ 0.310149] alternatives: applying system-wide alternatives
10166 05:59:42.093803 <6>[ 0.320095] devtmpfs: initialized
10167 05:59:42.108760 <6>[ 0.328318] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10168 05:59:42.115445 <6>[ 0.338276] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10169 05:59:42.121803 <6>[ 0.346502] pinctrl core: initialized pinctrl subsystem
10170 05:59:42.124931 <6>[ 0.353176] DMI not present or invalid.
10171 05:59:42.132300 <6>[ 0.357575] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10172 05:59:42.141563 <6>[ 0.364434] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10173 05:59:42.148181 <6>[ 0.371881] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10174 05:59:42.157868 <6>[ 0.379972] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10175 05:59:42.161266 <6>[ 0.388127] audit: initializing netlink subsys (disabled)
10176 05:59:42.170833 <5>[ 0.393822] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10177 05:59:42.177438 <6>[ 0.394522] thermal_sys: Registered thermal governor 'step_wise'
10178 05:59:42.183928 <6>[ 0.401788] thermal_sys: Registered thermal governor 'power_allocator'
10179 05:59:42.187144 <6>[ 0.408039] cpuidle: using governor menu
10180 05:59:42.193987 <6>[ 0.418995] NET: Registered PF_QIPCRTR protocol family
10181 05:59:42.200389 <6>[ 0.424478] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10182 05:59:42.207056 <6>[ 0.431579] ASID allocator initialised with 32768 entries
10183 05:59:42.210419 <6>[ 0.438125] Serial: AMBA PL011 UART driver
10184 05:59:42.219800 <4>[ 0.446830] Trying to register duplicate clock ID: 134
10185 05:59:42.275238 <6>[ 0.504634] KASLR enabled
10186 05:59:42.288953 <6>[ 0.512340] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10187 05:59:42.295859 <6>[ 0.519349] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10188 05:59:42.302424 <6>[ 0.525836] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10189 05:59:42.309186 <6>[ 0.532841] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10190 05:59:42.315626 <6>[ 0.539327] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10191 05:59:42.322733 <6>[ 0.546334] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10192 05:59:42.329390 <6>[ 0.552820] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10193 05:59:42.335631 <6>[ 0.559825] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10194 05:59:42.338908 <6>[ 0.567320] ACPI: Interpreter disabled.
10195 05:59:42.347863 <6>[ 0.573705] iommu: Default domain type: Translated
10196 05:59:42.353996 <6>[ 0.578816] iommu: DMA domain TLB invalidation policy: strict mode
10197 05:59:42.357340 <5>[ 0.585474] SCSI subsystem initialized
10198 05:59:42.363895 <6>[ 0.589632] usbcore: registered new interface driver usbfs
10199 05:59:42.370764 <6>[ 0.595361] usbcore: registered new interface driver hub
10200 05:59:42.373950 <6>[ 0.600914] usbcore: registered new device driver usb
10201 05:59:42.380942 <6>[ 0.607000] pps_core: LinuxPPS API ver. 1 registered
10202 05:59:42.390907 <6>[ 0.612195] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10203 05:59:42.394021 <6>[ 0.621542] PTP clock support registered
10204 05:59:42.397033 <6>[ 0.625782] EDAC MC: Ver: 3.0.0
10205 05:59:42.404673 <6>[ 0.630918] FPGA manager framework
10206 05:59:42.407927 <6>[ 0.634595] Advanced Linux Sound Architecture Driver Initialized.
10207 05:59:42.412053 <6>[ 0.641360] vgaarb: loaded
10208 05:59:42.418767 <6>[ 0.644479] clocksource: Switched to clocksource arch_sys_counter
10209 05:59:42.425353 <5>[ 0.650908] VFS: Disk quotas dquot_6.6.0
10210 05:59:42.431881 <6>[ 0.655094] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10211 05:59:42.434823 <6>[ 0.662280] pnp: PnP ACPI: disabled
10212 05:59:42.442946 <6>[ 0.668943] NET: Registered PF_INET protocol family
10213 05:59:42.449197 <6>[ 0.674308] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10214 05:59:42.461687 <6>[ 0.684298] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10215 05:59:42.471257 <6>[ 0.693087] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10216 05:59:42.477757 <6>[ 0.701056] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10217 05:59:42.484673 <6>[ 0.709456] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10218 05:59:42.495155 <6>[ 0.718114] TCP: Hash tables configured (established 32768 bind 32768)
10219 05:59:42.501865 <6>[ 0.724956] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10220 05:59:42.508519 <6>[ 0.731973] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10221 05:59:42.515118 <6>[ 0.739482] NET: Registered PF_UNIX/PF_LOCAL protocol family
10222 05:59:42.521282 <6>[ 0.745607] RPC: Registered named UNIX socket transport module.
10223 05:59:42.524824 <6>[ 0.751762] RPC: Registered udp transport module.
10224 05:59:42.531250 <6>[ 0.756697] RPC: Registered tcp transport module.
10225 05:59:42.538165 <6>[ 0.761627] RPC: Registered tcp NFSv4.1 backchannel transport module.
10226 05:59:42.541199 <6>[ 0.768294] PCI: CLS 0 bytes, default 64
10227 05:59:42.545092 <6>[ 0.772646] Unpacking initramfs...
10228 05:59:42.574169 <6>[ 0.797135] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10229 05:59:42.584064 <6>[ 0.805791] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10230 05:59:42.587716 <6>[ 0.814633] kvm [1]: IPA Size Limit: 40 bits
10231 05:59:42.593756 <6>[ 0.819161] kvm [1]: GICv3: no GICV resource entry
10232 05:59:42.597110 <6>[ 0.824181] kvm [1]: disabling GICv2 emulation
10233 05:59:42.603678 <6>[ 0.828870] kvm [1]: GIC system register CPU interface enabled
10234 05:59:42.607466 <6>[ 0.835016] kvm [1]: vgic interrupt IRQ18
10235 05:59:42.613562 <6>[ 0.839368] kvm [1]: VHE mode initialized successfully
10236 05:59:42.620800 <5>[ 0.845642] Initialise system trusted keyrings
10237 05:59:42.627155 <6>[ 0.850440] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10238 05:59:42.634160 <6>[ 0.860441] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10239 05:59:42.640916 <5>[ 0.866828] NFS: Registering the id_resolver key type
10240 05:59:42.643919 <5>[ 0.872134] Key type id_resolver registered
10241 05:59:42.650672 <5>[ 0.876548] Key type id_legacy registered
10242 05:59:42.657488 <6>[ 0.880826] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10243 05:59:42.664172 <6>[ 0.887745] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10244 05:59:42.670474 <6>[ 0.895447] 9p: Installing v9fs 9p2000 file system support
10245 05:59:42.707603 <5>[ 0.933460] Key type asymmetric registered
10246 05:59:42.710866 <5>[ 0.937793] Asymmetric key parser 'x509' registered
10247 05:59:42.721362 <6>[ 0.942956] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10248 05:59:42.723827 <6>[ 0.950574] io scheduler mq-deadline registered
10249 05:59:42.727541 <6>[ 0.955335] io scheduler kyber registered
10250 05:59:42.746364 <6>[ 0.972259] EINJ: ACPI disabled.
10251 05:59:42.778069 <4>[ 0.997283] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10252 05:59:42.787699 <4>[ 1.007919] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10253 05:59:42.802450 <6>[ 1.028884] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10254 05:59:42.811118 <6>[ 1.036918] printk: console [ttyS0] disabled
10255 05:59:42.838951 <6>[ 1.061584] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10256 05:59:42.845777 <6>[ 1.071057] printk: console [ttyS0] enabled
10257 05:59:42.848654 <6>[ 1.071057] printk: console [ttyS0] enabled
10258 05:59:42.855488 <6>[ 1.079951] printk: bootconsole [mtk8250] disabled
10259 05:59:42.858263 <6>[ 1.079951] printk: bootconsole [mtk8250] disabled
10260 05:59:42.865188 <6>[ 1.091280] SuperH (H)SCI(F) driver initialized
10261 05:59:42.868352 <6>[ 1.096570] msm_serial: driver initialized
10262 05:59:42.882620 <6>[ 1.105564] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10263 05:59:42.892469 <6>[ 1.114114] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10264 05:59:42.899241 <6>[ 1.122656] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10265 05:59:42.909020 <6>[ 1.131285] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10266 05:59:42.919723 <6>[ 1.139993] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10267 05:59:42.925699 <6>[ 1.148713] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10268 05:59:42.935701 <6>[ 1.157254] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10269 05:59:42.942375 <6>[ 1.166061] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10270 05:59:42.952738 <6>[ 1.174604] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10271 05:59:42.964074 <6>[ 1.190355] loop: module loaded
10272 05:59:42.971055 <6>[ 1.196277] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10273 05:59:42.993276 <4>[ 1.219637] mtk-pmic-keys: Failed to locate of_node [id: -1]
10274 05:59:43.000289 <6>[ 1.226553] megasas: 07.719.03.00-rc1
10275 05:59:43.010062 <6>[ 1.236163] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10276 05:59:43.018028 <6>[ 1.243870] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10277 05:59:43.034156 <6>[ 1.260280] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10278 05:59:43.090327 <6>[ 1.310024] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10279 05:59:43.304623 <6>[ 1.531453] Freeing initrd memory: 17376K
10280 05:59:43.315238 <6>[ 1.541832] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10281 05:59:43.326185 <6>[ 1.552790] tun: Universal TUN/TAP device driver, 1.6
10282 05:59:43.329424 <6>[ 1.558842] thunder_xcv, ver 1.0
10283 05:59:43.333037 <6>[ 1.562347] thunder_bgx, ver 1.0
10284 05:59:43.336328 <6>[ 1.565844] nicpf, ver 1.0
10285 05:59:43.346821 <6>[ 1.569856] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10286 05:59:43.350140 <6>[ 1.577332] hns3: Copyright (c) 2017 Huawei Corporation.
10287 05:59:43.356598 <6>[ 1.582921] hclge is initializing
10288 05:59:43.360251 <6>[ 1.586504] e1000: Intel(R) PRO/1000 Network Driver
10289 05:59:43.366908 <6>[ 1.591633] e1000: Copyright (c) 1999-2006 Intel Corporation.
10290 05:59:43.370090 <6>[ 1.597648] e1000e: Intel(R) PRO/1000 Network Driver
10291 05:59:43.377165 <6>[ 1.602865] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10292 05:59:43.383485 <6>[ 1.609050] igb: Intel(R) Gigabit Ethernet Network Driver
10293 05:59:43.390030 <6>[ 1.614700] igb: Copyright (c) 2007-2014 Intel Corporation.
10294 05:59:43.396876 <6>[ 1.620537] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10295 05:59:43.402972 <6>[ 1.627054] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10296 05:59:43.406443 <6>[ 1.633520] sky2: driver version 1.30
10297 05:59:43.412897 <6>[ 1.638514] VFIO - User Level meta-driver version: 0.3
10298 05:59:43.419940 <6>[ 1.646771] usbcore: registered new interface driver usb-storage
10299 05:59:43.426989 <6>[ 1.653212] usbcore: registered new device driver onboard-usb-hub
10300 05:59:43.436617 <6>[ 1.662355] mt6397-rtc mt6359-rtc: registered as rtc0
10301 05:59:43.446513 <6>[ 1.667815] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-25T05:59:43 UTC (1703483983)
10302 05:59:43.449623 <6>[ 1.677380] i2c_dev: i2c /dev entries driver
10303 05:59:43.466228 <6>[ 1.689122] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10304 05:59:43.486317 <6>[ 1.712103] cpu cpu0: EM: created perf domain
10305 05:59:43.489080 <6>[ 1.716913] cpu cpu4: EM: created perf domain
10306 05:59:43.496178 <6>[ 1.722443] sdhci: Secure Digital Host Controller Interface driver
10307 05:59:43.502760 <6>[ 1.728875] sdhci: Copyright(c) Pierre Ossman
10308 05:59:43.509153 <6>[ 1.733773] Synopsys Designware Multimedia Card Interface Driver
10309 05:59:43.516042 <6>[ 1.740366] sdhci-pltfm: SDHCI platform and OF driver helper
10310 05:59:43.519553 <6>[ 1.740418] mmc0: CQHCI version 5.10
10311 05:59:43.525725 <6>[ 1.750219] ledtrig-cpu: registered to indicate activity on CPUs
10312 05:59:43.532596 <6>[ 1.757250] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10313 05:59:43.539158 <6>[ 1.764277] usbcore: registered new interface driver usbhid
10314 05:59:43.542740 <6>[ 1.770098] usbhid: USB HID core driver
10315 05:59:43.549098 <6>[ 1.774296] spi_master spi0: will run message pump with realtime priority
10316 05:59:43.592989 <6>[ 1.812123] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10317 05:59:43.611776 <6>[ 1.828136] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10318 05:59:43.619240 <6>[ 1.843343] cros-ec-spi spi0.0: Chrome EC device registered
10319 05:59:43.622218 <6>[ 1.849379] mmc0: Command Queue Engine enabled
10320 05:59:43.628744 <6>[ 1.854126] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10321 05:59:43.635666 <6>[ 1.861873] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10322 05:59:43.645681 <6>[ 1.862760] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10323 05:59:43.652311 <6>[ 1.870342] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10324 05:59:43.655302 <6>[ 1.877080] NET: Registered PF_PACKET protocol family
10325 05:59:43.662264 <6>[ 1.883261] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10326 05:59:43.665497 <6>[ 1.887292] 9pnet: Installing 9P2000 support
10327 05:59:43.671914 <6>[ 1.893131] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10328 05:59:43.675483 <5>[ 1.896989] Key type dns_resolver registered
10329 05:59:43.681852 <6>[ 1.902811] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10330 05:59:43.685398 <6>[ 1.907125] registered taskstats version 1
10331 05:59:43.691837 <5>[ 1.917575] Loading compiled-in X.509 certificates
10332 05:59:43.720558 <4>[ 1.939562] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10333 05:59:43.729851 <4>[ 1.950257] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10334 05:59:43.737159 <3>[ 1.960781] debugfs: File 'uA_load' in directory '/' already present!
10335 05:59:43.743264 <3>[ 1.967480] debugfs: File 'min_uV' in directory '/' already present!
10336 05:59:43.749797 <3>[ 1.974145] debugfs: File 'max_uV' in directory '/' already present!
10337 05:59:43.756078 <3>[ 1.980758] debugfs: File 'constraint_flags' in directory '/' already present!
10338 05:59:43.767361 <3>[ 1.990204] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10339 05:59:43.775835 <6>[ 2.002150] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10340 05:59:43.782877 <6>[ 2.008877] xhci-mtk 11200000.usb: xHCI Host Controller
10341 05:59:43.788956 <6>[ 2.014375] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10342 05:59:43.799220 <6>[ 2.022263] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10343 05:59:43.805767 <6>[ 2.031684] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10344 05:59:43.812752 <6>[ 2.037744] xhci-mtk 11200000.usb: xHCI Host Controller
10345 05:59:43.819100 <6>[ 2.043228] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10346 05:59:43.825903 <6>[ 2.050881] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10347 05:59:43.832538 <6>[ 2.058634] hub 1-0:1.0: USB hub found
10348 05:59:43.835666 <6>[ 2.062648] hub 1-0:1.0: 1 port detected
10349 05:59:43.842346 <6>[ 2.066928] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10350 05:59:43.849660 <6>[ 2.075489] hub 2-0:1.0: USB hub found
10351 05:59:43.852511 <6>[ 2.079496] hub 2-0:1.0: 1 port detected
10352 05:59:43.861586 <6>[ 2.087668] mtk-msdc 11f70000.mmc: Got CD GPIO
10353 05:59:43.872037 <6>[ 2.094648] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10354 05:59:43.878667 <6>[ 2.102701] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10355 05:59:43.888267 <4>[ 2.110620] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10356 05:59:43.898476 <6>[ 2.120150] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10357 05:59:43.904683 <6>[ 2.128226] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10358 05:59:43.911819 <6>[ 2.136229] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10359 05:59:43.921736 <6>[ 2.144147] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10360 05:59:43.928526 <6>[ 2.151963] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10361 05:59:43.937911 <6>[ 2.159782] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10362 05:59:43.948022 <6>[ 2.169662] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10363 05:59:43.954291 <6>[ 2.178018] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10364 05:59:43.963945 <6>[ 2.186368] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10365 05:59:43.971085 <6>[ 2.194707] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10366 05:59:43.980941 <6>[ 2.203046] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10367 05:59:43.987163 <6>[ 2.211384] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10368 05:59:43.997304 <6>[ 2.219721] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10369 05:59:44.003738 <6>[ 2.228058] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10370 05:59:44.013642 <6>[ 2.236395] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10371 05:59:44.020390 <6>[ 2.244743] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10372 05:59:44.030550 <6>[ 2.253087] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10373 05:59:44.037317 <6>[ 2.261426] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10374 05:59:44.047035 <6>[ 2.269763] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10375 05:59:44.053690 <6>[ 2.278101] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10376 05:59:44.063249 <6>[ 2.286439] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10377 05:59:44.070705 <6>[ 2.295166] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10378 05:59:44.077033 <6>[ 2.302270] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10379 05:59:44.083830 <6>[ 2.309016] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10380 05:59:44.089994 <6>[ 2.315741] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10381 05:59:44.096881 <6>[ 2.322647] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10382 05:59:44.106236 <6>[ 2.329477] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10383 05:59:44.116777 <6>[ 2.338603] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10384 05:59:44.126696 <6>[ 2.347721] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10385 05:59:44.136663 <6>[ 2.357014] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10386 05:59:44.143019 <6>[ 2.366485] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10387 05:59:44.153277 <6>[ 2.375952] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10388 05:59:44.162681 <6>[ 2.385072] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10389 05:59:44.172906 <6>[ 2.394539] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10390 05:59:44.182479 <6>[ 2.403658] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10391 05:59:44.192598 <6>[ 2.412949] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10392 05:59:44.202365 <6>[ 2.423109] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10393 05:59:44.212775 <6>[ 2.434719] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10394 05:59:44.219001 <6>[ 2.444565] Trying to probe devices needed for running init ...
10395 05:59:44.242099 <6>[ 2.464939] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10396 05:59:44.270379 <6>[ 2.496423] hub 2-1:1.0: USB hub found
10397 05:59:44.273286 <6>[ 2.500935] hub 2-1:1.0: 3 ports detected
10398 05:59:44.281708 <6>[ 2.508034] hub 2-1:1.0: USB hub found
10399 05:59:44.285199 <6>[ 2.512347] hub 2-1:1.0: 3 ports detected
10400 05:59:44.393183 <6>[ 2.616742] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10401 05:59:44.548659 <6>[ 2.774790] hub 1-1:1.0: USB hub found
10402 05:59:44.551764 <6>[ 2.779290] hub 1-1:1.0: 4 ports detected
10403 05:59:44.561600 <6>[ 2.788135] hub 1-1:1.0: USB hub found
10404 05:59:44.565153 <6>[ 2.792458] hub 1-1:1.0: 4 ports detected
10405 05:59:44.625882 <6>[ 2.849066] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10406 05:59:44.885816 <6>[ 3.108801] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10407 05:59:45.018482 <6>[ 3.244692] hub 1-1.4:1.0: USB hub found
10408 05:59:45.021326 <6>[ 3.249370] hub 1-1.4:1.0: 2 ports detected
10409 05:59:45.031093 <6>[ 3.257409] hub 1-1.4:1.0: USB hub found
10410 05:59:45.034421 <6>[ 3.262079] hub 1-1.4:1.0: 2 ports detected
10411 05:59:45.329396 <6>[ 3.552753] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10412 05:59:45.521167 <6>[ 3.744726] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10413 05:59:56.502797 <6>[ 14.733792] ALSA device list:
10414 05:59:56.509104 <6>[ 14.737085] No soundcards found.
10415 05:59:56.517106 <6>[ 14.744876] Freeing unused kernel memory: 8448K
10416 05:59:56.520110 <6>[ 14.749962] Run /init as init process
10417 05:59:56.532069 Loading, please wait...
10418 05:59:56.551869 Starting version 247.3-7+deb11u2
10419 05:59:56.708848 <6>[ 14.933459] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10420 05:59:56.718573 <6>[ 14.946365] remoteproc remoteproc0: scp is available
10421 05:59:56.725016 <6>[ 14.952786] remoteproc remoteproc0: powering up scp
10422 05:59:56.735359 <6>[ 14.957983] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10423 05:59:56.738526 <6>[ 14.966458] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10424 05:59:56.748402 <6>[ 14.969667] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10425 05:59:56.758109 <3>[ 14.981507] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10426 05:59:56.764971 <6>[ 14.984433] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10427 05:59:56.771451 <4>[ 14.991575] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10428 05:59:56.781323 <3>[ 14.992498] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10429 05:59:56.787695 <3>[ 14.992516] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10430 05:59:56.794417 <3>[ 14.997465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10431 05:59:56.804650 <6>[ 14.997600] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10432 05:59:56.814723 <6>[ 14.997611] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10433 05:59:56.817710 <6>[ 14.999224] mc: Linux media interface: v0.10
10434 05:59:56.824371 <4>[ 15.005222] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10435 05:59:56.834522 <3>[ 15.012851] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10436 05:59:56.837877 <6>[ 15.029377] videodev: Linux video capture interface: v2.00
10437 05:59:56.847195 <3>[ 15.037694] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10438 05:59:56.854396 <3>[ 15.080139] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10439 05:59:56.863877 <4>[ 15.087758] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10440 05:59:56.870706 <4>[ 15.087758] Fallback method does not support PEC.
10441 05:59:56.877228 <3>[ 15.088274] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10442 05:59:56.883980 <6>[ 15.097759] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10443 05:59:56.891012 <6>[ 15.097806] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10444 05:59:56.897589 <6>[ 15.097815] remoteproc remoteproc0: remote processor scp is now up
10445 05:59:56.908128 <6>[ 15.103438] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10446 05:59:56.915107 <6>[ 15.110404] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10447 05:59:56.921186 <3>[ 15.110522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10448 05:59:56.931593 <3>[ 15.110557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10449 05:59:56.937811 <3>[ 15.110560] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10450 05:59:56.948138 <3>[ 15.110563] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10451 05:59:56.954506 <3>[ 15.110602] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10452 05:59:56.964864 <3>[ 15.110605] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10453 05:59:56.971225 <3>[ 15.110609] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10454 05:59:56.977851 <3>[ 15.110613] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10455 05:59:56.987875 <3>[ 15.110615] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10456 05:59:56.993921 <3>[ 15.110629] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10457 05:59:57.003903 <6>[ 15.111292] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10458 05:59:57.014056 <6>[ 15.111786] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10459 05:59:57.020598 <6>[ 15.117863] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10460 05:59:57.030351 <6>[ 15.120165] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10461 05:59:57.037117 <3>[ 15.123004] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10462 05:59:57.047327 <6>[ 15.131079] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10463 05:59:57.053834 <6>[ 15.132065] pci_bus 0000:00: root bus resource [bus 00-ff]
10464 05:59:57.063917 <3>[ 15.146691] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10465 05:59:57.070077 <6>[ 15.147387] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10466 05:59:57.080180 <4>[ 15.147897] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10467 05:59:57.086493 <4>[ 15.147902] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10468 05:59:57.090110 <6>[ 15.188741] Bluetooth: Core ver 2.22
10469 05:59:57.099786 <6>[ 15.196007] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10470 05:59:57.106484 <6>[ 15.196938] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10471 05:59:57.119755 <6>[ 15.198194] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10472 05:59:57.125826 <6>[ 15.198287] usbcore: registered new interface driver uvcvideo
10473 05:59:57.133114 <6>[ 15.204091] NET: Registered PF_BLUETOOTH protocol family
10474 05:59:57.136258 <6>[ 15.212143] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10475 05:59:57.142959 <6>[ 15.212865] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10476 05:59:57.148967 <6>[ 15.220222] r8152 2-1.3:1.0 eth0: v1.12.13
10477 05:59:57.155711 <6>[ 15.228264] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10478 05:59:57.162302 <6>[ 15.228501] Bluetooth: HCI device and connection manager initialized
10479 05:59:57.168825 <6>[ 15.228523] Bluetooth: HCI socket layer initialized
10480 05:59:57.172662 <6>[ 15.228535] Bluetooth: L2CAP socket layer initialized
10481 05:59:57.178650 <6>[ 15.228553] Bluetooth: SCO socket layer initialized
10482 05:59:57.182028 <6>[ 15.238442] usbcore: registered new interface driver r8152
10483 05:59:57.188607 <6>[ 15.247424] pci 0000:00:00.0: supports D1 D2
10484 05:59:57.195138 <6>[ 15.286473] usbcore: registered new interface driver cdc_ether
10485 05:59:57.201762 <6>[ 15.295039] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10486 05:59:57.205225 <6>[ 15.302843] usbcore: registered new interface driver btusb
10487 05:59:57.217813 <4>[ 15.303753] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10488 05:59:57.221379 <3>[ 15.303767] Bluetooth: hci0: Failed to load firmware file (-2)
10489 05:59:57.227862 <3>[ 15.303773] Bluetooth: hci0: Failed to set up firmware (-2)
10490 05:59:57.237860 <4>[ 15.303778] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10491 05:59:57.244417 <6>[ 15.311411] usbcore: registered new interface driver r8153_ecm
10492 05:59:57.254468 <6>[ 15.312106] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10493 05:59:57.261066 <6>[ 15.312180] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10494 05:59:57.267678 <6>[ 15.312204] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10495 05:59:57.274010 <6>[ 15.312219] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10496 05:59:57.280898 <6>[ 15.312234] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10497 05:59:57.287179 <6>[ 15.312336] pci 0000:01:00.0: supports D1 D2
10498 05:59:57.293730 <6>[ 15.312338] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10499 05:59:57.300642 <6>[ 15.324658] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10500 05:59:57.306943 <6>[ 15.349360] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10501 05:59:57.313758 <6>[ 15.352509] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10502 05:59:57.323892 <6>[ 15.547883] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10503 05:59:57.330103 <6>[ 15.555886] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10504 05:59:57.336669 <6>[ 15.563892] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10505 05:59:57.346891 <6>[ 15.571893] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10506 05:59:57.350130 <6>[ 15.579896] pci 0000:00:00.0: PCI bridge to [bus 01]
10507 05:59:57.359962 <6>[ 15.585111] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10508 05:59:57.366465 <6>[ 15.593233] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10509 05:59:57.373205 <6>[ 15.600064] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10510 05:59:57.379752 <6>[ 15.606812] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10511 05:59:57.400678 <5>[ 15.626128] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10512 05:59:57.418937 <5>[ 15.643988] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10513 05:59:57.425288 <4>[ 15.650920] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10514 05:59:57.432143 <6>[ 15.659819] cfg80211: failed to load regulatory.db
10515 05:59:57.490845 <6>[ 15.716057] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10516 05:59:57.497654 <6>[ 15.723611] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10517 05:59:57.522089 <6>[ 15.750677] mt7921e 0000:01:00.0: ASIC revision: 79610010
10518 05:59:57.623838 <6>[ 15.848039] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10519 05:59:57.626740 <6>[ 15.848039]
10520 05:59:57.630349 Begin: Loading essential drivers ... done.
10521 05:59:57.633727 Begin: Running /scripts/init-premount ... done.
10522 05:59:57.640037 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10523 05:59:57.649932 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10524 05:59:57.653313 Device /sys/class/net/enx00e04c6803bd found
10525 05:59:57.653886 done.
10526 05:59:57.683976 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10527 05:59:57.892805 <6>[ 16.117342] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10528 05:59:58.572539 <6>[ 16.800022] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10529 05:59:58.731968 <6>[ 16.959717] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10530 05:59:58.939782 IP-Config: no response after 2 secs - giving up
10531 05:59:58.972505 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10532 05:59:59.688059 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10533 05:59:59.694178 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10534 05:59:59.701299 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10535 05:59:59.707657 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10536 05:59:59.714572 host : mt8192-asurada-spherion-r0-cbg-4
10537 05:59:59.720564 domain : lava-rack
10538 05:59:59.724605 rootserver: 192.168.201.1 rootpath:
10539 05:59:59.725259 filename :
10540 05:59:59.821410 done.
10541 05:59:59.828018 Begin: Running /scripts/nfs-bottom ... done.
10542 05:59:59.845271 Begin: Running /scripts/init-bottom ... done.
10543 06:00:01.060544 <6>[ 19.288776] NET: Registered PF_INET6 protocol family
10544 06:00:01.068339 <6>[ 19.296345] Segment Routing with IPv6
10545 06:00:01.071073 <6>[ 19.300331] In-situ OAM (IOAM) with IPv6
10546 06:00:01.196833 <30>[ 19.405366] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10547 06:00:01.202968 <30>[ 19.429800] systemd[1]: Detected architecture arm64.
10548 06:00:01.221637
10549 06:00:01.224959 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10550 06:00:01.225453
10551 06:00:01.242808 <30>[ 19.471457] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10552 06:00:02.134188 <30>[ 20.359365] systemd[1]: Queued start job for default target Graphical Interface.
10553 06:00:02.170909 <30>[ 20.399115] systemd[1]: Created slice system-getty.slice.
10554 06:00:02.177234 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10555 06:00:02.193756 <30>[ 20.422123] systemd[1]: Created slice system-modprobe.slice.
10556 06:00:02.200557 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10557 06:00:02.218145 <30>[ 20.446825] systemd[1]: Created slice system-serial\x2dgetty.slice.
10558 06:00:02.228658 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10559 06:00:02.241244 <30>[ 20.469820] systemd[1]: Created slice User and Session Slice.
10560 06:00:02.247964 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10561 06:00:02.269257 <30>[ 20.493880] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10562 06:00:02.278847 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10563 06:00:02.296258 <30>[ 20.521522] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10564 06:00:02.303185 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10565 06:00:02.327540 <30>[ 20.548917] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10566 06:00:02.333767 <30>[ 20.561076] systemd[1]: Reached target Local Encrypted Volumes.
10567 06:00:02.340064 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10568 06:00:02.357041 <30>[ 20.585320] systemd[1]: Reached target Paths.
10569 06:00:02.360272 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10570 06:00:02.376433 <30>[ 20.604750] systemd[1]: Reached target Remote File Systems.
10571 06:00:02.382732 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10572 06:00:02.400931 <30>[ 20.629121] systemd[1]: Reached target Slices.
10573 06:00:02.407070 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10574 06:00:02.420752 <30>[ 20.648771] systemd[1]: Reached target Swap.
10575 06:00:02.424022 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10576 06:00:02.444355 <30>[ 20.669276] systemd[1]: Listening on initctl Compatibility Named Pipe.
10577 06:00:02.450924 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10578 06:00:02.457403 <30>[ 20.685393] systemd[1]: Listening on Journal Audit Socket.
10579 06:00:02.463525 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10580 06:00:02.481824 <30>[ 20.710187] systemd[1]: Listening on Journal Socket (/dev/log).
10581 06:00:02.488196 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10582 06:00:02.504804 <30>[ 20.733332] systemd[1]: Listening on Journal Socket.
10583 06:00:02.511383 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10584 06:00:02.529437 <30>[ 20.754275] systemd[1]: Listening on Network Service Netlink Socket.
10585 06:00:02.536055 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10586 06:00:02.551393 <30>[ 20.779787] systemd[1]: Listening on udev Control Socket.
10587 06:00:02.557796 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10588 06:00:02.572927 <30>[ 20.801206] systemd[1]: Listening on udev Kernel Socket.
10589 06:00:02.579643 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10590 06:00:02.632597 <30>[ 20.860957] systemd[1]: Mounting Huge Pages File System...
10591 06:00:02.638855 Mounting [0;1;39mHuge Pages File System[0m...
10592 06:00:02.656745 <30>[ 20.885087] systemd[1]: Mounting POSIX Message Queue File System...
10593 06:00:02.663254 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10594 06:00:02.685179 <30>[ 20.913729] systemd[1]: Mounting Kernel Debug File System...
10595 06:00:02.692098 Mounting [0;1;39mKernel Debug File System[0m...
10596 06:00:02.708283 <30>[ 20.933291] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10597 06:00:02.726163 <30>[ 20.951359] systemd[1]: Starting Create list of static device nodes for the current kernel...
10598 06:00:02.735929 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10599 06:00:02.753113 <30>[ 20.981667] systemd[1]: Starting Load Kernel Module configfs...
10600 06:00:02.760000 Starting [0;1;39mLoad Kernel Module configfs[0m...
10601 06:00:02.780948 <30>[ 21.009471] systemd[1]: Starting Load Kernel Module drm...
10602 06:00:02.787555 Starting [0;1;39mLoad Kernel Module drm[0m...
10603 06:00:02.805054 <30>[ 21.033813] systemd[1]: Starting Load Kernel Module fuse...
10604 06:00:02.812149 Starting [0;1;39mLoad Kernel Module fuse[0m...
10605 06:00:02.847768 <30>[ 21.073327] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10606 06:00:02.854588 <6>[ 21.083458] fuse: init (API version 7.37)
10607 06:00:02.862876 <30>[ 21.091744] systemd[1]: Starting Journal Service...
10608 06:00:02.869524 Starting [0;1;39mJournal Service[0m...
10609 06:00:02.894813 <30>[ 21.123739] systemd[1]: Starting Load Kernel Modules...
10610 06:00:02.901053 Starting [0;1;39mLoad Kernel Modules[0m...
10611 06:00:02.923906 <30>[ 21.149613] systemd[1]: Starting Remount Root and Kernel File Systems...
10612 06:00:02.930796 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10613 06:00:02.948238 <30>[ 21.177190] systemd[1]: Starting Coldplug All udev Devices...
10614 06:00:02.955487 Starting [0;1;39mColdplug All udev Devices[0m...
10615 06:00:02.975475 <30>[ 21.203833] systemd[1]: Mounted Huge Pages File System.
10616 06:00:02.985554 <3>[ 21.208833] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10617 06:00:02.992061 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10618 06:00:03.005710 <30>[ 21.233550] systemd[1]: Mounted POSIX Message Queue File System.
10619 06:00:03.015568 <3>[ 21.239105] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10620 06:00:03.022108 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10621 06:00:03.036599 <30>[ 21.265486] systemd[1]: Mounted Kernel Debug File System.
10622 06:00:03.043313 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10623 06:00:03.057129 <3>[ 21.282493] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10624 06:00:03.068901 <30>[ 21.293665] systemd[1]: Finished Create list of static device nodes for the current kernel.
10625 06:00:03.075653 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10626 06:00:03.085809 <3>[ 21.311186] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10627 06:00:03.093851 <30>[ 21.322355] systemd[1]: modprobe@configfs.service: Succeeded.
10628 06:00:03.101322 <30>[ 21.329487] systemd[1]: Finished Load Kernel Module configfs.
10629 06:00:03.108010 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10630 06:00:03.117987 <3>[ 21.341744] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10631 06:00:03.125725 <30>[ 21.354402] systemd[1]: modprobe@drm.service: Succeeded.
10632 06:00:03.133076 <30>[ 21.361592] systemd[1]: Finished Load Kernel Module drm.
10633 06:00:03.139941 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10634 06:00:03.151969 <3>[ 21.377203] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10635 06:00:03.159315 <30>[ 21.387857] systemd[1]: modprobe@fuse.service: Succeeded.
10636 06:00:03.166312 <30>[ 21.395254] systemd[1]: Finished Load Kernel Module fuse.
10637 06:00:03.173468 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10638 06:00:03.185456 <3>[ 21.410687] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10639 06:00:03.193638 <30>[ 21.421744] systemd[1]: Finished Load Kernel Modules.
10640 06:00:03.199603 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10641 06:00:03.217044 <30>[ 21.442506] systemd[1]: Finished Remount Root and Kernel File Systems.
10642 06:00:03.223973 <3>[ 21.443814] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10643 06:00:03.230467 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10644 06:00:03.257804 <3>[ 21.482971] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10645 06:00:03.291767 <3>[ 21.517095] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10646 06:00:03.298552 <30>[ 21.520880] systemd[1]: Mounting FUSE Control File System...
10647 06:00:03.304756 Mounting [0;1;39mFUSE Control File System[0m...
10648 06:00:03.319877 <30>[ 21.547767] systemd[1]: Mounting Kernel Configuration File System...
10649 06:00:03.326193 Mounting [0;1;39mKernel Configuration File System[0m...
10650 06:00:03.352541 <30>[ 21.577954] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10651 06:00:03.362157 <30>[ 21.587069] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10652 06:00:03.372565 <30>[ 21.600709] systemd[1]: Starting Load/Save Random Seed...
10653 06:00:03.379064 Starting [0;1;39mLoad/Save Random Seed[0m...
10654 06:00:03.396088 <30>[ 21.624938] systemd[1]: Starting Apply Kernel Variables...
10655 06:00:03.403038 Starting [0;1;39mApply Kernel Variables[0m...
10656 06:00:03.422904 <4>[ 21.641135] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10657 06:00:03.432343 <3>[ 21.657056] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10658 06:00:03.435705 <30>[ 21.661241] systemd[1]: Starting Create System Users...
10659 06:00:03.442227 Starting [0;1;39mCreate System Users[0m...
10660 06:00:03.458197 <30>[ 21.687116] systemd[1]: Started Journal Service.
10661 06:00:03.464913 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10662 06:00:03.489011 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10663 06:00:03.499934 See 'systemctl status systemd-udev-trigger.service' for details.
10664 06:00:03.516569 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10665 06:00:03.532439 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10666 06:00:03.553474 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10667 06:00:03.570159 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10668 06:00:03.586385 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10669 06:00:03.645278 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10670 06:00:03.662875 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10671 06:00:03.704126 <46>[ 21.929717] systemd-journald[289]: Received client request to flush runtime journal.
10672 06:00:03.752620 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10673 06:00:03.768804 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10674 06:00:03.784246 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10675 06:00:03.832051 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10676 06:00:05.117111 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10677 06:00:05.173311 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10678 06:00:05.210433 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10679 06:00:05.266479 Starting [0;1;39mNetwork Service[0m...
10680 06:00:05.751314 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10681 06:00:05.815892 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10682 06:00:05.835254 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10683 06:00:05.883734 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10684 06:00:05.919505 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10685 06:00:05.968955 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10686 06:00:06.005497 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10687 06:00:06.020498 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10688 06:00:06.068251 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10689 06:00:06.120893 Starting [0;1;39mNetwork Name Resolution[0m...
10690 06:00:06.143018 Starting [0;1;39mNetwork Time Synchronization[0m...
10691 06:00:06.159675 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10692 06:00:06.180727 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10693 06:00:06.235511 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10694 06:00:06.345485 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10695 06:00:06.360389 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10696 06:00:06.379274 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10697 06:00:06.392258 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10698 06:00:06.407976 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10699 06:00:06.538095 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10700 06:00:06.573982 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10701 06:00:06.597662 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10702 06:00:06.622040 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10703 06:00:06.635750 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10704 06:00:06.667436 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10705 06:00:06.679930 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10706 06:00:06.695775 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10707 06:00:06.733311 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10708 06:00:06.808052 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10709 06:00:06.912528 Starting [0;1;39mUser Login Management[0m...
10710 06:00:06.929443 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10711 06:00:06.936700 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10712 06:00:06.959562 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10713 06:00:07.017284 Starting [0;1;39mPermit User Sessions[0m...
10714 06:00:07.098930 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10715 06:00:07.115769 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10716 06:00:07.170654 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10717 06:00:07.191577 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10718 06:00:07.206349 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10719 06:00:07.224537 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10720 06:00:07.245010 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10721 06:00:07.263463 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10722 06:00:07.316157 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10723 06:00:07.364575 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10724 06:00:07.446928
10725 06:00:07.447489
10726 06:00:07.449850 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10727 06:00:07.450313
10728 06:00:07.452999 debian-bullseye-arm64 login: root (automatic login)
10729 06:00:07.453466
10730 06:00:07.453840
10731 06:00:07.821315 Linux debian-bullseye-arm64 6.1.67-cip12 #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023 aarch64
10732 06:00:07.821484
10733 06:00:07.827614 The programs included with the Debian GNU/Linux system are free software;
10734 06:00:07.834432 the exact distribution terms for each program are described in the
10735 06:00:07.837750 individual files in /usr/share/doc/*/copyright.
10736 06:00:07.837885
10737 06:00:07.844635 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10738 06:00:07.847450 permitted by applicable law.
10739 06:00:08.680676 Matched prompt #10: / #
10741 06:00:08.681179 Setting prompt string to ['/ #']
10742 06:00:08.681325 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10744 06:00:08.681638 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10745 06:00:08.681784 start: 2.2.6 expect-shell-connection (timeout 00:03:26) [common]
10746 06:00:08.681896 Setting prompt string to ['/ #']
10747 06:00:08.681995 Forcing a shell prompt, looking for ['/ #']
10749 06:00:08.732397 / #
10750 06:00:08.733380 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10751 06:00:08.733865 Waiting using forced prompt support (timeout 00:02:30)
10752 06:00:08.739254
10753 06:00:08.740204 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10754 06:00:08.740778 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
10756 06:00:08.842010 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12379454/extract-nfsrootfs-ytmy4fkh'
10757 06:00:08.848460 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12379454/extract-nfsrootfs-ytmy4fkh'
10759 06:00:08.950108 / # export NFS_SERVER_IP='192.168.201.1'
10760 06:00:08.956188 export NFS_SERVER_IP='192.168.201.1'
10761 06:00:08.956734 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10762 06:00:08.956979 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
10763 06:00:08.957175 end: 2 depthcharge-action (duration 00:01:35) [common]
10764 06:00:08.957365 start: 3 lava-test-retry (timeout 00:07:45) [common]
10765 06:00:08.957539 start: 3.1 lava-test-shell (timeout 00:07:45) [common]
10766 06:00:08.957691 Using namespace: common
10768 06:00:09.058550 / # #
10769 06:00:09.059214 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10770 06:00:09.065517 #
10771 06:00:09.066404 Using /lava-12379454
10773 06:00:09.167779 / # export SHELL=/bin/bash
10774 06:00:09.174333 export SHELL=/bin/bash
10776 06:00:09.276153 / # . /lava-12379454/environment
10777 06:00:09.282840 . /lava-12379454/environment
10779 06:00:09.390975 / # /lava-12379454/bin/lava-test-runner /lava-12379454/0
10780 06:00:09.391611 Test shell timeout: 10s (minimum of the action and connection timeout)
10781 06:00:09.397565 /lava-12379454/bin/lava-test-runner /lava-12379454/0
10782 06:00:09.700047 + export TESTRUN_ID=0_timesync-off
10783 06:00:09.703652 + TESTRUN_ID=0_timesync-off
10784 06:00:09.706906 + cd /lava-12379454/0/tests/0_timesync-off
10785 06:00:09.709674 ++ cat uuid
10786 06:00:09.713888 + UUID=12379454_1.6.2.3.1
10787 06:00:09.714354 + set +x
10788 06:00:09.720237 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12379454_1.6.2.3.1>
10789 06:00:09.721052 Received signal: <STARTRUN> 0_timesync-off 12379454_1.6.2.3.1
10790 06:00:09.721474 Starting test lava.0_timesync-off (12379454_1.6.2.3.1)
10791 06:00:09.721941 Skipping test definition patterns.
10792 06:00:09.723826 + systemctl stop systemd-timesyncd
10793 06:00:09.768618 + set +x
10794 06:00:09.771685 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12379454_1.6.2.3.1>
10795 06:00:09.772410 Received signal: <ENDRUN> 0_timesync-off 12379454_1.6.2.3.1
10796 06:00:09.772907 Ending use of test pattern.
10797 06:00:09.773266 Ending test lava.0_timesync-off (12379454_1.6.2.3.1), duration 0.05
10799 06:00:09.850629 + export TESTRUN_ID=1_kselftest-tpm2
10800 06:00:09.854094 + TESTRUN_ID=1_kselftest-tpm2
10801 06:00:09.860870 + cd /lava-12379454/0/tests/1_kselftest-tpm2
10802 06:00:09.861343 ++ cat uuid
10803 06:00:09.866981 + UUID=12379454_1.6.2.3.5
10804 06:00:09.867444 + set +x
10805 06:00:09.873991 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 12379454_1.6.2.3.5>
10806 06:00:09.874721 Received signal: <STARTRUN> 1_kselftest-tpm2 12379454_1.6.2.3.5
10807 06:00:09.875108 Starting test lava.1_kselftest-tpm2 (12379454_1.6.2.3.5)
10808 06:00:09.875532 Skipping test definition patterns.
10809 06:00:09.877176 + cd ./automated/linux/kselftest/
10810 06:00:09.903701 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10811 06:00:09.943884 INFO: install_deps skipped
10812 06:00:10.059847 --2023-12-25 06:00:10-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10813 06:00:10.083013 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10814 06:00:10.216243 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10815 06:00:10.349994 HTTP request sent, awaiting response... 200 OK
10816 06:00:10.353358 Length: 2966180 (2.8M) [application/octet-stream]
10817 06:00:10.356301 Saving to: 'kselftest.tar.xz'
10818 06:00:10.356806
10819 06:00:10.357186
10820 06:00:10.616495 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10821 06:00:10.883219 kselftest.tar.xz 1%[ ] 47.81K 181KB/s
10822 06:00:11.148673 kselftest.tar.xz 4%[ ] 132.65K 251KB/s
10823 06:00:11.414980 kselftest.tar.xz 7%[> ] 217.50K 274KB/s
10824 06:00:11.681625 kselftest.tar.xz 11%[=> ] 320.72K 303KB/s
10825 06:00:11.948232 kselftest.tar.xz 14%[=> ] 426.78K 322KB/s
10826 06:00:12.214395 kselftest.tar.xz 18%[==> ] 537.07K 338KB/s
10827 06:00:12.441215 kselftest.tar.xz 22%[===> ] 655.85K 354KB/s
10828 06:00:12.661868 kselftest.tar.xz 26%[====> ] 770.39K 371KB/s
10829 06:00:12.882068 kselftest.tar.xz 30%[=====> ] 882.10K 384KB/s
10830 06:00:13.108673 kselftest.tar.xz 33%[=====> ] 959.88K 381KB/s
10831 06:00:13.326510 kselftest.tar.xz 37%[======> ] 1.05M 393KB/s
10832 06:00:13.549117 kselftest.tar.xz 41%[=======> ] 1.16M 402KB/s
10833 06:00:13.775275 kselftest.tar.xz 43%[=======> ] 1.24M 399KB/s eta 4s
10834 06:00:13.994700 kselftest.tar.xz 47%[========> ] 1.35M 407KB/s eta 4s
10835 06:00:14.217594 kselftest.tar.xz 51%[=========> ] 1.46M 412KB/s eta 4s
10836 06:00:14.443905 kselftest.tar.xz 54%[=========> ] 1.54M 410KB/s eta 4s
10837 06:00:14.660794 kselftest.tar.xz 58%[==========> ] 1.65M 432KB/s eta 4s
10838 06:00:14.883145 kselftest.tar.xz 62%[===========> ] 1.76M 444KB/s eta 3s
10839 06:00:15.109012 kselftest.tar.xz 65%[============> ] 1.84M 439KB/s eta 3s
10840 06:00:15.326900 kselftest.tar.xz 69%[============> ] 1.96M 452KB/s eta 3s
10841 06:00:15.549290 kselftest.tar.xz 73%[=============> ] 2.07M 467KB/s eta 3s
10842 06:00:15.773683 kselftest.tar.xz 76%[==============> ] 2.16M 458KB/s eta 3s
10843 06:00:15.993112 kselftest.tar.xz 80%[===============> ] 2.28M 473KB/s eta 1s
10844 06:00:16.214339 kselftest.tar.xz 84%[===============> ] 2.40M 477KB/s eta 1s
10845 06:00:16.438940 kselftest.tar.xz 88%[================> ] 2.49M 478KB/s eta 1s
10846 06:00:16.755253 kselftest.tar.xz 92%[=================> ] 2.62M 481KB/s eta 1s
10847 06:00:16.881984 kselftest.tar.xz 96%[==================> ] 2.73M 475KB/s eta 1s
10848 06:00:16.888395 kselftest.tar.xz 100%[===================>] 2.83M 487KB/s in 6.5s
10849 06:00:16.888909
10850 06:00:17.146525 2023-12-25 06:00:17 (445 KB/s) - 'kselftest.tar.xz' saved [2966180/2966180]
10851 06:00:17.147043
10852 06:00:23.192927 skiplist:
10853 06:00:23.196269 ========================================
10854 06:00:23.199865 ========================================
10855 06:00:23.248146 tpm2:test_smoke.sh
10856 06:00:23.251060 tpm2:test_space.sh
10857 06:00:23.267572 ============== Tests to run ===============
10858 06:00:23.270856 tpm2:test_smoke.sh
10859 06:00:23.271277 tpm2:test_space.sh
10860 06:00:23.273849 ===========End Tests to run ===============
10861 06:00:23.277800 shardfile-tpm2 pass
10862 06:00:23.382110 <12>[ 41.613614] kselftest: Running tests in tpm2
10863 06:00:23.392074 TAP version 13
10864 06:00:23.403163 1..2
10865 06:00:23.434732 # selftests: tpm2: test_smoke.sh
10866 06:00:24.891196 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
10867 06:00:24.894137 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
10868 06:00:24.901323 # Exception ignored in: <function Client.__del__ at 0xffffae860d30>
10869 06:00:24.904437 # Traceback (most recent call last):
10870 06:00:24.914118 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10871 06:00:24.917228 # if self.tpm:
10872 06:00:24.920915 # AttributeError: 'Client' object has no attribute 'tpm'
10873 06:00:24.927247 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
10874 06:00:24.930852 # Exception ignored in: <function Client.__del__ at 0xffffae860d30>
10875 06:00:24.934023 # Traceback (most recent call last):
10876 06:00:24.944202 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10877 06:00:24.949785 # if self.tpm:
10878 06:00:24.950687 # AttributeError: 'Client' object has no attribute 'tpm'
10879 06:00:24.956920 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
10880 06:00:24.964055 # Exception ignored in: <function Client.__del__ at 0xffffae860d30>
10881 06:00:24.967389 # Traceback (most recent call last):
10882 06:00:24.976941 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10883 06:00:24.977507 # if self.tpm:
10884 06:00:24.983656 # AttributeError: 'Client' object has no attribute 'tpm'
10885 06:00:24.986944 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
10886 06:00:24.993476 # Exception ignored in: <function Client.__del__ at 0xffffae860d30>
10887 06:00:24.997009 # Traceback (most recent call last):
10888 06:00:25.006534 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10889 06:00:25.010075 # if self.tpm:
10890 06:00:25.013098 # AttributeError: 'Client' object has no attribute 'tpm'
10891 06:00:25.020095 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
10892 06:00:25.023438 # Exception ignored in: <function Client.__del__ at 0xffffae860d30>
10893 06:00:25.026432 # Traceback (most recent call last):
10894 06:00:25.036492 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10895 06:00:25.039726 # if self.tpm:
10896 06:00:25.043059 # AttributeError: 'Client' object has no attribute 'tpm'
10897 06:00:25.049771 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
10898 06:00:25.056204 # Exception ignored in: <function Client.__del__ at 0xffffae860d30>
10899 06:00:25.059317 # Traceback (most recent call last):
10900 06:00:25.069326 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10901 06:00:25.069877 # if self.tpm:
10902 06:00:25.076161 # AttributeError: 'Client' object has no attribute 'tpm'
10903 06:00:25.079500 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
10904 06:00:25.086233 # Exception ignored in: <function Client.__del__ at 0xffffae860d30>
10905 06:00:25.089382 # Traceback (most recent call last):
10906 06:00:25.099548 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10907 06:00:25.102987 # if self.tpm:
10908 06:00:25.106181 # AttributeError: 'Client' object has no attribute 'tpm'
10909 06:00:25.112858 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
10910 06:00:25.119646 # Exception ignored in: <function Client.__del__ at 0xffffae860d30>
10911 06:00:25.122694 # Traceback (most recent call last):
10912 06:00:25.132423 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10913 06:00:25.132922 # if self.tpm:
10914 06:00:25.139197 # AttributeError: 'Client' object has no attribute 'tpm'
10915 06:00:25.139658 #
10916 06:00:25.145812 # ======================================================================
10917 06:00:25.148895 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
10918 06:00:25.155791 # ----------------------------------------------------------------------
10919 06:00:25.159199 # Traceback (most recent call last):
10920 06:00:25.169118 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
10921 06:00:25.175507 # self.root_key = self.client.create_root_key()
10922 06:00:25.185547 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10923 06:00:25.192595 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10924 06:00:25.199506 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10925 06:00:25.203284 # raise ProtocolError(cc, rc)
10926 06:00:25.209385 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10927 06:00:25.209858 #
10928 06:00:25.216320 # ======================================================================
10929 06:00:25.223112 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
10930 06:00:25.229734 # ----------------------------------------------------------------------
10931 06:00:25.233108 # Traceback (most recent call last):
10932 06:00:25.242532 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10933 06:00:25.245914 # self.client = tpm2.Client()
10934 06:00:25.255822 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10935 06:00:25.259346 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10936 06:00:25.266073 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10937 06:00:25.266532 #
10938 06:00:25.272433 # ======================================================================
10939 06:00:25.275837 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
10940 06:00:25.282543 # ----------------------------------------------------------------------
10941 06:00:25.285924 # Traceback (most recent call last):
10942 06:00:25.295838 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10943 06:00:25.299269 # self.client = tpm2.Client()
10944 06:00:25.309089 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10945 06:00:25.312212 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10946 06:00:25.318988 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10947 06:00:25.319564 #
10948 06:00:25.325662 # ======================================================================
10949 06:00:25.329369 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
10950 06:00:25.335524 # ----------------------------------------------------------------------
10951 06:00:25.338972 # Traceback (most recent call last):
10952 06:00:25.348905 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10953 06:00:25.352004 # self.client = tpm2.Client()
10954 06:00:25.362042 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10955 06:00:25.368632 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10956 06:00:25.371821 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10957 06:00:25.372346 #
10958 06:00:25.378563 # ======================================================================
10959 06:00:25.385088 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
10960 06:00:25.391895 # ----------------------------------------------------------------------
10961 06:00:25.395079 # Traceback (most recent call last):
10962 06:00:25.405365 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10963 06:00:25.408559 # self.client = tpm2.Client()
10964 06:00:25.418370 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10965 06:00:25.422093 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10966 06:00:25.428343 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10967 06:00:25.428939 #
10968 06:00:25.434903 # ======================================================================
10969 06:00:25.438550 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
10970 06:00:25.445048 # ----------------------------------------------------------------------
10971 06:00:25.448234 # Traceback (most recent call last):
10972 06:00:25.458490 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10973 06:00:25.461547 # self.client = tpm2.Client()
10974 06:00:25.471686 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10975 06:00:25.478230 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10976 06:00:25.481296 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10977 06:00:25.481757 #
10978 06:00:25.488209 # ======================================================================
10979 06:00:25.494422 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
10980 06:00:25.501205 # ----------------------------------------------------------------------
10981 06:00:25.504660 # Traceback (most recent call last):
10982 06:00:25.515143 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10983 06:00:25.515704 # self.client = tpm2.Client()
10984 06:00:25.526863 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10985 06:00:25.529877 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10986 06:00:25.536816 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10987 06:00:25.537370 #
10988 06:00:25.545101 # ======================================================================
10989 06:00:25.548470 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
10990 06:00:25.555932 # ----------------------------------------------------------------------
10991 06:00:25.559504 # Traceback (most recent call last):
10992 06:00:25.567932 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10993 06:00:25.570922 # self.client = tpm2.Client()
10994 06:00:25.581697 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10995 06:00:25.586730 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10996 06:00:25.590230 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10997 06:00:25.590791 #
10998 06:00:25.596579 # ======================================================================
10999 06:00:25.604113 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11000 06:00:25.609964 # ----------------------------------------------------------------------
11001 06:00:25.613453 # Traceback (most recent call last):
11002 06:00:25.623357 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11003 06:00:25.626283 # self.client = tpm2.Client()
11004 06:00:25.636464 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11005 06:00:25.639862 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11006 06:00:25.646305 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11007 06:00:25.646852 #
11008 06:00:25.653295 # ----------------------------------------------------------------------
11009 06:00:25.656360 # Ran 9 tests in 0.053s
11010 06:00:25.656855 #
11011 06:00:25.657219 # FAILED (errors=9)
11012 06:00:25.659496 # test_async (tpm2_tests.AsyncTest) ... ok
11013 06:00:25.666246 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11014 06:00:25.666805 #
11015 06:00:25.672674 # ----------------------------------------------------------------------
11016 06:00:25.676292 # Ran 2 tests in 0.028s
11017 06:00:25.676901 #
11018 06:00:25.677278 # OK
11019 06:00:25.679512 ok 1 selftests: tpm2: test_smoke.sh
11020 06:00:25.682758 # selftests: tpm2: test_space.sh
11021 06:00:25.686146 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11022 06:00:25.692904 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11023 06:00:25.695945 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11024 06:00:25.699243 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11025 06:00:25.702918 #
11026 06:00:25.709045 # ======================================================================
11027 06:00:25.712680 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11028 06:00:25.719163 # ----------------------------------------------------------------------
11029 06:00:25.722613 # Traceback (most recent call last):
11030 06:00:25.732683 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11031 06:00:25.735857 # root1 = space1.create_root_key()
11032 06:00:25.745543 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11033 06:00:25.752870 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11034 06:00:25.762256 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11035 06:00:25.766090 # raise ProtocolError(cc, rc)
11036 06:00:25.772159 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11037 06:00:25.772618 #
11038 06:00:25.779171 # ======================================================================
11039 06:00:25.782232 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11040 06:00:25.788649 # ----------------------------------------------------------------------
11041 06:00:25.792454 # Traceback (most recent call last):
11042 06:00:25.802592 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11043 06:00:25.805619 # space1.create_root_key()
11044 06:00:25.815456 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11045 06:00:25.822575 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11046 06:00:25.832094 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11047 06:00:25.835498 # raise ProtocolError(cc, rc)
11048 06:00:25.842013 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11049 06:00:25.842556 #
11050 06:00:25.848591 # ======================================================================
11051 06:00:25.852315 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11052 06:00:25.858814 # ----------------------------------------------------------------------
11053 06:00:25.861920 # Traceback (most recent call last):
11054 06:00:25.872384 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11055 06:00:25.875641 # root1 = space1.create_root_key()
11056 06:00:25.888747 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11057 06:00:25.891956 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11058 06:00:25.902019 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11059 06:00:25.905179 # raise ProtocolError(cc, rc)
11060 06:00:25.912007 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11061 06:00:25.912768 #
11062 06:00:25.918746 # ======================================================================
11063 06:00:25.922007 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11064 06:00:25.928666 # ----------------------------------------------------------------------
11065 06:00:25.931923 # Traceback (most recent call last):
11066 06:00:25.945086 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11067 06:00:25.948360 # root1 = space1.create_root_key()
11068 06:00:25.958274 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11069 06:00:25.964539 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11070 06:00:25.974729 # File "/lava-12379454/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11071 06:00:25.978057 # raise ProtocolError(cc, rc)
11072 06:00:25.981100 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11073 06:00:25.984566 #
11074 06:00:25.987525 # ----------------------------------------------------------------------
11075 06:00:25.991102 # Ran 4 tests in 0.094s
11076 06:00:25.991688 #
11077 06:00:25.994553 # FAILED (errors=4)
11078 06:00:25.997774 not ok 2 selftests: tpm2: test_space.sh # exit=1
11079 06:00:26.055982 tpm2_test_smoke_sh pass
11080 06:00:26.059048 tpm2_test_space_sh fail
11081 06:00:26.074054 + ../../utils/send-to-lava.sh ./output/result.txt
11082 06:00:26.151559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11083 06:00:26.152497 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11085 06:00:26.208452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11086 06:00:26.209222 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11088 06:00:26.261758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11089 06:00:26.262498 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11091 06:00:26.265084 + set +x
11092 06:00:26.268576 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 12379454_1.6.2.3.5>
11093 06:00:26.269345 Received signal: <ENDRUN> 1_kselftest-tpm2 12379454_1.6.2.3.5
11094 06:00:26.269746 Ending use of test pattern.
11095 06:00:26.270088 Ending test lava.1_kselftest-tpm2 (12379454_1.6.2.3.5), duration 16.39
11097 06:00:26.271518 <LAVA_TEST_RUNNER EXIT>
11098 06:00:26.272165 ok: lava_test_shell seems to have completed
11099 06:00:26.272780 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11100 06:00:26.273227 end: 3.1 lava-test-shell (duration 00:00:17) [common]
11101 06:00:26.273708 end: 3 lava-test-retry (duration 00:00:17) [common]
11102 06:00:26.274198 start: 4 finalize (timeout 00:07:27) [common]
11103 06:00:26.274700 start: 4.1 power-off (timeout 00:00:30) [common]
11104 06:00:26.275502 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11105 06:00:26.366490 >> Command sent successfully.
11106 06:00:26.378226 Returned 0 in 0 seconds
11107 06:00:26.479688 end: 4.1 power-off (duration 00:00:00) [common]
11109 06:00:26.481300 start: 4.2 read-feedback (timeout 00:07:27) [common]
11110 06:00:26.482625 Listened to connection for namespace 'common' for up to 1s
11111 06:00:27.483175 Finalising connection for namespace 'common'
11112 06:00:27.483843 Disconnecting from shell: Finalise
11113 06:00:27.484259 / #
11114 06:00:27.585379 end: 4.2 read-feedback (duration 00:00:01) [common]
11115 06:00:27.586109 end: 4 finalize (duration 00:00:01) [common]
11116 06:00:27.586711 Cleaning after the job
11117 06:00:27.587229 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/ramdisk
11118 06:00:27.601635 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/kernel
11119 06:00:27.635896 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/dtb
11120 06:00:27.636181 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/nfsrootfs
11121 06:00:27.729134 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379454/tftp-deploy-batrup0z/modules
11122 06:00:27.736271 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12379454
11123 06:00:28.355568 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12379454
11124 06:00:28.355750 Job finished correctly