Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 17
- Kernel Errors: 36
- Errors: 0
1 05:56:03.304150 lava-dispatcher, installed at version: 2023.10
2 05:56:03.304448 start: 0 validate
3 05:56:03.304601 Start time: 2023-12-25 05:56:03.304594+00:00 (UTC)
4 05:56:03.304745 Using caching service: 'http://localhost/cache/?uri=%s'
5 05:56:03.304877 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 05:56:03.579247 Using caching service: 'http://localhost/cache/?uri=%s'
7 05:56:03.579994 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 05:56:03.849678 Using caching service: 'http://localhost/cache/?uri=%s'
9 05:56:03.850684 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 05:56:04.121384 Using caching service: 'http://localhost/cache/?uri=%s'
11 05:56:04.122175 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:56:04.392091 Using caching service: 'http://localhost/cache/?uri=%s'
13 05:56:04.392876 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 05:56:04.663011 validate duration: 1.36
16 05:56:04.663266 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:56:04.663366 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:56:04.663458 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:56:04.663597 Not decompressing ramdisk as can be used compressed.
20 05:56:04.663738 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
21 05:56:04.663818 saving as /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/ramdisk/initrd.cpio.gz
22 05:56:04.663881 total size: 4665398 (4 MB)
23 05:56:04.664923 progress 0 % (0 MB)
24 05:56:04.666341 progress 5 % (0 MB)
25 05:56:04.667588 progress 10 % (0 MB)
26 05:56:04.668792 progress 15 % (0 MB)
27 05:56:04.670139 progress 20 % (0 MB)
28 05:56:04.671367 progress 25 % (1 MB)
29 05:56:04.672550 progress 30 % (1 MB)
30 05:56:04.673765 progress 35 % (1 MB)
31 05:56:04.674983 progress 40 % (1 MB)
32 05:56:04.676317 progress 45 % (2 MB)
33 05:56:04.677520 progress 50 % (2 MB)
34 05:56:04.678754 progress 55 % (2 MB)
35 05:56:04.679964 progress 60 % (2 MB)
36 05:56:04.681211 progress 65 % (2 MB)
37 05:56:04.682492 progress 70 % (3 MB)
38 05:56:04.683675 progress 75 % (3 MB)
39 05:56:04.684855 progress 80 % (3 MB)
40 05:56:04.686259 progress 85 % (3 MB)
41 05:56:04.687431 progress 90 % (4 MB)
42 05:56:04.688602 progress 95 % (4 MB)
43 05:56:04.689797 progress 100 % (4 MB)
44 05:56:04.689977 4 MB downloaded in 0.03 s (170.51 MB/s)
45 05:56:04.690167 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:56:04.690400 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:56:04.690485 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:56:04.690567 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:56:04.690694 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 05:56:04.690762 saving as /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/kernel/Image
52 05:56:04.690822 total size: 50024960 (47 MB)
53 05:56:04.690883 No compression specified
54 05:56:04.691987 progress 0 % (0 MB)
55 05:56:04.704513 progress 5 % (2 MB)
56 05:56:04.717482 progress 10 % (4 MB)
57 05:56:04.730227 progress 15 % (7 MB)
58 05:56:04.743508 progress 20 % (9 MB)
59 05:56:04.756047 progress 25 % (11 MB)
60 05:56:04.768473 progress 30 % (14 MB)
61 05:56:04.781078 progress 35 % (16 MB)
62 05:56:04.793814 progress 40 % (19 MB)
63 05:56:04.806374 progress 45 % (21 MB)
64 05:56:04.819190 progress 50 % (23 MB)
65 05:56:04.831835 progress 55 % (26 MB)
66 05:56:04.844271 progress 60 % (28 MB)
67 05:56:04.856856 progress 65 % (31 MB)
68 05:56:04.869235 progress 70 % (33 MB)
69 05:56:04.881680 progress 75 % (35 MB)
70 05:56:04.894442 progress 80 % (38 MB)
71 05:56:04.906927 progress 85 % (40 MB)
72 05:56:04.919378 progress 90 % (42 MB)
73 05:56:04.931933 progress 95 % (45 MB)
74 05:56:04.944119 progress 100 % (47 MB)
75 05:56:04.944340 47 MB downloaded in 0.25 s (188.19 MB/s)
76 05:56:04.944496 end: 1.2.1 http-download (duration 00:00:00) [common]
78 05:56:04.944725 end: 1.2 download-retry (duration 00:00:00) [common]
79 05:56:04.944814 start: 1.3 download-retry (timeout 00:10:00) [common]
80 05:56:04.944899 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 05:56:04.945038 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 05:56:04.945112 saving as /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/dtb/mt8192-asurada-spherion-r0.dtb
83 05:56:04.945174 total size: 47278 (0 MB)
84 05:56:04.945236 No compression specified
85 05:56:04.946315 progress 69 % (0 MB)
86 05:56:04.946592 progress 100 % (0 MB)
87 05:56:04.946747 0 MB downloaded in 0.00 s (28.71 MB/s)
88 05:56:04.946872 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:56:04.947092 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:56:04.947179 start: 1.4 download-retry (timeout 00:10:00) [common]
92 05:56:04.947261 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 05:56:04.947375 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
94 05:56:04.947445 saving as /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/nfsrootfs/full.rootfs.tar
95 05:56:04.947512 total size: 89451516 (85 MB)
96 05:56:04.947575 Using unxz to decompress xz
97 05:56:04.950977 progress 0 % (0 MB)
98 05:56:05.158477 progress 5 % (4 MB)
99 05:56:05.373175 progress 10 % (8 MB)
100 05:56:05.621769 progress 15 % (12 MB)
101 05:56:05.812373 progress 20 % (17 MB)
102 05:56:05.905841 progress 25 % (21 MB)
103 05:56:06.148959 progress 30 % (25 MB)
104 05:56:06.429983 progress 35 % (29 MB)
105 05:56:06.688234 progress 40 % (34 MB)
106 05:56:06.949029 progress 45 % (38 MB)
107 05:56:07.193931 progress 50 % (42 MB)
108 05:56:07.453507 progress 55 % (46 MB)
109 05:56:07.700029 progress 60 % (51 MB)
110 05:56:07.961695 progress 65 % (55 MB)
111 05:56:08.248194 progress 70 % (59 MB)
112 05:56:08.545111 progress 75 % (64 MB)
113 05:56:08.834283 progress 80 % (68 MB)
114 05:56:09.085134 progress 85 % (72 MB)
115 05:56:09.308218 progress 90 % (76 MB)
116 05:56:09.562631 progress 95 % (81 MB)
117 05:56:09.821844 progress 100 % (85 MB)
118 05:56:09.828024 85 MB downloaded in 4.88 s (17.48 MB/s)
119 05:56:09.828265 end: 1.4.1 http-download (duration 00:00:05) [common]
121 05:56:09.828539 end: 1.4 download-retry (duration 00:00:05) [common]
122 05:56:09.828630 start: 1.5 download-retry (timeout 00:09:55) [common]
123 05:56:09.828716 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 05:56:09.828865 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 05:56:09.828934 saving as /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/modules/modules.tar
126 05:56:09.828995 total size: 8619328 (8 MB)
127 05:56:09.829059 Using unxz to decompress xz
128 05:56:09.832491 progress 0 % (0 MB)
129 05:56:09.852855 progress 5 % (0 MB)
130 05:56:09.875892 progress 10 % (0 MB)
131 05:56:09.898942 progress 15 % (1 MB)
132 05:56:09.922503 progress 20 % (1 MB)
133 05:56:09.946259 progress 25 % (2 MB)
134 05:56:09.971129 progress 30 % (2 MB)
135 05:56:09.996698 progress 35 % (2 MB)
136 05:56:10.019686 progress 40 % (3 MB)
137 05:56:10.043504 progress 45 % (3 MB)
138 05:56:10.068172 progress 50 % (4 MB)
139 05:56:10.091756 progress 55 % (4 MB)
140 05:56:10.116078 progress 60 % (4 MB)
141 05:56:10.141178 progress 65 % (5 MB)
142 05:56:10.167356 progress 70 % (5 MB)
143 05:56:10.190193 progress 75 % (6 MB)
144 05:56:10.216622 progress 80 % (6 MB)
145 05:56:10.241736 progress 85 % (7 MB)
146 05:56:10.266162 progress 90 % (7 MB)
147 05:56:10.294897 progress 95 % (7 MB)
148 05:56:10.323991 progress 100 % (8 MB)
149 05:56:10.328612 8 MB downloaded in 0.50 s (16.45 MB/s)
150 05:56:10.328854 end: 1.5.1 http-download (duration 00:00:01) [common]
152 05:56:10.329111 end: 1.5 download-retry (duration 00:00:01) [common]
153 05:56:10.329204 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 05:56:10.329298 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 05:56:11.881464 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12379447/extract-nfsrootfs-4f4eeh_n
156 05:56:11.881662 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 05:56:11.881762 start: 1.6.2 lava-overlay (timeout 00:09:53) [common]
158 05:56:11.881920 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf
159 05:56:11.882051 makedir: /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin
160 05:56:11.882149 makedir: /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/tests
161 05:56:11.882243 makedir: /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/results
162 05:56:11.882342 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-add-keys
163 05:56:11.882477 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-add-sources
164 05:56:11.882599 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-background-process-start
165 05:56:11.882718 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-background-process-stop
166 05:56:11.882835 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-common-functions
167 05:56:11.882951 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-echo-ipv4
168 05:56:11.883068 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-install-packages
169 05:56:11.883188 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-installed-packages
170 05:56:11.883304 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-os-build
171 05:56:11.883421 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-probe-channel
172 05:56:11.883537 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-probe-ip
173 05:56:11.883652 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-target-ip
174 05:56:11.883770 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-target-mac
175 05:56:11.883884 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-target-storage
176 05:56:11.884003 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-test-case
177 05:56:11.884121 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-test-event
178 05:56:11.884237 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-test-feedback
179 05:56:11.884353 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-test-raise
180 05:56:11.884468 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-test-reference
181 05:56:11.884583 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-test-runner
182 05:56:11.884698 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-test-set
183 05:56:11.884813 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-test-shell
184 05:56:11.884930 Updating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-install-packages (oe)
185 05:56:11.885072 Updating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/bin/lava-installed-packages (oe)
186 05:56:11.885194 Creating /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/environment
187 05:56:11.885285 LAVA metadata
188 05:56:11.885355 - LAVA_JOB_ID=12379447
189 05:56:11.885420 - LAVA_DISPATCHER_IP=192.168.201.1
190 05:56:11.885516 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:53) [common]
191 05:56:11.885581 skipped lava-vland-overlay
192 05:56:11.885653 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 05:56:11.885728 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
194 05:56:11.885788 skipped lava-multinode-overlay
195 05:56:11.885858 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 05:56:11.885933 start: 1.6.2.3 test-definition (timeout 00:09:53) [common]
197 05:56:11.886009 Loading test definitions
198 05:56:11.886094 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:53) [common]
199 05:56:11.886163 Using /lava-12379447 at stage 0
200 05:56:11.886447 uuid=12379447_1.6.2.3.1 testdef=None
201 05:56:11.886534 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 05:56:11.886617 start: 1.6.2.3.2 test-overlay (timeout 00:09:53) [common]
203 05:56:11.887073 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 05:56:11.887289 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:53) [common]
206 05:56:11.887861 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 05:56:11.888085 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
209 05:56:11.888642 runner path: /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/0/tests/0_lc-compliance test_uuid 12379447_1.6.2.3.1
210 05:56:11.888788 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 05:56:11.888988 Creating lava-test-runner.conf files
213 05:56:11.889050 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379447/lava-overlay-zmyh8sqf/lava-12379447/0 for stage 0
214 05:56:11.889135 - 0_lc-compliance
215 05:56:11.889227 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 05:56:11.889309 start: 1.6.2.4 compress-overlay (timeout 00:09:53) [common]
217 05:56:11.895087 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 05:56:11.895186 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
219 05:56:11.895271 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 05:56:11.895354 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 05:56:11.895440 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
222 05:56:12.006780 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 05:56:12.007134 start: 1.6.4 extract-modules (timeout 00:09:53) [common]
224 05:56:12.007251 extracting modules file /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379447/extract-nfsrootfs-4f4eeh_n
225 05:56:12.208815 extracting modules file /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379447/extract-overlay-ramdisk-f0k5jb9a/ramdisk
226 05:56:12.414179 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 05:56:12.414356 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 05:56:12.414455 [common] Applying overlay to NFS
229 05:56:12.414528 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379447/compress-overlay-rio8nn8i/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12379447/extract-nfsrootfs-4f4eeh_n
230 05:56:12.420743 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 05:56:12.420858 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 05:56:12.420948 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 05:56:12.421033 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 05:56:12.421118 Building ramdisk /var/lib/lava/dispatcher/tmp/12379447/extract-overlay-ramdisk-f0k5jb9a/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12379447/extract-overlay-ramdisk-f0k5jb9a/ramdisk
235 05:56:12.701927 >> 119415 blocks
236 05:56:14.617688 rename /var/lib/lava/dispatcher/tmp/12379447/extract-overlay-ramdisk-f0k5jb9a/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/ramdisk/ramdisk.cpio.gz
237 05:56:14.618149 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 05:56:14.618270 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 05:56:14.618374 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 05:56:14.618478 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/kernel/Image'
241 05:56:27.540296 Returned 0 in 12 seconds
242 05:56:27.641351 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/kernel/image.itb
243 05:56:27.983969 output: FIT description: Kernel Image image with one or more FDT blobs
244 05:56:27.984314 output: Created: Mon Dec 25 05:56:27 2023
245 05:56:27.984390 output: Image 0 (kernel-1)
246 05:56:27.984451 output: Description:
247 05:56:27.984512 output: Created: Mon Dec 25 05:56:27 2023
248 05:56:27.984574 output: Type: Kernel Image
249 05:56:27.984634 output: Compression: lzma compressed
250 05:56:27.984692 output: Data Size: 11481830 Bytes = 11212.72 KiB = 10.95 MiB
251 05:56:27.984748 output: Architecture: AArch64
252 05:56:27.984808 output: OS: Linux
253 05:56:27.984863 output: Load Address: 0x00000000
254 05:56:27.984919 output: Entry Point: 0x00000000
255 05:56:27.984977 output: Hash algo: crc32
256 05:56:27.985035 output: Hash value: a47c00f1
257 05:56:27.985090 output: Image 1 (fdt-1)
258 05:56:27.985149 output: Description: mt8192-asurada-spherion-r0
259 05:56:27.985203 output: Created: Mon Dec 25 05:56:27 2023
260 05:56:27.985256 output: Type: Flat Device Tree
261 05:56:27.985309 output: Compression: uncompressed
262 05:56:27.985362 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 05:56:27.985414 output: Architecture: AArch64
264 05:56:27.985467 output: Hash algo: crc32
265 05:56:27.985519 output: Hash value: cc4352de
266 05:56:27.985572 output: Image 2 (ramdisk-1)
267 05:56:27.985625 output: Description: unavailable
268 05:56:27.985677 output: Created: Mon Dec 25 05:56:27 2023
269 05:56:27.985731 output: Type: RAMDisk Image
270 05:56:27.985783 output: Compression: Unknown Compression
271 05:56:27.985836 output: Data Size: 17803080 Bytes = 17385.82 KiB = 16.98 MiB
272 05:56:27.985888 output: Architecture: AArch64
273 05:56:27.985946 output: OS: Linux
274 05:56:27.986037 output: Load Address: unavailable
275 05:56:27.986089 output: Entry Point: unavailable
276 05:56:27.986141 output: Hash algo: crc32
277 05:56:27.986193 output: Hash value: 537bc17d
278 05:56:27.986245 output: Default Configuration: 'conf-1'
279 05:56:27.986297 output: Configuration 0 (conf-1)
280 05:56:27.986349 output: Description: mt8192-asurada-spherion-r0
281 05:56:27.986401 output: Kernel: kernel-1
282 05:56:27.986457 output: Init Ramdisk: ramdisk-1
283 05:56:27.986509 output: FDT: fdt-1
284 05:56:27.986561 output: Loadables: kernel-1
285 05:56:27.986613 output:
286 05:56:27.986803 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 05:56:27.986899 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 05:56:27.987006 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 05:56:27.987098 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 05:56:27.987189 No LXC device requested
291 05:56:27.987270 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 05:56:27.987352 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 05:56:27.987431 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 05:56:27.987499 Checking files for TFTP limit of 4294967296 bytes.
295 05:56:27.987977 end: 1 tftp-deploy (duration 00:00:23) [common]
296 05:56:27.988081 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 05:56:27.988177 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 05:56:27.988298 substitutions:
299 05:56:27.988366 - {DTB}: 12379447/tftp-deploy-6ixcjb7k/dtb/mt8192-asurada-spherion-r0.dtb
300 05:56:27.988430 - {INITRD}: 12379447/tftp-deploy-6ixcjb7k/ramdisk/ramdisk.cpio.gz
301 05:56:27.988489 - {KERNEL}: 12379447/tftp-deploy-6ixcjb7k/kernel/Image
302 05:56:27.988547 - {LAVA_MAC}: None
303 05:56:27.988603 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12379447/extract-nfsrootfs-4f4eeh_n
304 05:56:27.988659 - {NFS_SERVER_IP}: 192.168.201.1
305 05:56:27.988713 - {PRESEED_CONFIG}: None
306 05:56:27.988766 - {PRESEED_LOCAL}: None
307 05:56:27.988819 - {RAMDISK}: 12379447/tftp-deploy-6ixcjb7k/ramdisk/ramdisk.cpio.gz
308 05:56:27.988873 - {ROOT_PART}: None
309 05:56:27.988926 - {ROOT}: None
310 05:56:27.988979 - {SERVER_IP}: 192.168.201.1
311 05:56:27.989031 - {TEE}: None
312 05:56:27.989084 Parsed boot commands:
313 05:56:27.989149 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 05:56:27.989328 Parsed boot commands: tftpboot 192.168.201.1 12379447/tftp-deploy-6ixcjb7k/kernel/image.itb 12379447/tftp-deploy-6ixcjb7k/kernel/cmdline
315 05:56:27.989414 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 05:56:27.989497 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 05:56:27.989588 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 05:56:27.989673 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 05:56:27.989745 Not connected, no need to disconnect.
320 05:56:27.989818 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 05:56:27.989898 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 05:56:27.989996 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
323 05:56:27.993201 Setting prompt string to ['lava-test: # ']
324 05:56:27.993528 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 05:56:27.993633 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 05:56:27.993726 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 05:56:27.993814 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 05:56:27.994005 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
329 05:56:33.139081 >> Command sent successfully.
330 05:56:33.150351 Returned 0 in 5 seconds
331 05:56:33.251611 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 05:56:33.253463 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 05:56:33.254167 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 05:56:33.254653 Setting prompt string to 'Starting depthcharge on Spherion...'
336 05:56:33.255042 Changing prompt to 'Starting depthcharge on Spherion...'
337 05:56:33.255424 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 05:56:33.256695 [Enter `^Ec?' for help]
339 05:56:33.415148
340 05:56:33.415906
341 05:56:33.416315 F0: 102B 0000
342 05:56:33.416678
343 05:56:33.417017 F3: 1001 0000 [0200]
344 05:56:33.418760
345 05:56:33.419241 F3: 1001 0000
346 05:56:33.419621
347 05:56:33.419972 F7: 102D 0000
348 05:56:33.420308
349 05:56:33.422669 F1: 0000 0000
350 05:56:33.423144
351 05:56:33.423517 V0: 0000 0000 [0001]
352 05:56:33.423868
353 05:56:33.424203 00: 0007 8000
354 05:56:33.424538
355 05:56:33.426498 01: 0000 0000
356 05:56:33.426992
357 05:56:33.427374 BP: 0C00 0209 [0000]
358 05:56:33.427730
359 05:56:33.430576 G0: 1182 0000
360 05:56:33.431137
361 05:56:33.431517 EC: 0000 0021 [4000]
362 05:56:33.431872
363 05:56:33.434000 S7: 0000 0000 [0000]
364 05:56:33.434482
365 05:56:33.434862 CC: 0000 0000 [0001]
366 05:56:33.435222
367 05:56:33.437180 T0: 0000 0040 [010F]
368 05:56:33.437672
369 05:56:33.438099 Jump to BL
370 05:56:33.438476
371 05:56:33.462483
372 05:56:33.463045
373 05:56:33.463645
374 05:56:33.470270 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 05:56:33.473875 ARM64: Exception handlers installed.
376 05:56:33.477459 ARM64: Testing exception
377 05:56:33.481568 ARM64: Done test exception
378 05:56:33.484972 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 05:56:33.496666 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 05:56:33.503430 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 05:56:33.513996 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 05:56:33.520293 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 05:56:33.527100 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 05:56:33.539073 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 05:56:33.546031 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 05:56:33.564984 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 05:56:33.568512 WDT: Last reset was cold boot
388 05:56:33.571696 SPI1(PAD0) initialized at 2873684 Hz
389 05:56:33.574946 SPI5(PAD0) initialized at 992727 Hz
390 05:56:33.578441 VBOOT: Loading verstage.
391 05:56:33.585405 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 05:56:33.588400 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 05:56:33.591865 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 05:56:33.595172 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 05:56:33.602637 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 05:56:33.609243 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 05:56:33.620191 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
398 05:56:33.620738
399 05:56:33.621116
400 05:56:33.630298 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 05:56:33.633246 ARM64: Exception handlers installed.
402 05:56:33.636550 ARM64: Testing exception
403 05:56:33.637031 ARM64: Done test exception
404 05:56:33.643328 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 05:56:33.646735 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 05:56:33.661409 Probing TPM: . done!
407 05:56:33.661895 TPM ready after 0 ms
408 05:56:33.668113 Connected to device vid:did:rid of 1ae0:0028:00
409 05:56:33.674852 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
410 05:56:33.678443 Initialized TPM device CR50 revision 0
411 05:56:33.742743 tlcl_send_startup: Startup return code is 0
412 05:56:33.743300 TPM: setup succeeded
413 05:56:33.754118 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 05:56:33.762864 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 05:56:33.773096 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 05:56:33.782728 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 05:56:33.786003 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 05:56:33.794419 in-header: 03 07 00 00 08 00 00 00
419 05:56:33.797883 in-data: aa e4 47 04 13 02 00 00
420 05:56:33.801337 Chrome EC: UHEPI supported
421 05:56:33.808953 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 05:56:33.812527 in-header: 03 ad 00 00 08 00 00 00
423 05:56:33.816136 in-data: 00 20 20 08 00 00 00 00
424 05:56:33.816667 Phase 1
425 05:56:33.820021 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 05:56:33.827712 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 05:56:33.831336 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 05:56:33.835202 Recovery requested (1009000e)
429 05:56:33.844039 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 05:56:33.849059 tlcl_extend: response is 0
431 05:56:33.858380 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 05:56:33.864876 tlcl_extend: response is 0
433 05:56:33.871484 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 05:56:33.891863 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
435 05:56:33.898952 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 05:56:33.899433
437 05:56:33.899809
438 05:56:33.909148 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 05:56:33.912373 ARM64: Exception handlers installed.
440 05:56:33.912853 ARM64: Testing exception
441 05:56:33.915666 ARM64: Done test exception
442 05:56:33.937558 pmic_efuse_setting: Set efuses in 11 msecs
443 05:56:33.940818 pmwrap_interface_init: Select PMIF_VLD_RDY
444 05:56:33.947204 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 05:56:33.950756 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 05:56:33.954510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 05:56:33.960555 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 05:56:33.963870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 05:56:33.971680 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 05:56:33.975267 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 05:56:33.979401 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 05:56:33.982623 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 05:56:33.990099 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 05:56:33.993734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 05:56:33.997468 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 05:56:34.004316 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 05:56:34.007876 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 05:56:34.014208 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 05:56:34.021349 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 05:56:34.024799 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 05:56:34.032256 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 05:56:34.036092 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 05:56:34.042341 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 05:56:34.049481 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 05:56:34.053534 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 05:56:34.060023 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 05:56:34.063648 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 05:56:34.069874 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 05:56:34.076816 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 05:56:34.080202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 05:56:34.086775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 05:56:34.090350 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 05:56:34.096878 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 05:56:34.099989 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 05:56:34.107292 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 05:56:34.110449 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 05:56:34.116817 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 05:56:34.120381 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 05:56:34.126965 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 05:56:34.130437 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 05:56:34.137282 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 05:56:34.140333 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 05:56:34.143743 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 05:56:34.150523 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 05:56:34.153657 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 05:56:34.157207 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 05:56:34.160775 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 05:56:34.168073 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 05:56:34.171693 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 05:56:34.175098 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 05:56:34.177935 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 05:56:34.185034 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 05:56:34.187864 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 05:56:34.191281 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 05:56:34.199179 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 05:56:34.206514 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 05:56:34.213688 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 05:56:34.221060 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 05:56:34.228421 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 05:56:34.232652 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 05:56:34.239803 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 05:56:34.243783 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 05:56:34.250792 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x13
504 05:56:34.254159 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 05:56:34.261164 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 05:56:34.264486 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 05:56:34.274136 [RTC]rtc_get_frequency_meter,154: input=15, output=772
508 05:56:34.283952 [RTC]rtc_get_frequency_meter,154: input=23, output=956
509 05:56:34.293032 [RTC]rtc_get_frequency_meter,154: input=19, output=865
510 05:56:34.302600 [RTC]rtc_get_frequency_meter,154: input=17, output=818
511 05:56:34.312409 [RTC]rtc_get_frequency_meter,154: input=16, output=796
512 05:56:34.316567 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
513 05:56:34.320605 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
514 05:56:34.324182 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
515 05:56:34.331792 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
516 05:56:34.335149 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
517 05:56:34.335648 ADC[4]: Raw value=902876 ID=7
518 05:56:34.338578 ADC[3]: Raw value=213179 ID=1
519 05:56:34.342058 RAM Code: 0x71
520 05:56:34.344908 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
521 05:56:34.348568 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
522 05:56:34.358372 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
523 05:56:34.365282 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
524 05:56:34.368773 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
525 05:56:34.372130 in-header: 03 07 00 00 08 00 00 00
526 05:56:34.375583 in-data: aa e4 47 04 13 02 00 00
527 05:56:34.378668 Chrome EC: UHEPI supported
528 05:56:34.385421 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
529 05:56:34.388683 in-header: 03 ed 00 00 08 00 00 00
530 05:56:34.391742 in-data: 80 20 60 08 00 00 00 00
531 05:56:34.395394 MRC: failed to locate region type 0.
532 05:56:34.402153 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
533 05:56:34.402734 DRAM-K: Running full calibration
534 05:56:34.408765 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
535 05:56:34.412208 header.status = 0x0
536 05:56:34.415366 header.version = 0x6 (expected: 0x6)
537 05:56:34.418545 header.size = 0xd00 (expected: 0xd00)
538 05:56:34.419123 header.flags = 0x0
539 05:56:34.425104 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
540 05:56:34.444006 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
541 05:56:34.450648 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
542 05:56:34.454059 dram_init: ddr_geometry: 2
543 05:56:34.457351 [EMI] MDL number = 2
544 05:56:34.457931 [EMI] Get MDL freq = 0
545 05:56:34.460511 dram_init: ddr_type: 0
546 05:56:34.460989 is_discrete_lpddr4: 1
547 05:56:34.464172 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
548 05:56:34.464748
549 05:56:34.465132
550 05:56:34.467429 [Bian_co] ETT version 0.0.0.1
551 05:56:34.474050 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
552 05:56:34.474532
553 05:56:34.477460 dramc_set_vcore_voltage set vcore to 650000
554 05:56:34.477972 Read voltage for 800, 4
555 05:56:34.480744 Vio18 = 0
556 05:56:34.481317 Vcore = 650000
557 05:56:34.481702 Vdram = 0
558 05:56:34.484144 Vddq = 0
559 05:56:34.484718 Vmddr = 0
560 05:56:34.487161 dram_init: config_dvfs: 1
561 05:56:34.490787 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
562 05:56:34.497092 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
563 05:56:34.500171 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
564 05:56:34.504157 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
565 05:56:34.506956 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
566 05:56:34.510370 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
567 05:56:34.513652 MEM_TYPE=3, freq_sel=18
568 05:56:34.517027 sv_algorithm_assistance_LP4_1600
569 05:56:34.520338 ============ PULL DRAM RESETB DOWN ============
570 05:56:34.526994 ========== PULL DRAM RESETB DOWN end =========
571 05:56:34.530803 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
572 05:56:34.533660 ===================================
573 05:56:34.537246 LPDDR4 DRAM CONFIGURATION
574 05:56:34.540479 ===================================
575 05:56:34.540958 EX_ROW_EN[0] = 0x0
576 05:56:34.544091 EX_ROW_EN[1] = 0x0
577 05:56:34.544673 LP4Y_EN = 0x0
578 05:56:34.547039 WORK_FSP = 0x0
579 05:56:34.547613 WL = 0x2
580 05:56:34.550551 RL = 0x2
581 05:56:34.551126 BL = 0x2
582 05:56:34.554045 RPST = 0x0
583 05:56:34.554618 RD_PRE = 0x0
584 05:56:34.556806 WR_PRE = 0x1
585 05:56:34.557279 WR_PST = 0x0
586 05:56:34.560147 DBI_WR = 0x0
587 05:56:34.560624 DBI_RD = 0x0
588 05:56:34.563519 OTF = 0x1
589 05:56:34.567116 ===================================
590 05:56:34.570614 ===================================
591 05:56:34.571088 ANA top config
592 05:56:34.573639 ===================================
593 05:56:34.577372 DLL_ASYNC_EN = 0
594 05:56:34.580190 ALL_SLAVE_EN = 1
595 05:56:34.583803 NEW_RANK_MODE = 1
596 05:56:34.584379 DLL_IDLE_MODE = 1
597 05:56:34.587187 LP45_APHY_COMB_EN = 1
598 05:56:34.590268 TX_ODT_DIS = 1
599 05:56:34.593717 NEW_8X_MODE = 1
600 05:56:34.597601 ===================================
601 05:56:34.600491 ===================================
602 05:56:34.603855 data_rate = 1600
603 05:56:34.607154 CKR = 1
604 05:56:34.607631 DQ_P2S_RATIO = 8
605 05:56:34.610491 ===================================
606 05:56:34.613700 CA_P2S_RATIO = 8
607 05:56:34.617057 DQ_CA_OPEN = 0
608 05:56:34.620334 DQ_SEMI_OPEN = 0
609 05:56:34.623667 CA_SEMI_OPEN = 0
610 05:56:34.624142 CA_FULL_RATE = 0
611 05:56:34.627062 DQ_CKDIV4_EN = 1
612 05:56:34.630477 CA_CKDIV4_EN = 1
613 05:56:34.633911 CA_PREDIV_EN = 0
614 05:56:34.637637 PH8_DLY = 0
615 05:56:34.640496 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
616 05:56:34.640968 DQ_AAMCK_DIV = 4
617 05:56:34.644272 CA_AAMCK_DIV = 4
618 05:56:34.647021 CA_ADMCK_DIV = 4
619 05:56:34.650563 DQ_TRACK_CA_EN = 0
620 05:56:34.654029 CA_PICK = 800
621 05:56:34.657476 CA_MCKIO = 800
622 05:56:34.658087 MCKIO_SEMI = 0
623 05:56:34.660323 PLL_FREQ = 3068
624 05:56:34.663804 DQ_UI_PI_RATIO = 32
625 05:56:34.666967 CA_UI_PI_RATIO = 0
626 05:56:34.670505 ===================================
627 05:56:34.674067 ===================================
628 05:56:34.677301 memory_type:LPDDR4
629 05:56:34.677872 GP_NUM : 10
630 05:56:34.680452 SRAM_EN : 1
631 05:56:34.683936 MD32_EN : 0
632 05:56:34.686869 ===================================
633 05:56:34.687348 [ANA_INIT] >>>>>>>>>>>>>>
634 05:56:34.690382 <<<<<< [CONFIGURE PHASE]: ANA_TX
635 05:56:34.694076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
636 05:56:34.697910 ===================================
637 05:56:34.701682 data_rate = 1600,PCW = 0X7600
638 05:56:34.705323 ===================================
639 05:56:34.705798 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
640 05:56:34.712545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
641 05:56:34.716362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
642 05:56:34.724030 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
643 05:56:34.728091 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
644 05:56:34.728571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
645 05:56:34.731846 [ANA_INIT] flow start
646 05:56:34.735176 [ANA_INIT] PLL >>>>>>>>
647 05:56:34.735656 [ANA_INIT] PLL <<<<<<<<
648 05:56:34.738919 [ANA_INIT] MIDPI >>>>>>>>
649 05:56:34.742396 [ANA_INIT] MIDPI <<<<<<<<
650 05:56:34.742831 [ANA_INIT] DLL >>>>>>>>
651 05:56:34.746351 [ANA_INIT] flow end
652 05:56:34.749936 ============ LP4 DIFF to SE enter ============
653 05:56:34.753534 ============ LP4 DIFF to SE exit ============
654 05:56:34.756915 [ANA_INIT] <<<<<<<<<<<<<
655 05:56:34.760869 [Flow] Enable top DCM control >>>>>
656 05:56:34.761337 [Flow] Enable top DCM control <<<<<
657 05:56:34.764570 Enable DLL master slave shuffle
658 05:56:34.772081 ==============================================================
659 05:56:34.772558 Gating Mode config
660 05:56:34.779070 ==============================================================
661 05:56:34.779501 Config description:
662 05:56:34.790118 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
663 05:56:34.797039 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
664 05:56:34.800853 SELPH_MODE 0: By rank 1: By Phase
665 05:56:34.804756 ==============================================================
666 05:56:34.808733 GAT_TRACK_EN = 1
667 05:56:34.812473 RX_GATING_MODE = 2
668 05:56:34.815742 RX_GATING_TRACK_MODE = 2
669 05:56:34.819717 SELPH_MODE = 1
670 05:56:34.823182 PICG_EARLY_EN = 1
671 05:56:34.823610 VALID_LAT_VALUE = 1
672 05:56:34.830762 ==============================================================
673 05:56:34.834338 Enter into Gating configuration >>>>
674 05:56:34.838085 Exit from Gating configuration <<<<
675 05:56:34.838609 Enter into DVFS_PRE_config >>>>>
676 05:56:34.849486 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
677 05:56:34.853438 Exit from DVFS_PRE_config <<<<<
678 05:56:34.856422 Enter into PICG configuration >>>>
679 05:56:34.859718 Exit from PICG configuration <<<<
680 05:56:34.863828 [RX_INPUT] configuration >>>>>
681 05:56:34.867359 [RX_INPUT] configuration <<<<<
682 05:56:34.870685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
683 05:56:34.874528 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
684 05:56:34.882374 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
685 05:56:34.889576 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
686 05:56:34.897048 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
687 05:56:34.900353 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
688 05:56:34.904254 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
689 05:56:34.907490 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
690 05:56:34.915179 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
691 05:56:34.919009 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
692 05:56:34.922518 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
693 05:56:34.926282 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
694 05:56:34.930225 ===================================
695 05:56:34.930651 LPDDR4 DRAM CONFIGURATION
696 05:56:34.933772 ===================================
697 05:56:34.937408 EX_ROW_EN[0] = 0x0
698 05:56:34.937833 EX_ROW_EN[1] = 0x0
699 05:56:34.941197 LP4Y_EN = 0x0
700 05:56:34.941650 WORK_FSP = 0x0
701 05:56:34.945381 WL = 0x2
702 05:56:34.945906 RL = 0x2
703 05:56:34.949132 BL = 0x2
704 05:56:34.949562 RPST = 0x0
705 05:56:34.952517 RD_PRE = 0x0
706 05:56:34.952947 WR_PRE = 0x1
707 05:56:34.956807 WR_PST = 0x0
708 05:56:34.957385 DBI_WR = 0x0
709 05:56:34.957767 DBI_RD = 0x0
710 05:56:34.960026 OTF = 0x1
711 05:56:34.963516 ===================================
712 05:56:34.967514 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
713 05:56:34.970913 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
714 05:56:34.974776 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
715 05:56:34.978359 ===================================
716 05:56:34.982251 LPDDR4 DRAM CONFIGURATION
717 05:56:34.985923 ===================================
718 05:56:34.986535 EX_ROW_EN[0] = 0x10
719 05:56:34.989336 EX_ROW_EN[1] = 0x0
720 05:56:34.989800 LP4Y_EN = 0x0
721 05:56:34.993369 WORK_FSP = 0x0
722 05:56:34.993801 WL = 0x2
723 05:56:34.996851 RL = 0x2
724 05:56:34.997279 BL = 0x2
725 05:56:35.000780 RPST = 0x0
726 05:56:35.001223 RD_PRE = 0x0
727 05:56:35.001565 WR_PRE = 0x1
728 05:56:35.004087 WR_PST = 0x0
729 05:56:35.004516 DBI_WR = 0x0
730 05:56:35.007812 DBI_RD = 0x0
731 05:56:35.008283 OTF = 0x1
732 05:56:35.011619 ===================================
733 05:56:35.018153 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
734 05:56:35.022932 nWR fixed to 40
735 05:56:35.026262 [ModeRegInit_LP4] CH0 RK0
736 05:56:35.026843 [ModeRegInit_LP4] CH0 RK1
737 05:56:35.030383 [ModeRegInit_LP4] CH1 RK0
738 05:56:35.030928 [ModeRegInit_LP4] CH1 RK1
739 05:56:35.033598 match AC timing 13
740 05:56:35.037523 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
741 05:56:35.040507 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
742 05:56:35.047200 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
743 05:56:35.050452 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
744 05:56:35.053702 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
745 05:56:35.057202 [EMI DOE] emi_dcm 0
746 05:56:35.060861 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
747 05:56:35.061285 ==
748 05:56:35.063813 Dram Type= 6, Freq= 0, CH_0, rank 0
749 05:56:35.070717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 05:56:35.071145 ==
751 05:56:35.073783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 05:56:35.080647 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 05:56:35.089896 [CA 0] Center 38 (7~69) winsize 63
754 05:56:35.093430 [CA 1] Center 38 (7~69) winsize 63
755 05:56:35.096433 [CA 2] Center 35 (5~66) winsize 62
756 05:56:35.100188 [CA 3] Center 35 (5~66) winsize 62
757 05:56:35.103376 [CA 4] Center 34 (4~65) winsize 62
758 05:56:35.106817 [CA 5] Center 33 (3~64) winsize 62
759 05:56:35.107246
760 05:56:35.109757 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 05:56:35.110225
762 05:56:35.113150 [CATrainingPosCal] consider 1 rank data
763 05:56:35.116824 u2DelayCellTimex100 = 270/100 ps
764 05:56:35.120199 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
765 05:56:35.123408 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
766 05:56:35.130055 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
767 05:56:35.133621 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
768 05:56:35.136536 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
769 05:56:35.140277 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 05:56:35.140705
771 05:56:35.143431 CA PerBit enable=1, Macro0, CA PI delay=33
772 05:56:35.143863
773 05:56:35.146974 [CBTSetCACLKResult] CA Dly = 33
774 05:56:35.147446 CS Dly: 5 (0~36)
775 05:56:35.147793 ==
776 05:56:35.149892 Dram Type= 6, Freq= 0, CH_0, rank 1
777 05:56:35.156746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
778 05:56:35.157302 ==
779 05:56:35.160152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
780 05:56:35.166880 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
781 05:56:35.176312 [CA 0] Center 38 (7~69) winsize 63
782 05:56:35.179755 [CA 1] Center 38 (8~69) winsize 62
783 05:56:35.182849 [CA 2] Center 36 (6~67) winsize 62
784 05:56:35.186293 [CA 3] Center 36 (5~67) winsize 63
785 05:56:35.189487 [CA 4] Center 35 (4~66) winsize 63
786 05:56:35.192744 [CA 5] Center 34 (4~65) winsize 62
787 05:56:35.193134
788 05:56:35.196282 [CmdBusTrainingLP45] Vref(ca) range 1: 34
789 05:56:35.196711
790 05:56:35.199787 [CATrainingPosCal] consider 2 rank data
791 05:56:35.203193 u2DelayCellTimex100 = 270/100 ps
792 05:56:35.206208 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
793 05:56:35.209863 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
794 05:56:35.216304 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
795 05:56:35.219935 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
796 05:56:35.223093 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
797 05:56:35.226258 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
798 05:56:35.226700
799 05:56:35.229785 CA PerBit enable=1, Macro0, CA PI delay=34
800 05:56:35.230269
801 05:56:35.233086 [CBTSetCACLKResult] CA Dly = 34
802 05:56:35.233529 CS Dly: 6 (0~38)
803 05:56:35.233998
804 05:56:35.236626 ----->DramcWriteLeveling(PI) begin...
805 05:56:35.240152 ==
806 05:56:35.240596 Dram Type= 6, Freq= 0, CH_0, rank 0
807 05:56:35.246359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 05:56:35.246806 ==
809 05:56:35.249967 Write leveling (Byte 0): 30 => 30
810 05:56:35.253015 Write leveling (Byte 1): 30 => 30
811 05:56:35.256512 DramcWriteLeveling(PI) end<-----
812 05:56:35.256953
813 05:56:35.257402 ==
814 05:56:35.259695 Dram Type= 6, Freq= 0, CH_0, rank 0
815 05:56:35.263214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
816 05:56:35.263650 ==
817 05:56:35.266362 [Gating] SW mode calibration
818 05:56:35.273455 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
819 05:56:35.277346 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
820 05:56:35.281307 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
821 05:56:35.288318 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
822 05:56:35.291924 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 05:56:35.294777 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 05:56:35.298917 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 05:56:35.305675 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 05:56:35.309241 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 05:56:35.312293 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 05:56:35.315738 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 05:56:35.322326 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 05:56:35.325630 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 05:56:35.329083 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 05:56:35.335714 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 05:56:35.339415 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 05:56:35.342425 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 05:56:35.349313 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 05:56:35.352798 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
837 05:56:35.356091 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
838 05:56:35.362514 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
839 05:56:35.366019 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 05:56:35.369261 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 05:56:35.376238 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 05:56:35.379115 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 05:56:35.382394 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 05:56:35.385866 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 05:56:35.392775 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
846 05:56:35.396043 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
847 05:56:35.399372 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
848 05:56:35.406371 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 05:56:35.409342 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 05:56:35.412808 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 05:56:35.419349 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 05:56:35.422773 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
853 05:56:35.426274 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
854 05:56:35.432892 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (1 1) (0 0)
855 05:56:35.436334 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
856 05:56:35.439843 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 05:56:35.446418 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 05:56:35.449480 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 05:56:35.452775 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 05:56:35.459322 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 05:56:35.462974 0 11 4 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
862 05:56:35.466497 0 11 8 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
863 05:56:35.469614 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
864 05:56:35.476076 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 05:56:35.479359 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 05:56:35.483226 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 05:56:35.489502 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 05:56:35.492969 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 05:56:35.496665 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
870 05:56:35.503243 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
871 05:56:35.506146 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 05:56:35.509465 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 05:56:35.515918 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 05:56:35.519822 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 05:56:35.523076 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 05:56:35.529474 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 05:56:35.532746 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 05:56:35.536609 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 05:56:35.543078 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 05:56:35.546455 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 05:56:35.549630 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 05:56:35.556317 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 05:56:35.559458 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 05:56:35.563010 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
885 05:56:35.566362 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
886 05:56:35.569770 Total UI for P1: 0, mck2ui 16
887 05:56:35.572995 best dqsien dly found for B0: ( 0, 14, 0)
888 05:56:35.579554 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
889 05:56:35.583418 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 05:56:35.586208 Total UI for P1: 0, mck2ui 16
891 05:56:35.589601 best dqsien dly found for B1: ( 0, 14, 6)
892 05:56:35.592950 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
893 05:56:35.596655 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
894 05:56:35.597260
895 05:56:35.599458 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
896 05:56:35.602901 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
897 05:56:35.606483 [Gating] SW calibration Done
898 05:56:35.607066 ==
899 05:56:35.609660 Dram Type= 6, Freq= 0, CH_0, rank 0
900 05:56:35.613178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 05:56:35.616388 ==
902 05:56:35.616967 RX Vref Scan: 0
903 05:56:35.617345
904 05:56:35.619853 RX Vref 0 -> 0, step: 1
905 05:56:35.620433
906 05:56:35.623245 RX Delay -130 -> 252, step: 16
907 05:56:35.626785 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
908 05:56:35.629705 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
909 05:56:35.633016 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
910 05:56:35.636638 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
911 05:56:35.642898 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
912 05:56:35.646156 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
913 05:56:35.649693 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
914 05:56:35.653143 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
915 05:56:35.656701 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
916 05:56:35.663075 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
917 05:56:35.666082 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
918 05:56:35.669417 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
919 05:56:35.672974 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
920 05:56:35.676371 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
921 05:56:35.683295 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
922 05:56:35.686288 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
923 05:56:35.686868 ==
924 05:56:35.689588 Dram Type= 6, Freq= 0, CH_0, rank 0
925 05:56:35.693335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 05:56:35.693905 ==
927 05:56:35.696497 DQS Delay:
928 05:56:35.697004 DQS0 = 0, DQS1 = 0
929 05:56:35.697394 DQM Delay:
930 05:56:35.699817 DQM0 = 89, DQM1 = 79
931 05:56:35.700290 DQ Delay:
932 05:56:35.703038 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
933 05:56:35.706531 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
934 05:56:35.709849 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
935 05:56:35.713068 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
936 05:56:35.713642
937 05:56:35.714072
938 05:56:35.714436 ==
939 05:56:35.716506 Dram Type= 6, Freq= 0, CH_0, rank 0
940 05:56:35.723110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 05:56:35.723687 ==
942 05:56:35.724072
943 05:56:35.724423
944 05:56:35.724758 TX Vref Scan disable
945 05:56:35.726365 == TX Byte 0 ==
946 05:56:35.729861 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
947 05:56:35.736174 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
948 05:56:35.736733 == TX Byte 1 ==
949 05:56:35.739650 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
950 05:56:35.743085 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
951 05:56:35.746376 ==
952 05:56:35.750106 Dram Type= 6, Freq= 0, CH_0, rank 0
953 05:56:35.753220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 05:56:35.753792 ==
955 05:56:35.765483 TX Vref=22, minBit 5, minWin=27, winSum=441
956 05:56:35.768464 TX Vref=24, minBit 6, minWin=27, winSum=444
957 05:56:35.772163 TX Vref=26, minBit 8, minWin=27, winSum=451
958 05:56:35.775610 TX Vref=28, minBit 8, minWin=27, winSum=452
959 05:56:35.778593 TX Vref=30, minBit 5, minWin=28, winSum=454
960 05:56:35.782022 TX Vref=32, minBit 3, minWin=28, winSum=456
961 05:56:35.788896 [TxChooseVref] Worse bit 3, Min win 28, Win sum 456, Final Vref 32
962 05:56:35.789457
963 05:56:35.792311 Final TX Range 1 Vref 32
964 05:56:35.792788
965 05:56:35.793229 ==
966 05:56:35.795486 Dram Type= 6, Freq= 0, CH_0, rank 0
967 05:56:35.798585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 05:56:35.799066 ==
969 05:56:35.799444
970 05:56:35.802300
971 05:56:35.802773 TX Vref Scan disable
972 05:56:35.805632 == TX Byte 0 ==
973 05:56:35.808861 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
974 05:56:35.812501 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
975 05:56:35.815226 == TX Byte 1 ==
976 05:56:35.818600 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
977 05:56:35.821800 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
978 05:56:35.825689
979 05:56:35.826300 [DATLAT]
980 05:56:35.826683 Freq=800, CH0 RK0
981 05:56:35.827041
982 05:56:35.828845 DATLAT Default: 0xa
983 05:56:35.829321 0, 0xFFFF, sum = 0
984 05:56:35.831828 1, 0xFFFF, sum = 0
985 05:56:35.832314 2, 0xFFFF, sum = 0
986 05:56:35.835331 3, 0xFFFF, sum = 0
987 05:56:35.835815 4, 0xFFFF, sum = 0
988 05:56:35.838568 5, 0xFFFF, sum = 0
989 05:56:35.839163 6, 0xFFFF, sum = 0
990 05:56:35.842022 7, 0xFFFF, sum = 0
991 05:56:35.842628 8, 0xFFFF, sum = 0
992 05:56:35.845502 9, 0x0, sum = 1
993 05:56:35.846044 10, 0x0, sum = 2
994 05:56:35.848412 11, 0x0, sum = 3
995 05:56:35.848895 12, 0x0, sum = 4
996 05:56:35.851764 best_step = 10
997 05:56:35.852266
998 05:56:35.852657 ==
999 05:56:35.855208 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 05:56:35.858824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 05:56:35.859403 ==
1002 05:56:35.862107 RX Vref Scan: 1
1003 05:56:35.862583
1004 05:56:35.862988 Set Vref Range= 32 -> 127
1005 05:56:35.863348
1006 05:56:35.865443 RX Vref 32 -> 127, step: 1
1007 05:56:35.865984
1008 05:56:35.868711 RX Delay -95 -> 252, step: 8
1009 05:56:35.869299
1010 05:56:35.871892 Set Vref, RX VrefLevel [Byte0]: 32
1011 05:56:35.875189 [Byte1]: 32
1012 05:56:35.875660
1013 05:56:35.878561 Set Vref, RX VrefLevel [Byte0]: 33
1014 05:56:35.881981 [Byte1]: 33
1015 05:56:35.885419
1016 05:56:35.885889 Set Vref, RX VrefLevel [Byte0]: 34
1017 05:56:35.888784 [Byte1]: 34
1018 05:56:35.893342
1019 05:56:35.893915 Set Vref, RX VrefLevel [Byte0]: 35
1020 05:56:35.896817 [Byte1]: 35
1021 05:56:35.900642
1022 05:56:35.901110 Set Vref, RX VrefLevel [Byte0]: 36
1023 05:56:35.903959 [Byte1]: 36
1024 05:56:35.908058
1025 05:56:35.908539 Set Vref, RX VrefLevel [Byte0]: 37
1026 05:56:35.911908 [Byte1]: 37
1027 05:56:35.915878
1028 05:56:35.916591 Set Vref, RX VrefLevel [Byte0]: 38
1029 05:56:35.919302 [Byte1]: 38
1030 05:56:35.923225
1031 05:56:35.923689 Set Vref, RX VrefLevel [Byte0]: 39
1032 05:56:35.926905 [Byte1]: 39
1033 05:56:35.931219
1034 05:56:35.931682 Set Vref, RX VrefLevel [Byte0]: 40
1035 05:56:35.934307 [Byte1]: 40
1036 05:56:35.939137
1037 05:56:35.939603 Set Vref, RX VrefLevel [Byte0]: 41
1038 05:56:35.942489 [Byte1]: 41
1039 05:56:35.946992
1040 05:56:35.947454 Set Vref, RX VrefLevel [Byte0]: 42
1041 05:56:35.950372 [Byte1]: 42
1042 05:56:35.954370
1043 05:56:35.954831 Set Vref, RX VrefLevel [Byte0]: 43
1044 05:56:35.957725 [Byte1]: 43
1045 05:56:35.961419
1046 05:56:35.961896 Set Vref, RX VrefLevel [Byte0]: 44
1047 05:56:35.964890 [Byte1]: 44
1048 05:56:35.969427
1049 05:56:35.969902 Set Vref, RX VrefLevel [Byte0]: 45
1050 05:56:35.972494 [Byte1]: 45
1051 05:56:35.976687
1052 05:56:35.977154 Set Vref, RX VrefLevel [Byte0]: 46
1053 05:56:35.980031 [Byte1]: 46
1054 05:56:35.984070
1055 05:56:35.984539 Set Vref, RX VrefLevel [Byte0]: 47
1056 05:56:35.987716 [Byte1]: 47
1057 05:56:35.992151
1058 05:56:35.992719 Set Vref, RX VrefLevel [Byte0]: 48
1059 05:56:35.995262 [Byte1]: 48
1060 05:56:35.999413
1061 05:56:35.999984 Set Vref, RX VrefLevel [Byte0]: 49
1062 05:56:36.002713 [Byte1]: 49
1063 05:56:36.007171
1064 05:56:36.007741 Set Vref, RX VrefLevel [Byte0]: 50
1065 05:56:36.010149 [Byte1]: 50
1066 05:56:36.014946
1067 05:56:36.015509 Set Vref, RX VrefLevel [Byte0]: 51
1068 05:56:36.018071 [Byte1]: 51
1069 05:56:36.022309
1070 05:56:36.022870 Set Vref, RX VrefLevel [Byte0]: 52
1071 05:56:36.025741 [Byte1]: 52
1072 05:56:36.029851
1073 05:56:36.030347 Set Vref, RX VrefLevel [Byte0]: 53
1074 05:56:36.033355 [Byte1]: 53
1075 05:56:36.037711
1076 05:56:36.038219 Set Vref, RX VrefLevel [Byte0]: 54
1077 05:56:36.040715 [Byte1]: 54
1078 05:56:36.045085
1079 05:56:36.045554 Set Vref, RX VrefLevel [Byte0]: 55
1080 05:56:36.048488 [Byte1]: 55
1081 05:56:36.053046
1082 05:56:36.053744 Set Vref, RX VrefLevel [Byte0]: 56
1083 05:56:36.056181 [Byte1]: 56
1084 05:56:36.060411
1085 05:56:36.060975 Set Vref, RX VrefLevel [Byte0]: 57
1086 05:56:36.063284 [Byte1]: 57
1087 05:56:36.067707
1088 05:56:36.068221 Set Vref, RX VrefLevel [Byte0]: 58
1089 05:56:36.071212 [Byte1]: 58
1090 05:56:36.075515
1091 05:56:36.075987 Set Vref, RX VrefLevel [Byte0]: 59
1092 05:56:36.078619 [Byte1]: 59
1093 05:56:36.083187
1094 05:56:36.083760 Set Vref, RX VrefLevel [Byte0]: 60
1095 05:56:36.086343 [Byte1]: 60
1096 05:56:36.090897
1097 05:56:36.091493 Set Vref, RX VrefLevel [Byte0]: 61
1098 05:56:36.094003 [Byte1]: 61
1099 05:56:36.098590
1100 05:56:36.099192 Set Vref, RX VrefLevel [Byte0]: 62
1101 05:56:36.101742 [Byte1]: 62
1102 05:56:36.106313
1103 05:56:36.106951 Set Vref, RX VrefLevel [Byte0]: 63
1104 05:56:36.109150 [Byte1]: 63
1105 05:56:36.113111
1106 05:56:36.113585 Set Vref, RX VrefLevel [Byte0]: 64
1107 05:56:36.116535 [Byte1]: 64
1108 05:56:36.121048
1109 05:56:36.121663 Set Vref, RX VrefLevel [Byte0]: 65
1110 05:56:36.124598 [Byte1]: 65
1111 05:56:36.128853
1112 05:56:36.129355 Set Vref, RX VrefLevel [Byte0]: 66
1113 05:56:36.132217 [Byte1]: 66
1114 05:56:36.136153
1115 05:56:36.136717 Set Vref, RX VrefLevel [Byte0]: 67
1116 05:56:36.139689 [Byte1]: 67
1117 05:56:36.144184
1118 05:56:36.144744 Set Vref, RX VrefLevel [Byte0]: 68
1119 05:56:36.147238 [Byte1]: 68
1120 05:56:36.151730
1121 05:56:36.152329 Set Vref, RX VrefLevel [Byte0]: 69
1122 05:56:36.155051 [Byte1]: 69
1123 05:56:36.158894
1124 05:56:36.159357 Set Vref, RX VrefLevel [Byte0]: 70
1125 05:56:36.162637 [Byte1]: 70
1126 05:56:36.166589
1127 05:56:36.167050 Set Vref, RX VrefLevel [Byte0]: 71
1128 05:56:36.170121 [Byte1]: 71
1129 05:56:36.173936
1130 05:56:36.174452 Set Vref, RX VrefLevel [Byte0]: 72
1131 05:56:36.177444 [Byte1]: 72
1132 05:56:36.181383
1133 05:56:36.184792 Set Vref, RX VrefLevel [Byte0]: 73
1134 05:56:36.188460 [Byte1]: 73
1135 05:56:36.189261
1136 05:56:36.191648 Set Vref, RX VrefLevel [Byte0]: 74
1137 05:56:36.195120 [Byte1]: 74
1138 05:56:36.195591
1139 05:56:36.198618 Set Vref, RX VrefLevel [Byte0]: 75
1140 05:56:36.201377 [Byte1]: 75
1141 05:56:36.202005
1142 05:56:36.205052 Set Vref, RX VrefLevel [Byte0]: 76
1143 05:56:36.208254 [Byte1]: 76
1144 05:56:36.212383
1145 05:56:36.212933 Set Vref, RX VrefLevel [Byte0]: 77
1146 05:56:36.215423 [Byte1]: 77
1147 05:56:36.219481
1148 05:56:36.219941 Set Vref, RX VrefLevel [Byte0]: 78
1149 05:56:36.223233 [Byte1]: 78
1150 05:56:36.227466
1151 05:56:36.227936 Final RX Vref Byte 0 = 61 to rank0
1152 05:56:36.230882 Final RX Vref Byte 1 = 62 to rank0
1153 05:56:36.233924 Final RX Vref Byte 0 = 61 to rank1
1154 05:56:36.237509 Final RX Vref Byte 1 = 62 to rank1==
1155 05:56:36.240812 Dram Type= 6, Freq= 0, CH_0, rank 0
1156 05:56:36.244121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 05:56:36.247828 ==
1158 05:56:36.248701 DQS Delay:
1159 05:56:36.249166 DQS0 = 0, DQS1 = 0
1160 05:56:36.250872 DQM Delay:
1161 05:56:36.251338 DQM0 = 93, DQM1 = 83
1162 05:56:36.254234 DQ Delay:
1163 05:56:36.254698 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1164 05:56:36.257728 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1165 05:56:36.261121 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1166 05:56:36.264570 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1167 05:56:36.265085
1168 05:56:36.267566
1169 05:56:36.274256 [DQSOSCAuto] RK0, (LSB)MR18= 0x3733, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1170 05:56:36.277841 CH0 RK0: MR19=606, MR18=3733
1171 05:56:36.284384 CH0_RK0: MR19=0x606, MR18=0x3733, DQSOSC=395, MR23=63, INC=94, DEC=63
1172 05:56:36.284958
1173 05:56:36.287792 ----->DramcWriteLeveling(PI) begin...
1174 05:56:36.288372 ==
1175 05:56:36.290986 Dram Type= 6, Freq= 0, CH_0, rank 1
1176 05:56:36.294737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1177 05:56:36.295330 ==
1178 05:56:36.297738 Write leveling (Byte 0): 31 => 31
1179 05:56:36.300938 Write leveling (Byte 1): 31 => 31
1180 05:56:36.304150 DramcWriteLeveling(PI) end<-----
1181 05:56:36.304625
1182 05:56:36.305100 ==
1183 05:56:36.307569 Dram Type= 6, Freq= 0, CH_0, rank 1
1184 05:56:36.310649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 05:56:36.311152 ==
1186 05:56:36.314294 [Gating] SW mode calibration
1187 05:56:36.321154 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1188 05:56:36.327622 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1189 05:56:36.330795 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1190 05:56:36.334303 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1191 05:56:36.382103 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1192 05:56:36.382687 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 05:56:36.383072 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 05:56:36.383425 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 05:56:36.384146 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 05:56:36.384527 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 05:56:36.384863 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 05:56:36.385185 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 05:56:36.385508 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 05:56:36.385823 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 05:56:36.426018 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 05:56:36.426589 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 05:56:36.426990 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 05:56:36.427496 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 05:56:36.427933 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 05:56:36.428827 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1207 05:56:36.429239 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1208 05:56:36.429584 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 05:56:36.429913 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 05:56:36.430279 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 05:56:36.453003 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 05:56:36.453825 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 05:56:36.454937 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 05:56:36.455548 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1215 05:56:36.456006 0 9 8 | B1->B0 | 2d2d 3434 | 1 0 | (1 1) (0 0)
1216 05:56:36.456351 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1217 05:56:36.456681 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 05:56:36.457066 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 05:56:36.463592 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 05:56:36.467146 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 05:56:36.470689 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 05:56:36.477405 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
1223 05:56:36.480884 0 10 8 | B1->B0 | 2d2d 2525 | 1 0 | (1 0) (0 0)
1224 05:56:36.484489 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 05:56:36.490772 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 05:56:36.494050 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 05:56:36.497730 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 05:56:36.500662 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 05:56:36.507485 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 05:56:36.510450 0 11 4 | B1->B0 | 2828 3333 | 0 1 | (0 0) (0 0)
1231 05:56:36.514165 0 11 8 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
1232 05:56:36.521249 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 05:56:36.524900 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 05:56:36.528583 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 05:56:36.531946 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 05:56:36.535861 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 05:56:36.542705 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 05:56:36.545900 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1239 05:56:36.550037 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1240 05:56:36.555826 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 05:56:36.559244 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 05:56:36.562504 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 05:56:36.569228 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 05:56:36.572470 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 05:56:36.576188 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 05:56:36.583153 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 05:56:36.586037 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 05:56:36.589443 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 05:56:36.596188 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 05:56:36.599688 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 05:56:36.603099 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 05:56:36.605930 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 05:56:36.612664 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 05:56:36.616345 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1255 05:56:36.619751 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 05:56:36.623117 Total UI for P1: 0, mck2ui 16
1257 05:56:36.626494 best dqsien dly found for B0: ( 0, 14, 4)
1258 05:56:36.630040 Total UI for P1: 0, mck2ui 16
1259 05:56:36.633073 best dqsien dly found for B1: ( 0, 14, 4)
1260 05:56:36.636464 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1261 05:56:36.639198 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1262 05:56:36.639674
1263 05:56:36.646308 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1264 05:56:36.649814 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1265 05:56:36.650430 [Gating] SW calibration Done
1266 05:56:36.653185 ==
1267 05:56:36.656601 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 05:56:36.659777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 05:56:36.660351 ==
1270 05:56:36.660729 RX Vref Scan: 0
1271 05:56:36.661077
1272 05:56:36.662793 RX Vref 0 -> 0, step: 1
1273 05:56:36.663266
1274 05:56:36.666204 RX Delay -130 -> 252, step: 16
1275 05:56:36.669643 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1276 05:56:36.672796 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1277 05:56:36.676226 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1278 05:56:36.682925 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1279 05:56:36.686399 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1280 05:56:36.689443 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1281 05:56:36.693207 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1282 05:56:36.696464 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1283 05:56:36.702951 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1284 05:56:36.706548 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1285 05:56:36.710004 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1286 05:56:36.712827 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1287 05:56:36.716543 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1288 05:56:36.723232 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1289 05:56:36.726416 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1290 05:56:36.729752 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1291 05:56:36.730354 ==
1292 05:56:36.733306 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 05:56:36.736631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 05:56:36.737076 ==
1295 05:56:36.739375 DQS Delay:
1296 05:56:36.739795 DQS0 = 0, DQS1 = 0
1297 05:56:36.743182 DQM Delay:
1298 05:56:36.743651 DQM0 = 88, DQM1 = 82
1299 05:56:36.744026 DQ Delay:
1300 05:56:36.746350 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1301 05:56:36.750315 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1302 05:56:36.753324 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1303 05:56:36.756738 DQ12 =77, DQ13 =93, DQ14 =93, DQ15 =93
1304 05:56:36.757305
1305 05:56:36.757683
1306 05:56:36.760025 ==
1307 05:56:36.760494 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 05:56:36.766827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 05:56:36.767454 ==
1310 05:56:36.767839
1311 05:56:36.768187
1312 05:56:36.770063 TX Vref Scan disable
1313 05:56:36.770533 == TX Byte 0 ==
1314 05:56:36.772932 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1315 05:56:36.780262 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1316 05:56:36.780837 == TX Byte 1 ==
1317 05:56:36.783447 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1318 05:56:36.790203 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1319 05:56:36.790773 ==
1320 05:56:36.793250 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 05:56:36.796261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 05:56:36.796676 ==
1323 05:56:36.809433 TX Vref=22, minBit 3, minWin=27, winSum=445
1324 05:56:36.812857 TX Vref=24, minBit 8, minWin=27, winSum=449
1325 05:56:36.816513 TX Vref=26, minBit 8, minWin=27, winSum=451
1326 05:56:36.819751 TX Vref=28, minBit 8, minWin=27, winSum=458
1327 05:56:36.823082 TX Vref=30, minBit 8, minWin=27, winSum=456
1328 05:56:36.826590 TX Vref=32, minBit 8, minWin=28, winSum=458
1329 05:56:36.832778 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
1330 05:56:36.833237
1331 05:56:36.836324 Final TX Range 1 Vref 32
1332 05:56:36.836777
1333 05:56:36.837134 ==
1334 05:56:36.839842 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 05:56:36.843295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 05:56:36.843729 ==
1337 05:56:36.844085
1338 05:56:36.844416
1339 05:56:36.846158 TX Vref Scan disable
1340 05:56:36.849900 == TX Byte 0 ==
1341 05:56:36.852896 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1342 05:56:36.856754 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1343 05:56:36.859826 == TX Byte 1 ==
1344 05:56:36.863271 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1345 05:56:36.866444 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1346 05:56:36.866855
1347 05:56:36.869852 [DATLAT]
1348 05:56:36.870314 Freq=800, CH0 RK1
1349 05:56:36.870645
1350 05:56:36.872987 DATLAT Default: 0xa
1351 05:56:36.873409 0, 0xFFFF, sum = 0
1352 05:56:36.876115 1, 0xFFFF, sum = 0
1353 05:56:36.876539 2, 0xFFFF, sum = 0
1354 05:56:36.879466 3, 0xFFFF, sum = 0
1355 05:56:36.879926 4, 0xFFFF, sum = 0
1356 05:56:36.882912 5, 0xFFFF, sum = 0
1357 05:56:36.883335 6, 0xFFFF, sum = 0
1358 05:56:36.886520 7, 0xFFFF, sum = 0
1359 05:56:36.886945 8, 0xFFFF, sum = 0
1360 05:56:36.889247 9, 0x0, sum = 1
1361 05:56:36.889670 10, 0x0, sum = 2
1362 05:56:36.892813 11, 0x0, sum = 3
1363 05:56:36.893233 12, 0x0, sum = 4
1364 05:56:36.896123 best_step = 10
1365 05:56:36.896538
1366 05:56:36.896866 ==
1367 05:56:36.899689 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 05:56:36.902891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 05:56:36.903312 ==
1370 05:56:36.906047 RX Vref Scan: 0
1371 05:56:36.906465
1372 05:56:36.906793 RX Vref 0 -> 0, step: 1
1373 05:56:36.907102
1374 05:56:36.909560 RX Delay -79 -> 252, step: 8
1375 05:56:36.915875 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1376 05:56:36.919612 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1377 05:56:36.922966 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1378 05:56:36.926352 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1379 05:56:36.929667 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1380 05:56:36.936285 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1381 05:56:36.939584 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1382 05:56:36.942578 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1383 05:56:36.945998 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1384 05:56:36.949497 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1385 05:56:36.952700 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1386 05:56:36.959555 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1387 05:56:36.962857 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1388 05:56:36.965797 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1389 05:56:36.969312 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1390 05:56:36.975803 iDelay=209, Bit 15, Center 84 (-23 ~ 192) 216
1391 05:56:36.976094 ==
1392 05:56:36.979572 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 05:56:36.982850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 05:56:36.983110 ==
1395 05:56:36.983269 DQS Delay:
1396 05:56:36.986201 DQS0 = 0, DQS1 = 0
1397 05:56:36.986481 DQM Delay:
1398 05:56:36.989578 DQM0 = 90, DQM1 = 80
1399 05:56:36.989817 DQ Delay:
1400 05:56:36.992453 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1401 05:56:36.996115 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1402 05:56:36.999391 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1403 05:56:37.002767 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1404 05:56:37.003038
1405 05:56:37.003192
1406 05:56:37.008895 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
1407 05:56:37.012702 CH0 RK1: MR19=606, MR18=3D17
1408 05:56:37.019172 CH0_RK1: MR19=0x606, MR18=0x3D17, DQSOSC=394, MR23=63, INC=95, DEC=63
1409 05:56:37.022648 [RxdqsGatingPostProcess] freq 800
1410 05:56:37.029358 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1411 05:56:37.030110 Pre-setting of DQS Precalculation
1412 05:56:37.036111 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1413 05:56:37.036847 ==
1414 05:56:37.039438 Dram Type= 6, Freq= 0, CH_1, rank 0
1415 05:56:37.043001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 05:56:37.043460 ==
1417 05:56:37.049517 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1418 05:56:37.055813 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1419 05:56:37.064238 [CA 0] Center 36 (6~67) winsize 62
1420 05:56:37.067933 [CA 1] Center 36 (6~67) winsize 62
1421 05:56:37.070986 [CA 2] Center 35 (5~65) winsize 61
1422 05:56:37.074425 [CA 3] Center 34 (4~65) winsize 62
1423 05:56:37.077881 [CA 4] Center 34 (4~65) winsize 62
1424 05:56:37.080848 [CA 5] Center 34 (3~65) winsize 63
1425 05:56:37.081570
1426 05:56:37.084114 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1427 05:56:37.084614
1428 05:56:37.087785 [CATrainingPosCal] consider 1 rank data
1429 05:56:37.090761 u2DelayCellTimex100 = 270/100 ps
1430 05:56:37.094086 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1431 05:56:37.097469 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1432 05:56:37.103867 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1433 05:56:37.107211 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1434 05:56:37.110559 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 05:56:37.113875 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1436 05:56:37.114162
1437 05:56:37.117070 CA PerBit enable=1, Macro0, CA PI delay=34
1438 05:56:37.117342
1439 05:56:37.120791 [CBTSetCACLKResult] CA Dly = 34
1440 05:56:37.121063 CS Dly: 5 (0~36)
1441 05:56:37.124045 ==
1442 05:56:37.124322 Dram Type= 6, Freq= 0, CH_1, rank 1
1443 05:56:37.130477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 05:56:37.130623 ==
1445 05:56:37.133684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 05:56:37.140589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 05:56:37.150348 [CA 0] Center 37 (7~68) winsize 62
1448 05:56:37.153265 [CA 1] Center 37 (6~68) winsize 63
1449 05:56:37.156752 [CA 2] Center 35 (5~66) winsize 62
1450 05:56:37.159970 [CA 3] Center 34 (4~65) winsize 62
1451 05:56:37.163830 [CA 4] Center 35 (5~65) winsize 61
1452 05:56:37.167189 [CA 5] Center 34 (4~65) winsize 62
1453 05:56:37.167889
1454 05:56:37.170685 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1455 05:56:37.171385
1456 05:56:37.173580 [CATrainingPosCal] consider 2 rank data
1457 05:56:37.176951 u2DelayCellTimex100 = 270/100 ps
1458 05:56:37.180584 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1459 05:56:37.183288 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1460 05:56:37.187129 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1461 05:56:37.190722 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1462 05:56:37.194317 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1463 05:56:37.198620 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 05:56:37.198750
1465 05:56:37.202527 CA PerBit enable=1, Macro0, CA PI delay=34
1466 05:56:37.202631
1467 05:56:37.206008 [CBTSetCACLKResult] CA Dly = 34
1468 05:56:37.209767 CS Dly: 5 (0~37)
1469 05:56:37.209898
1470 05:56:37.210017 ----->DramcWriteLeveling(PI) begin...
1471 05:56:37.213538 ==
1472 05:56:37.213642 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 05:56:37.221075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 05:56:37.221195 ==
1475 05:56:37.221278 Write leveling (Byte 0): 28 => 28
1476 05:56:37.224554 Write leveling (Byte 1): 28 => 28
1477 05:56:37.227812 DramcWriteLeveling(PI) end<-----
1478 05:56:37.227914
1479 05:56:37.227996 ==
1480 05:56:37.230959 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 05:56:37.237737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 05:56:37.237853 ==
1483 05:56:37.237953 [Gating] SW mode calibration
1484 05:56:37.248138 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1485 05:56:37.251545 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1486 05:56:37.254936 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1487 05:56:37.261577 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 05:56:37.264897 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 05:56:37.268255 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 05:56:37.274919 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 05:56:37.278396 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 05:56:37.281441 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 05:56:37.288447 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 05:56:37.291688 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 05:56:37.295000 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 05:56:37.301782 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 05:56:37.305067 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 05:56:37.307967 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 05:56:37.315463 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 05:56:37.318503 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 05:56:37.321926 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 05:56:37.324967 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 05:56:37.331613 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1504 05:56:37.335124 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 05:56:37.338469 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 05:56:37.345225 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 05:56:37.348376 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 05:56:37.351857 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 05:56:37.358445 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 05:56:37.361494 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 05:56:37.364945 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1512 05:56:37.371487 0 9 8 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1513 05:56:37.374979 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1514 05:56:37.378549 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 05:56:37.385201 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 05:56:37.388416 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 05:56:37.391628 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 05:56:37.398362 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 05:56:37.401848 0 10 4 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (1 0)
1520 05:56:37.404757 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 05:56:37.411470 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 05:56:37.414825 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 05:56:37.418410 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 05:56:37.425259 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 05:56:37.428684 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 05:56:37.431655 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 05:56:37.434898 0 11 4 | B1->B0 | 2f2f 3232 | 0 0 | (0 0) (1 1)
1528 05:56:37.441876 0 11 8 | B1->B0 | 4242 4444 | 0 0 | (0 0) (0 0)
1529 05:56:37.445214 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 05:56:37.448252 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 05:56:37.455083 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 05:56:37.458597 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 05:56:37.461935 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 05:56:37.468461 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 05:56:37.471678 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1536 05:56:37.474970 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 05:56:37.481896 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 05:56:37.484986 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 05:56:37.488520 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 05:56:37.495068 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 05:56:37.498492 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 05:56:37.502070 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 05:56:37.505636 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 05:56:37.511933 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 05:56:37.515410 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 05:56:37.518319 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 05:56:37.525199 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 05:56:37.528611 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 05:56:37.532221 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 05:56:37.538881 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 05:56:37.541794 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1552 05:56:37.545668 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 05:56:37.548801 Total UI for P1: 0, mck2ui 16
1554 05:56:37.552239 best dqsien dly found for B0: ( 0, 14, 4)
1555 05:56:37.555418 Total UI for P1: 0, mck2ui 16
1556 05:56:37.559231 best dqsien dly found for B1: ( 0, 14, 4)
1557 05:56:37.562093 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1558 05:56:37.565246 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1559 05:56:37.565809
1560 05:56:37.568638 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1561 05:56:37.575557 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1562 05:56:37.576188 [Gating] SW calibration Done
1563 05:56:37.576882 ==
1564 05:56:37.578681 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 05:56:37.585649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 05:56:37.586257 ==
1567 05:56:37.586640 RX Vref Scan: 0
1568 05:56:37.586986
1569 05:56:37.588945 RX Vref 0 -> 0, step: 1
1570 05:56:37.589411
1571 05:56:37.592144 RX Delay -130 -> 252, step: 16
1572 05:56:37.595484 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1573 05:56:37.598918 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1574 05:56:37.602389 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1575 05:56:37.609045 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1576 05:56:37.612341 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1577 05:56:37.615826 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1578 05:56:37.619007 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1579 05:56:37.622160 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1580 05:56:37.625678 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1581 05:56:37.632188 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1582 05:56:37.635473 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1583 05:56:37.638938 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1584 05:56:37.642624 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1585 05:56:37.645656 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1586 05:56:37.652341 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1587 05:56:37.655803 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1588 05:56:37.656271 ==
1589 05:56:37.659153 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 05:56:37.662425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 05:56:37.662900 ==
1592 05:56:37.665727 DQS Delay:
1593 05:56:37.666353 DQS0 = 0, DQS1 = 0
1594 05:56:37.666734 DQM Delay:
1595 05:56:37.669188 DQM0 = 91, DQM1 = 81
1596 05:56:37.669653 DQ Delay:
1597 05:56:37.672707 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1598 05:56:37.675420 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =93
1599 05:56:37.678862 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1600 05:56:37.682375 DQ12 =85, DQ13 =93, DQ14 =85, DQ15 =85
1601 05:56:37.683056
1602 05:56:37.683528
1603 05:56:37.683884 ==
1604 05:56:37.685631 Dram Type= 6, Freq= 0, CH_1, rank 0
1605 05:56:37.692728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1606 05:56:37.693299 ==
1607 05:56:37.693678
1608 05:56:37.694076
1609 05:56:37.694416 TX Vref Scan disable
1610 05:56:37.695994 == TX Byte 0 ==
1611 05:56:37.699668 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1612 05:56:37.703048 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1613 05:56:37.706094 == TX Byte 1 ==
1614 05:56:37.709368 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1615 05:56:37.716311 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1616 05:56:37.716875 ==
1617 05:56:37.719534 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 05:56:37.722687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 05:56:37.723256 ==
1620 05:56:37.734921 TX Vref=22, minBit 15, minWin=26, winSum=446
1621 05:56:37.738591 TX Vref=24, minBit 8, minWin=27, winSum=450
1622 05:56:37.741567 TX Vref=26, minBit 8, minWin=27, winSum=453
1623 05:56:37.745365 TX Vref=28, minBit 10, minWin=27, winSum=456
1624 05:56:37.748938 TX Vref=30, minBit 8, minWin=27, winSum=458
1625 05:56:37.751527 TX Vref=32, minBit 8, minWin=27, winSum=452
1626 05:56:37.758608 [TxChooseVref] Worse bit 8, Min win 27, Win sum 458, Final Vref 30
1627 05:56:37.759177
1628 05:56:37.762167 Final TX Range 1 Vref 30
1629 05:56:37.762718
1630 05:56:37.763089 ==
1631 05:56:37.765293 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 05:56:37.768964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 05:56:37.769563 ==
1634 05:56:37.769979
1635 05:56:37.770351
1636 05:56:37.772359 TX Vref Scan disable
1637 05:56:37.775457 == TX Byte 0 ==
1638 05:56:37.779328 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1639 05:56:37.782223 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1640 05:56:37.786017 == TX Byte 1 ==
1641 05:56:37.789126 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1642 05:56:37.792429 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1643 05:56:37.792896
1644 05:56:37.795467 [DATLAT]
1645 05:56:37.795933 Freq=800, CH1 RK0
1646 05:56:37.796305
1647 05:56:37.798850 DATLAT Default: 0xa
1648 05:56:37.799314 0, 0xFFFF, sum = 0
1649 05:56:37.802436 1, 0xFFFF, sum = 0
1650 05:56:37.802911 2, 0xFFFF, sum = 0
1651 05:56:37.806188 3, 0xFFFF, sum = 0
1652 05:56:37.806760 4, 0xFFFF, sum = 0
1653 05:56:37.809690 5, 0xFFFF, sum = 0
1654 05:56:37.810305 6, 0xFFFF, sum = 0
1655 05:56:37.812464 7, 0xFFFF, sum = 0
1656 05:56:37.813037 8, 0xFFFF, sum = 0
1657 05:56:37.816150 9, 0x0, sum = 1
1658 05:56:37.816729 10, 0x0, sum = 2
1659 05:56:37.819416 11, 0x0, sum = 3
1660 05:56:37.819889 12, 0x0, sum = 4
1661 05:56:37.822471 best_step = 10
1662 05:56:37.823040
1663 05:56:37.823413 ==
1664 05:56:37.826188 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 05:56:37.829322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 05:56:37.829904 ==
1667 05:56:37.830359 RX Vref Scan: 1
1668 05:56:37.830714
1669 05:56:37.832824 Set Vref Range= 32 -> 127
1670 05:56:37.833400
1671 05:56:37.836015 RX Vref 32 -> 127, step: 1
1672 05:56:37.836486
1673 05:56:37.839620 RX Delay -95 -> 252, step: 8
1674 05:56:37.840192
1675 05:56:37.842586 Set Vref, RX VrefLevel [Byte0]: 32
1676 05:56:37.846177 [Byte1]: 32
1677 05:56:37.846774
1678 05:56:37.849274 Set Vref, RX VrefLevel [Byte0]: 33
1679 05:56:37.852813 [Byte1]: 33
1680 05:56:37.853392
1681 05:56:37.856337 Set Vref, RX VrefLevel [Byte0]: 34
1682 05:56:37.859802 [Byte1]: 34
1683 05:56:37.863115
1684 05:56:37.863708 Set Vref, RX VrefLevel [Byte0]: 35
1685 05:56:37.866461 [Byte1]: 35
1686 05:56:37.870662
1687 05:56:37.871205 Set Vref, RX VrefLevel [Byte0]: 36
1688 05:56:37.876739 [Byte1]: 36
1689 05:56:37.877208
1690 05:56:37.880352 Set Vref, RX VrefLevel [Byte0]: 37
1691 05:56:37.883683 [Byte1]: 37
1692 05:56:37.884292
1693 05:56:37.887249 Set Vref, RX VrefLevel [Byte0]: 38
1694 05:56:37.890028 [Byte1]: 38
1695 05:56:37.890500
1696 05:56:37.893636 Set Vref, RX VrefLevel [Byte0]: 39
1697 05:56:37.896915 [Byte1]: 39
1698 05:56:37.900922
1699 05:56:37.901391 Set Vref, RX VrefLevel [Byte0]: 40
1700 05:56:37.904474 [Byte1]: 40
1701 05:56:37.908560
1702 05:56:37.909126 Set Vref, RX VrefLevel [Byte0]: 41
1703 05:56:37.911955 [Byte1]: 41
1704 05:56:37.916484
1705 05:56:37.917176 Set Vref, RX VrefLevel [Byte0]: 42
1706 05:56:37.919674 [Byte1]: 42
1707 05:56:37.923715
1708 05:56:37.924277 Set Vref, RX VrefLevel [Byte0]: 43
1709 05:56:37.926887 [Byte1]: 43
1710 05:56:37.931128
1711 05:56:37.931587 Set Vref, RX VrefLevel [Byte0]: 44
1712 05:56:37.934559 [Byte1]: 44
1713 05:56:37.939253
1714 05:56:37.939812 Set Vref, RX VrefLevel [Byte0]: 45
1715 05:56:37.942157 [Byte1]: 45
1716 05:56:37.946557
1717 05:56:37.947124 Set Vref, RX VrefLevel [Byte0]: 46
1718 05:56:37.949542 [Byte1]: 46
1719 05:56:37.954249
1720 05:56:37.954804 Set Vref, RX VrefLevel [Byte0]: 47
1721 05:56:37.957426 [Byte1]: 47
1722 05:56:37.961600
1723 05:56:37.962207 Set Vref, RX VrefLevel [Byte0]: 48
1724 05:56:37.965009 [Byte1]: 48
1725 05:56:37.969564
1726 05:56:37.970180 Set Vref, RX VrefLevel [Byte0]: 49
1727 05:56:37.972584 [Byte1]: 49
1728 05:56:37.976793
1729 05:56:37.977274 Set Vref, RX VrefLevel [Byte0]: 50
1730 05:56:37.979872 [Byte1]: 50
1731 05:56:37.984239
1732 05:56:37.984696 Set Vref, RX VrefLevel [Byte0]: 51
1733 05:56:37.988253 [Byte1]: 51
1734 05:56:37.991897
1735 05:56:37.992366 Set Vref, RX VrefLevel [Byte0]: 52
1736 05:56:37.995419 [Byte1]: 52
1737 05:56:37.999376
1738 05:56:37.999867 Set Vref, RX VrefLevel [Byte0]: 53
1739 05:56:38.002832 [Byte1]: 53
1740 05:56:38.007536
1741 05:56:38.008152 Set Vref, RX VrefLevel [Byte0]: 54
1742 05:56:38.010348 [Byte1]: 54
1743 05:56:38.014725
1744 05:56:38.015208 Set Vref, RX VrefLevel [Byte0]: 55
1745 05:56:38.018309 [Byte1]: 55
1746 05:56:38.022799
1747 05:56:38.023367 Set Vref, RX VrefLevel [Byte0]: 56
1748 05:56:38.025659 [Byte1]: 56
1749 05:56:38.030323
1750 05:56:38.030973 Set Vref, RX VrefLevel [Byte0]: 57
1751 05:56:38.033753 [Byte1]: 57
1752 05:56:38.038093
1753 05:56:38.038667 Set Vref, RX VrefLevel [Byte0]: 58
1754 05:56:38.041131 [Byte1]: 58
1755 05:56:38.045742
1756 05:56:38.046354 Set Vref, RX VrefLevel [Byte0]: 59
1757 05:56:38.048525 [Byte1]: 59
1758 05:56:38.053129
1759 05:56:38.053880 Set Vref, RX VrefLevel [Byte0]: 60
1760 05:56:38.056383 [Byte1]: 60
1761 05:56:38.060533
1762 05:56:38.061105 Set Vref, RX VrefLevel [Byte0]: 61
1763 05:56:38.063625 [Byte1]: 61
1764 05:56:38.068495
1765 05:56:38.069059 Set Vref, RX VrefLevel [Byte0]: 62
1766 05:56:38.071208 [Byte1]: 62
1767 05:56:38.075646
1768 05:56:38.076109 Set Vref, RX VrefLevel [Byte0]: 63
1769 05:56:38.079054 [Byte1]: 63
1770 05:56:38.083119
1771 05:56:38.083593 Set Vref, RX VrefLevel [Byte0]: 64
1772 05:56:38.086513 [Byte1]: 64
1773 05:56:38.090752
1774 05:56:38.091324 Set Vref, RX VrefLevel [Byte0]: 65
1775 05:56:38.094223 [Byte1]: 65
1776 05:56:38.098483
1777 05:56:38.099048 Set Vref, RX VrefLevel [Byte0]: 66
1778 05:56:38.101584 [Byte1]: 66
1779 05:56:38.106079
1780 05:56:38.106633 Set Vref, RX VrefLevel [Byte0]: 67
1781 05:56:38.109279 [Byte1]: 67
1782 05:56:38.114073
1783 05:56:38.114637 Set Vref, RX VrefLevel [Byte0]: 68
1784 05:56:38.116885 [Byte1]: 68
1785 05:56:38.121628
1786 05:56:38.122296 Set Vref, RX VrefLevel [Byte0]: 69
1787 05:56:38.125093 [Byte1]: 69
1788 05:56:38.129146
1789 05:56:38.129715 Set Vref, RX VrefLevel [Byte0]: 70
1790 05:56:38.131859 [Byte1]: 70
1791 05:56:38.136428
1792 05:56:38.136891 Set Vref, RX VrefLevel [Byte0]: 71
1793 05:56:38.140043 [Byte1]: 71
1794 05:56:38.144250
1795 05:56:38.144822 Set Vref, RX VrefLevel [Byte0]: 72
1796 05:56:38.147458 [Byte1]: 72
1797 05:56:38.151410
1798 05:56:38.151875 Set Vref, RX VrefLevel [Byte0]: 73
1799 05:56:38.155049 [Byte1]: 73
1800 05:56:38.159208
1801 05:56:38.159775 Set Vref, RX VrefLevel [Byte0]: 74
1802 05:56:38.162843 [Byte1]: 74
1803 05:56:38.167319
1804 05:56:38.167885 Set Vref, RX VrefLevel [Byte0]: 75
1805 05:56:38.170167 [Byte1]: 75
1806 05:56:38.174522
1807 05:56:38.175102 Set Vref, RX VrefLevel [Byte0]: 76
1808 05:56:38.177689 [Byte1]: 76
1809 05:56:38.181883
1810 05:56:38.182399 Final RX Vref Byte 0 = 51 to rank0
1811 05:56:38.185712 Final RX Vref Byte 1 = 62 to rank0
1812 05:56:38.188548 Final RX Vref Byte 0 = 51 to rank1
1813 05:56:38.192413 Final RX Vref Byte 1 = 62 to rank1==
1814 05:56:38.195321 Dram Type= 6, Freq= 0, CH_1, rank 0
1815 05:56:38.202141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1816 05:56:38.202616 ==
1817 05:56:38.202990 DQS Delay:
1818 05:56:38.203342 DQS0 = 0, DQS1 = 0
1819 05:56:38.205330 DQM Delay:
1820 05:56:38.205799 DQM0 = 92, DQM1 = 83
1821 05:56:38.208766 DQ Delay:
1822 05:56:38.212069 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
1823 05:56:38.215346 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1824 05:56:38.218746 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =76
1825 05:56:38.222101 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1826 05:56:38.222573
1827 05:56:38.222948
1828 05:56:38.228530 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1829 05:56:38.231976 CH1 RK0: MR19=606, MR18=2C49
1830 05:56:38.238416 CH1_RK0: MR19=0x606, MR18=0x2C49, DQSOSC=391, MR23=63, INC=96, DEC=64
1831 05:56:38.238927
1832 05:56:38.241782 ----->DramcWriteLeveling(PI) begin...
1833 05:56:38.242300 ==
1834 05:56:38.245056 Dram Type= 6, Freq= 0, CH_1, rank 1
1835 05:56:38.248624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1836 05:56:38.249097 ==
1837 05:56:38.252104 Write leveling (Byte 0): 28 => 28
1838 05:56:38.255879 Write leveling (Byte 1): 32 => 32
1839 05:56:38.258588 DramcWriteLeveling(PI) end<-----
1840 05:56:38.259060
1841 05:56:38.259432 ==
1842 05:56:38.262169 Dram Type= 6, Freq= 0, CH_1, rank 1
1843 05:56:38.265508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1844 05:56:38.266107 ==
1845 05:56:38.269035 [Gating] SW mode calibration
1846 05:56:38.275483 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1847 05:56:38.281978 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1848 05:56:38.285716 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1849 05:56:38.289123 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1850 05:56:38.295443 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 05:56:38.298679 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 05:56:38.302327 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 05:56:38.308977 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 05:56:38.312046 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 05:56:38.315450 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 05:56:38.322528 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 05:56:38.325399 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 05:56:38.328805 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 05:56:38.332126 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 05:56:38.338734 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 05:56:38.342275 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 05:56:38.345452 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 05:56:38.352163 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 05:56:38.355717 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 05:56:38.358846 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1866 05:56:38.365817 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 05:56:38.369054 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 05:56:38.371925 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 05:56:38.378877 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 05:56:38.382406 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 05:56:38.385707 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 05:56:38.392240 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 05:56:38.395554 0 9 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1874 05:56:38.398966 0 9 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1875 05:56:38.405653 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 05:56:38.409200 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 05:56:38.412098 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 05:56:38.418737 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1879 05:56:38.422310 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 05:56:38.426008 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1881 05:56:38.429134 0 10 4 | B1->B0 | 2f2f 3030 | 1 1 | (1 0) (1 0)
1882 05:56:38.435779 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1883 05:56:38.439262 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 05:56:38.442626 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 05:56:38.449248 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 05:56:38.452684 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 05:56:38.455699 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 05:56:38.462442 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 05:56:38.465659 0 11 4 | B1->B0 | 3535 2e2e | 1 0 | (0 0) (0 0)
1890 05:56:38.469091 0 11 8 | B1->B0 | 4545 3e3e | 0 0 | (0 0) (0 0)
1891 05:56:38.475563 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 05:56:38.478953 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 05:56:38.482409 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 05:56:38.489148 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 05:56:38.492655 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 05:56:38.495700 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 05:56:38.502608 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1898 05:56:38.505817 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 05:56:38.509109 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 05:56:38.512431 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 05:56:38.519343 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 05:56:38.522786 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 05:56:38.525918 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 05:56:38.532465 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 05:56:38.535894 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 05:56:38.539341 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 05:56:38.545766 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 05:56:38.548993 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 05:56:38.552628 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 05:56:38.559152 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 05:56:38.562500 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 05:56:38.566167 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 05:56:38.572353 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1914 05:56:38.572908 Total UI for P1: 0, mck2ui 16
1915 05:56:38.579705 best dqsien dly found for B1: ( 0, 14, 2)
1916 05:56:38.582476 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 05:56:38.585971 Total UI for P1: 0, mck2ui 16
1918 05:56:38.589814 best dqsien dly found for B0: ( 0, 14, 4)
1919 05:56:38.592711 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1920 05:56:38.596048 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1921 05:56:38.596620
1922 05:56:38.599254 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1923 05:56:38.602851 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1924 05:56:38.606120 [Gating] SW calibration Done
1925 05:56:38.606688 ==
1926 05:56:38.609617 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 05:56:38.613147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 05:56:38.613718 ==
1929 05:56:38.615940 RX Vref Scan: 0
1930 05:56:38.616522
1931 05:56:38.616904 RX Vref 0 -> 0, step: 1
1932 05:56:38.617259
1933 05:56:38.619711 RX Delay -130 -> 252, step: 16
1934 05:56:38.626278 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1935 05:56:38.629470 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1936 05:56:38.632722 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1937 05:56:38.635691 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1938 05:56:38.639497 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1939 05:56:38.642466 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1940 05:56:38.648984 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1941 05:56:38.652418 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1942 05:56:38.655918 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1943 05:56:38.659394 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1944 05:56:38.662744 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1945 05:56:38.669475 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1946 05:56:38.672640 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1947 05:56:38.675645 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1948 05:56:38.679369 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1949 05:56:38.686085 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1950 05:56:38.686650 ==
1951 05:56:38.689449 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 05:56:38.692539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 05:56:38.693107 ==
1954 05:56:38.693481 DQS Delay:
1955 05:56:38.695827 DQS0 = 0, DQS1 = 0
1956 05:56:38.696299 DQM Delay:
1957 05:56:38.698852 DQM0 = 88, DQM1 = 84
1958 05:56:38.699319 DQ Delay:
1959 05:56:38.702322 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1960 05:56:38.705623 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1961 05:56:38.709097 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1962 05:56:38.712650 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1963 05:56:38.713214
1964 05:56:38.713584
1965 05:56:38.713924 ==
1966 05:56:38.715312 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 05:56:38.718801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 05:56:38.719270 ==
1969 05:56:38.722221
1970 05:56:38.722788
1971 05:56:38.723159 TX Vref Scan disable
1972 05:56:38.725735 == TX Byte 0 ==
1973 05:56:38.729186 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1974 05:56:38.732210 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1975 05:56:38.735214 == TX Byte 1 ==
1976 05:56:38.738890 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1977 05:56:38.742011 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1978 05:56:38.742481 ==
1979 05:56:38.745687 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 05:56:38.752208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 05:56:38.752782 ==
1982 05:56:38.764484 TX Vref=22, minBit 8, minWin=27, winSum=451
1983 05:56:38.767648 TX Vref=24, minBit 8, minWin=28, winSum=459
1984 05:56:38.770638 TX Vref=26, minBit 13, minWin=27, winSum=456
1985 05:56:38.774126 TX Vref=28, minBit 8, minWin=27, winSum=460
1986 05:56:38.777903 TX Vref=30, minBit 8, minWin=28, winSum=461
1987 05:56:38.780785 TX Vref=32, minBit 8, minWin=28, winSum=459
1988 05:56:38.787319 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
1989 05:56:38.787787
1990 05:56:38.790802 Final TX Range 1 Vref 30
1991 05:56:38.791278
1992 05:56:38.791667 ==
1993 05:56:38.794386 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 05:56:38.797629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 05:56:38.798250 ==
1996 05:56:38.798633
1997 05:56:38.800939
1998 05:56:38.801405 TX Vref Scan disable
1999 05:56:38.804717 == TX Byte 0 ==
2000 05:56:38.808083 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2001 05:56:38.810999 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2002 05:56:38.814666 == TX Byte 1 ==
2003 05:56:38.817414 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2004 05:56:38.820632 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2005 05:56:38.824315
2006 05:56:38.824881 [DATLAT]
2007 05:56:38.825250 Freq=800, CH1 RK1
2008 05:56:38.825594
2009 05:56:38.827526 DATLAT Default: 0xa
2010 05:56:38.827993 0, 0xFFFF, sum = 0
2011 05:56:38.830713 1, 0xFFFF, sum = 0
2012 05:56:38.831293 2, 0xFFFF, sum = 0
2013 05:56:38.834312 3, 0xFFFF, sum = 0
2014 05:56:38.837425 4, 0xFFFF, sum = 0
2015 05:56:38.837898 5, 0xFFFF, sum = 0
2016 05:56:38.840749 6, 0xFFFF, sum = 0
2017 05:56:38.841328 7, 0xFFFF, sum = 0
2018 05:56:38.844589 8, 0xFFFF, sum = 0
2019 05:56:38.845163 9, 0x0, sum = 1
2020 05:56:38.845539 10, 0x0, sum = 2
2021 05:56:38.847675 11, 0x0, sum = 3
2022 05:56:38.848255 12, 0x0, sum = 4
2023 05:56:38.850810 best_step = 10
2024 05:56:38.851277
2025 05:56:38.851742 ==
2026 05:56:38.853784 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 05:56:38.857530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 05:56:38.858135 ==
2029 05:56:38.860969 RX Vref Scan: 0
2030 05:56:38.861543
2031 05:56:38.861919 RX Vref 0 -> 0, step: 1
2032 05:56:38.862327
2033 05:56:38.863839 RX Delay -95 -> 252, step: 8
2034 05:56:38.871025 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2035 05:56:38.874429 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2036 05:56:38.877802 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2037 05:56:38.881248 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2038 05:56:38.884490 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2039 05:56:38.891278 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2040 05:56:38.894520 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2041 05:56:38.898290 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2042 05:56:38.901407 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2043 05:56:38.904804 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2044 05:56:38.908221 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2045 05:56:38.914778 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2046 05:56:38.917973 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2047 05:56:38.921717 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2048 05:56:38.924415 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2049 05:56:38.928179 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2050 05:56:38.931587 ==
2051 05:56:38.934849 Dram Type= 6, Freq= 0, CH_1, rank 1
2052 05:56:38.938235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2053 05:56:38.938833 ==
2054 05:56:38.939210 DQS Delay:
2055 05:56:38.941240 DQS0 = 0, DQS1 = 0
2056 05:56:38.941805 DQM Delay:
2057 05:56:38.944805 DQM0 = 91, DQM1 = 84
2058 05:56:38.945269 DQ Delay:
2059 05:56:38.947942 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2060 05:56:38.951357 DQ4 =96, DQ5 =108, DQ6 =96, DQ7 =88
2061 05:56:38.954585 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2062 05:56:38.957881 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =96
2063 05:56:38.958392
2064 05:56:38.958762
2065 05:56:38.964945 [DQSOSCAuto] RK1, (LSB)MR18= 0x350a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
2066 05:56:38.967815 CH1 RK1: MR19=606, MR18=350A
2067 05:56:38.974698 CH1_RK1: MR19=0x606, MR18=0x350A, DQSOSC=396, MR23=63, INC=94, DEC=62
2068 05:56:38.978053 [RxdqsGatingPostProcess] freq 800
2069 05:56:38.981200 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2070 05:56:38.984458 Pre-setting of DQS Precalculation
2071 05:56:38.991388 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2072 05:56:38.998039 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2073 05:56:39.004549 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2074 05:56:39.005126
2075 05:56:39.005496
2076 05:56:39.007841 [Calibration Summary] 1600 Mbps
2077 05:56:39.011481 CH 0, Rank 0
2078 05:56:39.012050 SW Impedance : PASS
2079 05:56:39.014833 DUTY Scan : NO K
2080 05:56:39.015401 ZQ Calibration : PASS
2081 05:56:39.018198 Jitter Meter : NO K
2082 05:56:39.021475 CBT Training : PASS
2083 05:56:39.022088 Write leveling : PASS
2084 05:56:39.024834 RX DQS gating : PASS
2085 05:56:39.028357 RX DQ/DQS(RDDQC) : PASS
2086 05:56:39.028932 TX DQ/DQS : PASS
2087 05:56:39.031364 RX DATLAT : PASS
2088 05:56:39.034315 RX DQ/DQS(Engine): PASS
2089 05:56:39.034783 TX OE : NO K
2090 05:56:39.037902 All Pass.
2091 05:56:39.038517
2092 05:56:39.038896 CH 0, Rank 1
2093 05:56:39.041267 SW Impedance : PASS
2094 05:56:39.041734 DUTY Scan : NO K
2095 05:56:39.044727 ZQ Calibration : PASS
2096 05:56:39.047763 Jitter Meter : NO K
2097 05:56:39.048237 CBT Training : PASS
2098 05:56:39.051622 Write leveling : PASS
2099 05:56:39.052224 RX DQS gating : PASS
2100 05:56:39.054923 RX DQ/DQS(RDDQC) : PASS
2101 05:56:39.057925 TX DQ/DQS : PASS
2102 05:56:39.058531 RX DATLAT : PASS
2103 05:56:39.061649 RX DQ/DQS(Engine): PASS
2104 05:56:39.064662 TX OE : NO K
2105 05:56:39.065238 All Pass.
2106 05:56:39.065635
2107 05:56:39.066047 CH 1, Rank 0
2108 05:56:39.068531 SW Impedance : PASS
2109 05:56:39.071127 DUTY Scan : NO K
2110 05:56:39.071603 ZQ Calibration : PASS
2111 05:56:39.074870 Jitter Meter : NO K
2112 05:56:39.077984 CBT Training : PASS
2113 05:56:39.078471 Write leveling : PASS
2114 05:56:39.081215 RX DQS gating : PASS
2115 05:56:39.084539 RX DQ/DQS(RDDQC) : PASS
2116 05:56:39.085161 TX DQ/DQS : PASS
2117 05:56:39.088037 RX DATLAT : PASS
2118 05:56:39.088603 RX DQ/DQS(Engine): PASS
2119 05:56:39.091565 TX OE : NO K
2120 05:56:39.092135 All Pass.
2121 05:56:39.092514
2122 05:56:39.094874 CH 1, Rank 1
2123 05:56:39.095402 SW Impedance : PASS
2124 05:56:39.098329 DUTY Scan : NO K
2125 05:56:39.101608 ZQ Calibration : PASS
2126 05:56:39.102234 Jitter Meter : NO K
2127 05:56:39.104934 CBT Training : PASS
2128 05:56:39.108469 Write leveling : PASS
2129 05:56:39.108930 RX DQS gating : PASS
2130 05:56:39.112059 RX DQ/DQS(RDDQC) : PASS
2131 05:56:39.114759 TX DQ/DQS : PASS
2132 05:56:39.115233 RX DATLAT : PASS
2133 05:56:39.118246 RX DQ/DQS(Engine): PASS
2134 05:56:39.121813 TX OE : NO K
2135 05:56:39.122413 All Pass.
2136 05:56:39.122789
2137 05:56:39.123137 DramC Write-DBI off
2138 05:56:39.125182 PER_BANK_REFRESH: Hybrid Mode
2139 05:56:39.128275 TX_TRACKING: ON
2140 05:56:39.131480 [GetDramInforAfterCalByMRR] Vendor 6.
2141 05:56:39.135141 [GetDramInforAfterCalByMRR] Revision 606.
2142 05:56:39.138264 [GetDramInforAfterCalByMRR] Revision 2 0.
2143 05:56:39.138822 MR0 0x3b3b
2144 05:56:39.141563 MR8 0x5151
2145 05:56:39.144764 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2146 05:56:39.145244
2147 05:56:39.145752 MR0 0x3b3b
2148 05:56:39.146269 MR8 0x5151
2149 05:56:39.148197 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2150 05:56:39.148770
2151 05:56:39.158085 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2152 05:56:39.161412 [FAST_K] Save calibration result to emmc
2153 05:56:39.165139 [FAST_K] Save calibration result to emmc
2154 05:56:39.168331 dram_init: config_dvfs: 1
2155 05:56:39.171376 dramc_set_vcore_voltage set vcore to 662500
2156 05:56:39.175311 Read voltage for 1200, 2
2157 05:56:39.175884 Vio18 = 0
2158 05:56:39.176396 Vcore = 662500
2159 05:56:39.178296 Vdram = 0
2160 05:56:39.178769 Vddq = 0
2161 05:56:39.179269 Vmddr = 0
2162 05:56:39.184741 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2163 05:56:39.188690 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2164 05:56:39.191475 MEM_TYPE=3, freq_sel=15
2165 05:56:39.195305 sv_algorithm_assistance_LP4_1600
2166 05:56:39.198526 ============ PULL DRAM RESETB DOWN ============
2167 05:56:39.201536 ========== PULL DRAM RESETB DOWN end =========
2168 05:56:39.208164 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2169 05:56:39.211637 ===================================
2170 05:56:39.215104 LPDDR4 DRAM CONFIGURATION
2171 05:56:39.218490 ===================================
2172 05:56:39.218908 EX_ROW_EN[0] = 0x0
2173 05:56:39.221513 EX_ROW_EN[1] = 0x0
2174 05:56:39.221929 LP4Y_EN = 0x0
2175 05:56:39.225373 WORK_FSP = 0x0
2176 05:56:39.225898 WL = 0x4
2177 05:56:39.228831 RL = 0x4
2178 05:56:39.229358 BL = 0x2
2179 05:56:39.231802 RPST = 0x0
2180 05:56:39.232366 RD_PRE = 0x0
2181 05:56:39.235333 WR_PRE = 0x1
2182 05:56:39.235896 WR_PST = 0x0
2183 05:56:39.238109 DBI_WR = 0x0
2184 05:56:39.238569 DBI_RD = 0x0
2185 05:56:39.241815 OTF = 0x1
2186 05:56:39.245381 ===================================
2187 05:56:39.248635 ===================================
2188 05:56:39.249200 ANA top config
2189 05:56:39.251722 ===================================
2190 05:56:39.254889 DLL_ASYNC_EN = 0
2191 05:56:39.258300 ALL_SLAVE_EN = 0
2192 05:56:39.261289 NEW_RANK_MODE = 1
2193 05:56:39.261719 DLL_IDLE_MODE = 1
2194 05:56:39.265104 LP45_APHY_COMB_EN = 1
2195 05:56:39.268170 TX_ODT_DIS = 1
2196 05:56:39.271702 NEW_8X_MODE = 1
2197 05:56:39.275014 ===================================
2198 05:56:39.278601 ===================================
2199 05:56:39.281559 data_rate = 2400
2200 05:56:39.282012 CKR = 1
2201 05:56:39.285003 DQ_P2S_RATIO = 8
2202 05:56:39.288379 ===================================
2203 05:56:39.291860 CA_P2S_RATIO = 8
2204 05:56:39.295471 DQ_CA_OPEN = 0
2205 05:56:39.298370 DQ_SEMI_OPEN = 0
2206 05:56:39.298803 CA_SEMI_OPEN = 0
2207 05:56:39.301794 CA_FULL_RATE = 0
2208 05:56:39.305080 DQ_CKDIV4_EN = 0
2209 05:56:39.308473 CA_CKDIV4_EN = 0
2210 05:56:39.311799 CA_PREDIV_EN = 0
2211 05:56:39.315256 PH8_DLY = 17
2212 05:56:39.315732 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2213 05:56:39.318740 DQ_AAMCK_DIV = 4
2214 05:56:39.321480 CA_AAMCK_DIV = 4
2215 05:56:39.324898 CA_ADMCK_DIV = 4
2216 05:56:39.328572 DQ_TRACK_CA_EN = 0
2217 05:56:39.331504 CA_PICK = 1200
2218 05:56:39.335068 CA_MCKIO = 1200
2219 05:56:39.335489 MCKIO_SEMI = 0
2220 05:56:39.338547 PLL_FREQ = 2366
2221 05:56:39.342003 DQ_UI_PI_RATIO = 32
2222 05:56:39.344981 CA_UI_PI_RATIO = 0
2223 05:56:39.348422 ===================================
2224 05:56:39.351531 ===================================
2225 05:56:39.355133 memory_type:LPDDR4
2226 05:56:39.355359 GP_NUM : 10
2227 05:56:39.358716 SRAM_EN : 1
2228 05:56:39.358940 MD32_EN : 0
2229 05:56:39.361650 ===================================
2230 05:56:39.364965 [ANA_INIT] >>>>>>>>>>>>>>
2231 05:56:39.368461 <<<<<< [CONFIGURE PHASE]: ANA_TX
2232 05:56:39.371793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2233 05:56:39.375336 ===================================
2234 05:56:39.378606 data_rate = 2400,PCW = 0X5b00
2235 05:56:39.382138 ===================================
2236 05:56:39.385133 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2237 05:56:39.392142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2238 05:56:39.395668 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2239 05:56:39.401904 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2240 05:56:39.405428 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2241 05:56:39.409126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2242 05:56:39.409690 [ANA_INIT] flow start
2243 05:56:39.412208 [ANA_INIT] PLL >>>>>>>>
2244 05:56:39.415769 [ANA_INIT] PLL <<<<<<<<
2245 05:56:39.416335 [ANA_INIT] MIDPI >>>>>>>>
2246 05:56:39.418770 [ANA_INIT] MIDPI <<<<<<<<
2247 05:56:39.422239 [ANA_INIT] DLL >>>>>>>>
2248 05:56:39.422699 [ANA_INIT] DLL <<<<<<<<
2249 05:56:39.425308 [ANA_INIT] flow end
2250 05:56:39.428817 ============ LP4 DIFF to SE enter ============
2251 05:56:39.434924 ============ LP4 DIFF to SE exit ============
2252 05:56:39.435474 [ANA_INIT] <<<<<<<<<<<<<
2253 05:56:39.438705 [Flow] Enable top DCM control >>>>>
2254 05:56:39.442116 [Flow] Enable top DCM control <<<<<
2255 05:56:39.445579 Enable DLL master slave shuffle
2256 05:56:39.451981 ==============================================================
2257 05:56:39.452549 Gating Mode config
2258 05:56:39.458758 ==============================================================
2259 05:56:39.459329 Config description:
2260 05:56:39.468485 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2261 05:56:39.475309 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2262 05:56:39.481983 SELPH_MODE 0: By rank 1: By Phase
2263 05:56:39.485196 ==============================================================
2264 05:56:39.488631 GAT_TRACK_EN = 1
2265 05:56:39.491871 RX_GATING_MODE = 2
2266 05:56:39.495098 RX_GATING_TRACK_MODE = 2
2267 05:56:39.498156 SELPH_MODE = 1
2268 05:56:39.501824 PICG_EARLY_EN = 1
2269 05:56:39.505070 VALID_LAT_VALUE = 1
2270 05:56:39.511619 ==============================================================
2271 05:56:39.515433 Enter into Gating configuration >>>>
2272 05:56:39.518407 Exit from Gating configuration <<<<
2273 05:56:39.521920 Enter into DVFS_PRE_config >>>>>
2274 05:56:39.531984 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2275 05:56:39.535143 Exit from DVFS_PRE_config <<<<<
2276 05:56:39.538881 Enter into PICG configuration >>>>
2277 05:56:39.541873 Exit from PICG configuration <<<<
2278 05:56:39.542460 [RX_INPUT] configuration >>>>>
2279 05:56:39.545058 [RX_INPUT] configuration <<<<<
2280 05:56:39.551903 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2281 05:56:39.555083 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2282 05:56:39.561812 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2283 05:56:39.568492 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2284 05:56:39.575179 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2285 05:56:39.582121 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2286 05:56:39.584746 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2287 05:56:39.588403 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2288 05:56:39.594885 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2289 05:56:39.598393 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2290 05:56:39.601505 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2291 05:56:39.604898 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2292 05:56:39.608224 ===================================
2293 05:56:39.611328 LPDDR4 DRAM CONFIGURATION
2294 05:56:39.614614 ===================================
2295 05:56:39.618553 EX_ROW_EN[0] = 0x0
2296 05:56:39.619118 EX_ROW_EN[1] = 0x0
2297 05:56:39.621810 LP4Y_EN = 0x0
2298 05:56:39.622305 WORK_FSP = 0x0
2299 05:56:39.624839 WL = 0x4
2300 05:56:39.625429 RL = 0x4
2301 05:56:39.628476 BL = 0x2
2302 05:56:39.629048 RPST = 0x0
2303 05:56:39.631489 RD_PRE = 0x0
2304 05:56:39.632056 WR_PRE = 0x1
2305 05:56:39.634691 WR_PST = 0x0
2306 05:56:39.635160 DBI_WR = 0x0
2307 05:56:39.638549 DBI_RD = 0x0
2308 05:56:39.639125 OTF = 0x1
2309 05:56:39.641910 ===================================
2310 05:56:39.648491 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2311 05:56:39.651887 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2312 05:56:39.654639 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2313 05:56:39.658300 ===================================
2314 05:56:39.661742 LPDDR4 DRAM CONFIGURATION
2315 05:56:39.664767 ===================================
2316 05:56:39.668217 EX_ROW_EN[0] = 0x10
2317 05:56:39.668797 EX_ROW_EN[1] = 0x0
2318 05:56:39.671655 LP4Y_EN = 0x0
2319 05:56:39.672214 WORK_FSP = 0x0
2320 05:56:39.674931 WL = 0x4
2321 05:56:39.675399 RL = 0x4
2322 05:56:39.678340 BL = 0x2
2323 05:56:39.678947 RPST = 0x0
2324 05:56:39.681705 RD_PRE = 0x0
2325 05:56:39.682366 WR_PRE = 0x1
2326 05:56:39.684674 WR_PST = 0x0
2327 05:56:39.685142 DBI_WR = 0x0
2328 05:56:39.688024 DBI_RD = 0x0
2329 05:56:39.688495 OTF = 0x1
2330 05:56:39.691458 ===================================
2331 05:56:39.698249 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2332 05:56:39.698710 ==
2333 05:56:39.701347 Dram Type= 6, Freq= 0, CH_0, rank 0
2334 05:56:39.704793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2335 05:56:39.708161 ==
2336 05:56:39.708579 [Duty_Offset_Calibration]
2337 05:56:39.711518 B0:2 B1:0 CA:1
2338 05:56:39.711981
2339 05:56:39.714565 [DutyScan_Calibration_Flow] k_type=0
2340 05:56:39.722740
2341 05:56:39.723260 ==CLK 0==
2342 05:56:39.725642 Final CLK duty delay cell = -4
2343 05:56:39.729531 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2344 05:56:39.732811 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2345 05:56:39.736106 [-4] AVG Duty = 4953%(X100)
2346 05:56:39.736526
2347 05:56:39.738935 CH0 CLK Duty spec in!! Max-Min= 156%
2348 05:56:39.742655 [DutyScan_Calibration_Flow] ====Done====
2349 05:56:39.743071
2350 05:56:39.745566 [DutyScan_Calibration_Flow] k_type=1
2351 05:56:39.761828
2352 05:56:39.762407 ==DQS 0 ==
2353 05:56:39.764761 Final DQS duty delay cell = 0
2354 05:56:39.768340 [0] MAX Duty = 5187%(X100), DQS PI = 30
2355 05:56:39.771712 [0] MIN Duty = 4938%(X100), DQS PI = 0
2356 05:56:39.772269 [0] AVG Duty = 5062%(X100)
2357 05:56:39.774586
2358 05:56:39.775088 ==DQS 1 ==
2359 05:56:39.778127 Final DQS duty delay cell = -4
2360 05:56:39.781482 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2361 05:56:39.784661 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2362 05:56:39.787796 [-4] AVG Duty = 5015%(X100)
2363 05:56:39.788390
2364 05:56:39.791155 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2365 05:56:39.791854
2366 05:56:39.794435 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2367 05:56:39.798011 [DutyScan_Calibration_Flow] ====Done====
2368 05:56:39.798550
2369 05:56:39.801331 [DutyScan_Calibration_Flow] k_type=3
2370 05:56:39.818297
2371 05:56:39.818844 ==DQM 0 ==
2372 05:56:39.821515 Final DQM duty delay cell = 0
2373 05:56:39.825077 [0] MAX Duty = 5062%(X100), DQS PI = 24
2374 05:56:39.828081 [0] MIN Duty = 4813%(X100), DQS PI = 2
2375 05:56:39.828544 [0] AVG Duty = 4937%(X100)
2376 05:56:39.831866
2377 05:56:39.832416 ==DQM 1 ==
2378 05:56:39.834974 Final DQM duty delay cell = 0
2379 05:56:39.838077 [0] MAX Duty = 5187%(X100), DQS PI = 48
2380 05:56:39.841482 [0] MIN Duty = 5000%(X100), DQS PI = 20
2381 05:56:39.844961 [0] AVG Duty = 5093%(X100)
2382 05:56:39.845420
2383 05:56:39.848051 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2384 05:56:39.848607
2385 05:56:39.851478 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2386 05:56:39.854611 [DutyScan_Calibration_Flow] ====Done====
2387 05:56:39.855162
2388 05:56:39.858103 [DutyScan_Calibration_Flow] k_type=2
2389 05:56:39.874956
2390 05:56:39.875571 ==DQ 0 ==
2391 05:56:39.878079 Final DQ duty delay cell = -4
2392 05:56:39.881773 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2393 05:56:39.884734 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2394 05:56:39.887782 [-4] AVG Duty = 4953%(X100)
2395 05:56:39.888282
2396 05:56:39.888836 ==DQ 1 ==
2397 05:56:39.891482 Final DQ duty delay cell = 4
2398 05:56:39.894594 [4] MAX Duty = 5093%(X100), DQS PI = 4
2399 05:56:39.898320 [4] MIN Duty = 5031%(X100), DQS PI = 0
2400 05:56:39.898890 [4] AVG Duty = 5062%(X100)
2401 05:56:39.901642
2402 05:56:39.902292 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2403 05:56:39.904904
2404 05:56:39.908358 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2405 05:56:39.911638 [DutyScan_Calibration_Flow] ====Done====
2406 05:56:39.912112 ==
2407 05:56:39.915303 Dram Type= 6, Freq= 0, CH_1, rank 0
2408 05:56:39.918549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2409 05:56:39.919122 ==
2410 05:56:39.921820 [Duty_Offset_Calibration]
2411 05:56:39.922482 B0:0 B1:-1 CA:2
2412 05:56:39.922869
2413 05:56:39.924480 [DutyScan_Calibration_Flow] k_type=0
2414 05:56:39.934866
2415 05:56:39.935432 ==CLK 0==
2416 05:56:39.938486 Final CLK duty delay cell = 0
2417 05:56:39.941782 [0] MAX Duty = 5156%(X100), DQS PI = 16
2418 05:56:39.944488 [0] MIN Duty = 4938%(X100), DQS PI = 44
2419 05:56:39.944963 [0] AVG Duty = 5047%(X100)
2420 05:56:39.947958
2421 05:56:39.951722 CH1 CLK Duty spec in!! Max-Min= 218%
2422 05:56:39.954641 [DutyScan_Calibration_Flow] ====Done====
2423 05:56:39.955109
2424 05:56:39.958126 [DutyScan_Calibration_Flow] k_type=1
2425 05:56:39.974412
2426 05:56:39.974980 ==DQS 0 ==
2427 05:56:39.977570 Final DQS duty delay cell = 0
2428 05:56:39.981154 [0] MAX Duty = 5093%(X100), DQS PI = 26
2429 05:56:39.984206 [0] MIN Duty = 4969%(X100), DQS PI = 0
2430 05:56:39.984675 [0] AVG Duty = 5031%(X100)
2431 05:56:39.987842
2432 05:56:39.988455 ==DQS 1 ==
2433 05:56:39.991210 Final DQS duty delay cell = 0
2434 05:56:39.994432 [0] MAX Duty = 5156%(X100), DQS PI = 0
2435 05:56:39.997687 [0] MIN Duty = 4844%(X100), DQS PI = 36
2436 05:56:39.998198 [0] AVG Duty = 5000%(X100)
2437 05:56:39.998573
2438 05:56:40.004471 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2439 05:56:40.005041
2440 05:56:40.007791 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2441 05:56:40.011386 [DutyScan_Calibration_Flow] ====Done====
2442 05:56:40.011953
2443 05:56:40.014658 [DutyScan_Calibration_Flow] k_type=3
2444 05:56:40.031379
2445 05:56:40.031946 ==DQM 0 ==
2446 05:56:40.035163 Final DQM duty delay cell = 4
2447 05:56:40.038702 [4] MAX Duty = 5093%(X100), DQS PI = 20
2448 05:56:40.042024 [4] MIN Duty = 4938%(X100), DQS PI = 44
2449 05:56:40.042602 [4] AVG Duty = 5015%(X100)
2450 05:56:40.045216
2451 05:56:40.045788 ==DQM 1 ==
2452 05:56:40.048552 Final DQM duty delay cell = 0
2453 05:56:40.051781 [0] MAX Duty = 5249%(X100), DQS PI = 60
2454 05:56:40.054903 [0] MIN Duty = 4875%(X100), DQS PI = 36
2455 05:56:40.055477 [0] AVG Duty = 5062%(X100)
2456 05:56:40.058307
2457 05:56:40.061708 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2458 05:56:40.062335
2459 05:56:40.064979 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2460 05:56:40.068833 [DutyScan_Calibration_Flow] ====Done====
2461 05:56:40.069543
2462 05:56:40.071493 [DutyScan_Calibration_Flow] k_type=2
2463 05:56:40.088278
2464 05:56:40.088884 ==DQ 0 ==
2465 05:56:40.091587 Final DQ duty delay cell = 0
2466 05:56:40.094941 [0] MAX Duty = 5062%(X100), DQS PI = 20
2467 05:56:40.098462 [0] MIN Duty = 4938%(X100), DQS PI = 0
2468 05:56:40.099029 [0] AVG Duty = 5000%(X100)
2469 05:56:40.099409
2470 05:56:40.102048 ==DQ 1 ==
2471 05:56:40.105276 Final DQ duty delay cell = 0
2472 05:56:40.108218 [0] MAX Duty = 5031%(X100), DQS PI = 2
2473 05:56:40.111697 [0] MIN Duty = 4813%(X100), DQS PI = 34
2474 05:56:40.112260 [0] AVG Duty = 4922%(X100)
2475 05:56:40.112638
2476 05:56:40.115021 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2477 05:56:40.115588
2478 05:56:40.118111 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2479 05:56:40.124976 [DutyScan_Calibration_Flow] ====Done====
2480 05:56:40.127991 nWR fixed to 30
2481 05:56:40.128559 [ModeRegInit_LP4] CH0 RK0
2482 05:56:40.131663 [ModeRegInit_LP4] CH0 RK1
2483 05:56:40.135046 [ModeRegInit_LP4] CH1 RK0
2484 05:56:40.135676 [ModeRegInit_LP4] CH1 RK1
2485 05:56:40.138334 match AC timing 7
2486 05:56:40.141794 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2487 05:56:40.145004 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2488 05:56:40.151990 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2489 05:56:40.154634 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2490 05:56:40.161580 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2491 05:56:40.162200 ==
2492 05:56:40.164951 Dram Type= 6, Freq= 0, CH_0, rank 0
2493 05:56:40.168305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2494 05:56:40.168874 ==
2495 05:56:40.175097 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2496 05:56:40.177921 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2497 05:56:40.187982 [CA 0] Center 38 (7~69) winsize 63
2498 05:56:40.191349 [CA 1] Center 38 (8~69) winsize 62
2499 05:56:40.194518 [CA 2] Center 35 (5~66) winsize 62
2500 05:56:40.197910 [CA 3] Center 34 (4~65) winsize 62
2501 05:56:40.201626 [CA 4] Center 34 (4~65) winsize 62
2502 05:56:40.204970 [CA 5] Center 33 (3~64) winsize 62
2503 05:56:40.205563
2504 05:56:40.208092 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2505 05:56:40.208661
2506 05:56:40.211414 [CATrainingPosCal] consider 1 rank data
2507 05:56:40.215026 u2DelayCellTimex100 = 270/100 ps
2508 05:56:40.218578 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2509 05:56:40.221223 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2510 05:56:40.224861 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2511 05:56:40.231624 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2512 05:56:40.234950 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2513 05:56:40.238246 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2514 05:56:40.238719
2515 05:56:40.241320 CA PerBit enable=1, Macro0, CA PI delay=33
2516 05:56:40.241792
2517 05:56:40.244999 [CBTSetCACLKResult] CA Dly = 33
2518 05:56:40.245578 CS Dly: 6 (0~37)
2519 05:56:40.245997 ==
2520 05:56:40.248544 Dram Type= 6, Freq= 0, CH_0, rank 1
2521 05:56:40.255098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 05:56:40.255670 ==
2523 05:56:40.258855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2524 05:56:40.265300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2525 05:56:40.273614 [CA 0] Center 39 (8~70) winsize 63
2526 05:56:40.276726 [CA 1] Center 38 (8~69) winsize 62
2527 05:56:40.280024 [CA 2] Center 35 (5~66) winsize 62
2528 05:56:40.283276 [CA 3] Center 35 (5~66) winsize 62
2529 05:56:40.286649 [CA 4] Center 34 (4~65) winsize 62
2530 05:56:40.290136 [CA 5] Center 34 (4~64) winsize 61
2531 05:56:40.290634
2532 05:56:40.293472 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2533 05:56:40.293979
2534 05:56:40.296612 [CATrainingPosCal] consider 2 rank data
2535 05:56:40.299919 u2DelayCellTimex100 = 270/100 ps
2536 05:56:40.303675 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2537 05:56:40.306706 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2538 05:56:40.313504 CA2 delay=35 (5~66),Diff = 1 PI (4 cell)
2539 05:56:40.316826 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
2540 05:56:40.319930 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2541 05:56:40.323670 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2542 05:56:40.324194
2543 05:56:40.327080 CA PerBit enable=1, Macro0, CA PI delay=34
2544 05:56:40.327610
2545 05:56:40.330556 [CBTSetCACLKResult] CA Dly = 34
2546 05:56:40.331084 CS Dly: 7 (0~39)
2547 05:56:40.331430
2548 05:56:40.333832 ----->DramcWriteLeveling(PI) begin...
2549 05:56:40.336951 ==
2550 05:56:40.340160 Dram Type= 6, Freq= 0, CH_0, rank 0
2551 05:56:40.343696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2552 05:56:40.344223 ==
2553 05:56:40.346836 Write leveling (Byte 0): 34 => 34
2554 05:56:40.350214 Write leveling (Byte 1): 31 => 31
2555 05:56:40.353416 DramcWriteLeveling(PI) end<-----
2556 05:56:40.353799
2557 05:56:40.354171 ==
2558 05:56:40.356778 Dram Type= 6, Freq= 0, CH_0, rank 0
2559 05:56:40.360618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2560 05:56:40.361142 ==
2561 05:56:40.363579 [Gating] SW mode calibration
2562 05:56:40.370107 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2563 05:56:40.373575 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2564 05:56:40.380309 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2565 05:56:40.383596 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
2566 05:56:40.386775 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 05:56:40.393388 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2568 05:56:40.396987 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2569 05:56:40.400308 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2570 05:56:40.406803 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2571 05:56:40.410156 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2572 05:56:40.413544 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2573 05:56:40.420287 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 05:56:40.423603 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 05:56:40.427010 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 05:56:40.433441 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 05:56:40.436851 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 05:56:40.440486 1 0 24 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
2579 05:56:40.447354 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2580 05:56:40.450066 1 1 0 | B1->B0 | 3635 4646 | 1 0 | (0 0) (0 0)
2581 05:56:40.453736 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 05:56:40.457353 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 05:56:40.463725 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 05:56:40.466951 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 05:56:40.470410 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 05:56:40.476801 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2587 05:56:40.480375 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2588 05:56:40.483930 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2589 05:56:40.490181 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 05:56:40.493885 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 05:56:40.496891 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 05:56:40.503682 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 05:56:40.507046 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 05:56:40.510532 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 05:56:40.516986 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 05:56:40.520236 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 05:56:40.523489 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 05:56:40.530385 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 05:56:40.533854 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 05:56:40.537175 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 05:56:40.540072 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 05:56:40.546930 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2603 05:56:40.550033 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2604 05:56:40.553498 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2605 05:56:40.557005 Total UI for P1: 0, mck2ui 16
2606 05:56:40.560266 best dqsien dly found for B0: ( 1, 3, 26)
2607 05:56:40.567181 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 05:56:40.570685 Total UI for P1: 0, mck2ui 16
2609 05:56:40.573692 best dqsien dly found for B1: ( 1, 4, 0)
2610 05:56:40.577186 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2611 05:56:40.580591 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2612 05:56:40.581186
2613 05:56:40.583671 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2614 05:56:40.586992 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2615 05:56:40.590807 [Gating] SW calibration Done
2616 05:56:40.591390 ==
2617 05:56:40.593606 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 05:56:40.597295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 05:56:40.597877 ==
2620 05:56:40.600771 RX Vref Scan: 0
2621 05:56:40.601343
2622 05:56:40.601717 RX Vref 0 -> 0, step: 1
2623 05:56:40.602112
2624 05:56:40.603923 RX Delay -40 -> 252, step: 8
2625 05:56:40.606990 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2626 05:56:40.613613 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2627 05:56:40.616778 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2628 05:56:40.620799 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2629 05:56:40.623667 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2630 05:56:40.626988 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2631 05:56:40.634072 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2632 05:56:40.637464 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2633 05:56:40.640568 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2634 05:56:40.644213 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2635 05:56:40.647683 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2636 05:56:40.650891 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2637 05:56:40.657443 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2638 05:56:40.660876 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2639 05:56:40.664377 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2640 05:56:40.667395 iDelay=208, Bit 15, Center 119 (56 ~ 183) 128
2641 05:56:40.667866 ==
2642 05:56:40.670746 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 05:56:40.677424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 05:56:40.678017 ==
2645 05:56:40.678399 DQS Delay:
2646 05:56:40.680805 DQS0 = 0, DQS1 = 0
2647 05:56:40.681374 DQM Delay:
2648 05:56:40.681753 DQM0 = 122, DQM1 = 110
2649 05:56:40.684201 DQ Delay:
2650 05:56:40.687286 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2651 05:56:40.690487 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2652 05:56:40.693971 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2653 05:56:40.697735 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =119
2654 05:56:40.698356
2655 05:56:40.698737
2656 05:56:40.699151 ==
2657 05:56:40.700474 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 05:56:40.704113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 05:56:40.707042 ==
2660 05:56:40.707513
2661 05:56:40.707885
2662 05:56:40.708230 TX Vref Scan disable
2663 05:56:40.710386 == TX Byte 0 ==
2664 05:56:40.713998 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2665 05:56:40.717314 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2666 05:56:40.720665 == TX Byte 1 ==
2667 05:56:40.724319 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2668 05:56:40.727118 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2669 05:56:40.727584 ==
2670 05:56:40.730870 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 05:56:40.737227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 05:56:40.737821 ==
2673 05:56:40.748082 TX Vref=22, minBit 7, minWin=23, winSum=405
2674 05:56:40.751356 TX Vref=24, minBit 6, minWin=24, winSum=413
2675 05:56:40.754746 TX Vref=26, minBit 7, minWin=24, winSum=415
2676 05:56:40.758344 TX Vref=28, minBit 1, minWin=24, winSum=416
2677 05:56:40.761193 TX Vref=30, minBit 3, minWin=25, winSum=421
2678 05:56:40.764492 TX Vref=32, minBit 1, minWin=24, winSum=417
2679 05:56:40.771400 [TxChooseVref] Worse bit 3, Min win 25, Win sum 421, Final Vref 30
2680 05:56:40.772008
2681 05:56:40.774868 Final TX Range 1 Vref 30
2682 05:56:40.775513
2683 05:56:40.775891 ==
2684 05:56:40.778155 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 05:56:40.781500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 05:56:40.782111 ==
2687 05:56:40.782495
2688 05:56:40.782842
2689 05:56:40.785118 TX Vref Scan disable
2690 05:56:40.787771 == TX Byte 0 ==
2691 05:56:40.791754 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2692 05:56:40.794785 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2693 05:56:40.797785 == TX Byte 1 ==
2694 05:56:40.801750 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2695 05:56:40.805247 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2696 05:56:40.805832
2697 05:56:40.808104 [DATLAT]
2698 05:56:40.808664 Freq=1200, CH0 RK0
2699 05:56:40.809042
2700 05:56:40.811424 DATLAT Default: 0xd
2701 05:56:40.811894 0, 0xFFFF, sum = 0
2702 05:56:40.815336 1, 0xFFFF, sum = 0
2703 05:56:40.815910 2, 0xFFFF, sum = 0
2704 05:56:40.818268 3, 0xFFFF, sum = 0
2705 05:56:40.818842 4, 0xFFFF, sum = 0
2706 05:56:40.821671 5, 0xFFFF, sum = 0
2707 05:56:40.822363 6, 0xFFFF, sum = 0
2708 05:56:40.825237 7, 0xFFFF, sum = 0
2709 05:56:40.825810 8, 0xFFFF, sum = 0
2710 05:56:40.828602 9, 0xFFFF, sum = 0
2711 05:56:40.829176 10, 0xFFFF, sum = 0
2712 05:56:40.831743 11, 0xFFFF, sum = 0
2713 05:56:40.834602 12, 0x0, sum = 1
2714 05:56:40.835074 13, 0x0, sum = 2
2715 05:56:40.835485 14, 0x0, sum = 3
2716 05:56:40.838104 15, 0x0, sum = 4
2717 05:56:40.838579 best_step = 13
2718 05:56:40.838982
2719 05:56:40.839384 ==
2720 05:56:40.841261 Dram Type= 6, Freq= 0, CH_0, rank 0
2721 05:56:40.848232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2722 05:56:40.848811 ==
2723 05:56:40.849194 RX Vref Scan: 1
2724 05:56:40.849577
2725 05:56:40.851210 Set Vref Range= 32 -> 127
2726 05:56:40.851862
2727 05:56:40.854458 RX Vref 32 -> 127, step: 1
2728 05:56:40.854925
2729 05:56:40.858124 RX Delay -13 -> 252, step: 4
2730 05:56:40.858702
2731 05:56:40.861662 Set Vref, RX VrefLevel [Byte0]: 32
2732 05:56:40.864836 [Byte1]: 32
2733 05:56:40.865412
2734 05:56:40.868147 Set Vref, RX VrefLevel [Byte0]: 33
2735 05:56:40.871293 [Byte1]: 33
2736 05:56:40.871764
2737 05:56:40.874923 Set Vref, RX VrefLevel [Byte0]: 34
2738 05:56:40.878090 [Byte1]: 34
2739 05:56:40.882140
2740 05:56:40.882610 Set Vref, RX VrefLevel [Byte0]: 35
2741 05:56:40.885306 [Byte1]: 35
2742 05:56:40.890242
2743 05:56:40.890808 Set Vref, RX VrefLevel [Byte0]: 36
2744 05:56:40.892977 [Byte1]: 36
2745 05:56:40.897825
2746 05:56:40.898421 Set Vref, RX VrefLevel [Byte0]: 37
2747 05:56:40.901238 [Byte1]: 37
2748 05:56:40.905750
2749 05:56:40.906389 Set Vref, RX VrefLevel [Byte0]: 38
2750 05:56:40.909010 [Byte1]: 38
2751 05:56:40.913722
2752 05:56:40.914330 Set Vref, RX VrefLevel [Byte0]: 39
2753 05:56:40.917084 [Byte1]: 39
2754 05:56:40.921713
2755 05:56:40.922443 Set Vref, RX VrefLevel [Byte0]: 40
2756 05:56:40.924807 [Byte1]: 40
2757 05:56:40.929450
2758 05:56:40.930036 Set Vref, RX VrefLevel [Byte0]: 41
2759 05:56:40.932773 [Byte1]: 41
2760 05:56:40.937281
2761 05:56:40.937846 Set Vref, RX VrefLevel [Byte0]: 42
2762 05:56:40.940630 [Byte1]: 42
2763 05:56:40.945345
2764 05:56:40.945808 Set Vref, RX VrefLevel [Byte0]: 43
2765 05:56:40.948293 [Byte1]: 43
2766 05:56:40.952909
2767 05:56:40.953371 Set Vref, RX VrefLevel [Byte0]: 44
2768 05:56:40.956208 [Byte1]: 44
2769 05:56:40.960833
2770 05:56:40.961399 Set Vref, RX VrefLevel [Byte0]: 45
2771 05:56:40.964203 [Byte1]: 45
2772 05:56:40.968889
2773 05:56:40.969444 Set Vref, RX VrefLevel [Byte0]: 46
2774 05:56:40.972022 [Byte1]: 46
2775 05:56:40.976595
2776 05:56:40.977159 Set Vref, RX VrefLevel [Byte0]: 47
2777 05:56:40.979932 [Byte1]: 47
2778 05:56:40.984739
2779 05:56:40.985343 Set Vref, RX VrefLevel [Byte0]: 48
2780 05:56:40.988056 [Byte1]: 48
2781 05:56:40.992366
2782 05:56:40.992930 Set Vref, RX VrefLevel [Byte0]: 49
2783 05:56:40.995751 [Byte1]: 49
2784 05:56:41.000103
2785 05:56:41.000569 Set Vref, RX VrefLevel [Byte0]: 50
2786 05:56:41.003341 [Byte1]: 50
2787 05:56:41.008268
2788 05:56:41.008732 Set Vref, RX VrefLevel [Byte0]: 51
2789 05:56:41.011189 [Byte1]: 51
2790 05:56:41.016376
2791 05:56:41.016939 Set Vref, RX VrefLevel [Byte0]: 52
2792 05:56:41.019352 [Byte1]: 52
2793 05:56:41.024050
2794 05:56:41.024522 Set Vref, RX VrefLevel [Byte0]: 53
2795 05:56:41.027560 [Byte1]: 53
2796 05:56:41.032157
2797 05:56:41.032717 Set Vref, RX VrefLevel [Byte0]: 54
2798 05:56:41.034837 [Byte1]: 54
2799 05:56:41.040057
2800 05:56:41.040626 Set Vref, RX VrefLevel [Byte0]: 55
2801 05:56:41.042925 [Byte1]: 55
2802 05:56:41.047614
2803 05:56:41.048215 Set Vref, RX VrefLevel [Byte0]: 56
2804 05:56:41.051128 [Byte1]: 56
2805 05:56:41.055653
2806 05:56:41.056215 Set Vref, RX VrefLevel [Byte0]: 57
2807 05:56:41.058859 [Byte1]: 57
2808 05:56:41.063305
2809 05:56:41.063772 Set Vref, RX VrefLevel [Byte0]: 58
2810 05:56:41.066625 [Byte1]: 58
2811 05:56:41.071159
2812 05:56:41.071640 Set Vref, RX VrefLevel [Byte0]: 59
2813 05:56:41.074604 [Byte1]: 59
2814 05:56:41.079167
2815 05:56:41.079729 Set Vref, RX VrefLevel [Byte0]: 60
2816 05:56:41.082499 [Byte1]: 60
2817 05:56:41.086851
2818 05:56:41.087409 Set Vref, RX VrefLevel [Byte0]: 61
2819 05:56:41.090557 [Byte1]: 61
2820 05:56:41.094823
2821 05:56:41.095489 Set Vref, RX VrefLevel [Byte0]: 62
2822 05:56:41.098286 [Byte1]: 62
2823 05:56:41.102650
2824 05:56:41.103112 Set Vref, RX VrefLevel [Byte0]: 63
2825 05:56:41.106075 [Byte1]: 63
2826 05:56:41.110866
2827 05:56:41.111429 Set Vref, RX VrefLevel [Byte0]: 64
2828 05:56:41.114165 [Byte1]: 64
2829 05:56:41.118894
2830 05:56:41.119461 Set Vref, RX VrefLevel [Byte0]: 65
2831 05:56:41.122052 [Byte1]: 65
2832 05:56:41.126659
2833 05:56:41.127222 Set Vref, RX VrefLevel [Byte0]: 66
2834 05:56:41.129818 [Byte1]: 66
2835 05:56:41.134401
2836 05:56:41.134962 Set Vref, RX VrefLevel [Byte0]: 67
2837 05:56:41.137869 [Byte1]: 67
2838 05:56:41.142329
2839 05:56:41.142795 Set Vref, RX VrefLevel [Byte0]: 68
2840 05:56:41.145749 [Byte1]: 68
2841 05:56:41.150159
2842 05:56:41.150546 Set Vref, RX VrefLevel [Byte0]: 69
2843 05:56:41.153583 [Byte1]: 69
2844 05:56:41.158369
2845 05:56:41.158888 Set Vref, RX VrefLevel [Byte0]: 70
2846 05:56:41.161429 [Byte1]: 70
2847 05:56:41.166204
2848 05:56:41.166746 Final RX Vref Byte 0 = 57 to rank0
2849 05:56:41.169249 Final RX Vref Byte 1 = 49 to rank0
2850 05:56:41.172482 Final RX Vref Byte 0 = 57 to rank1
2851 05:56:41.175999 Final RX Vref Byte 1 = 49 to rank1==
2852 05:56:41.179183 Dram Type= 6, Freq= 0, CH_0, rank 0
2853 05:56:41.186050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 05:56:41.186585 ==
2855 05:56:41.186928 DQS Delay:
2856 05:56:41.187247 DQS0 = 0, DQS1 = 0
2857 05:56:41.189539 DQM Delay:
2858 05:56:41.190092 DQM0 = 122, DQM1 = 109
2859 05:56:41.192706 DQ Delay:
2860 05:56:41.195789 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =118
2861 05:56:41.199581 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2862 05:56:41.202381 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2863 05:56:41.206091 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2864 05:56:41.206609
2865 05:56:41.206945
2866 05:56:41.212883 [DQSOSCAuto] RK0, (LSB)MR18= 0x603, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 407 ps
2867 05:56:41.216191 CH0 RK0: MR19=404, MR18=603
2868 05:56:41.222437 CH0_RK0: MR19=0x404, MR18=0x603, DQSOSC=407, MR23=63, INC=39, DEC=26
2869 05:56:41.222960
2870 05:56:41.225763 ----->DramcWriteLeveling(PI) begin...
2871 05:56:41.226230 ==
2872 05:56:41.229553 Dram Type= 6, Freq= 0, CH_0, rank 1
2873 05:56:41.232897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2874 05:56:41.233425 ==
2875 05:56:41.236129 Write leveling (Byte 0): 35 => 35
2876 05:56:41.239009 Write leveling (Byte 1): 29 => 29
2877 05:56:41.242544 DramcWriteLeveling(PI) end<-----
2878 05:56:41.243068
2879 05:56:41.243407 ==
2880 05:56:41.245843 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 05:56:41.249633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 05:56:41.253028 ==
2883 05:56:41.253554 [Gating] SW mode calibration
2884 05:56:41.262827 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2885 05:56:41.266512 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2886 05:56:41.269673 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2887 05:56:41.276463 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 05:56:41.279377 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 05:56:41.282921 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 05:56:41.289504 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 05:56:41.292892 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 05:56:41.295834 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2893 05:56:41.303075 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
2894 05:56:41.306363 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 05:56:41.310047 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 05:56:41.312969 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 05:56:41.319687 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 05:56:41.323134 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 05:56:41.326332 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 05:56:41.333471 1 0 24 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
2901 05:56:41.336302 1 0 28 | B1->B0 | 3333 3b3b | 1 0 | (0 0) (0 0)
2902 05:56:41.339764 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 05:56:41.346731 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 05:56:41.350149 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 05:56:41.353100 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 05:56:41.360105 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 05:56:41.363209 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 05:56:41.366636 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 05:56:41.373281 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2910 05:56:41.376342 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2911 05:56:41.380258 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 05:56:41.383128 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 05:56:41.390196 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 05:56:41.393275 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 05:56:41.396496 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 05:56:41.403145 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 05:56:41.406562 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 05:56:41.409823 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 05:56:41.417076 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 05:56:41.419793 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 05:56:41.423186 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 05:56:41.430366 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 05:56:41.433692 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 05:56:41.437129 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 05:56:41.443488 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2926 05:56:41.447017 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 05:56:41.450374 Total UI for P1: 0, mck2ui 16
2928 05:56:41.453413 best dqsien dly found for B0: ( 1, 3, 28)
2929 05:56:41.457052 Total UI for P1: 0, mck2ui 16
2930 05:56:41.460096 best dqsien dly found for B1: ( 1, 3, 28)
2931 05:56:41.463510 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2932 05:56:41.466636 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2933 05:56:41.467206
2934 05:56:41.470378 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2935 05:56:41.473662 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2936 05:56:41.477134 [Gating] SW calibration Done
2937 05:56:41.477700 ==
2938 05:56:41.479890 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 05:56:41.483247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 05:56:41.483719 ==
2941 05:56:41.486834 RX Vref Scan: 0
2942 05:56:41.487404
2943 05:56:41.490141 RX Vref 0 -> 0, step: 1
2944 05:56:41.490693
2945 05:56:41.491063 RX Delay -40 -> 252, step: 8
2946 05:56:41.496541 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2947 05:56:41.500007 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2948 05:56:41.503089 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2949 05:56:41.506708 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2950 05:56:41.510055 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2951 05:56:41.516643 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2952 05:56:41.520466 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2953 05:56:41.523907 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2954 05:56:41.526859 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2955 05:56:41.530132 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2956 05:56:41.533401 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2957 05:56:41.539917 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2958 05:56:41.543607 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2959 05:56:41.547016 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2960 05:56:41.549770 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2961 05:56:41.556899 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2962 05:56:41.557472 ==
2963 05:56:41.560397 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 05:56:41.563366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 05:56:41.563941 ==
2966 05:56:41.564315 DQS Delay:
2967 05:56:41.566836 DQS0 = 0, DQS1 = 0
2968 05:56:41.567405 DQM Delay:
2969 05:56:41.570260 DQM0 = 120, DQM1 = 108
2970 05:56:41.570837 DQ Delay:
2971 05:56:41.573516 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2972 05:56:41.576899 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2973 05:56:41.580349 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2974 05:56:41.583558 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2975 05:56:41.584023
2976 05:56:41.584392
2977 05:56:41.584732 ==
2978 05:56:41.586500 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 05:56:41.593545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 05:56:41.594174 ==
2981 05:56:41.594563
2982 05:56:41.594911
2983 05:56:41.595239 TX Vref Scan disable
2984 05:56:41.597040 == TX Byte 0 ==
2985 05:56:41.600666 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2986 05:56:41.606987 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2987 05:56:41.607460 == TX Byte 1 ==
2988 05:56:41.610097 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2989 05:56:41.617089 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2990 05:56:41.617550 ==
2991 05:56:41.620493 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 05:56:41.623295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 05:56:41.623765 ==
2994 05:56:41.634761 TX Vref=22, minBit 3, minWin=24, winSum=413
2995 05:56:41.638146 TX Vref=24, minBit 1, minWin=24, winSum=411
2996 05:56:41.642213 TX Vref=26, minBit 1, minWin=25, winSum=420
2997 05:56:41.645310 TX Vref=28, minBit 3, minWin=24, winSum=422
2998 05:56:41.649019 TX Vref=30, minBit 5, minWin=25, winSum=425
2999 05:56:41.651848 TX Vref=32, minBit 1, minWin=25, winSum=423
3000 05:56:41.658902 [TxChooseVref] Worse bit 5, Min win 25, Win sum 425, Final Vref 30
3001 05:56:41.659370
3002 05:56:41.661805 Final TX Range 1 Vref 30
3003 05:56:41.662295
3004 05:56:41.662663 ==
3005 05:56:41.665398 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 05:56:41.668733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 05:56:41.669205 ==
3008 05:56:41.669577
3009 05:56:41.672511
3010 05:56:41.673082 TX Vref Scan disable
3011 05:56:41.675308 == TX Byte 0 ==
3012 05:56:41.678899 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3013 05:56:41.681882 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3014 05:56:41.685648 == TX Byte 1 ==
3015 05:56:41.688957 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3016 05:56:41.692061 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3017 05:56:41.692684
3018 05:56:41.695338 [DATLAT]
3019 05:56:41.695804 Freq=1200, CH0 RK1
3020 05:56:41.696178
3021 05:56:41.698664 DATLAT Default: 0xd
3022 05:56:41.699131 0, 0xFFFF, sum = 0
3023 05:56:41.701886 1, 0xFFFF, sum = 0
3024 05:56:41.702394 2, 0xFFFF, sum = 0
3025 05:56:41.705361 3, 0xFFFF, sum = 0
3026 05:56:41.705835 4, 0xFFFF, sum = 0
3027 05:56:41.709073 5, 0xFFFF, sum = 0
3028 05:56:41.709646 6, 0xFFFF, sum = 0
3029 05:56:41.712381 7, 0xFFFF, sum = 0
3030 05:56:41.712969 8, 0xFFFF, sum = 0
3031 05:56:41.715366 9, 0xFFFF, sum = 0
3032 05:56:41.718729 10, 0xFFFF, sum = 0
3033 05:56:41.719203 11, 0xFFFF, sum = 0
3034 05:56:41.722634 12, 0x0, sum = 1
3035 05:56:41.723234 13, 0x0, sum = 2
3036 05:56:41.723619 14, 0x0, sum = 3
3037 05:56:41.725514 15, 0x0, sum = 4
3038 05:56:41.726015 best_step = 13
3039 05:56:41.726394
3040 05:56:41.729114 ==
3041 05:56:41.729699 Dram Type= 6, Freq= 0, CH_0, rank 1
3042 05:56:41.735399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 05:56:41.735883 ==
3044 05:56:41.736361 RX Vref Scan: 0
3045 05:56:41.736814
3046 05:56:41.738647 RX Vref 0 -> 0, step: 1
3047 05:56:41.739055
3048 05:56:41.742041 RX Delay -21 -> 252, step: 4
3049 05:56:41.745440 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3050 05:56:41.749266 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3051 05:56:41.755407 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3052 05:56:41.758856 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3053 05:56:41.762237 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3054 05:56:41.766069 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3055 05:56:41.768978 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3056 05:56:41.775449 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3057 05:56:41.778481 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3058 05:56:41.782419 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3059 05:56:41.786033 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3060 05:56:41.789119 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3061 05:56:41.795235 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3062 05:56:41.798834 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3063 05:56:41.802335 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3064 05:56:41.805738 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3065 05:56:41.806252 ==
3066 05:56:41.808920 Dram Type= 6, Freq= 0, CH_0, rank 1
3067 05:56:41.812455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 05:56:41.815766 ==
3069 05:56:41.816357 DQS Delay:
3070 05:56:41.816843 DQS0 = 0, DQS1 = 0
3071 05:56:41.818825 DQM Delay:
3072 05:56:41.819311 DQM0 = 119, DQM1 = 108
3073 05:56:41.822355 DQ Delay:
3074 05:56:41.825643 DQ0 =116, DQ1 =122, DQ2 =116, DQ3 =114
3075 05:56:41.829030 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3076 05:56:41.832162 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3077 05:56:41.835713 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3078 05:56:41.836322
3079 05:56:41.836817
3080 05:56:41.842014 [DQSOSCAuto] RK1, (LSB)MR18= 0xef5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3081 05:56:41.845701 CH0 RK1: MR19=403, MR18=EF5
3082 05:56:41.852501 CH0_RK1: MR19=0x403, MR18=0xEF5, DQSOSC=404, MR23=63, INC=40, DEC=26
3083 05:56:41.855357 [RxdqsGatingPostProcess] freq 1200
3084 05:56:41.862453 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3085 05:56:41.863046 best DQS0 dly(2T, 0.5T) = (0, 11)
3086 05:56:41.865895 best DQS1 dly(2T, 0.5T) = (0, 12)
3087 05:56:41.868892 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3088 05:56:41.872364 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3089 05:56:41.875758 best DQS0 dly(2T, 0.5T) = (0, 11)
3090 05:56:41.878949 best DQS1 dly(2T, 0.5T) = (0, 11)
3091 05:56:41.881864 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3092 05:56:41.885773 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3093 05:56:41.889080 Pre-setting of DQS Precalculation
3094 05:56:41.892352 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3095 05:56:41.895890 ==
3096 05:56:41.898886 Dram Type= 6, Freq= 0, CH_1, rank 0
3097 05:56:41.902081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 05:56:41.902568 ==
3099 05:56:41.905322 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3100 05:56:41.912589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3101 05:56:41.921662 [CA 0] Center 37 (7~68) winsize 62
3102 05:56:41.925051 [CA 1] Center 37 (7~68) winsize 62
3103 05:56:41.928418 [CA 2] Center 35 (5~65) winsize 61
3104 05:56:41.931140 [CA 3] Center 34 (4~65) winsize 62
3105 05:56:41.934745 [CA 4] Center 34 (4~65) winsize 62
3106 05:56:41.938173 [CA 5] Center 33 (3~64) winsize 62
3107 05:56:41.938749
3108 05:56:41.941393 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3109 05:56:41.942009
3110 05:56:41.944752 [CATrainingPosCal] consider 1 rank data
3111 05:56:41.948176 u2DelayCellTimex100 = 270/100 ps
3112 05:56:41.951153 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3113 05:56:41.954615 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3114 05:56:41.961187 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3115 05:56:41.964901 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3116 05:56:41.968080 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3117 05:56:41.971797 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3118 05:56:41.972384
3119 05:56:41.974508 CA PerBit enable=1, Macro0, CA PI delay=33
3120 05:56:41.974993
3121 05:56:41.978209 [CBTSetCACLKResult] CA Dly = 33
3122 05:56:41.978838 CS Dly: 5 (0~36)
3123 05:56:41.979321 ==
3124 05:56:41.981414 Dram Type= 6, Freq= 0, CH_1, rank 1
3125 05:56:41.988058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 05:56:41.988545 ==
3127 05:56:41.991420 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3128 05:56:41.998102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3129 05:56:42.006808 [CA 0] Center 38 (8~69) winsize 62
3130 05:56:42.010155 [CA 1] Center 38 (7~69) winsize 63
3131 05:56:42.013600 [CA 2] Center 35 (5~66) winsize 62
3132 05:56:42.016791 [CA 3] Center 35 (5~65) winsize 61
3133 05:56:42.020602 [CA 4] Center 34 (4~64) winsize 61
3134 05:56:42.023270 [CA 5] Center 34 (4~64) winsize 61
3135 05:56:42.023743
3136 05:56:42.027386 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3137 05:56:42.027967
3138 05:56:42.030627 [CATrainingPosCal] consider 2 rank data
3139 05:56:42.033828 u2DelayCellTimex100 = 270/100 ps
3140 05:56:42.037152 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3141 05:56:42.040479 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3142 05:56:42.047108 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3143 05:56:42.050776 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3144 05:56:42.053604 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3145 05:56:42.057066 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3146 05:56:42.057658
3147 05:56:42.060310 CA PerBit enable=1, Macro0, CA PI delay=34
3148 05:56:42.060855
3149 05:56:42.064066 [CBTSetCACLKResult] CA Dly = 34
3150 05:56:42.064650 CS Dly: 6 (0~39)
3151 05:56:42.065031
3152 05:56:42.067374 ----->DramcWriteLeveling(PI) begin...
3153 05:56:42.070460 ==
3154 05:56:42.070934 Dram Type= 6, Freq= 0, CH_1, rank 0
3155 05:56:42.077049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 05:56:42.077630 ==
3157 05:56:42.080391 Write leveling (Byte 0): 26 => 26
3158 05:56:42.083912 Write leveling (Byte 1): 28 => 28
3159 05:56:42.084383 DramcWriteLeveling(PI) end<-----
3160 05:56:42.086810
3161 05:56:42.087280 ==
3162 05:56:42.090501 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 05:56:42.094099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 05:56:42.094679 ==
3165 05:56:42.097269 [Gating] SW mode calibration
3166 05:56:42.104275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3167 05:56:42.107157 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3168 05:56:42.113842 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 05:56:42.117456 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 05:56:42.120768 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 05:56:42.127442 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 05:56:42.130476 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 05:56:42.134419 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3174 05:56:42.140611 0 15 24 | B1->B0 | 2d2d 2a2a | 0 0 | (0 0) (1 0)
3175 05:56:42.143835 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 05:56:42.147456 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 05:56:42.154084 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 05:56:42.157723 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 05:56:42.160589 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 05:56:42.167341 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 05:56:42.170231 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 05:56:42.174217 1 0 24 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
3183 05:56:42.177159 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 05:56:42.184211 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 05:56:42.187331 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 05:56:42.190657 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 05:56:42.197554 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 05:56:42.200918 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 05:56:42.203930 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 05:56:42.210711 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3191 05:56:42.213819 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3192 05:56:42.217638 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 05:56:42.223822 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 05:56:42.227610 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 05:56:42.230432 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 05:56:42.237192 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 05:56:42.240437 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 05:56:42.243804 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 05:56:42.250645 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 05:56:42.254048 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 05:56:42.257419 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 05:56:42.260953 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 05:56:42.267166 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 05:56:42.270633 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 05:56:42.273796 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 05:56:42.280461 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3207 05:56:42.283861 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3208 05:56:42.287639 Total UI for P1: 0, mck2ui 16
3209 05:56:42.290790 best dqsien dly found for B0: ( 1, 3, 24)
3210 05:56:42.293908 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 05:56:42.297222 Total UI for P1: 0, mck2ui 16
3212 05:56:42.300639 best dqsien dly found for B1: ( 1, 3, 26)
3213 05:56:42.304072 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3214 05:56:42.307169 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3215 05:56:42.307353
3216 05:56:42.313825 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3217 05:56:42.317444 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3218 05:56:42.317872 [Gating] SW calibration Done
3219 05:56:42.320638 ==
3220 05:56:42.320946 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 05:56:42.326849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 05:56:42.327082 ==
3223 05:56:42.327266 RX Vref Scan: 0
3224 05:56:42.327437
3225 05:56:42.330485 RX Vref 0 -> 0, step: 1
3226 05:56:42.330669
3227 05:56:42.333894 RX Delay -40 -> 252, step: 8
3228 05:56:42.336875 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3229 05:56:42.340264 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3230 05:56:42.343900 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3231 05:56:42.350120 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3232 05:56:42.353531 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3233 05:56:42.356968 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3234 05:56:42.360347 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3235 05:56:42.363467 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3236 05:56:42.370303 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3237 05:56:42.373857 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3238 05:56:42.376857 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3239 05:56:42.380120 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3240 05:56:42.383762 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3241 05:56:42.390333 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3242 05:56:42.393865 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3243 05:56:42.397006 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3244 05:56:42.397092 ==
3245 05:56:42.400261 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 05:56:42.403747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 05:56:42.403834 ==
3248 05:56:42.407482 DQS Delay:
3249 05:56:42.407647 DQS0 = 0, DQS1 = 0
3250 05:56:42.407724 DQM Delay:
3251 05:56:42.410448 DQM0 = 121, DQM1 = 112
3252 05:56:42.410541 DQ Delay:
3253 05:56:42.413831 DQ0 =127, DQ1 =115, DQ2 =111, DQ3 =123
3254 05:56:42.417446 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3255 05:56:42.420441 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3256 05:56:42.426884 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3257 05:56:42.426981
3258 05:56:42.427049
3259 05:56:42.427111 ==
3260 05:56:42.430357 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 05:56:42.433599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 05:56:42.433684 ==
3263 05:56:42.433750
3264 05:56:42.433814
3265 05:56:42.437001 TX Vref Scan disable
3266 05:56:42.437084 == TX Byte 0 ==
3267 05:56:42.444215 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3268 05:56:42.447566 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3269 05:56:42.447994 == TX Byte 1 ==
3270 05:56:42.454172 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3271 05:56:42.457398 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3272 05:56:42.457828 ==
3273 05:56:42.460738 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 05:56:42.464137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 05:56:42.464567 ==
3276 05:56:42.476486 TX Vref=22, minBit 1, minWin=24, winSum=403
3277 05:56:42.479529 TX Vref=24, minBit 11, minWin=24, winSum=407
3278 05:56:42.483046 TX Vref=26, minBit 10, minWin=25, winSum=418
3279 05:56:42.486253 TX Vref=28, minBit 10, minWin=25, winSum=424
3280 05:56:42.489509 TX Vref=30, minBit 1, minWin=26, winSum=425
3281 05:56:42.496177 TX Vref=32, minBit 11, minWin=25, winSum=421
3282 05:56:42.499786 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 30
3283 05:56:42.499926
3284 05:56:42.502766 Final TX Range 1 Vref 30
3285 05:56:42.502949
3286 05:56:42.503059 ==
3287 05:56:42.506237 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 05:56:42.509567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 05:56:42.512933 ==
3290 05:56:42.513038
3291 05:56:42.513120
3292 05:56:42.513196 TX Vref Scan disable
3293 05:56:42.516145 == TX Byte 0 ==
3294 05:56:42.519699 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3295 05:56:42.523100 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3296 05:56:42.526111 == TX Byte 1 ==
3297 05:56:42.529519 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3298 05:56:42.533144 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3299 05:56:42.536087
3300 05:56:42.536186 [DATLAT]
3301 05:56:42.536261 Freq=1200, CH1 RK0
3302 05:56:42.536331
3303 05:56:42.539889 DATLAT Default: 0xd
3304 05:56:42.539975 0, 0xFFFF, sum = 0
3305 05:56:42.543012 1, 0xFFFF, sum = 0
3306 05:56:42.543181 2, 0xFFFF, sum = 0
3307 05:56:42.546356 3, 0xFFFF, sum = 0
3308 05:56:42.546466 4, 0xFFFF, sum = 0
3309 05:56:42.549652 5, 0xFFFF, sum = 0
3310 05:56:42.553034 6, 0xFFFF, sum = 0
3311 05:56:42.553122 7, 0xFFFF, sum = 0
3312 05:56:42.556417 8, 0xFFFF, sum = 0
3313 05:56:42.556504 9, 0xFFFF, sum = 0
3314 05:56:42.559803 10, 0xFFFF, sum = 0
3315 05:56:42.559976 11, 0xFFFF, sum = 0
3316 05:56:42.563063 12, 0x0, sum = 1
3317 05:56:42.563162 13, 0x0, sum = 2
3318 05:56:42.566398 14, 0x0, sum = 3
3319 05:56:42.566484 15, 0x0, sum = 4
3320 05:56:42.566555 best_step = 13
3321 05:56:42.566618
3322 05:56:42.569861 ==
3323 05:56:42.573390 Dram Type= 6, Freq= 0, CH_1, rank 0
3324 05:56:42.576721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3325 05:56:42.576905 ==
3326 05:56:42.576995 RX Vref Scan: 1
3327 05:56:42.577072
3328 05:56:42.579604 Set Vref Range= 32 -> 127
3329 05:56:42.579724
3330 05:56:42.583118 RX Vref 32 -> 127, step: 1
3331 05:56:42.583222
3332 05:56:42.586474 RX Delay -13 -> 252, step: 4
3333 05:56:42.586557
3334 05:56:42.589736 Set Vref, RX VrefLevel [Byte0]: 32
3335 05:56:42.593152 [Byte1]: 32
3336 05:56:42.593240
3337 05:56:42.596569 Set Vref, RX VrefLevel [Byte0]: 33
3338 05:56:42.599966 [Byte1]: 33
3339 05:56:42.600066
3340 05:56:42.603225 Set Vref, RX VrefLevel [Byte0]: 34
3341 05:56:42.606421 [Byte1]: 34
3342 05:56:42.611081
3343 05:56:42.611640 Set Vref, RX VrefLevel [Byte0]: 35
3344 05:56:42.614369 [Byte1]: 35
3345 05:56:42.618966
3346 05:56:42.619384 Set Vref, RX VrefLevel [Byte0]: 36
3347 05:56:42.622078 [Byte1]: 36
3348 05:56:42.626420
3349 05:56:42.629935 Set Vref, RX VrefLevel [Byte0]: 37
3350 05:56:42.630382 [Byte1]: 37
3351 05:56:42.634375
3352 05:56:42.634822 Set Vref, RX VrefLevel [Byte0]: 38
3353 05:56:42.637819 [Byte1]: 38
3354 05:56:42.642499
3355 05:56:42.642799 Set Vref, RX VrefLevel [Byte0]: 39
3356 05:56:42.645731 [Byte1]: 39
3357 05:56:42.650231
3358 05:56:42.650412 Set Vref, RX VrefLevel [Byte0]: 40
3359 05:56:42.653519 [Byte1]: 40
3360 05:56:42.658111
3361 05:56:42.658266 Set Vref, RX VrefLevel [Byte0]: 41
3362 05:56:42.661011 [Byte1]: 41
3363 05:56:42.665696
3364 05:56:42.665815 Set Vref, RX VrefLevel [Byte0]: 42
3365 05:56:42.668922 [Byte1]: 42
3366 05:56:42.673807
3367 05:56:42.673905 Set Vref, RX VrefLevel [Byte0]: 43
3368 05:56:42.677003 [Byte1]: 43
3369 05:56:42.681513
3370 05:56:42.681598 Set Vref, RX VrefLevel [Byte0]: 44
3371 05:56:42.684976 [Byte1]: 44
3372 05:56:42.689243
3373 05:56:42.689329 Set Vref, RX VrefLevel [Byte0]: 45
3374 05:56:42.692755 [Byte1]: 45
3375 05:56:42.697603
3376 05:56:42.697684 Set Vref, RX VrefLevel [Byte0]: 46
3377 05:56:42.701042 [Byte1]: 46
3378 05:56:42.705140
3379 05:56:42.705221 Set Vref, RX VrefLevel [Byte0]: 47
3380 05:56:42.708618 [Byte1]: 47
3381 05:56:42.713020
3382 05:56:42.713101 Set Vref, RX VrefLevel [Byte0]: 48
3383 05:56:42.716344 [Byte1]: 48
3384 05:56:42.720854
3385 05:56:42.720948 Set Vref, RX VrefLevel [Byte0]: 49
3386 05:56:42.724218 [Byte1]: 49
3387 05:56:42.728723
3388 05:56:42.728804 Set Vref, RX VrefLevel [Byte0]: 50
3389 05:56:42.732222 [Byte1]: 50
3390 05:56:42.737342
3391 05:56:42.737508 Set Vref, RX VrefLevel [Byte0]: 51
3392 05:56:42.740198 [Byte1]: 51
3393 05:56:42.745128
3394 05:56:42.745307 Set Vref, RX VrefLevel [Byte0]: 52
3395 05:56:42.748359 [Byte1]: 52
3396 05:56:42.752790
3397 05:56:42.752983 Set Vref, RX VrefLevel [Byte0]: 53
3398 05:56:42.756366 [Byte1]: 53
3399 05:56:42.760896
3400 05:56:42.761118 Set Vref, RX VrefLevel [Byte0]: 54
3401 05:56:42.763967 [Byte1]: 54
3402 05:56:42.768594
3403 05:56:42.768854 Set Vref, RX VrefLevel [Byte0]: 55
3404 05:56:42.771940 [Byte1]: 55
3405 05:56:42.776610
3406 05:56:42.776901 Set Vref, RX VrefLevel [Byte0]: 56
3407 05:56:42.779790 [Byte1]: 56
3408 05:56:42.784844
3409 05:56:42.785241 Set Vref, RX VrefLevel [Byte0]: 57
3410 05:56:42.787923 [Byte1]: 57
3411 05:56:42.792265
3412 05:56:42.792859 Set Vref, RX VrefLevel [Byte0]: 58
3413 05:56:42.795651 [Byte1]: 58
3414 05:56:42.800094
3415 05:56:42.800591 Set Vref, RX VrefLevel [Byte0]: 59
3416 05:56:42.803543 [Byte1]: 59
3417 05:56:42.808204
3418 05:56:42.808725 Set Vref, RX VrefLevel [Byte0]: 60
3419 05:56:42.811471 [Byte1]: 60
3420 05:56:42.815969
3421 05:56:42.816383 Set Vref, RX VrefLevel [Byte0]: 61
3422 05:56:42.819546 [Byte1]: 61
3423 05:56:42.823979
3424 05:56:42.824401 Set Vref, RX VrefLevel [Byte0]: 62
3425 05:56:42.827013 [Byte1]: 62
3426 05:56:42.832068
3427 05:56:42.832601 Set Vref, RX VrefLevel [Byte0]: 63
3428 05:56:42.835651 [Byte1]: 63
3429 05:56:42.839628
3430 05:56:42.840055 Set Vref, RX VrefLevel [Byte0]: 64
3431 05:56:42.843066 [Byte1]: 64
3432 05:56:42.847831
3433 05:56:42.848366 Set Vref, RX VrefLevel [Byte0]: 65
3434 05:56:42.851017 [Byte1]: 65
3435 05:56:42.856103
3436 05:56:42.856746 Set Vref, RX VrefLevel [Byte0]: 66
3437 05:56:42.859024 [Byte1]: 66
3438 05:56:42.863464
3439 05:56:42.863988 Final RX Vref Byte 0 = 52 to rank0
3440 05:56:42.867103 Final RX Vref Byte 1 = 52 to rank0
3441 05:56:42.870239 Final RX Vref Byte 0 = 52 to rank1
3442 05:56:42.873479 Final RX Vref Byte 1 = 52 to rank1==
3443 05:56:42.876730 Dram Type= 6, Freq= 0, CH_1, rank 0
3444 05:56:42.883503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3445 05:56:42.883960 ==
3446 05:56:42.884301 DQS Delay:
3447 05:56:42.884621 DQS0 = 0, DQS1 = 0
3448 05:56:42.887002 DQM Delay:
3449 05:56:42.887425 DQM0 = 119, DQM1 = 112
3450 05:56:42.890554 DQ Delay:
3451 05:56:42.893712 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3452 05:56:42.897384 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3453 05:56:42.900430 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3454 05:56:42.903689 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3455 05:56:42.904121
3456 05:56:42.904462
3457 05:56:42.910595 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3458 05:56:42.913592 CH1 RK0: MR19=304, MR18=FE12
3459 05:56:42.920777 CH1_RK0: MR19=0x304, MR18=0xFE12, DQSOSC=403, MR23=63, INC=40, DEC=26
3460 05:56:42.921313
3461 05:56:42.923792 ----->DramcWriteLeveling(PI) begin...
3462 05:56:42.924334 ==
3463 05:56:42.926997 Dram Type= 6, Freq= 0, CH_1, rank 1
3464 05:56:42.930135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 05:56:42.933639 ==
3466 05:56:42.934250 Write leveling (Byte 0): 25 => 25
3467 05:56:42.937190 Write leveling (Byte 1): 29 => 29
3468 05:56:42.940556 DramcWriteLeveling(PI) end<-----
3469 05:56:42.941113
3470 05:56:42.941465 ==
3471 05:56:42.943260 Dram Type= 6, Freq= 0, CH_1, rank 1
3472 05:56:42.950372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3473 05:56:42.950910 ==
3474 05:56:42.951257 [Gating] SW mode calibration
3475 05:56:42.960643 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3476 05:56:42.963619 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3477 05:56:42.967036 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 05:56:42.973687 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 05:56:42.976791 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 05:56:42.980288 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 05:56:42.987069 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 05:56:42.990159 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 05:56:42.993466 0 15 24 | B1->B0 | 2d2d 3434 | 1 1 | (1 0) (1 0)
3484 05:56:43.000191 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (1 0) (1 0)
3485 05:56:43.003658 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 05:56:43.006989 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 05:56:43.013994 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 05:56:43.016930 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 05:56:43.020300 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 05:56:43.027061 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 05:56:43.030501 1 0 24 | B1->B0 | 3535 2626 | 0 0 | (0 0) (0 0)
3492 05:56:43.033744 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3493 05:56:43.040267 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 05:56:43.043661 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 05:56:43.046808 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 05:56:43.053680 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 05:56:43.057307 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 05:56:43.060407 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 05:56:43.063411 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3500 05:56:43.070518 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3501 05:56:43.073702 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 05:56:43.077244 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 05:56:43.083533 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 05:56:43.086735 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 05:56:43.090535 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 05:56:43.097127 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 05:56:43.100594 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 05:56:43.103416 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 05:56:43.110184 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 05:56:43.113548 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 05:56:43.116644 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 05:56:43.123693 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 05:56:43.126537 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 05:56:43.129861 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 05:56:43.137039 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3516 05:56:43.140527 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3517 05:56:43.143622 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 05:56:43.146995 Total UI for P1: 0, mck2ui 16
3519 05:56:43.150387 best dqsien dly found for B0: ( 1, 3, 26)
3520 05:56:43.153470 Total UI for P1: 0, mck2ui 16
3521 05:56:43.156756 best dqsien dly found for B1: ( 1, 3, 28)
3522 05:56:43.159819 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3523 05:56:43.163369 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3524 05:56:43.163835
3525 05:56:43.166744 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3526 05:56:43.173393 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3527 05:56:43.173985 [Gating] SW calibration Done
3528 05:56:43.174369 ==
3529 05:56:43.176679 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 05:56:43.183262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 05:56:43.183862 ==
3532 05:56:43.184234 RX Vref Scan: 0
3533 05:56:43.184579
3534 05:56:43.186499 RX Vref 0 -> 0, step: 1
3535 05:56:43.186972
3536 05:56:43.190260 RX Delay -40 -> 252, step: 8
3537 05:56:43.193248 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3538 05:56:43.196696 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3539 05:56:43.200072 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3540 05:56:43.206424 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3541 05:56:43.209861 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3542 05:56:43.213670 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3543 05:56:43.216518 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3544 05:56:43.220038 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3545 05:56:43.226268 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3546 05:56:43.229673 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3547 05:56:43.233477 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3548 05:56:43.236723 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3549 05:56:43.239836 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3550 05:56:43.246792 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3551 05:56:43.249772 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3552 05:56:43.253037 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3553 05:56:43.253504 ==
3554 05:56:43.256322 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 05:56:43.259764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 05:56:43.260327 ==
3557 05:56:43.263305 DQS Delay:
3558 05:56:43.263771 DQS0 = 0, DQS1 = 0
3559 05:56:43.266486 DQM Delay:
3560 05:56:43.266952 DQM0 = 120, DQM1 = 112
3561 05:56:43.267321 DQ Delay:
3562 05:56:43.273211 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =123
3563 05:56:43.276460 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3564 05:56:43.279472 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3565 05:56:43.282950 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3566 05:56:43.283441
3567 05:56:43.283816
3568 05:56:43.284157 ==
3569 05:56:43.286498 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 05:56:43.289504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 05:56:43.290028 ==
3572 05:56:43.290407
3573 05:56:43.290748
3574 05:56:43.292990 TX Vref Scan disable
3575 05:56:43.296462 == TX Byte 0 ==
3576 05:56:43.300038 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3577 05:56:43.302772 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3578 05:56:43.306246 == TX Byte 1 ==
3579 05:56:43.309763 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3580 05:56:43.312970 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3581 05:56:43.313537 ==
3582 05:56:43.316684 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 05:56:43.319475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 05:56:43.323084 ==
3585 05:56:43.333416 TX Vref=22, minBit 1, minWin=25, winSum=418
3586 05:56:43.336793 TX Vref=24, minBit 1, minWin=25, winSum=418
3587 05:56:43.339856 TX Vref=26, minBit 1, minWin=26, winSum=427
3588 05:56:43.343455 TX Vref=28, minBit 8, minWin=26, winSum=429
3589 05:56:43.346078 TX Vref=30, minBit 9, minWin=25, winSum=426
3590 05:56:43.349776 TX Vref=32, minBit 1, minWin=26, winSum=428
3591 05:56:43.356318 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 28
3592 05:56:43.356795
3593 05:56:43.359990 Final TX Range 1 Vref 28
3594 05:56:43.360552
3595 05:56:43.360944 ==
3596 05:56:43.362523 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 05:56:43.365929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 05:56:43.366679 ==
3599 05:56:43.369312
3600 05:56:43.370099
3601 05:56:43.370495 TX Vref Scan disable
3602 05:56:43.372394 == TX Byte 0 ==
3603 05:56:43.376122 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3604 05:56:43.379743 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3605 05:56:43.382804 == TX Byte 1 ==
3606 05:56:43.385581 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3607 05:56:43.392409 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3608 05:56:43.392932
3609 05:56:43.393303 [DATLAT]
3610 05:56:43.393645 Freq=1200, CH1 RK1
3611 05:56:43.394013
3612 05:56:43.395710 DATLAT Default: 0xd
3613 05:56:43.396188 0, 0xFFFF, sum = 0
3614 05:56:43.399216 1, 0xFFFF, sum = 0
3615 05:56:43.402574 2, 0xFFFF, sum = 0
3616 05:56:43.403072 3, 0xFFFF, sum = 0
3617 05:56:43.405631 4, 0xFFFF, sum = 0
3618 05:56:43.406118 5, 0xFFFF, sum = 0
3619 05:56:43.408735 6, 0xFFFF, sum = 0
3620 05:56:43.409162 7, 0xFFFF, sum = 0
3621 05:56:43.412238 8, 0xFFFF, sum = 0
3622 05:56:43.412665 9, 0xFFFF, sum = 0
3623 05:56:43.415378 10, 0xFFFF, sum = 0
3624 05:56:43.415821 11, 0xFFFF, sum = 0
3625 05:56:43.418793 12, 0x0, sum = 1
3626 05:56:43.419218 13, 0x0, sum = 2
3627 05:56:43.422266 14, 0x0, sum = 3
3628 05:56:43.422690 15, 0x0, sum = 4
3629 05:56:43.425291 best_step = 13
3630 05:56:43.425729
3631 05:56:43.426094 ==
3632 05:56:43.428714 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 05:56:43.432206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 05:56:43.432734 ==
3635 05:56:43.433072 RX Vref Scan: 0
3636 05:56:43.435633
3637 05:56:43.436156 RX Vref 0 -> 0, step: 1
3638 05:56:43.436495
3639 05:56:43.439155 RX Delay -13 -> 252, step: 4
3640 05:56:43.445565 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3641 05:56:43.448940 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3642 05:56:43.452316 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3643 05:56:43.455406 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3644 05:56:43.458522 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3645 05:56:43.465523 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3646 05:56:43.468767 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3647 05:56:43.472371 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3648 05:56:43.475173 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3649 05:56:43.478466 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3650 05:56:43.481573 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3651 05:56:43.488283 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3652 05:56:43.491985 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3653 05:56:43.495341 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3654 05:56:43.498645 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3655 05:56:43.505125 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3656 05:56:43.505678 ==
3657 05:56:43.508673 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 05:56:43.511975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 05:56:43.512541 ==
3660 05:56:43.512912 DQS Delay:
3661 05:56:43.514849 DQS0 = 0, DQS1 = 0
3662 05:56:43.515311 DQM Delay:
3663 05:56:43.518299 DQM0 = 119, DQM1 = 112
3664 05:56:43.518761 DQ Delay:
3665 05:56:43.521834 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3666 05:56:43.525151 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3667 05:56:43.528685 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3668 05:56:43.531751 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3669 05:56:43.532325
3670 05:56:43.532693
3671 05:56:43.541833 [DQSOSCAuto] RK1, (LSB)MR18= 0x8ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 406 ps
3672 05:56:43.545151 CH1 RK1: MR19=403, MR18=8EC
3673 05:56:43.548907 CH1_RK1: MR19=0x403, MR18=0x8EC, DQSOSC=406, MR23=63, INC=39, DEC=26
3674 05:56:43.551482 [RxdqsGatingPostProcess] freq 1200
3675 05:56:43.558103 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3676 05:56:43.561608 best DQS0 dly(2T, 0.5T) = (0, 11)
3677 05:56:43.565086 best DQS1 dly(2T, 0.5T) = (0, 11)
3678 05:56:43.568488 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3679 05:56:43.571589 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3680 05:56:43.574983 best DQS0 dly(2T, 0.5T) = (0, 11)
3681 05:56:43.578110 best DQS1 dly(2T, 0.5T) = (0, 11)
3682 05:56:43.581301 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3683 05:56:43.584816 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3684 05:56:43.587943 Pre-setting of DQS Precalculation
3685 05:56:43.591376 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3686 05:56:43.598238 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3687 05:56:43.604656 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3688 05:56:43.605123
3689 05:56:43.605493
3690 05:56:43.607981 [Calibration Summary] 2400 Mbps
3691 05:56:43.611274 CH 0, Rank 0
3692 05:56:43.611739 SW Impedance : PASS
3693 05:56:43.614491 DUTY Scan : NO K
3694 05:56:43.617867 ZQ Calibration : PASS
3695 05:56:43.618318 Jitter Meter : NO K
3696 05:56:43.621371 CBT Training : PASS
3697 05:56:43.624855 Write leveling : PASS
3698 05:56:43.625278 RX DQS gating : PASS
3699 05:56:43.627788 RX DQ/DQS(RDDQC) : PASS
3700 05:56:43.631558 TX DQ/DQS : PASS
3701 05:56:43.632083 RX DATLAT : PASS
3702 05:56:43.634496 RX DQ/DQS(Engine): PASS
3703 05:56:43.634917 TX OE : NO K
3704 05:56:43.638338 All Pass.
3705 05:56:43.638862
3706 05:56:43.639203 CH 0, Rank 1
3707 05:56:43.641244 SW Impedance : PASS
3708 05:56:43.641666 DUTY Scan : NO K
3709 05:56:43.645005 ZQ Calibration : PASS
3710 05:56:43.648028 Jitter Meter : NO K
3711 05:56:43.648555 CBT Training : PASS
3712 05:56:43.651541 Write leveling : PASS
3713 05:56:43.654550 RX DQS gating : PASS
3714 05:56:43.655074 RX DQ/DQS(RDDQC) : PASS
3715 05:56:43.657833 TX DQ/DQS : PASS
3716 05:56:43.661564 RX DATLAT : PASS
3717 05:56:43.662143 RX DQ/DQS(Engine): PASS
3718 05:56:43.664324 TX OE : NO K
3719 05:56:43.664751 All Pass.
3720 05:56:43.665088
3721 05:56:43.667766 CH 1, Rank 0
3722 05:56:43.668186 SW Impedance : PASS
3723 05:56:43.671474 DUTY Scan : NO K
3724 05:56:43.674784 ZQ Calibration : PASS
3725 05:56:43.675313 Jitter Meter : NO K
3726 05:56:43.678092 CBT Training : PASS
3727 05:56:43.680951 Write leveling : PASS
3728 05:56:43.681376 RX DQS gating : PASS
3729 05:56:43.684501 RX DQ/DQS(RDDQC) : PASS
3730 05:56:43.687641 TX DQ/DQS : PASS
3731 05:56:43.688076 RX DATLAT : PASS
3732 05:56:43.690846 RX DQ/DQS(Engine): PASS
3733 05:56:43.691311 TX OE : NO K
3734 05:56:43.693972 All Pass.
3735 05:56:43.694462
3736 05:56:43.694806 CH 1, Rank 1
3737 05:56:43.697235 SW Impedance : PASS
3738 05:56:43.697661 DUTY Scan : NO K
3739 05:56:43.700874 ZQ Calibration : PASS
3740 05:56:43.704118 Jitter Meter : NO K
3741 05:56:43.704614 CBT Training : PASS
3742 05:56:43.707589 Write leveling : PASS
3743 05:56:43.711023 RX DQS gating : PASS
3744 05:56:43.711565 RX DQ/DQS(RDDQC) : PASS
3745 05:56:43.713791 TX DQ/DQS : PASS
3746 05:56:43.717275 RX DATLAT : PASS
3747 05:56:43.717711 RX DQ/DQS(Engine): PASS
3748 05:56:43.720596 TX OE : NO K
3749 05:56:43.721014 All Pass.
3750 05:56:43.721345
3751 05:56:43.724343 DramC Write-DBI off
3752 05:56:43.727389 PER_BANK_REFRESH: Hybrid Mode
3753 05:56:43.727807 TX_TRACKING: ON
3754 05:56:43.737288 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3755 05:56:43.740665 [FAST_K] Save calibration result to emmc
3756 05:56:43.743841 dramc_set_vcore_voltage set vcore to 650000
3757 05:56:43.747477 Read voltage for 600, 5
3758 05:56:43.747894 Vio18 = 0
3759 05:56:43.748227 Vcore = 650000
3760 05:56:43.751038 Vdram = 0
3761 05:56:43.751459 Vddq = 0
3762 05:56:43.751791 Vmddr = 0
3763 05:56:43.757581 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3764 05:56:43.760509 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3765 05:56:43.764128 MEM_TYPE=3, freq_sel=19
3766 05:56:43.767135 sv_algorithm_assistance_LP4_1600
3767 05:56:43.770793 ============ PULL DRAM RESETB DOWN ============
3768 05:56:43.774005 ========== PULL DRAM RESETB DOWN end =========
3769 05:56:43.780834 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3770 05:56:43.783908 ===================================
3771 05:56:43.784330 LPDDR4 DRAM CONFIGURATION
3772 05:56:43.787507 ===================================
3773 05:56:43.790564 EX_ROW_EN[0] = 0x0
3774 05:56:43.794316 EX_ROW_EN[1] = 0x0
3775 05:56:43.794750 LP4Y_EN = 0x0
3776 05:56:43.797203 WORK_FSP = 0x0
3777 05:56:43.797757 WL = 0x2
3778 05:56:43.800268 RL = 0x2
3779 05:56:43.800689 BL = 0x2
3780 05:56:43.803597 RPST = 0x0
3781 05:56:43.804150 RD_PRE = 0x0
3782 05:56:43.807416 WR_PRE = 0x1
3783 05:56:43.808017 WR_PST = 0x0
3784 05:56:43.810355 DBI_WR = 0x0
3785 05:56:43.810783 DBI_RD = 0x0
3786 05:56:43.813654 OTF = 0x1
3787 05:56:43.816973 ===================================
3788 05:56:43.820666 ===================================
3789 05:56:43.821115 ANA top config
3790 05:56:43.823692 ===================================
3791 05:56:43.827257 DLL_ASYNC_EN = 0
3792 05:56:43.830388 ALL_SLAVE_EN = 1
3793 05:56:43.833763 NEW_RANK_MODE = 1
3794 05:56:43.834302 DLL_IDLE_MODE = 1
3795 05:56:43.836943 LP45_APHY_COMB_EN = 1
3796 05:56:43.840862 TX_ODT_DIS = 1
3797 05:56:43.843733 NEW_8X_MODE = 1
3798 05:56:43.847154 ===================================
3799 05:56:43.850600 ===================================
3800 05:56:43.851031 data_rate = 1200
3801 05:56:43.853655 CKR = 1
3802 05:56:43.857248 DQ_P2S_RATIO = 8
3803 05:56:43.860885 ===================================
3804 05:56:43.863908 CA_P2S_RATIO = 8
3805 05:56:43.866996 DQ_CA_OPEN = 0
3806 05:56:43.870716 DQ_SEMI_OPEN = 0
3807 05:56:43.871222 CA_SEMI_OPEN = 0
3808 05:56:43.873776 CA_FULL_RATE = 0
3809 05:56:43.877256 DQ_CKDIV4_EN = 1
3810 05:56:43.880418 CA_CKDIV4_EN = 1
3811 05:56:43.883507 CA_PREDIV_EN = 0
3812 05:56:43.886866 PH8_DLY = 0
3813 05:56:43.886950 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3814 05:56:43.890443 DQ_AAMCK_DIV = 4
3815 05:56:43.893545 CA_AAMCK_DIV = 4
3816 05:56:43.896893 CA_ADMCK_DIV = 4
3817 05:56:43.900091 DQ_TRACK_CA_EN = 0
3818 05:56:43.903332 CA_PICK = 600
3819 05:56:43.906752 CA_MCKIO = 600
3820 05:56:43.906895 MCKIO_SEMI = 0
3821 05:56:43.910073 PLL_FREQ = 2288
3822 05:56:43.913349 DQ_UI_PI_RATIO = 32
3823 05:56:43.916443 CA_UI_PI_RATIO = 0
3824 05:56:43.920158 ===================================
3825 05:56:43.923172 ===================================
3826 05:56:43.926703 memory_type:LPDDR4
3827 05:56:43.926807 GP_NUM : 10
3828 05:56:43.929956 SRAM_EN : 1
3829 05:56:43.930059 MD32_EN : 0
3830 05:56:43.933198 ===================================
3831 05:56:43.936681 [ANA_INIT] >>>>>>>>>>>>>>
3832 05:56:43.939715 <<<<<< [CONFIGURE PHASE]: ANA_TX
3833 05:56:43.943437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3834 05:56:43.946678 ===================================
3835 05:56:43.950247 data_rate = 1200,PCW = 0X5800
3836 05:56:43.953226 ===================================
3837 05:56:43.956700 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3838 05:56:43.963350 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3839 05:56:43.967066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3840 05:56:43.973282 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3841 05:56:43.976963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3842 05:56:43.979965 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3843 05:56:43.980038 [ANA_INIT] flow start
3844 05:56:43.983466 [ANA_INIT] PLL >>>>>>>>
3845 05:56:43.986590 [ANA_INIT] PLL <<<<<<<<
3846 05:56:43.986662 [ANA_INIT] MIDPI >>>>>>>>
3847 05:56:43.989900 [ANA_INIT] MIDPI <<<<<<<<
3848 05:56:43.993330 [ANA_INIT] DLL >>>>>>>>
3849 05:56:43.993432 [ANA_INIT] flow end
3850 05:56:43.999824 ============ LP4 DIFF to SE enter ============
3851 05:56:44.003205 ============ LP4 DIFF to SE exit ============
3852 05:56:44.003279 [ANA_INIT] <<<<<<<<<<<<<
3853 05:56:44.006510 [Flow] Enable top DCM control >>>>>
3854 05:56:44.009825 [Flow] Enable top DCM control <<<<<
3855 05:56:44.013164 Enable DLL master slave shuffle
3856 05:56:44.020064 ==============================================================
3857 05:56:44.023297 Gating Mode config
3858 05:56:44.026459 ==============================================================
3859 05:56:44.029778 Config description:
3860 05:56:44.040114 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3861 05:56:44.046772 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3862 05:56:44.050079 SELPH_MODE 0: By rank 1: By Phase
3863 05:56:44.056905 ==============================================================
3864 05:56:44.060195 GAT_TRACK_EN = 1
3865 05:56:44.063452 RX_GATING_MODE = 2
3866 05:56:44.067046 RX_GATING_TRACK_MODE = 2
3867 05:56:44.067569 SELPH_MODE = 1
3868 05:56:44.070471 PICG_EARLY_EN = 1
3869 05:56:44.073414 VALID_LAT_VALUE = 1
3870 05:56:44.080697 ==============================================================
3871 05:56:44.083379 Enter into Gating configuration >>>>
3872 05:56:44.086920 Exit from Gating configuration <<<<
3873 05:56:44.090577 Enter into DVFS_PRE_config >>>>>
3874 05:56:44.100581 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3875 05:56:44.103589 Exit from DVFS_PRE_config <<<<<
3876 05:56:44.106915 Enter into PICG configuration >>>>
3877 05:56:44.109745 Exit from PICG configuration <<<<
3878 05:56:44.113228 [RX_INPUT] configuration >>>>>
3879 05:56:44.116602 [RX_INPUT] configuration <<<<<
3880 05:56:44.119894 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3881 05:56:44.126799 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3882 05:56:44.133522 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3883 05:56:44.139911 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3884 05:56:44.143226 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3885 05:56:44.150269 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3886 05:56:44.153176 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3887 05:56:44.159414 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3888 05:56:44.162734 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3889 05:56:44.166027 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3890 05:56:44.169604 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3891 05:56:44.176321 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3892 05:56:44.179815 ===================================
3893 05:56:44.182591 LPDDR4 DRAM CONFIGURATION
3894 05:56:44.186122 ===================================
3895 05:56:44.186317 EX_ROW_EN[0] = 0x0
3896 05:56:44.189605 EX_ROW_EN[1] = 0x0
3897 05:56:44.189797 LP4Y_EN = 0x0
3898 05:56:44.192480 WORK_FSP = 0x0
3899 05:56:44.192654 WL = 0x2
3900 05:56:44.195841 RL = 0x2
3901 05:56:44.196032 BL = 0x2
3902 05:56:44.199381 RPST = 0x0
3903 05:56:44.199601 RD_PRE = 0x0
3904 05:56:44.202970 WR_PRE = 0x1
3905 05:56:44.203207 WR_PST = 0x0
3906 05:56:44.205840 DBI_WR = 0x0
3907 05:56:44.206084 DBI_RD = 0x0
3908 05:56:44.209195 OTF = 0x1
3909 05:56:44.212757 ===================================
3910 05:56:44.216299 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3911 05:56:44.219646 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3912 05:56:44.226204 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3913 05:56:44.229211 ===================================
3914 05:56:44.229605 LPDDR4 DRAM CONFIGURATION
3915 05:56:44.233258 ===================================
3916 05:56:44.236446 EX_ROW_EN[0] = 0x10
3917 05:56:44.239339 EX_ROW_EN[1] = 0x0
3918 05:56:44.239833 LP4Y_EN = 0x0
3919 05:56:44.242532 WORK_FSP = 0x0
3920 05:56:44.243014 WL = 0x2
3921 05:56:44.246364 RL = 0x2
3922 05:56:44.246970 BL = 0x2
3923 05:56:44.249229 RPST = 0x0
3924 05:56:44.249737 RD_PRE = 0x0
3925 05:56:44.252923 WR_PRE = 0x1
3926 05:56:44.253458 WR_PST = 0x0
3927 05:56:44.255870 DBI_WR = 0x0
3928 05:56:44.256307 DBI_RD = 0x0
3929 05:56:44.259453 OTF = 0x1
3930 05:56:44.262942 ===================================
3931 05:56:44.268968 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3932 05:56:44.272341 nWR fixed to 30
3933 05:56:44.276021 [ModeRegInit_LP4] CH0 RK0
3934 05:56:44.276564 [ModeRegInit_LP4] CH0 RK1
3935 05:56:44.279410 [ModeRegInit_LP4] CH1 RK0
3936 05:56:44.282353 [ModeRegInit_LP4] CH1 RK1
3937 05:56:44.282845 match AC timing 17
3938 05:56:44.289346 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3939 05:56:44.292360 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3940 05:56:44.295644 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3941 05:56:44.302359 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3942 05:56:44.305495 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3943 05:56:44.305970 ==
3944 05:56:44.309182 Dram Type= 6, Freq= 0, CH_0, rank 0
3945 05:56:44.312068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3946 05:56:44.312493 ==
3947 05:56:44.319070 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3948 05:56:44.325429 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3949 05:56:44.328793 [CA 0] Center 36 (6~67) winsize 62
3950 05:56:44.332216 [CA 1] Center 36 (6~67) winsize 62
3951 05:56:44.335769 [CA 2] Center 34 (4~65) winsize 62
3952 05:56:44.339091 [CA 3] Center 34 (4~65) winsize 62
3953 05:56:44.342407 [CA 4] Center 34 (3~65) winsize 63
3954 05:56:44.345844 [CA 5] Center 33 (2~64) winsize 63
3955 05:56:44.346327
3956 05:56:44.348800 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3957 05:56:44.349301
3958 05:56:44.352120 [CATrainingPosCal] consider 1 rank data
3959 05:56:44.355510 u2DelayCellTimex100 = 270/100 ps
3960 05:56:44.358690 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3961 05:56:44.362342 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3962 05:56:44.365246 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3963 05:56:44.368810 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3964 05:56:44.372251 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3965 05:56:44.375403 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3966 05:56:44.375842
3967 05:56:44.382232 CA PerBit enable=1, Macro0, CA PI delay=33
3968 05:56:44.382669
3969 05:56:44.385262 [CBTSetCACLKResult] CA Dly = 33
3970 05:56:44.385767 CS Dly: 5 (0~36)
3971 05:56:44.386252 ==
3972 05:56:44.388644 Dram Type= 6, Freq= 0, CH_0, rank 1
3973 05:56:44.391769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 05:56:44.392211 ==
3975 05:56:44.398719 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3976 05:56:44.404789 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3977 05:56:44.408111 [CA 0] Center 36 (6~67) winsize 62
3978 05:56:44.411906 [CA 1] Center 36 (6~67) winsize 62
3979 05:56:44.414807 [CA 2] Center 35 (5~66) winsize 62
3980 05:56:44.418245 [CA 3] Center 35 (4~66) winsize 63
3981 05:56:44.421343 [CA 4] Center 34 (3~65) winsize 63
3982 05:56:44.424801 [CA 5] Center 34 (3~65) winsize 63
3983 05:56:44.424899
3984 05:56:44.428194 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3985 05:56:44.428277
3986 05:56:44.431585 [CATrainingPosCal] consider 2 rank data
3987 05:56:44.435120 u2DelayCellTimex100 = 270/100 ps
3988 05:56:44.438231 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3989 05:56:44.441569 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3990 05:56:44.444796 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3991 05:56:44.448092 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3992 05:56:44.451226 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3993 05:56:44.457891 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3994 05:56:44.458027
3995 05:56:44.461486 CA PerBit enable=1, Macro0, CA PI delay=33
3996 05:56:44.461569
3997 05:56:44.464868 [CBTSetCACLKResult] CA Dly = 33
3998 05:56:44.464940 CS Dly: 5 (0~37)
3999 05:56:44.465003
4000 05:56:44.467801 ----->DramcWriteLeveling(PI) begin...
4001 05:56:44.467885 ==
4002 05:56:44.471196 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 05:56:44.477551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 05:56:44.477635 ==
4005 05:56:44.481146 Write leveling (Byte 0): 33 => 33
4006 05:56:44.481229 Write leveling (Byte 1): 33 => 33
4007 05:56:44.484147 DramcWriteLeveling(PI) end<-----
4008 05:56:44.484230
4009 05:56:44.487678 ==
4010 05:56:44.487761 Dram Type= 6, Freq= 0, CH_0, rank 0
4011 05:56:44.494204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 05:56:44.494288 ==
4013 05:56:44.497716 [Gating] SW mode calibration
4014 05:56:44.504011 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4015 05:56:44.507397 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4016 05:56:44.513927 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4017 05:56:44.517536 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4018 05:56:44.520899 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4019 05:56:44.527302 0 9 12 | B1->B0 | 3333 2e2e | 1 0 | (1 1) (0 0)
4020 05:56:44.530724 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
4021 05:56:44.534221 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 05:56:44.540562 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 05:56:44.543926 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 05:56:44.546925 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 05:56:44.553631 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 05:56:44.556928 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4027 05:56:44.560326 0 10 12 | B1->B0 | 2828 4343 | 0 0 | (0 0) (0 0)
4028 05:56:44.566932 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4029 05:56:44.570149 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 05:56:44.573569 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 05:56:44.580095 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 05:56:44.583531 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 05:56:44.587011 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 05:56:44.593550 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 05:56:44.596906 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4036 05:56:44.600409 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4037 05:56:44.606772 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 05:56:44.609837 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 05:56:44.613247 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 05:56:44.620188 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 05:56:44.623383 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 05:56:44.626836 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 05:56:44.630220 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 05:56:44.636620 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 05:56:44.639756 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 05:56:44.643110 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 05:56:44.649632 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 05:56:44.653068 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 05:56:44.656316 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 05:56:44.663044 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 05:56:44.666499 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4052 05:56:44.669578 Total UI for P1: 0, mck2ui 16
4053 05:56:44.672897 best dqsien dly found for B0: ( 0, 13, 10)
4054 05:56:44.676342 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 05:56:44.679539 Total UI for P1: 0, mck2ui 16
4056 05:56:44.682974 best dqsien dly found for B1: ( 0, 13, 12)
4057 05:56:44.686247 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4058 05:56:44.692825 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4059 05:56:44.692911
4060 05:56:44.696413 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4061 05:56:44.699831 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4062 05:56:44.702834 [Gating] SW calibration Done
4063 05:56:44.702920 ==
4064 05:56:44.706394 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 05:56:44.709618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 05:56:44.709716 ==
4067 05:56:44.709782 RX Vref Scan: 0
4068 05:56:44.713084
4069 05:56:44.713167 RX Vref 0 -> 0, step: 1
4070 05:56:44.713234
4071 05:56:44.716417 RX Delay -230 -> 252, step: 16
4072 05:56:44.719478 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4073 05:56:44.726142 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4074 05:56:44.729805 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4075 05:56:44.732812 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4076 05:56:44.736244 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4077 05:56:44.739675 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4078 05:56:44.746023 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4079 05:56:44.749472 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4080 05:56:44.752559 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4081 05:56:44.756050 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4082 05:56:44.762921 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4083 05:56:44.765989 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4084 05:56:44.769485 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4085 05:56:44.772717 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4086 05:56:44.779407 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4087 05:56:44.782609 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4088 05:56:44.782693 ==
4089 05:56:44.785994 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 05:56:44.789140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 05:56:44.789223 ==
4092 05:56:44.789290 DQS Delay:
4093 05:56:44.792486 DQS0 = 0, DQS1 = 0
4094 05:56:44.792606 DQM Delay:
4095 05:56:44.795871 DQM0 = 49, DQM1 = 40
4096 05:56:44.795973 DQ Delay:
4097 05:56:44.799439 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =41
4098 05:56:44.802283 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4099 05:56:44.805805 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4100 05:56:44.809259 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =41
4101 05:56:44.809343
4102 05:56:44.809412
4103 05:56:44.809474 ==
4104 05:56:44.812798 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 05:56:44.815929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 05:56:44.818852 ==
4107 05:56:44.818935
4108 05:56:44.819001
4109 05:56:44.819061 TX Vref Scan disable
4110 05:56:44.822226 == TX Byte 0 ==
4111 05:56:44.825779 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4112 05:56:44.829269 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4113 05:56:44.832460 == TX Byte 1 ==
4114 05:56:44.835821 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4115 05:56:44.842531 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4116 05:56:44.842615 ==
4117 05:56:44.846002 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 05:56:44.848980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 05:56:44.849064 ==
4120 05:56:44.849130
4121 05:56:44.849190
4122 05:56:44.852047 TX Vref Scan disable
4123 05:56:44.852130 == TX Byte 0 ==
4124 05:56:44.858873 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4125 05:56:44.862435 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4126 05:56:44.862518 == TX Byte 1 ==
4127 05:56:44.869003 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4128 05:56:44.872331 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4129 05:56:44.872415
4130 05:56:44.872481 [DATLAT]
4131 05:56:44.875615 Freq=600, CH0 RK0
4132 05:56:44.875716
4133 05:56:44.875815 DATLAT Default: 0x9
4134 05:56:44.878892 0, 0xFFFF, sum = 0
4135 05:56:44.878977 1, 0xFFFF, sum = 0
4136 05:56:44.882128 2, 0xFFFF, sum = 0
4137 05:56:44.885789 3, 0xFFFF, sum = 0
4138 05:56:44.885873 4, 0xFFFF, sum = 0
4139 05:56:44.888912 5, 0xFFFF, sum = 0
4140 05:56:44.888997 6, 0xFFFF, sum = 0
4141 05:56:44.891972 7, 0xFFFF, sum = 0
4142 05:56:44.892056 8, 0x0, sum = 1
4143 05:56:44.892123 9, 0x0, sum = 2
4144 05:56:44.895586 10, 0x0, sum = 3
4145 05:56:44.895670 11, 0x0, sum = 4
4146 05:56:44.898597 best_step = 9
4147 05:56:44.898680
4148 05:56:44.898746 ==
4149 05:56:44.901902 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 05:56:44.905364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 05:56:44.905448 ==
4152 05:56:44.908449 RX Vref Scan: 1
4153 05:56:44.908532
4154 05:56:44.908598 RX Vref 0 -> 0, step: 1
4155 05:56:44.908661
4156 05:56:44.911806 RX Delay -179 -> 252, step: 8
4157 05:56:44.911890
4158 05:56:44.915274 Set Vref, RX VrefLevel [Byte0]: 57
4159 05:56:44.918321 [Byte1]: 49
4160 05:56:44.922813
4161 05:56:44.922896 Final RX Vref Byte 0 = 57 to rank0
4162 05:56:44.926245 Final RX Vref Byte 1 = 49 to rank0
4163 05:56:44.929221 Final RX Vref Byte 0 = 57 to rank1
4164 05:56:44.932711 Final RX Vref Byte 1 = 49 to rank1==
4165 05:56:44.936046 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 05:56:44.942851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 05:56:44.942936 ==
4168 05:56:44.943002 DQS Delay:
4169 05:56:44.945863 DQS0 = 0, DQS1 = 0
4170 05:56:44.945968 DQM Delay:
4171 05:56:44.946050 DQM0 = 48, DQM1 = 39
4172 05:56:44.949367 DQ Delay:
4173 05:56:44.952894 DQ0 =44, DQ1 =52, DQ2 =44, DQ3 =44
4174 05:56:44.955825 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4175 05:56:44.959227 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4176 05:56:44.962279 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4177 05:56:44.962362
4178 05:56:44.962428
4179 05:56:44.969363 [DQSOSCAuto] RK0, (LSB)MR18= 0x5852, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4180 05:56:44.972627 CH0 RK0: MR19=808, MR18=5852
4181 05:56:44.979006 CH0_RK0: MR19=0x808, MR18=0x5852, DQSOSC=393, MR23=63, INC=169, DEC=113
4182 05:56:44.979089
4183 05:56:44.982345 ----->DramcWriteLeveling(PI) begin...
4184 05:56:44.982430 ==
4185 05:56:44.985629 Dram Type= 6, Freq= 0, CH_0, rank 1
4186 05:56:44.989224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 05:56:44.989308 ==
4188 05:56:44.992243 Write leveling (Byte 0): 35 => 35
4189 05:56:44.995679 Write leveling (Byte 1): 30 => 30
4190 05:56:44.998940 DramcWriteLeveling(PI) end<-----
4191 05:56:44.999023
4192 05:56:44.999088 ==
4193 05:56:45.002316 Dram Type= 6, Freq= 0, CH_0, rank 1
4194 05:56:45.005668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 05:56:45.005752 ==
4196 05:56:45.009018 [Gating] SW mode calibration
4197 05:56:45.015539 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4198 05:56:45.022381 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4199 05:56:45.025382 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4200 05:56:45.032062 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4201 05:56:45.035599 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4202 05:56:45.038917 0 9 12 | B1->B0 | 3333 3131 | 0 0 | (0 1) (0 1)
4203 05:56:45.042199 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
4204 05:56:45.049149 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 05:56:45.052668 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 05:56:45.055777 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 05:56:45.062199 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 05:56:45.065681 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 05:56:45.068862 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 05:56:45.075751 0 10 12 | B1->B0 | 2b2b 2e2d | 0 1 | (0 0) (0 0)
4211 05:56:45.079098 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4212 05:56:45.082062 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 05:56:45.089019 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 05:56:45.092236 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 05:56:45.095589 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 05:56:45.101931 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 05:56:45.105525 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 05:56:45.108972 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 05:56:45.115441 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4220 05:56:45.118939 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 05:56:45.121844 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 05:56:45.128368 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 05:56:45.131880 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 05:56:45.135448 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 05:56:45.141956 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 05:56:45.145230 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 05:56:45.148564 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 05:56:45.155589 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 05:56:45.158601 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 05:56:45.162284 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 05:56:45.168730 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 05:56:45.172170 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 05:56:45.175176 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 05:56:45.178560 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4235 05:56:45.185340 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 05:56:45.188396 Total UI for P1: 0, mck2ui 16
4237 05:56:45.191878 best dqsien dly found for B0: ( 0, 13, 12)
4238 05:56:45.195360 Total UI for P1: 0, mck2ui 16
4239 05:56:45.198461 best dqsien dly found for B1: ( 0, 13, 12)
4240 05:56:45.201890 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4241 05:56:45.205205 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4242 05:56:45.205288
4243 05:56:45.208690 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4244 05:56:45.211771 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4245 05:56:45.215385 [Gating] SW calibration Done
4246 05:56:45.215469 ==
4247 05:56:45.218323 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 05:56:45.221849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 05:56:45.221992 ==
4250 05:56:45.224979 RX Vref Scan: 0
4251 05:56:45.225062
4252 05:56:45.228547 RX Vref 0 -> 0, step: 1
4253 05:56:45.228631
4254 05:56:45.228697 RX Delay -230 -> 252, step: 16
4255 05:56:45.234954 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4256 05:56:45.238418 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4257 05:56:45.241371 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4258 05:56:45.244859 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4259 05:56:45.251587 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4260 05:56:45.254978 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4261 05:56:45.257998 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4262 05:56:45.261445 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4263 05:56:45.264859 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4264 05:56:45.271456 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4265 05:56:45.274943 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4266 05:56:45.277877 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4267 05:56:45.281500 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4268 05:56:45.288002 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4269 05:56:45.291510 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4270 05:56:45.294980 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4271 05:56:45.295064 ==
4272 05:56:45.297848 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 05:56:45.301435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 05:56:45.304893 ==
4275 05:56:45.304977 DQS Delay:
4276 05:56:45.305043 DQS0 = 0, DQS1 = 0
4277 05:56:45.307947 DQM Delay:
4278 05:56:45.308030 DQM0 = 48, DQM1 = 43
4279 05:56:45.311295 DQ Delay:
4280 05:56:45.311414 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =41
4281 05:56:45.314631 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4282 05:56:45.317895 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4283 05:56:45.321500 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4284 05:56:45.321583
4285 05:56:45.324579
4286 05:56:45.324661 ==
4287 05:56:45.328210 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 05:56:45.331420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 05:56:45.331504 ==
4290 05:56:45.331570
4291 05:56:45.331633
4292 05:56:45.334512 TX Vref Scan disable
4293 05:56:45.334596 == TX Byte 0 ==
4294 05:56:45.341380 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4295 05:56:45.344370 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4296 05:56:45.344453 == TX Byte 1 ==
4297 05:56:45.351162 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4298 05:56:45.354537 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4299 05:56:45.354621 ==
4300 05:56:45.357901 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 05:56:45.361262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 05:56:45.361345 ==
4303 05:56:45.361412
4304 05:56:45.361472
4305 05:56:45.364150 TX Vref Scan disable
4306 05:56:45.367615 == TX Byte 0 ==
4307 05:56:45.371196 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4308 05:56:45.377627 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4309 05:56:45.377710 == TX Byte 1 ==
4310 05:56:45.381225 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4311 05:56:45.387599 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4312 05:56:45.387682
4313 05:56:45.387749 [DATLAT]
4314 05:56:45.387809 Freq=600, CH0 RK1
4315 05:56:45.387869
4316 05:56:45.390926 DATLAT Default: 0x9
4317 05:56:45.391035 0, 0xFFFF, sum = 0
4318 05:56:45.394391 1, 0xFFFF, sum = 0
4319 05:56:45.394476 2, 0xFFFF, sum = 0
4320 05:56:45.397839 3, 0xFFFF, sum = 0
4321 05:56:45.400746 4, 0xFFFF, sum = 0
4322 05:56:45.400830 5, 0xFFFF, sum = 0
4323 05:56:45.404117 6, 0xFFFF, sum = 0
4324 05:56:45.404202 7, 0xFFFF, sum = 0
4325 05:56:45.407607 8, 0x0, sum = 1
4326 05:56:45.407691 9, 0x0, sum = 2
4327 05:56:45.407758 10, 0x0, sum = 3
4328 05:56:45.410652 11, 0x0, sum = 4
4329 05:56:45.410763 best_step = 9
4330 05:56:45.410874
4331 05:56:45.410941 ==
4332 05:56:45.414185 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 05:56:45.420588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 05:56:45.420673 ==
4335 05:56:45.420739 RX Vref Scan: 0
4336 05:56:45.420799
4337 05:56:45.423889 RX Vref 0 -> 0, step: 1
4338 05:56:45.423971
4339 05:56:45.427400 RX Delay -179 -> 252, step: 8
4340 05:56:45.430939 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4341 05:56:45.437253 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4342 05:56:45.440843 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4343 05:56:45.444117 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4344 05:56:45.447205 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4345 05:56:45.450796 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4346 05:56:45.457269 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4347 05:56:45.460470 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4348 05:56:45.464047 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4349 05:56:45.467395 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4350 05:56:45.470390 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4351 05:56:45.476979 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4352 05:56:45.480394 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4353 05:56:45.483899 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4354 05:56:45.487388 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4355 05:56:45.494006 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4356 05:56:45.494087 ==
4357 05:56:45.496964 Dram Type= 6, Freq= 0, CH_0, rank 1
4358 05:56:45.500414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 05:56:45.500495 ==
4360 05:56:45.500559 DQS Delay:
4361 05:56:45.503854 DQS0 = 0, DQS1 = 0
4362 05:56:45.503935 DQM Delay:
4363 05:56:45.507341 DQM0 = 48, DQM1 = 40
4364 05:56:45.507422 DQ Delay:
4365 05:56:45.510223 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4366 05:56:45.513609 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =52
4367 05:56:45.517090 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4368 05:56:45.520475 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4369 05:56:45.520556
4370 05:56:45.520623
4371 05:56:45.527042 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e2b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
4372 05:56:45.530373 CH0 RK1: MR19=808, MR18=5E2B
4373 05:56:45.537183 CH0_RK1: MR19=0x808, MR18=0x5E2B, DQSOSC=392, MR23=63, INC=170, DEC=113
4374 05:56:45.540174 [RxdqsGatingPostProcess] freq 600
4375 05:56:45.546973 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4376 05:56:45.550239 Pre-setting of DQS Precalculation
4377 05:56:45.554120 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4378 05:56:45.554201 ==
4379 05:56:45.556688 Dram Type= 6, Freq= 0, CH_1, rank 0
4380 05:56:45.560546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4381 05:56:45.560628 ==
4382 05:56:45.566993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4383 05:56:45.573919 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4384 05:56:45.576874 [CA 0] Center 35 (5~66) winsize 62
4385 05:56:45.580395 [CA 1] Center 35 (5~66) winsize 62
4386 05:56:45.583957 [CA 2] Center 34 (4~65) winsize 62
4387 05:56:45.586933 [CA 3] Center 33 (3~64) winsize 62
4388 05:56:45.590425 [CA 4] Center 33 (3~64) winsize 62
4389 05:56:45.593894 [CA 5] Center 33 (3~64) winsize 62
4390 05:56:45.594015
4391 05:56:45.596855 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4392 05:56:45.596936
4393 05:56:45.600206 [CATrainingPosCal] consider 1 rank data
4394 05:56:45.603387 u2DelayCellTimex100 = 270/100 ps
4395 05:56:45.606879 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4396 05:56:45.610368 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4397 05:56:45.613444 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4398 05:56:45.617058 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4399 05:56:45.619926 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4400 05:56:45.626759 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4401 05:56:45.626841
4402 05:56:45.629685 CA PerBit enable=1, Macro0, CA PI delay=33
4403 05:56:45.629767
4404 05:56:45.633102 [CBTSetCACLKResult] CA Dly = 33
4405 05:56:45.633184 CS Dly: 5 (0~36)
4406 05:56:45.633248 ==
4407 05:56:45.636420 Dram Type= 6, Freq= 0, CH_1, rank 1
4408 05:56:45.639718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 05:56:45.643123 ==
4410 05:56:45.646809 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4411 05:56:45.652860 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4412 05:56:45.656602 [CA 0] Center 35 (5~66) winsize 62
4413 05:56:45.659887 [CA 1] Center 35 (5~66) winsize 62
4414 05:56:45.662733 [CA 2] Center 34 (4~65) winsize 62
4415 05:56:45.666056 [CA 3] Center 34 (4~65) winsize 62
4416 05:56:45.669609 [CA 4] Center 34 (4~65) winsize 62
4417 05:56:45.672964 [CA 5] Center 34 (4~64) winsize 61
4418 05:56:45.673045
4419 05:56:45.675932 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4420 05:56:45.676013
4421 05:56:45.679387 [CATrainingPosCal] consider 2 rank data
4422 05:56:45.682829 u2DelayCellTimex100 = 270/100 ps
4423 05:56:45.686371 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4424 05:56:45.689321 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4425 05:56:45.692898 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4426 05:56:45.699340 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4427 05:56:45.702715 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4428 05:56:45.706152 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4429 05:56:45.706233
4430 05:56:45.709486 CA PerBit enable=1, Macro0, CA PI delay=34
4431 05:56:45.709591
4432 05:56:45.712439 [CBTSetCACLKResult] CA Dly = 34
4433 05:56:45.712520 CS Dly: 5 (0~37)
4434 05:56:45.712584
4435 05:56:45.715893 ----->DramcWriteLeveling(PI) begin...
4436 05:56:45.715980 ==
4437 05:56:45.718943 Dram Type= 6, Freq= 0, CH_1, rank 0
4438 05:56:45.725857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 05:56:45.725982 ==
4440 05:56:45.728808 Write leveling (Byte 0): 29 => 29
4441 05:56:45.732423 Write leveling (Byte 1): 31 => 31
4442 05:56:45.735370 DramcWriteLeveling(PI) end<-----
4443 05:56:45.735442
4444 05:56:45.735508 ==
4445 05:56:45.738882 Dram Type= 6, Freq= 0, CH_1, rank 0
4446 05:56:45.742271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 05:56:45.742344 ==
4448 05:56:45.745452 [Gating] SW mode calibration
4449 05:56:45.752335 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4450 05:56:45.755223 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4451 05:56:45.762106 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4452 05:56:45.765272 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4453 05:56:45.768582 0 9 8 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
4454 05:56:45.775216 0 9 12 | B1->B0 | 2b2b 2727 | 0 0 | (1 1) (0 0)
4455 05:56:45.778800 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 05:56:45.782080 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 05:56:45.788674 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 05:56:45.792168 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 05:56:45.795135 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 05:56:45.801850 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 05:56:45.805136 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4462 05:56:45.808528 0 10 12 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
4463 05:56:45.815551 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 05:56:45.818574 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 05:56:45.822158 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 05:56:45.828337 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 05:56:45.831813 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 05:56:45.835117 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 05:56:45.842055 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4470 05:56:45.844883 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4471 05:56:45.848105 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 05:56:45.855385 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 05:56:45.858317 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 05:56:45.861887 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 05:56:45.868391 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 05:56:45.871954 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 05:56:45.874748 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 05:56:45.881602 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 05:56:45.884771 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 05:56:45.888234 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 05:56:45.894723 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 05:56:45.898225 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 05:56:45.901258 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 05:56:45.908103 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 05:56:45.911444 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4486 05:56:45.914848 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4487 05:56:45.917847 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 05:56:45.921390 Total UI for P1: 0, mck2ui 16
4489 05:56:45.924435 best dqsien dly found for B0: ( 0, 13, 10)
4490 05:56:45.928076 Total UI for P1: 0, mck2ui 16
4491 05:56:45.931427 best dqsien dly found for B1: ( 0, 13, 12)
4492 05:56:45.934361 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4493 05:56:45.941331 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4494 05:56:45.941432
4495 05:56:45.944877 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4496 05:56:45.947920 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4497 05:56:45.951108 [Gating] SW calibration Done
4498 05:56:45.951188 ==
4499 05:56:45.954646 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 05:56:45.958088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 05:56:45.958169 ==
4502 05:56:45.961019 RX Vref Scan: 0
4503 05:56:45.961099
4504 05:56:45.961162 RX Vref 0 -> 0, step: 1
4505 05:56:45.961221
4506 05:56:45.964388 RX Delay -230 -> 252, step: 16
4507 05:56:45.967836 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4508 05:56:45.974308 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4509 05:56:45.977870 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4510 05:56:45.981075 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4511 05:56:45.984001 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4512 05:56:45.991037 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4513 05:56:45.993935 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4514 05:56:45.997707 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4515 05:56:46.000826 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4516 05:56:46.004443 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4517 05:56:46.010790 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4518 05:56:46.014136 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4519 05:56:46.017406 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4520 05:56:46.020929 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4521 05:56:46.027452 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4522 05:56:46.031184 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4523 05:56:46.031268 ==
4524 05:56:46.034141 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 05:56:46.037530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 05:56:46.037615 ==
4527 05:56:46.040576 DQS Delay:
4528 05:56:46.040659 DQS0 = 0, DQS1 = 0
4529 05:56:46.040726 DQM Delay:
4530 05:56:46.043895 DQM0 = 48, DQM1 = 41
4531 05:56:46.043978 DQ Delay:
4532 05:56:46.047229 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4533 05:56:46.050769 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =49
4534 05:56:46.053986 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4535 05:56:46.057296 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =41
4536 05:56:46.057379
4537 05:56:46.057445
4538 05:56:46.057506 ==
4539 05:56:46.060580 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 05:56:46.067049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 05:56:46.067132 ==
4542 05:56:46.067198
4543 05:56:46.067258
4544 05:56:46.067317 TX Vref Scan disable
4545 05:56:46.071148 == TX Byte 0 ==
4546 05:56:46.074046 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4547 05:56:46.081076 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4548 05:56:46.081160 == TX Byte 1 ==
4549 05:56:46.083989 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4550 05:56:46.090705 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4551 05:56:46.090789 ==
4552 05:56:46.093889 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 05:56:46.097095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 05:56:46.097178 ==
4555 05:56:46.097243
4556 05:56:46.097304
4557 05:56:46.100718 TX Vref Scan disable
4558 05:56:46.103794 == TX Byte 0 ==
4559 05:56:46.107330 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4560 05:56:46.110718 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4561 05:56:46.113633 == TX Byte 1 ==
4562 05:56:46.116991 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4563 05:56:46.120650 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4564 05:56:46.120733
4565 05:56:46.120798 [DATLAT]
4566 05:56:46.123953 Freq=600, CH1 RK0
4567 05:56:46.124036
4568 05:56:46.126995 DATLAT Default: 0x9
4569 05:56:46.127078 0, 0xFFFF, sum = 0
4570 05:56:46.130420 1, 0xFFFF, sum = 0
4571 05:56:46.130505 2, 0xFFFF, sum = 0
4572 05:56:46.133922 3, 0xFFFF, sum = 0
4573 05:56:46.134043 4, 0xFFFF, sum = 0
4574 05:56:46.136948 5, 0xFFFF, sum = 0
4575 05:56:46.137032 6, 0xFFFF, sum = 0
4576 05:56:46.140402 7, 0xFFFF, sum = 0
4577 05:56:46.140486 8, 0x0, sum = 1
4578 05:56:46.143953 9, 0x0, sum = 2
4579 05:56:46.144038 10, 0x0, sum = 3
4580 05:56:46.144106 11, 0x0, sum = 4
4581 05:56:46.147226 best_step = 9
4582 05:56:46.147309
4583 05:56:46.147374 ==
4584 05:56:46.150348 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 05:56:46.153862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 05:56:46.153953 ==
4587 05:56:46.157174 RX Vref Scan: 1
4588 05:56:46.157257
4589 05:56:46.157322 RX Vref 0 -> 0, step: 1
4590 05:56:46.160122
4591 05:56:46.160205 RX Delay -179 -> 252, step: 8
4592 05:56:46.160271
4593 05:56:46.163721 Set Vref, RX VrefLevel [Byte0]: 52
4594 05:56:46.166827 [Byte1]: 52
4595 05:56:46.171432
4596 05:56:46.171515 Final RX Vref Byte 0 = 52 to rank0
4597 05:56:46.174418 Final RX Vref Byte 1 = 52 to rank0
4598 05:56:46.177866 Final RX Vref Byte 0 = 52 to rank1
4599 05:56:46.181309 Final RX Vref Byte 1 = 52 to rank1==
4600 05:56:46.184682 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 05:56:46.191147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 05:56:46.191232 ==
4603 05:56:46.191298 DQS Delay:
4604 05:56:46.191358 DQS0 = 0, DQS1 = 0
4605 05:56:46.194695 DQM Delay:
4606 05:56:46.194777 DQM0 = 47, DQM1 = 41
4607 05:56:46.198046 DQ Delay:
4608 05:56:46.201223 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4609 05:56:46.201307 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4610 05:56:46.204516 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4611 05:56:46.208081 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4612 05:56:46.211465
4613 05:56:46.211548
4614 05:56:46.217814 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d74, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4615 05:56:46.221198 CH1 RK0: MR19=808, MR18=4D74
4616 05:56:46.227822 CH1_RK0: MR19=0x808, MR18=0x4D74, DQSOSC=388, MR23=63, INC=174, DEC=116
4617 05:56:46.227906
4618 05:56:46.231293 ----->DramcWriteLeveling(PI) begin...
4619 05:56:46.231378 ==
4620 05:56:46.234344 Dram Type= 6, Freq= 0, CH_1, rank 1
4621 05:56:46.237840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 05:56:46.237924 ==
4623 05:56:46.241303 Write leveling (Byte 0): 28 => 28
4624 05:56:46.244294 Write leveling (Byte 1): 29 => 29
4625 05:56:46.247839 DramcWriteLeveling(PI) end<-----
4626 05:56:46.247922
4627 05:56:46.247988 ==
4628 05:56:46.251349 Dram Type= 6, Freq= 0, CH_1, rank 1
4629 05:56:46.254475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 05:56:46.254559 ==
4631 05:56:46.257739 [Gating] SW mode calibration
4632 05:56:46.264209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4633 05:56:46.270888 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4634 05:56:46.273879 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4635 05:56:46.280813 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4636 05:56:46.284281 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4637 05:56:46.287492 0 9 12 | B1->B0 | 2e2e 3333 | 0 0 | (1 1) (1 1)
4638 05:56:46.293808 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 05:56:46.297283 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 05:56:46.300881 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 05:56:46.304021 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 05:56:46.310864 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 05:56:46.313739 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 05:56:46.317328 0 10 8 | B1->B0 | 2827 2323 | 1 0 | (0 0) (0 0)
4645 05:56:46.323815 0 10 12 | B1->B0 | 3838 2e2e | 0 0 | (0 0) (0 0)
4646 05:56:46.327043 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 05:56:46.330376 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 05:56:46.336886 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 05:56:46.340414 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 05:56:46.343841 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 05:56:46.350315 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 05:56:46.353839 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 05:56:46.356812 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4654 05:56:46.363326 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 05:56:46.366723 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 05:56:46.370144 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 05:56:46.376819 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 05:56:46.380116 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 05:56:46.383397 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 05:56:46.389839 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 05:56:46.393109 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 05:56:46.396509 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 05:56:46.403015 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 05:56:46.406409 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 05:56:46.409700 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 05:56:46.416588 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 05:56:46.419848 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 05:56:46.422933 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 05:56:46.429890 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4670 05:56:46.430017 Total UI for P1: 0, mck2ui 16
4671 05:56:46.436411 best dqsien dly found for B0: ( 0, 13, 10)
4672 05:56:46.439926 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 05:56:46.442814 Total UI for P1: 0, mck2ui 16
4674 05:56:46.446337 best dqsien dly found for B1: ( 0, 13, 12)
4675 05:56:46.449820 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4676 05:56:46.452891 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4677 05:56:46.452974
4678 05:56:46.455916 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4679 05:56:46.459309 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4680 05:56:46.462610 [Gating] SW calibration Done
4681 05:56:46.462694 ==
4682 05:56:46.466175 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 05:56:46.472556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 05:56:46.472640 ==
4685 05:56:46.472706 RX Vref Scan: 0
4686 05:56:46.472766
4687 05:56:46.475839 RX Vref 0 -> 0, step: 1
4688 05:56:46.475923
4689 05:56:46.479434 RX Delay -230 -> 252, step: 16
4690 05:56:46.482358 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4691 05:56:46.485911 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4692 05:56:46.489374 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4693 05:56:46.495614 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4694 05:56:46.499294 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4695 05:56:46.502323 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4696 05:56:46.505844 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4697 05:56:46.508885 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4698 05:56:46.516048 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4699 05:56:46.518890 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4700 05:56:46.522307 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4701 05:56:46.525807 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4702 05:56:46.532446 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4703 05:56:46.535498 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4704 05:56:46.539065 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4705 05:56:46.542149 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4706 05:56:46.542259 ==
4707 05:56:46.545566 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 05:56:46.552102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 05:56:46.552185 ==
4710 05:56:46.552250 DQS Delay:
4711 05:56:46.555941 DQS0 = 0, DQS1 = 0
4712 05:56:46.556023 DQM Delay:
4713 05:56:46.556089 DQM0 = 51, DQM1 = 46
4714 05:56:46.558832 DQ Delay:
4715 05:56:46.562345 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4716 05:56:46.565714 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4717 05:56:46.568972 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4718 05:56:46.572121 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4719 05:56:46.572203
4720 05:56:46.572268
4721 05:56:46.572329 ==
4722 05:56:46.575668 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 05:56:46.579081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 05:56:46.579164 ==
4725 05:56:46.579230
4726 05:56:46.579291
4727 05:56:46.582326 TX Vref Scan disable
4728 05:56:46.582408 == TX Byte 0 ==
4729 05:56:46.589252 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4730 05:56:46.592294 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4731 05:56:46.592377 == TX Byte 1 ==
4732 05:56:46.598700 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4733 05:56:46.602516 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4734 05:56:46.602598 ==
4735 05:56:46.605399 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 05:56:46.608801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 05:56:46.608884 ==
4738 05:56:46.608950
4739 05:56:46.609010
4740 05:56:46.612324 TX Vref Scan disable
4741 05:56:46.615328 == TX Byte 0 ==
4742 05:56:46.618841 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4743 05:56:46.625344 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4744 05:56:46.625428 == TX Byte 1 ==
4745 05:56:46.628926 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4746 05:56:46.635583 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4747 05:56:46.635666
4748 05:56:46.635731 [DATLAT]
4749 05:56:46.635792 Freq=600, CH1 RK1
4750 05:56:46.635851
4751 05:56:46.638841 DATLAT Default: 0x9
4752 05:56:46.638951 0, 0xFFFF, sum = 0
4753 05:56:46.641813 1, 0xFFFF, sum = 0
4754 05:56:46.645356 2, 0xFFFF, sum = 0
4755 05:56:46.645456 3, 0xFFFF, sum = 0
4756 05:56:46.648863 4, 0xFFFF, sum = 0
4757 05:56:46.648966 5, 0xFFFF, sum = 0
4758 05:56:46.652070 6, 0xFFFF, sum = 0
4759 05:56:46.652148 7, 0xFFFF, sum = 0
4760 05:56:46.655029 8, 0x0, sum = 1
4761 05:56:46.655098 9, 0x0, sum = 2
4762 05:56:46.655163 10, 0x0, sum = 3
4763 05:56:46.658439 11, 0x0, sum = 4
4764 05:56:46.658540 best_step = 9
4765 05:56:46.658628
4766 05:56:46.658715 ==
4767 05:56:46.661625 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 05:56:46.668733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 05:56:46.668810 ==
4770 05:56:46.668873 RX Vref Scan: 0
4771 05:56:46.668935
4772 05:56:46.671772 RX Vref 0 -> 0, step: 1
4773 05:56:46.671855
4774 05:56:46.675054 RX Delay -179 -> 252, step: 8
4775 05:56:46.678559 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4776 05:56:46.684852 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4777 05:56:46.688181 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4778 05:56:46.691516 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4779 05:56:46.695034 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4780 05:56:46.698342 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4781 05:56:46.704754 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4782 05:56:46.708151 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4783 05:56:46.711635 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4784 05:56:46.714734 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4785 05:56:46.721348 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4786 05:56:46.724899 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4787 05:56:46.728013 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4788 05:56:46.731339 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4789 05:56:46.734898 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4790 05:56:46.741411 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4791 05:56:46.741494 ==
4792 05:56:46.744873 Dram Type= 6, Freq= 0, CH_1, rank 1
4793 05:56:46.748033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4794 05:56:46.748117 ==
4795 05:56:46.748183 DQS Delay:
4796 05:56:46.751409 DQS0 = 0, DQS1 = 0
4797 05:56:46.751493 DQM Delay:
4798 05:56:46.754466 DQM0 = 48, DQM1 = 42
4799 05:56:46.754549 DQ Delay:
4800 05:56:46.758003 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4801 05:56:46.761133 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4802 05:56:46.764607 DQ8 =32, DQ9 =32, DQ10 =40, DQ11 =36
4803 05:56:46.768189 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4804 05:56:46.768272
4805 05:56:46.768338
4806 05:56:46.777668 [DQSOSCAuto] RK1, (LSB)MR18= 0x5117, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
4807 05:56:46.777753 CH1 RK1: MR19=808, MR18=5117
4808 05:56:46.784465 CH1_RK1: MR19=0x808, MR18=0x5117, DQSOSC=394, MR23=63, INC=168, DEC=112
4809 05:56:46.787841 [RxdqsGatingPostProcess] freq 600
4810 05:56:46.794558 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4811 05:56:46.797822 Pre-setting of DQS Precalculation
4812 05:56:46.801271 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4813 05:56:46.807851 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4814 05:56:46.814593 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4815 05:56:46.814677
4816 05:56:46.817577
4817 05:56:46.817660 [Calibration Summary] 1200 Mbps
4818 05:56:46.821106 CH 0, Rank 0
4819 05:56:46.821189 SW Impedance : PASS
4820 05:56:46.824365 DUTY Scan : NO K
4821 05:56:46.827535 ZQ Calibration : PASS
4822 05:56:46.827619 Jitter Meter : NO K
4823 05:56:46.830958 CBT Training : PASS
4824 05:56:46.834439 Write leveling : PASS
4825 05:56:46.834522 RX DQS gating : PASS
4826 05:56:46.837759 RX DQ/DQS(RDDQC) : PASS
4827 05:56:46.840858 TX DQ/DQS : PASS
4828 05:56:46.840942 RX DATLAT : PASS
4829 05:56:46.844266 RX DQ/DQS(Engine): PASS
4830 05:56:46.847862 TX OE : NO K
4831 05:56:46.847946 All Pass.
4832 05:56:46.848012
4833 05:56:46.848073 CH 0, Rank 1
4834 05:56:46.851467 SW Impedance : PASS
4835 05:56:46.854135 DUTY Scan : NO K
4836 05:56:46.854219 ZQ Calibration : PASS
4837 05:56:46.857424 Jitter Meter : NO K
4838 05:56:46.857507 CBT Training : PASS
4839 05:56:46.861086 Write leveling : PASS
4840 05:56:46.864138 RX DQS gating : PASS
4841 05:56:46.864222 RX DQ/DQS(RDDQC) : PASS
4842 05:56:46.867619 TX DQ/DQS : PASS
4843 05:56:46.871066 RX DATLAT : PASS
4844 05:56:46.871150 RX DQ/DQS(Engine): PASS
4845 05:56:46.874095 TX OE : NO K
4846 05:56:46.874178 All Pass.
4847 05:56:46.874244
4848 05:56:46.877525 CH 1, Rank 0
4849 05:56:46.877607 SW Impedance : PASS
4850 05:56:46.880831 DUTY Scan : NO K
4851 05:56:46.884240 ZQ Calibration : PASS
4852 05:56:46.884323 Jitter Meter : NO K
4853 05:56:46.887773 CBT Training : PASS
4854 05:56:46.890658 Write leveling : PASS
4855 05:56:46.890741 RX DQS gating : PASS
4856 05:56:46.893952 RX DQ/DQS(RDDQC) : PASS
4857 05:56:46.897389 TX DQ/DQS : PASS
4858 05:56:46.897472 RX DATLAT : PASS
4859 05:56:46.900786 RX DQ/DQS(Engine): PASS
4860 05:56:46.904068 TX OE : NO K
4861 05:56:46.904152 All Pass.
4862 05:56:46.904217
4863 05:56:46.904278 CH 1, Rank 1
4864 05:56:46.907541 SW Impedance : PASS
4865 05:56:46.910812 DUTY Scan : NO K
4866 05:56:46.910895 ZQ Calibration : PASS
4867 05:56:46.914213 Jitter Meter : NO K
4868 05:56:46.914296 CBT Training : PASS
4869 05:56:46.917249 Write leveling : PASS
4870 05:56:46.920709 RX DQS gating : PASS
4871 05:56:46.920792 RX DQ/DQS(RDDQC) : PASS
4872 05:56:46.924106 TX DQ/DQS : PASS
4873 05:56:46.927177 RX DATLAT : PASS
4874 05:56:46.927260 RX DQ/DQS(Engine): PASS
4875 05:56:46.930868 TX OE : NO K
4876 05:56:46.930951 All Pass.
4877 05:56:46.931017
4878 05:56:46.933873 DramC Write-DBI off
4879 05:56:46.937389 PER_BANK_REFRESH: Hybrid Mode
4880 05:56:46.937472 TX_TRACKING: ON
4881 05:56:46.946946 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4882 05:56:46.950526 [FAST_K] Save calibration result to emmc
4883 05:56:46.953836 dramc_set_vcore_voltage set vcore to 662500
4884 05:56:46.957457 Read voltage for 933, 3
4885 05:56:46.957540 Vio18 = 0
4886 05:56:46.957606 Vcore = 662500
4887 05:56:46.960475 Vdram = 0
4888 05:56:46.960558 Vddq = 0
4889 05:56:46.960624 Vmddr = 0
4890 05:56:46.967017 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4891 05:56:46.970477 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4892 05:56:46.973712 MEM_TYPE=3, freq_sel=17
4893 05:56:46.977484 sv_algorithm_assistance_LP4_1600
4894 05:56:46.980637 ============ PULL DRAM RESETB DOWN ============
4895 05:56:46.983868 ========== PULL DRAM RESETB DOWN end =========
4896 05:56:46.990438 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4897 05:56:46.993876 ===================================
4898 05:56:46.993971 LPDDR4 DRAM CONFIGURATION
4899 05:56:46.997186 ===================================
4900 05:56:47.000431 EX_ROW_EN[0] = 0x0
4901 05:56:47.003567 EX_ROW_EN[1] = 0x0
4902 05:56:47.003650 LP4Y_EN = 0x0
4903 05:56:47.007060 WORK_FSP = 0x0
4904 05:56:47.007144 WL = 0x3
4905 05:56:47.010547 RL = 0x3
4906 05:56:47.010631 BL = 0x2
4907 05:56:47.013546 RPST = 0x0
4908 05:56:47.013629 RD_PRE = 0x0
4909 05:56:47.016846 WR_PRE = 0x1
4910 05:56:47.016929 WR_PST = 0x0
4911 05:56:47.020314 DBI_WR = 0x0
4912 05:56:47.020397 DBI_RD = 0x0
4913 05:56:47.023777 OTF = 0x1
4914 05:56:47.026787 ===================================
4915 05:56:47.030317 ===================================
4916 05:56:47.030400 ANA top config
4917 05:56:47.033690 ===================================
4918 05:56:47.037028 DLL_ASYNC_EN = 0
4919 05:56:47.040171 ALL_SLAVE_EN = 1
4920 05:56:47.043404 NEW_RANK_MODE = 1
4921 05:56:47.043488 DLL_IDLE_MODE = 1
4922 05:56:47.046934 LP45_APHY_COMB_EN = 1
4923 05:56:47.049969 TX_ODT_DIS = 1
4924 05:56:47.053461 NEW_8X_MODE = 1
4925 05:56:47.056909 ===================================
4926 05:56:47.059911 ===================================
4927 05:56:47.063389 data_rate = 1866
4928 05:56:47.063473 CKR = 1
4929 05:56:47.066843 DQ_P2S_RATIO = 8
4930 05:56:47.070115 ===================================
4931 05:56:47.073290 CA_P2S_RATIO = 8
4932 05:56:47.076535 DQ_CA_OPEN = 0
4933 05:56:47.080347 DQ_SEMI_OPEN = 0
4934 05:56:47.083459 CA_SEMI_OPEN = 0
4935 05:56:47.083533 CA_FULL_RATE = 0
4936 05:56:47.086644 DQ_CKDIV4_EN = 1
4937 05:56:47.089827 CA_CKDIV4_EN = 1
4938 05:56:47.093066 CA_PREDIV_EN = 0
4939 05:56:47.096509 PH8_DLY = 0
4940 05:56:47.099704 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4941 05:56:47.099783 DQ_AAMCK_DIV = 4
4942 05:56:47.103173 CA_AAMCK_DIV = 4
4943 05:56:47.106321 CA_ADMCK_DIV = 4
4944 05:56:47.109771 DQ_TRACK_CA_EN = 0
4945 05:56:47.113237 CA_PICK = 933
4946 05:56:47.116734 CA_MCKIO = 933
4947 05:56:47.116809 MCKIO_SEMI = 0
4948 05:56:47.119767 PLL_FREQ = 3732
4949 05:56:47.123032 DQ_UI_PI_RATIO = 32
4950 05:56:47.126617 CA_UI_PI_RATIO = 0
4951 05:56:47.129599 ===================================
4952 05:56:47.132999 ===================================
4953 05:56:47.136492 memory_type:LPDDR4
4954 05:56:47.136564 GP_NUM : 10
4955 05:56:47.139717 SRAM_EN : 1
4956 05:56:47.143292 MD32_EN : 0
4957 05:56:47.146275 ===================================
4958 05:56:47.146359 [ANA_INIT] >>>>>>>>>>>>>>
4959 05:56:47.149711 <<<<<< [CONFIGURE PHASE]: ANA_TX
4960 05:56:47.153133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4961 05:56:47.156635 ===================================
4962 05:56:47.159780 data_rate = 1866,PCW = 0X8f00
4963 05:56:47.163079 ===================================
4964 05:56:47.166491 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4965 05:56:47.172832 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4966 05:56:47.176596 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4967 05:56:47.183177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4968 05:56:47.186458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4969 05:56:47.189776 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4970 05:56:47.189860 [ANA_INIT] flow start
4971 05:56:47.192863 [ANA_INIT] PLL >>>>>>>>
4972 05:56:47.196396 [ANA_INIT] PLL <<<<<<<<
4973 05:56:47.199495 [ANA_INIT] MIDPI >>>>>>>>
4974 05:56:47.199578 [ANA_INIT] MIDPI <<<<<<<<
4975 05:56:47.202893 [ANA_INIT] DLL >>>>>>>>
4976 05:56:47.206066 [ANA_INIT] flow end
4977 05:56:47.209662 ============ LP4 DIFF to SE enter ============
4978 05:56:47.213108 ============ LP4 DIFF to SE exit ============
4979 05:56:47.216225 [ANA_INIT] <<<<<<<<<<<<<
4980 05:56:47.219715 [Flow] Enable top DCM control >>>>>
4981 05:56:47.222648 [Flow] Enable top DCM control <<<<<
4982 05:56:47.225807 Enable DLL master slave shuffle
4983 05:56:47.229355 ==============================================================
4984 05:56:47.233016 Gating Mode config
4985 05:56:47.239453 ==============================================================
4986 05:56:47.239537 Config description:
4987 05:56:47.249078 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4988 05:56:47.256119 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4989 05:56:47.259107 SELPH_MODE 0: By rank 1: By Phase
4990 05:56:47.265882 ==============================================================
4991 05:56:47.268920 GAT_TRACK_EN = 1
4992 05:56:47.272471 RX_GATING_MODE = 2
4993 05:56:47.275929 RX_GATING_TRACK_MODE = 2
4994 05:56:47.278848 SELPH_MODE = 1
4995 05:56:47.282182 PICG_EARLY_EN = 1
4996 05:56:47.285842 VALID_LAT_VALUE = 1
4997 05:56:47.288848 ==============================================================
4998 05:56:47.293009 Enter into Gating configuration >>>>
4999 05:56:47.295391 Exit from Gating configuration <<<<
5000 05:56:47.299136 Enter into DVFS_PRE_config >>>>>
5001 05:56:47.309026 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5002 05:56:47.312421 Exit from DVFS_PRE_config <<<<<
5003 05:56:47.315687 Enter into PICG configuration >>>>
5004 05:56:47.318923 Exit from PICG configuration <<<<
5005 05:56:47.321916 [RX_INPUT] configuration >>>>>
5006 05:56:47.325496 [RX_INPUT] configuration <<<<<
5007 05:56:47.332176 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5008 05:56:47.335145 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5009 05:56:47.342143 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5010 05:56:47.348889 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5011 05:56:47.355397 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5012 05:56:47.361867 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5013 05:56:47.365359 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5014 05:56:47.368357 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5015 05:56:47.371827 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5016 05:56:47.378212 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5017 05:56:47.381838 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5018 05:56:47.385112 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5019 05:56:47.388482 ===================================
5020 05:56:47.391950 LPDDR4 DRAM CONFIGURATION
5021 05:56:47.395359 ===================================
5022 05:56:47.395443 EX_ROW_EN[0] = 0x0
5023 05:56:47.398520 EX_ROW_EN[1] = 0x0
5024 05:56:47.401897 LP4Y_EN = 0x0
5025 05:56:47.401988 WORK_FSP = 0x0
5026 05:56:47.405026 WL = 0x3
5027 05:56:47.405110 RL = 0x3
5028 05:56:47.408386 BL = 0x2
5029 05:56:47.408469 RPST = 0x0
5030 05:56:47.411486 RD_PRE = 0x0
5031 05:56:47.411569 WR_PRE = 0x1
5032 05:56:47.414857 WR_PST = 0x0
5033 05:56:47.414941 DBI_WR = 0x0
5034 05:56:47.418327 DBI_RD = 0x0
5035 05:56:47.418411 OTF = 0x1
5036 05:56:47.421521 ===================================
5037 05:56:47.424862 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5038 05:56:47.431774 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5039 05:56:47.435013 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5040 05:56:47.438386 ===================================
5041 05:56:47.441491 LPDDR4 DRAM CONFIGURATION
5042 05:56:47.444869 ===================================
5043 05:56:47.444952 EX_ROW_EN[0] = 0x10
5044 05:56:47.448357 EX_ROW_EN[1] = 0x0
5045 05:56:47.448440 LP4Y_EN = 0x0
5046 05:56:47.451606 WORK_FSP = 0x0
5047 05:56:47.454532 WL = 0x3
5048 05:56:47.454615 RL = 0x3
5049 05:56:47.458047 BL = 0x2
5050 05:56:47.458130 RPST = 0x0
5051 05:56:47.461631 RD_PRE = 0x0
5052 05:56:47.461714 WR_PRE = 0x1
5053 05:56:47.464666 WR_PST = 0x0
5054 05:56:47.464749 DBI_WR = 0x0
5055 05:56:47.468195 DBI_RD = 0x0
5056 05:56:47.468278 OTF = 0x1
5057 05:56:47.471281 ===================================
5058 05:56:47.477757 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5059 05:56:47.482167 nWR fixed to 30
5060 05:56:47.485121 [ModeRegInit_LP4] CH0 RK0
5061 05:56:47.485205 [ModeRegInit_LP4] CH0 RK1
5062 05:56:47.488531 [ModeRegInit_LP4] CH1 RK0
5063 05:56:47.491783 [ModeRegInit_LP4] CH1 RK1
5064 05:56:47.491866 match AC timing 9
5065 05:56:47.498685 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5066 05:56:47.501720 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5067 05:56:47.505036 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5068 05:56:47.511590 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5069 05:56:47.515111 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5070 05:56:47.515196 ==
5071 05:56:47.518468 Dram Type= 6, Freq= 0, CH_0, rank 0
5072 05:56:47.521741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5073 05:56:47.521825 ==
5074 05:56:47.528173 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5075 05:56:47.535023 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5076 05:56:47.538309 [CA 0] Center 38 (8~69) winsize 62
5077 05:56:47.541784 [CA 1] Center 38 (8~69) winsize 62
5078 05:56:47.544744 [CA 2] Center 35 (5~65) winsize 61
5079 05:56:47.548248 [CA 3] Center 35 (5~65) winsize 61
5080 05:56:47.551166 [CA 4] Center 34 (4~64) winsize 61
5081 05:56:47.554597 [CA 5] Center 33 (3~64) winsize 62
5082 05:56:47.554681
5083 05:56:47.557921 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5084 05:56:47.558121
5085 05:56:47.561369 [CATrainingPosCal] consider 1 rank data
5086 05:56:47.564859 u2DelayCellTimex100 = 270/100 ps
5087 05:56:47.567798 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5088 05:56:47.571390 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5089 05:56:47.574820 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5090 05:56:47.577853 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5091 05:56:47.584441 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5092 05:56:47.587785 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5093 05:56:47.587869
5094 05:56:47.591301 CA PerBit enable=1, Macro0, CA PI delay=33
5095 05:56:47.591385
5096 05:56:47.594683 [CBTSetCACLKResult] CA Dly = 33
5097 05:56:47.594767 CS Dly: 7 (0~38)
5098 05:56:47.594834 ==
5099 05:56:47.598084 Dram Type= 6, Freq= 0, CH_0, rank 1
5100 05:56:47.601395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 05:56:47.604409 ==
5102 05:56:47.607833 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5103 05:56:47.614614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5104 05:56:47.617982 [CA 0] Center 38 (8~69) winsize 62
5105 05:56:47.621052 [CA 1] Center 38 (8~69) winsize 62
5106 05:56:47.624271 [CA 2] Center 36 (6~66) winsize 61
5107 05:56:47.627691 [CA 3] Center 35 (5~66) winsize 62
5108 05:56:47.630922 [CA 4] Center 34 (4~65) winsize 62
5109 05:56:47.634492 [CA 5] Center 34 (4~65) winsize 62
5110 05:56:47.634576
5111 05:56:47.638086 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5112 05:56:47.638168
5113 05:56:47.640925 [CATrainingPosCal] consider 2 rank data
5114 05:56:47.644727 u2DelayCellTimex100 = 270/100 ps
5115 05:56:47.647853 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5116 05:56:47.650777 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5117 05:56:47.654257 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5118 05:56:47.657736 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5119 05:56:47.664117 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5120 05:56:47.667509 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5121 05:56:47.667579
5122 05:56:47.670964 CA PerBit enable=1, Macro0, CA PI delay=34
5123 05:56:47.671035
5124 05:56:47.674354 [CBTSetCACLKResult] CA Dly = 34
5125 05:56:47.674420 CS Dly: 7 (0~39)
5126 05:56:47.674483
5127 05:56:47.677413 ----->DramcWriteLeveling(PI) begin...
5128 05:56:47.677481 ==
5129 05:56:47.681062 Dram Type= 6, Freq= 0, CH_0, rank 0
5130 05:56:47.687923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 05:56:47.688002 ==
5132 05:56:47.690840 Write leveling (Byte 0): 32 => 32
5133 05:56:47.694242 Write leveling (Byte 1): 32 => 32
5134 05:56:47.694316 DramcWriteLeveling(PI) end<-----
5135 05:56:47.694378
5136 05:56:47.697804 ==
5137 05:56:47.701059 Dram Type= 6, Freq= 0, CH_0, rank 0
5138 05:56:47.704450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5139 05:56:47.704533 ==
5140 05:56:47.707582 [Gating] SW mode calibration
5141 05:56:47.714050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5142 05:56:47.717777 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5143 05:56:47.724305 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
5144 05:56:47.727806 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 05:56:47.730949 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 05:56:47.737365 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 05:56:47.740638 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 05:56:47.744116 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 05:56:47.751051 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5150 05:56:47.754086 0 14 28 | B1->B0 | 3232 2323 | 1 0 | (1 0) (1 0)
5151 05:56:47.757552 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5152 05:56:47.764256 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 05:56:47.767161 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 05:56:47.770622 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 05:56:47.777603 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 05:56:47.780547 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 05:56:47.784058 0 15 24 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5158 05:56:47.790621 0 15 28 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
5159 05:56:47.794012 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 05:56:47.797533 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 05:56:47.803779 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 05:56:47.807004 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 05:56:47.810311 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 05:56:47.813921 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 05:56:47.820391 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5166 05:56:47.823673 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5167 05:56:47.827133 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5168 05:56:47.833892 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 05:56:47.836919 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 05:56:47.840425 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 05:56:47.847125 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 05:56:47.850548 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 05:56:47.853848 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 05:56:47.860463 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 05:56:47.863423 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 05:56:47.866852 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 05:56:47.873618 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 05:56:47.877099 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 05:56:47.880545 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 05:56:47.887017 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 05:56:47.890423 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5182 05:56:47.893396 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5183 05:56:47.900351 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5184 05:56:47.900435 Total UI for P1: 0, mck2ui 16
5185 05:56:47.906939 best dqsien dly found for B0: ( 1, 2, 26)
5186 05:56:47.910311 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 05:56:47.913655 Total UI for P1: 0, mck2ui 16
5188 05:56:47.916708 best dqsien dly found for B1: ( 1, 2, 30)
5189 05:56:47.920144 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5190 05:56:47.923708 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5191 05:56:47.923791
5192 05:56:47.926599 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5193 05:56:47.929875 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5194 05:56:47.933486 [Gating] SW calibration Done
5195 05:56:47.933568 ==
5196 05:56:47.936858 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 05:56:47.939979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 05:56:47.940062 ==
5199 05:56:47.943192 RX Vref Scan: 0
5200 05:56:47.943274
5201 05:56:47.946808 RX Vref 0 -> 0, step: 1
5202 05:56:47.946890
5203 05:56:47.946955 RX Delay -80 -> 252, step: 8
5204 05:56:47.953342 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5205 05:56:47.956673 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5206 05:56:47.959775 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5207 05:56:47.963272 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5208 05:56:47.966640 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5209 05:56:47.970071 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5210 05:56:47.976776 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5211 05:56:47.979747 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5212 05:56:47.983231 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5213 05:56:47.986637 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5214 05:56:47.989750 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5215 05:56:47.996686 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5216 05:56:47.999872 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5217 05:56:48.002902 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5218 05:56:48.006316 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5219 05:56:48.009694 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5220 05:56:48.009777 ==
5221 05:56:48.013293 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 05:56:48.019500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 05:56:48.019584 ==
5224 05:56:48.019649 DQS Delay:
5225 05:56:48.023006 DQS0 = 0, DQS1 = 0
5226 05:56:48.023088 DQM Delay:
5227 05:56:48.023153 DQM0 = 105, DQM1 = 90
5228 05:56:48.026332 DQ Delay:
5229 05:56:48.029789 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5230 05:56:48.033371 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5231 05:56:48.036311 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5232 05:56:48.039632 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =99
5233 05:56:48.039714
5234 05:56:48.039779
5235 05:56:48.039837 ==
5236 05:56:48.043198 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 05:56:48.046421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 05:56:48.046505 ==
5239 05:56:48.046570
5240 05:56:48.046630
5241 05:56:48.049608 TX Vref Scan disable
5242 05:56:48.053275 == TX Byte 0 ==
5243 05:56:48.056270 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5244 05:56:48.059913 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5245 05:56:48.059995 == TX Byte 1 ==
5246 05:56:48.066603 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5247 05:56:48.070108 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5248 05:56:48.070191 ==
5249 05:56:48.073081 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 05:56:48.076291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 05:56:48.076373 ==
5252 05:56:48.079426
5253 05:56:48.079508
5254 05:56:48.079573 TX Vref Scan disable
5255 05:56:48.082881 == TX Byte 0 ==
5256 05:56:48.086299 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5257 05:56:48.089762 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5258 05:56:48.092794 == TX Byte 1 ==
5259 05:56:48.096240 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5260 05:56:48.103107 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5261 05:56:48.103190
5262 05:56:48.103255 [DATLAT]
5263 05:56:48.103314 Freq=933, CH0 RK0
5264 05:56:48.103373
5265 05:56:48.106086 DATLAT Default: 0xd
5266 05:56:48.106168 0, 0xFFFF, sum = 0
5267 05:56:48.109548 1, 0xFFFF, sum = 0
5268 05:56:48.109632 2, 0xFFFF, sum = 0
5269 05:56:48.113044 3, 0xFFFF, sum = 0
5270 05:56:48.113129 4, 0xFFFF, sum = 0
5271 05:56:48.116053 5, 0xFFFF, sum = 0
5272 05:56:48.119378 6, 0xFFFF, sum = 0
5273 05:56:48.119462 7, 0xFFFF, sum = 0
5274 05:56:48.122818 8, 0xFFFF, sum = 0
5275 05:56:48.122902 9, 0xFFFF, sum = 0
5276 05:56:48.126417 10, 0x0, sum = 1
5277 05:56:48.126501 11, 0x0, sum = 2
5278 05:56:48.126568 12, 0x0, sum = 3
5279 05:56:48.129438 13, 0x0, sum = 4
5280 05:56:48.129522 best_step = 11
5281 05:56:48.129587
5282 05:56:48.133090 ==
5283 05:56:48.133173 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 05:56:48.139326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 05:56:48.139409 ==
5286 05:56:48.139475 RX Vref Scan: 1
5287 05:56:48.139535
5288 05:56:48.142912 RX Vref 0 -> 0, step: 1
5289 05:56:48.142995
5290 05:56:48.146397 RX Delay -53 -> 252, step: 4
5291 05:56:48.146479
5292 05:56:48.149299 Set Vref, RX VrefLevel [Byte0]: 57
5293 05:56:48.152881 [Byte1]: 49
5294 05:56:48.152964
5295 05:56:48.156137 Final RX Vref Byte 0 = 57 to rank0
5296 05:56:48.159712 Final RX Vref Byte 1 = 49 to rank0
5297 05:56:48.162763 Final RX Vref Byte 0 = 57 to rank1
5298 05:56:48.166364 Final RX Vref Byte 1 = 49 to rank1==
5299 05:56:48.169406 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 05:56:48.172721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 05:56:48.172804 ==
5302 05:56:48.176196 DQS Delay:
5303 05:56:48.176278 DQS0 = 0, DQS1 = 0
5304 05:56:48.179689 DQM Delay:
5305 05:56:48.179771 DQM0 = 107, DQM1 = 91
5306 05:56:48.179836 DQ Delay:
5307 05:56:48.182866 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5308 05:56:48.185918 DQ4 =108, DQ5 =98, DQ6 =118, DQ7 =114
5309 05:56:48.189346 DQ8 =86, DQ9 =78, DQ10 =90, DQ11 =90
5310 05:56:48.196345 DQ12 =94, DQ13 =94, DQ14 =102, DQ15 =98
5311 05:56:48.196428
5312 05:56:48.196494
5313 05:56:48.202734 [DQSOSCAuto] RK0, (LSB)MR18= 0x231f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
5314 05:56:48.206177 CH0 RK0: MR19=505, MR18=231F
5315 05:56:48.212579 CH0_RK0: MR19=0x505, MR18=0x231F, DQSOSC=410, MR23=63, INC=64, DEC=42
5316 05:56:48.212663
5317 05:56:48.216076 ----->DramcWriteLeveling(PI) begin...
5318 05:56:48.216162 ==
5319 05:56:48.219608 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 05:56:48.222462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 05:56:48.222545 ==
5322 05:56:48.225869 Write leveling (Byte 0): 35 => 35
5323 05:56:48.229405 Write leveling (Byte 1): 30 => 30
5324 05:56:48.232348 DramcWriteLeveling(PI) end<-----
5325 05:56:48.232431
5326 05:56:48.232497 ==
5327 05:56:48.235705 Dram Type= 6, Freq= 0, CH_0, rank 1
5328 05:56:48.239255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 05:56:48.239341 ==
5330 05:56:48.242280 [Gating] SW mode calibration
5331 05:56:48.249240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5332 05:56:48.255597 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5333 05:56:48.258919 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 05:56:48.262462 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 05:56:48.269075 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 05:56:48.272527 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 05:56:48.275523 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 05:56:48.282438 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 05:56:48.285765 0 14 24 | B1->B0 | 3333 3030 | 0 1 | (0 0) (1 1)
5340 05:56:48.289154 0 14 28 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (1 0)
5341 05:56:48.295560 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 05:56:48.298800 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 05:56:48.302325 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 05:56:48.308777 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 05:56:48.312219 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 05:56:48.315235 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 05:56:48.322394 0 15 24 | B1->B0 | 2929 2f2f | 0 0 | (0 0) (0 0)
5348 05:56:48.325373 0 15 28 | B1->B0 | 3939 4343 | 1 0 | (0 0) (0 0)
5349 05:56:48.328792 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 05:56:48.335173 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 05:56:48.338485 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 05:56:48.341817 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 05:56:48.348522 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 05:56:48.351956 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 05:56:48.355285 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5356 05:56:48.361760 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5357 05:56:48.365107 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 05:56:48.369137 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 05:56:48.375163 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 05:56:48.378658 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 05:56:48.381830 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 05:56:48.388554 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 05:56:48.391833 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 05:56:48.395225 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 05:56:48.401681 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 05:56:48.404980 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 05:56:48.408418 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 05:56:48.411934 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 05:56:48.418368 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 05:56:48.421866 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 05:56:48.424820 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5372 05:56:48.431767 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5373 05:56:48.434963 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 05:56:48.438376 Total UI for P1: 0, mck2ui 16
5375 05:56:48.441812 best dqsien dly found for B0: ( 1, 2, 26)
5376 05:56:48.444752 Total UI for P1: 0, mck2ui 16
5377 05:56:48.448362 best dqsien dly found for B1: ( 1, 2, 26)
5378 05:56:48.451785 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5379 05:56:48.454827 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5380 05:56:48.454909
5381 05:56:48.458212 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5382 05:56:48.461259 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5383 05:56:48.464739 [Gating] SW calibration Done
5384 05:56:48.464819 ==
5385 05:56:48.468052 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 05:56:48.475078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 05:56:48.475158 ==
5388 05:56:48.475221 RX Vref Scan: 0
5389 05:56:48.475280
5390 05:56:48.478082 RX Vref 0 -> 0, step: 1
5391 05:56:48.478162
5392 05:56:48.481764 RX Delay -80 -> 252, step: 8
5393 05:56:48.484894 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5394 05:56:48.488245 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5395 05:56:48.491441 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5396 05:56:48.495088 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5397 05:56:48.501426 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5398 05:56:48.504848 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5399 05:56:48.508146 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5400 05:56:48.511255 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5401 05:56:48.514761 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5402 05:56:48.517809 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5403 05:56:48.524795 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5404 05:56:48.527797 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5405 05:56:48.531329 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5406 05:56:48.534692 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5407 05:56:48.537878 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5408 05:56:48.541230 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5409 05:56:48.544772 ==
5410 05:56:48.544883 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 05:56:48.551119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 05:56:48.551217 ==
5413 05:56:48.551312 DQS Delay:
5414 05:56:48.554577 DQS0 = 0, DQS1 = 0
5415 05:56:48.554674 DQM Delay:
5416 05:56:48.557578 DQM0 = 104, DQM1 = 90
5417 05:56:48.557674 DQ Delay:
5418 05:56:48.561109 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5419 05:56:48.564598 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5420 05:56:48.568060 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5421 05:56:48.570950 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5422 05:56:48.571033
5423 05:56:48.571097
5424 05:56:48.571158 ==
5425 05:56:48.574288 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 05:56:48.577769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 05:56:48.577853 ==
5428 05:56:48.577919
5429 05:56:48.578019
5430 05:56:48.580889 TX Vref Scan disable
5431 05:56:48.584293 == TX Byte 0 ==
5432 05:56:48.587636 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5433 05:56:48.590820 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5434 05:56:48.594395 == TX Byte 1 ==
5435 05:56:48.597585 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5436 05:56:48.600778 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5437 05:56:48.600862 ==
5438 05:56:48.604373 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 05:56:48.610896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 05:56:48.610983 ==
5441 05:56:48.611075
5442 05:56:48.611175
5443 05:56:48.611262 TX Vref Scan disable
5444 05:56:48.615031 == TX Byte 0 ==
5445 05:56:48.618542 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5446 05:56:48.624866 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5447 05:56:48.624951 == TX Byte 1 ==
5448 05:56:48.628285 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5449 05:56:48.634786 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5450 05:56:48.634871
5451 05:56:48.634955 [DATLAT]
5452 05:56:48.635034 Freq=933, CH0 RK1
5453 05:56:48.635112
5454 05:56:48.638255 DATLAT Default: 0xb
5455 05:56:48.638340 0, 0xFFFF, sum = 0
5456 05:56:48.641468 1, 0xFFFF, sum = 0
5457 05:56:48.644892 2, 0xFFFF, sum = 0
5458 05:56:48.644978 3, 0xFFFF, sum = 0
5459 05:56:48.648267 4, 0xFFFF, sum = 0
5460 05:56:48.648354 5, 0xFFFF, sum = 0
5461 05:56:48.651361 6, 0xFFFF, sum = 0
5462 05:56:48.651447 7, 0xFFFF, sum = 0
5463 05:56:48.654699 8, 0xFFFF, sum = 0
5464 05:56:48.654785 9, 0xFFFF, sum = 0
5465 05:56:48.658172 10, 0x0, sum = 1
5466 05:56:48.658257 11, 0x0, sum = 2
5467 05:56:48.661634 12, 0x0, sum = 3
5468 05:56:48.661720 13, 0x0, sum = 4
5469 05:56:48.661824 best_step = 11
5470 05:56:48.661924
5471 05:56:48.664547 ==
5472 05:56:48.668166 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 05:56:48.671161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 05:56:48.671246 ==
5475 05:56:48.671331 RX Vref Scan: 0
5476 05:56:48.671411
5477 05:56:48.674720 RX Vref 0 -> 0, step: 1
5478 05:56:48.674805
5479 05:56:48.678141 RX Delay -53 -> 252, step: 4
5480 05:56:48.684672 iDelay=203, Bit 0, Center 102 (15 ~ 190) 176
5481 05:56:48.687713 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5482 05:56:48.691600 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5483 05:56:48.694857 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5484 05:56:48.697971 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5485 05:56:48.701103 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5486 05:56:48.707883 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5487 05:56:48.711241 iDelay=203, Bit 7, Center 110 (23 ~ 198) 176
5488 05:56:48.714448 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5489 05:56:48.718207 iDelay=203, Bit 9, Center 78 (-5 ~ 162) 168
5490 05:56:48.721475 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5491 05:56:48.724454 iDelay=203, Bit 11, Center 90 (7 ~ 174) 168
5492 05:56:48.731506 iDelay=203, Bit 12, Center 96 (11 ~ 182) 172
5493 05:56:48.734486 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5494 05:56:48.738003 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5495 05:56:48.741060 iDelay=203, Bit 15, Center 96 (11 ~ 182) 172
5496 05:56:48.741146 ==
5497 05:56:48.744442 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 05:56:48.750957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 05:56:48.751067 ==
5500 05:56:48.751169 DQS Delay:
5501 05:56:48.754622 DQS0 = 0, DQS1 = 0
5502 05:56:48.754706 DQM Delay:
5503 05:56:48.754810 DQM0 = 104, DQM1 = 91
5504 05:56:48.757704 DQ Delay:
5505 05:56:48.761301 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =98
5506 05:56:48.764231 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =110
5507 05:56:48.767830 DQ8 =84, DQ9 =78, DQ10 =94, DQ11 =90
5508 05:56:48.770986 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =96
5509 05:56:48.771072
5510 05:56:48.771159
5511 05:56:48.777494 [DQSOSCAuto] RK1, (LSB)MR18= 0x2406, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 410 ps
5512 05:56:48.780852 CH0 RK1: MR19=505, MR18=2406
5513 05:56:48.787365 CH0_RK1: MR19=0x505, MR18=0x2406, DQSOSC=410, MR23=63, INC=64, DEC=42
5514 05:56:48.790953 [RxdqsGatingPostProcess] freq 933
5515 05:56:48.797652 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5516 05:56:48.797757 best DQS0 dly(2T, 0.5T) = (0, 10)
5517 05:56:48.801352 best DQS1 dly(2T, 0.5T) = (0, 10)
5518 05:56:48.804068 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5519 05:56:48.807349 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5520 05:56:48.810830 best DQS0 dly(2T, 0.5T) = (0, 10)
5521 05:56:48.814200 best DQS1 dly(2T, 0.5T) = (0, 10)
5522 05:56:48.817373 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5523 05:56:48.820819 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5524 05:56:48.823848 Pre-setting of DQS Precalculation
5525 05:56:48.830826 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5526 05:56:48.830954 ==
5527 05:56:48.833834 Dram Type= 6, Freq= 0, CH_1, rank 0
5528 05:56:48.837136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 05:56:48.837220 ==
5530 05:56:48.843996 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5531 05:56:48.846876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5532 05:56:48.851091 [CA 0] Center 38 (8~68) winsize 61
5533 05:56:48.854840 [CA 1] Center 37 (7~68) winsize 62
5534 05:56:48.857903 [CA 2] Center 35 (6~65) winsize 60
5535 05:56:48.860982 [CA 3] Center 34 (4~65) winsize 62
5536 05:56:48.864412 [CA 4] Center 35 (5~65) winsize 61
5537 05:56:48.867907 [CA 5] Center 34 (4~64) winsize 61
5538 05:56:48.867992
5539 05:56:48.870878 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5540 05:56:48.870963
5541 05:56:48.874343 [CATrainingPosCal] consider 1 rank data
5542 05:56:48.877877 u2DelayCellTimex100 = 270/100 ps
5543 05:56:48.881132 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5544 05:56:48.884451 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5545 05:56:48.890781 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5546 05:56:48.894338 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5547 05:56:48.897866 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5548 05:56:48.901173 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5549 05:56:48.901257
5550 05:56:48.904754 CA PerBit enable=1, Macro0, CA PI delay=34
5551 05:56:48.904839
5552 05:56:48.907829 [CBTSetCACLKResult] CA Dly = 34
5553 05:56:48.907914 CS Dly: 6 (0~37)
5554 05:56:48.907980 ==
5555 05:56:48.911074 Dram Type= 6, Freq= 0, CH_1, rank 1
5556 05:56:48.917766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 05:56:48.917852 ==
5558 05:56:48.920994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5559 05:56:48.927862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5560 05:56:48.931031 [CA 0] Center 38 (8~69) winsize 62
5561 05:56:48.934233 [CA 1] Center 38 (8~69) winsize 62
5562 05:56:48.937836 [CA 2] Center 36 (6~66) winsize 61
5563 05:56:48.940951 [CA 3] Center 35 (5~65) winsize 61
5564 05:56:48.944413 [CA 4] Center 35 (6~65) winsize 60
5565 05:56:48.947871 [CA 5] Center 34 (5~64) winsize 60
5566 05:56:48.947955
5567 05:56:48.951189 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5568 05:56:48.951274
5569 05:56:48.954488 [CATrainingPosCal] consider 2 rank data
5570 05:56:48.957672 u2DelayCellTimex100 = 270/100 ps
5571 05:56:48.961208 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5572 05:56:48.964175 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5573 05:56:48.971187 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5574 05:56:48.974201 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5575 05:56:48.977682 CA4 delay=35 (6~65),Diff = 1 PI (6 cell)
5576 05:56:48.981175 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5577 05:56:48.981258
5578 05:56:48.984330 CA PerBit enable=1, Macro0, CA PI delay=34
5579 05:56:48.984413
5580 05:56:48.987535 [CBTSetCACLKResult] CA Dly = 34
5581 05:56:48.987618 CS Dly: 7 (0~39)
5582 05:56:48.987684
5583 05:56:48.990921 ----->DramcWriteLeveling(PI) begin...
5584 05:56:48.994431 ==
5585 05:56:48.997461 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 05:56:49.000945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 05:56:49.001028 ==
5588 05:56:49.003834 Write leveling (Byte 0): 28 => 28
5589 05:56:49.007331 Write leveling (Byte 1): 29 => 29
5590 05:56:49.010919 DramcWriteLeveling(PI) end<-----
5591 05:56:49.011001
5592 05:56:49.011067 ==
5593 05:56:49.013853 Dram Type= 6, Freq= 0, CH_1, rank 0
5594 05:56:49.017046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 05:56:49.017131 ==
5596 05:56:49.020516 [Gating] SW mode calibration
5597 05:56:49.027258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5598 05:56:49.033754 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5599 05:56:49.037353 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 05:56:49.040539 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 05:56:49.047494 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 05:56:49.050493 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 05:56:49.053899 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 05:56:49.060768 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 05:56:49.064082 0 14 24 | B1->B0 | 3333 3131 | 1 0 | (1 0) (0 1)
5606 05:56:49.067039 0 14 28 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
5607 05:56:49.070543 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 05:56:49.077240 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 05:56:49.080290 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 05:56:49.083795 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 05:56:49.090785 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 05:56:49.093655 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 05:56:49.097196 0 15 24 | B1->B0 | 2828 2e2e | 0 0 | (0 0) (0 0)
5614 05:56:49.104191 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5615 05:56:49.107047 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 05:56:49.110472 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 05:56:49.117246 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 05:56:49.120376 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 05:56:49.123560 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 05:56:49.130620 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 05:56:49.133820 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5622 05:56:49.137172 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 05:56:49.143842 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 05:56:49.147020 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 05:56:49.150569 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 05:56:49.156909 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 05:56:49.160220 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 05:56:49.163758 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 05:56:49.170481 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 05:56:49.173513 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 05:56:49.177291 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 05:56:49.183929 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 05:56:49.186877 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 05:56:49.190425 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 05:56:49.193548 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 05:56:49.200334 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5637 05:56:49.203829 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5638 05:56:49.206815 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5639 05:56:49.213350 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 05:56:49.216903 Total UI for P1: 0, mck2ui 16
5641 05:56:49.219912 best dqsien dly found for B0: ( 1, 2, 24)
5642 05:56:49.223446 Total UI for P1: 0, mck2ui 16
5643 05:56:49.226838 best dqsien dly found for B1: ( 1, 2, 28)
5644 05:56:49.230072 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5645 05:56:49.233343 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5646 05:56:49.233426
5647 05:56:49.236851 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5648 05:56:49.240221 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5649 05:56:49.243369 [Gating] SW calibration Done
5650 05:56:49.243441 ==
5651 05:56:49.246550 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 05:56:49.250150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 05:56:49.250223 ==
5654 05:56:49.253347 RX Vref Scan: 0
5655 05:56:49.253417
5656 05:56:49.253478 RX Vref 0 -> 0, step: 1
5657 05:56:49.256724
5658 05:56:49.256792 RX Delay -80 -> 252, step: 8
5659 05:56:49.263190 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5660 05:56:49.266580 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5661 05:56:49.269796 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5662 05:56:49.273079 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5663 05:56:49.276590 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5664 05:56:49.280038 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5665 05:56:49.286588 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5666 05:56:49.289527 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5667 05:56:49.292995 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5668 05:56:49.296420 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5669 05:56:49.299711 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5670 05:56:49.303119 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5671 05:56:49.309594 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5672 05:56:49.313104 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5673 05:56:49.316225 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5674 05:56:49.319596 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5675 05:56:49.319671 ==
5676 05:56:49.323225 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 05:56:49.326335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 05:56:49.329732 ==
5679 05:56:49.329799 DQS Delay:
5680 05:56:49.329863 DQS0 = 0, DQS1 = 0
5681 05:56:49.332945 DQM Delay:
5682 05:56:49.333010 DQM0 = 101, DQM1 = 95
5683 05:56:49.336258 DQ Delay:
5684 05:56:49.339366 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5685 05:56:49.339443 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5686 05:56:49.342986 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5687 05:56:49.349342 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5688 05:56:49.349431
5689 05:56:49.349501
5690 05:56:49.349589 ==
5691 05:56:49.352918 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 05:56:49.356098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 05:56:49.356169 ==
5694 05:56:49.356234
5695 05:56:49.356291
5696 05:56:49.359665 TX Vref Scan disable
5697 05:56:49.359733 == TX Byte 0 ==
5698 05:56:49.366470 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5699 05:56:49.369521 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5700 05:56:49.369619 == TX Byte 1 ==
5701 05:56:49.376134 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5702 05:56:49.379827 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5703 05:56:49.379924 ==
5704 05:56:49.382780 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 05:56:49.386245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 05:56:49.386314 ==
5707 05:56:49.386375
5708 05:56:49.386431
5709 05:56:49.389712 TX Vref Scan disable
5710 05:56:49.392783 == TX Byte 0 ==
5711 05:56:49.396200 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5712 05:56:49.399210 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5713 05:56:49.402586 == TX Byte 1 ==
5714 05:56:49.406010 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5715 05:56:49.409423 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5716 05:56:49.409494
5717 05:56:49.412849 [DATLAT]
5718 05:56:49.412928 Freq=933, CH1 RK0
5719 05:56:49.412996
5720 05:56:49.415791 DATLAT Default: 0xd
5721 05:56:49.415871 0, 0xFFFF, sum = 0
5722 05:56:49.419358 1, 0xFFFF, sum = 0
5723 05:56:49.419434 2, 0xFFFF, sum = 0
5724 05:56:49.422432 3, 0xFFFF, sum = 0
5725 05:56:49.422506 4, 0xFFFF, sum = 0
5726 05:56:49.425838 5, 0xFFFF, sum = 0
5727 05:56:49.425934 6, 0xFFFF, sum = 0
5728 05:56:49.429095 7, 0xFFFF, sum = 0
5729 05:56:49.432521 8, 0xFFFF, sum = 0
5730 05:56:49.432594 9, 0xFFFF, sum = 0
5731 05:56:49.435530 10, 0x0, sum = 1
5732 05:56:49.435598 11, 0x0, sum = 2
5733 05:56:49.435658 12, 0x0, sum = 3
5734 05:56:49.439168 13, 0x0, sum = 4
5735 05:56:49.439244 best_step = 11
5736 05:56:49.439304
5737 05:56:49.439361 ==
5738 05:56:49.442482 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 05:56:49.449017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 05:56:49.449122 ==
5741 05:56:49.449214 RX Vref Scan: 1
5742 05:56:49.449301
5743 05:56:49.452516 RX Vref 0 -> 0, step: 1
5744 05:56:49.452591
5745 05:56:49.455562 RX Delay -53 -> 252, step: 4
5746 05:56:49.455640
5747 05:56:49.459023 Set Vref, RX VrefLevel [Byte0]: 52
5748 05:56:49.462145 [Byte1]: 52
5749 05:56:49.462219
5750 05:56:49.465725 Final RX Vref Byte 0 = 52 to rank0
5751 05:56:49.469129 Final RX Vref Byte 1 = 52 to rank0
5752 05:56:49.472319 Final RX Vref Byte 0 = 52 to rank1
5753 05:56:49.475836 Final RX Vref Byte 1 = 52 to rank1==
5754 05:56:49.478984 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 05:56:49.482339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 05:56:49.482411 ==
5757 05:56:49.485876 DQS Delay:
5758 05:56:49.485970 DQS0 = 0, DQS1 = 0
5759 05:56:49.488774 DQM Delay:
5760 05:56:49.488844 DQM0 = 104, DQM1 = 98
5761 05:56:49.488903 DQ Delay:
5762 05:56:49.492311 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5763 05:56:49.495838 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5764 05:56:49.498855 DQ8 =88, DQ9 =88, DQ10 =102, DQ11 =94
5765 05:56:49.505339 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =102
5766 05:56:49.505417
5767 05:56:49.505481
5768 05:56:49.512079 [DQSOSCAuto] RK0, (LSB)MR18= 0x152d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 415 ps
5769 05:56:49.515551 CH1 RK0: MR19=505, MR18=152D
5770 05:56:49.522025 CH1_RK0: MR19=0x505, MR18=0x152D, DQSOSC=407, MR23=63, INC=65, DEC=43
5771 05:56:49.522107
5772 05:56:49.525338 ----->DramcWriteLeveling(PI) begin...
5773 05:56:49.525408 ==
5774 05:56:49.528993 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 05:56:49.532437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 05:56:49.532505 ==
5777 05:56:49.535507 Write leveling (Byte 0): 30 => 30
5778 05:56:49.539033 Write leveling (Byte 1): 31 => 31
5779 05:56:49.541944 DramcWriteLeveling(PI) end<-----
5780 05:56:49.542013
5781 05:56:49.542076 ==
5782 05:56:49.545592 Dram Type= 6, Freq= 0, CH_1, rank 1
5783 05:56:49.548881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 05:56:49.548950 ==
5785 05:56:49.552277 [Gating] SW mode calibration
5786 05:56:49.558843 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5787 05:56:49.565449 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5788 05:56:49.568533 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5789 05:56:49.575171 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 05:56:49.578645 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 05:56:49.581968 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 05:56:49.588615 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 05:56:49.592012 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 05:56:49.595023 0 14 24 | B1->B0 | 3131 3333 | 0 1 | (0 1) (1 1)
5795 05:56:49.601879 0 14 28 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
5796 05:56:49.604843 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5797 05:56:49.608461 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 05:56:49.611684 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 05:56:49.618528 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 05:56:49.621579 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 05:56:49.624936 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 05:56:49.631874 0 15 24 | B1->B0 | 2828 2323 | 1 0 | (0 0) (0 0)
5803 05:56:49.634821 0 15 28 | B1->B0 | 4343 3a3a | 0 0 | (0 0) (0 0)
5804 05:56:49.638344 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 05:56:49.644605 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 05:56:49.647945 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 05:56:49.651450 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 05:56:49.657877 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 05:56:49.661386 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 05:56:49.664621 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5811 05:56:49.671365 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5812 05:56:49.674461 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 05:56:49.677910 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 05:56:49.684457 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 05:56:49.688150 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 05:56:49.691106 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 05:56:49.697883 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 05:56:49.701061 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 05:56:49.704554 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 05:56:49.711159 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 05:56:49.714571 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 05:56:49.717612 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 05:56:49.724449 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 05:56:49.727840 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 05:56:49.730882 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 05:56:49.737708 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5827 05:56:49.740823 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5828 05:56:49.744237 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 05:56:49.747316 Total UI for P1: 0, mck2ui 16
5830 05:56:49.750831 best dqsien dly found for B0: ( 1, 2, 26)
5831 05:56:49.754384 Total UI for P1: 0, mck2ui 16
5832 05:56:49.757442 best dqsien dly found for B1: ( 1, 2, 26)
5833 05:56:49.760802 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5834 05:56:49.764257 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5835 05:56:49.764339
5836 05:56:49.767864 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5837 05:56:49.774371 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5838 05:56:49.774454 [Gating] SW calibration Done
5839 05:56:49.774520 ==
5840 05:56:49.777446 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 05:56:49.784005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 05:56:49.784089 ==
5843 05:56:49.784154 RX Vref Scan: 0
5844 05:56:49.784215
5845 05:56:49.787325 RX Vref 0 -> 0, step: 1
5846 05:56:49.787407
5847 05:56:49.790471 RX Delay -80 -> 252, step: 8
5848 05:56:49.793969 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5849 05:56:49.797222 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5850 05:56:49.800844 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5851 05:56:49.807118 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5852 05:56:49.810654 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5853 05:56:49.814158 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5854 05:56:49.817216 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5855 05:56:49.820601 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5856 05:56:49.823968 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5857 05:56:49.830314 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5858 05:56:49.833891 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5859 05:56:49.837347 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5860 05:56:49.840388 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5861 05:56:49.843898 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5862 05:56:49.846961 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5863 05:56:49.853963 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5864 05:56:49.854059 ==
5865 05:56:49.856947 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 05:56:49.860365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 05:56:49.860448 ==
5868 05:56:49.860519 DQS Delay:
5869 05:56:49.863398 DQS0 = 0, DQS1 = 0
5870 05:56:49.863481 DQM Delay:
5871 05:56:49.866917 DQM0 = 101, DQM1 = 96
5872 05:56:49.867000 DQ Delay:
5873 05:56:49.870517 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5874 05:56:49.873409 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =99
5875 05:56:49.876712 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5876 05:56:49.880164 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5877 05:56:49.880247
5878 05:56:49.880312
5879 05:56:49.880372 ==
5880 05:56:49.883666 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 05:56:49.890299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 05:56:49.890384 ==
5883 05:56:49.890450
5884 05:56:49.890512
5885 05:56:49.890571 TX Vref Scan disable
5886 05:56:49.893834 == TX Byte 0 ==
5887 05:56:49.897092 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5888 05:56:49.903793 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5889 05:56:49.903877 == TX Byte 1 ==
5890 05:56:49.906807 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5891 05:56:49.913835 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5892 05:56:49.913918 ==
5893 05:56:49.916899 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 05:56:49.920412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 05:56:49.920497 ==
5896 05:56:49.920563
5897 05:56:49.920624
5898 05:56:49.923799 TX Vref Scan disable
5899 05:56:49.923882 == TX Byte 0 ==
5900 05:56:49.930378 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5901 05:56:49.933824 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5902 05:56:49.933907 == TX Byte 1 ==
5903 05:56:49.940296 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5904 05:56:49.943382 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5905 05:56:49.943466
5906 05:56:49.943531 [DATLAT]
5907 05:56:49.946857 Freq=933, CH1 RK1
5908 05:56:49.946940
5909 05:56:49.947006 DATLAT Default: 0xb
5910 05:56:49.949884 0, 0xFFFF, sum = 0
5911 05:56:49.949992 1, 0xFFFF, sum = 0
5912 05:56:49.953478 2, 0xFFFF, sum = 0
5913 05:56:49.953569 3, 0xFFFF, sum = 0
5914 05:56:49.956587 4, 0xFFFF, sum = 0
5915 05:56:49.960137 5, 0xFFFF, sum = 0
5916 05:56:49.960227 6, 0xFFFF, sum = 0
5917 05:56:49.963348 7, 0xFFFF, sum = 0
5918 05:56:49.963432 8, 0xFFFF, sum = 0
5919 05:56:49.966802 9, 0xFFFF, sum = 0
5920 05:56:49.966887 10, 0x0, sum = 1
5921 05:56:49.969916 11, 0x0, sum = 2
5922 05:56:49.970037 12, 0x0, sum = 3
5923 05:56:49.970105 13, 0x0, sum = 4
5924 05:56:49.973319 best_step = 11
5925 05:56:49.973402
5926 05:56:49.973468 ==
5927 05:56:49.976753 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 05:56:49.980219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 05:56:49.980304 ==
5930 05:56:49.983418 RX Vref Scan: 0
5931 05:56:49.983530
5932 05:56:49.986649 RX Vref 0 -> 0, step: 1
5933 05:56:49.986733
5934 05:56:49.986799 RX Delay -53 -> 252, step: 4
5935 05:56:49.994117 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5936 05:56:49.997549 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5937 05:56:50.000645 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5938 05:56:50.004093 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5939 05:56:50.007219 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5940 05:56:50.014124 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5941 05:56:50.017408 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5942 05:56:50.020864 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5943 05:56:50.023936 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5944 05:56:50.027300 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5945 05:56:50.033814 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5946 05:56:50.037316 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5947 05:56:50.040873 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5948 05:56:50.043963 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5949 05:56:50.047316 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5950 05:56:50.053678 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5951 05:56:50.053762 ==
5952 05:56:50.057150 Dram Type= 6, Freq= 0, CH_1, rank 1
5953 05:56:50.060543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5954 05:56:50.060626 ==
5955 05:56:50.060692 DQS Delay:
5956 05:56:50.063583 DQS0 = 0, DQS1 = 0
5957 05:56:50.063656 DQM Delay:
5958 05:56:50.067006 DQM0 = 105, DQM1 = 97
5959 05:56:50.067076 DQ Delay:
5960 05:56:50.070552 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =102
5961 05:56:50.073508 DQ4 =106, DQ5 =116, DQ6 =112, DQ7 =102
5962 05:56:50.076947 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
5963 05:56:50.080390 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
5964 05:56:50.080484
5965 05:56:50.080574
5966 05:56:50.090197 [DQSOSCAuto] RK1, (LSB)MR18= 0x21fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5967 05:56:50.090304 CH1 RK1: MR19=504, MR18=21FD
5968 05:56:50.097041 CH1_RK1: MR19=0x504, MR18=0x21FD, DQSOSC=411, MR23=63, INC=64, DEC=42
5969 05:56:50.100570 [RxdqsGatingPostProcess] freq 933
5970 05:56:50.107140 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5971 05:56:50.110102 best DQS0 dly(2T, 0.5T) = (0, 10)
5972 05:56:50.113586 best DQS1 dly(2T, 0.5T) = (0, 10)
5973 05:56:50.116817 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5974 05:56:50.120063 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5975 05:56:50.123772 best DQS0 dly(2T, 0.5T) = (0, 10)
5976 05:56:50.126711 best DQS1 dly(2T, 0.5T) = (0, 10)
5977 05:56:50.130210 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5978 05:56:50.133209 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5979 05:56:50.133312 Pre-setting of DQS Precalculation
5980 05:56:50.139911 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5981 05:56:50.146757 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5982 05:56:50.153720 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5983 05:56:50.153820
5984 05:56:50.153911
5985 05:56:50.156711 [Calibration Summary] 1866 Mbps
5986 05:56:50.160302 CH 0, Rank 0
5987 05:56:50.160372 SW Impedance : PASS
5988 05:56:50.163330 DUTY Scan : NO K
5989 05:56:50.166719 ZQ Calibration : PASS
5990 05:56:50.166813 Jitter Meter : NO K
5991 05:56:50.170018 CBT Training : PASS
5992 05:56:50.170087 Write leveling : PASS
5993 05:56:50.173423 RX DQS gating : PASS
5994 05:56:50.176534 RX DQ/DQS(RDDQC) : PASS
5995 05:56:50.176628 TX DQ/DQS : PASS
5996 05:56:50.179976 RX DATLAT : PASS
5997 05:56:50.183559 RX DQ/DQS(Engine): PASS
5998 05:56:50.183637 TX OE : NO K
5999 05:56:50.186476 All Pass.
6000 05:56:50.186571
6001 05:56:50.186658 CH 0, Rank 1
6002 05:56:50.189862 SW Impedance : PASS
6003 05:56:50.189977 DUTY Scan : NO K
6004 05:56:50.193119 ZQ Calibration : PASS
6005 05:56:50.196378 Jitter Meter : NO K
6006 05:56:50.196478 CBT Training : PASS
6007 05:56:50.199826 Write leveling : PASS
6008 05:56:50.203180 RX DQS gating : PASS
6009 05:56:50.203276 RX DQ/DQS(RDDQC) : PASS
6010 05:56:50.206375 TX DQ/DQS : PASS
6011 05:56:50.209861 RX DATLAT : PASS
6012 05:56:50.209996 RX DQ/DQS(Engine): PASS
6013 05:56:50.212965 TX OE : NO K
6014 05:56:50.213063 All Pass.
6015 05:56:50.213127
6016 05:56:50.216438 CH 1, Rank 0
6017 05:56:50.216534 SW Impedance : PASS
6018 05:56:50.219612 DUTY Scan : NO K
6019 05:56:50.223180 ZQ Calibration : PASS
6020 05:56:50.223254 Jitter Meter : NO K
6021 05:56:50.226356 CBT Training : PASS
6022 05:56:50.226452 Write leveling : PASS
6023 05:56:50.229656 RX DQS gating : PASS
6024 05:56:50.233029 RX DQ/DQS(RDDQC) : PASS
6025 05:56:50.233133 TX DQ/DQS : PASS
6026 05:56:50.236509 RX DATLAT : PASS
6027 05:56:50.239783 RX DQ/DQS(Engine): PASS
6028 05:56:50.239864 TX OE : NO K
6029 05:56:50.242756 All Pass.
6030 05:56:50.242832
6031 05:56:50.242895 CH 1, Rank 1
6032 05:56:50.246149 SW Impedance : PASS
6033 05:56:50.246219 DUTY Scan : NO K
6034 05:56:50.249776 ZQ Calibration : PASS
6035 05:56:50.253149 Jitter Meter : NO K
6036 05:56:50.253216 CBT Training : PASS
6037 05:56:50.256425 Write leveling : PASS
6038 05:56:50.259369 RX DQS gating : PASS
6039 05:56:50.259440 RX DQ/DQS(RDDQC) : PASS
6040 05:56:50.262840 TX DQ/DQS : PASS
6041 05:56:50.266347 RX DATLAT : PASS
6042 05:56:50.266443 RX DQ/DQS(Engine): PASS
6043 05:56:50.269345 TX OE : NO K
6044 05:56:50.269440 All Pass.
6045 05:56:50.269528
6046 05:56:50.272751 DramC Write-DBI off
6047 05:56:50.276183 PER_BANK_REFRESH: Hybrid Mode
6048 05:56:50.276251 TX_TRACKING: ON
6049 05:56:50.286160 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6050 05:56:50.289164 [FAST_K] Save calibration result to emmc
6051 05:56:50.292572 dramc_set_vcore_voltage set vcore to 650000
6052 05:56:50.295983 Read voltage for 400, 6
6053 05:56:50.296079 Vio18 = 0
6054 05:56:50.296170 Vcore = 650000
6055 05:56:50.299183 Vdram = 0
6056 05:56:50.299266 Vddq = 0
6057 05:56:50.299357 Vmddr = 0
6058 05:56:50.305870 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6059 05:56:50.309379 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6060 05:56:50.312830 MEM_TYPE=3, freq_sel=20
6061 05:56:50.315806 sv_algorithm_assistance_LP4_800
6062 05:56:50.319162 ============ PULL DRAM RESETB DOWN ============
6063 05:56:50.322364 ========== PULL DRAM RESETB DOWN end =========
6064 05:56:50.329337 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6065 05:56:50.332213 ===================================
6066 05:56:50.332317 LPDDR4 DRAM CONFIGURATION
6067 05:56:50.335858 ===================================
6068 05:56:50.338845 EX_ROW_EN[0] = 0x0
6069 05:56:50.342108 EX_ROW_EN[1] = 0x0
6070 05:56:50.342187 LP4Y_EN = 0x0
6071 05:56:50.345567 WORK_FSP = 0x0
6072 05:56:50.345668 WL = 0x2
6073 05:56:50.349250 RL = 0x2
6074 05:56:50.349324 BL = 0x2
6075 05:56:50.352467 RPST = 0x0
6076 05:56:50.352539 RD_PRE = 0x0
6077 05:56:50.355601 WR_PRE = 0x1
6078 05:56:50.355683 WR_PST = 0x0
6079 05:56:50.359083 DBI_WR = 0x0
6080 05:56:50.359166 DBI_RD = 0x0
6081 05:56:50.362173 OTF = 0x1
6082 05:56:50.365690 ===================================
6083 05:56:50.368727 ===================================
6084 05:56:50.368810 ANA top config
6085 05:56:50.372252 ===================================
6086 05:56:50.375909 DLL_ASYNC_EN = 0
6087 05:56:50.378833 ALL_SLAVE_EN = 1
6088 05:56:50.382238 NEW_RANK_MODE = 1
6089 05:56:50.382321 DLL_IDLE_MODE = 1
6090 05:56:50.385794 LP45_APHY_COMB_EN = 1
6091 05:56:50.388868 TX_ODT_DIS = 1
6092 05:56:50.392305 NEW_8X_MODE = 1
6093 05:56:50.395876 ===================================
6094 05:56:50.398868 ===================================
6095 05:56:50.402160 data_rate = 800
6096 05:56:50.402243 CKR = 1
6097 05:56:50.405776 DQ_P2S_RATIO = 4
6098 05:56:50.408804 ===================================
6099 05:56:50.412228 CA_P2S_RATIO = 4
6100 05:56:50.415752 DQ_CA_OPEN = 0
6101 05:56:50.419001 DQ_SEMI_OPEN = 1
6102 05:56:50.419106 CA_SEMI_OPEN = 1
6103 05:56:50.422168 CA_FULL_RATE = 0
6104 05:56:50.425259 DQ_CKDIV4_EN = 0
6105 05:56:50.428440 CA_CKDIV4_EN = 1
6106 05:56:50.431981 CA_PREDIV_EN = 0
6107 05:56:50.435207 PH8_DLY = 0
6108 05:56:50.435318 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6109 05:56:50.438665 DQ_AAMCK_DIV = 0
6110 05:56:50.441756 CA_AAMCK_DIV = 0
6111 05:56:50.445507 CA_ADMCK_DIV = 4
6112 05:56:50.448392 DQ_TRACK_CA_EN = 0
6113 05:56:50.451754 CA_PICK = 800
6114 05:56:50.455295 CA_MCKIO = 400
6115 05:56:50.455378 MCKIO_SEMI = 400
6116 05:56:50.458770 PLL_FREQ = 3016
6117 05:56:50.461835 DQ_UI_PI_RATIO = 32
6118 05:56:50.465196 CA_UI_PI_RATIO = 32
6119 05:56:50.468239 ===================================
6120 05:56:50.471901 ===================================
6121 05:56:50.475028 memory_type:LPDDR4
6122 05:56:50.475111 GP_NUM : 10
6123 05:56:50.478339 SRAM_EN : 1
6124 05:56:50.481828 MD32_EN : 0
6125 05:56:50.485301 ===================================
6126 05:56:50.485384 [ANA_INIT] >>>>>>>>>>>>>>
6127 05:56:50.488346 <<<<<< [CONFIGURE PHASE]: ANA_TX
6128 05:56:50.491947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6129 05:56:50.495370 ===================================
6130 05:56:50.498224 data_rate = 800,PCW = 0X7400
6131 05:56:50.501840 ===================================
6132 05:56:50.504753 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6133 05:56:50.511638 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6134 05:56:50.521509 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6135 05:56:50.528070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6136 05:56:50.531816 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6137 05:56:50.534870 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6138 05:56:50.534953 [ANA_INIT] flow start
6139 05:56:50.538427 [ANA_INIT] PLL >>>>>>>>
6140 05:56:50.541726 [ANA_INIT] PLL <<<<<<<<
6141 05:56:50.541808 [ANA_INIT] MIDPI >>>>>>>>
6142 05:56:50.544909 [ANA_INIT] MIDPI <<<<<<<<
6143 05:56:50.548073 [ANA_INIT] DLL >>>>>>>>
6144 05:56:50.548156 [ANA_INIT] flow end
6145 05:56:50.554607 ============ LP4 DIFF to SE enter ============
6146 05:56:50.558067 ============ LP4 DIFF to SE exit ============
6147 05:56:50.558151 [ANA_INIT] <<<<<<<<<<<<<
6148 05:56:50.561548 [Flow] Enable top DCM control >>>>>
6149 05:56:50.564553 [Flow] Enable top DCM control <<<<<
6150 05:56:50.568048 Enable DLL master slave shuffle
6151 05:56:50.574857 ==============================================================
6152 05:56:50.577898 Gating Mode config
6153 05:56:50.581253 ==============================================================
6154 05:56:50.584820 Config description:
6155 05:56:50.594395 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6156 05:56:50.601615 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6157 05:56:50.604642 SELPH_MODE 0: By rank 1: By Phase
6158 05:56:50.611300 ==============================================================
6159 05:56:50.614612 GAT_TRACK_EN = 0
6160 05:56:50.617658 RX_GATING_MODE = 2
6161 05:56:50.621209 RX_GATING_TRACK_MODE = 2
6162 05:56:50.621292 SELPH_MODE = 1
6163 05:56:50.624310 PICG_EARLY_EN = 1
6164 05:56:50.627804 VALID_LAT_VALUE = 1
6165 05:56:50.634414 ==============================================================
6166 05:56:50.637895 Enter into Gating configuration >>>>
6167 05:56:50.640995 Exit from Gating configuration <<<<
6168 05:56:50.644171 Enter into DVFS_PRE_config >>>>>
6169 05:56:50.654177 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6170 05:56:50.657825 Exit from DVFS_PRE_config <<<<<
6171 05:56:50.660916 Enter into PICG configuration >>>>
6172 05:56:50.664106 Exit from PICG configuration <<<<
6173 05:56:50.667541 [RX_INPUT] configuration >>>>>
6174 05:56:50.670963 [RX_INPUT] configuration <<<<<
6175 05:56:50.674041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6176 05:56:50.681095 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6177 05:56:50.687785 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6178 05:56:50.694225 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6179 05:56:50.700630 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6180 05:56:50.704159 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6181 05:56:50.710643 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6182 05:56:50.714160 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6183 05:56:50.717331 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6184 05:56:50.720674 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6185 05:56:50.724252 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6186 05:56:50.730770 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6187 05:56:50.734220 ===================================
6188 05:56:50.737644 LPDDR4 DRAM CONFIGURATION
6189 05:56:50.737755 ===================================
6190 05:56:50.740931 EX_ROW_EN[0] = 0x0
6191 05:56:50.744208 EX_ROW_EN[1] = 0x0
6192 05:56:50.744286 LP4Y_EN = 0x0
6193 05:56:50.747380 WORK_FSP = 0x0
6194 05:56:50.747453 WL = 0x2
6195 05:56:50.750847 RL = 0x2
6196 05:56:50.750931 BL = 0x2
6197 05:56:50.753795 RPST = 0x0
6198 05:56:50.753879 RD_PRE = 0x0
6199 05:56:50.757473 WR_PRE = 0x1
6200 05:56:50.757557 WR_PST = 0x0
6201 05:56:50.760479 DBI_WR = 0x0
6202 05:56:50.760561 DBI_RD = 0x0
6203 05:56:50.764048 OTF = 0x1
6204 05:56:50.767576 ===================================
6205 05:56:50.770680 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6206 05:56:50.773862 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6207 05:56:50.780836 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6208 05:56:50.783792 ===================================
6209 05:56:50.783875 LPDDR4 DRAM CONFIGURATION
6210 05:56:50.787267 ===================================
6211 05:56:50.790960 EX_ROW_EN[0] = 0x10
6212 05:56:50.793855 EX_ROW_EN[1] = 0x0
6213 05:56:50.793952 LP4Y_EN = 0x0
6214 05:56:50.797252 WORK_FSP = 0x0
6215 05:56:50.797337 WL = 0x2
6216 05:56:50.800771 RL = 0x2
6217 05:56:50.800855 BL = 0x2
6218 05:56:50.803833 RPST = 0x0
6219 05:56:50.803916 RD_PRE = 0x0
6220 05:56:50.807334 WR_PRE = 0x1
6221 05:56:50.807417 WR_PST = 0x0
6222 05:56:50.810268 DBI_WR = 0x0
6223 05:56:50.810351 DBI_RD = 0x0
6224 05:56:50.813837 OTF = 0x1
6225 05:56:50.817237 ===================================
6226 05:56:50.823900 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6227 05:56:50.826952 nWR fixed to 30
6228 05:56:50.827037 [ModeRegInit_LP4] CH0 RK0
6229 05:56:50.830474 [ModeRegInit_LP4] CH0 RK1
6230 05:56:50.833903 [ModeRegInit_LP4] CH1 RK0
6231 05:56:50.836918 [ModeRegInit_LP4] CH1 RK1
6232 05:56:50.837001 match AC timing 19
6233 05:56:50.843583 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6234 05:56:50.847022 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6235 05:56:50.850369 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6236 05:56:50.856916 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6237 05:56:50.860465 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6238 05:56:50.860560 ==
6239 05:56:50.863415 Dram Type= 6, Freq= 0, CH_0, rank 0
6240 05:56:50.866886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 05:56:50.866973 ==
6242 05:56:50.873701 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6243 05:56:50.880243 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6244 05:56:50.883905 [CA 0] Center 36 (8~64) winsize 57
6245 05:56:50.883990 [CA 1] Center 36 (8~64) winsize 57
6246 05:56:50.886853 [CA 2] Center 36 (8~64) winsize 57
6247 05:56:50.890274 [CA 3] Center 36 (8~64) winsize 57
6248 05:56:50.893248 [CA 4] Center 36 (8~64) winsize 57
6249 05:56:50.896750 [CA 5] Center 36 (8~64) winsize 57
6250 05:56:50.896836
6251 05:56:50.900227 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6252 05:56:50.900312
6253 05:56:50.906717 [CATrainingPosCal] consider 1 rank data
6254 05:56:50.906807 u2DelayCellTimex100 = 270/100 ps
6255 05:56:50.910113 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 05:56:50.916636 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 05:56:50.920168 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 05:56:50.923193 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 05:56:50.926535 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 05:56:50.929920 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 05:56:50.930003
6262 05:56:50.933239 CA PerBit enable=1, Macro0, CA PI delay=36
6263 05:56:50.933314
6264 05:56:50.936755 [CBTSetCACLKResult] CA Dly = 36
6265 05:56:50.936829 CS Dly: 1 (0~32)
6266 05:56:50.940267 ==
6267 05:56:50.943347 Dram Type= 6, Freq= 0, CH_0, rank 1
6268 05:56:50.946907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 05:56:50.946986 ==
6270 05:56:50.950199 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6271 05:56:50.956426 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6272 05:56:50.960016 [CA 0] Center 36 (8~64) winsize 57
6273 05:56:50.963105 [CA 1] Center 36 (8~64) winsize 57
6274 05:56:50.966920 [CA 2] Center 36 (8~64) winsize 57
6275 05:56:50.970095 [CA 3] Center 36 (8~64) winsize 57
6276 05:56:50.973240 [CA 4] Center 36 (8~64) winsize 57
6277 05:56:50.976729 [CA 5] Center 36 (8~64) winsize 57
6278 05:56:50.976803
6279 05:56:50.979989 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6280 05:56:50.980064
6281 05:56:50.983117 [CATrainingPosCal] consider 2 rank data
6282 05:56:50.986313 u2DelayCellTimex100 = 270/100 ps
6283 05:56:50.989728 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 05:56:50.992878 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 05:56:50.996244 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 05:56:50.999835 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 05:56:51.006333 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 05:56:51.009594 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 05:56:51.009667
6290 05:56:51.012649 CA PerBit enable=1, Macro0, CA PI delay=36
6291 05:56:51.012723
6292 05:56:51.016168 [CBTSetCACLKResult] CA Dly = 36
6293 05:56:51.016252 CS Dly: 1 (0~32)
6294 05:56:51.016315
6295 05:56:51.019764 ----->DramcWriteLeveling(PI) begin...
6296 05:56:51.019838 ==
6297 05:56:51.022741 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 05:56:51.029132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 05:56:51.029214 ==
6300 05:56:51.032449 Write leveling (Byte 0): 40 => 8
6301 05:56:51.035922 Write leveling (Byte 1): 32 => 0
6302 05:56:51.035994 DramcWriteLeveling(PI) end<-----
6303 05:56:51.036056
6304 05:56:51.039348 ==
6305 05:56:51.042708 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 05:56:51.045741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 05:56:51.045842 ==
6308 05:56:51.049141 [Gating] SW mode calibration
6309 05:56:51.055784 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6310 05:56:51.059061 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6311 05:56:51.065891 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6312 05:56:51.068721 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6313 05:56:51.072224 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6314 05:56:51.078621 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6315 05:56:51.082123 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 05:56:51.085753 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6317 05:56:51.092064 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6318 05:56:51.095424 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 05:56:51.098974 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6320 05:56:51.102362 Total UI for P1: 0, mck2ui 16
6321 05:56:51.105388 best dqsien dly found for B0: ( 0, 14, 24)
6322 05:56:51.108839 Total UI for P1: 0, mck2ui 16
6323 05:56:51.111861 best dqsien dly found for B1: ( 0, 14, 24)
6324 05:56:51.115198 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6325 05:56:51.118711 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6326 05:56:51.122223
6327 05:56:51.125271 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6328 05:56:51.128721 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6329 05:56:51.131689 [Gating] SW calibration Done
6330 05:56:51.131758 ==
6331 05:56:51.135033 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 05:56:51.138543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 05:56:51.138613 ==
6334 05:56:51.138680 RX Vref Scan: 0
6335 05:56:51.138739
6336 05:56:51.142088 RX Vref 0 -> 0, step: 1
6337 05:56:51.142160
6338 05:56:51.144964 RX Delay -410 -> 252, step: 16
6339 05:56:51.148459 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6340 05:56:51.155047 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6341 05:56:51.158587 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6342 05:56:51.161583 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6343 05:56:51.165065 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6344 05:56:51.171542 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6345 05:56:51.175187 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6346 05:56:51.178247 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6347 05:56:51.181589 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6348 05:56:51.188099 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6349 05:56:51.191276 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6350 05:56:51.194590 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6351 05:56:51.197726 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6352 05:56:51.204632 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6353 05:56:51.207751 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6354 05:56:51.211203 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6355 05:56:51.211277 ==
6356 05:56:51.214683 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 05:56:51.220995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 05:56:51.221080 ==
6359 05:56:51.221143 DQS Delay:
6360 05:56:51.224478 DQS0 = 27, DQS1 = 43
6361 05:56:51.224553 DQM Delay:
6362 05:56:51.224614 DQM0 = 13, DQM1 = 12
6363 05:56:51.228005 DQ Delay:
6364 05:56:51.230969 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6365 05:56:51.234524 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6366 05:56:51.234622 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6367 05:56:51.237833 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6368 05:56:51.241086
6369 05:56:51.241160
6370 05:56:51.241224 ==
6371 05:56:51.244063 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 05:56:51.247497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 05:56:51.247573 ==
6374 05:56:51.247633
6375 05:56:51.247689
6376 05:56:51.251046 TX Vref Scan disable
6377 05:56:51.251110 == TX Byte 0 ==
6378 05:56:51.254081 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 05:56:51.260983 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 05:56:51.261053 == TX Byte 1 ==
6381 05:56:51.264421 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6382 05:56:51.270760 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6383 05:56:51.270838 ==
6384 05:56:51.274097 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 05:56:51.277780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 05:56:51.277882 ==
6387 05:56:51.277993
6388 05:56:51.278052
6389 05:56:51.280643 TX Vref Scan disable
6390 05:56:51.280718 == TX Byte 0 ==
6391 05:56:51.287522 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 05:56:51.290903 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 05:56:51.290985 == TX Byte 1 ==
6394 05:56:51.297233 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6395 05:56:51.300722 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6396 05:56:51.300810
6397 05:56:51.300878 [DATLAT]
6398 05:56:51.303835 Freq=400, CH0 RK0
6399 05:56:51.303905
6400 05:56:51.303976 DATLAT Default: 0xf
6401 05:56:51.307350 0, 0xFFFF, sum = 0
6402 05:56:51.307444 1, 0xFFFF, sum = 0
6403 05:56:51.310594 2, 0xFFFF, sum = 0
6404 05:56:51.310677 3, 0xFFFF, sum = 0
6405 05:56:51.314098 4, 0xFFFF, sum = 0
6406 05:56:51.314222 5, 0xFFFF, sum = 0
6407 05:56:51.317162 6, 0xFFFF, sum = 0
6408 05:56:51.317274 7, 0xFFFF, sum = 0
6409 05:56:51.320617 8, 0xFFFF, sum = 0
6410 05:56:51.320728 9, 0xFFFF, sum = 0
6411 05:56:51.324067 10, 0xFFFF, sum = 0
6412 05:56:51.327139 11, 0xFFFF, sum = 0
6413 05:56:51.327220 12, 0xFFFF, sum = 0
6414 05:56:51.330628 13, 0x0, sum = 1
6415 05:56:51.330713 14, 0x0, sum = 2
6416 05:56:51.330795 15, 0x0, sum = 3
6417 05:56:51.334082 16, 0x0, sum = 4
6418 05:56:51.334166 best_step = 14
6419 05:56:51.334248
6420 05:56:51.337076 ==
6421 05:56:51.337148 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 05:56:51.343913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 05:56:51.344000 ==
6424 05:56:51.344085 RX Vref Scan: 1
6425 05:56:51.344173
6426 05:56:51.347442 RX Vref 0 -> 0, step: 1
6427 05:56:51.347530
6428 05:56:51.350302 RX Delay -327 -> 252, step: 8
6429 05:56:51.350390
6430 05:56:51.353777 Set Vref, RX VrefLevel [Byte0]: 57
6431 05:56:51.357178 [Byte1]: 49
6432 05:56:51.360710
6433 05:56:51.360798 Final RX Vref Byte 0 = 57 to rank0
6434 05:56:51.363738 Final RX Vref Byte 1 = 49 to rank0
6435 05:56:51.367297 Final RX Vref Byte 0 = 57 to rank1
6436 05:56:51.370345 Final RX Vref Byte 1 = 49 to rank1==
6437 05:56:51.373725 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 05:56:51.380247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 05:56:51.380341 ==
6440 05:56:51.380428 DQS Delay:
6441 05:56:51.383548 DQS0 = 28, DQS1 = 48
6442 05:56:51.383634 DQM Delay:
6443 05:56:51.383722 DQM0 = 12, DQM1 = 16
6444 05:56:51.387378 DQ Delay:
6445 05:56:51.390210 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6446 05:56:51.390294 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6447 05:56:51.393887 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6448 05:56:51.397313 DQ12 =24, DQ13 =16, DQ14 =28, DQ15 =24
6449 05:56:51.397400
6450 05:56:51.400275
6451 05:56:51.406859 [DQSOSCAuto] RK0, (LSB)MR18= 0xa59d, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 389 ps
6452 05:56:51.410299 CH0 RK0: MR19=C0C, MR18=A59D
6453 05:56:51.416807 CH0_RK0: MR19=0xC0C, MR18=0xA59D, DQSOSC=389, MR23=63, INC=390, DEC=260
6454 05:56:51.416894 ==
6455 05:56:51.420325 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 05:56:51.423774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 05:56:51.423865 ==
6458 05:56:51.426793 [Gating] SW mode calibration
6459 05:56:51.433801 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6460 05:56:51.440458 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6461 05:56:51.443574 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6462 05:56:51.446906 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6463 05:56:51.453718 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6464 05:56:51.457158 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6465 05:56:51.460175 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 05:56:51.463622 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6467 05:56:51.470554 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6468 05:56:51.473888 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 05:56:51.476842 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6470 05:56:51.480317 Total UI for P1: 0, mck2ui 16
6471 05:56:51.483641 best dqsien dly found for B0: ( 0, 14, 24)
6472 05:56:51.486938 Total UI for P1: 0, mck2ui 16
6473 05:56:51.490402 best dqsien dly found for B1: ( 0, 14, 24)
6474 05:56:51.493805 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6475 05:56:51.497099 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6476 05:56:51.500392
6477 05:56:51.503844 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6478 05:56:51.506914 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6479 05:56:51.510330 [Gating] SW calibration Done
6480 05:56:51.510413 ==
6481 05:56:51.513799 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 05:56:51.517055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 05:56:51.517135 ==
6484 05:56:51.517224 RX Vref Scan: 0
6485 05:56:51.517303
6486 05:56:51.520292 RX Vref 0 -> 0, step: 1
6487 05:56:51.520382
6488 05:56:51.523456 RX Delay -410 -> 252, step: 16
6489 05:56:51.526577 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6490 05:56:51.533422 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6491 05:56:51.536880 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6492 05:56:51.540345 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6493 05:56:51.543380 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6494 05:56:51.549793 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6495 05:56:51.553681 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6496 05:56:51.556549 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6497 05:56:51.560005 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6498 05:56:51.566827 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6499 05:56:51.570311 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6500 05:56:51.573834 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6501 05:56:51.576674 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6502 05:56:51.583608 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6503 05:56:51.586722 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6504 05:56:51.590062 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6505 05:56:51.590152 ==
6506 05:56:51.593235 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 05:56:51.596673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 05:56:51.599964 ==
6509 05:56:51.600054 DQS Delay:
6510 05:56:51.600124 DQS0 = 27, DQS1 = 43
6511 05:56:51.603505 DQM Delay:
6512 05:56:51.603624 DQM0 = 9, DQM1 = 16
6513 05:56:51.606302 DQ Delay:
6514 05:56:51.606379 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6515 05:56:51.609748 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6516 05:56:51.612932 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6517 05:56:51.616492 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6518 05:56:51.616582
6519 05:56:51.616653
6520 05:56:51.619639 ==
6521 05:56:51.619720 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 05:56:51.626551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 05:56:51.626636 ==
6524 05:56:51.626707
6525 05:56:51.626768
6526 05:56:51.629647 TX Vref Scan disable
6527 05:56:51.629749 == TX Byte 0 ==
6528 05:56:51.632767 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6529 05:56:51.639570 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6530 05:56:51.639655 == TX Byte 1 ==
6531 05:56:51.642999 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6532 05:56:51.649476 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6533 05:56:51.649553 ==
6534 05:56:51.653002 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 05:56:51.656331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 05:56:51.656460 ==
6537 05:56:51.656527
6538 05:56:51.656620
6539 05:56:51.659828 TX Vref Scan disable
6540 05:56:51.659930 == TX Byte 0 ==
6541 05:56:51.662763 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6542 05:56:51.669326 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6543 05:56:51.669419 == TX Byte 1 ==
6544 05:56:51.672822 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6545 05:56:51.679159 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6546 05:56:51.679279
6547 05:56:51.679379 [DATLAT]
6548 05:56:51.679471 Freq=400, CH0 RK1
6549 05:56:51.679574
6550 05:56:51.682663 DATLAT Default: 0xe
6551 05:56:51.686234 0, 0xFFFF, sum = 0
6552 05:56:51.686308 1, 0xFFFF, sum = 0
6553 05:56:51.689204 2, 0xFFFF, sum = 0
6554 05:56:51.689289 3, 0xFFFF, sum = 0
6555 05:56:51.692431 4, 0xFFFF, sum = 0
6556 05:56:51.692513 5, 0xFFFF, sum = 0
6557 05:56:51.695976 6, 0xFFFF, sum = 0
6558 05:56:51.696081 7, 0xFFFF, sum = 0
6559 05:56:51.699454 8, 0xFFFF, sum = 0
6560 05:56:51.699530 9, 0xFFFF, sum = 0
6561 05:56:51.702437 10, 0xFFFF, sum = 0
6562 05:56:51.702530 11, 0xFFFF, sum = 0
6563 05:56:51.705773 12, 0xFFFF, sum = 0
6564 05:56:51.705889 13, 0x0, sum = 1
6565 05:56:51.709302 14, 0x0, sum = 2
6566 05:56:51.709389 15, 0x0, sum = 3
6567 05:56:51.712630 16, 0x0, sum = 4
6568 05:56:51.712715 best_step = 14
6569 05:56:51.712781
6570 05:56:51.712844 ==
6571 05:56:51.715635 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 05:56:51.722237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 05:56:51.722325 ==
6574 05:56:51.722394 RX Vref Scan: 0
6575 05:56:51.722458
6576 05:56:51.725550 RX Vref 0 -> 0, step: 1
6577 05:56:51.725633
6578 05:56:51.728926 RX Delay -327 -> 252, step: 8
6579 05:56:51.735361 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6580 05:56:51.738921 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6581 05:56:51.742370 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6582 05:56:51.745612 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6583 05:56:51.752069 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6584 05:56:51.755480 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6585 05:56:51.758508 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6586 05:56:51.762339 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6587 05:56:51.768349 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6588 05:56:51.771961 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6589 05:56:51.775104 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6590 05:56:51.778735 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6591 05:56:51.785213 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6592 05:56:51.788106 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6593 05:56:51.791580 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6594 05:56:51.798381 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6595 05:56:51.798465 ==
6596 05:56:51.801840 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 05:56:51.804939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 05:56:51.805023 ==
6599 05:56:51.805137 DQS Delay:
6600 05:56:51.808374 DQS0 = 28, DQS1 = 40
6601 05:56:51.808457 DQM Delay:
6602 05:56:51.811843 DQM0 = 10, DQM1 = 11
6603 05:56:51.811927 DQ Delay:
6604 05:56:51.814861 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6605 05:56:51.818310 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6606 05:56:51.821334 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6607 05:56:51.824771 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =16
6608 05:56:51.824857
6609 05:56:51.824925
6610 05:56:51.831561 [DQSOSCAuto] RK1, (LSB)MR18= 0xb568, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6611 05:56:51.834675 CH0 RK1: MR19=C0C, MR18=B568
6612 05:56:51.841472 CH0_RK1: MR19=0xC0C, MR18=0xB568, DQSOSC=387, MR23=63, INC=394, DEC=262
6613 05:56:51.844796 [RxdqsGatingPostProcess] freq 400
6614 05:56:51.851221 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6615 05:56:51.854574 best DQS0 dly(2T, 0.5T) = (0, 10)
6616 05:56:51.854653 best DQS1 dly(2T, 0.5T) = (0, 10)
6617 05:56:51.857636 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6618 05:56:51.861139 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6619 05:56:51.864441 best DQS0 dly(2T, 0.5T) = (0, 10)
6620 05:56:51.867312 best DQS1 dly(2T, 0.5T) = (0, 10)
6621 05:56:51.870881 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6622 05:56:51.874276 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6623 05:56:51.877763 Pre-setting of DQS Precalculation
6624 05:56:51.884259 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6625 05:56:51.884341 ==
6626 05:56:51.887241 Dram Type= 6, Freq= 0, CH_1, rank 0
6627 05:56:51.890623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 05:56:51.890710 ==
6629 05:56:51.897581 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6630 05:56:51.903767 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6631 05:56:51.903846 [CA 0] Center 36 (8~64) winsize 57
6632 05:56:51.907105 [CA 1] Center 36 (8~64) winsize 57
6633 05:56:51.910596 [CA 2] Center 36 (8~64) winsize 57
6634 05:56:51.914118 [CA 3] Center 36 (8~64) winsize 57
6635 05:56:51.917200 [CA 4] Center 36 (8~64) winsize 57
6636 05:56:51.920593 [CA 5] Center 36 (8~64) winsize 57
6637 05:56:51.920673
6638 05:56:51.924119 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6639 05:56:51.924198
6640 05:56:51.926996 [CATrainingPosCal] consider 1 rank data
6641 05:56:51.930527 u2DelayCellTimex100 = 270/100 ps
6642 05:56:51.933883 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 05:56:51.937167 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 05:56:51.943429 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 05:56:51.947079 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 05:56:51.950063 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 05:56:51.953728 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 05:56:51.953812
6649 05:56:51.956792 CA PerBit enable=1, Macro0, CA PI delay=36
6650 05:56:51.956876
6651 05:56:51.960071 [CBTSetCACLKResult] CA Dly = 36
6652 05:56:51.960153 CS Dly: 1 (0~32)
6653 05:56:51.963453 ==
6654 05:56:51.963536 Dram Type= 6, Freq= 0, CH_1, rank 1
6655 05:56:51.970103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 05:56:51.970186 ==
6657 05:56:51.973188 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6658 05:56:51.980213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6659 05:56:51.983676 [CA 0] Center 36 (8~64) winsize 57
6660 05:56:51.986790 [CA 1] Center 36 (8~64) winsize 57
6661 05:56:51.990170 [CA 2] Center 36 (8~64) winsize 57
6662 05:56:51.993228 [CA 3] Center 36 (8~64) winsize 57
6663 05:56:51.996596 [CA 4] Center 36 (8~64) winsize 57
6664 05:56:52.000089 [CA 5] Center 36 (8~64) winsize 57
6665 05:56:52.000172
6666 05:56:52.003444 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6667 05:56:52.003526
6668 05:56:52.006795 [CATrainingPosCal] consider 2 rank data
6669 05:56:52.010056 u2DelayCellTimex100 = 270/100 ps
6670 05:56:52.013571 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 05:56:52.016502 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 05:56:52.019948 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 05:56:52.023236 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 05:56:52.030057 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 05:56:52.033563 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 05:56:52.033647
6677 05:56:52.036499 CA PerBit enable=1, Macro0, CA PI delay=36
6678 05:56:52.036583
6679 05:56:52.039861 [CBTSetCACLKResult] CA Dly = 36
6680 05:56:52.039945 CS Dly: 1 (0~32)
6681 05:56:52.040012
6682 05:56:52.043056 ----->DramcWriteLeveling(PI) begin...
6683 05:56:52.043141 ==
6684 05:56:52.046497 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 05:56:52.053093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 05:56:52.053177 ==
6687 05:56:52.056234 Write leveling (Byte 0): 40 => 8
6688 05:56:52.056318 Write leveling (Byte 1): 32 => 0
6689 05:56:52.059684 DramcWriteLeveling(PI) end<-----
6690 05:56:52.059768
6691 05:56:52.059834 ==
6692 05:56:52.063025 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 05:56:52.069603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 05:56:52.069687 ==
6695 05:56:52.073094 [Gating] SW mode calibration
6696 05:56:52.079520 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6697 05:56:52.082989 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6698 05:56:52.089790 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6699 05:56:52.093240 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6700 05:56:52.096404 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6701 05:56:52.103232 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6702 05:56:52.106301 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 05:56:52.109612 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6704 05:56:52.113002 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6705 05:56:52.119835 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 05:56:52.123027 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6707 05:56:52.126344 Total UI for P1: 0, mck2ui 16
6708 05:56:52.129548 best dqsien dly found for B0: ( 0, 14, 24)
6709 05:56:52.133017 Total UI for P1: 0, mck2ui 16
6710 05:56:52.136406 best dqsien dly found for B1: ( 0, 14, 24)
6711 05:56:52.139583 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6712 05:56:52.142787 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6713 05:56:52.142871
6714 05:56:52.146004 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6715 05:56:52.152868 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6716 05:56:52.152970 [Gating] SW calibration Done
6717 05:56:52.153051 ==
6718 05:56:52.156204 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 05:56:52.162560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 05:56:52.162648 ==
6721 05:56:52.162715 RX Vref Scan: 0
6722 05:56:52.162777
6723 05:56:52.166008 RX Vref 0 -> 0, step: 1
6724 05:56:52.166091
6725 05:56:52.169106 RX Delay -410 -> 252, step: 16
6726 05:56:52.172813 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6727 05:56:52.175826 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6728 05:56:52.182304 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6729 05:56:52.185736 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6730 05:56:52.189266 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6731 05:56:52.192248 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6732 05:56:52.198847 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6733 05:56:52.202273 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6734 05:56:52.205577 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6735 05:56:52.209128 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6736 05:56:52.215846 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6737 05:56:52.219068 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6738 05:56:52.222561 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6739 05:56:52.225475 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6740 05:56:52.232249 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6741 05:56:52.235721 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6742 05:56:52.235805 ==
6743 05:56:52.239139 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 05:56:52.242422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 05:56:52.242507 ==
6746 05:56:52.245829 DQS Delay:
6747 05:56:52.245947 DQS0 = 27, DQS1 = 43
6748 05:56:52.249161 DQM Delay:
6749 05:56:52.249244 DQM0 = 5, DQM1 = 14
6750 05:56:52.249311 DQ Delay:
6751 05:56:52.252640 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6752 05:56:52.255984 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6753 05:56:52.258896 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6754 05:56:52.262433 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6755 05:56:52.262518
6756 05:56:52.262584
6757 05:56:52.262645 ==
6758 05:56:52.265514 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 05:56:52.268961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 05:56:52.272422 ==
6761 05:56:52.272535
6762 05:56:52.272629
6763 05:56:52.272719 TX Vref Scan disable
6764 05:56:52.275692 == TX Byte 0 ==
6765 05:56:52.278887 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 05:56:52.282050 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 05:56:52.285445 == TX Byte 1 ==
6768 05:56:52.288928 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6769 05:56:52.292091 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6770 05:56:52.292175 ==
6771 05:56:52.295520 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 05:56:52.302047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 05:56:52.302155 ==
6774 05:56:52.302224
6775 05:56:52.302288
6776 05:56:52.302347 TX Vref Scan disable
6777 05:56:52.305448 == TX Byte 0 ==
6778 05:56:52.309007 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 05:56:52.312052 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 05:56:52.315316 == TX Byte 1 ==
6781 05:56:52.318446 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6782 05:56:52.321766 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6783 05:56:52.321850
6784 05:56:52.325107 [DATLAT]
6785 05:56:52.325190 Freq=400, CH1 RK0
6786 05:56:52.325258
6787 05:56:52.328622 DATLAT Default: 0xf
6788 05:56:52.328706 0, 0xFFFF, sum = 0
6789 05:56:52.332137 1, 0xFFFF, sum = 0
6790 05:56:52.332222 2, 0xFFFF, sum = 0
6791 05:56:52.335407 3, 0xFFFF, sum = 0
6792 05:56:52.335492 4, 0xFFFF, sum = 0
6793 05:56:52.338775 5, 0xFFFF, sum = 0
6794 05:56:52.338860 6, 0xFFFF, sum = 0
6795 05:56:52.341666 7, 0xFFFF, sum = 0
6796 05:56:52.345128 8, 0xFFFF, sum = 0
6797 05:56:52.345213 9, 0xFFFF, sum = 0
6798 05:56:52.348742 10, 0xFFFF, sum = 0
6799 05:56:52.348827 11, 0xFFFF, sum = 0
6800 05:56:52.351532 12, 0xFFFF, sum = 0
6801 05:56:52.351663 13, 0x0, sum = 1
6802 05:56:52.355014 14, 0x0, sum = 2
6803 05:56:52.355098 15, 0x0, sum = 3
6804 05:56:52.358711 16, 0x0, sum = 4
6805 05:56:52.358796 best_step = 14
6806 05:56:52.358862
6807 05:56:52.358924 ==
6808 05:56:52.361791 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 05:56:52.365338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 05:56:52.365422 ==
6811 05:56:52.368327 RX Vref Scan: 1
6812 05:56:52.368410
6813 05:56:52.371879 RX Vref 0 -> 0, step: 1
6814 05:56:52.371962
6815 05:56:52.372028 RX Delay -327 -> 252, step: 8
6816 05:56:52.372091
6817 05:56:52.375355 Set Vref, RX VrefLevel [Byte0]: 52
6818 05:56:52.378230 [Byte1]: 52
6819 05:56:52.383892
6820 05:56:52.383977 Final RX Vref Byte 0 = 52 to rank0
6821 05:56:52.387108 Final RX Vref Byte 1 = 52 to rank0
6822 05:56:52.390301 Final RX Vref Byte 0 = 52 to rank1
6823 05:56:52.393556 Final RX Vref Byte 1 = 52 to rank1==
6824 05:56:52.397077 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 05:56:52.403938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 05:56:52.404024 ==
6827 05:56:52.404092 DQS Delay:
6828 05:56:52.406887 DQS0 = 32, DQS1 = 40
6829 05:56:52.406971 DQM Delay:
6830 05:56:52.407038 DQM0 = 12, DQM1 = 12
6831 05:56:52.410286 DQ Delay:
6832 05:56:52.413801 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6833 05:56:52.413885 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6834 05:56:52.416774 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6835 05:56:52.420157 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6836 05:56:52.420256
6837 05:56:52.420322
6838 05:56:52.430143 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ec8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6839 05:56:52.433577 CH1 RK0: MR19=C0C, MR18=8EC8
6840 05:56:52.440316 CH1_RK0: MR19=0xC0C, MR18=0x8EC8, DQSOSC=385, MR23=63, INC=398, DEC=265
6841 05:56:52.440401 ==
6842 05:56:52.443548 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 05:56:52.446952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 05:56:52.447038 ==
6845 05:56:52.449980 [Gating] SW mode calibration
6846 05:56:52.456859 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6847 05:56:52.463603 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6848 05:56:52.466757 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6849 05:56:52.470336 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6850 05:56:52.473376 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6851 05:56:52.480079 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6852 05:56:52.483469 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 05:56:52.486491 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6854 05:56:52.493105 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6855 05:56:52.496626 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 05:56:52.500033 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6857 05:56:52.503378 Total UI for P1: 0, mck2ui 16
6858 05:56:52.506439 best dqsien dly found for B0: ( 0, 14, 24)
6859 05:56:52.509956 Total UI for P1: 0, mck2ui 16
6860 05:56:52.513275 best dqsien dly found for B1: ( 0, 14, 24)
6861 05:56:52.516727 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6862 05:56:52.519701 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6863 05:56:52.523232
6864 05:56:52.526707 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6865 05:56:52.529593 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6866 05:56:52.532982 [Gating] SW calibration Done
6867 05:56:52.533066 ==
6868 05:56:52.536337 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 05:56:52.539822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 05:56:52.539906 ==
6871 05:56:52.539973 RX Vref Scan: 0
6872 05:56:52.542820
6873 05:56:52.542904 RX Vref 0 -> 0, step: 1
6874 05:56:52.542971
6875 05:56:52.546592 RX Delay -410 -> 252, step: 16
6876 05:56:52.549508 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6877 05:56:52.556354 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6878 05:56:52.559507 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6879 05:56:52.562738 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6880 05:56:52.566309 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6881 05:56:52.572882 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6882 05:56:52.576422 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6883 05:56:52.579490 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6884 05:56:52.582866 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6885 05:56:52.589609 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6886 05:56:52.593031 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6887 05:56:52.596501 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6888 05:56:52.599783 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6889 05:56:52.606148 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6890 05:56:52.609792 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6891 05:56:52.613121 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6892 05:56:52.613205 ==
6893 05:56:52.616443 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 05:56:52.619473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 05:56:52.622896 ==
6896 05:56:52.622980 DQS Delay:
6897 05:56:52.623047 DQS0 = 35, DQS1 = 43
6898 05:56:52.626292 DQM Delay:
6899 05:56:52.626376 DQM0 = 17, DQM1 = 20
6900 05:56:52.629752 DQ Delay:
6901 05:56:52.629836 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6902 05:56:52.632778 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6903 05:56:52.636489 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6904 05:56:52.639963 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6905 05:56:52.640047
6906 05:56:52.640113
6907 05:56:52.642907 ==
6908 05:56:52.646396 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 05:56:52.649707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 05:56:52.649816 ==
6911 05:56:52.649911
6912 05:56:52.650030
6913 05:56:52.652969 TX Vref Scan disable
6914 05:56:52.653053 == TX Byte 0 ==
6915 05:56:52.656217 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6916 05:56:52.662855 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6917 05:56:52.662939 == TX Byte 1 ==
6918 05:56:52.666284 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6919 05:56:52.672596 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6920 05:56:52.672679 ==
6921 05:56:52.675969 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 05:56:52.679413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 05:56:52.679558 ==
6924 05:56:52.679653
6925 05:56:52.679742
6926 05:56:52.682760 TX Vref Scan disable
6927 05:56:52.682863 == TX Byte 0 ==
6928 05:56:52.685784 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6929 05:56:52.692443 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6930 05:56:52.692550 == TX Byte 1 ==
6931 05:56:52.699390 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6932 05:56:52.702341 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6933 05:56:52.702457
6934 05:56:52.702552 [DATLAT]
6935 05:56:52.705709 Freq=400, CH1 RK1
6936 05:56:52.705808
6937 05:56:52.705898 DATLAT Default: 0xe
6938 05:56:52.709116 0, 0xFFFF, sum = 0
6939 05:56:52.709193 1, 0xFFFF, sum = 0
6940 05:56:52.712298 2, 0xFFFF, sum = 0
6941 05:56:52.712396 3, 0xFFFF, sum = 0
6942 05:56:52.715484 4, 0xFFFF, sum = 0
6943 05:56:52.715586 5, 0xFFFF, sum = 0
6944 05:56:52.718701 6, 0xFFFF, sum = 0
6945 05:56:52.718775 7, 0xFFFF, sum = 0
6946 05:56:52.722153 8, 0xFFFF, sum = 0
6947 05:56:52.722231 9, 0xFFFF, sum = 0
6948 05:56:52.725265 10, 0xFFFF, sum = 0
6949 05:56:52.728589 11, 0xFFFF, sum = 0
6950 05:56:52.728714 12, 0xFFFF, sum = 0
6951 05:56:52.732051 13, 0x0, sum = 1
6952 05:56:52.732151 14, 0x0, sum = 2
6953 05:56:52.732242 15, 0x0, sum = 3
6954 05:56:52.735593 16, 0x0, sum = 4
6955 05:56:52.735701 best_step = 14
6956 05:56:52.735791
6957 05:56:52.738951 ==
6958 05:56:52.739058 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 05:56:52.745317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 05:56:52.745431 ==
6961 05:56:52.745528 RX Vref Scan: 0
6962 05:56:52.745623
6963 05:56:52.748698 RX Vref 0 -> 0, step: 1
6964 05:56:52.748796
6965 05:56:52.752009 RX Delay -327 -> 252, step: 8
6966 05:56:52.758596 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6967 05:56:52.761599 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6968 05:56:52.765124 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6969 05:56:52.771635 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6970 05:56:52.774978 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6971 05:56:52.778528 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6972 05:56:52.781586 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6973 05:56:52.788214 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6974 05:56:52.791766 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6975 05:56:52.794965 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6976 05:56:52.797912 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6977 05:56:52.804873 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6978 05:56:52.807883 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6979 05:56:52.811376 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6980 05:56:52.814541 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6981 05:56:52.821519 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6982 05:56:52.821604 ==
6983 05:56:52.824663 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 05:56:52.827926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 05:56:52.828009 ==
6986 05:56:52.828108 DQS Delay:
6987 05:56:52.831145 DQS0 = 32, DQS1 = 36
6988 05:56:52.831252 DQM Delay:
6989 05:56:52.834256 DQM0 = 12, DQM1 = 12
6990 05:56:52.834345 DQ Delay:
6991 05:56:52.837693 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =16
6992 05:56:52.841143 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
6993 05:56:52.844323 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6994 05:56:52.847696 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6995 05:56:52.847803
6996 05:56:52.847896
6997 05:56:52.854262 [DQSOSCAuto] RK1, (LSB)MR18= 0xaa52, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6998 05:56:52.857684 CH1 RK1: MR19=C0C, MR18=AA52
6999 05:56:52.864277 CH1_RK1: MR19=0xC0C, MR18=0xAA52, DQSOSC=388, MR23=63, INC=392, DEC=261
7000 05:56:52.867596 [RxdqsGatingPostProcess] freq 400
7001 05:56:52.874125 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7002 05:56:52.877403 best DQS0 dly(2T, 0.5T) = (0, 10)
7003 05:56:52.880919 best DQS1 dly(2T, 0.5T) = (0, 10)
7004 05:56:52.884352 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7005 05:56:52.887338 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7006 05:56:52.887441 best DQS0 dly(2T, 0.5T) = (0, 10)
7007 05:56:52.891106 best DQS1 dly(2T, 0.5T) = (0, 10)
7008 05:56:52.894283 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7009 05:56:52.897703 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7010 05:56:52.900774 Pre-setting of DQS Precalculation
7011 05:56:52.907248 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7012 05:56:52.914215 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7013 05:56:52.920866 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7014 05:56:52.920974
7015 05:56:52.921066
7016 05:56:52.923912 [Calibration Summary] 800 Mbps
7017 05:56:52.924015 CH 0, Rank 0
7018 05:56:52.927569 SW Impedance : PASS
7019 05:56:52.930543 DUTY Scan : NO K
7020 05:56:52.930615 ZQ Calibration : PASS
7021 05:56:52.934086 Jitter Meter : NO K
7022 05:56:52.937244 CBT Training : PASS
7023 05:56:52.937327 Write leveling : PASS
7024 05:56:52.940668 RX DQS gating : PASS
7025 05:56:52.943907 RX DQ/DQS(RDDQC) : PASS
7026 05:56:52.943990 TX DQ/DQS : PASS
7027 05:56:52.947236 RX DATLAT : PASS
7028 05:56:52.950542 RX DQ/DQS(Engine): PASS
7029 05:56:52.950624 TX OE : NO K
7030 05:56:52.950691 All Pass.
7031 05:56:52.954061
7032 05:56:52.954143 CH 0, Rank 1
7033 05:56:52.957390 SW Impedance : PASS
7034 05:56:52.957472 DUTY Scan : NO K
7035 05:56:52.960450 ZQ Calibration : PASS
7036 05:56:52.960533 Jitter Meter : NO K
7037 05:56:52.963701 CBT Training : PASS
7038 05:56:52.967317 Write leveling : NO K
7039 05:56:52.967399 RX DQS gating : PASS
7040 05:56:52.970212 RX DQ/DQS(RDDQC) : PASS
7041 05:56:52.973805 TX DQ/DQS : PASS
7042 05:56:52.973888 RX DATLAT : PASS
7043 05:56:52.977352 RX DQ/DQS(Engine): PASS
7044 05:56:52.980217 TX OE : NO K
7045 05:56:52.980300 All Pass.
7046 05:56:52.980366
7047 05:56:52.980426 CH 1, Rank 0
7048 05:56:52.983499 SW Impedance : PASS
7049 05:56:52.986999 DUTY Scan : NO K
7050 05:56:52.987101 ZQ Calibration : PASS
7051 05:56:52.990469 Jitter Meter : NO K
7052 05:56:52.993503 CBT Training : PASS
7053 05:56:52.993591 Write leveling : PASS
7054 05:56:52.996827 RX DQS gating : PASS
7055 05:56:53.000252 RX DQ/DQS(RDDQC) : PASS
7056 05:56:53.000357 TX DQ/DQS : PASS
7057 05:56:53.003457 RX DATLAT : PASS
7058 05:56:53.006953 RX DQ/DQS(Engine): PASS
7059 05:56:53.007028 TX OE : NO K
7060 05:56:53.007102 All Pass.
7061 05:56:53.010490
7062 05:56:53.010572 CH 1, Rank 1
7063 05:56:53.013675 SW Impedance : PASS
7064 05:56:53.013775 DUTY Scan : NO K
7065 05:56:53.016760 ZQ Calibration : PASS
7066 05:56:53.016865 Jitter Meter : NO K
7067 05:56:53.020319 CBT Training : PASS
7068 05:56:53.023567 Write leveling : NO K
7069 05:56:53.023643 RX DQS gating : PASS
7070 05:56:53.026920 RX DQ/DQS(RDDQC) : PASS
7071 05:56:53.030318 TX DQ/DQS : PASS
7072 05:56:53.030419 RX DATLAT : PASS
7073 05:56:53.033254 RX DQ/DQS(Engine): PASS
7074 05:56:53.036817 TX OE : NO K
7075 05:56:53.036917 All Pass.
7076 05:56:53.037007
7077 05:56:53.039826 DramC Write-DBI off
7078 05:56:53.039927 PER_BANK_REFRESH: Hybrid Mode
7079 05:56:53.043509 TX_TRACKING: ON
7080 05:56:53.050123 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7081 05:56:53.056704 [FAST_K] Save calibration result to emmc
7082 05:56:53.059866 dramc_set_vcore_voltage set vcore to 725000
7083 05:56:53.059941 Read voltage for 1600, 0
7084 05:56:53.063210 Vio18 = 0
7085 05:56:53.063290 Vcore = 725000
7086 05:56:53.063354 Vdram = 0
7087 05:56:53.066615 Vddq = 0
7088 05:56:53.066686 Vmddr = 0
7089 05:56:53.069904 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7090 05:56:53.076525 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7091 05:56:53.079471 MEM_TYPE=3, freq_sel=13
7092 05:56:53.082995 sv_algorithm_assistance_LP4_3733
7093 05:56:53.086206 ============ PULL DRAM RESETB DOWN ============
7094 05:56:53.089718 ========== PULL DRAM RESETB DOWN end =========
7095 05:56:53.096142 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7096 05:56:53.099746 ===================================
7097 05:56:53.099820 LPDDR4 DRAM CONFIGURATION
7098 05:56:53.103079 ===================================
7099 05:56:53.106600 EX_ROW_EN[0] = 0x0
7100 05:56:53.106682 EX_ROW_EN[1] = 0x0
7101 05:56:53.109606 LP4Y_EN = 0x0
7102 05:56:53.113146 WORK_FSP = 0x1
7103 05:56:53.113229 WL = 0x5
7104 05:56:53.116259 RL = 0x5
7105 05:56:53.116342 BL = 0x2
7106 05:56:53.119707 RPST = 0x0
7107 05:56:53.119789 RD_PRE = 0x0
7108 05:56:53.122797 WR_PRE = 0x1
7109 05:56:53.122881 WR_PST = 0x1
7110 05:56:53.126274 DBI_WR = 0x0
7111 05:56:53.126366 DBI_RD = 0x0
7112 05:56:53.129645 OTF = 0x1
7113 05:56:53.132754 ===================================
7114 05:56:53.136072 ===================================
7115 05:56:53.136174 ANA top config
7116 05:56:53.139516 ===================================
7117 05:56:53.142940 DLL_ASYNC_EN = 0
7118 05:56:53.146267 ALL_SLAVE_EN = 0
7119 05:56:53.146372 NEW_RANK_MODE = 1
7120 05:56:53.149228 DLL_IDLE_MODE = 1
7121 05:56:53.152846 LP45_APHY_COMB_EN = 1
7122 05:56:53.156010 TX_ODT_DIS = 0
7123 05:56:53.159231 NEW_8X_MODE = 1
7124 05:56:53.162885 ===================================
7125 05:56:53.165841 ===================================
7126 05:56:53.165974 data_rate = 3200
7127 05:56:53.169248 CKR = 1
7128 05:56:53.172711 DQ_P2S_RATIO = 8
7129 05:56:53.176010 ===================================
7130 05:56:53.179376 CA_P2S_RATIO = 8
7131 05:56:53.182500 DQ_CA_OPEN = 0
7132 05:56:53.185807 DQ_SEMI_OPEN = 0
7133 05:56:53.185933 CA_SEMI_OPEN = 0
7134 05:56:53.189173 CA_FULL_RATE = 0
7135 05:56:53.192562 DQ_CKDIV4_EN = 0
7136 05:56:53.196140 CA_CKDIV4_EN = 0
7137 05:56:53.199078 CA_PREDIV_EN = 0
7138 05:56:53.202592 PH8_DLY = 12
7139 05:56:53.202692 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7140 05:56:53.205975 DQ_AAMCK_DIV = 4
7141 05:56:53.209192 CA_AAMCK_DIV = 4
7142 05:56:53.212598 CA_ADMCK_DIV = 4
7143 05:56:53.215601 DQ_TRACK_CA_EN = 0
7144 05:56:53.218990 CA_PICK = 1600
7145 05:56:53.222513 CA_MCKIO = 1600
7146 05:56:53.222613 MCKIO_SEMI = 0
7147 05:56:53.226009 PLL_FREQ = 3068
7148 05:56:53.229412 DQ_UI_PI_RATIO = 32
7149 05:56:53.232233 CA_UI_PI_RATIO = 0
7150 05:56:53.236062 ===================================
7151 05:56:53.239149 ===================================
7152 05:56:53.242634 memory_type:LPDDR4
7153 05:56:53.242734 GP_NUM : 10
7154 05:56:53.246087 SRAM_EN : 1
7155 05:56:53.246186 MD32_EN : 0
7156 05:56:53.249405 ===================================
7157 05:56:53.252518 [ANA_INIT] >>>>>>>>>>>>>>
7158 05:56:53.255835 <<<<<< [CONFIGURE PHASE]: ANA_TX
7159 05:56:53.259035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7160 05:56:53.262485 ===================================
7161 05:56:53.265642 data_rate = 3200,PCW = 0X7600
7162 05:56:53.269037 ===================================
7163 05:56:53.272476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7164 05:56:53.279185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7165 05:56:53.282474 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7166 05:56:53.288829 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7167 05:56:53.292328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7168 05:56:53.295677 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7169 05:56:53.295754 [ANA_INIT] flow start
7170 05:56:53.298950 [ANA_INIT] PLL >>>>>>>>
7171 05:56:53.302487 [ANA_INIT] PLL <<<<<<<<
7172 05:56:53.302557 [ANA_INIT] MIDPI >>>>>>>>
7173 05:56:53.305514 [ANA_INIT] MIDPI <<<<<<<<
7174 05:56:53.309013 [ANA_INIT] DLL >>>>>>>>
7175 05:56:53.309086 [ANA_INIT] DLL <<<<<<<<
7176 05:56:53.312436 [ANA_INIT] flow end
7177 05:56:53.315698 ============ LP4 DIFF to SE enter ============
7178 05:56:53.318861 ============ LP4 DIFF to SE exit ============
7179 05:56:53.322337 [ANA_INIT] <<<<<<<<<<<<<
7180 05:56:53.325774 [Flow] Enable top DCM control >>>>>
7181 05:56:53.329165 [Flow] Enable top DCM control <<<<<
7182 05:56:53.332233 Enable DLL master slave shuffle
7183 05:56:53.338977 ==============================================================
7184 05:56:53.339059 Gating Mode config
7185 05:56:53.345815 ==============================================================
7186 05:56:53.345905 Config description:
7187 05:56:53.355827 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7188 05:56:53.362136 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7189 05:56:53.368650 SELPH_MODE 0: By rank 1: By Phase
7190 05:56:53.372333 ==============================================================
7191 05:56:53.375753 GAT_TRACK_EN = 1
7192 05:56:53.378801 RX_GATING_MODE = 2
7193 05:56:53.382107 RX_GATING_TRACK_MODE = 2
7194 05:56:53.385278 SELPH_MODE = 1
7195 05:56:53.388852 PICG_EARLY_EN = 1
7196 05:56:53.392262 VALID_LAT_VALUE = 1
7197 05:56:53.398585 ==============================================================
7198 05:56:53.402172 Enter into Gating configuration >>>>
7199 05:56:53.405128 Exit from Gating configuration <<<<
7200 05:56:53.408575 Enter into DVFS_PRE_config >>>>>
7201 05:56:53.418609 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7202 05:56:53.422024 Exit from DVFS_PRE_config <<<<<
7203 05:56:53.425014 Enter into PICG configuration >>>>
7204 05:56:53.428376 Exit from PICG configuration <<<<
7205 05:56:53.431711 [RX_INPUT] configuration >>>>>
7206 05:56:53.431810 [RX_INPUT] configuration <<<<<
7207 05:56:53.438424 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7208 05:56:53.445203 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7209 05:56:53.448630 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7210 05:56:53.455075 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7211 05:56:53.461775 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7212 05:56:53.468448 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7213 05:56:53.471591 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7214 05:56:53.474867 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7215 05:56:53.481329 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7216 05:56:53.484731 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7217 05:56:53.487957 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7218 05:56:53.494746 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7219 05:56:53.497749 ===================================
7220 05:56:53.497821 LPDDR4 DRAM CONFIGURATION
7221 05:56:53.501168 ===================================
7222 05:56:53.504541 EX_ROW_EN[0] = 0x0
7223 05:56:53.504640 EX_ROW_EN[1] = 0x0
7224 05:56:53.508013 LP4Y_EN = 0x0
7225 05:56:53.511071 WORK_FSP = 0x1
7226 05:56:53.511167 WL = 0x5
7227 05:56:53.514499 RL = 0x5
7228 05:56:53.514569 BL = 0x2
7229 05:56:53.518078 RPST = 0x0
7230 05:56:53.518147 RD_PRE = 0x0
7231 05:56:53.520964 WR_PRE = 0x1
7232 05:56:53.521072 WR_PST = 0x1
7233 05:56:53.524379 DBI_WR = 0x0
7234 05:56:53.524510 DBI_RD = 0x0
7235 05:56:53.527995 OTF = 0x1
7236 05:56:53.530947 ===================================
7237 05:56:53.534233 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7238 05:56:53.537823 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7239 05:56:53.544222 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7240 05:56:53.547556 ===================================
7241 05:56:53.547629 LPDDR4 DRAM CONFIGURATION
7242 05:56:53.550835 ===================================
7243 05:56:53.554296 EX_ROW_EN[0] = 0x10
7244 05:56:53.554366 EX_ROW_EN[1] = 0x0
7245 05:56:53.557577 LP4Y_EN = 0x0
7246 05:56:53.560944 WORK_FSP = 0x1
7247 05:56:53.561058 WL = 0x5
7248 05:56:53.563810 RL = 0x5
7249 05:56:53.563880 BL = 0x2
7250 05:56:53.567290 RPST = 0x0
7251 05:56:53.567365 RD_PRE = 0x0
7252 05:56:53.570736 WR_PRE = 0x1
7253 05:56:53.570804 WR_PST = 0x1
7254 05:56:53.573822 DBI_WR = 0x0
7255 05:56:53.573909 DBI_RD = 0x0
7256 05:56:53.577079 OTF = 0x1
7257 05:56:53.580417 ===================================
7258 05:56:53.587407 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7259 05:56:53.587479 ==
7260 05:56:53.590548 Dram Type= 6, Freq= 0, CH_0, rank 0
7261 05:56:53.593829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7262 05:56:53.593899 ==
7263 05:56:53.597102 [Duty_Offset_Calibration]
7264 05:56:53.597170 B0:2 B1:0 CA:1
7265 05:56:53.597242
7266 05:56:53.600604 [DutyScan_Calibration_Flow] k_type=0
7267 05:56:53.610094
7268 05:56:53.610169 ==CLK 0==
7269 05:56:53.613278 Final CLK duty delay cell = -4
7270 05:56:53.616740 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7271 05:56:53.619832 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7272 05:56:53.623368 [-4] AVG Duty = 4906%(X100)
7273 05:56:53.623446
7274 05:56:53.626341 CH0 CLK Duty spec in!! Max-Min= 187%
7275 05:56:53.629828 [DutyScan_Calibration_Flow] ====Done====
7276 05:56:53.629932
7277 05:56:53.633230 [DutyScan_Calibration_Flow] k_type=1
7278 05:56:53.649805
7279 05:56:53.649911 ==DQS 0 ==
7280 05:56:53.652620 Final DQS duty delay cell = 0
7281 05:56:53.656210 [0] MAX Duty = 5249%(X100), DQS PI = 32
7282 05:56:53.659260 [0] MIN Duty = 4969%(X100), DQS PI = 0
7283 05:56:53.659362 [0] AVG Duty = 5109%(X100)
7284 05:56:53.662713
7285 05:56:53.662810 ==DQS 1 ==
7286 05:56:53.666217 Final DQS duty delay cell = -4
7287 05:56:53.669249 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7288 05:56:53.672785 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7289 05:56:53.675821 [-4] AVG Duty = 4984%(X100)
7290 05:56:53.675906
7291 05:56:53.679359 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7292 05:56:53.679444
7293 05:56:53.682636 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7294 05:56:53.686015 [DutyScan_Calibration_Flow] ====Done====
7295 05:56:53.686098
7296 05:56:53.689022 [DutyScan_Calibration_Flow] k_type=3
7297 05:56:53.707140
7298 05:56:53.707227 ==DQM 0 ==
7299 05:56:53.710315 Final DQM duty delay cell = 0
7300 05:56:53.713318 [0] MAX Duty = 5093%(X100), DQS PI = 26
7301 05:56:53.716921 [0] MIN Duty = 4813%(X100), DQS PI = 50
7302 05:56:53.720300 [0] AVG Duty = 4953%(X100)
7303 05:56:53.720375
7304 05:56:53.720438 ==DQM 1 ==
7305 05:56:53.723742 Final DQM duty delay cell = 0
7306 05:56:53.726746 [0] MAX Duty = 5249%(X100), DQS PI = 28
7307 05:56:53.730515 [0] MIN Duty = 5031%(X100), DQS PI = 6
7308 05:56:53.733652 [0] AVG Duty = 5140%(X100)
7309 05:56:53.733781
7310 05:56:53.736979 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7311 05:56:53.737054
7312 05:56:53.740394 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7313 05:56:53.743372 [DutyScan_Calibration_Flow] ====Done====
7314 05:56:53.743446
7315 05:56:53.746758 [DutyScan_Calibration_Flow] k_type=2
7316 05:56:53.763887
7317 05:56:53.763968 ==DQ 0 ==
7318 05:56:53.767471 Final DQ duty delay cell = 0
7319 05:56:53.771043 [0] MAX Duty = 5124%(X100), DQS PI = 34
7320 05:56:53.774353 [0] MIN Duty = 5000%(X100), DQS PI = 0
7321 05:56:53.774442 [0] AVG Duty = 5062%(X100)
7322 05:56:53.774510
7323 05:56:53.777271 ==DQ 1 ==
7324 05:56:53.780871 Final DQ duty delay cell = 0
7325 05:56:53.783786 [0] MAX Duty = 4969%(X100), DQS PI = 50
7326 05:56:53.787278 [0] MIN Duty = 4875%(X100), DQS PI = 10
7327 05:56:53.787363 [0] AVG Duty = 4922%(X100)
7328 05:56:53.787430
7329 05:56:53.790635 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7330 05:56:53.793934
7331 05:56:53.797493 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7332 05:56:53.800789 [DutyScan_Calibration_Flow] ====Done====
7333 05:56:53.800872 ==
7334 05:56:53.804154 Dram Type= 6, Freq= 0, CH_1, rank 0
7335 05:56:53.807250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7336 05:56:53.807333 ==
7337 05:56:53.810397 [Duty_Offset_Calibration]
7338 05:56:53.810480 B0:0 B1:-1 CA:2
7339 05:56:53.810545
7340 05:56:53.813934 [DutyScan_Calibration_Flow] k_type=0
7341 05:56:53.824169
7342 05:56:53.824253 ==CLK 0==
7343 05:56:53.827773 Final CLK duty delay cell = 0
7344 05:56:53.830788 [0] MAX Duty = 5156%(X100), DQS PI = 42
7345 05:56:53.834129 [0] MIN Duty = 4906%(X100), DQS PI = 12
7346 05:56:53.834212 [0] AVG Duty = 5031%(X100)
7347 05:56:53.837378
7348 05:56:53.840758 CH1 CLK Duty spec in!! Max-Min= 250%
7349 05:56:53.844241 [DutyScan_Calibration_Flow] ====Done====
7350 05:56:53.844324
7351 05:56:53.847260 [DutyScan_Calibration_Flow] k_type=1
7352 05:56:53.863959
7353 05:56:53.864040 ==DQS 0 ==
7354 05:56:53.867269 Final DQS duty delay cell = 0
7355 05:56:53.870758 [0] MAX Duty = 5062%(X100), DQS PI = 10
7356 05:56:53.873807 [0] MIN Duty = 5000%(X100), DQS PI = 0
7357 05:56:53.877215 [0] AVG Duty = 5031%(X100)
7358 05:56:53.877297
7359 05:56:53.877361 ==DQS 1 ==
7360 05:56:53.880746 Final DQS duty delay cell = 0
7361 05:56:53.883770 [0] MAX Duty = 5187%(X100), DQS PI = 26
7362 05:56:53.887157 [0] MIN Duty = 4844%(X100), DQS PI = 2
7363 05:56:53.887240 [0] AVG Duty = 5015%(X100)
7364 05:56:53.890578
7365 05:56:53.894133 CH1 DQS 0 Duty spec in!! Max-Min= 62%
7366 05:56:53.894215
7367 05:56:53.897006 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7368 05:56:53.900395 [DutyScan_Calibration_Flow] ====Done====
7369 05:56:53.900475
7370 05:56:53.903881 [DutyScan_Calibration_Flow] k_type=3
7371 05:56:53.920810
7372 05:56:53.920918 ==DQM 0 ==
7373 05:56:53.923972 Final DQM duty delay cell = 4
7374 05:56:53.927307 [4] MAX Duty = 5125%(X100), DQS PI = 24
7375 05:56:53.930878 [4] MIN Duty = 4969%(X100), DQS PI = 0
7376 05:56:53.930989 [4] AVG Duty = 5047%(X100)
7377 05:56:53.934211
7378 05:56:53.934292 ==DQM 1 ==
7379 05:56:53.937439 Final DQM duty delay cell = -4
7380 05:56:53.940728 [-4] MAX Duty = 4938%(X100), DQS PI = 26
7381 05:56:53.944019 [-4] MIN Duty = 4688%(X100), DQS PI = 2
7382 05:56:53.947489 [-4] AVG Duty = 4813%(X100)
7383 05:56:53.947571
7384 05:56:53.950886 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7385 05:56:53.950968
7386 05:56:53.953830 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7387 05:56:53.957328 [DutyScan_Calibration_Flow] ====Done====
7388 05:56:53.957409
7389 05:56:53.960318 [DutyScan_Calibration_Flow] k_type=2
7390 05:56:53.977968
7391 05:56:53.978049 ==DQ 0 ==
7392 05:56:53.980924 Final DQ duty delay cell = 0
7393 05:56:53.984471 [0] MAX Duty = 5093%(X100), DQS PI = 22
7394 05:56:53.987749 [0] MIN Duty = 4938%(X100), DQS PI = 0
7395 05:56:53.987831 [0] AVG Duty = 5015%(X100)
7396 05:56:53.991255
7397 05:56:53.991336 ==DQ 1 ==
7398 05:56:53.994199 Final DQ duty delay cell = 0
7399 05:56:53.997768 [0] MAX Duty = 5094%(X100), DQS PI = 34
7400 05:56:54.001277 [0] MIN Duty = 4813%(X100), DQS PI = 0
7401 05:56:54.001359 [0] AVG Duty = 4953%(X100)
7402 05:56:54.001423
7403 05:56:54.004178 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7404 05:56:54.007641
7405 05:56:54.010907 CH1 DQ 1 Duty spec in!! Max-Min= 281%
7406 05:56:54.014139 [DutyScan_Calibration_Flow] ====Done====
7407 05:56:54.017781 nWR fixed to 30
7408 05:56:54.017889 [ModeRegInit_LP4] CH0 RK0
7409 05:56:54.020977 [ModeRegInit_LP4] CH0 RK1
7410 05:56:54.024198 [ModeRegInit_LP4] CH1 RK0
7411 05:56:54.024281 [ModeRegInit_LP4] CH1 RK1
7412 05:56:54.027849 match AC timing 5
7413 05:56:54.030751 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7414 05:56:54.037517 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7415 05:56:54.040952 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7416 05:56:54.044186 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7417 05:56:54.050596 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7418 05:56:54.050678 [MiockJmeterHQA]
7419 05:56:54.050742
7420 05:56:54.054212 [DramcMiockJmeter] u1RxGatingPI = 0
7421 05:56:54.057253 0 : 4255, 4027
7422 05:56:54.057337 4 : 4253, 4027
7423 05:56:54.057404 8 : 4252, 4026
7424 05:56:54.060731 12 : 4253, 4027
7425 05:56:54.060816 16 : 4252, 4027
7426 05:56:54.064211 20 : 4253, 4026
7427 05:56:54.064314 24 : 4252, 4026
7428 05:56:54.067605 28 : 4363, 4138
7429 05:56:54.067689 32 : 4252, 4026
7430 05:56:54.070505 36 : 4252, 4027
7431 05:56:54.070589 40 : 4253, 4027
7432 05:56:54.070656 44 : 4255, 4029
7433 05:56:54.073930 48 : 4253, 4027
7434 05:56:54.074054 52 : 4363, 4138
7435 05:56:54.077466 56 : 4363, 4137
7436 05:56:54.077551 60 : 4250, 4027
7437 05:56:54.080777 64 : 4250, 4026
7438 05:56:54.080861 68 : 4250, 4027
7439 05:56:54.083777 72 : 4250, 4027
7440 05:56:54.083862 76 : 4253, 4029
7441 05:56:54.083929 80 : 4361, 4137
7442 05:56:54.087242 84 : 4250, 4026
7443 05:56:54.087357 88 : 4250, 3529
7444 05:56:54.090728 92 : 4250, 0
7445 05:56:54.090813 96 : 4361, 0
7446 05:56:54.090880 100 : 4250, 0
7447 05:56:54.094011 104 : 4249, 0
7448 05:56:54.094110 108 : 4249, 0
7449 05:56:54.097408 112 : 4250, 0
7450 05:56:54.097493 116 : 4253, 0
7451 05:56:54.097593 120 : 4361, 0
7452 05:56:54.100861 124 : 4360, 0
7453 05:56:54.100945 128 : 4363, 0
7454 05:56:54.103791 132 : 4250, 0
7455 05:56:54.103876 136 : 4361, 0
7456 05:56:54.103944 140 : 4360, 0
7457 05:56:54.107335 144 : 4250, 0
7458 05:56:54.107420 148 : 4250, 0
7459 05:56:54.107487 152 : 4250, 0
7460 05:56:54.110816 156 : 4249, 0
7461 05:56:54.110917 160 : 4250, 0
7462 05:56:54.114068 164 : 4250, 0
7463 05:56:54.114153 168 : 4252, 0
7464 05:56:54.114220 172 : 4253, 0
7465 05:56:54.117433 176 : 4249, 0
7466 05:56:54.117517 180 : 4363, 0
7467 05:56:54.120890 184 : 4250, 0
7468 05:56:54.120974 188 : 4361, 0
7469 05:56:54.121041 192 : 4360, 0
7470 05:56:54.123812 196 : 4250, 0
7471 05:56:54.123897 200 : 4250, 3
7472 05:56:54.127467 204 : 4250, 2404
7473 05:56:54.127552 208 : 4250, 4027
7474 05:56:54.127619 212 : 4361, 4137
7475 05:56:54.130553 216 : 4250, 4026
7476 05:56:54.130668 220 : 4250, 4027
7477 05:56:54.133780 224 : 4360, 4138
7478 05:56:54.133891 228 : 4250, 4027
7479 05:56:54.137211 232 : 4250, 4027
7480 05:56:54.137296 236 : 4363, 4139
7481 05:56:54.140797 240 : 4250, 4027
7482 05:56:54.140914 244 : 4250, 4027
7483 05:56:54.143721 248 : 4250, 4026
7484 05:56:54.143806 252 : 4253, 4029
7485 05:56:54.146994 256 : 4250, 4027
7486 05:56:54.147081 260 : 4250, 4027
7487 05:56:54.150258 264 : 4361, 4137
7488 05:56:54.150334 268 : 4250, 4026
7489 05:56:54.153720 272 : 4250, 4027
7490 05:56:54.153794 276 : 4360, 4138
7491 05:56:54.153858 280 : 4249, 4027
7492 05:56:54.157182 284 : 4250, 4026
7493 05:56:54.157255 288 : 4363, 4140
7494 05:56:54.160303 292 : 4250, 4027
7495 05:56:54.160375 296 : 4250, 4027
7496 05:56:54.163711 300 : 4250, 4026
7497 05:56:54.163784 304 : 4253, 4029
7498 05:56:54.167202 308 : 4250, 4027
7499 05:56:54.167276 312 : 4250, 3893
7500 05:56:54.170161 316 : 4361, 2101
7501 05:56:54.170234
7502 05:56:54.170295 MIOCK jitter meter ch=0
7503 05:56:54.170354
7504 05:56:54.173417 1T = (316-92) = 224 dly cells
7505 05:56:54.180292 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7506 05:56:54.180370 ==
7507 05:56:54.183854 Dram Type= 6, Freq= 0, CH_0, rank 0
7508 05:56:54.186717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7509 05:56:54.186795 ==
7510 05:56:54.193725 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7511 05:56:54.196740 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7512 05:56:54.200197 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7513 05:56:54.206781 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7514 05:56:54.216785 [CA 0] Center 42 (12~73) winsize 62
7515 05:56:54.219606 [CA 1] Center 43 (13~73) winsize 61
7516 05:56:54.223093 [CA 2] Center 38 (8~68) winsize 61
7517 05:56:54.226509 [CA 3] Center 37 (8~67) winsize 60
7518 05:56:54.229509 [CA 4] Center 36 (6~66) winsize 61
7519 05:56:54.232816 [CA 5] Center 35 (5~65) winsize 61
7520 05:56:54.232890
7521 05:56:54.236619 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7522 05:56:54.236694
7523 05:56:54.239751 [CATrainingPosCal] consider 1 rank data
7524 05:56:54.242804 u2DelayCellTimex100 = 290/100 ps
7525 05:56:54.249668 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7526 05:56:54.252983 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7527 05:56:54.256094 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7528 05:56:54.259282 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7529 05:56:54.262903 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7530 05:56:54.266341 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7531 05:56:54.266415
7532 05:56:54.269375 CA PerBit enable=1, Macro0, CA PI delay=35
7533 05:56:54.269447
7534 05:56:54.272755 [CBTSetCACLKResult] CA Dly = 35
7535 05:56:54.276137 CS Dly: 9 (0~40)
7536 05:56:54.279709 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7537 05:56:54.282526 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7538 05:56:54.282600 ==
7539 05:56:54.286043 Dram Type= 6, Freq= 0, CH_0, rank 1
7540 05:56:54.292375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 05:56:54.292456 ==
7542 05:56:54.295839 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7543 05:56:54.299356 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7544 05:56:54.305701 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7545 05:56:54.312697 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7546 05:56:54.319931 [CA 0] Center 43 (13~74) winsize 62
7547 05:56:54.323211 [CA 1] Center 43 (13~73) winsize 61
7548 05:56:54.326597 [CA 2] Center 38 (9~68) winsize 60
7549 05:56:54.329645 [CA 3] Center 38 (9~68) winsize 60
7550 05:56:54.333143 [CA 4] Center 37 (7~67) winsize 61
7551 05:56:54.336550 [CA 5] Center 36 (7~66) winsize 60
7552 05:56:54.336625
7553 05:56:54.339914 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7554 05:56:54.339987
7555 05:56:54.343283 [CATrainingPosCal] consider 2 rank data
7556 05:56:54.346574 u2DelayCellTimex100 = 290/100 ps
7557 05:56:54.349658 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7558 05:56:54.356515 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7559 05:56:54.359826 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7560 05:56:54.362871 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7561 05:56:54.366326 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7562 05:56:54.369596 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7563 05:56:54.369667
7564 05:56:54.373091 CA PerBit enable=1, Macro0, CA PI delay=36
7565 05:56:54.373162
7566 05:56:54.376027 [CBTSetCACLKResult] CA Dly = 36
7567 05:56:54.379357 CS Dly: 10 (0~43)
7568 05:56:54.382900 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7569 05:56:54.386190 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7570 05:56:54.386263
7571 05:56:54.389668 ----->DramcWriteLeveling(PI) begin...
7572 05:56:54.389748 ==
7573 05:56:54.392765 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 05:56:54.399550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 05:56:54.399629 ==
7576 05:56:54.402666 Write leveling (Byte 0): 36 => 36
7577 05:56:54.402743 Write leveling (Byte 1): 33 => 33
7578 05:56:54.406070 DramcWriteLeveling(PI) end<-----
7579 05:56:54.406144
7580 05:56:54.406206 ==
7581 05:56:54.409645 Dram Type= 6, Freq= 0, CH_0, rank 0
7582 05:56:54.416002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 05:56:54.416084 ==
7584 05:56:54.419133 [Gating] SW mode calibration
7585 05:56:54.425960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7586 05:56:54.429422 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7587 05:56:54.435884 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 05:56:54.439316 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 05:56:54.442813 1 4 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (1 1)
7590 05:56:54.449551 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7591 05:56:54.452676 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7592 05:56:54.456143 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7593 05:56:54.462424 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 05:56:54.466133 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 05:56:54.469273 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 05:56:54.472705 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 05:56:54.479361 1 5 8 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7598 05:56:54.482420 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7599 05:56:54.486175 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7600 05:56:54.492464 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
7601 05:56:54.495931 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 05:56:54.499314 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 05:56:54.506169 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 05:56:54.509163 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 05:56:54.512754 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7606 05:56:54.519104 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7607 05:56:54.522494 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7608 05:56:54.525862 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7609 05:56:54.532608 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 05:56:54.535950 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 05:56:54.538860 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 05:56:54.545738 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 05:56:54.549128 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 05:56:54.552177 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7615 05:56:54.558856 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7616 05:56:54.562140 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7617 05:56:54.565421 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 05:56:54.571764 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 05:56:54.575470 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 05:56:54.578579 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 05:56:54.585186 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 05:56:54.588502 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 05:56:54.591881 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 05:56:54.598823 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 05:56:54.601765 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 05:56:54.605146 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 05:56:54.611744 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 05:56:54.615325 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 05:56:54.618658 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7630 05:56:54.622078 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7631 05:56:54.628408 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7632 05:56:54.631898 Total UI for P1: 0, mck2ui 16
7633 05:56:54.635370 best dqsien dly found for B0: ( 1, 9, 10)
7634 05:56:54.638750 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7635 05:56:54.641715 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 05:56:54.645253 Total UI for P1: 0, mck2ui 16
7637 05:56:54.648243 best dqsien dly found for B1: ( 1, 9, 20)
7638 05:56:54.651523 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7639 05:56:54.658455 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7640 05:56:54.658541
7641 05:56:54.661623 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7642 05:56:54.664829 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7643 05:56:54.668267 [Gating] SW calibration Done
7644 05:56:54.668355 ==
7645 05:56:54.671687 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 05:56:54.674972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 05:56:54.675057 ==
7648 05:56:54.678015 RX Vref Scan: 0
7649 05:56:54.678099
7650 05:56:54.678190 RX Vref 0 -> 0, step: 1
7651 05:56:54.678269
7652 05:56:54.681734 RX Delay 0 -> 252, step: 8
7653 05:56:54.684787 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7654 05:56:54.688353 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7655 05:56:54.694958 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7656 05:56:54.698243 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7657 05:56:54.701802 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7658 05:56:54.705304 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7659 05:56:54.708072 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7660 05:56:54.711591 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7661 05:56:54.718298 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7662 05:56:54.721724 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7663 05:56:54.724641 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7664 05:56:54.728248 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7665 05:56:54.734789 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7666 05:56:54.738153 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7667 05:56:54.741427 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7668 05:56:54.744930 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7669 05:56:54.745031 ==
7670 05:56:54.747897 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 05:56:54.751361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 05:56:54.754682 ==
7673 05:56:54.754760 DQS Delay:
7674 05:56:54.754826 DQS0 = 0, DQS1 = 0
7675 05:56:54.758076 DQM Delay:
7676 05:56:54.758178 DQM0 = 138, DQM1 = 126
7677 05:56:54.761692 DQ Delay:
7678 05:56:54.764858 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7679 05:56:54.768167 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7680 05:56:54.771188 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7681 05:56:54.774170 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7682 05:56:54.774272
7683 05:56:54.774364
7684 05:56:54.774458 ==
7685 05:56:54.777591 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 05:56:54.781026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 05:56:54.781107 ==
7688 05:56:54.784489
7689 05:56:54.784573
7690 05:56:54.784638 TX Vref Scan disable
7691 05:56:54.787648 == TX Byte 0 ==
7692 05:56:54.791026 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7693 05:56:54.794388 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7694 05:56:54.797530 == TX Byte 1 ==
7695 05:56:54.801340 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7696 05:56:54.804196 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7697 05:56:54.807578 ==
7698 05:56:54.807693 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 05:56:54.814212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 05:56:54.814299 ==
7701 05:56:54.825801
7702 05:56:54.829190 TX Vref early break, caculate TX vref
7703 05:56:54.832698 TX Vref=16, minBit 7, minWin=22, winSum=375
7704 05:56:54.835797 TX Vref=18, minBit 6, minWin=23, winSum=387
7705 05:56:54.839293 TX Vref=20, minBit 0, minWin=24, winSum=393
7706 05:56:54.842721 TX Vref=22, minBit 1, minWin=24, winSum=408
7707 05:56:54.846075 TX Vref=24, minBit 1, minWin=25, winSum=413
7708 05:56:54.852701 TX Vref=26, minBit 0, minWin=25, winSum=425
7709 05:56:54.856181 TX Vref=28, minBit 2, minWin=26, winSum=432
7710 05:56:54.859544 TX Vref=30, minBit 2, minWin=25, winSum=421
7711 05:56:54.862802 TX Vref=32, minBit 2, minWin=24, winSum=410
7712 05:56:54.865768 TX Vref=34, minBit 0, minWin=25, winSum=406
7713 05:56:54.872414 [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 28
7714 05:56:54.872485
7715 05:56:54.875899 Final TX Range 0 Vref 28
7716 05:56:54.875966
7717 05:56:54.876026 ==
7718 05:56:54.879429 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 05:56:54.882360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 05:56:54.882431 ==
7721 05:56:54.882491
7722 05:56:54.882549
7723 05:56:54.885896 TX Vref Scan disable
7724 05:56:54.892390 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7725 05:56:54.892504 == TX Byte 0 ==
7726 05:56:54.895773 u2DelayCellOfst[0]=13 cells (4 PI)
7727 05:56:54.898827 u2DelayCellOfst[1]=16 cells (5 PI)
7728 05:56:54.902529 u2DelayCellOfst[2]=10 cells (3 PI)
7729 05:56:54.906028 u2DelayCellOfst[3]=13 cells (4 PI)
7730 05:56:54.909016 u2DelayCellOfst[4]=6 cells (2 PI)
7731 05:56:54.912442 u2DelayCellOfst[5]=0 cells (0 PI)
7732 05:56:54.915750 u2DelayCellOfst[6]=16 cells (5 PI)
7733 05:56:54.918780 u2DelayCellOfst[7]=13 cells (4 PI)
7734 05:56:54.922255 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7735 05:56:54.925344 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7736 05:56:54.929097 == TX Byte 1 ==
7737 05:56:54.929194 u2DelayCellOfst[8]=0 cells (0 PI)
7738 05:56:54.932452 u2DelayCellOfst[9]=0 cells (0 PI)
7739 05:56:54.935906 u2DelayCellOfst[10]=6 cells (2 PI)
7740 05:56:54.938874 u2DelayCellOfst[11]=3 cells (1 PI)
7741 05:56:54.942336 u2DelayCellOfst[12]=13 cells (4 PI)
7742 05:56:54.945751 u2DelayCellOfst[13]=13 cells (4 PI)
7743 05:56:54.948971 u2DelayCellOfst[14]=16 cells (5 PI)
7744 05:56:54.952456 u2DelayCellOfst[15]=10 cells (3 PI)
7745 05:56:54.955517 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7746 05:56:54.962174 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7747 05:56:54.962244 DramC Write-DBI on
7748 05:56:54.962317 ==
7749 05:56:54.965499 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 05:56:54.968990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 05:56:54.969086 ==
7752 05:56:54.971937
7753 05:56:54.972005
7754 05:56:54.972064 TX Vref Scan disable
7755 05:56:54.975594 == TX Byte 0 ==
7756 05:56:54.978931 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7757 05:56:54.981952 == TX Byte 1 ==
7758 05:56:54.985449 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7759 05:56:54.985544 DramC Write-DBI off
7760 05:56:54.988823
7761 05:56:54.988894 [DATLAT]
7762 05:56:54.988955 Freq=1600, CH0 RK0
7763 05:56:54.989014
7764 05:56:54.992190 DATLAT Default: 0xf
7765 05:56:54.992286 0, 0xFFFF, sum = 0
7766 05:56:54.995537 1, 0xFFFF, sum = 0
7767 05:56:54.995633 2, 0xFFFF, sum = 0
7768 05:56:54.998737 3, 0xFFFF, sum = 0
7769 05:56:55.002139 4, 0xFFFF, sum = 0
7770 05:56:55.002236 5, 0xFFFF, sum = 0
7771 05:56:55.005237 6, 0xFFFF, sum = 0
7772 05:56:55.005329 7, 0xFFFF, sum = 0
7773 05:56:55.008762 8, 0xFFFF, sum = 0
7774 05:56:55.008854 9, 0xFFFF, sum = 0
7775 05:56:55.012286 10, 0xFFFF, sum = 0
7776 05:56:55.012398 11, 0xFFFF, sum = 0
7777 05:56:55.015193 12, 0xFFFF, sum = 0
7778 05:56:55.015290 13, 0xFFFF, sum = 0
7779 05:56:55.018547 14, 0x0, sum = 1
7780 05:56:55.018617 15, 0x0, sum = 2
7781 05:56:55.022005 16, 0x0, sum = 3
7782 05:56:55.022077 17, 0x0, sum = 4
7783 05:56:55.025324 best_step = 15
7784 05:56:55.025424
7785 05:56:55.025518 ==
7786 05:56:55.028683 Dram Type= 6, Freq= 0, CH_0, rank 0
7787 05:56:55.031629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7788 05:56:55.031727 ==
7789 05:56:55.035125 RX Vref Scan: 1
7790 05:56:55.035195
7791 05:56:55.035256 Set Vref Range= 24 -> 127
7792 05:56:55.035318
7793 05:56:55.038674 RX Vref 24 -> 127, step: 1
7794 05:56:55.038741
7795 05:56:55.041625 RX Delay 19 -> 252, step: 4
7796 05:56:55.041690
7797 05:56:55.045055 Set Vref, RX VrefLevel [Byte0]: 24
7798 05:56:55.048518 [Byte1]: 24
7799 05:56:55.048585
7800 05:56:55.051817 Set Vref, RX VrefLevel [Byte0]: 25
7801 05:56:55.055218 [Byte1]: 25
7802 05:56:55.055285
7803 05:56:55.058733 Set Vref, RX VrefLevel [Byte0]: 26
7804 05:56:55.061730 [Byte1]: 26
7805 05:56:55.065588
7806 05:56:55.065654 Set Vref, RX VrefLevel [Byte0]: 27
7807 05:56:55.068790 [Byte1]: 27
7808 05:56:55.073124
7809 05:56:55.073190 Set Vref, RX VrefLevel [Byte0]: 28
7810 05:56:55.076609 [Byte1]: 28
7811 05:56:55.080832
7812 05:56:55.080927 Set Vref, RX VrefLevel [Byte0]: 29
7813 05:56:55.084130 [Byte1]: 29
7814 05:56:55.088213
7815 05:56:55.088298 Set Vref, RX VrefLevel [Byte0]: 30
7816 05:56:55.091583 [Byte1]: 30
7817 05:56:55.095757
7818 05:56:55.095865 Set Vref, RX VrefLevel [Byte0]: 31
7819 05:56:55.099208 [Byte1]: 31
7820 05:56:55.103429
7821 05:56:55.103525 Set Vref, RX VrefLevel [Byte0]: 32
7822 05:56:55.106839 [Byte1]: 32
7823 05:56:55.111101
7824 05:56:55.111174 Set Vref, RX VrefLevel [Byte0]: 33
7825 05:56:55.114559 [Byte1]: 33
7826 05:56:55.118691
7827 05:56:55.118788 Set Vref, RX VrefLevel [Byte0]: 34
7828 05:56:55.121990 [Byte1]: 34
7829 05:56:55.126069
7830 05:56:55.126147 Set Vref, RX VrefLevel [Byte0]: 35
7831 05:56:55.129564 [Byte1]: 35
7832 05:56:55.133862
7833 05:56:55.133932 Set Vref, RX VrefLevel [Byte0]: 36
7834 05:56:55.137370 [Byte1]: 36
7835 05:56:55.141412
7836 05:56:55.141483 Set Vref, RX VrefLevel [Byte0]: 37
7837 05:56:55.144718 [Byte1]: 37
7838 05:56:55.148689
7839 05:56:55.148761 Set Vref, RX VrefLevel [Byte0]: 38
7840 05:56:55.152271 [Byte1]: 38
7841 05:56:55.156346
7842 05:56:55.156416 Set Vref, RX VrefLevel [Byte0]: 39
7843 05:56:55.159662 [Byte1]: 39
7844 05:56:55.164318
7845 05:56:55.164388 Set Vref, RX VrefLevel [Byte0]: 40
7846 05:56:55.167189 [Byte1]: 40
7847 05:56:55.171534
7848 05:56:55.171601 Set Vref, RX VrefLevel [Byte0]: 41
7849 05:56:55.175132 [Byte1]: 41
7850 05:56:55.179203
7851 05:56:55.179273 Set Vref, RX VrefLevel [Byte0]: 42
7852 05:56:55.182499 [Byte1]: 42
7853 05:56:55.186734
7854 05:56:55.186803 Set Vref, RX VrefLevel [Byte0]: 43
7855 05:56:55.190161 [Byte1]: 43
7856 05:56:55.194141
7857 05:56:55.194238 Set Vref, RX VrefLevel [Byte0]: 44
7858 05:56:55.197657 [Byte1]: 44
7859 05:56:55.202122
7860 05:56:55.202218 Set Vref, RX VrefLevel [Byte0]: 45
7861 05:56:55.204969 [Byte1]: 45
7862 05:56:55.209359
7863 05:56:55.209457 Set Vref, RX VrefLevel [Byte0]: 46
7864 05:56:55.212654 [Byte1]: 46
7865 05:56:55.217120
7866 05:56:55.217222 Set Vref, RX VrefLevel [Byte0]: 47
7867 05:56:55.220379 [Byte1]: 47
7868 05:56:55.224620
7869 05:56:55.224699 Set Vref, RX VrefLevel [Byte0]: 48
7870 05:56:55.227738 [Byte1]: 48
7871 05:56:55.232085
7872 05:56:55.232159 Set Vref, RX VrefLevel [Byte0]: 49
7873 05:56:55.235560 [Byte1]: 49
7874 05:56:55.239981
7875 05:56:55.240059 Set Vref, RX VrefLevel [Byte0]: 50
7876 05:56:55.243019 [Byte1]: 50
7877 05:56:55.247607
7878 05:56:55.247677 Set Vref, RX VrefLevel [Byte0]: 51
7879 05:56:55.250567 [Byte1]: 51
7880 05:56:55.255117
7881 05:56:55.255187 Set Vref, RX VrefLevel [Byte0]: 52
7882 05:56:55.258113 [Byte1]: 52
7883 05:56:55.262293
7884 05:56:55.262361 Set Vref, RX VrefLevel [Byte0]: 53
7885 05:56:55.268785 [Byte1]: 53
7886 05:56:55.268855
7887 05:56:55.272255 Set Vref, RX VrefLevel [Byte0]: 54
7888 05:56:55.275651 [Byte1]: 54
7889 05:56:55.275719
7890 05:56:55.278889 Set Vref, RX VrefLevel [Byte0]: 55
7891 05:56:55.282251 [Byte1]: 55
7892 05:56:55.282320
7893 05:56:55.285772 Set Vref, RX VrefLevel [Byte0]: 56
7894 05:56:55.289042 [Byte1]: 56
7895 05:56:55.292806
7896 05:56:55.292902 Set Vref, RX VrefLevel [Byte0]: 57
7897 05:56:55.296252 [Byte1]: 57
7898 05:56:55.300283
7899 05:56:55.300382 Set Vref, RX VrefLevel [Byte0]: 58
7900 05:56:55.303878 [Byte1]: 58
7901 05:56:55.308171
7902 05:56:55.308268 Set Vref, RX VrefLevel [Byte0]: 59
7903 05:56:55.311522 [Byte1]: 59
7904 05:56:55.315441
7905 05:56:55.315510 Set Vref, RX VrefLevel [Byte0]: 60
7906 05:56:55.318702 [Byte1]: 60
7907 05:56:55.323436
7908 05:56:55.323537 Set Vref, RX VrefLevel [Byte0]: 61
7909 05:56:55.326773 [Byte1]: 61
7910 05:56:55.330799
7911 05:56:55.330875 Set Vref, RX VrefLevel [Byte0]: 62
7912 05:56:55.334074 [Byte1]: 62
7913 05:56:55.338365
7914 05:56:55.338435 Set Vref, RX VrefLevel [Byte0]: 63
7915 05:56:55.341576 [Byte1]: 63
7916 05:56:55.345635
7917 05:56:55.345702 Set Vref, RX VrefLevel [Byte0]: 64
7918 05:56:55.349167 [Byte1]: 64
7919 05:56:55.353329
7920 05:56:55.353396 Set Vref, RX VrefLevel [Byte0]: 65
7921 05:56:55.356759 [Byte1]: 65
7922 05:56:55.361208
7923 05:56:55.361274 Set Vref, RX VrefLevel [Byte0]: 66
7924 05:56:55.364443 [Byte1]: 66
7925 05:56:55.368439
7926 05:56:55.368505 Set Vref, RX VrefLevel [Byte0]: 67
7927 05:56:55.371900 [Byte1]: 67
7928 05:56:55.376353
7929 05:56:55.376449 Set Vref, RX VrefLevel [Byte0]: 68
7930 05:56:55.379397 [Byte1]: 68
7931 05:56:55.383656
7932 05:56:55.383727 Set Vref, RX VrefLevel [Byte0]: 69
7933 05:56:55.387136 [Byte1]: 69
7934 05:56:55.391553
7935 05:56:55.391652 Set Vref, RX VrefLevel [Byte0]: 70
7936 05:56:55.394743 [Byte1]: 70
7937 05:56:55.398694
7938 05:56:55.398764 Set Vref, RX VrefLevel [Byte0]: 71
7939 05:56:55.402269 [Byte1]: 71
7940 05:56:55.406652
7941 05:56:55.406750 Set Vref, RX VrefLevel [Byte0]: 72
7942 05:56:55.409760 [Byte1]: 72
7943 05:56:55.414013
7944 05:56:55.414087 Set Vref, RX VrefLevel [Byte0]: 73
7945 05:56:55.417331 [Byte1]: 73
7946 05:56:55.421876
7947 05:56:55.421994 Set Vref, RX VrefLevel [Byte0]: 74
7948 05:56:55.424629 [Byte1]: 74
7949 05:56:55.429114
7950 05:56:55.429225 Set Vref, RX VrefLevel [Byte0]: 75
7951 05:56:55.432348 [Byte1]: 75
7952 05:56:55.436995
7953 05:56:55.437099 Set Vref, RX VrefLevel [Byte0]: 76
7954 05:56:55.439876 [Byte1]: 76
7955 05:56:55.444454
7956 05:56:55.444556 Set Vref, RX VrefLevel [Byte0]: 77
7957 05:56:55.447764 [Byte1]: 77
7958 05:56:55.452134
7959 05:56:55.452217 Set Vref, RX VrefLevel [Byte0]: 78
7960 05:56:55.455238 [Byte1]: 78
7961 05:56:55.459505
7962 05:56:55.459587 Set Vref, RX VrefLevel [Byte0]: 79
7963 05:56:55.462440 [Byte1]: 79
7964 05:56:55.466763
7965 05:56:55.466917 Final RX Vref Byte 0 = 60 to rank0
7966 05:56:55.470156 Final RX Vref Byte 1 = 61 to rank0
7967 05:56:55.473538 Final RX Vref Byte 0 = 60 to rank1
7968 05:56:55.476964 Final RX Vref Byte 1 = 61 to rank1==
7969 05:56:55.480347 Dram Type= 6, Freq= 0, CH_0, rank 0
7970 05:56:55.486922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7971 05:56:55.487008 ==
7972 05:56:55.487075 DQS Delay:
7973 05:56:55.487135 DQS0 = 0, DQS1 = 0
7974 05:56:55.490385 DQM Delay:
7975 05:56:55.490467 DQM0 = 135, DQM1 = 124
7976 05:56:55.493491 DQ Delay:
7977 05:56:55.496762 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7978 05:56:55.500578 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =144
7979 05:56:55.503472 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7980 05:56:55.507006 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
7981 05:56:55.507090
7982 05:56:55.507156
7983 05:56:55.507217
7984 05:56:55.510541 [DramC_TX_OE_Calibration] TA2
7985 05:56:55.513497 Original DQ_B0 (3 6) =30, OEN = 27
7986 05:56:55.516784 Original DQ_B1 (3 6) =30, OEN = 27
7987 05:56:55.520314 24, 0x0, End_B0=24 End_B1=24
7988 05:56:55.520400 25, 0x0, End_B0=25 End_B1=25
7989 05:56:55.523297 26, 0x0, End_B0=26 End_B1=26
7990 05:56:55.526761 27, 0x0, End_B0=27 End_B1=27
7991 05:56:55.530559 28, 0x0, End_B0=28 End_B1=28
7992 05:56:55.530643 29, 0x0, End_B0=29 End_B1=29
7993 05:56:55.533392 30, 0x0, End_B0=30 End_B1=30
7994 05:56:55.536917 31, 0x4141, End_B0=30 End_B1=30
7995 05:56:55.540309 Byte0 end_step=30 best_step=27
7996 05:56:55.543802 Byte1 end_step=30 best_step=27
7997 05:56:55.547044 Byte0 TX OE(2T, 0.5T) = (3, 3)
7998 05:56:55.547157 Byte1 TX OE(2T, 0.5T) = (3, 3)
7999 05:56:55.549858
8000 05:56:55.549981
8001 05:56:55.556625 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8002 05:56:55.559836 CH0 RK0: MR19=303, MR18=1E1C
8003 05:56:55.566742 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
8004 05:56:55.566858
8005 05:56:55.569767 ----->DramcWriteLeveling(PI) begin...
8006 05:56:55.569852 ==
8007 05:56:55.573053 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 05:56:55.576511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 05:56:55.576596 ==
8010 05:56:55.579822 Write leveling (Byte 0): 39 => 39
8011 05:56:55.583321 Write leveling (Byte 1): 30 => 30
8012 05:56:55.586830 DramcWriteLeveling(PI) end<-----
8013 05:56:55.586915
8014 05:56:55.586980 ==
8015 05:56:55.590058 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 05:56:55.593452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 05:56:55.593566 ==
8018 05:56:55.596335 [Gating] SW mode calibration
8019 05:56:55.603050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8020 05:56:55.609893 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8021 05:56:55.612969 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 05:56:55.616487 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 05:56:55.623206 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 05:56:55.626375 1 4 12 | B1->B0 | 2524 3131 | 1 0 | (1 1) (0 0)
8025 05:56:55.629435 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 05:56:55.636121 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 05:56:55.639431 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 05:56:55.642806 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 05:56:55.649787 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 05:56:55.652793 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8031 05:56:55.656509 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8032 05:56:55.662786 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
8033 05:56:55.666039 1 5 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
8034 05:56:55.669478 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8035 05:56:55.676291 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 05:56:55.679270 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 05:56:55.682682 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 05:56:55.689088 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 05:56:55.692554 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8040 05:56:55.695939 1 6 12 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8041 05:56:55.702835 1 6 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8042 05:56:55.706144 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 05:56:55.709460 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 05:56:55.716007 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 05:56:55.719058 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 05:56:55.722436 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 05:56:55.729363 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 05:56:55.732434 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8049 05:56:55.735750 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8050 05:56:55.742250 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 05:56:55.745756 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 05:56:55.749196 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 05:56:55.755792 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 05:56:55.759071 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 05:56:55.762394 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 05:56:55.768722 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 05:56:55.772447 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 05:56:55.775463 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 05:56:55.778782 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 05:56:55.785635 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 05:56:55.789025 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 05:56:55.792082 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 05:56:55.798928 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 05:56:55.802172 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8065 05:56:55.805153 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8066 05:56:55.808548 Total UI for P1: 0, mck2ui 16
8067 05:56:55.811857 best dqsien dly found for B0: ( 1, 9, 12)
8068 05:56:55.818740 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 05:56:55.821686 Total UI for P1: 0, mck2ui 16
8070 05:56:55.825173 best dqsien dly found for B1: ( 1, 9, 14)
8071 05:56:55.828839 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8072 05:56:55.832085 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8073 05:56:55.832168
8074 05:56:55.835273 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8075 05:56:55.838639 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8076 05:56:55.841773 [Gating] SW calibration Done
8077 05:56:55.841860 ==
8078 05:56:55.845382 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 05:56:55.848765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 05:56:55.848869 ==
8081 05:56:55.852155 RX Vref Scan: 0
8082 05:56:55.852266
8083 05:56:55.852356 RX Vref 0 -> 0, step: 1
8084 05:56:55.855117
8085 05:56:55.855189 RX Delay 0 -> 252, step: 8
8086 05:56:55.858513 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8087 05:56:55.865038 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8088 05:56:55.868826 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8089 05:56:55.871738 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8090 05:56:55.875315 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8091 05:56:55.878539 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8092 05:56:55.885257 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8093 05:56:55.888644 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8094 05:56:55.891633 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8095 05:56:55.894879 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8096 05:56:55.898408 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8097 05:56:55.905023 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8098 05:56:55.908478 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8099 05:56:55.911557 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8100 05:56:55.914728 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8101 05:56:55.921666 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8102 05:56:55.921739 ==
8103 05:56:55.925214 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 05:56:55.928163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 05:56:55.928240 ==
8106 05:56:55.928302 DQS Delay:
8107 05:56:55.931778 DQS0 = 0, DQS1 = 0
8108 05:56:55.931849 DQM Delay:
8109 05:56:55.934945 DQM0 = 136, DQM1 = 125
8110 05:56:55.935017 DQ Delay:
8111 05:56:55.938221 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8112 05:56:55.941612 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8113 05:56:55.945154 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8114 05:56:55.948011 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8115 05:56:55.948109
8116 05:56:55.948197
8117 05:56:55.951741 ==
8118 05:56:55.951816 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 05:56:55.958116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 05:56:55.958196 ==
8121 05:56:55.958259
8122 05:56:55.958317
8123 05:56:55.961575 TX Vref Scan disable
8124 05:56:55.961643 == TX Byte 0 ==
8125 05:56:55.965069 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8126 05:56:55.971418 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8127 05:56:55.971514 == TX Byte 1 ==
8128 05:56:55.974641 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8129 05:56:55.981415 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8130 05:56:55.981515 ==
8131 05:56:55.984923 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 05:56:55.988078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 05:56:55.988152 ==
8134 05:56:56.003200
8135 05:56:56.006574 TX Vref early break, caculate TX vref
8136 05:56:56.009709 TX Vref=16, minBit 0, minWin=23, winSum=388
8137 05:56:56.013299 TX Vref=18, minBit 0, minWin=23, winSum=398
8138 05:56:56.016696 TX Vref=20, minBit 8, minWin=24, winSum=409
8139 05:56:56.020007 TX Vref=22, minBit 8, minWin=24, winSum=413
8140 05:56:56.022893 TX Vref=24, minBit 0, minWin=25, winSum=425
8141 05:56:56.029721 TX Vref=26, minBit 0, minWin=26, winSum=431
8142 05:56:56.033242 TX Vref=28, minBit 0, minWin=26, winSum=434
8143 05:56:56.036437 TX Vref=30, minBit 0, minWin=26, winSum=427
8144 05:56:56.039993 TX Vref=32, minBit 8, minWin=25, winSum=420
8145 05:56:56.043279 TX Vref=34, minBit 0, minWin=25, winSum=413
8146 05:56:56.046502 TX Vref=36, minBit 2, minWin=24, winSum=400
8147 05:56:56.053226 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 28
8148 05:56:56.053302
8149 05:56:56.056493 Final TX Range 0 Vref 28
8150 05:56:56.056564
8151 05:56:56.056625 ==
8152 05:56:56.059597 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 05:56:56.063038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 05:56:56.063128 ==
8155 05:56:56.063218
8156 05:56:56.063305
8157 05:56:56.066098 TX Vref Scan disable
8158 05:56:56.073170 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8159 05:56:56.073244 == TX Byte 0 ==
8160 05:56:56.076112 u2DelayCellOfst[0]=13 cells (4 PI)
8161 05:56:56.079684 u2DelayCellOfst[1]=20 cells (6 PI)
8162 05:56:56.082961 u2DelayCellOfst[2]=13 cells (4 PI)
8163 05:56:56.086135 u2DelayCellOfst[3]=13 cells (4 PI)
8164 05:56:56.089699 u2DelayCellOfst[4]=10 cells (3 PI)
8165 05:56:56.093132 u2DelayCellOfst[5]=0 cells (0 PI)
8166 05:56:56.096277 u2DelayCellOfst[6]=20 cells (6 PI)
8167 05:56:56.099710 u2DelayCellOfst[7]=20 cells (6 PI)
8168 05:56:56.102725 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8169 05:56:56.106185 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8170 05:56:56.109537 == TX Byte 1 ==
8171 05:56:56.112794 u2DelayCellOfst[8]=3 cells (1 PI)
8172 05:56:56.116190 u2DelayCellOfst[9]=0 cells (0 PI)
8173 05:56:56.116308 u2DelayCellOfst[10]=6 cells (2 PI)
8174 05:56:56.119681 u2DelayCellOfst[11]=3 cells (1 PI)
8175 05:56:56.122969 u2DelayCellOfst[12]=13 cells (4 PI)
8176 05:56:56.125876 u2DelayCellOfst[13]=13 cells (4 PI)
8177 05:56:56.129301 u2DelayCellOfst[14]=16 cells (5 PI)
8178 05:56:56.132865 u2DelayCellOfst[15]=10 cells (3 PI)
8179 05:56:56.139172 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8180 05:56:56.142592 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8181 05:56:56.142676 DramC Write-DBI on
8182 05:56:56.142742 ==
8183 05:56:56.145947 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 05:56:56.152625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 05:56:56.152710 ==
8186 05:56:56.152776
8187 05:56:56.152837
8188 05:56:56.152896 TX Vref Scan disable
8189 05:56:56.156588 == TX Byte 0 ==
8190 05:56:56.159953 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8191 05:56:56.163211 == TX Byte 1 ==
8192 05:56:56.166684 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8193 05:56:56.170150 DramC Write-DBI off
8194 05:56:56.170233
8195 05:56:56.170299 [DATLAT]
8196 05:56:56.170361 Freq=1600, CH0 RK1
8197 05:56:56.170422
8198 05:56:56.173511 DATLAT Default: 0xf
8199 05:56:56.173637 0, 0xFFFF, sum = 0
8200 05:56:56.176562 1, 0xFFFF, sum = 0
8201 05:56:56.179978 2, 0xFFFF, sum = 0
8202 05:56:56.180063 3, 0xFFFF, sum = 0
8203 05:56:56.183039 4, 0xFFFF, sum = 0
8204 05:56:56.183124 5, 0xFFFF, sum = 0
8205 05:56:56.186519 6, 0xFFFF, sum = 0
8206 05:56:56.186617 7, 0xFFFF, sum = 0
8207 05:56:56.189702 8, 0xFFFF, sum = 0
8208 05:56:56.189829 9, 0xFFFF, sum = 0
8209 05:56:56.193057 10, 0xFFFF, sum = 0
8210 05:56:56.193174 11, 0xFFFF, sum = 0
8211 05:56:56.196231 12, 0xFFFF, sum = 0
8212 05:56:56.196316 13, 0xFFFF, sum = 0
8213 05:56:56.200017 14, 0x0, sum = 1
8214 05:56:56.200101 15, 0x0, sum = 2
8215 05:56:56.202944 16, 0x0, sum = 3
8216 05:56:56.203028 17, 0x0, sum = 4
8217 05:56:56.206478 best_step = 15
8218 05:56:56.206560
8219 05:56:56.206626 ==
8220 05:56:56.209356 Dram Type= 6, Freq= 0, CH_0, rank 1
8221 05:56:56.212920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8222 05:56:56.213003 ==
8223 05:56:56.216281 RX Vref Scan: 0
8224 05:56:56.216379
8225 05:56:56.216445 RX Vref 0 -> 0, step: 1
8226 05:56:56.216507
8227 05:56:56.219574 RX Delay 11 -> 252, step: 4
8228 05:56:56.225792 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8229 05:56:56.229253 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8230 05:56:56.232726 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8231 05:56:56.236188 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8232 05:56:56.239725 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8233 05:56:56.242603 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8234 05:56:56.249539 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8235 05:56:56.252461 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8236 05:56:56.256080 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8237 05:56:56.259011 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8238 05:56:56.262481 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8239 05:56:56.269254 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8240 05:56:56.272356 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8241 05:56:56.275731 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8242 05:56:56.279155 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8243 05:56:56.285554 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8244 05:56:56.285638 ==
8245 05:56:56.289117 Dram Type= 6, Freq= 0, CH_0, rank 1
8246 05:56:56.292359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8247 05:56:56.292443 ==
8248 05:56:56.292510 DQS Delay:
8249 05:56:56.295386 DQS0 = 0, DQS1 = 0
8250 05:56:56.295497 DQM Delay:
8251 05:56:56.299016 DQM0 = 133, DQM1 = 123
8252 05:56:56.299132 DQ Delay:
8253 05:56:56.302149 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8254 05:56:56.306047 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8255 05:56:56.309204 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8256 05:56:56.312111 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8257 05:56:56.312191
8258 05:56:56.312256
8259 05:56:56.315615
8260 05:56:56.315688 [DramC_TX_OE_Calibration] TA2
8261 05:56:56.319043 Original DQ_B0 (3 6) =30, OEN = 27
8262 05:56:56.322282 Original DQ_B1 (3 6) =30, OEN = 27
8263 05:56:56.325285 24, 0x0, End_B0=24 End_B1=24
8264 05:56:56.328644 25, 0x0, End_B0=25 End_B1=25
8265 05:56:56.332032 26, 0x0, End_B0=26 End_B1=26
8266 05:56:56.332115 27, 0x0, End_B0=27 End_B1=27
8267 05:56:56.335547 28, 0x0, End_B0=28 End_B1=28
8268 05:56:56.339034 29, 0x0, End_B0=29 End_B1=29
8269 05:56:56.341915 30, 0x0, End_B0=30 End_B1=30
8270 05:56:56.345414 31, 0x4545, End_B0=30 End_B1=30
8271 05:56:56.345493 Byte0 end_step=30 best_step=27
8272 05:56:56.348772 Byte1 end_step=30 best_step=27
8273 05:56:56.351777 Byte0 TX OE(2T, 0.5T) = (3, 3)
8274 05:56:56.355136 Byte1 TX OE(2T, 0.5T) = (3, 3)
8275 05:56:56.355218
8276 05:56:56.355321
8277 05:56:56.362075 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
8278 05:56:56.365525 CH0 RK1: MR19=303, MR18=1F0C
8279 05:56:56.372086 CH0_RK1: MR19=0x303, MR18=0x1F0C, DQSOSC=394, MR23=63, INC=23, DEC=15
8280 05:56:56.375175 [RxdqsGatingPostProcess] freq 1600
8281 05:56:56.382134 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8282 05:56:56.385105 best DQS0 dly(2T, 0.5T) = (1, 1)
8283 05:56:56.385180 best DQS1 dly(2T, 0.5T) = (1, 1)
8284 05:56:56.388582 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8285 05:56:56.391971 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8286 05:56:56.395494 best DQS0 dly(2T, 0.5T) = (1, 1)
8287 05:56:56.398656 best DQS1 dly(2T, 0.5T) = (1, 1)
8288 05:56:56.401786 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8289 05:56:56.405385 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8290 05:56:56.408539 Pre-setting of DQS Precalculation
8291 05:56:56.411679 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8292 05:56:56.415360 ==
8293 05:56:56.415469 Dram Type= 6, Freq= 0, CH_1, rank 0
8294 05:56:56.421703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 05:56:56.421786 ==
8296 05:56:56.425039 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8297 05:56:56.432026 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8298 05:56:56.435156 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8299 05:56:56.441973 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8300 05:56:56.449715 [CA 0] Center 42 (12~72) winsize 61
8301 05:56:56.453263 [CA 1] Center 42 (12~72) winsize 61
8302 05:56:56.456141 [CA 2] Center 38 (9~68) winsize 60
8303 05:56:56.459512 [CA 3] Center 37 (8~67) winsize 60
8304 05:56:56.462733 [CA 4] Center 38 (8~68) winsize 61
8305 05:56:56.466086 [CA 5] Center 37 (7~67) winsize 61
8306 05:56:56.466164
8307 05:56:56.469448 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8308 05:56:56.469534
8309 05:56:56.472801 [CATrainingPosCal] consider 1 rank data
8310 05:56:56.476299 u2DelayCellTimex100 = 290/100 ps
8311 05:56:56.479293 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8312 05:56:56.486418 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8313 05:56:56.490023 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8314 05:56:56.493036 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8315 05:56:56.496333 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8316 05:56:56.499829 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8317 05:56:56.499900
8318 05:56:56.502920 CA PerBit enable=1, Macro0, CA PI delay=37
8319 05:56:56.502991
8320 05:56:56.506526 [CBTSetCACLKResult] CA Dly = 37
8321 05:56:56.506606 CS Dly: 8 (0~39)
8322 05:56:56.513096 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8323 05:56:56.516282 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8324 05:56:56.516354 ==
8325 05:56:56.519466 Dram Type= 6, Freq= 0, CH_1, rank 1
8326 05:56:56.522712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 05:56:56.522783 ==
8328 05:56:56.529404 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8329 05:56:56.532710 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8330 05:56:56.539139 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8331 05:56:56.542455 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8332 05:56:56.552718 [CA 0] Center 42 (13~72) winsize 60
8333 05:56:56.556271 [CA 1] Center 41 (11~71) winsize 61
8334 05:56:56.559180 [CA 2] Center 37 (8~67) winsize 60
8335 05:56:56.562729 [CA 3] Center 37 (8~66) winsize 59
8336 05:56:56.566069 [CA 4] Center 37 (8~67) winsize 60
8337 05:56:56.569250 [CA 5] Center 36 (7~66) winsize 60
8338 05:56:56.569328
8339 05:56:56.572715 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8340 05:56:56.572787
8341 05:56:56.576118 [CATrainingPosCal] consider 2 rank data
8342 05:56:56.579384 u2DelayCellTimex100 = 290/100 ps
8343 05:56:56.582780 CA0 delay=42 (13~72),Diff = 6 PI (20 cell)
8344 05:56:56.589214 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8345 05:56:56.592694 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8346 05:56:56.595791 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8347 05:56:56.599332 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8348 05:56:56.602314 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8349 05:56:56.602384
8350 05:56:56.605805 CA PerBit enable=1, Macro0, CA PI delay=36
8351 05:56:56.605911
8352 05:56:56.609406 [CBTSetCACLKResult] CA Dly = 36
8353 05:56:56.612578 CS Dly: 10 (0~44)
8354 05:56:56.615910 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8355 05:56:56.619125 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8356 05:56:56.619205
8357 05:56:56.622529 ----->DramcWriteLeveling(PI) begin...
8358 05:56:56.622608 ==
8359 05:56:56.626087 Dram Type= 6, Freq= 0, CH_1, rank 0
8360 05:56:56.629357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 05:56:56.632795 ==
8362 05:56:56.635613 Write leveling (Byte 0): 25 => 25
8363 05:56:56.635682 Write leveling (Byte 1): 27 => 27
8364 05:56:56.639342 DramcWriteLeveling(PI) end<-----
8365 05:56:56.639409
8366 05:56:56.639469 ==
8367 05:56:56.642138 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 05:56:56.649071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 05:56:56.649148 ==
8370 05:56:56.652114 [Gating] SW mode calibration
8371 05:56:56.658786 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8372 05:56:56.662167 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8373 05:56:56.669012 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 05:56:56.672280 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 05:56:56.675597 1 4 8 | B1->B0 | 2d2d 3131 | 1 1 | (1 1) (0 0)
8376 05:56:56.682347 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 05:56:56.685386 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 05:56:56.688821 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 05:56:56.695275 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 05:56:56.698763 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 05:56:56.702251 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 05:56:56.708856 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 05:56:56.711894 1 5 8 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (1 0)
8384 05:56:56.715562 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8385 05:56:56.718549 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 05:56:56.725114 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 05:56:56.728781 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 05:56:56.731964 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 05:56:56.738388 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 05:56:56.741841 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8391 05:56:56.745322 1 6 8 | B1->B0 | 3b3b 4444 | 1 0 | (0 0) (0 0)
8392 05:56:56.751794 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 05:56:56.755187 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 05:56:56.758643 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 05:56:56.765360 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 05:56:56.768965 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 05:56:56.771863 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 05:56:56.778570 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8399 05:56:56.781650 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8400 05:56:56.785046 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8401 05:56:56.791841 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8402 05:56:56.795367 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 05:56:56.798338 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 05:56:56.805262 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 05:56:56.808383 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 05:56:56.811861 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 05:56:56.818209 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 05:56:56.821813 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 05:56:56.824677 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 05:56:56.831423 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 05:56:56.834844 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 05:56:56.838343 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 05:56:56.844932 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 05:56:56.848216 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 05:56:56.851677 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8416 05:56:56.855036 Total UI for P1: 0, mck2ui 16
8417 05:56:56.858136 best dqsien dly found for B0: ( 1, 9, 6)
8418 05:56:56.861692 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8419 05:56:56.868281 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 05:56:56.871313 Total UI for P1: 0, mck2ui 16
8421 05:56:56.874780 best dqsien dly found for B1: ( 1, 9, 10)
8422 05:56:56.878419 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8423 05:56:56.881682 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8424 05:56:56.881765
8425 05:56:56.885022 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8426 05:56:56.887955 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8427 05:56:56.891227 [Gating] SW calibration Done
8428 05:56:56.891325 ==
8429 05:56:56.894733 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 05:56:56.898324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 05:56:56.898408 ==
8432 05:56:56.901285 RX Vref Scan: 0
8433 05:56:56.901368
8434 05:56:56.901433 RX Vref 0 -> 0, step: 1
8435 05:56:56.904778
8436 05:56:56.904877 RX Delay 0 -> 252, step: 8
8437 05:56:56.908191 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8438 05:56:56.914555 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8439 05:56:56.918169 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8440 05:56:56.921498 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8441 05:56:56.924852 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8442 05:56:56.927966 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8443 05:56:56.934788 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8444 05:56:56.938059 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8445 05:56:56.941524 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8446 05:56:56.944714 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8447 05:56:56.947820 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8448 05:56:56.954693 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8449 05:56:56.958100 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8450 05:56:56.961233 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8451 05:56:56.964821 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8452 05:56:56.968251 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8453 05:56:56.971322 ==
8454 05:56:56.971423 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 05:56:56.978217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 05:56:56.978317 ==
8457 05:56:56.978399 DQS Delay:
8458 05:56:56.981763 DQS0 = 0, DQS1 = 0
8459 05:56:56.981862 DQM Delay:
8460 05:56:56.984695 DQM0 = 136, DQM1 = 130
8461 05:56:56.984819 DQ Delay:
8462 05:56:56.988177 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8463 05:56:56.991667 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8464 05:56:56.995026 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8465 05:56:56.998336 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8466 05:56:56.998435
8467 05:56:56.998533
8468 05:56:56.998609 ==
8469 05:56:57.001289 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 05:56:57.008182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 05:56:57.008284 ==
8472 05:56:57.008383
8473 05:56:57.008459
8474 05:56:57.008522 TX Vref Scan disable
8475 05:56:57.011676 == TX Byte 0 ==
8476 05:56:57.014669 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8477 05:56:57.017747 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8478 05:56:57.021226 == TX Byte 1 ==
8479 05:56:57.024698 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8480 05:56:57.031246 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8481 05:56:57.031378 ==
8482 05:56:57.034763 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 05:56:57.037737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 05:56:57.037819 ==
8485 05:56:57.048728
8486 05:56:57.052360 TX Vref early break, caculate TX vref
8487 05:56:57.055555 TX Vref=16, minBit 10, minWin=22, winSum=373
8488 05:56:57.058828 TX Vref=18, minBit 10, minWin=22, winSum=379
8489 05:56:57.062184 TX Vref=20, minBit 0, minWin=24, winSum=395
8490 05:56:57.065500 TX Vref=22, minBit 10, minWin=24, winSum=403
8491 05:56:57.071848 TX Vref=24, minBit 10, minWin=24, winSum=408
8492 05:56:57.075425 TX Vref=26, minBit 10, minWin=25, winSum=422
8493 05:56:57.078873 TX Vref=28, minBit 1, minWin=26, winSum=428
8494 05:56:57.081919 TX Vref=30, minBit 12, minWin=25, winSum=420
8495 05:56:57.085324 TX Vref=32, minBit 8, minWin=24, winSum=405
8496 05:56:57.092138 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
8497 05:56:57.092222
8498 05:56:57.095546 Final TX Range 0 Vref 28
8499 05:56:57.095643
8500 05:56:57.095709 ==
8501 05:56:57.098364 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 05:56:57.101882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 05:56:57.102022 ==
8504 05:56:57.102117
8505 05:56:57.102224
8506 05:56:57.105427 TX Vref Scan disable
8507 05:56:57.111884 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8508 05:56:57.111967 == TX Byte 0 ==
8509 05:56:57.115316 u2DelayCellOfst[0]=13 cells (4 PI)
8510 05:56:57.118304 u2DelayCellOfst[1]=10 cells (3 PI)
8511 05:56:57.121761 u2DelayCellOfst[2]=0 cells (0 PI)
8512 05:56:57.125328 u2DelayCellOfst[3]=6 cells (2 PI)
8513 05:56:57.128165 u2DelayCellOfst[4]=6 cells (2 PI)
8514 05:56:57.131703 u2DelayCellOfst[5]=16 cells (5 PI)
8515 05:56:57.135206 u2DelayCellOfst[6]=16 cells (5 PI)
8516 05:56:57.135289 u2DelayCellOfst[7]=6 cells (2 PI)
8517 05:56:57.141777 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8518 05:56:57.144731 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8519 05:56:57.144814 == TX Byte 1 ==
8520 05:56:57.148244 u2DelayCellOfst[8]=0 cells (0 PI)
8521 05:56:57.151583 u2DelayCellOfst[9]=3 cells (1 PI)
8522 05:56:57.154907 u2DelayCellOfst[10]=10 cells (3 PI)
8523 05:56:57.158162 u2DelayCellOfst[11]=3 cells (1 PI)
8524 05:56:57.161736 u2DelayCellOfst[12]=13 cells (4 PI)
8525 05:56:57.164799 u2DelayCellOfst[13]=20 cells (6 PI)
8526 05:56:57.168548 u2DelayCellOfst[14]=20 cells (6 PI)
8527 05:56:57.171513 u2DelayCellOfst[15]=16 cells (5 PI)
8528 05:56:57.174625 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8529 05:56:57.181291 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8530 05:56:57.181391 DramC Write-DBI on
8531 05:56:57.181472 ==
8532 05:56:57.184705 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 05:56:57.188194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 05:56:57.191150 ==
8535 05:56:57.191234
8536 05:56:57.191299
8537 05:56:57.191360 TX Vref Scan disable
8538 05:56:57.194826 == TX Byte 0 ==
8539 05:56:57.197884 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8540 05:56:57.201302 == TX Byte 1 ==
8541 05:56:57.204601 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8542 05:56:57.204684 DramC Write-DBI off
8543 05:56:57.207877
8544 05:56:57.207959 [DATLAT]
8545 05:56:57.208024 Freq=1600, CH1 RK0
8546 05:56:57.208085
8547 05:56:57.211330 DATLAT Default: 0xf
8548 05:56:57.211412 0, 0xFFFF, sum = 0
8549 05:56:57.214927 1, 0xFFFF, sum = 0
8550 05:56:57.215012 2, 0xFFFF, sum = 0
8551 05:56:57.217798 3, 0xFFFF, sum = 0
8552 05:56:57.221229 4, 0xFFFF, sum = 0
8553 05:56:57.221313 5, 0xFFFF, sum = 0
8554 05:56:57.224844 6, 0xFFFF, sum = 0
8555 05:56:57.224928 7, 0xFFFF, sum = 0
8556 05:56:57.227842 8, 0xFFFF, sum = 0
8557 05:56:57.227927 9, 0xFFFF, sum = 0
8558 05:56:57.231152 10, 0xFFFF, sum = 0
8559 05:56:57.231235 11, 0xFFFF, sum = 0
8560 05:56:57.234709 12, 0xFFFF, sum = 0
8561 05:56:57.234795 13, 0xFFFF, sum = 0
8562 05:56:57.238139 14, 0x0, sum = 1
8563 05:56:57.238222 15, 0x0, sum = 2
8564 05:56:57.241139 16, 0x0, sum = 3
8565 05:56:57.241222 17, 0x0, sum = 4
8566 05:56:57.244685 best_step = 15
8567 05:56:57.244767
8568 05:56:57.244833 ==
8569 05:56:57.247628 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 05:56:57.251157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 05:56:57.251240 ==
8572 05:56:57.251306 RX Vref Scan: 1
8573 05:56:57.254503
8574 05:56:57.254584 Set Vref Range= 24 -> 127
8575 05:56:57.254650
8576 05:56:57.257897 RX Vref 24 -> 127, step: 1
8577 05:56:57.257987
8578 05:56:57.260886 RX Delay 19 -> 252, step: 4
8579 05:56:57.260968
8580 05:56:57.264670 Set Vref, RX VrefLevel [Byte0]: 24
8581 05:56:57.267915 [Byte1]: 24
8582 05:56:57.267998
8583 05:56:57.270845 Set Vref, RX VrefLevel [Byte0]: 25
8584 05:56:57.274448 [Byte1]: 25
8585 05:56:57.274574
8586 05:56:57.277806 Set Vref, RX VrefLevel [Byte0]: 26
8587 05:56:57.280981 [Byte1]: 26
8588 05:56:57.284825
8589 05:56:57.284899 Set Vref, RX VrefLevel [Byte0]: 27
8590 05:56:57.288381 [Byte1]: 27
8591 05:56:57.292271
8592 05:56:57.292372 Set Vref, RX VrefLevel [Byte0]: 28
8593 05:56:57.295648 [Byte1]: 28
8594 05:56:57.299894
8595 05:56:57.299972 Set Vref, RX VrefLevel [Byte0]: 29
8596 05:56:57.303395 [Byte1]: 29
8597 05:56:57.307665
8598 05:56:57.307740 Set Vref, RX VrefLevel [Byte0]: 30
8599 05:56:57.311142 [Byte1]: 30
8600 05:56:57.315238
8601 05:56:57.315338 Set Vref, RX VrefLevel [Byte0]: 31
8602 05:56:57.318709 [Byte1]: 31
8603 05:56:57.322701
8604 05:56:57.322775 Set Vref, RX VrefLevel [Byte0]: 32
8605 05:56:57.326225 [Byte1]: 32
8606 05:56:57.330108
8607 05:56:57.330192 Set Vref, RX VrefLevel [Byte0]: 33
8608 05:56:57.333644 [Byte1]: 33
8609 05:56:57.338109
8610 05:56:57.338187 Set Vref, RX VrefLevel [Byte0]: 34
8611 05:56:57.341011 [Byte1]: 34
8612 05:56:57.345505
8613 05:56:57.345577 Set Vref, RX VrefLevel [Byte0]: 35
8614 05:56:57.348495 [Byte1]: 35
8615 05:56:57.352921
8616 05:56:57.353013 Set Vref, RX VrefLevel [Byte0]: 36
8617 05:56:57.356235 [Byte1]: 36
8618 05:56:57.360524
8619 05:56:57.360634 Set Vref, RX VrefLevel [Byte0]: 37
8620 05:56:57.363945 [Byte1]: 37
8621 05:56:57.368245
8622 05:56:57.368351 Set Vref, RX VrefLevel [Byte0]: 38
8623 05:56:57.371575 [Byte1]: 38
8624 05:56:57.375690
8625 05:56:57.375787 Set Vref, RX VrefLevel [Byte0]: 39
8626 05:56:57.378986 [Byte1]: 39
8627 05:56:57.383515
8628 05:56:57.383615 Set Vref, RX VrefLevel [Byte0]: 40
8629 05:56:57.386727 [Byte1]: 40
8630 05:56:57.390753
8631 05:56:57.390851 Set Vref, RX VrefLevel [Byte0]: 41
8632 05:56:57.394052 [Byte1]: 41
8633 05:56:57.398614
8634 05:56:57.398730 Set Vref, RX VrefLevel [Byte0]: 42
8635 05:56:57.401819 [Byte1]: 42
8636 05:56:57.406301
8637 05:56:57.406383 Set Vref, RX VrefLevel [Byte0]: 43
8638 05:56:57.409125 [Byte1]: 43
8639 05:56:57.413871
8640 05:56:57.413976 Set Vref, RX VrefLevel [Byte0]: 44
8641 05:56:57.416888 [Byte1]: 44
8642 05:56:57.421235
8643 05:56:57.421317 Set Vref, RX VrefLevel [Byte0]: 45
8644 05:56:57.424797 [Byte1]: 45
8645 05:56:57.428720
8646 05:56:57.428803 Set Vref, RX VrefLevel [Byte0]: 46
8647 05:56:57.432156 [Byte1]: 46
8648 05:56:57.436183
8649 05:56:57.436264 Set Vref, RX VrefLevel [Byte0]: 47
8650 05:56:57.439609 [Byte1]: 47
8651 05:56:57.443647
8652 05:56:57.443729 Set Vref, RX VrefLevel [Byte0]: 48
8653 05:56:57.447271 [Byte1]: 48
8654 05:56:57.451680
8655 05:56:57.451762 Set Vref, RX VrefLevel [Byte0]: 49
8656 05:56:57.454636 [Byte1]: 49
8657 05:56:57.459168
8658 05:56:57.459250 Set Vref, RX VrefLevel [Byte0]: 50
8659 05:56:57.462596 [Byte1]: 50
8660 05:56:57.466473
8661 05:56:57.466555 Set Vref, RX VrefLevel [Byte0]: 51
8662 05:56:57.469906 [Byte1]: 51
8663 05:56:57.474429
8664 05:56:57.474511 Set Vref, RX VrefLevel [Byte0]: 52
8665 05:56:57.477702 [Byte1]: 52
8666 05:56:57.481681
8667 05:56:57.481763 Set Vref, RX VrefLevel [Byte0]: 53
8668 05:56:57.484942 [Byte1]: 53
8669 05:56:57.489517
8670 05:56:57.489599 Set Vref, RX VrefLevel [Byte0]: 54
8671 05:56:57.492837 [Byte1]: 54
8672 05:56:57.496797
8673 05:56:57.496898 Set Vref, RX VrefLevel [Byte0]: 55
8674 05:56:57.500133 [Byte1]: 55
8675 05:56:57.504669
8676 05:56:57.504751 Set Vref, RX VrefLevel [Byte0]: 56
8677 05:56:57.507772 [Byte1]: 56
8678 05:56:57.512103
8679 05:56:57.512185 Set Vref, RX VrefLevel [Byte0]: 57
8680 05:56:57.515367 [Byte1]: 57
8681 05:56:57.519823
8682 05:56:57.519906 Set Vref, RX VrefLevel [Byte0]: 58
8683 05:56:57.522827 [Byte1]: 58
8684 05:56:57.527311
8685 05:56:57.527411 Set Vref, RX VrefLevel [Byte0]: 59
8686 05:56:57.530702 [Byte1]: 59
8687 05:56:57.535058
8688 05:56:57.535157 Set Vref, RX VrefLevel [Byte0]: 60
8689 05:56:57.538090 [Byte1]: 60
8690 05:56:57.542465
8691 05:56:57.542565 Set Vref, RX VrefLevel [Byte0]: 61
8692 05:56:57.545963 [Byte1]: 61
8693 05:56:57.549903
8694 05:56:57.550041 Set Vref, RX VrefLevel [Byte0]: 62
8695 05:56:57.553275 [Byte1]: 62
8696 05:56:57.557295
8697 05:56:57.557394 Set Vref, RX VrefLevel [Byte0]: 63
8698 05:56:57.560735 [Byte1]: 63
8699 05:56:57.565149
8700 05:56:57.565276 Set Vref, RX VrefLevel [Byte0]: 64
8701 05:56:57.568350 [Byte1]: 64
8702 05:56:57.572822
8703 05:56:57.572924 Set Vref, RX VrefLevel [Byte0]: 65
8704 05:56:57.575848 [Byte1]: 65
8705 05:56:57.580176
8706 05:56:57.580261 Set Vref, RX VrefLevel [Byte0]: 66
8707 05:56:57.583471 [Byte1]: 66
8708 05:56:57.587950
8709 05:56:57.588037 Set Vref, RX VrefLevel [Byte0]: 67
8710 05:56:57.591227 [Byte1]: 67
8711 05:56:57.595224
8712 05:56:57.595307 Set Vref, RX VrefLevel [Byte0]: 68
8713 05:56:57.598801 [Byte1]: 68
8714 05:56:57.602907
8715 05:56:57.603038 Set Vref, RX VrefLevel [Byte0]: 69
8716 05:56:57.606269 [Byte1]: 69
8717 05:56:57.610714
8718 05:56:57.610796 Set Vref, RX VrefLevel [Byte0]: 70
8719 05:56:57.613889 [Byte1]: 70
8720 05:56:57.618221
8721 05:56:57.618305 Set Vref, RX VrefLevel [Byte0]: 71
8722 05:56:57.621706 [Byte1]: 71
8723 05:56:57.625549
8724 05:56:57.625632 Set Vref, RX VrefLevel [Byte0]: 72
8725 05:56:57.629060 [Byte1]: 72
8726 05:56:57.633329
8727 05:56:57.633412 Set Vref, RX VrefLevel [Byte0]: 73
8728 05:56:57.636827 [Byte1]: 73
8729 05:56:57.640795
8730 05:56:57.640878 Final RX Vref Byte 0 = 59 to rank0
8731 05:56:57.644092 Final RX Vref Byte 1 = 65 to rank0
8732 05:56:57.647547 Final RX Vref Byte 0 = 59 to rank1
8733 05:56:57.650544 Final RX Vref Byte 1 = 65 to rank1==
8734 05:56:57.653992 Dram Type= 6, Freq= 0, CH_1, rank 0
8735 05:56:57.660564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8736 05:56:57.660648 ==
8737 05:56:57.660715 DQS Delay:
8738 05:56:57.660780 DQS0 = 0, DQS1 = 0
8739 05:56:57.664150 DQM Delay:
8740 05:56:57.664234 DQM0 = 134, DQM1 = 129
8741 05:56:57.667152 DQ Delay:
8742 05:56:57.670408 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
8743 05:56:57.673730 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8744 05:56:57.677108 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8745 05:56:57.680681 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =136
8746 05:56:57.680765
8747 05:56:57.680831
8748 05:56:57.680892
8749 05:56:57.684138 [DramC_TX_OE_Calibration] TA2
8750 05:56:57.687338 Original DQ_B0 (3 6) =30, OEN = 27
8751 05:56:57.690816 Original DQ_B1 (3 6) =30, OEN = 27
8752 05:56:57.693703 24, 0x0, End_B0=24 End_B1=24
8753 05:56:57.693821 25, 0x0, End_B0=25 End_B1=25
8754 05:56:57.697559 26, 0x0, End_B0=26 End_B1=26
8755 05:56:57.700342 27, 0x0, End_B0=27 End_B1=27
8756 05:56:57.703770 28, 0x0, End_B0=28 End_B1=28
8757 05:56:57.707263 29, 0x0, End_B0=29 End_B1=29
8758 05:56:57.707347 30, 0x0, End_B0=30 End_B1=30
8759 05:56:57.710514 31, 0x5151, End_B0=30 End_B1=30
8760 05:56:57.714104 Byte0 end_step=30 best_step=27
8761 05:56:57.717447 Byte1 end_step=30 best_step=27
8762 05:56:57.720539 Byte0 TX OE(2T, 0.5T) = (3, 3)
8763 05:56:57.720623 Byte1 TX OE(2T, 0.5T) = (3, 3)
8764 05:56:57.723740
8765 05:56:57.723823
8766 05:56:57.730424 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8767 05:56:57.733765 CH1 RK0: MR19=303, MR18=1624
8768 05:56:57.740200 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8769 05:56:57.740285
8770 05:56:57.743670 ----->DramcWriteLeveling(PI) begin...
8771 05:56:57.743760 ==
8772 05:56:57.747371 Dram Type= 6, Freq= 0, CH_1, rank 1
8773 05:56:57.750334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8774 05:56:57.750418 ==
8775 05:56:57.753697 Write leveling (Byte 0): 26 => 26
8776 05:56:57.756699 Write leveling (Byte 1): 28 => 28
8777 05:56:57.760232 DramcWriteLeveling(PI) end<-----
8778 05:56:57.760316
8779 05:56:57.760382 ==
8780 05:56:57.763675 Dram Type= 6, Freq= 0, CH_1, rank 1
8781 05:56:57.766620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8782 05:56:57.766703 ==
8783 05:56:57.770076 [Gating] SW mode calibration
8784 05:56:57.776711 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8785 05:56:57.783523 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8786 05:56:57.786539 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 05:56:57.793284 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 05:56:57.796668 1 4 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8789 05:56:57.800344 1 4 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
8790 05:56:57.803144 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 05:56:57.809891 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 05:56:57.813141 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 05:56:57.816888 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 05:56:57.823342 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 05:56:57.826548 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8796 05:56:57.829754 1 5 8 | B1->B0 | 2626 3434 | 0 1 | (1 0) (1 0)
8797 05:56:57.836589 1 5 12 | B1->B0 | 2323 2c2c | 0 0 | (1 0) (0 1)
8798 05:56:57.839945 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 05:56:57.842959 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 05:56:57.849818 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 05:56:57.852846 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 05:56:57.856348 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 05:56:57.863101 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8804 05:56:57.866603 1 6 8 | B1->B0 | 4343 2323 | 0 0 | (0 0) (0 0)
8805 05:56:57.869579 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8806 05:56:57.876509 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 05:56:57.879774 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 05:56:57.882950 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 05:56:57.889802 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 05:56:57.892736 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 05:56:57.896075 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 05:56:57.903196 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8813 05:56:57.906082 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8814 05:56:57.909575 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 05:56:57.916431 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 05:56:57.919572 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 05:56:57.922969 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 05:56:57.929584 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 05:56:57.932722 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 05:56:57.936085 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 05:56:57.942593 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 05:56:57.946181 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 05:56:57.949726 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 05:56:57.952746 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 05:56:57.959411 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 05:56:57.962810 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 05:56:57.965750 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 05:56:57.972689 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8829 05:56:57.976166 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8830 05:56:57.979232 Total UI for P1: 0, mck2ui 16
8831 05:56:57.982551 best dqsien dly found for B1: ( 1, 9, 8)
8832 05:56:57.985870 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 05:56:57.989174 Total UI for P1: 0, mck2ui 16
8834 05:56:57.992682 best dqsien dly found for B0: ( 1, 9, 10)
8835 05:56:57.995817 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8836 05:56:57.999042 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8837 05:56:57.999126
8838 05:56:58.006058 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8839 05:56:58.008854 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8840 05:56:58.012324 [Gating] SW calibration Done
8841 05:56:58.012407 ==
8842 05:56:58.015477 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 05:56:58.018904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 05:56:58.018988 ==
8845 05:56:58.019055 RX Vref Scan: 0
8846 05:56:58.022224
8847 05:56:58.022310 RX Vref 0 -> 0, step: 1
8848 05:56:58.022389
8849 05:56:58.025588 RX Delay 0 -> 252, step: 8
8850 05:56:58.029159 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8851 05:56:58.032261 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8852 05:56:58.039016 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8853 05:56:58.042139 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8854 05:56:58.045501 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8855 05:56:58.049181 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8856 05:56:58.052179 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8857 05:56:58.055451 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8858 05:56:58.062370 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8859 05:56:58.065349 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8860 05:56:58.068754 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8861 05:56:58.072213 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8862 05:56:58.078789 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8863 05:56:58.082220 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8864 05:56:58.085209 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8865 05:56:58.088509 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8866 05:56:58.088592 ==
8867 05:56:58.091787 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 05:56:58.098824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 05:56:58.098907 ==
8870 05:56:58.098973 DQS Delay:
8871 05:56:58.099035 DQS0 = 0, DQS1 = 0
8872 05:56:58.101837 DQM Delay:
8873 05:56:58.101920 DQM0 = 136, DQM1 = 132
8874 05:56:58.105199 DQ Delay:
8875 05:56:58.108389 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8876 05:56:58.111869 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =135
8877 05:56:58.115562 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8878 05:56:58.118551 DQ12 =143, DQ13 =139, DQ14 =135, DQ15 =143
8879 05:56:58.118634
8880 05:56:58.118700
8881 05:56:58.118762 ==
8882 05:56:58.122042 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 05:56:58.125437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 05:56:58.128443 ==
8885 05:56:58.128563
8886 05:56:58.128675
8887 05:56:58.128781 TX Vref Scan disable
8888 05:56:58.131866 == TX Byte 0 ==
8889 05:56:58.135141 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8890 05:56:58.138493 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8891 05:56:58.141874 == TX Byte 1 ==
8892 05:56:58.145410 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8893 05:56:58.148385 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8894 05:56:58.148463 ==
8895 05:56:58.152027 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 05:56:58.158137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 05:56:58.158216 ==
8898 05:56:58.171151
8899 05:56:58.174727 TX Vref early break, caculate TX vref
8900 05:56:58.177636 TX Vref=16, minBit 9, minWin=22, winSum=380
8901 05:56:58.181119 TX Vref=18, minBit 8, minWin=23, winSum=393
8902 05:56:58.184605 TX Vref=20, minBit 9, minWin=23, winSum=398
8903 05:56:58.188006 TX Vref=22, minBit 11, minWin=24, winSum=411
8904 05:56:58.191000 TX Vref=24, minBit 9, minWin=24, winSum=416
8905 05:56:58.197775 TX Vref=26, minBit 9, minWin=25, winSum=422
8906 05:56:58.201351 TX Vref=28, minBit 11, minWin=24, winSum=418
8907 05:56:58.204323 TX Vref=30, minBit 9, minWin=24, winSum=414
8908 05:56:58.207672 TX Vref=32, minBit 1, minWin=24, winSum=401
8909 05:56:58.211055 TX Vref=34, minBit 10, minWin=23, winSum=400
8910 05:56:58.214546 TX Vref=36, minBit 9, minWin=22, winSum=393
8911 05:56:58.221066 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 26
8912 05:56:58.221173
8913 05:56:58.224643 Final TX Range 0 Vref 26
8914 05:56:58.224746
8915 05:56:58.224836 ==
8916 05:56:58.227576 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 05:56:58.230905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 05:56:58.231034 ==
8919 05:56:58.231128
8920 05:56:58.234543
8921 05:56:58.234629 TX Vref Scan disable
8922 05:56:58.241204 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8923 05:56:58.241320 == TX Byte 0 ==
8924 05:56:58.244155 u2DelayCellOfst[0]=13 cells (4 PI)
8925 05:56:58.247826 u2DelayCellOfst[1]=10 cells (3 PI)
8926 05:56:58.250746 u2DelayCellOfst[2]=0 cells (0 PI)
8927 05:56:58.254064 u2DelayCellOfst[3]=3 cells (1 PI)
8928 05:56:58.257948 u2DelayCellOfst[4]=6 cells (2 PI)
8929 05:56:58.260685 u2DelayCellOfst[5]=16 cells (5 PI)
8930 05:56:58.264020 u2DelayCellOfst[6]=16 cells (5 PI)
8931 05:56:58.267354 u2DelayCellOfst[7]=3 cells (1 PI)
8932 05:56:58.271049 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8933 05:56:58.274119 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8934 05:56:58.277638 == TX Byte 1 ==
8935 05:56:58.280619 u2DelayCellOfst[8]=0 cells (0 PI)
8936 05:56:58.284053 u2DelayCellOfst[9]=3 cells (1 PI)
8937 05:56:58.284152 u2DelayCellOfst[10]=10 cells (3 PI)
8938 05:56:58.287409 u2DelayCellOfst[11]=3 cells (1 PI)
8939 05:56:58.290759 u2DelayCellOfst[12]=16 cells (5 PI)
8940 05:56:58.294174 u2DelayCellOfst[13]=16 cells (5 PI)
8941 05:56:58.297252 u2DelayCellOfst[14]=20 cells (6 PI)
8942 05:56:58.300577 u2DelayCellOfst[15]=20 cells (6 PI)
8943 05:56:58.307339 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8944 05:56:58.310951 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8945 05:56:58.311061 DramC Write-DBI on
8946 05:56:58.311151 ==
8947 05:56:58.314218 Dram Type= 6, Freq= 0, CH_1, rank 1
8948 05:56:58.320798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8949 05:56:58.320906 ==
8950 05:56:58.321000
8951 05:56:58.321087
8952 05:56:58.321176 TX Vref Scan disable
8953 05:56:58.324858 == TX Byte 0 ==
8954 05:56:58.327977 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8955 05:56:58.331362 == TX Byte 1 ==
8956 05:56:58.334186 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8957 05:56:58.337762 DramC Write-DBI off
8958 05:56:58.337878
8959 05:56:58.338012 [DATLAT]
8960 05:56:58.338106 Freq=1600, CH1 RK1
8961 05:56:58.338202
8962 05:56:58.341166 DATLAT Default: 0xf
8963 05:56:58.344462 0, 0xFFFF, sum = 0
8964 05:56:58.344547 1, 0xFFFF, sum = 0
8965 05:56:58.347841 2, 0xFFFF, sum = 0
8966 05:56:58.347939 3, 0xFFFF, sum = 0
8967 05:56:58.350840 4, 0xFFFF, sum = 0
8968 05:56:58.350939 5, 0xFFFF, sum = 0
8969 05:56:58.354155 6, 0xFFFF, sum = 0
8970 05:56:58.354254 7, 0xFFFF, sum = 0
8971 05:56:58.357623 8, 0xFFFF, sum = 0
8972 05:56:58.357707 9, 0xFFFF, sum = 0
8973 05:56:58.360931 10, 0xFFFF, sum = 0
8974 05:56:58.361015 11, 0xFFFF, sum = 0
8975 05:56:58.364371 12, 0xFFFF, sum = 0
8976 05:56:58.364454 13, 0xFFFF, sum = 0
8977 05:56:58.367430 14, 0x0, sum = 1
8978 05:56:58.367546 15, 0x0, sum = 2
8979 05:56:58.370499 16, 0x0, sum = 3
8980 05:56:58.370584 17, 0x0, sum = 4
8981 05:56:58.373754 best_step = 15
8982 05:56:58.373836
8983 05:56:58.373901 ==
8984 05:56:58.377283 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 05:56:58.380728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 05:56:58.380811 ==
8987 05:56:58.384216 RX Vref Scan: 0
8988 05:56:58.384298
8989 05:56:58.384365 RX Vref 0 -> 0, step: 1
8990 05:56:58.384426
8991 05:56:58.387256 RX Delay 19 -> 252, step: 4
8992 05:56:58.390536 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8993 05:56:58.397527 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8994 05:56:58.400794 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8995 05:56:58.404348 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8996 05:56:58.407311 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8997 05:56:58.410657 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8998 05:56:58.417517 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8999 05:56:58.420832 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
9000 05:56:58.423798 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
9001 05:56:58.427224 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9002 05:56:58.430603 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9003 05:56:58.436868 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9004 05:56:58.440171 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9005 05:56:58.443755 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9006 05:56:58.447181 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9007 05:56:58.450496 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9008 05:56:58.453899 ==
9009 05:56:58.454010 Dram Type= 6, Freq= 0, CH_1, rank 1
9010 05:56:58.460364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9011 05:56:58.460438 ==
9012 05:56:58.460541 DQS Delay:
9013 05:56:58.463787 DQS0 = 0, DQS1 = 0
9014 05:56:58.463880 DQM Delay:
9015 05:56:58.466791 DQM0 = 133, DQM1 = 130
9016 05:56:58.466874 DQ Delay:
9017 05:56:58.470371 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9018 05:56:58.473807 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
9019 05:56:58.476842 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =124
9020 05:56:58.480405 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9021 05:56:58.480489
9022 05:56:58.480564
9023 05:56:58.480629
9024 05:56:58.483533 [DramC_TX_OE_Calibration] TA2
9025 05:56:58.486745 Original DQ_B0 (3 6) =30, OEN = 27
9026 05:56:58.490113 Original DQ_B1 (3 6) =30, OEN = 27
9027 05:56:58.493487 24, 0x0, End_B0=24 End_B1=24
9028 05:56:58.496853 25, 0x0, End_B0=25 End_B1=25
9029 05:56:58.496928 26, 0x0, End_B0=26 End_B1=26
9030 05:56:58.500257 27, 0x0, End_B0=27 End_B1=27
9031 05:56:58.503677 28, 0x0, End_B0=28 End_B1=28
9032 05:56:58.507034 29, 0x0, End_B0=29 End_B1=29
9033 05:56:58.507110 30, 0x0, End_B0=30 End_B1=30
9034 05:56:58.510167 31, 0x4141, End_B0=30 End_B1=30
9035 05:56:58.513501 Byte0 end_step=30 best_step=27
9036 05:56:58.517026 Byte1 end_step=30 best_step=27
9037 05:56:58.520055 Byte0 TX OE(2T, 0.5T) = (3, 3)
9038 05:56:58.523454 Byte1 TX OE(2T, 0.5T) = (3, 3)
9039 05:56:58.523557
9040 05:56:58.523642
9041 05:56:58.529768 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9042 05:56:58.533247 CH1 RK1: MR19=303, MR18=1C07
9043 05:56:58.539687 CH1_RK1: MR19=0x303, MR18=0x1C07, DQSOSC=395, MR23=63, INC=23, DEC=15
9044 05:56:58.543030 [RxdqsGatingPostProcess] freq 1600
9045 05:56:58.549963 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9046 05:56:58.550070 best DQS0 dly(2T, 0.5T) = (1, 1)
9047 05:56:58.553257 best DQS1 dly(2T, 0.5T) = (1, 1)
9048 05:56:58.556231 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9049 05:56:58.559768 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9050 05:56:58.563279 best DQS0 dly(2T, 0.5T) = (1, 1)
9051 05:56:58.566248 best DQS1 dly(2T, 0.5T) = (1, 1)
9052 05:56:58.569701 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9053 05:56:58.573015 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9054 05:56:58.576257 Pre-setting of DQS Precalculation
9055 05:56:58.579605 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9056 05:56:58.589400 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9057 05:56:58.596703 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9058 05:56:58.596796
9059 05:56:58.596874
9060 05:56:58.599753 [Calibration Summary] 3200 Mbps
9061 05:56:58.599838 CH 0, Rank 0
9062 05:56:58.602783 SW Impedance : PASS
9063 05:56:58.602868 DUTY Scan : NO K
9064 05:56:58.606119 ZQ Calibration : PASS
9065 05:56:58.609656 Jitter Meter : NO K
9066 05:56:58.609755 CBT Training : PASS
9067 05:56:58.613031 Write leveling : PASS
9068 05:56:58.616311 RX DQS gating : PASS
9069 05:56:58.616395 RX DQ/DQS(RDDQC) : PASS
9070 05:56:58.619723 TX DQ/DQS : PASS
9071 05:56:58.619813 RX DATLAT : PASS
9072 05:56:58.622718 RX DQ/DQS(Engine): PASS
9073 05:56:58.626141 TX OE : PASS
9074 05:56:58.626224 All Pass.
9075 05:56:58.626295
9076 05:56:58.626407 CH 0, Rank 1
9077 05:56:58.629744 SW Impedance : PASS
9078 05:56:58.633188 DUTY Scan : NO K
9079 05:56:58.633273 ZQ Calibration : PASS
9080 05:56:58.636226 Jitter Meter : NO K
9081 05:56:58.639765 CBT Training : PASS
9082 05:56:58.639852 Write leveling : PASS
9083 05:56:58.642803 RX DQS gating : PASS
9084 05:56:58.646379 RX DQ/DQS(RDDQC) : PASS
9085 05:56:58.646468 TX DQ/DQS : PASS
9086 05:56:58.649778 RX DATLAT : PASS
9087 05:56:58.652714 RX DQ/DQS(Engine): PASS
9088 05:56:58.652811 TX OE : PASS
9089 05:56:58.656293 All Pass.
9090 05:56:58.656383
9091 05:56:58.656448 CH 1, Rank 0
9092 05:56:58.659453 SW Impedance : PASS
9093 05:56:58.659543 DUTY Scan : NO K
9094 05:56:58.662942 ZQ Calibration : PASS
9095 05:56:58.666418 Jitter Meter : NO K
9096 05:56:58.666516 CBT Training : PASS
9097 05:56:58.669273 Write leveling : PASS
9098 05:56:58.669370 RX DQS gating : PASS
9099 05:56:58.672869 RX DQ/DQS(RDDQC) : PASS
9100 05:56:58.676092 TX DQ/DQS : PASS
9101 05:56:58.676180 RX DATLAT : PASS
9102 05:56:58.679292 RX DQ/DQS(Engine): PASS
9103 05:56:58.682901 TX OE : PASS
9104 05:56:58.682984 All Pass.
9105 05:56:58.683052
9106 05:56:58.683131 CH 1, Rank 1
9107 05:56:58.686263 SW Impedance : PASS
9108 05:56:58.689423 DUTY Scan : NO K
9109 05:56:58.689506 ZQ Calibration : PASS
9110 05:56:58.692980 Jitter Meter : NO K
9111 05:56:58.696124 CBT Training : PASS
9112 05:56:58.696241 Write leveling : PASS
9113 05:56:58.699525 RX DQS gating : PASS
9114 05:56:58.702537 RX DQ/DQS(RDDQC) : PASS
9115 05:56:58.702640 TX DQ/DQS : PASS
9116 05:56:58.705875 RX DATLAT : PASS
9117 05:56:58.709374 RX DQ/DQS(Engine): PASS
9118 05:56:58.709448 TX OE : PASS
9119 05:56:58.712313 All Pass.
9120 05:56:58.712389
9121 05:56:58.712454 DramC Write-DBI on
9122 05:56:58.715792 PER_BANK_REFRESH: Hybrid Mode
9123 05:56:58.715896 TX_TRACKING: ON
9124 05:56:58.725545 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9125 05:56:58.732686 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9126 05:56:58.742177 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9127 05:56:58.745732 [FAST_K] Save calibration result to emmc
9128 05:56:58.749044 sync common calibartion params.
9129 05:56:58.749127 sync cbt_mode0:1, 1:1
9130 05:56:58.752227 dram_init: ddr_geometry: 2
9131 05:56:58.755811 dram_init: ddr_geometry: 2
9132 05:56:58.755894 dram_init: ddr_geometry: 2
9133 05:56:58.758715 0:dram_rank_size:100000000
9134 05:56:58.762082 1:dram_rank_size:100000000
9135 05:56:58.768897 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9136 05:56:58.768980 DFS_SHUFFLE_HW_MODE: ON
9137 05:56:58.772240 dramc_set_vcore_voltage set vcore to 725000
9138 05:56:58.775333 Read voltage for 1600, 0
9139 05:56:58.775416 Vio18 = 0
9140 05:56:58.778566 Vcore = 725000
9141 05:56:58.778649 Vdram = 0
9142 05:56:58.778715 Vddq = 0
9143 05:56:58.782170 Vmddr = 0
9144 05:56:58.782253 switch to 3200 Mbps bootup
9145 05:56:58.785619 [DramcRunTimeConfig]
9146 05:56:58.785700 PHYPLL
9147 05:56:58.788589 DPM_CONTROL_AFTERK: ON
9148 05:56:58.788671 PER_BANK_REFRESH: ON
9149 05:56:58.791820 REFRESH_OVERHEAD_REDUCTION: ON
9150 05:56:58.795443 CMD_PICG_NEW_MODE: OFF
9151 05:56:58.795526 XRTWTW_NEW_MODE: ON
9152 05:56:58.798907 XRTRTR_NEW_MODE: ON
9153 05:56:58.798988 TX_TRACKING: ON
9154 05:56:58.801936 RDSEL_TRACKING: OFF
9155 05:56:58.805234 DQS Precalculation for DVFS: ON
9156 05:56:58.805316 RX_TRACKING: OFF
9157 05:56:58.808575 HW_GATING DBG: ON
9158 05:56:58.808658 ZQCS_ENABLE_LP4: ON
9159 05:56:58.811893 RX_PICG_NEW_MODE: ON
9160 05:56:58.811975 TX_PICG_NEW_MODE: ON
9161 05:56:58.815265 ENABLE_RX_DCM_DPHY: ON
9162 05:56:58.818656 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9163 05:56:58.822083 DUMMY_READ_FOR_TRACKING: OFF
9164 05:56:58.822166 !!! SPM_CONTROL_AFTERK: OFF
9165 05:56:58.825281 !!! SPM could not control APHY
9166 05:56:58.828706 IMPEDANCE_TRACKING: ON
9167 05:56:58.828788 TEMP_SENSOR: ON
9168 05:56:58.831738 HW_SAVE_FOR_SR: OFF
9169 05:56:58.835084 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9170 05:56:58.838354 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9171 05:56:58.838437 Read ODT Tracking: ON
9172 05:56:58.841703 Refresh Rate DeBounce: ON
9173 05:56:58.845108 DFS_NO_QUEUE_FLUSH: ON
9174 05:56:58.848716 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9175 05:56:58.848798 ENABLE_DFS_RUNTIME_MRW: OFF
9176 05:56:58.851638 DDR_RESERVE_NEW_MODE: ON
9177 05:56:58.855119 MR_CBT_SWITCH_FREQ: ON
9178 05:56:58.855201 =========================
9179 05:56:58.875417 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9180 05:56:58.878672 dram_init: ddr_geometry: 2
9181 05:56:58.897231 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9182 05:56:58.900266 dram_init: dram init end (result: 0)
9183 05:56:58.907153 DRAM-K: Full calibration passed in 24492 msecs
9184 05:56:58.910408 MRC: failed to locate region type 0.
9185 05:56:58.910515 DRAM rank0 size:0x100000000,
9186 05:56:58.913558 DRAM rank1 size=0x100000000
9187 05:56:58.923571 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9188 05:56:58.930365 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9189 05:56:58.936699 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9190 05:56:58.943342 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9191 05:56:58.946805 DRAM rank0 size:0x100000000,
9192 05:56:58.949927 DRAM rank1 size=0x100000000
9193 05:56:58.950025 CBMEM:
9194 05:56:58.953314 IMD: root @ 0xfffff000 254 entries.
9195 05:56:58.956809 IMD: root @ 0xffffec00 62 entries.
9196 05:56:58.960163 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9197 05:56:58.963199 WARNING: RO_VPD is uninitialized or empty.
9198 05:56:58.970000 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9199 05:56:58.976842 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9200 05:56:58.990132 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9201 05:56:59.001284 BS: romstage times (exec / console): total (unknown) / 23994 ms
9202 05:56:59.001389
9203 05:56:59.001483
9204 05:56:59.011063 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9205 05:56:59.014740 ARM64: Exception handlers installed.
9206 05:56:59.017900 ARM64: Testing exception
9207 05:56:59.021219 ARM64: Done test exception
9208 05:56:59.021326 Enumerating buses...
9209 05:56:59.024635 Show all devs... Before device enumeration.
9210 05:56:59.027959 Root Device: enabled 1
9211 05:56:59.031191 CPU_CLUSTER: 0: enabled 1
9212 05:56:59.031297 CPU: 00: enabled 1
9213 05:56:59.034640 Compare with tree...
9214 05:56:59.034740 Root Device: enabled 1
9215 05:56:59.037922 CPU_CLUSTER: 0: enabled 1
9216 05:56:59.041011 CPU: 00: enabled 1
9217 05:56:59.041084 Root Device scanning...
9218 05:56:59.044370 scan_static_bus for Root Device
9219 05:56:59.047823 CPU_CLUSTER: 0 enabled
9220 05:56:59.051305 scan_static_bus for Root Device done
9221 05:56:59.054306 scan_bus: bus Root Device finished in 8 msecs
9222 05:56:59.054382 done
9223 05:56:59.060763 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9224 05:56:59.064188 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9225 05:56:59.070757 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9226 05:56:59.074305 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9227 05:56:59.077613 Allocating resources...
9228 05:56:59.081137 Reading resources...
9229 05:56:59.083950 Root Device read_resources bus 0 link: 0
9230 05:56:59.084024 DRAM rank0 size:0x100000000,
9231 05:56:59.087431 DRAM rank1 size=0x100000000
9232 05:56:59.090937 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9233 05:56:59.093810 CPU: 00 missing read_resources
9234 05:56:59.100837 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9235 05:56:59.104242 Root Device read_resources bus 0 link: 0 done
9236 05:56:59.104344 Done reading resources.
9237 05:56:59.110431 Show resources in subtree (Root Device)...After reading.
9238 05:56:59.113868 Root Device child on link 0 CPU_CLUSTER: 0
9239 05:56:59.117225 CPU_CLUSTER: 0 child on link 0 CPU: 00
9240 05:56:59.127058 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9241 05:56:59.127165 CPU: 00
9242 05:56:59.130399 Root Device assign_resources, bus 0 link: 0
9243 05:56:59.133932 CPU_CLUSTER: 0 missing set_resources
9244 05:56:59.140566 Root Device assign_resources, bus 0 link: 0 done
9245 05:56:59.140673 Done setting resources.
9246 05:56:59.146814 Show resources in subtree (Root Device)...After assigning values.
9247 05:56:59.150161 Root Device child on link 0 CPU_CLUSTER: 0
9248 05:56:59.153755 CPU_CLUSTER: 0 child on link 0 CPU: 00
9249 05:56:59.163702 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9250 05:56:59.163808 CPU: 00
9251 05:56:59.167008 Done allocating resources.
9252 05:56:59.170268 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9253 05:56:59.173831 Enabling resources...
9254 05:56:59.173933 done.
9255 05:56:59.180340 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9256 05:56:59.180446 Initializing devices...
9257 05:56:59.183915 Root Device init
9258 05:56:59.184033 init hardware done!
9259 05:56:59.187324 0x00000018: ctrlr->caps
9260 05:56:59.190363 52.000 MHz: ctrlr->f_max
9261 05:56:59.190469 0.400 MHz: ctrlr->f_min
9262 05:56:59.193802 0x40ff8080: ctrlr->voltages
9263 05:56:59.193884 sclk: 390625
9264 05:56:59.196799 Bus Width = 1
9265 05:56:59.196898 sclk: 390625
9266 05:56:59.200424 Bus Width = 1
9267 05:56:59.200524 Early init status = 3
9268 05:56:59.206762 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9269 05:56:59.210164 in-header: 03 fc 00 00 01 00 00 00
9270 05:56:59.210265 in-data: 00
9271 05:56:59.216553 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9272 05:56:59.219978 in-header: 03 fd 00 00 00 00 00 00
9273 05:56:59.223270 in-data:
9274 05:56:59.226537 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9275 05:56:59.229848 in-header: 03 fc 00 00 01 00 00 00
9276 05:56:59.233280 in-data: 00
9277 05:56:59.236563 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9278 05:56:59.241765 in-header: 03 fd 00 00 00 00 00 00
9279 05:56:59.244996 in-data:
9280 05:56:59.248478 [SSUSB] Setting up USB HOST controller...
9281 05:56:59.251555 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9282 05:56:59.255069 [SSUSB] phy power-on done.
9283 05:56:59.258425 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9284 05:56:59.265260 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9285 05:56:59.268390 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9286 05:56:59.275136 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9287 05:56:59.281791 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9288 05:56:59.288442 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9289 05:56:59.295103 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9290 05:56:59.301438 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9291 05:56:59.304868 SPM: binary array size = 0x9dc
9292 05:56:59.308421 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9293 05:56:59.315070 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9294 05:56:59.321652 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9295 05:56:59.325028 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9296 05:56:59.331252 configure_display: Starting display init
9297 05:56:59.365115 anx7625_power_on_init: Init interface.
9298 05:56:59.368211 anx7625_disable_pd_protocol: Disabled PD feature.
9299 05:56:59.371548 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9300 05:56:59.399675 anx7625_start_dp_work: Secure OCM version=00
9301 05:56:59.402585 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9302 05:56:59.417612 sp_tx_get_edid_block: EDID Block = 1
9303 05:56:59.520021 Extracted contents:
9304 05:56:59.523380 header: 00 ff ff ff ff ff ff 00
9305 05:56:59.526824 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9306 05:56:59.529793 version: 01 04
9307 05:56:59.533313 basic params: 95 1f 11 78 0a
9308 05:56:59.536544 chroma info: 76 90 94 55 54 90 27 21 50 54
9309 05:56:59.539841 established: 00 00 00
9310 05:56:59.546754 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9311 05:56:59.549690 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9312 05:56:59.556701 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9313 05:56:59.562939 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9314 05:56:59.569772 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9315 05:56:59.573061 extensions: 00
9316 05:56:59.573261 checksum: fb
9317 05:56:59.573353
9318 05:56:59.576333 Manufacturer: IVO Model 57d Serial Number 0
9319 05:56:59.579946 Made week 0 of 2020
9320 05:56:59.580048 EDID version: 1.4
9321 05:56:59.583074 Digital display
9322 05:56:59.586440 6 bits per primary color channel
9323 05:56:59.586519 DisplayPort interface
9324 05:56:59.589463 Maximum image size: 31 cm x 17 cm
9325 05:56:59.593041 Gamma: 220%
9326 05:56:59.593120 Check DPMS levels
9327 05:56:59.596228 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9328 05:56:59.602872 First detailed timing is preferred timing
9329 05:56:59.602979 Established timings supported:
9330 05:56:59.606337 Standard timings supported:
9331 05:56:59.609735 Detailed timings
9332 05:56:59.613158 Hex of detail: 383680a07038204018303c0035ae10000019
9333 05:56:59.616154 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9334 05:56:59.622950 0780 0798 07c8 0820 hborder 0
9335 05:56:59.626310 0438 043b 0447 0458 vborder 0
9336 05:56:59.629380 -hsync -vsync
9337 05:56:59.629479 Did detailed timing
9338 05:56:59.636284 Hex of detail: 000000000000000000000000000000000000
9339 05:56:59.636393 Manufacturer-specified data, tag 0
9340 05:56:59.642552 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9341 05:56:59.645999 ASCII string: InfoVision
9342 05:56:59.649493 Hex of detail: 000000fe00523134304e574635205248200a
9343 05:56:59.652497 ASCII string: R140NWF5 RH
9344 05:56:59.652596 Checksum
9345 05:56:59.655975 Checksum: 0xfb (valid)
9346 05:56:59.659458 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9347 05:56:59.662692 DSI data_rate: 832800000 bps
9348 05:56:59.669135 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9349 05:56:59.672673 anx7625_parse_edid: pixelclock(138800).
9350 05:56:59.675984 hactive(1920), hsync(48), hfp(24), hbp(88)
9351 05:56:59.679157 vactive(1080), vsync(12), vfp(3), vbp(17)
9352 05:56:59.682409 anx7625_dsi_config: config dsi.
9353 05:56:59.688907 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9354 05:56:59.701835 anx7625_dsi_config: success to config DSI
9355 05:56:59.705242 anx7625_dp_start: MIPI phy setup OK.
9356 05:56:59.708799 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9357 05:56:59.712175 mtk_ddp_mode_set invalid vrefresh 60
9358 05:56:59.715180 main_disp_path_setup
9359 05:56:59.715254 ovl_layer_smi_id_en
9360 05:56:59.718789 ovl_layer_smi_id_en
9361 05:56:59.718859 ccorr_config
9362 05:56:59.718920 aal_config
9363 05:56:59.721789 gamma_config
9364 05:56:59.721859 postmask_config
9365 05:56:59.725133 dither_config
9366 05:56:59.728630 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9367 05:56:59.735478 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9368 05:56:59.738514 Root Device init finished in 552 msecs
9369 05:56:59.741905 CPU_CLUSTER: 0 init
9370 05:56:59.748530 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9371 05:56:59.751861 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9372 05:56:59.755281 APU_MBOX 0x190000b0 = 0x10001
9373 05:56:59.758750 APU_MBOX 0x190001b0 = 0x10001
9374 05:56:59.761793 APU_MBOX 0x190005b0 = 0x10001
9375 05:56:59.765183 APU_MBOX 0x190006b0 = 0x10001
9376 05:56:59.768590 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9377 05:56:59.781100 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9378 05:56:59.793788 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9379 05:56:59.800042 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9380 05:56:59.811736 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9381 05:56:59.820691 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9382 05:56:59.824156 CPU_CLUSTER: 0 init finished in 81 msecs
9383 05:56:59.827470 Devices initialized
9384 05:56:59.830887 Show all devs... After init.
9385 05:56:59.830993 Root Device: enabled 1
9386 05:56:59.833930 CPU_CLUSTER: 0: enabled 1
9387 05:56:59.837241 CPU: 00: enabled 1
9388 05:56:59.840788 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9389 05:56:59.843846 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9390 05:56:59.847250 ELOG: NV offset 0x57f000 size 0x1000
9391 05:56:59.853760 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9392 05:56:59.860619 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9393 05:56:59.864189 ELOG: Event(17) added with size 13 at 2023-12-25 05:56:17 UTC
9394 05:56:59.867207 out: cmd=0x121: 03 db 21 01 00 00 00 00
9395 05:56:59.871025 in-header: 03 3e 00 00 2c 00 00 00
9396 05:56:59.884466 in-data: 21 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9397 05:56:59.891033 ELOG: Event(A1) added with size 10 at 2023-12-25 05:56:17 UTC
9398 05:56:59.897756 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9399 05:56:59.904300 ELOG: Event(A0) added with size 9 at 2023-12-25 05:56:17 UTC
9400 05:56:59.907918 elog_add_boot_reason: Logged dev mode boot
9401 05:56:59.910933 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9402 05:56:59.914388 Finalize devices...
9403 05:56:59.914466 Devices finalized
9404 05:56:59.921223 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9405 05:56:59.924734 Writing coreboot table at 0xffe64000
9406 05:56:59.928375 0. 000000000010a000-0000000000113fff: RAMSTAGE
9407 05:56:59.931488 1. 0000000040000000-00000000400fffff: RAM
9408 05:56:59.934859 2. 0000000040100000-000000004032afff: RAMSTAGE
9409 05:56:59.941285 3. 000000004032b000-00000000545fffff: RAM
9410 05:56:59.944779 4. 0000000054600000-000000005465ffff: BL31
9411 05:56:59.948210 5. 0000000054660000-00000000ffe63fff: RAM
9412 05:56:59.951081 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9413 05:56:59.957930 7. 0000000100000000-000000023fffffff: RAM
9414 05:56:59.958057 Passing 5 GPIOs to payload:
9415 05:56:59.964436 NAME | PORT | POLARITY | VALUE
9416 05:56:59.967828 EC in RW | 0x000000aa | low | undefined
9417 05:56:59.974216 EC interrupt | 0x00000005 | low | undefined
9418 05:56:59.977471 TPM interrupt | 0x000000ab | high | undefined
9419 05:56:59.981205 SD card detect | 0x00000011 | high | undefined
9420 05:56:59.987526 speaker enable | 0x00000093 | high | undefined
9421 05:56:59.990817 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9422 05:56:59.994455 in-header: 03 f9 00 00 02 00 00 00
9423 05:56:59.994529 in-data: 02 00
9424 05:56:59.997507 ADC[4]: Raw value=901032 ID=7
9425 05:57:00.000840 ADC[3]: Raw value=212810 ID=1
9426 05:57:00.000930 RAM Code: 0x71
9427 05:57:00.004398 ADC[6]: Raw value=74502 ID=0
9428 05:57:00.007655 ADC[5]: Raw value=212072 ID=1
9429 05:57:00.007734 SKU Code: 0x1
9430 05:57:00.014213 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 584a
9431 05:57:00.017431 coreboot table: 964 bytes.
9432 05:57:00.020737 IMD ROOT 0. 0xfffff000 0x00001000
9433 05:57:00.023939 IMD SMALL 1. 0xffffe000 0x00001000
9434 05:57:00.027321 RO MCACHE 2. 0xffffc000 0x00001104
9435 05:57:00.030978 CONSOLE 3. 0xfff7c000 0x00080000
9436 05:57:00.033883 FMAP 4. 0xfff7b000 0x00000452
9437 05:57:00.037356 TIME STAMP 5. 0xfff7a000 0x00000910
9438 05:57:00.040718 VBOOT WORK 6. 0xfff66000 0x00014000
9439 05:57:00.044149 RAMOOPS 7. 0xffe66000 0x00100000
9440 05:57:00.047715 COREBOOT 8. 0xffe64000 0x00002000
9441 05:57:00.047873 IMD small region:
9442 05:57:00.050805 IMD ROOT 0. 0xffffec00 0x00000400
9443 05:57:00.054301 VPD 1. 0xffffeb80 0x0000006c
9444 05:57:00.057602 MMC STATUS 2. 0xffffeb60 0x00000004
9445 05:57:00.064295 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9446 05:57:00.064400 Probing TPM: done!
9447 05:57:00.070677 Connected to device vid:did:rid of 1ae0:0028:00
9448 05:57:00.080915 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9449 05:57:00.084920 Initialized TPM device CR50 revision 0
9450 05:57:00.084995 Checking cr50 for pending updates
9451 05:57:00.090977 Reading cr50 TPM mode
9452 05:57:00.099240 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9453 05:57:00.105648 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9454 05:57:00.146130 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9455 05:57:00.149118 Checking segment from ROM address 0x40100000
9456 05:57:00.152649 Checking segment from ROM address 0x4010001c
9457 05:57:00.159155 Loading segment from ROM address 0x40100000
9458 05:57:00.159258 code (compression=0)
9459 05:57:00.169270 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9460 05:57:00.175806 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9461 05:57:00.175912 it's not compressed!
9462 05:57:00.182546 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9463 05:57:00.185933 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9464 05:57:00.206517 Loading segment from ROM address 0x4010001c
9465 05:57:00.206625 Entry Point 0x80000000
9466 05:57:00.209915 Loaded segments
9467 05:57:00.212864 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9468 05:57:00.219748 Jumping to boot code at 0x80000000(0xffe64000)
9469 05:57:00.226345 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9470 05:57:00.233270 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9471 05:57:00.240880 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9472 05:57:00.244037 Checking segment from ROM address 0x40100000
9473 05:57:00.247280 Checking segment from ROM address 0x4010001c
9474 05:57:00.254287 Loading segment from ROM address 0x40100000
9475 05:57:00.254400 code (compression=1)
9476 05:57:00.260670 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9477 05:57:00.270815 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9478 05:57:00.270929 using LZMA
9479 05:57:00.279195 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9480 05:57:00.285698 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9481 05:57:00.289124 Loading segment from ROM address 0x4010001c
9482 05:57:00.289234 Entry Point 0x54601000
9483 05:57:00.292616 Loaded segments
9484 05:57:00.295824 NOTICE: MT8192 bl31_setup
9485 05:57:00.303018 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9486 05:57:00.306149 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9487 05:57:00.309644 WARNING: region 0:
9488 05:57:00.312765 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 05:57:00.312849 WARNING: region 1:
9490 05:57:00.319364 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9491 05:57:00.322747 WARNING: region 2:
9492 05:57:00.326194 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9493 05:57:00.329468 WARNING: region 3:
9494 05:57:00.333052 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9495 05:57:00.336131 WARNING: region 4:
9496 05:57:00.342678 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9497 05:57:00.342763 WARNING: region 5:
9498 05:57:00.346157 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 05:57:00.349348 WARNING: region 6:
9500 05:57:00.353027 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 05:57:00.353111 WARNING: region 7:
9502 05:57:00.359416 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 05:57:00.366535 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9504 05:57:00.369868 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9505 05:57:00.373149 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9506 05:57:00.379533 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9507 05:57:00.383005 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9508 05:57:00.386055 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9509 05:57:00.392900 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9510 05:57:00.396307 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9511 05:57:00.399630 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9512 05:57:00.406526 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9513 05:57:00.409870 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9514 05:57:00.413328 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9515 05:57:00.419805 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9516 05:57:00.423195 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9517 05:57:00.429708 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9518 05:57:00.433071 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9519 05:57:00.436488 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9520 05:57:00.443151 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9521 05:57:00.446769 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9522 05:57:00.449983 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9523 05:57:00.456683 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9524 05:57:00.459739 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9525 05:57:00.466814 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9526 05:57:00.469886 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9527 05:57:00.473230 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9528 05:57:00.480002 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9529 05:57:00.483537 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9530 05:57:00.490345 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9531 05:57:00.493197 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9532 05:57:00.496885 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9533 05:57:00.503223 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9534 05:57:00.506830 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9535 05:57:00.509956 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9536 05:57:00.516790 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9537 05:57:00.519797 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9538 05:57:00.523152 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9539 05:57:00.526792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9540 05:57:00.533312 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9541 05:57:00.536686 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9542 05:57:00.540054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9543 05:57:00.543427 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9544 05:57:00.550281 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9545 05:57:00.553431 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9546 05:57:00.556581 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9547 05:57:00.560215 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9548 05:57:00.566682 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9549 05:57:00.570195 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9550 05:57:00.573135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9551 05:57:00.579935 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9552 05:57:00.583246 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9553 05:57:00.586692 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9554 05:57:00.593183 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9555 05:57:00.596688 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9556 05:57:00.603279 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9557 05:57:00.606709 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9558 05:57:00.610180 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9559 05:57:00.616798 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9560 05:57:00.619789 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9561 05:57:00.626781 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9562 05:57:00.630239 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9563 05:57:00.636604 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9564 05:57:00.640149 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9565 05:57:00.646911 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9566 05:57:00.649801 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9567 05:57:00.653719 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9568 05:57:00.660097 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9569 05:57:00.663275 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9570 05:57:00.669794 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9571 05:57:00.673553 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9572 05:57:00.679912 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9573 05:57:00.683242 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9574 05:57:00.686612 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9575 05:57:00.693357 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9576 05:57:00.696830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9577 05:57:00.703630 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9578 05:57:00.707002 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9579 05:57:00.710640 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9580 05:57:00.716977 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9581 05:57:00.720525 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9582 05:57:00.727313 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9583 05:57:00.730287 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9584 05:57:00.737230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9585 05:57:00.740697 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9586 05:57:00.743761 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9587 05:57:00.750349 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9588 05:57:00.753896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9589 05:57:00.760672 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9590 05:57:00.763783 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9591 05:57:00.770641 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9592 05:57:00.773887 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9593 05:57:00.777486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9594 05:57:00.783743 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9595 05:57:00.787387 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9596 05:57:00.793747 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9597 05:57:00.797358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9598 05:57:00.804118 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9599 05:57:00.807422 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9600 05:57:00.810725 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9601 05:57:00.814170 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9602 05:57:00.820605 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9603 05:57:00.824079 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9604 05:57:00.827372 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9605 05:57:00.833912 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9606 05:57:00.837336 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9607 05:57:00.844244 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9608 05:57:00.847279 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9609 05:57:00.850478 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9610 05:57:00.857522 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9611 05:57:00.860928 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9612 05:57:00.867348 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9613 05:57:00.870768 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9614 05:57:00.874168 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9615 05:57:00.880826 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9616 05:57:00.884227 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9617 05:57:00.887350 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9618 05:57:00.893870 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9619 05:57:00.897398 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9620 05:57:00.900929 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9621 05:57:00.907459 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9622 05:57:00.910824 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9623 05:57:00.914082 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9624 05:57:00.917425 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9625 05:57:00.923925 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9626 05:57:00.927277 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9627 05:57:00.930660 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9628 05:57:00.937648 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9629 05:57:00.940660 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9630 05:57:00.944139 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9631 05:57:00.950645 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9632 05:57:00.954087 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9633 05:57:00.957463 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9634 05:57:00.964065 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9635 05:57:00.967561 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9636 05:57:00.974149 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9637 05:57:00.977648 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9638 05:57:00.981029 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9639 05:57:00.987427 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9640 05:57:00.991078 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9641 05:57:00.997423 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9642 05:57:01.000928 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9643 05:57:01.004411 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9644 05:57:01.011140 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9645 05:57:01.014506 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9646 05:57:01.017720 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9647 05:57:01.024777 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9648 05:57:01.028146 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9649 05:57:01.034405 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9650 05:57:01.037774 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9651 05:57:01.040743 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9652 05:57:01.047637 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9653 05:57:01.051182 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9654 05:57:01.057596 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9655 05:57:01.060908 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9656 05:57:01.064370 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9657 05:57:01.071247 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9658 05:57:01.074202 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9659 05:57:01.080808 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9660 05:57:01.084060 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9661 05:57:01.088000 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9662 05:57:01.094221 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9663 05:57:01.098099 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9664 05:57:01.101255 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9665 05:57:01.107484 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9666 05:57:01.111185 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9667 05:57:01.117799 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9668 05:57:01.120751 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9669 05:57:01.124547 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9670 05:57:01.130848 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9671 05:57:01.134291 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9672 05:57:01.140862 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9673 05:57:01.144327 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9674 05:57:01.147237 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9675 05:57:01.154234 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9676 05:57:01.157175 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9677 05:57:01.164185 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9678 05:57:01.167226 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9679 05:57:01.170652 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9680 05:57:01.177239 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9681 05:57:01.180678 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9682 05:57:01.183973 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9683 05:57:01.190459 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9684 05:57:01.193845 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9685 05:57:01.200713 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9686 05:57:01.204135 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9687 05:57:01.207242 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9688 05:57:01.213755 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9689 05:57:01.217545 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9690 05:57:01.223654 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9691 05:57:01.226935 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9692 05:57:01.230303 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9693 05:57:01.237274 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9694 05:57:01.240170 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9695 05:57:01.246897 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9696 05:57:01.250336 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9697 05:57:01.257295 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9698 05:57:01.260215 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9699 05:57:01.263677 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9700 05:57:01.270087 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9701 05:57:01.273600 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9702 05:57:01.280478 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9703 05:57:01.283462 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9704 05:57:01.286971 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9705 05:57:01.293784 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9706 05:57:01.296582 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9707 05:57:01.303443 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9708 05:57:01.306904 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9709 05:57:01.313474 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9710 05:57:01.316670 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9711 05:57:01.320146 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9712 05:57:01.326877 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9713 05:57:01.330091 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9714 05:57:01.336509 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9715 05:57:01.340014 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9716 05:57:01.346681 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9717 05:57:01.349920 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9718 05:57:01.352939 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9719 05:57:01.359945 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9720 05:57:01.362930 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9721 05:57:01.369717 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9722 05:57:01.372980 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9723 05:57:01.376416 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9724 05:57:01.383394 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9725 05:57:01.386304 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9726 05:57:01.393123 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9727 05:57:01.396207 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9728 05:57:01.399672 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9729 05:57:01.406548 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9730 05:57:01.409450 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9731 05:57:01.416699 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9732 05:57:01.419732 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9733 05:57:01.422895 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9734 05:57:01.426480 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9735 05:57:01.432928 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9736 05:57:01.435985 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9737 05:57:01.439463 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9738 05:57:01.446387 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9739 05:57:01.449832 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9740 05:57:01.453085 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9741 05:57:01.459685 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9742 05:57:01.463123 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9743 05:57:01.466166 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9744 05:57:01.473168 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9745 05:57:01.476455 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9746 05:57:01.479775 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9747 05:57:01.486195 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9748 05:57:01.489753 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9749 05:57:01.496180 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9750 05:57:01.499695 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9751 05:57:01.502586 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9752 05:57:01.509339 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9753 05:57:01.512785 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9754 05:57:01.516097 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9755 05:57:01.523008 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9756 05:57:01.526317 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9757 05:57:01.529547 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9758 05:57:01.536041 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9759 05:57:01.539552 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9760 05:57:01.545998 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9761 05:57:01.549695 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9762 05:57:01.552897 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9763 05:57:01.559383 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9764 05:57:01.562787 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9765 05:57:01.566202 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9766 05:57:01.572769 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9767 05:57:01.576194 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9768 05:57:01.579300 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9769 05:57:01.585728 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9770 05:57:01.589254 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9771 05:57:01.592580 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9772 05:57:01.599130 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9773 05:57:01.602493 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9774 05:57:01.605884 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9775 05:57:01.608790 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9776 05:57:01.615468 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9777 05:57:01.618662 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9778 05:57:01.622492 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9779 05:57:01.625413 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9780 05:57:01.632264 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9781 05:57:01.635526 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9782 05:57:01.638691 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9783 05:57:01.645518 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9784 05:57:01.648635 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9785 05:57:01.651845 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9786 05:57:01.658629 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9787 05:57:01.662032 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9788 05:57:01.665401 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9789 05:57:01.671437 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9790 05:57:01.674946 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9791 05:57:01.681409 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9792 05:57:01.684816 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9793 05:57:01.691688 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9794 05:57:01.695189 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9795 05:57:01.698200 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9796 05:57:01.704627 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9797 05:57:01.708327 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9798 05:57:01.714576 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9799 05:57:01.718128 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9800 05:57:01.721552 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9801 05:57:01.728316 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9802 05:57:01.731156 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9803 05:57:01.737984 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9804 05:57:01.740968 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9805 05:57:01.747952 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9806 05:57:01.751085 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9807 05:57:01.754182 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9808 05:57:01.760728 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9809 05:57:01.764244 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9810 05:57:01.771185 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9811 05:57:01.774175 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9812 05:57:01.777820 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9813 05:57:01.784125 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9814 05:57:01.787637 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9815 05:57:01.794209 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9816 05:57:01.797663 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9817 05:57:01.801155 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9818 05:57:01.807695 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9819 05:57:01.811263 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9820 05:57:01.817513 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9821 05:57:01.820964 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9822 05:57:01.824084 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9823 05:57:01.831001 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9824 05:57:01.834440 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9825 05:57:01.840700 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9826 05:57:01.844068 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9827 05:57:01.847516 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9828 05:57:01.854187 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9829 05:57:01.857708 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9830 05:57:01.864379 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9831 05:57:01.867386 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9832 05:57:01.870931 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9833 05:57:01.877484 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9834 05:57:01.880949 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9835 05:57:01.887392 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9836 05:57:01.890818 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9837 05:57:01.894517 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9838 05:57:01.900937 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9839 05:57:01.904489 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9840 05:57:01.910907 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9841 05:57:01.914362 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9842 05:57:01.917799 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9843 05:57:01.924152 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9844 05:57:01.927703 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9845 05:57:01.934483 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9846 05:57:01.937444 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9847 05:57:01.944226 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9848 05:57:01.947539 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9849 05:57:01.951077 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9850 05:57:01.957731 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9851 05:57:01.960767 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9852 05:57:01.967722 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9853 05:57:01.970881 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9854 05:57:01.974338 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9855 05:57:01.980992 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9856 05:57:01.984270 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9857 05:57:01.990782 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9858 05:57:01.994181 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9859 05:57:01.997479 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9860 05:57:02.004150 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9861 05:57:02.007633 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9862 05:57:02.014036 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9863 05:57:02.017502 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9864 05:57:02.023947 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9865 05:57:02.027287 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9866 05:57:02.030769 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9867 05:57:02.037102 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9868 05:57:02.040628 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9869 05:57:02.047078 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9870 05:57:02.050299 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9871 05:57:02.057364 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9872 05:57:02.060384 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9873 05:57:02.063832 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9874 05:57:02.070274 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9875 05:57:02.073978 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9876 05:57:02.080536 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9877 05:57:02.083773 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9878 05:57:02.090133 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9879 05:57:02.093619 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9880 05:57:02.097074 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9881 05:57:02.103606 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9882 05:57:02.106941 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9883 05:57:02.113777 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9884 05:57:02.116794 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9885 05:57:02.123517 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9886 05:57:02.126941 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9887 05:57:02.133731 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9888 05:57:02.136742 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9889 05:57:02.140525 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9890 05:57:02.147078 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9891 05:57:02.149976 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9892 05:57:02.156648 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9893 05:57:02.160221 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9894 05:57:02.166664 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9895 05:57:02.169697 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9896 05:57:02.173252 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9897 05:57:02.179955 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9898 05:57:02.183335 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9899 05:57:02.190043 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9900 05:57:02.193159 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9901 05:57:02.199505 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9902 05:57:02.203097 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9903 05:57:02.209422 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9904 05:57:02.213009 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9905 05:57:02.216482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9906 05:57:02.223033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9907 05:57:02.226256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9908 05:57:02.233002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9909 05:57:02.236354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9910 05:57:02.242695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9911 05:57:02.246147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9912 05:57:02.252910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9913 05:57:02.256245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9914 05:57:02.262838 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9915 05:57:02.266344 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9916 05:57:02.269239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9917 05:57:02.276183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9918 05:57:02.279594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9919 05:57:02.286160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9920 05:57:02.289625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9921 05:57:02.296003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9922 05:57:02.299620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9923 05:57:02.306220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9924 05:57:02.309168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9925 05:57:02.315794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9926 05:57:02.319201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9927 05:57:02.326123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9928 05:57:02.329526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9929 05:57:02.335896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9930 05:57:02.339340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9931 05:57:02.345711 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9932 05:57:02.349114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9933 05:57:02.355801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9934 05:57:02.359290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9935 05:57:02.366042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9936 05:57:02.369420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9937 05:57:02.375736 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9938 05:57:02.375848 INFO: [APUAPC] vio 0
9939 05:57:02.382672 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9940 05:57:02.386147 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9941 05:57:02.389314 INFO: [APUAPC] D0_APC_0: 0x400510
9942 05:57:02.392710 INFO: [APUAPC] D0_APC_1: 0x0
9943 05:57:02.396155 INFO: [APUAPC] D0_APC_2: 0x1540
9944 05:57:02.398993 INFO: [APUAPC] D0_APC_3: 0x0
9945 05:57:02.402510 INFO: [APUAPC] D1_APC_0: 0xffffffff
9946 05:57:02.406015 INFO: [APUAPC] D1_APC_1: 0xffffffff
9947 05:57:02.409170 INFO: [APUAPC] D1_APC_2: 0x3fffff
9948 05:57:02.412783 INFO: [APUAPC] D1_APC_3: 0x0
9949 05:57:02.415887 INFO: [APUAPC] D2_APC_0: 0xffffffff
9950 05:57:02.419005 INFO: [APUAPC] D2_APC_1: 0xffffffff
9951 05:57:02.422529 INFO: [APUAPC] D2_APC_2: 0x3fffff
9952 05:57:02.425717 INFO: [APUAPC] D2_APC_3: 0x0
9953 05:57:02.429207 INFO: [APUAPC] D3_APC_0: 0xffffffff
9954 05:57:02.432739 INFO: [APUAPC] D3_APC_1: 0xffffffff
9955 05:57:02.435808 INFO: [APUAPC] D3_APC_2: 0x3fffff
9956 05:57:02.435896 INFO: [APUAPC] D3_APC_3: 0x0
9957 05:57:02.439191 INFO: [APUAPC] D4_APC_0: 0xffffffff
9958 05:57:02.446026 INFO: [APUAPC] D4_APC_1: 0xffffffff
9959 05:57:02.448954 INFO: [APUAPC] D4_APC_2: 0x3fffff
9960 05:57:02.449037 INFO: [APUAPC] D4_APC_3: 0x0
9961 05:57:02.452570 INFO: [APUAPC] D5_APC_0: 0xffffffff
9962 05:57:02.455815 INFO: [APUAPC] D5_APC_1: 0xffffffff
9963 05:57:02.459258 INFO: [APUAPC] D5_APC_2: 0x3fffff
9964 05:57:02.462731 INFO: [APUAPC] D5_APC_3: 0x0
9965 05:57:02.466055 INFO: [APUAPC] D6_APC_0: 0xffffffff
9966 05:57:02.469379 INFO: [APUAPC] D6_APC_1: 0xffffffff
9967 05:57:02.472810 INFO: [APUAPC] D6_APC_2: 0x3fffff
9968 05:57:02.475787 INFO: [APUAPC] D6_APC_3: 0x0
9969 05:57:02.479306 INFO: [APUAPC] D7_APC_0: 0xffffffff
9970 05:57:02.482717 INFO: [APUAPC] D7_APC_1: 0xffffffff
9971 05:57:02.485723 INFO: [APUAPC] D7_APC_2: 0x3fffff
9972 05:57:02.489180 INFO: [APUAPC] D7_APC_3: 0x0
9973 05:57:02.492659 INFO: [APUAPC] D8_APC_0: 0xffffffff
9974 05:57:02.495921 INFO: [APUAPC] D8_APC_1: 0xffffffff
9975 05:57:02.499440 INFO: [APUAPC] D8_APC_2: 0x3fffff
9976 05:57:02.502424 INFO: [APUAPC] D8_APC_3: 0x0
9977 05:57:02.505853 INFO: [APUAPC] D9_APC_0: 0xffffffff
9978 05:57:02.509043 INFO: [APUAPC] D9_APC_1: 0xffffffff
9979 05:57:02.512871 INFO: [APUAPC] D9_APC_2: 0x3fffff
9980 05:57:02.515838 INFO: [APUAPC] D9_APC_3: 0x0
9981 05:57:02.519162 INFO: [APUAPC] D10_APC_0: 0xffffffff
9982 05:57:02.522548 INFO: [APUAPC] D10_APC_1: 0xffffffff
9983 05:57:02.525838 INFO: [APUAPC] D10_APC_2: 0x3fffff
9984 05:57:02.529412 INFO: [APUAPC] D10_APC_3: 0x0
9985 05:57:02.532458 INFO: [APUAPC] D11_APC_0: 0xffffffff
9986 05:57:02.535842 INFO: [APUAPC] D11_APC_1: 0xffffffff
9987 05:57:02.539323 INFO: [APUAPC] D11_APC_2: 0x3fffff
9988 05:57:02.542920 INFO: [APUAPC] D11_APC_3: 0x0
9989 05:57:02.546163 INFO: [APUAPC] D12_APC_0: 0xffffffff
9990 05:57:02.549299 INFO: [APUAPC] D12_APC_1: 0xffffffff
9991 05:57:02.552755 INFO: [APUAPC] D12_APC_2: 0x3fffff
9992 05:57:02.555854 INFO: [APUAPC] D12_APC_3: 0x0
9993 05:57:02.559153 INFO: [APUAPC] D13_APC_0: 0xffffffff
9994 05:57:02.562409 INFO: [APUAPC] D13_APC_1: 0xffffffff
9995 05:57:02.565792 INFO: [APUAPC] D13_APC_2: 0x3fffff
9996 05:57:02.569117 INFO: [APUAPC] D13_APC_3: 0x0
9997 05:57:02.572524 INFO: [APUAPC] D14_APC_0: 0xffffffff
9998 05:57:02.575956 INFO: [APUAPC] D14_APC_1: 0xffffffff
9999 05:57:02.579019 INFO: [APUAPC] D14_APC_2: 0x3fffff
10000 05:57:02.582437 INFO: [APUAPC] D14_APC_3: 0x0
10001 05:57:02.585931 INFO: [APUAPC] D15_APC_0: 0xffffffff
10002 05:57:02.589276 INFO: [APUAPC] D15_APC_1: 0xffffffff
10003 05:57:02.592335 INFO: [APUAPC] D15_APC_2: 0x3fffff
10004 05:57:02.595818 INFO: [APUAPC] D15_APC_3: 0x0
10005 05:57:02.599454 INFO: [APUAPC] APC_CON: 0x4
10006 05:57:02.602471 INFO: [NOCDAPC] D0_APC_0: 0x0
10007 05:57:02.605846 INFO: [NOCDAPC] D0_APC_1: 0x0
10008 05:57:02.605973 INFO: [NOCDAPC] D1_APC_0: 0x0
10009 05:57:02.609345 INFO: [NOCDAPC] D1_APC_1: 0xfff
10010 05:57:02.612660 INFO: [NOCDAPC] D2_APC_0: 0x0
10011 05:57:02.615826 INFO: [NOCDAPC] D2_APC_1: 0xfff
10012 05:57:02.619267 INFO: [NOCDAPC] D3_APC_0: 0x0
10013 05:57:02.622228 INFO: [NOCDAPC] D3_APC_1: 0xfff
10014 05:57:02.625656 INFO: [NOCDAPC] D4_APC_0: 0x0
10015 05:57:02.628820 INFO: [NOCDAPC] D4_APC_1: 0xfff
10016 05:57:02.632145 INFO: [NOCDAPC] D5_APC_0: 0x0
10017 05:57:02.635742 INFO: [NOCDAPC] D5_APC_1: 0xfff
10018 05:57:02.638832 INFO: [NOCDAPC] D6_APC_0: 0x0
10019 05:57:02.638916 INFO: [NOCDAPC] D6_APC_1: 0xfff
10020 05:57:02.642028 INFO: [NOCDAPC] D7_APC_0: 0x0
10021 05:57:02.645643 INFO: [NOCDAPC] D7_APC_1: 0xfff
10022 05:57:02.649068 INFO: [NOCDAPC] D8_APC_0: 0x0
10023 05:57:02.652087 INFO: [NOCDAPC] D8_APC_1: 0xfff
10024 05:57:02.655433 INFO: [NOCDAPC] D9_APC_0: 0x0
10025 05:57:02.658827 INFO: [NOCDAPC] D9_APC_1: 0xfff
10026 05:57:02.662206 INFO: [NOCDAPC] D10_APC_0: 0x0
10027 05:57:02.665437 INFO: [NOCDAPC] D10_APC_1: 0xfff
10028 05:57:02.668435 INFO: [NOCDAPC] D11_APC_0: 0x0
10029 05:57:02.671851 INFO: [NOCDAPC] D11_APC_1: 0xfff
10030 05:57:02.675149 INFO: [NOCDAPC] D12_APC_0: 0x0
10031 05:57:02.678740 INFO: [NOCDAPC] D12_APC_1: 0xfff
10032 05:57:02.678824 INFO: [NOCDAPC] D13_APC_0: 0x0
10033 05:57:02.682177 INFO: [NOCDAPC] D13_APC_1: 0xfff
10034 05:57:02.685309 INFO: [NOCDAPC] D14_APC_0: 0x0
10035 05:57:02.688926 INFO: [NOCDAPC] D14_APC_1: 0xfff
10036 05:57:02.691955 INFO: [NOCDAPC] D15_APC_0: 0x0
10037 05:57:02.695288 INFO: [NOCDAPC] D15_APC_1: 0xfff
10038 05:57:02.698759 INFO: [NOCDAPC] APC_CON: 0x4
10039 05:57:02.701633 INFO: [APUAPC] set_apusys_apc done
10040 05:57:02.705020 INFO: [DEVAPC] devapc_init done
10041 05:57:02.708512 INFO: GICv3 without legacy support detected.
10042 05:57:02.711981 INFO: ARM GICv3 driver initialized in EL3
10043 05:57:02.718668 INFO: Maximum SPI INTID supported: 639
10044 05:57:02.721815 INFO: BL31: Initializing runtime services
10045 05:57:02.728263 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10046 05:57:02.728347 INFO: SPM: enable CPC mode
10047 05:57:02.734918 INFO: mcdi ready for mcusys-off-idle and system suspend
10048 05:57:02.738131 INFO: BL31: Preparing for EL3 exit to normal world
10049 05:57:02.741529 INFO: Entry point address = 0x80000000
10050 05:57:02.744622 INFO: SPSR = 0x8
10051 05:57:02.750883
10052 05:57:02.750967
10053 05:57:02.751033
10054 05:57:02.754255 Starting depthcharge on Spherion...
10055 05:57:02.754339
10056 05:57:02.754406 Wipe memory regions:
10057 05:57:02.754468
10058 05:57:02.755102 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10059 05:57:02.755203 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10060 05:57:02.755288 Setting prompt string to ['asurada:']
10061 05:57:02.755368 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10062 05:57:02.757120 [0x00000040000000, 0x00000054600000)
10063 05:57:02.879787
10064 05:57:02.879905 [0x00000054660000, 0x00000080000000)
10065 05:57:03.140155
10066 05:57:03.140293 [0x000000821a7280, 0x000000ffe64000)
10067 05:57:03.884890
10068 05:57:03.885031 [0x00000100000000, 0x00000240000000)
10069 05:57:05.775380
10070 05:57:05.778477 Initializing XHCI USB controller at 0x11200000.
10071 05:57:06.816891
10072 05:57:06.819816 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10073 05:57:06.819907
10074 05:57:06.819974
10075 05:57:06.820038
10076 05:57:06.820315 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10078 05:57:06.920656 asurada: tftpboot 192.168.201.1 12379447/tftp-deploy-6ixcjb7k/kernel/image.itb 12379447/tftp-deploy-6ixcjb7k/kernel/cmdline
10079 05:57:06.920773 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10080 05:57:06.920889 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10081 05:57:06.925093 tftpboot 192.168.201.1 12379447/tftp-deploy-6ixcjb7k/kernel/image.itbtp-deploy-6ixcjb7k/kernel/cmdline
10082 05:57:06.925180
10083 05:57:06.925246 Waiting for link
10084 05:57:07.085396
10085 05:57:07.085541 R8152: Initializing
10086 05:57:07.085623
10087 05:57:07.088714 Version 9 (ocp_data = 6010)
10088 05:57:07.088798
10089 05:57:07.092261 R8152: Done initializing
10090 05:57:07.092372
10091 05:57:07.092464 Adding net device
10092 05:57:08.964473
10093 05:57:08.964622 done.
10094 05:57:08.964690
10095 05:57:08.964752 MAC: 00:e0:4c:72:2d:d6
10096 05:57:08.964810
10097 05:57:08.967711 Sending DHCP discover... done.
10098 05:57:08.967796
10099 05:57:14.120237 Waiting for reply... done.
10100 05:57:14.120799
10101 05:57:14.121170 Sending DHCP request... done.
10102 05:57:14.123397
10103 05:57:14.123798 Waiting for reply... done.
10104 05:57:14.126554
10105 05:57:14.127022 My ip is 192.168.201.21
10106 05:57:14.127412
10107 05:57:14.130333 The DHCP server ip is 192.168.201.1
10108 05:57:14.130946
10109 05:57:14.133370 TFTP server IP predefined by user: 192.168.201.1
10110 05:57:14.133992
10111 05:57:14.140192 Bootfile predefined by user: 12379447/tftp-deploy-6ixcjb7k/kernel/image.itb
10112 05:57:14.140765
10113 05:57:14.143101 Sending tftp read request... done.
10114 05:57:14.143569
10115 05:57:14.150686 Waiting for the transfer...
10116 05:57:14.151182
10117 05:57:14.448750 00000000 ################################################################
10118 05:57:14.448892
10119 05:57:14.731209 00080000 ################################################################
10120 05:57:14.731375
10121 05:57:14.989390 00100000 ################################################################
10122 05:57:14.989553
10123 05:57:15.245744 00180000 ################################################################
10124 05:57:15.245914
10125 05:57:15.497716 00200000 ################################################################
10126 05:57:15.497848
10127 05:57:15.747345 00280000 ################################################################
10128 05:57:15.747471
10129 05:57:16.028756 00300000 ################################################################
10130 05:57:16.028916
10131 05:57:16.300280 00380000 ################################################################
10132 05:57:16.300408
10133 05:57:16.579824 00400000 ################################################################
10134 05:57:16.579956
10135 05:57:16.829150 00480000 ################################################################
10136 05:57:16.829306
10137 05:57:17.090518 00500000 ################################################################
10138 05:57:17.090645
10139 05:57:17.378799 00580000 ################################################################
10140 05:57:17.378930
10141 05:57:17.667342 00600000 ################################################################
10142 05:57:17.667474
10143 05:57:17.954303 00680000 ################################################################
10144 05:57:17.954437
10145 05:57:18.245829 00700000 ################################################################
10146 05:57:18.246006
10147 05:57:18.520863 00780000 ################################################################
10148 05:57:18.521003
10149 05:57:18.801633 00800000 ################################################################
10150 05:57:18.801774
10151 05:57:19.092630 00880000 ################################################################
10152 05:57:19.092761
10153 05:57:19.373851 00900000 ################################################################
10154 05:57:19.374038
10155 05:57:19.631651 00980000 ################################################################
10156 05:57:19.631777
10157 05:57:19.899706 00a00000 ################################################################
10158 05:57:19.899838
10159 05:57:20.175700 00a80000 ################################################################
10160 05:57:20.175828
10161 05:57:20.437482 00b00000 ################################################################
10162 05:57:20.437610
10163 05:57:20.691793 00b80000 ################################################################
10164 05:57:20.691918
10165 05:57:20.942657 00c00000 ################################################################
10166 05:57:20.942809
10167 05:57:21.221698 00c80000 ################################################################
10168 05:57:21.221838
10169 05:57:21.511045 00d00000 ################################################################
10170 05:57:21.511196
10171 05:57:21.786674 00d80000 ################################################################
10172 05:57:21.786857
10173 05:57:22.056146 00e00000 ################################################################
10174 05:57:22.056308
10175 05:57:22.337007 00e80000 ################################################################
10176 05:57:22.337158
10177 05:57:22.609008 00f00000 ################################################################
10178 05:57:22.609159
10179 05:57:22.872330 00f80000 ################################################################
10180 05:57:22.872463
10181 05:57:23.157217 01000000 ################################################################
10182 05:57:23.157362
10183 05:57:23.441292 01080000 ################################################################
10184 05:57:23.441426
10185 05:57:23.707673 01100000 ################################################################
10186 05:57:23.707822
10187 05:57:23.960723 01180000 ################################################################
10188 05:57:23.960890
10189 05:57:24.257304 01200000 ################################################################
10190 05:57:24.257464
10191 05:57:24.551864 01280000 ################################################################
10192 05:57:24.552029
10193 05:57:24.838025 01300000 ################################################################
10194 05:57:24.838177
10195 05:57:25.104678 01380000 ################################################################
10196 05:57:25.104840
10197 05:57:25.402131 01400000 ################################################################
10198 05:57:25.402258
10199 05:57:25.676270 01480000 ################################################################
10200 05:57:25.676435
10201 05:57:25.925863 01500000 ################################################################
10202 05:57:25.926063
10203 05:57:26.208919 01580000 ################################################################
10204 05:57:26.209076
10205 05:57:26.491720 01600000 ################################################################
10206 05:57:26.491886
10207 05:57:26.771734 01680000 ################################################################
10208 05:57:26.771878
10209 05:57:27.033069 01700000 ################################################################
10210 05:57:27.033205
10211 05:57:27.329063 01780000 ################################################################
10212 05:57:27.329196
10213 05:57:27.606721 01800000 ################################################################
10214 05:57:27.606859
10215 05:57:27.863940 01880000 ################################################################
10216 05:57:27.864077
10217 05:57:28.127975 01900000 ################################################################
10218 05:57:28.128110
10219 05:57:28.393660 01980000 ################################################################
10220 05:57:28.393814
10221 05:57:28.689715 01a00000 ################################################################
10222 05:57:28.689873
10223 05:57:28.964221 01a80000 ################################################################
10224 05:57:28.964360
10225 05:57:29.212633 01b00000 ################################################################
10226 05:57:29.212764
10227 05:57:29.491536 01b80000 ############################################################# done.
10228 05:57:29.492069
10229 05:57:29.494491 The bootfile was 29334222 bytes long.
10230 05:57:29.495087
10231 05:57:29.497618 Sending tftp read request... done.
10232 05:57:29.497722
10233 05:57:29.497814 Waiting for the transfer...
10234 05:57:29.497902
10235 05:57:29.501257 00000000 # done.
10236 05:57:29.501345
10237 05:57:29.507703 Command line loaded dynamically from TFTP file: 12379447/tftp-deploy-6ixcjb7k/kernel/cmdline
10238 05:57:29.507874
10239 05:57:29.530853 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12379447/extract-nfsrootfs-4f4eeh_n,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10240 05:57:29.531092
10241 05:57:29.531218 Loading FIT.
10242 05:57:29.531330
10243 05:57:29.533971 Image ramdisk-1 has 17803080 bytes.
10244 05:57:29.534202
10245 05:57:29.537420 Image fdt-1 has 47278 bytes.
10246 05:57:29.537672
10247 05:57:29.540961 Image kernel-1 has 11481830 bytes.
10248 05:57:29.541242
10249 05:57:29.550805 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10250 05:57:29.551124
10251 05:57:29.567473 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10252 05:57:29.568061
10253 05:57:29.574729 Choosing best match conf-1 for compat google,spherion-rev2.
10254 05:57:29.575310
10255 05:57:29.581456 Connected to device vid:did:rid of 1ae0:0028:00
10256 05:57:29.588547
10257 05:57:29.592000 tpm_get_response: command 0x17b, return code 0x0
10258 05:57:29.592579
10259 05:57:29.594823 ec_init: CrosEC protocol v3 supported (256, 248)
10260 05:57:29.598938
10261 05:57:29.602592 tpm_cleanup: add release locality here.
10262 05:57:29.603170
10263 05:57:29.603660 Shutting down all USB controllers.
10264 05:57:29.605595
10265 05:57:29.606121 Removing current net device
10266 05:57:29.606603
10267 05:57:29.612541 Exiting depthcharge with code 4 at timestamp: 56146478
10268 05:57:29.613122
10269 05:57:29.615475 LZMA decompressing kernel-1 to 0x821a6718
10270 05:57:29.615960
10271 05:57:29.619164 LZMA decompressing kernel-1 to 0x40000000
10272 05:57:31.055957
10273 05:57:31.056533 jumping to kernel
10274 05:57:31.058625 end: 2.2.4 bootloader-commands (duration 00:00:28) [common]
10275 05:57:31.059223 start: 2.2.5 auto-login-action (timeout 00:03:57) [common]
10276 05:57:31.059692 Setting prompt string to ['Linux version [0-9]']
10277 05:57:31.060178 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10278 05:57:31.060644 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10279 05:57:31.137801
10280 05:57:31.141277 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10281 05:57:31.145201 start: 2.2.5.1 login-action (timeout 00:03:57) [common]
10282 05:57:31.145810 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10283 05:57:31.146343 Setting prompt string to []
10284 05:57:31.146884 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10285 05:57:31.147373 Using line separator: #'\n'#
10286 05:57:31.147790 No login prompt set.
10287 05:57:31.148252 Parsing kernel messages
10288 05:57:31.148785 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10289 05:57:31.149515 [login-action] Waiting for messages, (timeout 00:03:57)
10290 05:57:31.164131 [ 0.000000] Linux version 6.1.67-cip12 (KernelCI@build-j59664-arm64-gcc-10-defconfig-arm64-chromebook-fgc24) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023
10291 05:57:31.167157 [ 0.000000] random: crng init done
10292 05:57:31.174003 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10293 05:57:31.177328 [ 0.000000] efi: UEFI not found.
10294 05:57:31.184152 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10295 05:57:31.190529 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10296 05:57:31.200395 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10297 05:57:31.210660 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10298 05:57:31.217329 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10299 05:57:31.224266 [ 0.000000] printk: bootconsole [mtk8250] enabled
10300 05:57:31.230649 [ 0.000000] NUMA: No NUMA configuration found
10301 05:57:31.237329 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10302 05:57:31.240852 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10303 05:57:31.243885 [ 0.000000] Zone ranges:
10304 05:57:31.250602 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10305 05:57:31.253525 [ 0.000000] DMA32 empty
10306 05:57:31.260741 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10307 05:57:31.263803 [ 0.000000] Movable zone start for each node
10308 05:57:31.267182 [ 0.000000] Early memory node ranges
10309 05:57:31.273737 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10310 05:57:31.280538 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10311 05:57:31.286859 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10312 05:57:31.293696 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10313 05:57:31.300006 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10314 05:57:31.306212 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10315 05:57:31.362558 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10316 05:57:31.369053 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10317 05:57:31.375782 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10318 05:57:31.379298 [ 0.000000] psci: probing for conduit method from DT.
10319 05:57:31.385741 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10320 05:57:31.388977 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10321 05:57:31.395251 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10322 05:57:31.398365 [ 0.000000] psci: SMC Calling Convention v1.2
10323 05:57:31.405370 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10324 05:57:31.408953 [ 0.000000] Detected VIPT I-cache on CPU0
10325 05:57:31.415256 [ 0.000000] CPU features: detected: GIC system register CPU interface
10326 05:57:31.422181 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10327 05:57:31.428428 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10328 05:57:31.435218 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10329 05:57:31.442094 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10330 05:57:31.451501 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10331 05:57:31.455271 [ 0.000000] alternatives: applying boot alternatives
10332 05:57:31.461799 [ 0.000000] Fallback order for Node 0: 0
10333 05:57:31.468377 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10334 05:57:31.471460 [ 0.000000] Policy zone: Normal
10335 05:57:31.494608 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12379447/extract-nfsrootfs-4f4eeh_n,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10336 05:57:31.504532 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10337 05:57:31.515001 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10338 05:57:31.525508 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10339 05:57:31.532155 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10340 05:57:31.535606 <6>[ 0.000000] software IO TLB: area num 8.
10341 05:57:31.593002 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10342 05:57:31.742076 <6>[ 0.000000] Memory: 7951332K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 401436K reserved, 32768K cma-reserved)
10343 05:57:31.748514 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10344 05:57:31.754979 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10345 05:57:31.758387 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10346 05:57:31.765485 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10347 05:57:31.772145 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10348 05:57:31.775530 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10349 05:57:31.785500 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10350 05:57:31.791590 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10351 05:57:31.798394 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10352 05:57:31.805180 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10353 05:57:31.808199 <6>[ 0.000000] GICv3: 608 SPIs implemented
10354 05:57:31.811534 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10355 05:57:31.818147 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10356 05:57:31.821245 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10357 05:57:31.828055 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10358 05:57:31.841238 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10359 05:57:31.851143 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10360 05:57:31.861009 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10361 05:57:31.868727 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10362 05:57:31.881829 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10363 05:57:31.888567 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10364 05:57:31.895002 <6>[ 0.009183] Console: colour dummy device 80x25
10365 05:57:31.905307 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10366 05:57:31.911747 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10367 05:57:31.914999 <6>[ 0.029251] LSM: Security Framework initializing
10368 05:57:31.922058 <6>[ 0.034188] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10369 05:57:31.931580 <6>[ 0.042002] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10370 05:57:31.941614 <6>[ 0.051466] cblist_init_generic: Setting adjustable number of callback queues.
10371 05:57:31.944568 <6>[ 0.058953] cblist_init_generic: Setting shift to 3 and lim to 1.
10372 05:57:31.954861 <6>[ 0.065291] cblist_init_generic: Setting adjustable number of callback queues.
10373 05:57:31.961014 <6>[ 0.072719] cblist_init_generic: Setting shift to 3 and lim to 1.
10374 05:57:31.964601 <6>[ 0.079120] rcu: Hierarchical SRCU implementation.
10375 05:57:31.971003 <6>[ 0.084166] rcu: Max phase no-delay instances is 1000.
10376 05:57:31.977781 <6>[ 0.091214] EFI services will not be available.
10377 05:57:31.981070 <6>[ 0.096168] smp: Bringing up secondary CPUs ...
10378 05:57:31.989779 <6>[ 0.101215] Detected VIPT I-cache on CPU1
10379 05:57:31.996080 <6>[ 0.101284] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10380 05:57:32.002911 <6>[ 0.101315] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10381 05:57:32.006474 <6>[ 0.101650] Detected VIPT I-cache on CPU2
10382 05:57:32.013114 <6>[ 0.101698] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10383 05:57:32.022898 <6>[ 0.101713] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10384 05:57:32.026521 <6>[ 0.101968] Detected VIPT I-cache on CPU3
10385 05:57:32.032820 <6>[ 0.102014] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10386 05:57:32.038996 <6>[ 0.102027] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10387 05:57:32.042598 <6>[ 0.102331] CPU features: detected: Spectre-v4
10388 05:57:32.049229 <6>[ 0.102337] CPU features: detected: Spectre-BHB
10389 05:57:32.052578 <6>[ 0.102342] Detected PIPT I-cache on CPU4
10390 05:57:32.059155 <6>[ 0.102400] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10391 05:57:32.065658 <6>[ 0.102416] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10392 05:57:32.072899 <6>[ 0.102710] Detected PIPT I-cache on CPU5
10393 05:57:32.079285 <6>[ 0.102771] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10394 05:57:32.085796 <6>[ 0.102787] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10395 05:57:32.089123 <6>[ 0.103069] Detected PIPT I-cache on CPU6
10396 05:57:32.095667 <6>[ 0.103134] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10397 05:57:32.102075 <6>[ 0.103150] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10398 05:57:32.108817 <6>[ 0.103445] Detected PIPT I-cache on CPU7
10399 05:57:32.115478 <6>[ 0.103509] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10400 05:57:32.122150 <6>[ 0.103525] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10401 05:57:32.125848 <6>[ 0.103574] smp: Brought up 1 node, 8 CPUs
10402 05:57:32.132330 <6>[ 0.244932] SMP: Total of 8 processors activated.
10403 05:57:32.135543 <6>[ 0.249853] CPU features: detected: 32-bit EL0 Support
10404 05:57:32.145021 <6>[ 0.255216] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10405 05:57:32.151666 <6>[ 0.264017] CPU features: detected: Common not Private translations
10406 05:57:32.158567 <6>[ 0.270493] CPU features: detected: CRC32 instructions
10407 05:57:32.161775 <6>[ 0.275877] CPU features: detected: RCpc load-acquire (LDAPR)
10408 05:57:32.168645 <6>[ 0.281874] CPU features: detected: LSE atomic instructions
10409 05:57:32.175093 <6>[ 0.287691] CPU features: detected: Privileged Access Never
10410 05:57:32.181819 <6>[ 0.293470] CPU features: detected: RAS Extension Support
10411 05:57:32.188279 <6>[ 0.299114] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10412 05:57:32.191453 <6>[ 0.306378] CPU: All CPU(s) started at EL2
10413 05:57:32.198096 <6>[ 0.310694] alternatives: applying system-wide alternatives
10414 05:57:32.207697 <6>[ 0.321446] devtmpfs: initialized
10415 05:57:32.219586 <6>[ 0.330378] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10416 05:57:32.229825 <6>[ 0.340339] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10417 05:57:32.235996 <6>[ 0.348542] pinctrl core: initialized pinctrl subsystem
10418 05:57:32.239893 <6>[ 0.355219] DMI not present or invalid.
10419 05:57:32.246171 <6>[ 0.359629] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10420 05:57:32.256250 <6>[ 0.366498] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10421 05:57:32.262457 <6>[ 0.374079] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10422 05:57:32.272849 <6>[ 0.382301] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10423 05:57:32.275971 <6>[ 0.390544] audit: initializing netlink subsys (disabled)
10424 05:57:32.286012 <5>[ 0.396237] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10425 05:57:32.292293 <6>[ 0.396943] thermal_sys: Registered thermal governor 'step_wise'
10426 05:57:32.299149 <6>[ 0.404203] thermal_sys: Registered thermal governor 'power_allocator'
10427 05:57:32.302636 <6>[ 0.410456] cpuidle: using governor menu
10428 05:57:32.309147 <6>[ 0.421411] NET: Registered PF_QIPCRTR protocol family
10429 05:57:32.315772 <6>[ 0.426893] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10430 05:57:32.319297 <6>[ 0.433998] ASID allocator initialised with 32768 entries
10431 05:57:32.326809 <6>[ 0.440565] Serial: AMBA PL011 UART driver
10432 05:57:32.334947 <4>[ 0.449338] Trying to register duplicate clock ID: 134
10433 05:57:32.389496 <6>[ 0.506583] KASLR enabled
10434 05:57:32.403696 <6>[ 0.514295] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10435 05:57:32.410113 <6>[ 0.521312] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10436 05:57:32.417082 <6>[ 0.527804] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10437 05:57:32.423564 <6>[ 0.534808] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10438 05:57:32.430072 <6>[ 0.541295] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10439 05:57:32.436475 <6>[ 0.548298] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10440 05:57:32.443835 <6>[ 0.554787] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10441 05:57:32.450073 <6>[ 0.561790] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10442 05:57:32.453060 <6>[ 0.569285] ACPI: Interpreter disabled.
10443 05:57:32.461755 <6>[ 0.575661] iommu: Default domain type: Translated
10444 05:57:32.468085 <6>[ 0.580772] iommu: DMA domain TLB invalidation policy: strict mode
10445 05:57:32.471214 <5>[ 0.587431] SCSI subsystem initialized
10446 05:57:32.478037 <6>[ 0.591596] usbcore: registered new interface driver usbfs
10447 05:57:32.484610 <6>[ 0.597327] usbcore: registered new interface driver hub
10448 05:57:32.487928 <6>[ 0.602877] usbcore: registered new device driver usb
10449 05:57:32.494926 <6>[ 0.608971] pps_core: LinuxPPS API ver. 1 registered
10450 05:57:32.504784 <6>[ 0.614164] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10451 05:57:32.508579 <6>[ 0.623510] PTP clock support registered
10452 05:57:32.511563 <6>[ 0.627750] EDAC MC: Ver: 3.0.0
10453 05:57:32.518654 <6>[ 0.632904] FPGA manager framework
10454 05:57:32.525430 <6>[ 0.636582] Advanced Linux Sound Architecture Driver Initialized.
10455 05:57:32.528922 <6>[ 0.643350] vgaarb: loaded
10456 05:57:32.535309 <6>[ 0.646513] clocksource: Switched to clocksource arch_sys_counter
10457 05:57:32.538657 <5>[ 0.652945] VFS: Disk quotas dquot_6.6.0
10458 05:57:32.545064 <6>[ 0.657130] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10459 05:57:32.548548 <6>[ 0.664320] pnp: PnP ACPI: disabled
10460 05:57:32.556844 <6>[ 0.671006] NET: Registered PF_INET protocol family
10461 05:57:32.563667 <6>[ 0.676283] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10462 05:57:32.578082 <6>[ 0.688597] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10463 05:57:32.587874 <6>[ 0.697415] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10464 05:57:32.594256 <6>[ 0.705385] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10465 05:57:32.604111 <6>[ 0.714085] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10466 05:57:32.610678 <6>[ 0.723833] TCP: Hash tables configured (established 65536 bind 65536)
10467 05:57:32.617314 <6>[ 0.730688] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10468 05:57:32.627372 <6>[ 0.737886] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10469 05:57:32.633745 <6>[ 0.745586] NET: Registered PF_UNIX/PF_LOCAL protocol family
10470 05:57:32.637428 <6>[ 0.751765] RPC: Registered named UNIX socket transport module.
10471 05:57:32.643909 <6>[ 0.757917] RPC: Registered udp transport module.
10472 05:57:32.647434 <6>[ 0.762849] RPC: Registered tcp transport module.
10473 05:57:32.653673 <6>[ 0.767781] RPC: Registered tcp NFSv4.1 backchannel transport module.
10474 05:57:32.660461 <6>[ 0.774451] PCI: CLS 0 bytes, default 64
10475 05:57:32.663962 <6>[ 0.778852] Unpacking initramfs...
10476 05:57:32.687899 <6>[ 0.798596] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10477 05:57:32.697923 <6>[ 0.807251] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10478 05:57:32.701180 <6>[ 0.816102] kvm [1]: IPA Size Limit: 40 bits
10479 05:57:32.708189 <6>[ 0.820629] kvm [1]: GICv3: no GICV resource entry
10480 05:57:32.711089 <6>[ 0.825650] kvm [1]: disabling GICv2 emulation
10481 05:57:32.717652 <6>[ 0.830336] kvm [1]: GIC system register CPU interface enabled
10482 05:57:32.721031 <6>[ 0.836497] kvm [1]: vgic interrupt IRQ18
10483 05:57:32.727887 <6>[ 0.840846] kvm [1]: VHE mode initialized successfully
10484 05:57:32.734643 <5>[ 0.847280] Initialise system trusted keyrings
10485 05:57:32.740567 <6>[ 0.852075] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10486 05:57:32.748331 <6>[ 0.862012] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10487 05:57:32.754480 <5>[ 0.868399] NFS: Registering the id_resolver key type
10488 05:57:32.758120 <5>[ 0.873699] Key type id_resolver registered
10489 05:57:32.764535 <5>[ 0.878112] Key type id_legacy registered
10490 05:57:32.771169 <6>[ 0.882390] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10491 05:57:32.777482 <6>[ 0.889311] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10492 05:57:32.783993 <6>[ 0.897035] 9p: Installing v9fs 9p2000 file system support
10493 05:57:32.820667 <5>[ 0.934641] Key type asymmetric registered
10494 05:57:32.823678 <5>[ 0.938974] Asymmetric key parser 'x509' registered
10495 05:57:32.834034 <6>[ 0.944110] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10496 05:57:32.837244 <6>[ 0.951727] io scheduler mq-deadline registered
10497 05:57:32.840826 <6>[ 0.956506] io scheduler kyber registered
10498 05:57:32.858924 <6>[ 0.973321] EINJ: ACPI disabled.
10499 05:57:32.892143 <4>[ 0.999556] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10500 05:57:32.901915 <4>[ 1.010206] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10501 05:57:32.916718 <6>[ 1.031093] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10502 05:57:32.925103 <6>[ 1.039271] printk: console [ttyS0] disabled
10503 05:57:32.953051 <6>[ 1.063934] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10504 05:57:32.959711 <6>[ 1.073413] printk: console [ttyS0] enabled
10505 05:57:32.963008 <6>[ 1.073413] printk: console [ttyS0] enabled
10506 05:57:32.969803 <6>[ 1.082312] printk: bootconsole [mtk8250] disabled
10507 05:57:32.973027 <6>[ 1.082312] printk: bootconsole [mtk8250] disabled
10508 05:57:32.979566 <6>[ 1.093529] SuperH (H)SCI(F) driver initialized
10509 05:57:32.982480 <6>[ 1.098812] msm_serial: driver initialized
10510 05:57:32.997017 <6>[ 1.107802] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10511 05:57:33.007203 <6>[ 1.116350] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10512 05:57:33.013368 <6>[ 1.124893] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10513 05:57:33.023630 <6>[ 1.133522] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10514 05:57:33.030023 <6>[ 1.142236] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10515 05:57:33.040120 <6>[ 1.150949] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10516 05:57:33.050026 <6>[ 1.159490] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10517 05:57:33.056630 <6>[ 1.168307] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10518 05:57:33.066691 <6>[ 1.176850] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10519 05:57:33.078111 <6>[ 1.192437] loop: module loaded
10520 05:57:33.084838 <6>[ 1.198403] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10521 05:57:33.107593 <4>[ 1.221909] mtk-pmic-keys: Failed to locate of_node [id: -1]
10522 05:57:33.114564 <6>[ 1.228966] megasas: 07.719.03.00-rc1
10523 05:57:33.124189 <6>[ 1.238754] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10524 05:57:33.131898 <6>[ 1.245892] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10525 05:57:33.148704 <6>[ 1.262654] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10526 05:57:33.205260 <6>[ 1.312777] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10527 05:57:33.400953 <6>[ 1.515181] Freeing initrd memory: 17384K
10528 05:57:33.411686 <6>[ 1.525504] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10529 05:57:33.422873 <6>[ 1.536634] tun: Universal TUN/TAP device driver, 1.6
10530 05:57:33.426093 <6>[ 1.542707] thunder_xcv, ver 1.0
10531 05:57:33.429577 <6>[ 1.546206] thunder_bgx, ver 1.0
10532 05:57:33.433002 <6>[ 1.549704] nicpf, ver 1.0
10533 05:57:33.443144 <6>[ 1.553734] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10534 05:57:33.446302 <6>[ 1.561210] hns3: Copyright (c) 2017 Huawei Corporation.
10535 05:57:33.452674 <6>[ 1.566799] hclge is initializing
10536 05:57:33.455700 <6>[ 1.570377] e1000: Intel(R) PRO/1000 Network Driver
10537 05:57:33.462683 <6>[ 1.575507] e1000: Copyright (c) 1999-2006 Intel Corporation.
10538 05:57:33.466049 <6>[ 1.581520] e1000e: Intel(R) PRO/1000 Network Driver
10539 05:57:33.472687 <6>[ 1.586736] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10540 05:57:33.479385 <6>[ 1.592921] igb: Intel(R) Gigabit Ethernet Network Driver
10541 05:57:33.486409 <6>[ 1.598572] igb: Copyright (c) 2007-2014 Intel Corporation.
10542 05:57:33.492663 <6>[ 1.604410] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10543 05:57:33.499118 <6>[ 1.610929] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10544 05:57:33.502589 <6>[ 1.617393] sky2: driver version 1.30
10545 05:57:33.509282 <6>[ 1.622387] VFIO - User Level meta-driver version: 0.3
10546 05:57:33.516875 <6>[ 1.630656] usbcore: registered new interface driver usb-storage
10547 05:57:33.523201 <6>[ 1.637102] usbcore: registered new device driver onboard-usb-hub
10548 05:57:33.532408 <6>[ 1.646267] mt6397-rtc mt6359-rtc: registered as rtc0
10549 05:57:33.542180 <6>[ 1.651727] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-25T05:56:51 UTC (1703483811)
10550 05:57:33.545418 <6>[ 1.661300] i2c_dev: i2c /dev entries driver
10551 05:57:33.562472 <6>[ 1.673079] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10552 05:57:33.581975 <6>[ 1.696073] cpu cpu0: EM: created perf domain
10553 05:57:33.585295 <6>[ 1.701009] cpu cpu4: EM: created perf domain
10554 05:57:33.592482 <6>[ 1.706640] sdhci: Secure Digital Host Controller Interface driver
10555 05:57:33.599293 <6>[ 1.713069] sdhci: Copyright(c) Pierre Ossman
10556 05:57:33.605904 <6>[ 1.718026] Synopsys Designware Multimedia Card Interface Driver
10557 05:57:33.612612 <6>[ 1.724665] sdhci-pltfm: SDHCI platform and OF driver helper
10558 05:57:33.616309 <6>[ 1.724802] mmc0: CQHCI version 5.10
10559 05:57:33.622650 <6>[ 1.735019] ledtrig-cpu: registered to indicate activity on CPUs
10560 05:57:33.629658 <6>[ 1.742596] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10561 05:57:33.636280 <6>[ 1.749974] usbcore: registered new interface driver usbhid
10562 05:57:33.638890 <6>[ 1.755799] usbhid: USB HID core driver
10563 05:57:33.649217 <6>[ 1.760007] spi_master spi0: will run message pump with realtime priority
10564 05:57:33.690591 <6>[ 1.798128] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10565 05:57:33.709801 <6>[ 1.814157] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10566 05:57:33.713986 <6>[ 1.827713] mmc0: Command Queue Engine enabled
10567 05:57:33.720558 <6>[ 1.832455] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10568 05:57:33.727428 <6>[ 1.839593] cros-ec-spi spi0.0: Chrome EC device registered
10569 05:57:33.730599 <6>[ 1.839809] mmcblk0: mmc0:0001 DA4128 116 GiB
10570 05:57:33.740961 <6>[ 1.855430] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10571 05:57:33.749080 <6>[ 1.863125] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10572 05:57:33.755340 <6>[ 1.869083] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10573 05:57:33.762426 <6>[ 1.875188] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10574 05:57:33.776068 <6>[ 1.886867] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10575 05:57:33.783708 <6>[ 1.897595] NET: Registered PF_PACKET protocol family
10576 05:57:33.787062 <6>[ 1.903035] 9pnet: Installing 9P2000 support
10577 05:57:33.793556 <5>[ 1.907623] Key type dns_resolver registered
10578 05:57:33.796586 <6>[ 1.912711] registered taskstats version 1
10579 05:57:33.803244 <5>[ 1.917108] Loading compiled-in X.509 certificates
10580 05:57:33.837109 <4>[ 1.944698] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10581 05:57:33.847177 <4>[ 1.955524] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10582 05:57:33.853974 <3>[ 1.966065] debugfs: File 'uA_load' in directory '/' already present!
10583 05:57:33.860539 <3>[ 1.972764] debugfs: File 'min_uV' in directory '/' already present!
10584 05:57:33.867378 <3>[ 1.979371] debugfs: File 'max_uV' in directory '/' already present!
10585 05:57:33.874176 <3>[ 1.985978] debugfs: File 'constraint_flags' in directory '/' already present!
10586 05:57:33.884998 <3>[ 1.995596] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10587 05:57:33.893571 <6>[ 2.008054] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10588 05:57:33.900680 <6>[ 2.015003] xhci-mtk 11200000.usb: xHCI Host Controller
10589 05:57:33.907330 <6>[ 2.020504] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10590 05:57:33.917438 <6>[ 2.028340] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10591 05:57:33.923993 <6>[ 2.037758] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10592 05:57:33.930629 <6>[ 2.043848] xhci-mtk 11200000.usb: xHCI Host Controller
10593 05:57:33.937698 <6>[ 2.049329] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10594 05:57:33.944252 <6>[ 2.056976] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10595 05:57:33.950834 <6>[ 2.064614] hub 1-0:1.0: USB hub found
10596 05:57:33.954019 <6>[ 2.068625] hub 1-0:1.0: 1 port detected
10597 05:57:33.960681 <6>[ 2.072894] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10598 05:57:33.967616 <6>[ 2.081437] hub 2-0:1.0: USB hub found
10599 05:57:33.970775 <6>[ 2.085440] hub 2-0:1.0: 1 port detected
10600 05:57:33.979967 <6>[ 2.093824] mtk-msdc 11f70000.mmc: Got CD GPIO
10601 05:57:33.991064 <6>[ 2.101751] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10602 05:57:33.997695 <6>[ 2.109793] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10603 05:57:34.007427 <4>[ 2.117784] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10604 05:57:34.017551 <6>[ 2.127316] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10605 05:57:34.024014 <6>[ 2.135399] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10606 05:57:34.030802 <6>[ 2.143416] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10607 05:57:34.040538 <6>[ 2.151331] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10608 05:57:34.047475 <6>[ 2.159148] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10609 05:57:34.057077 <6>[ 2.166967] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10610 05:57:34.066926 <6>[ 2.177336] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10611 05:57:34.073812 <6>[ 2.185695] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10612 05:57:34.083929 <6>[ 2.194033] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10613 05:57:34.090136 <6>[ 2.202371] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10614 05:57:34.099999 <6>[ 2.210711] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10615 05:57:34.106942 <6>[ 2.219050] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10616 05:57:34.117145 <6>[ 2.227387] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10617 05:57:34.123520 <6>[ 2.235726] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10618 05:57:34.133708 <6>[ 2.244065] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10619 05:57:34.140394 <6>[ 2.252411] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10620 05:57:34.150276 <6>[ 2.260750] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10621 05:57:34.156784 <6>[ 2.269099] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10622 05:57:34.167006 <6>[ 2.277437] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10623 05:57:34.173754 <6>[ 2.285775] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10624 05:57:34.184056 <6>[ 2.294117] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10625 05:57:34.190581 <6>[ 2.302833] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10626 05:57:34.196928 <6>[ 2.309970] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10627 05:57:34.203769 <6>[ 2.316722] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10628 05:57:34.210245 <6>[ 2.323475] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10629 05:57:34.217248 <6>[ 2.330417] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10630 05:57:34.226764 <6>[ 2.337255] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10631 05:57:34.236993 <6>[ 2.346386] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10632 05:57:34.246465 <6>[ 2.355504] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10633 05:57:34.253560 <6>[ 2.364797] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10634 05:57:34.263715 <6>[ 2.374268] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10635 05:57:34.273806 <6>[ 2.383735] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10636 05:57:34.283309 <6>[ 2.392854] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10637 05:57:34.293071 <6>[ 2.402323] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10638 05:57:34.300157 <6>[ 2.411442] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10639 05:57:34.312974 <6>[ 2.420735] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10640 05:57:34.323020 <6>[ 2.430895] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10641 05:57:34.333221 <6>[ 2.442762] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10642 05:57:34.339323 <6>[ 2.452320] Trying to probe devices needed for running init ...
10643 05:57:34.359649 <6>[ 2.470838] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10644 05:57:34.388286 <6>[ 2.502533] hub 2-1:1.0: USB hub found
10645 05:57:34.391546 <6>[ 2.507041] hub 2-1:1.0: 3 ports detected
10646 05:57:34.399981 <6>[ 2.514279] hub 2-1:1.0: USB hub found
10647 05:57:34.402949 <6>[ 2.518716] hub 2-1:1.0: 3 ports detected
10648 05:57:34.511432 <6>[ 2.622791] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10649 05:57:34.666041 <6>[ 2.780461] hub 1-1:1.0: USB hub found
10650 05:57:34.669357 <6>[ 2.784870] hub 1-1:1.0: 4 ports detected
10651 05:57:34.678284 <6>[ 2.792621] hub 1-1:1.0: USB hub found
10652 05:57:34.681242 <6>[ 2.797135] hub 1-1:1.0: 4 ports detected
10653 05:57:34.747940 <6>[ 2.858897] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10654 05:57:35.003409 <6>[ 3.114826] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10655 05:57:35.136247 <6>[ 3.250790] hub 1-1.4:1.0: USB hub found
10656 05:57:35.140006 <6>[ 3.255471] hub 1-1.4:1.0: 2 ports detected
10657 05:57:35.149822 <6>[ 3.264172] hub 1-1.4:1.0: USB hub found
10658 05:57:35.153441 <6>[ 3.268781] hub 1-1.4:1.0: 2 ports detected
10659 05:57:35.451391 <6>[ 3.562803] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10660 05:57:35.643556 <6>[ 3.754802] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10661 05:57:46.616196 <6>[ 14.735812] ALSA device list:
10662 05:57:46.623039 <6>[ 14.739107] No soundcards found.
10663 05:57:46.630922 <6>[ 14.747000] Freeing unused kernel memory: 8448K
10664 05:57:46.633994 <6>[ 14.752103] Run /init as init process
10665 05:57:46.645443 Loading, please wait...
10666 05:57:46.666742 Starting version 247.3-7+deb11u2
10667 05:57:46.852905 <6>[ 14.965972] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10668 05:57:46.863071 <3>[ 14.976069] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 05:57:46.874795 <3>[ 14.987062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 05:57:46.884318 <4>[ 14.996828] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10671 05:57:46.890898 <3>[ 14.997939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 05:57:46.905784 <6>[ 15.018143] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10673 05:57:46.912165 <3>[ 15.019151] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 05:57:46.918974 <4>[ 15.019157] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10675 05:57:46.928645 <6>[ 15.025773] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10676 05:57:46.935412 <6>[ 15.027201] remoteproc remoteproc0: scp is available
10677 05:57:46.938648 <6>[ 15.027267] remoteproc remoteproc0: powering up scp
10678 05:57:46.948758 <6>[ 15.027271] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10679 05:57:46.952076 <6>[ 15.027285] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10680 05:57:46.962761 <6>[ 15.031480] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10681 05:57:46.969441 <3>[ 15.033837] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 05:57:46.972908 <6>[ 15.036447] mc: Linux media interface: v0.10
10683 05:57:46.982844 <6>[ 15.041148] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10684 05:57:46.989517 <6>[ 15.045026] usbcore: registered new interface driver r8152
10685 05:57:46.996170 <3>[ 15.049812] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 05:57:47.003309 <6>[ 15.061084] videodev: Linux video capture interface: v2.00
10687 05:57:47.009932 <4>[ 15.068066] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10688 05:57:47.016688 <4>[ 15.068066] Fallback method does not support PEC.
10689 05:57:47.023162 <3>[ 15.068601] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 05:57:47.033327 <3>[ 15.068610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 05:57:47.039809 <3>[ 15.068671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 05:57:47.049673 <3>[ 15.084712] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10693 05:57:47.055889 <3>[ 15.090054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 05:57:47.066067 <6>[ 15.106962] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10695 05:57:47.075816 <3>[ 15.108960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 05:57:47.082714 <3>[ 15.108963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 05:57:47.092977 <3>[ 15.109014] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 05:57:47.099479 <3>[ 15.109027] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 05:57:47.106185 <3>[ 15.109030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 05:57:47.116044 <3>[ 15.109034] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 05:57:47.122896 <3>[ 15.109040] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 05:57:47.132595 <3>[ 15.109075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 05:57:47.142472 <6>[ 15.117938] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10704 05:57:47.149426 <3>[ 15.128552] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10705 05:57:47.155800 <6>[ 15.130940] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10706 05:57:47.165652 <6>[ 15.134766] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10707 05:57:47.175331 <4>[ 15.149308] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10708 05:57:47.182193 <6>[ 15.160840] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10709 05:57:47.191984 <6>[ 15.160869] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10710 05:57:47.198962 <6>[ 15.160876] remoteproc remoteproc0: remote processor scp is now up
10711 05:57:47.205443 <4>[ 15.170638] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10712 05:57:47.211946 <6>[ 15.176372] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10713 05:57:47.218375 <6>[ 15.176382] pci_bus 0000:00: root bus resource [bus 00-ff]
10714 05:57:47.225393 <6>[ 15.176390] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10715 05:57:47.234888 <6>[ 15.176398] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10716 05:57:47.241383 <6>[ 15.176435] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10717 05:57:47.247869 <6>[ 15.176455] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10718 05:57:47.251144 <6>[ 15.176538] pci 0000:00:00.0: supports D1 D2
10719 05:57:47.261082 <6>[ 15.176542] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10720 05:57:47.267797 <6>[ 15.178175] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10721 05:57:47.274842 <6>[ 15.179059] usbcore: registered new interface driver cdc_ether
10722 05:57:47.277643 <6>[ 15.189507] Bluetooth: Core ver 2.22
10723 05:57:47.284233 <6>[ 15.189617] usbcore: registered new interface driver r8153_ecm
10724 05:57:47.290891 <6>[ 15.196793] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10725 05:57:47.294726 <6>[ 15.204445] NET: Registered PF_BLUETOOTH protocol family
10726 05:57:47.304238 <6>[ 15.206397] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10727 05:57:47.311180 <6>[ 15.208255] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10728 05:57:47.321160 <6>[ 15.212713] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10729 05:57:47.327615 <6>[ 15.220515] Bluetooth: HCI device and connection manager initialized
10730 05:57:47.331054 <6>[ 15.220534] Bluetooth: HCI socket layer initialized
10731 05:57:47.337438 <6>[ 15.221210] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10732 05:57:47.344229 <6>[ 15.221684] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10733 05:57:47.357274 <6>[ 15.222875] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10734 05:57:47.364198 <6>[ 15.223038] usbcore: registered new interface driver uvcvideo
10735 05:57:47.370651 <6>[ 15.228732] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10736 05:57:47.377439 <6>[ 15.236690] Bluetooth: L2CAP socket layer initialized
10737 05:57:47.380261 <6>[ 15.236701] Bluetooth: SCO socket layer initialized
10738 05:57:47.387281 <6>[ 15.287610] usbcore: registered new interface driver btusb
10739 05:57:47.397486 <4>[ 15.288619] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10740 05:57:47.403846 <3>[ 15.288634] Bluetooth: hci0: Failed to load firmware file (-2)
10741 05:57:47.410676 <3>[ 15.288640] Bluetooth: hci0: Failed to set up firmware (-2)
10742 05:57:47.420560 <4>[ 15.288647] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10743 05:57:47.427105 <6>[ 15.296226] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10744 05:57:47.433714 <6>[ 15.548735] pci 0000:01:00.0: supports D1 D2
10745 05:57:47.440388 <6>[ 15.553344] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10746 05:57:47.454916 <6>[ 15.570782] r8152 2-1.3:1.0 eth0: v1.12.13
10747 05:57:47.461403 <6>[ 15.572255] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10748 05:57:47.468127 <6>[ 15.582169] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10749 05:57:47.474985 <6>[ 15.586881] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10750 05:57:47.484560 <6>[ 15.590269] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10751 05:57:47.491322 <6>[ 15.604329] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10752 05:57:47.497789 <6>[ 15.612331] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10753 05:57:47.507880 <6>[ 15.620331] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10754 05:57:47.511425 <6>[ 15.628331] pci 0000:00:00.0: PCI bridge to [bus 01]
10755 05:57:47.521123 <6>[ 15.633548] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10756 05:57:47.527888 <6>[ 15.641673] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10757 05:57:47.534506 <6>[ 15.648507] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10758 05:57:47.540835 <6>[ 15.655516] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10759 05:57:47.576418 <5>[ 15.689079] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10760 05:57:47.595574 <5>[ 15.708128] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10761 05:57:47.602091 <4>[ 15.715053] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10762 05:57:47.608804 <6>[ 15.723962] cfg80211: failed to load regulatory.db
10763 05:57:47.670270 <6>[ 15.782673] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10764 05:57:47.676501 <6>[ 15.790223] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10765 05:57:47.700851 <6>[ 15.817018] mt7921e 0000:01:00.0: ASIC revision: 79610010
10766 05:57:47.806073 <6>[ 15.918985] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10767 05:57:47.809308 <6>[ 15.918985]
10768 05:57:47.812801 Begin: Loading essential drivers ... done.
10769 05:57:47.819768 Begin: Running /scripts/init-premount ... done.
10770 05:57:47.826210 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10771 05:57:47.832812 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10772 05:57:47.839453 Device /sys/class/net/enx00e04c722dd6 found
10773 05:57:47.839912 done.
10774 05:57:47.878033 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10775 05:57:48.073498 <6>[ 16.186280] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10776 05:57:48.801369 <6>[ 16.917739] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10777 05:57:48.916282 <6>[ 17.032487] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10778 05:57:49.035798 IP-Config: no response after 2 secs - giving up
10779 05:57:49.066724 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:7b mtu 1500 DHCP
10780 05:57:49.793902 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10781 05:57:49.796777 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10782 05:57:49.803633 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10783 05:57:49.813707 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10784 05:57:49.820139 host : mt8192-asurada-spherion-r0-cbg-1
10785 05:57:49.826742 domain : lava-rack
10786 05:57:49.829694 rootserver: 192.168.201.1 rootpath:
10787 05:57:49.830133 filename :
10788 05:57:49.942324 done.
10789 05:57:49.949122 Begin: Running /scripts/nfs-bottom ... done.
10790 05:57:49.966597 Begin: Running /scripts/init-bottom ... done.
10791 05:57:51.137571 <6>[ 19.254091] NET: Registered PF_INET6 protocol family
10792 05:57:51.145264 <6>[ 19.261881] Segment Routing with IPv6
10793 05:57:51.148506 <6>[ 19.265878] In-situ OAM (IOAM) with IPv6
10794 05:57:51.266854 <30>[ 19.363747] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10795 05:57:51.269807 <30>[ 19.388137] systemd[1]: Detected architecture arm64.
10796 05:57:51.290753
10797 05:57:51.293730 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10798 05:57:51.293825
10799 05:57:51.316222 <30>[ 19.432852] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10800 05:57:52.079141 <30>[ 20.192479] systemd[1]: Queued start job for default target Graphical Interface.
10801 05:57:52.112203 <30>[ 20.229182] systemd[1]: Created slice system-getty.slice.
10802 05:57:52.118926 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10803 05:57:52.135420 <30>[ 20.252169] systemd[1]: Created slice system-modprobe.slice.
10804 05:57:52.141900 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10805 05:57:52.158999 <30>[ 20.276021] systemd[1]: Created slice system-serial\x2dgetty.slice.
10806 05:57:52.169159 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10807 05:57:52.182808 <30>[ 20.299864] systemd[1]: Created slice User and Session Slice.
10808 05:57:52.189757 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10809 05:57:52.209798 <30>[ 20.323254] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10810 05:57:52.219999 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10811 05:57:52.237603 <30>[ 20.351011] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10812 05:57:52.243769 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10813 05:57:52.264525 <30>[ 20.374923] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10814 05:57:52.271362 <30>[ 20.387090] systemd[1]: Reached target Local Encrypted Volumes.
10815 05:57:52.277821 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10816 05:57:52.294149 <30>[ 20.410933] systemd[1]: Reached target Paths.
10817 05:57:52.297296 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10818 05:57:52.314016 <30>[ 20.430790] systemd[1]: Reached target Remote File Systems.
10819 05:57:52.320205 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10820 05:57:52.338548 <30>[ 20.455155] systemd[1]: Reached target Slices.
10821 05:57:52.344887 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10822 05:57:52.357882 <30>[ 20.474849] systemd[1]: Reached target Swap.
10823 05:57:52.361407 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10824 05:57:52.382140 <30>[ 20.495364] systemd[1]: Listening on initctl Compatibility Named Pipe.
10825 05:57:52.388212 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10826 05:57:52.394945 <30>[ 20.511354] systemd[1]: Listening on Journal Audit Socket.
10827 05:57:52.401665 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10828 05:57:52.419264 <30>[ 20.535938] systemd[1]: Listening on Journal Socket (/dev/log).
10829 05:57:52.425766 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10830 05:57:52.443520 <30>[ 20.560046] systemd[1]: Listening on Journal Socket.
10831 05:57:52.450024 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10832 05:57:52.466789 <30>[ 20.580374] systemd[1]: Listening on Network Service Netlink Socket.
10833 05:57:52.473393 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10834 05:57:52.488263 <30>[ 20.605194] systemd[1]: Listening on udev Control Socket.
10835 05:57:52.495083 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10836 05:57:52.510541 <30>[ 20.627231] systemd[1]: Listening on udev Kernel Socket.
10837 05:57:52.517013 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10838 05:57:52.574159 <30>[ 20.690948] systemd[1]: Mounting Huge Pages File System...
10839 05:57:52.580579 Mounting [0;1;39mHuge Pages File System[0m...
10840 05:57:52.598943 <30>[ 20.715615] systemd[1]: Mounting POSIX Message Queue File System...
10841 05:57:52.605574 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10842 05:57:52.626439 <30>[ 20.743538] systemd[1]: Mounting Kernel Debug File System...
10843 05:57:52.633119 Mounting [0;1;39mKernel Debug File System[0m...
10844 05:57:52.649870 <30>[ 20.763484] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10845 05:57:52.665507 <30>[ 20.779032] systemd[1]: Starting Create list of static device nodes for the current kernel...
10846 05:57:52.671878 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10847 05:57:52.694779 <30>[ 20.811521] systemd[1]: Starting Load Kernel Module configfs...
10848 05:57:52.701459 Starting [0;1;39mLoad Kernel Module configfs[0m...
10849 05:57:52.738492 <30>[ 20.855142] systemd[1]: Starting Load Kernel Module drm...
10850 05:57:52.744638 Starting [0;1;39mLoad Kernel Module drm[0m...
10851 05:57:52.763079 <30>[ 20.879565] systemd[1]: Starting Load Kernel Module fuse...
10852 05:57:52.769437 Starting [0;1;39mLoad Kernel Module fuse[0m...
10853 05:57:52.801312 <6>[ 20.917888] fuse: init (API version 7.37)
10854 05:57:52.811412 <30>[ 20.918748] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10855 05:57:52.859456 <30>[ 20.975598] systemd[1]: Starting Journal Service...
10856 05:57:52.866043 Starting [0;1;39mJournal Service[0m...
10857 05:57:52.887120 <30>[ 21.003737] systemd[1]: Starting Load Kernel Modules...
10858 05:57:52.893522 Starting [0;1;39mLoad Kernel Modules[0m...
10859 05:57:52.912576 <30>[ 21.025819] systemd[1]: Starting Remount Root and Kernel File Systems...
10860 05:57:52.918888 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10861 05:57:52.955765 <30>[ 21.071955] systemd[1]: Starting Coldplug All udev Devices...
10862 05:57:52.961824 Starting [0;1;39mColdplug All udev Devices[0m...
10863 05:57:52.978083 <30>[ 21.094756] systemd[1]: Mounted Huge Pages File System.
10864 05:57:52.985119 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10865 05:57:52.998316 <30>[ 21.115109] systemd[1]: Mounted POSIX Message Queue File System.
10866 05:57:53.004883 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10867 05:57:53.023375 <30>[ 21.139656] systemd[1]: Mounted Kernel Debug File System.
10868 05:57:53.037015 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<3>[ 21.149124] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10869 05:57:53.039950 g File System[0m.
10870 05:57:53.059029 <30>[ 21.171608] systemd[1]: Finished Create list of static device nodes for the current kernel.
10871 05:57:53.068920 [[0;32m OK [<3>[ 21.181601] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 05:57:53.075675 0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10873 05:57:53.091059 <30>[ 21.207732] systemd[1]: modprobe@configfs.service: Succeeded.
10874 05:57:53.098124 <30>[ 21.214599] systemd[1]: Finished Load Kernel Module configfs.
10875 05:57:53.104801 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10876 05:57:53.119690 <30>[ 21.235892] systemd[1]: modprobe@drm.service: Succeeded.
10877 05:57:53.130148 <3>[ 21.237418] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 05:57:53.132794 <30>[ 21.242234] systemd[1]: Finished Load Kernel Module drm.
10879 05:57:53.140040 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10880 05:57:53.155547 <30>[ 21.272155] systemd[1]: modprobe@fuse.service: Succeeded.
10881 05:57:53.165616 <3>[ 21.272867] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 05:57:53.172430 <30>[ 21.279312] systemd[1]: Finished Load Kernel Module fuse.
10883 05:57:53.178536 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10884 05:57:53.195636 <3>[ 21.308398] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 05:57:53.203478 <30>[ 21.319846] systemd[1]: Finished Load Kernel Modules.
10886 05:57:53.209993 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10887 05:57:53.225971 <3>[ 21.338778] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 05:57:53.232202 <30>[ 21.340386] systemd[1]: Finished Remount Root and Kernel File Systems.
10889 05:57:53.238955 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10890 05:57:53.256186 <3>[ 21.369088] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 05:57:53.291391 <3>[ 21.404356] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 05:57:53.297883 <30>[ 21.409381] systemd[1]: Mounting FUSE Control File System...
10893 05:57:53.304595 Mounting [0;1;39mFUSE Control File System[0m...
10894 05:57:53.324028 <3>[ 21.437222] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 05:57:53.330656 <30>[ 21.439831] systemd[1]: Mounting Kernel Configuration File System...
10896 05:57:53.336995 Mounting [0;1;39mKernel Configuration File System[0m...
10897 05:57:53.356436 <3>[ 21.469894] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 05:57:53.372171 <30>[ 21.485181] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10899 05:57:53.381878 <30>[ 21.494340] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10900 05:57:53.419520 <30>[ 21.535112] systemd[1]: Starting Load/Save Random Seed...
10901 05:57:53.422751 Starting [0;1;39mLoad/Save Random Seed[0m...
10902 05:57:53.442918 <30>[ 21.558798] systemd[1]: Starting Apply Kernel Variables...
10903 05:57:53.459408 <4>[ 21.563868] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10904 05:57:53.465642 <3>[ 21.580342] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10905 05:57:53.472368 Starting [0;1;39mApply Kernel Variables[0m...
10906 05:57:53.494876 <30>[ 21.611489] systemd[1]: Starting Create System Users...
10907 05:57:53.501158 Starting [0;1;39mCreate System Users[0m...
10908 05:57:53.517386 <30>[ 21.634109] systemd[1]: Started Journal Service.
10909 05:57:53.523709 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10910 05:57:53.548830 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10911 05:57:53.561767 See 'systemctl status systemd-udev-trigger.service' for details.
10912 05:57:53.578596 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10913 05:57:53.599590 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10914 05:57:53.620447 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10915 05:57:53.640820 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10916 05:57:53.660883 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10917 05:57:53.699262 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10918 05:57:53.720516 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10919 05:57:53.743257 <46>[ 21.857221] systemd-journald[299]: Received client request to flush runtime journal.
10920 05:57:54.601273 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10921 05:57:54.614709 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10922 05:57:54.629929 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10923 05:57:54.673552 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10924 05:57:55.161604 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10925 05:57:55.207016 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10926 05:57:55.259814 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10927 05:57:55.319817 Starting [0;1;39mNetwork Service[0m...
10928 05:57:55.619596 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10929 05:57:55.678060 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10930 05:57:55.698470 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10931 05:57:55.891188 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10932 05:57:55.930347 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10933 05:57:55.959881 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10934 05:57:56.021391 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10935 05:57:56.038911 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10936 05:57:56.058227 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10937 05:57:56.078908 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10938 05:57:56.147040 Starting [0;1;39mNetwork Name Resolution[0m...
10939 05:57:56.176115 Starting [0;1;39mNetwork Time Synchronization[0m...
10940 05:57:56.195809 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10941 05:57:56.314775 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10942 05:57:56.628244 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10943 05:57:56.649874 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10944 05:57:56.673281 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10945 05:57:56.685834 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10946 05:57:56.701407 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10947 05:57:56.729517 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10948 05:57:56.756660 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10949 05:57:56.777563 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10950 05:57:56.797336 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10951 05:57:56.810314 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10952 05:57:56.832402 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10953 05:57:56.845722 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10954 05:57:56.862290 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10955 05:57:56.910511 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10956 05:57:57.014881 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10957 05:57:57.054238 Starting [0;1;39mUser Login Management[0m...
10958 05:57:57.070290 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10959 05:57:57.090870 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10960 05:57:57.111733 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10961 05:57:57.156240 Starting [0;1;39mPermit User Sessions[0m...
10962 05:57:57.259976 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10963 05:57:57.300764 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10964 05:57:57.321425 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10965 05:57:57.343039 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10966 05:57:57.371499 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10967 05:57:57.392754 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10968 05:57:57.416503 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10969 05:57:57.438156 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10970 05:57:57.492752 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10971 05:57:57.556638 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10972 05:57:57.637202
10973 05:57:57.637738
10974 05:57:57.640064 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10975 05:57:57.640543
10976 05:57:57.643402 debian-bullseye-arm64 login: root (automatic login)
10977 05:57:57.643829
10978 05:57:57.644191
10979 05:57:57.940538 Linux debian-bullseye-arm64 6.1.67-cip12 #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023 aarch64
10980 05:57:57.941107
10981 05:57:57.946788 The programs included with the Debian GNU/Linux system are free software;
10982 05:57:57.953637 the exact distribution terms for each program are described in the
10983 05:57:57.956874 individual files in /usr/share/doc/*/copyright.
10984 05:57:57.957341
10985 05:57:57.963640 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10986 05:57:57.966545 permitted by applicable law.
10987 05:57:58.039887 Matched prompt #10: / #
10989 05:57:58.040127 Setting prompt string to ['/ #']
10990 05:57:58.040221 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10992 05:57:58.040442 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10993 05:57:58.040542 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
10994 05:57:58.040611 Setting prompt string to ['/ #']
10995 05:57:58.040671 Forcing a shell prompt, looking for ['/ #']
10997 05:57:58.090989 / #
10998 05:57:58.091656 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10999 05:57:58.092186 Waiting using forced prompt support (timeout 00:02:30)
11000 05:57:58.097138
11001 05:57:58.098163 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11002 05:57:58.098698 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
11004 05:57:58.199951 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12379447/extract-nfsrootfs-4f4eeh_n'
11005 05:57:58.206530 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12379447/extract-nfsrootfs-4f4eeh_n'
11007 05:57:58.308384 / # export NFS_SERVER_IP='192.168.201.1'
11008 05:57:58.314907 export NFS_SERVER_IP='192.168.201.1'
11009 05:57:58.315846 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11010 05:57:58.316361 end: 2.2 depthcharge-retry (duration 00:01:30) [common]
11011 05:57:58.316939 end: 2 depthcharge-action (duration 00:01:30) [common]
11012 05:57:58.317435 start: 3 lava-test-retry (timeout 00:30:00) [common]
11013 05:57:58.317910 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11014 05:57:58.318374 Using namespace: common
11016 05:57:58.419640 / # #
11017 05:57:58.420261 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11018 05:57:58.426175 #
11019 05:57:58.427041 Using /lava-12379447
11021 05:57:58.528341 / # export SHELL=/bin/sh
11022 05:57:58.534737 export SHELL=/bin/sh
11024 05:57:58.636593 / # . /lava-12379447/environment
11025 05:57:58.642766 . /lava-12379447/environment
11027 05:57:58.750302 / # /lava-12379447/bin/lava-test-runner /lava-12379447/0
11028 05:57:58.750975 Test shell timeout: 10s (minimum of the action and connection timeout)
11029 05:57:58.756568 /lava-12379447/bin/lava-test-runner /lava-12379447/0
11030 05:57:58.986898 + export TESTRUN_ID=0_lc-compliance
11031 05:57:58.993309 + cd /lava-12379447/0/tests/0_lc-compliance
11032 05:57:58.993894 + cat uuid
11033 05:57:59.000015 + UUID=12379447_1.6.2.3.1
11034 05:57:59.000459 + set +x
11035 05:57:59.006589 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 12379447_1.6.2.3.1>
11036 05:57:59.007308 Received signal: <STARTRUN> 0_lc-compliance 12379447_1.6.2.3.1
11037 05:57:59.007716 Starting test lava.0_lc-compliance (12379447_1.6.2.3.1)
11038 05:57:59.008143 Skipping test definition patterns.
11039 05:57:59.010194 + /usr/bin/lc-compliance-parser.sh
11040 05:58:00.223620 [0:00:28.278370423] [409] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:297 [0mlibcamera v0.0.0+1-1f607da9
11041 05:58:00.227089 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11042 05:58:00.240991 [0:00:28.294986443] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11043 05:58:00.299564 [0:00:28.355609802] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11044 05:58:00.310648 [==========] Running 120 tests from 1 test suite.
11045 05:58:00.354280 [0:00:28.411062799] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11046 05:58:00.382912 [----------] Global test environment set-up.
11047 05:58:00.406650 [0:00:28.463852789] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11048 05:58:00.457491 [----------] 120 tests from CaptureTests/SingleStream
11049 05:58:00.525502 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11050 05:58:00.585824 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11051 05:58:00.586609 Received signal: <TESTSET> START CaptureTests/SingleStream
11052 05:58:00.586980 Starting test_set CaptureTests/SingleStream
11053 05:58:00.589303 Camera needs 4 requests, can't test only 1
11054 05:58:00.660734 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11055 05:58:00.734695
11056 05:58:00.812558 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (61 ms)
11057 05:58:00.835139 [0:00:28.897167170] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11058 05:58:00.910475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11059 05:58:00.910771 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11061 05:58:00.922422 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11062 05:58:00.961710 Camera needs 4 requests, can't test only 2
11063 05:58:01.031213 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11064 05:58:01.097389
11065 05:58:01.162829 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (55 ms)
11066 05:58:01.246503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11067 05:58:01.246856 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11069 05:58:01.260188 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11070 05:58:01.299796 [0:00:29.369472336] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11071 05:58:01.318199 Camera needs 4 requests, can't test only 3
11072 05:58:01.390833 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11073 05:58:01.461379
11074 05:58:01.541978 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (53 ms)
11075 05:58:01.622271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11076 05:58:01.622709 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11078 05:58:01.636361 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11079 05:58:01.681860 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (433 ms)
11080 05:58:01.765457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11081 05:58:01.765787 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11083 05:58:01.778561 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11084 05:58:01.821815 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (473 ms)
11085 05:58:01.888214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11086 05:58:01.888528 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11088 05:58:01.898792 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11089 05:58:01.986797 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (704 ms)
11090 05:58:01.996511 [0:00:30.074378492] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11091 05:58:02.065683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11092 05:58:02.066031 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11094 05:58:02.078317 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11095 05:58:02.981867 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1005 ms)
11096 05:58:02.991590 [0:00:31.079486575] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11097 05:58:03.076321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11098 05:58:03.077088 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11100 05:58:03.092592 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11101 05:58:04.409042 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1440 ms)
11102 05:58:04.419016 [0:00:32.519934229] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11103 05:58:04.496200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11104 05:58:04.496483 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11106 05:58:04.509803 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11107 05:58:06.503185 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2109 ms)
11108 05:58:06.512945 [0:00:34.629956167] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11109 05:58:06.594744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11110 05:58:06.595454 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11112 05:58:06.611223 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11113 05:58:09.666567 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3181 ms)
11114 05:58:09.676616 [0:00:37.810703702] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11115 05:58:09.727837 [0:00:37.862961503] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11116 05:58:09.762088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11117 05:58:09.762801 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11119 05:58:09.781371 [0:00:37.917000142] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11120 05:58:09.784523 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11121 05:58:09.836096 [0:00:37.971354747] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11122 05:58:09.839287 Camera needs 4 requests, can't test only 1
11123 05:58:09.909027 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11124 05:58:09.982400
11125 05:58:10.065202 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (54 ms)
11126 05:58:10.158690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11127 05:58:10.159417 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11129 05:58:10.175172 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11130 05:58:10.198796 [0:00:38.335638950] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11131 05:58:10.230298 Camera needs 4 requests, can't test only 2
11132 05:58:10.304373 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11133 05:58:10.370295
11134 05:58:10.428894 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (53 ms)
11135 05:58:10.518037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11136 05:58:10.518873 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11138 05:58:10.533992 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11139 05:58:10.591116 Camera needs 4 requests, can't test only 3
11140 05:58:10.663736 [0:00:38.802351352] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11141 05:58:10.674307 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11142 05:58:10.742401
11143 05:58:10.817073 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (54 ms)
11144 05:58:10.896723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11145 05:58:10.897021 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11147 05:58:10.908987 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11148 05:58:10.951475 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (364 ms)
11149 05:58:11.012853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11150 05:58:11.013151 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11152 05:58:11.024536 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11153 05:58:11.063445 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (466 ms)
11154 05:58:11.126086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11155 05:58:11.126377 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11157 05:58:11.135908 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11158 05:58:11.350804 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (698 ms)
11159 05:58:11.363598 [0:00:39.500765639] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11160 05:58:11.416926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11161 05:58:11.417218 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11163 05:58:11.428114 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11164 05:58:12.247829 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (900 ms)
11165 05:58:12.260665 [0:00:40.401616661] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11166 05:58:12.319978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11167 05:58:12.320256 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11169 05:58:12.331440 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11170 05:58:13.642386 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1398 ms)
11171 05:58:13.655802 [0:00:41.799699483] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11172 05:58:13.714939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11173 05:58:13.715215 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11175 05:58:13.725444 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11176 05:58:15.738154 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2099 ms)
11177 05:58:15.751045 [0:00:43.899595085] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11178 05:58:15.811655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11179 05:58:15.811970 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11181 05:58:15.821370 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11182 05:58:17.877768 <6>[ 46.000849] vpu: disabling
11183 05:58:17.880979 <6>[ 46.003950] vproc2: disabling
11184 05:58:17.884374 <6>[ 46.007279] vproc1: disabling
11185 05:58:17.887563 <6>[ 46.010623] vaud18: disabling
11186 05:58:17.894226 <6>[ 46.014139] vsram_others: disabling
11187 05:58:17.897744 <6>[ 46.018102] va09: disabling
11188 05:58:17.900698 <6>[ 46.021269] vsram_md: disabling
11189 05:58:17.904278 <6>[ 46.024836] Vgpu: disabling
11190 05:58:18.964955 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3233 ms)
11191 05:58:18.978286 [0:00:47.131894369] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11192 05:58:19.026290 [0:00:47.184970443] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11193 05:58:19.034748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11194 05:58:19.035079 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11196 05:58:19.044243 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11197 05:58:19.080227 [0:00:47.238837100] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11198 05:58:19.083589 Camera needs 4 requests, can't test only 1
11199 05:58:19.134666 [0:00:47.293266700] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11200 05:58:19.138118 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11201 05:58:19.189534
11202 05:58:19.245107 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (53 ms)
11203 05:58:19.309878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11204 05:58:19.310206 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11206 05:58:19.319259 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11207 05:58:19.354861 Camera needs 4 requests, can't test only 2
11208 05:58:19.410510 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11209 05:58:19.465460
11210 05:58:19.498771 [0:00:47.657820269] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11211 05:58:19.529730 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (54 ms)
11212 05:58:19.593887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11213 05:58:19.594205 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11215 05:58:19.605248 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11216 05:58:19.640811 Camera needs 4 requests, can't test only 3
11217 05:58:19.692353 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11218 05:58:19.741569
11219 05:58:19.802048 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (54 ms)
11220 05:58:19.865586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11221 05:58:19.865874 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11223 05:58:19.875189 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11224 05:58:19.909948 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (365 ms)
11225 05:58:19.962938 [0:00:48.122427749] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11226 05:58:19.980663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11227 05:58:19.980941 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11229 05:58:19.991302 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11230 05:58:20.027732 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (465 ms)
11231 05:58:20.086266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11232 05:58:20.086541 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11234 05:58:20.095763 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11235 05:58:20.649898 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (696 ms)
11236 05:58:20.663240 [0:00:48.818741798] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11237 05:58:20.710077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11238 05:58:20.710355 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11240 05:58:20.721298 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11241 05:58:21.546238 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (897 ms)
11242 05:58:21.559848 [0:00:49.716216848] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11243 05:58:21.614807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11244 05:58:21.615097 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11246 05:58:21.624774 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11247 05:58:22.941419 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1396 ms)
11248 05:58:22.954469 [0:00:51.112372423] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11249 05:58:23.006605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11250 05:58:23.006892 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11252 05:58:23.016242 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11253 05:58:25.069528 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2129 ms)
11254 05:58:25.082347 [0:00:53.241179119] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11255 05:58:25.165569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11256 05:58:25.166468 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11258 05:58:25.181816 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11259 05:58:28.296466 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3229 ms)
11260 05:58:28.309428 [0:00:56.470459575] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11261 05:58:28.358106 [0:00:56.523650697] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11262 05:58:28.386593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11263 05:58:28.387285 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11265 05:58:28.410567 [0:00:56.575932665] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11266 05:58:28.413679 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11267 05:58:28.456291 Camera needs 4 requests, can't test only 1
11268 05:58:28.466616 [0:00:56.631273748] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11269 05:58:28.531274 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11270 05:58:28.602527
11271 05:58:28.688268 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (54 ms)
11272 05:58:28.781662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11273 05:58:28.782499 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11275 05:58:28.798725 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11276 05:58:28.830006 [0:00:56.995722993] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11277 05:58:28.853074 Camera needs 4 requests, can't test only 2
11278 05:58:28.935305 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11279 05:58:29.011394
11280 05:58:29.092309 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (53 ms)
11281 05:58:29.182067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11282 05:58:29.182885 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11284 05:58:29.199885 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11285 05:58:29.254799 Camera needs 4 requests, can't test only 3
11286 05:58:29.291422 [0:00:57.457581484] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11287 05:58:29.332314 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11288 05:58:29.405450
11289 05:58:29.486798 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (54 ms)
11290 05:58:29.575430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11291 05:58:29.576428 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11293 05:58:29.591192 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11294 05:58:29.645739 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (365 ms)
11295 05:58:29.729821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11296 05:58:29.730210 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11298 05:58:29.744750 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11299 05:58:29.789920 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (462 ms)
11300 05:58:29.870298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11301 05:58:29.870606 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11303 05:58:29.886287 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11304 05:58:29.979939 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (696 ms)
11305 05:58:29.989207 [0:00:58.154457575] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11306 05:58:30.072825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11307 05:58:30.073755 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11309 05:58:30.088795 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11310 05:58:30.912114 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (933 ms)
11311 05:58:30.925271 [0:00:59.086918975] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11312 05:58:31.007608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11313 05:58:31.008370 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11315 05:58:31.025080 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11316 05:58:32.307302 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1395 ms)
11317 05:58:32.320283 [0:01:00.482077033] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11318 05:58:32.405923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11319 05:58:32.406663 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11321 05:58:32.422232 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11322 05:58:34.401697 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2095 ms)
11323 05:58:34.415043 [0:01:02.576444945] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11324 05:58:34.495735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11325 05:58:34.496468 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11327 05:58:34.510894 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11328 05:58:37.564860 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3164 ms)
11329 05:58:37.578393 [0:01:05.740534072] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11330 05:58:37.626699 [0:01:05.794029806] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11331 05:58:37.653912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11332 05:58:37.654734 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11334 05:58:37.670185 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11335 05:58:37.680228 [0:01:05.848378101] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11336 05:58:37.720785 Camera needs 4 requests, can't test only 1
11337 05:58:37.735824 [0:01:05.902229845] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11338 05:58:37.787030 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11339 05:58:37.847479
11340 05:58:37.928170 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (53 ms)
11341 05:58:38.018939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11342 05:58:38.019399 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11344 05:58:38.031178 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11345 05:58:38.079947 Camera needs 4 requests, can't test only 2
11346 05:58:38.142919 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11347 05:58:38.202230
11348 05:58:38.278195 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (54 ms)
11349 05:58:38.366366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11350 05:58:38.366786 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11352 05:58:38.381242 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11353 05:58:38.426024 Camera needs 4 requests, can't test only 3
11354 05:58:38.485012 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11355 05:58:38.564458
11356 05:58:38.644751 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (53 ms)
11357 05:58:38.742054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11358 05:58:38.742872 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11360 05:58:38.758317 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11361 05:58:38.972839 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1247 ms)
11362 05:58:38.986123 [0:01:07.148611187] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11363 05:58:39.071747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11364 05:58:39.072169 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11366 05:58:39.084953 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11367 05:58:40.423850 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1451 ms)
11368 05:58:40.436785 [0:01:08.599488578] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11369 05:58:40.522938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11370 05:58:40.523658 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11372 05:58:40.537929 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11373 05:58:42.504492 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2081 ms)
11374 05:58:42.517849 [0:01:10.680773369] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11375 05:58:42.599686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11376 05:58:42.600596 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11378 05:58:42.616127 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11379 05:58:45.286703 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2782 ms)
11380 05:58:45.299600 [0:01:13.462906678] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11381 05:58:45.372678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11382 05:58:45.373508 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11384 05:58:45.390179 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11385 05:58:49.465411 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4179 ms)
11386 05:58:49.478425 [0:01:17.642474354] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11387 05:58:49.559705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11388 05:58:49.560450 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11390 05:58:49.577306 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11391 05:58:55.775522 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6311 ms)
11392 05:58:55.789001 [0:01:23.953193915] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11393 05:58:55.869921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11394 05:58:55.870255 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11396 05:58:55.886328 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11397 05:59:05.421853 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9647 ms)
11398 05:59:05.434801 [0:01:33.600485663] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11399 05:59:05.481883 [0:01:33.652416299] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11400 05:59:05.517199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11401 05:59:05.517529 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11403 05:59:05.534961 [0:01:33.706111025] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11404 05:59:05.541572 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11405 05:59:05.572721 Camera needs 4 requests, can't test only 1
11406 05:59:05.590019 [0:01:33.760826760] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11407 05:59:05.651179 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11408 05:59:05.720738
11409 05:59:05.807370 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (52 ms)
11410 05:59:05.896203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11411 05:59:05.896963 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11413 05:59:05.910153 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11414 05:59:05.966892 Camera needs 4 requests, can't test only 2
11415 05:59:06.044682 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11416 05:59:06.122104
11417 05:59:06.210404 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (53 ms)
11418 05:59:06.302449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11419 05:59:06.303225 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11421 05:59:06.319065 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11422 05:59:06.373374 Camera needs 4 requests, can't test only 3
11423 05:59:06.441072 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11424 05:59:06.511688
11425 05:59:06.596469 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (55 ms)
11426 05:59:06.674969 [0:01:34.845788047] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11427 05:59:06.695074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11428 05:59:06.695848 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11430 05:59:06.708548 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11431 05:59:06.763301 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1085 ms)
11432 05:59:06.855798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11433 05:59:06.856592 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11435 05:59:06.867762 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11436 05:59:08.052857 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1383 ms)
11437 05:59:08.062897 [0:01:36.228587567] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11438 05:59:08.136515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11439 05:59:08.136802 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11441 05:59:08.146627 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11442 05:59:10.130455 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2077 ms)
11443 05:59:10.140232 [0:01:38.306771943] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11444 05:59:10.223900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11445 05:59:10.224675 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11447 05:59:10.236745 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11448 05:59:12.811308 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2681 ms)
11449 05:59:12.820950 [0:01:40.987755259] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11450 05:59:12.907641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11451 05:59:12.908574 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11453 05:59:12.919338 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11454 05:59:16.924012 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4113 ms)
11455 05:59:16.933668 [0:01:45.100683584] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11456 05:59:17.013563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11457 05:59:17.014329 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11459 05:59:17.026971 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11460 05:59:23.228922 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6306 ms)
11461 05:59:23.239273 [0:01:51.407580258] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11462 05:59:23.300004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11463 05:59:23.300329 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11465 05:59:23.310383 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11466 05:59:32.837321 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9609 ms)
11467 05:59:32.847004 [0:02:01.016677707] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11468 05:59:32.893098 [0:02:01.067704345] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11469 05:59:32.904170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11470 05:59:32.904457 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11472 05:59:32.911447 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11473 05:59:32.946452 [0:02:01.120679452] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11474 05:59:32.949503 Camera needs 4 requests, can't test only 1
11475 05:59:32.999851 [0:02:01.174183870] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11476 05:59:33.010695 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11477 05:59:33.061819
11478 05:59:33.120321 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (51 ms)
11479 05:59:33.216712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11480 05:59:33.217025 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11482 05:59:33.223550 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11483 05:59:33.262817 Camera needs 4 requests, can't test only 2
11484 05:59:33.318528 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11485 05:59:33.376216
11486 05:59:33.445409 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (53 ms)
11487 05:59:33.517735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11488 05:59:33.518048 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11490 05:59:33.525710 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11491 05:59:33.562638 Camera needs 4 requests, can't test only 3
11492 05:59:33.620703 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11493 05:59:33.681779
11494 05:59:33.753211 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (53 ms)
11495 05:59:33.827027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11496 05:59:33.827352 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11498 05:59:33.836858 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11499 05:59:34.078106 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1084 ms)
11500 05:59:34.088072 [0:02:02.257840120] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11501 05:59:34.153866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11502 05:59:34.154238 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11504 05:59:34.164240 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11505 05:59:35.460151 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1381 ms)
11506 05:59:35.469833 [0:02:03.639348374] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11507 05:59:35.533363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11508 05:59:35.533664 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11510 05:59:35.543793 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11511 05:59:37.536619 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2076 ms)
11512 05:59:37.546372 [0:02:05.715486569] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11513 05:59:37.614101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11514 05:59:37.614429 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11516 05:59:37.624034 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11517 05:59:40.315010 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2777 ms)
11518 05:59:40.324697 [0:02:08.493635273] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11519 05:59:40.393407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11520 05:59:40.393720 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11522 05:59:40.401915 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11523 05:59:44.491163 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4175 ms)
11524 05:59:44.500844 [0:02:12.669465554] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11525 05:59:44.562897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11526 05:59:44.563229 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11528 05:59:44.572409 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11529 05:59:50.764946 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6274 ms)
11530 05:59:50.775080 [0:02:18.943215237] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11531 05:59:50.841525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11532 05:59:50.841814 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11534 05:59:50.849479 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11535 06:00:00.374180 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9608 ms)
11536 06:00:00.383782 [0:02:28.551405372] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11537 06:00:00.430590 [0:02:28.603367159] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11538 06:00:00.459650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11539 06:00:00.460009 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11541 06:00:00.470595 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11542 06:00:00.483757 [0:02:28.655480312] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11543 06:00:00.523314 Camera needs 4 requests, can't test only 1
11544 06:00:00.536386 [0:02:28.709001971] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11545 06:00:00.599764 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11546 06:00:00.670983
11547 06:00:00.751940 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (53 ms)
11548 06:00:00.841418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11549 06:00:00.842168 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11551 06:00:00.852781 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11552 06:00:00.903875 Camera needs 4 requests, can't test only 2
11553 06:00:00.982278 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11554 06:00:01.047699
11555 06:00:01.119657 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (51 ms)
11556 06:00:01.198459 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11558 06:00:01.201330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11559 06:00:01.213283 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11560 06:00:01.272243 Camera needs 4 requests, can't test only 3
11561 06:00:01.349590 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11562 06:00:01.428213
11563 06:00:01.520493 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (54 ms)
11564 06:00:01.615433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11565 06:00:01.616340 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11567 06:00:01.625078 [0:02:29.792997326] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11568 06:00:01.632298 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11569 06:00:01.690081 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1084 ms)
11570 06:00:01.778868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11571 06:00:01.779185 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11573 06:00:01.788465 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11574 06:00:02.999579 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1383 ms)
11575 06:00:03.009205 [0:02:31.176382403] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11576 06:00:03.083291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11577 06:00:03.083606 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11579 06:00:03.091573 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11580 06:00:05.077242 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2079 ms)
11581 06:00:05.086926 [0:02:33.254811121] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11582 06:00:05.166001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11583 06:00:05.166729 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11585 06:00:05.177302 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11586 06:00:07.793251 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2716 ms)
11587 06:00:07.803268 [0:02:35.970497749] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11588 06:00:07.882992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11589 06:00:07.883777 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11591 06:00:07.894393 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11592 06:00:11.969149 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4176 ms)
11593 06:00:11.978886 [0:02:40.146919517] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11594 06:00:12.039573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11595 06:00:12.039848 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11597 06:00:12.046372 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11598 06:00:18.276238 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6307 ms)
11599 06:00:18.286158 [0:02:46.454196390] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11600 06:00:18.347089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11601 06:00:18.347365 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11603 06:00:18.353819 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11604 06:00:27.885546 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9610 ms)
11605 06:00:27.895551 [0:02:56.063374429] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11606 06:00:27.967958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11607 06:00:27.968781 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11609 06:00:27.980398 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11610 06:00:28.209114 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (326 ms)
11611 06:00:28.219018 [0:02:56.390724549] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11612 06:00:28.306985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11613 06:00:28.307853 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11615 06:00:28.323833 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11616 06:00:28.570202 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (360 ms)
11617 06:00:28.583071 [0:02:56.751303370] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11618 06:00:28.661612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11619 06:00:28.662369 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11621 06:00:28.678133 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11622 06:00:28.867816 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (298 ms)
11623 06:00:28.877774 [0:02:57.049239148] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11624 06:00:28.960941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11625 06:00:28.961211 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11627 06:00:28.973138 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11628 06:00:29.296217 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (428 ms)
11629 06:00:29.308760 [0:02:57.477365569] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11630 06:00:29.381452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11631 06:00:29.382227 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11633 06:00:29.396377 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11634 06:00:29.759215 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (463 ms)
11635 06:00:29.768971 [0:02:57.940283014] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11636 06:00:29.845531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11637 06:00:29.846397 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11639 06:00:29.859029 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11640 06:00:30.453845 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (694 ms)
11641 06:00:30.466985 [0:02:58.635260649] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11642 06:00:30.544516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11643 06:00:30.545277 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11645 06:00:30.559731 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11646 06:00:31.447821 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (994 ms)
11647 06:00:31.461014 [0:02:59.629298662] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11648 06:00:31.545869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11649 06:00:31.546655 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11651 06:00:31.559374 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11652 06:00:32.875003 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1427 ms)
11653 06:00:32.887660 [0:03:01.056226984] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11654 06:00:32.964371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11655 06:00:32.965297 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11657 06:00:32.981344 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11658 06:00:34.967510 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2093 ms)
11659 06:00:34.980653 [0:03:03.149628967] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11660 06:00:35.049168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11661 06:00:35.049469 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11663 06:00:35.061269 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11664 06:00:38.129951 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3163 ms)
11665 06:00:38.143566 [0:03:06.312146681] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11666 06:00:38.203936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11667 06:00:38.204230 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11669 06:00:38.217705 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11670 06:00:38.461288 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (327 ms)
11671 06:00:38.470905 [0:03:06.639679658] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11672 06:00:38.547797 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11674 06:00:38.550639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11675 06:00:38.560587 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11676 06:00:38.723778 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (263 ms)
11677 06:00:38.733816 [0:03:06.902594957] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11678 06:00:38.804644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11679 06:00:38.804963 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11681 06:00:38.812524 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11682 06:00:39.020491 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (296 ms)
11683 06:00:39.030215 [0:03:07.198678125] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11684 06:00:39.109371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11685 06:00:39.110151 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11687 06:00:39.122476 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11688 06:00:39.448039 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (428 ms)
11689 06:00:39.458228 [0:03:07.626891593] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11690 06:00:39.544448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11691 06:00:39.545242 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11693 06:00:39.556610 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11694 06:00:39.911238 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (463 ms)
11695 06:00:39.920613 [0:03:08.090040909] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11696 06:00:39.998827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11697 06:00:39.999137 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11699 06:00:40.007165 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11700 06:00:40.605672 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (694 ms)
11701 06:00:40.615569 [0:03:08.784085359] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11702 06:00:40.681842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11703 06:00:40.682174 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11705 06:00:40.689281 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11706 06:00:41.599494 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (994 ms)
11707 06:00:41.609381 [0:03:09.778480383] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11708 06:00:41.690650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11709 06:00:41.691446 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11711 06:00:41.701779 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11712 06:00:43.026945 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1427 ms)
11713 06:00:43.036983 [0:03:11.205324109] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11714 06:00:43.115613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11715 06:00:43.116422 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11717 06:00:43.127775 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11718 06:00:45.119846 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2094 ms)
11719 06:00:45.129454 [0:03:13.298654672] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11720 06:00:45.208113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11721 06:00:45.208969 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11723 06:00:45.221477 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11724 06:00:48.282702 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3163 ms)
11725 06:00:48.292795 [0:03:16.461540049] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11726 06:00:48.370616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11727 06:00:48.371348 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11729 06:00:48.383236 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11730 06:00:48.609979 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (327 ms)
11731 06:00:48.619641 [0:03:16.788838084] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11732 06:00:48.707536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11733 06:00:48.708354 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11735 06:00:48.719512 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11736 06:00:48.937680 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (328 ms)
11737 06:00:48.947787 [0:03:17.116806757] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11738 06:00:49.032283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11739 06:00:49.033072 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11741 06:00:49.045604 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11742 06:00:49.234437 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (296 ms)
11743 06:00:49.243934 [0:03:17.413349274] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11744 06:00:49.337286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11745 06:00:49.338095 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11747 06:00:49.348745 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11748 06:00:49.662312 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (428 ms)
11749 06:00:49.672046 [0:03:17.841639614] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11750 06:00:49.755298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11751 06:00:49.756060 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11753 06:00:49.767590 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11754 06:00:50.158384 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (495 ms)
11755 06:00:50.168142 [0:03:18.337370765] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11756 06:00:50.253519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11757 06:00:50.253805 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11759 06:00:50.263711 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11760 06:00:50.852405 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (695 ms)
11761 06:00:50.862232 [0:03:19.031835873] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11762 06:00:50.929572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11763 06:00:50.929906 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11765 06:00:50.939146 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11766 06:00:51.748421 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (896 ms)
11767 06:00:51.758527 [0:03:19.927518896] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11768 06:00:51.842792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11769 06:00:51.843537 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11771 06:00:51.855110 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11772 06:00:53.142063 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1393 ms)
11773 06:00:53.152123 [0:03:21.321472522] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11774 06:00:53.226174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11775 06:00:53.226440 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11777 06:00:53.238080 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11778 06:00:55.235429 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2094 ms)
11779 06:00:55.245302 [0:03:23.415054691] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11780 06:00:55.322824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11781 06:00:55.323556 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11783 06:00:55.334273 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11784 06:00:58.461514 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3226 ms)
11785 06:00:58.471026 [0:03:26.640601396] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11786 06:00:58.557052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11787 06:00:58.558025 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11789 06:00:58.568509 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11790 06:00:58.754997 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (294 ms)
11791 06:00:58.764845 [0:03:26.935015570] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11792 06:00:58.847384 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11794 06:00:58.850054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11795 06:00:58.863015 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11796 06:00:59.083601 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (328 ms)
11797 06:00:59.093287 [0:03:27.263208425] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11798 06:00:59.176481 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11800 06:00:59.179497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11801 06:00:59.191383 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11802 06:00:59.379499 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (296 ms)
11803 06:00:59.389004 [0:03:27.559153612] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11804 06:00:59.469604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11805 06:00:59.470539 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11807 06:00:59.486580 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11808 06:00:59.836478 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (461 ms)
11809 06:00:59.849611 [0:03:28.019874417] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11810 06:00:59.931140 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11812 06:00:59.934145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11813 06:00:59.946055 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11814 06:01:00.400947 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (561 ms)
11815 06:01:00.410706 [0:03:28.580342769] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11816 06:01:00.488290 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11818 06:01:00.491441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11819 06:01:00.504497 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11820 06:01:01.094797 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (693 ms)
11821 06:01:01.104038 [0:03:29.274669769] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11822 06:01:01.190712 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11824 06:01:01.193290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11825 06:01:01.204835 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11826 06:01:01.990363 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (897 ms)
11827 06:01:02.000519 [0:03:30.170645637] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11828 06:01:02.089252 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11830 06:01:02.092046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11831 06:01:02.105848 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11832 06:01:03.321580 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1331 ms)
11833 06:01:03.331611 [0:03:31.501853753] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11834 06:01:03.415676 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11836 06:01:03.418718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11837 06:01:03.434241 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11838 06:01:05.448092 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2126 ms)
11839 06:01:05.457588 [0:03:33.628295761] [409] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11840 06:01:05.540609 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11842 06:01:05.543508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11843 06:01:05.558077 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11844 06:01:08.611598 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3164 ms)
11845 06:01:08.701028 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11847 06:01:08.703980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11848 06:01:08.714144 [----------] 120 tests from CaptureTests/SingleStream (188497 ms total)
11849 06:01:08.784443
11850 06:01:08.867175 [----------] Global test environment tear-down
11851 06:01:08.940167 [==========] 120 tests from 1 test suite ran. (188497 ms total)
11852 06:01:09.017754 <LAVA_SIGNAL_TESTSET STOP>
11853 06:01:09.018520 Received signal: <TESTSET> STOP
11854 06:01:09.018917 Closing test_set CaptureTests/SingleStream
11855 06:01:09.030015 + set +x
11856 06:01:09.033611 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 12379447_1.6.2.3.1>
11857 06:01:09.034313 Received signal: <ENDRUN> 0_lc-compliance 12379447_1.6.2.3.1
11858 06:01:09.034707 Ending use of test pattern.
11859 06:01:09.035029 Ending test lava.0_lc-compliance (12379447_1.6.2.3.1), duration 190.03
11861 06:01:09.036676 <LAVA_TEST_RUNNER EXIT>
11862 06:01:09.037340 ok: lava_test_shell seems to have completed
11863 06:01:09.046452 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11864 06:01:09.047312 end: 3.1 lava-test-shell (duration 00:03:11) [common]
11865 06:01:09.047750 end: 3 lava-test-retry (duration 00:03:11) [common]
11866 06:01:09.048193 start: 4 finalize (timeout 00:10:00) [common]
11867 06:01:09.048636 start: 4.1 power-off (timeout 00:00:30) [common]
11868 06:01:09.049359 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11869 06:01:09.167093 >> Command sent successfully.
11870 06:01:09.171935 Returned 0 in 0 seconds
11871 06:01:09.272917 end: 4.1 power-off (duration 00:00:00) [common]
11873 06:01:09.274431 start: 4.2 read-feedback (timeout 00:10:00) [common]
11874 06:01:09.275689 Listened to connection for namespace 'common' for up to 1s
11875 06:01:10.275587 Finalising connection for namespace 'common'
11876 06:01:10.276273 Disconnecting from shell: Finalise
11877 06:01:10.276695 / #
11878 06:01:10.377778 end: 4.2 read-feedback (duration 00:00:01) [common]
11879 06:01:10.378665 end: 4 finalize (duration 00:00:01) [common]
11880 06:01:10.379316 Cleaning after the job
11881 06:01:10.379889 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/ramdisk
11882 06:01:10.390148 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/kernel
11883 06:01:10.420146 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/dtb
11884 06:01:10.420489 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/nfsrootfs
11885 06:01:10.468545 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379447/tftp-deploy-6ixcjb7k/modules
11886 06:01:10.474034 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12379447
11887 06:01:10.726269 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12379447
11888 06:01:10.726451 Job finished correctly