Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 16
- Kernel Errors: 27
- Errors: 1
1 05:51:32.388864 lava-dispatcher, installed at version: 2023.10
2 05:51:32.389082 start: 0 validate
3 05:51:32.389211 Start time: 2023-12-25 05:51:32.389204+00:00 (UTC)
4 05:51:32.389321 Using caching service: 'http://localhost/cache/?uri=%s'
5 05:51:32.389445 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 05:51:32.659285 Using caching service: 'http://localhost/cache/?uri=%s'
7 05:51:32.659992 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 05:52:19.434601 Using caching service: 'http://localhost/cache/?uri=%s'
9 05:52:19.434768 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 05:52:19.705041 Using caching service: 'http://localhost/cache/?uri=%s'
11 05:52:19.705758 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 05:52:23.478468 validate duration: 51.09
14 05:52:23.479899 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:52:23.480450 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:52:23.481037 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:52:23.481918 Not decompressing ramdisk as can be used compressed.
18 05:52:23.482455 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 05:52:23.482837 saving as /var/lib/lava/dispatcher/tmp/12379427/tftp-deploy-3jn6beu8/ramdisk/rootfs.cpio.gz
20 05:52:23.483203 total size: 8181372 (7 MB)
21 05:52:23.754585 progress 0 % (0 MB)
22 05:52:23.756942 progress 5 % (0 MB)
23 05:52:23.759164 progress 10 % (0 MB)
24 05:52:23.761473 progress 15 % (1 MB)
25 05:52:23.763648 progress 20 % (1 MB)
26 05:52:23.766023 progress 25 % (1 MB)
27 05:52:23.768104 progress 30 % (2 MB)
28 05:52:23.770502 progress 35 % (2 MB)
29 05:52:23.772684 progress 40 % (3 MB)
30 05:52:23.774970 progress 45 % (3 MB)
31 05:52:23.777145 progress 50 % (3 MB)
32 05:52:23.779505 progress 55 % (4 MB)
33 05:52:23.781553 progress 60 % (4 MB)
34 05:52:23.783827 progress 65 % (5 MB)
35 05:52:23.786016 progress 70 % (5 MB)
36 05:52:23.788212 progress 75 % (5 MB)
37 05:52:23.790448 progress 80 % (6 MB)
38 05:52:23.792764 progress 85 % (6 MB)
39 05:52:23.794926 progress 90 % (7 MB)
40 05:52:23.797199 progress 95 % (7 MB)
41 05:52:23.799399 progress 100 % (7 MB)
42 05:52:23.799600 7 MB downloaded in 0.32 s (24.66 MB/s)
43 05:52:23.799759 end: 1.1.1 http-download (duration 00:00:00) [common]
45 05:52:23.799995 end: 1.1 download-retry (duration 00:00:00) [common]
46 05:52:23.800080 start: 1.2 download-retry (timeout 00:10:00) [common]
47 05:52:23.800164 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 05:52:23.800303 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 05:52:23.800370 saving as /var/lib/lava/dispatcher/tmp/12379427/tftp-deploy-3jn6beu8/kernel/Image
50 05:52:23.800430 total size: 50024960 (47 MB)
51 05:52:23.800490 No compression specified
52 05:52:23.801651 progress 0 % (0 MB)
53 05:52:23.814835 progress 5 % (2 MB)
54 05:52:23.828344 progress 10 % (4 MB)
55 05:52:23.841747 progress 15 % (7 MB)
56 05:52:23.855426 progress 20 % (9 MB)
57 05:52:23.868349 progress 25 % (11 MB)
58 05:52:23.881149 progress 30 % (14 MB)
59 05:52:23.894134 progress 35 % (16 MB)
60 05:52:23.906884 progress 40 % (19 MB)
61 05:52:23.919712 progress 45 % (21 MB)
62 05:52:23.932864 progress 50 % (23 MB)
63 05:52:23.945714 progress 55 % (26 MB)
64 05:52:23.958795 progress 60 % (28 MB)
65 05:52:23.971883 progress 65 % (31 MB)
66 05:52:23.984878 progress 70 % (33 MB)
67 05:52:23.997679 progress 75 % (35 MB)
68 05:52:24.010583 progress 80 % (38 MB)
69 05:52:24.023518 progress 85 % (40 MB)
70 05:52:24.036398 progress 90 % (42 MB)
71 05:52:24.049401 progress 95 % (45 MB)
72 05:52:24.062147 progress 100 % (47 MB)
73 05:52:24.062384 47 MB downloaded in 0.26 s (182.13 MB/s)
74 05:52:24.062538 end: 1.2.1 http-download (duration 00:00:00) [common]
76 05:52:24.062771 end: 1.2 download-retry (duration 00:00:00) [common]
77 05:52:24.062856 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:52:24.062947 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:52:24.063085 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 05:52:24.063156 saving as /var/lib/lava/dispatcher/tmp/12379427/tftp-deploy-3jn6beu8/dtb/mt8192-asurada-spherion-r0.dtb
81 05:52:24.063218 total size: 47278 (0 MB)
82 05:52:24.063279 No compression specified
83 05:52:24.064369 progress 69 % (0 MB)
84 05:52:24.064645 progress 100 % (0 MB)
85 05:52:24.064845 0 MB downloaded in 0.00 s (27.75 MB/s)
86 05:52:24.064967 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:52:24.065186 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:52:24.065274 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:52:24.065354 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:52:24.065467 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 05:52:24.065534 saving as /var/lib/lava/dispatcher/tmp/12379427/tftp-deploy-3jn6beu8/modules/modules.tar
93 05:52:24.065594 total size: 8619328 (8 MB)
94 05:52:24.065654 Using unxz to decompress xz
95 05:52:24.069760 progress 0 % (0 MB)
96 05:52:24.090926 progress 5 % (0 MB)
97 05:52:24.114155 progress 10 % (0 MB)
98 05:52:24.137699 progress 15 % (1 MB)
99 05:52:24.161347 progress 20 % (1 MB)
100 05:52:24.185512 progress 25 % (2 MB)
101 05:52:24.211414 progress 30 % (2 MB)
102 05:52:24.237696 progress 35 % (2 MB)
103 05:52:24.261632 progress 40 % (3 MB)
104 05:52:24.286159 progress 45 % (3 MB)
105 05:52:24.311676 progress 50 % (4 MB)
106 05:52:24.336317 progress 55 % (4 MB)
107 05:52:24.361457 progress 60 % (4 MB)
108 05:52:24.387123 progress 65 % (5 MB)
109 05:52:24.414388 progress 70 % (5 MB)
110 05:52:24.438197 progress 75 % (6 MB)
111 05:52:24.465666 progress 80 % (6 MB)
112 05:52:24.491691 progress 85 % (7 MB)
113 05:52:24.516728 progress 90 % (7 MB)
114 05:52:24.546783 progress 95 % (7 MB)
115 05:52:24.577409 progress 100 % (8 MB)
116 05:52:24.582074 8 MB downloaded in 0.52 s (15.92 MB/s)
117 05:52:24.582324 end: 1.4.1 http-download (duration 00:00:01) [common]
119 05:52:24.582649 end: 1.4 download-retry (duration 00:00:01) [common]
120 05:52:24.582744 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 05:52:24.582848 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 05:52:24.582930 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:52:24.583013 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 05:52:24.583238 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln
125 05:52:24.583372 makedir: /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin
126 05:52:24.583476 makedir: /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/tests
127 05:52:24.583574 makedir: /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/results
128 05:52:24.583690 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-add-keys
129 05:52:24.583839 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-add-sources
130 05:52:24.583976 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-background-process-start
131 05:52:24.584127 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-background-process-stop
132 05:52:24.584254 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-common-functions
133 05:52:24.584379 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-echo-ipv4
134 05:52:24.584507 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-install-packages
135 05:52:24.584632 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-installed-packages
136 05:52:24.584801 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-os-build
137 05:52:24.584933 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-probe-channel
138 05:52:24.585070 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-probe-ip
139 05:52:24.585196 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-target-ip
140 05:52:24.585321 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-target-mac
141 05:52:24.585444 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-target-storage
142 05:52:24.585572 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-test-case
143 05:52:24.585695 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-test-event
144 05:52:24.585818 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-test-feedback
145 05:52:24.585942 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-test-raise
146 05:52:24.586067 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-test-reference
147 05:52:24.586193 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-test-runner
148 05:52:24.586321 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-test-set
149 05:52:24.586446 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-test-shell
150 05:52:24.586575 Updating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-install-packages (oe)
151 05:52:24.586724 Updating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/bin/lava-installed-packages (oe)
152 05:52:24.586851 Creating /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/environment
153 05:52:24.586953 LAVA metadata
154 05:52:24.587025 - LAVA_JOB_ID=12379427
155 05:52:24.587088 - LAVA_DISPATCHER_IP=192.168.201.1
156 05:52:24.587193 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 05:52:24.587282 skipped lava-vland-overlay
158 05:52:24.587358 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 05:52:24.587439 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 05:52:24.587503 skipped lava-multinode-overlay
161 05:52:24.587574 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 05:52:24.587654 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 05:52:24.587729 Loading test definitions
164 05:52:24.587818 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 05:52:24.587892 Using /lava-12379427 at stage 0
166 05:52:24.588197 uuid=12379427_1.5.2.3.1 testdef=None
167 05:52:24.588291 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 05:52:24.588393 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 05:52:24.588986 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 05:52:24.589205 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 05:52:24.589836 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 05:52:24.590059 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 05:52:24.590709 runner path: /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/0/tests/0_dmesg test_uuid 12379427_1.5.2.3.1
176 05:52:24.590865 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 05:52:24.591091 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 05:52:24.591162 Using /lava-12379427 at stage 1
180 05:52:24.591488 uuid=12379427_1.5.2.3.5 testdef=None
181 05:52:24.591593 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 05:52:24.591677 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 05:52:24.592160 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 05:52:24.592373 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 05:52:24.593545 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 05:52:24.593772 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 05:52:24.594461 runner path: /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/1/tests/1_bootrr test_uuid 12379427_1.5.2.3.5
190 05:52:24.594612 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 05:52:24.594817 Creating lava-test-runner.conf files
193 05:52:24.594879 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/0 for stage 0
194 05:52:24.594968 - 0_dmesg
195 05:52:24.595053 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379427/lava-overlay-aeqhu_ln/lava-12379427/1 for stage 1
196 05:52:24.595166 - 1_bootrr
197 05:52:24.595261 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 05:52:24.595351 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 05:52:24.603977 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 05:52:24.604092 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 05:52:24.604184 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 05:52:24.604270 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 05:52:24.604353 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 05:52:24.856140 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 05:52:24.856559 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 05:52:24.856675 extracting modules file /var/lib/lava/dispatcher/tmp/12379427/tftp-deploy-3jn6beu8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379427/extract-overlay-ramdisk-wplek6i6/ramdisk
207 05:52:25.086491 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 05:52:25.086657 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 05:52:25.086761 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379427/compress-overlay-p02a4amd/overlay-1.5.2.4.tar.gz to ramdisk
210 05:52:25.086833 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379427/compress-overlay-p02a4amd/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12379427/extract-overlay-ramdisk-wplek6i6/ramdisk
211 05:52:25.095369 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 05:52:25.095523 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 05:52:25.095626 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 05:52:25.095717 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 05:52:25.095802 Building ramdisk /var/lib/lava/dispatcher/tmp/12379427/extract-overlay-ramdisk-wplek6i6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12379427/extract-overlay-ramdisk-wplek6i6/ramdisk
216 05:52:25.470349 >> 145327 blocks
217 05:52:27.842400 rename /var/lib/lava/dispatcher/tmp/12379427/extract-overlay-ramdisk-wplek6i6/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12379427/tftp-deploy-3jn6beu8/ramdisk/ramdisk.cpio.gz
218 05:52:27.842891 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 05:52:27.843025 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 05:52:27.843133 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 05:52:27.843260 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12379427/tftp-deploy-3jn6beu8/kernel/Image'
222 05:52:40.520373 Returned 0 in 12 seconds
223 05:52:40.621044 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12379427/tftp-deploy-3jn6beu8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12379427/tftp-deploy-3jn6beu8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12379427/tftp-deploy-3jn6beu8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12379427/tftp-deploy-3jn6beu8/kernel/image.itb
224 05:52:41.014403 output: FIT description: Kernel Image image with one or more FDT blobs
225 05:52:41.014776 output: Created: Mon Dec 25 05:52:40 2023
226 05:52:41.014854 output: Image 0 (kernel-1)
227 05:52:41.014921 output: Description:
228 05:52:41.014983 output: Created: Mon Dec 25 05:52:40 2023
229 05:52:41.015045 output: Type: Kernel Image
230 05:52:41.015104 output: Compression: lzma compressed
231 05:52:41.015161 output: Data Size: 11481830 Bytes = 11212.72 KiB = 10.95 MiB
232 05:52:41.015220 output: Architecture: AArch64
233 05:52:41.015278 output: OS: Linux
234 05:52:41.015338 output: Load Address: 0x00000000
235 05:52:41.015393 output: Entry Point: 0x00000000
236 05:52:41.015451 output: Hash algo: crc32
237 05:52:41.015508 output: Hash value: a47c00f1
238 05:52:41.015564 output: Image 1 (fdt-1)
239 05:52:41.015621 output: Description: mt8192-asurada-spherion-r0
240 05:52:41.015675 output: Created: Mon Dec 25 05:52:40 2023
241 05:52:41.015727 output: Type: Flat Device Tree
242 05:52:41.015779 output: Compression: uncompressed
243 05:52:41.015831 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 05:52:41.015884 output: Architecture: AArch64
245 05:52:41.015935 output: Hash algo: crc32
246 05:52:41.015986 output: Hash value: cc4352de
247 05:52:41.016038 output: Image 2 (ramdisk-1)
248 05:52:41.016089 output: Description: unavailable
249 05:52:41.016140 output: Created: Mon Dec 25 05:52:40 2023
250 05:52:41.016191 output: Type: RAMDisk Image
251 05:52:41.016243 output: Compression: Unknown Compression
252 05:52:41.016295 output: Data Size: 21393668 Bytes = 20892.25 KiB = 20.40 MiB
253 05:52:41.016347 output: Architecture: AArch64
254 05:52:41.016399 output: OS: Linux
255 05:52:41.016451 output: Load Address: unavailable
256 05:52:41.016502 output: Entry Point: unavailable
257 05:52:41.016554 output: Hash algo: crc32
258 05:52:41.016605 output: Hash value: 597a256f
259 05:52:41.016656 output: Default Configuration: 'conf-1'
260 05:52:41.016718 output: Configuration 0 (conf-1)
261 05:52:41.016811 output: Description: mt8192-asurada-spherion-r0
262 05:52:41.016863 output: Kernel: kernel-1
263 05:52:41.016915 output: Init Ramdisk: ramdisk-1
264 05:52:41.016967 output: FDT: fdt-1
265 05:52:41.017018 output: Loadables: kernel-1
266 05:52:41.017069 output:
267 05:52:41.017275 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
268 05:52:41.017373 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
269 05:52:41.017527 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
270 05:52:41.017627 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
271 05:52:41.017704 No LXC device requested
272 05:52:41.017784 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 05:52:41.017866 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
274 05:52:41.017941 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 05:52:41.018009 Checking files for TFTP limit of 4294967296 bytes.
276 05:52:41.018509 end: 1 tftp-deploy (duration 00:00:18) [common]
277 05:52:41.018611 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 05:52:41.018700 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 05:52:41.018823 substitutions:
280 05:52:41.018888 - {DTB}: 12379427/tftp-deploy-3jn6beu8/dtb/mt8192-asurada-spherion-r0.dtb
281 05:52:41.018948 - {INITRD}: 12379427/tftp-deploy-3jn6beu8/ramdisk/ramdisk.cpio.gz
282 05:52:41.019006 - {KERNEL}: 12379427/tftp-deploy-3jn6beu8/kernel/Image
283 05:52:41.019063 - {LAVA_MAC}: None
284 05:52:41.019119 - {PRESEED_CONFIG}: None
285 05:52:41.019172 - {PRESEED_LOCAL}: None
286 05:52:41.019225 - {RAMDISK}: 12379427/tftp-deploy-3jn6beu8/ramdisk/ramdisk.cpio.gz
287 05:52:41.019278 - {ROOT_PART}: None
288 05:52:41.019331 - {ROOT}: None
289 05:52:41.019383 - {SERVER_IP}: 192.168.201.1
290 05:52:41.019442 - {TEE}: None
291 05:52:41.019527 Parsed boot commands:
292 05:52:41.019581 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 05:52:41.019762 Parsed boot commands: tftpboot 192.168.201.1 12379427/tftp-deploy-3jn6beu8/kernel/image.itb 12379427/tftp-deploy-3jn6beu8/kernel/cmdline
294 05:52:41.019852 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 05:52:41.019935 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 05:52:41.020027 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 05:52:41.020111 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 05:52:41.020181 Not connected, no need to disconnect.
299 05:52:41.020252 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 05:52:41.020333 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 05:52:41.020400 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
302 05:52:41.024587 Setting prompt string to ['lava-test: # ']
303 05:52:41.025008 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 05:52:41.025117 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 05:52:41.025213 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 05:52:41.025518 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 05:52:41.025749 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
308 05:52:46.158843 >> Command sent successfully.
309 05:52:46.161341 Returned 0 in 5 seconds
310 05:52:46.261750 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 05:52:46.262082 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 05:52:46.262186 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 05:52:46.262279 Setting prompt string to 'Starting depthcharge on Spherion...'
315 05:52:46.262347 Changing prompt to 'Starting depthcharge on Spherion...'
316 05:52:46.262415 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 05:52:46.262677 [Enter `^Ec?' for help]
318 05:52:46.444518
319 05:52:46.444673
320 05:52:46.444798 F0: 102B 0000
321 05:52:46.444867
322 05:52:46.444930 F3: 1001 0000 [0200]
323 05:52:46.444988
324 05:52:46.448244 F3: 1001 0000
325 05:52:46.448331
326 05:52:46.448395 F7: 102D 0000
327 05:52:46.448456
328 05:52:46.448513 F1: 0000 0000
329 05:52:46.448569
330 05:52:46.451737 V0: 0000 0000 [0001]
331 05:52:46.451824
332 05:52:46.451889 00: 0007 8000
333 05:52:46.451956
334 05:52:46.455667 01: 0000 0000
335 05:52:46.455758
336 05:52:46.455827 BP: 0C00 0209 [0000]
337 05:52:46.455887
338 05:52:46.459260 G0: 1182 0000
339 05:52:46.459347
340 05:52:46.459413 EC: 0000 0021 [4000]
341 05:52:46.459474
342 05:52:46.463774 S7: 0000 0000 [0000]
343 05:52:46.463866
344 05:52:46.463931 CC: 0000 0000 [0001]
345 05:52:46.463991
346 05:52:46.464049 T0: 0000 0040 [010F]
347 05:52:46.464106
348 05:52:46.467276 Jump to BL
349 05:52:46.467362
350 05:52:46.491324
351 05:52:46.491516
352 05:52:46.491590
353 05:52:46.497842 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 05:52:46.501130 ARM64: Exception handlers installed.
355 05:52:46.504633 ARM64: Testing exception
356 05:52:46.508407 ARM64: Done test exception
357 05:52:46.514533 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 05:52:46.524959 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 05:52:46.531359 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 05:52:46.541908 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 05:52:46.548586 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 05:52:46.558837 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 05:52:46.569103 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 05:52:46.575686 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 05:52:46.593893 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 05:52:46.597329 WDT: Last reset was cold boot
367 05:52:46.600416 SPI1(PAD0) initialized at 2873684 Hz
368 05:52:46.603753 SPI5(PAD0) initialized at 992727 Hz
369 05:52:46.607586 VBOOT: Loading verstage.
370 05:52:46.613921 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 05:52:46.617193 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 05:52:46.620763 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 05:52:46.624260 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 05:52:46.631387 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 05:52:46.637892 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 05:52:46.648836 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 05:52:46.648919
378 05:52:46.648985
379 05:52:46.658705 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 05:52:46.662095 ARM64: Exception handlers installed.
381 05:52:46.665893 ARM64: Testing exception
382 05:52:46.665980 ARM64: Done test exception
383 05:52:46.672187 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 05:52:46.675542 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 05:52:46.689715 Probing TPM: . done!
386 05:52:46.689799 TPM ready after 0 ms
387 05:52:46.696620 Connected to device vid:did:rid of 1ae0:0028:00
388 05:52:46.703451 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
389 05:52:46.746244 Initialized TPM device CR50 revision 0
390 05:52:46.757741 tlcl_send_startup: Startup return code is 0
391 05:52:46.757847 TPM: setup succeeded
392 05:52:46.768977 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 05:52:46.778449 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 05:52:46.787924 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 05:52:46.797067 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 05:52:46.800279 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 05:52:46.803525 in-header: 03 07 00 00 08 00 00 00
398 05:52:46.806814 in-data: aa e4 47 04 13 02 00 00
399 05:52:46.810477 Chrome EC: UHEPI supported
400 05:52:46.817118 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 05:52:46.820154 in-header: 03 9d 00 00 08 00 00 00
402 05:52:46.823866 in-data: 10 20 20 08 00 00 00 00
403 05:52:46.823948 Phase 1
404 05:52:46.830309 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 05:52:46.833469 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 05:52:46.840557 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 05:52:46.843706 Recovery requested (1009000e)
408 05:52:46.850494 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 05:52:46.856260 tlcl_extend: response is 0
410 05:52:46.864311 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 05:52:46.869493 tlcl_extend: response is 0
412 05:52:46.876165 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 05:52:46.897044 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 05:52:46.903725 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 05:52:46.903812
416 05:52:46.903879
417 05:52:46.913664 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 05:52:46.917078 ARM64: Exception handlers installed.
419 05:52:46.920343 ARM64: Testing exception
420 05:52:46.920432 ARM64: Done test exception
421 05:52:46.939820 pmic_efuse_setting: Set efuses in 11 msecs
422 05:52:46.947892 pmwrap_interface_init: Select PMIF_VLD_RDY
423 05:52:46.951295 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 05:52:46.958285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 05:52:46.961711 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 05:52:46.965490 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 05:52:46.973339 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 05:52:46.976886 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 05:52:46.980054 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 05:52:46.986569 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 05:52:46.989958 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 05:52:46.993317 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 05:52:46.999930 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 05:52:47.003704 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 05:52:47.006825 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 05:52:47.013709 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 05:52:47.020574 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 05:52:47.027180 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 05:52:47.030746 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 05:52:47.037774 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 05:52:47.045075 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 05:52:47.048667 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 05:52:47.054659 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 05:52:47.061380 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 05:52:47.065059 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 05:52:47.071168 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 05:52:47.074478 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 05:52:47.081504 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 05:52:47.088048 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 05:52:47.091102 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 05:52:47.097705 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 05:52:47.101118 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 05:52:47.108049 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 05:52:47.111249 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 05:52:47.117918 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 05:52:47.121324 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 05:52:47.128013 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 05:52:47.131437 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 05:52:47.137840 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 05:52:47.141056 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 05:52:47.144318 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 05:52:47.151051 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 05:52:47.154713 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 05:52:47.157763 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 05:52:47.164639 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 05:52:47.167700 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 05:52:47.171086 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 05:52:47.177980 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 05:52:47.181558 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 05:52:47.184446 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 05:52:47.187842 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 05:52:47.194537 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 05:52:47.197844 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 05:52:47.204664 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 05:52:47.214898 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 05:52:47.218037 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 05:52:47.228087 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 05:52:47.234792 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 05:52:47.240996 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 05:52:47.244884 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 05:52:47.248072 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 05:52:47.255211 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
483 05:52:47.262001 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 05:52:47.265099 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 05:52:47.268440 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 05:52:47.280057 [RTC]rtc_get_frequency_meter,154: input=15, output=764
487 05:52:47.289098 [RTC]rtc_get_frequency_meter,154: input=23, output=947
488 05:52:47.298883 [RTC]rtc_get_frequency_meter,154: input=19, output=856
489 05:52:47.308213 [RTC]rtc_get_frequency_meter,154: input=17, output=810
490 05:52:47.317630 [RTC]rtc_get_frequency_meter,154: input=16, output=785
491 05:52:47.327285 [RTC]rtc_get_frequency_meter,154: input=16, output=786
492 05:52:47.337117 [RTC]rtc_get_frequency_meter,154: input=17, output=810
493 05:52:47.339963 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
494 05:52:47.347166 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
495 05:52:47.350702 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 05:52:47.354148 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 05:52:47.360459 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 05:52:47.363913 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 05:52:47.367121 ADC[4]: Raw value=670432 ID=5
500 05:52:47.367205 ADC[3]: Raw value=212549 ID=1
501 05:52:47.370619 RAM Code: 0x51
502 05:52:47.373894 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 05:52:47.380310 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 05:52:47.387059 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
505 05:52:47.393522 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
506 05:52:47.396688 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 05:52:47.400376 in-header: 03 07 00 00 08 00 00 00
508 05:52:47.403412 in-data: aa e4 47 04 13 02 00 00
509 05:52:47.406644 Chrome EC: UHEPI supported
510 05:52:47.413491 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 05:52:47.416934 in-header: 03 d5 00 00 08 00 00 00
512 05:52:47.420257 in-data: 98 20 60 08 00 00 00 00
513 05:52:47.423165 MRC: failed to locate region type 0.
514 05:52:47.430205 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 05:52:47.433315 DRAM-K: Running full calibration
516 05:52:47.436886 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
517 05:52:47.439727 header.status = 0x0
518 05:52:47.442911 header.version = 0x6 (expected: 0x6)
519 05:52:47.446511 header.size = 0xd00 (expected: 0xd00)
520 05:52:47.446614 header.flags = 0x0
521 05:52:47.453063 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 05:52:47.471499 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
523 05:52:47.478340 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 05:52:47.481627 dram_init: ddr_geometry: 0
525 05:52:47.485132 [EMI] MDL number = 0
526 05:52:47.485260 [EMI] Get MDL freq = 0
527 05:52:47.488836 dram_init: ddr_type: 0
528 05:52:47.488928 is_discrete_lpddr4: 1
529 05:52:47.492030 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 05:52:47.492154
531 05:52:47.492225
532 05:52:47.495847 [Bian_co] ETT version 0.0.0.1
533 05:52:47.499085 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
534 05:52:47.499181
535 05:52:47.505935 dramc_set_vcore_voltage set vcore to 650000
536 05:52:47.506023 Read voltage for 800, 4
537 05:52:47.509180 Vio18 = 0
538 05:52:47.509263 Vcore = 650000
539 05:52:47.509329 Vdram = 0
540 05:52:47.509390 Vddq = 0
541 05:52:47.512392 Vmddr = 0
542 05:52:47.512475 dram_init: config_dvfs: 1
543 05:52:47.519068 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 05:52:47.525892 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 05:52:47.528921 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
546 05:52:47.532423 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
547 05:52:47.535946 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
548 05:52:47.539440 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
549 05:52:47.542042 MEM_TYPE=3, freq_sel=18
550 05:52:47.545767 sv_algorithm_assistance_LP4_1600
551 05:52:47.549079 ============ PULL DRAM RESETB DOWN ============
552 05:52:47.552165 ========== PULL DRAM RESETB DOWN end =========
553 05:52:47.559130 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 05:52:47.562271 ===================================
555 05:52:47.562357 LPDDR4 DRAM CONFIGURATION
556 05:52:47.565784 ===================================
557 05:52:47.569001 EX_ROW_EN[0] = 0x0
558 05:52:47.569088 EX_ROW_EN[1] = 0x0
559 05:52:47.572602 LP4Y_EN = 0x0
560 05:52:47.572717 WORK_FSP = 0x0
561 05:52:47.575563 WL = 0x2
562 05:52:47.579389 RL = 0x2
563 05:52:47.579474 BL = 0x2
564 05:52:47.582204 RPST = 0x0
565 05:52:47.582287 RD_PRE = 0x0
566 05:52:47.585405 WR_PRE = 0x1
567 05:52:47.585491 WR_PST = 0x0
568 05:52:47.588895 DBI_WR = 0x0
569 05:52:47.588979 DBI_RD = 0x0
570 05:52:47.592294 OTF = 0x1
571 05:52:47.595782 ===================================
572 05:52:47.598823 ===================================
573 05:52:47.598909 ANA top config
574 05:52:47.602150 ===================================
575 05:52:47.605709 DLL_ASYNC_EN = 0
576 05:52:47.608979 ALL_SLAVE_EN = 1
577 05:52:47.609064 NEW_RANK_MODE = 1
578 05:52:47.612175 DLL_IDLE_MODE = 1
579 05:52:47.615737 LP45_APHY_COMB_EN = 1
580 05:52:47.619528 TX_ODT_DIS = 1
581 05:52:47.619612 NEW_8X_MODE = 1
582 05:52:47.622767 ===================================
583 05:52:47.625855 ===================================
584 05:52:47.629040 data_rate = 1600
585 05:52:47.632214 CKR = 1
586 05:52:47.635568 DQ_P2S_RATIO = 8
587 05:52:47.638830 ===================================
588 05:52:47.642386 CA_P2S_RATIO = 8
589 05:52:47.645525 DQ_CA_OPEN = 0
590 05:52:47.645613 DQ_SEMI_OPEN = 0
591 05:52:47.649044 CA_SEMI_OPEN = 0
592 05:52:47.652370 CA_FULL_RATE = 0
593 05:52:47.655619 DQ_CKDIV4_EN = 1
594 05:52:47.658740 CA_CKDIV4_EN = 1
595 05:52:47.661978 CA_PREDIV_EN = 0
596 05:52:47.662065 PH8_DLY = 0
597 05:52:47.665884 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 05:52:47.668619 DQ_AAMCK_DIV = 4
599 05:52:47.672386 CA_AAMCK_DIV = 4
600 05:52:47.675549 CA_ADMCK_DIV = 4
601 05:52:47.678904 DQ_TRACK_CA_EN = 0
602 05:52:47.678990 CA_PICK = 800
603 05:52:47.682484 CA_MCKIO = 800
604 05:52:47.685546 MCKIO_SEMI = 0
605 05:52:47.688989 PLL_FREQ = 3068
606 05:52:47.692448 DQ_UI_PI_RATIO = 32
607 05:52:47.695721 CA_UI_PI_RATIO = 0
608 05:52:47.698962 ===================================
609 05:52:47.702284 ===================================
610 05:52:47.702370 memory_type:LPDDR4
611 05:52:47.705989 GP_NUM : 10
612 05:52:47.709393 SRAM_EN : 1
613 05:52:47.709477 MD32_EN : 0
614 05:52:47.712467 ===================================
615 05:52:47.715733 [ANA_INIT] >>>>>>>>>>>>>>
616 05:52:47.718859 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 05:52:47.722308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 05:52:47.725398 ===================================
619 05:52:47.728937 data_rate = 1600,PCW = 0X7600
620 05:52:47.732042 ===================================
621 05:52:47.735407 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 05:52:47.739197 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 05:52:47.745655 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 05:52:47.749271 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 05:52:47.752023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 05:52:47.755599 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 05:52:47.758723 [ANA_INIT] flow start
628 05:52:47.762237 [ANA_INIT] PLL >>>>>>>>
629 05:52:47.762323 [ANA_INIT] PLL <<<<<<<<
630 05:52:47.765338 [ANA_INIT] MIDPI >>>>>>>>
631 05:52:47.768713 [ANA_INIT] MIDPI <<<<<<<<
632 05:52:47.771881 [ANA_INIT] DLL >>>>>>>>
633 05:52:47.771968 [ANA_INIT] flow end
634 05:52:47.775399 ============ LP4 DIFF to SE enter ============
635 05:52:47.781883 ============ LP4 DIFF to SE exit ============
636 05:52:47.781976 [ANA_INIT] <<<<<<<<<<<<<
637 05:52:47.785421 [Flow] Enable top DCM control >>>>>
638 05:52:47.788420 [Flow] Enable top DCM control <<<<<
639 05:52:47.792126 Enable DLL master slave shuffle
640 05:52:47.798549 ==============================================================
641 05:52:47.798647 Gating Mode config
642 05:52:47.805097 ==============================================================
643 05:52:47.808496 Config description:
644 05:52:47.818814 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 05:52:47.825390 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 05:52:47.828268 SELPH_MODE 0: By rank 1: By Phase
647 05:52:47.835328 ==============================================================
648 05:52:47.838465 GAT_TRACK_EN = 1
649 05:52:47.838551 RX_GATING_MODE = 2
650 05:52:47.841923 RX_GATING_TRACK_MODE = 2
651 05:52:47.845174 SELPH_MODE = 1
652 05:52:47.848412 PICG_EARLY_EN = 1
653 05:52:47.851889 VALID_LAT_VALUE = 1
654 05:52:47.858195 ==============================================================
655 05:52:47.861731 Enter into Gating configuration >>>>
656 05:52:47.864702 Exit from Gating configuration <<<<
657 05:52:47.868106 Enter into DVFS_PRE_config >>>>>
658 05:52:47.878187 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 05:52:47.881491 Exit from DVFS_PRE_config <<<<<
660 05:52:47.884642 Enter into PICG configuration >>>>
661 05:52:47.888162 Exit from PICG configuration <<<<
662 05:52:47.891327 [RX_INPUT] configuration >>>>>
663 05:52:47.894985 [RX_INPUT] configuration <<<<<
664 05:52:47.898052 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 05:52:47.904723 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 05:52:47.911422 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 05:52:47.917935 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 05:52:47.921686 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 05:52:47.927905 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 05:52:47.931466 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 05:52:47.938407 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 05:52:47.941401 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 05:52:47.944570 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 05:52:47.948237 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 05:52:47.954455 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 05:52:47.957737 ===================================
677 05:52:47.957823 LPDDR4 DRAM CONFIGURATION
678 05:52:47.961264 ===================================
679 05:52:47.964322 EX_ROW_EN[0] = 0x0
680 05:52:47.967894 EX_ROW_EN[1] = 0x0
681 05:52:47.967977 LP4Y_EN = 0x0
682 05:52:47.971018 WORK_FSP = 0x0
683 05:52:47.971101 WL = 0x2
684 05:52:47.974484 RL = 0x2
685 05:52:47.974566 BL = 0x2
686 05:52:47.977717 RPST = 0x0
687 05:52:47.977800 RD_PRE = 0x0
688 05:52:47.981072 WR_PRE = 0x1
689 05:52:47.981154 WR_PST = 0x0
690 05:52:47.984297 DBI_WR = 0x0
691 05:52:47.984379 DBI_RD = 0x0
692 05:52:47.987616 OTF = 0x1
693 05:52:47.991364 ===================================
694 05:52:47.994459 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 05:52:47.997532 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 05:52:48.004221 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 05:52:48.007690 ===================================
698 05:52:48.007774 LPDDR4 DRAM CONFIGURATION
699 05:52:48.010952 ===================================
700 05:52:48.014254 EX_ROW_EN[0] = 0x10
701 05:52:48.017527 EX_ROW_EN[1] = 0x0
702 05:52:48.017603 LP4Y_EN = 0x0
703 05:52:48.020915 WORK_FSP = 0x0
704 05:52:48.021035 WL = 0x2
705 05:52:48.024029 RL = 0x2
706 05:52:48.024112 BL = 0x2
707 05:52:48.027616 RPST = 0x0
708 05:52:48.027700 RD_PRE = 0x0
709 05:52:48.030933 WR_PRE = 0x1
710 05:52:48.031009 WR_PST = 0x0
711 05:52:48.034128 DBI_WR = 0x0
712 05:52:48.034233 DBI_RD = 0x0
713 05:52:48.037176 OTF = 0x1
714 05:52:48.040881 ===================================
715 05:52:48.047138 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 05:52:48.051135 nWR fixed to 40
717 05:52:48.051213 [ModeRegInit_LP4] CH0 RK0
718 05:52:48.053844 [ModeRegInit_LP4] CH0 RK1
719 05:52:48.057364 [ModeRegInit_LP4] CH1 RK0
720 05:52:48.060648 [ModeRegInit_LP4] CH1 RK1
721 05:52:48.060787 match AC timing 12
722 05:52:48.063810 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
723 05:52:48.070946 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 05:52:48.073656 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 05:52:48.077212 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 05:52:48.083805 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 05:52:48.083887 [EMI DOE] emi_dcm 0
728 05:52:48.090430 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 05:52:48.090517 ==
730 05:52:48.093813 Dram Type= 6, Freq= 0, CH_0, rank 0
731 05:52:48.097275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
732 05:52:48.097364 ==
733 05:52:48.103608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 05:52:48.106866 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 05:52:48.117153 [CA 0] Center 37 (7~68) winsize 62
736 05:52:48.120829 [CA 1] Center 37 (7~68) winsize 62
737 05:52:48.124123 [CA 2] Center 35 (5~66) winsize 62
738 05:52:48.127567 [CA 3] Center 35 (5~66) winsize 62
739 05:52:48.130761 [CA 4] Center 34 (4~65) winsize 62
740 05:52:48.134037 [CA 5] Center 34 (3~65) winsize 63
741 05:52:48.134123
742 05:52:48.137506 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 05:52:48.137591
744 05:52:48.140697 [CATrainingPosCal] consider 1 rank data
745 05:52:48.144119 u2DelayCellTimex100 = 270/100 ps
746 05:52:48.147464 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
747 05:52:48.150534 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
748 05:52:48.157219 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
749 05:52:48.160598 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
750 05:52:48.163885 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
751 05:52:48.167471 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
752 05:52:48.167561
753 05:52:48.170722 CA PerBit enable=1, Macro0, CA PI delay=34
754 05:52:48.170818
755 05:52:48.174075 [CBTSetCACLKResult] CA Dly = 34
756 05:52:48.174158 CS Dly: 5 (0~36)
757 05:52:48.174225 ==
758 05:52:48.177460 Dram Type= 6, Freq= 0, CH_0, rank 1
759 05:52:48.183801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
760 05:52:48.183888 ==
761 05:52:48.187466 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 05:52:48.193968 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 05:52:48.203092 [CA 0] Center 37 (6~68) winsize 63
764 05:52:48.206608 [CA 1] Center 37 (6~68) winsize 63
765 05:52:48.210087 [CA 2] Center 35 (4~66) winsize 63
766 05:52:48.213145 [CA 3] Center 34 (4~65) winsize 62
767 05:52:48.216486 [CA 4] Center 33 (3~64) winsize 62
768 05:52:48.220227 [CA 5] Center 33 (3~64) winsize 62
769 05:52:48.220311
770 05:52:48.223258 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 05:52:48.223343
772 05:52:48.226651 [CATrainingPosCal] consider 2 rank data
773 05:52:48.230051 u2DelayCellTimex100 = 270/100 ps
774 05:52:48.232897 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
775 05:52:48.236990 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
776 05:52:48.243413 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
777 05:52:48.246227 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
778 05:52:48.249814 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
779 05:52:48.252970 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 05:52:48.253054
781 05:52:48.256394 CA PerBit enable=1, Macro0, CA PI delay=33
782 05:52:48.256477
783 05:52:48.259869 [CBTSetCACLKResult] CA Dly = 33
784 05:52:48.259952 CS Dly: 6 (0~38)
785 05:52:48.260019
786 05:52:48.263264 ----->DramcWriteLeveling(PI) begin...
787 05:52:48.266396 ==
788 05:52:48.269675 Dram Type= 6, Freq= 0, CH_0, rank 0
789 05:52:48.273208 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
790 05:52:48.273294 ==
791 05:52:48.276287 Write leveling (Byte 0): 27 => 27
792 05:52:48.279843 Write leveling (Byte 1): 27 => 27
793 05:52:48.283048 DramcWriteLeveling(PI) end<-----
794 05:52:48.283133
795 05:52:48.283199 ==
796 05:52:48.286573 Dram Type= 6, Freq= 0, CH_0, rank 0
797 05:52:48.289547 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
798 05:52:48.289632 ==
799 05:52:48.293083 [Gating] SW mode calibration
800 05:52:48.299561 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 05:52:48.306251 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 05:52:48.309782 0 6 0 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 1)
803 05:52:48.312999 0 6 4 | B1->B0 | 2a2a 2525 | 1 0 | (1 0) (0 0)
804 05:52:48.316171 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 05:52:48.322827 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 05:52:48.326060 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 05:52:48.329483 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 05:52:48.336313 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 05:52:48.339654 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 05:52:48.342759 0 7 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
811 05:52:48.349670 0 7 4 | B1->B0 | 3b3b 3f3f | 1 0 | (0 0) (0 0)
812 05:52:48.353209 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
813 05:52:48.356190 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
814 05:52:48.362945 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
815 05:52:48.366534 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
816 05:52:48.369855 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
817 05:52:48.376427 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
818 05:52:48.379626 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
819 05:52:48.382909 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
820 05:52:48.389782 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
821 05:52:48.393215 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
822 05:52:48.396515 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
823 05:52:48.402773 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
824 05:52:48.406043 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
825 05:52:48.409682 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
826 05:52:48.415960 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
827 05:52:48.419285 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
828 05:52:48.422520 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
829 05:52:48.426225 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
830 05:52:48.432784 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 05:52:48.435949 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 05:52:48.439206 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 05:52:48.446252 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 05:52:48.449630 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
835 05:52:48.452891 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
836 05:52:48.456039 Total UI for P1: 0, mck2ui 16
837 05:52:48.459318 best dqsien dly found for B1: ( 0, 10, 0)
838 05:52:48.466172 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 05:52:48.466272 Total UI for P1: 0, mck2ui 16
840 05:52:48.472741 best dqsien dly found for B0: ( 0, 10, 4)
841 05:52:48.476564 best DQS0 dly(MCK, UI, PI) = (0, 10, 4)
842 05:52:48.479399 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
843 05:52:48.479485
844 05:52:48.483139 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 4)
845 05:52:48.486175 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
846 05:52:48.490128 [Gating] SW calibration Done
847 05:52:48.490218 ==
848 05:52:48.493214 Dram Type= 6, Freq= 0, CH_0, rank 0
849 05:52:48.496988 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
850 05:52:48.497085 ==
851 05:52:48.497153 RX Vref Scan: 0
852 05:52:48.500045
853 05:52:48.500129 RX Vref 0 -> 0, step: 1
854 05:52:48.500196
855 05:52:48.503273 RX Delay -130 -> 252, step: 16
856 05:52:48.506935 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
857 05:52:48.510071 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
858 05:52:48.516922 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
859 05:52:48.520100 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
860 05:52:48.523513 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
861 05:52:48.526642 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
862 05:52:48.530427 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
863 05:52:48.536610 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
864 05:52:48.539978 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
865 05:52:48.543316 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
866 05:52:48.547067 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
867 05:52:48.550351 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
868 05:52:48.557108 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
869 05:52:48.560407 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
870 05:52:48.563333 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
871 05:52:48.566869 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
872 05:52:48.566954 ==
873 05:52:48.570365 Dram Type= 6, Freq= 0, CH_0, rank 0
874 05:52:48.576618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
875 05:52:48.576774 ==
876 05:52:48.576843 DQS Delay:
877 05:52:48.576905 DQS0 = 0, DQS1 = 0
878 05:52:48.580111 DQM Delay:
879 05:52:48.580195 DQM0 = 83, DQM1 = 74
880 05:52:48.583812 DQ Delay:
881 05:52:48.587298 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
882 05:52:48.587413 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
883 05:52:48.590313 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
884 05:52:48.596915 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
885 05:52:48.597022
886 05:52:48.597119
887 05:52:48.597214 ==
888 05:52:48.600275 Dram Type= 6, Freq= 0, CH_0, rank 0
889 05:52:48.603415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
890 05:52:48.603500 ==
891 05:52:48.603567
892 05:52:48.603628
893 05:52:48.606570 TX Vref Scan disable
894 05:52:48.606654 == TX Byte 0 ==
895 05:52:48.613434 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
896 05:52:48.616747 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
897 05:52:48.616834 == TX Byte 1 ==
898 05:52:48.623367 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
899 05:52:48.627016 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
900 05:52:48.627132 ==
901 05:52:48.629784 Dram Type= 6, Freq= 0, CH_0, rank 0
902 05:52:48.633166 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
903 05:52:48.633252 ==
904 05:52:48.647024 TX Vref=22, minBit 1, minWin=27, winSum=440
905 05:52:48.650136 TX Vref=24, minBit 2, minWin=27, winSum=445
906 05:52:48.653586 TX Vref=26, minBit 4, minWin=27, winSum=447
907 05:52:48.656656 TX Vref=28, minBit 1, minWin=28, winSum=451
908 05:52:48.660180 TX Vref=30, minBit 1, minWin=28, winSum=450
909 05:52:48.663432 TX Vref=32, minBit 1, minWin=27, winSum=448
910 05:52:48.670191 [TxChooseVref] Worse bit 1, Min win 28, Win sum 451, Final Vref 28
911 05:52:48.670287
912 05:52:48.673250 Final TX Range 1 Vref 28
913 05:52:48.673337
914 05:52:48.673423 ==
915 05:52:48.676988 Dram Type= 6, Freq= 0, CH_0, rank 0
916 05:52:48.680417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
917 05:52:48.680503 ==
918 05:52:48.680604
919 05:52:48.683551
920 05:52:48.683636 TX Vref Scan disable
921 05:52:48.686545 == TX Byte 0 ==
922 05:52:48.689978 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
923 05:52:48.693432 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
924 05:52:48.696571 == TX Byte 1 ==
925 05:52:48.700104 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
926 05:52:48.703255 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
927 05:52:48.706488
928 05:52:48.706598 [DATLAT]
929 05:52:48.706699 Freq=800, CH0 RK0
930 05:52:48.706798
931 05:52:48.709872 DATLAT Default: 0xa
932 05:52:48.709964 0, 0xFFFF, sum = 0
933 05:52:48.713672 1, 0xFFFF, sum = 0
934 05:52:48.713763 2, 0xFFFF, sum = 0
935 05:52:48.716521 3, 0xFFFF, sum = 0
936 05:52:48.716607 4, 0xFFFF, sum = 0
937 05:52:48.720276 5, 0xFFFF, sum = 0
938 05:52:48.720363 6, 0xFFFF, sum = 0
939 05:52:48.723693 7, 0xFFFF, sum = 0
940 05:52:48.723778 8, 0x0, sum = 1
941 05:52:48.727050 9, 0x0, sum = 2
942 05:52:48.727137 10, 0x0, sum = 3
943 05:52:48.730327 11, 0x0, sum = 4
944 05:52:48.730439 best_step = 9
945 05:52:48.730524
946 05:52:48.730605 ==
947 05:52:48.733800 Dram Type= 6, Freq= 0, CH_0, rank 0
948 05:52:48.740122 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
949 05:52:48.740214 ==
950 05:52:48.740300 RX Vref Scan: 1
951 05:52:48.740380
952 05:52:48.743411 Set Vref Range= 32 -> 127
953 05:52:48.743496
954 05:52:48.746789 RX Vref 32 -> 127, step: 1
955 05:52:48.746874
956 05:52:48.746959 RX Delay -111 -> 252, step: 8
957 05:52:48.750214
958 05:52:48.750299 Set Vref, RX VrefLevel [Byte0]: 32
959 05:52:48.753544 [Byte1]: 32
960 05:52:48.757573
961 05:52:48.757660 Set Vref, RX VrefLevel [Byte0]: 33
962 05:52:48.760901 [Byte1]: 33
963 05:52:48.765295
964 05:52:48.765383 Set Vref, RX VrefLevel [Byte0]: 34
965 05:52:48.768364 [Byte1]: 34
966 05:52:48.773083
967 05:52:48.773170 Set Vref, RX VrefLevel [Byte0]: 35
968 05:52:48.776225 [Byte1]: 35
969 05:52:48.780629
970 05:52:48.780718 Set Vref, RX VrefLevel [Byte0]: 36
971 05:52:48.784089 [Byte1]: 36
972 05:52:48.788074
973 05:52:48.788158 Set Vref, RX VrefLevel [Byte0]: 37
974 05:52:48.791299 [Byte1]: 37
975 05:52:48.795856
976 05:52:48.795978 Set Vref, RX VrefLevel [Byte0]: 38
977 05:52:48.799284 [Byte1]: 38
978 05:52:48.803766
979 05:52:48.803852 Set Vref, RX VrefLevel [Byte0]: 39
980 05:52:48.806759 [Byte1]: 39
981 05:52:48.811273
982 05:52:48.811367 Set Vref, RX VrefLevel [Byte0]: 40
983 05:52:48.814377 [Byte1]: 40
984 05:52:48.818708
985 05:52:48.818796 Set Vref, RX VrefLevel [Byte0]: 41
986 05:52:48.821859 [Byte1]: 41
987 05:52:48.826397
988 05:52:48.829613 Set Vref, RX VrefLevel [Byte0]: 42
989 05:52:48.832833 [Byte1]: 42
990 05:52:48.832922
991 05:52:48.836269 Set Vref, RX VrefLevel [Byte0]: 43
992 05:52:48.839721 [Byte1]: 43
993 05:52:48.839809
994 05:52:48.842715 Set Vref, RX VrefLevel [Byte0]: 44
995 05:52:48.846076 [Byte1]: 44
996 05:52:48.846162
997 05:52:48.849377 Set Vref, RX VrefLevel [Byte0]: 45
998 05:52:48.852728 [Byte1]: 45
999 05:52:48.856923
1000 05:52:48.857009 Set Vref, RX VrefLevel [Byte0]: 46
1001 05:52:48.860367 [Byte1]: 46
1002 05:52:48.864649
1003 05:52:48.864770 Set Vref, RX VrefLevel [Byte0]: 47
1004 05:52:48.868210 [Byte1]: 47
1005 05:52:48.872456
1006 05:52:48.872539 Set Vref, RX VrefLevel [Byte0]: 48
1007 05:52:48.875446 [Byte1]: 48
1008 05:52:48.879829
1009 05:52:48.879914 Set Vref, RX VrefLevel [Byte0]: 49
1010 05:52:48.883116 [Byte1]: 49
1011 05:52:48.887590
1012 05:52:48.887676 Set Vref, RX VrefLevel [Byte0]: 50
1013 05:52:48.890819 [Byte1]: 50
1014 05:52:48.895520
1015 05:52:48.895607 Set Vref, RX VrefLevel [Byte0]: 51
1016 05:52:48.898409 [Byte1]: 51
1017 05:52:48.902653
1018 05:52:48.902739 Set Vref, RX VrefLevel [Byte0]: 52
1019 05:52:48.906097 [Byte1]: 52
1020 05:52:48.910253
1021 05:52:48.910343 Set Vref, RX VrefLevel [Byte0]: 53
1022 05:52:48.914033 [Byte1]: 53
1023 05:52:48.918033
1024 05:52:48.918126 Set Vref, RX VrefLevel [Byte0]: 54
1025 05:52:48.921231 [Byte1]: 54
1026 05:52:48.925675
1027 05:52:48.925766 Set Vref, RX VrefLevel [Byte0]: 55
1028 05:52:48.929105 [Byte1]: 55
1029 05:52:48.933379
1030 05:52:48.933473 Set Vref, RX VrefLevel [Byte0]: 56
1031 05:52:48.936940 [Byte1]: 56
1032 05:52:48.941403
1033 05:52:48.941496 Set Vref, RX VrefLevel [Byte0]: 57
1034 05:52:48.944313 [Byte1]: 57
1035 05:52:48.948607
1036 05:52:48.948695 Set Vref, RX VrefLevel [Byte0]: 58
1037 05:52:48.952201 [Byte1]: 58
1038 05:52:48.956050
1039 05:52:48.956141 Set Vref, RX VrefLevel [Byte0]: 59
1040 05:52:48.959484 [Byte1]: 59
1041 05:52:48.963879
1042 05:52:48.963976 Set Vref, RX VrefLevel [Byte0]: 60
1043 05:52:48.967202 [Byte1]: 60
1044 05:52:48.971426
1045 05:52:48.971515 Set Vref, RX VrefLevel [Byte0]: 61
1046 05:52:48.975066 [Byte1]: 61
1047 05:52:48.979513
1048 05:52:48.979601 Set Vref, RX VrefLevel [Byte0]: 62
1049 05:52:48.982700 [Byte1]: 62
1050 05:52:48.986870
1051 05:52:48.986959 Set Vref, RX VrefLevel [Byte0]: 63
1052 05:52:48.990556 [Byte1]: 63
1053 05:52:48.994583
1054 05:52:48.994674 Set Vref, RX VrefLevel [Byte0]: 64
1055 05:52:48.997782 [Byte1]: 64
1056 05:52:49.002526
1057 05:52:49.002620 Set Vref, RX VrefLevel [Byte0]: 65
1058 05:52:49.005561 [Byte1]: 65
1059 05:52:49.010018
1060 05:52:49.010111 Set Vref, RX VrefLevel [Byte0]: 66
1061 05:52:49.013385 [Byte1]: 66
1062 05:52:49.017726
1063 05:52:49.017816 Set Vref, RX VrefLevel [Byte0]: 67
1064 05:52:49.020587 [Byte1]: 67
1065 05:52:49.025237
1066 05:52:49.025332 Set Vref, RX VrefLevel [Byte0]: 68
1067 05:52:49.028479 [Byte1]: 68
1068 05:52:49.033106
1069 05:52:49.033197 Set Vref, RX VrefLevel [Byte0]: 69
1070 05:52:49.036444 [Byte1]: 69
1071 05:52:49.040606
1072 05:52:49.040712 Set Vref, RX VrefLevel [Byte0]: 70
1073 05:52:49.043840 [Byte1]: 70
1074 05:52:49.048339
1075 05:52:49.048433 Set Vref, RX VrefLevel [Byte0]: 71
1076 05:52:49.051510 [Byte1]: 71
1077 05:52:49.055951
1078 05:52:49.056039 Set Vref, RX VrefLevel [Byte0]: 72
1079 05:52:49.058964 [Byte1]: 72
1080 05:52:49.063351
1081 05:52:49.063439 Set Vref, RX VrefLevel [Byte0]: 73
1082 05:52:49.066385 [Byte1]: 73
1083 05:52:49.071487
1084 05:52:49.071584 Set Vref, RX VrefLevel [Byte0]: 74
1085 05:52:49.074157 [Byte1]: 74
1086 05:52:49.078795
1087 05:52:49.078887 Final RX Vref Byte 0 = 52 to rank0
1088 05:52:49.082305 Final RX Vref Byte 1 = 54 to rank0
1089 05:52:49.085565 Final RX Vref Byte 0 = 52 to rank1
1090 05:52:49.088698 Final RX Vref Byte 1 = 54 to rank1==
1091 05:52:49.091696 Dram Type= 6, Freq= 0, CH_0, rank 0
1092 05:52:49.098664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1093 05:52:49.098778 ==
1094 05:52:49.098848 DQS Delay:
1095 05:52:49.098909 DQS0 = 0, DQS1 = 0
1096 05:52:49.101886 DQM Delay:
1097 05:52:49.101970 DQM0 = 84, DQM1 = 73
1098 05:52:49.105327 DQ Delay:
1099 05:52:49.108857 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1100 05:52:49.108948 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1101 05:52:49.112058 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1102 05:52:49.118685 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1103 05:52:49.118786
1104 05:52:49.118852
1105 05:52:49.125466 [DQSOSCAuto] RK0, (LSB)MR18= 0x3232, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1106 05:52:49.128687 CH0 RK0: MR19=606, MR18=3232
1107 05:52:49.135223 CH0_RK0: MR19=0x606, MR18=0x3232, DQSOSC=397, MR23=63, INC=93, DEC=62
1108 05:52:49.135331
1109 05:52:49.138756 ----->DramcWriteLeveling(PI) begin...
1110 05:52:49.138846 ==
1111 05:52:49.141903 Dram Type= 6, Freq= 0, CH_0, rank 1
1112 05:52:49.145949 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1113 05:52:49.146040 ==
1114 05:52:49.148403 Write leveling (Byte 0): 31 => 31
1115 05:52:49.152065 Write leveling (Byte 1): 29 => 29
1116 05:52:49.155281 DramcWriteLeveling(PI) end<-----
1117 05:52:49.155372
1118 05:52:49.155437 ==
1119 05:52:49.159000 Dram Type= 6, Freq= 0, CH_0, rank 1
1120 05:52:49.162211 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1121 05:52:49.162300 ==
1122 05:52:49.165347 [Gating] SW mode calibration
1123 05:52:49.171913 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1124 05:52:49.178436 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1125 05:52:49.182405 0 6 0 | B1->B0 | 3333 3030 | 0 1 | (0 1) (0 0)
1126 05:52:49.185394 0 6 4 | B1->B0 | 2525 2323 | 1 0 | (0 0) (1 0)
1127 05:52:49.192053 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1128 05:52:49.195242 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1129 05:52:49.198744 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1130 05:52:49.205434 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1131 05:52:49.209059 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1132 05:52:49.212321 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1133 05:52:49.218726 0 7 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1134 05:52:49.221863 0 7 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1135 05:52:49.225703 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1136 05:52:49.231825 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1137 05:52:49.235665 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1138 05:52:49.238434 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1139 05:52:49.242300 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1140 05:52:49.248486 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1141 05:52:49.251868 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1142 05:52:49.255405 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1143 05:52:49.262423 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1144 05:52:49.265513 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1145 05:52:49.268445 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1146 05:52:49.275365 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1147 05:52:49.279007 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1148 05:52:49.282228 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1149 05:52:49.288701 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1150 05:52:49.291947 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1151 05:52:49.295752 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1152 05:52:49.302370 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1153 05:52:49.305182 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1154 05:52:49.308940 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1155 05:52:49.315268 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1156 05:52:49.318771 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1157 05:52:49.322079 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1158 05:52:49.328982 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1159 05:52:49.331664 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1160 05:52:49.335211 Total UI for P1: 0, mck2ui 16
1161 05:52:49.338702 best dqsien dly found for B0: ( 0, 10, 4)
1162 05:52:49.341719 Total UI for P1: 0, mck2ui 16
1163 05:52:49.345400 best dqsien dly found for B1: ( 0, 10, 4)
1164 05:52:49.348385 best DQS0 dly(MCK, UI, PI) = (0, 10, 4)
1165 05:52:49.351854 best DQS1 dly(MCK, UI, PI) = (0, 10, 4)
1166 05:52:49.351939
1167 05:52:49.355304 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 4)
1168 05:52:49.358385 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 4)
1169 05:52:49.361677 [Gating] SW calibration Done
1170 05:52:49.361761 ==
1171 05:52:49.365164 Dram Type= 6, Freq= 0, CH_0, rank 1
1172 05:52:49.409368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1173 05:52:49.409514 ==
1174 05:52:49.409598 RX Vref Scan: 0
1175 05:52:49.409660
1176 05:52:49.409953 RX Vref 0 -> 0, step: 1
1177 05:52:49.410034
1178 05:52:49.410099 RX Delay -130 -> 252, step: 16
1179 05:52:49.410420 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1180 05:52:49.410948 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1181 05:52:49.411029 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1182 05:52:49.411279 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1183 05:52:49.411732 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1184 05:52:49.412084 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1185 05:52:49.412165 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1186 05:52:49.412508 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1187 05:52:49.441510 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1188 05:52:49.441643 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1189 05:52:49.441926 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1190 05:52:49.442374 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1191 05:52:49.442735 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1192 05:52:49.442817 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1193 05:52:49.443293 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1194 05:52:49.443696 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1195 05:52:49.443777 ==
1196 05:52:49.443842 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 05:52:49.449779 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1198 05:52:49.449867 ==
1199 05:52:49.449933 DQS Delay:
1200 05:52:49.449993 DQS0 = 0, DQS1 = 0
1201 05:52:49.453255 DQM Delay:
1202 05:52:49.453338 DQM0 = 82, DQM1 = 74
1203 05:52:49.456472 DQ Delay:
1204 05:52:49.459743 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1205 05:52:49.462949 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1206 05:52:49.466265 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1207 05:52:49.469447 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1208 05:52:49.469523
1209 05:52:49.469586
1210 05:52:49.469645 ==
1211 05:52:49.472767 Dram Type= 6, Freq= 0, CH_0, rank 1
1212 05:52:49.476060 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1213 05:52:49.476144 ==
1214 05:52:49.476208
1215 05:52:49.476269
1216 05:52:49.479582 TX Vref Scan disable
1217 05:52:49.479665 == TX Byte 0 ==
1218 05:52:49.486061 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1219 05:52:49.489798 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1220 05:52:49.489877 == TX Byte 1 ==
1221 05:52:49.496591 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1222 05:52:49.499896 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1223 05:52:49.499982 ==
1224 05:52:49.502882 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 05:52:49.506148 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1226 05:52:49.506232 ==
1227 05:52:49.520098 TX Vref=22, minBit 9, minWin=27, winSum=448
1228 05:52:49.523151 TX Vref=24, minBit 0, minWin=28, winSum=451
1229 05:52:49.527060 TX Vref=26, minBit 2, minWin=28, winSum=456
1230 05:52:49.529914 TX Vref=28, minBit 2, minWin=28, winSum=459
1231 05:52:49.533119 TX Vref=30, minBit 0, minWin=28, winSum=456
1232 05:52:49.539841 TX Vref=32, minBit 0, minWin=28, winSum=454
1233 05:52:49.542974 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 28
1234 05:52:49.543054
1235 05:52:49.546756 Final TX Range 1 Vref 28
1236 05:52:49.546841
1237 05:52:49.546904 ==
1238 05:52:49.549782 Dram Type= 6, Freq= 0, CH_0, rank 1
1239 05:52:49.553238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1240 05:52:49.556561 ==
1241 05:52:49.556677
1242 05:52:49.556805
1243 05:52:49.556868 TX Vref Scan disable
1244 05:52:49.559968 == TX Byte 0 ==
1245 05:52:49.563363 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1246 05:52:49.569906 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1247 05:52:49.569984 == TX Byte 1 ==
1248 05:52:49.572987 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1249 05:52:49.579759 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1250 05:52:49.579849
1251 05:52:49.579913 [DATLAT]
1252 05:52:49.579973 Freq=800, CH0 RK1
1253 05:52:49.580040
1254 05:52:49.583330 DATLAT Default: 0x9
1255 05:52:49.583419 0, 0xFFFF, sum = 0
1256 05:52:49.586390 1, 0xFFFF, sum = 0
1257 05:52:49.586467 2, 0xFFFF, sum = 0
1258 05:52:49.589979 3, 0xFFFF, sum = 0
1259 05:52:49.590063 4, 0xFFFF, sum = 0
1260 05:52:49.593180 5, 0xFFFF, sum = 0
1261 05:52:49.596667 6, 0xFFFF, sum = 0
1262 05:52:49.596786 7, 0xFFFF, sum = 0
1263 05:52:49.596890 8, 0x0, sum = 1
1264 05:52:49.599908 9, 0x0, sum = 2
1265 05:52:49.599993 10, 0x0, sum = 3
1266 05:52:49.603278 11, 0x0, sum = 4
1267 05:52:49.603386 best_step = 9
1268 05:52:49.603486
1269 05:52:49.603583 ==
1270 05:52:49.606448 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 05:52:49.613795 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1272 05:52:49.613885 ==
1273 05:52:49.613969 RX Vref Scan: 0
1274 05:52:49.614048
1275 05:52:49.617171 RX Vref 0 -> 0, step: 1
1276 05:52:49.617254
1277 05:52:49.620133 RX Delay -111 -> 252, step: 8
1278 05:52:49.623290 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1279 05:52:49.626737 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1280 05:52:49.633184 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1281 05:52:49.636926 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1282 05:52:49.639881 iDelay=217, Bit 4, Center 92 (-23 ~ 208) 232
1283 05:52:49.643165 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1284 05:52:49.646611 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1285 05:52:49.651005 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1286 05:52:49.656877 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1287 05:52:49.659984 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1288 05:52:49.663241 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1289 05:52:49.666771 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1290 05:52:49.673494 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1291 05:52:49.676597 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1292 05:52:49.679903 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1293 05:52:49.683560 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1294 05:52:49.683646 ==
1295 05:52:49.686739 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 05:52:49.693327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1297 05:52:49.693412 ==
1298 05:52:49.693495 DQS Delay:
1299 05:52:49.693593 DQS0 = 0, DQS1 = 0
1300 05:52:49.696653 DQM Delay:
1301 05:52:49.696786 DQM0 = 87, DQM1 = 74
1302 05:52:49.699888 DQ Delay:
1303 05:52:49.702953 DQ0 =80, DQ1 =88, DQ2 =88, DQ3 =84
1304 05:52:49.703025 DQ4 =92, DQ5 =76, DQ6 =92, DQ7 =96
1305 05:52:49.706277 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1306 05:52:49.709791 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1307 05:52:49.713237
1308 05:52:49.713359
1309 05:52:49.719700 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d3d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1310 05:52:49.723298 CH0 RK1: MR19=606, MR18=3D3D
1311 05:52:49.729725 CH0_RK1: MR19=0x606, MR18=0x3D3D, DQSOSC=394, MR23=63, INC=95, DEC=63
1312 05:52:49.733097 [RxdqsGatingPostProcess] freq 800
1313 05:52:49.736288 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1314 05:52:49.740129 Pre-setting of DQS Precalculation
1315 05:52:49.746380 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1316 05:52:49.746466 ==
1317 05:52:49.749668 Dram Type= 6, Freq= 0, CH_1, rank 0
1318 05:52:49.753516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1319 05:52:49.753600 ==
1320 05:52:49.759496 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1321 05:52:49.763128 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1322 05:52:49.772904 [CA 0] Center 36 (6~67) winsize 62
1323 05:52:49.776067 [CA 1] Center 36 (6~67) winsize 62
1324 05:52:49.779410 [CA 2] Center 34 (4~65) winsize 62
1325 05:52:49.782592 [CA 3] Center 34 (4~65) winsize 62
1326 05:52:49.786139 [CA 4] Center 33 (3~64) winsize 62
1327 05:52:49.789206 [CA 5] Center 33 (2~64) winsize 63
1328 05:52:49.789281
1329 05:52:49.792654 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1330 05:52:49.792753
1331 05:52:49.795726 [CATrainingPosCal] consider 1 rank data
1332 05:52:49.799428 u2DelayCellTimex100 = 270/100 ps
1333 05:52:49.802652 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1334 05:52:49.809404 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1335 05:52:49.812317 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1336 05:52:49.815690 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1337 05:52:49.819075 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1338 05:52:49.822366 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
1339 05:52:49.822452
1340 05:52:49.825827 CA PerBit enable=1, Macro0, CA PI delay=33
1341 05:52:49.825910
1342 05:52:49.829060 [CBTSetCACLKResult] CA Dly = 33
1343 05:52:49.829148 CS Dly: 4 (0~35)
1344 05:52:49.832802 ==
1345 05:52:49.832880 Dram Type= 6, Freq= 0, CH_1, rank 1
1346 05:52:49.839166 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1347 05:52:49.839248 ==
1348 05:52:49.842437 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1349 05:52:49.848971 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1350 05:52:49.858336 [CA 0] Center 36 (6~67) winsize 62
1351 05:52:49.861626 [CA 1] Center 36 (6~67) winsize 62
1352 05:52:49.864882 [CA 2] Center 34 (4~65) winsize 62
1353 05:52:49.868810 [CA 3] Center 34 (4~64) winsize 61
1354 05:52:49.871856 [CA 4] Center 33 (3~64) winsize 62
1355 05:52:49.875427 [CA 5] Center 33 (3~64) winsize 62
1356 05:52:49.875509
1357 05:52:49.878862 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1358 05:52:49.878943
1359 05:52:49.882107 [CATrainingPosCal] consider 2 rank data
1360 05:52:49.885394 u2DelayCellTimex100 = 270/100 ps
1361 05:52:49.888741 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1362 05:52:49.891779 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1363 05:52:49.898792 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1364 05:52:49.901816 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1365 05:52:49.905415 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1366 05:52:49.908504 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1367 05:52:49.908610
1368 05:52:49.912349 CA PerBit enable=1, Macro0, CA PI delay=33
1369 05:52:49.912430
1370 05:52:49.915179 [CBTSetCACLKResult] CA Dly = 33
1371 05:52:49.915261 CS Dly: 4 (0~36)
1372 05:52:49.915325
1373 05:52:49.918980 ----->DramcWriteLeveling(PI) begin...
1374 05:52:49.921635 ==
1375 05:52:49.921761 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 05:52:49.928469 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1377 05:52:49.928564 ==
1378 05:52:49.932007 Write leveling (Byte 0): 23 => 23
1379 05:52:49.935187 Write leveling (Byte 1): 23 => 23
1380 05:52:49.938575 DramcWriteLeveling(PI) end<-----
1381 05:52:49.938676
1382 05:52:49.938774 ==
1383 05:52:49.941760 Dram Type= 6, Freq= 0, CH_1, rank 0
1384 05:52:49.945327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1385 05:52:49.945413 ==
1386 05:52:49.948571 [Gating] SW mode calibration
1387 05:52:49.955478 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1388 05:52:49.958550 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1389 05:52:49.964960 0 6 0 | B1->B0 | 3030 2424 | 0 0 | (1 0) (0 0)
1390 05:52:49.968699 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1391 05:52:49.971646 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1392 05:52:49.978773 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1393 05:52:49.981681 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1394 05:52:49.984903 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1395 05:52:49.991713 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1396 05:52:49.994983 0 6 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1397 05:52:49.998842 0 7 0 | B1->B0 | 3030 4343 | 0 0 | (0 0) (0 0)
1398 05:52:50.004865 0 7 4 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
1399 05:52:50.008383 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1400 05:52:50.011878 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1401 05:52:50.018570 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1402 05:52:50.021531 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1403 05:52:50.025231 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1404 05:52:50.031523 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1405 05:52:50.034839 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1406 05:52:50.038156 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1407 05:52:50.045283 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1408 05:52:50.048455 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1409 05:52:50.051936 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1410 05:52:50.055174 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1411 05:52:50.061852 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1412 05:52:50.065008 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1413 05:52:50.068088 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1414 05:52:50.075110 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1415 05:52:50.078345 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1416 05:52:50.081689 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1417 05:52:50.088386 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1418 05:52:50.091732 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1419 05:52:50.094872 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1420 05:52:50.101358 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1421 05:52:50.104604 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1422 05:52:50.108178 Total UI for P1: 0, mck2ui 16
1423 05:52:50.111394 best dqsien dly found for B0: ( 0, 9, 30)
1424 05:52:50.115253 Total UI for P1: 0, mck2ui 16
1425 05:52:50.117966 best dqsien dly found for B1: ( 0, 9, 30)
1426 05:52:50.121500 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1427 05:52:50.124986 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1428 05:52:50.125067
1429 05:52:50.127900 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1430 05:52:50.131443 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1431 05:52:50.134931 [Gating] SW calibration Done
1432 05:52:50.135012 ==
1433 05:52:50.138345 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 05:52:50.141375 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1435 05:52:50.144999 ==
1436 05:52:50.145080 RX Vref Scan: 0
1437 05:52:50.145144
1438 05:52:50.148287 RX Vref 0 -> 0, step: 1
1439 05:52:50.148367
1440 05:52:50.151465 RX Delay -130 -> 252, step: 16
1441 05:52:50.154629 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1442 05:52:50.158389 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1443 05:52:50.161509 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1444 05:52:50.164884 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1445 05:52:50.171942 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1446 05:52:50.174906 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1447 05:52:50.177848 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1448 05:52:50.181364 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1449 05:52:50.185103 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1450 05:52:50.191238 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1451 05:52:50.194796 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1452 05:52:50.197889 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1453 05:52:50.201561 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1454 05:52:50.204880 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1455 05:52:50.211158 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1456 05:52:50.214717 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1457 05:52:50.214804 ==
1458 05:52:50.218255 Dram Type= 6, Freq= 0, CH_1, rank 0
1459 05:52:50.221285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1460 05:52:50.221368 ==
1461 05:52:50.224612 DQS Delay:
1462 05:52:50.224741 DQS0 = 0, DQS1 = 0
1463 05:52:50.224823 DQM Delay:
1464 05:52:50.227729 DQM0 = 81, DQM1 = 71
1465 05:52:50.227801 DQ Delay:
1466 05:52:50.231503 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1467 05:52:50.234483 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1468 05:52:50.238260 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1469 05:52:50.241084 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1470 05:52:50.241164
1471 05:52:50.241227
1472 05:52:50.241285 ==
1473 05:52:50.244418 Dram Type= 6, Freq= 0, CH_1, rank 0
1474 05:52:50.251530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1475 05:52:50.251611 ==
1476 05:52:50.251674
1477 05:52:50.251731
1478 05:52:50.251786 TX Vref Scan disable
1479 05:52:50.254799 == TX Byte 0 ==
1480 05:52:50.257735 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1481 05:52:50.261450 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1482 05:52:50.264569 == TX Byte 1 ==
1483 05:52:50.268168 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1484 05:52:50.271145 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1485 05:52:50.274594 ==
1486 05:52:50.277725 Dram Type= 6, Freq= 0, CH_1, rank 0
1487 05:52:50.281086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1488 05:52:50.281167 ==
1489 05:52:50.293168 TX Vref=22, minBit 0, minWin=27, winSum=453
1490 05:52:50.296845 TX Vref=24, minBit 0, minWin=27, winSum=454
1491 05:52:50.299668 TX Vref=26, minBit 3, minWin=28, winSum=460
1492 05:52:50.303318 TX Vref=28, minBit 3, minWin=28, winSum=461
1493 05:52:50.306674 TX Vref=30, minBit 3, minWin=28, winSum=461
1494 05:52:50.309856 TX Vref=32, minBit 3, minWin=28, winSum=460
1495 05:52:50.316542 [TxChooseVref] Worse bit 3, Min win 28, Win sum 461, Final Vref 28
1496 05:52:50.316656
1497 05:52:50.319657 Final TX Range 1 Vref 28
1498 05:52:50.319768
1499 05:52:50.319844 ==
1500 05:52:50.323320 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 05:52:50.326525 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1502 05:52:50.326636 ==
1503 05:52:50.329878
1504 05:52:50.329958
1505 05:52:50.330025 TX Vref Scan disable
1506 05:52:50.333764 == TX Byte 0 ==
1507 05:52:50.336382 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1508 05:52:50.343104 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1509 05:52:50.343192 == TX Byte 1 ==
1510 05:52:50.346285 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1511 05:52:50.353044 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1512 05:52:50.353127
1513 05:52:50.353191 [DATLAT]
1514 05:52:50.353249 Freq=800, CH1 RK0
1515 05:52:50.353306
1516 05:52:50.356684 DATLAT Default: 0xa
1517 05:52:50.356807 0, 0xFFFF, sum = 0
1518 05:52:50.359955 1, 0xFFFF, sum = 0
1519 05:52:50.360037 2, 0xFFFF, sum = 0
1520 05:52:50.363094 3, 0xFFFF, sum = 0
1521 05:52:50.366379 4, 0xFFFF, sum = 0
1522 05:52:50.366482 5, 0xFFFF, sum = 0
1523 05:52:50.369905 6, 0xFFFF, sum = 0
1524 05:52:50.370001 7, 0xFFFF, sum = 0
1525 05:52:50.370064 8, 0x0, sum = 1
1526 05:52:50.373212 9, 0x0, sum = 2
1527 05:52:50.373283 10, 0x0, sum = 3
1528 05:52:50.376156 11, 0x0, sum = 4
1529 05:52:50.376229 best_step = 9
1530 05:52:50.376297
1531 05:52:50.376355 ==
1532 05:52:50.379555 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 05:52:50.386215 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1534 05:52:50.386320 ==
1535 05:52:50.386421 RX Vref Scan: 1
1536 05:52:50.386498
1537 05:52:50.389641 Set Vref Range= 32 -> 127
1538 05:52:50.389719
1539 05:52:50.393031 RX Vref 32 -> 127, step: 1
1540 05:52:50.393103
1541 05:52:50.396271 RX Delay -111 -> 252, step: 8
1542 05:52:50.396342
1543 05:52:50.396416 Set Vref, RX VrefLevel [Byte0]: 32
1544 05:52:50.399896 [Byte1]: 32
1545 05:52:50.404161
1546 05:52:50.404279 Set Vref, RX VrefLevel [Byte0]: 33
1547 05:52:50.407477 [Byte1]: 33
1548 05:52:50.412048
1549 05:52:50.412129 Set Vref, RX VrefLevel [Byte0]: 34
1550 05:52:50.415331 [Byte1]: 34
1551 05:52:50.419368
1552 05:52:50.419448 Set Vref, RX VrefLevel [Byte0]: 35
1553 05:52:50.422571 [Byte1]: 35
1554 05:52:50.427312
1555 05:52:50.427394 Set Vref, RX VrefLevel [Byte0]: 36
1556 05:52:50.430297 [Byte1]: 36
1557 05:52:50.434563
1558 05:52:50.434641 Set Vref, RX VrefLevel [Byte0]: 37
1559 05:52:50.437980 [Byte1]: 37
1560 05:52:50.442263
1561 05:52:50.442343 Set Vref, RX VrefLevel [Byte0]: 38
1562 05:52:50.445527 [Byte1]: 38
1563 05:52:50.449945
1564 05:52:50.450025 Set Vref, RX VrefLevel [Byte0]: 39
1565 05:52:50.453420 [Byte1]: 39
1566 05:52:50.457655
1567 05:52:50.457735 Set Vref, RX VrefLevel [Byte0]: 40
1568 05:52:50.460687 [Byte1]: 40
1569 05:52:50.465466
1570 05:52:50.465586 Set Vref, RX VrefLevel [Byte0]: 41
1571 05:52:50.468392 [Byte1]: 41
1572 05:52:50.472805
1573 05:52:50.472877 Set Vref, RX VrefLevel [Byte0]: 42
1574 05:52:50.476189 [Byte1]: 42
1575 05:52:50.480471
1576 05:52:50.480541 Set Vref, RX VrefLevel [Byte0]: 43
1577 05:52:50.483772 [Byte1]: 43
1578 05:52:50.488282
1579 05:52:50.488356 Set Vref, RX VrefLevel [Byte0]: 44
1580 05:52:50.491386 [Byte1]: 44
1581 05:52:50.495739
1582 05:52:50.495831 Set Vref, RX VrefLevel [Byte0]: 45
1583 05:52:50.499034 [Byte1]: 45
1584 05:52:50.503265
1585 05:52:50.503360 Set Vref, RX VrefLevel [Byte0]: 46
1586 05:52:50.507068 [Byte1]: 46
1587 05:52:50.511245
1588 05:52:50.511324 Set Vref, RX VrefLevel [Byte0]: 47
1589 05:52:50.514729 [Byte1]: 47
1590 05:52:50.518922
1591 05:52:50.519007 Set Vref, RX VrefLevel [Byte0]: 48
1592 05:52:50.522148 [Byte1]: 48
1593 05:52:50.526619
1594 05:52:50.526699 Set Vref, RX VrefLevel [Byte0]: 49
1595 05:52:50.529934 [Byte1]: 49
1596 05:52:50.534001
1597 05:52:50.534081 Set Vref, RX VrefLevel [Byte0]: 50
1598 05:52:50.537234 [Byte1]: 50
1599 05:52:50.541680
1600 05:52:50.541766 Set Vref, RX VrefLevel [Byte0]: 51
1601 05:52:50.545338 [Byte1]: 51
1602 05:52:50.549538
1603 05:52:50.549624 Set Vref, RX VrefLevel [Byte0]: 52
1604 05:52:50.552665 [Byte1]: 52
1605 05:52:50.557227
1606 05:52:50.557308 Set Vref, RX VrefLevel [Byte0]: 53
1607 05:52:50.560196 [Byte1]: 53
1608 05:52:50.564488
1609 05:52:50.564596 Set Vref, RX VrefLevel [Byte0]: 54
1610 05:52:50.568010 [Byte1]: 54
1611 05:52:50.572355
1612 05:52:50.572437 Set Vref, RX VrefLevel [Byte0]: 55
1613 05:52:50.575780 [Byte1]: 55
1614 05:52:50.579889
1615 05:52:50.579958 Set Vref, RX VrefLevel [Byte0]: 56
1616 05:52:50.583625 [Byte1]: 56
1617 05:52:50.587749
1618 05:52:50.587829 Set Vref, RX VrefLevel [Byte0]: 57
1619 05:52:50.591073 [Byte1]: 57
1620 05:52:50.595137
1621 05:52:50.595217 Set Vref, RX VrefLevel [Byte0]: 58
1622 05:52:50.598960 [Byte1]: 58
1623 05:52:50.602776
1624 05:52:50.602863 Set Vref, RX VrefLevel [Byte0]: 59
1625 05:52:50.606000 [Byte1]: 59
1626 05:52:50.610542
1627 05:52:50.610622 Set Vref, RX VrefLevel [Byte0]: 60
1628 05:52:50.613635 [Byte1]: 60
1629 05:52:50.618348
1630 05:52:50.618430 Set Vref, RX VrefLevel [Byte0]: 61
1631 05:52:50.621642 [Byte1]: 61
1632 05:52:50.625833
1633 05:52:50.625914 Set Vref, RX VrefLevel [Byte0]: 62
1634 05:52:50.628969 [Byte1]: 62
1635 05:52:50.633569
1636 05:52:50.633649 Set Vref, RX VrefLevel [Byte0]: 63
1637 05:52:50.637184 [Byte1]: 63
1638 05:52:50.641514
1639 05:52:50.641593 Set Vref, RX VrefLevel [Byte0]: 64
1640 05:52:50.644364 [Byte1]: 64
1641 05:52:50.648930
1642 05:52:50.649007 Set Vref, RX VrefLevel [Byte0]: 65
1643 05:52:50.652384 [Byte1]: 65
1644 05:52:50.656305
1645 05:52:50.656427 Set Vref, RX VrefLevel [Byte0]: 66
1646 05:52:50.659994 [Byte1]: 66
1647 05:52:50.664135
1648 05:52:50.664213 Set Vref, RX VrefLevel [Byte0]: 67
1649 05:52:50.667548 [Byte1]: 67
1650 05:52:50.671564
1651 05:52:50.671638 Set Vref, RX VrefLevel [Byte0]: 68
1652 05:52:50.674913 [Byte1]: 68
1653 05:52:50.679392
1654 05:52:50.679465 Set Vref, RX VrefLevel [Byte0]: 69
1655 05:52:50.682567 [Byte1]: 69
1656 05:52:50.687013
1657 05:52:50.687094 Set Vref, RX VrefLevel [Byte0]: 70
1658 05:52:50.690412 [Byte1]: 70
1659 05:52:50.694873
1660 05:52:50.694957 Set Vref, RX VrefLevel [Byte0]: 71
1661 05:52:50.698284 [Byte1]: 71
1662 05:52:50.702555
1663 05:52:50.702646 Set Vref, RX VrefLevel [Byte0]: 72
1664 05:52:50.705928 [Byte1]: 72
1665 05:52:50.709987
1666 05:52:50.710060 Set Vref, RX VrefLevel [Byte0]: 73
1667 05:52:50.713488 [Byte1]: 73
1668 05:52:50.717728
1669 05:52:50.717809 Set Vref, RX VrefLevel [Byte0]: 74
1670 05:52:50.721316 [Byte1]: 74
1671 05:52:50.725208
1672 05:52:50.725285 Set Vref, RX VrefLevel [Byte0]: 75
1673 05:52:50.728407 [Byte1]: 75
1674 05:52:50.732860
1675 05:52:50.732937 Final RX Vref Byte 0 = 56 to rank0
1676 05:52:50.736141 Final RX Vref Byte 1 = 53 to rank0
1677 05:52:50.739711 Final RX Vref Byte 0 = 56 to rank1
1678 05:52:50.742584 Final RX Vref Byte 1 = 53 to rank1==
1679 05:52:50.746061 Dram Type= 6, Freq= 0, CH_1, rank 0
1680 05:52:50.753144 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1681 05:52:50.753226 ==
1682 05:52:50.753298 DQS Delay:
1683 05:52:50.753358 DQS0 = 0, DQS1 = 0
1684 05:52:50.756274 DQM Delay:
1685 05:52:50.756372 DQM0 = 79, DQM1 = 71
1686 05:52:50.759782 DQ Delay:
1687 05:52:50.762561 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
1688 05:52:50.766076 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1689 05:52:50.769585 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1690 05:52:50.772587 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1691 05:52:50.772688
1692 05:52:50.772806
1693 05:52:50.779346 [DQSOSCAuto] RK0, (LSB)MR18= 0x4646, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1694 05:52:50.782834 CH1 RK0: MR19=606, MR18=4646
1695 05:52:50.789416 CH1_RK0: MR19=0x606, MR18=0x4646, DQSOSC=392, MR23=63, INC=96, DEC=64
1696 05:52:50.789505
1697 05:52:50.792632 ----->DramcWriteLeveling(PI) begin...
1698 05:52:50.792778 ==
1699 05:52:50.796038 Dram Type= 6, Freq= 0, CH_1, rank 1
1700 05:52:50.799310 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1701 05:52:50.799393 ==
1702 05:52:50.802766 Write leveling (Byte 0): 23 => 23
1703 05:52:50.806124 Write leveling (Byte 1): 23 => 23
1704 05:52:50.809361 DramcWriteLeveling(PI) end<-----
1705 05:52:50.809436
1706 05:52:50.809508 ==
1707 05:52:50.812653 Dram Type= 6, Freq= 0, CH_1, rank 1
1708 05:52:50.816065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1709 05:52:50.816141 ==
1710 05:52:50.819703 [Gating] SW mode calibration
1711 05:52:50.826157 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1712 05:52:50.832861 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1713 05:52:50.836130 0 6 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
1714 05:52:50.839629 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1715 05:52:50.846484 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1716 05:52:50.849397 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1717 05:52:50.852982 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1718 05:52:50.859654 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1719 05:52:50.862647 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1720 05:52:50.865976 0 6 28 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
1721 05:52:50.872605 0 7 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1722 05:52:50.875987 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1723 05:52:50.879412 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1724 05:52:50.886278 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1725 05:52:50.889648 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1726 05:52:50.892515 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1727 05:52:50.899132 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1728 05:52:50.902930 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1729 05:52:50.906091 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1730 05:52:50.912601 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 05:52:50.915651 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 05:52:50.919251 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 05:52:50.925761 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 05:52:50.929005 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1735 05:52:50.932239 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1736 05:52:50.938990 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1737 05:52:50.942237 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1738 05:52:50.945924 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1739 05:52:50.949260 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1740 05:52:50.955925 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1741 05:52:50.959174 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1742 05:52:50.962243 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1743 05:52:50.968971 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1744 05:52:50.972398 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1745 05:52:50.975435 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1746 05:52:50.978749 Total UI for P1: 0, mck2ui 16
1747 05:52:50.982073 best dqsien dly found for B0: ( 0, 9, 28)
1748 05:52:50.988951 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1749 05:52:50.989100 Total UI for P1: 0, mck2ui 16
1750 05:52:50.995653 best dqsien dly found for B1: ( 0, 9, 30)
1751 05:52:50.999160 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1752 05:52:51.002354 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1753 05:52:51.002474
1754 05:52:51.005444 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1755 05:52:51.008862 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1756 05:52:51.012352 [Gating] SW calibration Done
1757 05:52:51.012451 ==
1758 05:52:51.015670 Dram Type= 6, Freq= 0, CH_1, rank 1
1759 05:52:51.018638 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1760 05:52:51.018736 ==
1761 05:52:51.022360 RX Vref Scan: 0
1762 05:52:51.022465
1763 05:52:51.022559 RX Vref 0 -> 0, step: 1
1764 05:52:51.022621
1765 05:52:51.025290 RX Delay -130 -> 252, step: 16
1766 05:52:51.032064 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1767 05:52:51.035700 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1768 05:52:51.038764 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1769 05:52:51.042301 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1770 05:52:51.045380 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1771 05:52:51.048583 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1772 05:52:51.055421 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1773 05:52:51.058552 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1774 05:52:51.062301 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1775 05:52:51.065389 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1776 05:52:51.071817 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1777 05:52:51.075343 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1778 05:52:51.079010 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1779 05:52:51.081960 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1780 05:52:51.085162 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1781 05:52:51.092145 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1782 05:52:51.092232 ==
1783 05:52:51.095269 Dram Type= 6, Freq= 0, CH_1, rank 1
1784 05:52:51.098455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1785 05:52:51.098531 ==
1786 05:52:51.098592 DQS Delay:
1787 05:52:51.101896 DQS0 = 0, DQS1 = 0
1788 05:52:51.101981 DQM Delay:
1789 05:52:51.105273 DQM0 = 81, DQM1 = 72
1790 05:52:51.105353 DQ Delay:
1791 05:52:51.108527 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1792 05:52:51.111976 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1793 05:52:51.115199 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1794 05:52:51.118576 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1795 05:52:51.118662
1796 05:52:51.118729
1797 05:52:51.118809 ==
1798 05:52:51.122007 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 05:52:51.125182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1800 05:52:51.125271 ==
1801 05:52:51.125341
1802 05:52:51.128325
1803 05:52:51.128468 TX Vref Scan disable
1804 05:52:51.131544 == TX Byte 0 ==
1805 05:52:51.135057 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1806 05:52:51.138207 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1807 05:52:51.141645 == TX Byte 1 ==
1808 05:52:51.145017 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1809 05:52:51.148502 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1810 05:52:51.148606 ==
1811 05:52:51.151611 Dram Type= 6, Freq= 0, CH_1, rank 1
1812 05:52:51.158050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1813 05:52:51.158143 ==
1814 05:52:51.170090 TX Vref=22, minBit 0, minWin=28, winSum=451
1815 05:52:51.173091 TX Vref=24, minBit 0, minWin=28, winSum=454
1816 05:52:51.176477 TX Vref=26, minBit 3, minWin=28, winSum=458
1817 05:52:51.179801 TX Vref=28, minBit 9, minWin=28, winSum=462
1818 05:52:51.183298 TX Vref=30, minBit 0, minWin=28, winSum=458
1819 05:52:51.189766 TX Vref=32, minBit 0, minWin=28, winSum=456
1820 05:52:51.192871 [TxChooseVref] Worse bit 9, Min win 28, Win sum 462, Final Vref 28
1821 05:52:51.192994
1822 05:52:51.196633 Final TX Range 1 Vref 28
1823 05:52:51.196741
1824 05:52:51.196822 ==
1825 05:52:51.199609 Dram Type= 6, Freq= 0, CH_1, rank 1
1826 05:52:51.203339 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1827 05:52:51.203428 ==
1828 05:52:51.206578
1829 05:52:51.206651
1830 05:52:51.206711 TX Vref Scan disable
1831 05:52:51.209442 == TX Byte 0 ==
1832 05:52:51.213145 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1833 05:52:51.219612 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1834 05:52:51.219722 == TX Byte 1 ==
1835 05:52:51.222710 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1836 05:52:51.229413 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1837 05:52:51.229505
1838 05:52:51.229568 [DATLAT]
1839 05:52:51.229628 Freq=800, CH1 RK1
1840 05:52:51.229684
1841 05:52:51.232861 DATLAT Default: 0x9
1842 05:52:51.232965 0, 0xFFFF, sum = 0
1843 05:52:51.236163 1, 0xFFFF, sum = 0
1844 05:52:51.239532 2, 0xFFFF, sum = 0
1845 05:52:51.239613 3, 0xFFFF, sum = 0
1846 05:52:51.242555 4, 0xFFFF, sum = 0
1847 05:52:51.242636 5, 0xFFFF, sum = 0
1848 05:52:51.245967 6, 0xFFFF, sum = 0
1849 05:52:51.246040 7, 0xFFFF, sum = 0
1850 05:52:51.249447 8, 0x0, sum = 1
1851 05:52:51.249519 9, 0x0, sum = 2
1852 05:52:51.249580 10, 0x0, sum = 3
1853 05:52:51.252909 11, 0x0, sum = 4
1854 05:52:51.252981 best_step = 9
1855 05:52:51.253039
1856 05:52:51.253094 ==
1857 05:52:51.256015 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 05:52:51.262308 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1859 05:52:51.262390 ==
1860 05:52:51.262454 RX Vref Scan: 0
1861 05:52:51.262514
1862 05:52:51.266168 RX Vref 0 -> 0, step: 1
1863 05:52:51.266249
1864 05:52:51.269032 RX Delay -111 -> 252, step: 8
1865 05:52:51.272531 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1866 05:52:51.279070 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1867 05:52:51.282434 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1868 05:52:51.285640 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1869 05:52:51.288659 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1870 05:52:51.292116 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1871 05:52:51.298811 iDelay=217, Bit 6, Center 88 (-31 ~ 208) 240
1872 05:52:51.302183 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1873 05:52:51.305785 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1874 05:52:51.308685 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1875 05:52:51.312045 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1876 05:52:51.318609 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1877 05:52:51.322107 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1878 05:52:51.325452 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1879 05:52:51.328582 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1880 05:52:51.332091 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1881 05:52:51.335149 ==
1882 05:52:51.338521 Dram Type= 6, Freq= 0, CH_1, rank 1
1883 05:52:51.342323 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1884 05:52:51.342406 ==
1885 05:52:51.342470 DQS Delay:
1886 05:52:51.345693 DQS0 = 0, DQS1 = 0
1887 05:52:51.345773 DQM Delay:
1888 05:52:51.349133 DQM0 = 82, DQM1 = 72
1889 05:52:51.349213 DQ Delay:
1890 05:52:51.351977 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1891 05:52:51.355294 DQ4 =80, DQ5 =96, DQ6 =88, DQ7 =80
1892 05:52:51.358766 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1893 05:52:51.361947 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =80
1894 05:52:51.362028
1895 05:52:51.362144
1896 05:52:51.368711 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b3b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1897 05:52:51.371955 CH1 RK1: MR19=606, MR18=3B3B
1898 05:52:51.378515 CH1_RK1: MR19=0x606, MR18=0x3B3B, DQSOSC=394, MR23=63, INC=95, DEC=63
1899 05:52:51.381828 [RxdqsGatingPostProcess] freq 800
1900 05:52:51.385420 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1901 05:52:51.388467 Pre-setting of DQS Precalculation
1902 05:52:51.395208 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1903 05:52:51.401864 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1904 05:52:51.408679 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1905 05:52:51.408814
1906 05:52:51.408879
1907 05:52:51.412310 [Calibration Summary] 1600 Mbps
1908 05:52:51.412390 CH 0, Rank 0
1909 05:52:51.415298 SW Impedance : PASS
1910 05:52:51.418459 DUTY Scan : NO K
1911 05:52:51.418540 ZQ Calibration : PASS
1912 05:52:51.422125 Jitter Meter : NO K
1913 05:52:51.425101 CBT Training : PASS
1914 05:52:51.425181 Write leveling : PASS
1915 05:52:51.428553 RX DQS gating : PASS
1916 05:52:51.432475 RX DQ/DQS(RDDQC) : PASS
1917 05:52:51.432557 TX DQ/DQS : PASS
1918 05:52:51.435332 RX DATLAT : PASS
1919 05:52:51.438852 RX DQ/DQS(Engine): PASS
1920 05:52:51.438933 TX OE : NO K
1921 05:52:51.438998 All Pass.
1922 05:52:51.441937
1923 05:52:51.442018 CH 0, Rank 1
1924 05:52:51.445121 SW Impedance : PASS
1925 05:52:51.445201 DUTY Scan : NO K
1926 05:52:51.448616 ZQ Calibration : PASS
1927 05:52:51.448698 Jitter Meter : NO K
1928 05:52:51.451790 CBT Training : PASS
1929 05:52:51.456030 Write leveling : PASS
1930 05:52:51.456170 RX DQS gating : PASS
1931 05:52:51.458406 RX DQ/DQS(RDDQC) : PASS
1932 05:52:51.461877 TX DQ/DQS : PASS
1933 05:52:51.461977 RX DATLAT : PASS
1934 05:52:51.465563 RX DQ/DQS(Engine): PASS
1935 05:52:51.468462 TX OE : NO K
1936 05:52:51.468557 All Pass.
1937 05:52:51.468622
1938 05:52:51.468682 CH 1, Rank 0
1939 05:52:51.471733 SW Impedance : PASS
1940 05:52:51.475381 DUTY Scan : NO K
1941 05:52:51.475463 ZQ Calibration : PASS
1942 05:52:51.478423 Jitter Meter : NO K
1943 05:52:51.482116 CBT Training : PASS
1944 05:52:51.482197 Write leveling : PASS
1945 05:52:51.485248 RX DQS gating : PASS
1946 05:52:51.485329 RX DQ/DQS(RDDQC) : PASS
1947 05:52:51.488591 TX DQ/DQS : PASS
1948 05:52:51.491878 RX DATLAT : PASS
1949 05:52:51.491959 RX DQ/DQS(Engine): PASS
1950 05:52:51.495126 TX OE : NO K
1951 05:52:51.495222 All Pass.
1952 05:52:51.495285
1953 05:52:51.498518 CH 1, Rank 1
1954 05:52:51.498598 SW Impedance : PASS
1955 05:52:51.501734 DUTY Scan : NO K
1956 05:52:51.505284 ZQ Calibration : PASS
1957 05:52:51.505393 Jitter Meter : NO K
1958 05:52:51.508612 CBT Training : PASS
1959 05:52:51.511940 Write leveling : PASS
1960 05:52:51.512021 RX DQS gating : PASS
1961 05:52:51.515237 RX DQ/DQS(RDDQC) : PASS
1962 05:52:51.518456 TX DQ/DQS : PASS
1963 05:52:51.518538 RX DATLAT : PASS
1964 05:52:51.521948 RX DQ/DQS(Engine): PASS
1965 05:52:51.525170 TX OE : NO K
1966 05:52:51.525251 All Pass.
1967 05:52:51.525314
1968 05:52:51.525379 DramC Write-DBI off
1969 05:52:51.528629 PER_BANK_REFRESH: Hybrid Mode
1970 05:52:51.531684 TX_TRACKING: ON
1971 05:52:51.535416 [GetDramInforAfterCalByMRR] Vendor 6.
1972 05:52:51.538568 [GetDramInforAfterCalByMRR] Revision 606.
1973 05:52:51.541855 [GetDramInforAfterCalByMRR] Revision 2 0.
1974 05:52:51.541936 MR0 0x3939
1975 05:52:51.545157 MR8 0x1111
1976 05:52:51.548266 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1977 05:52:51.548347
1978 05:52:51.548410 MR0 0x3939
1979 05:52:51.548468 MR8 0x1111
1980 05:52:51.551830 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1981 05:52:51.555217
1982 05:52:51.561619 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1983 05:52:51.564975 [FAST_K] Save calibration result to emmc
1984 05:52:51.568332 [FAST_K] Save calibration result to emmc
1985 05:52:51.571732 dram_init: config_dvfs: 1
1986 05:52:51.574973 dramc_set_vcore_voltage set vcore to 662500
1987 05:52:51.578350 Read voltage for 1200, 2
1988 05:52:51.578431 Vio18 = 0
1989 05:52:51.581635 Vcore = 662500
1990 05:52:51.581715 Vdram = 0
1991 05:52:51.581779 Vddq = 0
1992 05:52:51.581838 Vmddr = 0
1993 05:52:51.588716 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1994 05:52:51.595428 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1995 05:52:51.595512 MEM_TYPE=3, freq_sel=15
1996 05:52:51.598209 sv_algorithm_assistance_LP4_1600
1997 05:52:51.601702 ============ PULL DRAM RESETB DOWN ============
1998 05:52:51.608131 ========== PULL DRAM RESETB DOWN end =========
1999 05:52:51.611512 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2000 05:52:51.614692 ===================================
2001 05:52:51.618204 LPDDR4 DRAM CONFIGURATION
2002 05:52:51.621807 ===================================
2003 05:52:51.621892 EX_ROW_EN[0] = 0x0
2004 05:52:51.624841 EX_ROW_EN[1] = 0x0
2005 05:52:51.624921 LP4Y_EN = 0x0
2006 05:52:51.628381 WORK_FSP = 0x0
2007 05:52:51.628462 WL = 0x4
2008 05:52:51.631726 RL = 0x4
2009 05:52:51.631809 BL = 0x2
2010 05:52:51.634940 RPST = 0x0
2011 05:52:51.635022 RD_PRE = 0x0
2012 05:52:51.638330 WR_PRE = 0x1
2013 05:52:51.641509 WR_PST = 0x0
2014 05:52:51.641590 DBI_WR = 0x0
2015 05:52:51.644970 DBI_RD = 0x0
2016 05:52:51.645051 OTF = 0x1
2017 05:52:51.648185 ===================================
2018 05:52:51.651445 ===================================
2019 05:52:51.651527 ANA top config
2020 05:52:51.655182 ===================================
2021 05:52:51.658660 DLL_ASYNC_EN = 0
2022 05:52:51.661831 ALL_SLAVE_EN = 0
2023 05:52:51.665072 NEW_RANK_MODE = 1
2024 05:52:51.668483 DLL_IDLE_MODE = 1
2025 05:52:51.668564 LP45_APHY_COMB_EN = 1
2026 05:52:51.671709 TX_ODT_DIS = 1
2027 05:52:51.675402 NEW_8X_MODE = 1
2028 05:52:51.678402 ===================================
2029 05:52:51.681765 ===================================
2030 05:52:51.685123 data_rate = 2400
2031 05:52:51.688866 CKR = 1
2032 05:52:51.688948 DQ_P2S_RATIO = 8
2033 05:52:51.691716 ===================================
2034 05:52:51.695115 CA_P2S_RATIO = 8
2035 05:52:51.698450 DQ_CA_OPEN = 0
2036 05:52:51.702006 DQ_SEMI_OPEN = 0
2037 05:52:51.705052 CA_SEMI_OPEN = 0
2038 05:52:51.705135 CA_FULL_RATE = 0
2039 05:52:51.708375 DQ_CKDIV4_EN = 0
2040 05:52:51.711713 CA_CKDIV4_EN = 0
2041 05:52:51.714983 CA_PREDIV_EN = 0
2042 05:52:51.718237 PH8_DLY = 17
2043 05:52:51.721709 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2044 05:52:51.724888 DQ_AAMCK_DIV = 4
2045 05:52:51.725014 CA_AAMCK_DIV = 4
2046 05:52:51.728332 CA_ADMCK_DIV = 4
2047 05:52:51.731574 DQ_TRACK_CA_EN = 0
2048 05:52:51.734737 CA_PICK = 1200
2049 05:52:51.738402 CA_MCKIO = 1200
2050 05:52:51.741584 MCKIO_SEMI = 0
2051 05:52:51.745032 PLL_FREQ = 2366
2052 05:52:51.745114 DQ_UI_PI_RATIO = 32
2053 05:52:51.748313 CA_UI_PI_RATIO = 0
2054 05:52:51.751447 ===================================
2055 05:52:51.755003 ===================================
2056 05:52:51.758143 memory_type:LPDDR4
2057 05:52:51.761868 GP_NUM : 10
2058 05:52:51.761951 SRAM_EN : 1
2059 05:52:51.764997 MD32_EN : 0
2060 05:52:51.768600 ===================================
2061 05:52:51.768702 [ANA_INIT] >>>>>>>>>>>>>>
2062 05:52:51.771747 <<<<<< [CONFIGURE PHASE]: ANA_TX
2063 05:52:51.774832 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2064 05:52:51.778261 ===================================
2065 05:52:51.781546 data_rate = 2400,PCW = 0X5b00
2066 05:52:51.784634 ===================================
2067 05:52:51.788233 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2068 05:52:51.795063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2069 05:52:51.798339 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2070 05:52:51.804696 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2071 05:52:51.808407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2072 05:52:51.811404 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2073 05:52:51.814864 [ANA_INIT] flow start
2074 05:52:51.814943 [ANA_INIT] PLL >>>>>>>>
2075 05:52:51.818295 [ANA_INIT] PLL <<<<<<<<
2076 05:52:51.821449 [ANA_INIT] MIDPI >>>>>>>>
2077 05:52:51.821531 [ANA_INIT] MIDPI <<<<<<<<
2078 05:52:51.825046 [ANA_INIT] DLL >>>>>>>>
2079 05:52:51.828006 [ANA_INIT] DLL <<<<<<<<
2080 05:52:51.828077 [ANA_INIT] flow end
2081 05:52:51.834809 ============ LP4 DIFF to SE enter ============
2082 05:52:51.838100 ============ LP4 DIFF to SE exit ============
2083 05:52:51.838174 [ANA_INIT] <<<<<<<<<<<<<
2084 05:52:51.841520 [Flow] Enable top DCM control >>>>>
2085 05:52:51.844863 [Flow] Enable top DCM control <<<<<
2086 05:52:51.847872 Enable DLL master slave shuffle
2087 05:52:51.854340 ==============================================================
2088 05:52:51.858102 Gating Mode config
2089 05:52:51.861123 ==============================================================
2090 05:52:51.864358 Config description:
2091 05:52:51.874330 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2092 05:52:51.881590 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2093 05:52:51.884924 SELPH_MODE 0: By rank 1: By Phase
2094 05:52:51.891254 ==============================================================
2095 05:52:51.894481 GAT_TRACK_EN = 1
2096 05:52:51.897471 RX_GATING_MODE = 2
2097 05:52:51.900851 RX_GATING_TRACK_MODE = 2
2098 05:52:51.900948 SELPH_MODE = 1
2099 05:52:51.904109 PICG_EARLY_EN = 1
2100 05:52:51.907971 VALID_LAT_VALUE = 1
2101 05:52:51.914447 ==============================================================
2102 05:52:51.917611 Enter into Gating configuration >>>>
2103 05:52:51.921127 Exit from Gating configuration <<<<
2104 05:52:51.924187 Enter into DVFS_PRE_config >>>>>
2105 05:52:51.934566 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2106 05:52:51.937529 Exit from DVFS_PRE_config <<<<<
2107 05:52:51.941107 Enter into PICG configuration >>>>
2108 05:52:51.944152 Exit from PICG configuration <<<<
2109 05:52:51.947718 [RX_INPUT] configuration >>>>>
2110 05:52:51.950730 [RX_INPUT] configuration <<<<<
2111 05:52:51.953949 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2112 05:52:51.960851 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2113 05:52:51.967462 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2114 05:52:51.973939 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2115 05:52:51.977387 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2116 05:52:51.984065 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2117 05:52:51.987202 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2118 05:52:51.993973 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2119 05:52:51.997251 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2120 05:52:52.000563 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2121 05:52:52.004466 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2122 05:52:52.010924 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2123 05:52:52.013909 ===================================
2124 05:52:52.013998 LPDDR4 DRAM CONFIGURATION
2125 05:52:52.017439 ===================================
2126 05:52:52.020883 EX_ROW_EN[0] = 0x0
2127 05:52:52.024194 EX_ROW_EN[1] = 0x0
2128 05:52:52.024264 LP4Y_EN = 0x0
2129 05:52:52.027379 WORK_FSP = 0x0
2130 05:52:52.027449 WL = 0x4
2131 05:52:52.030490 RL = 0x4
2132 05:52:52.030568 BL = 0x2
2133 05:52:52.034242 RPST = 0x0
2134 05:52:52.034315 RD_PRE = 0x0
2135 05:52:52.037554 WR_PRE = 0x1
2136 05:52:52.037624 WR_PST = 0x0
2137 05:52:52.040575 DBI_WR = 0x0
2138 05:52:52.040646 DBI_RD = 0x0
2139 05:52:52.043991 OTF = 0x1
2140 05:52:52.047120 ===================================
2141 05:52:52.050494 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2142 05:52:52.053932 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2143 05:52:52.060568 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2144 05:52:52.064402 ===================================
2145 05:52:52.064485 LPDDR4 DRAM CONFIGURATION
2146 05:52:52.067456 ===================================
2147 05:52:52.070493 EX_ROW_EN[0] = 0x10
2148 05:52:52.074163 EX_ROW_EN[1] = 0x0
2149 05:52:52.074244 LP4Y_EN = 0x0
2150 05:52:52.077367 WORK_FSP = 0x0
2151 05:52:52.077448 WL = 0x4
2152 05:52:52.080904 RL = 0x4
2153 05:52:52.080985 BL = 0x2
2154 05:52:52.083892 RPST = 0x0
2155 05:52:52.083971 RD_PRE = 0x0
2156 05:52:52.087178 WR_PRE = 0x1
2157 05:52:52.087259 WR_PST = 0x0
2158 05:52:52.090851 DBI_WR = 0x0
2159 05:52:52.090931 DBI_RD = 0x0
2160 05:52:52.093980 OTF = 0x1
2161 05:52:52.097116 ===================================
2162 05:52:52.103991 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2163 05:52:52.104075 ==
2164 05:52:52.107691 Dram Type= 6, Freq= 0, CH_0, rank 0
2165 05:52:52.110976 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2166 05:52:52.111057 ==
2167 05:52:52.114245 [Duty_Offset_Calibration]
2168 05:52:52.114323 B0:0 B1:2 CA:1
2169 05:52:52.114386
2170 05:52:52.117367 [DutyScan_Calibration_Flow] k_type=0
2171 05:52:52.127140
2172 05:52:52.127225 ==CLK 0==
2173 05:52:52.130325 Final CLK duty delay cell = 0
2174 05:52:52.133490 [0] MAX Duty = 5093%(X100), DQS PI = 12
2175 05:52:52.136992 [0] MIN Duty = 4938%(X100), DQS PI = 52
2176 05:52:52.137102 [0] AVG Duty = 5015%(X100)
2177 05:52:52.140386
2178 05:52:52.143912 CH0 CLK Duty spec in!! Max-Min= 155%
2179 05:52:52.146810 [DutyScan_Calibration_Flow] ====Done====
2180 05:52:52.146927
2181 05:52:52.150017 [DutyScan_Calibration_Flow] k_type=1
2182 05:52:52.166472
2183 05:52:52.166579 ==DQS 0 ==
2184 05:52:52.169571 Final DQS duty delay cell = 0
2185 05:52:52.173112 [0] MAX Duty = 5125%(X100), DQS PI = 32
2186 05:52:52.176586 [0] MIN Duty = 5031%(X100), DQS PI = 6
2187 05:52:52.176667 [0] AVG Duty = 5078%(X100)
2188 05:52:52.179613
2189 05:52:52.179693 ==DQS 1 ==
2190 05:52:52.183271 Final DQS duty delay cell = 0
2191 05:52:52.186380 [0] MAX Duty = 5031%(X100), DQS PI = 50
2192 05:52:52.189754 [0] MIN Duty = 4906%(X100), DQS PI = 16
2193 05:52:52.189839 [0] AVG Duty = 4968%(X100)
2194 05:52:52.192900
2195 05:52:52.196153 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2196 05:52:52.196237
2197 05:52:52.199602 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2198 05:52:52.203441 [DutyScan_Calibration_Flow] ====Done====
2199 05:52:52.203524
2200 05:52:52.206255 [DutyScan_Calibration_Flow] k_type=3
2201 05:52:52.223339
2202 05:52:52.223451 ==DQM 0 ==
2203 05:52:52.226926 Final DQM duty delay cell = 0
2204 05:52:52.230126 [0] MAX Duty = 5156%(X100), DQS PI = 20
2205 05:52:52.233754 [0] MIN Duty = 4969%(X100), DQS PI = 42
2206 05:52:52.236541 [0] AVG Duty = 5062%(X100)
2207 05:52:52.236640
2208 05:52:52.236764 ==DQM 1 ==
2209 05:52:52.240129 Final DQM duty delay cell = 4
2210 05:52:52.243601 [4] MAX Duty = 5187%(X100), DQS PI = 54
2211 05:52:52.246598 [4] MIN Duty = 5000%(X100), DQS PI = 18
2212 05:52:52.249994 [4] AVG Duty = 5093%(X100)
2213 05:52:52.250066
2214 05:52:52.253699 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2215 05:52:52.253770
2216 05:52:52.256680 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2217 05:52:52.260206 [DutyScan_Calibration_Flow] ====Done====
2218 05:52:52.260284
2219 05:52:52.263519 [DutyScan_Calibration_Flow] k_type=2
2220 05:52:52.278699
2221 05:52:52.278784 ==DQ 0 ==
2222 05:52:52.282449 Final DQ duty delay cell = -4
2223 05:52:52.285352 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2224 05:52:52.288437 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2225 05:52:52.291792 [-4] AVG Duty = 4937%(X100)
2226 05:52:52.291871
2227 05:52:52.291933 ==DQ 1 ==
2228 05:52:52.295079 Final DQ duty delay cell = -4
2229 05:52:52.298400 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2230 05:52:52.301633 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2231 05:52:52.305207 [-4] AVG Duty = 4984%(X100)
2232 05:52:52.305312
2233 05:52:52.308202 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2234 05:52:52.308297
2235 05:52:52.312044 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2236 05:52:52.315106 [DutyScan_Calibration_Flow] ====Done====
2237 05:52:52.315206 ==
2238 05:52:52.318308 Dram Type= 6, Freq= 0, CH_1, rank 0
2239 05:52:52.321506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2240 05:52:52.321581 ==
2241 05:52:52.324953 [Duty_Offset_Calibration]
2242 05:52:52.325025 B0:0 B1:5 CA:-5
2243 05:52:52.325086
2244 05:52:52.328018 [DutyScan_Calibration_Flow] k_type=0
2245 05:52:52.338942
2246 05:52:52.339150 ==CLK 0==
2247 05:52:52.342304 Final CLK duty delay cell = 0
2248 05:52:52.345966 [0] MAX Duty = 5094%(X100), DQS PI = 24
2249 05:52:52.348951 [0] MIN Duty = 4907%(X100), DQS PI = 44
2250 05:52:52.349087 [0] AVG Duty = 5000%(X100)
2251 05:52:52.352197
2252 05:52:52.355926 CH1 CLK Duty spec in!! Max-Min= 187%
2253 05:52:52.359253 [DutyScan_Calibration_Flow] ====Done====
2254 05:52:52.359402
2255 05:52:52.362523 [DutyScan_Calibration_Flow] k_type=1
2256 05:52:52.377764
2257 05:52:52.377926 ==DQS 0 ==
2258 05:52:52.381014 Final DQS duty delay cell = 0
2259 05:52:52.384140 [0] MAX Duty = 5125%(X100), DQS PI = 16
2260 05:52:52.387469 [0] MIN Duty = 4875%(X100), DQS PI = 40
2261 05:52:52.390770 [0] AVG Duty = 5000%(X100)
2262 05:52:52.390890
2263 05:52:52.390984 ==DQS 1 ==
2264 05:52:52.394162 Final DQS duty delay cell = -4
2265 05:52:52.397629 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2266 05:52:52.401103 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2267 05:52:52.404060 [-4] AVG Duty = 4953%(X100)
2268 05:52:52.404198
2269 05:52:52.407474 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2270 05:52:52.407590
2271 05:52:52.410679 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2272 05:52:52.414363 [DutyScan_Calibration_Flow] ====Done====
2273 05:52:52.414482
2274 05:52:52.417728 [DutyScan_Calibration_Flow] k_type=3
2275 05:52:52.432660
2276 05:52:52.432828 ==DQM 0 ==
2277 05:52:52.436136 Final DQM duty delay cell = -4
2278 05:52:52.439552 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2279 05:52:52.442869 [-4] MIN Duty = 4875%(X100), DQS PI = 38
2280 05:52:52.445837 [-4] AVG Duty = 4968%(X100)
2281 05:52:52.445944
2282 05:52:52.446034 ==DQM 1 ==
2283 05:52:52.449430 Final DQM duty delay cell = -4
2284 05:52:52.452671 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2285 05:52:52.455996 [-4] MIN Duty = 4906%(X100), DQS PI = 42
2286 05:52:52.459411 [-4] AVG Duty = 5000%(X100)
2287 05:52:52.459511
2288 05:52:52.462820 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2289 05:52:52.462923
2290 05:52:52.466129 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2291 05:52:52.469288 [DutyScan_Calibration_Flow] ====Done====
2292 05:52:52.469368
2293 05:52:52.472639 [DutyScan_Calibration_Flow] k_type=2
2294 05:52:52.490396
2295 05:52:52.490544 ==DQ 0 ==
2296 05:52:52.493488 Final DQ duty delay cell = 0
2297 05:52:52.496701 [0] MAX Duty = 5062%(X100), DQS PI = 0
2298 05:52:52.500069 [0] MIN Duty = 4938%(X100), DQS PI = 44
2299 05:52:52.500162 [0] AVG Duty = 5000%(X100)
2300 05:52:52.500230
2301 05:52:52.503297 ==DQ 1 ==
2302 05:52:52.506629 Final DQ duty delay cell = 0
2303 05:52:52.510255 [0] MAX Duty = 5031%(X100), DQS PI = 8
2304 05:52:52.513142 [0] MIN Duty = 4876%(X100), DQS PI = 62
2305 05:52:52.513265 [0] AVG Duty = 4953%(X100)
2306 05:52:52.513347
2307 05:52:52.516647 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2308 05:52:52.516779
2309 05:52:52.520019 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2310 05:52:52.526687 [DutyScan_Calibration_Flow] ====Done====
2311 05:52:52.530376 nWR fixed to 30
2312 05:52:52.530502 [ModeRegInit_LP4] CH0 RK0
2313 05:52:52.533233 [ModeRegInit_LP4] CH0 RK1
2314 05:52:52.536559 [ModeRegInit_LP4] CH1 RK0
2315 05:52:52.536657 [ModeRegInit_LP4] CH1 RK1
2316 05:52:52.539882 match AC timing 6
2317 05:52:52.543818 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2318 05:52:52.546670 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2319 05:52:52.553295 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2320 05:52:52.556556 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2321 05:52:52.563884 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2322 05:52:52.563971 ==
2323 05:52:52.566414 Dram Type= 6, Freq= 0, CH_0, rank 0
2324 05:52:52.569896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2325 05:52:52.570001 ==
2326 05:52:52.576736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2327 05:52:52.579698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2328 05:52:52.589702 [CA 0] Center 39 (9~70) winsize 62
2329 05:52:52.593053 [CA 1] Center 39 (8~70) winsize 63
2330 05:52:52.596325 [CA 2] Center 36 (5~67) winsize 63
2331 05:52:52.599797 [CA 3] Center 35 (4~66) winsize 63
2332 05:52:52.603267 [CA 4] Center 34 (3~65) winsize 63
2333 05:52:52.606653 [CA 5] Center 33 (3~64) winsize 62
2334 05:52:52.606733
2335 05:52:52.609707 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2336 05:52:52.609786
2337 05:52:52.613089 [CATrainingPosCal] consider 1 rank data
2338 05:52:52.616298 u2DelayCellTimex100 = 270/100 ps
2339 05:52:52.619553 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2340 05:52:52.622941 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2341 05:52:52.629610 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2342 05:52:52.632991 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2343 05:52:52.636240 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2344 05:52:52.639699 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2345 05:52:52.639779
2346 05:52:52.643123 CA PerBit enable=1, Macro0, CA PI delay=33
2347 05:52:52.643203
2348 05:52:52.646125 [CBTSetCACLKResult] CA Dly = 33
2349 05:52:52.646204 CS Dly: 7 (0~38)
2350 05:52:52.649356 ==
2351 05:52:52.653140 Dram Type= 6, Freq= 0, CH_0, rank 1
2352 05:52:52.656137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2353 05:52:52.656211 ==
2354 05:52:52.659545 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2355 05:52:52.666089 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2356 05:52:52.674980 [CA 0] Center 39 (8~70) winsize 63
2357 05:52:52.678514 [CA 1] Center 39 (8~70) winsize 63
2358 05:52:52.681893 [CA 2] Center 36 (5~67) winsize 63
2359 05:52:52.685292 [CA 3] Center 35 (4~66) winsize 63
2360 05:52:52.688820 [CA 4] Center 33 (3~64) winsize 62
2361 05:52:52.691468 [CA 5] Center 34 (3~65) winsize 63
2362 05:52:52.691572
2363 05:52:52.694754 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2364 05:52:52.694858
2365 05:52:52.698108 [CATrainingPosCal] consider 2 rank data
2366 05:52:52.701432 u2DelayCellTimex100 = 270/100 ps
2367 05:52:52.704836 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2368 05:52:52.711681 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2369 05:52:52.714661 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2370 05:52:52.718529 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2371 05:52:52.721693 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2372 05:52:52.724651 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2373 05:52:52.724787
2374 05:52:52.728237 CA PerBit enable=1, Macro0, CA PI delay=33
2375 05:52:52.728328
2376 05:52:52.731581 [CBTSetCACLKResult] CA Dly = 33
2377 05:52:52.735042 CS Dly: 7 (0~39)
2378 05:52:52.735116
2379 05:52:52.738170 ----->DramcWriteLeveling(PI) begin...
2380 05:52:52.738249 ==
2381 05:52:52.741347 Dram Type= 6, Freq= 0, CH_0, rank 0
2382 05:52:52.744622 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2383 05:52:52.744742 ==
2384 05:52:52.747991 Write leveling (Byte 0): 28 => 28
2385 05:52:52.751727 Write leveling (Byte 1): 24 => 24
2386 05:52:52.754706 DramcWriteLeveling(PI) end<-----
2387 05:52:52.754806
2388 05:52:52.754898 ==
2389 05:52:52.758189 Dram Type= 6, Freq= 0, CH_0, rank 0
2390 05:52:52.761226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2391 05:52:52.761326 ==
2392 05:52:52.764489 [Gating] SW mode calibration
2393 05:52:52.771201 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2394 05:52:52.778697 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2395 05:52:52.781216 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2396 05:52:52.784540 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2397 05:52:52.791192 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2398 05:52:52.794432 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2399 05:52:52.797807 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2400 05:52:52.804949 0 11 20 | B1->B0 | 3232 2d2d | 0 0 | (0 1) (0 1)
2401 05:52:52.807806 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2402 05:52:52.811061 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2403 05:52:52.817785 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2404 05:52:52.821009 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2405 05:52:52.824607 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2406 05:52:52.831004 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2407 05:52:52.834449 0 12 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2408 05:52:52.837747 0 12 20 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (0 0)
2409 05:52:52.844143 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2410 05:52:52.847791 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2411 05:52:52.851127 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2412 05:52:52.854094 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2413 05:52:52.861022 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2414 05:52:52.864221 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2415 05:52:52.868062 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2416 05:52:52.874533 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2417 05:52:52.877718 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 05:52:52.880950 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 05:52:52.887365 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 05:52:52.890702 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 05:52:52.894315 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 05:52:52.900691 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2423 05:52:52.904519 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2424 05:52:52.907380 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2425 05:52:52.914386 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2426 05:52:52.917514 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2427 05:52:52.921332 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2428 05:52:52.927768 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2429 05:52:52.930614 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2430 05:52:52.934036 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2431 05:52:52.940539 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2432 05:52:52.944214 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2433 05:52:52.947536 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2434 05:52:52.950854 Total UI for P1: 0, mck2ui 16
2435 05:52:52.954243 best dqsien dly found for B0: ( 0, 15, 18)
2436 05:52:52.957457 Total UI for P1: 0, mck2ui 16
2437 05:52:52.960741 best dqsien dly found for B1: ( 0, 15, 20)
2438 05:52:52.963905 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2439 05:52:52.967157 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2440 05:52:52.967238
2441 05:52:52.970840 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2442 05:52:52.977343 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2443 05:52:52.977489 [Gating] SW calibration Done
2444 05:52:52.980920 ==
2445 05:52:52.981005 Dram Type= 6, Freq= 0, CH_0, rank 0
2446 05:52:52.987345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2447 05:52:52.987601 ==
2448 05:52:52.987702 RX Vref Scan: 0
2449 05:52:52.987785
2450 05:52:52.990647 RX Vref 0 -> 0, step: 1
2451 05:52:52.990748
2452 05:52:52.994044 RX Delay -40 -> 252, step: 8
2453 05:52:52.997157 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2454 05:52:53.000638 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2455 05:52:53.004061 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2456 05:52:53.010690 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2457 05:52:53.013864 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2458 05:52:53.017141 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2459 05:52:53.020488 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2460 05:52:53.024072 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2461 05:52:53.027302 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2462 05:52:53.033977 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2463 05:52:53.037353 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2464 05:52:53.040631 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2465 05:52:53.044481 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2466 05:52:53.050546 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2467 05:52:53.053834 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2468 05:52:53.057518 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2469 05:52:53.057599 ==
2470 05:52:53.060523 Dram Type= 6, Freq= 0, CH_0, rank 0
2471 05:52:53.063815 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2472 05:52:53.063896 ==
2473 05:52:53.067327 DQS Delay:
2474 05:52:53.067439 DQS0 = 0, DQS1 = 0
2475 05:52:53.070616 DQM Delay:
2476 05:52:53.070696 DQM0 = 115, DQM1 = 106
2477 05:52:53.070760 DQ Delay:
2478 05:52:53.073865 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2479 05:52:53.077203 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2480 05:52:53.083826 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2481 05:52:53.087144 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2482 05:52:53.087225
2483 05:52:53.087306
2484 05:52:53.087378 ==
2485 05:52:53.090604 Dram Type= 6, Freq= 0, CH_0, rank 0
2486 05:52:53.094116 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2487 05:52:53.094198 ==
2488 05:52:53.094262
2489 05:52:53.094321
2490 05:52:53.097447 TX Vref Scan disable
2491 05:52:53.100279 == TX Byte 0 ==
2492 05:52:53.103996 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2493 05:52:53.107002 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2494 05:52:53.110452 == TX Byte 1 ==
2495 05:52:53.113675 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2496 05:52:53.117216 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2497 05:52:53.117296 ==
2498 05:52:53.120503 Dram Type= 6, Freq= 0, CH_0, rank 0
2499 05:52:53.123764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2500 05:52:53.123845 ==
2501 05:52:53.137337 TX Vref=22, minBit 8, minWin=24, winSum=413
2502 05:52:53.140254 TX Vref=24, minBit 8, minWin=24, winSum=421
2503 05:52:53.143734 TX Vref=26, minBit 8, minWin=25, winSum=426
2504 05:52:53.147218 TX Vref=28, minBit 8, minWin=25, winSum=429
2505 05:52:53.150674 TX Vref=30, minBit 8, minWin=26, winSum=432
2506 05:52:53.153998 TX Vref=32, minBit 8, minWin=26, winSum=433
2507 05:52:53.160304 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 32
2508 05:52:53.160387
2509 05:52:53.163857 Final TX Range 1 Vref 32
2510 05:52:53.163938
2511 05:52:53.164002 ==
2512 05:52:53.167013 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 05:52:53.170228 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2514 05:52:53.170309 ==
2515 05:52:53.170372
2516 05:52:53.173653
2517 05:52:53.173734 TX Vref Scan disable
2518 05:52:53.176639 == TX Byte 0 ==
2519 05:52:53.180271 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2520 05:52:53.183615 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2521 05:52:53.187099 == TX Byte 1 ==
2522 05:52:53.190220 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2523 05:52:53.193547 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2524 05:52:53.193627
2525 05:52:53.196640 [DATLAT]
2526 05:52:53.196776 Freq=1200, CH0 RK0
2527 05:52:53.196841
2528 05:52:53.200211 DATLAT Default: 0xd
2529 05:52:53.200292 0, 0xFFFF, sum = 0
2530 05:52:53.203509 1, 0xFFFF, sum = 0
2531 05:52:53.203593 2, 0xFFFF, sum = 0
2532 05:52:53.207091 3, 0xFFFF, sum = 0
2533 05:52:53.207174 4, 0xFFFF, sum = 0
2534 05:52:53.210427 5, 0xFFFF, sum = 0
2535 05:52:53.210511 6, 0xFFFF, sum = 0
2536 05:52:53.213355 7, 0xFFFF, sum = 0
2537 05:52:53.216739 8, 0xFFFF, sum = 0
2538 05:52:53.216837 9, 0xFFFF, sum = 0
2539 05:52:53.219966 10, 0xFFFF, sum = 0
2540 05:52:53.220047 11, 0x0, sum = 1
2541 05:52:53.223297 12, 0x0, sum = 2
2542 05:52:53.223405 13, 0x0, sum = 3
2543 05:52:53.223499 14, 0x0, sum = 4
2544 05:52:53.226729 best_step = 12
2545 05:52:53.226841
2546 05:52:53.226948 ==
2547 05:52:53.230407 Dram Type= 6, Freq= 0, CH_0, rank 0
2548 05:52:53.234102 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2549 05:52:53.234177 ==
2550 05:52:53.237113 RX Vref Scan: 1
2551 05:52:53.237187
2552 05:52:53.240011 Set Vref Range= 32 -> 127
2553 05:52:53.240083
2554 05:52:53.240144 RX Vref 32 -> 127, step: 1
2555 05:52:53.240201
2556 05:52:53.243431 RX Delay -21 -> 252, step: 4
2557 05:52:53.243546
2558 05:52:53.246919 Set Vref, RX VrefLevel [Byte0]: 32
2559 05:52:53.249958 [Byte1]: 32
2560 05:52:53.253443
2561 05:52:53.253516 Set Vref, RX VrefLevel [Byte0]: 33
2562 05:52:53.256661 [Byte1]: 33
2563 05:52:53.261361
2564 05:52:53.261441 Set Vref, RX VrefLevel [Byte0]: 34
2565 05:52:53.264546 [Byte1]: 34
2566 05:52:53.269371
2567 05:52:53.272986 Set Vref, RX VrefLevel [Byte0]: 35
2568 05:52:53.273071 [Byte1]: 35
2569 05:52:53.277101
2570 05:52:53.277179 Set Vref, RX VrefLevel [Byte0]: 36
2571 05:52:53.280481 [Byte1]: 36
2572 05:52:53.285083
2573 05:52:53.285164 Set Vref, RX VrefLevel [Byte0]: 37
2574 05:52:53.288773 [Byte1]: 37
2575 05:52:53.292939
2576 05:52:53.293022 Set Vref, RX VrefLevel [Byte0]: 38
2577 05:52:53.296102 [Byte1]: 38
2578 05:52:53.300843
2579 05:52:53.300948 Set Vref, RX VrefLevel [Byte0]: 39
2580 05:52:53.304369 [Byte1]: 39
2581 05:52:53.308674
2582 05:52:53.308821 Set Vref, RX VrefLevel [Byte0]: 40
2583 05:52:53.312265 [Byte1]: 40
2584 05:52:53.317019
2585 05:52:53.317126 Set Vref, RX VrefLevel [Byte0]: 41
2586 05:52:53.320220 [Byte1]: 41
2587 05:52:53.325157
2588 05:52:53.325262 Set Vref, RX VrefLevel [Byte0]: 42
2589 05:52:53.328054 [Byte1]: 42
2590 05:52:53.332753
2591 05:52:53.332834 Set Vref, RX VrefLevel [Byte0]: 43
2592 05:52:53.335912 [Byte1]: 43
2593 05:52:53.340768
2594 05:52:53.340848 Set Vref, RX VrefLevel [Byte0]: 44
2595 05:52:53.343769 [Byte1]: 44
2596 05:52:53.348695
2597 05:52:53.348783 Set Vref, RX VrefLevel [Byte0]: 45
2598 05:52:53.351765 [Byte1]: 45
2599 05:52:53.356338
2600 05:52:53.356419 Set Vref, RX VrefLevel [Byte0]: 46
2601 05:52:53.359565 [Byte1]: 46
2602 05:52:53.364604
2603 05:52:53.364683 Set Vref, RX VrefLevel [Byte0]: 47
2604 05:52:53.367706 [Byte1]: 47
2605 05:52:53.372578
2606 05:52:53.372657 Set Vref, RX VrefLevel [Byte0]: 48
2607 05:52:53.375584 [Byte1]: 48
2608 05:52:53.380354
2609 05:52:53.380434 Set Vref, RX VrefLevel [Byte0]: 49
2610 05:52:53.383649 [Byte1]: 49
2611 05:52:53.388311
2612 05:52:53.388392 Set Vref, RX VrefLevel [Byte0]: 50
2613 05:52:53.391513 [Byte1]: 50
2614 05:52:53.396101
2615 05:52:53.396181 Set Vref, RX VrefLevel [Byte0]: 51
2616 05:52:53.399286 [Byte1]: 51
2617 05:52:53.404203
2618 05:52:53.404291 Set Vref, RX VrefLevel [Byte0]: 52
2619 05:52:53.407345 [Byte1]: 52
2620 05:52:53.411921
2621 05:52:53.412001 Set Vref, RX VrefLevel [Byte0]: 53
2622 05:52:53.415381 [Byte1]: 53
2623 05:52:53.419758
2624 05:52:53.419881 Set Vref, RX VrefLevel [Byte0]: 54
2625 05:52:53.423170 [Byte1]: 54
2626 05:52:53.427704
2627 05:52:53.427784 Set Vref, RX VrefLevel [Byte0]: 55
2628 05:52:53.431019 [Byte1]: 55
2629 05:52:53.435512
2630 05:52:53.435591 Set Vref, RX VrefLevel [Byte0]: 56
2631 05:52:53.438865 [Byte1]: 56
2632 05:52:53.443581
2633 05:52:53.443675 Set Vref, RX VrefLevel [Byte0]: 57
2634 05:52:53.446982 [Byte1]: 57
2635 05:52:53.451807
2636 05:52:53.451889 Set Vref, RX VrefLevel [Byte0]: 58
2637 05:52:53.454700 [Byte1]: 58
2638 05:52:53.459287
2639 05:52:53.459367 Set Vref, RX VrefLevel [Byte0]: 59
2640 05:52:53.462694 [Byte1]: 59
2641 05:52:53.467626
2642 05:52:53.467706 Set Vref, RX VrefLevel [Byte0]: 60
2643 05:52:53.470731 [Byte1]: 60
2644 05:52:53.475101
2645 05:52:53.475180 Set Vref, RX VrefLevel [Byte0]: 61
2646 05:52:53.478458 [Byte1]: 61
2647 05:52:53.483315
2648 05:52:53.483394 Set Vref, RX VrefLevel [Byte0]: 62
2649 05:52:53.486914 [Byte1]: 62
2650 05:52:53.491475
2651 05:52:53.491554 Set Vref, RX VrefLevel [Byte0]: 63
2652 05:52:53.494617 [Byte1]: 63
2653 05:52:53.499179
2654 05:52:53.499258 Set Vref, RX VrefLevel [Byte0]: 64
2655 05:52:53.502244 [Byte1]: 64
2656 05:52:53.507252
2657 05:52:53.507349 Set Vref, RX VrefLevel [Byte0]: 65
2658 05:52:53.510368 [Byte1]: 65
2659 05:52:53.514702
2660 05:52:53.514784 Final RX Vref Byte 0 = 47 to rank0
2661 05:52:53.518588 Final RX Vref Byte 1 = 48 to rank0
2662 05:52:53.521405 Final RX Vref Byte 0 = 47 to rank1
2663 05:52:53.524927 Final RX Vref Byte 1 = 48 to rank1==
2664 05:52:53.528421 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 05:52:53.535007 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2666 05:52:53.535090 ==
2667 05:52:53.535173 DQS Delay:
2668 05:52:53.535251 DQS0 = 0, DQS1 = 0
2669 05:52:53.538000 DQM Delay:
2670 05:52:53.538086 DQM0 = 114, DQM1 = 105
2671 05:52:53.541301 DQ Delay:
2672 05:52:53.545105 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2673 05:52:53.548307 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2674 05:52:53.551362 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2675 05:52:53.554950 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2676 05:52:53.555033
2677 05:52:53.555116
2678 05:52:53.561448 [DQSOSCAuto] RK0, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2679 05:52:53.564590 CH0 RK0: MR19=404, MR18=606
2680 05:52:53.571794 CH0_RK0: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
2681 05:52:53.571878
2682 05:52:53.574953 ----->DramcWriteLeveling(PI) begin...
2683 05:52:53.575037 ==
2684 05:52:53.578370 Dram Type= 6, Freq= 0, CH_0, rank 1
2685 05:52:53.581480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2686 05:52:53.581563 ==
2687 05:52:53.584697 Write leveling (Byte 0): 26 => 26
2688 05:52:53.588144 Write leveling (Byte 1): 25 => 25
2689 05:52:53.591338 DramcWriteLeveling(PI) end<-----
2690 05:52:53.591420
2691 05:52:53.591504 ==
2692 05:52:53.594836 Dram Type= 6, Freq= 0, CH_0, rank 1
2693 05:52:53.598250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2694 05:52:53.601472 ==
2695 05:52:53.601554 [Gating] SW mode calibration
2696 05:52:53.611329 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2697 05:52:53.615024 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2698 05:52:53.618013 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2699 05:52:53.624998 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2700 05:52:53.628256 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2701 05:52:53.631303 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2702 05:52:53.638057 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2703 05:52:53.641088 0 11 20 | B1->B0 | 3232 2a2a | 1 1 | (1 0) (1 0)
2704 05:52:53.644493 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2705 05:52:53.651246 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2706 05:52:53.654531 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2707 05:52:53.657997 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2708 05:52:53.665334 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2709 05:52:53.668558 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2710 05:52:53.671569 0 12 16 | B1->B0 | 2727 3333 | 0 0 | (0 0) (0 0)
2711 05:52:53.678087 0 12 20 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)
2712 05:52:53.681302 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2713 05:52:53.685006 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2714 05:52:53.691821 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2715 05:52:53.695352 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2716 05:52:53.698163 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2717 05:52:53.704239 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2718 05:52:53.707652 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2719 05:52:53.711338 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2720 05:52:53.714592 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2721 05:52:53.720897 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 05:52:53.724606 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 05:52:53.727797 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 05:52:53.734453 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 05:52:53.737406 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 05:52:53.740748 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 05:52:53.747883 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2728 05:52:53.751398 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2729 05:52:53.754214 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2730 05:52:53.761047 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2731 05:52:53.764737 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2732 05:52:53.767777 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2733 05:52:53.774668 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2734 05:52:53.777987 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2735 05:52:53.781229 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2736 05:52:53.784388 Total UI for P1: 0, mck2ui 16
2737 05:52:53.787775 best dqsien dly found for B0: ( 0, 15, 16)
2738 05:52:53.794906 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2739 05:52:53.795381 Total UI for P1: 0, mck2ui 16
2740 05:52:53.801414 best dqsien dly found for B1: ( 0, 15, 18)
2741 05:52:53.805199 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2742 05:52:53.807656 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2743 05:52:53.808087
2744 05:52:53.811353 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2745 05:52:53.814645 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2746 05:52:53.817568 [Gating] SW calibration Done
2747 05:52:53.818115 ==
2748 05:52:53.821166 Dram Type= 6, Freq= 0, CH_0, rank 1
2749 05:52:53.824612 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2750 05:52:53.825161 ==
2751 05:52:53.827999 RX Vref Scan: 0
2752 05:52:53.828432
2753 05:52:53.828968 RX Vref 0 -> 0, step: 1
2754 05:52:53.829408
2755 05:52:53.831183 RX Delay -40 -> 252, step: 8
2756 05:52:53.834568 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2757 05:52:53.841135 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2758 05:52:53.844850 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2759 05:52:53.847818 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2760 05:52:53.850853 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2761 05:52:53.854245 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2762 05:52:53.861061 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2763 05:52:53.864274 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2764 05:52:53.868185 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2765 05:52:53.870635 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2766 05:52:53.874084 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2767 05:52:53.880992 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2768 05:52:53.884268 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2769 05:52:53.887716 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2770 05:52:53.890796 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2771 05:52:53.894146 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2772 05:52:53.897424 ==
2773 05:52:53.897996 Dram Type= 6, Freq= 0, CH_0, rank 1
2774 05:52:53.903886 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2775 05:52:53.904466 ==
2776 05:52:53.905058 DQS Delay:
2777 05:52:53.907386 DQS0 = 0, DQS1 = 0
2778 05:52:53.907801 DQM Delay:
2779 05:52:53.910712 DQM0 = 115, DQM1 = 107
2780 05:52:53.911269 DQ Delay:
2781 05:52:53.914230 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2782 05:52:53.917572 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2783 05:52:53.920670 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2784 05:52:53.924140 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2785 05:52:53.924558
2786 05:52:53.924997
2787 05:52:53.925310 ==
2788 05:52:53.927647 Dram Type= 6, Freq= 0, CH_0, rank 1
2789 05:52:53.934287 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2790 05:52:53.934957 ==
2791 05:52:53.935480
2792 05:52:53.935809
2793 05:52:53.936109 TX Vref Scan disable
2794 05:52:53.937317 == TX Byte 0 ==
2795 05:52:53.940968 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2796 05:52:53.944341 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2797 05:52:53.947755 == TX Byte 1 ==
2798 05:52:53.950980 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2799 05:52:53.954550 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2800 05:52:53.957424 ==
2801 05:52:53.961106 Dram Type= 6, Freq= 0, CH_0, rank 1
2802 05:52:53.964048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2803 05:52:53.964467 ==
2804 05:52:53.975195 TX Vref=22, minBit 5, minWin=25, winSum=413
2805 05:52:53.978791 TX Vref=24, minBit 1, minWin=25, winSum=422
2806 05:52:53.982115 TX Vref=26, minBit 10, minWin=25, winSum=425
2807 05:52:53.985248 TX Vref=28, minBit 1, minWin=26, winSum=429
2808 05:52:53.988738 TX Vref=30, minBit 1, minWin=26, winSum=428
2809 05:52:53.995080 TX Vref=32, minBit 5, minWin=26, winSum=430
2810 05:52:53.998439 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 32
2811 05:52:53.998861
2812 05:52:54.001476 Final TX Range 1 Vref 32
2813 05:52:54.001999
2814 05:52:54.002346 ==
2815 05:52:54.005171 Dram Type= 6, Freq= 0, CH_0, rank 1
2816 05:52:54.008166 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2817 05:52:54.008645 ==
2818 05:52:54.011565
2819 05:52:54.011989
2820 05:52:54.012335 TX Vref Scan disable
2821 05:52:54.015284 == TX Byte 0 ==
2822 05:52:54.018222 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2823 05:52:54.021705 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2824 05:52:54.024970 == TX Byte 1 ==
2825 05:52:54.028655 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2826 05:52:54.031560 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2827 05:52:54.032103
2828 05:52:54.034887 [DATLAT]
2829 05:52:54.035338 Freq=1200, CH0 RK1
2830 05:52:54.035694
2831 05:52:54.038163 DATLAT Default: 0xc
2832 05:52:54.038579 0, 0xFFFF, sum = 0
2833 05:52:54.041446 1, 0xFFFF, sum = 0
2834 05:52:54.041866 2, 0xFFFF, sum = 0
2835 05:52:54.044908 3, 0xFFFF, sum = 0
2836 05:52:54.045328 4, 0xFFFF, sum = 0
2837 05:52:54.048298 5, 0xFFFF, sum = 0
2838 05:52:54.048744 6, 0xFFFF, sum = 0
2839 05:52:54.051555 7, 0xFFFF, sum = 0
2840 05:52:54.055134 8, 0xFFFF, sum = 0
2841 05:52:54.055556 9, 0xFFFF, sum = 0
2842 05:52:54.058217 10, 0xFFFF, sum = 0
2843 05:52:54.058639 11, 0x0, sum = 1
2844 05:52:54.061662 12, 0x0, sum = 2
2845 05:52:54.062162 13, 0x0, sum = 3
2846 05:52:54.062550 14, 0x0, sum = 4
2847 05:52:54.065085 best_step = 12
2848 05:52:54.065500
2849 05:52:54.065908 ==
2850 05:52:54.068198 Dram Type= 6, Freq= 0, CH_0, rank 1
2851 05:52:54.071554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2852 05:52:54.072039 ==
2853 05:52:54.074574 RX Vref Scan: 0
2854 05:52:54.074989
2855 05:52:54.078157 RX Vref 0 -> 0, step: 1
2856 05:52:54.078630
2857 05:52:54.079023 RX Delay -21 -> 252, step: 4
2858 05:52:54.085596 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2859 05:52:54.088674 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2860 05:52:54.091916 iDelay=195, Bit 2, Center 112 (39 ~ 186) 148
2861 05:52:54.095035 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2862 05:52:54.098708 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2863 05:52:54.104962 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2864 05:52:54.108472 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2865 05:52:54.112485 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
2866 05:52:54.114970 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2867 05:52:54.118593 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2868 05:52:54.125116 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2869 05:52:54.128329 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2870 05:52:54.131810 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2871 05:52:54.134895 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2872 05:52:54.138199 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2873 05:52:54.145104 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2874 05:52:54.145556 ==
2875 05:52:54.148418 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 05:52:54.151869 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2877 05:52:54.152296 ==
2878 05:52:54.152734 DQS Delay:
2879 05:52:54.154928 DQS0 = 0, DQS1 = 0
2880 05:52:54.155374 DQM Delay:
2881 05:52:54.158278 DQM0 = 115, DQM1 = 105
2882 05:52:54.158860 DQ Delay:
2883 05:52:54.161555 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2884 05:52:54.165234 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2885 05:52:54.168490 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2886 05:52:54.171738 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2887 05:52:54.172149
2888 05:52:54.172473
2889 05:52:54.182170 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2890 05:52:54.185241 CH0 RK1: MR19=404, MR18=F0F
2891 05:52:54.188353 CH0_RK1: MR19=0x404, MR18=0xF0F, DQSOSC=404, MR23=63, INC=40, DEC=26
2892 05:52:54.191747 [RxdqsGatingPostProcess] freq 1200
2893 05:52:54.198394 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2894 05:52:54.201633 Pre-setting of DQS Precalculation
2895 05:52:54.204937 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2896 05:52:54.208314 ==
2897 05:52:54.208752 Dram Type= 6, Freq= 0, CH_1, rank 0
2898 05:52:54.215008 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2899 05:52:54.215423 ==
2900 05:52:54.218304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2901 05:52:54.224992 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2902 05:52:54.233616 [CA 0] Center 37 (7~68) winsize 62
2903 05:52:54.236780 [CA 1] Center 37 (7~68) winsize 62
2904 05:52:54.240357 [CA 2] Center 34 (4~65) winsize 62
2905 05:52:54.243651 [CA 3] Center 33 (3~64) winsize 62
2906 05:52:54.246690 [CA 4] Center 32 (2~63) winsize 62
2907 05:52:54.250048 [CA 5] Center 32 (2~63) winsize 62
2908 05:52:54.250462
2909 05:52:54.253610 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2910 05:52:54.254019
2911 05:52:54.257090 [CATrainingPosCal] consider 1 rank data
2912 05:52:54.260253 u2DelayCellTimex100 = 270/100 ps
2913 05:52:54.263771 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2914 05:52:54.267090 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2915 05:52:54.273654 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2916 05:52:54.276852 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2917 05:52:54.280052 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2918 05:52:54.283521 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2919 05:52:54.283935
2920 05:52:54.286955 CA PerBit enable=1, Macro0, CA PI delay=32
2921 05:52:54.287651
2922 05:52:54.290037 [CBTSetCACLKResult] CA Dly = 32
2923 05:52:54.290501 CS Dly: 6 (0~37)
2924 05:52:54.293677 ==
2925 05:52:54.294087 Dram Type= 6, Freq= 0, CH_1, rank 1
2926 05:52:54.300367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2927 05:52:54.300826 ==
2928 05:52:54.303626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2929 05:52:54.310199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2930 05:52:54.318975 [CA 0] Center 37 (7~68) winsize 62
2931 05:52:54.322187 [CA 1] Center 37 (7~68) winsize 62
2932 05:52:54.325819 [CA 2] Center 33 (3~64) winsize 62
2933 05:52:54.328751 [CA 3] Center 34 (4~64) winsize 61
2934 05:52:54.332409 [CA 4] Center 32 (2~63) winsize 62
2935 05:52:54.335303 [CA 5] Center 32 (1~63) winsize 63
2936 05:52:54.335767
2937 05:52:54.338810 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2938 05:52:54.339319
2939 05:52:54.342454 [CATrainingPosCal] consider 2 rank data
2940 05:52:54.345583 u2DelayCellTimex100 = 270/100 ps
2941 05:52:54.348652 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2942 05:52:54.352265 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2943 05:52:54.358731 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2944 05:52:54.362105 CA3 delay=34 (4~64),Diff = 2 PI (9 cell)
2945 05:52:54.365494 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2946 05:52:54.368836 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2947 05:52:54.369296
2948 05:52:54.371981 CA PerBit enable=1, Macro0, CA PI delay=32
2949 05:52:54.372420
2950 05:52:54.375522 [CBTSetCACLKResult] CA Dly = 32
2951 05:52:54.375935 CS Dly: 6 (0~38)
2952 05:52:54.376262
2953 05:52:54.378524 ----->DramcWriteLeveling(PI) begin...
2954 05:52:54.381945 ==
2955 05:52:54.385231 Dram Type= 6, Freq= 0, CH_1, rank 0
2956 05:52:54.388793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2957 05:52:54.389207 ==
2958 05:52:54.391906 Write leveling (Byte 0): 21 => 21
2959 05:52:54.395340 Write leveling (Byte 1): 23 => 23
2960 05:52:54.398482 DramcWriteLeveling(PI) end<-----
2961 05:52:54.398896
2962 05:52:54.399221 ==
2963 05:52:54.401806 Dram Type= 6, Freq= 0, CH_1, rank 0
2964 05:52:54.404879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2965 05:52:54.405295 ==
2966 05:52:54.408772 [Gating] SW mode calibration
2967 05:52:54.415204 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2968 05:52:54.421604 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2969 05:52:54.424881 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2970 05:52:54.428606 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2971 05:52:54.434760 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2972 05:52:54.438280 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2973 05:52:54.441760 0 11 16 | B1->B0 | 3131 2424 | 0 0 | (0 1) (1 0)
2974 05:52:54.447938 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2975 05:52:54.451114 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2976 05:52:54.454691 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2977 05:52:54.461639 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2978 05:52:54.464626 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2979 05:52:54.467865 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2980 05:52:54.474625 0 12 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2981 05:52:54.477766 0 12 16 | B1->B0 | 3333 4545 | 1 0 | (0 0) (0 0)
2982 05:52:54.481236 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2983 05:52:54.487835 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2984 05:52:54.491039 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2985 05:52:54.494445 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2986 05:52:54.500901 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 05:52:54.504151 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2988 05:52:54.507733 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2989 05:52:54.510758 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2990 05:52:54.517904 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2991 05:52:54.521180 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 05:52:54.527733 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 05:52:54.530841 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 05:52:54.534317 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 05:52:54.537490 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 05:52:54.544109 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 05:52:54.547433 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 05:52:54.550950 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 05:52:54.557667 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 05:52:54.561001 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 05:52:54.563849 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3002 05:52:54.570935 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3003 05:52:54.574179 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3004 05:52:54.577421 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3005 05:52:54.584054 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3006 05:52:54.587277 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3007 05:52:54.590515 Total UI for P1: 0, mck2ui 16
3008 05:52:54.594097 best dqsien dly found for B0: ( 0, 15, 16)
3009 05:52:54.597221 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3010 05:52:54.600801 Total UI for P1: 0, mck2ui 16
3011 05:52:54.603676 best dqsien dly found for B1: ( 0, 15, 18)
3012 05:52:54.607469 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3013 05:52:54.610297 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3014 05:52:54.610719
3015 05:52:54.617314 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3016 05:52:54.620577 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3017 05:52:54.621062 [Gating] SW calibration Done
3018 05:52:54.623643 ==
3019 05:52:54.627091 Dram Type= 6, Freq= 0, CH_1, rank 0
3020 05:52:54.630374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3021 05:52:54.630790 ==
3022 05:52:54.631119 RX Vref Scan: 0
3023 05:52:54.631423
3024 05:52:54.633730 RX Vref 0 -> 0, step: 1
3025 05:52:54.634143
3026 05:52:54.636960 RX Delay -40 -> 252, step: 8
3027 05:52:54.640426 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3028 05:52:54.643658 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3029 05:52:54.650718 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3030 05:52:54.653871 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3031 05:52:54.657083 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3032 05:52:54.660276 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3033 05:52:54.663898 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3034 05:52:54.670423 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3035 05:52:54.673720 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3036 05:52:54.676868 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3037 05:52:54.680506 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3038 05:52:54.683788 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3039 05:52:54.687023 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3040 05:52:54.693798 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3041 05:52:54.697040 iDelay=208, Bit 14, Center 115 (48 ~ 183) 136
3042 05:52:54.700547 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3043 05:52:54.700987 ==
3044 05:52:54.703646 Dram Type= 6, Freq= 0, CH_1, rank 0
3045 05:52:54.707074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3046 05:52:54.707482 ==
3047 05:52:54.710688 DQS Delay:
3048 05:52:54.711096 DQS0 = 0, DQS1 = 0
3049 05:52:54.713937 DQM Delay:
3050 05:52:54.714348 DQM0 = 116, DQM1 = 108
3051 05:52:54.716881 DQ Delay:
3052 05:52:54.720645 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3053 05:52:54.723666 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3054 05:52:54.727346 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3055 05:52:54.730494 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3056 05:52:54.730906
3057 05:52:54.731230
3058 05:52:54.731528 ==
3059 05:52:54.733827 Dram Type= 6, Freq= 0, CH_1, rank 0
3060 05:52:54.737364 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3061 05:52:54.737965 ==
3062 05:52:54.738469
3063 05:52:54.738795
3064 05:52:54.740390 TX Vref Scan disable
3065 05:52:54.744124 == TX Byte 0 ==
3066 05:52:54.747414 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3067 05:52:54.750206 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3068 05:52:54.754134 == TX Byte 1 ==
3069 05:52:54.756836 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3070 05:52:54.760633 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3071 05:52:54.761081 ==
3072 05:52:54.763458 Dram Type= 6, Freq= 0, CH_1, rank 0
3073 05:52:54.766887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3074 05:52:54.770669 ==
3075 05:52:54.780347 TX Vref=22, minBit 3, minWin=25, winSum=412
3076 05:52:54.783628 TX Vref=24, minBit 13, minWin=25, winSum=416
3077 05:52:54.786648 TX Vref=26, minBit 0, minWin=26, winSum=424
3078 05:52:54.789830 TX Vref=28, minBit 0, minWin=26, winSum=427
3079 05:52:54.793636 TX Vref=30, minBit 8, minWin=26, winSum=430
3080 05:52:54.799959 TX Vref=32, minBit 9, minWin=26, winSum=429
3081 05:52:54.803191 [TxChooseVref] Worse bit 8, Min win 26, Win sum 430, Final Vref 30
3082 05:52:54.803606
3083 05:52:54.806814 Final TX Range 1 Vref 30
3084 05:52:54.807233
3085 05:52:54.807659 ==
3086 05:52:54.810316 Dram Type= 6, Freq= 0, CH_1, rank 0
3087 05:52:54.813676 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3088 05:52:54.814106 ==
3089 05:52:54.816788
3090 05:52:54.817200
3091 05:52:54.817530 TX Vref Scan disable
3092 05:52:54.819891 == TX Byte 0 ==
3093 05:52:54.823230 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3094 05:52:54.826697 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3095 05:52:54.830493 == TX Byte 1 ==
3096 05:52:54.833531 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3097 05:52:54.836827 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3098 05:52:54.837239
3099 05:52:54.840385 [DATLAT]
3100 05:52:54.840833 Freq=1200, CH1 RK0
3101 05:52:54.841169
3102 05:52:54.843332 DATLAT Default: 0xd
3103 05:52:54.843775 0, 0xFFFF, sum = 0
3104 05:52:54.846447 1, 0xFFFF, sum = 0
3105 05:52:54.846864 2, 0xFFFF, sum = 0
3106 05:52:54.850099 3, 0xFFFF, sum = 0
3107 05:52:54.850538 4, 0xFFFF, sum = 0
3108 05:52:54.853285 5, 0xFFFF, sum = 0
3109 05:52:54.856969 6, 0xFFFF, sum = 0
3110 05:52:54.857489 7, 0xFFFF, sum = 0
3111 05:52:54.860200 8, 0xFFFF, sum = 0
3112 05:52:54.860629 9, 0xFFFF, sum = 0
3113 05:52:54.863278 10, 0xFFFF, sum = 0
3114 05:52:54.863777 11, 0x0, sum = 1
3115 05:52:54.867065 12, 0x0, sum = 2
3116 05:52:54.867489 13, 0x0, sum = 3
3117 05:52:54.867922 14, 0x0, sum = 4
3118 05:52:54.869993 best_step = 12
3119 05:52:54.870411
3120 05:52:54.870916 ==
3121 05:52:54.873465 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 05:52:54.876892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3123 05:52:54.877415 ==
3124 05:52:54.880077 RX Vref Scan: 1
3125 05:52:54.880498
3126 05:52:54.884156 Set Vref Range= 32 -> 127
3127 05:52:54.884673
3128 05:52:54.885153 RX Vref 32 -> 127, step: 1
3129 05:52:54.885558
3130 05:52:54.886746 RX Delay -29 -> 252, step: 4
3131 05:52:54.887170
3132 05:52:54.889870 Set Vref, RX VrefLevel [Byte0]: 32
3133 05:52:54.893336 [Byte1]: 32
3134 05:52:54.896841
3135 05:52:54.897264 Set Vref, RX VrefLevel [Byte0]: 33
3136 05:52:54.900635 [Byte1]: 33
3137 05:52:54.904999
3138 05:52:54.905522 Set Vref, RX VrefLevel [Byte0]: 34
3139 05:52:54.907769 [Byte1]: 34
3140 05:52:54.912674
3141 05:52:54.913150 Set Vref, RX VrefLevel [Byte0]: 35
3142 05:52:54.915832 [Byte1]: 35
3143 05:52:54.920476
3144 05:52:54.920939 Set Vref, RX VrefLevel [Byte0]: 36
3145 05:52:54.923715 [Byte1]: 36
3146 05:52:54.928651
3147 05:52:54.929109 Set Vref, RX VrefLevel [Byte0]: 37
3148 05:52:54.931938 [Byte1]: 37
3149 05:52:54.936614
3150 05:52:54.937169 Set Vref, RX VrefLevel [Byte0]: 38
3151 05:52:54.939936 [Byte1]: 38
3152 05:52:54.944573
3153 05:52:54.945130 Set Vref, RX VrefLevel [Byte0]: 39
3154 05:52:54.947696 [Byte1]: 39
3155 05:52:54.952679
3156 05:52:54.953220 Set Vref, RX VrefLevel [Byte0]: 40
3157 05:52:54.956202 [Byte1]: 40
3158 05:52:54.960368
3159 05:52:54.960917 Set Vref, RX VrefLevel [Byte0]: 41
3160 05:52:54.963560 [Byte1]: 41
3161 05:52:54.968554
3162 05:52:54.969106 Set Vref, RX VrefLevel [Byte0]: 42
3163 05:52:54.971900 [Byte1]: 42
3164 05:52:54.976374
3165 05:52:54.976919 Set Vref, RX VrefLevel [Byte0]: 43
3166 05:52:54.980015 [Byte1]: 43
3167 05:52:54.983998
3168 05:52:54.984408 Set Vref, RX VrefLevel [Byte0]: 44
3169 05:52:54.987331 [Byte1]: 44
3170 05:52:54.992404
3171 05:52:54.992856 Set Vref, RX VrefLevel [Byte0]: 45
3172 05:52:54.995420 [Byte1]: 45
3173 05:52:55.000368
3174 05:52:55.000820 Set Vref, RX VrefLevel [Byte0]: 46
3175 05:52:55.003680 [Byte1]: 46
3176 05:52:55.008142
3177 05:52:55.008551 Set Vref, RX VrefLevel [Byte0]: 47
3178 05:52:55.011706 [Byte1]: 47
3179 05:52:55.015988
3180 05:52:55.016495 Set Vref, RX VrefLevel [Byte0]: 48
3181 05:52:55.019408 [Byte1]: 48
3182 05:52:55.024187
3183 05:52:55.024598 Set Vref, RX VrefLevel [Byte0]: 49
3184 05:52:55.027384 [Byte1]: 49
3185 05:52:55.032542
3186 05:52:55.033113 Set Vref, RX VrefLevel [Byte0]: 50
3187 05:52:55.035471 [Byte1]: 50
3188 05:52:55.040158
3189 05:52:55.040570 Set Vref, RX VrefLevel [Byte0]: 51
3190 05:52:55.043590 [Byte1]: 51
3191 05:52:55.048294
3192 05:52:55.048854 Set Vref, RX VrefLevel [Byte0]: 52
3193 05:52:55.051503 [Byte1]: 52
3194 05:52:55.056053
3195 05:52:55.056558 Set Vref, RX VrefLevel [Byte0]: 53
3196 05:52:55.059451 [Byte1]: 53
3197 05:52:55.063929
3198 05:52:55.064438 Set Vref, RX VrefLevel [Byte0]: 54
3199 05:52:55.066938 [Byte1]: 54
3200 05:52:55.071875
3201 05:52:55.072423 Set Vref, RX VrefLevel [Byte0]: 55
3202 05:52:55.075277 [Byte1]: 55
3203 05:52:55.080068
3204 05:52:55.080571 Set Vref, RX VrefLevel [Byte0]: 56
3205 05:52:55.083062 [Byte1]: 56
3206 05:52:55.088307
3207 05:52:55.088855 Set Vref, RX VrefLevel [Byte0]: 57
3208 05:52:55.091523 [Byte1]: 57
3209 05:52:55.095951
3210 05:52:55.096464 Set Vref, RX VrefLevel [Byte0]: 58
3211 05:52:55.099070 [Byte1]: 58
3212 05:52:55.103751
3213 05:52:55.104254 Set Vref, RX VrefLevel [Byte0]: 59
3214 05:52:55.106791 [Byte1]: 59
3215 05:52:55.112123
3216 05:52:55.112952 Set Vref, RX VrefLevel [Byte0]: 60
3217 05:52:55.114907 [Byte1]: 60
3218 05:52:55.119445
3219 05:52:55.119852 Set Vref, RX VrefLevel [Byte0]: 61
3220 05:52:55.122638 [Byte1]: 61
3221 05:52:55.127585
3222 05:52:55.128087 Set Vref, RX VrefLevel [Byte0]: 62
3223 05:52:55.130585 [Byte1]: 62
3224 05:52:55.135598
3225 05:52:55.136269 Set Vref, RX VrefLevel [Byte0]: 63
3226 05:52:55.138830 [Byte1]: 63
3227 05:52:55.143622
3228 05:52:55.144106 Set Vref, RX VrefLevel [Byte0]: 64
3229 05:52:55.146976 [Byte1]: 64
3230 05:52:55.151317
3231 05:52:55.151730 Set Vref, RX VrefLevel [Byte0]: 65
3232 05:52:55.154431 [Byte1]: 65
3233 05:52:55.159375
3234 05:52:55.159788 Final RX Vref Byte 0 = 55 to rank0
3235 05:52:55.163008 Final RX Vref Byte 1 = 49 to rank0
3236 05:52:55.166119 Final RX Vref Byte 0 = 55 to rank1
3237 05:52:55.169592 Final RX Vref Byte 1 = 49 to rank1==
3238 05:52:55.172772 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 05:52:55.179479 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3240 05:52:55.179988 ==
3241 05:52:55.180371 DQS Delay:
3242 05:52:55.180691 DQS0 = 0, DQS1 = 0
3243 05:52:55.182453 DQM Delay:
3244 05:52:55.183122 DQM0 = 115, DQM1 = 105
3245 05:52:55.186032 DQ Delay:
3246 05:52:55.189314 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3247 05:52:55.192157 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3248 05:52:55.195944 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3249 05:52:55.199272 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =114
3250 05:52:55.199911
3251 05:52:55.200502
3252 05:52:55.205938 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
3253 05:52:55.208746 CH1 RK0: MR19=404, MR18=1313
3254 05:52:55.215292 CH1_RK0: MR19=0x404, MR18=0x1313, DQSOSC=402, MR23=63, INC=40, DEC=27
3255 05:52:55.215654
3256 05:52:55.219161 ----->DramcWriteLeveling(PI) begin...
3257 05:52:55.219444 ==
3258 05:52:55.221957 Dram Type= 6, Freq= 0, CH_1, rank 1
3259 05:52:55.225396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3260 05:52:55.228839 ==
3261 05:52:55.229037 Write leveling (Byte 0): 21 => 21
3262 05:52:55.231930 Write leveling (Byte 1): 23 => 23
3263 05:52:55.235556 DramcWriteLeveling(PI) end<-----
3264 05:52:55.235733
3265 05:52:55.235893 ==
3266 05:52:55.238348 Dram Type= 6, Freq= 0, CH_1, rank 1
3267 05:52:55.245235 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3268 05:52:55.245384 ==
3269 05:52:55.245519 [Gating] SW mode calibration
3270 05:52:55.255418 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3271 05:52:55.258721 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3272 05:52:55.262029 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3273 05:52:55.268670 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3274 05:52:55.272438 0 11 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3275 05:52:55.275299 0 11 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
3276 05:52:55.282109 0 11 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
3277 05:52:55.285256 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3278 05:52:55.288690 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3279 05:52:55.295571 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3280 05:52:55.298685 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3281 05:52:55.301801 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3282 05:52:55.308925 0 12 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3283 05:52:55.312115 0 12 12 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
3284 05:52:55.315663 0 12 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
3285 05:52:55.322003 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3286 05:52:55.325532 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3287 05:52:55.328686 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3288 05:52:55.335094 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3289 05:52:55.338686 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3290 05:52:55.341665 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3291 05:52:55.348557 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3292 05:52:55.351879 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3293 05:52:55.355042 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 05:52:55.362057 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 05:52:55.365464 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 05:52:55.368639 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 05:52:55.375021 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 05:52:55.378343 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 05:52:55.381910 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 05:52:55.388971 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 05:52:55.391767 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3302 05:52:55.394798 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3303 05:52:55.398453 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3304 05:52:55.405563 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3305 05:52:55.408819 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3306 05:52:55.412068 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3307 05:52:55.418650 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3308 05:52:55.421847 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3309 05:52:55.425123 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3310 05:52:55.428397 Total UI for P1: 0, mck2ui 16
3311 05:52:55.431818 best dqsien dly found for B0: ( 0, 15, 14)
3312 05:52:55.438620 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3313 05:52:55.438942 Total UI for P1: 0, mck2ui 16
3314 05:52:55.445240 best dqsien dly found for B1: ( 0, 15, 16)
3315 05:52:55.448864 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3316 05:52:55.452149 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3317 05:52:55.452689
3318 05:52:55.455103 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3319 05:52:55.458539 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3320 05:52:55.462066 [Gating] SW calibration Done
3321 05:52:55.462762 ==
3322 05:52:55.465302 Dram Type= 6, Freq= 0, CH_1, rank 1
3323 05:52:55.468540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3324 05:52:55.468985 ==
3325 05:52:55.471869 RX Vref Scan: 0
3326 05:52:55.472383
3327 05:52:55.472742 RX Vref 0 -> 0, step: 1
3328 05:52:55.475067
3329 05:52:55.475417 RX Delay -40 -> 252, step: 8
3330 05:52:55.482120 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3331 05:52:55.485508 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
3332 05:52:55.488236 iDelay=200, Bit 2, Center 103 (24 ~ 183) 160
3333 05:52:55.491765 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3334 05:52:55.495089 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3335 05:52:55.498426 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3336 05:52:55.505310 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3337 05:52:55.508278 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3338 05:52:55.512157 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3339 05:52:55.515118 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3340 05:52:55.518566 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3341 05:52:55.525277 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3342 05:52:55.528452 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3343 05:52:55.531679 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3344 05:52:55.534795 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3345 05:52:55.538307 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3346 05:52:55.541614 ==
3347 05:52:55.545636 Dram Type= 6, Freq= 0, CH_1, rank 1
3348 05:52:55.548696 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3349 05:52:55.549274 ==
3350 05:52:55.549604 DQS Delay:
3351 05:52:55.551638 DQS0 = 0, DQS1 = 0
3352 05:52:55.552138 DQM Delay:
3353 05:52:55.555065 DQM0 = 115, DQM1 = 105
3354 05:52:55.555562 DQ Delay:
3355 05:52:55.558607 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3356 05:52:55.561487 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3357 05:52:55.565088 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3358 05:52:55.568158 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3359 05:52:55.568637
3360 05:52:55.568994
3361 05:52:55.569323 ==
3362 05:52:55.571600 Dram Type= 6, Freq= 0, CH_1, rank 1
3363 05:52:55.578061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3364 05:52:55.578547 ==
3365 05:52:55.578868
3366 05:52:55.579188
3367 05:52:55.579548 TX Vref Scan disable
3368 05:52:55.581577 == TX Byte 0 ==
3369 05:52:55.585038 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3370 05:52:55.588439 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3371 05:52:55.591845 == TX Byte 1 ==
3372 05:52:55.595179 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3373 05:52:55.598181 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3374 05:52:55.601847 ==
3375 05:52:55.604977 Dram Type= 6, Freq= 0, CH_1, rank 1
3376 05:52:55.608492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3377 05:52:55.609035 ==
3378 05:52:55.619608 TX Vref=22, minBit 8, minWin=25, winSum=419
3379 05:52:55.622836 TX Vref=24, minBit 0, minWin=26, winSum=426
3380 05:52:55.626142 TX Vref=26, minBit 9, minWin=25, winSum=428
3381 05:52:55.629361 TX Vref=28, minBit 8, minWin=26, winSum=430
3382 05:52:55.633040 TX Vref=30, minBit 0, minWin=26, winSum=430
3383 05:52:55.636281 TX Vref=32, minBit 0, minWin=26, winSum=432
3384 05:52:55.642679 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 32
3385 05:52:55.643189
3386 05:52:55.646124 Final TX Range 1 Vref 32
3387 05:52:55.646531
3388 05:52:55.646849 ==
3389 05:52:55.649489 Dram Type= 6, Freq= 0, CH_1, rank 1
3390 05:52:55.658436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3391 05:52:55.658878 ==
3392 05:52:55.659233
3393 05:52:55.659540
3394 05:52:55.659827 TX Vref Scan disable
3395 05:52:55.660430 == TX Byte 0 ==
3396 05:52:55.662502 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3397 05:52:55.666149 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3398 05:52:55.669326 == TX Byte 1 ==
3399 05:52:55.672615 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3400 05:52:55.675805 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3401 05:52:55.676214
3402 05:52:55.679660 [DATLAT]
3403 05:52:55.680077 Freq=1200, CH1 RK1
3404 05:52:55.680399
3405 05:52:55.682694 DATLAT Default: 0xc
3406 05:52:55.683098 0, 0xFFFF, sum = 0
3407 05:52:55.686089 1, 0xFFFF, sum = 0
3408 05:52:55.686501 2, 0xFFFF, sum = 0
3409 05:52:55.689252 3, 0xFFFF, sum = 0
3410 05:52:55.689677 4, 0xFFFF, sum = 0
3411 05:52:55.692460 5, 0xFFFF, sum = 0
3412 05:52:55.692918 6, 0xFFFF, sum = 0
3413 05:52:55.695751 7, 0xFFFF, sum = 0
3414 05:52:55.698771 8, 0xFFFF, sum = 0
3415 05:52:55.698852 9, 0xFFFF, sum = 0
3416 05:52:55.702742 10, 0xFFFF, sum = 0
3417 05:52:55.703152 11, 0x0, sum = 1
3418 05:52:55.706216 12, 0x0, sum = 2
3419 05:52:55.706626 13, 0x0, sum = 3
3420 05:52:55.706953 14, 0x0, sum = 4
3421 05:52:55.709005 best_step = 12
3422 05:52:55.709412
3423 05:52:55.709733 ==
3424 05:52:55.713073 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 05:52:55.715629 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3426 05:52:55.716054 ==
3427 05:52:55.719080 RX Vref Scan: 0
3428 05:52:55.719490
3429 05:52:55.719814 RX Vref 0 -> 0, step: 1
3430 05:52:55.722500
3431 05:52:55.723007 RX Delay -29 -> 252, step: 4
3432 05:52:55.729643 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3433 05:52:55.732993 iDelay=199, Bit 1, Center 108 (39 ~ 178) 140
3434 05:52:55.736253 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3435 05:52:55.740030 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3436 05:52:55.742969 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3437 05:52:55.749522 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3438 05:52:55.753311 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3439 05:52:55.756308 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3440 05:52:55.759349 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3441 05:52:55.763543 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3442 05:52:55.769650 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3443 05:52:55.772946 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3444 05:52:55.776414 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3445 05:52:55.779693 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3446 05:52:55.782902 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3447 05:52:55.790083 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3448 05:52:55.790609 ==
3449 05:52:55.792945 Dram Type= 6, Freq= 0, CH_1, rank 1
3450 05:52:55.796234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3451 05:52:55.796917 ==
3452 05:52:55.797262 DQS Delay:
3453 05:52:55.799618 DQS0 = 0, DQS1 = 0
3454 05:52:55.800122 DQM Delay:
3455 05:52:55.802961 DQM0 = 114, DQM1 = 103
3456 05:52:55.803365 DQ Delay:
3457 05:52:55.806787 DQ0 =114, DQ1 =108, DQ2 =108, DQ3 =112
3458 05:52:55.809517 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3459 05:52:55.813073 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3460 05:52:55.816337 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =110
3461 05:52:55.816829
3462 05:52:55.817192
3463 05:52:55.826303 [DQSOSCAuto] RK1, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3464 05:52:55.829291 CH1 RK1: MR19=404, MR18=808
3465 05:52:55.832808 CH1_RK1: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
3466 05:52:55.835913 [RxdqsGatingPostProcess] freq 1200
3467 05:52:55.843098 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3468 05:52:55.846393 Pre-setting of DQS Precalculation
3469 05:52:55.850154 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3470 05:52:55.859773 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3471 05:52:55.866540 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3472 05:52:55.867098
3473 05:52:55.867461
3474 05:52:55.869458 [Calibration Summary] 2400 Mbps
3475 05:52:55.869876 CH 0, Rank 0
3476 05:52:55.872995 SW Impedance : PASS
3477 05:52:55.873552 DUTY Scan : NO K
3478 05:52:55.876288 ZQ Calibration : PASS
3479 05:52:55.879596 Jitter Meter : NO K
3480 05:52:55.880157 CBT Training : PASS
3481 05:52:55.883251 Write leveling : PASS
3482 05:52:55.886429 RX DQS gating : PASS
3483 05:52:55.886992 RX DQ/DQS(RDDQC) : PASS
3484 05:52:55.889791 TX DQ/DQS : PASS
3485 05:52:55.893009 RX DATLAT : PASS
3486 05:52:55.893583 RX DQ/DQS(Engine): PASS
3487 05:52:55.896291 TX OE : NO K
3488 05:52:55.896987 All Pass.
3489 05:52:55.897368
3490 05:52:55.899757 CH 0, Rank 1
3491 05:52:55.900313 SW Impedance : PASS
3492 05:52:55.902929 DUTY Scan : NO K
3493 05:52:55.903387 ZQ Calibration : PASS
3494 05:52:55.905884 Jitter Meter : NO K
3495 05:52:55.909413 CBT Training : PASS
3496 05:52:55.909818 Write leveling : PASS
3497 05:52:55.912881 RX DQS gating : PASS
3498 05:52:55.915870 RX DQ/DQS(RDDQC) : PASS
3499 05:52:55.916495 TX DQ/DQS : PASS
3500 05:52:55.919832 RX DATLAT : PASS
3501 05:52:55.922404 RX DQ/DQS(Engine): PASS
3502 05:52:55.922824 TX OE : NO K
3503 05:52:55.926426 All Pass.
3504 05:52:55.926941
3505 05:52:55.927280 CH 1, Rank 0
3506 05:52:55.928982 SW Impedance : PASS
3507 05:52:55.929396 DUTY Scan : NO K
3508 05:52:55.932595 ZQ Calibration : PASS
3509 05:52:55.936003 Jitter Meter : NO K
3510 05:52:55.936417 CBT Training : PASS
3511 05:52:55.939385 Write leveling : PASS
3512 05:52:55.942281 RX DQS gating : PASS
3513 05:52:55.942698 RX DQ/DQS(RDDQC) : PASS
3514 05:52:55.946027 TX DQ/DQS : PASS
3515 05:52:55.946518 RX DATLAT : PASS
3516 05:52:55.949157 RX DQ/DQS(Engine): PASS
3517 05:52:55.952830 TX OE : NO K
3518 05:52:55.953365 All Pass.
3519 05:52:55.953702
3520 05:52:55.954008 CH 1, Rank 1
3521 05:52:55.955920 SW Impedance : PASS
3522 05:52:55.959204 DUTY Scan : NO K
3523 05:52:55.959619 ZQ Calibration : PASS
3524 05:52:55.962749 Jitter Meter : NO K
3525 05:52:55.965606 CBT Training : PASS
3526 05:52:55.965688 Write leveling : PASS
3527 05:52:55.969086 RX DQS gating : PASS
3528 05:52:55.971828 RX DQ/DQS(RDDQC) : PASS
3529 05:52:55.971909 TX DQ/DQS : PASS
3530 05:52:55.975023 RX DATLAT : PASS
3531 05:52:55.978512 RX DQ/DQS(Engine): PASS
3532 05:52:55.978593 TX OE : NO K
3533 05:52:55.982034 All Pass.
3534 05:52:55.982197
3535 05:52:55.982275 DramC Write-DBI off
3536 05:52:55.985597 PER_BANK_REFRESH: Hybrid Mode
3537 05:52:55.985761 TX_TRACKING: ON
3538 05:52:55.995773 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3539 05:52:55.998830 [FAST_K] Save calibration result to emmc
3540 05:52:56.002245 dramc_set_vcore_voltage set vcore to 650000
3541 05:52:56.005503 Read voltage for 600, 5
3542 05:52:56.005706 Vio18 = 0
3543 05:52:56.009101 Vcore = 650000
3544 05:52:56.009287 Vdram = 0
3545 05:52:56.009406 Vddq = 0
3546 05:52:56.009513 Vmddr = 0
3547 05:52:56.015336 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3548 05:52:56.021808 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3549 05:52:56.022074 MEM_TYPE=3, freq_sel=19
3550 05:52:56.025346 sv_algorithm_assistance_LP4_1600
3551 05:52:56.028508 ============ PULL DRAM RESETB DOWN ============
3552 05:52:56.035508 ========== PULL DRAM RESETB DOWN end =========
3553 05:52:56.038646 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3554 05:52:56.042062 ===================================
3555 05:52:56.045355 LPDDR4 DRAM CONFIGURATION
3556 05:52:56.048775 ===================================
3557 05:52:56.049196 EX_ROW_EN[0] = 0x0
3558 05:52:56.052224 EX_ROW_EN[1] = 0x0
3559 05:52:56.052789 LP4Y_EN = 0x0
3560 05:52:56.055261 WORK_FSP = 0x0
3561 05:52:56.058742 WL = 0x2
3562 05:52:56.059263 RL = 0x2
3563 05:52:56.062067 BL = 0x2
3564 05:52:56.062482 RPST = 0x0
3565 05:52:56.065332 RD_PRE = 0x0
3566 05:52:56.065864 WR_PRE = 0x1
3567 05:52:56.068985 WR_PST = 0x0
3568 05:52:56.069506 DBI_WR = 0x0
3569 05:52:56.072424 DBI_RD = 0x0
3570 05:52:56.072975 OTF = 0x1
3571 05:52:56.075385 ===================================
3572 05:52:56.078902 ===================================
3573 05:52:56.082084 ANA top config
3574 05:52:56.086038 ===================================
3575 05:52:56.086571 DLL_ASYNC_EN = 0
3576 05:52:56.088672 ALL_SLAVE_EN = 1
3577 05:52:56.091844 NEW_RANK_MODE = 1
3578 05:52:56.095039 DLL_IDLE_MODE = 1
3579 05:52:56.095457 LP45_APHY_COMB_EN = 1
3580 05:52:56.098538 TX_ODT_DIS = 1
3581 05:52:56.101636 NEW_8X_MODE = 1
3582 05:52:56.105166 ===================================
3583 05:52:56.108673 ===================================
3584 05:52:56.111666 data_rate = 1200
3585 05:52:56.114742 CKR = 1
3586 05:52:56.118375 DQ_P2S_RATIO = 8
3587 05:52:56.121521 ===================================
3588 05:52:56.121938 CA_P2S_RATIO = 8
3589 05:52:56.125024 DQ_CA_OPEN = 0
3590 05:52:56.128504 DQ_SEMI_OPEN = 0
3591 05:52:56.131556 CA_SEMI_OPEN = 0
3592 05:52:56.134871 CA_FULL_RATE = 0
3593 05:52:56.138162 DQ_CKDIV4_EN = 1
3594 05:52:56.138577 CA_CKDIV4_EN = 1
3595 05:52:56.141533 CA_PREDIV_EN = 0
3596 05:52:56.144859 PH8_DLY = 0
3597 05:52:56.147610 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3598 05:52:56.151288 DQ_AAMCK_DIV = 4
3599 05:52:56.154892 CA_AAMCK_DIV = 4
3600 05:52:56.155424 CA_ADMCK_DIV = 4
3601 05:52:56.158235 DQ_TRACK_CA_EN = 0
3602 05:52:56.161570 CA_PICK = 600
3603 05:52:56.164643 CA_MCKIO = 600
3604 05:52:56.167871 MCKIO_SEMI = 0
3605 05:52:56.171360 PLL_FREQ = 2288
3606 05:52:56.174689 DQ_UI_PI_RATIO = 32
3607 05:52:56.175112 CA_UI_PI_RATIO = 0
3608 05:52:56.177881 ===================================
3609 05:52:56.181604 ===================================
3610 05:52:56.184538 memory_type:LPDDR4
3611 05:52:56.188307 GP_NUM : 10
3612 05:52:56.188864 SRAM_EN : 1
3613 05:52:56.191680 MD32_EN : 0
3614 05:52:56.194651 ===================================
3615 05:52:56.197465 [ANA_INIT] >>>>>>>>>>>>>>
3616 05:52:56.201699 <<<<<< [CONFIGURE PHASE]: ANA_TX
3617 05:52:56.204329 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3618 05:52:56.207624 ===================================
3619 05:52:56.210770 data_rate = 1200,PCW = 0X5800
3620 05:52:56.214196 ===================================
3621 05:52:56.217431 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3622 05:52:56.220802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3623 05:52:56.227289 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3624 05:52:56.230419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3625 05:52:56.233899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3626 05:52:56.237285 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3627 05:52:56.240593 [ANA_INIT] flow start
3628 05:52:56.244113 [ANA_INIT] PLL >>>>>>>>
3629 05:52:56.244527 [ANA_INIT] PLL <<<<<<<<
3630 05:52:56.246877 [ANA_INIT] MIDPI >>>>>>>>
3631 05:52:56.250234 [ANA_INIT] MIDPI <<<<<<<<
3632 05:52:56.250651 [ANA_INIT] DLL >>>>>>>>
3633 05:52:56.253635 [ANA_INIT] flow end
3634 05:52:56.256435 ============ LP4 DIFF to SE enter ============
3635 05:52:56.263457 ============ LP4 DIFF to SE exit ============
3636 05:52:56.263539 [ANA_INIT] <<<<<<<<<<<<<
3637 05:52:56.266763 [Flow] Enable top DCM control >>>>>
3638 05:52:56.270075 [Flow] Enable top DCM control <<<<<
3639 05:52:56.273216 Enable DLL master slave shuffle
3640 05:52:56.279656 ==============================================================
3641 05:52:56.279738 Gating Mode config
3642 05:52:56.286814 ==============================================================
3643 05:52:56.289907 Config description:
3644 05:52:56.296442 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3645 05:52:56.303454 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3646 05:52:56.309620 SELPH_MODE 0: By rank 1: By Phase
3647 05:52:56.316474 ==============================================================
3648 05:52:56.320061 GAT_TRACK_EN = 1
3649 05:52:56.320290 RX_GATING_MODE = 2
3650 05:52:56.323296 RX_GATING_TRACK_MODE = 2
3651 05:52:56.326578 SELPH_MODE = 1
3652 05:52:56.330038 PICG_EARLY_EN = 1
3653 05:52:56.333184 VALID_LAT_VALUE = 1
3654 05:52:56.340125 ==============================================================
3655 05:52:56.343431 Enter into Gating configuration >>>>
3656 05:52:56.346533 Exit from Gating configuration <<<<
3657 05:52:56.350015 Enter into DVFS_PRE_config >>>>>
3658 05:52:56.359696 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3659 05:52:56.362757 Exit from DVFS_PRE_config <<<<<
3660 05:52:56.366061 Enter into PICG configuration >>>>
3661 05:52:56.369680 Exit from PICG configuration <<<<
3662 05:52:56.372701 [RX_INPUT] configuration >>>>>
3663 05:52:56.376215 [RX_INPUT] configuration <<<<<
3664 05:52:56.379482 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3665 05:52:56.385788 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3666 05:52:56.392566 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3667 05:52:56.399108 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3668 05:52:56.402493 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3669 05:52:56.409169 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3670 05:52:56.412360 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3671 05:52:56.419024 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3672 05:52:56.422636 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3673 05:52:56.425947 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3674 05:52:56.428913 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3675 05:52:56.435805 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3676 05:52:56.438781 ===================================
3677 05:52:56.442407 LPDDR4 DRAM CONFIGURATION
3678 05:52:56.445210 ===================================
3679 05:52:56.445634 EX_ROW_EN[0] = 0x0
3680 05:52:56.448628 EX_ROW_EN[1] = 0x0
3681 05:52:56.449191 LP4Y_EN = 0x0
3682 05:52:56.452111 WORK_FSP = 0x0
3683 05:52:56.452517 WL = 0x2
3684 05:52:56.455714 RL = 0x2
3685 05:52:56.456287 BL = 0x2
3686 05:52:56.458478 RPST = 0x0
3687 05:52:56.458886 RD_PRE = 0x0
3688 05:52:56.461978 WR_PRE = 0x1
3689 05:52:56.462381 WR_PST = 0x0
3690 05:52:56.465542 DBI_WR = 0x0
3691 05:52:56.465950 DBI_RD = 0x0
3692 05:52:56.468769 OTF = 0x1
3693 05:52:56.471859 ===================================
3694 05:52:56.475067 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3695 05:52:56.478841 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3696 05:52:56.485083 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3697 05:52:56.488121 ===================================
3698 05:52:56.488200 LPDDR4 DRAM CONFIGURATION
3699 05:52:56.491542 ===================================
3700 05:52:56.494548 EX_ROW_EN[0] = 0x10
3701 05:52:56.497856 EX_ROW_EN[1] = 0x0
3702 05:52:56.497935 LP4Y_EN = 0x0
3703 05:52:56.501149 WORK_FSP = 0x0
3704 05:52:56.501228 WL = 0x2
3705 05:52:56.504624 RL = 0x2
3706 05:52:56.504761 BL = 0x2
3707 05:52:56.507984 RPST = 0x0
3708 05:52:56.508063 RD_PRE = 0x0
3709 05:52:56.511073 WR_PRE = 0x1
3710 05:52:56.511152 WR_PST = 0x0
3711 05:52:56.514906 DBI_WR = 0x0
3712 05:52:56.515010 DBI_RD = 0x0
3713 05:52:56.517826 OTF = 0x1
3714 05:52:56.521265 ===================================
3715 05:52:56.527667 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3716 05:52:56.531162 nWR fixed to 30
3717 05:52:56.534560 [ModeRegInit_LP4] CH0 RK0
3718 05:52:56.534640 [ModeRegInit_LP4] CH0 RK1
3719 05:52:56.537565 [ModeRegInit_LP4] CH1 RK0
3720 05:52:56.540906 [ModeRegInit_LP4] CH1 RK1
3721 05:52:56.541011 match AC timing 16
3722 05:52:56.547608 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3723 05:52:56.550957 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3724 05:52:56.554632 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3725 05:52:56.560631 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3726 05:52:56.564283 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3727 05:52:56.564364 ==
3728 05:52:56.567827 Dram Type= 6, Freq= 0, CH_0, rank 0
3729 05:52:56.570754 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3730 05:52:56.570835 ==
3731 05:52:56.577293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3732 05:52:56.584023 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3733 05:52:56.587201 [CA 0] Center 35 (5~66) winsize 62
3734 05:52:56.590546 [CA 1] Center 35 (5~66) winsize 62
3735 05:52:56.593874 [CA 2] Center 34 (4~65) winsize 62
3736 05:52:56.597419 [CA 3] Center 34 (4~65) winsize 62
3737 05:52:56.600297 [CA 4] Center 33 (3~64) winsize 62
3738 05:52:56.603512 [CA 5] Center 33 (3~64) winsize 62
3739 05:52:56.603591
3740 05:52:56.607438 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3741 05:52:56.607510
3742 05:52:56.610201 [CATrainingPosCal] consider 1 rank data
3743 05:52:56.613653 u2DelayCellTimex100 = 270/100 ps
3744 05:52:56.616920 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3745 05:52:56.620060 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3746 05:52:56.623462 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3747 05:52:56.626878 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3748 05:52:56.633801 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3749 05:52:56.637164 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3750 05:52:56.637237
3751 05:52:56.640300 CA PerBit enable=1, Macro0, CA PI delay=33
3752 05:52:56.640371
3753 05:52:56.643984 [CBTSetCACLKResult] CA Dly = 33
3754 05:52:56.644081 CS Dly: 5 (0~36)
3755 05:52:56.644171 ==
3756 05:52:56.646805 Dram Type= 6, Freq= 0, CH_0, rank 1
3757 05:52:56.653379 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3758 05:52:56.653454 ==
3759 05:52:56.656434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3760 05:52:56.663596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3761 05:52:56.667061 [CA 0] Center 36 (6~66) winsize 61
3762 05:52:56.669660 [CA 1] Center 35 (5~66) winsize 62
3763 05:52:56.673584 [CA 2] Center 34 (4~65) winsize 62
3764 05:52:56.676565 [CA 3] Center 34 (4~65) winsize 62
3765 05:52:56.679882 [CA 4] Center 33 (3~64) winsize 62
3766 05:52:56.683319 [CA 5] Center 33 (3~64) winsize 62
3767 05:52:56.683418
3768 05:52:56.686611 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3769 05:52:56.686684
3770 05:52:56.689401 [CATrainingPosCal] consider 2 rank data
3771 05:52:56.692602 u2DelayCellTimex100 = 270/100 ps
3772 05:52:56.696282 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3773 05:52:56.699698 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3774 05:52:56.706251 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3775 05:52:56.709845 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3776 05:52:56.712631 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3777 05:52:56.715956 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3778 05:52:56.716027
3779 05:52:56.719215 CA PerBit enable=1, Macro0, CA PI delay=33
3780 05:52:56.719342
3781 05:52:56.722837 [CBTSetCACLKResult] CA Dly = 33
3782 05:52:56.722938 CS Dly: 5 (0~36)
3783 05:52:56.723027
3784 05:52:56.726137 ----->DramcWriteLeveling(PI) begin...
3785 05:52:56.729455 ==
3786 05:52:56.732646 Dram Type= 6, Freq= 0, CH_0, rank 0
3787 05:52:56.736030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3788 05:52:56.736101 ==
3789 05:52:56.739191 Write leveling (Byte 0): 30 => 30
3790 05:52:56.742723 Write leveling (Byte 1): 30 => 30
3791 05:52:56.745873 DramcWriteLeveling(PI) end<-----
3792 05:52:56.745971
3793 05:52:56.746059 ==
3794 05:52:56.749531 Dram Type= 6, Freq= 0, CH_0, rank 0
3795 05:52:56.752641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3796 05:52:56.752758 ==
3797 05:52:56.755987 [Gating] SW mode calibration
3798 05:52:56.762303 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3799 05:52:56.769232 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3800 05:52:56.772408 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3801 05:52:56.775636 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3802 05:52:56.782574 0 5 8 | B1->B0 | 3232 3333 | 1 1 | (1 1) (1 1)
3803 05:52:56.785790 0 5 12 | B1->B0 | 2929 2323 | 1 0 | (0 1) (0 0)
3804 05:52:56.788634 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3805 05:52:56.796029 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3806 05:52:56.798793 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3807 05:52:56.801958 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3808 05:52:56.809104 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3809 05:52:56.811641 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3810 05:52:56.815160 0 6 8 | B1->B0 | 2b2b 3232 | 0 0 | (1 1) (0 0)
3811 05:52:56.821632 0 6 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3812 05:52:56.825209 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3813 05:52:56.828305 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3814 05:52:56.834748 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3815 05:52:56.838028 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3816 05:52:56.841626 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3817 05:52:56.847837 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3818 05:52:56.851196 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3819 05:52:56.854502 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 05:52:56.861320 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 05:52:56.864582 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 05:52:56.867848 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 05:52:56.874238 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 05:52:56.877619 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 05:52:56.881229 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 05:52:56.887590 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 05:52:56.891166 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 05:52:56.894437 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3829 05:52:56.900725 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3830 05:52:56.904567 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3831 05:52:56.907954 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3832 05:52:56.911242 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3833 05:52:56.917459 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3834 05:52:56.921066 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
3835 05:52:56.924089 Total UI for P1: 0, mck2ui 16
3836 05:52:56.927506 best dqsien dly found for B0: ( 0, 9, 6)
3837 05:52:56.930837 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3838 05:52:56.937308 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3839 05:52:56.940580 Total UI for P1: 0, mck2ui 16
3840 05:52:56.943925 best dqsien dly found for B1: ( 0, 9, 12)
3841 05:52:56.947609 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3842 05:52:56.950603 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
3843 05:52:56.950673
3844 05:52:56.953695 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3845 05:52:56.957269 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
3846 05:52:56.960210 [Gating] SW calibration Done
3847 05:52:56.960306 ==
3848 05:52:56.964040 Dram Type= 6, Freq= 0, CH_0, rank 0
3849 05:52:56.967138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3850 05:52:56.967211 ==
3851 05:52:56.970654 RX Vref Scan: 0
3852 05:52:56.970749
3853 05:52:56.973810 RX Vref 0 -> 0, step: 1
3854 05:52:56.973909
3855 05:52:56.973996 RX Delay -230 -> 252, step: 16
3856 05:52:56.980202 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3857 05:52:56.983576 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3858 05:52:56.986896 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3859 05:52:56.990480 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3860 05:52:56.996917 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3861 05:52:57.000206 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3862 05:52:57.003644 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3863 05:52:57.006945 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3864 05:52:57.013431 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3865 05:52:57.016683 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3866 05:52:57.020082 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3867 05:52:57.023391 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3868 05:52:57.029867 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3869 05:52:57.033104 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3870 05:52:57.036407 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3871 05:52:57.039634 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3872 05:52:57.039733 ==
3873 05:52:57.042904 Dram Type= 6, Freq= 0, CH_0, rank 0
3874 05:52:57.049622 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3875 05:52:57.049713 ==
3876 05:52:57.049779 DQS Delay:
3877 05:52:57.052817 DQS0 = 0, DQS1 = 0
3878 05:52:57.052949 DQM Delay:
3879 05:52:57.053038 DQM0 = 38, DQM1 = 33
3880 05:52:57.056355 DQ Delay:
3881 05:52:57.059471 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3882 05:52:57.062778 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
3883 05:52:57.065797 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3884 05:52:57.069304 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3885 05:52:57.069405
3886 05:52:57.069505
3887 05:52:57.069596 ==
3888 05:52:57.072782 Dram Type= 6, Freq= 0, CH_0, rank 0
3889 05:52:57.075819 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3890 05:52:57.075895 ==
3891 05:52:57.075982
3892 05:52:57.076049
3893 05:52:57.079316 TX Vref Scan disable
3894 05:52:57.082378 == TX Byte 0 ==
3895 05:52:57.085866 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3896 05:52:57.089091 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3897 05:52:57.092321 == TX Byte 1 ==
3898 05:52:57.095716 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3899 05:52:57.098843 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3900 05:52:57.098918 ==
3901 05:52:57.102540 Dram Type= 6, Freq= 0, CH_0, rank 0
3902 05:52:57.105780 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3903 05:52:57.109076 ==
3904 05:52:57.109153
3905 05:52:57.109228
3906 05:52:57.109311 TX Vref Scan disable
3907 05:52:57.112656 == TX Byte 0 ==
3908 05:52:57.116237 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3909 05:52:57.122617 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3910 05:52:57.122742 == TX Byte 1 ==
3911 05:52:57.126308 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3912 05:52:57.132441 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3913 05:52:57.132545
3914 05:52:57.132641 [DATLAT]
3915 05:52:57.132777 Freq=600, CH0 RK0
3916 05:52:57.132888
3917 05:52:57.135891 DATLAT Default: 0x9
3918 05:52:57.135963 0, 0xFFFF, sum = 0
3919 05:52:57.138989 1, 0xFFFF, sum = 0
3920 05:52:57.142551 2, 0xFFFF, sum = 0
3921 05:52:57.142652 3, 0xFFFF, sum = 0
3922 05:52:57.145680 4, 0xFFFF, sum = 0
3923 05:52:57.145780 5, 0xFFFF, sum = 0
3924 05:52:57.149324 6, 0xFFFF, sum = 0
3925 05:52:57.149426 7, 0x0, sum = 1
3926 05:52:57.149494 8, 0x0, sum = 2
3927 05:52:57.152237 9, 0x0, sum = 3
3928 05:52:57.152357 10, 0x0, sum = 4
3929 05:52:57.155742 best_step = 8
3930 05:52:57.155845
3931 05:52:57.155933 ==
3932 05:52:57.159457 Dram Type= 6, Freq= 0, CH_0, rank 0
3933 05:52:57.162461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3934 05:52:57.162563 ==
3935 05:52:57.165744 RX Vref Scan: 1
3936 05:52:57.165844
3937 05:52:57.165946 RX Vref 0 -> 0, step: 1
3938 05:52:57.166036
3939 05:52:57.168972 RX Delay -195 -> 252, step: 8
3940 05:52:57.169059
3941 05:52:57.172155 Set Vref, RX VrefLevel [Byte0]: 47
3942 05:52:57.175602 [Byte1]: 48
3943 05:52:57.179968
3944 05:52:57.180054 Final RX Vref Byte 0 = 47 to rank0
3945 05:52:57.183281 Final RX Vref Byte 1 = 48 to rank0
3946 05:52:57.186339 Final RX Vref Byte 0 = 47 to rank1
3947 05:52:57.189761 Final RX Vref Byte 1 = 48 to rank1==
3948 05:52:57.193062 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 05:52:57.199585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3950 05:52:57.199690 ==
3951 05:52:57.199782 DQS Delay:
3952 05:52:57.203083 DQS0 = 0, DQS1 = 0
3953 05:52:57.203184 DQM Delay:
3954 05:52:57.203278 DQM0 = 40, DQM1 = 30
3955 05:52:57.205953 DQ Delay:
3956 05:52:57.209401 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
3957 05:52:57.212831 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =52
3958 05:52:57.216149 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =24
3959 05:52:57.219129 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3960 05:52:57.219230
3961 05:52:57.219338
3962 05:52:57.225758 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3963 05:52:57.229468 CH0 RK0: MR19=808, MR18=5454
3964 05:52:57.236270 CH0_RK0: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113
3965 05:52:57.236375
3966 05:52:57.239022 ----->DramcWriteLeveling(PI) begin...
3967 05:52:57.239126 ==
3968 05:52:57.242844 Dram Type= 6, Freq= 0, CH_0, rank 1
3969 05:52:57.245769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3970 05:52:57.245872 ==
3971 05:52:57.249193 Write leveling (Byte 0): 32 => 32
3972 05:52:57.252275 Write leveling (Byte 1): 28 => 28
3973 05:52:57.255659 DramcWriteLeveling(PI) end<-----
3974 05:52:57.255761
3975 05:52:57.255850 ==
3976 05:52:57.258861 Dram Type= 6, Freq= 0, CH_0, rank 1
3977 05:52:57.262198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3978 05:52:57.265813 ==
3979 05:52:57.265887 [Gating] SW mode calibration
3980 05:52:57.275345 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3981 05:52:57.278546 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3982 05:52:57.282262 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 05:52:57.288721 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3984 05:52:57.292012 0 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
3985 05:52:57.295155 0 5 12 | B1->B0 | 2626 2424 | 1 0 | (1 0) (0 0)
3986 05:52:57.301969 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 05:52:57.305377 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 05:52:57.308316 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 05:52:57.315035 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 05:52:57.318512 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 05:52:57.321524 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 05:52:57.328045 0 6 8 | B1->B0 | 2a2a 3131 | 0 1 | (0 0) (0 0)
3993 05:52:57.331631 0 6 12 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
3994 05:52:57.334877 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 05:52:57.341383 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 05:52:57.344758 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 05:52:57.348344 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 05:52:57.354658 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 05:52:57.358159 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 05:52:57.361290 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4001 05:52:57.367690 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 05:52:57.371069 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 05:52:57.374542 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 05:52:57.381400 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 05:52:57.384403 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 05:52:57.387868 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 05:52:57.393800 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 05:52:57.397528 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 05:52:57.400634 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 05:52:57.407309 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 05:52:57.410827 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 05:52:57.414012 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 05:52:57.420510 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 05:52:57.423750 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 05:52:57.427020 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 05:52:57.433960 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4017 05:52:57.434072 Total UI for P1: 0, mck2ui 16
4018 05:52:57.440597 best dqsien dly found for B0: ( 0, 9, 6)
4019 05:52:57.443651 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4020 05:52:57.447288 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 05:52:57.450168 Total UI for P1: 0, mck2ui 16
4022 05:52:57.453917 best dqsien dly found for B1: ( 0, 9, 10)
4023 05:52:57.456764 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4024 05:52:57.460052 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4025 05:52:57.460161
4026 05:52:57.467078 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4027 05:52:57.470140 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4028 05:52:57.470330 [Gating] SW calibration Done
4029 05:52:57.473787 ==
4030 05:52:57.476614 Dram Type= 6, Freq= 0, CH_0, rank 1
4031 05:52:57.480370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4032 05:52:57.480456 ==
4033 05:52:57.480537 RX Vref Scan: 0
4034 05:52:57.480628
4035 05:52:57.483489 RX Vref 0 -> 0, step: 1
4036 05:52:57.483598
4037 05:52:57.486839 RX Delay -230 -> 252, step: 16
4038 05:52:57.489993 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4039 05:52:57.493540 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4040 05:52:57.499838 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4041 05:52:57.503191 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4042 05:52:57.506599 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4043 05:52:57.509939 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4044 05:52:57.516499 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4045 05:52:57.520566 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4046 05:52:57.523230 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4047 05:52:57.526861 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4048 05:52:57.529809 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4049 05:52:57.536548 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4050 05:52:57.539629 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4051 05:52:57.542885 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4052 05:52:57.546655 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4053 05:52:57.553292 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4054 05:52:57.553406 ==
4055 05:52:57.556266 Dram Type= 6, Freq= 0, CH_0, rank 1
4056 05:52:57.559776 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4057 05:52:57.559857 ==
4058 05:52:57.559920 DQS Delay:
4059 05:52:57.562960 DQS0 = 0, DQS1 = 0
4060 05:52:57.563041 DQM Delay:
4061 05:52:57.566129 DQM0 = 41, DQM1 = 33
4062 05:52:57.566210 DQ Delay:
4063 05:52:57.569358 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4064 05:52:57.572626 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4065 05:52:57.576457 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4066 05:52:57.579628 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4067 05:52:57.579708
4068 05:52:57.579771
4069 05:52:57.579830 ==
4070 05:52:57.582717 Dram Type= 6, Freq= 0, CH_0, rank 1
4071 05:52:57.589431 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4072 05:52:57.589512 ==
4073 05:52:57.589576
4074 05:52:57.589635
4075 05:52:57.589691 TX Vref Scan disable
4076 05:52:57.592597 == TX Byte 0 ==
4077 05:52:57.596265 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4078 05:52:57.602641 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4079 05:52:57.602722 == TX Byte 1 ==
4080 05:52:57.605866 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4081 05:52:57.612413 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4082 05:52:57.612494 ==
4083 05:52:57.615741 Dram Type= 6, Freq= 0, CH_0, rank 1
4084 05:52:57.619269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4085 05:52:57.619350 ==
4086 05:52:57.619414
4087 05:52:57.619473
4088 05:52:57.622296 TX Vref Scan disable
4089 05:52:57.625775 == TX Byte 0 ==
4090 05:52:57.629299 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4091 05:52:57.632432 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4092 05:52:57.635720 == TX Byte 1 ==
4093 05:52:57.639565 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4094 05:52:57.642106 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4095 05:52:57.642214
4096 05:52:57.642305 [DATLAT]
4097 05:52:57.645768 Freq=600, CH0 RK1
4098 05:52:57.645844
4099 05:52:57.648909 DATLAT Default: 0x8
4100 05:52:57.648991 0, 0xFFFF, sum = 0
4101 05:52:57.652049 1, 0xFFFF, sum = 0
4102 05:52:57.652175 2, 0xFFFF, sum = 0
4103 05:52:57.655275 3, 0xFFFF, sum = 0
4104 05:52:57.655357 4, 0xFFFF, sum = 0
4105 05:52:57.658708 5, 0xFFFF, sum = 0
4106 05:52:57.658791 6, 0xFFFF, sum = 0
4107 05:52:57.662293 7, 0x0, sum = 1
4108 05:52:57.662375 8, 0x0, sum = 2
4109 05:52:57.665277 9, 0x0, sum = 3
4110 05:52:57.665359 10, 0x0, sum = 4
4111 05:52:57.665425 best_step = 8
4112 05:52:57.665485
4113 05:52:57.669157 ==
4114 05:52:57.669237 Dram Type= 6, Freq= 0, CH_0, rank 1
4115 05:52:57.675425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4116 05:52:57.675506 ==
4117 05:52:57.675570 RX Vref Scan: 0
4118 05:52:57.675630
4119 05:52:57.678599 RX Vref 0 -> 0, step: 1
4120 05:52:57.678680
4121 05:52:57.681918 RX Delay -195 -> 252, step: 8
4122 05:52:57.688495 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4123 05:52:57.692216 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4124 05:52:57.695484 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4125 05:52:57.698797 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4126 05:52:57.702259 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4127 05:52:57.708400 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4128 05:52:57.712079 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4129 05:52:57.715347 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4130 05:52:57.718631 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4131 05:52:57.724926 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4132 05:52:57.728456 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4133 05:52:57.731640 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4134 05:52:57.734946 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4135 05:52:57.741755 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4136 05:52:57.745266 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4137 05:52:57.748214 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4138 05:52:57.748317 ==
4139 05:52:57.751263 Dram Type= 6, Freq= 0, CH_0, rank 1
4140 05:52:57.754654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4141 05:52:57.754763 ==
4142 05:52:57.758079 DQS Delay:
4143 05:52:57.758183 DQS0 = 0, DQS1 = 0
4144 05:52:57.761263 DQM Delay:
4145 05:52:57.761336 DQM0 = 41, DQM1 = 33
4146 05:52:57.761397 DQ Delay:
4147 05:52:57.764826 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4148 05:52:57.768097 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4149 05:52:57.771243 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4150 05:52:57.774902 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4151 05:52:57.774985
4152 05:52:57.775048
4153 05:52:57.784559 [DQSOSCAuto] RK1, (LSB)MR18= 0x6363, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4154 05:52:57.787709 CH0 RK1: MR19=808, MR18=6363
4155 05:52:57.794204 CH0_RK1: MR19=0x808, MR18=0x6363, DQSOSC=391, MR23=63, INC=171, DEC=114
4156 05:52:57.797431 [RxdqsGatingPostProcess] freq 600
4157 05:52:57.800692 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4158 05:52:57.804447 Pre-setting of DQS Precalculation
4159 05:52:57.811066 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4160 05:52:57.811142 ==
4161 05:52:57.814180 Dram Type= 6, Freq= 0, CH_1, rank 0
4162 05:52:57.817663 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4163 05:52:57.817763 ==
4164 05:52:57.823954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4165 05:52:57.827090 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4166 05:52:57.831262 [CA 0] Center 35 (5~66) winsize 62
4167 05:52:57.834678 [CA 1] Center 35 (4~66) winsize 63
4168 05:52:57.837824 [CA 2] Center 33 (3~64) winsize 62
4169 05:52:57.841461 [CA 3] Center 33 (3~64) winsize 62
4170 05:52:57.844740 [CA 4] Center 33 (2~64) winsize 63
4171 05:52:57.848282 [CA 5] Center 33 (2~64) winsize 63
4172 05:52:57.848383
4173 05:52:57.851111 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4174 05:52:57.851212
4175 05:52:57.854852 [CATrainingPosCal] consider 1 rank data
4176 05:52:57.857842 u2DelayCellTimex100 = 270/100 ps
4177 05:52:57.861303 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4178 05:52:57.867843 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4179 05:52:57.871085 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4180 05:52:57.874579 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4181 05:52:57.877805 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4182 05:52:57.880806 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4183 05:52:57.880881
4184 05:52:57.884182 CA PerBit enable=1, Macro0, CA PI delay=33
4185 05:52:57.884287
4186 05:52:57.887777 [CBTSetCACLKResult] CA Dly = 33
4187 05:52:57.891219 CS Dly: 4 (0~35)
4188 05:52:57.891316 ==
4189 05:52:57.894654 Dram Type= 6, Freq= 0, CH_1, rank 1
4190 05:52:57.897469 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4191 05:52:57.897544 ==
4192 05:52:57.903918 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4193 05:52:57.907501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4194 05:52:57.911555 [CA 0] Center 35 (5~66) winsize 62
4195 05:52:57.914871 [CA 1] Center 34 (4~65) winsize 62
4196 05:52:57.918041 [CA 2] Center 33 (3~64) winsize 62
4197 05:52:57.921570 [CA 3] Center 33 (3~64) winsize 62
4198 05:52:57.924854 [CA 4] Center 32 (2~63) winsize 62
4199 05:52:57.928319 [CA 5] Center 32 (2~63) winsize 62
4200 05:52:57.928420
4201 05:52:57.931479 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4202 05:52:57.931576
4203 05:52:57.934987 [CATrainingPosCal] consider 2 rank data
4204 05:52:57.937759 u2DelayCellTimex100 = 270/100 ps
4205 05:52:57.941297 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4206 05:52:57.947875 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4207 05:52:57.951012 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4208 05:52:57.954662 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4209 05:52:57.957797 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4210 05:52:57.961085 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4211 05:52:57.961159
4212 05:52:57.964351 CA PerBit enable=1, Macro0, CA PI delay=32
4213 05:52:57.964450
4214 05:52:57.967428 [CBTSetCACLKResult] CA Dly = 32
4215 05:52:57.970912 CS Dly: 4 (0~35)
4216 05:52:57.971010
4217 05:52:57.974138 ----->DramcWriteLeveling(PI) begin...
4218 05:52:57.974237 ==
4219 05:52:57.977783 Dram Type= 6, Freq= 0, CH_1, rank 0
4220 05:52:57.980755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4221 05:52:57.980832 ==
4222 05:52:57.984303 Write leveling (Byte 0): 30 => 30
4223 05:52:57.987642 Write leveling (Byte 1): 30 => 30
4224 05:52:57.990677 DramcWriteLeveling(PI) end<-----
4225 05:52:57.990752
4226 05:52:57.990843 ==
4227 05:52:57.993818 Dram Type= 6, Freq= 0, CH_1, rank 0
4228 05:52:57.997181 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4229 05:52:57.997261 ==
4230 05:52:58.000832 [Gating] SW mode calibration
4231 05:52:58.007550 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4232 05:52:58.013800 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4233 05:52:58.017175 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 05:52:58.020848 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 0)
4235 05:52:58.027124 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4236 05:52:58.030582 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4237 05:52:58.033750 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 05:52:58.041193 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 05:52:58.044055 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 05:52:58.046937 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 05:52:58.054083 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 05:52:58.056981 0 6 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4243 05:52:58.060329 0 6 8 | B1->B0 | 3131 4040 | 0 0 | (0 0) (0 0)
4244 05:52:58.066984 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 05:52:58.070244 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 05:52:58.073701 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 05:52:58.080468 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 05:52:58.083367 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 05:52:58.087022 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 05:52:58.093889 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 05:52:58.096638 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4252 05:52:58.099832 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 05:52:58.106706 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 05:52:58.110070 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 05:52:58.113526 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 05:52:58.119884 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 05:52:58.123314 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 05:52:58.126274 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 05:52:58.133181 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 05:52:58.136384 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 05:52:58.139588 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 05:52:58.146186 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 05:52:58.149693 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 05:52:58.152856 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 05:52:58.159304 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 05:52:58.162735 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 05:52:58.165903 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4268 05:52:58.169327 Total UI for P1: 0, mck2ui 16
4269 05:52:58.172477 best dqsien dly found for B0: ( 0, 9, 6)
4270 05:52:58.175912 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 05:52:58.179108 Total UI for P1: 0, mck2ui 16
4272 05:52:58.182686 best dqsien dly found for B1: ( 0, 9, 8)
4273 05:52:58.186030 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4274 05:52:58.192427 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4275 05:52:58.192540
4276 05:52:58.195659 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4277 05:52:58.198885 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4278 05:52:58.202198 [Gating] SW calibration Done
4279 05:52:58.202279 ==
4280 05:52:58.205879 Dram Type= 6, Freq= 0, CH_1, rank 0
4281 05:52:58.209127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4282 05:52:58.209208 ==
4283 05:52:58.212250 RX Vref Scan: 0
4284 05:52:58.212330
4285 05:52:58.212393 RX Vref 0 -> 0, step: 1
4286 05:52:58.212453
4287 05:52:58.215830 RX Delay -230 -> 252, step: 16
4288 05:52:58.218790 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4289 05:52:58.225612 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4290 05:52:58.228889 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4291 05:52:58.232511 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4292 05:52:58.235643 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4293 05:52:58.241913 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4294 05:52:58.245314 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4295 05:52:58.248689 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4296 05:52:58.251664 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4297 05:52:58.255409 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4298 05:52:58.261786 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4299 05:52:58.265024 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4300 05:52:58.268626 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4301 05:52:58.272041 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4302 05:52:58.278444 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4303 05:52:58.281781 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4304 05:52:58.281858 ==
4305 05:52:58.285042 Dram Type= 6, Freq= 0, CH_1, rank 0
4306 05:52:58.288474 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4307 05:52:58.288571 ==
4308 05:52:58.291579 DQS Delay:
4309 05:52:58.291651 DQS0 = 0, DQS1 = 0
4310 05:52:58.295003 DQM Delay:
4311 05:52:58.295079 DQM0 = 39, DQM1 = 32
4312 05:52:58.295138 DQ Delay:
4313 05:52:58.297989 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4314 05:52:58.301737 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4315 05:52:58.304869 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4316 05:52:58.308085 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4317 05:52:58.308181
4318 05:52:58.308272
4319 05:52:58.308357 ==
4320 05:52:58.311749 Dram Type= 6, Freq= 0, CH_1, rank 0
4321 05:52:58.318248 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4322 05:52:58.318323 ==
4323 05:52:58.318391
4324 05:52:58.318449
4325 05:52:58.318506 TX Vref Scan disable
4326 05:52:58.321952 == TX Byte 0 ==
4327 05:52:58.325246 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4328 05:52:58.332238 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4329 05:52:58.332339 == TX Byte 1 ==
4330 05:52:58.335026 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4331 05:52:58.341673 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4332 05:52:58.341747 ==
4333 05:52:58.345018 Dram Type= 6, Freq= 0, CH_1, rank 0
4334 05:52:58.348325 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4335 05:52:58.348425 ==
4336 05:52:58.348514
4337 05:52:58.348602
4338 05:52:58.351890 TX Vref Scan disable
4339 05:52:58.354857 == TX Byte 0 ==
4340 05:52:58.358497 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4341 05:52:58.361692 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4342 05:52:58.365096 == TX Byte 1 ==
4343 05:52:58.368343 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4344 05:52:58.371687 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4345 05:52:58.371793
4346 05:52:58.371882 [DATLAT]
4347 05:52:58.374640 Freq=600, CH1 RK0
4348 05:52:58.374737
4349 05:52:58.378117 DATLAT Default: 0x9
4350 05:52:58.378207 0, 0xFFFF, sum = 0
4351 05:52:58.381292 1, 0xFFFF, sum = 0
4352 05:52:58.381367 2, 0xFFFF, sum = 0
4353 05:52:58.384731 3, 0xFFFF, sum = 0
4354 05:52:58.384817 4, 0xFFFF, sum = 0
4355 05:52:58.388179 5, 0xFFFF, sum = 0
4356 05:52:58.388278 6, 0xFFFF, sum = 0
4357 05:52:58.391121 7, 0x0, sum = 1
4358 05:52:58.391220 8, 0x0, sum = 2
4359 05:52:58.394676 9, 0x0, sum = 3
4360 05:52:58.394775 10, 0x0, sum = 4
4361 05:52:58.394877 best_step = 8
4362 05:52:58.394963
4363 05:52:58.397969 ==
4364 05:52:58.401147 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 05:52:58.404840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4366 05:52:58.404926 ==
4367 05:52:58.404988 RX Vref Scan: 1
4368 05:52:58.405046
4369 05:52:58.407789 RX Vref 0 -> 0, step: 1
4370 05:52:58.407884
4371 05:52:58.411142 RX Delay -195 -> 252, step: 8
4372 05:52:58.411239
4373 05:52:58.414271 Set Vref, RX VrefLevel [Byte0]: 55
4374 05:52:58.418120 [Byte1]: 49
4375 05:52:58.418226
4376 05:52:58.420948 Final RX Vref Byte 0 = 55 to rank0
4377 05:52:58.424628 Final RX Vref Byte 1 = 49 to rank0
4378 05:52:58.427495 Final RX Vref Byte 0 = 55 to rank1
4379 05:52:58.430764 Final RX Vref Byte 1 = 49 to rank1==
4380 05:52:58.434283 Dram Type= 6, Freq= 0, CH_1, rank 0
4381 05:52:58.437480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4382 05:52:58.441072 ==
4383 05:52:58.441153 DQS Delay:
4384 05:52:58.441215 DQS0 = 0, DQS1 = 0
4385 05:52:58.444301 DQM Delay:
4386 05:52:58.444379 DQM0 = 37, DQM1 = 30
4387 05:52:58.447317 DQ Delay:
4388 05:52:58.450754 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4389 05:52:58.450835 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4390 05:52:58.454071 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =24
4391 05:52:58.460667 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4392 05:52:58.460787
4393 05:52:58.460851
4394 05:52:58.467505 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e6e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4395 05:52:58.470804 CH1 RK0: MR19=808, MR18=6E6E
4396 05:52:58.477355 CH1_RK0: MR19=0x808, MR18=0x6E6E, DQSOSC=389, MR23=63, INC=173, DEC=115
4397 05:52:58.477437
4398 05:52:58.480492 ----->DramcWriteLeveling(PI) begin...
4399 05:52:58.480573 ==
4400 05:52:58.484143 Dram Type= 6, Freq= 0, CH_1, rank 1
4401 05:52:58.487353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4402 05:52:58.487435 ==
4403 05:52:58.490243 Write leveling (Byte 0): 29 => 29
4404 05:52:58.493525 Write leveling (Byte 1): 29 => 29
4405 05:52:58.497204 DramcWriteLeveling(PI) end<-----
4406 05:52:58.497284
4407 05:52:58.497347 ==
4408 05:52:58.500329 Dram Type= 6, Freq= 0, CH_1, rank 1
4409 05:52:58.503825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4410 05:52:58.503906 ==
4411 05:52:58.506949 [Gating] SW mode calibration
4412 05:52:58.513548 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4413 05:52:58.520224 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4414 05:52:58.523296 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 05:52:58.530139 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4416 05:52:58.533721 0 5 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4417 05:52:58.536661 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 05:52:58.543571 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 05:52:58.547228 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 05:52:58.550233 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 05:52:58.556500 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 05:52:58.560009 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 05:52:58.563272 0 6 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
4424 05:52:58.569913 0 6 8 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
4425 05:52:58.572724 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 05:52:58.576295 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 05:52:58.582842 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 05:52:58.586217 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 05:52:58.589763 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 05:52:58.596222 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 05:52:58.599638 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 05:52:58.602595 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 05:52:58.609324 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 05:52:58.612674 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 05:52:58.615807 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 05:52:58.622489 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 05:52:58.625500 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 05:52:58.629275 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 05:52:58.635396 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 05:52:58.638952 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 05:52:58.642514 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 05:52:58.649191 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 05:52:58.652516 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 05:52:58.655677 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 05:52:58.659296 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 05:52:58.665508 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4447 05:52:58.669277 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4448 05:52:58.672112 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4449 05:52:58.678734 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 05:52:58.682065 Total UI for P1: 0, mck2ui 16
4451 05:52:58.685302 best dqsien dly found for B0: ( 0, 9, 4)
4452 05:52:58.688616 Total UI for P1: 0, mck2ui 16
4453 05:52:58.692149 best dqsien dly found for B1: ( 0, 9, 10)
4454 05:52:58.695186 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4455 05:52:58.698810 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4456 05:52:58.698886
4457 05:52:58.702158 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4458 05:52:58.705495 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4459 05:52:58.708419 [Gating] SW calibration Done
4460 05:52:58.708491 ==
4461 05:52:58.711648 Dram Type= 6, Freq= 0, CH_1, rank 1
4462 05:52:58.715138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4463 05:52:58.715210 ==
4464 05:52:58.718460 RX Vref Scan: 0
4465 05:52:58.718556
4466 05:52:58.718643 RX Vref 0 -> 0, step: 1
4467 05:52:58.721950
4468 05:52:58.722049 RX Delay -230 -> 252, step: 16
4469 05:52:58.728624 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4470 05:52:58.731544 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4471 05:52:58.735262 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4472 05:52:58.738508 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4473 05:52:58.745424 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4474 05:52:58.748503 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4475 05:52:58.751858 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4476 05:52:58.754829 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4477 05:52:58.758206 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4478 05:52:58.765212 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4479 05:52:58.768493 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4480 05:52:58.771222 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4481 05:52:58.774496 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4482 05:52:58.781400 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4483 05:52:58.784879 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4484 05:52:58.788156 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4485 05:52:58.788248 ==
4486 05:52:58.791281 Dram Type= 6, Freq= 0, CH_1, rank 1
4487 05:52:58.797956 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4488 05:52:58.798044 ==
4489 05:52:58.798110 DQS Delay:
4490 05:52:58.798170 DQS0 = 0, DQS1 = 0
4491 05:52:58.800929 DQM Delay:
4492 05:52:58.801041 DQM0 = 42, DQM1 = 35
4493 05:52:58.804288 DQ Delay:
4494 05:52:58.807753 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4495 05:52:58.811052 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4496 05:52:58.811165 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4497 05:52:58.818137 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4498 05:52:58.818249
4499 05:52:58.818364
4500 05:52:58.818467 ==
4501 05:52:58.821230 Dram Type= 6, Freq= 0, CH_1, rank 1
4502 05:52:58.824417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4503 05:52:58.824535 ==
4504 05:52:58.824634
4505 05:52:58.824771
4506 05:52:58.827382 TX Vref Scan disable
4507 05:52:58.827484 == TX Byte 0 ==
4508 05:52:58.834216 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4509 05:52:58.837675 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4510 05:52:58.837853 == TX Byte 1 ==
4511 05:52:58.843964 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4512 05:52:58.847426 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4513 05:52:58.847538 ==
4514 05:52:58.850895 Dram Type= 6, Freq= 0, CH_1, rank 1
4515 05:52:58.854198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4516 05:52:58.854277 ==
4517 05:52:58.854342
4518 05:52:58.857591
4519 05:52:58.857680 TX Vref Scan disable
4520 05:52:58.860684 == TX Byte 0 ==
4521 05:52:58.864017 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4522 05:52:58.870773 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4523 05:52:58.870875 == TX Byte 1 ==
4524 05:52:58.873740 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4525 05:52:58.880339 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4526 05:52:58.880461
4527 05:52:58.880562 [DATLAT]
4528 05:52:58.880656 Freq=600, CH1 RK1
4529 05:52:58.880772
4530 05:52:58.884011 DATLAT Default: 0x8
4531 05:52:58.884133 0, 0xFFFF, sum = 0
4532 05:52:58.886952 1, 0xFFFF, sum = 0
4533 05:52:58.890657 2, 0xFFFF, sum = 0
4534 05:52:58.890785 3, 0xFFFF, sum = 0
4535 05:52:58.893598 4, 0xFFFF, sum = 0
4536 05:52:58.893720 5, 0xFFFF, sum = 0
4537 05:52:58.897364 6, 0xFFFF, sum = 0
4538 05:52:58.897472 7, 0x0, sum = 1
4539 05:52:58.900293 8, 0x0, sum = 2
4540 05:52:58.900390 9, 0x0, sum = 3
4541 05:52:58.900479 10, 0x0, sum = 4
4542 05:52:58.903388 best_step = 8
4543 05:52:58.903481
4544 05:52:58.903567 ==
4545 05:52:58.906683 Dram Type= 6, Freq= 0, CH_1, rank 1
4546 05:52:58.910106 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4547 05:52:58.910184 ==
4548 05:52:58.913322 RX Vref Scan: 0
4549 05:52:58.913395
4550 05:52:58.913456 RX Vref 0 -> 0, step: 1
4551 05:52:58.916515
4552 05:52:58.916612 RX Delay -195 -> 252, step: 8
4553 05:52:58.924165 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4554 05:52:58.927485 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4555 05:52:58.931303 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4556 05:52:58.934008 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4557 05:52:58.940914 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4558 05:52:58.944101 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4559 05:52:58.947215 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4560 05:52:58.950830 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4561 05:52:58.957423 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4562 05:52:58.960931 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4563 05:52:58.963990 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4564 05:52:58.967382 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4565 05:52:58.970543 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4566 05:52:58.977462 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4567 05:52:58.980271 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4568 05:52:58.983700 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4569 05:52:58.983773 ==
4570 05:52:58.987368 Dram Type= 6, Freq= 0, CH_1, rank 1
4571 05:52:58.993897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4572 05:52:58.993974 ==
4573 05:52:58.994038 DQS Delay:
4574 05:52:58.997347 DQS0 = 0, DQS1 = 0
4575 05:52:58.997441 DQM Delay:
4576 05:52:58.997530 DQM0 = 37, DQM1 = 30
4577 05:52:59.000478 DQ Delay:
4578 05:52:59.003640 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4579 05:52:59.007060 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4580 05:52:59.010482 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4581 05:52:59.013706 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4582 05:52:59.013804
4583 05:52:59.013904
4584 05:52:59.020597 [DQSOSCAuto] RK1, (LSB)MR18= 0x5858, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4585 05:52:59.023678 CH1 RK1: MR19=808, MR18=5858
4586 05:52:59.030094 CH1_RK1: MR19=0x808, MR18=0x5858, DQSOSC=393, MR23=63, INC=169, DEC=113
4587 05:52:59.033416 [RxdqsGatingPostProcess] freq 600
4588 05:52:59.036636 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4589 05:52:59.040098 Pre-setting of DQS Precalculation
4590 05:52:59.046562 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4591 05:52:59.053233 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4592 05:52:59.059958 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4593 05:52:59.060060
4594 05:52:59.060149
4595 05:52:59.063201 [Calibration Summary] 1200 Mbps
4596 05:52:59.063298 CH 0, Rank 0
4597 05:52:59.066567 SW Impedance : PASS
4598 05:52:59.070187 DUTY Scan : NO K
4599 05:52:59.070259 ZQ Calibration : PASS
4600 05:52:59.073241 Jitter Meter : NO K
4601 05:52:59.076628 CBT Training : PASS
4602 05:52:59.076771 Write leveling : PASS
4603 05:52:59.080094 RX DQS gating : PASS
4604 05:52:59.083417 RX DQ/DQS(RDDQC) : PASS
4605 05:52:59.083490 TX DQ/DQS : PASS
4606 05:52:59.086526 RX DATLAT : PASS
4607 05:52:59.089661 RX DQ/DQS(Engine): PASS
4608 05:52:59.089766 TX OE : NO K
4609 05:52:59.089854 All Pass.
4610 05:52:59.093060
4611 05:52:59.093154 CH 0, Rank 1
4612 05:52:59.096640 SW Impedance : PASS
4613 05:52:59.096751 DUTY Scan : NO K
4614 05:52:59.100012 ZQ Calibration : PASS
4615 05:52:59.100108 Jitter Meter : NO K
4616 05:52:59.102969 CBT Training : PASS
4617 05:52:59.106507 Write leveling : PASS
4618 05:52:59.106612 RX DQS gating : PASS
4619 05:52:59.109868 RX DQ/DQS(RDDQC) : PASS
4620 05:52:59.112732 TX DQ/DQS : PASS
4621 05:52:59.112804 RX DATLAT : PASS
4622 05:52:59.116615 RX DQ/DQS(Engine): PASS
4623 05:52:59.119576 TX OE : NO K
4624 05:52:59.119673 All Pass.
4625 05:52:59.119771
4626 05:52:59.119856 CH 1, Rank 0
4627 05:52:59.123170 SW Impedance : PASS
4628 05:52:59.126429 DUTY Scan : NO K
4629 05:52:59.126528 ZQ Calibration : PASS
4630 05:52:59.129426 Jitter Meter : NO K
4631 05:52:59.132598 CBT Training : PASS
4632 05:52:59.132695 Write leveling : PASS
4633 05:52:59.136007 RX DQS gating : PASS
4634 05:52:59.139249 RX DQ/DQS(RDDQC) : PASS
4635 05:52:59.139346 TX DQ/DQS : PASS
4636 05:52:59.142867 RX DATLAT : PASS
4637 05:52:59.145974 RX DQ/DQS(Engine): PASS
4638 05:52:59.146071 TX OE : NO K
4639 05:52:59.149188 All Pass.
4640 05:52:59.149271
4641 05:52:59.149337 CH 1, Rank 1
4642 05:52:59.152633 SW Impedance : PASS
4643 05:52:59.152722 DUTY Scan : NO K
4644 05:52:59.156396 ZQ Calibration : PASS
4645 05:52:59.159335 Jitter Meter : NO K
4646 05:52:59.159413 CBT Training : PASS
4647 05:52:59.162392 Write leveling : PASS
4648 05:52:59.165707 RX DQS gating : PASS
4649 05:52:59.165789 RX DQ/DQS(RDDQC) : PASS
4650 05:52:59.168926 TX DQ/DQS : PASS
4651 05:52:59.169006 RX DATLAT : PASS
4652 05:52:59.172394 RX DQ/DQS(Engine): PASS
4653 05:52:59.176005 TX OE : NO K
4654 05:52:59.176087 All Pass.
4655 05:52:59.176151
4656 05:52:59.179070 DramC Write-DBI off
4657 05:52:59.179166 PER_BANK_REFRESH: Hybrid Mode
4658 05:52:59.182240 TX_TRACKING: ON
4659 05:52:59.192297 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4660 05:52:59.195700 [FAST_K] Save calibration result to emmc
4661 05:52:59.198956 dramc_set_vcore_voltage set vcore to 662500
4662 05:52:59.199055 Read voltage for 933, 3
4663 05:52:59.202459 Vio18 = 0
4664 05:52:59.202555 Vcore = 662500
4665 05:52:59.202642 Vdram = 0
4666 05:52:59.205638 Vddq = 0
4667 05:52:59.205705 Vmddr = 0
4668 05:52:59.212336 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4669 05:52:59.215179 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4670 05:52:59.218451 MEM_TYPE=3, freq_sel=17
4671 05:52:59.221881 sv_algorithm_assistance_LP4_1600
4672 05:52:59.225085 ============ PULL DRAM RESETB DOWN ============
4673 05:52:59.228397 ========== PULL DRAM RESETB DOWN end =========
4674 05:52:59.235465 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4675 05:52:59.238398 ===================================
4676 05:52:59.238501 LPDDR4 DRAM CONFIGURATION
4677 05:52:59.241666 ===================================
4678 05:52:59.245438 EX_ROW_EN[0] = 0x0
4679 05:52:59.248710 EX_ROW_EN[1] = 0x0
4680 05:52:59.248819 LP4Y_EN = 0x0
4681 05:52:59.251836 WORK_FSP = 0x0
4682 05:52:59.251908 WL = 0x3
4683 05:52:59.255503 RL = 0x3
4684 05:52:59.255607 BL = 0x2
4685 05:52:59.258389 RPST = 0x0
4686 05:52:59.258458 RD_PRE = 0x0
4687 05:52:59.261822 WR_PRE = 0x1
4688 05:52:59.261917 WR_PST = 0x0
4689 05:52:59.264876 DBI_WR = 0x0
4690 05:52:59.264975 DBI_RD = 0x0
4691 05:52:59.268667 OTF = 0x1
4692 05:52:59.271531 ===================================
4693 05:52:59.274973 ===================================
4694 05:52:59.275049 ANA top config
4695 05:52:59.278308 ===================================
4696 05:52:59.281516 DLL_ASYNC_EN = 0
4697 05:52:59.285460 ALL_SLAVE_EN = 1
4698 05:52:59.288412 NEW_RANK_MODE = 1
4699 05:52:59.288511 DLL_IDLE_MODE = 1
4700 05:52:59.291336 LP45_APHY_COMB_EN = 1
4701 05:52:59.294628 TX_ODT_DIS = 1
4702 05:52:59.297733 NEW_8X_MODE = 1
4703 05:52:59.301151 ===================================
4704 05:52:59.304478 ===================================
4705 05:52:59.308447 data_rate = 1866
4706 05:52:59.308546 CKR = 1
4707 05:52:59.311257 DQ_P2S_RATIO = 8
4708 05:52:59.314525 ===================================
4709 05:52:59.317741 CA_P2S_RATIO = 8
4710 05:52:59.321326 DQ_CA_OPEN = 0
4711 05:52:59.324616 DQ_SEMI_OPEN = 0
4712 05:52:59.327727 CA_SEMI_OPEN = 0
4713 05:52:59.327835 CA_FULL_RATE = 0
4714 05:52:59.331060 DQ_CKDIV4_EN = 1
4715 05:52:59.334683 CA_CKDIV4_EN = 1
4716 05:52:59.337948 CA_PREDIV_EN = 0
4717 05:52:59.341038 PH8_DLY = 0
4718 05:52:59.344229 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4719 05:52:59.344329 DQ_AAMCK_DIV = 4
4720 05:52:59.348130 CA_AAMCK_DIV = 4
4721 05:52:59.350934 CA_ADMCK_DIV = 4
4722 05:52:59.354722 DQ_TRACK_CA_EN = 0
4723 05:52:59.357586 CA_PICK = 933
4724 05:52:59.360916 CA_MCKIO = 933
4725 05:52:59.361015 MCKIO_SEMI = 0
4726 05:52:59.364144 PLL_FREQ = 3732
4727 05:52:59.367658 DQ_UI_PI_RATIO = 32
4728 05:52:59.371468 CA_UI_PI_RATIO = 0
4729 05:52:59.374152 ===================================
4730 05:52:59.377483 ===================================
4731 05:52:59.380632 memory_type:LPDDR4
4732 05:52:59.380765 GP_NUM : 10
4733 05:52:59.383949 SRAM_EN : 1
4734 05:52:59.387107 MD32_EN : 0
4735 05:52:59.390829 ===================================
4736 05:52:59.390938 [ANA_INIT] >>>>>>>>>>>>>>
4737 05:52:59.393973 <<<<<< [CONFIGURE PHASE]: ANA_TX
4738 05:52:59.397131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4739 05:52:59.400855 ===================================
4740 05:52:59.403786 data_rate = 1866,PCW = 0X8f00
4741 05:52:59.407062 ===================================
4742 05:52:59.410636 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4743 05:52:59.416514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4744 05:52:59.423440 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4745 05:52:59.426435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4746 05:52:59.429981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4747 05:52:59.433518 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4748 05:52:59.436864 [ANA_INIT] flow start
4749 05:52:59.436963 [ANA_INIT] PLL >>>>>>>>
4750 05:52:59.440085 [ANA_INIT] PLL <<<<<<<<
4751 05:52:59.443162 [ANA_INIT] MIDPI >>>>>>>>
4752 05:52:59.443260 [ANA_INIT] MIDPI <<<<<<<<
4753 05:52:59.446469 [ANA_INIT] DLL >>>>>>>>
4754 05:52:59.450210 [ANA_INIT] flow end
4755 05:52:59.453505 ============ LP4 DIFF to SE enter ============
4756 05:52:59.456638 ============ LP4 DIFF to SE exit ============
4757 05:52:59.460029 [ANA_INIT] <<<<<<<<<<<<<
4758 05:52:59.462862 [Flow] Enable top DCM control >>>>>
4759 05:52:59.466317 [Flow] Enable top DCM control <<<<<
4760 05:52:59.469470 Enable DLL master slave shuffle
4761 05:52:59.472957 ==============================================================
4762 05:52:59.476331 Gating Mode config
4763 05:52:59.482844 ==============================================================
4764 05:52:59.482944 Config description:
4765 05:52:59.492595 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4766 05:52:59.499269 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4767 05:52:59.506105 SELPH_MODE 0: By rank 1: By Phase
4768 05:52:59.509268 ==============================================================
4769 05:52:59.512523 GAT_TRACK_EN = 1
4770 05:52:59.515856 RX_GATING_MODE = 2
4771 05:52:59.519112 RX_GATING_TRACK_MODE = 2
4772 05:52:59.522635 SELPH_MODE = 1
4773 05:52:59.525976 PICG_EARLY_EN = 1
4774 05:52:59.529320 VALID_LAT_VALUE = 1
4775 05:52:59.532291 ==============================================================
4776 05:52:59.536047 Enter into Gating configuration >>>>
4777 05:52:59.542059 Exit from Gating configuration <<<<
4778 05:52:59.542133 Enter into DVFS_PRE_config >>>>>
4779 05:52:59.555872 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4780 05:52:59.559053 Exit from DVFS_PRE_config <<<<<
4781 05:52:59.561942 Enter into PICG configuration >>>>
4782 05:52:59.565308 Exit from PICG configuration <<<<
4783 05:52:59.565388 [RX_INPUT] configuration >>>>>
4784 05:52:59.568790 [RX_INPUT] configuration <<<<<
4785 05:52:59.575377 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4786 05:52:59.582122 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4787 05:52:59.585471 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4788 05:52:59.591616 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4789 05:52:59.598882 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4790 05:52:59.605110 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4791 05:52:59.608336 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4792 05:52:59.611586 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4793 05:52:59.618022 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4794 05:52:59.621512 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4795 05:52:59.624594 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4796 05:52:59.631300 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4797 05:52:59.634911 ===================================
4798 05:52:59.635014 LPDDR4 DRAM CONFIGURATION
4799 05:52:59.638046 ===================================
4800 05:52:59.641545 EX_ROW_EN[0] = 0x0
4801 05:52:59.641632 EX_ROW_EN[1] = 0x0
4802 05:52:59.645067 LP4Y_EN = 0x0
4803 05:52:59.647843 WORK_FSP = 0x0
4804 05:52:59.647917 WL = 0x3
4805 05:52:59.651361 RL = 0x3
4806 05:52:59.651463 BL = 0x2
4807 05:52:59.654481 RPST = 0x0
4808 05:52:59.654583 RD_PRE = 0x0
4809 05:52:59.657604 WR_PRE = 0x1
4810 05:52:59.657700 WR_PST = 0x0
4811 05:52:59.661333 DBI_WR = 0x0
4812 05:52:59.661414 DBI_RD = 0x0
4813 05:52:59.664214 OTF = 0x1
4814 05:52:59.667389 ===================================
4815 05:52:59.670830 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4816 05:52:59.674098 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4817 05:52:59.681062 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4818 05:52:59.684243 ===================================
4819 05:52:59.684348 LPDDR4 DRAM CONFIGURATION
4820 05:52:59.687366 ===================================
4821 05:52:59.690731 EX_ROW_EN[0] = 0x10
4822 05:52:59.690823 EX_ROW_EN[1] = 0x0
4823 05:52:59.694016 LP4Y_EN = 0x0
4824 05:52:59.697673 WORK_FSP = 0x0
4825 05:52:59.697772 WL = 0x3
4826 05:52:59.700696 RL = 0x3
4827 05:52:59.700812 BL = 0x2
4828 05:52:59.703941 RPST = 0x0
4829 05:52:59.704033 RD_PRE = 0x0
4830 05:52:59.707425 WR_PRE = 0x1
4831 05:52:59.707523 WR_PST = 0x0
4832 05:52:59.710569 DBI_WR = 0x0
4833 05:52:59.710639 DBI_RD = 0x0
4834 05:52:59.713829 OTF = 0x1
4835 05:52:59.717260 ===================================
4836 05:52:59.723534 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4837 05:52:59.726975 nWR fixed to 30
4838 05:52:59.727075 [ModeRegInit_LP4] CH0 RK0
4839 05:52:59.730368 [ModeRegInit_LP4] CH0 RK1
4840 05:52:59.733333 [ModeRegInit_LP4] CH1 RK0
4841 05:52:59.736702 [ModeRegInit_LP4] CH1 RK1
4842 05:52:59.736818 match AC timing 8
4843 05:52:59.740253 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4844 05:52:59.746578 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4845 05:52:59.750448 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4846 05:52:59.756987 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4847 05:52:59.759837 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4848 05:52:59.759934 ==
4849 05:52:59.763564 Dram Type= 6, Freq= 0, CH_0, rank 0
4850 05:52:59.766898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4851 05:52:59.767002 ==
4852 05:52:59.773264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4853 05:52:59.779833 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4854 05:52:59.783089 [CA 0] Center 38 (8~69) winsize 62
4855 05:52:59.786253 [CA 1] Center 38 (8~69) winsize 62
4856 05:52:59.789535 [CA 2] Center 36 (6~67) winsize 62
4857 05:52:59.793095 [CA 3] Center 36 (5~67) winsize 63
4858 05:52:59.796330 [CA 4] Center 34 (4~65) winsize 62
4859 05:52:59.799530 [CA 5] Center 34 (4~65) winsize 62
4860 05:52:59.799603
4861 05:52:59.803093 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4862 05:52:59.803197
4863 05:52:59.806294 [CATrainingPosCal] consider 1 rank data
4864 05:52:59.809952 u2DelayCellTimex100 = 270/100 ps
4865 05:52:59.813130 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4866 05:52:59.816311 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4867 05:52:59.819392 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4868 05:52:59.822873 CA3 delay=36 (5~67),Diff = 2 PI (12 cell)
4869 05:52:59.826086 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4870 05:52:59.829460 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4871 05:52:59.829540
4872 05:52:59.836093 CA PerBit enable=1, Macro0, CA PI delay=34
4873 05:52:59.836172
4874 05:52:59.839758 [CBTSetCACLKResult] CA Dly = 34
4875 05:52:59.839866 CS Dly: 7 (0~38)
4876 05:52:59.839933 ==
4877 05:52:59.842734 Dram Type= 6, Freq= 0, CH_0, rank 1
4878 05:52:59.845901 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4879 05:52:59.845998 ==
4880 05:52:59.852381 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4881 05:52:59.859080 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4882 05:52:59.862407 [CA 0] Center 38 (8~69) winsize 62
4883 05:52:59.865837 [CA 1] Center 38 (8~69) winsize 62
4884 05:52:59.868946 [CA 2] Center 35 (5~66) winsize 62
4885 05:52:59.872490 [CA 3] Center 35 (5~66) winsize 62
4886 05:52:59.875627 [CA 4] Center 34 (3~65) winsize 63
4887 05:52:59.879291 [CA 5] Center 34 (4~65) winsize 62
4888 05:52:59.879389
4889 05:52:59.882460 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4890 05:52:59.882555
4891 05:52:59.885657 [CATrainingPosCal] consider 2 rank data
4892 05:52:59.888832 u2DelayCellTimex100 = 270/100 ps
4893 05:52:59.892162 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4894 05:52:59.895738 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4895 05:52:59.898577 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
4896 05:52:59.902337 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4897 05:52:59.908628 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4898 05:52:59.912018 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4899 05:52:59.912115
4900 05:52:59.915516 CA PerBit enable=1, Macro0, CA PI delay=34
4901 05:52:59.915612
4902 05:52:59.918752 [CBTSetCACLKResult] CA Dly = 34
4903 05:52:59.918849 CS Dly: 7 (0~39)
4904 05:52:59.918936
4905 05:52:59.922159 ----->DramcWriteLeveling(PI) begin...
4906 05:52:59.922263 ==
4907 05:52:59.925214 Dram Type= 6, Freq= 0, CH_0, rank 0
4908 05:52:59.931839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4909 05:52:59.931942 ==
4910 05:52:59.935091 Write leveling (Byte 0): 29 => 29
4911 05:52:59.938798 Write leveling (Byte 1): 28 => 28
4912 05:52:59.938898 DramcWriteLeveling(PI) end<-----
4913 05:52:59.938998
4914 05:52:59.941933 ==
4915 05:52:59.945297 Dram Type= 6, Freq= 0, CH_0, rank 0
4916 05:52:59.948277 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4917 05:52:59.948376 ==
4918 05:52:59.951807 [Gating] SW mode calibration
4919 05:52:59.958615 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4920 05:52:59.961566 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4921 05:52:59.968022 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4922 05:52:59.971586 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4923 05:52:59.974893 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4924 05:52:59.981531 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4925 05:52:59.984784 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4926 05:52:59.988037 0 10 20 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 1)
4927 05:52:59.994402 0 10 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
4928 05:52:59.997803 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4929 05:53:00.001264 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4930 05:53:00.007775 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4931 05:53:00.010992 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4932 05:53:00.014396 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4933 05:53:00.021302 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4934 05:53:00.024509 0 11 20 | B1->B0 | 2929 3030 | 0 0 | (0 0) (0 0)
4935 05:53:00.027533 0 11 24 | B1->B0 | 3535 4343 | 0 0 | (0 0) (0 0)
4936 05:53:00.034175 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4937 05:53:00.037784 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4938 05:53:00.040813 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4939 05:53:00.047482 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4940 05:53:00.050770 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4941 05:53:00.054507 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4942 05:53:00.060827 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4943 05:53:00.063841 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4944 05:53:00.067733 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 05:53:00.073733 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 05:53:00.077173 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 05:53:00.080331 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 05:53:00.087328 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 05:53:00.090498 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 05:53:00.093925 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4951 05:53:00.100642 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4952 05:53:00.103586 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4953 05:53:00.107151 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4954 05:53:00.113808 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4955 05:53:00.117472 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4956 05:53:00.120203 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4957 05:53:00.127281 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4958 05:53:00.130089 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4959 05:53:00.133348 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4960 05:53:00.140086 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4961 05:53:00.140166 Total UI for P1: 0, mck2ui 16
4962 05:53:00.146461 best dqsien dly found for B0: ( 0, 14, 22)
4963 05:53:00.146544 Total UI for P1: 0, mck2ui 16
4964 05:53:00.153132 best dqsien dly found for B1: ( 0, 14, 22)
4965 05:53:00.156542 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4966 05:53:00.159645 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
4967 05:53:00.159721
4968 05:53:00.163434 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4969 05:53:00.166404 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
4970 05:53:00.169601 [Gating] SW calibration Done
4971 05:53:00.169681 ==
4972 05:53:00.173148 Dram Type= 6, Freq= 0, CH_0, rank 0
4973 05:53:00.176222 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4974 05:53:00.176318 ==
4975 05:53:00.179570 RX Vref Scan: 0
4976 05:53:00.179649
4977 05:53:00.179712 RX Vref 0 -> 0, step: 1
4978 05:53:00.179769
4979 05:53:00.183001 RX Delay -80 -> 252, step: 8
4980 05:53:00.189458 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4981 05:53:00.192935 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4982 05:53:00.195950 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4983 05:53:00.199348 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4984 05:53:00.202742 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4985 05:53:00.205814 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4986 05:53:00.212560 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4987 05:53:00.215950 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
4988 05:53:00.219260 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4989 05:53:00.222632 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4990 05:53:00.226143 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4991 05:53:00.232360 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
4992 05:53:00.235593 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4993 05:53:00.239454 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4994 05:53:00.242493 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4995 05:53:00.245678 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4996 05:53:00.245776 ==
4997 05:53:00.248897 Dram Type= 6, Freq= 0, CH_0, rank 0
4998 05:53:00.255902 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4999 05:53:00.256005 ==
5000 05:53:00.256095 DQS Delay:
5001 05:53:00.256185 DQS0 = 0, DQS1 = 0
5002 05:53:00.259121 DQM Delay:
5003 05:53:00.259217 DQM0 = 95, DQM1 = 85
5004 05:53:00.262403 DQ Delay:
5005 05:53:00.265751 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5006 05:53:00.268739 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5007 05:53:00.272523 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5008 05:53:00.275701 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5009 05:53:00.275773
5010 05:53:00.275835
5011 05:53:00.275892 ==
5012 05:53:00.278870 Dram Type= 6, Freq= 0, CH_0, rank 0
5013 05:53:00.282512 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5014 05:53:00.282611 ==
5015 05:53:00.282700
5016 05:53:00.282785
5017 05:53:00.285596 TX Vref Scan disable
5018 05:53:00.285666 == TX Byte 0 ==
5019 05:53:00.292354 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5020 05:53:00.295443 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5021 05:53:00.295547 == TX Byte 1 ==
5022 05:53:00.302385 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5023 05:53:00.305467 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5024 05:53:00.305571 ==
5025 05:53:00.308848 Dram Type= 6, Freq= 0, CH_0, rank 0
5026 05:53:00.311980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5027 05:53:00.312078 ==
5028 05:53:00.312168
5029 05:53:00.315257
5030 05:53:00.315359 TX Vref Scan disable
5031 05:53:00.318866 == TX Byte 0 ==
5032 05:53:00.322113 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5033 05:53:00.324964 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5034 05:53:00.328603 == TX Byte 1 ==
5035 05:53:00.331824 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5036 05:53:00.335177 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5037 05:53:00.338598
5038 05:53:00.338699 [DATLAT]
5039 05:53:00.338790 Freq=933, CH0 RK0
5040 05:53:00.338877
5041 05:53:00.341564 DATLAT Default: 0xd
5042 05:53:00.341631 0, 0xFFFF, sum = 0
5043 05:53:00.345227 1, 0xFFFF, sum = 0
5044 05:53:00.345294 2, 0xFFFF, sum = 0
5045 05:53:00.348203 3, 0xFFFF, sum = 0
5046 05:53:00.351774 4, 0xFFFF, sum = 0
5047 05:53:00.351881 5, 0xFFFF, sum = 0
5048 05:53:00.355227 6, 0xFFFF, sum = 0
5049 05:53:00.355325 7, 0xFFFF, sum = 0
5050 05:53:00.358318 8, 0xFFFF, sum = 0
5051 05:53:00.358388 9, 0xFFFF, sum = 0
5052 05:53:00.361562 10, 0x0, sum = 1
5053 05:53:00.361647 11, 0x0, sum = 2
5054 05:53:00.364685 12, 0x0, sum = 3
5055 05:53:00.364830 13, 0x0, sum = 4
5056 05:53:00.364921 best_step = 11
5057 05:53:00.365016
5058 05:53:00.368180 ==
5059 05:53:00.371506 Dram Type= 6, Freq= 0, CH_0, rank 0
5060 05:53:00.374528 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5061 05:53:00.374598 ==
5062 05:53:00.374658 RX Vref Scan: 1
5063 05:53:00.374716
5064 05:53:00.378318 RX Vref 0 -> 0, step: 1
5065 05:53:00.378414
5066 05:53:00.381420 RX Delay -69 -> 252, step: 4
5067 05:53:00.381505
5068 05:53:00.384802 Set Vref, RX VrefLevel [Byte0]: 47
5069 05:53:00.387901 [Byte1]: 48
5070 05:53:00.387998
5071 05:53:00.391539 Final RX Vref Byte 0 = 47 to rank0
5072 05:53:00.394676 Final RX Vref Byte 1 = 48 to rank0
5073 05:53:00.398122 Final RX Vref Byte 0 = 47 to rank1
5074 05:53:00.401594 Final RX Vref Byte 1 = 48 to rank1==
5075 05:53:00.404449 Dram Type= 6, Freq= 0, CH_0, rank 0
5076 05:53:00.411397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5077 05:53:00.411506 ==
5078 05:53:00.411597 DQS Delay:
5079 05:53:00.411683 DQS0 = 0, DQS1 = 0
5080 05:53:00.414219 DQM Delay:
5081 05:53:00.414320 DQM0 = 97, DQM1 = 86
5082 05:53:00.417584 DQ Delay:
5083 05:53:00.421016 DQ0 =92, DQ1 =100, DQ2 =96, DQ3 =94
5084 05:53:00.424231 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5085 05:53:00.427666 DQ8 =78, DQ9 =70, DQ10 =88, DQ11 =78
5086 05:53:00.431115 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =96
5087 05:53:00.431214
5088 05:53:00.431301
5089 05:53:00.437695 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5090 05:53:00.440809 CH0 RK0: MR19=505, MR18=1D1D
5091 05:53:00.447883 CH0_RK0: MR19=0x505, MR18=0x1D1D, DQSOSC=412, MR23=63, INC=63, DEC=42
5092 05:53:00.447986
5093 05:53:00.450746 ----->DramcWriteLeveling(PI) begin...
5094 05:53:00.450821 ==
5095 05:53:00.453864 Dram Type= 6, Freq= 0, CH_0, rank 1
5096 05:53:00.457582 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5097 05:53:00.457654 ==
5098 05:53:00.460959 Write leveling (Byte 0): 28 => 28
5099 05:53:00.464191 Write leveling (Byte 1): 28 => 28
5100 05:53:00.467383 DramcWriteLeveling(PI) end<-----
5101 05:53:00.467479
5102 05:53:00.467570 ==
5103 05:53:00.470510 Dram Type= 6, Freq= 0, CH_0, rank 1
5104 05:53:00.473730 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5105 05:53:00.473836 ==
5106 05:53:00.477251 [Gating] SW mode calibration
5107 05:53:00.483628 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5108 05:53:00.490673 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5109 05:53:00.493714 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 05:53:00.500614 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 05:53:00.503689 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 05:53:00.506961 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 05:53:00.513764 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5114 05:53:00.516562 0 10 20 | B1->B0 | 3131 3030 | 0 0 | (0 1) (0 0)
5115 05:53:00.520315 0 10 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
5116 05:53:00.526671 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 05:53:00.529954 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 05:53:00.533589 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 05:53:00.540193 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 05:53:00.543059 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 05:53:00.546472 0 11 16 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
5122 05:53:00.553330 0 11 20 | B1->B0 | 2b2b 3636 | 1 1 | (0 0) (0 0)
5123 05:53:00.556362 0 11 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5124 05:53:00.559995 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 05:53:00.566507 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 05:53:00.570144 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 05:53:00.573321 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 05:53:00.579942 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 05:53:00.582652 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 05:53:00.586412 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5131 05:53:00.593128 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5132 05:53:00.596060 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 05:53:00.599709 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 05:53:00.606067 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 05:53:00.609571 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 05:53:00.612613 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 05:53:00.619360 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 05:53:00.622373 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 05:53:00.626205 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 05:53:00.632287 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 05:53:00.635898 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 05:53:00.639428 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 05:53:00.645380 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 05:53:00.649037 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 05:53:00.652416 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 05:53:00.659003 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5147 05:53:00.662051 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 05:53:00.665581 Total UI for P1: 0, mck2ui 16
5149 05:53:00.669141 best dqsien dly found for B0: ( 0, 14, 20)
5150 05:53:00.671991 Total UI for P1: 0, mck2ui 16
5151 05:53:00.675342 best dqsien dly found for B1: ( 0, 14, 20)
5152 05:53:00.678676 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5153 05:53:00.682150 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5154 05:53:00.682270
5155 05:53:00.685307 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5156 05:53:00.688742 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5157 05:53:00.692103 [Gating] SW calibration Done
5158 05:53:00.692197 ==
5159 05:53:00.695624 Dram Type= 6, Freq= 0, CH_0, rank 1
5160 05:53:00.698413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5161 05:53:00.701690 ==
5162 05:53:00.701760 RX Vref Scan: 0
5163 05:53:00.701838
5164 05:53:00.705218 RX Vref 0 -> 0, step: 1
5165 05:53:00.705302
5166 05:53:00.708371 RX Delay -80 -> 252, step: 8
5167 05:53:00.711821 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5168 05:53:00.714856 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5169 05:53:00.718509 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5170 05:53:00.721899 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5171 05:53:00.724866 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5172 05:53:00.731454 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5173 05:53:00.734748 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5174 05:53:00.738276 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5175 05:53:00.741476 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5176 05:53:00.745023 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5177 05:53:00.751431 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5178 05:53:00.754522 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5179 05:53:00.758060 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5180 05:53:00.761304 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5181 05:53:00.764799 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5182 05:53:00.767734 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5183 05:53:00.771698 ==
5184 05:53:00.774401 Dram Type= 6, Freq= 0, CH_0, rank 1
5185 05:53:00.778031 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5186 05:53:00.778119 ==
5187 05:53:00.778187 DQS Delay:
5188 05:53:00.781178 DQS0 = 0, DQS1 = 0
5189 05:53:00.781250 DQM Delay:
5190 05:53:00.784623 DQM0 = 95, DQM1 = 86
5191 05:53:00.784745 DQ Delay:
5192 05:53:00.787979 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =87
5193 05:53:00.790982 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5194 05:53:00.794270 DQ8 =71, DQ9 =71, DQ10 =87, DQ11 =79
5195 05:53:00.797966 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5196 05:53:00.798040
5197 05:53:00.798104
5198 05:53:00.798162 ==
5199 05:53:00.800909 Dram Type= 6, Freq= 0, CH_0, rank 1
5200 05:53:00.804267 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5201 05:53:00.804370 ==
5202 05:53:00.804461
5203 05:53:00.804550
5204 05:53:00.807314 TX Vref Scan disable
5205 05:53:00.810998 == TX Byte 0 ==
5206 05:53:00.814136 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5207 05:53:00.817505 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5208 05:53:00.820912 == TX Byte 1 ==
5209 05:53:00.824036 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5210 05:53:00.827606 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5211 05:53:00.827708 ==
5212 05:53:00.830943 Dram Type= 6, Freq= 0, CH_0, rank 1
5213 05:53:00.837553 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5214 05:53:00.837674 ==
5215 05:53:00.837769
5216 05:53:00.837858
5217 05:53:00.837961 TX Vref Scan disable
5218 05:53:00.841419 == TX Byte 0 ==
5219 05:53:00.844491 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5220 05:53:00.851197 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5221 05:53:00.851295 == TX Byte 1 ==
5222 05:53:00.854425 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5223 05:53:00.861039 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5224 05:53:00.861119
5225 05:53:00.861182 [DATLAT]
5226 05:53:00.861241 Freq=933, CH0 RK1
5227 05:53:00.861298
5228 05:53:00.864617 DATLAT Default: 0xb
5229 05:53:00.864696 0, 0xFFFF, sum = 0
5230 05:53:00.867699 1, 0xFFFF, sum = 0
5231 05:53:00.867780 2, 0xFFFF, sum = 0
5232 05:53:00.871152 3, 0xFFFF, sum = 0
5233 05:53:00.874254 4, 0xFFFF, sum = 0
5234 05:53:00.874336 5, 0xFFFF, sum = 0
5235 05:53:00.877670 6, 0xFFFF, sum = 0
5236 05:53:00.877751 7, 0xFFFF, sum = 0
5237 05:53:00.881013 8, 0xFFFF, sum = 0
5238 05:53:00.881095 9, 0xFFFF, sum = 0
5239 05:53:00.885012 10, 0x0, sum = 1
5240 05:53:00.885093 11, 0x0, sum = 2
5241 05:53:00.887915 12, 0x0, sum = 3
5242 05:53:00.887996 13, 0x0, sum = 4
5243 05:53:00.888061 best_step = 11
5244 05:53:00.888119
5245 05:53:00.891255 ==
5246 05:53:00.894103 Dram Type= 6, Freq= 0, CH_0, rank 1
5247 05:53:00.897613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5248 05:53:00.897706 ==
5249 05:53:00.897776 RX Vref Scan: 0
5250 05:53:00.897836
5251 05:53:00.900745 RX Vref 0 -> 0, step: 1
5252 05:53:00.900833
5253 05:53:00.903980 RX Delay -69 -> 252, step: 4
5254 05:53:00.907377 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5255 05:53:00.914130 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5256 05:53:00.917923 iDelay=199, Bit 2, Center 96 (3 ~ 190) 188
5257 05:53:00.920762 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5258 05:53:00.923959 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5259 05:53:00.927408 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5260 05:53:00.934163 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5261 05:53:00.937827 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5262 05:53:00.940852 iDelay=199, Bit 8, Center 78 (-9 ~ 166) 176
5263 05:53:00.943785 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5264 05:53:00.947428 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5265 05:53:00.950646 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5266 05:53:00.956989 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5267 05:53:00.960847 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5268 05:53:00.963684 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5269 05:53:00.967258 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5270 05:53:00.967337 ==
5271 05:53:00.970264 Dram Type= 6, Freq= 0, CH_0, rank 1
5272 05:53:00.974168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5273 05:53:00.977407 ==
5274 05:53:00.977480 DQS Delay:
5275 05:53:00.977542 DQS0 = 0, DQS1 = 0
5276 05:53:00.980516 DQM Delay:
5277 05:53:00.980587 DQM0 = 97, DQM1 = 87
5278 05:53:00.983605 DQ Delay:
5279 05:53:00.983677 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5280 05:53:00.990115 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =106
5281 05:53:00.993527 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =80
5282 05:53:00.996936 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94
5283 05:53:00.997009
5284 05:53:00.997070
5285 05:53:01.003315 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d2d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5286 05:53:01.006569 CH0 RK1: MR19=505, MR18=2D2D
5287 05:53:01.013213 CH0_RK1: MR19=0x505, MR18=0x2D2D, DQSOSC=407, MR23=63, INC=65, DEC=43
5288 05:53:01.016471 [RxdqsGatingPostProcess] freq 933
5289 05:53:01.020191 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5290 05:53:01.023476 Pre-setting of DQS Precalculation
5291 05:53:01.030077 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5292 05:53:01.030156 ==
5293 05:53:01.033282 Dram Type= 6, Freq= 0, CH_1, rank 0
5294 05:53:01.036634 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5295 05:53:01.036768 ==
5296 05:53:01.042994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5297 05:53:01.049995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5298 05:53:01.053225 [CA 0] Center 37 (7~68) winsize 62
5299 05:53:01.056654 [CA 1] Center 37 (6~68) winsize 63
5300 05:53:01.059862 [CA 2] Center 34 (4~65) winsize 62
5301 05:53:01.063117 [CA 3] Center 34 (4~65) winsize 62
5302 05:53:01.066416 [CA 4] Center 33 (2~64) winsize 63
5303 05:53:01.069733 [CA 5] Center 33 (2~64) winsize 63
5304 05:53:01.069806
5305 05:53:01.072814 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5306 05:53:01.072885
5307 05:53:01.076212 [CATrainingPosCal] consider 1 rank data
5308 05:53:01.079242 u2DelayCellTimex100 = 270/100 ps
5309 05:53:01.082579 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5310 05:53:01.086140 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5311 05:53:01.089414 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5312 05:53:01.093024 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5313 05:53:01.095889 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5314 05:53:01.099568 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5315 05:53:01.099638
5316 05:53:01.106068 CA PerBit enable=1, Macro0, CA PI delay=33
5317 05:53:01.106138
5318 05:53:01.106198 [CBTSetCACLKResult] CA Dly = 33
5319 05:53:01.109308 CS Dly: 5 (0~36)
5320 05:53:01.109372 ==
5321 05:53:01.112668 Dram Type= 6, Freq= 0, CH_1, rank 1
5322 05:53:01.115990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5323 05:53:01.116058 ==
5324 05:53:01.122428 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5325 05:53:01.129126 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5326 05:53:01.132286 [CA 0] Center 37 (6~68) winsize 63
5327 05:53:01.135672 [CA 1] Center 37 (6~68) winsize 63
5328 05:53:01.139077 [CA 2] Center 34 (4~65) winsize 62
5329 05:53:01.142473 [CA 3] Center 34 (4~65) winsize 62
5330 05:53:01.145886 [CA 4] Center 33 (3~64) winsize 62
5331 05:53:01.148945 [CA 5] Center 33 (3~64) winsize 62
5332 05:53:01.149020
5333 05:53:01.152237 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5334 05:53:01.152310
5335 05:53:01.155249 [CATrainingPosCal] consider 2 rank data
5336 05:53:01.158917 u2DelayCellTimex100 = 270/100 ps
5337 05:53:01.162116 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5338 05:53:01.165459 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5339 05:53:01.168866 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5340 05:53:01.172187 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5341 05:53:01.175385 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5342 05:53:01.181682 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5343 05:53:01.181756
5344 05:53:01.185255 CA PerBit enable=1, Macro0, CA PI delay=33
5345 05:53:01.185321
5346 05:53:01.188460 [CBTSetCACLKResult] CA Dly = 33
5347 05:53:01.188524 CS Dly: 5 (0~37)
5348 05:53:01.188585
5349 05:53:01.191611 ----->DramcWriteLeveling(PI) begin...
5350 05:53:01.191679 ==
5351 05:53:01.194938 Dram Type= 6, Freq= 0, CH_1, rank 0
5352 05:53:01.201931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5353 05:53:01.202008 ==
5354 05:53:01.204765 Write leveling (Byte 0): 26 => 26
5355 05:53:01.204848 Write leveling (Byte 1): 26 => 26
5356 05:53:01.208066 DramcWriteLeveling(PI) end<-----
5357 05:53:01.208130
5358 05:53:01.211419 ==
5359 05:53:01.211485 Dram Type= 6, Freq= 0, CH_1, rank 0
5360 05:53:01.218046 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5361 05:53:01.218117 ==
5362 05:53:01.221225 [Gating] SW mode calibration
5363 05:53:01.227811 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5364 05:53:01.231097 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5365 05:53:01.237875 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 05:53:01.241166 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 05:53:01.244412 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 05:53:01.250840 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 05:53:01.254577 0 10 16 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
5370 05:53:01.257824 0 10 20 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
5371 05:53:01.264489 0 10 24 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
5372 05:53:01.267927 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 05:53:01.270840 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 05:53:01.277308 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 05:53:01.280698 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 05:53:01.283936 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 05:53:01.290533 0 11 16 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5378 05:53:01.293832 0 11 20 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
5379 05:53:01.297352 0 11 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5380 05:53:01.303969 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 05:53:01.307070 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 05:53:01.310317 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 05:53:01.317112 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 05:53:01.320374 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5385 05:53:01.323525 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5386 05:53:01.330303 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 05:53:01.333791 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 05:53:01.336941 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 05:53:01.343850 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 05:53:01.347065 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 05:53:01.350056 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 05:53:01.356778 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 05:53:01.360239 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 05:53:01.363582 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 05:53:01.369830 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 05:53:01.373405 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 05:53:01.376395 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 05:53:01.383207 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 05:53:01.386525 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 05:53:01.389980 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 05:53:01.396251 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5402 05:53:01.399726 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 05:53:01.403226 Total UI for P1: 0, mck2ui 16
5404 05:53:01.407662 best dqsien dly found for B0: ( 0, 14, 16)
5405 05:53:01.409739 Total UI for P1: 0, mck2ui 16
5406 05:53:01.413113 best dqsien dly found for B1: ( 0, 14, 18)
5407 05:53:01.416185 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5408 05:53:01.419412 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5409 05:53:01.419486
5410 05:53:01.422953 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5411 05:53:01.425827 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5412 05:53:01.429327 [Gating] SW calibration Done
5413 05:53:01.429407 ==
5414 05:53:01.432997 Dram Type= 6, Freq= 0, CH_1, rank 0
5415 05:53:01.436296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5416 05:53:01.439528 ==
5417 05:53:01.439607 RX Vref Scan: 0
5418 05:53:01.439669
5419 05:53:01.443217 RX Vref 0 -> 0, step: 1
5420 05:53:01.443295
5421 05:53:01.443358 RX Delay -80 -> 252, step: 8
5422 05:53:01.449482 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5423 05:53:01.452919 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5424 05:53:01.456069 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5425 05:53:01.459446 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5426 05:53:01.462912 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5427 05:53:01.469390 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5428 05:53:01.472789 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5429 05:53:01.476113 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5430 05:53:01.479432 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5431 05:53:01.482634 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5432 05:53:01.486071 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5433 05:53:01.492953 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5434 05:53:01.496005 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5435 05:53:01.499853 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5436 05:53:01.502466 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5437 05:53:01.506232 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5438 05:53:01.506332 ==
5439 05:53:01.509134 Dram Type= 6, Freq= 0, CH_1, rank 0
5440 05:53:01.515808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5441 05:53:01.515929 ==
5442 05:53:01.516025 DQS Delay:
5443 05:53:01.519491 DQS0 = 0, DQS1 = 0
5444 05:53:01.519622 DQM Delay:
5445 05:53:01.522657 DQM0 = 94, DQM1 = 86
5446 05:53:01.522805 DQ Delay:
5447 05:53:01.525906 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5448 05:53:01.529332 DQ4 =91, DQ5 =107, DQ6 =99, DQ7 =91
5449 05:53:01.532685 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5450 05:53:01.535658 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =95
5451 05:53:01.535945
5452 05:53:01.536128
5453 05:53:01.536291 ==
5454 05:53:01.539834 Dram Type= 6, Freq= 0, CH_1, rank 0
5455 05:53:01.542658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5456 05:53:01.542947 ==
5457 05:53:01.543175
5458 05:53:01.543408
5459 05:53:01.545879 TX Vref Scan disable
5460 05:53:01.549334 == TX Byte 0 ==
5461 05:53:01.553052 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5462 05:53:01.555935 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5463 05:53:01.559584 == TX Byte 1 ==
5464 05:53:01.562632 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5465 05:53:01.565930 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5466 05:53:01.566384 ==
5467 05:53:01.569385 Dram Type= 6, Freq= 0, CH_1, rank 0
5468 05:53:01.572628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5469 05:53:01.575812 ==
5470 05:53:01.576234
5471 05:53:01.576559
5472 05:53:01.576961 TX Vref Scan disable
5473 05:53:01.579255 == TX Byte 0 ==
5474 05:53:01.582581 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5475 05:53:01.589187 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5476 05:53:01.589721 == TX Byte 1 ==
5477 05:53:01.592438 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5478 05:53:01.599467 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5479 05:53:01.599990
5480 05:53:01.600445 [DATLAT]
5481 05:53:01.600848 Freq=933, CH1 RK0
5482 05:53:01.601279
5483 05:53:01.602425 DATLAT Default: 0xd
5484 05:53:01.605879 0, 0xFFFF, sum = 0
5485 05:53:01.606342 1, 0xFFFF, sum = 0
5486 05:53:01.609398 2, 0xFFFF, sum = 0
5487 05:53:01.609858 3, 0xFFFF, sum = 0
5488 05:53:01.612316 4, 0xFFFF, sum = 0
5489 05:53:01.612862 5, 0xFFFF, sum = 0
5490 05:53:01.616092 6, 0xFFFF, sum = 0
5491 05:53:01.616646 7, 0xFFFF, sum = 0
5492 05:53:01.619118 8, 0xFFFF, sum = 0
5493 05:53:01.619580 9, 0xFFFF, sum = 0
5494 05:53:01.622323 10, 0x0, sum = 1
5495 05:53:01.622784 11, 0x0, sum = 2
5496 05:53:01.625500 12, 0x0, sum = 3
5497 05:53:01.625959 13, 0x0, sum = 4
5498 05:53:01.629007 best_step = 11
5499 05:53:01.629460
5500 05:53:01.629818 ==
5501 05:53:01.632187 Dram Type= 6, Freq= 0, CH_1, rank 0
5502 05:53:01.635157 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5503 05:53:01.635792 ==
5504 05:53:01.636168 RX Vref Scan: 1
5505 05:53:01.638439
5506 05:53:01.638887 RX Vref 0 -> 0, step: 1
5507 05:53:01.639241
5508 05:53:01.641720 RX Delay -69 -> 252, step: 4
5509 05:53:01.642128
5510 05:53:01.645102 Set Vref, RX VrefLevel [Byte0]: 55
5511 05:53:01.648779 [Byte1]: 49
5512 05:53:01.651978
5513 05:53:01.655203 Final RX Vref Byte 0 = 55 to rank0
5514 05:53:01.655616 Final RX Vref Byte 1 = 49 to rank0
5515 05:53:01.658683 Final RX Vref Byte 0 = 55 to rank1
5516 05:53:01.661928 Final RX Vref Byte 1 = 49 to rank1==
5517 05:53:01.665418 Dram Type= 6, Freq= 0, CH_1, rank 0
5518 05:53:01.671771 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5519 05:53:01.672201 ==
5520 05:53:01.672525 DQS Delay:
5521 05:53:01.674986 DQS0 = 0, DQS1 = 0
5522 05:53:01.675398 DQM Delay:
5523 05:53:01.675723 DQM0 = 94, DQM1 = 88
5524 05:53:01.678462 DQ Delay:
5525 05:53:01.681828 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
5526 05:53:01.685000 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =92
5527 05:53:01.688263 DQ8 =72, DQ9 =78, DQ10 =90, DQ11 =80
5528 05:53:01.691740 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5529 05:53:01.692197
5530 05:53:01.692556
5531 05:53:01.698559 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b2b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5532 05:53:01.701562 CH1 RK0: MR19=505, MR18=2B2B
5533 05:53:01.707770 CH1_RK0: MR19=0x505, MR18=0x2B2B, DQSOSC=408, MR23=63, INC=65, DEC=43
5534 05:53:01.708477
5535 05:53:01.711294 ----->DramcWriteLeveling(PI) begin...
5536 05:53:01.711749 ==
5537 05:53:01.714704 Dram Type= 6, Freq= 0, CH_1, rank 1
5538 05:53:01.718083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5539 05:53:01.718539 ==
5540 05:53:01.721325 Write leveling (Byte 0): 25 => 25
5541 05:53:01.724751 Write leveling (Byte 1): 23 => 23
5542 05:53:01.727888 DramcWriteLeveling(PI) end<-----
5543 05:53:01.728357
5544 05:53:01.728752 ==
5545 05:53:01.730923 Dram Type= 6, Freq= 0, CH_1, rank 1
5546 05:53:01.734547 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5547 05:53:01.737921 ==
5548 05:53:01.738371 [Gating] SW mode calibration
5549 05:53:01.748296 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5550 05:53:01.750939 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5551 05:53:01.754016 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 05:53:01.761351 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 05:53:01.764487 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 05:53:01.767797 0 10 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5555 05:53:01.774023 0 10 16 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
5556 05:53:01.777412 0 10 20 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
5557 05:53:01.780799 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 05:53:01.787458 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 05:53:01.791074 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 05:53:01.794099 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 05:53:01.800987 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 05:53:01.803996 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5563 05:53:01.807350 0 11 16 | B1->B0 | 2424 4242 | 0 0 | (0 0) (0 0)
5564 05:53:01.813947 0 11 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5565 05:53:01.817069 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 05:53:01.820490 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 05:53:01.827050 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 05:53:01.829925 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 05:53:01.833537 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 05:53:01.840375 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 05:53:01.843573 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5572 05:53:01.847074 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5573 05:53:01.853330 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5574 05:53:01.856407 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 05:53:01.859877 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 05:53:01.866855 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 05:53:01.870001 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 05:53:01.872835 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 05:53:01.880121 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 05:53:01.882802 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 05:53:01.886454 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 05:53:01.892865 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 05:53:01.896257 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 05:53:01.899406 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 05:53:01.906080 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 05:53:01.909543 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 05:53:01.912817 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5588 05:53:01.919496 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5589 05:53:01.922807 Total UI for P1: 0, mck2ui 16
5590 05:53:01.925852 best dqsien dly found for B0: ( 0, 14, 16)
5591 05:53:01.929028 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 05:53:01.932640 Total UI for P1: 0, mck2ui 16
5593 05:53:01.935306 best dqsien dly found for B1: ( 0, 14, 18)
5594 05:53:01.939476 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5595 05:53:01.942614 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5596 05:53:01.943165
5597 05:53:01.945330 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5598 05:53:01.952270 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5599 05:53:01.952920 [Gating] SW calibration Done
5600 05:53:01.953290 ==
5601 05:53:01.955421 Dram Type= 6, Freq= 0, CH_1, rank 1
5602 05:53:01.961947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5603 05:53:01.962498 ==
5604 05:53:01.962855 RX Vref Scan: 0
5605 05:53:01.963187
5606 05:53:01.965373 RX Vref 0 -> 0, step: 1
5607 05:53:01.965824
5608 05:53:01.968579 RX Delay -80 -> 252, step: 8
5609 05:53:01.972432 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5610 05:53:01.975182 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5611 05:53:01.978720 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5612 05:53:01.982030 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5613 05:53:01.989357 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5614 05:53:01.992201 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5615 05:53:01.995666 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5616 05:53:01.998740 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5617 05:53:02.002074 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5618 05:53:02.005415 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5619 05:53:02.012193 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5620 05:53:02.015670 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5621 05:53:02.018408 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5622 05:53:02.021873 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5623 05:53:02.025458 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5624 05:53:02.031513 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5625 05:53:02.031971 ==
5626 05:53:02.035263 Dram Type= 6, Freq= 0, CH_1, rank 1
5627 05:53:02.038146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5628 05:53:02.038614 ==
5629 05:53:02.038973 DQS Delay:
5630 05:53:02.041597 DQS0 = 0, DQS1 = 0
5631 05:53:02.042051 DQM Delay:
5632 05:53:02.044775 DQM0 = 94, DQM1 = 86
5633 05:53:02.045230 DQ Delay:
5634 05:53:02.048080 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =91
5635 05:53:02.051773 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5636 05:53:02.054809 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =75
5637 05:53:02.058188 DQ12 =99, DQ13 =99, DQ14 =91, DQ15 =95
5638 05:53:02.058640
5639 05:53:02.058995
5640 05:53:02.059322 ==
5641 05:53:02.061034 Dram Type= 6, Freq= 0, CH_1, rank 1
5642 05:53:02.064461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5643 05:53:02.068092 ==
5644 05:53:02.068641
5645 05:53:02.069043
5646 05:53:02.069372 TX Vref Scan disable
5647 05:53:02.071227 == TX Byte 0 ==
5648 05:53:02.074400 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5649 05:53:02.077796 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5650 05:53:02.080834 == TX Byte 1 ==
5651 05:53:02.084675 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5652 05:53:02.091105 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5653 05:53:02.091660 ==
5654 05:53:02.094299 Dram Type= 6, Freq= 0, CH_1, rank 1
5655 05:53:02.097676 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5656 05:53:02.098230 ==
5657 05:53:02.098588
5658 05:53:02.098917
5659 05:53:02.101184 TX Vref Scan disable
5660 05:53:02.101740 == TX Byte 0 ==
5661 05:53:02.107123 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5662 05:53:02.111184 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5663 05:53:02.111731 == TX Byte 1 ==
5664 05:53:02.117224 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5665 05:53:02.121209 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5666 05:53:02.121767
5667 05:53:02.122128 [DATLAT]
5668 05:53:02.123749 Freq=933, CH1 RK1
5669 05:53:02.124203
5670 05:53:02.124558 DATLAT Default: 0xb
5671 05:53:02.127410 0, 0xFFFF, sum = 0
5672 05:53:02.127871 1, 0xFFFF, sum = 0
5673 05:53:02.130356 2, 0xFFFF, sum = 0
5674 05:53:02.133624 3, 0xFFFF, sum = 0
5675 05:53:02.134084 4, 0xFFFF, sum = 0
5676 05:53:02.137250 5, 0xFFFF, sum = 0
5677 05:53:02.137711 6, 0xFFFF, sum = 0
5678 05:53:02.140578 7, 0xFFFF, sum = 0
5679 05:53:02.141090 8, 0xFFFF, sum = 0
5680 05:53:02.143837 9, 0xFFFF, sum = 0
5681 05:53:02.144595 10, 0x0, sum = 1
5682 05:53:02.147285 11, 0x0, sum = 2
5683 05:53:02.147840 12, 0x0, sum = 3
5684 05:53:02.150312 13, 0x0, sum = 4
5685 05:53:02.150772 best_step = 11
5686 05:53:02.151128
5687 05:53:02.151460 ==
5688 05:53:02.153494 Dram Type= 6, Freq= 0, CH_1, rank 1
5689 05:53:02.157204 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5690 05:53:02.157661 ==
5691 05:53:02.160680 RX Vref Scan: 0
5692 05:53:02.161281
5693 05:53:02.163637 RX Vref 0 -> 0, step: 1
5694 05:53:02.164088
5695 05:53:02.164506 RX Delay -77 -> 252, step: 4
5696 05:53:02.171976 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5697 05:53:02.175137 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5698 05:53:02.178484 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5699 05:53:02.181684 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5700 05:53:02.184785 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5701 05:53:02.191491 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5702 05:53:02.194799 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5703 05:53:02.198352 iDelay=203, Bit 7, Center 96 (3 ~ 190) 188
5704 05:53:02.201294 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5705 05:53:02.204987 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5706 05:53:02.208244 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5707 05:53:02.214265 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5708 05:53:02.217650 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5709 05:53:02.221541 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5710 05:53:02.224664 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5711 05:53:02.227883 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5712 05:53:02.228449 ==
5713 05:53:02.231163 Dram Type= 6, Freq= 0, CH_1, rank 1
5714 05:53:02.237605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5715 05:53:02.238063 ==
5716 05:53:02.238421 DQS Delay:
5717 05:53:02.241157 DQS0 = 0, DQS1 = 0
5718 05:53:02.241611 DQM Delay:
5719 05:53:02.241969 DQM0 = 96, DQM1 = 87
5720 05:53:02.244424 DQ Delay:
5721 05:53:02.248320 DQ0 =98, DQ1 =92, DQ2 =88, DQ3 =92
5722 05:53:02.251235 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =96
5723 05:53:02.254294 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5724 05:53:02.257317 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5725 05:53:02.257772
5726 05:53:02.258125
5727 05:53:02.264639 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5728 05:53:02.267548 CH1 RK1: MR19=505, MR18=2121
5729 05:53:02.273964 CH1_RK1: MR19=0x505, MR18=0x2121, DQSOSC=411, MR23=63, INC=64, DEC=42
5730 05:53:02.277593 [RxdqsGatingPostProcess] freq 933
5731 05:53:02.283982 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5732 05:53:02.284544 Pre-setting of DQS Precalculation
5733 05:53:02.290390 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5734 05:53:02.297019 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5735 05:53:02.304059 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5736 05:53:02.304616
5737 05:53:02.305021
5738 05:53:02.307425 [Calibration Summary] 1866 Mbps
5739 05:53:02.310290 CH 0, Rank 0
5740 05:53:02.310744 SW Impedance : PASS
5741 05:53:02.313676 DUTY Scan : NO K
5742 05:53:02.316827 ZQ Calibration : PASS
5743 05:53:02.317282 Jitter Meter : NO K
5744 05:53:02.320185 CBT Training : PASS
5745 05:53:02.324131 Write leveling : PASS
5746 05:53:02.324693 RX DQS gating : PASS
5747 05:53:02.327326 RX DQ/DQS(RDDQC) : PASS
5748 05:53:02.330083 TX DQ/DQS : PASS
5749 05:53:02.330587 RX DATLAT : PASS
5750 05:53:02.333250 RX DQ/DQS(Engine): PASS
5751 05:53:02.333700 TX OE : NO K
5752 05:53:02.336894 All Pass.
5753 05:53:02.337341
5754 05:53:02.337693 CH 0, Rank 1
5755 05:53:02.340102 SW Impedance : PASS
5756 05:53:02.340550 DUTY Scan : NO K
5757 05:53:02.343251 ZQ Calibration : PASS
5758 05:53:02.346414 Jitter Meter : NO K
5759 05:53:02.346865 CBT Training : PASS
5760 05:53:02.349762 Write leveling : PASS
5761 05:53:02.353419 RX DQS gating : PASS
5762 05:53:02.353872 RX DQ/DQS(RDDQC) : PASS
5763 05:53:02.356828 TX DQ/DQS : PASS
5764 05:53:02.360371 RX DATLAT : PASS
5765 05:53:02.360959 RX DQ/DQS(Engine): PASS
5766 05:53:02.363248 TX OE : NO K
5767 05:53:02.363698 All Pass.
5768 05:53:02.364050
5769 05:53:02.366555 CH 1, Rank 0
5770 05:53:02.367105 SW Impedance : PASS
5771 05:53:02.369985 DUTY Scan : NO K
5772 05:53:02.373342 ZQ Calibration : PASS
5773 05:53:02.374017 Jitter Meter : NO K
5774 05:53:02.376310 CBT Training : PASS
5775 05:53:02.379949 Write leveling : PASS
5776 05:53:02.380453 RX DQS gating : PASS
5777 05:53:02.383386 RX DQ/DQS(RDDQC) : PASS
5778 05:53:02.387054 TX DQ/DQS : PASS
5779 05:53:02.387607 RX DATLAT : PASS
5780 05:53:02.389979 RX DQ/DQS(Engine): PASS
5781 05:53:02.390605 TX OE : NO K
5782 05:53:02.393193 All Pass.
5783 05:53:02.393741
5784 05:53:02.394094 CH 1, Rank 1
5785 05:53:02.396137 SW Impedance : PASS
5786 05:53:02.396586 DUTY Scan : NO K
5787 05:53:02.399702 ZQ Calibration : PASS
5788 05:53:02.402803 Jitter Meter : NO K
5789 05:53:02.403255 CBT Training : PASS
5790 05:53:02.406305 Write leveling : PASS
5791 05:53:02.409774 RX DQS gating : PASS
5792 05:53:02.410329 RX DQ/DQS(RDDQC) : PASS
5793 05:53:02.412917 TX DQ/DQS : PASS
5794 05:53:02.416463 RX DATLAT : PASS
5795 05:53:02.417050 RX DQ/DQS(Engine): PASS
5796 05:53:02.419989 TX OE : NO K
5797 05:53:02.420571 All Pass.
5798 05:53:02.420972
5799 05:53:02.423129 DramC Write-DBI off
5800 05:53:02.426192 PER_BANK_REFRESH: Hybrid Mode
5801 05:53:02.426747 TX_TRACKING: ON
5802 05:53:02.436400 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5803 05:53:02.439357 [FAST_K] Save calibration result to emmc
5804 05:53:02.442937 dramc_set_vcore_voltage set vcore to 650000
5805 05:53:02.446034 Read voltage for 400, 6
5806 05:53:02.446486 Vio18 = 0
5807 05:53:02.446841 Vcore = 650000
5808 05:53:02.449146 Vdram = 0
5809 05:53:02.449711 Vddq = 0
5810 05:53:02.450077 Vmddr = 0
5811 05:53:02.456055 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5812 05:53:02.459196 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5813 05:53:02.462532 MEM_TYPE=3, freq_sel=20
5814 05:53:02.466181 sv_algorithm_assistance_LP4_800
5815 05:53:02.469471 ============ PULL DRAM RESETB DOWN ============
5816 05:53:02.475976 ========== PULL DRAM RESETB DOWN end =========
5817 05:53:02.478950 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5818 05:53:02.481927 ===================================
5819 05:53:02.485912 LPDDR4 DRAM CONFIGURATION
5820 05:53:02.488746 ===================================
5821 05:53:02.489214 EX_ROW_EN[0] = 0x0
5822 05:53:02.492233 EX_ROW_EN[1] = 0x0
5823 05:53:02.493027 LP4Y_EN = 0x0
5824 05:53:02.495393 WORK_FSP = 0x0
5825 05:53:02.495947 WL = 0x2
5826 05:53:02.499255 RL = 0x2
5827 05:53:02.499807 BL = 0x2
5828 05:53:02.501948 RPST = 0x0
5829 05:53:02.505242 RD_PRE = 0x0
5830 05:53:02.505793 WR_PRE = 0x1
5831 05:53:02.508358 WR_PST = 0x0
5832 05:53:02.508880 DBI_WR = 0x0
5833 05:53:02.511901 DBI_RD = 0x0
5834 05:53:02.512457 OTF = 0x1
5835 05:53:02.515212 ===================================
5836 05:53:02.518324 ===================================
5837 05:53:02.521517 ANA top config
5838 05:53:02.524770 ===================================
5839 05:53:02.525371 DLL_ASYNC_EN = 0
5840 05:53:02.528494 ALL_SLAVE_EN = 1
5841 05:53:02.531758 NEW_RANK_MODE = 1
5842 05:53:02.535129 DLL_IDLE_MODE = 1
5843 05:53:02.535579 LP45_APHY_COMB_EN = 1
5844 05:53:02.538445 TX_ODT_DIS = 1
5845 05:53:02.541177 NEW_8X_MODE = 1
5846 05:53:02.544625 ===================================
5847 05:53:02.548087 ===================================
5848 05:53:02.551445 data_rate = 800
5849 05:53:02.554533 CKR = 1
5850 05:53:02.558072 DQ_P2S_RATIO = 4
5851 05:53:02.561578 ===================================
5852 05:53:02.562127 CA_P2S_RATIO = 4
5853 05:53:02.564526 DQ_CA_OPEN = 0
5854 05:53:02.567915 DQ_SEMI_OPEN = 1
5855 05:53:02.571143 CA_SEMI_OPEN = 1
5856 05:53:02.574219 CA_FULL_RATE = 0
5857 05:53:02.577853 DQ_CKDIV4_EN = 0
5858 05:53:02.578303 CA_CKDIV4_EN = 1
5859 05:53:02.580813 CA_PREDIV_EN = 0
5860 05:53:02.584129 PH8_DLY = 0
5861 05:53:02.587772 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5862 05:53:02.590783 DQ_AAMCK_DIV = 0
5863 05:53:02.594092 CA_AAMCK_DIV = 0
5864 05:53:02.594545 CA_ADMCK_DIV = 4
5865 05:53:02.597498 DQ_TRACK_CA_EN = 0
5866 05:53:02.600944 CA_PICK = 800
5867 05:53:02.603996 CA_MCKIO = 400
5868 05:53:02.607580 MCKIO_SEMI = 400
5869 05:53:02.610853 PLL_FREQ = 3016
5870 05:53:02.613996 DQ_UI_PI_RATIO = 32
5871 05:53:02.617543 CA_UI_PI_RATIO = 32
5872 05:53:02.620605 ===================================
5873 05:53:02.623821 ===================================
5874 05:53:02.624368 memory_type:LPDDR4
5875 05:53:02.627351 GP_NUM : 10
5876 05:53:02.627873 SRAM_EN : 1
5877 05:53:02.630380 MD32_EN : 0
5878 05:53:02.634048 ===================================
5879 05:53:02.637394 [ANA_INIT] >>>>>>>>>>>>>>
5880 05:53:02.640786 <<<<<< [CONFIGURE PHASE]: ANA_TX
5881 05:53:02.644007 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5882 05:53:02.647068 ===================================
5883 05:53:02.650645 data_rate = 800,PCW = 0X7400
5884 05:53:02.651092 ===================================
5885 05:53:02.657174 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5886 05:53:02.660351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5887 05:53:02.673715 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5888 05:53:02.677275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5889 05:53:02.680631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5890 05:53:02.684084 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5891 05:53:02.687061 [ANA_INIT] flow start
5892 05:53:02.687604 [ANA_INIT] PLL >>>>>>>>
5893 05:53:02.690385 [ANA_INIT] PLL <<<<<<<<
5894 05:53:02.693795 [ANA_INIT] MIDPI >>>>>>>>
5895 05:53:02.697124 [ANA_INIT] MIDPI <<<<<<<<
5896 05:53:02.697645 [ANA_INIT] DLL >>>>>>>>
5897 05:53:02.700517 [ANA_INIT] flow end
5898 05:53:02.703709 ============ LP4 DIFF to SE enter ============
5899 05:53:02.707271 ============ LP4 DIFF to SE exit ============
5900 05:53:02.710337 [ANA_INIT] <<<<<<<<<<<<<
5901 05:53:02.713748 [Flow] Enable top DCM control >>>>>
5902 05:53:02.716772 [Flow] Enable top DCM control <<<<<
5903 05:53:02.719923 Enable DLL master slave shuffle
5904 05:53:02.726657 ==============================================================
5905 05:53:02.727167 Gating Mode config
5906 05:53:02.733068 ==============================================================
5907 05:53:02.733727 Config description:
5908 05:53:02.743195 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5909 05:53:02.749607 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5910 05:53:02.756210 SELPH_MODE 0: By rank 1: By Phase
5911 05:53:02.759780 ==============================================================
5912 05:53:02.763026 GAT_TRACK_EN = 0
5913 05:53:02.766591 RX_GATING_MODE = 2
5914 05:53:02.770310 RX_GATING_TRACK_MODE = 2
5915 05:53:02.773268 SELPH_MODE = 1
5916 05:53:02.776413 PICG_EARLY_EN = 1
5917 05:53:02.779579 VALID_LAT_VALUE = 1
5918 05:53:02.786362 ==============================================================
5919 05:53:02.789567 Enter into Gating configuration >>>>
5920 05:53:02.793034 Exit from Gating configuration <<<<
5921 05:53:02.793496 Enter into DVFS_PRE_config >>>>>
5922 05:53:02.806029 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5923 05:53:02.809310 Exit from DVFS_PRE_config <<<<<
5924 05:53:02.812887 Enter into PICG configuration >>>>
5925 05:53:02.815985 Exit from PICG configuration <<<<
5926 05:53:02.816513 [RX_INPUT] configuration >>>>>
5927 05:53:02.819402 [RX_INPUT] configuration <<<<<
5928 05:53:02.826229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5929 05:53:02.829503 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5930 05:53:02.835813 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5931 05:53:02.842416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5932 05:53:02.849273 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5933 05:53:02.855624 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5934 05:53:02.858864 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5935 05:53:02.862527 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5936 05:53:02.869217 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5937 05:53:02.872067 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5938 05:53:02.875810 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5939 05:53:02.882343 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5940 05:53:02.885212 ===================================
5941 05:53:02.885668 LPDDR4 DRAM CONFIGURATION
5942 05:53:02.889247 ===================================
5943 05:53:02.892371 EX_ROW_EN[0] = 0x0
5944 05:53:02.892885 EX_ROW_EN[1] = 0x0
5945 05:53:02.895507 LP4Y_EN = 0x0
5946 05:53:02.896062 WORK_FSP = 0x0
5947 05:53:02.899314 WL = 0x2
5948 05:53:02.900040 RL = 0x2
5949 05:53:02.901892 BL = 0x2
5950 05:53:02.905816 RPST = 0x0
5951 05:53:02.906270 RD_PRE = 0x0
5952 05:53:02.908526 WR_PRE = 0x1
5953 05:53:02.908998 WR_PST = 0x0
5954 05:53:02.911803 DBI_WR = 0x0
5955 05:53:02.912253 DBI_RD = 0x0
5956 05:53:02.915490 OTF = 0x1
5957 05:53:02.919148 ===================================
5958 05:53:02.922055 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5959 05:53:02.925457 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5960 05:53:02.928934 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5961 05:53:02.931622 ===================================
5962 05:53:02.935225 LPDDR4 DRAM CONFIGURATION
5963 05:53:02.938924 ===================================
5964 05:53:02.941929 EX_ROW_EN[0] = 0x10
5965 05:53:02.942383 EX_ROW_EN[1] = 0x0
5966 05:53:02.945311 LP4Y_EN = 0x0
5967 05:53:02.945756 WORK_FSP = 0x0
5968 05:53:02.948236 WL = 0x2
5969 05:53:02.948683 RL = 0x2
5970 05:53:02.951792 BL = 0x2
5971 05:53:02.952245 RPST = 0x0
5972 05:53:02.955082 RD_PRE = 0x0
5973 05:53:02.958461 WR_PRE = 0x1
5974 05:53:02.958912 WR_PST = 0x0
5975 05:53:02.961433 DBI_WR = 0x0
5976 05:53:02.961878 DBI_RD = 0x0
5977 05:53:02.964982 OTF = 0x1
5978 05:53:02.968189 ===================================
5979 05:53:02.971845 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5980 05:53:02.977358 nWR fixed to 30
5981 05:53:02.980294 [ModeRegInit_LP4] CH0 RK0
5982 05:53:02.980788 [ModeRegInit_LP4] CH0 RK1
5983 05:53:02.983975 [ModeRegInit_LP4] CH1 RK0
5984 05:53:02.987305 [ModeRegInit_LP4] CH1 RK1
5985 05:53:02.987851 match AC timing 18
5986 05:53:02.993699 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5987 05:53:02.996915 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5988 05:53:02.999919 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5989 05:53:03.007172 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5990 05:53:03.010273 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5991 05:53:03.010727 ==
5992 05:53:03.013861 Dram Type= 6, Freq= 0, CH_0, rank 0
5993 05:53:03.016880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5994 05:53:03.017334 ==
5995 05:53:03.023483 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5996 05:53:03.029546 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5997 05:53:03.033001 [CA 0] Center 36 (8~64) winsize 57
5998 05:53:03.036544 [CA 1] Center 36 (8~64) winsize 57
5999 05:53:03.039936 [CA 2] Center 36 (8~64) winsize 57
6000 05:53:03.042993 [CA 3] Center 36 (8~64) winsize 57
6001 05:53:03.046154 [CA 4] Center 36 (8~64) winsize 57
6002 05:53:03.046606 [CA 5] Center 36 (8~64) winsize 57
6003 05:53:03.049864
6004 05:53:03.053112 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6005 05:53:03.053565
6006 05:53:03.056084 [CATrainingPosCal] consider 1 rank data
6007 05:53:03.059551 u2DelayCellTimex100 = 270/100 ps
6008 05:53:03.062995 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6009 05:53:03.066289 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6010 05:53:03.069454 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6011 05:53:03.072871 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6012 05:53:03.075939 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6013 05:53:03.079238 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6014 05:53:03.079759
6015 05:53:03.082498 CA PerBit enable=1, Macro0, CA PI delay=36
6016 05:53:03.085989
6017 05:53:03.086440 [CBTSetCACLKResult] CA Dly = 36
6018 05:53:03.089295 CS Dly: 1 (0~32)
6019 05:53:03.089747 ==
6020 05:53:03.092786 Dram Type= 6, Freq= 0, CH_0, rank 1
6021 05:53:03.095451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6022 05:53:03.095908 ==
6023 05:53:03.102621 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6024 05:53:03.108819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6025 05:53:03.112156 [CA 0] Center 36 (8~64) winsize 57
6026 05:53:03.115928 [CA 1] Center 36 (8~64) winsize 57
6027 05:53:03.116468 [CA 2] Center 36 (8~64) winsize 57
6028 05:53:03.119457 [CA 3] Center 36 (8~64) winsize 57
6029 05:53:03.122152 [CA 4] Center 36 (8~64) winsize 57
6030 05:53:03.125772 [CA 5] Center 36 (8~64) winsize 57
6031 05:53:03.126381
6032 05:53:03.128967 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6033 05:53:03.132325
6034 05:53:03.135419 [CATrainingPosCal] consider 2 rank data
6035 05:53:03.135881 u2DelayCellTimex100 = 270/100 ps
6036 05:53:03.142181 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6037 05:53:03.145261 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6038 05:53:03.149068 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6039 05:53:03.151968 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6040 05:53:03.155274 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6041 05:53:03.158968 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6042 05:53:03.159419
6043 05:53:03.162338 CA PerBit enable=1, Macro0, CA PI delay=36
6044 05:53:03.162890
6045 05:53:03.165099 [CBTSetCACLKResult] CA Dly = 36
6046 05:53:03.168785 CS Dly: 1 (0~32)
6047 05:53:03.169352
6048 05:53:03.171712 ----->DramcWriteLeveling(PI) begin...
6049 05:53:03.172171 ==
6050 05:53:03.175354 Dram Type= 6, Freq= 0, CH_0, rank 0
6051 05:53:03.178471 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6052 05:53:03.179068 ==
6053 05:53:03.181676 Write leveling (Byte 0): 32 => 0
6054 05:53:03.185049 Write leveling (Byte 1): 32 => 0
6055 05:53:03.188099 DramcWriteLeveling(PI) end<-----
6056 05:53:03.188531
6057 05:53:03.188915 ==
6058 05:53:03.191508 Dram Type= 6, Freq= 0, CH_0, rank 0
6059 05:53:03.195190 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6060 05:53:03.195643 ==
6061 05:53:03.198189 [Gating] SW mode calibration
6062 05:53:03.204828 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6063 05:53:03.211307 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6064 05:53:03.214577 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6065 05:53:03.218408 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6066 05:53:03.224892 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6067 05:53:03.228173 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6068 05:53:03.231161 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6069 05:53:03.237877 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6070 05:53:03.241399 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6071 05:53:03.244280 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6072 05:53:03.251117 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6073 05:53:03.254209 Total UI for P1: 0, mck2ui 16
6074 05:53:03.257775 best dqsien dly found for B0: ( 0, 10, 16)
6075 05:53:03.260743 Total UI for P1: 0, mck2ui 16
6076 05:53:03.264054 best dqsien dly found for B1: ( 0, 10, 24)
6077 05:53:03.267615 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6078 05:53:03.271083 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6079 05:53:03.271536
6080 05:53:03.274170 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6081 05:53:03.277174 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6082 05:53:03.280760 [Gating] SW calibration Done
6083 05:53:03.281213 ==
6084 05:53:03.283840 Dram Type= 6, Freq= 0, CH_0, rank 0
6085 05:53:03.287456 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6086 05:53:03.287910 ==
6087 05:53:03.290405 RX Vref Scan: 0
6088 05:53:03.291017
6089 05:53:03.294101 RX Vref 0 -> 0, step: 1
6090 05:53:03.294546
6091 05:53:03.294907 RX Delay -410 -> 252, step: 16
6092 05:53:03.300848 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6093 05:53:03.303936 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6094 05:53:03.307647 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6095 05:53:03.310965 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6096 05:53:03.317825 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6097 05:53:03.321207 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6098 05:53:03.323971 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6099 05:53:03.327608 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6100 05:53:03.334356 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6101 05:53:03.337122 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6102 05:53:03.340765 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6103 05:53:03.347760 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6104 05:53:03.350485 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6105 05:53:03.354244 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6106 05:53:03.357289 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6107 05:53:03.364105 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6108 05:53:03.364649 ==
6109 05:53:03.367830 Dram Type= 6, Freq= 0, CH_0, rank 0
6110 05:53:03.370300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6111 05:53:03.370758 ==
6112 05:53:03.371111 DQS Delay:
6113 05:53:03.374054 DQS0 = 43, DQS1 = 59
6114 05:53:03.374502 DQM Delay:
6115 05:53:03.377326 DQM0 = 5, DQM1 = 14
6116 05:53:03.377774 DQ Delay:
6117 05:53:03.380288 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6118 05:53:03.384128 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6119 05:53:03.387046 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6120 05:53:03.390255 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6121 05:53:03.390706
6122 05:53:03.391059
6123 05:53:03.391390 ==
6124 05:53:03.393900 Dram Type= 6, Freq= 0, CH_0, rank 0
6125 05:53:03.396738 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6126 05:53:03.397195 ==
6127 05:53:03.397553
6128 05:53:03.397878
6129 05:53:03.400421 TX Vref Scan disable
6130 05:53:03.400899 == TX Byte 0 ==
6131 05:53:03.406775 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6132 05:53:03.410444 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6133 05:53:03.410897 == TX Byte 1 ==
6134 05:53:03.416954 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6135 05:53:03.420351 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6136 05:53:03.420855 ==
6137 05:53:03.423570 Dram Type= 6, Freq= 0, CH_0, rank 0
6138 05:53:03.426827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6139 05:53:03.427284 ==
6140 05:53:03.427780
6141 05:53:03.430264
6142 05:53:03.430716 TX Vref Scan disable
6143 05:53:03.433444 == TX Byte 0 ==
6144 05:53:03.436616 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6145 05:53:03.440257 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6146 05:53:03.443160 == TX Byte 1 ==
6147 05:53:03.446353 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6148 05:53:03.450332 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6149 05:53:03.450865
6150 05:53:03.452998 [DATLAT]
6151 05:53:03.453408 Freq=400, CH0 RK0
6152 05:53:03.453735
6153 05:53:03.456461 DATLAT Default: 0xf
6154 05:53:03.456903 0, 0xFFFF, sum = 0
6155 05:53:03.459632 1, 0xFFFF, sum = 0
6156 05:53:03.460048 2, 0xFFFF, sum = 0
6157 05:53:03.463262 3, 0xFFFF, sum = 0
6158 05:53:03.463678 4, 0xFFFF, sum = 0
6159 05:53:03.466225 5, 0xFFFF, sum = 0
6160 05:53:03.466642 6, 0xFFFF, sum = 0
6161 05:53:03.469353 7, 0xFFFF, sum = 0
6162 05:53:03.469767 8, 0xFFFF, sum = 0
6163 05:53:03.472684 9, 0xFFFF, sum = 0
6164 05:53:03.473129 10, 0xFFFF, sum = 0
6165 05:53:03.476044 11, 0xFFFF, sum = 0
6166 05:53:03.476459 12, 0x0, sum = 1
6167 05:53:03.479592 13, 0x0, sum = 2
6168 05:53:03.480008 14, 0x0, sum = 3
6169 05:53:03.482804 15, 0x0, sum = 4
6170 05:53:03.483221 best_step = 13
6171 05:53:03.483548
6172 05:53:03.483854 ==
6173 05:53:03.486988 Dram Type= 6, Freq= 0, CH_0, rank 0
6174 05:53:03.493055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6175 05:53:03.493521 ==
6176 05:53:03.493889 RX Vref Scan: 1
6177 05:53:03.494409
6178 05:53:03.496172 RX Vref 0 -> 0, step: 1
6179 05:53:03.496584
6180 05:53:03.499257 RX Delay -359 -> 252, step: 8
6181 05:53:03.499668
6182 05:53:03.502399 Set Vref, RX VrefLevel [Byte0]: 47
6183 05:53:03.506112 [Byte1]: 48
6184 05:53:03.509459
6185 05:53:03.509904 Final RX Vref Byte 0 = 47 to rank0
6186 05:53:03.512474 Final RX Vref Byte 1 = 48 to rank0
6187 05:53:03.515727 Final RX Vref Byte 0 = 47 to rank1
6188 05:53:03.519017 Final RX Vref Byte 1 = 48 to rank1==
6189 05:53:03.522118 Dram Type= 6, Freq= 0, CH_0, rank 0
6190 05:53:03.529018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6191 05:53:03.529430 ==
6192 05:53:03.529754 DQS Delay:
6193 05:53:03.532800 DQS0 = 52, DQS1 = 68
6194 05:53:03.533303 DQM Delay:
6195 05:53:03.533630 DQM0 = 9, DQM1 = 17
6196 05:53:03.535358 DQ Delay:
6197 05:53:03.538727 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6198 05:53:03.539126 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6199 05:53:03.542012 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6200 05:53:03.545470 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6201 05:53:03.545882
6202 05:53:03.548824
6203 05:53:03.555445 [DQSOSCAuto] RK0, (LSB)MR18= 0xa5a5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6204 05:53:03.558854 CH0 RK0: MR19=C0C, MR18=A5A5
6205 05:53:03.565186 CH0_RK0: MR19=0xC0C, MR18=0xA5A5, DQSOSC=389, MR23=63, INC=390, DEC=260
6206 05:53:03.565598 ==
6207 05:53:03.568508 Dram Type= 6, Freq= 0, CH_0, rank 1
6208 05:53:03.571880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6209 05:53:03.572303 ==
6210 05:53:03.574904 [Gating] SW mode calibration
6211 05:53:03.581822 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6212 05:53:03.588910 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6213 05:53:03.591798 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6214 05:53:03.595373 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6215 05:53:03.601372 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6216 05:53:03.604939 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6217 05:53:03.608376 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6218 05:53:03.614892 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6219 05:53:03.618474 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6220 05:53:03.621336 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6221 05:53:03.627965 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6222 05:53:03.628381 Total UI for P1: 0, mck2ui 16
6223 05:53:03.634811 best dqsien dly found for B0: ( 0, 10, 16)
6224 05:53:03.635270 Total UI for P1: 0, mck2ui 16
6225 05:53:03.640990 best dqsien dly found for B1: ( 0, 10, 16)
6226 05:53:03.644542 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6227 05:53:03.647802 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6228 05:53:03.648231
6229 05:53:03.651222 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6230 05:53:03.654482 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6231 05:53:03.657843 [Gating] SW calibration Done
6232 05:53:03.658270 ==
6233 05:53:03.661018 Dram Type= 6, Freq= 0, CH_0, rank 1
6234 05:53:03.664322 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6235 05:53:03.664885 ==
6236 05:53:03.667450 RX Vref Scan: 0
6237 05:53:03.667967
6238 05:53:03.668315 RX Vref 0 -> 0, step: 1
6239 05:53:03.668757
6240 05:53:03.671059 RX Delay -410 -> 252, step: 16
6241 05:53:03.677684 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6242 05:53:03.680696 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6243 05:53:03.684200 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6244 05:53:03.687428 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6245 05:53:03.693676 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6246 05:53:03.697207 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6247 05:53:03.700372 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6248 05:53:03.704078 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6249 05:53:03.710249 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6250 05:53:03.713779 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6251 05:53:03.717057 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6252 05:53:03.720701 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6253 05:53:03.727324 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6254 05:53:03.730512 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6255 05:53:03.733461 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6256 05:53:03.740224 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6257 05:53:03.740636 ==
6258 05:53:03.743836 Dram Type= 6, Freq= 0, CH_0, rank 1
6259 05:53:03.747188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6260 05:53:03.747610 ==
6261 05:53:03.747953 DQS Delay:
6262 05:53:03.750153 DQS0 = 43, DQS1 = 59
6263 05:53:03.750669 DQM Delay:
6264 05:53:03.753630 DQM0 = 7, DQM1 = 15
6265 05:53:03.754049 DQ Delay:
6266 05:53:03.756891 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6267 05:53:03.760283 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6268 05:53:03.763226 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6269 05:53:03.766706 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6270 05:53:03.767128
6271 05:53:03.767520
6272 05:53:03.767914 ==
6273 05:53:03.769937 Dram Type= 6, Freq= 0, CH_0, rank 1
6274 05:53:03.773373 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6275 05:53:03.773981 ==
6276 05:53:03.774391
6277 05:53:03.774897
6278 05:53:03.776248 TX Vref Scan disable
6279 05:53:03.776837 == TX Byte 0 ==
6280 05:53:03.783114 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6281 05:53:03.786442 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6282 05:53:03.786923 == TX Byte 1 ==
6283 05:53:03.792957 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6284 05:53:03.796184 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6285 05:53:03.796609 ==
6286 05:53:03.799660 Dram Type= 6, Freq= 0, CH_0, rank 1
6287 05:53:03.802932 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6288 05:53:03.803360 ==
6289 05:53:03.803695
6290 05:53:03.806437
6291 05:53:03.806863 TX Vref Scan disable
6292 05:53:03.809267 == TX Byte 0 ==
6293 05:53:03.813260 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6294 05:53:03.816328 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6295 05:53:03.819244 == TX Byte 1 ==
6296 05:53:03.822571 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6297 05:53:03.826120 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6298 05:53:03.826538
6299 05:53:03.826864 [DATLAT]
6300 05:53:03.829176 Freq=400, CH0 RK1
6301 05:53:03.829594
6302 05:53:03.829919 DATLAT Default: 0xd
6303 05:53:03.832589 0, 0xFFFF, sum = 0
6304 05:53:03.835907 1, 0xFFFF, sum = 0
6305 05:53:03.836330 2, 0xFFFF, sum = 0
6306 05:53:03.839040 3, 0xFFFF, sum = 0
6307 05:53:03.839562 4, 0xFFFF, sum = 0
6308 05:53:03.842343 5, 0xFFFF, sum = 0
6309 05:53:03.842809 6, 0xFFFF, sum = 0
6310 05:53:03.845880 7, 0xFFFF, sum = 0
6311 05:53:03.846282 8, 0xFFFF, sum = 0
6312 05:53:03.849193 9, 0xFFFF, sum = 0
6313 05:53:03.849639 10, 0xFFFF, sum = 0
6314 05:53:03.852302 11, 0xFFFF, sum = 0
6315 05:53:03.852748 12, 0x0, sum = 1
6316 05:53:03.855600 13, 0x0, sum = 2
6317 05:53:03.856010 14, 0x0, sum = 3
6318 05:53:03.858865 15, 0x0, sum = 4
6319 05:53:03.859279 best_step = 13
6320 05:53:03.859727
6321 05:53:03.860243 ==
6322 05:53:03.861994 Dram Type= 6, Freq= 0, CH_0, rank 1
6323 05:53:03.865199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6324 05:53:03.868892 ==
6325 05:53:03.869185 RX Vref Scan: 0
6326 05:53:03.869414
6327 05:53:03.871758 RX Vref 0 -> 0, step: 1
6328 05:53:03.872132
6329 05:53:03.874946 RX Delay -359 -> 252, step: 8
6330 05:53:03.881784 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6331 05:53:03.885206 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6332 05:53:03.888255 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6333 05:53:03.891634 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6334 05:53:03.898416 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6335 05:53:03.901841 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6336 05:53:03.905017 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6337 05:53:03.908221 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6338 05:53:03.915104 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6339 05:53:03.918141 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6340 05:53:03.921534 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6341 05:53:03.924578 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6342 05:53:03.931779 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6343 05:53:03.934880 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6344 05:53:03.937805 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6345 05:53:03.944635 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6346 05:53:03.945049 ==
6347 05:53:03.948066 Dram Type= 6, Freq= 0, CH_0, rank 1
6348 05:53:03.951060 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6349 05:53:03.951448 ==
6350 05:53:03.951785 DQS Delay:
6351 05:53:03.954344 DQS0 = 52, DQS1 = 64
6352 05:53:03.954714 DQM Delay:
6353 05:53:03.957812 DQM0 = 10, DQM1 = 13
6354 05:53:03.958187 DQ Delay:
6355 05:53:03.961069 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4
6356 05:53:03.964651 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6357 05:53:03.967632 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6358 05:53:03.971060 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6359 05:53:03.971411
6360 05:53:03.971685
6361 05:53:03.977682 [DQSOSCAuto] RK1, (LSB)MR18= 0xbaba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6362 05:53:03.981073 CH0 RK1: MR19=C0C, MR18=BABA
6363 05:53:03.987572 CH0_RK1: MR19=0xC0C, MR18=0xBABA, DQSOSC=386, MR23=63, INC=396, DEC=264
6364 05:53:03.990874 [RxdqsGatingPostProcess] freq 400
6365 05:53:03.997847 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6366 05:53:03.998235 Pre-setting of DQS Precalculation
6367 05:53:04.003841 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6368 05:53:04.004269 ==
6369 05:53:04.007566 Dram Type= 6, Freq= 0, CH_1, rank 0
6370 05:53:04.010631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6371 05:53:04.011012 ==
6372 05:53:04.017602 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6373 05:53:04.023883 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6374 05:53:04.026956 [CA 0] Center 36 (8~64) winsize 57
6375 05:53:04.030170 [CA 1] Center 36 (8~64) winsize 57
6376 05:53:04.034145 [CA 2] Center 36 (8~64) winsize 57
6377 05:53:04.037013 [CA 3] Center 36 (8~64) winsize 57
6378 05:53:04.040295 [CA 4] Center 36 (8~64) winsize 57
6379 05:53:04.040677 [CA 5] Center 36 (8~64) winsize 57
6380 05:53:04.043519
6381 05:53:04.046971 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6382 05:53:04.047351
6383 05:53:04.050249 [CATrainingPosCal] consider 1 rank data
6384 05:53:04.053562 u2DelayCellTimex100 = 270/100 ps
6385 05:53:04.056947 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6386 05:53:04.060517 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6387 05:53:04.063404 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6388 05:53:04.066604 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6389 05:53:04.070070 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6390 05:53:04.073207 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6391 05:53:04.073589
6392 05:53:04.076451 CA PerBit enable=1, Macro0, CA PI delay=36
6393 05:53:04.079771
6394 05:53:04.080197 [CBTSetCACLKResult] CA Dly = 36
6395 05:53:04.083305 CS Dly: 1 (0~32)
6396 05:53:04.083689 ==
6397 05:53:04.086651 Dram Type= 6, Freq= 0, CH_1, rank 1
6398 05:53:04.089598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6399 05:53:04.089983 ==
6400 05:53:04.096758 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6401 05:53:04.103115 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6402 05:53:04.105992 [CA 0] Center 36 (8~64) winsize 57
6403 05:53:04.109754 [CA 1] Center 36 (8~64) winsize 57
6404 05:53:04.112543 [CA 2] Center 36 (8~64) winsize 57
6405 05:53:04.116075 [CA 3] Center 36 (8~64) winsize 57
6406 05:53:04.116457 [CA 4] Center 36 (8~64) winsize 57
6407 05:53:04.119705 [CA 5] Center 36 (8~64) winsize 57
6408 05:53:04.120078
6409 05:53:04.126274 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6410 05:53:04.126648
6411 05:53:04.129474 [CATrainingPosCal] consider 2 rank data
6412 05:53:04.132943 u2DelayCellTimex100 = 270/100 ps
6413 05:53:04.136223 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6414 05:53:04.139464 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6415 05:53:04.142737 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6416 05:53:04.145586 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6417 05:53:04.149439 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6418 05:53:04.152670 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6419 05:53:04.153149
6420 05:53:04.155573 CA PerBit enable=1, Macro0, CA PI delay=36
6421 05:53:04.155934
6422 05:53:04.159114 [CBTSetCACLKResult] CA Dly = 36
6423 05:53:04.162206 CS Dly: 1 (0~32)
6424 05:53:04.162570
6425 05:53:04.165444 ----->DramcWriteLeveling(PI) begin...
6426 05:53:04.165877 ==
6427 05:53:04.169025 Dram Type= 6, Freq= 0, CH_1, rank 0
6428 05:53:04.172568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6429 05:53:04.173064 ==
6430 05:53:04.175535 Write leveling (Byte 0): 32 => 0
6431 05:53:04.178660 Write leveling (Byte 1): 32 => 0
6432 05:53:04.182248 DramcWriteLeveling(PI) end<-----
6433 05:53:04.182618
6434 05:53:04.182924 ==
6435 05:53:04.185540 Dram Type= 6, Freq= 0, CH_1, rank 0
6436 05:53:04.189118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6437 05:53:04.189557 ==
6438 05:53:04.192176 [Gating] SW mode calibration
6439 05:53:04.198590 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6440 05:53:04.204893 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6441 05:53:04.208822 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6442 05:53:04.215406 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 05:53:04.218812 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6444 05:53:04.221936 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6445 05:53:04.225003 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 05:53:04.231835 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 05:53:04.234936 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 05:53:04.238217 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6449 05:53:04.244801 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 05:53:04.248376 Total UI for P1: 0, mck2ui 16
6451 05:53:04.251919 best dqsien dly found for B0: ( 0, 10, 16)
6452 05:53:04.255180 Total UI for P1: 0, mck2ui 16
6453 05:53:04.258091 best dqsien dly found for B1: ( 0, 10, 16)
6454 05:53:04.261663 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6455 05:53:04.264674 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6456 05:53:04.265096
6457 05:53:04.268236 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6458 05:53:04.271179 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6459 05:53:04.274410 [Gating] SW calibration Done
6460 05:53:04.274765 ==
6461 05:53:04.277923 Dram Type= 6, Freq= 0, CH_1, rank 0
6462 05:53:04.281490 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6463 05:53:04.284491 ==
6464 05:53:04.284882 RX Vref Scan: 0
6465 05:53:04.285184
6466 05:53:04.288100 RX Vref 0 -> 0, step: 1
6467 05:53:04.288458
6468 05:53:04.291162 RX Delay -410 -> 252, step: 16
6469 05:53:04.294552 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6470 05:53:04.297748 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6471 05:53:04.301177 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6472 05:53:04.307847 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6473 05:53:04.311283 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6474 05:53:04.314500 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6475 05:53:04.317688 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6476 05:53:04.324082 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6477 05:53:04.327402 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6478 05:53:04.330726 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6479 05:53:04.334031 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6480 05:53:04.340449 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6481 05:53:04.343927 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6482 05:53:04.347199 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6483 05:53:04.353435 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6484 05:53:04.356781 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6485 05:53:04.357117 ==
6486 05:53:04.360293 Dram Type= 6, Freq= 0, CH_1, rank 0
6487 05:53:04.363401 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6488 05:53:04.363833 ==
6489 05:53:04.366667 DQS Delay:
6490 05:53:04.366983 DQS0 = 43, DQS1 = 59
6491 05:53:04.370437 DQM Delay:
6492 05:53:04.370829 DQM0 = 6, DQM1 = 15
6493 05:53:04.371279 DQ Delay:
6494 05:53:04.373539 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6495 05:53:04.376915 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6496 05:53:04.380403 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6497 05:53:04.383226 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6498 05:53:04.383698
6499 05:53:04.384083
6500 05:53:04.384472 ==
6501 05:53:04.386474 Dram Type= 6, Freq= 0, CH_1, rank 0
6502 05:53:04.389732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6503 05:53:04.393486 ==
6504 05:53:04.393848
6505 05:53:04.394226
6506 05:53:04.394580 TX Vref Scan disable
6507 05:53:04.396581 == TX Byte 0 ==
6508 05:53:04.400079 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6509 05:53:04.403566 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6510 05:53:04.406951 == TX Byte 1 ==
6511 05:53:04.409435 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6512 05:53:04.412818 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6513 05:53:04.412925 ==
6514 05:53:04.416608 Dram Type= 6, Freq= 0, CH_1, rank 0
6515 05:53:04.422863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6516 05:53:04.422966 ==
6517 05:53:04.423047
6518 05:53:04.423128
6519 05:53:04.425868 TX Vref Scan disable
6520 05:53:04.425941 == TX Byte 0 ==
6521 05:53:04.429332 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6522 05:53:04.436100 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6523 05:53:04.436200 == TX Byte 1 ==
6524 05:53:04.438953 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6525 05:53:04.445486 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6526 05:53:04.445566
6527 05:53:04.445648 [DATLAT]
6528 05:53:04.445731 Freq=400, CH1 RK0
6529 05:53:04.445808
6530 05:53:04.448979 DATLAT Default: 0xf
6531 05:53:04.452391 0, 0xFFFF, sum = 0
6532 05:53:04.452492 1, 0xFFFF, sum = 0
6533 05:53:04.455541 2, 0xFFFF, sum = 0
6534 05:53:04.455640 3, 0xFFFF, sum = 0
6535 05:53:04.458796 4, 0xFFFF, sum = 0
6536 05:53:04.458895 5, 0xFFFF, sum = 0
6537 05:53:04.462274 6, 0xFFFF, sum = 0
6538 05:53:04.462374 7, 0xFFFF, sum = 0
6539 05:53:04.465147 8, 0xFFFF, sum = 0
6540 05:53:04.465220 9, 0xFFFF, sum = 0
6541 05:53:04.468821 10, 0xFFFF, sum = 0
6542 05:53:04.468901 11, 0xFFFF, sum = 0
6543 05:53:04.471933 12, 0x0, sum = 1
6544 05:53:04.472006 13, 0x0, sum = 2
6545 05:53:04.475121 14, 0x0, sum = 3
6546 05:53:04.475220 15, 0x0, sum = 4
6547 05:53:04.478561 best_step = 13
6548 05:53:04.478658
6549 05:53:04.478754 ==
6550 05:53:04.482206 Dram Type= 6, Freq= 0, CH_1, rank 0
6551 05:53:04.485629 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6552 05:53:04.485703 ==
6553 05:53:04.488615 RX Vref Scan: 1
6554 05:53:04.488721
6555 05:53:04.488829 RX Vref 0 -> 0, step: 1
6556 05:53:04.488910
6557 05:53:04.492083 RX Delay -359 -> 252, step: 8
6558 05:53:04.492154
6559 05:53:04.495427 Set Vref, RX VrefLevel [Byte0]: 55
6560 05:53:04.498707 [Byte1]: 49
6561 05:53:04.503262
6562 05:53:04.503361 Final RX Vref Byte 0 = 55 to rank0
6563 05:53:04.506652 Final RX Vref Byte 1 = 49 to rank0
6564 05:53:04.509561 Final RX Vref Byte 0 = 55 to rank1
6565 05:53:04.512746 Final RX Vref Byte 1 = 49 to rank1==
6566 05:53:04.516484 Dram Type= 6, Freq= 0, CH_1, rank 0
6567 05:53:04.523008 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6568 05:53:04.523085 ==
6569 05:53:04.523169 DQS Delay:
6570 05:53:04.526201 DQS0 = 48, DQS1 = 64
6571 05:53:04.526275 DQM Delay:
6572 05:53:04.526354 DQM0 = 7, DQM1 = 15
6573 05:53:04.529504 DQ Delay:
6574 05:53:04.532730 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6575 05:53:04.532822 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6576 05:53:04.536200 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6577 05:53:04.539353 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6578 05:53:04.539453
6579 05:53:04.539552
6580 05:53:04.549728 [DQSOSCAuto] RK0, (LSB)MR18= 0xc9c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6581 05:53:04.552761 CH1 RK0: MR19=C0C, MR18=C9C9
6582 05:53:04.559449 CH1_RK0: MR19=0xC0C, MR18=0xC9C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6583 05:53:04.559527 ==
6584 05:53:04.562655 Dram Type= 6, Freq= 0, CH_1, rank 1
6585 05:53:04.565811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6586 05:53:04.565889 ==
6587 05:53:04.569253 [Gating] SW mode calibration
6588 05:53:04.575965 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6589 05:53:04.582273 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6590 05:53:04.585506 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6591 05:53:04.589270 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6592 05:53:04.595366 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6593 05:53:04.599216 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6594 05:53:04.602140 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6595 05:53:04.609135 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6596 05:53:04.611834 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6597 05:53:04.615346 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6598 05:53:04.618451 Total UI for P1: 0, mck2ui 16
6599 05:53:04.622037 best dqsien dly found for B0: ( 0, 10, 8)
6600 05:53:04.628503 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6601 05:53:04.628584 Total UI for P1: 0, mck2ui 16
6602 05:53:04.631769 best dqsien dly found for B1: ( 0, 10, 16)
6603 05:53:04.638205 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6604 05:53:04.641551 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6605 05:53:04.641672
6606 05:53:04.645160 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6607 05:53:04.648248 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6608 05:53:04.651546 [Gating] SW calibration Done
6609 05:53:04.651643 ==
6610 05:53:04.654663 Dram Type= 6, Freq= 0, CH_1, rank 1
6611 05:53:04.658910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6612 05:53:04.659009 ==
6613 05:53:04.661668 RX Vref Scan: 0
6614 05:53:04.661738
6615 05:53:04.661798 RX Vref 0 -> 0, step: 1
6616 05:53:04.661859
6617 05:53:04.665157 RX Delay -410 -> 252, step: 16
6618 05:53:04.671397 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6619 05:53:04.674654 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6620 05:53:04.677877 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6621 05:53:04.681753 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6622 05:53:04.688353 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6623 05:53:04.691330 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6624 05:53:04.694869 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6625 05:53:04.698253 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6626 05:53:04.704690 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6627 05:53:04.708188 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6628 05:53:04.711242 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6629 05:53:04.714539 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6630 05:53:04.720953 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6631 05:53:04.724662 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6632 05:53:04.727713 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6633 05:53:04.730935 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6634 05:53:04.734352 ==
6635 05:53:04.737553 Dram Type= 6, Freq= 0, CH_1, rank 1
6636 05:53:04.740867 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6637 05:53:04.740948 ==
6638 05:53:04.741012 DQS Delay:
6639 05:53:04.744270 DQS0 = 43, DQS1 = 59
6640 05:53:04.744351 DQM Delay:
6641 05:53:04.747414 DQM0 = 10, DQM1 = 18
6642 05:53:04.747495 DQ Delay:
6643 05:53:04.750886 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6644 05:53:04.754149 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6645 05:53:04.757456 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6646 05:53:04.760822 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6647 05:53:04.760902
6648 05:53:04.760965
6649 05:53:04.761025 ==
6650 05:53:04.764191 Dram Type= 6, Freq= 0, CH_1, rank 1
6651 05:53:04.767658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6652 05:53:04.767740 ==
6653 05:53:04.767803
6654 05:53:04.767863
6655 05:53:04.770845 TX Vref Scan disable
6656 05:53:04.770926 == TX Byte 0 ==
6657 05:53:04.777606 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6658 05:53:04.780493 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6659 05:53:04.780573 == TX Byte 1 ==
6660 05:53:04.787096 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6661 05:53:04.790425 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6662 05:53:04.790505 ==
6663 05:53:04.794119 Dram Type= 6, Freq= 0, CH_1, rank 1
6664 05:53:04.797350 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6665 05:53:04.797457 ==
6666 05:53:04.797548
6667 05:53:04.797625
6668 05:53:04.800612 TX Vref Scan disable
6669 05:53:04.800727 == TX Byte 0 ==
6670 05:53:04.806834 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6671 05:53:04.810625 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6672 05:53:04.810706 == TX Byte 1 ==
6673 05:53:04.816990 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6674 05:53:04.820521 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6675 05:53:04.820601
6676 05:53:04.820664 [DATLAT]
6677 05:53:04.823924 Freq=400, CH1 RK1
6678 05:53:04.824003
6679 05:53:04.824067 DATLAT Default: 0xd
6680 05:53:04.827377 0, 0xFFFF, sum = 0
6681 05:53:04.827459 1, 0xFFFF, sum = 0
6682 05:53:04.830538 2, 0xFFFF, sum = 0
6683 05:53:04.830619 3, 0xFFFF, sum = 0
6684 05:53:04.833507 4, 0xFFFF, sum = 0
6685 05:53:04.833589 5, 0xFFFF, sum = 0
6686 05:53:04.836689 6, 0xFFFF, sum = 0
6687 05:53:04.836796 7, 0xFFFF, sum = 0
6688 05:53:04.840167 8, 0xFFFF, sum = 0
6689 05:53:04.843342 9, 0xFFFF, sum = 0
6690 05:53:04.843424 10, 0xFFFF, sum = 0
6691 05:53:04.846874 11, 0xFFFF, sum = 0
6692 05:53:04.846956 12, 0x0, sum = 1
6693 05:53:04.849868 13, 0x0, sum = 2
6694 05:53:04.849960 14, 0x0, sum = 3
6695 05:53:04.850026 15, 0x0, sum = 4
6696 05:53:04.853357 best_step = 13
6697 05:53:04.853437
6698 05:53:04.853500 ==
6699 05:53:04.856534 Dram Type= 6, Freq= 0, CH_1, rank 1
6700 05:53:04.859874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6701 05:53:04.859956 ==
6702 05:53:04.863087 RX Vref Scan: 0
6703 05:53:04.863167
6704 05:53:04.866663 RX Vref 0 -> 0, step: 1
6705 05:53:04.866744
6706 05:53:04.866807 RX Delay -359 -> 252, step: 8
6707 05:53:04.875399 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6708 05:53:04.878372 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6709 05:53:04.881679 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6710 05:53:04.885021 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6711 05:53:04.891978 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6712 05:53:04.894902 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6713 05:53:04.898383 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6714 05:53:04.901752 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6715 05:53:04.908648 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6716 05:53:04.912058 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6717 05:53:04.915093 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6718 05:53:04.918605 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6719 05:53:04.924721 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6720 05:53:04.928227 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6721 05:53:04.931804 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6722 05:53:04.938617 iDelay=225, Bit 15, Center -44 (-287 ~ 200) 488
6723 05:53:04.938722 ==
6724 05:53:04.941343 Dram Type= 6, Freq= 0, CH_1, rank 1
6725 05:53:04.944725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6726 05:53:04.944827 ==
6727 05:53:04.944890 DQS Delay:
6728 05:53:04.947995 DQS0 = 48, DQS1 = 64
6729 05:53:04.948076 DQM Delay:
6730 05:53:04.951309 DQM0 = 9, DQM1 = 15
6731 05:53:04.951389 DQ Delay:
6732 05:53:04.954624 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6733 05:53:04.957818 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6734 05:53:04.961103 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6735 05:53:04.964713 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6736 05:53:04.964809
6737 05:53:04.964874
6738 05:53:04.971279 [DQSOSCAuto] RK1, (LSB)MR18= 0x9e9e, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
6739 05:53:04.974760 CH1 RK1: MR19=C0C, MR18=9E9E
6740 05:53:04.981125 CH1_RK1: MR19=0xC0C, MR18=0x9E9E, DQSOSC=390, MR23=63, INC=388, DEC=258
6741 05:53:04.984562 [RxdqsGatingPostProcess] freq 400
6742 05:53:04.990829 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6743 05:53:04.994416 Pre-setting of DQS Precalculation
6744 05:53:04.998095 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6745 05:53:05.004256 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6746 05:53:05.010803 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6747 05:53:05.010885
6748 05:53:05.013869
6749 05:53:05.013950 [Calibration Summary] 800 Mbps
6750 05:53:05.017576 CH 0, Rank 0
6751 05:53:05.017657 SW Impedance : PASS
6752 05:53:05.020466 DUTY Scan : NO K
6753 05:53:05.024193 ZQ Calibration : PASS
6754 05:53:05.024274 Jitter Meter : NO K
6755 05:53:05.027369 CBT Training : PASS
6756 05:53:05.030481 Write leveling : PASS
6757 05:53:05.030561 RX DQS gating : PASS
6758 05:53:05.034179 RX DQ/DQS(RDDQC) : PASS
6759 05:53:05.037549 TX DQ/DQS : PASS
6760 05:53:05.037630 RX DATLAT : PASS
6761 05:53:05.040888 RX DQ/DQS(Engine): PASS
6762 05:53:05.040968 TX OE : NO K
6763 05:53:05.043975 All Pass.
6764 05:53:05.044055
6765 05:53:05.044121 CH 0, Rank 1
6766 05:53:05.047356 SW Impedance : PASS
6767 05:53:05.050859 DUTY Scan : NO K
6768 05:53:05.050940 ZQ Calibration : PASS
6769 05:53:05.053644 Jitter Meter : NO K
6770 05:53:05.053724 CBT Training : PASS
6771 05:53:05.057334 Write leveling : NO K
6772 05:53:05.060239 RX DQS gating : PASS
6773 05:53:05.060319 RX DQ/DQS(RDDQC) : PASS
6774 05:53:05.063714 TX DQ/DQS : PASS
6775 05:53:05.067046 RX DATLAT : PASS
6776 05:53:05.067127 RX DQ/DQS(Engine): PASS
6777 05:53:05.070117 TX OE : NO K
6778 05:53:05.070197 All Pass.
6779 05:53:05.070262
6780 05:53:05.073499 CH 1, Rank 0
6781 05:53:05.073580 SW Impedance : PASS
6782 05:53:05.076627 DUTY Scan : NO K
6783 05:53:05.080239 ZQ Calibration : PASS
6784 05:53:05.080319 Jitter Meter : NO K
6785 05:53:05.083500 CBT Training : PASS
6786 05:53:05.086820 Write leveling : PASS
6787 05:53:05.086901 RX DQS gating : PASS
6788 05:53:05.090087 RX DQ/DQS(RDDQC) : PASS
6789 05:53:05.093125 TX DQ/DQS : PASS
6790 05:53:05.093208 RX DATLAT : PASS
6791 05:53:05.096891 RX DQ/DQS(Engine): PASS
6792 05:53:05.100072 TX OE : NO K
6793 05:53:05.100153 All Pass.
6794 05:53:05.100216
6795 05:53:05.100275 CH 1, Rank 1
6796 05:53:05.103391 SW Impedance : PASS
6797 05:53:05.106526 DUTY Scan : NO K
6798 05:53:05.106607 ZQ Calibration : PASS
6799 05:53:05.109689 Jitter Meter : NO K
6800 05:53:05.113433 CBT Training : PASS
6801 05:53:05.113540 Write leveling : NO K
6802 05:53:05.116498 RX DQS gating : PASS
6803 05:53:05.116578 RX DQ/DQS(RDDQC) : PASS
6804 05:53:05.119649 TX DQ/DQS : PASS
6805 05:53:05.123202 RX DATLAT : PASS
6806 05:53:05.123282 RX DQ/DQS(Engine): PASS
6807 05:53:05.126702 TX OE : NO K
6808 05:53:05.126812 All Pass.
6809 05:53:05.126876
6810 05:53:05.129634 DramC Write-DBI off
6811 05:53:05.133049 PER_BANK_REFRESH: Hybrid Mode
6812 05:53:05.133129 TX_TRACKING: ON
6813 05:53:05.143280 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6814 05:53:05.146169 [FAST_K] Save calibration result to emmc
6815 05:53:05.149485 dramc_set_vcore_voltage set vcore to 725000
6816 05:53:05.152958 Read voltage for 1600, 0
6817 05:53:05.153038 Vio18 = 0
6818 05:53:05.156062 Vcore = 725000
6819 05:53:05.156143 Vdram = 0
6820 05:53:05.156207 Vddq = 0
6821 05:53:05.156268 Vmddr = 0
6822 05:53:05.162868 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6823 05:53:05.169341 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6824 05:53:05.169448 MEM_TYPE=3, freq_sel=13
6825 05:53:05.172310 sv_algorithm_assistance_LP4_3733
6826 05:53:05.175875 ============ PULL DRAM RESETB DOWN ============
6827 05:53:05.182449 ========== PULL DRAM RESETB DOWN end =========
6828 05:53:05.185664 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6829 05:53:05.189097 ===================================
6830 05:53:05.192354 LPDDR4 DRAM CONFIGURATION
6831 05:53:05.195842 ===================================
6832 05:53:05.195923 EX_ROW_EN[0] = 0x0
6833 05:53:05.198901 EX_ROW_EN[1] = 0x0
6834 05:53:05.202358 LP4Y_EN = 0x0
6835 05:53:05.202438 WORK_FSP = 0x1
6836 05:53:05.205572 WL = 0x5
6837 05:53:05.205652 RL = 0x5
6838 05:53:05.208635 BL = 0x2
6839 05:53:05.208776 RPST = 0x0
6840 05:53:05.211965 RD_PRE = 0x0
6841 05:53:05.212046 WR_PRE = 0x1
6842 05:53:05.215341 WR_PST = 0x1
6843 05:53:05.215421 DBI_WR = 0x0
6844 05:53:05.218796 DBI_RD = 0x0
6845 05:53:05.218938 OTF = 0x1
6846 05:53:05.221989 ===================================
6847 05:53:05.225354 ===================================
6848 05:53:05.228558 ANA top config
6849 05:53:05.232003 ===================================
6850 05:53:05.232084 DLL_ASYNC_EN = 0
6851 05:53:05.235452 ALL_SLAVE_EN = 0
6852 05:53:05.238955 NEW_RANK_MODE = 1
6853 05:53:05.242038 DLL_IDLE_MODE = 1
6854 05:53:05.245202 LP45_APHY_COMB_EN = 1
6855 05:53:05.245285 TX_ODT_DIS = 0
6856 05:53:05.249057 NEW_8X_MODE = 1
6857 05:53:05.251913 ===================================
6858 05:53:05.255363 ===================================
6859 05:53:05.259049 data_rate = 3200
6860 05:53:05.261821 CKR = 1
6861 05:53:05.265237 DQ_P2S_RATIO = 8
6862 05:53:05.268827 ===================================
6863 05:53:05.268952 CA_P2S_RATIO = 8
6864 05:53:05.272301 DQ_CA_OPEN = 0
6865 05:53:05.275096 DQ_SEMI_OPEN = 0
6866 05:53:05.278444 CA_SEMI_OPEN = 0
6867 05:53:05.281766 CA_FULL_RATE = 0
6868 05:53:05.285079 DQ_CKDIV4_EN = 0
6869 05:53:05.285160 CA_CKDIV4_EN = 0
6870 05:53:05.288409 CA_PREDIV_EN = 0
6871 05:53:05.291727 PH8_DLY = 12
6872 05:53:05.294936 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6873 05:53:05.298516 DQ_AAMCK_DIV = 4
6874 05:53:05.301501 CA_AAMCK_DIV = 4
6875 05:53:05.304940 CA_ADMCK_DIV = 4
6876 05:53:05.305017 DQ_TRACK_CA_EN = 0
6877 05:53:05.308349 CA_PICK = 1600
6878 05:53:05.311401 CA_MCKIO = 1600
6879 05:53:05.315057 MCKIO_SEMI = 0
6880 05:53:05.318398 PLL_FREQ = 3068
6881 05:53:05.321407 DQ_UI_PI_RATIO = 32
6882 05:53:05.324876 CA_UI_PI_RATIO = 0
6883 05:53:05.328021 ===================================
6884 05:53:05.331247 ===================================
6885 05:53:05.331325 memory_type:LPDDR4
6886 05:53:05.334870 GP_NUM : 10
6887 05:53:05.337905 SRAM_EN : 1
6888 05:53:05.337989 MD32_EN : 0
6889 05:53:05.341453 ===================================
6890 05:53:05.344529 [ANA_INIT] >>>>>>>>>>>>>>
6891 05:53:05.347722 <<<<<< [CONFIGURE PHASE]: ANA_TX
6892 05:53:05.351262 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6893 05:53:05.354911 ===================================
6894 05:53:05.357671 data_rate = 3200,PCW = 0X7600
6895 05:53:05.360909 ===================================
6896 05:53:05.364521 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6897 05:53:05.368086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6898 05:53:05.374290 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6899 05:53:05.377459 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6900 05:53:05.381236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6901 05:53:05.384284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6902 05:53:05.387469 [ANA_INIT] flow start
6903 05:53:05.391011 [ANA_INIT] PLL >>>>>>>>
6904 05:53:05.391104 [ANA_INIT] PLL <<<<<<<<
6905 05:53:05.394531 [ANA_INIT] MIDPI >>>>>>>>
6906 05:53:05.397948 [ANA_INIT] MIDPI <<<<<<<<
6907 05:53:05.401138 [ANA_INIT] DLL >>>>>>>>
6908 05:53:05.401217 [ANA_INIT] DLL <<<<<<<<
6909 05:53:05.404430 [ANA_INIT] flow end
6910 05:53:05.407310 ============ LP4 DIFF to SE enter ============
6911 05:53:05.410658 ============ LP4 DIFF to SE exit ============
6912 05:53:05.414080 [ANA_INIT] <<<<<<<<<<<<<
6913 05:53:05.417280 [Flow] Enable top DCM control >>>>>
6914 05:53:05.420613 [Flow] Enable top DCM control <<<<<
6915 05:53:05.423846 Enable DLL master slave shuffle
6916 05:53:05.430869 ==============================================================
6917 05:53:05.430945 Gating Mode config
6918 05:53:05.437166 ==============================================================
6919 05:53:05.437246 Config description:
6920 05:53:05.447249 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6921 05:53:05.453836 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6922 05:53:05.460712 SELPH_MODE 0: By rank 1: By Phase
6923 05:53:05.463532 ==============================================================
6924 05:53:05.467284 GAT_TRACK_EN = 1
6925 05:53:05.470350 RX_GATING_MODE = 2
6926 05:53:05.473648 RX_GATING_TRACK_MODE = 2
6927 05:53:05.477021 SELPH_MODE = 1
6928 05:53:05.480262 PICG_EARLY_EN = 1
6929 05:53:05.483634 VALID_LAT_VALUE = 1
6930 05:53:05.486869 ==============================================================
6931 05:53:05.490185 Enter into Gating configuration >>>>
6932 05:53:05.493745 Exit from Gating configuration <<<<
6933 05:53:05.496940 Enter into DVFS_PRE_config >>>>>
6934 05:53:05.510141 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6935 05:53:05.513589 Exit from DVFS_PRE_config <<<<<
6936 05:53:05.517006 Enter into PICG configuration >>>>
6937 05:53:05.519968 Exit from PICG configuration <<<<
6938 05:53:05.520046 [RX_INPUT] configuration >>>>>
6939 05:53:05.523490 [RX_INPUT] configuration <<<<<
6940 05:53:05.530189 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6941 05:53:05.533352 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6942 05:53:05.539946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6943 05:53:05.546448 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6944 05:53:05.552815 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6945 05:53:05.559766 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6946 05:53:05.562939 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6947 05:53:05.566416 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6948 05:53:05.572741 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6949 05:53:05.576151 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6950 05:53:05.579293 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6951 05:53:05.586252 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6952 05:53:05.589570 ===================================
6953 05:53:05.589652 LPDDR4 DRAM CONFIGURATION
6954 05:53:05.592952 ===================================
6955 05:53:05.596175 EX_ROW_EN[0] = 0x0
6956 05:53:05.596256 EX_ROW_EN[1] = 0x0
6957 05:53:05.599359 LP4Y_EN = 0x0
6958 05:53:05.599429 WORK_FSP = 0x1
6959 05:53:05.602960 WL = 0x5
6960 05:53:05.603035 RL = 0x5
6961 05:53:05.605932 BL = 0x2
6962 05:53:05.609436 RPST = 0x0
6963 05:53:05.609512 RD_PRE = 0x0
6964 05:53:05.612360 WR_PRE = 0x1
6965 05:53:05.612434 WR_PST = 0x1
6966 05:53:05.615869 DBI_WR = 0x0
6967 05:53:05.615975 DBI_RD = 0x0
6968 05:53:05.619155 OTF = 0x1
6969 05:53:05.622928 ===================================
6970 05:53:05.625716 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6971 05:53:05.629357 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6972 05:53:05.632347 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6973 05:53:05.635632 ===================================
6974 05:53:05.638858 LPDDR4 DRAM CONFIGURATION
6975 05:53:05.642301 ===================================
6976 05:53:05.645590 EX_ROW_EN[0] = 0x10
6977 05:53:05.645669 EX_ROW_EN[1] = 0x0
6978 05:53:05.649193 LP4Y_EN = 0x0
6979 05:53:05.649266 WORK_FSP = 0x1
6980 05:53:05.652263 WL = 0x5
6981 05:53:05.652332 RL = 0x5
6982 05:53:05.655601 BL = 0x2
6983 05:53:05.655674 RPST = 0x0
6984 05:53:05.659166 RD_PRE = 0x0
6985 05:53:05.662692 WR_PRE = 0x1
6986 05:53:05.662768 WR_PST = 0x1
6987 05:53:05.665320 DBI_WR = 0x0
6988 05:53:05.665392 DBI_RD = 0x0
6989 05:53:05.668762 OTF = 0x1
6990 05:53:05.671965 ===================================
6991 05:53:05.675326 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6992 05:53:05.678606 ==
6993 05:53:05.681904 Dram Type= 6, Freq= 0, CH_0, rank 0
6994 05:53:05.685790 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6995 05:53:05.685867 ==
6996 05:53:05.689091 [Duty_Offset_Calibration]
6997 05:53:05.689162 B0:0 B1:2 CA:1
6998 05:53:05.689222
6999 05:53:05.691998 [DutyScan_Calibration_Flow] k_type=0
7000 05:53:05.701868
7001 05:53:05.701943 ==CLK 0==
7002 05:53:05.705358 Final CLK duty delay cell = 0
7003 05:53:05.708572 [0] MAX Duty = 5156%(X100), DQS PI = 20
7004 05:53:05.711933 [0] MIN Duty = 4938%(X100), DQS PI = 50
7005 05:53:05.715351 [0] AVG Duty = 5047%(X100)
7006 05:53:05.715430
7007 05:53:05.718534 CH0 CLK Duty spec in!! Max-Min= 218%
7008 05:53:05.722188 [DutyScan_Calibration_Flow] ====Done====
7009 05:53:05.722262
7010 05:53:05.725216 [DutyScan_Calibration_Flow] k_type=1
7011 05:53:05.742378
7012 05:53:05.742453 ==DQS 0 ==
7013 05:53:05.745358 Final DQS duty delay cell = 0
7014 05:53:05.748693 [0] MAX Duty = 5125%(X100), DQS PI = 30
7015 05:53:05.751663 [0] MIN Duty = 5031%(X100), DQS PI = 8
7016 05:53:05.755387 [0] AVG Duty = 5078%(X100)
7017 05:53:05.755470
7018 05:53:05.755533 ==DQS 1 ==
7019 05:53:05.758796 Final DQS duty delay cell = 0
7020 05:53:05.761740 [0] MAX Duty = 5031%(X100), DQS PI = 4
7021 05:53:05.765147 [0] MIN Duty = 4876%(X100), DQS PI = 16
7022 05:53:05.768180 [0] AVG Duty = 4953%(X100)
7023 05:53:05.768260
7024 05:53:05.771602 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7025 05:53:05.771681
7026 05:53:05.774771 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7027 05:53:05.778336 [DutyScan_Calibration_Flow] ====Done====
7028 05:53:05.778417
7029 05:53:05.781634 [DutyScan_Calibration_Flow] k_type=3
7030 05:53:05.798590
7031 05:53:05.798670 ==DQM 0 ==
7032 05:53:05.802398 Final DQM duty delay cell = 0
7033 05:53:05.805570 [0] MAX Duty = 5187%(X100), DQS PI = 22
7034 05:53:05.808593 [0] MIN Duty = 4907%(X100), DQS PI = 42
7035 05:53:05.812054 [0] AVG Duty = 5047%(X100)
7036 05:53:05.812134
7037 05:53:05.812196 ==DQM 1 ==
7038 05:53:05.815689 Final DQM duty delay cell = 0
7039 05:53:05.818710 [0] MAX Duty = 5031%(X100), DQS PI = 4
7040 05:53:05.821747 [0] MIN Duty = 4782%(X100), DQS PI = 12
7041 05:53:05.825490 [0] AVG Duty = 4906%(X100)
7042 05:53:05.825571
7043 05:53:05.828550 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7044 05:53:05.828631
7045 05:53:05.831533 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7046 05:53:05.835050 [DutyScan_Calibration_Flow] ====Done====
7047 05:53:05.835130
7048 05:53:05.838187 [DutyScan_Calibration_Flow] k_type=2
7049 05:53:05.855620
7050 05:53:05.855699 ==DQ 0 ==
7051 05:53:05.858585 Final DQ duty delay cell = 0
7052 05:53:05.861626 [0] MAX Duty = 5218%(X100), DQS PI = 18
7053 05:53:05.865311 [0] MIN Duty = 4938%(X100), DQS PI = 54
7054 05:53:05.865390 [0] AVG Duty = 5078%(X100)
7055 05:53:05.868387
7056 05:53:05.868459 ==DQ 1 ==
7057 05:53:05.871597 Final DQ duty delay cell = -4
7058 05:53:05.874909 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7059 05:53:05.878456 [-4] MIN Duty = 4844%(X100), DQS PI = 36
7060 05:53:05.881693 [-4] AVG Duty = 4953%(X100)
7061 05:53:05.881770
7062 05:53:05.884941 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7063 05:53:05.885020
7064 05:53:05.888542 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7065 05:53:05.891613 [DutyScan_Calibration_Flow] ====Done====
7066 05:53:05.891688 ==
7067 05:53:05.895003 Dram Type= 6, Freq= 0, CH_1, rank 0
7068 05:53:05.898353 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7069 05:53:05.898429 ==
7070 05:53:05.901397 [Duty_Offset_Calibration]
7071 05:53:05.901492 B0:0 B1:4 CA:-5
7072 05:53:05.901585
7073 05:53:05.905197 [DutyScan_Calibration_Flow] k_type=0
7074 05:53:05.915964
7075 05:53:05.916041 ==CLK 0==
7076 05:53:05.919051 Final CLK duty delay cell = 0
7077 05:53:05.922564 [0] MAX Duty = 5156%(X100), DQS PI = 18
7078 05:53:05.925541 [0] MIN Duty = 4875%(X100), DQS PI = 50
7079 05:53:05.928911 [0] AVG Duty = 5015%(X100)
7080 05:53:05.928987
7081 05:53:05.932432 CH1 CLK Duty spec in!! Max-Min= 281%
7082 05:53:05.935445 [DutyScan_Calibration_Flow] ====Done====
7083 05:53:05.935522
7084 05:53:05.938727 [DutyScan_Calibration_Flow] k_type=1
7085 05:53:05.954949
7086 05:53:05.955032 ==DQS 0 ==
7087 05:53:05.958040 Final DQS duty delay cell = 0
7088 05:53:05.961466 [0] MAX Duty = 5156%(X100), DQS PI = 18
7089 05:53:05.964635 [0] MIN Duty = 4907%(X100), DQS PI = 42
7090 05:53:05.967766 [0] AVG Duty = 5031%(X100)
7091 05:53:05.967841
7092 05:53:05.967902 ==DQS 1 ==
7093 05:53:05.971363 Final DQS duty delay cell = -4
7094 05:53:05.974490 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7095 05:53:05.977643 [-4] MIN Duty = 4844%(X100), DQS PI = 42
7096 05:53:05.981166 [-4] AVG Duty = 4922%(X100)
7097 05:53:05.981245
7098 05:53:05.984500 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7099 05:53:05.984600
7100 05:53:05.987551 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7101 05:53:05.991000 [DutyScan_Calibration_Flow] ====Done====
7102 05:53:05.991075
7103 05:53:05.994483 [DutyScan_Calibration_Flow] k_type=3
7104 05:53:06.010363
7105 05:53:06.010464 ==DQM 0 ==
7106 05:53:06.013890 Final DQM duty delay cell = -4
7107 05:53:06.017128 [-4] MAX Duty = 5093%(X100), DQS PI = 32
7108 05:53:06.020350 [-4] MIN Duty = 4782%(X100), DQS PI = 46
7109 05:53:06.023548 [-4] AVG Duty = 4937%(X100)
7110 05:53:06.023644
7111 05:53:06.023713 ==DQM 1 ==
7112 05:53:06.026754 Final DQM duty delay cell = -4
7113 05:53:06.030155 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7114 05:53:06.033447 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7115 05:53:06.036713 [-4] AVG Duty = 5000%(X100)
7116 05:53:06.036811
7117 05:53:06.040482 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7118 05:53:06.040563
7119 05:53:06.043455 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7120 05:53:06.046439 [DutyScan_Calibration_Flow] ====Done====
7121 05:53:06.046548
7122 05:53:06.050226 [DutyScan_Calibration_Flow] k_type=2
7123 05:53:06.068319
7124 05:53:06.068404 ==DQ 0 ==
7125 05:53:06.071454 Final DQ duty delay cell = 0
7126 05:53:06.074582 [0] MAX Duty = 5093%(X100), DQS PI = 20
7127 05:53:06.077927 [0] MIN Duty = 4969%(X100), DQS PI = 46
7128 05:53:06.078008 [0] AVG Duty = 5031%(X100)
7129 05:53:06.081148
7130 05:53:06.081229 ==DQ 1 ==
7131 05:53:06.084871 Final DQ duty delay cell = 0
7132 05:53:06.088021 [0] MAX Duty = 5031%(X100), DQS PI = 4
7133 05:53:06.091380 [0] MIN Duty = 4876%(X100), DQS PI = 28
7134 05:53:06.091461 [0] AVG Duty = 4953%(X100)
7135 05:53:06.091525
7136 05:53:06.097700 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7137 05:53:06.097781
7138 05:53:06.101557 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7139 05:53:06.104312 [DutyScan_Calibration_Flow] ====Done====
7140 05:53:06.107708 nWR fixed to 30
7141 05:53:06.107790 [ModeRegInit_LP4] CH0 RK0
7142 05:53:06.110902 [ModeRegInit_LP4] CH0 RK1
7143 05:53:06.114118 [ModeRegInit_LP4] CH1 RK0
7144 05:53:06.117454 [ModeRegInit_LP4] CH1 RK1
7145 05:53:06.117535 match AC timing 4
7146 05:53:06.124398 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7147 05:53:06.127590 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7148 05:53:06.131012 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7149 05:53:06.137181 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7150 05:53:06.140512 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7151 05:53:06.140594 [MiockJmeterHQA]
7152 05:53:06.140691
7153 05:53:06.143778 [DramcMiockJmeter] u1RxGatingPI = 0
7154 05:53:06.147673 0 : 4363, 4137
7155 05:53:06.147763 4 : 4363, 4138
7156 05:53:06.150701 8 : 4253, 4027
7157 05:53:06.150784 12 : 4252, 4027
7158 05:53:06.150850 16 : 4253, 4026
7159 05:53:06.153898 20 : 4252, 4027
7160 05:53:06.153979 24 : 4252, 4027
7161 05:53:06.157127 28 : 4252, 4027
7162 05:53:06.157238 32 : 4366, 4140
7163 05:53:06.160974 36 : 4253, 4026
7164 05:53:06.161069 40 : 4255, 4030
7165 05:53:06.164592 44 : 4253, 4026
7166 05:53:06.164673 48 : 4363, 4138
7167 05:53:06.164780 52 : 4252, 4027
7168 05:53:06.167356 56 : 4363, 4137
7169 05:53:06.167438 60 : 4250, 4027
7170 05:53:06.170816 64 : 4250, 4026
7171 05:53:06.170898 68 : 4250, 4026
7172 05:53:06.173739 72 : 4253, 4030
7173 05:53:06.173821 76 : 4361, 4137
7174 05:53:06.177086 80 : 4250, 4027
7175 05:53:06.177169 84 : 4360, 4137
7176 05:53:06.177235 88 : 4250, 4026
7177 05:53:06.180649 92 : 4250, 4027
7178 05:53:06.180772 96 : 4250, 4026
7179 05:53:06.183562 100 : 4361, 1853
7180 05:53:06.183644 104 : 4250, 0
7181 05:53:06.187291 108 : 4255, 0
7182 05:53:06.187373 112 : 4250, 0
7183 05:53:06.187438 116 : 4249, 0
7184 05:53:06.190074 120 : 4361, 0
7185 05:53:06.190156 124 : 4250, 0
7186 05:53:06.193870 128 : 4250, 0
7187 05:53:06.193952 132 : 4361, 0
7188 05:53:06.194016 136 : 4360, 0
7189 05:53:06.197064 140 : 4363, 0
7190 05:53:06.197146 144 : 4250, 0
7191 05:53:06.197221 148 : 4361, 0
7192 05:53:06.200185 152 : 4250, 0
7193 05:53:06.200268 156 : 4250, 0
7194 05:53:06.203766 160 : 4250, 0
7195 05:53:06.203848 164 : 4250, 0
7196 05:53:06.203913 168 : 4252, 0
7197 05:53:06.207178 172 : 4361, 0
7198 05:53:06.207260 176 : 4250, 0
7199 05:53:06.210234 180 : 4250, 0
7200 05:53:06.210316 184 : 4250, 0
7201 05:53:06.210382 188 : 4360, 0
7202 05:53:06.213625 192 : 4361, 0
7203 05:53:06.213708 196 : 4250, 0
7204 05:53:06.216779 200 : 4250, 0
7205 05:53:06.216861 204 : 4250, 0
7206 05:53:06.216927 208 : 4253, 0
7207 05:53:06.220211 212 : 4250, 0
7208 05:53:06.220293 216 : 4250, 0
7209 05:53:06.223371 220 : 4252, 787
7210 05:53:06.223453 224 : 4250, 4011
7211 05:53:06.226945 228 : 4250, 4026
7212 05:53:06.227046 232 : 4250, 4027
7213 05:53:06.227142 236 : 4250, 4027
7214 05:53:06.229877 240 : 4250, 4027
7215 05:53:06.229959 244 : 4250, 4026
7216 05:53:06.233209 248 : 4250, 4027
7217 05:53:06.233291 252 : 4252, 4030
7218 05:53:06.236388 256 : 4250, 4027
7219 05:53:06.236470 260 : 4360, 4137
7220 05:53:06.239957 264 : 4361, 4137
7221 05:53:06.240039 268 : 4250, 4027
7222 05:53:06.243409 272 : 4363, 4140
7223 05:53:06.243492 276 : 4250, 4027
7224 05:53:06.246439 280 : 4250, 4026
7225 05:53:06.246521 284 : 4253, 4029
7226 05:53:06.249987 288 : 4252, 4030
7227 05:53:06.250069 292 : 4250, 4027
7228 05:53:06.253419 296 : 4252, 4029
7229 05:53:06.253500 300 : 4250, 4027
7230 05:53:06.253566 304 : 4252, 4030
7231 05:53:06.256921 308 : 4250, 4027
7232 05:53:06.257004 312 : 4360, 4137
7233 05:53:06.259647 316 : 4361, 4137
7234 05:53:06.259729 320 : 4250, 4027
7235 05:53:06.263213 324 : 4363, 4140
7236 05:53:06.263295 328 : 4250, 4027
7237 05:53:06.266481 332 : 4250, 4026
7238 05:53:06.266564 336 : 4250, 3963
7239 05:53:06.269634 340 : 4253, 2045
7240 05:53:06.269716
7241 05:53:06.269781 MIOCK jitter meter ch=0
7242 05:53:06.269841
7243 05:53:06.272834 1T = (340-100) = 240 dly cells
7244 05:53:06.279569 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7245 05:53:06.279651 ==
7246 05:53:06.283097 Dram Type= 6, Freq= 0, CH_0, rank 0
7247 05:53:06.286332 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7248 05:53:06.286413 ==
7249 05:53:06.292605 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7250 05:53:06.296386 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7251 05:53:06.302591 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7252 05:53:06.305983 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7253 05:53:06.315299 [CA 0] Center 42 (12~73) winsize 62
7254 05:53:06.318500 [CA 1] Center 42 (12~73) winsize 62
7255 05:53:06.321932 [CA 2] Center 39 (9~69) winsize 61
7256 05:53:06.325222 [CA 3] Center 38 (9~68) winsize 60
7257 05:53:06.328463 [CA 4] Center 36 (6~67) winsize 62
7258 05:53:06.331938 [CA 5] Center 36 (6~66) winsize 61
7259 05:53:06.332012
7260 05:53:06.335127 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7261 05:53:06.335221
7262 05:53:06.338532 [CATrainingPosCal] consider 1 rank data
7263 05:53:06.342111 u2DelayCellTimex100 = 271/100 ps
7264 05:53:06.345097 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7265 05:53:06.351795 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7266 05:53:06.355087 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7267 05:53:06.358386 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7268 05:53:06.361983 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
7269 05:53:06.364922 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7270 05:53:06.364996
7271 05:53:06.368350 CA PerBit enable=1, Macro0, CA PI delay=36
7272 05:53:06.368446
7273 05:53:06.371291 [CBTSetCACLKResult] CA Dly = 36
7274 05:53:06.375038 CS Dly: 10 (0~41)
7275 05:53:06.378359 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7276 05:53:06.382123 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7277 05:53:06.382215 ==
7278 05:53:06.385215 Dram Type= 6, Freq= 0, CH_0, rank 1
7279 05:53:06.388152 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7280 05:53:06.391638 ==
7281 05:53:06.394777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7282 05:53:06.397979 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7283 05:53:06.404487 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7284 05:53:06.411157 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7285 05:53:06.417762 [CA 0] Center 42 (12~73) winsize 62
7286 05:53:06.421049 [CA 1] Center 42 (12~73) winsize 62
7287 05:53:06.424527 [CA 2] Center 38 (9~68) winsize 60
7288 05:53:06.428359 [CA 3] Center 37 (8~67) winsize 60
7289 05:53:06.431296 [CA 4] Center 36 (6~66) winsize 61
7290 05:53:06.434242 [CA 5] Center 36 (6~66) winsize 61
7291 05:53:06.434317
7292 05:53:06.438190 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7293 05:53:06.438261
7294 05:53:06.441306 [CATrainingPosCal] consider 2 rank data
7295 05:53:06.444726 u2DelayCellTimex100 = 271/100 ps
7296 05:53:06.447646 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7297 05:53:06.454338 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7298 05:53:06.457663 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7299 05:53:06.461296 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7300 05:53:06.464407 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7301 05:53:06.467531 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7302 05:53:06.467611
7303 05:53:06.470891 CA PerBit enable=1, Macro0, CA PI delay=36
7304 05:53:06.470971
7305 05:53:06.474645 [CBTSetCACLKResult] CA Dly = 36
7306 05:53:06.477826 CS Dly: 10 (0~42)
7307 05:53:06.480833 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7308 05:53:06.484534 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7309 05:53:06.484613
7310 05:53:06.487505 ----->DramcWriteLeveling(PI) begin...
7311 05:53:06.487591 ==
7312 05:53:06.490848 Dram Type= 6, Freq= 0, CH_0, rank 0
7313 05:53:06.497665 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7314 05:53:06.497773 ==
7315 05:53:06.501034 Write leveling (Byte 0): 30 => 30
7316 05:53:06.501118 Write leveling (Byte 1): 27 => 27
7317 05:53:06.504468 DramcWriteLeveling(PI) end<-----
7318 05:53:06.504562
7319 05:53:06.504648 ==
7320 05:53:06.507842 Dram Type= 6, Freq= 0, CH_0, rank 0
7321 05:53:06.513939 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7322 05:53:06.514014 ==
7323 05:53:06.517216 [Gating] SW mode calibration
7324 05:53:06.524042 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7325 05:53:06.527292 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7326 05:53:06.533910 0 12 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7327 05:53:06.537174 0 12 4 | B1->B0 | 2525 3333 | 0 1 | (0 0) (0 0)
7328 05:53:06.540549 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7329 05:53:06.547036 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7330 05:53:06.550177 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7331 05:53:06.553850 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7332 05:53:06.560121 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7333 05:53:06.563548 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7334 05:53:06.566962 0 13 0 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7335 05:53:06.573488 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (1 0)
7336 05:53:06.576656 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7337 05:53:06.580104 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7338 05:53:06.586733 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7339 05:53:06.590374 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7340 05:53:06.593533 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7341 05:53:06.600299 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7342 05:53:06.603257 0 14 0 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7343 05:53:06.606681 0 14 4 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
7344 05:53:06.613430 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7345 05:53:06.616634 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7346 05:53:06.619794 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7347 05:53:06.626690 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7348 05:53:06.629717 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7349 05:53:06.632816 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7350 05:53:06.639522 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7351 05:53:06.642857 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7352 05:53:06.646314 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7353 05:53:06.652781 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 05:53:06.656157 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7355 05:53:06.659417 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 05:53:06.665648 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 05:53:06.669432 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 05:53:06.672502 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 05:53:06.679213 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 05:53:06.682672 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7361 05:53:06.685755 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7362 05:53:06.692166 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7363 05:53:06.695448 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7364 05:53:06.698885 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7365 05:53:06.705349 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7366 05:53:06.708604 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7367 05:53:06.712186 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7368 05:53:06.718690 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7369 05:53:06.718765 Total UI for P1: 0, mck2ui 16
7370 05:53:06.725418 best dqsien dly found for B0: ( 1, 1, 4)
7371 05:53:06.728676 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7372 05:53:06.732083 Total UI for P1: 0, mck2ui 16
7373 05:53:06.735028 best dqsien dly found for B1: ( 1, 1, 6)
7374 05:53:06.738746 best DQS0 dly(MCK, UI, PI) = (1, 1, 4)
7375 05:53:06.741490 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7376 05:53:06.741583
7377 05:53:06.744933 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 4)
7378 05:53:06.748605 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7379 05:53:06.751553 [Gating] SW calibration Done
7380 05:53:06.751654 ==
7381 05:53:06.754829 Dram Type= 6, Freq= 0, CH_0, rank 0
7382 05:53:06.758510 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7383 05:53:06.758611 ==
7384 05:53:06.761475 RX Vref Scan: 0
7385 05:53:06.761576
7386 05:53:06.764685 RX Vref 0 -> 0, step: 1
7387 05:53:06.764800
7388 05:53:06.764862 RX Delay 0 -> 252, step: 8
7389 05:53:06.771764 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7390 05:53:06.774682 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7391 05:53:06.778084 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7392 05:53:06.781630 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7393 05:53:06.784880 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7394 05:53:06.791337 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7395 05:53:06.794403 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7396 05:53:06.797778 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7397 05:53:06.801056 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7398 05:53:06.804307 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7399 05:53:06.811092 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7400 05:53:06.814561 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7401 05:53:06.818113 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7402 05:53:06.820933 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7403 05:53:06.827985 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7404 05:53:06.830965 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7405 05:53:06.831037 ==
7406 05:53:06.834221 Dram Type= 6, Freq= 0, CH_0, rank 0
7407 05:53:06.837657 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7408 05:53:06.837729 ==
7409 05:53:06.840632 DQS Delay:
7410 05:53:06.840746 DQS0 = 0, DQS1 = 0
7411 05:53:06.840821 DQM Delay:
7412 05:53:06.844326 DQM0 = 130, DQM1 = 125
7413 05:53:06.844419 DQ Delay:
7414 05:53:06.847454 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7415 05:53:06.850626 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7416 05:53:06.853966 DQ8 =115, DQ9 =107, DQ10 =127, DQ11 =115
7417 05:53:06.860331 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7418 05:53:06.860430
7419 05:53:06.860523
7420 05:53:06.860609 ==
7421 05:53:06.863827 Dram Type= 6, Freq= 0, CH_0, rank 0
7422 05:53:06.867057 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7423 05:53:06.867152 ==
7424 05:53:06.867242
7425 05:53:06.867335
7426 05:53:06.870215 TX Vref Scan disable
7427 05:53:06.870297 == TX Byte 0 ==
7428 05:53:06.876929 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7429 05:53:06.880112 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7430 05:53:06.880187 == TX Byte 1 ==
7431 05:53:06.886912 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7432 05:53:06.890317 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7433 05:53:06.890392 ==
7434 05:53:06.893735 Dram Type= 6, Freq= 0, CH_0, rank 0
7435 05:53:06.896923 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7436 05:53:06.896997 ==
7437 05:53:06.912161
7438 05:53:06.915166 TX Vref early break, caculate TX vref
7439 05:53:06.918991 TX Vref=16, minBit 8, minWin=22, winSum=371
7440 05:53:06.921808 TX Vref=18, minBit 8, minWin=22, winSum=382
7441 05:53:06.925518 TX Vref=20, minBit 8, minWin=23, winSum=391
7442 05:53:06.928911 TX Vref=22, minBit 8, minWin=23, winSum=395
7443 05:53:06.932187 TX Vref=24, minBit 8, minWin=24, winSum=406
7444 05:53:06.938226 TX Vref=26, minBit 8, minWin=24, winSum=413
7445 05:53:06.941589 TX Vref=28, minBit 3, minWin=25, winSum=415
7446 05:53:06.945167 TX Vref=30, minBit 0, minWin=25, winSum=411
7447 05:53:06.948148 TX Vref=32, minBit 2, minWin=24, winSum=398
7448 05:53:06.952129 TX Vref=34, minBit 0, minWin=24, winSum=397
7449 05:53:06.955169 TX Vref=36, minBit 0, minWin=23, winSum=384
7450 05:53:06.961466 [TxChooseVref] Worse bit 3, Min win 25, Win sum 415, Final Vref 28
7451 05:53:06.961567
7452 05:53:06.964847 Final TX Range 0 Vref 28
7453 05:53:06.964921
7454 05:53:06.964990 ==
7455 05:53:06.968020 Dram Type= 6, Freq= 0, CH_0, rank 0
7456 05:53:06.971740 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7457 05:53:06.971838 ==
7458 05:53:06.974891
7459 05:53:06.974988
7460 05:53:06.975076 TX Vref Scan disable
7461 05:53:06.981292 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7462 05:53:06.981430 == TX Byte 0 ==
7463 05:53:06.984607 u2DelayCellOfst[0]=14 cells (4 PI)
7464 05:53:06.988291 u2DelayCellOfst[1]=18 cells (5 PI)
7465 05:53:06.991143 u2DelayCellOfst[2]=14 cells (4 PI)
7466 05:53:06.994546 u2DelayCellOfst[3]=14 cells (4 PI)
7467 05:53:06.997903 u2DelayCellOfst[4]=10 cells (3 PI)
7468 05:53:07.001204 u2DelayCellOfst[5]=0 cells (0 PI)
7469 05:53:07.004921 u2DelayCellOfst[6]=18 cells (5 PI)
7470 05:53:07.008123 u2DelayCellOfst[7]=18 cells (5 PI)
7471 05:53:07.011416 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7472 05:53:07.014630 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7473 05:53:07.018027 == TX Byte 1 ==
7474 05:53:07.021178 u2DelayCellOfst[8]=0 cells (0 PI)
7475 05:53:07.024513 u2DelayCellOfst[9]=0 cells (0 PI)
7476 05:53:07.027725 u2DelayCellOfst[10]=7 cells (2 PI)
7477 05:53:07.030967 u2DelayCellOfst[11]=3 cells (1 PI)
7478 05:53:07.034759 u2DelayCellOfst[12]=14 cells (4 PI)
7479 05:53:07.034837 u2DelayCellOfst[13]=10 cells (3 PI)
7480 05:53:07.037683 u2DelayCellOfst[14]=18 cells (5 PI)
7481 05:53:07.040980 u2DelayCellOfst[15]=14 cells (4 PI)
7482 05:53:07.047593 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7483 05:53:07.051360 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7484 05:53:07.051460 DramC Write-DBI on
7485 05:53:07.054163 ==
7486 05:53:07.057504 Dram Type= 6, Freq= 0, CH_0, rank 0
7487 05:53:07.060859 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7488 05:53:07.060931 ==
7489 05:53:07.060992
7490 05:53:07.061050
7491 05:53:07.063951 TX Vref Scan disable
7492 05:53:07.064021 == TX Byte 0 ==
7493 05:53:07.070604 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7494 05:53:07.070681 == TX Byte 1 ==
7495 05:53:07.073965 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7496 05:53:07.077280 DramC Write-DBI off
7497 05:53:07.077378
7498 05:53:07.077466 [DATLAT]
7499 05:53:07.080577 Freq=1600, CH0 RK0
7500 05:53:07.080672
7501 05:53:07.080781 DATLAT Default: 0xf
7502 05:53:07.083860 0, 0xFFFF, sum = 0
7503 05:53:07.083957 1, 0xFFFF, sum = 0
7504 05:53:07.087079 2, 0xFFFF, sum = 0
7505 05:53:07.087151 3, 0xFFFF, sum = 0
7506 05:53:07.090377 4, 0xFFFF, sum = 0
7507 05:53:07.090451 5, 0xFFFF, sum = 0
7508 05:53:07.093814 6, 0xFFFF, sum = 0
7509 05:53:07.097037 7, 0xFFFF, sum = 0
7510 05:53:07.097137 8, 0xFFFF, sum = 0
7511 05:53:07.100537 9, 0xFFFF, sum = 0
7512 05:53:07.100609 10, 0xFFFF, sum = 0
7513 05:53:07.103661 11, 0xFFFF, sum = 0
7514 05:53:07.103767 12, 0xFFF, sum = 0
7515 05:53:07.106962 13, 0x0, sum = 1
7516 05:53:07.107039 14, 0x0, sum = 2
7517 05:53:07.110091 15, 0x0, sum = 3
7518 05:53:07.110180 16, 0x0, sum = 4
7519 05:53:07.113869 best_step = 14
7520 05:53:07.113957
7521 05:53:07.114019 ==
7522 05:53:07.117138 Dram Type= 6, Freq= 0, CH_0, rank 0
7523 05:53:07.119954 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7524 05:53:07.120042 ==
7525 05:53:07.120109 RX Vref Scan: 1
7526 05:53:07.120168
7527 05:53:07.123617 Set Vref Range= 24 -> 127
7528 05:53:07.123686
7529 05:53:07.127038 RX Vref 24 -> 127, step: 1
7530 05:53:07.127181
7531 05:53:07.130151 RX Delay 11 -> 252, step: 4
7532 05:53:07.130249
7533 05:53:07.133766 Set Vref, RX VrefLevel [Byte0]: 24
7534 05:53:07.136832 [Byte1]: 24
7535 05:53:07.136904
7536 05:53:07.140051 Set Vref, RX VrefLevel [Byte0]: 25
7537 05:53:07.142998 [Byte1]: 25
7538 05:53:07.143139
7539 05:53:07.146142 Set Vref, RX VrefLevel [Byte0]: 26
7540 05:53:07.150153 [Byte1]: 26
7541 05:53:07.154050
7542 05:53:07.154156 Set Vref, RX VrefLevel [Byte0]: 27
7543 05:53:07.157066 [Byte1]: 27
7544 05:53:07.161419
7545 05:53:07.161525 Set Vref, RX VrefLevel [Byte0]: 28
7546 05:53:07.164965 [Byte1]: 28
7547 05:53:07.169043
7548 05:53:07.169118 Set Vref, RX VrefLevel [Byte0]: 29
7549 05:53:07.172501 [Byte1]: 29
7550 05:53:07.176989
7551 05:53:07.177063 Set Vref, RX VrefLevel [Byte0]: 30
7552 05:53:07.179736 [Byte1]: 30
7553 05:53:07.184089
7554 05:53:07.184188 Set Vref, RX VrefLevel [Byte0]: 31
7555 05:53:07.187705 [Byte1]: 31
7556 05:53:07.191951
7557 05:53:07.192050 Set Vref, RX VrefLevel [Byte0]: 32
7558 05:53:07.195213 [Byte1]: 32
7559 05:53:07.199480
7560 05:53:07.199580 Set Vref, RX VrefLevel [Byte0]: 33
7561 05:53:07.202909 [Byte1]: 33
7562 05:53:07.207301
7563 05:53:07.207394 Set Vref, RX VrefLevel [Byte0]: 34
7564 05:53:07.210442 [Byte1]: 34
7565 05:53:07.214726
7566 05:53:07.214826 Set Vref, RX VrefLevel [Byte0]: 35
7567 05:53:07.218281 [Byte1]: 35
7568 05:53:07.222686
7569 05:53:07.222793 Set Vref, RX VrefLevel [Byte0]: 36
7570 05:53:07.225849 [Byte1]: 36
7571 05:53:07.230207
7572 05:53:07.230317 Set Vref, RX VrefLevel [Byte0]: 37
7573 05:53:07.233268 [Byte1]: 37
7574 05:53:07.237855
7575 05:53:07.237931 Set Vref, RX VrefLevel [Byte0]: 38
7576 05:53:07.241061 [Byte1]: 38
7577 05:53:07.245172
7578 05:53:07.245244 Set Vref, RX VrefLevel [Byte0]: 39
7579 05:53:07.248348 [Byte1]: 39
7580 05:53:07.252873
7581 05:53:07.252963 Set Vref, RX VrefLevel [Byte0]: 40
7582 05:53:07.256028 [Byte1]: 40
7583 05:53:07.260463
7584 05:53:07.260572 Set Vref, RX VrefLevel [Byte0]: 41
7585 05:53:07.263975 [Byte1]: 41
7586 05:53:07.268044
7587 05:53:07.268149 Set Vref, RX VrefLevel [Byte0]: 42
7588 05:53:07.271651 [Byte1]: 42
7589 05:53:07.275938
7590 05:53:07.276038 Set Vref, RX VrefLevel [Byte0]: 43
7591 05:53:07.279197 [Byte1]: 43
7592 05:53:07.283552
7593 05:53:07.283627 Set Vref, RX VrefLevel [Byte0]: 44
7594 05:53:07.286801 [Byte1]: 44
7595 05:53:07.290781
7596 05:53:07.290861 Set Vref, RX VrefLevel [Byte0]: 45
7597 05:53:07.294569 [Byte1]: 45
7598 05:53:07.298355
7599 05:53:07.298429 Set Vref, RX VrefLevel [Byte0]: 46
7600 05:53:07.301717 [Byte1]: 46
7601 05:53:07.306663
7602 05:53:07.306738 Set Vref, RX VrefLevel [Byte0]: 47
7603 05:53:07.309742 [Byte1]: 47
7604 05:53:07.313740
7605 05:53:07.313813 Set Vref, RX VrefLevel [Byte0]: 48
7606 05:53:07.317343 [Byte1]: 48
7607 05:53:07.321830
7608 05:53:07.321919 Set Vref, RX VrefLevel [Byte0]: 49
7609 05:53:07.324649 [Byte1]: 49
7610 05:53:07.328835
7611 05:53:07.328916 Set Vref, RX VrefLevel [Byte0]: 50
7612 05:53:07.332271 [Byte1]: 50
7613 05:53:07.336793
7614 05:53:07.336892 Set Vref, RX VrefLevel [Byte0]: 51
7615 05:53:07.340101 [Byte1]: 51
7616 05:53:07.344353
7617 05:53:07.344459 Set Vref, RX VrefLevel [Byte0]: 52
7618 05:53:07.347476 [Byte1]: 52
7619 05:53:07.351592
7620 05:53:07.351693 Set Vref, RX VrefLevel [Byte0]: 53
7621 05:53:07.355193 [Byte1]: 53
7622 05:53:07.359667
7623 05:53:07.359768 Set Vref, RX VrefLevel [Byte0]: 54
7624 05:53:07.362896 [Byte1]: 54
7625 05:53:07.367059
7626 05:53:07.367159 Set Vref, RX VrefLevel [Byte0]: 55
7627 05:53:07.370404 [Byte1]: 55
7628 05:53:07.374660
7629 05:53:07.374745 Set Vref, RX VrefLevel [Byte0]: 56
7630 05:53:07.378230 [Byte1]: 56
7631 05:53:07.382351
7632 05:53:07.382429 Set Vref, RX VrefLevel [Byte0]: 57
7633 05:53:07.385393 [Byte1]: 57
7634 05:53:07.390123
7635 05:53:07.390226 Set Vref, RX VrefLevel [Byte0]: 58
7636 05:53:07.393253 [Byte1]: 58
7637 05:53:07.397603
7638 05:53:07.397703 Set Vref, RX VrefLevel [Byte0]: 59
7639 05:53:07.400983 [Byte1]: 59
7640 05:53:07.405241
7641 05:53:07.405318 Set Vref, RX VrefLevel [Byte0]: 60
7642 05:53:07.408395 [Byte1]: 60
7643 05:53:07.412667
7644 05:53:07.412801 Set Vref, RX VrefLevel [Byte0]: 61
7645 05:53:07.416075 [Byte1]: 61
7646 05:53:07.420112
7647 05:53:07.420214 Set Vref, RX VrefLevel [Byte0]: 62
7648 05:53:07.423825 [Byte1]: 62
7649 05:53:07.428286
7650 05:53:07.428394 Set Vref, RX VrefLevel [Byte0]: 63
7651 05:53:07.431561 [Byte1]: 63
7652 05:53:07.435661
7653 05:53:07.435736 Set Vref, RX VrefLevel [Byte0]: 64
7654 05:53:07.438978 [Byte1]: 64
7655 05:53:07.443417
7656 05:53:07.443490 Set Vref, RX VrefLevel [Byte0]: 65
7657 05:53:07.446393 [Byte1]: 65
7658 05:53:07.450612
7659 05:53:07.450693 Set Vref, RX VrefLevel [Byte0]: 66
7660 05:53:07.454223 [Byte1]: 66
7661 05:53:07.458672
7662 05:53:07.458774 Set Vref, RX VrefLevel [Byte0]: 67
7663 05:53:07.461998 [Byte1]: 67
7664 05:53:07.466105
7665 05:53:07.466186 Set Vref, RX VrefLevel [Byte0]: 68
7666 05:53:07.469173 [Byte1]: 68
7667 05:53:07.473929
7668 05:53:07.474021 Set Vref, RX VrefLevel [Byte0]: 69
7669 05:53:07.476655 [Byte1]: 69
7670 05:53:07.481290
7671 05:53:07.481394 Set Vref, RX VrefLevel [Byte0]: 70
7672 05:53:07.484599 [Byte1]: 70
7673 05:53:07.488852
7674 05:53:07.488956 Final RX Vref Byte 0 = 53 to rank0
7675 05:53:07.492377 Final RX Vref Byte 1 = 55 to rank0
7676 05:53:07.495552 Final RX Vref Byte 0 = 53 to rank1
7677 05:53:07.498604 Final RX Vref Byte 1 = 55 to rank1==
7678 05:53:07.502224 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 05:53:07.508915 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7680 05:53:07.508997 ==
7681 05:53:07.509062 DQS Delay:
7682 05:53:07.512013 DQS0 = 0, DQS1 = 0
7683 05:53:07.512094 DQM Delay:
7684 05:53:07.512157 DQM0 = 127, DQM1 = 121
7685 05:53:07.515567 DQ Delay:
7686 05:53:07.518486 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =124
7687 05:53:07.521854 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7688 05:53:07.525345 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7689 05:53:07.529026 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7690 05:53:07.529106
7691 05:53:07.529188
7692 05:53:07.529267
7693 05:53:07.531763 [DramC_TX_OE_Calibration] TA2
7694 05:53:07.535359 Original DQ_B0 (3 6) =30, OEN = 27
7695 05:53:07.538331 Original DQ_B1 (3 6) =30, OEN = 27
7696 05:53:07.541939 24, 0x0, End_B0=24 End_B1=24
7697 05:53:07.542020 25, 0x0, End_B0=25 End_B1=25
7698 05:53:07.545055 26, 0x0, End_B0=26 End_B1=26
7699 05:53:07.548275 27, 0x0, End_B0=27 End_B1=27
7700 05:53:07.551356 28, 0x0, End_B0=28 End_B1=28
7701 05:53:07.555165 29, 0x0, End_B0=29 End_B1=29
7702 05:53:07.555265 30, 0x0, End_B0=30 End_B1=30
7703 05:53:07.558376 31, 0x4141, End_B0=30 End_B1=30
7704 05:53:07.561714 Byte0 end_step=30 best_step=27
7705 05:53:07.564782 Byte1 end_step=30 best_step=27
7706 05:53:07.568071 Byte0 TX OE(2T, 0.5T) = (3, 3)
7707 05:53:07.571656 Byte1 TX OE(2T, 0.5T) = (3, 3)
7708 05:53:07.571751
7709 05:53:07.571846
7710 05:53:07.578203 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7711 05:53:07.582008 CH0 RK0: MR19=303, MR18=1515
7712 05:53:07.588373 CH0_RK0: MR19=0x303, MR18=0x1515, DQSOSC=399, MR23=63, INC=23, DEC=15
7713 05:53:07.588448
7714 05:53:07.591614 ----->DramcWriteLeveling(PI) begin...
7715 05:53:07.591696 ==
7716 05:53:07.594701 Dram Type= 6, Freq= 0, CH_0, rank 1
7717 05:53:07.598143 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7718 05:53:07.598245 ==
7719 05:53:07.601477 Write leveling (Byte 0): 28 => 28
7720 05:53:07.604879 Write leveling (Byte 1): 26 => 26
7721 05:53:07.607900 DramcWriteLeveling(PI) end<-----
7722 05:53:07.607976
7723 05:53:07.608075 ==
7724 05:53:07.611351 Dram Type= 6, Freq= 0, CH_0, rank 1
7725 05:53:07.614543 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7726 05:53:07.614621 ==
7727 05:53:07.617869 [Gating] SW mode calibration
7728 05:53:07.624639 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7729 05:53:07.631060 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7730 05:53:07.634178 0 12 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
7731 05:53:07.640961 0 12 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7732 05:53:07.644209 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7733 05:53:07.647516 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7734 05:53:07.654392 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7735 05:53:07.657550 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7736 05:53:07.660621 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7737 05:53:07.667635 0 12 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7738 05:53:07.670492 0 13 0 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
7739 05:53:07.673864 0 13 4 | B1->B0 | 3333 2323 | 0 0 | (0 1) (1 0)
7740 05:53:07.680436 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7741 05:53:07.683883 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7742 05:53:07.687179 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7743 05:53:07.693447 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7744 05:53:07.697293 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7745 05:53:07.700148 0 13 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7746 05:53:07.706919 0 14 0 | B1->B0 | 2424 4141 | 0 0 | (0 0) (0 0)
7747 05:53:07.710089 0 14 4 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
7748 05:53:07.713279 0 14 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7749 05:53:07.720080 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7750 05:53:07.723466 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7751 05:53:07.726618 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7752 05:53:07.733041 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7753 05:53:07.736430 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7754 05:53:07.740010 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7755 05:53:07.746513 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7756 05:53:07.749922 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7757 05:53:07.753223 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 05:53:07.759552 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 05:53:07.763108 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 05:53:07.766221 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 05:53:07.772945 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7762 05:53:07.776372 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 05:53:07.779603 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7764 05:53:07.786009 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7765 05:53:07.789111 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7766 05:53:07.792692 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7767 05:53:07.799610 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7768 05:53:07.802725 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7769 05:53:07.806072 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7770 05:53:07.812823 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7771 05:53:07.816009 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7772 05:53:07.819164 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7773 05:53:07.823037 Total UI for P1: 0, mck2ui 16
7774 05:53:07.825934 best dqsien dly found for B0: ( 1, 0, 30)
7775 05:53:07.828935 Total UI for P1: 0, mck2ui 16
7776 05:53:07.832456 best dqsien dly found for B1: ( 1, 1, 4)
7777 05:53:07.836038 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7778 05:53:07.839054 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7779 05:53:07.839149
7780 05:53:07.842581 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7781 05:53:07.849243 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7782 05:53:07.849321 [Gating] SW calibration Done
7783 05:53:07.849384 ==
7784 05:53:07.852315 Dram Type= 6, Freq= 0, CH_0, rank 1
7785 05:53:07.859100 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7786 05:53:07.859197 ==
7787 05:53:07.859287 RX Vref Scan: 0
7788 05:53:07.859375
7789 05:53:07.861996 RX Vref 0 -> 0, step: 1
7790 05:53:07.862067
7791 05:53:07.865815 RX Delay 0 -> 252, step: 8
7792 05:53:07.868871 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7793 05:53:07.872012 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7794 05:53:07.875232 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7795 05:53:07.881749 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7796 05:53:07.885441 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7797 05:53:07.888474 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7798 05:53:07.891899 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7799 05:53:07.895331 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7800 05:53:07.901664 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7801 05:53:07.905335 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7802 05:53:07.908321 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7803 05:53:07.911651 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7804 05:53:07.914863 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7805 05:53:07.921188 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7806 05:53:07.924865 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7807 05:53:07.927912 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7808 05:53:07.927988 ==
7809 05:53:07.931414 Dram Type= 6, Freq= 0, CH_0, rank 1
7810 05:53:07.934669 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7811 05:53:07.937914 ==
7812 05:53:07.937989 DQS Delay:
7813 05:53:07.938071 DQS0 = 0, DQS1 = 0
7814 05:53:07.941163 DQM Delay:
7815 05:53:07.941237 DQM0 = 130, DQM1 = 124
7816 05:53:07.944542 DQ Delay:
7817 05:53:07.947939 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7818 05:53:07.951237 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7819 05:53:07.954727 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7820 05:53:07.957942 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7821 05:53:07.958018
7822 05:53:07.958116
7823 05:53:07.958211 ==
7824 05:53:07.961140 Dram Type= 6, Freq= 0, CH_0, rank 1
7825 05:53:07.964966 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7826 05:53:07.965043 ==
7827 05:53:07.965125
7828 05:53:07.967893
7829 05:53:07.967967 TX Vref Scan disable
7830 05:53:07.971286 == TX Byte 0 ==
7831 05:53:07.974459 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7832 05:53:07.977722 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7833 05:53:07.981008 == TX Byte 1 ==
7834 05:53:07.984469 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7835 05:53:07.987735 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7836 05:53:07.987809 ==
7837 05:53:07.991003 Dram Type= 6, Freq= 0, CH_0, rank 1
7838 05:53:07.997641 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7839 05:53:07.997721 ==
7840 05:53:08.009201
7841 05:53:08.012844 TX Vref early break, caculate TX vref
7842 05:53:08.015826 TX Vref=16, minBit 9, minWin=22, winSum=374
7843 05:53:08.019300 TX Vref=18, minBit 11, minWin=22, winSum=380
7844 05:53:08.022862 TX Vref=20, minBit 9, minWin=23, winSum=391
7845 05:53:08.025870 TX Vref=22, minBit 8, minWin=24, winSum=401
7846 05:53:08.029005 TX Vref=24, minBit 8, minWin=24, winSum=411
7847 05:53:08.035389 TX Vref=26, minBit 1, minWin=24, winSum=413
7848 05:53:08.038781 TX Vref=28, minBit 1, minWin=25, winSum=418
7849 05:53:08.042120 TX Vref=30, minBit 8, minWin=24, winSum=410
7850 05:53:08.045327 TX Vref=32, minBit 3, minWin=24, winSum=401
7851 05:53:08.048620 TX Vref=34, minBit 8, minWin=23, winSum=396
7852 05:53:08.055449 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 28
7853 05:53:08.055553
7854 05:53:08.058816 Final TX Range 0 Vref 28
7855 05:53:08.058915
7856 05:53:08.059012 ==
7857 05:53:08.062271 Dram Type= 6, Freq= 0, CH_0, rank 1
7858 05:53:08.065346 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7859 05:53:08.065424 ==
7860 05:53:08.065504
7861 05:53:08.065585
7862 05:53:08.068472 TX Vref Scan disable
7863 05:53:08.075067 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7864 05:53:08.075168 == TX Byte 0 ==
7865 05:53:08.078644 u2DelayCellOfst[0]=14 cells (4 PI)
7866 05:53:08.081678 u2DelayCellOfst[1]=18 cells (5 PI)
7867 05:53:08.085037 u2DelayCellOfst[2]=14 cells (4 PI)
7868 05:53:08.088400 u2DelayCellOfst[3]=14 cells (4 PI)
7869 05:53:08.092492 u2DelayCellOfst[4]=10 cells (3 PI)
7870 05:53:08.094778 u2DelayCellOfst[5]=0 cells (0 PI)
7871 05:53:08.098365 u2DelayCellOfst[6]=18 cells (5 PI)
7872 05:53:08.101921 u2DelayCellOfst[7]=18 cells (5 PI)
7873 05:53:08.104830 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7874 05:53:08.108024 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7875 05:53:08.111481 == TX Byte 1 ==
7876 05:53:08.114921 u2DelayCellOfst[8]=3 cells (1 PI)
7877 05:53:08.118216 u2DelayCellOfst[9]=0 cells (0 PI)
7878 05:53:08.121556 u2DelayCellOfst[10]=10 cells (3 PI)
7879 05:53:08.121638 u2DelayCellOfst[11]=3 cells (1 PI)
7880 05:53:08.124863 u2DelayCellOfst[12]=14 cells (4 PI)
7881 05:53:08.128072 u2DelayCellOfst[13]=14 cells (4 PI)
7882 05:53:08.131399 u2DelayCellOfst[14]=18 cells (5 PI)
7883 05:53:08.134507 u2DelayCellOfst[15]=14 cells (4 PI)
7884 05:53:08.141348 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7885 05:53:08.144391 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7886 05:53:08.144491 DramC Write-DBI on
7887 05:53:08.147816 ==
7888 05:53:08.147896 Dram Type= 6, Freq= 0, CH_0, rank 1
7889 05:53:08.154586 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7890 05:53:08.154665 ==
7891 05:53:08.154748
7892 05:53:08.154827
7893 05:53:08.157937 TX Vref Scan disable
7894 05:53:08.158013 == TX Byte 0 ==
7895 05:53:08.164599 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7896 05:53:08.164702 == TX Byte 1 ==
7897 05:53:08.168153 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7898 05:53:08.171241 DramC Write-DBI off
7899 05:53:08.171342
7900 05:53:08.171439 [DATLAT]
7901 05:53:08.174210 Freq=1600, CH0 RK1
7902 05:53:08.174311
7903 05:53:08.174408 DATLAT Default: 0xe
7904 05:53:08.177711 0, 0xFFFF, sum = 0
7905 05:53:08.177806 1, 0xFFFF, sum = 0
7906 05:53:08.180839 2, 0xFFFF, sum = 0
7907 05:53:08.180958 3, 0xFFFF, sum = 0
7908 05:53:08.184322 4, 0xFFFF, sum = 0
7909 05:53:08.184424 5, 0xFFFF, sum = 0
7910 05:53:08.187622 6, 0xFFFF, sum = 0
7911 05:53:08.187701 7, 0xFFFF, sum = 0
7912 05:53:08.190703 8, 0xFFFF, sum = 0
7913 05:53:08.190803 9, 0xFFFF, sum = 0
7914 05:53:08.194473 10, 0xFFFF, sum = 0
7915 05:53:08.197384 11, 0xFFFF, sum = 0
7916 05:53:08.197485 12, 0x8FFF, sum = 0
7917 05:53:08.200605 13, 0x0, sum = 1
7918 05:53:08.200726 14, 0x0, sum = 2
7919 05:53:08.204170 15, 0x0, sum = 3
7920 05:53:08.204275 16, 0x0, sum = 4
7921 05:53:08.204377 best_step = 14
7922 05:53:08.204474
7923 05:53:08.207293 ==
7924 05:53:08.210617 Dram Type= 6, Freq= 0, CH_0, rank 1
7925 05:53:08.214456 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7926 05:53:08.214536 ==
7927 05:53:08.214599 RX Vref Scan: 0
7928 05:53:08.214658
7929 05:53:08.217333 RX Vref 0 -> 0, step: 1
7930 05:53:08.217413
7931 05:53:08.220579 RX Delay 11 -> 252, step: 4
7932 05:53:08.224004 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7933 05:53:08.227422 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7934 05:53:08.234436 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7935 05:53:08.237287 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7936 05:53:08.240430 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7937 05:53:08.243801 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7938 05:53:08.247171 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7939 05:53:08.253733 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
7940 05:53:08.257013 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7941 05:53:08.260603 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7942 05:53:08.263720 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7943 05:53:08.267082 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7944 05:53:08.273755 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7945 05:53:08.276811 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7946 05:53:08.280262 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
7947 05:53:08.283454 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7948 05:53:08.283530 ==
7949 05:53:08.286983 Dram Type= 6, Freq= 0, CH_0, rank 1
7950 05:53:08.293706 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7951 05:53:08.293808 ==
7952 05:53:08.293908 DQS Delay:
7953 05:53:08.296827 DQS0 = 0, DQS1 = 0
7954 05:53:08.296902 DQM Delay:
7955 05:53:08.299928 DQM0 = 129, DQM1 = 120
7956 05:53:08.300002 DQ Delay:
7957 05:53:08.303785 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
7958 05:53:08.306649 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =140
7959 05:53:08.309906 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7960 05:53:08.313289 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
7961 05:53:08.313386
7962 05:53:08.313482
7963 05:53:08.313577
7964 05:53:08.316972 [DramC_TX_OE_Calibration] TA2
7965 05:53:08.319908 Original DQ_B0 (3 6) =30, OEN = 27
7966 05:53:08.323383 Original DQ_B1 (3 6) =30, OEN = 27
7967 05:53:08.326624 24, 0x0, End_B0=24 End_B1=24
7968 05:53:08.329807 25, 0x0, End_B0=25 End_B1=25
7969 05:53:08.329907 26, 0x0, End_B0=26 End_B1=26
7970 05:53:08.333134 27, 0x0, End_B0=27 End_B1=27
7971 05:53:08.336377 28, 0x0, End_B0=28 End_B1=28
7972 05:53:08.339717 29, 0x0, End_B0=29 End_B1=29
7973 05:53:08.343023 30, 0x0, End_B0=30 End_B1=30
7974 05:53:08.343123 31, 0x4141, End_B0=30 End_B1=30
7975 05:53:08.346118 Byte0 end_step=30 best_step=27
7976 05:53:08.349920 Byte1 end_step=30 best_step=27
7977 05:53:08.352669 Byte0 TX OE(2T, 0.5T) = (3, 3)
7978 05:53:08.355893 Byte1 TX OE(2T, 0.5T) = (3, 3)
7979 05:53:08.355975
7980 05:53:08.356038
7981 05:53:08.362605 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7982 05:53:08.365851 CH0 RK1: MR19=303, MR18=2222
7983 05:53:08.372739 CH0_RK1: MR19=0x303, MR18=0x2222, DQSOSC=392, MR23=63, INC=24, DEC=16
7984 05:53:08.375817 [RxdqsGatingPostProcess] freq 1600
7985 05:53:08.382393 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7986 05:53:08.385680 Pre-setting of DQS Precalculation
7987 05:53:08.389511 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7988 05:53:08.389591 ==
7989 05:53:08.392583 Dram Type= 6, Freq= 0, CH_1, rank 0
7990 05:53:08.395571 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7991 05:53:08.395656 ==
7992 05:53:08.402216 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7993 05:53:08.405983 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7994 05:53:08.412375 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7995 05:53:08.415903 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7996 05:53:08.425028 [CA 0] Center 41 (11~71) winsize 61
7997 05:53:08.427940 [CA 1] Center 40 (10~71) winsize 62
7998 05:53:08.431272 [CA 2] Center 36 (7~66) winsize 60
7999 05:53:08.434949 [CA 3] Center 35 (6~65) winsize 60
8000 05:53:08.437966 [CA 4] Center 33 (4~63) winsize 60
8001 05:53:08.441433 [CA 5] Center 33 (4~63) winsize 60
8002 05:53:08.441513
8003 05:53:08.444601 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8004 05:53:08.444681
8005 05:53:08.448181 [CATrainingPosCal] consider 1 rank data
8006 05:53:08.451100 u2DelayCellTimex100 = 271/100 ps
8007 05:53:08.458232 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8008 05:53:08.461072 CA1 delay=40 (10~71),Diff = 7 PI (25 cell)
8009 05:53:08.464445 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8010 05:53:08.467954 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8011 05:53:08.471202 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8012 05:53:08.474371 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8013 05:53:08.474452
8014 05:53:08.477841 CA PerBit enable=1, Macro0, CA PI delay=33
8015 05:53:08.477921
8016 05:53:08.481144 [CBTSetCACLKResult] CA Dly = 33
8017 05:53:08.484104 CS Dly: 8 (0~39)
8018 05:53:08.487595 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8019 05:53:08.490776 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8020 05:53:08.490857 ==
8021 05:53:08.494158 Dram Type= 6, Freq= 0, CH_1, rank 1
8022 05:53:08.501079 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8023 05:53:08.501160 ==
8024 05:53:08.504179 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8025 05:53:08.507360 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8026 05:53:08.514356 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8027 05:53:08.520631 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8028 05:53:08.527078 [CA 0] Center 41 (11~71) winsize 61
8029 05:53:08.530412 [CA 1] Center 41 (11~71) winsize 61
8030 05:53:08.533732 [CA 2] Center 36 (7~66) winsize 60
8031 05:53:08.537387 [CA 3] Center 35 (6~65) winsize 60
8032 05:53:08.540604 [CA 4] Center 34 (5~64) winsize 60
8033 05:53:08.546586 [CA 5] Center 34 (5~64) winsize 60
8034 05:53:08.546665
8035 05:53:08.547446 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8036 05:53:08.547526
8037 05:53:08.550591 [CATrainingPosCal] consider 2 rank data
8038 05:53:08.553674 u2DelayCellTimex100 = 271/100 ps
8039 05:53:08.557109 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8040 05:53:08.563574 CA1 delay=41 (11~71),Diff = 7 PI (25 cell)
8041 05:53:08.567028 CA2 delay=36 (7~66),Diff = 2 PI (7 cell)
8042 05:53:08.570295 CA3 delay=35 (6~65),Diff = 1 PI (3 cell)
8043 05:53:08.573425 CA4 delay=34 (5~63),Diff = 0 PI (0 cell)
8044 05:53:08.576859 CA5 delay=34 (5~63),Diff = 0 PI (0 cell)
8045 05:53:08.576936
8046 05:53:08.580210 CA PerBit enable=1, Macro0, CA PI delay=34
8047 05:53:08.580290
8048 05:53:08.583581 [CBTSetCACLKResult] CA Dly = 34
8049 05:53:08.587012 CS Dly: 9 (0~41)
8050 05:53:08.590071 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8051 05:53:08.593642 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8052 05:53:08.593740
8053 05:53:08.596465 ----->DramcWriteLeveling(PI) begin...
8054 05:53:08.596567 ==
8055 05:53:08.600103 Dram Type= 6, Freq= 0, CH_1, rank 0
8056 05:53:08.606532 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8057 05:53:08.606610 ==
8058 05:53:08.609932 Write leveling (Byte 0): 22 => 22
8059 05:53:08.613499 Write leveling (Byte 1): 22 => 22
8060 05:53:08.613596 DramcWriteLeveling(PI) end<-----
8061 05:53:08.613693
8062 05:53:08.616523 ==
8063 05:53:08.619882 Dram Type= 6, Freq= 0, CH_1, rank 0
8064 05:53:08.623202 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8065 05:53:08.623300 ==
8066 05:53:08.626344 [Gating] SW mode calibration
8067 05:53:08.633029 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8068 05:53:08.636235 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8069 05:53:08.643088 0 12 0 | B1->B0 | 3030 3434 | 0 1 | (1 1) (1 1)
8070 05:53:08.646471 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 05:53:08.649521 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 05:53:08.656298 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 05:53:08.659610 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 05:53:08.662801 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 05:53:08.669492 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8076 05:53:08.672838 0 12 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
8077 05:53:08.676006 0 13 0 | B1->B0 | 3333 2525 | 1 0 | (1 1) (1 0)
8078 05:53:08.682771 0 13 4 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8079 05:53:08.686265 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 05:53:08.689297 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 05:53:08.696261 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 05:53:08.699120 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 05:53:08.702544 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 05:53:08.709027 0 13 28 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
8085 05:53:08.712418 0 14 0 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
8086 05:53:08.715584 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 05:53:08.722170 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 05:53:08.725330 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 05:53:08.728490 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 05:53:08.735427 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 05:53:08.738660 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 05:53:08.742125 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8093 05:53:08.748786 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8094 05:53:08.751603 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8095 05:53:08.755212 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 05:53:08.761459 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 05:53:08.765232 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 05:53:08.768207 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 05:53:08.774794 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 05:53:08.778610 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 05:53:08.781774 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 05:53:08.788400 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 05:53:08.791413 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 05:53:08.794724 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 05:53:08.801577 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 05:53:08.804692 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 05:53:08.807870 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8108 05:53:08.814414 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8109 05:53:08.817601 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8110 05:53:08.820952 Total UI for P1: 0, mck2ui 16
8111 05:53:08.824263 best dqsien dly found for B0: ( 1, 0, 26)
8112 05:53:08.828012 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8113 05:53:08.834573 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8114 05:53:08.834653 Total UI for P1: 0, mck2ui 16
8115 05:53:08.841416 best dqsien dly found for B1: ( 1, 1, 2)
8116 05:53:08.844109 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8117 05:53:08.847882 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8118 05:53:08.847978
8119 05:53:08.851145 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8120 05:53:08.854086 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8121 05:53:08.857253 [Gating] SW calibration Done
8122 05:53:08.857326 ==
8123 05:53:08.860638 Dram Type= 6, Freq= 0, CH_1, rank 0
8124 05:53:08.864131 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8125 05:53:08.864207 ==
8126 05:53:08.867422 RX Vref Scan: 0
8127 05:53:08.867494
8128 05:53:08.867555 RX Vref 0 -> 0, step: 1
8129 05:53:08.867620
8130 05:53:08.870834 RX Delay 0 -> 252, step: 8
8131 05:53:08.873809 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8132 05:53:08.880581 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8133 05:53:08.884073 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8134 05:53:08.887457 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8135 05:53:08.890476 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8136 05:53:08.893923 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8137 05:53:08.900119 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8138 05:53:08.903908 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8139 05:53:08.906949 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8140 05:53:08.910073 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8141 05:53:08.913766 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8142 05:53:08.919915 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8143 05:53:08.923233 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8144 05:53:08.927064 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8145 05:53:08.930098 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8146 05:53:08.936539 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8147 05:53:08.936612 ==
8148 05:53:08.939761 Dram Type= 6, Freq= 0, CH_1, rank 0
8149 05:53:08.943125 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8150 05:53:08.943223 ==
8151 05:53:08.943318 DQS Delay:
8152 05:53:08.946503 DQS0 = 0, DQS1 = 0
8153 05:53:08.946583 DQM Delay:
8154 05:53:08.949646 DQM0 = 130, DQM1 = 125
8155 05:53:08.949727 DQ Delay:
8156 05:53:08.952951 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8157 05:53:08.956297 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8158 05:53:08.960019 DQ8 =107, DQ9 =119, DQ10 =123, DQ11 =115
8159 05:53:08.963163 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8160 05:53:08.963251
8161 05:53:08.963315
8162 05:53:08.966317 ==
8163 05:53:08.969871 Dram Type= 6, Freq= 0, CH_1, rank 0
8164 05:53:08.972537 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8165 05:53:08.972615 ==
8166 05:53:08.972687
8167 05:53:08.972802
8168 05:53:08.976069 TX Vref Scan disable
8169 05:53:08.976145 == TX Byte 0 ==
8170 05:53:08.983024 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8171 05:53:08.985998 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8172 05:53:08.986075 == TX Byte 1 ==
8173 05:53:08.992634 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8174 05:53:08.996055 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8175 05:53:08.996129 ==
8176 05:53:08.999693 Dram Type= 6, Freq= 0, CH_1, rank 0
8177 05:53:09.002720 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8178 05:53:09.002802 ==
8179 05:53:09.016492
8180 05:53:09.019706 TX Vref early break, caculate TX vref
8181 05:53:09.023181 TX Vref=16, minBit 3, minWin=21, winSum=364
8182 05:53:09.026218 TX Vref=18, minBit 3, minWin=21, winSum=374
8183 05:53:09.029858 TX Vref=20, minBit 1, minWin=22, winSum=382
8184 05:53:09.032964 TX Vref=22, minBit 3, minWin=22, winSum=389
8185 05:53:09.036094 TX Vref=24, minBit 0, minWin=24, winSum=397
8186 05:53:09.043330 TX Vref=26, minBit 3, minWin=23, winSum=406
8187 05:53:09.046047 TX Vref=28, minBit 3, minWin=23, winSum=410
8188 05:53:09.049685 TX Vref=30, minBit 1, minWin=24, winSum=409
8189 05:53:09.052623 TX Vref=32, minBit 3, minWin=23, winSum=396
8190 05:53:09.055988 TX Vref=34, minBit 3, minWin=22, winSum=389
8191 05:53:09.059485 TX Vref=36, minBit 1, minWin=22, winSum=377
8192 05:53:09.066271 [TxChooseVref] Worse bit 1, Min win 24, Win sum 409, Final Vref 30
8193 05:53:09.066352
8194 05:53:09.069414 Final TX Range 0 Vref 30
8195 05:53:09.069491
8196 05:53:09.069553 ==
8197 05:53:09.072560 Dram Type= 6, Freq= 0, CH_1, rank 0
8198 05:53:09.075729 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8199 05:53:09.075807 ==
8200 05:53:09.075871
8201 05:53:09.079047
8202 05:53:09.079122 TX Vref Scan disable
8203 05:53:09.085841 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8204 05:53:09.085916 == TX Byte 0 ==
8205 05:53:09.089276 u2DelayCellOfst[0]=14 cells (4 PI)
8206 05:53:09.092745 u2DelayCellOfst[1]=10 cells (3 PI)
8207 05:53:09.096074 u2DelayCellOfst[2]=0 cells (0 PI)
8208 05:53:09.099204 u2DelayCellOfst[3]=7 cells (2 PI)
8209 05:53:09.102520 u2DelayCellOfst[4]=7 cells (2 PI)
8210 05:53:09.105727 u2DelayCellOfst[5]=14 cells (4 PI)
8211 05:53:09.109170 u2DelayCellOfst[6]=18 cells (5 PI)
8212 05:53:09.112590 u2DelayCellOfst[7]=7 cells (2 PI)
8213 05:53:09.115970 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8214 05:53:09.118852 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8215 05:53:09.122072 == TX Byte 1 ==
8216 05:53:09.125476 u2DelayCellOfst[8]=0 cells (0 PI)
8217 05:53:09.128647 u2DelayCellOfst[9]=7 cells (2 PI)
8218 05:53:09.132366 u2DelayCellOfst[10]=10 cells (3 PI)
8219 05:53:09.132437 u2DelayCellOfst[11]=3 cells (1 PI)
8220 05:53:09.135648 u2DelayCellOfst[12]=18 cells (5 PI)
8221 05:53:09.138785 u2DelayCellOfst[13]=21 cells (6 PI)
8222 05:53:09.142429 u2DelayCellOfst[14]=21 cells (6 PI)
8223 05:53:09.145758 u2DelayCellOfst[15]=21 cells (6 PI)
8224 05:53:09.152010 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8225 05:53:09.155483 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8226 05:53:09.155554 DramC Write-DBI on
8227 05:53:09.155624 ==
8228 05:53:09.158766 Dram Type= 6, Freq= 0, CH_1, rank 0
8229 05:53:09.165372 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8230 05:53:09.165445 ==
8231 05:53:09.165506
8232 05:53:09.165567
8233 05:53:09.165622 TX Vref Scan disable
8234 05:53:09.169294 == TX Byte 0 ==
8235 05:53:09.172580 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8236 05:53:09.176091 == TX Byte 1 ==
8237 05:53:09.179499 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8238 05:53:09.182702 DramC Write-DBI off
8239 05:53:09.182782
8240 05:53:09.182845 [DATLAT]
8241 05:53:09.182904 Freq=1600, CH1 RK0
8242 05:53:09.182961
8243 05:53:09.186132 DATLAT Default: 0xf
8244 05:53:09.186205 0, 0xFFFF, sum = 0
8245 05:53:09.189192 1, 0xFFFF, sum = 0
8246 05:53:09.192805 2, 0xFFFF, sum = 0
8247 05:53:09.192877 3, 0xFFFF, sum = 0
8248 05:53:09.196117 4, 0xFFFF, sum = 0
8249 05:53:09.196188 5, 0xFFFF, sum = 0
8250 05:53:09.199392 6, 0xFFFF, sum = 0
8251 05:53:09.199473 7, 0xFFFF, sum = 0
8252 05:53:09.202557 8, 0xFFFF, sum = 0
8253 05:53:09.202637 9, 0xFFFF, sum = 0
8254 05:53:09.205900 10, 0xFFFF, sum = 0
8255 05:53:09.205984 11, 0xFFFF, sum = 0
8256 05:53:09.209309 12, 0xF7F, sum = 0
8257 05:53:09.209393 13, 0x0, sum = 1
8258 05:53:09.212567 14, 0x0, sum = 2
8259 05:53:09.212647 15, 0x0, sum = 3
8260 05:53:09.215995 16, 0x0, sum = 4
8261 05:53:09.216075 best_step = 14
8262 05:53:09.216137
8263 05:53:09.216195 ==
8264 05:53:09.218956 Dram Type= 6, Freq= 0, CH_1, rank 0
8265 05:53:09.222150 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8266 05:53:09.225675 ==
8267 05:53:09.225787 RX Vref Scan: 1
8268 05:53:09.225878
8269 05:53:09.228981 Set Vref Range= 24 -> 127
8270 05:53:09.229075
8271 05:53:09.232100 RX Vref 24 -> 127, step: 1
8272 05:53:09.232179
8273 05:53:09.232241 RX Delay 3 -> 252, step: 4
8274 05:53:09.232300
8275 05:53:09.235735 Set Vref, RX VrefLevel [Byte0]: 24
8276 05:53:09.238929 [Byte1]: 24
8277 05:53:09.242663
8278 05:53:09.242742 Set Vref, RX VrefLevel [Byte0]: 25
8279 05:53:09.245807 [Byte1]: 25
8280 05:53:09.250317
8281 05:53:09.250401 Set Vref, RX VrefLevel [Byte0]: 26
8282 05:53:09.253436 [Byte1]: 26
8283 05:53:09.258059
8284 05:53:09.258136 Set Vref, RX VrefLevel [Byte0]: 27
8285 05:53:09.261210 [Byte1]: 27
8286 05:53:09.265587
8287 05:53:09.265670 Set Vref, RX VrefLevel [Byte0]: 28
8288 05:53:09.268807 [Byte1]: 28
8289 05:53:09.273328
8290 05:53:09.273408 Set Vref, RX VrefLevel [Byte0]: 29
8291 05:53:09.276700 [Byte1]: 29
8292 05:53:09.281137
8293 05:53:09.281217 Set Vref, RX VrefLevel [Byte0]: 30
8294 05:53:09.284110 [Byte1]: 30
8295 05:53:09.288323
8296 05:53:09.288469 Set Vref, RX VrefLevel [Byte0]: 31
8297 05:53:09.291908 [Byte1]: 31
8298 05:53:09.296206
8299 05:53:09.296286 Set Vref, RX VrefLevel [Byte0]: 32
8300 05:53:09.299378 [Byte1]: 32
8301 05:53:09.303736
8302 05:53:09.303815 Set Vref, RX VrefLevel [Byte0]: 33
8303 05:53:09.307161 [Byte1]: 33
8304 05:53:09.311764
8305 05:53:09.311843 Set Vref, RX VrefLevel [Byte0]: 34
8306 05:53:09.314930 [Byte1]: 34
8307 05:53:09.319137
8308 05:53:09.319264 Set Vref, RX VrefLevel [Byte0]: 35
8309 05:53:09.322539 [Byte1]: 35
8310 05:53:09.326726
8311 05:53:09.326805 Set Vref, RX VrefLevel [Byte0]: 36
8312 05:53:09.330308 [Byte1]: 36
8313 05:53:09.334412
8314 05:53:09.334491 Set Vref, RX VrefLevel [Byte0]: 37
8315 05:53:09.338090 [Byte1]: 37
8316 05:53:09.342070
8317 05:53:09.342149 Set Vref, RX VrefLevel [Byte0]: 38
8318 05:53:09.345640 [Byte1]: 38
8319 05:53:09.349860
8320 05:53:09.349940 Set Vref, RX VrefLevel [Byte0]: 39
8321 05:53:09.353034 [Byte1]: 39
8322 05:53:09.357545
8323 05:53:09.357625 Set Vref, RX VrefLevel [Byte0]: 40
8324 05:53:09.360923 [Byte1]: 40
8325 05:53:09.365407
8326 05:53:09.365486 Set Vref, RX VrefLevel [Byte0]: 41
8327 05:53:09.368529 [Byte1]: 41
8328 05:53:09.372946
8329 05:53:09.373024 Set Vref, RX VrefLevel [Byte0]: 42
8330 05:53:09.376219 [Byte1]: 42
8331 05:53:09.380388
8332 05:53:09.380468 Set Vref, RX VrefLevel [Byte0]: 43
8333 05:53:09.383813 [Byte1]: 43
8334 05:53:09.387831
8335 05:53:09.387909 Set Vref, RX VrefLevel [Byte0]: 44
8336 05:53:09.391254 [Byte1]: 44
8337 05:53:09.395485
8338 05:53:09.395564 Set Vref, RX VrefLevel [Byte0]: 45
8339 05:53:09.398839 [Byte1]: 45
8340 05:53:09.403140
8341 05:53:09.403219 Set Vref, RX VrefLevel [Byte0]: 46
8342 05:53:09.406870 [Byte1]: 46
8343 05:53:09.411129
8344 05:53:09.411208 Set Vref, RX VrefLevel [Byte0]: 47
8345 05:53:09.414246 [Byte1]: 47
8346 05:53:09.418821
8347 05:53:09.418926 Set Vref, RX VrefLevel [Byte0]: 48
8348 05:53:09.421825 [Byte1]: 48
8349 05:53:09.426108
8350 05:53:09.426191 Set Vref, RX VrefLevel [Byte0]: 49
8351 05:53:09.429422 [Byte1]: 49
8352 05:53:09.434060
8353 05:53:09.434140 Set Vref, RX VrefLevel [Byte0]: 50
8354 05:53:09.440345 [Byte1]: 50
8355 05:53:09.440426
8356 05:53:09.443541 Set Vref, RX VrefLevel [Byte0]: 51
8357 05:53:09.447047 [Byte1]: 51
8358 05:53:09.447126
8359 05:53:09.450897 Set Vref, RX VrefLevel [Byte0]: 52
8360 05:53:09.453380 [Byte1]: 52
8361 05:53:09.456933
8362 05:53:09.457013 Set Vref, RX VrefLevel [Byte0]: 53
8363 05:53:09.460747 [Byte1]: 53
8364 05:53:09.464300
8365 05:53:09.464379 Set Vref, RX VrefLevel [Byte0]: 54
8366 05:53:09.468226 [Byte1]: 54
8367 05:53:09.472182
8368 05:53:09.472261 Set Vref, RX VrefLevel [Byte0]: 55
8369 05:53:09.475428 [Byte1]: 55
8370 05:53:09.479730
8371 05:53:09.479815 Set Vref, RX VrefLevel [Byte0]: 56
8372 05:53:09.482996 [Byte1]: 56
8373 05:53:09.487531
8374 05:53:09.487614 Set Vref, RX VrefLevel [Byte0]: 57
8375 05:53:09.490819 [Byte1]: 57
8376 05:53:09.495214
8377 05:53:09.495297 Set Vref, RX VrefLevel [Byte0]: 58
8378 05:53:09.498706 [Byte1]: 58
8379 05:53:09.502665
8380 05:53:09.506281 Set Vref, RX VrefLevel [Byte0]: 59
8381 05:53:09.509442 [Byte1]: 59
8382 05:53:09.509526
8383 05:53:09.512766 Set Vref, RX VrefLevel [Byte0]: 60
8384 05:53:09.516335 [Byte1]: 60
8385 05:53:09.516419
8386 05:53:09.519337 Set Vref, RX VrefLevel [Byte0]: 61
8387 05:53:09.522516 [Byte1]: 61
8388 05:53:09.522600
8389 05:53:09.525938 Set Vref, RX VrefLevel [Byte0]: 62
8390 05:53:09.529325 [Byte1]: 62
8391 05:53:09.533365
8392 05:53:09.533448 Set Vref, RX VrefLevel [Byte0]: 63
8393 05:53:09.536648 [Byte1]: 63
8394 05:53:09.541080
8395 05:53:09.541161 Set Vref, RX VrefLevel [Byte0]: 64
8396 05:53:09.544188 [Byte1]: 64
8397 05:53:09.548654
8398 05:53:09.548760 Set Vref, RX VrefLevel [Byte0]: 65
8399 05:53:09.551986 [Byte1]: 65
8400 05:53:09.556642
8401 05:53:09.556766 Set Vref, RX VrefLevel [Byte0]: 66
8402 05:53:09.559394 [Byte1]: 66
8403 05:53:09.563832
8404 05:53:09.563915 Set Vref, RX VrefLevel [Byte0]: 67
8405 05:53:09.567495 [Byte1]: 67
8406 05:53:09.571670
8407 05:53:09.571754 Set Vref, RX VrefLevel [Byte0]: 68
8408 05:53:09.574835 [Byte1]: 68
8409 05:53:09.579215
8410 05:53:09.579298 Set Vref, RX VrefLevel [Byte0]: 69
8411 05:53:09.582947 [Byte1]: 69
8412 05:53:09.587235
8413 05:53:09.587319 Set Vref, RX VrefLevel [Byte0]: 70
8414 05:53:09.590384 [Byte1]: 70
8415 05:53:09.594864
8416 05:53:09.594947 Set Vref, RX VrefLevel [Byte0]: 71
8417 05:53:09.597933 [Byte1]: 71
8418 05:53:09.602335
8419 05:53:09.602424 Set Vref, RX VrefLevel [Byte0]: 72
8420 05:53:09.605541 [Byte1]: 72
8421 05:53:09.609908
8422 05:53:09.609992 Set Vref, RX VrefLevel [Byte0]: 73
8423 05:53:09.613660 [Byte1]: 73
8424 05:53:09.617750
8425 05:53:09.617834 Set Vref, RX VrefLevel [Byte0]: 74
8426 05:53:09.621004 [Byte1]: 74
8427 05:53:09.625277
8428 05:53:09.625361 Set Vref, RX VrefLevel [Byte0]: 75
8429 05:53:09.628552 [Byte1]: 75
8430 05:53:09.632734
8431 05:53:09.632832 Set Vref, RX VrefLevel [Byte0]: 76
8432 05:53:09.636357 [Byte1]: 76
8433 05:53:09.640452
8434 05:53:09.640542 Final RX Vref Byte 0 = 60 to rank0
8435 05:53:09.643897 Final RX Vref Byte 1 = 58 to rank0
8436 05:53:09.647362 Final RX Vref Byte 0 = 60 to rank1
8437 05:53:09.650280 Final RX Vref Byte 1 = 58 to rank1==
8438 05:53:09.653719 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 05:53:09.660032 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8440 05:53:09.660117 ==
8441 05:53:09.660204 DQS Delay:
8442 05:53:09.663582 DQS0 = 0, DQS1 = 0
8443 05:53:09.663670 DQM Delay:
8444 05:53:09.663756 DQM0 = 129, DQM1 = 122
8445 05:53:09.666827 DQ Delay:
8446 05:53:09.670519 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =128
8447 05:53:09.673574 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =124
8448 05:53:09.676919 DQ8 =106, DQ9 =112, DQ10 =126, DQ11 =110
8449 05:53:09.680294 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =132
8450 05:53:09.680379
8451 05:53:09.680464
8452 05:53:09.680544
8453 05:53:09.683639 [DramC_TX_OE_Calibration] TA2
8454 05:53:09.686821 Original DQ_B0 (3 6) =30, OEN = 27
8455 05:53:09.690076 Original DQ_B1 (3 6) =30, OEN = 27
8456 05:53:09.693473 24, 0x0, End_B0=24 End_B1=24
8457 05:53:09.693558 25, 0x0, End_B0=25 End_B1=25
8458 05:53:09.696638 26, 0x0, End_B0=26 End_B1=26
8459 05:53:09.699922 27, 0x0, End_B0=27 End_B1=27
8460 05:53:09.703866 28, 0x0, End_B0=28 End_B1=28
8461 05:53:09.706842 29, 0x0, End_B0=29 End_B1=29
8462 05:53:09.706927 30, 0x0, End_B0=30 End_B1=30
8463 05:53:09.710429 31, 0x4141, End_B0=30 End_B1=30
8464 05:53:09.713640 Byte0 end_step=30 best_step=27
8465 05:53:09.716743 Byte1 end_step=30 best_step=27
8466 05:53:09.719936 Byte0 TX OE(2T, 0.5T) = (3, 3)
8467 05:53:09.723387 Byte1 TX OE(2T, 0.5T) = (3, 3)
8468 05:53:09.723471
8469 05:53:09.723558
8470 05:53:09.730155 [DQSOSCAuto] RK0, (LSB)MR18= 0x2828, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8471 05:53:09.733271 CH1 RK0: MR19=303, MR18=2828
8472 05:53:09.739786 CH1_RK0: MR19=0x303, MR18=0x2828, DQSOSC=389, MR23=63, INC=24, DEC=16
8473 05:53:09.739870
8474 05:53:09.743345 ----->DramcWriteLeveling(PI) begin...
8475 05:53:09.743430 ==
8476 05:53:09.746315 Dram Type= 6, Freq= 0, CH_1, rank 1
8477 05:53:09.750086 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8478 05:53:09.750171 ==
8479 05:53:09.753010 Write leveling (Byte 0): 21 => 21
8480 05:53:09.756282 Write leveling (Byte 1): 23 => 23
8481 05:53:09.759637 DramcWriteLeveling(PI) end<-----
8482 05:53:09.759720
8483 05:53:09.759804 ==
8484 05:53:09.762854 Dram Type= 6, Freq= 0, CH_1, rank 1
8485 05:53:09.766524 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8486 05:53:09.766608 ==
8487 05:53:09.769898 [Gating] SW mode calibration
8488 05:53:09.776376 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8489 05:53:09.782743 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8490 05:53:09.786269 0 12 0 | B1->B0 | 3332 3434 | 1 1 | (0 0) (1 1)
8491 05:53:09.792929 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8492 05:53:09.795981 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8493 05:53:09.799480 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8494 05:53:09.806360 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8495 05:53:09.809049 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8496 05:53:09.812235 0 12 24 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
8497 05:53:09.819213 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8498 05:53:09.822488 0 13 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8499 05:53:09.825788 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8500 05:53:09.832192 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8501 05:53:09.835434 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8502 05:53:09.839436 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8503 05:53:09.845187 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8504 05:53:09.848834 0 13 24 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8505 05:53:09.851929 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8506 05:53:09.858558 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8507 05:53:09.861973 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8508 05:53:09.865116 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8509 05:53:09.871821 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8510 05:53:09.875214 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8511 05:53:09.878504 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8512 05:53:09.885622 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8513 05:53:09.888667 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8514 05:53:09.892086 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8515 05:53:09.898730 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8516 05:53:09.901946 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8517 05:53:09.904989 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8518 05:53:09.911755 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8519 05:53:09.914899 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8520 05:53:09.918314 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8521 05:53:09.924777 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8522 05:53:09.928084 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8523 05:53:09.931173 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8524 05:53:09.938119 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8525 05:53:09.941238 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8526 05:53:09.944923 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8527 05:53:09.951538 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8528 05:53:09.954408 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8529 05:53:09.957663 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8530 05:53:09.961084 Total UI for P1: 0, mck2ui 16
8531 05:53:09.964348 best dqsien dly found for B0: ( 1, 0, 24)
8532 05:53:09.968018 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8533 05:53:09.974444 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8534 05:53:09.977732 Total UI for P1: 0, mck2ui 16
8535 05:53:09.981210 best dqsien dly found for B1: ( 1, 1, 0)
8536 05:53:09.984552 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8537 05:53:09.987588 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8538 05:53:09.987672
8539 05:53:09.990822 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8540 05:53:09.994393 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8541 05:53:09.997587 [Gating] SW calibration Done
8542 05:53:09.997671 ==
8543 05:53:10.000839 Dram Type= 6, Freq= 0, CH_1, rank 1
8544 05:53:10.004843 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8545 05:53:10.004927 ==
8546 05:53:10.007482 RX Vref Scan: 0
8547 05:53:10.007565
8548 05:53:10.010595 RX Vref 0 -> 0, step: 1
8549 05:53:10.010679
8550 05:53:10.010764 RX Delay 0 -> 252, step: 8
8551 05:53:10.017513 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8552 05:53:10.020824 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8553 05:53:10.024268 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8554 05:53:10.027433 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8555 05:53:10.030524 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8556 05:53:10.037481 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8557 05:53:10.040672 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8558 05:53:10.044402 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8559 05:53:10.047469 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8560 05:53:10.050570 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8561 05:53:10.054380 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8562 05:53:10.060518 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8563 05:53:10.063661 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8564 05:53:10.067522 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8565 05:53:10.070578 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8566 05:53:10.077033 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8567 05:53:10.077118 ==
8568 05:53:10.080488 Dram Type= 6, Freq= 0, CH_1, rank 1
8569 05:53:10.083590 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8570 05:53:10.083674 ==
8571 05:53:10.083761 DQS Delay:
8572 05:53:10.086851 DQS0 = 0, DQS1 = 0
8573 05:53:10.086959 DQM Delay:
8574 05:53:10.090656 DQM0 = 131, DQM1 = 124
8575 05:53:10.090740 DQ Delay:
8576 05:53:10.093755 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8577 05:53:10.096988 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8578 05:53:10.100624 DQ8 =107, DQ9 =111, DQ10 =123, DQ11 =119
8579 05:53:10.104028 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8580 05:53:10.104112
8581 05:53:10.106900
8582 05:53:10.106984 ==
8583 05:53:10.110121 Dram Type= 6, Freq= 0, CH_1, rank 1
8584 05:53:10.113788 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8585 05:53:10.113873 ==
8586 05:53:10.113958
8587 05:53:10.114038
8588 05:53:10.116849 TX Vref Scan disable
8589 05:53:10.116933 == TX Byte 0 ==
8590 05:53:10.123769 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8591 05:53:10.126736 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8592 05:53:10.126837 == TX Byte 1 ==
8593 05:53:10.133182 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8594 05:53:10.137000 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8595 05:53:10.137084 ==
8596 05:53:10.139978 Dram Type= 6, Freq= 0, CH_1, rank 1
8597 05:53:10.143254 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8598 05:53:10.143338 ==
8599 05:53:10.157606
8600 05:53:10.161124 TX Vref early break, caculate TX vref
8601 05:53:10.164510 TX Vref=16, minBit 2, minWin=22, winSum=370
8602 05:53:10.167541 TX Vref=18, minBit 0, minWin=22, winSum=385
8603 05:53:10.170839 TX Vref=20, minBit 3, minWin=23, winSum=392
8604 05:53:10.173942 TX Vref=22, minBit 2, minWin=24, winSum=400
8605 05:53:10.177355 TX Vref=24, minBit 2, minWin=24, winSum=407
8606 05:53:10.184041 TX Vref=26, minBit 0, minWin=25, winSum=419
8607 05:53:10.187308 TX Vref=28, minBit 3, minWin=24, winSum=414
8608 05:53:10.190960 TX Vref=30, minBit 0, minWin=25, winSum=413
8609 05:53:10.193752 TX Vref=32, minBit 9, minWin=24, winSum=409
8610 05:53:10.197062 TX Vref=34, minBit 1, minWin=24, winSum=400
8611 05:53:10.200921 TX Vref=36, minBit 0, minWin=23, winSum=393
8612 05:53:10.207212 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 26
8613 05:53:10.207294
8614 05:53:10.210228 Final TX Range 0 Vref 26
8615 05:53:10.210309
8616 05:53:10.210373 ==
8617 05:53:10.213674 Dram Type= 6, Freq= 0, CH_1, rank 1
8618 05:53:10.217092 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8619 05:53:10.217174 ==
8620 05:53:10.217239
8621 05:53:10.220516
8622 05:53:10.220597 TX Vref Scan disable
8623 05:53:10.227085 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8624 05:53:10.227165 == TX Byte 0 ==
8625 05:53:10.230744 u2DelayCellOfst[0]=18 cells (5 PI)
8626 05:53:10.233367 u2DelayCellOfst[1]=10 cells (3 PI)
8627 05:53:10.236933 u2DelayCellOfst[2]=0 cells (0 PI)
8628 05:53:10.240255 u2DelayCellOfst[3]=10 cells (3 PI)
8629 05:53:10.243528 u2DelayCellOfst[4]=10 cells (3 PI)
8630 05:53:10.246748 u2DelayCellOfst[5]=18 cells (5 PI)
8631 05:53:10.250002 u2DelayCellOfst[6]=14 cells (4 PI)
8632 05:53:10.253110 u2DelayCellOfst[7]=7 cells (2 PI)
8633 05:53:10.256973 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8634 05:53:10.259974 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8635 05:53:10.263440 == TX Byte 1 ==
8636 05:53:10.266817 u2DelayCellOfst[8]=0 cells (0 PI)
8637 05:53:10.269780 u2DelayCellOfst[9]=3 cells (1 PI)
8638 05:53:10.273187 u2DelayCellOfst[10]=10 cells (3 PI)
8639 05:53:10.276243 u2DelayCellOfst[11]=0 cells (0 PI)
8640 05:53:10.279527 u2DelayCellOfst[12]=14 cells (4 PI)
8641 05:53:10.283190 u2DelayCellOfst[13]=18 cells (5 PI)
8642 05:53:10.283271 u2DelayCellOfst[14]=18 cells (5 PI)
8643 05:53:10.286291 u2DelayCellOfst[15]=18 cells (5 PI)
8644 05:53:10.292675 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8645 05:53:10.296001 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8646 05:53:10.299565 DramC Write-DBI on
8647 05:53:10.299647 ==
8648 05:53:10.303015 Dram Type= 6, Freq= 0, CH_1, rank 1
8649 05:53:10.306184 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8650 05:53:10.306269 ==
8651 05:53:10.306354
8652 05:53:10.306434
8653 05:53:10.309403 TX Vref Scan disable
8654 05:53:10.309488 == TX Byte 0 ==
8655 05:53:10.316119 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8656 05:53:10.316203 == TX Byte 1 ==
8657 05:53:10.319330 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8658 05:53:10.322623 DramC Write-DBI off
8659 05:53:10.322708
8660 05:53:10.322794 [DATLAT]
8661 05:53:10.325837 Freq=1600, CH1 RK1
8662 05:53:10.325921
8663 05:53:10.326007 DATLAT Default: 0xe
8664 05:53:10.329291 0, 0xFFFF, sum = 0
8665 05:53:10.329377 1, 0xFFFF, sum = 0
8666 05:53:10.332914 2, 0xFFFF, sum = 0
8667 05:53:10.332996 3, 0xFFFF, sum = 0
8668 05:53:10.336178 4, 0xFFFF, sum = 0
8669 05:53:10.336260 5, 0xFFFF, sum = 0
8670 05:53:10.339413 6, 0xFFFF, sum = 0
8671 05:53:10.342619 7, 0xFFFF, sum = 0
8672 05:53:10.342701 8, 0xFFFF, sum = 0
8673 05:53:10.345848 9, 0xFFFF, sum = 0
8674 05:53:10.345929 10, 0xFFFF, sum = 0
8675 05:53:10.349258 11, 0xFFFF, sum = 0
8676 05:53:10.349339 12, 0xF7F, sum = 0
8677 05:53:10.352415 13, 0x0, sum = 1
8678 05:53:10.352540 14, 0x0, sum = 2
8679 05:53:10.355632 15, 0x0, sum = 3
8680 05:53:10.355741 16, 0x0, sum = 4
8681 05:53:10.355837 best_step = 14
8682 05:53:10.359178
8683 05:53:10.359258 ==
8684 05:53:10.362516 Dram Type= 6, Freq= 0, CH_1, rank 1
8685 05:53:10.365477 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8686 05:53:10.365558 ==
8687 05:53:10.365622 RX Vref Scan: 0
8688 05:53:10.365682
8689 05:53:10.368813 RX Vref 0 -> 0, step: 1
8690 05:53:10.368920
8691 05:53:10.372358 RX Delay 3 -> 252, step: 4
8692 05:53:10.375792 iDelay=195, Bit 0, Center 130 (79 ~ 182) 104
8693 05:53:10.382157 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8694 05:53:10.385786 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8695 05:53:10.388645 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8696 05:53:10.392415 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8697 05:53:10.395893 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8698 05:53:10.402074 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8699 05:53:10.405368 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8700 05:53:10.408900 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8701 05:53:10.411842 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8702 05:53:10.415073 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8703 05:53:10.422052 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8704 05:53:10.425191 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8705 05:53:10.428388 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8706 05:53:10.431693 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8707 05:53:10.435309 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8708 05:53:10.438466 ==
8709 05:53:10.441797 Dram Type= 6, Freq= 0, CH_1, rank 1
8710 05:53:10.445142 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8711 05:53:10.445225 ==
8712 05:53:10.445289 DQS Delay:
8713 05:53:10.448532 DQS0 = 0, DQS1 = 0
8714 05:53:10.448613 DQM Delay:
8715 05:53:10.451688 DQM0 = 127, DQM1 = 122
8716 05:53:10.451769 DQ Delay:
8717 05:53:10.454962 DQ0 =130, DQ1 =122, DQ2 =118, DQ3 =124
8718 05:53:10.458786 DQ4 =124, DQ5 =138, DQ6 =134, DQ7 =126
8719 05:53:10.461479 DQ8 =104, DQ9 =108, DQ10 =124, DQ11 =114
8720 05:53:10.465067 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8721 05:53:10.465148
8722 05:53:10.465226
8723 05:53:10.465300
8724 05:53:10.468492 [DramC_TX_OE_Calibration] TA2
8725 05:53:10.471813 Original DQ_B0 (3 6) =30, OEN = 27
8726 05:53:10.475035 Original DQ_B1 (3 6) =30, OEN = 27
8727 05:53:10.477876 24, 0x0, End_B0=24 End_B1=24
8728 05:53:10.481272 25, 0x0, End_B0=25 End_B1=25
8729 05:53:10.481355 26, 0x0, End_B0=26 End_B1=26
8730 05:53:10.484843 27, 0x0, End_B0=27 End_B1=27
8731 05:53:10.488323 28, 0x0, End_B0=28 End_B1=28
8732 05:53:10.491402 29, 0x0, End_B0=29 End_B1=29
8733 05:53:10.494642 30, 0x0, End_B0=30 End_B1=30
8734 05:53:10.494724 31, 0x4545, End_B0=30 End_B1=30
8735 05:53:10.497933 Byte0 end_step=30 best_step=27
8736 05:53:10.501501 Byte1 end_step=30 best_step=27
8737 05:53:10.504696 Byte0 TX OE(2T, 0.5T) = (3, 3)
8738 05:53:10.508129 Byte1 TX OE(2T, 0.5T) = (3, 3)
8739 05:53:10.508210
8740 05:53:10.508274
8741 05:53:10.514550 [DQSOSCAuto] RK1, (LSB)MR18= 0x1717, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
8742 05:53:10.518242 CH1 RK1: MR19=303, MR18=1717
8743 05:53:10.524413 CH1_RK1: MR19=0x303, MR18=0x1717, DQSOSC=398, MR23=63, INC=23, DEC=15
8744 05:53:10.527545 [RxdqsGatingPostProcess] freq 1600
8745 05:53:10.534265 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8746 05:53:10.537726 Pre-setting of DQS Precalculation
8747 05:53:10.540888 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8748 05:53:10.547515 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8749 05:53:10.554140 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8750 05:53:10.554227
8751 05:53:10.557531
8752 05:53:10.557614 [Calibration Summary] 3200 Mbps
8753 05:53:10.561085 CH 0, Rank 0
8754 05:53:10.561194 SW Impedance : PASS
8755 05:53:10.564421 DUTY Scan : NO K
8756 05:53:10.567714 ZQ Calibration : PASS
8757 05:53:10.567795 Jitter Meter : NO K
8758 05:53:10.570792 CBT Training : PASS
8759 05:53:10.574147 Write leveling : PASS
8760 05:53:10.574228 RX DQS gating : PASS
8761 05:53:10.577611 RX DQ/DQS(RDDQC) : PASS
8762 05:53:10.580684 TX DQ/DQS : PASS
8763 05:53:10.580813 RX DATLAT : PASS
8764 05:53:10.584151 RX DQ/DQS(Engine): PASS
8765 05:53:10.587315 TX OE : PASS
8766 05:53:10.587396 All Pass.
8767 05:53:10.587459
8768 05:53:10.587518 CH 0, Rank 1
8769 05:53:10.590863 SW Impedance : PASS
8770 05:53:10.593988 DUTY Scan : NO K
8771 05:53:10.594070 ZQ Calibration : PASS
8772 05:53:10.597449 Jitter Meter : NO K
8773 05:53:10.600681 CBT Training : PASS
8774 05:53:10.600811 Write leveling : PASS
8775 05:53:10.604003 RX DQS gating : PASS
8776 05:53:10.604083 RX DQ/DQS(RDDQC) : PASS
8777 05:53:10.606984 TX DQ/DQS : PASS
8778 05:53:10.610487 RX DATLAT : PASS
8779 05:53:10.610568 RX DQ/DQS(Engine): PASS
8780 05:53:10.613536 TX OE : PASS
8781 05:53:10.613642 All Pass.
8782 05:53:10.613707
8783 05:53:10.616952 CH 1, Rank 0
8784 05:53:10.617033 SW Impedance : PASS
8785 05:53:10.620523 DUTY Scan : NO K
8786 05:53:10.623887 ZQ Calibration : PASS
8787 05:53:10.623970 Jitter Meter : NO K
8788 05:53:10.626811 CBT Training : PASS
8789 05:53:10.630333 Write leveling : PASS
8790 05:53:10.630416 RX DQS gating : PASS
8791 05:53:10.633791 RX DQ/DQS(RDDQC) : PASS
8792 05:53:10.636922 TX DQ/DQS : PASS
8793 05:53:10.637006 RX DATLAT : PASS
8794 05:53:10.640027 RX DQ/DQS(Engine): PASS
8795 05:53:10.643671 TX OE : PASS
8796 05:53:10.643754 All Pass.
8797 05:53:10.643839
8798 05:53:10.643919 CH 1, Rank 1
8799 05:53:10.647024 SW Impedance : PASS
8800 05:53:10.649990 DUTY Scan : NO K
8801 05:53:10.650074 ZQ Calibration : PASS
8802 05:53:10.653219 Jitter Meter : NO K
8803 05:53:10.656629 CBT Training : PASS
8804 05:53:10.656735 Write leveling : PASS
8805 05:53:10.660090 RX DQS gating : PASS
8806 05:53:10.663195 RX DQ/DQS(RDDQC) : PASS
8807 05:53:10.663303 TX DQ/DQS : PASS
8808 05:53:10.666675 RX DATLAT : PASS
8809 05:53:10.666759 RX DQ/DQS(Engine): PASS
8810 05:53:10.670225 TX OE : PASS
8811 05:53:10.670309 All Pass.
8812 05:53:10.670395
8813 05:53:10.673294 DramC Write-DBI on
8814 05:53:10.676522 PER_BANK_REFRESH: Hybrid Mode
8815 05:53:10.676605 TX_TRACKING: ON
8816 05:53:10.686782 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8817 05:53:10.693413 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8818 05:53:10.703001 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8819 05:53:10.706337 [FAST_K] Save calibration result to emmc
8820 05:53:10.706422 sync common calibartion params.
8821 05:53:10.710087 sync cbt_mode0:0, 1:0
8822 05:53:10.713290 dram_init: ddr_geometry: 0
8823 05:53:10.716505 dram_init: ddr_geometry: 0
8824 05:53:10.716588 dram_init: ddr_geometry: 0
8825 05:53:10.719620 0:dram_rank_size:80000000
8826 05:53:10.722906 1:dram_rank_size:80000000
8827 05:53:10.726252 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8828 05:53:10.729365 DFS_SHUFFLE_HW_MODE: ON
8829 05:53:10.732823 dramc_set_vcore_voltage set vcore to 725000
8830 05:53:10.736158 Read voltage for 1600, 0
8831 05:53:10.736242 Vio18 = 0
8832 05:53:10.739859 Vcore = 725000
8833 05:53:10.739944 Vdram = 0
8834 05:53:10.740029 Vddq = 0
8835 05:53:10.740109 Vmddr = 0
8836 05:53:10.743071 switch to 3200 Mbps bootup
8837 05:53:10.746607 [DramcRunTimeConfig]
8838 05:53:10.746690 PHYPLL
8839 05:53:10.746775 DPM_CONTROL_AFTERK: ON
8840 05:53:10.749321 PER_BANK_REFRESH: ON
8841 05:53:10.752783 REFRESH_OVERHEAD_REDUCTION: ON
8842 05:53:10.756137 CMD_PICG_NEW_MODE: OFF
8843 05:53:10.756221 XRTWTW_NEW_MODE: ON
8844 05:53:10.759981 XRTRTR_NEW_MODE: ON
8845 05:53:10.760065 TX_TRACKING: ON
8846 05:53:10.762463 RDSEL_TRACKING: OFF
8847 05:53:10.762547 DQS Precalculation for DVFS: ON
8848 05:53:10.765858 RX_TRACKING: OFF
8849 05:53:10.765941 HW_GATING DBG: ON
8850 05:53:10.769379 ZQCS_ENABLE_LP4: ON
8851 05:53:10.772487 RX_PICG_NEW_MODE: ON
8852 05:53:10.772570 TX_PICG_NEW_MODE: ON
8853 05:53:10.775794 ENABLE_RX_DCM_DPHY: ON
8854 05:53:10.779259 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8855 05:53:10.779343 DUMMY_READ_FOR_TRACKING: OFF
8856 05:53:10.782515 !!! SPM_CONTROL_AFTERK: OFF
8857 05:53:10.785798 !!! SPM could not control APHY
8858 05:53:10.789297 IMPEDANCE_TRACKING: ON
8859 05:53:10.789380 TEMP_SENSOR: ON
8860 05:53:10.792544 HW_SAVE_FOR_SR: OFF
8861 05:53:10.795843 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8862 05:53:10.799242 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8863 05:53:10.799326 Read ODT Tracking: ON
8864 05:53:10.802612 Refresh Rate DeBounce: ON
8865 05:53:10.805685 DFS_NO_QUEUE_FLUSH: ON
8866 05:53:10.808630 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8867 05:53:10.808736 ENABLE_DFS_RUNTIME_MRW: OFF
8868 05:53:10.812480 DDR_RESERVE_NEW_MODE: ON
8869 05:53:10.815348 MR_CBT_SWITCH_FREQ: ON
8870 05:53:10.815431 =========================
8871 05:53:10.835387 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8872 05:53:10.838995 dram_init: ddr_geometry: 0
8873 05:53:10.856872 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8874 05:53:10.859855 dram_init: dram init end (result: 0)
8875 05:53:10.866369 DRAM-K: Full calibration passed in 23423 msecs
8876 05:53:10.869790 MRC: failed to locate region type 0.
8877 05:53:10.869886 DRAM rank0 size:0x80000000,
8878 05:53:10.873328 DRAM rank1 size=0x80000000
8879 05:53:10.883020 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8880 05:53:10.889896 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8881 05:53:10.896494 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8882 05:53:10.902920 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8883 05:53:10.906188 DRAM rank0 size:0x80000000,
8884 05:53:10.910079 DRAM rank1 size=0x80000000
8885 05:53:10.910160 CBMEM:
8886 05:53:10.913035 IMD: root @ 0xfffff000 254 entries.
8887 05:53:10.916639 IMD: root @ 0xffffec00 62 entries.
8888 05:53:10.919369 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8889 05:53:10.922589 WARNING: RO_VPD is uninitialized or empty.
8890 05:53:10.929464 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8891 05:53:10.936255 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8892 05:53:10.948973 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8893 05:53:10.960115 BS: romstage times (exec / console): total (unknown) / 22964 ms
8894 05:53:10.960246
8895 05:53:10.960336
8896 05:53:10.970346 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8897 05:53:10.973718 ARM64: Exception handlers installed.
8898 05:53:10.976919 ARM64: Testing exception
8899 05:53:10.980279 ARM64: Done test exception
8900 05:53:10.980431 Enumerating buses...
8901 05:53:10.983673 Show all devs... Before device enumeration.
8902 05:53:10.987055 Root Device: enabled 1
8903 05:53:10.990305 CPU_CLUSTER: 0: enabled 1
8904 05:53:10.990405 CPU: 00: enabled 1
8905 05:53:10.993509 Compare with tree...
8906 05:53:10.993586 Root Device: enabled 1
8907 05:53:10.996427 CPU_CLUSTER: 0: enabled 1
8908 05:53:11.000094 CPU: 00: enabled 1
8909 05:53:11.000178 Root Device scanning...
8910 05:53:11.003285 scan_static_bus for Root Device
8911 05:53:11.006688 CPU_CLUSTER: 0 enabled
8912 05:53:11.009578 scan_static_bus for Root Device done
8913 05:53:11.013389 scan_bus: bus Root Device finished in 8 msecs
8914 05:53:11.013474 done
8915 05:53:11.019844 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8916 05:53:11.022763 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8917 05:53:11.029859 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8918 05:53:11.032805 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8919 05:53:11.036202 Allocating resources...
8920 05:53:11.039698 Reading resources...
8921 05:53:11.042562 Root Device read_resources bus 0 link: 0
8922 05:53:11.046183 DRAM rank0 size:0x80000000,
8923 05:53:11.046266 DRAM rank1 size=0x80000000
8924 05:53:11.049228 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8925 05:53:11.052404 CPU: 00 missing read_resources
8926 05:53:11.059426 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8927 05:53:11.062691 Root Device read_resources bus 0 link: 0 done
8928 05:53:11.066061 Done reading resources.
8929 05:53:11.068989 Show resources in subtree (Root Device)...After reading.
8930 05:53:11.072333 Root Device child on link 0 CPU_CLUSTER: 0
8931 05:53:11.075805 CPU_CLUSTER: 0 child on link 0 CPU: 00
8932 05:53:11.085802 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8933 05:53:11.085887 CPU: 00
8934 05:53:11.089141 Root Device assign_resources, bus 0 link: 0
8935 05:53:11.092386 CPU_CLUSTER: 0 missing set_resources
8936 05:53:11.099060 Root Device assign_resources, bus 0 link: 0 done
8937 05:53:11.099141 Done setting resources.
8938 05:53:11.105722 Show resources in subtree (Root Device)...After assigning values.
8939 05:53:11.109149 Root Device child on link 0 CPU_CLUSTER: 0
8940 05:53:11.112374 CPU_CLUSTER: 0 child on link 0 CPU: 00
8941 05:53:11.122108 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8942 05:53:11.122190 CPU: 00
8943 05:53:11.125686 Done allocating resources.
8944 05:53:11.132424 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8945 05:53:11.132506 Enabling resources...
8946 05:53:11.132569 done.
8947 05:53:11.138582 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8948 05:53:11.142084 Initializing devices...
8949 05:53:11.142165 Root Device init
8950 05:53:11.144920 init hardware done!
8951 05:53:11.145028 0x00000018: ctrlr->caps
8952 05:53:11.148540 52.000 MHz: ctrlr->f_max
8953 05:53:11.151698 0.400 MHz: ctrlr->f_min
8954 05:53:11.151784 0x40ff8080: ctrlr->voltages
8955 05:53:11.155021 sclk: 390625
8956 05:53:11.155102 Bus Width = 1
8957 05:53:11.155166 sclk: 390625
8958 05:53:11.158613 Bus Width = 1
8959 05:53:11.161731 Early init status = 3
8960 05:53:11.164996 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8961 05:53:11.168580 in-header: 03 fb 00 00 01 00 00 00
8962 05:53:11.171528 in-data: 01
8963 05:53:11.174971 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8964 05:53:11.178410 in-header: 03 fb 00 00 01 00 00 00
8965 05:53:11.181803 in-data: 01
8966 05:53:11.184877 [SSUSB] Setting up USB HOST controller...
8967 05:53:11.187917 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8968 05:53:11.191321 [SSUSB] phy power-on done.
8969 05:53:11.194999 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8970 05:53:11.201292 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8971 05:53:11.205029 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8972 05:53:11.211157 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8973 05:53:11.217897 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8974 05:53:11.224271 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8975 05:53:11.231291 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8976 05:53:11.237761 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8977 05:53:11.241001 SPM: binary array size = 0x9dc
8978 05:53:11.244157 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8979 05:53:11.250834 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8980 05:53:11.257801 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8981 05:53:11.264414 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8982 05:53:11.267762 configure_display: Starting display init
8983 05:53:11.301449 anx7625_power_on_init: Init interface.
8984 05:53:11.304666 anx7625_disable_pd_protocol: Disabled PD feature.
8985 05:53:11.308156 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8986 05:53:11.335707 anx7625_start_dp_work: Secure OCM version=00
8987 05:53:11.339786 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8988 05:53:11.353950 sp_tx_get_edid_block: EDID Block = 1
8989 05:53:11.456373 Extracted contents:
8990 05:53:11.459878 header: 00 ff ff ff ff ff ff 00
8991 05:53:11.463393 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8992 05:53:11.466741 version: 01 04
8993 05:53:11.469677 basic params: 95 1f 11 78 0a
8994 05:53:11.472970 chroma info: 76 90 94 55 54 90 27 21 50 54
8995 05:53:11.476309 established: 00 00 00
8996 05:53:11.482869 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8997 05:53:11.489487 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8998 05:53:11.493050 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8999 05:53:11.499252 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9000 05:53:11.506166 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9001 05:53:11.509626 extensions: 00
9002 05:53:11.509700 checksum: fb
9003 05:53:11.509762
9004 05:53:11.513083 Manufacturer: IVO Model 57d Serial Number 0
9005 05:53:11.516049 Made week 0 of 2020
9006 05:53:11.519432 EDID version: 1.4
9007 05:53:11.519534 Digital display
9008 05:53:11.522744 6 bits per primary color channel
9009 05:53:11.522838 DisplayPort interface
9010 05:53:11.525847 Maximum image size: 31 cm x 17 cm
9011 05:53:11.529274 Gamma: 220%
9012 05:53:11.529375 Check DPMS levels
9013 05:53:11.535922 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9014 05:53:11.538774 First detailed timing is preferred timing
9015 05:53:11.538880 Established timings supported:
9016 05:53:11.542301 Standard timings supported:
9017 05:53:11.545626 Detailed timings
9018 05:53:11.548877 Hex of detail: 383680a07038204018303c0035ae10000019
9019 05:53:11.555319 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9020 05:53:11.558661 0780 0798 07c8 0820 hborder 0
9021 05:53:11.562108 0438 043b 0447 0458 vborder 0
9022 05:53:11.565467 -hsync -vsync
9023 05:53:11.565548 Did detailed timing
9024 05:53:11.571838 Hex of detail: 000000000000000000000000000000000000
9025 05:53:11.575394 Manufacturer-specified data, tag 0
9026 05:53:11.578680 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9027 05:53:11.581877 ASCII string: InfoVision
9028 05:53:11.584939 Hex of detail: 000000fe00523134304e574635205248200a
9029 05:53:11.588361 ASCII string: R140NWF5 RH
9030 05:53:11.588441 Checksum
9031 05:53:11.591658 Checksum: 0xfb (valid)
9032 05:53:11.595100 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9033 05:53:11.598400 DSI data_rate: 832800000 bps
9034 05:53:11.604690 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9035 05:53:11.608057 anx7625_parse_edid: pixelclock(138800).
9036 05:53:11.611332 hactive(1920), hsync(48), hfp(24), hbp(88)
9037 05:53:11.614752 vactive(1080), vsync(12), vfp(3), vbp(17)
9038 05:53:11.618066 anx7625_dsi_config: config dsi.
9039 05:53:11.624500 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9040 05:53:11.638978 anx7625_dsi_config: success to config DSI
9041 05:53:11.641859 anx7625_dp_start: MIPI phy setup OK.
9042 05:53:11.645340 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9043 05:53:11.648508 mtk_ddp_mode_set invalid vrefresh 60
9044 05:53:11.651498 main_disp_path_setup
9045 05:53:11.651611 ovl_layer_smi_id_en
9046 05:53:11.654827 ovl_layer_smi_id_en
9047 05:53:11.654912 ccorr_config
9048 05:53:11.654976 aal_config
9049 05:53:11.658668 gamma_config
9050 05:53:11.658749 postmask_config
9051 05:53:11.661320 dither_config
9052 05:53:11.665016 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9053 05:53:11.671767 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9054 05:53:11.674864 Root Device init finished in 529 msecs
9055 05:53:11.678455 CPU_CLUSTER: 0 init
9056 05:53:11.684933 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9057 05:53:11.691531 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9058 05:53:11.691614 APU_MBOX 0x190000b0 = 0x10001
9059 05:53:11.694985 APU_MBOX 0x190001b0 = 0x10001
9060 05:53:11.698153 APU_MBOX 0x190005b0 = 0x10001
9061 05:53:11.701522 APU_MBOX 0x190006b0 = 0x10001
9062 05:53:11.708047 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9063 05:53:11.717541 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9064 05:53:11.730052 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9065 05:53:11.736676 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9066 05:53:11.748624 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9067 05:53:11.757505 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9068 05:53:11.760543 CPU_CLUSTER: 0 init finished in 81 msecs
9069 05:53:11.764159 Devices initialized
9070 05:53:11.767207 Show all devs... After init.
9071 05:53:11.767289 Root Device: enabled 1
9072 05:53:11.770809 CPU_CLUSTER: 0: enabled 1
9073 05:53:11.773804 CPU: 00: enabled 1
9074 05:53:11.777151 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9075 05:53:11.780661 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9076 05:53:11.783893 ELOG: NV offset 0x57f000 size 0x1000
9077 05:53:11.790307 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9078 05:53:11.797241 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9079 05:53:11.800567 ELOG: Event(17) added with size 13 at 2023-12-25 05:53:11 UTC
9080 05:53:11.807175 out: cmd=0x121: 03 db 21 01 00 00 00 00
9081 05:53:11.810223 in-header: 03 0e 00 00 2c 00 00 00
9082 05:53:11.823560 in-data: 55 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9083 05:53:11.826588 ELOG: Event(A1) added with size 10 at 2023-12-25 05:53:11 UTC
9084 05:53:11.833535 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9085 05:53:11.840285 ELOG: Event(A0) added with size 9 at 2023-12-25 05:53:12 UTC
9086 05:53:11.843576 elog_add_boot_reason: Logged dev mode boot
9087 05:53:11.850608 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9088 05:53:11.850690 Finalize devices...
9089 05:53:11.853686 Devices finalized
9090 05:53:11.856737 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9091 05:53:11.860172 Writing coreboot table at 0xffe64000
9092 05:53:11.863332 0. 000000000010a000-0000000000113fff: RAMSTAGE
9093 05:53:11.870011 1. 0000000040000000-00000000400fffff: RAM
9094 05:53:11.873140 2. 0000000040100000-000000004032afff: RAMSTAGE
9095 05:53:11.876687 3. 000000004032b000-00000000545fffff: RAM
9096 05:53:11.880247 4. 0000000054600000-000000005465ffff: BL31
9097 05:53:11.883578 5. 0000000054660000-00000000ffe63fff: RAM
9098 05:53:11.889607 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9099 05:53:11.892910 7. 0000000100000000-000000013fffffff: RAM
9100 05:53:11.896370 Passing 5 GPIOs to payload:
9101 05:53:11.899956 NAME | PORT | POLARITY | VALUE
9102 05:53:11.906429 EC in RW | 0x000000aa | low | undefined
9103 05:53:11.909989 EC interrupt | 0x00000005 | low | undefined
9104 05:53:11.913019 TPM interrupt | 0x000000ab | high | undefined
9105 05:53:11.919634 SD card detect | 0x00000011 | high | undefined
9106 05:53:11.922717 speaker enable | 0x00000093 | high | undefined
9107 05:53:11.925949 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9108 05:53:11.929496 in-header: 03 f8 00 00 02 00 00 00
9109 05:53:11.932517 in-data: 03 00
9110 05:53:11.935837 ADC[4]: Raw value=668590 ID=5
9111 05:53:11.935919 ADC[3]: Raw value=212180 ID=1
9112 05:53:11.939535 RAM Code: 0x51
9113 05:53:11.942607 ADC[6]: Raw value=74778 ID=0
9114 05:53:11.942713 ADC[5]: Raw value=211444 ID=1
9115 05:53:11.946085 SKU Code: 0x1
9116 05:53:11.952521 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 97e2
9117 05:53:11.952603 coreboot table: 964 bytes.
9118 05:53:11.955849 IMD ROOT 0. 0xfffff000 0x00001000
9119 05:53:11.959336 IMD SMALL 1. 0xffffe000 0x00001000
9120 05:53:11.962765 RO MCACHE 2. 0xffffc000 0x00001104
9121 05:53:11.965868 CONSOLE 3. 0xfff7c000 0x00080000
9122 05:53:11.968885 FMAP 4. 0xfff7b000 0x00000452
9123 05:53:11.972238 TIME STAMP 5. 0xfff7a000 0x00000910
9124 05:53:11.975770 VBOOT WORK 6. 0xfff66000 0x00014000
9125 05:53:11.979053 RAMOOPS 7. 0xffe66000 0x00100000
9126 05:53:11.982399 COREBOOT 8. 0xffe64000 0x00002000
9127 05:53:11.985530 IMD small region:
9128 05:53:11.988645 IMD ROOT 0. 0xffffec00 0x00000400
9129 05:53:11.992530 VPD 1. 0xffffeb80 0x0000006c
9130 05:53:11.995451 MMC STATUS 2. 0xffffeb60 0x00000004
9131 05:53:11.998933 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9132 05:53:12.002116 Probing TPM: done!
9133 05:53:12.005946 Connected to device vid:did:rid of 1ae0:0028:00
9134 05:53:12.016894 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9135 05:53:12.020029 Initialized TPM device CR50 revision 0
9136 05:53:12.023200 Checking cr50 for pending updates
9137 05:53:12.027197 Reading cr50 TPM mode
9138 05:53:12.035988 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9139 05:53:12.042256 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9140 05:53:12.082725 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9141 05:53:12.085660 Checking segment from ROM address 0x40100000
9142 05:53:12.089851 Checking segment from ROM address 0x4010001c
9143 05:53:12.095925 Loading segment from ROM address 0x40100000
9144 05:53:12.096007 code (compression=0)
9145 05:53:12.105831 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9146 05:53:12.112867 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9147 05:53:12.112949 it's not compressed!
9148 05:53:12.119241 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9149 05:53:12.122781 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9150 05:53:12.142918 Loading segment from ROM address 0x4010001c
9151 05:53:12.143001 Entry Point 0x80000000
9152 05:53:12.146599 Loaded segments
9153 05:53:12.149741 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9154 05:53:12.156088 Jumping to boot code at 0x80000000(0xffe64000)
9155 05:53:12.162889 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9156 05:53:12.169488 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9157 05:53:12.177632 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9158 05:53:12.180599 Checking segment from ROM address 0x40100000
9159 05:53:12.184166 Checking segment from ROM address 0x4010001c
9160 05:53:12.190978 Loading segment from ROM address 0x40100000
9161 05:53:12.191060 code (compression=1)
9162 05:53:12.197465 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9163 05:53:12.207076 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9164 05:53:12.207159 using LZMA
9165 05:53:12.215759 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9166 05:53:12.222433 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9167 05:53:12.225774 Loading segment from ROM address 0x4010001c
9168 05:53:12.225856 Entry Point 0x54601000
9169 05:53:12.229433 Loaded segments
9170 05:53:12.232331 NOTICE: MT8192 bl31_setup
9171 05:53:12.239117 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9172 05:53:12.242788 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9173 05:53:12.246010 WARNING: region 0:
9174 05:53:12.249640 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9175 05:53:12.249721 WARNING: region 1:
9176 05:53:12.255846 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9177 05:53:12.259311 WARNING: region 2:
9178 05:53:12.262781 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9179 05:53:12.265761 WARNING: region 3:
9180 05:53:12.269351 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9181 05:53:12.272941 WARNING: region 4:
9182 05:53:12.279346 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9183 05:53:12.279428 WARNING: region 5:
9184 05:53:12.282723 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9185 05:53:12.285776 WARNING: region 6:
9186 05:53:12.289122 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9187 05:53:12.292852 WARNING: region 7:
9188 05:53:12.296041 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9189 05:53:12.302560 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9190 05:53:12.305991 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9191 05:53:12.309499 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9192 05:53:12.316305 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9193 05:53:12.319248 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9194 05:53:12.322395 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9195 05:53:12.329033 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9196 05:53:12.332431 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9197 05:53:12.339104 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9198 05:53:12.342230 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9199 05:53:12.345768 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9200 05:53:12.352938 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9201 05:53:12.355858 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9202 05:53:12.359383 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9203 05:53:12.365689 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9204 05:53:12.369007 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9205 05:53:12.375673 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9206 05:53:12.379383 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9207 05:53:12.382817 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9208 05:53:12.389026 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9209 05:53:12.392419 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9210 05:53:12.395964 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9211 05:53:12.402036 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9212 05:53:12.405626 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9213 05:53:12.412304 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9214 05:53:12.415505 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9215 05:53:12.418804 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9216 05:53:12.425354 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9217 05:53:12.429086 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9218 05:53:12.435487 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9219 05:53:12.438856 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9220 05:53:12.442319 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9221 05:53:12.449146 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9222 05:53:12.452217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9223 05:53:12.455630 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9224 05:53:12.458909 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9225 05:53:12.465277 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9226 05:53:12.468899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9227 05:53:12.472485 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9228 05:53:12.475432 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9229 05:53:12.482462 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9230 05:53:12.485409 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9231 05:53:12.488999 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9232 05:53:12.491915 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9233 05:53:12.498822 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9234 05:53:12.502561 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9235 05:53:12.505211 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9236 05:53:12.508556 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9237 05:53:12.515072 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9238 05:53:12.519096 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9239 05:53:12.525059 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9240 05:53:12.528644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9241 05:53:12.535033 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9242 05:53:12.538825 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9243 05:53:12.542049 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9244 05:53:12.548720 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9245 05:53:12.551954 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9246 05:53:12.558394 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9247 05:53:12.561753 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9248 05:53:12.568370 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9249 05:53:12.571803 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9250 05:53:12.578692 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9251 05:53:12.582122 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9252 05:53:12.585422 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9253 05:53:12.592113 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9254 05:53:12.595172 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9255 05:53:12.601927 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9256 05:53:12.605092 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9257 05:53:12.611607 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9258 05:53:12.615238 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9259 05:53:12.618639 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9260 05:53:12.625273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9261 05:53:12.628645 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9262 05:53:12.635264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9263 05:53:12.638664 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9264 05:53:12.644936 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9265 05:53:12.648510 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9266 05:53:12.651858 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9267 05:53:12.658109 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9268 05:53:12.662238 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9269 05:53:12.668387 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9270 05:53:12.671626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9271 05:53:12.678468 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9272 05:53:12.681927 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9273 05:53:12.688064 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9274 05:53:12.691982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9275 05:53:12.695068 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9276 05:53:12.701545 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9277 05:53:12.704852 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9278 05:53:12.711425 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9279 05:53:12.714682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9280 05:53:12.721165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9281 05:53:12.724580 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9282 05:53:12.727996 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9283 05:53:12.735141 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9284 05:53:12.738398 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9285 05:53:12.744946 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9286 05:53:12.748177 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9287 05:53:12.751424 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9288 05:53:12.754969 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9289 05:53:12.761351 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9290 05:53:12.764862 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9291 05:53:12.768281 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9292 05:53:12.774790 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9293 05:53:12.778182 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9294 05:53:12.784887 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9295 05:53:12.787955 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9296 05:53:12.791572 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9297 05:53:12.797968 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9298 05:53:12.801231 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9299 05:53:12.808292 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9300 05:53:12.811434 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9301 05:53:12.814798 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9302 05:53:12.821209 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9303 05:53:12.824619 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9304 05:53:12.831415 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9305 05:53:12.834677 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9306 05:53:12.837645 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9307 05:53:12.844354 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9308 05:53:12.847555 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9309 05:53:12.851312 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9310 05:53:12.854629 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9311 05:53:12.857811 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9312 05:53:12.864441 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9313 05:53:12.867600 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9314 05:53:12.874474 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9315 05:53:12.877855 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9316 05:53:12.880933 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9317 05:53:12.887606 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9318 05:53:12.891075 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9319 05:53:12.931263 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9320 05:53:12.931395 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9321 05:53:12.931497 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9322 05:53:12.931594 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9323 05:53:12.931687 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9324 05:53:12.931777 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9325 05:53:12.931865 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9326 05:53:12.931959 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9327 05:53:12.933902 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9328 05:53:12.937189 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9329 05:53:12.941110 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9330 05:53:12.947530 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9331 05:53:12.950726 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9332 05:53:12.957292 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9333 05:53:12.960977 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9334 05:53:12.964200 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9335 05:53:12.970891 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9336 05:53:12.974395 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9337 05:53:12.977502 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9338 05:53:12.984459 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9339 05:53:12.987618 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9340 05:53:12.994415 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9341 05:53:12.997971 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9342 05:53:13.001095 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9343 05:53:13.007743 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9344 05:53:13.010954 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9345 05:53:13.014372 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9346 05:53:13.020974 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9347 05:53:13.024132 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9348 05:53:13.031272 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9349 05:53:13.034605 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9350 05:53:13.037592 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9351 05:53:13.044170 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9352 05:53:13.047260 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9353 05:53:13.053974 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9354 05:53:13.057394 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9355 05:53:13.060582 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9356 05:53:13.067151 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9357 05:53:13.070833 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9358 05:53:13.077154 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9359 05:53:13.080160 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9360 05:53:13.086980 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9361 05:53:13.090264 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9362 05:53:13.093482 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9363 05:53:13.100120 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9364 05:53:13.103410 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9365 05:53:13.106973 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9366 05:53:13.113246 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9367 05:53:13.116819 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9368 05:53:13.123470 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9369 05:53:13.126906 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9370 05:53:13.129765 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9371 05:53:13.136282 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9372 05:53:13.139733 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9373 05:53:13.146244 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9374 05:53:13.149656 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9375 05:53:13.153226 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9376 05:53:13.160009 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9377 05:53:13.162896 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9378 05:53:13.169927 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9379 05:53:13.173254 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9380 05:53:13.179341 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9381 05:53:13.183078 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9382 05:53:13.186125 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9383 05:53:13.192855 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9384 05:53:13.196375 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9385 05:53:13.203034 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9386 05:53:13.206277 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9387 05:53:13.209575 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9388 05:53:13.216267 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9389 05:53:13.219319 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9390 05:53:13.225861 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9391 05:53:13.229659 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9392 05:53:13.235994 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9393 05:53:13.239024 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9394 05:53:13.242299 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9395 05:53:13.249059 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9396 05:53:13.252135 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9397 05:53:13.258619 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9398 05:53:13.261985 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9399 05:53:13.268815 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9400 05:53:13.271908 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9401 05:53:13.275596 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9402 05:53:13.282013 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9403 05:53:13.285661 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9404 05:53:13.292255 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9405 05:53:13.295069 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9406 05:53:13.298434 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9407 05:53:13.305101 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9408 05:53:13.308338 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9409 05:53:13.314972 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9410 05:53:13.318427 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9411 05:53:13.325082 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9412 05:53:13.328547 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9413 05:53:13.331568 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9414 05:53:13.338609 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9415 05:53:13.341349 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9416 05:53:13.348141 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9417 05:53:13.351754 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9418 05:53:13.354766 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9419 05:53:13.361303 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9420 05:53:13.364629 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9421 05:53:13.367986 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9422 05:53:13.371421 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9423 05:53:13.377739 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9424 05:53:13.381320 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9425 05:53:13.385054 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9426 05:53:13.391523 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9427 05:53:13.394914 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9428 05:53:13.398129 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9429 05:53:13.404834 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9430 05:53:13.407870 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9431 05:53:13.414612 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9432 05:53:13.417938 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9433 05:53:13.421633 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9434 05:53:13.428148 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9435 05:53:13.431184 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9436 05:53:13.434425 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9437 05:53:13.441192 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9438 05:53:13.444701 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9439 05:53:13.450941 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9440 05:53:13.454388 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9441 05:53:13.457625 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9442 05:53:13.464113 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9443 05:53:13.467878 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9444 05:53:13.470812 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9445 05:53:13.477416 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9446 05:53:13.480957 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9447 05:53:13.484234 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9448 05:53:13.490673 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9449 05:53:13.494164 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9450 05:53:13.500494 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9451 05:53:13.503657 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9452 05:53:13.507158 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9453 05:53:13.513998 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9454 05:53:13.517051 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9455 05:53:13.523989 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9456 05:53:13.527026 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9457 05:53:13.530585 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9458 05:53:13.533938 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9459 05:53:13.540466 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9460 05:53:13.543763 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9461 05:53:13.547209 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9462 05:53:13.550429 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9463 05:53:13.557146 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9464 05:53:13.560147 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9465 05:53:13.563612 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9466 05:53:13.566998 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9467 05:53:13.573422 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9468 05:53:13.576983 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9469 05:53:13.580488 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9470 05:53:13.583335 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9471 05:53:13.590241 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9472 05:53:13.593522 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9473 05:53:13.599941 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9474 05:53:13.603321 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9475 05:53:13.609998 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9476 05:53:13.613211 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9477 05:53:13.619941 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9478 05:53:13.623200 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9479 05:53:13.626527 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9480 05:53:13.633195 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9481 05:53:13.636251 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9482 05:53:13.639500 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9483 05:53:13.646285 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9484 05:53:13.649579 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9485 05:53:13.656253 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9486 05:53:13.659695 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9487 05:53:13.666021 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9488 05:53:13.669455 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9489 05:53:13.672255 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9490 05:53:13.678939 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9491 05:53:13.682617 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9492 05:53:13.688977 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9493 05:53:13.692129 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9494 05:53:13.695499 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9495 05:53:13.702027 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9496 05:53:13.705366 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9497 05:53:13.712291 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9498 05:53:13.715557 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9499 05:53:13.721920 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9500 05:53:13.725233 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9501 05:53:13.728662 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9502 05:53:13.735345 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9503 05:53:13.738745 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9504 05:53:13.744828 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9505 05:53:13.748361 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9506 05:53:13.751626 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9507 05:53:13.758411 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9508 05:53:13.761600 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9509 05:53:13.768171 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9510 05:53:13.771307 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9511 05:53:13.777990 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9512 05:53:13.781383 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9513 05:53:13.784394 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9514 05:53:13.791221 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9515 05:53:13.794133 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9516 05:53:13.801625 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9517 05:53:13.804236 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9518 05:53:13.807247 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9519 05:53:13.814809 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9520 05:53:13.817547 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9521 05:53:13.823965 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9522 05:53:13.827641 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9523 05:53:13.834252 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9524 05:53:13.837028 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9525 05:53:13.840418 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9526 05:53:13.847222 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9527 05:53:13.850812 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9528 05:53:13.856841 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9529 05:53:13.860423 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9530 05:53:13.863656 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9531 05:53:13.870090 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9532 05:53:13.873346 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9533 05:53:13.880097 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9534 05:53:13.883385 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9535 05:53:13.886793 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9536 05:53:13.893423 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9537 05:53:13.897137 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9538 05:53:13.903179 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9539 05:53:13.906589 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9540 05:53:13.913172 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9541 05:53:13.916345 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9542 05:53:13.919920 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9543 05:53:13.926422 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9544 05:53:13.930011 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9545 05:53:13.936348 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9546 05:53:13.939611 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9547 05:53:13.946190 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9548 05:53:13.949413 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9549 05:53:13.956163 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9550 05:53:13.959272 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9551 05:53:13.962767 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9552 05:53:13.969167 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9553 05:53:13.972651 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9554 05:53:13.979242 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9555 05:53:13.982953 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9556 05:53:13.989181 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9557 05:53:13.992628 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9558 05:53:13.995900 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9559 05:53:14.002220 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9560 05:53:14.005761 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9561 05:53:14.012613 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9562 05:53:14.015796 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9563 05:53:14.022318 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9564 05:53:14.025310 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9565 05:53:14.031921 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9566 05:53:14.035621 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9567 05:53:14.038709 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9568 05:53:14.045323 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9569 05:53:14.048890 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9570 05:53:14.055201 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9571 05:53:14.058340 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9572 05:53:14.065286 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9573 05:53:14.068494 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9574 05:53:14.071756 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9575 05:53:14.078294 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9576 05:53:14.081480 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9577 05:53:14.088297 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9578 05:53:14.091612 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9579 05:53:14.098268 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9580 05:53:14.101362 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9581 05:53:14.108003 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9582 05:53:14.111571 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9583 05:53:14.114716 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9584 05:53:14.121321 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9585 05:53:14.124392 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9586 05:53:14.131172 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9587 05:53:14.134299 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9588 05:53:14.141297 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9589 05:53:14.144794 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9590 05:53:14.151057 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9591 05:53:14.154459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9592 05:53:14.157820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9593 05:53:14.164081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9594 05:53:14.167610 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9595 05:53:14.173781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9596 05:53:14.177451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9597 05:53:14.183908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9598 05:53:14.187097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9599 05:53:14.193501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9600 05:53:14.196883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9601 05:53:14.203696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9602 05:53:14.207288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9603 05:53:14.213862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9604 05:53:14.217094 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9605 05:53:14.223477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9606 05:53:14.227070 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9607 05:53:14.233338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9608 05:53:14.236713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9609 05:53:14.243226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9610 05:53:14.246677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9611 05:53:14.253180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9612 05:53:14.256606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9613 05:53:14.262838 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9614 05:53:14.266108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9615 05:53:14.273207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9616 05:53:14.276303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9617 05:53:14.283176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9618 05:53:14.286263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9619 05:53:14.292951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9620 05:53:14.295884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9621 05:53:14.302678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9622 05:53:14.305805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9623 05:53:14.312953 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9624 05:53:14.313037 INFO: [APUAPC] vio 0
9625 05:53:14.319500 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9626 05:53:14.322791 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9627 05:53:14.326074 INFO: [APUAPC] D0_APC_0: 0x400510
9628 05:53:14.329617 INFO: [APUAPC] D0_APC_1: 0x0
9629 05:53:14.332471 INFO: [APUAPC] D0_APC_2: 0x1540
9630 05:53:14.335653 INFO: [APUAPC] D0_APC_3: 0x0
9631 05:53:14.339164 INFO: [APUAPC] D1_APC_0: 0xffffffff
9632 05:53:14.342236 INFO: [APUAPC] D1_APC_1: 0xffffffff
9633 05:53:14.345489 INFO: [APUAPC] D1_APC_2: 0x3fffff
9634 05:53:14.348922 INFO: [APUAPC] D1_APC_3: 0x0
9635 05:53:14.352263 INFO: [APUAPC] D2_APC_0: 0xffffffff
9636 05:53:14.355588 INFO: [APUAPC] D2_APC_1: 0xffffffff
9637 05:53:14.358752 INFO: [APUAPC] D2_APC_2: 0x3fffff
9638 05:53:14.362468 INFO: [APUAPC] D2_APC_3: 0x0
9639 05:53:14.365328 INFO: [APUAPC] D3_APC_0: 0xffffffff
9640 05:53:14.368713 INFO: [APUAPC] D3_APC_1: 0xffffffff
9641 05:53:14.371993 INFO: [APUAPC] D3_APC_2: 0x3fffff
9642 05:53:14.375410 INFO: [APUAPC] D3_APC_3: 0x0
9643 05:53:14.378649 INFO: [APUAPC] D4_APC_0: 0xffffffff
9644 05:53:14.381787 INFO: [APUAPC] D4_APC_1: 0xffffffff
9645 05:53:14.385185 INFO: [APUAPC] D4_APC_2: 0x3fffff
9646 05:53:14.388309 INFO: [APUAPC] D4_APC_3: 0x0
9647 05:53:14.391851 INFO: [APUAPC] D5_APC_0: 0xffffffff
9648 05:53:14.394986 INFO: [APUAPC] D5_APC_1: 0xffffffff
9649 05:53:14.398381 INFO: [APUAPC] D5_APC_2: 0x3fffff
9650 05:53:14.398459 INFO: [APUAPC] D5_APC_3: 0x0
9651 05:53:14.404910 INFO: [APUAPC] D6_APC_0: 0xffffffff
9652 05:53:14.408339 INFO: [APUAPC] D6_APC_1: 0xffffffff
9653 05:53:14.411941 INFO: [APUAPC] D6_APC_2: 0x3fffff
9654 05:53:14.412038 INFO: [APUAPC] D6_APC_3: 0x0
9655 05:53:14.414901 INFO: [APUAPC] D7_APC_0: 0xffffffff
9656 05:53:14.421634 INFO: [APUAPC] D7_APC_1: 0xffffffff
9657 05:53:14.424693 INFO: [APUAPC] D7_APC_2: 0x3fffff
9658 05:53:14.424787 INFO: [APUAPC] D7_APC_3: 0x0
9659 05:53:14.427993 INFO: [APUAPC] D8_APC_0: 0xffffffff
9660 05:53:14.431563 INFO: [APUAPC] D8_APC_1: 0xffffffff
9661 05:53:14.434468 INFO: [APUAPC] D8_APC_2: 0x3fffff
9662 05:53:14.438240 INFO: [APUAPC] D8_APC_3: 0x0
9663 05:53:14.441517 INFO: [APUAPC] D9_APC_0: 0xffffffff
9664 05:53:14.444364 INFO: [APUAPC] D9_APC_1: 0xffffffff
9665 05:53:14.447709 INFO: [APUAPC] D9_APC_2: 0x3fffff
9666 05:53:14.451612 INFO: [APUAPC] D9_APC_3: 0x0
9667 05:53:14.454583 INFO: [APUAPC] D10_APC_0: 0xffffffff
9668 05:53:14.458143 INFO: [APUAPC] D10_APC_1: 0xffffffff
9669 05:53:14.461111 INFO: [APUAPC] D10_APC_2: 0x3fffff
9670 05:53:14.464417 INFO: [APUAPC] D10_APC_3: 0x0
9671 05:53:14.467609 INFO: [APUAPC] D11_APC_0: 0xffffffff
9672 05:53:14.471164 INFO: [APUAPC] D11_APC_1: 0xffffffff
9673 05:53:14.474278 INFO: [APUAPC] D11_APC_2: 0x3fffff
9674 05:53:14.477641 INFO: [APUAPC] D11_APC_3: 0x0
9675 05:53:14.481447 INFO: [APUAPC] D12_APC_0: 0xffffffff
9676 05:53:14.484252 INFO: [APUAPC] D12_APC_1: 0xffffffff
9677 05:53:14.487712 INFO: [APUAPC] D12_APC_2: 0x3fffff
9678 05:53:14.490697 INFO: [APUAPC] D12_APC_3: 0x0
9679 05:53:14.494547 INFO: [APUAPC] D13_APC_0: 0xffffffff
9680 05:53:14.500680 INFO: [APUAPC] D13_APC_1: 0xffffffff
9681 05:53:14.504136 INFO: [APUAPC] D13_APC_2: 0x3fffff
9682 05:53:14.504217 INFO: [APUAPC] D13_APC_3: 0x0
9683 05:53:14.507516 INFO: [APUAPC] D14_APC_0: 0xffffffff
9684 05:53:14.514443 INFO: [APUAPC] D14_APC_1: 0xffffffff
9685 05:53:14.517762 INFO: [APUAPC] D14_APC_2: 0x3fffff
9686 05:53:14.517843 INFO: [APUAPC] D14_APC_3: 0x0
9687 05:53:14.523949 INFO: [APUAPC] D15_APC_0: 0xffffffff
9688 05:53:14.527220 INFO: [APUAPC] D15_APC_1: 0xffffffff
9689 05:53:14.530464 INFO: [APUAPC] D15_APC_2: 0x3fffff
9690 05:53:14.530544 INFO: [APUAPC] D15_APC_3: 0x0
9691 05:53:14.533715 INFO: [APUAPC] APC_CON: 0x4
9692 05:53:14.536896 INFO: [NOCDAPC] D0_APC_0: 0x0
9693 05:53:14.540596 INFO: [NOCDAPC] D0_APC_1: 0x0
9694 05:53:14.543566 INFO: [NOCDAPC] D1_APC_0: 0x0
9695 05:53:14.546945 INFO: [NOCDAPC] D1_APC_1: 0xfff
9696 05:53:14.550350 INFO: [NOCDAPC] D2_APC_0: 0x0
9697 05:53:14.553879 INFO: [NOCDAPC] D2_APC_1: 0xfff
9698 05:53:14.556606 INFO: [NOCDAPC] D3_APC_0: 0x0
9699 05:53:14.559995 INFO: [NOCDAPC] D3_APC_1: 0xfff
9700 05:53:14.563309 INFO: [NOCDAPC] D4_APC_0: 0x0
9701 05:53:14.563390 INFO: [NOCDAPC] D4_APC_1: 0xfff
9702 05:53:14.566592 INFO: [NOCDAPC] D5_APC_0: 0x0
9703 05:53:14.570001 INFO: [NOCDAPC] D5_APC_1: 0xfff
9704 05:53:14.573564 INFO: [NOCDAPC] D6_APC_0: 0x0
9705 05:53:14.576880 INFO: [NOCDAPC] D6_APC_1: 0xfff
9706 05:53:14.579806 INFO: [NOCDAPC] D7_APC_0: 0x0
9707 05:53:14.583099 INFO: [NOCDAPC] D7_APC_1: 0xfff
9708 05:53:14.586754 INFO: [NOCDAPC] D8_APC_0: 0x0
9709 05:53:14.589916 INFO: [NOCDAPC] D8_APC_1: 0xfff
9710 05:53:14.593454 INFO: [NOCDAPC] D9_APC_0: 0x0
9711 05:53:14.596595 INFO: [NOCDAPC] D9_APC_1: 0xfff
9712 05:53:14.596690 INFO: [NOCDAPC] D10_APC_0: 0x0
9713 05:53:14.599612 INFO: [NOCDAPC] D10_APC_1: 0xfff
9714 05:53:14.603075 INFO: [NOCDAPC] D11_APC_0: 0x0
9715 05:53:14.606538 INFO: [NOCDAPC] D11_APC_1: 0xfff
9716 05:53:14.609678 INFO: [NOCDAPC] D12_APC_0: 0x0
9717 05:53:14.613464 INFO: [NOCDAPC] D12_APC_1: 0xfff
9718 05:53:14.616334 INFO: [NOCDAPC] D13_APC_0: 0x0
9719 05:53:14.619670 INFO: [NOCDAPC] D13_APC_1: 0xfff
9720 05:53:14.623239 INFO: [NOCDAPC] D14_APC_0: 0x0
9721 05:53:14.626520 INFO: [NOCDAPC] D14_APC_1: 0xfff
9722 05:53:14.629717 INFO: [NOCDAPC] D15_APC_0: 0x0
9723 05:53:14.633114 INFO: [NOCDAPC] D15_APC_1: 0xfff
9724 05:53:14.636351 INFO: [NOCDAPC] APC_CON: 0x4
9725 05:53:14.639762 INFO: [APUAPC] set_apusys_apc done
9726 05:53:14.642739 INFO: [DEVAPC] devapc_init done
9727 05:53:14.645928 INFO: GICv3 without legacy support detected.
9728 05:53:14.649131 INFO: ARM GICv3 driver initialized in EL3
9729 05:53:14.652972 INFO: Maximum SPI INTID supported: 639
9730 05:53:14.655907 INFO: BL31: Initializing runtime services
9731 05:53:14.662749 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9732 05:53:14.665867 INFO: SPM: enable CPC mode
9733 05:53:14.672420 INFO: mcdi ready for mcusys-off-idle and system suspend
9734 05:53:14.675626 INFO: BL31: Preparing for EL3 exit to normal world
9735 05:53:14.678925 INFO: Entry point address = 0x80000000
9736 05:53:14.682453 INFO: SPSR = 0x8
9737 05:53:14.687081
9738 05:53:14.687161
9739 05:53:14.687225
9740 05:53:14.690741 Starting depthcharge on Spherion...
9741 05:53:14.690822
9742 05:53:14.690886 Wipe memory regions:
9743 05:53:14.690945
9744 05:53:14.691575 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9745 05:53:14.691679 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9746 05:53:14.691762 Setting prompt string to ['asurada:']
9747 05:53:14.691840 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9748 05:53:14.693791 [0x00000040000000, 0x00000054600000)
9749 05:53:14.816385
9750 05:53:14.816500 [0x00000054660000, 0x00000080000000)
9751 05:53:15.076925
9752 05:53:15.077067 [0x000000821a7280, 0x000000ffe64000)
9753 05:53:15.821413
9754 05:53:15.821561 [0x00000100000000, 0x00000140000000)
9755 05:53:16.202324
9756 05:53:16.205849 Initializing XHCI USB controller at 0x11200000.
9757 05:53:17.243633
9758 05:53:17.246858 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9759 05:53:17.246945
9760 05:53:17.247010
9761 05:53:17.247070
9762 05:53:17.247349 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9764 05:53:17.347724 asurada: tftpboot 192.168.201.1 12379427/tftp-deploy-3jn6beu8/kernel/image.itb 12379427/tftp-deploy-3jn6beu8/kernel/cmdline
9765 05:53:17.347886 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9766 05:53:17.347989 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9767 05:53:17.351792 tftpboot 192.168.201.1 12379427/tftp-deploy-3jn6beu8/kernel/image.itp-deploy-3jn6beu8/kernel/cmdline
9768 05:53:17.351877
9769 05:53:17.351942 Waiting for link
9770 05:53:17.512900
9771 05:53:17.513023 R8152: Initializing
9772 05:53:17.513107
9773 05:53:17.515741 Version 9 (ocp_data = 6010)
9774 05:53:17.515814
9775 05:53:17.519134 R8152: Done initializing
9776 05:53:17.519240
9777 05:53:17.519331 Adding net device
9778 05:53:19.520736
9779 05:53:19.520889 done.
9780 05:53:19.520959
9781 05:53:19.521020 MAC: 00:e0:4c:68:03:bd
9782 05:53:19.521079
9783 05:53:19.523844 Sending DHCP discover... done.
9784 05:53:19.523953
9785 05:53:19.527202 Waiting for reply... done.
9786 05:53:19.527286
9787 05:53:19.530364 Sending DHCP request... done.
9788 05:53:19.530446
9789 05:53:19.530511 Waiting for reply... done.
9790 05:53:19.533823
9791 05:53:19.533903 My ip is 192.168.201.16
9792 05:53:19.533968
9793 05:53:19.537459 The DHCP server ip is 192.168.201.1
9794 05:53:19.537541
9795 05:53:19.540230 TFTP server IP predefined by user: 192.168.201.1
9796 05:53:19.540326
9797 05:53:19.547246 Bootfile predefined by user: 12379427/tftp-deploy-3jn6beu8/kernel/image.itb
9798 05:53:19.547343
9799 05:53:19.550117 Sending tftp read request... done.
9800 05:53:19.550228
9801 05:53:19.553476 Waiting for the transfer...
9802 05:53:19.553557
9803 05:53:19.806490 00000000 ################################################################
9804 05:53:19.806650
9805 05:53:20.056951 00080000 ################################################################
9806 05:53:20.057083
9807 05:53:20.307091 00100000 ################################################################
9808 05:53:20.307269
9809 05:53:20.556302 00180000 ################################################################
9810 05:53:20.556438
9811 05:53:20.805974 00200000 ################################################################
9812 05:53:20.806110
9813 05:53:21.058493 00280000 ################################################################
9814 05:53:21.058634
9815 05:53:21.318529 00300000 ################################################################
9816 05:53:21.318660
9817 05:53:21.575995 00380000 ################################################################
9818 05:53:21.576140
9819 05:53:21.846084 00400000 ################################################################
9820 05:53:21.846212
9821 05:53:22.098872 00480000 ################################################################
9822 05:53:22.099029
9823 05:53:22.355979 00500000 ################################################################
9824 05:53:22.356145
9825 05:53:22.616336 00580000 ################################################################
9826 05:53:22.616466
9827 05:53:22.879695 00600000 ################################################################
9828 05:53:22.879852
9829 05:53:23.137797 00680000 ################################################################
9830 05:53:23.137957
9831 05:53:23.395063 00700000 ################################################################
9832 05:53:23.395197
9833 05:53:23.653240 00780000 ################################################################
9834 05:53:23.653378
9835 05:53:23.909703 00800000 ################################################################
9836 05:53:23.909836
9837 05:53:24.164888 00880000 ################################################################
9838 05:53:24.165051
9839 05:53:24.419569 00900000 ################################################################
9840 05:53:24.419709
9841 05:53:24.678341 00980000 ################################################################
9842 05:53:24.678481
9843 05:53:24.933700 00a00000 ################################################################
9844 05:53:24.933832
9845 05:53:25.190040 00a80000 ################################################################
9846 05:53:25.190176
9847 05:53:25.448875 00b00000 ################################################################
9848 05:53:25.449005
9849 05:53:25.704474 00b80000 ################################################################
9850 05:53:25.704618
9851 05:53:25.961042 00c00000 ################################################################
9852 05:53:25.961171
9853 05:53:26.216758 00c80000 ################################################################
9854 05:53:26.216906
9855 05:53:26.472696 00d00000 ################################################################
9856 05:53:26.472845
9857 05:53:26.731951 00d80000 ################################################################
9858 05:53:26.732108
9859 05:53:26.990136 00e00000 ################################################################
9860 05:53:26.990267
9861 05:53:27.256282 00e80000 ################################################################
9862 05:53:27.256412
9863 05:53:27.518411 00f00000 ################################################################
9864 05:53:27.518566
9865 05:53:27.784521 00f80000 ################################################################
9866 05:53:27.784670
9867 05:53:28.044082 01000000 ################################################################
9868 05:53:28.044215
9869 05:53:28.305361 01080000 ################################################################
9870 05:53:28.305498
9871 05:53:28.567345 01100000 ################################################################
9872 05:53:28.567479
9873 05:53:28.828978 01180000 ################################################################
9874 05:53:28.829126
9875 05:53:29.090165 01200000 ################################################################
9876 05:53:29.090329
9877 05:53:29.351250 01280000 ################################################################
9878 05:53:29.351409
9879 05:53:29.610719 01300000 ################################################################
9880 05:53:29.610879
9881 05:53:29.873608 01380000 ################################################################
9882 05:53:29.873755
9883 05:53:30.136819 01400000 ################################################################
9884 05:53:30.136994
9885 05:53:30.408324 01480000 ################################################################
9886 05:53:30.408497
9887 05:53:30.670844 01500000 ################################################################
9888 05:53:30.671030
9889 05:53:30.936722 01580000 ################################################################
9890 05:53:30.936886
9891 05:53:31.198915 01600000 ################################################################
9892 05:53:31.199087
9893 05:53:31.453210 01680000 ################################################################
9894 05:53:31.453366
9895 05:53:31.708470 01700000 ################################################################
9896 05:53:31.708647
9897 05:53:31.969876 01780000 ################################################################
9898 05:53:31.970034
9899 05:53:32.222267 01800000 ################################################################
9900 05:53:32.222411
9901 05:53:32.473408 01880000 ################################################################
9902 05:53:32.473571
9903 05:53:32.722826 01900000 ################################################################
9904 05:53:32.722989
9905 05:53:32.975051 01980000 ################################################################
9906 05:53:32.975216
9907 05:53:33.225130 01a00000 ################################################################
9908 05:53:33.225272
9909 05:53:33.480458 01a80000 ################################################################
9910 05:53:33.480622
9911 05:53:33.735526 01b00000 ################################################################
9912 05:53:33.735656
9913 05:53:33.990725 01b80000 ################################################################
9914 05:53:33.990891
9915 05:53:34.243540 01c00000 ################################################################
9916 05:53:34.243693
9917 05:53:34.506172 01c80000 ################################################################
9918 05:53:34.506307
9919 05:53:34.778205 01d00000 ################################################################
9920 05:53:34.778340
9921 05:53:35.040434 01d80000 ################################################################
9922 05:53:35.040608
9923 05:53:35.296361 01e00000 ################################################################
9924 05:53:35.296492
9925 05:53:35.553316 01e80000 ################################################################
9926 05:53:35.553448
9927 05:53:35.761319 01f00000 #################################################### done.
9928 05:53:35.761458
9929 05:53:35.764596 The bootfile was 32924810 bytes long.
9930 05:53:35.764680
9931 05:53:35.767978 Sending tftp read request... done.
9932 05:53:35.768060
9933 05:53:35.771023 Waiting for the transfer...
9934 05:53:35.771105
9935 05:53:35.771170 00000000 # done.
9936 05:53:35.771233
9937 05:53:35.780953 Command line loaded dynamically from TFTP file: 12379427/tftp-deploy-3jn6beu8/kernel/cmdline
9938 05:53:35.781040
9939 05:53:35.794128 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
9940 05:53:35.794248
9941 05:53:35.794344 Loading FIT.
9942 05:53:35.794433
9943 05:53:35.797417 Image ramdisk-1 has 21393668 bytes.
9944 05:53:35.797503
9945 05:53:35.800979 Image fdt-1 has 47278 bytes.
9946 05:53:35.801059
9947 05:53:35.804318 Image kernel-1 has 11481830 bytes.
9948 05:53:35.804426
9949 05:53:35.810627 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9950 05:53:35.810709
9951 05:53:35.830686 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9952 05:53:35.830777
9953 05:53:35.833572 Choosing best match conf-1 for compat google,spherion-rev3.
9954 05:53:35.839065
9955 05:53:35.843756 Connected to device vid:did:rid of 1ae0:0028:00
9956 05:53:35.850382
9957 05:53:35.853580 tpm_get_response: command 0x17b, return code 0x0
9958 05:53:35.853661
9959 05:53:35.857377 ec_init: CrosEC protocol v3 supported (256, 248)
9960 05:53:35.860971
9961 05:53:35.864759 tpm_cleanup: add release locality here.
9962 05:53:35.864841
9963 05:53:35.864931 Shutting down all USB controllers.
9964 05:53:35.867737
9965 05:53:35.867872 Removing current net device
9966 05:53:35.867951
9967 05:53:35.874229 Exiting depthcharge with code 4 at timestamp: 49379635
9968 05:53:35.874327
9969 05:53:35.877591 LZMA decompressing kernel-1 to 0x821a6718
9970 05:53:35.877693
9971 05:53:35.880884 LZMA decompressing kernel-1 to 0x40000000
9972 05:53:37.317105
9973 05:53:37.317273 jumping to kernel
9974 05:53:37.317749 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
9975 05:53:37.317849 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
9976 05:53:37.317927 Setting prompt string to ['Linux version [0-9]']
9977 05:53:37.317995 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9978 05:53:37.318063 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
9979 05:53:37.367391
9980 05:53:37.370839 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
9981 05:53:37.374399 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
9982 05:53:37.374492 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
9983 05:53:37.374564 Setting prompt string to []
9984 05:53:37.374642 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
9985 05:53:37.374717 Using line separator: #'\n'#
9986 05:53:37.374776 No login prompt set.
9987 05:53:37.374837 Parsing kernel messages
9988 05:53:37.374892 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
9989 05:53:37.374991 [login-action] Waiting for messages, (timeout 00:04:04)
9990 05:53:37.393501 [ 0.000000] Linux version 6.1.67-cip12 (KernelCI@build-j59664-arm64-gcc-10-defconfig-arm64-chromebook-fgc24) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023
9991 05:53:37.397202 [ 0.000000] random: crng init done
9992 05:53:37.403349 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
9993 05:53:37.406884 [ 0.000000] efi: UEFI not found.
9994 05:53:37.413128 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
9995 05:53:37.423303 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
9996 05:53:37.430099 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
9997 05:53:37.440118 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
9998 05:53:37.446512 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
9999 05:53:37.452888 [ 0.000000] printk: bootconsole [mtk8250] enabled
10000 05:53:37.459670 [ 0.000000] NUMA: No NUMA configuration found
10001 05:53:37.466162 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10002 05:53:37.472616 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d3a00-0x13f7d5fff]
10003 05:53:37.472728 [ 0.000000] Zone ranges:
10004 05:53:37.479188 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10005 05:53:37.482475 [ 0.000000] DMA32 empty
10006 05:53:37.489017 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10007 05:53:37.492274 [ 0.000000] Movable zone start for each node
10008 05:53:37.495599 [ 0.000000] Early memory node ranges
10009 05:53:37.502168 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10010 05:53:37.508568 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10011 05:53:37.515347 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10012 05:53:37.521844 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10013 05:53:37.528354 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10014 05:53:37.534910 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10015 05:53:37.565928 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10016 05:53:37.572151 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10017 05:53:37.578979 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10018 05:53:37.582296 [ 0.000000] psci: probing for conduit method from DT.
10019 05:53:37.588828 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10020 05:53:37.592065 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10021 05:53:37.598513 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10022 05:53:37.602129 [ 0.000000] psci: SMC Calling Convention v1.2
10023 05:53:37.608568 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10024 05:53:37.611798 [ 0.000000] Detected VIPT I-cache on CPU0
10025 05:53:37.618254 [ 0.000000] CPU features: detected: GIC system register CPU interface
10026 05:53:37.624977 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10027 05:53:37.631666 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10028 05:53:37.638418 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10029 05:53:37.648239 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10030 05:53:37.654613 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10031 05:53:37.657942 [ 0.000000] alternatives: applying boot alternatives
10032 05:53:37.664416 [ 0.000000] Fallback order for Node 0: 0
10033 05:53:37.671108 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10034 05:53:37.674417 [ 0.000000] Policy zone: Normal
10035 05:53:37.687266 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10036 05:53:37.697294 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10037 05:53:37.708688 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10038 05:53:37.718227 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10039 05:53:37.724931 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10040 05:53:37.727944 <6>[ 0.000000] software IO TLB: area num 8.
10041 05:53:37.784028 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10042 05:53:37.863987 <6>[ 0.000000] Memory: 3833416K/4191232K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 325048K reserved, 32768K cma-reserved)
10043 05:53:37.871146 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10044 05:53:37.877496 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10045 05:53:37.880346 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10046 05:53:37.886871 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10047 05:53:37.893678 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10048 05:53:37.896792 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10049 05:53:37.906960 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10050 05:53:37.913558 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10051 05:53:37.920367 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10052 05:53:37.926833 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10053 05:53:37.929805 <6>[ 0.000000] GICv3: 608 SPIs implemented
10054 05:53:37.933263 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10055 05:53:37.939819 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10056 05:53:37.943059 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10057 05:53:37.949940 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10058 05:53:37.962906 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10059 05:53:37.976074 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10060 05:53:37.982862 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10061 05:53:37.990573 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10062 05:53:38.004061 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10063 05:53:38.010487 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10064 05:53:38.017003 <6>[ 0.009178] Console: colour dummy device 80x25
10065 05:53:38.026930 <6>[ 0.013933] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10066 05:53:38.033456 <6>[ 0.024439] pid_max: default: 32768 minimum: 301
10067 05:53:38.036722 <6>[ 0.029309] LSM: Security Framework initializing
10068 05:53:38.043440 <6>[ 0.034220] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10069 05:53:38.053663 <6>[ 0.041827] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10070 05:53:38.060014 <6>[ 0.051057] cblist_init_generic: Setting adjustable number of callback queues.
10071 05:53:38.066545 <6>[ 0.058545] cblist_init_generic: Setting shift to 3 and lim to 1.
10072 05:53:38.076630 <6>[ 0.064883] cblist_init_generic: Setting adjustable number of callback queues.
10073 05:53:38.083116 <6>[ 0.072309] cblist_init_generic: Setting shift to 3 and lim to 1.
10074 05:53:38.086653 <6>[ 0.078710] rcu: Hierarchical SRCU implementation.
10075 05:53:38.093037 <6>[ 0.083756] rcu: Max phase no-delay instances is 1000.
10076 05:53:38.099423 <6>[ 0.090807] EFI services will not be available.
10077 05:53:38.102733 <6>[ 0.095761] smp: Bringing up secondary CPUs ...
10078 05:53:38.110904 <6>[ 0.100803] Detected VIPT I-cache on CPU1
10079 05:53:38.117782 <6>[ 0.100872] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10080 05:53:38.124368 <6>[ 0.100900] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10081 05:53:38.127175 <6>[ 0.101226] Detected VIPT I-cache on CPU2
10082 05:53:38.137362 <6>[ 0.101273] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10083 05:53:38.144065 <6>[ 0.101289] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10084 05:53:38.147170 <6>[ 0.101542] Detected VIPT I-cache on CPU3
10085 05:53:38.153650 <6>[ 0.101588] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10086 05:53:38.160440 <6>[ 0.101603] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10087 05:53:38.167095 <6>[ 0.101903] CPU features: detected: Spectre-v4
10088 05:53:38.170691 <6>[ 0.101910] CPU features: detected: Spectre-BHB
10089 05:53:38.173910 <6>[ 0.101916] Detected PIPT I-cache on CPU4
10090 05:53:38.179967 <6>[ 0.101971] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10091 05:53:38.189811 <6>[ 0.101988] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10092 05:53:38.193293 <6>[ 0.102276] Detected PIPT I-cache on CPU5
10093 05:53:38.199900 <6>[ 0.102339] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10094 05:53:38.206642 <6>[ 0.102356] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10095 05:53:38.209559 <6>[ 0.102633] Detected PIPT I-cache on CPU6
10096 05:53:38.219623 <6>[ 0.102695] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10097 05:53:38.226403 <6>[ 0.102711] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10098 05:53:38.229393 <6>[ 0.103008] Detected PIPT I-cache on CPU7
10099 05:53:38.235986 <6>[ 0.103074] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10100 05:53:38.242533 <6>[ 0.103090] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10101 05:53:38.246488 <6>[ 0.103137] smp: Brought up 1 node, 8 CPUs
10102 05:53:38.252744 <6>[ 0.244532] SMP: Total of 8 processors activated.
10103 05:53:38.259509 <6>[ 0.249483] CPU features: detected: 32-bit EL0 Support
10104 05:53:38.265842 <6>[ 0.254880] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10105 05:53:38.272612 <6>[ 0.263681] CPU features: detected: Common not Private translations
10106 05:53:38.279046 <6>[ 0.270157] CPU features: detected: CRC32 instructions
10107 05:53:38.285687 <6>[ 0.275541] CPU features: detected: RCpc load-acquire (LDAPR)
10108 05:53:38.288848 <6>[ 0.281539] CPU features: detected: LSE atomic instructions
10109 05:53:38.295394 <6>[ 0.287356] CPU features: detected: Privileged Access Never
10110 05:53:38.302507 <6>[ 0.293136] CPU features: detected: RAS Extension Support
10111 05:53:38.308833 <6>[ 0.298745] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10112 05:53:38.312202 <6>[ 0.305964] CPU: All CPU(s) started at EL2
10113 05:53:38.318774 <6>[ 0.310281] alternatives: applying system-wide alternatives
10114 05:53:38.328177 <6>[ 0.320227] devtmpfs: initialized
10115 05:53:38.343256 <6>[ 0.328425] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10116 05:53:38.349776 <6>[ 0.338383] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10117 05:53:38.356374 <6>[ 0.346616] pinctrl core: initialized pinctrl subsystem
10118 05:53:38.359320 <6>[ 0.353290] DMI not present or invalid.
10119 05:53:38.366113 <6>[ 0.357692] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10120 05:53:38.375925 <6>[ 0.364532] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10121 05:53:38.382638 <6>[ 0.371977] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10122 05:53:38.392298 <6>[ 0.380062] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10123 05:53:38.395882 <6>[ 0.388221] audit: initializing netlink subsys (disabled)
10124 05:53:38.405557 <5>[ 0.393914] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10125 05:53:38.411892 <6>[ 0.394619] thermal_sys: Registered thermal governor 'step_wise'
10126 05:53:38.418707 <6>[ 0.401881] thermal_sys: Registered thermal governor 'power_allocator'
10127 05:53:38.421823 <6>[ 0.408136] cpuidle: using governor menu
10128 05:53:38.428629 <6>[ 0.419089] NET: Registered PF_QIPCRTR protocol family
10129 05:53:38.435239 <6>[ 0.424589] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10130 05:53:38.441547 <6>[ 0.431693] ASID allocator initialised with 32768 entries
10131 05:53:38.444741 <6>[ 0.438244] Serial: AMBA PL011 UART driver
10132 05:53:38.454734 <4>[ 0.447034] Trying to register duplicate clock ID: 134
10133 05:53:38.509561 <6>[ 0.504888] KASLR enabled
10134 05:53:38.523704 <6>[ 0.512596] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10135 05:53:38.530514 <6>[ 0.519612] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10136 05:53:38.536703 <6>[ 0.526105] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10137 05:53:38.543404 <6>[ 0.533111] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10138 05:53:38.550281 <6>[ 0.539600] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10139 05:53:38.556575 <6>[ 0.546607] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10140 05:53:38.563282 <6>[ 0.553094] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10141 05:53:38.569773 <6>[ 0.560096] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10142 05:53:38.572824 <6>[ 0.567595] ACPI: Interpreter disabled.
10143 05:53:38.582098 <6>[ 0.574000] iommu: Default domain type: Translated
10144 05:53:38.588146 <6>[ 0.579114] iommu: DMA domain TLB invalidation policy: strict mode
10145 05:53:38.591613 <5>[ 0.585773] SCSI subsystem initialized
10146 05:53:38.598495 <6>[ 0.589933] usbcore: registered new interface driver usbfs
10147 05:53:38.605100 <6>[ 0.595664] usbcore: registered new interface driver hub
10148 05:53:38.608270 <6>[ 0.601216] usbcore: registered new device driver usb
10149 05:53:38.615452 <6>[ 0.607315] pps_core: LinuxPPS API ver. 1 registered
10150 05:53:38.624834 <6>[ 0.612509] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10151 05:53:38.628196 <6>[ 0.621851] PTP clock support registered
10152 05:53:38.631613 <6>[ 0.626093] EDAC MC: Ver: 3.0.0
10153 05:53:38.638889 <6>[ 0.631241] FPGA manager framework
10154 05:53:38.645416 <6>[ 0.634918] Advanced Linux Sound Architecture Driver Initialized.
10155 05:53:38.648984 <6>[ 0.641689] vgaarb: loaded
10156 05:53:38.655380 <6>[ 0.644827] clocksource: Switched to clocksource arch_sys_counter
10157 05:53:38.658935 <5>[ 0.651265] VFS: Disk quotas dquot_6.6.0
10158 05:53:38.665545 <6>[ 0.655448] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10159 05:53:38.668507 <6>[ 0.662633] pnp: PnP ACPI: disabled
10160 05:53:38.677113 <6>[ 0.669315] NET: Registered PF_INET protocol family
10161 05:53:38.683520 <6>[ 0.674689] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10162 05:53:38.695912 <6>[ 0.684692] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10163 05:53:38.705913 <6>[ 0.693484] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10164 05:53:38.712403 <6>[ 0.701452] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10165 05:53:38.719054 <6>[ 0.709855] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10166 05:53:38.729535 <6>[ 0.718508] TCP: Hash tables configured (established 32768 bind 32768)
10167 05:53:38.736566 <6>[ 0.725361] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10168 05:53:38.742751 <6>[ 0.732376] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10169 05:53:38.749393 <6>[ 0.739900] NET: Registered PF_UNIX/PF_LOCAL protocol family
10170 05:53:38.755976 <6>[ 0.746020] RPC: Registered named UNIX socket transport module.
10171 05:53:38.759256 <6>[ 0.752174] RPC: Registered udp transport module.
10172 05:53:38.765702 <6>[ 0.757105] RPC: Registered tcp transport module.
10173 05:53:38.772683 <6>[ 0.762037] RPC: Registered tcp NFSv4.1 backchannel transport module.
10174 05:53:38.776143 <6>[ 0.768699] PCI: CLS 0 bytes, default 64
10175 05:53:38.779202 <6>[ 0.773095] Unpacking initramfs...
10176 05:53:38.788985 <6>[ 0.776801] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10177 05:53:38.795661 <6>[ 0.785445] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10178 05:53:38.802424 <6>[ 0.794286] kvm [1]: IPA Size Limit: 40 bits
10179 05:53:38.805560 <6>[ 0.798818] kvm [1]: GICv3: no GICV resource entry
10180 05:53:38.811862 <6>[ 0.803840] kvm [1]: disabling GICv2 emulation
10181 05:53:38.818815 <6>[ 0.808525] kvm [1]: GIC system register CPU interface enabled
10182 05:53:38.821685 <6>[ 0.814696] kvm [1]: vgic interrupt IRQ18
10183 05:53:38.828257 <6>[ 0.819054] kvm [1]: VHE mode initialized successfully
10184 05:53:38.831726 <5>[ 0.825545] Initialise system trusted keyrings
10185 05:53:38.838498 <6>[ 0.830364] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10186 05:53:38.848219 <6>[ 0.840317] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10187 05:53:38.854788 <5>[ 0.846736] NFS: Registering the id_resolver key type
10188 05:53:38.858296 <5>[ 0.852042] Key type id_resolver registered
10189 05:53:38.864779 <5>[ 0.856459] Key type id_legacy registered
10190 05:53:38.871226 <6>[ 0.860741] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10191 05:53:38.878062 <6>[ 0.867662] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10192 05:53:38.884439 <6>[ 0.875386] 9p: Installing v9fs 9p2000 file system support
10193 05:53:38.921351 <5>[ 0.913498] Key type asymmetric registered
10194 05:53:38.924721 <5>[ 0.917836] Asymmetric key parser 'x509' registered
10195 05:53:38.934982 <6>[ 0.922980] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10196 05:53:38.937430 <6>[ 0.930594] io scheduler mq-deadline registered
10197 05:53:38.940999 <6>[ 0.935355] io scheduler kyber registered
10198 05:53:38.960094 <6>[ 0.952556] EINJ: ACPI disabled.
10199 05:53:38.992370 <4>[ 0.977770] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10200 05:53:39.002288 <4>[ 0.988406] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10201 05:53:39.017228 <6>[ 1.009455] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10202 05:53:39.025320 <6>[ 1.017547] printk: console [ttyS0] disabled
10203 05:53:39.053614 <6>[ 1.042217] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10204 05:53:39.059642 <6>[ 1.051692] printk: console [ttyS0] enabled
10205 05:53:39.063522 <6>[ 1.051692] printk: console [ttyS0] enabled
10206 05:53:39.070032 <6>[ 1.060588] printk: bootconsole [mtk8250] disabled
10207 05:53:39.073184 <6>[ 1.060588] printk: bootconsole [mtk8250] disabled
10208 05:53:39.079650 <6>[ 1.071875] SuperH (H)SCI(F) driver initialized
10209 05:53:39.083050 <6>[ 1.077157] msm_serial: driver initialized
10210 05:53:39.097626 <6>[ 1.086174] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10211 05:53:39.107116 <6>[ 1.094722] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10212 05:53:39.113732 <6>[ 1.103265] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10213 05:53:39.123735 <6>[ 1.111895] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10214 05:53:39.133714 <6>[ 1.120607] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10215 05:53:39.140297 <6>[ 1.129327] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10216 05:53:39.150192 <6>[ 1.137868] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10217 05:53:39.156733 <6>[ 1.146671] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10218 05:53:39.167168 <6>[ 1.155214] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10219 05:53:39.178483 <6>[ 1.170807] loop: module loaded
10220 05:53:39.185303 <6>[ 1.176778] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10221 05:53:39.208015 <4>[ 1.200214] mtk-pmic-keys: Failed to locate of_node [id: -1]
10222 05:53:39.214786 <6>[ 1.207147] megasas: 07.719.03.00-rc1
10223 05:53:39.224770 <6>[ 1.216807] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10224 05:53:39.231963 <6>[ 1.224221] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10225 05:53:39.248527 <6>[ 1.240738] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10226 05:53:39.304277 <6>[ 1.290011] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10227 05:53:39.682091 <6>[ 1.674477] Freeing initrd memory: 20888K
10228 05:53:39.698046 <6>[ 1.690237] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10229 05:53:39.709073 <6>[ 1.701349] tun: Universal TUN/TAP device driver, 1.6
10230 05:53:39.712157 <6>[ 1.707417] thunder_xcv, ver 1.0
10231 05:53:39.715618 <6>[ 1.710922] thunder_bgx, ver 1.0
10232 05:53:39.718709 <6>[ 1.714415] nicpf, ver 1.0
10233 05:53:39.729299 <6>[ 1.718447] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10234 05:53:39.732654 <6>[ 1.725923] hns3: Copyright (c) 2017 Huawei Corporation.
10235 05:53:39.739626 <6>[ 1.731511] hclge is initializing
10236 05:53:39.742464 <6>[ 1.735091] e1000: Intel(R) PRO/1000 Network Driver
10237 05:53:39.749221 <6>[ 1.740221] e1000: Copyright (c) 1999-2006 Intel Corporation.
10238 05:53:39.752507 <6>[ 1.746234] e1000e: Intel(R) PRO/1000 Network Driver
10239 05:53:39.759263 <6>[ 1.751449] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10240 05:53:39.765937 <6>[ 1.757637] igb: Intel(R) Gigabit Ethernet Network Driver
10241 05:53:39.772388 <6>[ 1.763287] igb: Copyright (c) 2007-2014 Intel Corporation.
10242 05:53:39.778932 <6>[ 1.769123] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10243 05:53:39.785822 <6>[ 1.775642] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10244 05:53:39.789281 <6>[ 1.782105] sky2: driver version 1.30
10245 05:53:39.795732 <6>[ 1.787100] VFIO - User Level meta-driver version: 0.3
10246 05:53:39.803201 <6>[ 1.795327] usbcore: registered new interface driver usb-storage
10247 05:53:39.809595 <6>[ 1.801770] usbcore: registered new device driver onboard-usb-hub
10248 05:53:39.818573 <6>[ 1.810935] mt6397-rtc mt6359-rtc: registered as rtc0
10249 05:53:39.828537 <6>[ 1.816396] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-25T05:53:39 UTC (1703483619)
10250 05:53:39.831922 <6>[ 1.825964] i2c_dev: i2c /dev entries driver
10251 05:53:39.848399 <6>[ 1.837693] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10252 05:53:39.868685 <6>[ 1.860660] cpu cpu0: EM: created perf domain
10253 05:53:39.871474 <6>[ 1.865469] cpu cpu4: EM: created perf domain
10254 05:53:39.878760 <6>[ 1.871016] sdhci: Secure Digital Host Controller Interface driver
10255 05:53:39.885200 <6>[ 1.877448] sdhci: Copyright(c) Pierre Ossman
10256 05:53:39.891820 <6>[ 1.882347] Synopsys Designware Multimedia Card Interface Driver
10257 05:53:39.898523 <6>[ 1.888964] sdhci-pltfm: SDHCI platform and OF driver helper
10258 05:53:39.901717 <6>[ 1.889061] mmc0: CQHCI version 5.10
10259 05:53:39.908619 <6>[ 1.899004] ledtrig-cpu: registered to indicate activity on CPUs
10260 05:53:39.915280 <6>[ 1.906001] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10261 05:53:39.921904 <6>[ 1.913027] usbcore: registered new interface driver usbhid
10262 05:53:39.925317 <6>[ 1.918847] usbhid: USB HID core driver
10263 05:53:39.931840 <6>[ 1.923046] spi_master spi0: will run message pump with realtime priority
10264 05:53:39.971959 <6>[ 1.957829] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10265 05:53:39.990939 <6>[ 1.973535] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10266 05:53:39.995079 <6>[ 1.987153] mmc0: Command Queue Engine enabled
10267 05:53:40.001473 <6>[ 1.991938] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10268 05:53:40.008057 <6>[ 1.998864] cros-ec-spi spi0.0: Chrome EC device registered
10269 05:53:40.011690 <6>[ 1.999203] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10270 05:53:40.025524 <6>[ 2.017564] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10271 05:53:40.035208 <6>[ 2.022048] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10272 05:53:40.041799 <6>[ 2.024548] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10273 05:53:40.045117 <6>[ 2.033664] NET: Registered PF_PACKET protocol family
10274 05:53:40.051853 <6>[ 2.038662] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10275 05:53:40.054901 <6>[ 2.043386] 9pnet: Installing 9P2000 support
10276 05:53:40.061676 <6>[ 2.049188] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10277 05:53:40.068098 <5>[ 2.053070] Key type dns_resolver registered
10278 05:53:40.071556 <6>[ 2.064507] registered taskstats version 1
10279 05:53:40.078330 <5>[ 2.068884] Loading compiled-in X.509 certificates
10280 05:53:40.104402 <4>[ 2.089966] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10281 05:53:40.115045 <4>[ 2.100672] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10282 05:53:40.121045 <3>[ 2.111206] debugfs: File 'uA_load' in directory '/' already present!
10283 05:53:40.127911 <3>[ 2.117908] debugfs: File 'min_uV' in directory '/' already present!
10284 05:53:40.134449 <3>[ 2.124575] debugfs: File 'max_uV' in directory '/' already present!
10285 05:53:40.140929 <3>[ 2.131187] debugfs: File 'constraint_flags' in directory '/' already present!
10286 05:53:40.151925 <3>[ 2.140610] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10287 05:53:40.159664 <6>[ 2.152170] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10288 05:53:40.167400 <6>[ 2.159112] xhci-mtk 11200000.usb: xHCI Host Controller
10289 05:53:40.173776 <6>[ 2.164620] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10290 05:53:40.183923 <6>[ 2.172460] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10291 05:53:40.190041 <6>[ 2.181875] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10292 05:53:40.196731 <6>[ 2.187938] xhci-mtk 11200000.usb: xHCI Host Controller
10293 05:53:40.203670 <6>[ 2.193413] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10294 05:53:40.210264 <6>[ 2.201057] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10295 05:53:40.216916 <6>[ 2.208701] hub 1-0:1.0: USB hub found
10296 05:53:40.220259 <6>[ 2.212708] hub 1-0:1.0: 1 port detected
10297 05:53:40.226946 <6>[ 2.216969] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10298 05:53:40.233450 <6>[ 2.225494] hub 2-0:1.0: USB hub found
10299 05:53:40.236825 <6>[ 2.229496] hub 2-0:1.0: 1 port detected
10300 05:53:40.244205 <6>[ 2.236755] mtk-msdc 11f70000.mmc: Got CD GPIO
10301 05:53:40.254429 <6>[ 2.243551] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10302 05:53:40.261049 <6>[ 2.251573] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10303 05:53:40.271148 <4>[ 2.259592] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10304 05:53:40.280942 <6>[ 2.269126] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10305 05:53:40.287632 <6>[ 2.277219] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10306 05:53:40.297740 <6>[ 2.285331] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10307 05:53:40.304445 <6>[ 2.293290] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10308 05:53:40.311164 <6>[ 2.301108] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10309 05:53:40.320593 <6>[ 2.308924] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10310 05:53:40.330594 <6>[ 2.319337] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10311 05:53:40.337550 <6>[ 2.327717] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10312 05:53:40.347265 <6>[ 2.336054] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10313 05:53:40.356860 <6>[ 2.344391] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10314 05:53:40.363642 <6>[ 2.352730] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10315 05:53:40.373318 <6>[ 2.361069] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10316 05:53:40.380040 <6>[ 2.369406] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10317 05:53:40.389864 <6>[ 2.377745] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10318 05:53:40.396675 <6>[ 2.386097] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10319 05:53:40.406685 <6>[ 2.394437] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10320 05:53:40.413142 <6>[ 2.402778] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10321 05:53:40.423211 <6>[ 2.411117] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10322 05:53:40.429651 <6>[ 2.419455] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10323 05:53:40.439493 <6>[ 2.427795] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10324 05:53:40.446815 <6>[ 2.436134] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10325 05:53:40.452821 <6>[ 2.444863] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10326 05:53:40.459581 <6>[ 2.451846] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10327 05:53:40.466359 <6>[ 2.458585] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10328 05:53:40.476438 <6>[ 2.465319] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10329 05:53:40.482818 <6>[ 2.472224] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10330 05:53:40.489596 <6>[ 2.479076] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10331 05:53:40.499293 <6>[ 2.488202] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10332 05:53:40.509287 <6>[ 2.497323] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10333 05:53:40.519284 <6>[ 2.506619] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10334 05:53:40.529000 <6>[ 2.516090] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10335 05:53:40.538684 <6>[ 2.525557] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10336 05:53:40.545533 <6>[ 2.534682] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10337 05:53:40.555555 <6>[ 2.544149] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10338 05:53:40.565437 <6>[ 2.553266] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10339 05:53:40.575210 <6>[ 2.562560] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10340 05:53:40.585191 <6>[ 2.572719] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10341 05:53:40.594943 <6>[ 2.584242] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10342 05:53:40.652363 <6>[ 2.641088] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10343 05:53:40.807119 <6>[ 2.799213] hub 1-1:1.0: USB hub found
10344 05:53:40.810045 <6>[ 2.803697] hub 1-1:1.0: 4 ports detected
10345 05:53:40.819580 <6>[ 2.812020] hub 1-1:1.0: USB hub found
10346 05:53:40.822930 <6>[ 2.816395] hub 1-1:1.0: 4 ports detected
10347 05:53:40.932454 <6>[ 2.921328] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10348 05:53:40.957581 <6>[ 2.949927] hub 2-1:1.0: USB hub found
10349 05:53:40.960696 <6>[ 2.954355] hub 2-1:1.0: 3 ports detected
10350 05:53:40.969038 <6>[ 2.961445] hub 2-1:1.0: USB hub found
10351 05:53:40.972403 <6>[ 2.965886] hub 2-1:1.0: 3 ports detected
10352 05:53:41.147709 <6>[ 3.137112] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10353 05:53:41.280009 <6>[ 3.272246] hub 1-1.4:1.0: USB hub found
10354 05:53:41.283270 <6>[ 3.276770] hub 1-1.4:1.0: 2 ports detected
10355 05:53:41.291035 <6>[ 3.283398] hub 1-1.4:1.0: USB hub found
10356 05:53:41.293910 <6>[ 3.287944] hub 1-1.4:1.0: 2 ports detected
10357 05:53:41.360218 <6>[ 3.349146] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10358 05:53:41.591857 <6>[ 3.581129] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10359 05:53:41.783868 <6>[ 3.773097] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10360 05:53:52.897037 <6>[ 14.894097] ALSA device list:
10361 05:53:52.903653 <6>[ 14.897390] No soundcards found.
10362 05:53:52.911370 <6>[ 14.905188] Freeing unused kernel memory: 8448K
10363 05:53:52.914627 <6>[ 14.910280] Run /init as init process
10364 05:53:52.952818 Starting syslogd: OK
10365 05:53:52.956620 Starting klogd: OK
10366 05:53:52.962607 Running sysctl: OK
10367 05:53:52.972433 Populating /dev using udev: <30>[ 14.965872] udevd[193]: starting version 3.2.9
10368 05:53:52.980919 <27>[ 14.974815] udevd[193]: specified user 'tss' unknown
10369 05:53:52.987446 <27>[ 14.980315] udevd[193]: specified group 'tss' unknown
10370 05:53:52.994056 <30>[ 14.986981] udevd[194]: starting eudev-3.2.9
10371 05:53:53.009894 <27>[ 15.003769] udevd[194]: specified user 'tss' unknown
10372 05:53:53.016740 <27>[ 15.009123] udevd[194]: specified group 'tss' unknown
10373 05:53:53.109903 <6>[ 15.100609] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10374 05:53:53.132507 <6>[ 15.123296] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10375 05:53:53.135885 <6>[ 15.123343] remoteproc remoteproc0: scp is available
10376 05:53:53.142769 <6>[ 15.123460] remoteproc remoteproc0: powering up scp
10377 05:53:53.152573 <6>[ 15.130959] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10378 05:53:53.159277 <6>[ 15.130967] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10379 05:53:53.168962 <6>[ 15.159295] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10380 05:53:53.175761 <6>[ 15.167879] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10381 05:53:53.179189 <6>[ 15.168330] mc: Linux media interface: v0.10
10382 05:53:53.185781 <4>[ 15.168883] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10383 05:53:53.192199 <4>[ 15.169508] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10384 05:53:53.198768 <6>[ 15.170446] usbcore: registered new interface driver r8152
10385 05:53:53.208665 <3>[ 15.171287] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10386 05:53:53.215825 <3>[ 15.171298] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10387 05:53:53.225419 <3>[ 15.171301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10388 05:53:53.231912 <3>[ 15.171359] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10389 05:53:53.238911 <3>[ 15.171363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10390 05:53:53.248404 <3>[ 15.171365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10391 05:53:53.255105 <3>[ 15.171370] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10392 05:53:53.264831 <3>[ 15.171373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10393 05:53:53.271416 <3>[ 15.171392] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10394 05:53:53.281290 <3>[ 15.171417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10395 05:53:53.288764 <3>[ 15.171420] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10396 05:53:53.295884 <3>[ 15.171423] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10397 05:53:53.305691 <3>[ 15.171441] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10398 05:53:53.311855 <3>[ 15.171444] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10399 05:53:53.322081 <3>[ 15.171447] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10400 05:53:53.328815 <3>[ 15.171571] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10401 05:53:53.338571 <3>[ 15.171575] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10402 05:53:53.345330 <3>[ 15.171596] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10403 05:53:53.355404 <6>[ 15.208199] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10404 05:53:53.361888 <6>[ 15.261764] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10405 05:53:53.372336 <6>[ 15.263590] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10406 05:53:53.379081 <6>[ 15.266346] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10407 05:53:53.382372 <6>[ 15.266353] pci_bus 0000:00: root bus resource [bus 00-ff]
10408 05:53:53.392035 <6>[ 15.266358] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10409 05:53:53.402041 <6>[ 15.266363] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10410 05:53:53.405548 <6>[ 15.266399] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10411 05:53:53.415008 <6>[ 15.266416] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10412 05:53:53.418703 <6>[ 15.266485] pci 0000:00:00.0: supports D1 D2
10413 05:53:53.425442 <6>[ 15.266487] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10414 05:53:53.435427 <6>[ 15.267434] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10415 05:53:53.441911 <6>[ 15.267525] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10416 05:53:53.448512 <6>[ 15.267549] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10417 05:53:53.454731 <6>[ 15.267565] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10418 05:53:53.461355 <6>[ 15.267580] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10419 05:53:53.467837 <6>[ 15.267687] pci 0000:01:00.0: supports D1 D2
10420 05:53:53.474556 <6>[ 15.267688] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10421 05:53:53.484498 <6>[ 15.271800] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10422 05:53:53.491005 <4>[ 15.273844] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10423 05:53:53.497390 <4>[ 15.273844] Fallback method does not support PEC.
10424 05:53:53.507515 <6>[ 15.275832] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10425 05:53:53.514027 <6>[ 15.277142] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10426 05:53:53.521172 <6>[ 15.277178] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10427 05:53:53.527541 <6>[ 15.277184] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10428 05:53:53.537420 <6>[ 15.277197] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10429 05:53:53.543748 <6>[ 15.277214] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10430 05:53:53.554000 <6>[ 15.277230] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10431 05:53:53.557376 <6>[ 15.277246] pci 0000:00:00.0: PCI bridge to [bus 01]
10432 05:53:53.567562 <6>[ 15.277254] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10433 05:53:53.573608 <6>[ 15.277408] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10434 05:53:53.576867 <6>[ 15.278352] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10435 05:53:53.583296 <6>[ 15.278576] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10436 05:53:53.593545 <3>[ 15.289387] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10437 05:53:53.600105 <6>[ 15.298819] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10438 05:53:53.609888 <6>[ 15.303828] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10439 05:53:53.616657 <6>[ 15.303847] remoteproc remoteproc0: remote processor scp is now up
10440 05:53:53.619793 <6>[ 15.312667] videodev: Linux video capture interface: v2.00
10441 05:53:53.626366 <6>[ 15.321564] usbcore: registered new interface driver cdc_ether
10442 05:53:53.636283 <5>[ 15.327638] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10443 05:53:53.643167 <4>[ 15.328298] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10444 05:53:53.652626 <4>[ 15.328320] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10445 05:53:53.655985 <6>[ 15.337297] Bluetooth: Core ver 2.22
10446 05:53:53.662986 <6>[ 15.338143] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10447 05:53:53.673004 <6>[ 15.340037] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10448 05:53:53.676515 <6>[ 15.345106] r8152 2-1.3:1.0 eth0: v1.12.13
10449 05:53:53.682872 <6>[ 15.352608] NET: Registered PF_BLUETOOTH protocol family
10450 05:53:53.689032 <6>[ 15.352859] usbcore: registered new interface driver r8153_ecm
10451 05:53:53.695883 <5>[ 15.354500] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10452 05:53:53.702300 <4>[ 15.354552] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10453 05:53:53.709159 <6>[ 15.354557] cfg80211: failed to load regulatory.db
10454 05:53:53.718755 <3>[ 15.376535] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10455 05:53:53.725509 <6>[ 15.382259] Bluetooth: HCI device and connection manager initialized
10456 05:53:53.732065 <6>[ 15.400587] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10457 05:53:53.735459 <6>[ 15.405551] Bluetooth: HCI socket layer initialized
10458 05:53:53.741840 <6>[ 15.405557] Bluetooth: L2CAP socket layer initialized
10459 05:53:53.755104 <6>[ 15.414969] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10460 05:53:53.758516 <6>[ 15.417551] Bluetooth: SCO socket layer initialized
10461 05:53:53.764935 <6>[ 15.424589] usbcore: registered new interface driver uvcvideo
10462 05:53:53.771973 <6>[ 15.433862] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10463 05:53:53.778375 <6>[ 15.462494] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10464 05:53:53.785136 <6>[ 15.482514] usbcore: registered new interface driver btusb
10465 05:53:53.795014 <4>[ 15.483228] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10466 05:53:53.801370 <3>[ 15.483239] Bluetooth: hci0: Failed to load firmware file (-2)
10467 05:53:53.808361 <3>[ 15.483243] Bluetooth: hci0: Failed to set up firmware (-2)
10468 05:53:53.818013 <4>[ 15.483247] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10469 05:53:53.824568 <6>[ 15.495615] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10470 05:53:53.847079 <6>[ 15.840959] mt7921e 0000:01:00.0: ASIC revision: 79610010
10471 05:53:53.949362 <6>[ 15.940080] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10472 05:53:53.953129 <6>[ 15.940080]
10473 05:53:53.961286 done
10474 05:53:53.973034 Saving random seed: OK
10475 05:53:53.990740 Starting network: OK
10476 05:53:54.021129 Starting dropbear sshd: <6>[ 16.015158] NET: Registered PF_INET6 protocol family
10477 05:53:54.028104 <6>[ 16.021486] Segment Routing with IPv6
10478 05:53:54.031223 <6>[ 16.025458] In-situ OAM (IOAM) with IPv6
10479 05:53:54.034186 OK
10480 05:53:54.043896 /bin/sh: can't access tty; job control turned off
10481 05:53:54.044230 Matched prompt #10: / #
10483 05:53:54.044432 Setting prompt string to ['/ #']
10484 05:53:54.044525 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10486 05:53:54.044750 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10487 05:53:54.044851 start: 2.2.6 expect-shell-connection (timeout 00:03:47) [common]
10488 05:53:54.044922 Setting prompt string to ['/ #']
10489 05:53:54.044983 Forcing a shell prompt, looking for ['/ #']
10491 05:53:54.095161 / #
10492 05:53:54.095255 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10493 05:53:54.095332 Waiting using forced prompt support (timeout 00:02:30)
10494 05:53:54.100347
10495 05:53:54.100616 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10496 05:53:54.100718 start: 2.2.7 export-device-env (timeout 00:03:47) [common]
10497 05:53:54.100854 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10498 05:53:54.100941 end: 2.2 depthcharge-retry (duration 00:01:13) [common]
10499 05:53:54.101029 end: 2 depthcharge-action (duration 00:01:13) [common]
10500 05:53:54.101115 start: 3 lava-test-retry (timeout 00:01:00) [common]
10501 05:53:54.101199 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10502 05:53:54.101273 Using namespace: common
10504 05:53:54.201533 / # #
10505 05:53:54.201646 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10506 05:53:54.207159 #
10507 05:53:54.207419 Using /lava-12379427
10509 05:53:54.307685 / # export SHELL=/bin/sh
10510 05:53:54.307837 <6>[ 16.210608] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10511 05:53:54.312663 export SHELL=/bin/sh
10513 05:53:54.413134 / # . /lava-12379427/environment
10514 05:53:54.418322 . /lava-12379427/environment
10516 05:53:54.518795 / # /lava-12379427/bin/lava-test-runner /lava-12379427/0
10517 05:53:54.518916 Test shell timeout: 10s (minimum of the action and connection timeout)
10518 05:53:54.523958 /lava-12379427/bin/lava-test-runner /lava-12379427/0
10519 05:53:54.543008 + export 'TESTRUN_ID=0_dmesg'
10520 05:53:54.549562 +<8>[ 16.542359] <LAVA_SIGNAL_STARTRUN 0_dmesg 12379427_1.5.2.3.1>
10521 05:53:54.549814 Received signal: <STARTRUN> 0_dmesg 12379427_1.5.2.3.1
10522 05:53:54.549888 Starting test lava.0_dmesg (12379427_1.5.2.3.1)
10523 05:53:54.549970 Skipping test definition patterns.
10524 05:53:54.553156 cd /lava-12379427/0/tests/0_dmesg
10525 05:53:54.553229 + cat uuid
10526 05:53:54.556690 + UUID=12379427_1.5.2.3.1
10527 05:53:54.556807 + set +x
10528 05:53:54.569463 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dme<8>[ 16.559791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10529 05:53:54.569541 sg.sh
10530 05:53:54.569771 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10532 05:53:54.587948 <8>[ 16.578752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10533 05:53:54.588195 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10535 05:53:54.605156 <8>[ 16.595833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10536 05:53:54.605403 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10538 05:53:54.608438 + set +x
10539 05:53:54.611645 <8>[ 16.605403] <LAVA_SIGNAL_ENDRUN 0_dmesg 12379427_1.5.2.3.1>
10540 05:53:54.611888 Received signal: <ENDRUN> 0_dmesg 12379427_1.5.2.3.1
10541 05:53:54.611966 Ending use of test pattern.
10542 05:53:54.612027 Ending test lava.0_dmesg (12379427_1.5.2.3.1), duration 0.06
10544 05:53:54.615340 <LAVA_TEST_RUNNER EXIT>
10545 05:53:54.615581 ok: lava_test_shell seems to have completed
10546 05:53:54.615677 alert: pass
crit: pass
emerg: pass
10547 05:53:54.615760 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10548 05:53:54.615842 end: 3 lava-test-retry (duration 00:00:01) [common]
10549 05:53:54.615922 start: 4 lava-test-retry (timeout 00:01:00) [common]
10550 05:53:54.616001 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10551 05:53:54.616063 Using namespace: common
10553 05:53:54.716326 / # #
10554 05:53:54.716441 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10555 05:53:54.716542 Using /lava-12379427
10557 05:53:54.816805 export SHELL=/bin/sh
10558 05:53:54.816951 #
10560 05:53:54.917395 / # export SHELL=/bin/sh. /lava-12379427/environment
10561 05:53:54.917548
10563 05:53:55.018009 / # . /lava-12379427/environment/lava-12379427/bin/lava-test-runner /lava-12379427/1
10564 05:53:55.018129 Test shell timeout: 10s (minimum of the action and connection timeout)
10565 05:53:55.018240
10566 05:53:55.022945 / # /lava-12379427/bin/lava-test-runner /lava-12379427/1
10567 05:53:55.040957 + export 'TESTRUN_ID=1_bootrr'
10568 05:53:55.047472 + <8>[ 17.040195] <LAVA_SIGNAL_STARTRUN 1_bootrr 12379427_1.5.2.3.5>
10569 05:53:55.047722 Received signal: <STARTRUN> 1_bootrr 12379427_1.5.2.3.5
10570 05:53:55.047793 Starting test lava.1_bootrr (12379427_1.5.2.3.5)
10571 05:53:55.047872 Skipping test definition patterns.
10572 05:53:55.051096 cd /lava-12379427/1/tests/1_bootrr
10573 05:53:55.051164 + cat uuid
10574 05:53:55.060853 + UUID=12379427_<6>[ 17.051888] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10575 05:53:55.060931 1.5.2.3.5
10576 05:53:55.060995 + set +x
10577 05:53:55.070894 + export 'PATH=/opt/bootrr/<8>[ 17.062375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10578 05:53:55.071140 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10580 05:53:55.077318 libexec/bootrr/helpers:/lava-12379427/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10581 05:53:55.080801 + cd /opt/bootrr/libexec/bootrr
10582 05:53:55.090856 + sh helpers/boo<8>[ 17.080795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10583 05:53:55.090929 trr-auto
10584 05:53:55.091159 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10586 05:53:55.093703 /lava-12379427/1/../bin/lava-test-case
10587 05:53:55.097067 /lava-12379427/1/../bin/lava-test-case
10588 05:53:55.100683 /usr/bin/tpm2_getcap
10589 05:53:55.130249 /lava-12379427/1/../bin/lava-test-case
10590 05:53:55.136702 <8>[ 17.127566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10591 05:53:55.136984 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10593 05:53:55.158065 /lava-12379427/1/../bin/lava-tes<8>[ 17.147598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10594 05:53:55.158145 t-case
10595 05:53:55.158376 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10597 05:53:55.174858 /lava-12379427/1/../bin/lava-tes<8>[ 17.164541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10598 05:53:55.174934 t-case
10599 05:53:55.175164 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10601 05:53:55.184653 /lava-12379427/1/../bin/lava-test-case
10602 05:53:55.190726 <8>[ 17.181700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10603 05:53:55.190968 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10605 05:53:55.202284 /lava-12379427/1/../bin/lava-test-case
10606 05:53:55.209139 <8>[ 17.199728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10607 05:53:55.209385 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10609 05:53:55.226612 /lava-12379427/1/../bin/lava-tes<8>[ 17.216566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10610 05:53:55.226691 t-case
10611 05:53:55.226924 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10613 05:53:55.236790 /lava-12379427/1/../bin/lava-test-case
10614 05:53:55.243000 <8>[ 17.234363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10615 05:53:55.243241 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10617 05:53:55.254512 /lava-12379427/1/../bin/lava-test-case
10618 05:53:55.264409 <8>[ 17.255267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10619 05:53:55.264672 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10621 05:53:55.272948 /lava-12379427/1/../bin/lava-test-case
10622 05:53:55.282470 <8>[ 17.271005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10623 05:53:55.282750 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10625 05:53:55.292594 /lava-12379427/1/../bin/lava-test-case
10626 05:53:55.298824 <8>[ 17.289974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10627 05:53:55.299074 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10629 05:53:55.310530 /lava-12379427/1/../bin/lava-test-case
10630 05:53:55.317293 <8>[ 17.308247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10631 05:53:55.317545 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10633 05:53:55.330103 /lava-12379427/1/../bin/lava-test-case
10634 05:53:55.340015 <8>[ 17.330028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10635 05:53:55.340299 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10637 05:53:55.351066 /lava-12379427/1/../bin/lava-test-case
10638 05:53:55.357445 <8>[ 17.348208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10639 05:53:55.357696 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10641 05:53:55.366558 /lava-12379427/1/../bin/lava-test-case
10642 05:53:55.377009 <8>[ 17.366989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10643 05:53:55.377282 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10645 05:53:55.386486 /lava-12379427/1/../bin/lava-test-case
10646 05:53:55.392763 <8>[ 17.384288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10647 05:53:55.393007 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10649 05:53:55.402672 /lava-12379427/1/../bin/lava-test-case
10650 05:53:55.409084 <8>[ 17.400701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10651 05:53:55.409331 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10653 05:53:55.421517 /lava-12379427/1/../bin/lava-test-case
10654 05:53:55.428216 <8>[ 17.419179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10655 05:53:55.428494 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10657 05:53:55.436852 /lava-12379427/1/../bin/lava-test-case
10658 05:53:55.443173 <8>[ 17.434985] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10659 05:53:55.443424 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10661 05:53:55.453369 /lava-12379427/1/../bin/lava-test-case
10662 05:53:55.460012 <8>[ 17.451987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10663 05:53:55.460258 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10665 05:53:55.468919 /lava-12379427/1/../bin/lava-test-case
10666 05:53:55.475626 <8>[ 17.466447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10667 05:53:55.475873 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10669 05:53:55.486597 /lava-12379427/1/../bin/lava-test-case
10670 05:53:55.493358 <8>[ 17.483802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10671 05:53:55.493603 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10673 05:53:55.501353 /lava-12379427/1/../bin/lava-test-case
10674 05:53:55.507751 <8>[ 17.498970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10675 05:53:55.508008 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10677 05:53:55.526045 /lava-12379427/1/../bin/lava-tes<8>[ 17.516340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10678 05:53:55.526129 t-case
10679 05:53:55.526364 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10681 05:53:55.536591 /lava-12379427/1/../bin/lava-test-case
10682 05:53:55.543181 <8>[ 17.533820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10683 05:53:55.543435 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10685 05:53:55.553105 /lava-12379427/1/../bin/lava-test-case
10686 05:53:55.560048 <8>[ 17.551756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10687 05:53:55.560329 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10689 05:53:55.572821 /lava-12379427/1/../bin/lava-test-case
10690 05:53:55.579002 <8>[ 17.569787] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10691 05:53:55.579278 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10693 05:53:55.587894 /lava-12379427/1/../bin/lava-test-case
10694 05:53:55.594804 <8>[ 17.585348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10695 05:53:55.595047 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10697 05:53:55.607611 /lava-12379427/1/../bin/lava-test-case
10698 05:53:55.614167 <8>[ 17.606028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10699 05:53:55.614410 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10701 05:53:55.626224 /lava-12379427/1/../bin/lava-test-case
10702 05:53:55.632428 <8>[ 17.622914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10703 05:53:55.632672 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10705 05:53:55.654391 /lava-12379427/1/../bin/lava-tes<8>[ 17.644239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10706 05:53:55.654475 t-case
10707 05:53:55.654725 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10709 05:53:55.663288 /lava-12379427/1/../bin/lava-test-case
10710 05:53:55.670015 <8>[ 17.661362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10711 05:53:55.670269 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10713 05:53:55.680445 /lava-12379427/1/../bin/lava-test-case
10714 05:53:55.687152 <8>[ 17.678387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10715 05:53:55.687411 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10717 05:53:55.698138 /lava-12379427/1/../bin/lava-test-case
10718 05:53:55.704695 <8>[ 17.695632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10719 05:53:55.704983 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10721 05:53:55.715852 /lava-12379427/1/../bin/lava-test-case
10722 05:53:55.722475 <8>[ 17.713100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10723 05:53:55.722728 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10725 05:53:55.732337 /lava-12379427/1/../bin/lava-test-case
10726 05:53:55.738726 <8>[ 17.729964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10727 05:53:55.738978 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10729 05:53:55.757843 /lava-12379427/1/../bin/lava-tes<8>[ 17.747930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10730 05:53:55.757922 t-case
10731 05:53:55.758164 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10733 05:53:55.772646 /lava-12379427/1/../bin/lava-tes<8>[ 17.762869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10734 05:53:55.772773 t-case
10735 05:53:55.773035 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10737 05:53:55.783613 /lava-12379427/1/../bin/lava-test-case
10738 05:53:55.790048 <8>[ 17.782455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10739 05:53:55.790299 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10741 05:53:55.807547 /lava-12379427/1/../bin/lava-tes<8>[ 17.797815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10742 05:53:55.807649 t-case
10743 05:53:55.807919 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10745 05:53:55.825263 /lava-12379427/1/../bin/lava-tes<8>[ 17.815229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
10746 05:53:55.825356 t-case
10747 05:53:55.825595 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
10749 05:53:55.833722 /lava-12379427/1/../bin/lava-test-case
10750 05:53:55.840379 <8>[ 17.831888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
10751 05:53:55.840626 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
10753 05:53:55.853428 /lava-12379427/1/../bin/lava-test-case
10754 05:53:55.859891 <8>[ 17.850935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
10755 05:53:55.860137 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
10757 05:53:55.869397 /lava-12379427/1/../bin/lava-test-case
10758 05:53:55.876251 <8>[ 17.867826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
10759 05:53:55.876495 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
10761 05:53:55.889444 /lava-12379427/1/../bin/lava-test-case
10762 05:53:55.895838 <8>[ 17.886724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
10763 05:53:55.896078 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
10765 05:53:55.903464 /lava-12379427/1/../bin/lava-test-case
10766 05:53:55.910105 <8>[ 17.901630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
10767 05:53:55.910351 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
10769 05:53:55.925090 /lava-12379427/1/../bin/lava-test-case
10770 05:53:55.931512 <8>[ 17.922822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
10771 05:53:55.931754 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
10773 05:53:55.941013 /lava-12379427/1/../bin/lava-test-case
10774 05:53:55.947264 <8>[ 17.939234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
10775 05:53:55.947505 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
10777 05:53:55.959445 /lava-12379427/1/../bin/lava-test-case
10778 05:53:55.965481 <8>[ 17.956416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
10779 05:53:55.965727 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
10781 05:53:55.978973 /lava-12379427/1/../bin/lava-test-case
10782 05:53:55.985675 <8>[ 17.977340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
10783 05:53:55.985916 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
10785 05:53:55.995570 /lava-12379427/1/../bin/lava-test-case
10786 05:53:56.002439 <8>[ 17.993756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
10787 05:53:56.002681 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
10789 05:53:56.016841 /lava-12379427/1/../bin/lava-test-case
10790 05:53:56.023476 <8>[ 18.015705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
10791 05:53:56.023721 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
10793 05:53:56.041026 /lava-12379427/1/../bin/lava-tes<8>[ 18.031037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
10794 05:53:56.041108 t-case
10795 05:53:56.041343 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
10797 05:53:56.051238 /lava-12379427/1/../bin/lava-test-case
10798 05:53:56.057766 <8>[ 18.048402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
10799 05:53:56.058013 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
10801 05:53:56.078067 /lava-12379427/1/../bin/lava-tes<8>[ 18.068270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
10802 05:53:56.078145 t-case
10803 05:53:56.078381 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
10805 05:53:56.093773 /lava-12379427/1/../bin/lava-test-case
10806 05:53:56.100129 <8>[ 18.091076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
10807 05:53:56.100371 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
10809 05:53:56.118314 /lava-12379427/1/../bin/lava-tes<8>[ 18.108283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
10810 05:53:56.118402 t-case
10811 05:53:56.118636 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
10813 05:53:56.130621 /lava-12379427/1/../bin/lava-test-case
10814 05:53:56.137127 <8>[ 18.128341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
10815 05:53:56.137379 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
10817 05:53:56.145000 /lava-12379427/1/../bin/lava-test-case
10818 05:53:56.152429 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
10820 05:53:56.154678 <8>[ 18.144704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
10821 05:53:56.165441 /lava-12379427/1/../bin/lava-test-case
10822 05:53:56.172641 <8>[ 18.162694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
10823 05:53:56.172913 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
10825 05:53:56.181226 /lava-12379427/1/../bin/lava-test-case
10826 05:53:56.187850 <8>[ 18.180412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
10827 05:53:56.188102 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
10829 05:53:56.198969 /lava-12379427/1/../bin/lava-test-case
10830 05:53:56.205765 <8>[ 18.196248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
10831 05:53:56.206016 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
10833 05:53:56.223702 /lava-12379427/1/../bin/lava-tes<8>[ 18.213595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
10834 05:53:56.223784 t-case
10835 05:53:56.224018 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
10837 05:53:56.238886 /lava-12379427/1/../bin/lava-tes<8>[ 18.229110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
10838 05:53:56.238967 t-case
10839 05:53:56.239201 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
10841 05:53:56.257870 /lava-12379427/1/../bin/lava-tes<8>[ 18.247782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
10842 05:53:56.257952 t-case
10843 05:53:56.258186 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
10845 05:53:56.273441 /lava-12379427/1/../bin/lava-tes<8>[ 18.263618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
10846 05:53:56.273523 t-case
10847 05:53:56.273757 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
10849 05:53:56.290445 /lava-12379427/1/../bin/lava-tes<8>[ 18.280200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
10850 05:53:56.290527 t-case
10851 05:53:56.290760 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
10853 05:53:56.301386 /lava-12379427/1/../bin/lava-test-case
10854 05:53:56.308085 <8>[ 18.299169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
10855 05:53:56.308338 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
10857 05:53:56.317841 /lava-12379427/1/../bin/lava-test-case
10858 05:53:56.324370 <8>[ 18.315411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
10859 05:53:56.324622 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
10861 05:53:56.343731 /lava-12379427/1/../bin/lava-tes<8>[ 18.333872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
10862 05:53:56.343813 t-case
10863 05:53:56.344047 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
10865 05:53:56.354667 /lava-12379427/1/../bin/lava-test-case
10866 05:53:56.361509 <8>[ 18.352284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
10867 05:53:56.361760 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
10869 05:53:56.371817 /lava-12379427/1/../bin/lava-test-case
10870 05:53:56.378142 <8>[ 18.369185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
10871 05:53:56.378394 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
10873 05:53:56.389635 /lava-12379427/1/../bin/lava-test-case
10874 05:53:56.396129 <8>[ 18.387371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
10875 05:53:56.396380 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
10877 05:53:56.406018 /lava-12379427/1/../bin/lava-test-case
10878 05:53:56.412220 <8>[ 18.404285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
10879 05:53:56.412471 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
10881 05:53:56.422796 /lava-12379427/1/../bin/lava-test-case
10882 05:53:56.429710 <8>[ 18.421652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
10883 05:53:56.429963 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
10885 05:53:56.441315 /lava-12379427/1/../bin/lava-test-case
10886 05:53:56.447346 <8>[ 18.438133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
10887 05:53:56.447598 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
10889 05:53:56.456714 /lava-12379427/1/../bin/lava-test-case
10890 05:53:56.463129 <8>[ 18.454687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
10891 05:53:56.463378 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
10893 05:53:56.476053 /lava-12379427/1/../bin/lava-test-case
10894 05:53:56.482078 <8>[ 18.473376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
10895 05:53:56.482321 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
10897 05:53:56.492856 /lava-12379427/1/../bin/lava-test-case
10898 05:53:56.499131 <8>[ 18.491130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
10899 05:53:56.499414 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
10901 05:53:56.511105 /lava-12379427/1/../bin/lava-test-case
10902 05:53:56.517433 <8>[ 18.508509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
10903 05:53:56.517673 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
10905 05:53:56.527208 /lava-12379427/1/../bin/lava-test-case
10906 05:53:56.533923 <8>[ 18.525955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
10907 05:53:56.534171 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
10909 05:53:56.543294 /lava-12379427/1/../bin/lava-test-case
10910 05:53:56.550179 <8>[ 18.542184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
10911 05:53:56.550428 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
10913 05:53:56.560714 /lava-12379427/1/../bin/lava-test-case
10914 05:53:56.567452 <8>[ 18.559457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
10915 05:53:56.567695 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
10917 05:53:56.576740 /lava-12379427/1/../bin/lava-test-case
10918 05:53:56.583514 <8>[ 18.574311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
10919 05:53:56.583762 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
10921 05:53:56.596146 /lava-12379427/1/../bin/lava-test-case
10922 05:53:56.603018 <8>[ 18.593670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
10923 05:53:56.603265 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
10925 05:53:56.610226 /lava-12379427/1/../bin/lava-test-case
10926 05:53:56.617147 <8>[ 18.609120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
10927 05:53:56.617392 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
10929 05:53:56.631291 /lava-12379427/1/../bin/lava-test-case
10930 05:53:56.637264 <8>[ 18.628418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
10931 05:53:56.637509 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
10933 05:53:56.646928 /lava-12379427/1/../bin/lava-test-case
10934 05:53:56.654053 <8>[ 18.644633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
10935 05:53:56.654303 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
10937 05:53:56.673450 /lava-12379427/1/../bin/lava-tes<8>[ 18.663503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
10938 05:53:56.673534 t-case
10939 05:53:56.673768 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
10941 05:53:56.680759 /lava-12379427/1/../bin/lava-test-case
10942 05:53:56.687108 <8>[ 18.679408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
10943 05:53:56.687351 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
10945 05:53:56.706152 /lava-12379427/1/../bin/lava-tes<8>[ 18.696177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
10946 05:53:56.706236 t-case
10947 05:53:56.706471 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
10949 05:53:56.721719 /lava-12379427/1/../bin/lava-tes<8>[ 18.711754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
10950 05:53:56.721797 t-case
10951 05:53:56.722028 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
10953 05:53:56.739332 /lava-12379427/1/../bin/lava-tes<8>[ 18.729432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
10954 05:53:56.739414 t-case
10955 05:53:56.739648 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
10957 05:53:56.748242 /lava-12379427/1/../bin/lava-test-case
10958 05:53:56.754863 <8>[ 18.746973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
10959 05:53:56.755104 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
10961 05:53:56.764531 /lava-12379427/1/../bin/lava-test-case
10962 05:53:56.771451 <8>[ 18.762334] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
10963 05:53:56.771695 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
10965 05:53:56.782500 /lava-12379427/1/../bin/lava-test-case
10966 05:53:56.788945 <8>[ 18.779892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
10967 05:53:56.789187 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
10969 05:53:56.803553 /lava-12379427/1/../bin/lava-tes<8>[ 18.793837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
10970 05:53:56.803630 t-case
10971 05:53:56.803865 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
10973 05:53:56.815842 /lava-12379427/1/../bin/lava-test-case
10974 05:53:56.822359 <8>[ 18.814792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
10975 05:53:56.822607 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
10977 05:53:56.831301 /lava-12379427/1/../bin/lava-test-case
10978 05:53:56.837848 <8>[ 18.828524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
10979 05:53:56.838095 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
10981 05:53:57.852982 /lava-12379427/1/../bin/lava-test-case
10982 05:53:57.859182 <8>[ 19.851408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
10983 05:53:57.859444 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
10985 05:53:57.867809 /lava-12379427/1/../bin/lava-test-case
10986 05:53:57.874757 <8>[ 19.865418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
10987 05:53:57.875004 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
10989 05:53:58.890784 /lava-12379427/1/../bin/lava-test-case
10990 05:53:58.897195 <8>[ 20.889359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
10991 05:53:58.897467 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
10993 05:53:58.905761 /lava-12379427/1/../bin/lava-test-case
10994 05:53:58.912485 <8>[ 20.904182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
10995 05:53:58.912746 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
10997 05:53:59.927730 /lava-12379427/1/../bin/lava-test-case
10998 05:53:59.933981 <8>[ 21.925316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
10999 05:53:59.934242 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11001 05:53:59.953672 /lava-12379427/1/../bin/lava-tes<8>[ 21.944320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11002 05:53:59.953777 t-case
11003 05:53:59.954039 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11005 05:54:00.967353 /lava-12379427/1/../bin/lava-test-case
11006 05:54:00.973658 <8>[ 22.964993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11007 05:54:00.973924 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11009 05:54:00.983236 /lava-12379427/1/../bin/lava-test-case
11010 05:54:00.989436 <8>[ 22.981693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11011 05:54:00.989688 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11013 05:54:02.004459 /lava-12379427/1/../bin/lava-test-case
11014 05:54:02.010974 <8>[ 24.002955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11015 05:54:02.011239 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11017 05:54:02.022149 /lava-12379427/1/../bin/lava-test-case
11018 05:54:02.031945 <8>[ 24.021883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11019 05:54:02.032194 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11021 05:54:03.044002 /lava-12379427/1/../bin/lava-test-case
11022 05:54:03.050690 <8>[ 25.041657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11023 05:54:03.051523 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11025 05:54:03.070598 /lava-12379427/1/../bin/lava-tes<8>[ 25.061069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11026 05:54:03.071195 t-case
11027 05:54:03.071831 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11029 05:54:04.083316 /lava-12379427/1/../bin/lava-test-case
11030 05:54:04.089624 <8>[ 26.081124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11031 05:54:04.090353 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11033 05:54:04.101621 /lava-12379427/1/../bin/lava-test-case
11034 05:54:04.108379 <8>[ 26.100386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11035 05:54:04.109239 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11037 05:54:04.125575 /lava-12379427/1/../bin/lava-tes<8>[ 26.115998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11038 05:54:04.126100 t-case
11039 05:54:04.126685 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11041 05:54:05.136421 /lava-12379427/1/../bin/lava-test-case
11042 05:54:05.143070 <8>[ 27.134276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11043 05:54:05.143807 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11045 05:54:05.160896 /lava-12379427/1/../bin/lava-tes<8>[ 27.151197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11046 05:54:05.161365 t-case
11047 05:54:05.161987 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11049 05:54:05.182753 /lava-12379427/1/../bin/lava-tes<8>[ 27.172708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11050 05:54:05.183306 t-case
11051 05:54:05.183949 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11053 05:54:05.190452 /lava-12379427/1/../bin/lava-test-case
11054 05:54:05.196953 <8>[ 27.188584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11055 05:54:05.197779 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11057 05:54:05.209157 /lava-12379427/1/../bin/lava-test-case
11058 05:54:05.215276 <8>[ 27.206829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11059 05:54:05.216095 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11061 05:54:05.233391 /lava-12379427/1/../bin/lava-tes<8>[ 27.224067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11062 05:54:05.234103 t-case
11063 05:54:05.234915 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11065 05:54:05.245334 /lava-12379427/1/../bin/lava-test-case
11066 05:54:05.255156 <8>[ 27.245006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11067 05:54:05.255964 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11069 05:54:05.262186 /lava-12379427/1/../bin/lava-test-case
11070 05:54:05.272132 <8>[ 27.263540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11071 05:54:05.272929 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11073 05:54:05.284016 /lava-12379427/1/../bin/lava-test-case
11074 05:54:05.290580 <8>[ 27.282329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11075 05:54:05.291302 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11077 05:54:05.300784 /lava-12379427/1/../bin/lava-test-case
11078 05:54:05.307383 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11080 05:54:05.310086 <8>[ 27.300379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11081 05:54:05.324806 /lava-12379427/1/../bin/lava-tes<8>[ 27.315593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11082 05:54:05.325354 t-case
11083 05:54:05.325991 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11085 05:54:05.334460 /lava-12379427/1/../bin/lava-test-case
11086 05:54:05.341056 <8>[ 27.332521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11087 05:54:05.341782 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11089 05:54:05.359067 /lava-12379427/1/../bin/lava-tes<8>[ 27.349616] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11090 05:54:05.359594 t-case
11091 05:54:05.360227 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11093 05:54:05.369569 /lava-12379427/1/../bin/lava-test-case
11094 05:54:05.376094 <8>[ 27.367899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11095 05:54:05.376837 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11097 05:54:05.393111 /lava-12379427/1/../bin/lava-tes<8>[ 27.383429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11098 05:54:05.393726 t-case
11099 05:54:05.394366 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11101 05:54:05.402954 /lava-12379427/1/../bin/lava-test-case
11102 05:54:05.409325 <8>[ 27.401509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11103 05:54:05.410155 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11105 05:54:05.426476 /lava-12379427/1/../bin/lava-tes<8>[ 27.416761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11106 05:54:05.427035 t-case
11107 05:54:05.427677 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11109 05:54:05.436234 /lava-12379427/1/../bin/lava-test-case
11110 05:54:05.442680 <8>[ 27.433860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11111 05:54:05.443482 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11113 05:54:05.451887 /lava-12379427/1/../bin/lava-test-case
11114 05:54:05.458978 <8>[ 27.450375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11115 05:54:05.459731 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11117 05:54:05.468865 /lava-12379427/1/../bin/lava-test-case
11118 05:54:05.475860 <8>[ 27.466959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11119 05:54:05.476630 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11121 05:54:05.484947 /lava-12379427/1/../bin/lava-test-case
11122 05:54:05.491861 <8>[ 27.482953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11123 05:54:05.492702 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11125 05:54:06.503981 /lava-12379427/1/../bin/lava-test-case
11126 05:54:06.510503 <8>[ 28.501636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11127 05:54:06.511346 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11129 05:54:07.526747 /lava-12379427/1/../bin/lava-test-case
11130 05:54:07.533293 <8>[ 29.525745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11131 05:54:07.534217 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11133 05:54:07.541381 /lava-12379427/1/../bin/lava-test-case
11134 05:54:07.548170 <8>[ 29.539717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11135 05:54:07.549063 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11137 05:54:07.569969 /lava-12379427/1/../bin/lava-tes<8>[ 29.560529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11138 05:54:07.570574 t-case
11139 05:54:07.571235 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11141 05:54:07.585660 /lava-12379427/1/../bin/lava-tes<8>[ 29.576515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11142 05:54:07.586277 t-case
11143 05:54:07.586921 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11145 05:54:07.596941 /lava-12379427/1/../bin/lava-test-case
11146 05:54:07.603703 <8>[ 29.595422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11147 05:54:07.604532 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11149 05:54:07.612933 /lava-12379427/1/../bin/lava-test-case
11150 05:54:07.619372 <8>[ 29.611221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11151 05:54:07.620208 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11153 05:54:07.629053 /lava-12379427/1/../bin/lava-test-case
11154 05:54:07.639118 <8>[ 29.630834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11155 05:54:07.639936 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11157 05:54:07.647855 /lava-12379427/1/../bin/lava-test-case
11158 05:54:07.654276 <8>[ 29.645669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11159 05:54:07.655014 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11161 05:54:07.664425 /lava-12379427/1/../bin/lava-test-case
11162 05:54:07.670716 <8>[ 29.664429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11163 05:54:07.671452 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11165 05:54:07.680788 /lava-12379427/1/../bin/lava-test-case
11166 05:54:07.687144 <8>[ 29.678904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11167 05:54:07.687979 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11169 05:54:07.699812 /lava-12379427/1/../bin/lava-test-case
11170 05:54:07.706286 <8>[ 29.699042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11171 05:54:07.707121 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11173 05:54:07.721336 /lava-12379427/1/../bin/lava-tes<8>[ 29.712106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11174 05:54:07.721882 t-case
11175 05:54:07.722520 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11177 05:54:07.741739 /lava-12379427/1/../bin/lava-tes<8>[ 29.732049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11178 05:54:07.742306 t-case
11179 05:54:07.742950 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11181 05:54:07.748884 /lava-12379427/1/../bin/lava-test-case
11182 05:54:07.758777 <8>[ 29.750476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11183 05:54:07.759670 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11185 05:54:07.773856 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11187 05:54:07.776357 /lava-12379427/1/../bin/lava-tes<8>[ 29.767320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11188 05:54:07.776860 t-case
11189 05:54:07.783338 /lava-12379427/1/../bin/lava-test-case
11190 05:54:07.790019 <8>[ 29.782506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11191 05:54:07.790853 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11193 05:54:07.805567 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11195 05:54:07.808226 /lava-12379427/1/../bin/lava-tes<8>[ 29.799053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11196 05:54:07.808832 t-case
11197 05:54:07.815574 /lava-12379427/1/../bin/lava-test-case
11198 05:54:07.822213 <8>[ 29.814200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11199 05:54:07.822984 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11201 05:54:07.839253 /lava-12379427/1/../bin/lava-tes<8>[ 29.833075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11202 05:54:07.840093 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11204 05:54:07.842193 t-case
11205 05:54:07.848652 /lava-12379427/1/../bin/lava-test-case
11206 05:54:07.855337 <8>[ 29.847347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11207 05:54:07.856176 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11209 05:54:07.866878 /lava-12379427/1/../bin/lava-test-case
11210 05:54:07.873814 <8>[ 29.865020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11211 05:54:07.874547 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11213 05:54:08.885089 /lava-12379427/1/../bin/lava-test-case
11214 05:54:08.892117 <8>[ 30.884189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11215 05:54:08.892987 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11217 05:54:09.907227 /lava-12379427/1/../bin/lava-test-case
11218 05:54:09.913715 <8>[ 31.906825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11219 05:54:09.914447 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11220 05:54:09.914914 Bad test result: blocked
11221 05:54:09.923061 /lava-12379427/1/../bin/lava-test-case
11222 05:54:09.929481 <8>[ 31.921602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11223 05:54:09.930370 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11225 05:54:10.944389 /lava-12379427/1/../bin/lava-test-case
11226 05:54:10.950876 <8>[ 32.943642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11227 05:54:10.951157 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11229 05:54:10.961218 /lava-12379427/1/../bin/lava-test-case
11230 05:54:10.967316 <8>[ 32.960768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11231 05:54:10.967583 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11233 05:54:10.979909 /lava-12379427/1/../bin/lava-test-case
11234 05:54:10.986099 <8>[ 32.979830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11235 05:54:10.986365 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11237 05:54:11.000015 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11239 05:54:11.002968 /lava-12379427/1/../bin/lava-tes<8>[ 32.995069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11240 05:54:11.003053 t-case
11241 05:54:11.019754 /lava-12379427/1/../bin/lava-tes<8>[ 33.011893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11242 05:54:11.019832 t-case
11243 05:54:11.020074 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11245 05:54:11.029601 /lava-12379427/1/../bin/lava-test-case
11246 05:54:11.036210 <8>[ 33.028632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11247 05:54:11.036456 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11249 05:54:11.053299 /lava-12379427/1/../bin/lava-tes<8>[ 33.045474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11250 05:54:11.053380 t-case
11251 05:54:11.053612 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11253 05:54:12.066294 /lava-12379427/1/../bin/lava-test-case
11254 05:54:12.072595 <8>[ 34.064610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11255 05:54:12.073644 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11257 05:54:12.082560 /lava-12379427/1/../bin/lava-test-case
11258 05:54:12.088771 <8>[ 34.081799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11259 05:54:12.089026 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11261 05:54:13.102144 /lava-12379427/1/../bin/lava-test-case
11262 05:54:13.108773 <8>[ 35.100592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11263 05:54:13.109703 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11265 05:54:13.119259 /lava-12379427/1/../bin/lava-test-case
11266 05:54:13.125640 <8>[ 35.118988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11267 05:54:13.126508 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11269 05:54:14.140482 /lava-12379427/1/../bin/lava-test-case
11270 05:54:14.147112 <8>[ 36.140767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11271 05:54:14.147860 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11273 05:54:14.156018 /lava-12379427/1/../bin/lava-test-case
11274 05:54:14.162544 <8>[ 36.154941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11275 05:54:14.163410 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11277 05:54:15.178050 /lava-12379427/1/../bin/lava-test-case
11278 05:54:15.184679 <8>[ 37.178096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11279 05:54:15.185440 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11281 05:54:15.194759 /lava-12379427/1/../bin/lava-test-case
11282 05:54:15.201346 <8>[ 37.193894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11283 05:54:15.202099 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11285 05:54:15.213155 /lava-12379427/1/../bin/lava-test-case
11286 05:54:15.219154 <8>[ 37.213151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11287 05:54:15.220018 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11289 05:54:15.230387 /lava-12379427/1/../bin/lava-test-case
11290 05:54:15.237080 <8>[ 37.230539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11291 05:54:15.237939 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11293 05:54:15.251647 /lava-12379427/1/../bin/lava-tes<8>[ 37.243437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11294 05:54:15.252208 t-case
11295 05:54:15.252845 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11297 05:54:15.263995 /lava-12379427/1/../bin/lava-test-case
11298 05:54:15.270670 <8>[ 37.265611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11299 05:54:15.271502 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11301 05:54:15.280386 /lava-12379427/1/../bin/lava-test-case
11302 05:54:15.287345 <8>[ 37.280106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11303 05:54:15.288182 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11305 05:54:15.305190 /lava-12379427/1/../bin/lava-tes<8>[ 37.296633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11306 05:54:15.305740 t-case
11307 05:54:15.306372 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11309 05:54:15.322236 /lava-12379427/1/../bin/lava-tes<8>[ 37.314030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11310 05:54:15.322798 t-case
11311 05:54:15.323443 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11313 05:54:15.331938 /lava-12379427/1/../bin/lava-test-case
11314 05:54:15.338559 <8>[ 37.332491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11315 05:54:15.339400 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11317 05:54:15.344032 + set +x
11318 05:54:15.347412 Received signal: <ENDRUN> 1_bootrr 12379427_1.5.2.3.5
11319 05:54:15.348012 Ending use of test pattern.
11320 05:54:15.348424 Ending test lava.1_bootrr (12379427_1.5.2.3.5), duration 20.30
11322 05:54:15.350147 <8>[ 37.342812] <LAVA_SIGNAL_ENDRUN 1_bootrr 12379427_1.5.2.3.5>
11323 05:54:15.350531 <LAVA_TEST_RUNNER EXIT>
11324 05:54:15.351133 ok: lava_test_shell seems to have completed
11325 05:54:15.356902 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11326 05:54:15.357699 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11327 05:54:15.358178 end: 4 lava-test-retry (duration 00:00:21) [common]
11328 05:54:15.358680 start: 5 finalize (timeout 00:08:08) [common]
11329 05:54:15.359158 start: 5.1 power-off (timeout 00:00:30) [common]
11330 05:54:15.360096 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11331 05:54:15.447229 >> Command sent successfully.
11332 05:54:15.451482 Returned 0 in 0 seconds
11333 05:54:15.552507 end: 5.1 power-off (duration 00:00:00) [common]
11335 05:54:15.554431 start: 5.2 read-feedback (timeout 00:08:08) [common]
11336 05:54:15.556036 Listened to connection for namespace 'common' for up to 1s
11337 05:54:15.557037 Listened to connection for namespace 'common' for up to 1s
11338 05:54:16.556548 Finalising connection for namespace 'common'
11339 05:54:16.557402 Disconnecting from shell: Finalise
11340 05:54:16.557883 / #
11341 05:54:16.659014 end: 5.2 read-feedback (duration 00:00:01) [common]
11342 05:54:16.659755 end: 5 finalize (duration 00:00:01) [common]
11343 05:54:16.660683 Cleaning after the job
11344 05:54:16.661346 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379427/tftp-deploy-3jn6beu8/ramdisk
11345 05:54:16.676820 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379427/tftp-deploy-3jn6beu8/kernel
11346 05:54:16.704958 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379427/tftp-deploy-3jn6beu8/dtb
11347 05:54:16.705273 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379427/tftp-deploy-3jn6beu8/modules
11348 05:54:16.716375 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12379427
11349 05:54:16.764780 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12379427
11350 05:54:16.764955 Job finished correctly