Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 16
- Kernel Errors: 35
- Errors: 0
1 06:02:03.586581 lava-dispatcher, installed at version: 2023.10
2 06:02:03.586777 start: 0 validate
3 06:02:03.586913 Start time: 2023-12-25 06:02:03.586906+00:00 (UTC)
4 06:02:03.587038 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:02:03.587175 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 06:02:03.858648 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:02:03.858817 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:02:04.116714 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:02:04.116923 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:02:04.382522 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:02:04.382685 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 06:02:04.649411 validate duration: 1.06
14 06:02:04.649691 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:02:04.649790 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:02:04.649880 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:02:04.650041 Not decompressing ramdisk as can be used compressed.
18 06:02:04.650131 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 06:02:04.650200 saving as /var/lib/lava/dispatcher/tmp/12379474/tftp-deploy-ibdd2s4k/ramdisk/rootfs.cpio.gz
20 06:02:04.650267 total size: 43284872 (41 MB)
21 06:02:04.651399 progress 0 % (0 MB)
22 06:02:04.662813 progress 5 % (2 MB)
23 06:02:04.673803 progress 10 % (4 MB)
24 06:02:04.684888 progress 15 % (6 MB)
25 06:02:04.695807 progress 20 % (8 MB)
26 06:02:04.706699 progress 25 % (10 MB)
27 06:02:04.717567 progress 30 % (12 MB)
28 06:02:04.728511 progress 35 % (14 MB)
29 06:02:04.739436 progress 40 % (16 MB)
30 06:02:04.750451 progress 45 % (18 MB)
31 06:02:04.761502 progress 50 % (20 MB)
32 06:02:04.772657 progress 55 % (22 MB)
33 06:02:04.783634 progress 60 % (24 MB)
34 06:02:04.794658 progress 65 % (26 MB)
35 06:02:04.805509 progress 70 % (28 MB)
36 06:02:04.816417 progress 75 % (30 MB)
37 06:02:04.827295 progress 80 % (33 MB)
38 06:02:04.838160 progress 85 % (35 MB)
39 06:02:04.848968 progress 90 % (37 MB)
40 06:02:04.859741 progress 95 % (39 MB)
41 06:02:04.870466 progress 100 % (41 MB)
42 06:02:04.870717 41 MB downloaded in 0.22 s (187.25 MB/s)
43 06:02:04.870880 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:02:04.871127 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:02:04.871216 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:02:04.871301 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:02:04.871434 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 06:02:04.871505 saving as /var/lib/lava/dispatcher/tmp/12379474/tftp-deploy-ibdd2s4k/kernel/Image
50 06:02:04.871570 total size: 50024960 (47 MB)
51 06:02:04.871633 No compression specified
52 06:02:04.872892 progress 0 % (0 MB)
53 06:02:04.885821 progress 5 % (2 MB)
54 06:02:04.898455 progress 10 % (4 MB)
55 06:02:04.911016 progress 15 % (7 MB)
56 06:02:04.923730 progress 20 % (9 MB)
57 06:02:04.936247 progress 25 % (11 MB)
58 06:02:04.948924 progress 30 % (14 MB)
59 06:02:04.961641 progress 35 % (16 MB)
60 06:02:04.974329 progress 40 % (19 MB)
61 06:02:04.986971 progress 45 % (21 MB)
62 06:02:04.999652 progress 50 % (23 MB)
63 06:02:05.012328 progress 55 % (26 MB)
64 06:02:05.024919 progress 60 % (28 MB)
65 06:02:05.037595 progress 65 % (31 MB)
66 06:02:05.050153 progress 70 % (33 MB)
67 06:02:05.062763 progress 75 % (35 MB)
68 06:02:05.075501 progress 80 % (38 MB)
69 06:02:05.088018 progress 85 % (40 MB)
70 06:02:05.100474 progress 90 % (42 MB)
71 06:02:05.112973 progress 95 % (45 MB)
72 06:02:05.125175 progress 100 % (47 MB)
73 06:02:05.125380 47 MB downloaded in 0.25 s (187.97 MB/s)
74 06:02:05.125531 end: 1.2.1 http-download (duration 00:00:00) [common]
76 06:02:05.125761 end: 1.2 download-retry (duration 00:00:00) [common]
77 06:02:05.125854 start: 1.3 download-retry (timeout 00:10:00) [common]
78 06:02:05.125950 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 06:02:05.126091 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 06:02:05.126164 saving as /var/lib/lava/dispatcher/tmp/12379474/tftp-deploy-ibdd2s4k/dtb/mt8192-asurada-spherion-r0.dtb
81 06:02:05.126227 total size: 47278 (0 MB)
82 06:02:05.126290 No compression specified
83 06:02:05.127344 progress 69 % (0 MB)
84 06:02:05.127618 progress 100 % (0 MB)
85 06:02:05.127773 0 MB downloaded in 0.00 s (29.20 MB/s)
86 06:02:05.127896 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:02:05.128120 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:02:05.128208 start: 1.4 download-retry (timeout 00:10:00) [common]
90 06:02:05.128295 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 06:02:05.128407 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 06:02:05.128477 saving as /var/lib/lava/dispatcher/tmp/12379474/tftp-deploy-ibdd2s4k/modules/modules.tar
93 06:02:05.128540 total size: 8619328 (8 MB)
94 06:02:05.128603 Using unxz to decompress xz
95 06:02:05.132300 progress 0 % (0 MB)
96 06:02:05.153631 progress 5 % (0 MB)
97 06:02:05.177362 progress 10 % (0 MB)
98 06:02:05.201364 progress 15 % (1 MB)
99 06:02:05.225480 progress 20 % (1 MB)
100 06:02:05.250071 progress 25 % (2 MB)
101 06:02:05.275868 progress 30 % (2 MB)
102 06:02:05.302332 progress 35 % (2 MB)
103 06:02:05.325832 progress 40 % (3 MB)
104 06:02:05.350269 progress 45 % (3 MB)
105 06:02:05.375722 progress 50 % (4 MB)
106 06:02:05.400239 progress 55 % (4 MB)
107 06:02:05.425187 progress 60 % (4 MB)
108 06:02:05.450821 progress 65 % (5 MB)
109 06:02:05.477888 progress 70 % (5 MB)
110 06:02:05.501578 progress 75 % (6 MB)
111 06:02:05.528734 progress 80 % (6 MB)
112 06:02:05.554712 progress 85 % (7 MB)
113 06:02:05.581890 progress 90 % (7 MB)
114 06:02:05.614121 progress 95 % (7 MB)
115 06:02:05.644238 progress 100 % (8 MB)
116 06:02:05.649040 8 MB downloaded in 0.52 s (15.79 MB/s)
117 06:02:05.649300 end: 1.4.1 http-download (duration 00:00:01) [common]
119 06:02:05.649568 end: 1.4 download-retry (duration 00:00:01) [common]
120 06:02:05.649661 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 06:02:05.649758 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 06:02:05.649840 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:02:05.649927 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 06:02:05.650153 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv
125 06:02:05.650284 makedir: /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin
126 06:02:05.650389 makedir: /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/tests
127 06:02:05.650487 makedir: /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/results
128 06:02:05.650603 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-add-keys
129 06:02:05.650745 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-add-sources
130 06:02:05.650871 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-background-process-start
131 06:02:05.650997 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-background-process-stop
132 06:02:05.651120 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-common-functions
133 06:02:05.651243 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-echo-ipv4
134 06:02:05.651363 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-install-packages
135 06:02:05.651483 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-installed-packages
136 06:02:05.651600 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-os-build
137 06:02:05.651719 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-probe-channel
138 06:02:05.651838 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-probe-ip
139 06:02:05.651957 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-target-ip
140 06:02:05.652075 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-target-mac
141 06:02:05.652193 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-target-storage
142 06:02:05.652317 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-test-case
143 06:02:05.652438 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-test-event
144 06:02:05.652557 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-test-feedback
145 06:02:05.652678 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-test-raise
146 06:02:05.652797 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-test-reference
147 06:02:05.652915 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-test-runner
148 06:02:05.653036 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-test-set
149 06:02:05.653156 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-test-shell
150 06:02:05.653278 Updating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-install-packages (oe)
151 06:02:05.653422 Updating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/bin/lava-installed-packages (oe)
152 06:02:05.653546 Creating /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/environment
153 06:02:05.653649 LAVA metadata
154 06:02:05.653722 - LAVA_JOB_ID=12379474
155 06:02:05.653787 - LAVA_DISPATCHER_IP=192.168.201.1
156 06:02:05.653889 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 06:02:05.653983 skipped lava-vland-overlay
158 06:02:05.654072 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 06:02:05.654157 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 06:02:05.654224 skipped lava-multinode-overlay
161 06:02:05.654298 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 06:02:05.654382 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 06:02:05.654457 Loading test definitions
164 06:02:05.654548 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 06:02:05.654623 Using /lava-12379474 at stage 0
166 06:02:05.654914 uuid=12379474_1.5.2.3.1 testdef=None
167 06:02:05.655002 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 06:02:05.655086 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 06:02:05.655581 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 06:02:05.655804 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 06:02:05.656478 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 06:02:05.656848 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 06:02:05.657728 runner path: /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/0/tests/0_igt-gpu-panfrost test_uuid 12379474_1.5.2.3.1
176 06:02:05.657920 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 06:02:05.658170 Creating lava-test-runner.conf files
179 06:02:05.658236 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379474/lava-overlay-16x146sv/lava-12379474/0 for stage 0
180 06:02:05.658324 - 0_igt-gpu-panfrost
181 06:02:05.658420 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 06:02:05.658505 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 06:02:05.665084 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 06:02:05.665194 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 06:02:05.665285 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 06:02:05.665372 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 06:02:05.665466 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 06:02:06.977881 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 06:02:06.978270 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 06:02:06.978385 extracting modules file /var/lib/lava/dispatcher/tmp/12379474/tftp-deploy-ibdd2s4k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379474/extract-overlay-ramdisk-z09c09zz/ramdisk
191 06:02:07.186397 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 06:02:07.186567 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 06:02:07.186666 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379474/compress-overlay-k0s8w774/overlay-1.5.2.4.tar.gz to ramdisk
194 06:02:07.186742 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379474/compress-overlay-k0s8w774/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12379474/extract-overlay-ramdisk-z09c09zz/ramdisk
195 06:02:07.192994 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 06:02:07.193108 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 06:02:07.193201 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 06:02:07.193294 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 06:02:07.193372 Building ramdisk /var/lib/lava/dispatcher/tmp/12379474/extract-overlay-ramdisk-z09c09zz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12379474/extract-overlay-ramdisk-z09c09zz/ramdisk
200 06:02:08.126730 >> 369993 blocks
201 06:02:13.785127 rename /var/lib/lava/dispatcher/tmp/12379474/extract-overlay-ramdisk-z09c09zz/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12379474/tftp-deploy-ibdd2s4k/ramdisk/ramdisk.cpio.gz
202 06:02:13.785533 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 06:02:13.785682 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 06:02:13.785812 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 06:02:13.785975 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12379474/tftp-deploy-ibdd2s4k/kernel/Image'
206 06:02:25.958260 Returned 0 in 12 seconds
207 06:02:26.058851 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12379474/tftp-deploy-ibdd2s4k/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12379474/tftp-deploy-ibdd2s4k/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12379474/tftp-deploy-ibdd2s4k/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12379474/tftp-deploy-ibdd2s4k/kernel/image.itb
208 06:02:26.792268 output: FIT description: Kernel Image image with one or more FDT blobs
209 06:02:26.792641 output: Created: Mon Dec 25 06:02:26 2023
210 06:02:26.792717 output: Image 0 (kernel-1)
211 06:02:26.792785 output: Description:
212 06:02:26.792859 output: Created: Mon Dec 25 06:02:26 2023
213 06:02:26.792924 output: Type: Kernel Image
214 06:02:26.792983 output: Compression: lzma compressed
215 06:02:26.793042 output: Data Size: 11481830 Bytes = 11212.72 KiB = 10.95 MiB
216 06:02:26.793102 output: Architecture: AArch64
217 06:02:26.793160 output: OS: Linux
218 06:02:26.793213 output: Load Address: 0x00000000
219 06:02:26.793269 output: Entry Point: 0x00000000
220 06:02:26.793324 output: Hash algo: crc32
221 06:02:26.793379 output: Hash value: a47c00f1
222 06:02:26.793434 output: Image 1 (fdt-1)
223 06:02:26.793490 output: Description: mt8192-asurada-spherion-r0
224 06:02:26.793543 output: Created: Mon Dec 25 06:02:26 2023
225 06:02:26.793596 output: Type: Flat Device Tree
226 06:02:26.793649 output: Compression: uncompressed
227 06:02:26.793702 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 06:02:26.793764 output: Architecture: AArch64
229 06:02:26.793856 output: Hash algo: crc32
230 06:02:26.793961 output: Hash value: cc4352de
231 06:02:26.794033 output: Image 2 (ramdisk-1)
232 06:02:26.794087 output: Description: unavailable
233 06:02:26.794140 output: Created: Mon Dec 25 06:02:26 2023
234 06:02:26.794194 output: Type: RAMDisk Image
235 06:02:26.794247 output: Compression: Unknown Compression
236 06:02:26.794300 output: Data Size: 56452572 Bytes = 55129.46 KiB = 53.84 MiB
237 06:02:26.794353 output: Architecture: AArch64
238 06:02:26.794414 output: OS: Linux
239 06:02:26.794467 output: Load Address: unavailable
240 06:02:26.794521 output: Entry Point: unavailable
241 06:02:26.794579 output: Hash algo: crc32
242 06:02:26.794633 output: Hash value: 4532ff3b
243 06:02:26.794686 output: Default Configuration: 'conf-1'
244 06:02:26.794739 output: Configuration 0 (conf-1)
245 06:02:26.794791 output: Description: mt8192-asurada-spherion-r0
246 06:02:26.794844 output: Kernel: kernel-1
247 06:02:26.794904 output: Init Ramdisk: ramdisk-1
248 06:02:26.794957 output: FDT: fdt-1
249 06:02:26.795010 output: Loadables: kernel-1
250 06:02:26.795062 output:
251 06:02:26.795246 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 06:02:26.795342 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 06:02:26.795451 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 06:02:26.795542 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 06:02:26.795621 No LXC device requested
256 06:02:26.795700 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 06:02:26.795783 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 06:02:26.795896 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 06:02:26.795996 Checking files for TFTP limit of 4294967296 bytes.
260 06:02:26.796493 end: 1 tftp-deploy (duration 00:00:22) [common]
261 06:02:26.796601 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 06:02:26.796696 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 06:02:26.796819 substitutions:
264 06:02:26.796886 - {DTB}: 12379474/tftp-deploy-ibdd2s4k/dtb/mt8192-asurada-spherion-r0.dtb
265 06:02:26.796950 - {INITRD}: 12379474/tftp-deploy-ibdd2s4k/ramdisk/ramdisk.cpio.gz
266 06:02:26.797010 - {KERNEL}: 12379474/tftp-deploy-ibdd2s4k/kernel/Image
267 06:02:26.797069 - {LAVA_MAC}: None
268 06:02:26.797125 - {PRESEED_CONFIG}: None
269 06:02:26.797204 - {PRESEED_LOCAL}: None
270 06:02:26.797261 - {RAMDISK}: 12379474/tftp-deploy-ibdd2s4k/ramdisk/ramdisk.cpio.gz
271 06:02:26.797317 - {ROOT_PART}: None
272 06:02:26.797372 - {ROOT}: None
273 06:02:26.797427 - {SERVER_IP}: 192.168.201.1
274 06:02:26.797496 - {TEE}: None
275 06:02:26.797552 Parsed boot commands:
276 06:02:26.797607 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 06:02:26.797779 Parsed boot commands: tftpboot 192.168.201.1 12379474/tftp-deploy-ibdd2s4k/kernel/image.itb 12379474/tftp-deploy-ibdd2s4k/kernel/cmdline
278 06:02:26.797867 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 06:02:26.797958 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 06:02:26.798099 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 06:02:26.798183 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 06:02:26.798255 Not connected, no need to disconnect.
283 06:02:26.798329 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 06:02:26.798408 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 06:02:26.798474 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 06:02:26.801806 Setting prompt string to ['lava-test: # ']
287 06:02:26.802208 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 06:02:26.802318 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 06:02:26.802417 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 06:02:26.802510 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 06:02:26.802705 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 06:02:31.950265 >> Command sent successfully.
293 06:02:31.961035 Returned 0 in 5 seconds
294 06:02:32.062274 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 06:02:32.063723 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 06:02:32.064277 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 06:02:32.064767 Setting prompt string to 'Starting depthcharge on Spherion...'
299 06:02:32.065144 Changing prompt to 'Starting depthcharge on Spherion...'
300 06:02:32.065536 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 06:02:32.066831 [Enter `^Ec?' for help]
302 06:02:32.225571
303 06:02:32.226246
304 06:02:32.226704 F0: 102B 0000
305 06:02:32.227126
306 06:02:32.227475 F3: 1001 0000 [0200]
307 06:02:32.227833
308 06:02:32.229136 F3: 1001 0000
309 06:02:32.229678
310 06:02:32.230095 F7: 102D 0000
311 06:02:32.230502
312 06:02:32.230839 F1: 0000 0000
313 06:02:32.232907
314 06:02:32.233408 V0: 0000 0000 [0001]
315 06:02:32.233847
316 06:02:32.234330 00: 0007 8000
317 06:02:32.234699
318 06:02:32.236714 01: 0000 0000
319 06:02:32.237294
320 06:02:32.237792 BP: 0C00 0209 [0000]
321 06:02:32.238211
322 06:02:32.240440 G0: 1182 0000
323 06:02:32.241010
324 06:02:32.241450 EC: 0000 0021 [4000]
325 06:02:32.242175
326 06:02:32.244042 S7: 0000 0000 [0000]
327 06:02:32.244576
328 06:02:32.244995 CC: 0000 0000 [0001]
329 06:02:32.245354
330 06:02:32.247634 T0: 0000 0040 [010F]
331 06:02:32.248155
332 06:02:32.248552 Jump to BL
333 06:02:32.248931
334 06:02:32.272271
335 06:02:32.272702
336 06:02:32.273039
337 06:02:32.279591 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 06:02:32.283574 ARM64: Exception handlers installed.
339 06:02:32.286707 ARM64: Testing exception
340 06:02:32.290369 ARM64: Done test exception
341 06:02:32.297843 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 06:02:32.305436 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 06:02:32.312530 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 06:02:32.323321 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 06:02:32.330107 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 06:02:32.340088 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 06:02:32.350518 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 06:02:32.357292 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 06:02:32.375202 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 06:02:32.378479 WDT: Last reset was cold boot
351 06:02:32.381854 SPI1(PAD0) initialized at 2873684 Hz
352 06:02:32.385362 SPI5(PAD0) initialized at 992727 Hz
353 06:02:32.388792 VBOOT: Loading verstage.
354 06:02:32.395329 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 06:02:32.398554 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 06:02:32.401857 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 06:02:32.405344 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 06:02:32.412431 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 06:02:32.419439 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 06:02:32.430563 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 06:02:32.431157
362 06:02:32.431656
363 06:02:32.440510 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 06:02:32.443583 ARM64: Exception handlers installed.
365 06:02:32.446869 ARM64: Testing exception
366 06:02:32.447481 ARM64: Done test exception
367 06:02:32.453738 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 06:02:32.457103 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 06:02:32.471161 Probing TPM: . done!
370 06:02:32.471767 TPM ready after 0 ms
371 06:02:32.478031 Connected to device vid:did:rid of 1ae0:0028:00
372 06:02:32.485130 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 06:02:32.542323 Initialized TPM device CR50 revision 0
374 06:02:32.545671 tlcl_send_startup: Startup return code is 0
375 06:02:32.551884 TPM: setup succeeded
376 06:02:32.562766 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 06:02:32.571859 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 06:02:32.581891 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 06:02:32.590732 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 06:02:32.594741 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 06:02:32.606582 in-header: 03 07 00 00 08 00 00 00
382 06:02:32.610342 in-data: aa e4 47 04 13 02 00 00
383 06:02:32.614149 Chrome EC: UHEPI supported
384 06:02:32.621224 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 06:02:32.624611 in-header: 03 ad 00 00 08 00 00 00
386 06:02:32.628601 in-data: 00 20 20 08 00 00 00 00
387 06:02:32.629192 Phase 1
388 06:02:32.632040 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 06:02:32.639283 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 06:02:32.643180 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 06:02:32.646838 Recovery requested (1009000e)
392 06:02:32.655962 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 06:02:32.661672 tlcl_extend: response is 0
394 06:02:32.670935 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 06:02:32.676120 tlcl_extend: response is 0
396 06:02:32.683173 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 06:02:32.703142 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 06:02:32.710618 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 06:02:32.711200
400 06:02:32.711716
401 06:02:32.720436 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 06:02:32.723688 ARM64: Exception handlers installed.
403 06:02:32.724182 ARM64: Testing exception
404 06:02:32.727413 ARM64: Done test exception
405 06:02:32.749803 pmic_efuse_setting: Set efuses in 11 msecs
406 06:02:32.752342 pmwrap_interface_init: Select PMIF_VLD_RDY
407 06:02:32.759298 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 06:02:32.762983 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 06:02:32.766114 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 06:02:32.772804 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 06:02:32.776374 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 06:02:32.783898 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 06:02:32.787099 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 06:02:32.790808 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 06:02:32.794587 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 06:02:32.801782 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 06:02:32.805716 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 06:02:32.808988 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 06:02:32.815710 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 06:02:32.822252 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 06:02:32.825506 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 06:02:32.833169 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 06:02:32.836809 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 06:02:32.844212 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 06:02:32.848235 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 06:02:32.854900 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 06:02:32.861575 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 06:02:32.865689 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 06:02:32.872556 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 06:02:32.876065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 06:02:32.882049 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 06:02:32.888956 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 06:02:32.892251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 06:02:32.898634 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 06:02:32.902258 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 06:02:32.909155 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 06:02:32.912396 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 06:02:32.919198 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 06:02:32.922673 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 06:02:32.929318 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 06:02:32.932275 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 06:02:32.939262 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 06:02:32.942671 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 06:02:32.949250 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 06:02:32.952825 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 06:02:32.955801 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 06:02:32.959218 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 06:02:32.966645 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 06:02:32.970050 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 06:02:32.973757 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 06:02:32.977141 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 06:02:32.983637 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 06:02:32.987080 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 06:02:32.990530 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 06:02:32.997094 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 06:02:33.000363 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 06:02:33.003598 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 06:02:33.010387 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 06:02:33.020059 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 06:02:33.023632 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 06:02:33.033633 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 06:02:33.040444 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 06:02:33.047063 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 06:02:33.050393 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 06:02:33.053179 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 06:02:33.061611 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x13
467 06:02:33.068155 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 06:02:33.071384 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 06:02:33.074588 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 06:02:33.086075 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 06:02:33.095150 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 06:02:33.104983 [RTC]rtc_get_frequency_meter,154: input=19, output=864
473 06:02:33.114444 [RTC]rtc_get_frequency_meter,154: input=17, output=817
474 06:02:33.124329 [RTC]rtc_get_frequency_meter,154: input=16, output=793
475 06:02:33.127492 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 06:02:33.133858 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 06:02:33.137039 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 06:02:33.140548 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 06:02:33.144283 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 06:02:33.148236 ADC[4]: Raw value=902507 ID=7
481 06:02:33.151462 ADC[3]: Raw value=213179 ID=1
482 06:02:33.151947 RAM Code: 0x71
483 06:02:33.155438 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 06:02:33.162855 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 06:02:33.170802 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 06:02:33.177460 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 06:02:33.180580 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 06:02:33.185083 in-header: 03 07 00 00 08 00 00 00
489 06:02:33.188398 in-data: aa e4 47 04 13 02 00 00
490 06:02:33.188878 Chrome EC: UHEPI supported
491 06:02:33.195877 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 06:02:33.199596 in-header: 03 ed 00 00 08 00 00 00
493 06:02:33.203231 in-data: 80 20 60 08 00 00 00 00
494 06:02:33.206410 MRC: failed to locate region type 0.
495 06:02:33.213144 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 06:02:33.216298 DRAM-K: Running full calibration
497 06:02:33.223023 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 06:02:33.223167 header.status = 0x0
499 06:02:33.226782 header.version = 0x6 (expected: 0x6)
500 06:02:33.229815 header.size = 0xd00 (expected: 0xd00)
501 06:02:33.233189 header.flags = 0x0
502 06:02:33.239565 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 06:02:33.255925 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
504 06:02:33.263227 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 06:02:33.266658 dram_init: ddr_geometry: 2
506 06:02:33.266746 [EMI] MDL number = 2
507 06:02:33.270943 [EMI] Get MDL freq = 0
508 06:02:33.271028 dram_init: ddr_type: 0
509 06:02:33.274521 is_discrete_lpddr4: 1
510 06:02:33.278532 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 06:02:33.278618
512 06:02:33.278685
513 06:02:33.278748 [Bian_co] ETT version 0.0.0.1
514 06:02:33.285861 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 06:02:33.285952
516 06:02:33.288999 dramc_set_vcore_voltage set vcore to 650000
517 06:02:33.289085 Read voltage for 800, 4
518 06:02:33.292324 Vio18 = 0
519 06:02:33.292411 Vcore = 650000
520 06:02:33.292493 Vdram = 0
521 06:02:33.295822 Vddq = 0
522 06:02:33.295908 Vmddr = 0
523 06:02:33.299434 dram_init: config_dvfs: 1
524 06:02:33.302623 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 06:02:33.309303 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 06:02:33.312607 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 06:02:33.315826 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 06:02:33.319122 [SwImpedanceCal] DRVP=16, DRVN=25, ODTN=9
529 06:02:33.322549 freq_region=1, Reg: DRVP=16, DRVN=25, ODTN=9
530 06:02:33.325867 MEM_TYPE=3, freq_sel=18
531 06:02:33.329294 sv_algorithm_assistance_LP4_1600
532 06:02:33.332330 ============ PULL DRAM RESETB DOWN ============
533 06:02:33.335707 ========== PULL DRAM RESETB DOWN end =========
534 06:02:33.342806 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 06:02:33.346245 ===================================
536 06:02:33.346363 LPDDR4 DRAM CONFIGURATION
537 06:02:33.349610 ===================================
538 06:02:33.352713 EX_ROW_EN[0] = 0x0
539 06:02:33.356429 EX_ROW_EN[1] = 0x0
540 06:02:33.356600 LP4Y_EN = 0x0
541 06:02:33.359689 WORK_FSP = 0x0
542 06:02:33.359860 WL = 0x2
543 06:02:33.362793 RL = 0x2
544 06:02:33.362961 BL = 0x2
545 06:02:33.366216 RPST = 0x0
546 06:02:33.366310 RD_PRE = 0x0
547 06:02:33.369400 WR_PRE = 0x1
548 06:02:33.369584 WR_PST = 0x0
549 06:02:33.372451 DBI_WR = 0x0
550 06:02:33.372576 DBI_RD = 0x0
551 06:02:33.375856 OTF = 0x1
552 06:02:33.379646 ===================================
553 06:02:33.382617 ===================================
554 06:02:33.382738 ANA top config
555 06:02:33.386510 ===================================
556 06:02:33.389674 DLL_ASYNC_EN = 0
557 06:02:33.392632 ALL_SLAVE_EN = 1
558 06:02:33.396406 NEW_RANK_MODE = 1
559 06:02:33.396668 DLL_IDLE_MODE = 1
560 06:02:33.399525 LP45_APHY_COMB_EN = 1
561 06:02:33.402740 TX_ODT_DIS = 1
562 06:02:33.406490 NEW_8X_MODE = 1
563 06:02:33.409738 ===================================
564 06:02:33.412936 ===================================
565 06:02:33.413390 data_rate = 1600
566 06:02:33.416375 CKR = 1
567 06:02:33.420023 DQ_P2S_RATIO = 8
568 06:02:33.423130 ===================================
569 06:02:33.426343 CA_P2S_RATIO = 8
570 06:02:33.430074 DQ_CA_OPEN = 0
571 06:02:33.432939 DQ_SEMI_OPEN = 0
572 06:02:33.433427 CA_SEMI_OPEN = 0
573 06:02:33.436512 CA_FULL_RATE = 0
574 06:02:33.439747 DQ_CKDIV4_EN = 1
575 06:02:33.442872 CA_CKDIV4_EN = 1
576 06:02:33.446238 CA_PREDIV_EN = 0
577 06:02:33.449875 PH8_DLY = 0
578 06:02:33.450635 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 06:02:33.453270 DQ_AAMCK_DIV = 4
580 06:02:33.456621 CA_AAMCK_DIV = 4
581 06:02:33.459856 CA_ADMCK_DIV = 4
582 06:02:33.462898 DQ_TRACK_CA_EN = 0
583 06:02:33.466732 CA_PICK = 800
584 06:02:33.467218 CA_MCKIO = 800
585 06:02:33.469668 MCKIO_SEMI = 0
586 06:02:33.472958 PLL_FREQ = 3068
587 06:02:33.476592 DQ_UI_PI_RATIO = 32
588 06:02:33.479856 CA_UI_PI_RATIO = 0
589 06:02:33.482763 ===================================
590 06:02:33.486416 ===================================
591 06:02:33.489878 memory_type:LPDDR4
592 06:02:33.490499 GP_NUM : 10
593 06:02:33.493035 SRAM_EN : 1
594 06:02:33.493618 MD32_EN : 0
595 06:02:33.496352 ===================================
596 06:02:33.500080 [ANA_INIT] >>>>>>>>>>>>>>
597 06:02:33.503380 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 06:02:33.507906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 06:02:33.511323 ===================================
600 06:02:33.511823 data_rate = 1600,PCW = 0X7600
601 06:02:33.515150 ===================================
602 06:02:33.518839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 06:02:33.525889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 06:02:33.529826 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 06:02:33.533571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 06:02:33.536770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 06:02:33.540506 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 06:02:33.543560 [ANA_INIT] flow start
609 06:02:33.547219 [ANA_INIT] PLL >>>>>>>>
610 06:02:33.547800 [ANA_INIT] PLL <<<<<<<<
611 06:02:33.550122 [ANA_INIT] MIDPI >>>>>>>>
612 06:02:33.553856 [ANA_INIT] MIDPI <<<<<<<<
613 06:02:33.554461 [ANA_INIT] DLL >>>>>>>>
614 06:02:33.557497 [ANA_INIT] flow end
615 06:02:33.560488 ============ LP4 DIFF to SE enter ============
616 06:02:33.567156 ============ LP4 DIFF to SE exit ============
617 06:02:33.567775 [ANA_INIT] <<<<<<<<<<<<<
618 06:02:33.570479 [Flow] Enable top DCM control >>>>>
619 06:02:33.573789 [Flow] Enable top DCM control <<<<<
620 06:02:33.577193 Enable DLL master slave shuffle
621 06:02:33.583679 ==============================================================
622 06:02:33.584185 Gating Mode config
623 06:02:33.590856 ==============================================================
624 06:02:33.591459 Config description:
625 06:02:33.600754 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 06:02:33.606915 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 06:02:33.614494 SELPH_MODE 0: By rank 1: By Phase
628 06:02:33.617012 ==============================================================
629 06:02:33.620393 GAT_TRACK_EN = 1
630 06:02:33.623718 RX_GATING_MODE = 2
631 06:02:33.627008 RX_GATING_TRACK_MODE = 2
632 06:02:33.631056 SELPH_MODE = 1
633 06:02:33.633793 PICG_EARLY_EN = 1
634 06:02:33.637131 VALID_LAT_VALUE = 1
635 06:02:33.643621 ==============================================================
636 06:02:33.647295 Enter into Gating configuration >>>>
637 06:02:33.650603 Exit from Gating configuration <<<<
638 06:02:33.651184 Enter into DVFS_PRE_config >>>>>
639 06:02:33.664133 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 06:02:33.667447 Exit from DVFS_PRE_config <<<<<
641 06:02:33.670855 Enter into PICG configuration >>>>
642 06:02:33.673978 Exit from PICG configuration <<<<
643 06:02:33.674463 [RX_INPUT] configuration >>>>>
644 06:02:33.677299 [RX_INPUT] configuration <<<<<
645 06:02:33.684103 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 06:02:33.687294 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 06:02:33.694194 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 06:02:33.701829 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 06:02:33.708866 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 06:02:33.713036 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 06:02:33.716515 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 06:02:33.720273 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 06:02:33.723641 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 06:02:33.730976 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 06:02:33.734568 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 06:02:33.738543 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 06:02:33.742245 ===================================
658 06:02:33.745923 LPDDR4 DRAM CONFIGURATION
659 06:02:33.746536 ===================================
660 06:02:33.749536 EX_ROW_EN[0] = 0x0
661 06:02:33.750068 EX_ROW_EN[1] = 0x0
662 06:02:33.753365 LP4Y_EN = 0x0
663 06:02:33.753983 WORK_FSP = 0x0
664 06:02:33.756949 WL = 0x2
665 06:02:33.757530 RL = 0x2
666 06:02:33.760554 BL = 0x2
667 06:02:33.761037 RPST = 0x0
668 06:02:33.764689 RD_PRE = 0x0
669 06:02:33.765273 WR_PRE = 0x1
670 06:02:33.768531 WR_PST = 0x0
671 06:02:33.769207 DBI_WR = 0x0
672 06:02:33.769602 DBI_RD = 0x0
673 06:02:33.772389 OTF = 0x1
674 06:02:33.777174 ===================================
675 06:02:33.780192 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 06:02:33.783508 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 06:02:33.787850 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 06:02:33.791450 ===================================
679 06:02:33.794666 LPDDR4 DRAM CONFIGURATION
680 06:02:33.798272 ===================================
681 06:02:33.798770 EX_ROW_EN[0] = 0x10
682 06:02:33.802371 EX_ROW_EN[1] = 0x0
683 06:02:33.802871 LP4Y_EN = 0x0
684 06:02:33.806155 WORK_FSP = 0x0
685 06:02:33.806762 WL = 0x2
686 06:02:33.807262 RL = 0x2
687 06:02:33.810021 BL = 0x2
688 06:02:33.810620 RPST = 0x0
689 06:02:33.813486 RD_PRE = 0x0
690 06:02:33.814119 WR_PRE = 0x1
691 06:02:33.817289 WR_PST = 0x0
692 06:02:33.817786 DBI_WR = 0x0
693 06:02:33.820813 DBI_RD = 0x0
694 06:02:33.821310 OTF = 0x1
695 06:02:33.825097 ===================================
696 06:02:33.831859 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 06:02:33.835545 nWR fixed to 40
698 06:02:33.836047 [ModeRegInit_LP4] CH0 RK0
699 06:02:33.839654 [ModeRegInit_LP4] CH0 RK1
700 06:02:33.843490 [ModeRegInit_LP4] CH1 RK0
701 06:02:33.844080 [ModeRegInit_LP4] CH1 RK1
702 06:02:33.847318 match AC timing 13
703 06:02:33.850569 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 06:02:33.854307 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 06:02:33.858447 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 06:02:33.865543 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 06:02:33.869085 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 06:02:33.869676 [EMI DOE] emi_dcm 0
709 06:02:33.873056 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 06:02:33.873643 ==
711 06:02:33.876218 Dram Type= 6, Freq= 0, CH_0, rank 0
712 06:02:33.880415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 06:02:33.883618 ==
714 06:02:33.887373 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 06:02:33.894548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 06:02:33.902240 [CA 0] Center 38 (7~69) winsize 63
717 06:02:33.905719 [CA 1] Center 38 (7~69) winsize 63
718 06:02:33.909212 [CA 2] Center 35 (5~66) winsize 62
719 06:02:33.912912 [CA 3] Center 35 (5~66) winsize 62
720 06:02:33.916684 [CA 4] Center 35 (4~66) winsize 63
721 06:02:33.920332 [CA 5] Center 34 (4~64) winsize 61
722 06:02:33.920855
723 06:02:33.924007 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 06:02:33.924583
725 06:02:33.928170 [CATrainingPosCal] consider 1 rank data
726 06:02:33.928895 u2DelayCellTimex100 = 270/100 ps
727 06:02:33.935397 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
728 06:02:33.939020 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
729 06:02:33.942754 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
730 06:02:33.943232 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
731 06:02:33.946475 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
732 06:02:33.950096 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
733 06:02:33.953526
734 06:02:33.957450 CA PerBit enable=1, Macro0, CA PI delay=34
735 06:02:33.958077
736 06:02:33.958463 [CBTSetCACLKResult] CA Dly = 34
737 06:02:33.961352 CS Dly: 6 (0~37)
738 06:02:33.961920 ==
739 06:02:33.964434 Dram Type= 6, Freq= 0, CH_0, rank 1
740 06:02:33.969057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 06:02:33.969639 ==
742 06:02:33.972476 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 06:02:33.979386 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 06:02:33.989356 [CA 0] Center 38 (7~69) winsize 63
745 06:02:33.993079 [CA 1] Center 38 (7~69) winsize 63
746 06:02:33.996590 [CA 2] Center 36 (6~67) winsize 62
747 06:02:34.000412 [CA 3] Center 35 (5~66) winsize 62
748 06:02:34.004048 [CA 4] Center 35 (4~66) winsize 63
749 06:02:34.004525 [CA 5] Center 34 (4~65) winsize 62
750 06:02:34.004901
751 06:02:34.010579 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 06:02:34.011063
753 06:02:34.014588 [CATrainingPosCal] consider 2 rank data
754 06:02:34.017779 u2DelayCellTimex100 = 270/100 ps
755 06:02:34.020735 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 06:02:34.024532 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
757 06:02:34.027427 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 06:02:34.031099 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 06:02:34.034671 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
760 06:02:34.037602 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 06:02:34.038210
762 06:02:34.041219 CA PerBit enable=1, Macro0, CA PI delay=34
763 06:02:34.041801
764 06:02:34.044238 [CBTSetCACLKResult] CA Dly = 34
765 06:02:34.047756 CS Dly: 6 (0~38)
766 06:02:34.048333
767 06:02:34.050856 ----->DramcWriteLeveling(PI) begin...
768 06:02:34.051348 ==
769 06:02:34.054560 Dram Type= 6, Freq= 0, CH_0, rank 0
770 06:02:34.057499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 06:02:34.058017 ==
772 06:02:34.061252 Write leveling (Byte 0): 31 => 31
773 06:02:34.064404 Write leveling (Byte 1): 31 => 31
774 06:02:34.067441 DramcWriteLeveling(PI) end<-----
775 06:02:34.068017
776 06:02:34.068392 ==
777 06:02:34.070994 Dram Type= 6, Freq= 0, CH_0, rank 0
778 06:02:34.074043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 06:02:34.074615 ==
780 06:02:34.077799 [Gating] SW mode calibration
781 06:02:34.084996 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 06:02:34.088794 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 06:02:34.096110 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
784 06:02:34.099600 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 06:02:34.103117 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 06:02:34.106465 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 06:02:34.112954 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 06:02:34.116639 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 06:02:34.119676 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 06:02:34.126424 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 06:02:34.129585 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 06:02:34.133391 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 06:02:34.140038 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 06:02:34.143183 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 06:02:34.146552 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 06:02:34.149894 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 06:02:34.157081 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 06:02:34.160225 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 06:02:34.163444 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 06:02:34.170283 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
801 06:02:34.173558 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 06:02:34.176552 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 06:02:34.183587 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 06:02:34.186878 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 06:02:34.190086 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 06:02:34.196737 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 06:02:34.200285 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 06:02:34.203353 0 9 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
809 06:02:34.210226 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
810 06:02:34.213223 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
811 06:02:34.216585 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 06:02:34.223372 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 06:02:34.226579 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 06:02:34.230170 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 06:02:34.233595 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 06:02:34.239886 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
817 06:02:34.243586 0 10 8 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
818 06:02:34.247124 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 06:02:34.253493 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 06:02:34.257242 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 06:02:34.260439 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 06:02:34.266958 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 06:02:34.270127 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 06:02:34.273786 0 11 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
825 06:02:34.280574 0 11 8 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
826 06:02:34.283749 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
827 06:02:34.286708 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 06:02:34.293709 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 06:02:34.296887 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 06:02:34.300118 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 06:02:34.307066 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
832 06:02:34.309985 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 06:02:34.313204 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 06:02:34.320274 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 06:02:34.323603 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 06:02:34.326820 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 06:02:34.329921 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 06:02:34.336822 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 06:02:34.340030 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 06:02:34.343642 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 06:02:34.350182 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 06:02:34.353379 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 06:02:34.357015 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 06:02:34.363531 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 06:02:34.366601 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 06:02:34.370080 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 06:02:34.376499 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
848 06:02:34.380251 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
849 06:02:34.383533 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
850 06:02:34.386734 Total UI for P1: 0, mck2ui 16
851 06:02:34.390453 best dqsien dly found for B0: ( 0, 14, 2)
852 06:02:34.396904 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 06:02:34.397497 Total UI for P1: 0, mck2ui 16
854 06:02:34.400358 best dqsien dly found for B1: ( 0, 14, 6)
855 06:02:34.407341 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
856 06:02:34.410172 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
857 06:02:34.410758
858 06:02:34.413446 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
859 06:02:34.416641 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
860 06:02:34.420500 [Gating] SW calibration Done
861 06:02:34.421087 ==
862 06:02:34.423873 Dram Type= 6, Freq= 0, CH_0, rank 0
863 06:02:34.426845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 06:02:34.427437 ==
865 06:02:34.427823 RX Vref Scan: 0
866 06:02:34.430144
867 06:02:34.430643 RX Vref 0 -> 0, step: 1
868 06:02:34.431029
869 06:02:34.433202 RX Delay -130 -> 252, step: 16
870 06:02:34.437029 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
871 06:02:34.440275 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
872 06:02:34.446826 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
873 06:02:34.450076 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
874 06:02:34.453442 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
875 06:02:34.457087 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 06:02:34.460606 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 06:02:34.467052 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 06:02:34.470167 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 06:02:34.473578 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
880 06:02:34.476848 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 06:02:34.480246 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 06:02:34.486975 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
883 06:02:34.490319 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 06:02:34.493292 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 06:02:34.496876 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
886 06:02:34.497359 ==
887 06:02:34.499915 Dram Type= 6, Freq= 0, CH_0, rank 0
888 06:02:34.506897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 06:02:34.507388 ==
890 06:02:34.507773 DQS Delay:
891 06:02:34.510441 DQS0 = 0, DQS1 = 0
892 06:02:34.511022 DQM Delay:
893 06:02:34.511409 DQM0 = 88, DQM1 = 78
894 06:02:34.513445 DQ Delay:
895 06:02:34.516983 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
896 06:02:34.520477 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
897 06:02:34.524074 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
898 06:02:34.526960 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =77
899 06:02:34.527539
900 06:02:34.527922
901 06:02:34.528277 ==
902 06:02:34.530520 Dram Type= 6, Freq= 0, CH_0, rank 0
903 06:02:34.533389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 06:02:34.533872 ==
905 06:02:34.534301
906 06:02:34.534655
907 06:02:34.536740 TX Vref Scan disable
908 06:02:34.537219 == TX Byte 0 ==
909 06:02:34.543579 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
910 06:02:34.546687 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
911 06:02:34.547167 == TX Byte 1 ==
912 06:02:34.553806 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 06:02:34.556795 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 06:02:34.557278 ==
915 06:02:34.560630 Dram Type= 6, Freq= 0, CH_0, rank 0
916 06:02:34.564068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 06:02:34.564655 ==
918 06:02:34.577494 TX Vref=22, minBit 11, minWin=26, winSum=440
919 06:02:34.580599 TX Vref=24, minBit 7, minWin=27, winSum=444
920 06:02:34.583988 TX Vref=26, minBit 9, minWin=27, winSum=451
921 06:02:34.587848 TX Vref=28, minBit 8, minWin=27, winSum=455
922 06:02:34.590851 TX Vref=30, minBit 8, minWin=27, winSum=454
923 06:02:34.594199 TX Vref=32, minBit 3, minWin=28, winSum=455
924 06:02:34.600803 [TxChooseVref] Worse bit 3, Min win 28, Win sum 455, Final Vref 32
925 06:02:34.601382
926 06:02:34.604206 Final TX Range 1 Vref 32
927 06:02:34.604797
928 06:02:34.605177 ==
929 06:02:34.607512 Dram Type= 6, Freq= 0, CH_0, rank 0
930 06:02:34.610511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 06:02:34.610992 ==
932 06:02:34.614033
933 06:02:34.614606
934 06:02:34.614986 TX Vref Scan disable
935 06:02:34.617617 == TX Byte 0 ==
936 06:02:34.620915 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
937 06:02:34.624315 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
938 06:02:34.627460 == TX Byte 1 ==
939 06:02:34.630523 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 06:02:34.633998 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 06:02:34.637300
942 06:02:34.637790 [DATLAT]
943 06:02:34.638249 Freq=800, CH0 RK0
944 06:02:34.638620
945 06:02:34.640979 DATLAT Default: 0xa
946 06:02:34.641583 0, 0xFFFF, sum = 0
947 06:02:34.644321 1, 0xFFFF, sum = 0
948 06:02:34.644935 2, 0xFFFF, sum = 0
949 06:02:34.647323 3, 0xFFFF, sum = 0
950 06:02:34.647827 4, 0xFFFF, sum = 0
951 06:02:34.650595 5, 0xFFFF, sum = 0
952 06:02:34.651090 6, 0xFFFF, sum = 0
953 06:02:34.654079 7, 0xFFFF, sum = 0
954 06:02:34.657514 8, 0xFFFF, sum = 0
955 06:02:34.658172 9, 0x0, sum = 1
956 06:02:34.658576 10, 0x0, sum = 2
957 06:02:34.661193 11, 0x0, sum = 3
958 06:02:34.661787 12, 0x0, sum = 4
959 06:02:34.664428 best_step = 10
960 06:02:34.665046
961 06:02:34.665433 ==
962 06:02:34.667426 Dram Type= 6, Freq= 0, CH_0, rank 0
963 06:02:34.670978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 06:02:34.671466 ==
965 06:02:34.673904 RX Vref Scan: 1
966 06:02:34.674424
967 06:02:34.674810 Set Vref Range= 32 -> 127
968 06:02:34.675166
969 06:02:34.677650 RX Vref 32 -> 127, step: 1
970 06:02:34.678170
971 06:02:34.681043 RX Delay -95 -> 252, step: 8
972 06:02:34.681649
973 06:02:34.684336 Set Vref, RX VrefLevel [Byte0]: 32
974 06:02:34.687499 [Byte1]: 32
975 06:02:34.687981
976 06:02:34.691108 Set Vref, RX VrefLevel [Byte0]: 33
977 06:02:34.694875 [Byte1]: 33
978 06:02:34.697908
979 06:02:34.698407 Set Vref, RX VrefLevel [Byte0]: 34
980 06:02:34.700921 [Byte1]: 34
981 06:02:34.705194
982 06:02:34.705772 Set Vref, RX VrefLevel [Byte0]: 35
983 06:02:34.708877 [Byte1]: 35
984 06:02:34.712555
985 06:02:34.713060 Set Vref, RX VrefLevel [Byte0]: 36
986 06:02:34.716325 [Byte1]: 36
987 06:02:34.720478
988 06:02:34.721076 Set Vref, RX VrefLevel [Byte0]: 37
989 06:02:34.724164 [Byte1]: 37
990 06:02:34.728213
991 06:02:34.728785 Set Vref, RX VrefLevel [Byte0]: 38
992 06:02:34.731427 [Byte1]: 38
993 06:02:34.735440
994 06:02:34.735910 Set Vref, RX VrefLevel [Byte0]: 39
995 06:02:34.738835 [Byte1]: 39
996 06:02:34.743343
997 06:02:34.743960 Set Vref, RX VrefLevel [Byte0]: 40
998 06:02:34.746867 [Byte1]: 40
999 06:02:34.751402
1000 06:02:34.751868 Set Vref, RX VrefLevel [Byte0]: 41
1001 06:02:34.754227 [Byte1]: 41
1002 06:02:34.758336
1003 06:02:34.761906 Set Vref, RX VrefLevel [Byte0]: 42
1004 06:02:34.762502 [Byte1]: 42
1005 06:02:34.766506
1006 06:02:34.766999 Set Vref, RX VrefLevel [Byte0]: 43
1007 06:02:34.769632 [Byte1]: 43
1008 06:02:34.774099
1009 06:02:34.774633 Set Vref, RX VrefLevel [Byte0]: 44
1010 06:02:34.777503 [Byte1]: 44
1011 06:02:34.781483
1012 06:02:34.781983 Set Vref, RX VrefLevel [Byte0]: 45
1013 06:02:34.784961 [Byte1]: 45
1014 06:02:34.788756
1015 06:02:34.789229 Set Vref, RX VrefLevel [Byte0]: 46
1016 06:02:34.791970 [Byte1]: 46
1017 06:02:34.796260
1018 06:02:34.796739 Set Vref, RX VrefLevel [Byte0]: 47
1019 06:02:34.800023 [Byte1]: 47
1020 06:02:34.804207
1021 06:02:34.804861 Set Vref, RX VrefLevel [Byte0]: 48
1022 06:02:34.807503 [Byte1]: 48
1023 06:02:34.811621
1024 06:02:34.812103 Set Vref, RX VrefLevel [Byte0]: 49
1025 06:02:34.815087 [Byte1]: 49
1026 06:02:34.819122
1027 06:02:34.819613 Set Vref, RX VrefLevel [Byte0]: 50
1028 06:02:34.822374 [Byte1]: 50
1029 06:02:34.826658
1030 06:02:34.827225 Set Vref, RX VrefLevel [Byte0]: 51
1031 06:02:34.830038 [Byte1]: 51
1032 06:02:34.834390
1033 06:02:34.834858 Set Vref, RX VrefLevel [Byte0]: 52
1034 06:02:34.837901 [Byte1]: 52
1035 06:02:34.842162
1036 06:02:34.842724 Set Vref, RX VrefLevel [Byte0]: 53
1037 06:02:34.845342 [Byte1]: 53
1038 06:02:34.849517
1039 06:02:34.850116 Set Vref, RX VrefLevel [Byte0]: 54
1040 06:02:34.853313 [Byte1]: 54
1041 06:02:34.857367
1042 06:02:34.857976 Set Vref, RX VrefLevel [Byte0]: 55
1043 06:02:34.860604 [Byte1]: 55
1044 06:02:34.864784
1045 06:02:34.865348 Set Vref, RX VrefLevel [Byte0]: 56
1046 06:02:34.867983 [Byte1]: 56
1047 06:02:34.872309
1048 06:02:34.872882 Set Vref, RX VrefLevel [Byte0]: 57
1049 06:02:34.875702 [Byte1]: 57
1050 06:02:34.879961
1051 06:02:34.880432 Set Vref, RX VrefLevel [Byte0]: 58
1052 06:02:34.883449 [Byte1]: 58
1053 06:02:34.887428
1054 06:02:34.887896 Set Vref, RX VrefLevel [Byte0]: 59
1055 06:02:34.890851 [Byte1]: 59
1056 06:02:34.895526
1057 06:02:34.896012 Set Vref, RX VrefLevel [Byte0]: 60
1058 06:02:34.898730 [Byte1]: 60
1059 06:02:34.902987
1060 06:02:34.903454 Set Vref, RX VrefLevel [Byte0]: 61
1061 06:02:34.906313 [Byte1]: 61
1062 06:02:34.910431
1063 06:02:34.911025 Set Vref, RX VrefLevel [Byte0]: 62
1064 06:02:34.913873 [Byte1]: 62
1065 06:02:34.918491
1066 06:02:34.918958 Set Vref, RX VrefLevel [Byte0]: 63
1067 06:02:34.921245 [Byte1]: 63
1068 06:02:34.925714
1069 06:02:34.926336 Set Vref, RX VrefLevel [Byte0]: 64
1070 06:02:34.929189 [Byte1]: 64
1071 06:02:34.933311
1072 06:02:34.933811 Set Vref, RX VrefLevel [Byte0]: 65
1073 06:02:34.936843 [Byte1]: 65
1074 06:02:34.940963
1075 06:02:34.941439 Set Vref, RX VrefLevel [Byte0]: 66
1076 06:02:34.944489 [Byte1]: 66
1077 06:02:34.948624
1078 06:02:34.949109 Set Vref, RX VrefLevel [Byte0]: 67
1079 06:02:34.951612 [Byte1]: 67
1080 06:02:34.956087
1081 06:02:34.956667 Set Vref, RX VrefLevel [Byte0]: 68
1082 06:02:34.959614 [Byte1]: 68
1083 06:02:34.963513
1084 06:02:34.964000 Set Vref, RX VrefLevel [Byte0]: 69
1085 06:02:34.966960 [Byte1]: 69
1086 06:02:34.971173
1087 06:02:34.971753 Set Vref, RX VrefLevel [Byte0]: 70
1088 06:02:34.974535 [Byte1]: 70
1089 06:02:34.978836
1090 06:02:34.979438 Set Vref, RX VrefLevel [Byte0]: 71
1091 06:02:34.982069 [Byte1]: 71
1092 06:02:34.986616
1093 06:02:34.987213 Set Vref, RX VrefLevel [Byte0]: 72
1094 06:02:34.989524 [Byte1]: 72
1095 06:02:34.993864
1096 06:02:34.994530 Set Vref, RX VrefLevel [Byte0]: 73
1097 06:02:34.997554 [Byte1]: 73
1098 06:02:35.001584
1099 06:02:35.002202 Set Vref, RX VrefLevel [Byte0]: 74
1100 06:02:35.004765 [Byte1]: 74
1101 06:02:35.009394
1102 06:02:35.010018 Set Vref, RX VrefLevel [Byte0]: 75
1103 06:02:35.012404 [Byte1]: 75
1104 06:02:35.016487
1105 06:02:35.016974 Set Vref, RX VrefLevel [Byte0]: 76
1106 06:02:35.020168 [Byte1]: 76
1107 06:02:35.024437
1108 06:02:35.024923 Set Vref, RX VrefLevel [Byte0]: 77
1109 06:02:35.027600 [Byte1]: 77
1110 06:02:35.031937
1111 06:02:35.032424 Set Vref, RX VrefLevel [Byte0]: 78
1112 06:02:35.035239 [Byte1]: 78
1113 06:02:35.039473
1114 06:02:35.039954 Final RX Vref Byte 0 = 63 to rank0
1115 06:02:35.042729 Final RX Vref Byte 1 = 60 to rank0
1116 06:02:35.046401 Final RX Vref Byte 0 = 63 to rank1
1117 06:02:35.049403 Final RX Vref Byte 1 = 60 to rank1==
1118 06:02:35.053024 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 06:02:35.059662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 06:02:35.060250 ==
1121 06:02:35.060744 DQS Delay:
1122 06:02:35.061197 DQS0 = 0, DQS1 = 0
1123 06:02:35.062649 DQM Delay:
1124 06:02:35.063136 DQM0 = 93, DQM1 = 82
1125 06:02:35.066519 DQ Delay:
1126 06:02:35.069889 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1127 06:02:35.072885 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1128 06:02:35.076346 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1129 06:02:35.080003 DQ12 =88, DQ13 =80, DQ14 =92, DQ15 =92
1130 06:02:35.080644
1131 06:02:35.081138
1132 06:02:35.086068 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1133 06:02:35.090102 CH0 RK0: MR19=606, MR18=3E39
1134 06:02:35.096416 CH0_RK0: MR19=0x606, MR18=0x3E39, DQSOSC=394, MR23=63, INC=95, DEC=63
1135 06:02:35.096990
1136 06:02:35.099845 ----->DramcWriteLeveling(PI) begin...
1137 06:02:35.100376 ==
1138 06:02:35.103056 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 06:02:35.106287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 06:02:35.106779 ==
1141 06:02:35.109361 Write leveling (Byte 0): 32 => 32
1142 06:02:35.113126 Write leveling (Byte 1): 30 => 30
1143 06:02:35.116024 DramcWriteLeveling(PI) end<-----
1144 06:02:35.116496
1145 06:02:35.116867 ==
1146 06:02:35.119582 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 06:02:35.123061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 06:02:35.123536 ==
1149 06:02:35.126416 [Gating] SW mode calibration
1150 06:02:35.132906 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 06:02:35.139548 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 06:02:35.143253 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 06:02:35.146379 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1154 06:02:35.193814 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 06:02:35.194454 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 06:02:35.195219 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 06:02:35.195605 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 06:02:35.195955 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 06:02:35.196306 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 06:02:35.196633 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 06:02:35.196951 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 06:02:35.197330 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 06:02:35.197664 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 06:02:35.237609 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 06:02:35.238301 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 06:02:35.239091 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 06:02:35.239510 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 06:02:35.239868 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 06:02:35.240271 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1170 06:02:35.240804 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 06:02:35.241155 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 06:02:35.241480 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 06:02:35.241796 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 06:02:35.265239 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 06:02:35.265813 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 06:02:35.266270 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 06:02:35.266964 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 06:02:35.267333 0 9 8 | B1->B0 | 2d2d 3333 | 0 1 | (0 0) (1 1)
1179 06:02:35.267673 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 06:02:35.267996 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 06:02:35.269132 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 06:02:35.275908 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 06:02:35.279477 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 06:02:35.282752 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 06:02:35.289426 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
1186 06:02:35.292621 0 10 8 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
1187 06:02:35.295918 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 06:02:35.302754 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 06:02:35.305860 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 06:02:35.309757 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 06:02:35.315900 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 06:02:35.318840 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 06:02:35.322745 0 11 4 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
1194 06:02:35.329186 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1195 06:02:35.333170 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 06:02:35.336676 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 06:02:35.340464 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 06:02:35.343988 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 06:02:35.351017 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 06:02:35.354310 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 06:02:35.358026 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 06:02:35.361692 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 06:02:35.368519 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 06:02:35.371764 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 06:02:35.375335 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 06:02:35.381823 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 06:02:35.385182 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 06:02:35.388855 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 06:02:35.391834 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 06:02:35.398676 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 06:02:35.402126 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 06:02:35.405616 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 06:02:35.412104 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 06:02:35.415720 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 06:02:35.418531 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 06:02:35.425414 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 06:02:35.428807 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1218 06:02:35.432258 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1219 06:02:35.435397 Total UI for P1: 0, mck2ui 16
1220 06:02:35.438852 best dqsien dly found for B0: ( 0, 14, 4)
1221 06:02:35.445420 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 06:02:35.445896 Total UI for P1: 0, mck2ui 16
1223 06:02:35.448648 best dqsien dly found for B1: ( 0, 14, 6)
1224 06:02:35.455596 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1225 06:02:35.458619 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1226 06:02:35.459097
1227 06:02:35.462335 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1228 06:02:35.465983 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1229 06:02:35.468946 [Gating] SW calibration Done
1230 06:02:35.469422 ==
1231 06:02:35.472656 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 06:02:35.475949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 06:02:35.476539 ==
1234 06:02:35.476921 RX Vref Scan: 0
1235 06:02:35.477276
1236 06:02:35.479338 RX Vref 0 -> 0, step: 1
1237 06:02:35.479932
1238 06:02:35.482359 RX Delay -130 -> 252, step: 16
1239 06:02:35.486233 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1240 06:02:35.489006 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1241 06:02:35.495781 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1242 06:02:35.498936 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1243 06:02:35.502379 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1244 06:02:35.505763 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1245 06:02:35.509272 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1246 06:02:35.512554 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1247 06:02:35.519140 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1248 06:02:35.522904 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1249 06:02:35.526070 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1250 06:02:35.528973 iDelay=206, Bit 11, Center 85 (-18 ~ 189) 208
1251 06:02:35.532517 iDelay=206, Bit 12, Center 85 (-18 ~ 189) 208
1252 06:02:35.539230 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1253 06:02:35.542529 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1254 06:02:35.546109 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1255 06:02:35.546577 ==
1256 06:02:35.549600 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 06:02:35.552390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 06:02:35.556327 ==
1259 06:02:35.556938 DQS Delay:
1260 06:02:35.557523 DQS0 = 0, DQS1 = 0
1261 06:02:35.559384 DQM Delay:
1262 06:02:35.559879 DQM0 = 90, DQM1 = 83
1263 06:02:35.560251 DQ Delay:
1264 06:02:35.562521 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1265 06:02:35.566214 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1266 06:02:35.569354 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =85
1267 06:02:35.573120 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =93
1268 06:02:35.573746
1269 06:02:35.574166
1270 06:02:35.576221 ==
1271 06:02:35.576792 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 06:02:35.582953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 06:02:35.583523 ==
1274 06:02:35.583897
1275 06:02:35.584240
1276 06:02:35.586169 TX Vref Scan disable
1277 06:02:35.586708 == TX Byte 0 ==
1278 06:02:35.589686 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1279 06:02:35.596263 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1280 06:02:35.597025 == TX Byte 1 ==
1281 06:02:35.599486 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1282 06:02:35.606027 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1283 06:02:35.606747 ==
1284 06:02:35.609823 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 06:02:35.612842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 06:02:35.613475 ==
1287 06:02:35.626047 TX Vref=22, minBit 3, minWin=27, winSum=446
1288 06:02:35.629394 TX Vref=24, minBit 8, minWin=27, winSum=450
1289 06:02:35.633246 TX Vref=26, minBit 8, minWin=27, winSum=452
1290 06:02:35.636046 TX Vref=28, minBit 8, minWin=27, winSum=454
1291 06:02:35.639725 TX Vref=30, minBit 8, minWin=27, winSum=456
1292 06:02:35.642680 TX Vref=32, minBit 8, minWin=28, winSum=458
1293 06:02:35.649470 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
1294 06:02:35.649970
1295 06:02:35.652897 Final TX Range 1 Vref 32
1296 06:02:35.653366
1297 06:02:35.653729 ==
1298 06:02:35.655907 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 06:02:35.659473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 06:02:35.659942 ==
1301 06:02:35.660309
1302 06:02:35.662664
1303 06:02:35.663127 TX Vref Scan disable
1304 06:02:35.665901 == TX Byte 0 ==
1305 06:02:35.669222 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1306 06:02:35.672549 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1307 06:02:35.676086 == TX Byte 1 ==
1308 06:02:35.679585 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1309 06:02:35.682768 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1310 06:02:35.686073
1311 06:02:35.686502 [DATLAT]
1312 06:02:35.686861 Freq=800, CH0 RK1
1313 06:02:35.687116
1314 06:02:35.689380 DATLAT Default: 0xa
1315 06:02:35.689815 0, 0xFFFF, sum = 0
1316 06:02:35.692709 1, 0xFFFF, sum = 0
1317 06:02:35.693153 2, 0xFFFF, sum = 0
1318 06:02:35.696096 3, 0xFFFF, sum = 0
1319 06:02:35.696540 4, 0xFFFF, sum = 0
1320 06:02:35.699174 5, 0xFFFF, sum = 0
1321 06:02:35.699507 6, 0xFFFF, sum = 0
1322 06:02:35.702621 7, 0xFFFF, sum = 0
1323 06:02:35.706028 8, 0xFFFF, sum = 0
1324 06:02:35.706370 9, 0x0, sum = 1
1325 06:02:35.706635 10, 0x0, sum = 2
1326 06:02:35.709576 11, 0x0, sum = 3
1327 06:02:35.710056 12, 0x0, sum = 4
1328 06:02:35.712922 best_step = 10
1329 06:02:35.713485
1330 06:02:35.713858 ==
1331 06:02:35.716243 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 06:02:35.719150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 06:02:35.719479 ==
1334 06:02:35.722756 RX Vref Scan: 0
1335 06:02:35.723099
1336 06:02:35.723379 RX Vref 0 -> 0, step: 1
1337 06:02:35.723634
1338 06:02:35.725922 RX Delay -95 -> 252, step: 8
1339 06:02:35.732713 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1340 06:02:35.736173 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1341 06:02:35.739336 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1342 06:02:35.742321 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1343 06:02:35.746049 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1344 06:02:35.752687 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1345 06:02:35.755973 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1346 06:02:35.759585 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1347 06:02:35.762922 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1348 06:02:35.766282 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1349 06:02:35.772808 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1350 06:02:35.776356 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1351 06:02:35.779675 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1352 06:02:35.783027 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1353 06:02:35.786612 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1354 06:02:35.792951 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1355 06:02:35.793505 ==
1356 06:02:35.796544 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 06:02:35.799938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 06:02:35.800397 ==
1359 06:02:35.800757 DQS Delay:
1360 06:02:35.802866 DQS0 = 0, DQS1 = 0
1361 06:02:35.803374 DQM Delay:
1362 06:02:35.806271 DQM0 = 90, DQM1 = 83
1363 06:02:35.806842 DQ Delay:
1364 06:02:35.809811 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1365 06:02:35.813226 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1366 06:02:35.816411 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1367 06:02:35.819680 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1368 06:02:35.820136
1369 06:02:35.820492
1370 06:02:35.825998 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
1371 06:02:35.829624 CH0 RK1: MR19=606, MR18=3B16
1372 06:02:35.836527 CH0_RK1: MR19=0x606, MR18=0x3B16, DQSOSC=394, MR23=63, INC=95, DEC=63
1373 06:02:35.839393 [RxdqsGatingPostProcess] freq 800
1374 06:02:35.846354 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 06:02:35.849394 Pre-setting of DQS Precalculation
1376 06:02:35.853030 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 06:02:35.853602 ==
1378 06:02:35.856285 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 06:02:35.859866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 06:02:35.860416 ==
1381 06:02:35.866561 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 06:02:35.873110 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 06:02:35.881302 [CA 0] Center 36 (6~67) winsize 62
1384 06:02:35.884456 [CA 1] Center 37 (6~68) winsize 63
1385 06:02:35.888031 [CA 2] Center 35 (5~65) winsize 61
1386 06:02:35.891190 [CA 3] Center 34 (4~65) winsize 62
1387 06:02:35.894902 [CA 4] Center 34 (4~65) winsize 62
1388 06:02:35.897866 [CA 5] Center 34 (3~65) winsize 63
1389 06:02:35.898350
1390 06:02:35.901262 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1391 06:02:35.901718
1392 06:02:35.904932 [CATrainingPosCal] consider 1 rank data
1393 06:02:35.907742 u2DelayCellTimex100 = 270/100 ps
1394 06:02:35.911389 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 06:02:35.914649 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1396 06:02:35.921511 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1397 06:02:35.924686 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 06:02:35.928135 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 06:02:35.931102 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1400 06:02:35.931563
1401 06:02:35.934542 CA PerBit enable=1, Macro0, CA PI delay=34
1402 06:02:35.935000
1403 06:02:35.937580 [CBTSetCACLKResult] CA Dly = 34
1404 06:02:35.938297 CS Dly: 5 (0~36)
1405 06:02:35.938720 ==
1406 06:02:35.940858 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 06:02:35.947776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 06:02:35.948265 ==
1409 06:02:35.951143 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 06:02:35.957760 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 06:02:35.967532 [CA 0] Center 37 (7~68) winsize 62
1412 06:02:35.970458 [CA 1] Center 37 (6~68) winsize 63
1413 06:02:35.974160 [CA 2] Center 35 (5~66) winsize 62
1414 06:02:35.977378 [CA 3] Center 34 (4~65) winsize 62
1415 06:02:35.980736 [CA 4] Center 35 (5~65) winsize 61
1416 06:02:35.983698 [CA 5] Center 34 (4~64) winsize 61
1417 06:02:35.984175
1418 06:02:35.987526 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 06:02:35.988000
1420 06:02:35.990588 [CATrainingPosCal] consider 2 rank data
1421 06:02:35.994085 u2DelayCellTimex100 = 270/100 ps
1422 06:02:35.997067 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1423 06:02:36.000966 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1424 06:02:36.004486 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1425 06:02:36.008463 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 06:02:36.012224 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 06:02:36.016131 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 06:02:36.016607
1429 06:02:36.019925 CA PerBit enable=1, Macro0, CA PI delay=34
1430 06:02:36.020410
1431 06:02:36.023723 [CBTSetCACLKResult] CA Dly = 34
1432 06:02:36.027180 CS Dly: 5 (0~37)
1433 06:02:36.027773
1434 06:02:36.030862 ----->DramcWriteLeveling(PI) begin...
1435 06:02:36.031343 ==
1436 06:02:36.033889 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 06:02:36.037499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 06:02:36.037975 ==
1439 06:02:36.040951 Write leveling (Byte 0): 27 => 27
1440 06:02:36.044037 Write leveling (Byte 1): 29 => 29
1441 06:02:36.044471 DramcWriteLeveling(PI) end<-----
1442 06:02:36.047809
1443 06:02:36.048349 ==
1444 06:02:36.050754 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 06:02:36.054318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 06:02:36.054797 ==
1447 06:02:36.057264 [Gating] SW mode calibration
1448 06:02:36.064594 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 06:02:36.067522 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 06:02:36.074465 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1451 06:02:36.078029 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 06:02:36.080808 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 06:02:36.087833 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 06:02:36.090859 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 06:02:36.094591 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 06:02:36.100884 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 06:02:36.104382 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 06:02:36.107889 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 06:02:36.114250 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 06:02:36.117448 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 06:02:36.121378 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 06:02:36.124122 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 06:02:36.130911 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 06:02:36.134615 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 06:02:36.137694 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 06:02:36.144503 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 06:02:36.147906 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1468 06:02:36.151157 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 06:02:36.157718 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 06:02:36.160944 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 06:02:36.164761 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 06:02:36.171208 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 06:02:36.174291 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 06:02:36.177608 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 06:02:36.184610 0 9 4 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
1476 06:02:36.187506 0 9 8 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
1477 06:02:36.190762 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 06:02:36.197741 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 06:02:36.201211 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 06:02:36.204794 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 06:02:36.211100 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 06:02:36.214276 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1483 06:02:36.217650 0 10 4 | B1->B0 | 3131 2e2e | 1 1 | (1 0) (0 0)
1484 06:02:36.220965 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1485 06:02:36.227972 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 06:02:36.231189 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 06:02:36.234767 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 06:02:36.240808 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 06:02:36.244351 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 06:02:36.248207 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1491 06:02:36.254550 0 11 4 | B1->B0 | 3030 3636 | 1 0 | (0 0) (0 0)
1492 06:02:36.257698 0 11 8 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
1493 06:02:36.261412 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 06:02:36.267519 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 06:02:36.271144 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 06:02:36.274555 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 06:02:36.281086 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 06:02:36.284787 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 06:02:36.287632 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 06:02:36.294590 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 06:02:36.297935 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 06:02:36.300951 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 06:02:36.304568 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 06:02:36.311366 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 06:02:36.314476 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 06:02:36.317867 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 06:02:36.324373 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 06:02:36.327963 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 06:02:36.330982 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 06:02:36.337712 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 06:02:36.341102 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 06:02:36.344528 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 06:02:36.351061 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 06:02:36.354343 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 06:02:36.357453 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 06:02:36.364535 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1517 06:02:36.365258 Total UI for P1: 0, mck2ui 16
1518 06:02:36.371062 best dqsien dly found for B0: ( 0, 14, 4)
1519 06:02:36.374599 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 06:02:36.377732 Total UI for P1: 0, mck2ui 16
1521 06:02:36.381023 best dqsien dly found for B1: ( 0, 14, 6)
1522 06:02:36.384220 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1523 06:02:36.387749 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1524 06:02:36.388258
1525 06:02:36.391205 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 06:02:36.394486 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1527 06:02:36.398017 [Gating] SW calibration Done
1528 06:02:36.398602 ==
1529 06:02:36.401238 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 06:02:36.404466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 06:02:36.405182 ==
1532 06:02:36.407886 RX Vref Scan: 0
1533 06:02:36.408352
1534 06:02:36.411071 RX Vref 0 -> 0, step: 1
1535 06:02:36.411745
1536 06:02:36.412347 RX Delay -130 -> 252, step: 16
1537 06:02:36.417780 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1538 06:02:36.421155 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1539 06:02:36.424150 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1540 06:02:36.427607 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1541 06:02:36.431108 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1542 06:02:36.437779 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1543 06:02:36.440746 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1544 06:02:36.443975 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1545 06:02:36.447495 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1546 06:02:36.450729 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1547 06:02:36.457806 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1548 06:02:36.461081 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1549 06:02:36.464584 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1550 06:02:36.467745 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1551 06:02:36.470813 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1552 06:02:36.477676 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1553 06:02:36.478295 ==
1554 06:02:36.480600 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 06:02:36.484275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 06:02:36.484809 ==
1557 06:02:36.485188 DQS Delay:
1558 06:02:36.487636 DQS0 = 0, DQS1 = 0
1559 06:02:36.488207 DQM Delay:
1560 06:02:36.491021 DQM0 = 92, DQM1 = 80
1561 06:02:36.491490 DQ Delay:
1562 06:02:36.494374 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1563 06:02:36.497829 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =93
1564 06:02:36.501162 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1565 06:02:36.504405 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1566 06:02:36.504978
1567 06:02:36.505355
1568 06:02:36.505700 ==
1569 06:02:36.507423 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 06:02:36.510605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 06:02:36.514202 ==
1572 06:02:36.514774
1573 06:02:36.515147
1574 06:02:36.515491 TX Vref Scan disable
1575 06:02:36.517545 == TX Byte 0 ==
1576 06:02:36.521084 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1577 06:02:36.524549 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1578 06:02:36.527903 == TX Byte 1 ==
1579 06:02:36.531225 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1580 06:02:36.534028 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1581 06:02:36.534503 ==
1582 06:02:36.537477 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 06:02:36.543826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 06:02:36.544310 ==
1585 06:02:36.556275 TX Vref=22, minBit 8, minWin=27, winSum=448
1586 06:02:36.559775 TX Vref=24, minBit 8, minWin=27, winSum=451
1587 06:02:36.563210 TX Vref=26, minBit 10, minWin=27, winSum=453
1588 06:02:36.566457 TX Vref=28, minBit 10, minWin=27, winSum=454
1589 06:02:36.569638 TX Vref=30, minBit 8, minWin=27, winSum=457
1590 06:02:36.572722 TX Vref=32, minBit 8, minWin=27, winSum=454
1591 06:02:36.579786 [TxChooseVref] Worse bit 8, Min win 27, Win sum 457, Final Vref 30
1592 06:02:36.580341
1593 06:02:36.583901 Final TX Range 1 Vref 30
1594 06:02:36.584377
1595 06:02:36.584754 ==
1596 06:02:36.587240 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 06:02:36.590450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 06:02:36.591149 ==
1599 06:02:36.591569
1600 06:02:36.591940
1601 06:02:36.594323 TX Vref Scan disable
1602 06:02:36.597559 == TX Byte 0 ==
1603 06:02:36.600688 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1604 06:02:36.604485 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1605 06:02:36.607746 == TX Byte 1 ==
1606 06:02:36.610776 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1607 06:02:36.614138 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1608 06:02:36.614708
1609 06:02:36.615081 [DATLAT]
1610 06:02:36.617649 Freq=800, CH1 RK0
1611 06:02:36.618258
1612 06:02:36.620503 DATLAT Default: 0xa
1613 06:02:36.620997 0, 0xFFFF, sum = 0
1614 06:02:36.624112 1, 0xFFFF, sum = 0
1615 06:02:36.624596 2, 0xFFFF, sum = 0
1616 06:02:36.627741 3, 0xFFFF, sum = 0
1617 06:02:36.628319 4, 0xFFFF, sum = 0
1618 06:02:36.630667 5, 0xFFFF, sum = 0
1619 06:02:36.631193 6, 0xFFFF, sum = 0
1620 06:02:36.634115 7, 0xFFFF, sum = 0
1621 06:02:36.634683 8, 0xFFFF, sum = 0
1622 06:02:36.637809 9, 0x0, sum = 1
1623 06:02:36.638419 10, 0x0, sum = 2
1624 06:02:36.640940 11, 0x0, sum = 3
1625 06:02:36.641540 12, 0x0, sum = 4
1626 06:02:36.641964 best_step = 10
1627 06:02:36.642353
1628 06:02:36.644019 ==
1629 06:02:36.647722 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 06:02:36.650813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 06:02:36.651294 ==
1632 06:02:36.651669 RX Vref Scan: 1
1633 06:02:36.652021
1634 06:02:36.653995 Set Vref Range= 32 -> 127
1635 06:02:36.654476
1636 06:02:36.657467 RX Vref 32 -> 127, step: 1
1637 06:02:36.657969
1638 06:02:36.660959 RX Delay -95 -> 252, step: 8
1639 06:02:36.661560
1640 06:02:36.663975 Set Vref, RX VrefLevel [Byte0]: 32
1641 06:02:36.667627 [Byte1]: 32
1642 06:02:36.668104
1643 06:02:36.670644 Set Vref, RX VrefLevel [Byte0]: 33
1644 06:02:36.674146 [Byte1]: 33
1645 06:02:36.674619
1646 06:02:36.677970 Set Vref, RX VrefLevel [Byte0]: 34
1647 06:02:36.681162 [Byte1]: 34
1648 06:02:36.684471
1649 06:02:36.685117 Set Vref, RX VrefLevel [Byte0]: 35
1650 06:02:36.687387 [Byte1]: 35
1651 06:02:36.691693
1652 06:02:36.692164 Set Vref, RX VrefLevel [Byte0]: 36
1653 06:02:36.695354 [Byte1]: 36
1654 06:02:36.699163
1655 06:02:36.699639 Set Vref, RX VrefLevel [Byte0]: 37
1656 06:02:36.702397 [Byte1]: 37
1657 06:02:36.707009
1658 06:02:36.707596 Set Vref, RX VrefLevel [Byte0]: 38
1659 06:02:36.710477 [Byte1]: 38
1660 06:02:36.714408
1661 06:02:36.715009 Set Vref, RX VrefLevel [Byte0]: 39
1662 06:02:36.717502 [Byte1]: 39
1663 06:02:36.722296
1664 06:02:36.722762 Set Vref, RX VrefLevel [Byte0]: 40
1665 06:02:36.725420 [Byte1]: 40
1666 06:02:36.729508
1667 06:02:36.729993 Set Vref, RX VrefLevel [Byte0]: 41
1668 06:02:36.732953 [Byte1]: 41
1669 06:02:36.737683
1670 06:02:36.738298 Set Vref, RX VrefLevel [Byte0]: 42
1671 06:02:36.740728 [Byte1]: 42
1672 06:02:36.745006
1673 06:02:36.745574 Set Vref, RX VrefLevel [Byte0]: 43
1674 06:02:36.748354 [Byte1]: 43
1675 06:02:36.752686
1676 06:02:36.753254 Set Vref, RX VrefLevel [Byte0]: 44
1677 06:02:36.755858 [Byte1]: 44
1678 06:02:36.759845
1679 06:02:36.760356 Set Vref, RX VrefLevel [Byte0]: 45
1680 06:02:36.763302 [Byte1]: 45
1681 06:02:36.767478
1682 06:02:36.767947 Set Vref, RX VrefLevel [Byte0]: 46
1683 06:02:36.770897 [Byte1]: 46
1684 06:02:36.775354
1685 06:02:36.775922 Set Vref, RX VrefLevel [Byte0]: 47
1686 06:02:36.778709 [Byte1]: 47
1687 06:02:36.783103
1688 06:02:36.783664 Set Vref, RX VrefLevel [Byte0]: 48
1689 06:02:36.786450 [Byte1]: 48
1690 06:02:36.790589
1691 06:02:36.791059 Set Vref, RX VrefLevel [Byte0]: 49
1692 06:02:36.794177 [Byte1]: 49
1693 06:02:36.798221
1694 06:02:36.798788 Set Vref, RX VrefLevel [Byte0]: 50
1695 06:02:36.801536 [Byte1]: 50
1696 06:02:36.805661
1697 06:02:36.806278 Set Vref, RX VrefLevel [Byte0]: 51
1698 06:02:36.809446 [Byte1]: 51
1699 06:02:36.813381
1700 06:02:36.813848 Set Vref, RX VrefLevel [Byte0]: 52
1701 06:02:36.816498 [Byte1]: 52
1702 06:02:36.820797
1703 06:02:36.821266 Set Vref, RX VrefLevel [Byte0]: 53
1704 06:02:36.824413 [Byte1]: 53
1705 06:02:36.828292
1706 06:02:36.828763 Set Vref, RX VrefLevel [Byte0]: 54
1707 06:02:36.831689 [Byte1]: 54
1708 06:02:36.836018
1709 06:02:36.836523 Set Vref, RX VrefLevel [Byte0]: 55
1710 06:02:36.839493 [Byte1]: 55
1711 06:02:36.843635
1712 06:02:36.844103 Set Vref, RX VrefLevel [Byte0]: 56
1713 06:02:36.847043 [Byte1]: 56
1714 06:02:36.851290
1715 06:02:36.851760 Set Vref, RX VrefLevel [Byte0]: 57
1716 06:02:36.854629 [Byte1]: 57
1717 06:02:36.859067
1718 06:02:36.859492 Set Vref, RX VrefLevel [Byte0]: 58
1719 06:02:36.862376 [Byte1]: 58
1720 06:02:36.866860
1721 06:02:36.867342 Set Vref, RX VrefLevel [Byte0]: 59
1722 06:02:36.869811 [Byte1]: 59
1723 06:02:36.873888
1724 06:02:36.874220 Set Vref, RX VrefLevel [Byte0]: 60
1725 06:02:36.877094 [Byte1]: 60
1726 06:02:36.881367
1727 06:02:36.881594 Set Vref, RX VrefLevel [Byte0]: 61
1728 06:02:36.884663 [Byte1]: 61
1729 06:02:36.888799
1730 06:02:36.888982 Set Vref, RX VrefLevel [Byte0]: 62
1731 06:02:36.892417 [Byte1]: 62
1732 06:02:36.896654
1733 06:02:36.896787 Set Vref, RX VrefLevel [Byte0]: 63
1734 06:02:36.899706 [Byte1]: 63
1735 06:02:36.904293
1736 06:02:36.904425 Set Vref, RX VrefLevel [Byte0]: 64
1737 06:02:36.907801 [Byte1]: 64
1738 06:02:36.912166
1739 06:02:36.912589 Set Vref, RX VrefLevel [Byte0]: 65
1740 06:02:36.915249 [Byte1]: 65
1741 06:02:36.919355
1742 06:02:36.919657 Set Vref, RX VrefLevel [Byte0]: 66
1743 06:02:36.922807 [Byte1]: 66
1744 06:02:36.926930
1745 06:02:36.927159 Set Vref, RX VrefLevel [Byte0]: 67
1746 06:02:36.930339 [Byte1]: 67
1747 06:02:36.934592
1748 06:02:36.934821 Set Vref, RX VrefLevel [Byte0]: 68
1749 06:02:36.937895 [Byte1]: 68
1750 06:02:36.942338
1751 06:02:36.942571 Set Vref, RX VrefLevel [Byte0]: 69
1752 06:02:36.945576 [Byte1]: 69
1753 06:02:36.950034
1754 06:02:36.950265 Set Vref, RX VrefLevel [Byte0]: 70
1755 06:02:36.952892 [Byte1]: 70
1756 06:02:36.957484
1757 06:02:36.957669 Set Vref, RX VrefLevel [Byte0]: 71
1758 06:02:36.960548 [Byte1]: 71
1759 06:02:36.964839
1760 06:02:36.964996 Set Vref, RX VrefLevel [Byte0]: 72
1761 06:02:36.968104 [Byte1]: 72
1762 06:02:36.972611
1763 06:02:36.972729 Set Vref, RX VrefLevel [Byte0]: 73
1764 06:02:36.975720 [Byte1]: 73
1765 06:02:36.979839
1766 06:02:36.979943 Set Vref, RX VrefLevel [Byte0]: 74
1767 06:02:36.983416 [Byte1]: 74
1768 06:02:36.987839
1769 06:02:36.988013 Set Vref, RX VrefLevel [Byte0]: 75
1770 06:02:36.991227 [Byte1]: 75
1771 06:02:36.995746
1772 06:02:36.995920 Set Vref, RX VrefLevel [Byte0]: 76
1773 06:02:36.998831 [Byte1]: 76
1774 06:02:37.003152
1775 06:02:37.003323 Set Vref, RX VrefLevel [Byte0]: 77
1776 06:02:37.006460 [Byte1]: 77
1777 06:02:37.010605
1778 06:02:37.010760 Set Vref, RX VrefLevel [Byte0]: 78
1779 06:02:37.014230 [Byte1]: 78
1780 06:02:37.018169
1781 06:02:37.018368 Set Vref, RX VrefLevel [Byte0]: 79
1782 06:02:37.021720 [Byte1]: 79
1783 06:02:37.025781
1784 06:02:37.026010 Final RX Vref Byte 0 = 52 to rank0
1785 06:02:37.029301 Final RX Vref Byte 1 = 60 to rank0
1786 06:02:37.032851 Final RX Vref Byte 0 = 52 to rank1
1787 06:02:37.035971 Final RX Vref Byte 1 = 60 to rank1==
1788 06:02:37.039229 Dram Type= 6, Freq= 0, CH_1, rank 0
1789 06:02:37.042509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 06:02:37.045865 ==
1791 06:02:37.046208 DQS Delay:
1792 06:02:37.046407 DQS0 = 0, DQS1 = 0
1793 06:02:37.049552 DQM Delay:
1794 06:02:37.049926 DQM0 = 92, DQM1 = 82
1795 06:02:37.053094 DQ Delay:
1796 06:02:37.056451 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
1797 06:02:37.056917 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1798 06:02:37.059785 DQ8 =72, DQ9 =68, DQ10 =88, DQ11 =76
1799 06:02:37.062841 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1800 06:02:37.066415
1801 06:02:37.066980
1802 06:02:37.073386 [DQSOSCAuto] RK0, (LSB)MR18= 0x2947, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1803 06:02:37.076635 CH1 RK0: MR19=606, MR18=2947
1804 06:02:37.083146 CH1_RK0: MR19=0x606, MR18=0x2947, DQSOSC=392, MR23=63, INC=96, DEC=64
1805 06:02:37.083626
1806 06:02:37.086098 ----->DramcWriteLeveling(PI) begin...
1807 06:02:37.086578 ==
1808 06:02:37.089544 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 06:02:37.092999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 06:02:37.093572 ==
1811 06:02:37.096638 Write leveling (Byte 0): 28 => 28
1812 06:02:37.100034 Write leveling (Byte 1): 32 => 32
1813 06:02:37.102872 DramcWriteLeveling(PI) end<-----
1814 06:02:37.103443
1815 06:02:37.103819 ==
1816 06:02:37.106177 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 06:02:37.109857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 06:02:37.110525 ==
1819 06:02:37.113290 [Gating] SW mode calibration
1820 06:02:37.119881 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1821 06:02:37.126423 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1822 06:02:37.129600 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1823 06:02:37.133293 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 06:02:37.139680 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 06:02:37.142899 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 06:02:37.146576 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 06:02:37.153209 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 06:02:37.156387 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 06:02:37.160047 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 06:02:37.163374 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 06:02:37.170046 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 06:02:37.173896 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 06:02:37.176836 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 06:02:37.183590 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 06:02:37.186525 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 06:02:37.190055 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 06:02:37.196744 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 06:02:37.199834 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 06:02:37.203539 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1840 06:02:37.210122 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 06:02:37.213391 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 06:02:37.216892 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 06:02:37.223440 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 06:02:37.226688 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 06:02:37.230333 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 06:02:37.236834 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 06:02:37.240015 0 9 4 | B1->B0 | 2424 2323 | 1 0 | (1 1) (0 0)
1848 06:02:37.243195 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1849 06:02:37.246541 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 06:02:37.253607 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 06:02:37.257040 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 06:02:37.260032 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 06:02:37.267443 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 06:02:37.270222 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 06:02:37.273713 0 10 4 | B1->B0 | 2e2e 2f2f | 1 1 | (1 1) (1 0)
1856 06:02:37.279947 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1857 06:02:37.283260 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 06:02:37.287115 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 06:02:37.293241 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 06:02:37.296865 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 06:02:37.300361 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 06:02:37.306797 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 06:02:37.310247 0 11 4 | B1->B0 | 2d2d 2828 | 1 0 | (0 0) (0 0)
1864 06:02:37.313726 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
1865 06:02:37.320292 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 06:02:37.323517 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 06:02:37.326928 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 06:02:37.333971 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 06:02:37.337068 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 06:02:37.340202 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 06:02:37.343183 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1872 06:02:37.350462 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 06:02:37.353556 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 06:02:37.357011 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 06:02:37.363217 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 06:02:37.367135 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 06:02:37.369968 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 06:02:37.376692 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 06:02:37.380107 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 06:02:37.383410 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 06:02:37.390498 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 06:02:37.393530 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 06:02:37.397165 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 06:02:37.403491 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 06:02:37.406841 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 06:02:37.410299 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 06:02:37.413849 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 06:02:37.416683 Total UI for P1: 0, mck2ui 16
1889 06:02:37.420165 best dqsien dly found for B0: ( 0, 14, 2)
1890 06:02:37.423362 Total UI for P1: 0, mck2ui 16
1891 06:02:37.427024 best dqsien dly found for B1: ( 0, 14, 2)
1892 06:02:37.430215 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1893 06:02:37.433518 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1894 06:02:37.436902
1895 06:02:37.440107 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1896 06:02:37.443992 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1897 06:02:37.444615 [Gating] SW calibration Done
1898 06:02:37.446732 ==
1899 06:02:37.450048 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 06:02:37.453331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 06:02:37.454007 ==
1902 06:02:37.454586 RX Vref Scan: 0
1903 06:02:37.455108
1904 06:02:37.456711 RX Vref 0 -> 0, step: 1
1905 06:02:37.457258
1906 06:02:37.460136 RX Delay -130 -> 252, step: 16
1907 06:02:37.463541 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1908 06:02:37.467080 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1909 06:02:37.470194 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1910 06:02:37.476975 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1911 06:02:37.480500 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1912 06:02:37.483755 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1913 06:02:37.486908 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1914 06:02:37.490530 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1915 06:02:37.497179 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1916 06:02:37.500733 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1917 06:02:37.503723 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1918 06:02:37.507118 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1919 06:02:37.510281 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1920 06:02:37.517330 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1921 06:02:37.520506 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1922 06:02:37.523678 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1923 06:02:37.524154 ==
1924 06:02:37.527150 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 06:02:37.530993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 06:02:37.531565 ==
1927 06:02:37.534098 DQS Delay:
1928 06:02:37.534564 DQS0 = 0, DQS1 = 0
1929 06:02:37.537060 DQM Delay:
1930 06:02:37.537528 DQM0 = 90, DQM1 = 87
1931 06:02:37.537904 DQ Delay:
1932 06:02:37.540802 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1933 06:02:37.543767 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1934 06:02:37.547166 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1935 06:02:37.550452 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1936 06:02:37.550919
1937 06:02:37.551285
1938 06:02:37.553559 ==
1939 06:02:37.557357 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 06:02:37.560571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 06:02:37.561143 ==
1942 06:02:37.561511
1943 06:02:37.561877
1944 06:02:37.563753 TX Vref Scan disable
1945 06:02:37.564326 == TX Byte 0 ==
1946 06:02:37.567017 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1947 06:02:37.573991 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1948 06:02:37.574588 == TX Byte 1 ==
1949 06:02:37.577609 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1950 06:02:37.583626 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1951 06:02:37.584208 ==
1952 06:02:37.586873 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 06:02:37.590361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 06:02:37.590953 ==
1955 06:02:37.604346 TX Vref=22, minBit 13, minWin=27, winSum=451
1956 06:02:37.607430 TX Vref=24, minBit 8, minWin=27, winSum=452
1957 06:02:37.610861 TX Vref=26, minBit 8, minWin=27, winSum=456
1958 06:02:37.613652 TX Vref=28, minBit 8, minWin=28, winSum=458
1959 06:02:37.617342 TX Vref=30, minBit 8, minWin=28, winSum=462
1960 06:02:37.620609 TX Vref=32, minBit 8, minWin=27, winSum=460
1961 06:02:37.627262 [TxChooseVref] Worse bit 8, Min win 28, Win sum 462, Final Vref 30
1962 06:02:37.627827
1963 06:02:37.630881 Final TX Range 1 Vref 30
1964 06:02:37.631458
1965 06:02:37.631833 ==
1966 06:02:37.633920 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 06:02:37.637498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 06:02:37.638127 ==
1969 06:02:37.638515
1970 06:02:37.638868
1971 06:02:37.641169 TX Vref Scan disable
1972 06:02:37.644343 == TX Byte 0 ==
1973 06:02:37.647463 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1974 06:02:37.650974 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1975 06:02:37.654369 == TX Byte 1 ==
1976 06:02:37.657336 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1977 06:02:37.660901 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1978 06:02:37.661478
1979 06:02:37.664337 [DATLAT]
1980 06:02:37.664912 Freq=800, CH1 RK1
1981 06:02:37.665290
1982 06:02:37.667503 DATLAT Default: 0xa
1983 06:02:37.668083 0, 0xFFFF, sum = 0
1984 06:02:37.670870 1, 0xFFFF, sum = 0
1985 06:02:37.671346 2, 0xFFFF, sum = 0
1986 06:02:37.674140 3, 0xFFFF, sum = 0
1987 06:02:37.674619 4, 0xFFFF, sum = 0
1988 06:02:37.677804 5, 0xFFFF, sum = 0
1989 06:02:37.678440 6, 0xFFFF, sum = 0
1990 06:02:37.680930 7, 0xFFFF, sum = 0
1991 06:02:37.681515 8, 0xFFFF, sum = 0
1992 06:02:37.684558 9, 0x0, sum = 1
1993 06:02:37.685146 10, 0x0, sum = 2
1994 06:02:37.687542 11, 0x0, sum = 3
1995 06:02:37.688020 12, 0x0, sum = 4
1996 06:02:37.690758 best_step = 10
1997 06:02:37.691231
1998 06:02:37.691604 ==
1999 06:02:37.694100 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 06:02:37.697635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 06:02:37.698272 ==
2002 06:02:37.701027 RX Vref Scan: 0
2003 06:02:37.701600
2004 06:02:37.702005 RX Vref 0 -> 0, step: 1
2005 06:02:37.702363
2006 06:02:37.704669 RX Delay -79 -> 252, step: 8
2007 06:02:37.711115 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2008 06:02:37.714853 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2009 06:02:37.717856 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2010 06:02:37.721432 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2011 06:02:37.724084 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2012 06:02:37.727919 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2013 06:02:37.734341 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2014 06:02:37.737630 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2015 06:02:37.740845 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2016 06:02:37.743945 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2017 06:02:37.747233 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2018 06:02:37.754091 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2019 06:02:37.758109 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2020 06:02:37.761440 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2021 06:02:37.764259 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2022 06:02:37.767822 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2023 06:02:37.770860 ==
2024 06:02:37.774498 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 06:02:37.777738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 06:02:37.778340 ==
2027 06:02:37.778719 DQS Delay:
2028 06:02:37.780952 DQS0 = 0, DQS1 = 0
2029 06:02:37.781528 DQM Delay:
2030 06:02:37.783978 DQM0 = 92, DQM1 = 84
2031 06:02:37.784453 DQ Delay:
2032 06:02:37.787601 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2033 06:02:37.790605 DQ4 =96, DQ5 =108, DQ6 =96, DQ7 =88
2034 06:02:37.794437 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2035 06:02:37.797755 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2036 06:02:37.798358
2037 06:02:37.798735
2038 06:02:37.804342 [DQSOSCAuto] RK1, (LSB)MR18= 0x380d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2039 06:02:37.808030 CH1 RK1: MR19=606, MR18=380D
2040 06:02:37.814545 CH1_RK1: MR19=0x606, MR18=0x380D, DQSOSC=395, MR23=63, INC=94, DEC=63
2041 06:02:37.817844 [RxdqsGatingPostProcess] freq 800
2042 06:02:37.820959 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2043 06:02:37.824512 Pre-setting of DQS Precalculation
2044 06:02:37.830664 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2045 06:02:37.837546 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2046 06:02:37.844291 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2047 06:02:37.844875
2048 06:02:37.845255
2049 06:02:37.847448 [Calibration Summary] 1600 Mbps
2050 06:02:37.847919 CH 0, Rank 0
2051 06:02:37.850861 SW Impedance : PASS
2052 06:02:37.854339 DUTY Scan : NO K
2053 06:02:37.854845 ZQ Calibration : PASS
2054 06:02:37.857768 Jitter Meter : NO K
2055 06:02:37.861307 CBT Training : PASS
2056 06:02:37.861882 Write leveling : PASS
2057 06:02:37.864117 RX DQS gating : PASS
2058 06:02:37.868090 RX DQ/DQS(RDDQC) : PASS
2059 06:02:37.868684 TX DQ/DQS : PASS
2060 06:02:37.871089 RX DATLAT : PASS
2061 06:02:37.874336 RX DQ/DQS(Engine): PASS
2062 06:02:37.874803 TX OE : NO K
2063 06:02:37.877875 All Pass.
2064 06:02:37.878486
2065 06:02:37.878861 CH 0, Rank 1
2066 06:02:37.881204 SW Impedance : PASS
2067 06:02:37.881786 DUTY Scan : NO K
2068 06:02:37.884506 ZQ Calibration : PASS
2069 06:02:37.885084 Jitter Meter : NO K
2070 06:02:37.887738 CBT Training : PASS
2071 06:02:37.891271 Write leveling : PASS
2072 06:02:37.891851 RX DQS gating : PASS
2073 06:02:37.894514 RX DQ/DQS(RDDQC) : PASS
2074 06:02:37.898007 TX DQ/DQS : PASS
2075 06:02:37.898588 RX DATLAT : PASS
2076 06:02:37.901604 RX DQ/DQS(Engine): PASS
2077 06:02:37.904563 TX OE : NO K
2078 06:02:37.905135 All Pass.
2079 06:02:37.905517
2080 06:02:37.905870 CH 1, Rank 0
2081 06:02:37.907886 SW Impedance : PASS
2082 06:02:37.911429 DUTY Scan : NO K
2083 06:02:37.912011 ZQ Calibration : PASS
2084 06:02:37.914779 Jitter Meter : NO K
2085 06:02:37.918066 CBT Training : PASS
2086 06:02:37.918641 Write leveling : PASS
2087 06:02:37.921332 RX DQS gating : PASS
2088 06:02:37.922004 RX DQ/DQS(RDDQC) : PASS
2089 06:02:37.924370 TX DQ/DQS : PASS
2090 06:02:37.927682 RX DATLAT : PASS
2091 06:02:37.928159 RX DQ/DQS(Engine): PASS
2092 06:02:37.931078 TX OE : NO K
2093 06:02:37.931551 All Pass.
2094 06:02:37.931924
2095 06:02:37.934990 CH 1, Rank 1
2096 06:02:37.935609 SW Impedance : PASS
2097 06:02:37.937746 DUTY Scan : NO K
2098 06:02:37.941625 ZQ Calibration : PASS
2099 06:02:37.942267 Jitter Meter : NO K
2100 06:02:37.944477 CBT Training : PASS
2101 06:02:37.947588 Write leveling : PASS
2102 06:02:37.948080 RX DQS gating : PASS
2103 06:02:37.951756 RX DQ/DQS(RDDQC) : PASS
2104 06:02:37.954399 TX DQ/DQS : PASS
2105 06:02:37.954880 RX DATLAT : PASS
2106 06:02:37.958447 RX DQ/DQS(Engine): PASS
2107 06:02:37.958919 TX OE : NO K
2108 06:02:37.961360 All Pass.
2109 06:02:37.961975
2110 06:02:37.962377 DramC Write-DBI off
2111 06:02:37.964748 PER_BANK_REFRESH: Hybrid Mode
2112 06:02:37.968072 TX_TRACKING: ON
2113 06:02:37.971236 [GetDramInforAfterCalByMRR] Vendor 6.
2114 06:02:37.974508 [GetDramInforAfterCalByMRR] Revision 606.
2115 06:02:37.978117 [GetDramInforAfterCalByMRR] Revision 2 0.
2116 06:02:37.978547 MR0 0x3b3b
2117 06:02:37.978890 MR8 0x5151
2118 06:02:37.984705 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 06:02:37.985289
2120 06:02:37.985738 MR0 0x3b3b
2121 06:02:37.986134 MR8 0x5151
2122 06:02:37.988016 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 06:02:37.988492
2124 06:02:37.998204 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2125 06:02:38.001370 [FAST_K] Save calibration result to emmc
2126 06:02:38.004810 [FAST_K] Save calibration result to emmc
2127 06:02:38.008245 dram_init: config_dvfs: 1
2128 06:02:38.011018 dramc_set_vcore_voltage set vcore to 662500
2129 06:02:38.014817 Read voltage for 1200, 2
2130 06:02:38.015386 Vio18 = 0
2131 06:02:38.015762 Vcore = 662500
2132 06:02:38.018539 Vdram = 0
2133 06:02:38.019106 Vddq = 0
2134 06:02:38.019480 Vmddr = 0
2135 06:02:38.024658 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2136 06:02:38.028204 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2137 06:02:38.031884 MEM_TYPE=3, freq_sel=15
2138 06:02:38.035028 sv_algorithm_assistance_LP4_1600
2139 06:02:38.037887 ============ PULL DRAM RESETB DOWN ============
2140 06:02:38.041255 ========== PULL DRAM RESETB DOWN end =========
2141 06:02:38.047999 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2142 06:02:38.051289 ===================================
2143 06:02:38.051834 LPDDR4 DRAM CONFIGURATION
2144 06:02:38.054779 ===================================
2145 06:02:38.058115 EX_ROW_EN[0] = 0x0
2146 06:02:38.061674 EX_ROW_EN[1] = 0x0
2147 06:02:38.062304 LP4Y_EN = 0x0
2148 06:02:38.065040 WORK_FSP = 0x0
2149 06:02:38.065605 WL = 0x4
2150 06:02:38.068654 RL = 0x4
2151 06:02:38.069218 BL = 0x2
2152 06:02:38.071330 RPST = 0x0
2153 06:02:38.071802 RD_PRE = 0x0
2154 06:02:38.074667 WR_PRE = 0x1
2155 06:02:38.075233 WR_PST = 0x0
2156 06:02:38.078126 DBI_WR = 0x0
2157 06:02:38.078551 DBI_RD = 0x0
2158 06:02:38.081889 OTF = 0x1
2159 06:02:38.085178 ===================================
2160 06:02:38.088178 ===================================
2161 06:02:38.088649 ANA top config
2162 06:02:38.091213 ===================================
2163 06:02:38.095077 DLL_ASYNC_EN = 0
2164 06:02:38.098685 ALL_SLAVE_EN = 0
2165 06:02:38.101708 NEW_RANK_MODE = 1
2166 06:02:38.102307 DLL_IDLE_MODE = 1
2167 06:02:38.104778 LP45_APHY_COMB_EN = 1
2168 06:02:38.108145 TX_ODT_DIS = 1
2169 06:02:38.111761 NEW_8X_MODE = 1
2170 06:02:38.115131 ===================================
2171 06:02:38.118450 ===================================
2172 06:02:38.119018 data_rate = 2400
2173 06:02:38.121723 CKR = 1
2174 06:02:38.124948 DQ_P2S_RATIO = 8
2175 06:02:38.128229 ===================================
2176 06:02:38.132039 CA_P2S_RATIO = 8
2177 06:02:38.135077 DQ_CA_OPEN = 0
2178 06:02:38.138478 DQ_SEMI_OPEN = 0
2179 06:02:38.139059 CA_SEMI_OPEN = 0
2180 06:02:38.141753 CA_FULL_RATE = 0
2181 06:02:38.145006 DQ_CKDIV4_EN = 0
2182 06:02:38.148192 CA_CKDIV4_EN = 0
2183 06:02:38.151668 CA_PREDIV_EN = 0
2184 06:02:38.154726 PH8_DLY = 17
2185 06:02:38.155195 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2186 06:02:38.158227 DQ_AAMCK_DIV = 4
2187 06:02:38.161583 CA_AAMCK_DIV = 4
2188 06:02:38.165364 CA_ADMCK_DIV = 4
2189 06:02:38.168327 DQ_TRACK_CA_EN = 0
2190 06:02:38.171503 CA_PICK = 1200
2191 06:02:38.175198 CA_MCKIO = 1200
2192 06:02:38.175731 MCKIO_SEMI = 0
2193 06:02:38.178624 PLL_FREQ = 2366
2194 06:02:38.181801 DQ_UI_PI_RATIO = 32
2195 06:02:38.185089 CA_UI_PI_RATIO = 0
2196 06:02:38.188034 ===================================
2197 06:02:38.191670 ===================================
2198 06:02:38.194990 memory_type:LPDDR4
2199 06:02:38.195458 GP_NUM : 10
2200 06:02:38.198470 SRAM_EN : 1
2201 06:02:38.199043 MD32_EN : 0
2202 06:02:38.201584 ===================================
2203 06:02:38.205244 [ANA_INIT] >>>>>>>>>>>>>>
2204 06:02:38.208348 <<<<<< [CONFIGURE PHASE]: ANA_TX
2205 06:02:38.211484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2206 06:02:38.215149 ===================================
2207 06:02:38.218317 data_rate = 2400,PCW = 0X5b00
2208 06:02:38.221605 ===================================
2209 06:02:38.224967 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2210 06:02:38.232100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 06:02:38.235479 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 06:02:38.241882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2213 06:02:38.245265 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2214 06:02:38.248549 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2215 06:02:38.249022 [ANA_INIT] flow start
2216 06:02:38.251700 [ANA_INIT] PLL >>>>>>>>
2217 06:02:38.255026 [ANA_INIT] PLL <<<<<<<<
2218 06:02:38.255493 [ANA_INIT] MIDPI >>>>>>>>
2219 06:02:38.258378 [ANA_INIT] MIDPI <<<<<<<<
2220 06:02:38.261824 [ANA_INIT] DLL >>>>>>>>
2221 06:02:38.262451 [ANA_INIT] DLL <<<<<<<<
2222 06:02:38.265025 [ANA_INIT] flow end
2223 06:02:38.268213 ============ LP4 DIFF to SE enter ============
2224 06:02:38.271682 ============ LP4 DIFF to SE exit ============
2225 06:02:38.275245 [ANA_INIT] <<<<<<<<<<<<<
2226 06:02:38.278502 [Flow] Enable top DCM control >>>>>
2227 06:02:38.282312 [Flow] Enable top DCM control <<<<<
2228 06:02:38.284892 Enable DLL master slave shuffle
2229 06:02:38.291621 ==============================================================
2230 06:02:38.292189 Gating Mode config
2231 06:02:38.298745 ==============================================================
2232 06:02:38.299323 Config description:
2233 06:02:38.308728 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2234 06:02:38.315344 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2235 06:02:38.322107 SELPH_MODE 0: By rank 1: By Phase
2236 06:02:38.325164 ==============================================================
2237 06:02:38.328566 GAT_TRACK_EN = 1
2238 06:02:38.331950 RX_GATING_MODE = 2
2239 06:02:38.335225 RX_GATING_TRACK_MODE = 2
2240 06:02:38.338690 SELPH_MODE = 1
2241 06:02:38.342445 PICG_EARLY_EN = 1
2242 06:02:38.345213 VALID_LAT_VALUE = 1
2243 06:02:38.348740 ==============================================================
2244 06:02:38.352082 Enter into Gating configuration >>>>
2245 06:02:38.355131 Exit from Gating configuration <<<<
2246 06:02:38.358738 Enter into DVFS_PRE_config >>>>>
2247 06:02:38.372044 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2248 06:02:38.375166 Exit from DVFS_PRE_config <<<<<
2249 06:02:38.375597 Enter into PICG configuration >>>>
2250 06:02:38.378726 Exit from PICG configuration <<<<
2251 06:02:38.382167 [RX_INPUT] configuration >>>>>
2252 06:02:38.385364 [RX_INPUT] configuration <<<<<
2253 06:02:38.392061 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2254 06:02:38.394996 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2255 06:02:38.402042 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 06:02:38.408298 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 06:02:38.415383 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 06:02:38.422523 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 06:02:38.425132 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2260 06:02:38.428751 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2261 06:02:38.432022 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2262 06:02:38.438640 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2263 06:02:38.442122 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2264 06:02:38.445485 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 06:02:38.448482 ===================================
2266 06:02:38.452496 LPDDR4 DRAM CONFIGURATION
2267 06:02:38.455700 ===================================
2268 06:02:38.456269 EX_ROW_EN[0] = 0x0
2269 06:02:38.458537 EX_ROW_EN[1] = 0x0
2270 06:02:38.462366 LP4Y_EN = 0x0
2271 06:02:38.462837 WORK_FSP = 0x0
2272 06:02:38.465289 WL = 0x4
2273 06:02:38.465756 RL = 0x4
2274 06:02:38.468822 BL = 0x2
2275 06:02:38.469296 RPST = 0x0
2276 06:02:38.472386 RD_PRE = 0x0
2277 06:02:38.472920 WR_PRE = 0x1
2278 06:02:38.475303 WR_PST = 0x0
2279 06:02:38.475772 DBI_WR = 0x0
2280 06:02:38.478716 DBI_RD = 0x0
2281 06:02:38.479186 OTF = 0x1
2282 06:02:38.481777 ===================================
2283 06:02:38.485307 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2284 06:02:38.492056 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2285 06:02:38.495203 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2286 06:02:38.498704 ===================================
2287 06:02:38.501991 LPDDR4 DRAM CONFIGURATION
2288 06:02:38.505291 ===================================
2289 06:02:38.505800 EX_ROW_EN[0] = 0x10
2290 06:02:38.508466 EX_ROW_EN[1] = 0x0
2291 06:02:38.509011 LP4Y_EN = 0x0
2292 06:02:38.511804 WORK_FSP = 0x0
2293 06:02:38.512298 WL = 0x4
2294 06:02:38.515475 RL = 0x4
2295 06:02:38.515890 BL = 0x2
2296 06:02:38.518706 RPST = 0x0
2297 06:02:38.519122 RD_PRE = 0x0
2298 06:02:38.521964 WR_PRE = 0x1
2299 06:02:38.522380 WR_PST = 0x0
2300 06:02:38.525550 DBI_WR = 0x0
2301 06:02:38.528590 DBI_RD = 0x0
2302 06:02:38.528999 OTF = 0x1
2303 06:02:38.531998 ===================================
2304 06:02:38.538880 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2305 06:02:38.539305 ==
2306 06:02:38.541732 Dram Type= 6, Freq= 0, CH_0, rank 0
2307 06:02:38.545346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2308 06:02:38.545639 ==
2309 06:02:38.548802 [Duty_Offset_Calibration]
2310 06:02:38.549136 B0:2 B1:0 CA:1
2311 06:02:38.549413
2312 06:02:38.551922 [DutyScan_Calibration_Flow] k_type=0
2313 06:02:38.561901
2314 06:02:38.562226 ==CLK 0==
2315 06:02:38.565618 Final CLK duty delay cell = -4
2316 06:02:38.569006 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2317 06:02:38.572230 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2318 06:02:38.575349 [-4] AVG Duty = 4953%(X100)
2319 06:02:38.575762
2320 06:02:38.578593 CH0 CLK Duty spec in!! Max-Min= 156%
2321 06:02:38.582145 [DutyScan_Calibration_Flow] ====Done====
2322 06:02:38.582649
2323 06:02:38.585373 [DutyScan_Calibration_Flow] k_type=1
2324 06:02:38.601291
2325 06:02:38.601799 ==DQS 0 ==
2326 06:02:38.604205 Final DQS duty delay cell = 0
2327 06:02:38.607658 [0] MAX Duty = 5187%(X100), DQS PI = 32
2328 06:02:38.610925 [0] MIN Duty = 4938%(X100), DQS PI = 0
2329 06:02:38.611405 [0] AVG Duty = 5062%(X100)
2330 06:02:38.614129
2331 06:02:38.614536 ==DQS 1 ==
2332 06:02:38.617658 Final DQS duty delay cell = -4
2333 06:02:38.620664 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2334 06:02:38.623998 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2335 06:02:38.627594 [-4] AVG Duty = 5031%(X100)
2336 06:02:38.628011
2337 06:02:38.630795 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2338 06:02:38.631209
2339 06:02:38.634140 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2340 06:02:38.637589 [DutyScan_Calibration_Flow] ====Done====
2341 06:02:38.638038
2342 06:02:38.640764 [DutyScan_Calibration_Flow] k_type=3
2343 06:02:38.657930
2344 06:02:38.658473 ==DQM 0 ==
2345 06:02:38.661061 Final DQM duty delay cell = 0
2346 06:02:38.664600 [0] MAX Duty = 5062%(X100), DQS PI = 24
2347 06:02:38.668298 [0] MIN Duty = 4813%(X100), DQS PI = 0
2348 06:02:38.668864 [0] AVG Duty = 4937%(X100)
2349 06:02:38.669351
2350 06:02:38.671204 ==DQM 1 ==
2351 06:02:38.674574 Final DQM duty delay cell = 0
2352 06:02:38.678058 [0] MAX Duty = 5187%(X100), DQS PI = 46
2353 06:02:38.681615 [0] MIN Duty = 5000%(X100), DQS PI = 12
2354 06:02:38.682221 [0] AVG Duty = 5093%(X100)
2355 06:02:38.682719
2356 06:02:38.688229 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2357 06:02:38.688788
2358 06:02:38.691279 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2359 06:02:38.694677 [DutyScan_Calibration_Flow] ====Done====
2360 06:02:38.695135
2361 06:02:38.697648 [DutyScan_Calibration_Flow] k_type=2
2362 06:02:38.714602
2363 06:02:38.715159 ==DQ 0 ==
2364 06:02:38.718089 Final DQ duty delay cell = -4
2365 06:02:38.720942 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2366 06:02:38.724420 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2367 06:02:38.727897 [-4] AVG Duty = 4953%(X100)
2368 06:02:38.728449
2369 06:02:38.728814 ==DQ 1 ==
2370 06:02:38.730867 Final DQ duty delay cell = 4
2371 06:02:38.734416 [4] MAX Duty = 5093%(X100), DQS PI = 6
2372 06:02:38.737435 [4] MIN Duty = 5031%(X100), DQS PI = 0
2373 06:02:38.737915 [4] AVG Duty = 5062%(X100)
2374 06:02:38.738316
2375 06:02:38.741214 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2376 06:02:38.744652
2377 06:02:38.747854 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2378 06:02:38.751039 [DutyScan_Calibration_Flow] ====Done====
2379 06:02:38.751506 ==
2380 06:02:38.754446 Dram Type= 6, Freq= 0, CH_1, rank 0
2381 06:02:38.757773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2382 06:02:38.758364 ==
2383 06:02:38.761369 [Duty_Offset_Calibration]
2384 06:02:38.761921 B0:0 B1:-1 CA:2
2385 06:02:38.762348
2386 06:02:38.764418 [DutyScan_Calibration_Flow] k_type=0
2387 06:02:38.774618
2388 06:02:38.775173 ==CLK 0==
2389 06:02:38.777637 Final CLK duty delay cell = 0
2390 06:02:38.781286 [0] MAX Duty = 5156%(X100), DQS PI = 16
2391 06:02:38.784396 [0] MIN Duty = 4938%(X100), DQS PI = 44
2392 06:02:38.785054 [0] AVG Duty = 5047%(X100)
2393 06:02:38.787816
2394 06:02:38.790744 CH1 CLK Duty spec in!! Max-Min= 218%
2395 06:02:38.794695 [DutyScan_Calibration_Flow] ====Done====
2396 06:02:38.795317
2397 06:02:38.797598 [DutyScan_Calibration_Flow] k_type=1
2398 06:02:38.814148
2399 06:02:38.814750 ==DQS 0 ==
2400 06:02:38.817150 Final DQS duty delay cell = 0
2401 06:02:38.820155 [0] MAX Duty = 5093%(X100), DQS PI = 24
2402 06:02:38.823556 [0] MIN Duty = 4969%(X100), DQS PI = 0
2403 06:02:38.824012 [0] AVG Duty = 5031%(X100)
2404 06:02:38.827084
2405 06:02:38.827532 ==DQS 1 ==
2406 06:02:38.830467 Final DQS duty delay cell = 0
2407 06:02:38.833878 [0] MAX Duty = 5156%(X100), DQS PI = 0
2408 06:02:38.837612 [0] MIN Duty = 4875%(X100), DQS PI = 34
2409 06:02:38.838248 [0] AVG Duty = 5015%(X100)
2410 06:02:38.838623
2411 06:02:38.844227 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2412 06:02:38.844792
2413 06:02:38.847468 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2414 06:02:38.850836 [DutyScan_Calibration_Flow] ====Done====
2415 06:02:38.851452
2416 06:02:38.853807 [DutyScan_Calibration_Flow] k_type=3
2417 06:02:38.870423
2418 06:02:38.870974 ==DQM 0 ==
2419 06:02:38.873510 Final DQM duty delay cell = 4
2420 06:02:38.876849 [4] MAX Duty = 5093%(X100), DQS PI = 6
2421 06:02:38.880401 [4] MIN Duty = 4938%(X100), DQS PI = 48
2422 06:02:38.880962 [4] AVG Duty = 5015%(X100)
2423 06:02:38.883400
2424 06:02:38.883853 ==DQM 1 ==
2425 06:02:38.887101 Final DQM duty delay cell = -4
2426 06:02:38.890389 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2427 06:02:38.893383 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2428 06:02:38.896828 [-4] AVG Duty = 4875%(X100)
2429 06:02:38.897498
2430 06:02:38.900215 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2431 06:02:38.900672
2432 06:02:38.903416 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2433 06:02:38.906557 [DutyScan_Calibration_Flow] ====Done====
2434 06:02:38.907066
2435 06:02:38.910073 [DutyScan_Calibration_Flow] k_type=2
2436 06:02:38.927173
2437 06:02:38.927716 ==DQ 0 ==
2438 06:02:38.930666 Final DQ duty delay cell = 0
2439 06:02:38.933743 [0] MAX Duty = 5062%(X100), DQS PI = 18
2440 06:02:38.936960 [0] MIN Duty = 4938%(X100), DQS PI = 0
2441 06:02:38.937507 [0] AVG Duty = 5000%(X100)
2442 06:02:38.937876
2443 06:02:38.940574 ==DQ 1 ==
2444 06:02:38.943485 Final DQ duty delay cell = 0
2445 06:02:38.946934 [0] MAX Duty = 5000%(X100), DQS PI = 0
2446 06:02:38.950519 [0] MIN Duty = 4813%(X100), DQS PI = 34
2447 06:02:38.951010 [0] AVG Duty = 4906%(X100)
2448 06:02:38.951355
2449 06:02:38.953661 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2450 06:02:38.954121
2451 06:02:38.957055 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2452 06:02:38.964004 [DutyScan_Calibration_Flow] ====Done====
2453 06:02:38.966821 nWR fixed to 30
2454 06:02:38.967313 [ModeRegInit_LP4] CH0 RK0
2455 06:02:38.970541 [ModeRegInit_LP4] CH0 RK1
2456 06:02:38.973915 [ModeRegInit_LP4] CH1 RK0
2457 06:02:38.974479 [ModeRegInit_LP4] CH1 RK1
2458 06:02:38.977195 match AC timing 7
2459 06:02:38.980552 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2460 06:02:38.983645 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2461 06:02:38.990311 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2462 06:02:38.993550 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2463 06:02:39.000458 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2464 06:02:39.000988 ==
2465 06:02:39.003806 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 06:02:39.007067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 06:02:39.007593 ==
2468 06:02:39.013758 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 06:02:39.017575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2470 06:02:39.026931 [CA 0] Center 38 (8~69) winsize 62
2471 06:02:39.029883 [CA 1] Center 38 (8~69) winsize 62
2472 06:02:39.033381 [CA 2] Center 35 (5~66) winsize 62
2473 06:02:39.036956 [CA 3] Center 35 (4~66) winsize 63
2474 06:02:39.039973 [CA 4] Center 34 (4~65) winsize 62
2475 06:02:39.043242 [CA 5] Center 33 (3~63) winsize 61
2476 06:02:39.043838
2477 06:02:39.046404 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2478 06:02:39.046870
2479 06:02:39.050094 [CATrainingPosCal] consider 1 rank data
2480 06:02:39.053206 u2DelayCellTimex100 = 270/100 ps
2481 06:02:39.057237 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2482 06:02:39.060470 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2483 06:02:39.067039 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2484 06:02:39.070507 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2485 06:02:39.073561 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2486 06:02:39.077120 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2487 06:02:39.077703
2488 06:02:39.080272 CA PerBit enable=1, Macro0, CA PI delay=33
2489 06:02:39.080854
2490 06:02:39.083654 [CBTSetCACLKResult] CA Dly = 33
2491 06:02:39.084239 CS Dly: 6 (0~37)
2492 06:02:39.084620 ==
2493 06:02:39.087147 Dram Type= 6, Freq= 0, CH_0, rank 1
2494 06:02:39.094124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 06:02:39.094711 ==
2496 06:02:39.096865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2497 06:02:39.103797 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2498 06:02:39.112432 [CA 0] Center 39 (8~70) winsize 63
2499 06:02:39.115977 [CA 1] Center 38 (8~69) winsize 62
2500 06:02:39.118886 [CA 2] Center 35 (5~66) winsize 62
2501 06:02:39.122988 [CA 3] Center 35 (5~66) winsize 62
2502 06:02:39.125767 [CA 4] Center 34 (4~65) winsize 62
2503 06:02:39.129428 [CA 5] Center 34 (4~64) winsize 61
2504 06:02:39.130066
2505 06:02:39.132670 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2506 06:02:39.133187
2507 06:02:39.136082 [CATrainingPosCal] consider 2 rank data
2508 06:02:39.139290 u2DelayCellTimex100 = 270/100 ps
2509 06:02:39.142837 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2510 06:02:39.145765 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2511 06:02:39.152185 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2512 06:02:39.155845 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2513 06:02:39.159408 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2514 06:02:39.162630 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2515 06:02:39.163107
2516 06:02:39.165976 CA PerBit enable=1, Macro0, CA PI delay=33
2517 06:02:39.166452
2518 06:02:39.169351 [CBTSetCACLKResult] CA Dly = 33
2519 06:02:39.169922 CS Dly: 7 (0~39)
2520 06:02:39.170349
2521 06:02:39.172578 ----->DramcWriteLeveling(PI) begin...
2522 06:02:39.173158 ==
2523 06:02:39.176069 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 06:02:39.182841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 06:02:39.183415 ==
2526 06:02:39.186531 Write leveling (Byte 0): 35 => 35
2527 06:02:39.189422 Write leveling (Byte 1): 33 => 33
2528 06:02:39.189896 DramcWriteLeveling(PI) end<-----
2529 06:02:39.192885
2530 06:02:39.193453 ==
2531 06:02:39.196096 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 06:02:39.199797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 06:02:39.200369 ==
2534 06:02:39.202839 [Gating] SW mode calibration
2535 06:02:39.209654 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2536 06:02:39.213148 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2537 06:02:39.220008 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2538 06:02:39.222840 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2539 06:02:39.226124 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 06:02:39.232867 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 06:02:39.236211 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 06:02:39.239630 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 06:02:39.246202 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2544 06:02:39.249752 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2545 06:02:39.252681 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
2546 06:02:39.256274 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2547 06:02:39.262863 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 06:02:39.266134 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 06:02:39.269444 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 06:02:39.276264 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 06:02:39.279408 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2552 06:02:39.282826 1 0 28 | B1->B0 | 2525 4646 | 1 0 | (0 0) (0 0)
2553 06:02:39.289617 1 1 0 | B1->B0 | 2a2a 4646 | 0 0 | (1 1) (0 0)
2554 06:02:39.292826 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 06:02:39.296373 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 06:02:39.303063 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 06:02:39.306212 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 06:02:39.309644 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 06:02:39.316290 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2560 06:02:39.319487 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2561 06:02:39.322730 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2562 06:02:39.329822 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 06:02:39.332754 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 06:02:39.336564 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 06:02:39.342849 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 06:02:39.346539 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 06:02:39.349732 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 06:02:39.352924 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 06:02:39.359459 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 06:02:39.362761 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 06:02:39.366350 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 06:02:39.372797 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 06:02:39.375935 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 06:02:39.379335 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 06:02:39.386184 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2576 06:02:39.389828 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2577 06:02:39.392836 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 06:02:39.396156 Total UI for P1: 0, mck2ui 16
2579 06:02:39.399566 best dqsien dly found for B0: ( 1, 3, 26)
2580 06:02:39.403218 Total UI for P1: 0, mck2ui 16
2581 06:02:39.406380 best dqsien dly found for B1: ( 1, 3, 30)
2582 06:02:39.409692 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2583 06:02:39.413371 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2584 06:02:39.413991
2585 06:02:39.419987 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2586 06:02:39.422809 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2587 06:02:39.423301 [Gating] SW calibration Done
2588 06:02:39.426447 ==
2589 06:02:39.430039 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 06:02:39.433287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 06:02:39.433777 ==
2592 06:02:39.434296 RX Vref Scan: 0
2593 06:02:39.434756
2594 06:02:39.436641 RX Vref 0 -> 0, step: 1
2595 06:02:39.437219
2596 06:02:39.439808 RX Delay -40 -> 252, step: 8
2597 06:02:39.443374 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2598 06:02:39.446601 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2599 06:02:39.449808 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2600 06:02:39.456408 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2601 06:02:39.459948 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2602 06:02:39.463200 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2603 06:02:39.466704 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2604 06:02:39.469839 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2605 06:02:39.476296 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2606 06:02:39.479835 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2607 06:02:39.483284 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2608 06:02:39.486492 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2609 06:02:39.490086 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2610 06:02:39.496441 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2611 06:02:39.500299 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2612 06:02:39.503341 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2613 06:02:39.503926 ==
2614 06:02:39.506946 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 06:02:39.509880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 06:02:39.510504 ==
2617 06:02:39.513339 DQS Delay:
2618 06:02:39.513918 DQS0 = 0, DQS1 = 0
2619 06:02:39.514446 DQM Delay:
2620 06:02:39.516305 DQM0 = 123, DQM1 = 110
2621 06:02:39.516791 DQ Delay:
2622 06:02:39.519657 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2623 06:02:39.523278 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2624 06:02:39.529610 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2625 06:02:39.532884 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2626 06:02:39.533376
2627 06:02:39.533858
2628 06:02:39.534373 ==
2629 06:02:39.536428 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 06:02:39.539701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 06:02:39.540203 ==
2632 06:02:39.540581
2633 06:02:39.540928
2634 06:02:39.543045 TX Vref Scan disable
2635 06:02:39.543514 == TX Byte 0 ==
2636 06:02:39.549618 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2637 06:02:39.552982 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2638 06:02:39.553452 == TX Byte 1 ==
2639 06:02:39.559558 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2640 06:02:39.562983 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2641 06:02:39.563455 ==
2642 06:02:39.566446 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 06:02:39.569787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 06:02:39.570486 ==
2645 06:02:39.582786 TX Vref=22, minBit 0, minWin=24, winSum=397
2646 06:02:39.586353 TX Vref=24, minBit 0, minWin=24, winSum=406
2647 06:02:39.589439 TX Vref=26, minBit 0, minWin=24, winSum=407
2648 06:02:39.592517 TX Vref=28, minBit 1, minWin=25, winSum=412
2649 06:02:39.596256 TX Vref=30, minBit 4, minWin=25, winSum=417
2650 06:02:39.599343 TX Vref=32, minBit 3, minWin=25, winSum=414
2651 06:02:39.606234 [TxChooseVref] Worse bit 4, Min win 25, Win sum 417, Final Vref 30
2652 06:02:39.606807
2653 06:02:39.609269 Final TX Range 1 Vref 30
2654 06:02:39.609736
2655 06:02:39.610136 ==
2656 06:02:39.612832 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 06:02:39.616224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 06:02:39.616832 ==
2659 06:02:39.617209
2660 06:02:39.617555
2661 06:02:39.618918 TX Vref Scan disable
2662 06:02:39.622639 == TX Byte 0 ==
2663 06:02:39.625830 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2664 06:02:39.629107 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2665 06:02:39.632504 == TX Byte 1 ==
2666 06:02:39.636231 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2667 06:02:39.639161 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2668 06:02:39.639706
2669 06:02:39.642562 [DATLAT]
2670 06:02:39.643029 Freq=1200, CH0 RK0
2671 06:02:39.643405
2672 06:02:39.646094 DATLAT Default: 0xd
2673 06:02:39.646657 0, 0xFFFF, sum = 0
2674 06:02:39.649313 1, 0xFFFF, sum = 0
2675 06:02:39.649892 2, 0xFFFF, sum = 0
2676 06:02:39.652529 3, 0xFFFF, sum = 0
2677 06:02:39.653008 4, 0xFFFF, sum = 0
2678 06:02:39.656004 5, 0xFFFF, sum = 0
2679 06:02:39.656485 6, 0xFFFF, sum = 0
2680 06:02:39.659284 7, 0xFFFF, sum = 0
2681 06:02:39.659761 8, 0xFFFF, sum = 0
2682 06:02:39.662710 9, 0xFFFF, sum = 0
2683 06:02:39.663182 10, 0xFFFF, sum = 0
2684 06:02:39.666108 11, 0xFFFF, sum = 0
2685 06:02:39.666617 12, 0x0, sum = 1
2686 06:02:39.669467 13, 0x0, sum = 2
2687 06:02:39.669969 14, 0x0, sum = 3
2688 06:02:39.672913 15, 0x0, sum = 4
2689 06:02:39.673389 best_step = 13
2690 06:02:39.673761
2691 06:02:39.674172 ==
2692 06:02:39.675935 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 06:02:39.682605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 06:02:39.683192 ==
2695 06:02:39.683694 RX Vref Scan: 1
2696 06:02:39.684062
2697 06:02:39.686221 Set Vref Range= 32 -> 127
2698 06:02:39.686790
2699 06:02:39.689435 RX Vref 32 -> 127, step: 1
2700 06:02:39.690054
2701 06:02:39.693143 RX Delay -13 -> 252, step: 4
2702 06:02:39.693719
2703 06:02:39.695976 Set Vref, RX VrefLevel [Byte0]: 32
2704 06:02:39.699177 [Byte1]: 32
2705 06:02:39.699646
2706 06:02:39.702604 Set Vref, RX VrefLevel [Byte0]: 33
2707 06:02:39.706217 [Byte1]: 33
2708 06:02:39.706786
2709 06:02:39.709221 Set Vref, RX VrefLevel [Byte0]: 34
2710 06:02:39.712542 [Byte1]: 34
2711 06:02:39.716527
2712 06:02:39.717112 Set Vref, RX VrefLevel [Byte0]: 35
2713 06:02:39.719966 [Byte1]: 35
2714 06:02:39.724939
2715 06:02:39.725504 Set Vref, RX VrefLevel [Byte0]: 36
2716 06:02:39.727757 [Byte1]: 36
2717 06:02:39.732345
2718 06:02:39.732813 Set Vref, RX VrefLevel [Byte0]: 37
2719 06:02:39.735822 [Byte1]: 37
2720 06:02:39.740115
2721 06:02:39.740583 Set Vref, RX VrefLevel [Byte0]: 38
2722 06:02:39.743512 [Byte1]: 38
2723 06:02:39.748099
2724 06:02:39.748835 Set Vref, RX VrefLevel [Byte0]: 39
2725 06:02:39.751312 [Byte1]: 39
2726 06:02:39.756363
2727 06:02:39.756923 Set Vref, RX VrefLevel [Byte0]: 40
2728 06:02:39.759131 [Byte1]: 40
2729 06:02:39.764132
2730 06:02:39.764696 Set Vref, RX VrefLevel [Byte0]: 41
2731 06:02:39.767371 [Byte1]: 41
2732 06:02:39.772066
2733 06:02:39.772628 Set Vref, RX VrefLevel [Byte0]: 42
2734 06:02:39.775519 [Byte1]: 42
2735 06:02:39.779951
2736 06:02:39.780419 Set Vref, RX VrefLevel [Byte0]: 43
2737 06:02:39.783303 [Byte1]: 43
2738 06:02:39.787748
2739 06:02:39.788447 Set Vref, RX VrefLevel [Byte0]: 44
2740 06:02:39.790747 [Byte1]: 44
2741 06:02:39.795759
2742 06:02:39.796324 Set Vref, RX VrefLevel [Byte0]: 45
2743 06:02:39.798868 [Byte1]: 45
2744 06:02:39.803404
2745 06:02:39.803971 Set Vref, RX VrefLevel [Byte0]: 46
2746 06:02:39.806696 [Byte1]: 46
2747 06:02:39.811290
2748 06:02:39.811860 Set Vref, RX VrefLevel [Byte0]: 47
2749 06:02:39.814633 [Byte1]: 47
2750 06:02:39.819592
2751 06:02:39.820157 Set Vref, RX VrefLevel [Byte0]: 48
2752 06:02:39.822801 [Byte1]: 48
2753 06:02:39.826981
2754 06:02:39.827545 Set Vref, RX VrefLevel [Byte0]: 49
2755 06:02:39.830249 [Byte1]: 49
2756 06:02:39.834711
2757 06:02:39.835180 Set Vref, RX VrefLevel [Byte0]: 50
2758 06:02:39.838362 [Byte1]: 50
2759 06:02:39.842819
2760 06:02:39.843382 Set Vref, RX VrefLevel [Byte0]: 51
2761 06:02:39.846172 [Byte1]: 51
2762 06:02:39.850621
2763 06:02:39.851253 Set Vref, RX VrefLevel [Byte0]: 52
2764 06:02:39.854316 [Byte1]: 52
2765 06:02:39.858522
2766 06:02:39.858989 Set Vref, RX VrefLevel [Byte0]: 53
2767 06:02:39.861872 [Byte1]: 53
2768 06:02:39.866793
2769 06:02:39.867356 Set Vref, RX VrefLevel [Byte0]: 54
2770 06:02:39.870053 [Byte1]: 54
2771 06:02:39.874377
2772 06:02:39.874944 Set Vref, RX VrefLevel [Byte0]: 55
2773 06:02:39.877534 [Byte1]: 55
2774 06:02:39.882619
2775 06:02:39.883184 Set Vref, RX VrefLevel [Byte0]: 56
2776 06:02:39.885829 [Byte1]: 56
2777 06:02:39.890188
2778 06:02:39.890775 Set Vref, RX VrefLevel [Byte0]: 57
2779 06:02:39.893479 [Byte1]: 57
2780 06:02:39.898043
2781 06:02:39.898606 Set Vref, RX VrefLevel [Byte0]: 58
2782 06:02:39.901348 [Byte1]: 58
2783 06:02:39.906529
2784 06:02:39.907095 Set Vref, RX VrefLevel [Byte0]: 59
2785 06:02:39.909104 [Byte1]: 59
2786 06:02:39.914089
2787 06:02:39.914653 Set Vref, RX VrefLevel [Byte0]: 60
2788 06:02:39.917232 [Byte1]: 60
2789 06:02:39.922101
2790 06:02:39.922662 Set Vref, RX VrefLevel [Byte0]: 61
2791 06:02:39.924899 [Byte1]: 61
2792 06:02:39.929535
2793 06:02:39.930033 Set Vref, RX VrefLevel [Byte0]: 62
2794 06:02:39.933199 [Byte1]: 62
2795 06:02:39.937541
2796 06:02:39.938151 Set Vref, RX VrefLevel [Byte0]: 63
2797 06:02:39.940934 [Byte1]: 63
2798 06:02:39.945423
2799 06:02:39.946028 Set Vref, RX VrefLevel [Byte0]: 64
2800 06:02:39.948625 [Byte1]: 64
2801 06:02:39.953387
2802 06:02:39.956655 Set Vref, RX VrefLevel [Byte0]: 65
2803 06:02:39.957146 [Byte1]: 65
2804 06:02:39.961089
2805 06:02:39.961554 Set Vref, RX VrefLevel [Byte0]: 66
2806 06:02:39.964542 [Byte1]: 66
2807 06:02:39.969250
2808 06:02:39.969820 Set Vref, RX VrefLevel [Byte0]: 67
2809 06:02:39.972436 [Byte1]: 67
2810 06:02:39.976696
2811 06:02:39.977163 Set Vref, RX VrefLevel [Byte0]: 68
2812 06:02:39.980066 [Byte1]: 68
2813 06:02:39.984983
2814 06:02:39.985553 Set Vref, RX VrefLevel [Byte0]: 69
2815 06:02:39.988154 [Byte1]: 69
2816 06:02:39.992727
2817 06:02:39.993296 Final RX Vref Byte 0 = 60 to rank0
2818 06:02:39.996368 Final RX Vref Byte 1 = 50 to rank0
2819 06:02:39.999791 Final RX Vref Byte 0 = 60 to rank1
2820 06:02:40.003004 Final RX Vref Byte 1 = 50 to rank1==
2821 06:02:40.006167 Dram Type= 6, Freq= 0, CH_0, rank 0
2822 06:02:40.012870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 06:02:40.013437 ==
2824 06:02:40.013814 DQS Delay:
2825 06:02:40.014201 DQS0 = 0, DQS1 = 0
2826 06:02:40.016207 DQM Delay:
2827 06:02:40.016679 DQM0 = 122, DQM1 = 110
2828 06:02:40.019311 DQ Delay:
2829 06:02:40.022551 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2830 06:02:40.026109 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2831 06:02:40.029140 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =108
2832 06:02:40.032505 DQ12 =116, DQ13 =112, DQ14 =122, DQ15 =116
2833 06:02:40.033124
2834 06:02:40.033656
2835 06:02:40.039415 [DQSOSCAuto] RK0, (LSB)MR18= 0xc09, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2836 06:02:40.042843 CH0 RK0: MR19=404, MR18=C09
2837 06:02:40.049227 CH0_RK0: MR19=0x404, MR18=0xC09, DQSOSC=405, MR23=63, INC=39, DEC=26
2838 06:02:40.049789
2839 06:02:40.052656 ----->DramcWriteLeveling(PI) begin...
2840 06:02:40.053243 ==
2841 06:02:40.055884 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 06:02:40.059326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 06:02:40.059806 ==
2844 06:02:40.062672 Write leveling (Byte 0): 36 => 36
2845 06:02:40.066052 Write leveling (Byte 1): 30 => 30
2846 06:02:40.069554 DramcWriteLeveling(PI) end<-----
2847 06:02:40.070171
2848 06:02:40.070552 ==
2849 06:02:40.073212 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 06:02:40.076026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 06:02:40.079850 ==
2852 06:02:40.080319 [Gating] SW mode calibration
2853 06:02:40.089721 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2854 06:02:40.092693 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2855 06:02:40.096202 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2856 06:02:40.102968 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 06:02:40.106314 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 06:02:40.109741 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 06:02:40.116428 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 06:02:40.119836 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 06:02:40.122663 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 06:02:40.129196 0 15 28 | B1->B0 | 3131 2e2e | 0 0 | (0 1) (0 0)
2863 06:02:40.132576 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 06:02:40.136129 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 06:02:40.142771 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 06:02:40.146327 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 06:02:40.149614 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 06:02:40.152941 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 06:02:40.159647 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2870 06:02:40.163206 1 0 28 | B1->B0 | 3737 3f3f | 0 0 | (1 1) (0 0)
2871 06:02:40.166384 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 06:02:40.172959 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 06:02:40.176093 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 06:02:40.179460 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 06:02:40.186342 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 06:02:40.189710 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 06:02:40.192624 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 06:02:40.199884 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2879 06:02:40.203499 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2880 06:02:40.206498 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 06:02:40.213216 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 06:02:40.216194 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 06:02:40.219832 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 06:02:40.226106 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 06:02:40.229734 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 06:02:40.232768 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 06:02:40.239800 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 06:02:40.242620 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 06:02:40.246438 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 06:02:40.249626 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 06:02:40.256511 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 06:02:40.259549 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 06:02:40.262754 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 06:02:40.269667 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2895 06:02:40.273248 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2896 06:02:40.276268 Total UI for P1: 0, mck2ui 16
2897 06:02:40.279870 best dqsien dly found for B1: ( 1, 3, 28)
2898 06:02:40.283256 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 06:02:40.286382 Total UI for P1: 0, mck2ui 16
2900 06:02:40.289884 best dqsien dly found for B0: ( 1, 3, 30)
2901 06:02:40.293412 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2902 06:02:40.296351 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2903 06:02:40.296927
2904 06:02:40.303532 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2905 06:02:40.306547 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2906 06:02:40.307131 [Gating] SW calibration Done
2907 06:02:40.309841 ==
2908 06:02:40.313137 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 06:02:40.316757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 06:02:40.317338 ==
2911 06:02:40.317718 RX Vref Scan: 0
2912 06:02:40.318107
2913 06:02:40.319665 RX Vref 0 -> 0, step: 1
2914 06:02:40.320136
2915 06:02:40.323346 RX Delay -40 -> 252, step: 8
2916 06:02:40.326313 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2917 06:02:40.329752 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2918 06:02:40.332980 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2919 06:02:40.339902 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2920 06:02:40.343244 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2921 06:02:40.346813 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2922 06:02:40.349895 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2923 06:02:40.353312 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2924 06:02:40.359464 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2925 06:02:40.363139 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2926 06:02:40.366230 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2927 06:02:40.369580 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2928 06:02:40.373124 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2929 06:02:40.379472 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2930 06:02:40.383100 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2931 06:02:40.386794 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2932 06:02:40.387372 ==
2933 06:02:40.390049 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 06:02:40.393481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 06:02:40.394108 ==
2936 06:02:40.396392 DQS Delay:
2937 06:02:40.396971 DQS0 = 0, DQS1 = 0
2938 06:02:40.399851 DQM Delay:
2939 06:02:40.400442 DQM0 = 120, DQM1 = 108
2940 06:02:40.400825 DQ Delay:
2941 06:02:40.403142 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2942 06:02:40.406830 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2943 06:02:40.413183 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2944 06:02:40.416474 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2945 06:02:40.417057
2946 06:02:40.417438
2947 06:02:40.417783 ==
2948 06:02:40.419619 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 06:02:40.423612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 06:02:40.424197 ==
2951 06:02:40.424575
2952 06:02:40.424941
2953 06:02:40.426422 TX Vref Scan disable
2954 06:02:40.426896 == TX Byte 0 ==
2955 06:02:40.433221 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2956 06:02:40.436354 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2957 06:02:40.436835 == TX Byte 1 ==
2958 06:02:40.443202 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2959 06:02:40.446486 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2960 06:02:40.447061 ==
2961 06:02:40.450063 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 06:02:40.453630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 06:02:40.454275 ==
2964 06:02:40.466245 TX Vref=22, minBit 0, minWin=26, winSum=423
2965 06:02:40.470070 TX Vref=24, minBit 1, minWin=25, winSum=423
2966 06:02:40.473460 TX Vref=26, minBit 2, minWin=26, winSum=430
2967 06:02:40.476854 TX Vref=28, minBit 0, minWin=26, winSum=430
2968 06:02:40.479903 TX Vref=30, minBit 5, minWin=25, winSum=431
2969 06:02:40.483515 TX Vref=32, minBit 3, minWin=26, winSum=431
2970 06:02:40.490319 [TxChooseVref] Worse bit 3, Min win 26, Win sum 431, Final Vref 32
2971 06:02:40.490892
2972 06:02:40.493242 Final TX Range 1 Vref 32
2973 06:02:40.493858
2974 06:02:40.494273 ==
2975 06:02:40.496993 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 06:02:40.500320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 06:02:40.500983 ==
2978 06:02:40.501375
2979 06:02:40.501729
2980 06:02:40.506229 TX Vref Scan disable
2981 06:02:40.506702 == TX Byte 0 ==
2982 06:02:40.510153 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2983 06:02:40.513394 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2984 06:02:40.517073 == TX Byte 1 ==
2985 06:02:40.520155 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2986 06:02:40.523879 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2987 06:02:40.524517
2988 06:02:40.527051 [DATLAT]
2989 06:02:40.527618 Freq=1200, CH0 RK1
2990 06:02:40.527998
2991 06:02:40.530238 DATLAT Default: 0xd
2992 06:02:40.530712 0, 0xFFFF, sum = 0
2993 06:02:40.533187 1, 0xFFFF, sum = 0
2994 06:02:40.533668 2, 0xFFFF, sum = 0
2995 06:02:40.537099 3, 0xFFFF, sum = 0
2996 06:02:40.537674 4, 0xFFFF, sum = 0
2997 06:02:40.539894 5, 0xFFFF, sum = 0
2998 06:02:40.540408 6, 0xFFFF, sum = 0
2999 06:02:40.543274 7, 0xFFFF, sum = 0
3000 06:02:40.543775 8, 0xFFFF, sum = 0
3001 06:02:40.546707 9, 0xFFFF, sum = 0
3002 06:02:40.547283 10, 0xFFFF, sum = 0
3003 06:02:40.550116 11, 0xFFFF, sum = 0
3004 06:02:40.550597 12, 0x0, sum = 1
3005 06:02:40.553281 13, 0x0, sum = 2
3006 06:02:40.553758 14, 0x0, sum = 3
3007 06:02:40.556766 15, 0x0, sum = 4
3008 06:02:40.557246 best_step = 13
3009 06:02:40.557617
3010 06:02:40.558008 ==
3011 06:02:40.560059 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 06:02:40.566549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 06:02:40.567035 ==
3014 06:02:40.567405 RX Vref Scan: 0
3015 06:02:40.567751
3016 06:02:40.570150 RX Vref 0 -> 0, step: 1
3017 06:02:40.570889
3018 06:02:40.573411 RX Delay -21 -> 252, step: 4
3019 06:02:40.576557 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3020 06:02:40.580267 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3021 06:02:40.586638 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3022 06:02:40.590319 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3023 06:02:40.593792 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3024 06:02:40.597031 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3025 06:02:40.600030 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3026 06:02:40.607200 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3027 06:02:40.610161 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3028 06:02:40.613797 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3029 06:02:40.617268 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3030 06:02:40.620870 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3031 06:02:40.623510 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3032 06:02:40.630534 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3033 06:02:40.633822 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3034 06:02:40.637230 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3035 06:02:40.637808 ==
3036 06:02:40.640452 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 06:02:40.643646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 06:02:40.644123 ==
3039 06:02:40.647156 DQS Delay:
3040 06:02:40.647624 DQS0 = 0, DQS1 = 0
3041 06:02:40.650396 DQM Delay:
3042 06:02:40.650979 DQM0 = 119, DQM1 = 107
3043 06:02:40.653893 DQ Delay:
3044 06:02:40.656904 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =112
3045 06:02:40.660215 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3046 06:02:40.663740 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3047 06:02:40.667348 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3048 06:02:40.667925
3049 06:02:40.668299
3050 06:02:40.673820 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 406 ps
3051 06:02:40.676850 CH0 RK1: MR19=403, MR18=AF1
3052 06:02:40.683882 CH0_RK1: MR19=0x403, MR18=0xAF1, DQSOSC=406, MR23=63, INC=39, DEC=26
3053 06:02:40.687129 [RxdqsGatingPostProcess] freq 1200
3054 06:02:40.690385 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3055 06:02:40.693508 best DQS0 dly(2T, 0.5T) = (0, 11)
3056 06:02:40.697032 best DQS1 dly(2T, 0.5T) = (0, 11)
3057 06:02:40.700234 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3058 06:02:40.703842 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3059 06:02:40.706840 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 06:02:40.710293 best DQS1 dly(2T, 0.5T) = (0, 11)
3061 06:02:40.714052 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 06:02:40.716956 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3063 06:02:40.720348 Pre-setting of DQS Precalculation
3064 06:02:40.723839 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3065 06:02:40.726874 ==
3066 06:02:40.727455 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 06:02:40.733809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 06:02:40.734426 ==
3069 06:02:40.737068 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3070 06:02:40.743643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3071 06:02:40.752881 [CA 0] Center 37 (7~68) winsize 62
3072 06:02:40.756224 [CA 1] Center 37 (7~68) winsize 62
3073 06:02:40.759223 [CA 2] Center 35 (5~65) winsize 61
3074 06:02:40.762789 [CA 3] Center 34 (4~65) winsize 62
3075 06:02:40.766154 [CA 4] Center 34 (4~64) winsize 61
3076 06:02:40.769405 [CA 5] Center 33 (3~64) winsize 62
3077 06:02:40.769877
3078 06:02:40.772885 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3079 06:02:40.773466
3080 06:02:40.776592 [CATrainingPosCal] consider 1 rank data
3081 06:02:40.779322 u2DelayCellTimex100 = 270/100 ps
3082 06:02:40.782700 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3083 06:02:40.786002 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3084 06:02:40.792545 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3085 06:02:40.795679 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3086 06:02:40.799225 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3087 06:02:40.802519 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3088 06:02:40.802996
3089 06:02:40.806148 CA PerBit enable=1, Macro0, CA PI delay=33
3090 06:02:40.806726
3091 06:02:40.809488 [CBTSetCACLKResult] CA Dly = 33
3092 06:02:40.810118 CS Dly: 5 (0~36)
3093 06:02:40.810508 ==
3094 06:02:40.812835 Dram Type= 6, Freq= 0, CH_1, rank 1
3095 06:02:40.819097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 06:02:40.819656 ==
3097 06:02:40.822772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 06:02:40.829171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3099 06:02:40.838621 [CA 0] Center 38 (8~68) winsize 61
3100 06:02:40.841367 [CA 1] Center 38 (7~69) winsize 63
3101 06:02:40.844932 [CA 2] Center 35 (5~66) winsize 62
3102 06:02:40.848760 [CA 3] Center 35 (5~65) winsize 61
3103 06:02:40.851588 [CA 4] Center 35 (5~65) winsize 61
3104 06:02:40.854896 [CA 5] Center 34 (4~64) winsize 61
3105 06:02:40.855482
3106 06:02:40.858337 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3107 06:02:40.858907
3108 06:02:40.861479 [CATrainingPosCal] consider 2 rank data
3109 06:02:40.864843 u2DelayCellTimex100 = 270/100 ps
3110 06:02:40.868236 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3111 06:02:40.871678 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3112 06:02:40.878220 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3113 06:02:40.881552 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3114 06:02:40.884583 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3115 06:02:40.888139 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3116 06:02:40.888709
3117 06:02:40.891758 CA PerBit enable=1, Macro0, CA PI delay=34
3118 06:02:40.892337
3119 06:02:40.894744 [CBTSetCACLKResult] CA Dly = 34
3120 06:02:40.895216 CS Dly: 6 (0~39)
3121 06:02:40.895592
3122 06:02:40.897865 ----->DramcWriteLeveling(PI) begin...
3123 06:02:40.901305 ==
3124 06:02:40.904783 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 06:02:40.908178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 06:02:40.908683 ==
3127 06:02:40.911659 Write leveling (Byte 0): 24 => 24
3128 06:02:40.914707 Write leveling (Byte 1): 28 => 28
3129 06:02:40.917883 DramcWriteLeveling(PI) end<-----
3130 06:02:40.918501
3131 06:02:40.918881 ==
3132 06:02:40.921525 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 06:02:40.924839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 06:02:40.925415 ==
3135 06:02:40.928291 [Gating] SW mode calibration
3136 06:02:40.935007 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3137 06:02:40.937883 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3138 06:02:40.945242 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 06:02:40.948093 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 06:02:40.951646 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 06:02:40.958160 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 06:02:40.961771 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 06:02:40.964923 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3144 06:02:40.971606 0 15 24 | B1->B0 | 3030 2727 | 0 0 | (0 0) (0 1)
3145 06:02:40.974786 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3146 06:02:40.978134 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 06:02:40.984985 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 06:02:40.988446 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 06:02:40.991493 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 06:02:40.998277 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 06:02:41.002046 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 06:02:41.004685 1 0 24 | B1->B0 | 3535 4040 | 0 0 | (0 0) (0 0)
3153 06:02:41.008447 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 06:02:41.014958 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 06:02:41.018202 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 06:02:41.021793 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 06:02:41.028405 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 06:02:41.031816 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 06:02:41.034916 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3160 06:02:41.041861 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3161 06:02:41.045131 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3162 06:02:41.048409 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 06:02:41.055824 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 06:02:41.058466 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 06:02:41.062025 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 06:02:41.068761 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 06:02:41.072043 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 06:02:41.075280 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 06:02:41.082360 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 06:02:41.085688 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 06:02:41.088863 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 06:02:41.091970 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 06:02:41.098827 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 06:02:41.102351 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 06:02:41.105279 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 06:02:41.112476 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3177 06:02:41.115418 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3178 06:02:41.119479 Total UI for P1: 0, mck2ui 16
3179 06:02:41.122228 best dqsien dly found for B0: ( 1, 3, 24)
3180 06:02:41.125547 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 06:02:41.128845 Total UI for P1: 0, mck2ui 16
3182 06:02:41.132219 best dqsien dly found for B1: ( 1, 3, 26)
3183 06:02:41.135595 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3184 06:02:41.139028 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3185 06:02:41.139608
3186 06:02:41.145607 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3187 06:02:41.148457 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3188 06:02:41.148932 [Gating] SW calibration Done
3189 06:02:41.151991 ==
3190 06:02:41.152464 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 06:02:41.158953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 06:02:41.159519 ==
3193 06:02:41.159900 RX Vref Scan: 0
3194 06:02:41.160248
3195 06:02:41.162177 RX Vref 0 -> 0, step: 1
3196 06:02:41.162647
3197 06:02:41.165499 RX Delay -40 -> 252, step: 8
3198 06:02:41.168881 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3199 06:02:41.172352 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3200 06:02:41.175595 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3201 06:02:41.182173 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3202 06:02:41.185595 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3203 06:02:41.188763 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3204 06:02:41.192163 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3205 06:02:41.195533 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3206 06:02:41.202394 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3207 06:02:41.205437 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3208 06:02:41.208986 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3209 06:02:41.212399 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3210 06:02:41.215643 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3211 06:02:41.222437 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3212 06:02:41.225791 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3213 06:02:41.228769 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3214 06:02:41.229244 ==
3215 06:02:41.232087 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 06:02:41.235288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 06:02:41.235758 ==
3218 06:02:41.239151 DQS Delay:
3219 06:02:41.239724 DQS0 = 0, DQS1 = 0
3220 06:02:41.240103 DQM Delay:
3221 06:02:41.242236 DQM0 = 120, DQM1 = 112
3222 06:02:41.242706 DQ Delay:
3223 06:02:41.245191 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3224 06:02:41.249186 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =123
3225 06:02:41.252259 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3226 06:02:41.258751 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3227 06:02:41.259315
3228 06:02:41.259691
3229 06:02:41.260035 ==
3230 06:02:41.262048 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 06:02:41.265423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 06:02:41.265897 ==
3233 06:02:41.266318
3234 06:02:41.266667
3235 06:02:41.268896 TX Vref Scan disable
3236 06:02:41.269468 == TX Byte 0 ==
3237 06:02:41.275499 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3238 06:02:41.278856 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3239 06:02:41.279436 == TX Byte 1 ==
3240 06:02:41.285768 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3241 06:02:41.288863 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3242 06:02:41.289337 ==
3243 06:02:41.292351 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 06:02:41.295313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 06:02:41.295790 ==
3246 06:02:41.308362 TX Vref=22, minBit 10, minWin=23, winSum=403
3247 06:02:41.311684 TX Vref=24, minBit 11, minWin=24, winSum=413
3248 06:02:41.314842 TX Vref=26, minBit 8, minWin=25, winSum=411
3249 06:02:41.318512 TX Vref=28, minBit 10, minWin=25, winSum=422
3250 06:02:41.321607 TX Vref=30, minBit 11, minWin=25, winSum=423
3251 06:02:41.328625 TX Vref=32, minBit 11, minWin=25, winSum=422
3252 06:02:41.331704 [TxChooseVref] Worse bit 11, Min win 25, Win sum 423, Final Vref 30
3253 06:02:41.332178
3254 06:02:41.334869 Final TX Range 1 Vref 30
3255 06:02:41.335349
3256 06:02:41.335721 ==
3257 06:02:41.338565 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 06:02:41.341698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 06:02:41.345106 ==
3260 06:02:41.345706
3261 06:02:41.346124
3262 06:02:41.346472 TX Vref Scan disable
3263 06:02:41.348523 == TX Byte 0 ==
3264 06:02:41.351757 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3265 06:02:41.355326 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3266 06:02:41.358429 == TX Byte 1 ==
3267 06:02:41.361977 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3268 06:02:41.365181 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3269 06:02:41.369076
3270 06:02:41.369645 [DATLAT]
3271 06:02:41.370068 Freq=1200, CH1 RK0
3272 06:02:41.370428
3273 06:02:41.371659 DATLAT Default: 0xd
3274 06:02:41.372123 0, 0xFFFF, sum = 0
3275 06:02:41.375444 1, 0xFFFF, sum = 0
3276 06:02:41.376023 2, 0xFFFF, sum = 0
3277 06:02:41.378471 3, 0xFFFF, sum = 0
3278 06:02:41.378950 4, 0xFFFF, sum = 0
3279 06:02:41.381882 5, 0xFFFF, sum = 0
3280 06:02:41.385137 6, 0xFFFF, sum = 0
3281 06:02:41.385614 7, 0xFFFF, sum = 0
3282 06:02:41.388336 8, 0xFFFF, sum = 0
3283 06:02:41.388812 9, 0xFFFF, sum = 0
3284 06:02:41.392175 10, 0xFFFF, sum = 0
3285 06:02:41.392762 11, 0xFFFF, sum = 0
3286 06:02:41.395471 12, 0x0, sum = 1
3287 06:02:41.396062 13, 0x0, sum = 2
3288 06:02:41.398802 14, 0x0, sum = 3
3289 06:02:41.399388 15, 0x0, sum = 4
3290 06:02:41.399769 best_step = 13
3291 06:02:41.400115
3292 06:02:41.401751 ==
3293 06:02:41.402263 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 06:02:41.408738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 06:02:41.409202 ==
3296 06:02:41.409565 RX Vref Scan: 1
3297 06:02:41.409901
3298 06:02:41.411883 Set Vref Range= 32 -> 127
3299 06:02:41.412340
3300 06:02:41.415291 RX Vref 32 -> 127, step: 1
3301 06:02:41.415749
3302 06:02:41.418510 RX Delay -13 -> 252, step: 4
3303 06:02:41.418969
3304 06:02:41.422000 Set Vref, RX VrefLevel [Byte0]: 32
3305 06:02:41.424766 [Byte1]: 32
3306 06:02:41.425088
3307 06:02:41.428568 Set Vref, RX VrefLevel [Byte0]: 33
3308 06:02:41.431873 [Byte1]: 33
3309 06:02:41.432198
3310 06:02:41.435175 Set Vref, RX VrefLevel [Byte0]: 34
3311 06:02:41.438425 [Byte1]: 34
3312 06:02:41.442723
3313 06:02:41.443147 Set Vref, RX VrefLevel [Byte0]: 35
3314 06:02:41.445821 [Byte1]: 35
3315 06:02:41.450795
3316 06:02:41.451215 Set Vref, RX VrefLevel [Byte0]: 36
3317 06:02:41.453837 [Byte1]: 36
3318 06:02:41.458860
3319 06:02:41.459288 Set Vref, RX VrefLevel [Byte0]: 37
3320 06:02:41.461656 [Byte1]: 37
3321 06:02:41.466045
3322 06:02:41.466367 Set Vref, RX VrefLevel [Byte0]: 38
3323 06:02:41.469867 [Byte1]: 38
3324 06:02:41.474241
3325 06:02:41.474562 Set Vref, RX VrefLevel [Byte0]: 39
3326 06:02:41.477745 [Byte1]: 39
3327 06:02:41.482354
3328 06:02:41.482876 Set Vref, RX VrefLevel [Byte0]: 40
3329 06:02:41.486031 [Byte1]: 40
3330 06:02:41.490495
3331 06:02:41.491013 Set Vref, RX VrefLevel [Byte0]: 41
3332 06:02:41.493349 [Byte1]: 41
3333 06:02:41.498479
3334 06:02:41.499036 Set Vref, RX VrefLevel [Byte0]: 42
3335 06:02:41.501605 [Byte1]: 42
3336 06:02:41.506105
3337 06:02:41.506670 Set Vref, RX VrefLevel [Byte0]: 43
3338 06:02:41.509161 [Byte1]: 43
3339 06:02:41.513635
3340 06:02:41.514118 Set Vref, RX VrefLevel [Byte0]: 44
3341 06:02:41.517198 [Byte1]: 44
3342 06:02:41.521791
3343 06:02:41.522388 Set Vref, RX VrefLevel [Byte0]: 45
3344 06:02:41.525036 [Byte1]: 45
3345 06:02:41.529312
3346 06:02:41.529768 Set Vref, RX VrefLevel [Byte0]: 46
3347 06:02:41.533148 [Byte1]: 46
3348 06:02:41.537834
3349 06:02:41.538433 Set Vref, RX VrefLevel [Byte0]: 47
3350 06:02:41.540917 [Byte1]: 47
3351 06:02:41.545234
3352 06:02:41.545794 Set Vref, RX VrefLevel [Byte0]: 48
3353 06:02:41.548706 [Byte1]: 48
3354 06:02:41.553045
3355 06:02:41.553505 Set Vref, RX VrefLevel [Byte0]: 49
3356 06:02:41.556761 [Byte1]: 49
3357 06:02:41.561344
3358 06:02:41.561916 Set Vref, RX VrefLevel [Byte0]: 50
3359 06:02:41.564488 [Byte1]: 50
3360 06:02:41.568993
3361 06:02:41.569556 Set Vref, RX VrefLevel [Byte0]: 51
3362 06:02:41.572487 [Byte1]: 51
3363 06:02:41.576999
3364 06:02:41.577682 Set Vref, RX VrefLevel [Byte0]: 52
3365 06:02:41.580436 [Byte1]: 52
3366 06:02:41.584656
3367 06:02:41.585140 Set Vref, RX VrefLevel [Byte0]: 53
3368 06:02:41.588411 [Byte1]: 53
3369 06:02:41.592760
3370 06:02:41.593317 Set Vref, RX VrefLevel [Byte0]: 54
3371 06:02:41.595922 [Byte1]: 54
3372 06:02:41.600618
3373 06:02:41.601076 Set Vref, RX VrefLevel [Byte0]: 55
3374 06:02:41.603723 [Byte1]: 55
3375 06:02:41.608109
3376 06:02:41.608564 Set Vref, RX VrefLevel [Byte0]: 56
3377 06:02:41.612430 [Byte1]: 56
3378 06:02:41.616393
3379 06:02:41.616955 Set Vref, RX VrefLevel [Byte0]: 57
3380 06:02:41.619601 [Byte1]: 57
3381 06:02:41.624287
3382 06:02:41.624847 Set Vref, RX VrefLevel [Byte0]: 58
3383 06:02:41.627442 [Byte1]: 58
3384 06:02:41.632476
3385 06:02:41.632935 Set Vref, RX VrefLevel [Byte0]: 59
3386 06:02:41.635212 [Byte1]: 59
3387 06:02:41.640133
3388 06:02:41.640698 Set Vref, RX VrefLevel [Byte0]: 60
3389 06:02:41.643107 [Byte1]: 60
3390 06:02:41.647937
3391 06:02:41.648500 Set Vref, RX VrefLevel [Byte0]: 61
3392 06:02:41.651287 [Byte1]: 61
3393 06:02:41.655743
3394 06:02:41.656303 Set Vref, RX VrefLevel [Byte0]: 62
3395 06:02:41.658889 [Byte1]: 62
3396 06:02:41.663471
3397 06:02:41.663931 Set Vref, RX VrefLevel [Byte0]: 63
3398 06:02:41.666834 [Byte1]: 63
3399 06:02:41.671276
3400 06:02:41.671743 Set Vref, RX VrefLevel [Byte0]: 64
3401 06:02:41.674864 [Byte1]: 64
3402 06:02:41.679170
3403 06:02:41.679626 Set Vref, RX VrefLevel [Byte0]: 65
3404 06:02:41.682472 [Byte1]: 65
3405 06:02:41.687008
3406 06:02:41.687464 Set Vref, RX VrefLevel [Byte0]: 66
3407 06:02:41.690382 [Byte1]: 66
3408 06:02:41.695142
3409 06:02:41.695672 Set Vref, RX VrefLevel [Byte0]: 67
3410 06:02:41.698158 [Byte1]: 67
3411 06:02:41.703361
3412 06:02:41.703941 Final RX Vref Byte 0 = 54 to rank0
3413 06:02:41.706212 Final RX Vref Byte 1 = 53 to rank0
3414 06:02:41.709757 Final RX Vref Byte 0 = 54 to rank1
3415 06:02:41.713484 Final RX Vref Byte 1 = 53 to rank1==
3416 06:02:41.716584 Dram Type= 6, Freq= 0, CH_1, rank 0
3417 06:02:41.719892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3418 06:02:41.723163 ==
3419 06:02:41.723636 DQS Delay:
3420 06:02:41.724006 DQS0 = 0, DQS1 = 0
3421 06:02:41.726683 DQM Delay:
3422 06:02:41.727260 DQM0 = 119, DQM1 = 112
3423 06:02:41.730244 DQ Delay:
3424 06:02:41.733572 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3425 06:02:41.736370 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =118
3426 06:02:41.740188 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3427 06:02:41.742846 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3428 06:02:41.743321
3429 06:02:41.743691
3430 06:02:41.750127 [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3431 06:02:41.752994 CH1 RK0: MR19=404, MR18=316
3432 06:02:41.759996 CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27
3433 06:02:41.760572
3434 06:02:41.763340 ----->DramcWriteLeveling(PI) begin...
3435 06:02:41.763819 ==
3436 06:02:41.766479 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 06:02:41.769752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 06:02:41.770280 ==
3439 06:02:41.773238 Write leveling (Byte 0): 25 => 25
3440 06:02:41.776395 Write leveling (Byte 1): 28 => 28
3441 06:02:41.779854 DramcWriteLeveling(PI) end<-----
3442 06:02:41.780332
3443 06:02:41.780702 ==
3444 06:02:41.782983 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 06:02:41.786532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3446 06:02:41.789600 ==
3447 06:02:41.790108 [Gating] SW mode calibration
3448 06:02:41.799693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3449 06:02:41.803245 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3450 06:02:41.806840 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 06:02:41.813435 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 06:02:41.816400 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 06:02:41.820163 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 06:02:41.827224 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 06:02:41.830244 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 06:02:41.833187 0 15 24 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 0)
3457 06:02:41.840040 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 0)
3458 06:02:41.843637 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 06:02:41.846872 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 06:02:41.850334 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 06:02:41.857115 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 06:02:41.860267 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 06:02:41.863419 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 06:02:41.870475 1 0 24 | B1->B0 | 3d3d 2828 | 0 0 | (0 0) (0 0)
3465 06:02:41.873671 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 06:02:41.876665 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 06:02:41.883646 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 06:02:41.886695 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 06:02:41.890305 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 06:02:41.896963 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 06:02:41.899964 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 06:02:41.903473 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3473 06:02:41.910382 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3474 06:02:41.913982 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 06:02:41.916681 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 06:02:41.923474 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 06:02:41.926849 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 06:02:41.930051 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 06:02:41.936555 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 06:02:41.939731 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 06:02:41.943602 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 06:02:41.949932 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 06:02:41.953347 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 06:02:41.956693 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 06:02:41.963409 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 06:02:41.966623 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 06:02:41.969803 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 06:02:41.976702 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3489 06:02:41.979766 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3490 06:02:41.983015 Total UI for P1: 0, mck2ui 16
3491 06:02:41.986574 best dqsien dly found for B0: ( 1, 3, 24)
3492 06:02:41.989751 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 06:02:41.993122 Total UI for P1: 0, mck2ui 16
3494 06:02:41.996345 best dqsien dly found for B1: ( 1, 3, 26)
3495 06:02:41.999924 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3496 06:02:42.003032 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3497 06:02:42.003519
3498 06:02:42.006308 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3499 06:02:42.013106 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3500 06:02:42.013671 [Gating] SW calibration Done
3501 06:02:42.014091 ==
3502 06:02:42.015979 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 06:02:42.022874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3504 06:02:42.023434 ==
3505 06:02:42.023815 RX Vref Scan: 0
3506 06:02:42.024166
3507 06:02:42.026300 RX Vref 0 -> 0, step: 1
3508 06:02:42.026867
3509 06:02:42.029195 RX Delay -40 -> 252, step: 8
3510 06:02:42.032799 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3511 06:02:42.036098 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3512 06:02:42.039682 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3513 06:02:42.046535 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3514 06:02:42.049373 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3515 06:02:42.053368 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3516 06:02:42.056042 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3517 06:02:42.059449 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3518 06:02:42.062922 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3519 06:02:42.069645 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3520 06:02:42.072704 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3521 06:02:42.076375 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3522 06:02:42.079592 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3523 06:02:42.082598 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3524 06:02:42.089357 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3525 06:02:42.092975 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3526 06:02:42.093556 ==
3527 06:02:42.095849 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 06:02:42.099718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 06:02:42.100291 ==
3530 06:02:42.102621 DQS Delay:
3531 06:02:42.103086 DQS0 = 0, DQS1 = 0
3532 06:02:42.103453 DQM Delay:
3533 06:02:42.106324 DQM0 = 119, DQM1 = 113
3534 06:02:42.106888 DQ Delay:
3535 06:02:42.109813 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3536 06:02:42.113102 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3537 06:02:42.115952 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3538 06:02:42.122799 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3539 06:02:42.123377
3540 06:02:42.123754
3541 06:02:42.124103 ==
3542 06:02:42.126117 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 06:02:42.129380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 06:02:42.129997 ==
3545 06:02:42.130388
3546 06:02:42.130742
3547 06:02:42.132651 TX Vref Scan disable
3548 06:02:42.133124 == TX Byte 0 ==
3549 06:02:42.139273 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3550 06:02:42.142459 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3551 06:02:42.143041 == TX Byte 1 ==
3552 06:02:42.149442 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3553 06:02:42.152846 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3554 06:02:42.153424 ==
3555 06:02:42.155531 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 06:02:42.159368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 06:02:42.159951 ==
3558 06:02:42.171965 TX Vref=22, minBit 1, minWin=25, winSum=414
3559 06:02:42.175228 TX Vref=24, minBit 9, minWin=25, winSum=420
3560 06:02:42.178466 TX Vref=26, minBit 1, minWin=26, winSum=426
3561 06:02:42.181639 TX Vref=28, minBit 1, minWin=26, winSum=430
3562 06:02:42.185297 TX Vref=30, minBit 10, minWin=25, winSum=426
3563 06:02:42.191790 TX Vref=32, minBit 0, minWin=26, winSum=425
3564 06:02:42.194966 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
3565 06:02:42.195447
3566 06:02:42.198439 Final TX Range 1 Vref 28
3567 06:02:42.198935
3568 06:02:42.199312 ==
3569 06:02:42.201422 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 06:02:42.204843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 06:02:42.205323 ==
3572 06:02:42.208443
3573 06:02:42.208912
3574 06:02:42.209279 TX Vref Scan disable
3575 06:02:42.211759 == TX Byte 0 ==
3576 06:02:42.214601 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3577 06:02:42.221173 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3578 06:02:42.221506 == TX Byte 1 ==
3579 06:02:42.224918 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3580 06:02:42.231363 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3581 06:02:42.231694
3582 06:02:42.231956 [DATLAT]
3583 06:02:42.232195 Freq=1200, CH1 RK1
3584 06:02:42.232433
3585 06:02:42.234547 DATLAT Default: 0xd
3586 06:02:42.234873 0, 0xFFFF, sum = 0
3587 06:02:42.237882 1, 0xFFFF, sum = 0
3588 06:02:42.241472 2, 0xFFFF, sum = 0
3589 06:02:42.241807 3, 0xFFFF, sum = 0
3590 06:02:42.244768 4, 0xFFFF, sum = 0
3591 06:02:42.245102 5, 0xFFFF, sum = 0
3592 06:02:42.248080 6, 0xFFFF, sum = 0
3593 06:02:42.248414 7, 0xFFFF, sum = 0
3594 06:02:42.251630 8, 0xFFFF, sum = 0
3595 06:02:42.251964 9, 0xFFFF, sum = 0
3596 06:02:42.254706 10, 0xFFFF, sum = 0
3597 06:02:42.255039 11, 0xFFFF, sum = 0
3598 06:02:42.257891 12, 0x0, sum = 1
3599 06:02:42.258251 13, 0x0, sum = 2
3600 06:02:42.261694 14, 0x0, sum = 3
3601 06:02:42.262058 15, 0x0, sum = 4
3602 06:02:42.262332 best_step = 13
3603 06:02:42.264747
3604 06:02:42.265075 ==
3605 06:02:42.268110 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 06:02:42.271148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 06:02:42.271623 ==
3608 06:02:42.271970 RX Vref Scan: 0
3609 06:02:42.272286
3610 06:02:42.274802 RX Vref 0 -> 0, step: 1
3611 06:02:42.275235
3612 06:02:42.278239 RX Delay -13 -> 252, step: 4
3613 06:02:42.281279 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3614 06:02:42.288287 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3615 06:02:42.291384 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3616 06:02:42.294522 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3617 06:02:42.298259 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3618 06:02:42.301747 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3619 06:02:42.308334 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3620 06:02:42.311340 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3621 06:02:42.314922 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3622 06:02:42.318012 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3623 06:02:42.321519 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3624 06:02:42.327768 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3625 06:02:42.331503 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3626 06:02:42.334509 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3627 06:02:42.338219 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3628 06:02:42.341763 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3629 06:02:42.344426 ==
3630 06:02:42.347760 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 06:02:42.351710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 06:02:42.352307 ==
3633 06:02:42.352697 DQS Delay:
3634 06:02:42.354379 DQS0 = 0, DQS1 = 0
3635 06:02:42.354854 DQM Delay:
3636 06:02:42.358210 DQM0 = 119, DQM1 = 113
3637 06:02:42.358795 DQ Delay:
3638 06:02:42.361535 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3639 06:02:42.364576 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3640 06:02:42.367872 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3641 06:02:42.371161 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3642 06:02:42.371637
3643 06:02:42.372033
3644 06:02:42.381346 [DQSOSCAuto] RK1, (LSB)MR18= 0xaee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3645 06:02:42.381933 CH1 RK1: MR19=403, MR18=AEE
3646 06:02:42.387661 CH1_RK1: MR19=0x403, MR18=0xAEE, DQSOSC=406, MR23=63, INC=39, DEC=26
3647 06:02:42.391105 [RxdqsGatingPostProcess] freq 1200
3648 06:02:42.397709 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3649 06:02:42.400973 best DQS0 dly(2T, 0.5T) = (0, 11)
3650 06:02:42.404585 best DQS1 dly(2T, 0.5T) = (0, 11)
3651 06:02:42.407743 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3652 06:02:42.411062 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3653 06:02:42.414595 best DQS0 dly(2T, 0.5T) = (0, 11)
3654 06:02:42.417661 best DQS1 dly(2T, 0.5T) = (0, 11)
3655 06:02:42.421036 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3656 06:02:42.421617 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3657 06:02:42.424209 Pre-setting of DQS Precalculation
3658 06:02:42.431225 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3659 06:02:42.437665 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3660 06:02:42.444328 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3661 06:02:42.444949
3662 06:02:42.445334
3663 06:02:42.447307 [Calibration Summary] 2400 Mbps
3664 06:02:42.450990 CH 0, Rank 0
3665 06:02:42.451573 SW Impedance : PASS
3666 06:02:42.454460 DUTY Scan : NO K
3667 06:02:42.457400 ZQ Calibration : PASS
3668 06:02:42.457878 Jitter Meter : NO K
3669 06:02:42.460755 CBT Training : PASS
3670 06:02:42.461337 Write leveling : PASS
3671 06:02:42.464024 RX DQS gating : PASS
3672 06:02:42.467684 RX DQ/DQS(RDDQC) : PASS
3673 06:02:42.468265 TX DQ/DQS : PASS
3674 06:02:42.470877 RX DATLAT : PASS
3675 06:02:42.473769 RX DQ/DQS(Engine): PASS
3676 06:02:42.474352 TX OE : NO K
3677 06:02:42.477052 All Pass.
3678 06:02:42.477562
3679 06:02:42.478171 CH 0, Rank 1
3680 06:02:42.480309 SW Impedance : PASS
3681 06:02:42.480781 DUTY Scan : NO K
3682 06:02:42.483859 ZQ Calibration : PASS
3683 06:02:42.487341 Jitter Meter : NO K
3684 06:02:42.487819 CBT Training : PASS
3685 06:02:42.490429 Write leveling : PASS
3686 06:02:42.493927 RX DQS gating : PASS
3687 06:02:42.494538 RX DQ/DQS(RDDQC) : PASS
3688 06:02:42.497505 TX DQ/DQS : PASS
3689 06:02:42.501151 RX DATLAT : PASS
3690 06:02:42.501729 RX DQ/DQS(Engine): PASS
3691 06:02:42.503722 TX OE : NO K
3692 06:02:42.504196 All Pass.
3693 06:02:42.504574
3694 06:02:42.507217 CH 1, Rank 0
3695 06:02:42.507786 SW Impedance : PASS
3696 06:02:42.510396 DUTY Scan : NO K
3697 06:02:42.513723 ZQ Calibration : PASS
3698 06:02:42.514329 Jitter Meter : NO K
3699 06:02:42.517174 CBT Training : PASS
3700 06:02:42.517737 Write leveling : PASS
3701 06:02:42.520827 RX DQS gating : PASS
3702 06:02:42.523640 RX DQ/DQS(RDDQC) : PASS
3703 06:02:42.524116 TX DQ/DQS : PASS
3704 06:02:42.527185 RX DATLAT : PASS
3705 06:02:42.530482 RX DQ/DQS(Engine): PASS
3706 06:02:42.530955 TX OE : NO K
3707 06:02:42.533651 All Pass.
3708 06:02:42.534142
3709 06:02:42.534677 CH 1, Rank 1
3710 06:02:42.536777 SW Impedance : PASS
3711 06:02:42.537264 DUTY Scan : NO K
3712 06:02:42.540121 ZQ Calibration : PASS
3713 06:02:42.543907 Jitter Meter : NO K
3714 06:02:42.544490 CBT Training : PASS
3715 06:02:42.546856 Write leveling : PASS
3716 06:02:42.550824 RX DQS gating : PASS
3717 06:02:42.551392 RX DQ/DQS(RDDQC) : PASS
3718 06:02:42.553933 TX DQ/DQS : PASS
3719 06:02:42.556804 RX DATLAT : PASS
3720 06:02:42.557449 RX DQ/DQS(Engine): PASS
3721 06:02:42.560177 TX OE : NO K
3722 06:02:42.560744 All Pass.
3723 06:02:42.561123
3724 06:02:42.563931 DramC Write-DBI off
3725 06:02:42.567016 PER_BANK_REFRESH: Hybrid Mode
3726 06:02:42.567587 TX_TRACKING: ON
3727 06:02:42.576771 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3728 06:02:42.580028 [FAST_K] Save calibration result to emmc
3729 06:02:42.583533 dramc_set_vcore_voltage set vcore to 650000
3730 06:02:42.586506 Read voltage for 600, 5
3731 06:02:42.586981 Vio18 = 0
3732 06:02:42.587354 Vcore = 650000
3733 06:02:42.589822 Vdram = 0
3734 06:02:42.590327 Vddq = 0
3735 06:02:42.590703 Vmddr = 0
3736 06:02:42.596575 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3737 06:02:42.600145 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3738 06:02:42.603243 MEM_TYPE=3, freq_sel=19
3739 06:02:42.606472 sv_algorithm_assistance_LP4_1600
3740 06:02:42.610095 ============ PULL DRAM RESETB DOWN ============
3741 06:02:42.613353 ========== PULL DRAM RESETB DOWN end =========
3742 06:02:42.619766 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3743 06:02:42.623140 ===================================
3744 06:02:42.623618 LPDDR4 DRAM CONFIGURATION
3745 06:02:42.626497 ===================================
3746 06:02:42.629588 EX_ROW_EN[0] = 0x0
3747 06:02:42.632931 EX_ROW_EN[1] = 0x0
3748 06:02:42.633416 LP4Y_EN = 0x0
3749 06:02:42.636232 WORK_FSP = 0x0
3750 06:02:42.636893 WL = 0x2
3751 06:02:42.639724 RL = 0x2
3752 06:02:42.640301 BL = 0x2
3753 06:02:42.643037 RPST = 0x0
3754 06:02:42.643510 RD_PRE = 0x0
3755 06:02:42.646323 WR_PRE = 0x1
3756 06:02:42.646797 WR_PST = 0x0
3757 06:02:42.649851 DBI_WR = 0x0
3758 06:02:42.650380 DBI_RD = 0x0
3759 06:02:42.653069 OTF = 0x1
3760 06:02:42.656524 ===================================
3761 06:02:42.659713 ===================================
3762 06:02:42.660403 ANA top config
3763 06:02:42.663535 ===================================
3764 06:02:42.666457 DLL_ASYNC_EN = 0
3765 06:02:42.669825 ALL_SLAVE_EN = 1
3766 06:02:42.672998 NEW_RANK_MODE = 1
3767 06:02:42.673504 DLL_IDLE_MODE = 1
3768 06:02:42.676312 LP45_APHY_COMB_EN = 1
3769 06:02:42.680130 TX_ODT_DIS = 1
3770 06:02:42.682691 NEW_8X_MODE = 1
3771 06:02:42.686048 ===================================
3772 06:02:42.689543 ===================================
3773 06:02:42.692872 data_rate = 1200
3774 06:02:42.693447 CKR = 1
3775 06:02:42.696635 DQ_P2S_RATIO = 8
3776 06:02:42.699579 ===================================
3777 06:02:42.702693 CA_P2S_RATIO = 8
3778 06:02:42.706527 DQ_CA_OPEN = 0
3779 06:02:42.709760 DQ_SEMI_OPEN = 0
3780 06:02:42.713138 CA_SEMI_OPEN = 0
3781 06:02:42.713707 CA_FULL_RATE = 0
3782 06:02:42.716332 DQ_CKDIV4_EN = 1
3783 06:02:42.719246 CA_CKDIV4_EN = 1
3784 06:02:42.722858 CA_PREDIV_EN = 0
3785 06:02:42.726482 PH8_DLY = 0
3786 06:02:42.729575 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3787 06:02:42.730162 DQ_AAMCK_DIV = 4
3788 06:02:42.733043 CA_AAMCK_DIV = 4
3789 06:02:42.735894 CA_ADMCK_DIV = 4
3790 06:02:42.739421 DQ_TRACK_CA_EN = 0
3791 06:02:42.742532 CA_PICK = 600
3792 06:02:42.745842 CA_MCKIO = 600
3793 06:02:42.746358 MCKIO_SEMI = 0
3794 06:02:42.749176 PLL_FREQ = 2288
3795 06:02:42.752817 DQ_UI_PI_RATIO = 32
3796 06:02:42.755994 CA_UI_PI_RATIO = 0
3797 06:02:42.759133 ===================================
3798 06:02:42.762802 ===================================
3799 06:02:42.766104 memory_type:LPDDR4
3800 06:02:42.766670 GP_NUM : 10
3801 06:02:42.769583 SRAM_EN : 1
3802 06:02:42.772470 MD32_EN : 0
3803 06:02:42.776099 ===================================
3804 06:02:42.776669 [ANA_INIT] >>>>>>>>>>>>>>
3805 06:02:42.779674 <<<<<< [CONFIGURE PHASE]: ANA_TX
3806 06:02:42.782554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3807 06:02:42.785794 ===================================
3808 06:02:42.789372 data_rate = 1200,PCW = 0X5800
3809 06:02:42.792817 ===================================
3810 06:02:42.796091 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3811 06:02:42.802392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3812 06:02:42.805987 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 06:02:42.812727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3814 06:02:42.816073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3815 06:02:42.819116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3816 06:02:42.819596 [ANA_INIT] flow start
3817 06:02:42.822488 [ANA_INIT] PLL >>>>>>>>
3818 06:02:42.826089 [ANA_INIT] PLL <<<<<<<<
3819 06:02:42.826651 [ANA_INIT] MIDPI >>>>>>>>
3820 06:02:42.829338 [ANA_INIT] MIDPI <<<<<<<<
3821 06:02:42.832582 [ANA_INIT] DLL >>>>>>>>
3822 06:02:42.833143 [ANA_INIT] flow end
3823 06:02:42.839507 ============ LP4 DIFF to SE enter ============
3824 06:02:42.842210 ============ LP4 DIFF to SE exit ============
3825 06:02:42.845904 [ANA_INIT] <<<<<<<<<<<<<
3826 06:02:42.849028 [Flow] Enable top DCM control >>>>>
3827 06:02:42.852720 [Flow] Enable top DCM control <<<<<
3828 06:02:42.853298 Enable DLL master slave shuffle
3829 06:02:42.858812 ==============================================================
3830 06:02:42.862178 Gating Mode config
3831 06:02:42.865256 ==============================================================
3832 06:02:42.868653 Config description:
3833 06:02:42.878730 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3834 06:02:42.885495 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3835 06:02:42.889156 SELPH_MODE 0: By rank 1: By Phase
3836 06:02:42.895226 ==============================================================
3837 06:02:42.898476 GAT_TRACK_EN = 1
3838 06:02:42.901936 RX_GATING_MODE = 2
3839 06:02:42.905649 RX_GATING_TRACK_MODE = 2
3840 06:02:42.908745 SELPH_MODE = 1
3841 06:02:42.912400 PICG_EARLY_EN = 1
3842 06:02:42.912968 VALID_LAT_VALUE = 1
3843 06:02:42.918815 ==============================================================
3844 06:02:42.921988 Enter into Gating configuration >>>>
3845 06:02:42.925303 Exit from Gating configuration <<<<
3846 06:02:42.928856 Enter into DVFS_PRE_config >>>>>
3847 06:02:42.938388 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3848 06:02:42.942122 Exit from DVFS_PRE_config <<<<<
3849 06:02:42.945328 Enter into PICG configuration >>>>
3850 06:02:42.948229 Exit from PICG configuration <<<<
3851 06:02:42.952029 [RX_INPUT] configuration >>>>>
3852 06:02:42.955009 [RX_INPUT] configuration <<<<<
3853 06:02:42.961825 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3854 06:02:42.964979 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3855 06:02:42.971508 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3856 06:02:42.978323 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3857 06:02:42.985119 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3858 06:02:42.992182 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3859 06:02:42.994721 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3860 06:02:42.998004 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3861 06:02:43.002017 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3862 06:02:43.005088 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3863 06:02:43.011745 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3864 06:02:43.015338 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3865 06:02:43.018654 ===================================
3866 06:02:43.021697 LPDDR4 DRAM CONFIGURATION
3867 06:02:43.024898 ===================================
3868 06:02:43.025469 EX_ROW_EN[0] = 0x0
3869 06:02:43.028708 EX_ROW_EN[1] = 0x0
3870 06:02:43.029275 LP4Y_EN = 0x0
3871 06:02:43.031748 WORK_FSP = 0x0
3872 06:02:43.032322 WL = 0x2
3873 06:02:43.035154 RL = 0x2
3874 06:02:43.035716 BL = 0x2
3875 06:02:43.038095 RPST = 0x0
3876 06:02:43.041487 RD_PRE = 0x0
3877 06:02:43.042099 WR_PRE = 0x1
3878 06:02:43.045148 WR_PST = 0x0
3879 06:02:43.045718 DBI_WR = 0x0
3880 06:02:43.048375 DBI_RD = 0x0
3881 06:02:43.048847 OTF = 0x1
3882 06:02:43.051694 ===================================
3883 06:02:43.055010 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3884 06:02:43.061741 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3885 06:02:43.064539 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3886 06:02:43.067947 ===================================
3887 06:02:43.071342 LPDDR4 DRAM CONFIGURATION
3888 06:02:43.074524 ===================================
3889 06:02:43.075005 EX_ROW_EN[0] = 0x10
3890 06:02:43.078006 EX_ROW_EN[1] = 0x0
3891 06:02:43.078495 LP4Y_EN = 0x0
3892 06:02:43.081027 WORK_FSP = 0x0
3893 06:02:43.081500 WL = 0x2
3894 06:02:43.085104 RL = 0x2
3895 06:02:43.085673 BL = 0x2
3896 06:02:43.088075 RPST = 0x0
3897 06:02:43.088548 RD_PRE = 0x0
3898 06:02:43.091713 WR_PRE = 0x1
3899 06:02:43.092283 WR_PST = 0x0
3900 06:02:43.094866 DBI_WR = 0x0
3901 06:02:43.097739 DBI_RD = 0x0
3902 06:02:43.098311 OTF = 0x1
3903 06:02:43.101415 ===================================
3904 06:02:43.107891 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3905 06:02:43.111621 nWR fixed to 30
3906 06:02:43.114750 [ModeRegInit_LP4] CH0 RK0
3907 06:02:43.115317 [ModeRegInit_LP4] CH0 RK1
3908 06:02:43.118308 [ModeRegInit_LP4] CH1 RK0
3909 06:02:43.120954 [ModeRegInit_LP4] CH1 RK1
3910 06:02:43.121424 match AC timing 17
3911 06:02:43.127920 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3912 06:02:43.131360 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3913 06:02:43.134697 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3914 06:02:43.141257 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3915 06:02:43.144424 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3916 06:02:43.144996 ==
3917 06:02:43.147884 Dram Type= 6, Freq= 0, CH_0, rank 0
3918 06:02:43.151087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3919 06:02:43.151658 ==
3920 06:02:43.158353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3921 06:02:43.164564 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3922 06:02:43.168366 [CA 0] Center 36 (5~67) winsize 63
3923 06:02:43.170991 [CA 1] Center 36 (6~67) winsize 62
3924 06:02:43.174517 [CA 2] Center 34 (4~65) winsize 62
3925 06:02:43.178017 [CA 3] Center 34 (3~65) winsize 63
3926 06:02:43.181298 [CA 4] Center 33 (3~64) winsize 62
3927 06:02:43.184489 [CA 5] Center 33 (3~64) winsize 62
3928 06:02:43.185071
3929 06:02:43.187530 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3930 06:02:43.188012
3931 06:02:43.190877 [CATrainingPosCal] consider 1 rank data
3932 06:02:43.194391 u2DelayCellTimex100 = 270/100 ps
3933 06:02:43.198033 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3934 06:02:43.201200 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3935 06:02:43.204528 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3936 06:02:43.207327 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3937 06:02:43.211093 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3938 06:02:43.217553 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3939 06:02:43.218179
3940 06:02:43.220600 CA PerBit enable=1, Macro0, CA PI delay=33
3941 06:02:43.221083
3942 06:02:43.223960 [CBTSetCACLKResult] CA Dly = 33
3943 06:02:43.224560 CS Dly: 5 (0~36)
3944 06:02:43.225051 ==
3945 06:02:43.227586 Dram Type= 6, Freq= 0, CH_0, rank 1
3946 06:02:43.230790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3947 06:02:43.234190 ==
3948 06:02:43.237368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3949 06:02:43.244501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3950 06:02:43.247457 [CA 0] Center 36 (6~67) winsize 62
3951 06:02:43.251060 [CA 1] Center 36 (6~67) winsize 62
3952 06:02:43.254189 [CA 2] Center 34 (4~65) winsize 62
3953 06:02:43.257110 [CA 3] Center 34 (3~65) winsize 63
3954 06:02:43.261089 [CA 4] Center 34 (3~65) winsize 63
3955 06:02:43.264442 [CA 5] Center 33 (3~64) winsize 62
3956 06:02:43.265028
3957 06:02:43.267461 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3958 06:02:43.268019
3959 06:02:43.270623 [CATrainingPosCal] consider 2 rank data
3960 06:02:43.273840 u2DelayCellTimex100 = 270/100 ps
3961 06:02:43.277202 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3962 06:02:43.280930 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3963 06:02:43.283925 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3964 06:02:43.287254 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3965 06:02:43.290675 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3966 06:02:43.297317 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3967 06:02:43.297795
3968 06:02:43.301044 CA PerBit enable=1, Macro0, CA PI delay=33
3969 06:02:43.301615
3970 06:02:43.304040 [CBTSetCACLKResult] CA Dly = 33
3971 06:02:43.304653 CS Dly: 6 (0~38)
3972 06:02:43.305038
3973 06:02:43.307441 ----->DramcWriteLeveling(PI) begin...
3974 06:02:43.307917 ==
3975 06:02:43.311158 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 06:02:43.317738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 06:02:43.318355 ==
3978 06:02:43.320471 Write leveling (Byte 0): 35 => 35
3979 06:02:43.320942 Write leveling (Byte 1): 32 => 32
3980 06:02:43.323999 DramcWriteLeveling(PI) end<-----
3981 06:02:43.324576
3982 06:02:43.324951 ==
3983 06:02:43.327195 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 06:02:43.334100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 06:02:43.334669 ==
3986 06:02:43.337400 [Gating] SW mode calibration
3987 06:02:43.343996 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3988 06:02:43.347188 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3989 06:02:43.354199 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 06:02:43.357301 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 06:02:43.360761 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3992 06:02:43.367661 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 1)
3993 06:02:43.370581 0 9 16 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
3994 06:02:43.374176 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 06:02:43.380529 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 06:02:43.383573 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 06:02:43.386924 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 06:02:43.390788 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 06:02:43.397294 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 06:02:43.400638 0 10 12 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
4001 06:02:43.403940 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4002 06:02:43.410699 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 06:02:43.414240 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 06:02:43.417476 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 06:02:43.423925 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 06:02:43.426969 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 06:02:43.430656 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 06:02:43.437439 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4009 06:02:43.440404 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4010 06:02:43.443419 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 06:02:43.450503 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 06:02:43.453971 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 06:02:43.457119 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 06:02:43.463771 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 06:02:43.466814 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 06:02:43.470829 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 06:02:43.477122 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 06:02:43.480853 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 06:02:43.483755 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 06:02:43.486900 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 06:02:43.494065 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 06:02:43.497220 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 06:02:43.500381 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4024 06:02:43.507008 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4025 06:02:43.510368 Total UI for P1: 0, mck2ui 16
4026 06:02:43.513703 best dqsien dly found for B0: ( 0, 13, 8)
4027 06:02:43.517377 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 06:02:43.520197 Total UI for P1: 0, mck2ui 16
4029 06:02:43.523394 best dqsien dly found for B1: ( 0, 13, 12)
4030 06:02:43.527126 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4031 06:02:43.530223 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4032 06:02:43.530792
4033 06:02:43.533454 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4034 06:02:43.536730 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4035 06:02:43.540426 [Gating] SW calibration Done
4036 06:02:43.541004 ==
4037 06:02:43.543433 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 06:02:43.550035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 06:02:43.550508 ==
4040 06:02:43.550881 RX Vref Scan: 0
4041 06:02:43.551234
4042 06:02:43.553497 RX Vref 0 -> 0, step: 1
4043 06:02:43.553998
4044 06:02:43.556823 RX Delay -230 -> 252, step: 16
4045 06:02:43.560087 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4046 06:02:43.563652 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4047 06:02:43.566806 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4048 06:02:43.573384 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4049 06:02:43.576853 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4050 06:02:43.580245 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4051 06:02:43.583366 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4052 06:02:43.586845 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4053 06:02:43.593635 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4054 06:02:43.596595 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4055 06:02:43.599995 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4056 06:02:43.603678 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4057 06:02:43.610034 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4058 06:02:43.613129 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4059 06:02:43.616777 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4060 06:02:43.619690 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4061 06:02:43.620157 ==
4062 06:02:43.623452 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 06:02:43.630100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 06:02:43.630671 ==
4065 06:02:43.631049 DQS Delay:
4066 06:02:43.633134 DQS0 = 0, DQS1 = 0
4067 06:02:43.633720 DQM Delay:
4068 06:02:43.636695 DQM0 = 52, DQM1 = 39
4069 06:02:43.637297 DQ Delay:
4070 06:02:43.639711 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4071 06:02:43.643163 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =57
4072 06:02:43.646514 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =25
4073 06:02:43.650013 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4074 06:02:43.650502
4075 06:02:43.650870
4076 06:02:43.651215 ==
4077 06:02:43.653043 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 06:02:43.656161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 06:02:43.656801 ==
4080 06:02:43.657340
4081 06:02:43.657872
4082 06:02:43.659737 TX Vref Scan disable
4083 06:02:43.662918 == TX Byte 0 ==
4084 06:02:43.666343 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4085 06:02:43.669572 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4086 06:02:43.673152 == TX Byte 1 ==
4087 06:02:43.676399 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4088 06:02:43.679900 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4089 06:02:43.680472 ==
4090 06:02:43.682896 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 06:02:43.686060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 06:02:43.689438 ==
4093 06:02:43.690057
4094 06:02:43.690440
4095 06:02:43.690786 TX Vref Scan disable
4096 06:02:43.693440 == TX Byte 0 ==
4097 06:02:43.697240 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4098 06:02:43.703111 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4099 06:02:43.703678 == TX Byte 1 ==
4100 06:02:43.706913 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4101 06:02:43.713197 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4102 06:02:43.713789
4103 06:02:43.714250 [DATLAT]
4104 06:02:43.714611 Freq=600, CH0 RK0
4105 06:02:43.714955
4106 06:02:43.716715 DATLAT Default: 0x9
4107 06:02:43.717185 0, 0xFFFF, sum = 0
4108 06:02:43.720086 1, 0xFFFF, sum = 0
4109 06:02:43.720561 2, 0xFFFF, sum = 0
4110 06:02:43.723107 3, 0xFFFF, sum = 0
4111 06:02:43.726596 4, 0xFFFF, sum = 0
4112 06:02:43.727103 5, 0xFFFF, sum = 0
4113 06:02:43.730359 6, 0xFFFF, sum = 0
4114 06:02:43.730959 7, 0xFFFF, sum = 0
4115 06:02:43.731351 8, 0x0, sum = 1
4116 06:02:43.733610 9, 0x0, sum = 2
4117 06:02:43.734240 10, 0x0, sum = 3
4118 06:02:43.736578 11, 0x0, sum = 4
4119 06:02:43.737061 best_step = 9
4120 06:02:43.737438
4121 06:02:43.737785 ==
4122 06:02:43.739805 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 06:02:43.746539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 06:02:43.747125 ==
4125 06:02:43.747506 RX Vref Scan: 1
4126 06:02:43.747858
4127 06:02:43.749997 RX Vref 0 -> 0, step: 1
4128 06:02:43.750531
4129 06:02:43.754050 RX Delay -179 -> 252, step: 8
4130 06:02:43.754630
4131 06:02:43.756738 Set Vref, RX VrefLevel [Byte0]: 60
4132 06:02:43.759873 [Byte1]: 50
4133 06:02:43.760450
4134 06:02:43.763414 Final RX Vref Byte 0 = 60 to rank0
4135 06:02:43.766786 Final RX Vref Byte 1 = 50 to rank0
4136 06:02:43.769883 Final RX Vref Byte 0 = 60 to rank1
4137 06:02:43.773361 Final RX Vref Byte 1 = 50 to rank1==
4138 06:02:43.776476 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 06:02:43.779936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 06:02:43.780518 ==
4141 06:02:43.783026 DQS Delay:
4142 06:02:43.783504 DQS0 = 0, DQS1 = 0
4143 06:02:43.786235 DQM Delay:
4144 06:02:43.786705 DQM0 = 50, DQM1 = 37
4145 06:02:43.787082 DQ Delay:
4146 06:02:43.789508 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4147 06:02:43.793516 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4148 06:02:43.796489 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4149 06:02:43.800274 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4150 06:02:43.800852
4151 06:02:43.801230
4152 06:02:43.809656 [DQSOSCAuto] RK0, (LSB)MR18= 0x5751, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4153 06:02:43.812868 CH0 RK0: MR19=808, MR18=5751
4154 06:02:43.816589 CH0_RK0: MR19=0x808, MR18=0x5751, DQSOSC=393, MR23=63, INC=169, DEC=113
4155 06:02:43.817178
4156 06:02:43.822903 ----->DramcWriteLeveling(PI) begin...
4157 06:02:43.823387 ==
4158 06:02:43.826556 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 06:02:43.830041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 06:02:43.830618 ==
4161 06:02:43.832880 Write leveling (Byte 0): 34 => 34
4162 06:02:43.836204 Write leveling (Byte 1): 30 => 30
4163 06:02:43.839373 DramcWriteLeveling(PI) end<-----
4164 06:02:43.839861
4165 06:02:43.840275 ==
4166 06:02:43.842810 Dram Type= 6, Freq= 0, CH_0, rank 1
4167 06:02:43.846337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 06:02:43.846921 ==
4169 06:02:43.849537 [Gating] SW mode calibration
4170 06:02:43.856611 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4171 06:02:43.863088 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4172 06:02:43.866633 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4173 06:02:43.869669 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 06:02:43.872880 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 06:02:43.879585 0 9 12 | B1->B0 | 3333 3333 | 1 0 | (1 1) (0 0)
4176 06:02:43.882839 0 9 16 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
4177 06:02:43.886552 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 06:02:43.893049 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 06:02:43.896348 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 06:02:43.899491 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 06:02:43.906250 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 06:02:43.909399 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 06:02:43.912874 0 10 12 | B1->B0 | 2c2c 3535 | 0 0 | (0 0) (0 0)
4184 06:02:43.919572 0 10 16 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
4185 06:02:43.922557 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 06:02:43.926313 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 06:02:43.932593 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 06:02:43.936146 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 06:02:43.939085 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 06:02:43.945862 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 06:02:43.949673 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4192 06:02:43.952912 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 06:02:43.959221 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 06:02:43.962470 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 06:02:43.965797 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 06:02:43.972881 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 06:02:43.976169 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 06:02:43.979100 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 06:02:43.986203 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 06:02:43.989306 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 06:02:43.993079 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 06:02:43.996036 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 06:02:44.002857 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 06:02:44.006206 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 06:02:44.009314 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 06:02:44.016211 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 06:02:44.019515 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4208 06:02:44.022645 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 06:02:44.026132 Total UI for P1: 0, mck2ui 16
4210 06:02:44.029617 best dqsien dly found for B0: ( 0, 13, 14)
4211 06:02:44.032704 Total UI for P1: 0, mck2ui 16
4212 06:02:44.035738 best dqsien dly found for B1: ( 0, 13, 12)
4213 06:02:44.039408 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4214 06:02:44.042849 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4215 06:02:44.043454
4216 06:02:44.049496 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4217 06:02:44.053014 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4218 06:02:44.056253 [Gating] SW calibration Done
4219 06:02:44.056832 ==
4220 06:02:44.059453 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 06:02:44.062559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 06:02:44.063033 ==
4223 06:02:44.063406 RX Vref Scan: 0
4224 06:02:44.063804
4225 06:02:44.065595 RX Vref 0 -> 0, step: 1
4226 06:02:44.066246
4227 06:02:44.069042 RX Delay -230 -> 252, step: 16
4228 06:02:44.072395 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4229 06:02:44.075686 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4230 06:02:44.082487 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4231 06:02:44.085801 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4232 06:02:44.089291 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4233 06:02:44.092592 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4234 06:02:44.099136 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4235 06:02:44.102195 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4236 06:02:44.105976 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4237 06:02:44.109030 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4238 06:02:44.115793 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4239 06:02:44.118793 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4240 06:02:44.122275 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4241 06:02:44.125655 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4242 06:02:44.132121 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4243 06:02:44.135702 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4244 06:02:44.136212 ==
4245 06:02:44.138928 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 06:02:44.142353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 06:02:44.142921 ==
4248 06:02:44.143300 DQS Delay:
4249 06:02:44.145391 DQS0 = 0, DQS1 = 0
4250 06:02:44.145854 DQM Delay:
4251 06:02:44.148886 DQM0 = 49, DQM1 = 42
4252 06:02:44.149351 DQ Delay:
4253 06:02:44.152106 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =49
4254 06:02:44.155398 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4255 06:02:44.158766 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4256 06:02:44.162126 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4257 06:02:44.162618
4258 06:02:44.163023
4259 06:02:44.163382 ==
4260 06:02:44.165352 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 06:02:44.168651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 06:02:44.172353 ==
4263 06:02:44.172932
4264 06:02:44.173307
4265 06:02:44.173648 TX Vref Scan disable
4266 06:02:44.175695 == TX Byte 0 ==
4267 06:02:44.178625 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4268 06:02:44.181869 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4269 06:02:44.185140 == TX Byte 1 ==
4270 06:02:44.188381 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4271 06:02:44.191813 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4272 06:02:44.195531 ==
4273 06:02:44.198684 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 06:02:44.202325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 06:02:44.202912 ==
4276 06:02:44.203294
4277 06:02:44.203644
4278 06:02:44.205259 TX Vref Scan disable
4279 06:02:44.208896 == TX Byte 0 ==
4280 06:02:44.212164 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4281 06:02:44.215113 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4282 06:02:44.218470 == TX Byte 1 ==
4283 06:02:44.222192 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4284 06:02:44.225306 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4285 06:02:44.225882
4286 06:02:44.226351 [DATLAT]
4287 06:02:44.228202 Freq=600, CH0 RK1
4288 06:02:44.228679
4289 06:02:44.229055 DATLAT Default: 0x9
4290 06:02:44.231770 0, 0xFFFF, sum = 0
4291 06:02:44.234829 1, 0xFFFF, sum = 0
4292 06:02:44.235410 2, 0xFFFF, sum = 0
4293 06:02:44.238280 3, 0xFFFF, sum = 0
4294 06:02:44.238748 4, 0xFFFF, sum = 0
4295 06:02:44.241380 5, 0xFFFF, sum = 0
4296 06:02:44.241852 6, 0xFFFF, sum = 0
4297 06:02:44.244826 7, 0xFFFF, sum = 0
4298 06:02:44.245299 8, 0x0, sum = 1
4299 06:02:44.247890 9, 0x0, sum = 2
4300 06:02:44.248356 10, 0x0, sum = 3
4301 06:02:44.248728 11, 0x0, sum = 4
4302 06:02:44.251268 best_step = 9
4303 06:02:44.251733
4304 06:02:44.252098 ==
4305 06:02:44.254495 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 06:02:44.258065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 06:02:44.258532 ==
4308 06:02:44.261460 RX Vref Scan: 0
4309 06:02:44.261920
4310 06:02:44.262313 RX Vref 0 -> 0, step: 1
4311 06:02:44.264719
4312 06:02:44.265177 RX Delay -179 -> 252, step: 8
4313 06:02:44.272464 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4314 06:02:44.275851 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4315 06:02:44.278996 iDelay=205, Bit 2, Center 44 (-107 ~ 196) 304
4316 06:02:44.282236 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4317 06:02:44.285685 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4318 06:02:44.292032 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4319 06:02:44.295691 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4320 06:02:44.298941 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4321 06:02:44.302233 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4322 06:02:44.308758 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4323 06:02:44.312157 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4324 06:02:44.315538 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4325 06:02:44.318818 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4326 06:02:44.325610 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4327 06:02:44.328671 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4328 06:02:44.332137 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4329 06:02:44.332709 ==
4330 06:02:44.335920 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 06:02:44.338481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 06:02:44.338946 ==
4333 06:02:44.342058 DQS Delay:
4334 06:02:44.342590 DQS0 = 0, DQS1 = 0
4335 06:02:44.345372 DQM Delay:
4336 06:02:44.345859 DQM0 = 47, DQM1 = 41
4337 06:02:44.346291 DQ Delay:
4338 06:02:44.348297 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4339 06:02:44.351847 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4340 06:02:44.354990 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4341 06:02:44.358244 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =52
4342 06:02:44.358706
4343 06:02:44.359069
4344 06:02:44.368510 [DQSOSCAuto] RK1, (LSB)MR18= 0x6431, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4345 06:02:44.372348 CH0 RK1: MR19=808, MR18=6431
4346 06:02:44.378115 CH0_RK1: MR19=0x808, MR18=0x6431, DQSOSC=391, MR23=63, INC=171, DEC=114
4347 06:02:44.378585 [RxdqsGatingPostProcess] freq 600
4348 06:02:44.385113 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4349 06:02:44.388463 Pre-setting of DQS Precalculation
4350 06:02:44.391858 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4351 06:02:44.394827 ==
4352 06:02:44.395283 Dram Type= 6, Freq= 0, CH_1, rank 0
4353 06:02:44.401649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 06:02:44.402326 ==
4355 06:02:44.405142 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4356 06:02:44.411463 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4357 06:02:44.415390 [CA 0] Center 35 (5~66) winsize 62
4358 06:02:44.418402 [CA 1] Center 35 (5~66) winsize 62
4359 06:02:44.421689 [CA 2] Center 34 (4~65) winsize 62
4360 06:02:44.425439 [CA 3] Center 33 (3~64) winsize 62
4361 06:02:44.428374 [CA 4] Center 34 (3~65) winsize 63
4362 06:02:44.431690 [CA 5] Center 33 (3~64) winsize 62
4363 06:02:44.432248
4364 06:02:44.435197 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4365 06:02:44.435750
4366 06:02:44.438610 [CATrainingPosCal] consider 1 rank data
4367 06:02:44.441559 u2DelayCellTimex100 = 270/100 ps
4368 06:02:44.445006 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4369 06:02:44.448498 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4370 06:02:44.455113 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4371 06:02:44.458320 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4372 06:02:44.461770 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4373 06:02:44.465301 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4374 06:02:44.465869
4375 06:02:44.468315 CA PerBit enable=1, Macro0, CA PI delay=33
4376 06:02:44.468824
4377 06:02:44.471583 [CBTSetCACLKResult] CA Dly = 33
4378 06:02:44.472046 CS Dly: 4 (0~35)
4379 06:02:44.474849 ==
4380 06:02:44.475311 Dram Type= 6, Freq= 0, CH_1, rank 1
4381 06:02:44.481693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 06:02:44.482209 ==
4383 06:02:44.484798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4384 06:02:44.491541 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4385 06:02:44.495102 [CA 0] Center 35 (5~66) winsize 62
4386 06:02:44.498473 [CA 1] Center 35 (5~66) winsize 62
4387 06:02:44.502034 [CA 2] Center 34 (4~65) winsize 62
4388 06:02:44.505391 [CA 3] Center 34 (4~65) winsize 62
4389 06:02:44.508625 [CA 4] Center 34 (4~65) winsize 62
4390 06:02:44.511971 [CA 5] Center 33 (3~64) winsize 62
4391 06:02:44.512502
4392 06:02:44.515408 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4393 06:02:44.515955
4394 06:02:44.518791 [CATrainingPosCal] consider 2 rank data
4395 06:02:44.521758 u2DelayCellTimex100 = 270/100 ps
4396 06:02:44.524996 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4397 06:02:44.532235 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4398 06:02:44.535340 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4399 06:02:44.538305 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4400 06:02:44.541526 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4401 06:02:44.545096 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4402 06:02:44.545556
4403 06:02:44.548785 CA PerBit enable=1, Macro0, CA PI delay=33
4404 06:02:44.549317
4405 06:02:44.551697 [CBTSetCACLKResult] CA Dly = 33
4406 06:02:44.552150 CS Dly: 5 (0~37)
4407 06:02:44.555272
4408 06:02:44.558147 ----->DramcWriteLeveling(PI) begin...
4409 06:02:44.558617 ==
4410 06:02:44.561450 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 06:02:44.565189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 06:02:44.565650 ==
4413 06:02:44.568274 Write leveling (Byte 0): 30 => 30
4414 06:02:44.571907 Write leveling (Byte 1): 31 => 31
4415 06:02:44.574849 DramcWriteLeveling(PI) end<-----
4416 06:02:44.575382
4417 06:02:44.575755 ==
4418 06:02:44.578311 Dram Type= 6, Freq= 0, CH_1, rank 0
4419 06:02:44.581507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 06:02:44.582021 ==
4421 06:02:44.584707 [Gating] SW mode calibration
4422 06:02:44.591521 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4423 06:02:44.598070 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4424 06:02:44.601554 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4425 06:02:44.605145 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 06:02:44.611563 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4427 06:02:44.614804 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (1 1) (0 0)
4428 06:02:44.618287 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 06:02:44.625113 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 06:02:44.628288 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 06:02:44.631285 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 06:02:44.634522 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 06:02:44.641260 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 06:02:44.644684 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 06:02:44.648142 0 10 12 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
4436 06:02:44.654878 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 06:02:44.658297 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 06:02:44.661474 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 06:02:44.668038 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 06:02:44.671211 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 06:02:44.674527 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 06:02:44.681169 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4443 06:02:44.684497 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 06:02:44.687725 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 06:02:44.694424 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 06:02:44.698046 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 06:02:44.701465 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 06:02:44.707874 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 06:02:44.711089 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 06:02:44.714450 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 06:02:44.721237 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 06:02:44.724259 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 06:02:44.727727 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 06:02:44.734272 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 06:02:44.737509 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 06:02:44.740932 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 06:02:44.747551 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 06:02:44.750658 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 06:02:44.754499 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4460 06:02:44.757425 Total UI for P1: 0, mck2ui 16
4461 06:02:44.761037 best dqsien dly found for B1: ( 0, 13, 10)
4462 06:02:44.763989 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 06:02:44.767563 Total UI for P1: 0, mck2ui 16
4464 06:02:44.771183 best dqsien dly found for B0: ( 0, 13, 12)
4465 06:02:44.774190 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4466 06:02:44.780859 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4467 06:02:44.781431
4468 06:02:44.783890 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4469 06:02:44.787565 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4470 06:02:44.791299 [Gating] SW calibration Done
4471 06:02:44.791776 ==
4472 06:02:44.794073 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 06:02:44.797422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 06:02:44.797898 ==
4475 06:02:44.801239 RX Vref Scan: 0
4476 06:02:44.801710
4477 06:02:44.802132 RX Vref 0 -> 0, step: 1
4478 06:02:44.802493
4479 06:02:44.804058 RX Delay -230 -> 252, step: 16
4480 06:02:44.807570 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4481 06:02:44.814372 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4482 06:02:44.817458 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4483 06:02:44.821125 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4484 06:02:44.824304 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4485 06:02:44.827050 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4486 06:02:44.834128 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4487 06:02:44.837595 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4488 06:02:44.840533 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4489 06:02:44.843896 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4490 06:02:44.850310 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4491 06:02:44.854034 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4492 06:02:44.857016 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4493 06:02:44.860424 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4494 06:02:44.867039 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4495 06:02:44.870628 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4496 06:02:44.871144 ==
4497 06:02:44.873818 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 06:02:44.877175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 06:02:44.877745 ==
4500 06:02:44.880368 DQS Delay:
4501 06:02:44.880940 DQS0 = 0, DQS1 = 0
4502 06:02:44.881354 DQM Delay:
4503 06:02:44.883433 DQM0 = 51, DQM1 = 40
4504 06:02:44.884123 DQ Delay:
4505 06:02:44.886978 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4506 06:02:44.890039 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4507 06:02:44.893285 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4508 06:02:44.896977 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =41
4509 06:02:44.897477
4510 06:02:44.897844
4511 06:02:44.898242 ==
4512 06:02:44.900079 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 06:02:44.906606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 06:02:44.907105 ==
4515 06:02:44.907581
4516 06:02:44.908024
4517 06:02:44.908457 TX Vref Scan disable
4518 06:02:44.910541 == TX Byte 0 ==
4519 06:02:44.913996 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4520 06:02:44.920500 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4521 06:02:44.921075 == TX Byte 1 ==
4522 06:02:44.923676 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4523 06:02:44.930746 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4524 06:02:44.931324 ==
4525 06:02:44.933711 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 06:02:44.937056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 06:02:44.937742 ==
4528 06:02:44.938218
4529 06:02:44.938571
4530 06:02:44.940101 TX Vref Scan disable
4531 06:02:44.943890 == TX Byte 0 ==
4532 06:02:44.946685 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4533 06:02:44.950379 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4534 06:02:44.953356 == TX Byte 1 ==
4535 06:02:44.956823 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4536 06:02:44.960202 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4537 06:02:44.960684
4538 06:02:44.961161 [DATLAT]
4539 06:02:44.963522 Freq=600, CH1 RK0
4540 06:02:44.964112
4541 06:02:44.964600 DATLAT Default: 0x9
4542 06:02:44.967016 0, 0xFFFF, sum = 0
4543 06:02:44.969973 1, 0xFFFF, sum = 0
4544 06:02:44.970464 2, 0xFFFF, sum = 0
4545 06:02:44.973624 3, 0xFFFF, sum = 0
4546 06:02:44.974257 4, 0xFFFF, sum = 0
4547 06:02:44.976849 5, 0xFFFF, sum = 0
4548 06:02:44.977445 6, 0xFFFF, sum = 0
4549 06:02:44.979918 7, 0xFFFF, sum = 0
4550 06:02:44.980523 8, 0x0, sum = 1
4551 06:02:44.983460 9, 0x0, sum = 2
4552 06:02:44.983994 10, 0x0, sum = 3
4553 06:02:44.984481 11, 0x0, sum = 4
4554 06:02:44.986575 best_step = 9
4555 06:02:44.987056
4556 06:02:44.987549 ==
4557 06:02:44.990024 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 06:02:44.993148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 06:02:44.993664 ==
4560 06:02:44.996538 RX Vref Scan: 1
4561 06:02:44.997151
4562 06:02:44.997627 RX Vref 0 -> 0, step: 1
4563 06:02:45.000063
4564 06:02:45.000685 RX Delay -179 -> 252, step: 8
4565 06:02:45.001134
4566 06:02:45.003101 Set Vref, RX VrefLevel [Byte0]: 54
4567 06:02:45.006275 [Byte1]: 53
4568 06:02:45.010675
4569 06:02:45.011157 Final RX Vref Byte 0 = 54 to rank0
4570 06:02:45.013986 Final RX Vref Byte 1 = 53 to rank0
4571 06:02:45.017418 Final RX Vref Byte 0 = 54 to rank1
4572 06:02:45.020559 Final RX Vref Byte 1 = 53 to rank1==
4573 06:02:45.023877 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 06:02:45.030558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 06:02:45.031016 ==
4576 06:02:45.031388 DQS Delay:
4577 06:02:45.031736 DQS0 = 0, DQS1 = 0
4578 06:02:45.034316 DQM Delay:
4579 06:02:45.034884 DQM0 = 49, DQM1 = 40
4580 06:02:45.037152 DQ Delay:
4581 06:02:45.040582 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4582 06:02:45.043924 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4583 06:02:45.047052 DQ8 =28, DQ9 =24, DQ10 =44, DQ11 =32
4584 06:02:45.050588 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =44
4585 06:02:45.051059
4586 06:02:45.051431
4587 06:02:45.056782 [DQSOSCAuto] RK0, (LSB)MR18= 0x456c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4588 06:02:45.060230 CH1 RK0: MR19=808, MR18=456C
4589 06:02:45.066863 CH1_RK0: MR19=0x808, MR18=0x456C, DQSOSC=389, MR23=63, INC=173, DEC=115
4590 06:02:45.067407
4591 06:02:45.070175 ----->DramcWriteLeveling(PI) begin...
4592 06:02:45.070651 ==
4593 06:02:45.073664 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 06:02:45.076919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 06:02:45.077462 ==
4596 06:02:45.080264 Write leveling (Byte 0): 29 => 29
4597 06:02:45.083443 Write leveling (Byte 1): 29 => 29
4598 06:02:45.086957 DramcWriteLeveling(PI) end<-----
4599 06:02:45.087424
4600 06:02:45.087786 ==
4601 06:02:45.090092 Dram Type= 6, Freq= 0, CH_1, rank 1
4602 06:02:45.093725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 06:02:45.094243 ==
4604 06:02:45.096776 [Gating] SW mode calibration
4605 06:02:45.103313 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4606 06:02:45.110361 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4607 06:02:45.113592 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4608 06:02:45.120090 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4609 06:02:45.123488 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
4610 06:02:45.126686 0 9 12 | B1->B0 | 2e2e 3333 | 0 0 | (1 0) (0 1)
4611 06:02:45.133227 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 06:02:45.136824 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 06:02:45.140212 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 06:02:45.146486 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 06:02:45.150063 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 06:02:45.153372 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 06:02:45.156557 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 06:02:45.163273 0 10 12 | B1->B0 | 4040 3030 | 0 0 | (0 0) (0 0)
4619 06:02:45.166726 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 06:02:45.169872 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 06:02:45.176722 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 06:02:45.180216 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 06:02:45.183347 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 06:02:45.189775 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 06:02:45.193421 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 06:02:45.196708 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 06:02:45.203087 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 06:02:45.206620 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 06:02:45.209871 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 06:02:45.216978 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 06:02:45.220060 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 06:02:45.223205 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 06:02:45.230048 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 06:02:45.233310 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 06:02:45.236486 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 06:02:45.243231 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 06:02:45.246377 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 06:02:45.250136 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 06:02:45.256454 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 06:02:45.259973 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 06:02:45.263020 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4642 06:02:45.266559 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4643 06:02:45.273089 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 06:02:45.276597 Total UI for P1: 0, mck2ui 16
4645 06:02:45.279827 best dqsien dly found for B0: ( 0, 13, 12)
4646 06:02:45.283089 Total UI for P1: 0, mck2ui 16
4647 06:02:45.286399 best dqsien dly found for B1: ( 0, 13, 10)
4648 06:02:45.290194 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4649 06:02:45.293154 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4650 06:02:45.293701
4651 06:02:45.296854 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4652 06:02:45.299933 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4653 06:02:45.303103 [Gating] SW calibration Done
4654 06:02:45.303670 ==
4655 06:02:45.306253 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 06:02:45.310026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 06:02:45.310602 ==
4658 06:02:45.313476 RX Vref Scan: 0
4659 06:02:45.314128
4660 06:02:45.316368 RX Vref 0 -> 0, step: 1
4661 06:02:45.316934
4662 06:02:45.317309 RX Delay -230 -> 252, step: 16
4663 06:02:45.323137 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4664 06:02:45.326119 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4665 06:02:45.329728 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4666 06:02:45.333097 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4667 06:02:45.339664 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4668 06:02:45.342933 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4669 06:02:45.346177 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4670 06:02:45.349414 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4671 06:02:45.352870 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4672 06:02:45.359482 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4673 06:02:45.362918 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4674 06:02:45.366420 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4675 06:02:45.369494 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4676 06:02:45.376007 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4677 06:02:45.379477 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4678 06:02:45.382962 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4679 06:02:45.383534 ==
4680 06:02:45.385931 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 06:02:45.389426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 06:02:45.390056 ==
4683 06:02:45.392533 DQS Delay:
4684 06:02:45.393014 DQS0 = 0, DQS1 = 0
4685 06:02:45.396147 DQM Delay:
4686 06:02:45.396690 DQM0 = 51, DQM1 = 47
4687 06:02:45.397064 DQ Delay:
4688 06:02:45.399322 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4689 06:02:45.402623 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4690 06:02:45.406066 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4691 06:02:45.409706 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4692 06:02:45.410392
4693 06:02:45.410956
4694 06:02:45.412619 ==
4695 06:02:45.416271 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 06:02:45.419517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 06:02:45.420071 ==
4698 06:02:45.420452
4699 06:02:45.420801
4700 06:02:45.422784 TX Vref Scan disable
4701 06:02:45.423236 == TX Byte 0 ==
4702 06:02:45.426048 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4703 06:02:45.432776 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4704 06:02:45.433266 == TX Byte 1 ==
4705 06:02:45.435893 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4706 06:02:45.442850 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4707 06:02:45.443326 ==
4708 06:02:45.445861 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 06:02:45.449617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 06:02:45.450169 ==
4711 06:02:45.450565
4712 06:02:45.450916
4713 06:02:45.452735 TX Vref Scan disable
4714 06:02:45.455914 == TX Byte 0 ==
4715 06:02:45.459395 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4716 06:02:45.462573 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4717 06:02:45.466436 == TX Byte 1 ==
4718 06:02:45.469705 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4719 06:02:45.472815 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4720 06:02:45.473357
4721 06:02:45.475904 [DATLAT]
4722 06:02:45.476373 Freq=600, CH1 RK1
4723 06:02:45.476748
4724 06:02:45.479312 DATLAT Default: 0x9
4725 06:02:45.479784 0, 0xFFFF, sum = 0
4726 06:02:45.482612 1, 0xFFFF, sum = 0
4727 06:02:45.483087 2, 0xFFFF, sum = 0
4728 06:02:45.486098 3, 0xFFFF, sum = 0
4729 06:02:45.486608 4, 0xFFFF, sum = 0
4730 06:02:45.489507 5, 0xFFFF, sum = 0
4731 06:02:45.490011 6, 0xFFFF, sum = 0
4732 06:02:45.492468 7, 0xFFFF, sum = 0
4733 06:02:45.492948 8, 0x0, sum = 1
4734 06:02:45.495863 9, 0x0, sum = 2
4735 06:02:45.496341 10, 0x0, sum = 3
4736 06:02:45.499331 11, 0x0, sum = 4
4737 06:02:45.499810 best_step = 9
4738 06:02:45.500187
4739 06:02:45.500529 ==
4740 06:02:45.502492 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 06:02:45.505776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 06:02:45.506346 ==
4743 06:02:45.509062 RX Vref Scan: 0
4744 06:02:45.509530
4745 06:02:45.512829 RX Vref 0 -> 0, step: 1
4746 06:02:45.513303
4747 06:02:45.513677 RX Delay -163 -> 252, step: 8
4748 06:02:45.520195 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4749 06:02:45.523932 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4750 06:02:45.527335 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4751 06:02:45.530269 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4752 06:02:45.537289 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4753 06:02:45.540228 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4754 06:02:45.543563 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4755 06:02:45.547299 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4756 06:02:45.550169 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4757 06:02:45.557240 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4758 06:02:45.560451 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4759 06:02:45.563302 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4760 06:02:45.566808 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4761 06:02:45.570290 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4762 06:02:45.577075 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4763 06:02:45.580089 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4764 06:02:45.580567 ==
4765 06:02:45.583403 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 06:02:45.586538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 06:02:45.587015 ==
4768 06:02:45.590252 DQS Delay:
4769 06:02:45.590715 DQS0 = 0, DQS1 = 0
4770 06:02:45.591081 DQM Delay:
4771 06:02:45.593647 DQM0 = 48, DQM1 = 44
4772 06:02:45.594140 DQ Delay:
4773 06:02:45.597300 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4774 06:02:45.600063 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4775 06:02:45.603539 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4776 06:02:45.606521 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4777 06:02:45.606995
4778 06:02:45.607369
4779 06:02:45.617028 [DQSOSCAuto] RK1, (LSB)MR18= 0x5319, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
4780 06:02:45.620122 CH1 RK1: MR19=808, MR18=5319
4781 06:02:45.623339 CH1_RK1: MR19=0x808, MR18=0x5319, DQSOSC=394, MR23=63, INC=168, DEC=112
4782 06:02:45.626413 [RxdqsGatingPostProcess] freq 600
4783 06:02:45.633187 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4784 06:02:45.636662 Pre-setting of DQS Precalculation
4785 06:02:45.639825 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4786 06:02:45.649913 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4787 06:02:45.656347 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4788 06:02:45.656912
4789 06:02:45.657292
4790 06:02:45.659811 [Calibration Summary] 1200 Mbps
4791 06:02:45.660288 CH 0, Rank 0
4792 06:02:45.662796 SW Impedance : PASS
4793 06:02:45.663270 DUTY Scan : NO K
4794 06:02:45.666370 ZQ Calibration : PASS
4795 06:02:45.669755 Jitter Meter : NO K
4796 06:02:45.670288 CBT Training : PASS
4797 06:02:45.672847 Write leveling : PASS
4798 06:02:45.676527 RX DQS gating : PASS
4799 06:02:45.677069 RX DQ/DQS(RDDQC) : PASS
4800 06:02:45.679675 TX DQ/DQS : PASS
4801 06:02:45.680310 RX DATLAT : PASS
4802 06:02:45.683176 RX DQ/DQS(Engine): PASS
4803 06:02:45.686125 TX OE : NO K
4804 06:02:45.686598 All Pass.
4805 06:02:45.686973
4806 06:02:45.687339 CH 0, Rank 1
4807 06:02:45.689836 SW Impedance : PASS
4808 06:02:45.693149 DUTY Scan : NO K
4809 06:02:45.693887 ZQ Calibration : PASS
4810 06:02:45.696447 Jitter Meter : NO K
4811 06:02:45.699440 CBT Training : PASS
4812 06:02:45.699909 Write leveling : PASS
4813 06:02:45.703091 RX DQS gating : PASS
4814 06:02:45.706062 RX DQ/DQS(RDDQC) : PASS
4815 06:02:45.706684 TX DQ/DQS : PASS
4816 06:02:45.709388 RX DATLAT : PASS
4817 06:02:45.712688 RX DQ/DQS(Engine): PASS
4818 06:02:45.713253 TX OE : NO K
4819 06:02:45.715896 All Pass.
4820 06:02:45.716369
4821 06:02:45.716747 CH 1, Rank 0
4822 06:02:45.719549 SW Impedance : PASS
4823 06:02:45.720090 DUTY Scan : NO K
4824 06:02:45.722736 ZQ Calibration : PASS
4825 06:02:45.726183 Jitter Meter : NO K
4826 06:02:45.726660 CBT Training : PASS
4827 06:02:45.729282 Write leveling : PASS
4828 06:02:45.732903 RX DQS gating : PASS
4829 06:02:45.733381 RX DQ/DQS(RDDQC) : PASS
4830 06:02:45.735958 TX DQ/DQS : PASS
4831 06:02:45.736528 RX DATLAT : PASS
4832 06:02:45.739200 RX DQ/DQS(Engine): PASS
4833 06:02:45.742612 TX OE : NO K
4834 06:02:45.743089 All Pass.
4835 06:02:45.743467
4836 06:02:45.743818 CH 1, Rank 1
4837 06:02:45.745869 SW Impedance : PASS
4838 06:02:45.749334 DUTY Scan : NO K
4839 06:02:45.749806 ZQ Calibration : PASS
4840 06:02:45.752422 Jitter Meter : NO K
4841 06:02:45.755706 CBT Training : PASS
4842 06:02:45.756179 Write leveling : PASS
4843 06:02:45.759190 RX DQS gating : PASS
4844 06:02:45.762440 RX DQ/DQS(RDDQC) : PASS
4845 06:02:45.762917 TX DQ/DQS : PASS
4846 06:02:45.765782 RX DATLAT : PASS
4847 06:02:45.769208 RX DQ/DQS(Engine): PASS
4848 06:02:45.769686 TX OE : NO K
4849 06:02:45.772648 All Pass.
4850 06:02:45.773115
4851 06:02:45.773486 DramC Write-DBI off
4852 06:02:45.775664 PER_BANK_REFRESH: Hybrid Mode
4853 06:02:45.776202 TX_TRACKING: ON
4854 06:02:45.785727 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4855 06:02:45.789220 [FAST_K] Save calibration result to emmc
4856 06:02:45.792981 dramc_set_vcore_voltage set vcore to 662500
4857 06:02:45.795582 Read voltage for 933, 3
4858 06:02:45.796053 Vio18 = 0
4859 06:02:45.798723 Vcore = 662500
4860 06:02:45.799192 Vdram = 0
4861 06:02:45.799561 Vddq = 0
4862 06:02:45.799904 Vmddr = 0
4863 06:02:45.805603 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4864 06:02:45.812343 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4865 06:02:45.812922 MEM_TYPE=3, freq_sel=17
4866 06:02:45.815866 sv_algorithm_assistance_LP4_1600
4867 06:02:45.819316 ============ PULL DRAM RESETB DOWN ============
4868 06:02:45.826015 ========== PULL DRAM RESETB DOWN end =========
4869 06:02:45.829284 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4870 06:02:45.832237 ===================================
4871 06:02:45.835741 LPDDR4 DRAM CONFIGURATION
4872 06:02:45.839132 ===================================
4873 06:02:45.839604 EX_ROW_EN[0] = 0x0
4874 06:02:45.842463 EX_ROW_EN[1] = 0x0
4875 06:02:45.842938 LP4Y_EN = 0x0
4876 06:02:45.845779 WORK_FSP = 0x0
4877 06:02:45.846348 WL = 0x3
4878 06:02:45.849395 RL = 0x3
4879 06:02:45.849867 BL = 0x2
4880 06:02:45.852408 RPST = 0x0
4881 06:02:45.855737 RD_PRE = 0x0
4882 06:02:45.856212 WR_PRE = 0x1
4883 06:02:45.859006 WR_PST = 0x0
4884 06:02:45.859625 DBI_WR = 0x0
4885 06:02:45.862666 DBI_RD = 0x0
4886 06:02:45.863242 OTF = 0x1
4887 06:02:45.865526 ===================================
4888 06:02:45.869220 ===================================
4889 06:02:45.872240 ANA top config
4890 06:02:45.875760 ===================================
4891 06:02:45.876303 DLL_ASYNC_EN = 0
4892 06:02:45.878826 ALL_SLAVE_EN = 1
4893 06:02:45.882129 NEW_RANK_MODE = 1
4894 06:02:45.885504 DLL_IDLE_MODE = 1
4895 06:02:45.886106 LP45_APHY_COMB_EN = 1
4896 06:02:45.889144 TX_ODT_DIS = 1
4897 06:02:45.892379 NEW_8X_MODE = 1
4898 06:02:45.895522 ===================================
4899 06:02:45.898801 ===================================
4900 06:02:45.902021 data_rate = 1866
4901 06:02:45.905341 CKR = 1
4902 06:02:45.905808 DQ_P2S_RATIO = 8
4903 06:02:45.909056 ===================================
4904 06:02:45.912158 CA_P2S_RATIO = 8
4905 06:02:45.915224 DQ_CA_OPEN = 0
4906 06:02:45.918623 DQ_SEMI_OPEN = 0
4907 06:02:45.922309 CA_SEMI_OPEN = 0
4908 06:02:45.925255 CA_FULL_RATE = 0
4909 06:02:45.925787 DQ_CKDIV4_EN = 1
4910 06:02:45.928679 CA_CKDIV4_EN = 1
4911 06:02:45.932002 CA_PREDIV_EN = 0
4912 06:02:45.935424 PH8_DLY = 0
4913 06:02:45.938652 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4914 06:02:45.941739 DQ_AAMCK_DIV = 4
4915 06:02:45.942242 CA_AAMCK_DIV = 4
4916 06:02:45.945273 CA_ADMCK_DIV = 4
4917 06:02:45.948494 DQ_TRACK_CA_EN = 0
4918 06:02:45.952065 CA_PICK = 933
4919 06:02:45.955005 CA_MCKIO = 933
4920 06:02:45.958475 MCKIO_SEMI = 0
4921 06:02:45.961854 PLL_FREQ = 3732
4922 06:02:45.962425 DQ_UI_PI_RATIO = 32
4923 06:02:45.965458 CA_UI_PI_RATIO = 0
4924 06:02:45.968522 ===================================
4925 06:02:45.971914 ===================================
4926 06:02:45.975259 memory_type:LPDDR4
4927 06:02:45.978477 GP_NUM : 10
4928 06:02:45.978961 SRAM_EN : 1
4929 06:02:45.981796 MD32_EN : 0
4930 06:02:45.985230 ===================================
4931 06:02:45.988231 [ANA_INIT] >>>>>>>>>>>>>>
4932 06:02:45.988773 <<<<<< [CONFIGURE PHASE]: ANA_TX
4933 06:02:45.994873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4934 06:02:45.995358 ===================================
4935 06:02:45.998284 data_rate = 1866,PCW = 0X8f00
4936 06:02:46.001532 ===================================
4937 06:02:46.005178 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4938 06:02:46.011468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4939 06:02:46.018231 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4940 06:02:46.021776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4941 06:02:46.024735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4942 06:02:46.028160 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4943 06:02:46.031863 [ANA_INIT] flow start
4944 06:02:46.032339 [ANA_INIT] PLL >>>>>>>>
4945 06:02:46.034984 [ANA_INIT] PLL <<<<<<<<
4946 06:02:46.038237 [ANA_INIT] MIDPI >>>>>>>>
4947 06:02:46.038713 [ANA_INIT] MIDPI <<<<<<<<
4948 06:02:46.041458 [ANA_INIT] DLL >>>>>>>>
4949 06:02:46.045085 [ANA_INIT] flow end
4950 06:02:46.048468 ============ LP4 DIFF to SE enter ============
4951 06:02:46.051307 ============ LP4 DIFF to SE exit ============
4952 06:02:46.054641 [ANA_INIT] <<<<<<<<<<<<<
4953 06:02:46.058061 [Flow] Enable top DCM control >>>>>
4954 06:02:46.061440 [Flow] Enable top DCM control <<<<<
4955 06:02:46.064759 Enable DLL master slave shuffle
4956 06:02:46.068373 ==============================================================
4957 06:02:46.071684 Gating Mode config
4958 06:02:46.078189 ==============================================================
4959 06:02:46.078668 Config description:
4960 06:02:46.088939 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4961 06:02:46.094602 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4962 06:02:46.098356 SELPH_MODE 0: By rank 1: By Phase
4963 06:02:46.104679 ==============================================================
4964 06:02:46.108430 GAT_TRACK_EN = 1
4965 06:02:46.111400 RX_GATING_MODE = 2
4966 06:02:46.114983 RX_GATING_TRACK_MODE = 2
4967 06:02:46.118400 SELPH_MODE = 1
4968 06:02:46.121715 PICG_EARLY_EN = 1
4969 06:02:46.124659 VALID_LAT_VALUE = 1
4970 06:02:46.127926 ==============================================================
4971 06:02:46.131342 Enter into Gating configuration >>>>
4972 06:02:46.134811 Exit from Gating configuration <<<<
4973 06:02:46.138154 Enter into DVFS_PRE_config >>>>>
4974 06:02:46.151478 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4975 06:02:46.154783 Exit from DVFS_PRE_config <<<<<
4976 06:02:46.155255 Enter into PICG configuration >>>>
4977 06:02:46.157887 Exit from PICG configuration <<<<
4978 06:02:46.161145 [RX_INPUT] configuration >>>>>
4979 06:02:46.164286 [RX_INPUT] configuration <<<<<
4980 06:02:46.171062 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4981 06:02:46.174478 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4982 06:02:46.181145 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4983 06:02:46.187560 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4984 06:02:46.194279 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4985 06:02:46.200819 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4986 06:02:46.203963 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4987 06:02:46.207704 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4988 06:02:46.210873 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4989 06:02:46.217276 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4990 06:02:46.220503 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4991 06:02:46.223811 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4992 06:02:46.227442 ===================================
4993 06:02:46.230571 LPDDR4 DRAM CONFIGURATION
4994 06:02:46.233936 ===================================
4995 06:02:46.237367 EX_ROW_EN[0] = 0x0
4996 06:02:46.237876 EX_ROW_EN[1] = 0x0
4997 06:02:46.240575 LP4Y_EN = 0x0
4998 06:02:46.241042 WORK_FSP = 0x0
4999 06:02:46.243692 WL = 0x3
5000 06:02:46.244158 RL = 0x3
5001 06:02:46.247195 BL = 0x2
5002 06:02:46.247660 RPST = 0x0
5003 06:02:46.250537 RD_PRE = 0x0
5004 06:02:46.250998 WR_PRE = 0x1
5005 06:02:46.253641 WR_PST = 0x0
5006 06:02:46.254148 DBI_WR = 0x0
5007 06:02:46.257124 DBI_RD = 0x0
5008 06:02:46.257624 OTF = 0x1
5009 06:02:46.260238 ===================================
5010 06:02:46.267251 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5011 06:02:46.270327 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5012 06:02:46.274031 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5013 06:02:46.276843 ===================================
5014 06:02:46.280284 LPDDR4 DRAM CONFIGURATION
5015 06:02:46.283645 ===================================
5016 06:02:46.287271 EX_ROW_EN[0] = 0x10
5017 06:02:46.287746 EX_ROW_EN[1] = 0x0
5018 06:02:46.290455 LP4Y_EN = 0x0
5019 06:02:46.290947 WORK_FSP = 0x0
5020 06:02:46.293727 WL = 0x3
5021 06:02:46.294253 RL = 0x3
5022 06:02:46.297149 BL = 0x2
5023 06:02:46.297620 RPST = 0x0
5024 06:02:46.300119 RD_PRE = 0x0
5025 06:02:46.300592 WR_PRE = 0x1
5026 06:02:46.303745 WR_PST = 0x0
5027 06:02:46.304215 DBI_WR = 0x0
5028 06:02:46.307446 DBI_RD = 0x0
5029 06:02:46.307918 OTF = 0x1
5030 06:02:46.310500 ===================================
5031 06:02:46.316746 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5032 06:02:46.321442 nWR fixed to 30
5033 06:02:46.324826 [ModeRegInit_LP4] CH0 RK0
5034 06:02:46.325369 [ModeRegInit_LP4] CH0 RK1
5035 06:02:46.327882 [ModeRegInit_LP4] CH1 RK0
5036 06:02:46.331313 [ModeRegInit_LP4] CH1 RK1
5037 06:02:46.331881 match AC timing 9
5038 06:02:46.337730 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5039 06:02:46.341075 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5040 06:02:46.344379 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5041 06:02:46.351269 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5042 06:02:46.354381 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5043 06:02:46.354846 ==
5044 06:02:46.357654 Dram Type= 6, Freq= 0, CH_0, rank 0
5045 06:02:46.361013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5046 06:02:46.361560 ==
5047 06:02:46.367939 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5048 06:02:46.374600 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5049 06:02:46.377725 [CA 0] Center 38 (7~69) winsize 63
5050 06:02:46.381010 [CA 1] Center 38 (8~69) winsize 62
5051 06:02:46.384402 [CA 2] Center 35 (5~66) winsize 62
5052 06:02:46.387957 [CA 3] Center 35 (5~65) winsize 61
5053 06:02:46.391012 [CA 4] Center 34 (4~64) winsize 61
5054 06:02:46.394557 [CA 5] Center 33 (3~64) winsize 62
5055 06:02:46.395032
5056 06:02:46.397469 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5057 06:02:46.397980
5058 06:02:46.401044 [CATrainingPosCal] consider 1 rank data
5059 06:02:46.404364 u2DelayCellTimex100 = 270/100 ps
5060 06:02:46.407900 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5061 06:02:46.410913 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5062 06:02:46.414481 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5063 06:02:46.417601 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5064 06:02:46.420950 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5065 06:02:46.427467 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5066 06:02:46.427940
5067 06:02:46.431051 CA PerBit enable=1, Macro0, CA PI delay=33
5068 06:02:46.431674
5069 06:02:46.434277 [CBTSetCACLKResult] CA Dly = 33
5070 06:02:46.434795 CS Dly: 6 (0~37)
5071 06:02:46.435273 ==
5072 06:02:46.437484 Dram Type= 6, Freq= 0, CH_0, rank 1
5073 06:02:46.440540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5074 06:02:46.443921 ==
5075 06:02:46.447636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5076 06:02:46.454013 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5077 06:02:46.457258 [CA 0] Center 38 (7~69) winsize 63
5078 06:02:46.460757 [CA 1] Center 38 (8~69) winsize 62
5079 06:02:46.464058 [CA 2] Center 36 (6~66) winsize 61
5080 06:02:46.467491 [CA 3] Center 35 (5~66) winsize 62
5081 06:02:46.470552 [CA 4] Center 34 (4~65) winsize 62
5082 06:02:46.474417 [CA 5] Center 34 (4~65) winsize 62
5083 06:02:46.474993
5084 06:02:46.477550 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5085 06:02:46.478172
5086 06:02:46.480501 [CATrainingPosCal] consider 2 rank data
5087 06:02:46.484399 u2DelayCellTimex100 = 270/100 ps
5088 06:02:46.487931 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5089 06:02:46.490592 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5090 06:02:46.493778 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5091 06:02:46.497304 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5092 06:02:46.503814 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5093 06:02:46.506999 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5094 06:02:46.507477
5095 06:02:46.510346 CA PerBit enable=1, Macro0, CA PI delay=34
5096 06:02:46.510862
5097 06:02:46.513667 [CBTSetCACLKResult] CA Dly = 34
5098 06:02:46.514334 CS Dly: 7 (0~39)
5099 06:02:46.514818
5100 06:02:46.517348 ----->DramcWriteLeveling(PI) begin...
5101 06:02:46.517834 ==
5102 06:02:46.520219 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 06:02:46.527174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 06:02:46.527748 ==
5105 06:02:46.530381 Write leveling (Byte 0): 32 => 32
5106 06:02:46.534034 Write leveling (Byte 1): 30 => 30
5107 06:02:46.534502 DramcWriteLeveling(PI) end<-----
5108 06:02:46.534880
5109 06:02:46.537139 ==
5110 06:02:46.540547 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 06:02:46.544011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 06:02:46.544485 ==
5113 06:02:46.547206 [Gating] SW mode calibration
5114 06:02:46.553845 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5115 06:02:46.557113 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5116 06:02:46.563572 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5117 06:02:46.567008 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 06:02:46.570463 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 06:02:46.576897 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 06:02:46.580765 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 06:02:46.583840 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 06:02:46.590306 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5123 06:02:46.593350 0 14 28 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
5124 06:02:46.596550 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5125 06:02:46.603355 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 06:02:46.606515 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 06:02:46.609990 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 06:02:46.616683 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 06:02:46.620239 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 06:02:46.623277 0 15 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5131 06:02:46.630018 0 15 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
5132 06:02:46.633160 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 06:02:46.636331 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 06:02:46.643022 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 06:02:46.646861 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 06:02:46.649975 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 06:02:46.653185 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 06:02:46.660291 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 06:02:46.663002 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5140 06:02:46.669789 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5141 06:02:46.673156 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 06:02:46.676221 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 06:02:46.679843 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 06:02:46.686509 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 06:02:46.689650 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 06:02:46.692611 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 06:02:46.699524 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 06:02:46.702924 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 06:02:46.706435 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 06:02:46.712682 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 06:02:46.716495 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 06:02:46.719387 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 06:02:46.726211 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 06:02:46.729239 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 06:02:46.732840 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5156 06:02:46.736473 Total UI for P1: 0, mck2ui 16
5157 06:02:46.739271 best dqsien dly found for B0: ( 1, 2, 26)
5158 06:02:46.746290 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 06:02:46.746789 Total UI for P1: 0, mck2ui 16
5160 06:02:46.752853 best dqsien dly found for B1: ( 1, 2, 28)
5161 06:02:46.756161 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5162 06:02:46.759277 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5163 06:02:46.759745
5164 06:02:46.762510 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5165 06:02:46.765756 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5166 06:02:46.769282 [Gating] SW calibration Done
5167 06:02:46.769750 ==
5168 06:02:46.772630 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 06:02:46.775985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 06:02:46.776563 ==
5171 06:02:46.779614 RX Vref Scan: 0
5172 06:02:46.780076
5173 06:02:46.780483 RX Vref 0 -> 0, step: 1
5174 06:02:46.780844
5175 06:02:46.782602 RX Delay -80 -> 252, step: 8
5176 06:02:46.785973 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5177 06:02:46.792445 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5178 06:02:46.796027 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5179 06:02:46.799413 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5180 06:02:46.802689 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5181 06:02:46.806094 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5182 06:02:46.813050 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5183 06:02:46.816128 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5184 06:02:46.819701 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5185 06:02:46.822620 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5186 06:02:46.826158 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5187 06:02:46.829294 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5188 06:02:46.836204 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5189 06:02:46.839425 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5190 06:02:46.842435 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5191 06:02:46.845676 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5192 06:02:46.846176 ==
5193 06:02:46.849462 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 06:02:46.852367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 06:02:46.852843 ==
5196 06:02:46.855632 DQS Delay:
5197 06:02:46.856100 DQS0 = 0, DQS1 = 0
5198 06:02:46.859201 DQM Delay:
5199 06:02:46.859671 DQM0 = 106, DQM1 = 92
5200 06:02:46.860043 DQ Delay:
5201 06:02:46.862418 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5202 06:02:46.865701 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5203 06:02:46.869423 DQ8 =83, DQ9 =79, DQ10 =95, DQ11 =91
5204 06:02:46.872338 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5205 06:02:46.875790
5206 06:02:46.876260
5207 06:02:46.876703 ==
5208 06:02:46.878951 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 06:02:46.882888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 06:02:46.883487 ==
5211 06:02:46.883867
5212 06:02:46.884208
5213 06:02:46.885903 TX Vref Scan disable
5214 06:02:46.886411 == TX Byte 0 ==
5215 06:02:46.892546 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5216 06:02:46.895553 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5217 06:02:46.896024 == TX Byte 1 ==
5218 06:02:46.902445 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5219 06:02:46.905491 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5220 06:02:46.906006 ==
5221 06:02:46.909148 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 06:02:46.912469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 06:02:46.913084 ==
5224 06:02:46.913462
5225 06:02:46.913808
5226 06:02:46.915703 TX Vref Scan disable
5227 06:02:46.919267 == TX Byte 0 ==
5228 06:02:46.922331 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5229 06:02:46.926019 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5230 06:02:46.929566 == TX Byte 1 ==
5231 06:02:46.932180 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5232 06:02:46.936045 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5233 06:02:46.936617
5234 06:02:46.938916 [DATLAT]
5235 06:02:46.939387 Freq=933, CH0 RK0
5236 06:02:46.939766
5237 06:02:46.942294 DATLAT Default: 0xd
5238 06:02:46.942901 0, 0xFFFF, sum = 0
5239 06:02:46.945383 1, 0xFFFF, sum = 0
5240 06:02:46.945893 2, 0xFFFF, sum = 0
5241 06:02:46.948862 3, 0xFFFF, sum = 0
5242 06:02:46.949382 4, 0xFFFF, sum = 0
5243 06:02:46.951930 5, 0xFFFF, sum = 0
5244 06:02:46.952406 6, 0xFFFF, sum = 0
5245 06:02:46.955501 7, 0xFFFF, sum = 0
5246 06:02:46.955977 8, 0xFFFF, sum = 0
5247 06:02:46.958659 9, 0xFFFF, sum = 0
5248 06:02:46.959136 10, 0x0, sum = 1
5249 06:02:46.962205 11, 0x0, sum = 2
5250 06:02:46.962776 12, 0x0, sum = 3
5251 06:02:46.965338 13, 0x0, sum = 4
5252 06:02:46.965812 best_step = 11
5253 06:02:46.966238
5254 06:02:46.966589 ==
5255 06:02:46.968819 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 06:02:46.975284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 06:02:46.975954 ==
5258 06:02:46.976500 RX Vref Scan: 1
5259 06:02:46.976872
5260 06:02:46.979187 RX Vref 0 -> 0, step: 1
5261 06:02:46.979672
5262 06:02:46.982203 RX Delay -53 -> 252, step: 4
5263 06:02:46.982775
5264 06:02:46.985466 Set Vref, RX VrefLevel [Byte0]: 60
5265 06:02:46.988834 [Byte1]: 50
5266 06:02:46.989316
5267 06:02:46.991795 Final RX Vref Byte 0 = 60 to rank0
5268 06:02:46.995250 Final RX Vref Byte 1 = 50 to rank0
5269 06:02:46.998500 Final RX Vref Byte 0 = 60 to rank1
5270 06:02:47.001848 Final RX Vref Byte 1 = 50 to rank1==
5271 06:02:47.005282 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 06:02:47.008659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 06:02:47.009254 ==
5274 06:02:47.011967 DQS Delay:
5275 06:02:47.012435 DQS0 = 0, DQS1 = 0
5276 06:02:47.012811 DQM Delay:
5277 06:02:47.015120 DQM0 = 107, DQM1 = 92
5278 06:02:47.015596 DQ Delay:
5279 06:02:47.018678 DQ0 =106, DQ1 =108, DQ2 =102, DQ3 =106
5280 06:02:47.021914 DQ4 =108, DQ5 =98, DQ6 =118, DQ7 =114
5281 06:02:47.025293 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =90
5282 06:02:47.028367 DQ12 =94, DQ13 =94, DQ14 =102, DQ15 =98
5283 06:02:47.028845
5284 06:02:47.032168
5285 06:02:47.038832 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
5286 06:02:47.041978 CH0 RK0: MR19=505, MR18=1F1B
5287 06:02:47.048278 CH0_RK0: MR19=0x505, MR18=0x1F1B, DQSOSC=412, MR23=63, INC=63, DEC=42
5288 06:02:47.048934
5289 06:02:47.051529 ----->DramcWriteLeveling(PI) begin...
5290 06:02:47.052042 ==
5291 06:02:47.055244 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 06:02:47.058290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 06:02:47.058800 ==
5294 06:02:47.061463 Write leveling (Byte 0): 33 => 33
5295 06:02:47.064748 Write leveling (Byte 1): 30 => 30
5296 06:02:47.068399 DramcWriteLeveling(PI) end<-----
5297 06:02:47.068888
5298 06:02:47.069255 ==
5299 06:02:47.071630 Dram Type= 6, Freq= 0, CH_0, rank 1
5300 06:02:47.075001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 06:02:47.075463 ==
5302 06:02:47.078247 [Gating] SW mode calibration
5303 06:02:47.085130 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5304 06:02:47.091428 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5305 06:02:47.094932 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 06:02:47.098274 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 06:02:47.104898 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 06:02:47.108531 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 06:02:47.111705 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 06:02:47.117920 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 06:02:47.121504 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5312 06:02:47.124531 0 14 28 | B1->B0 | 2c2c 2727 | 0 0 | (1 0) (0 0)
5313 06:02:47.131183 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 06:02:47.134624 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 06:02:47.138055 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 06:02:47.144337 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 06:02:47.148051 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 06:02:47.151257 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 06:02:47.157634 0 15 24 | B1->B0 | 2a2a 2c2c | 0 0 | (0 0) (0 0)
5320 06:02:47.161159 0 15 28 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
5321 06:02:47.164498 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 06:02:47.171318 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 06:02:47.174702 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 06:02:47.177719 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 06:02:47.184247 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 06:02:47.187420 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 06:02:47.190706 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 06:02:47.197455 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5329 06:02:47.200618 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 06:02:47.203977 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 06:02:47.210702 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 06:02:47.214052 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 06:02:47.217297 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 06:02:47.223890 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 06:02:47.227203 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 06:02:47.230862 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 06:02:47.234106 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 06:02:47.240404 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 06:02:47.244112 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 06:02:47.247246 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 06:02:47.253874 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 06:02:47.257207 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 06:02:47.260825 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5344 06:02:47.267389 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5345 06:02:47.270689 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5346 06:02:47.274297 Total UI for P1: 0, mck2ui 16
5347 06:02:47.277640 best dqsien dly found for B1: ( 1, 2, 26)
5348 06:02:47.280484 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 06:02:47.283968 Total UI for P1: 0, mck2ui 16
5350 06:02:47.287289 best dqsien dly found for B0: ( 1, 2, 28)
5351 06:02:47.291003 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5352 06:02:47.293868 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5353 06:02:47.294459
5354 06:02:47.300392 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5355 06:02:47.304163 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5356 06:02:47.304630 [Gating] SW calibration Done
5357 06:02:47.307457 ==
5358 06:02:47.310598 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 06:02:47.313795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 06:02:47.314445 ==
5361 06:02:47.314979 RX Vref Scan: 0
5362 06:02:47.315519
5363 06:02:47.317240 RX Vref 0 -> 0, step: 1
5364 06:02:47.317702
5365 06:02:47.320434 RX Delay -80 -> 252, step: 8
5366 06:02:47.323650 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5367 06:02:47.327216 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5368 06:02:47.330521 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5369 06:02:47.337265 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5370 06:02:47.340287 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5371 06:02:47.343967 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5372 06:02:47.346939 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5373 06:02:47.350609 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5374 06:02:47.353878 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5375 06:02:47.360271 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5376 06:02:47.363534 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5377 06:02:47.366916 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5378 06:02:47.370518 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5379 06:02:47.373525 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5380 06:02:47.377102 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5381 06:02:47.384015 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5382 06:02:47.384498 ==
5383 06:02:47.387393 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 06:02:47.390210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 06:02:47.390683 ==
5386 06:02:47.391053 DQS Delay:
5387 06:02:47.393511 DQS0 = 0, DQS1 = 0
5388 06:02:47.394009 DQM Delay:
5389 06:02:47.397137 DQM0 = 104, DQM1 = 90
5390 06:02:47.397624 DQ Delay:
5391 06:02:47.400260 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5392 06:02:47.403737 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5393 06:02:47.406711 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5394 06:02:47.409880 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5395 06:02:47.410406
5396 06:02:47.410778
5397 06:02:47.411154 ==
5398 06:02:47.413175 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 06:02:47.419910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 06:02:47.420382 ==
5401 06:02:47.420750
5402 06:02:47.421144
5403 06:02:47.421481 TX Vref Scan disable
5404 06:02:47.423395 == TX Byte 0 ==
5405 06:02:47.426754 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5406 06:02:47.430260 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5407 06:02:47.433603 == TX Byte 1 ==
5408 06:02:47.436560 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5409 06:02:47.443281 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5410 06:02:47.443750 ==
5411 06:02:47.446768 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 06:02:47.450221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 06:02:47.450815 ==
5414 06:02:47.451192
5415 06:02:47.451536
5416 06:02:47.453450 TX Vref Scan disable
5417 06:02:47.453994 == TX Byte 0 ==
5418 06:02:47.460416 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5419 06:02:47.463281 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5420 06:02:47.463749 == TX Byte 1 ==
5421 06:02:47.470047 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5422 06:02:47.473446 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5423 06:02:47.473974
5424 06:02:47.474390 [DATLAT]
5425 06:02:47.476862 Freq=933, CH0 RK1
5426 06:02:47.477450
5427 06:02:47.477826 DATLAT Default: 0xb
5428 06:02:47.480275 0, 0xFFFF, sum = 0
5429 06:02:47.480880 1, 0xFFFF, sum = 0
5430 06:02:47.483339 2, 0xFFFF, sum = 0
5431 06:02:47.483912 3, 0xFFFF, sum = 0
5432 06:02:47.486452 4, 0xFFFF, sum = 0
5433 06:02:47.486925 5, 0xFFFF, sum = 0
5434 06:02:47.489837 6, 0xFFFF, sum = 0
5435 06:02:47.493212 7, 0xFFFF, sum = 0
5436 06:02:47.493814 8, 0xFFFF, sum = 0
5437 06:02:47.496594 9, 0xFFFF, sum = 0
5438 06:02:47.497262 10, 0x0, sum = 1
5439 06:02:47.497765 11, 0x0, sum = 2
5440 06:02:47.500047 12, 0x0, sum = 3
5441 06:02:47.500534 13, 0x0, sum = 4
5442 06:02:47.503269 best_step = 11
5443 06:02:47.503832
5444 06:02:47.504246 ==
5445 06:02:47.506527 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 06:02:47.509740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 06:02:47.510268 ==
5448 06:02:47.513488 RX Vref Scan: 0
5449 06:02:47.514111
5450 06:02:47.514491 RX Vref 0 -> 0, step: 1
5451 06:02:47.514837
5452 06:02:47.516399 RX Delay -53 -> 252, step: 4
5453 06:02:47.523564 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5454 06:02:47.527240 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5455 06:02:47.530467 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5456 06:02:47.533591 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5457 06:02:47.536736 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5458 06:02:47.544046 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5459 06:02:47.546924 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5460 06:02:47.550885 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5461 06:02:47.553656 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5462 06:02:47.557069 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5463 06:02:47.560659 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5464 06:02:47.567057 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5465 06:02:47.570425 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5466 06:02:47.573628 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5467 06:02:47.577407 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5468 06:02:47.580470 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5469 06:02:47.583824 ==
5470 06:02:47.586900 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 06:02:47.590461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 06:02:47.590935 ==
5473 06:02:47.591307 DQS Delay:
5474 06:02:47.594037 DQS0 = 0, DQS1 = 0
5475 06:02:47.594604 DQM Delay:
5476 06:02:47.596808 DQM0 = 104, DQM1 = 92
5477 06:02:47.597483 DQ Delay:
5478 06:02:47.600114 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =98
5479 06:02:47.603899 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =112
5480 06:02:47.606946 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =92
5481 06:02:47.610366 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =96
5482 06:02:47.610836
5483 06:02:47.611207
5484 06:02:47.620301 [DQSOSCAuto] RK1, (LSB)MR18= 0x2405, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 410 ps
5485 06:02:47.620860 CH0 RK1: MR19=505, MR18=2405
5486 06:02:47.626678 CH0_RK1: MR19=0x505, MR18=0x2405, DQSOSC=410, MR23=63, INC=64, DEC=42
5487 06:02:47.629999 [RxdqsGatingPostProcess] freq 933
5488 06:02:47.636925 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5489 06:02:47.639837 best DQS0 dly(2T, 0.5T) = (0, 10)
5490 06:02:47.643201 best DQS1 dly(2T, 0.5T) = (0, 10)
5491 06:02:47.646327 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5492 06:02:47.649752 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5493 06:02:47.650382 best DQS0 dly(2T, 0.5T) = (0, 10)
5494 06:02:47.653123 best DQS1 dly(2T, 0.5T) = (0, 10)
5495 06:02:47.656237 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5496 06:02:47.659814 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5497 06:02:47.663088 Pre-setting of DQS Precalculation
5498 06:02:47.669801 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5499 06:02:47.670425 ==
5500 06:02:47.673108 Dram Type= 6, Freq= 0, CH_1, rank 0
5501 06:02:47.676329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 06:02:47.676915 ==
5503 06:02:47.683249 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5504 06:02:47.689246 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5505 06:02:47.692988 [CA 0] Center 37 (7~68) winsize 62
5506 06:02:47.696369 [CA 1] Center 37 (7~68) winsize 62
5507 06:02:47.699681 [CA 2] Center 36 (6~66) winsize 61
5508 06:02:47.702621 [CA 3] Center 34 (4~65) winsize 62
5509 06:02:47.706603 [CA 4] Center 34 (4~65) winsize 62
5510 06:02:47.709407 [CA 5] Center 34 (4~65) winsize 62
5511 06:02:47.710058
5512 06:02:47.712672 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5513 06:02:47.713243
5514 06:02:47.715871 [CATrainingPosCal] consider 1 rank data
5515 06:02:47.719391 u2DelayCellTimex100 = 270/100 ps
5516 06:02:47.722671 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5517 06:02:47.726153 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5518 06:02:47.729452 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5519 06:02:47.732737 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5520 06:02:47.736163 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5521 06:02:47.739714 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5522 06:02:47.740297
5523 06:02:47.745778 CA PerBit enable=1, Macro0, CA PI delay=34
5524 06:02:47.746429
5525 06:02:47.746969 [CBTSetCACLKResult] CA Dly = 34
5526 06:02:47.748833 CS Dly: 6 (0~37)
5527 06:02:47.749305 ==
5528 06:02:47.752507 Dram Type= 6, Freq= 0, CH_1, rank 1
5529 06:02:47.755495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 06:02:47.755976 ==
5531 06:02:47.762326 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5532 06:02:47.769074 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5533 06:02:47.772267 [CA 0] Center 38 (8~69) winsize 62
5534 06:02:47.775464 [CA 1] Center 38 (7~69) winsize 63
5535 06:02:47.778923 [CA 2] Center 35 (5~66) winsize 62
5536 06:02:47.782078 [CA 3] Center 35 (5~65) winsize 61
5537 06:02:47.785433 [CA 4] Center 35 (6~65) winsize 60
5538 06:02:47.788835 [CA 5] Center 35 (5~65) winsize 61
5539 06:02:47.789279
5540 06:02:47.792017 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5541 06:02:47.792509
5542 06:02:47.795515 [CATrainingPosCal] consider 2 rank data
5543 06:02:47.798782 u2DelayCellTimex100 = 270/100 ps
5544 06:02:47.801912 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5545 06:02:47.805903 CA1 delay=37 (7~68),Diff = 2 PI (12 cell)
5546 06:02:47.808846 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5547 06:02:47.811863 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5548 06:02:47.815573 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
5549 06:02:47.818607 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5550 06:02:47.822021
5551 06:02:47.825235 CA PerBit enable=1, Macro0, CA PI delay=35
5552 06:02:47.825886
5553 06:02:47.828917 [CBTSetCACLKResult] CA Dly = 35
5554 06:02:47.829674 CS Dly: 7 (0~39)
5555 06:02:47.830311
5556 06:02:47.832389 ----->DramcWriteLeveling(PI) begin...
5557 06:02:47.833104 ==
5558 06:02:47.835632 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 06:02:47.839017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 06:02:47.842022 ==
5561 06:02:47.842594 Write leveling (Byte 0): 29 => 29
5562 06:02:47.845650 Write leveling (Byte 1): 30 => 30
5563 06:02:47.848640 DramcWriteLeveling(PI) end<-----
5564 06:02:47.849118
5565 06:02:47.849603 ==
5566 06:02:47.852207 Dram Type= 6, Freq= 0, CH_1, rank 0
5567 06:02:47.858911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 06:02:47.859394 ==
5569 06:02:47.859771 [Gating] SW mode calibration
5570 06:02:47.868896 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5571 06:02:47.872165 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5572 06:02:47.875220 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 06:02:47.882153 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 06:02:47.885238 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 06:02:47.888668 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 06:02:47.895471 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 06:02:47.898511 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5578 06:02:47.902001 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5579 06:02:47.908664 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5580 06:02:47.911870 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 06:02:47.915326 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 06:02:47.922352 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 06:02:47.925612 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 06:02:47.928287 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 06:02:47.934822 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 06:02:47.938523 0 15 24 | B1->B0 | 2828 2f2f | 0 0 | (1 1) (1 1)
5587 06:02:47.941817 0 15 28 | B1->B0 | 3c3c 4040 | 0 0 | (0 0) (0 0)
5588 06:02:47.948312 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 06:02:47.951542 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 06:02:47.954774 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 06:02:47.961704 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 06:02:47.965157 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 06:02:47.968138 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5594 06:02:47.974977 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5595 06:02:47.978234 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 06:02:47.981569 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 06:02:47.988077 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 06:02:47.991443 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 06:02:47.995329 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 06:02:48.001306 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 06:02:48.004836 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 06:02:48.008050 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 06:02:48.014479 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 06:02:48.017983 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 06:02:48.021225 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 06:02:48.027624 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 06:02:48.031056 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 06:02:48.034605 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 06:02:48.037782 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5610 06:02:48.044366 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5611 06:02:48.048003 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 06:02:48.051083 Total UI for P1: 0, mck2ui 16
5613 06:02:48.055068 best dqsien dly found for B0: ( 1, 2, 22)
5614 06:02:48.057779 Total UI for P1: 0, mck2ui 16
5615 06:02:48.061161 best dqsien dly found for B1: ( 1, 2, 24)
5616 06:02:48.064635 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5617 06:02:48.068005 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5618 06:02:48.068474
5619 06:02:48.071210 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5620 06:02:48.074437 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5621 06:02:48.077875 [Gating] SW calibration Done
5622 06:02:48.078377 ==
5623 06:02:48.081445 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 06:02:48.087898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 06:02:48.088373 ==
5626 06:02:48.088750 RX Vref Scan: 0
5627 06:02:48.089101
5628 06:02:48.091257 RX Vref 0 -> 0, step: 1
5629 06:02:48.091844
5630 06:02:48.094205 RX Delay -80 -> 252, step: 8
5631 06:02:48.097673 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5632 06:02:48.100839 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5633 06:02:48.104446 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5634 06:02:48.107691 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5635 06:02:48.111006 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5636 06:02:48.117592 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5637 06:02:48.120894 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5638 06:02:48.124550 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5639 06:02:48.127656 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5640 06:02:48.130865 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5641 06:02:48.137655 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5642 06:02:48.140740 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5643 06:02:48.144084 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5644 06:02:48.147448 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5645 06:02:48.150802 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5646 06:02:48.153898 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5647 06:02:48.154517 ==
5648 06:02:48.157568 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 06:02:48.164400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 06:02:48.164974 ==
5651 06:02:48.165349 DQS Delay:
5652 06:02:48.167488 DQS0 = 0, DQS1 = 0
5653 06:02:48.167959 DQM Delay:
5654 06:02:48.168335 DQM0 = 102, DQM1 = 95
5655 06:02:48.170800 DQ Delay:
5656 06:02:48.174656 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5657 06:02:48.178184 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5658 06:02:48.180847 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5659 06:02:48.184366 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5660 06:02:48.184838
5661 06:02:48.185213
5662 06:02:48.185560 ==
5663 06:02:48.187568 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 06:02:48.190923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 06:02:48.191400 ==
5666 06:02:48.191776
5667 06:02:48.192256
5668 06:02:48.194290 TX Vref Scan disable
5669 06:02:48.197295 == TX Byte 0 ==
5670 06:02:48.200591 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5671 06:02:48.204370 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5672 06:02:48.207598 == TX Byte 1 ==
5673 06:02:48.210812 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5674 06:02:48.213908 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5675 06:02:48.214415 ==
5676 06:02:48.217239 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 06:02:48.220804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 06:02:48.223929 ==
5679 06:02:48.224412
5680 06:02:48.224782
5681 06:02:48.225126 TX Vref Scan disable
5682 06:02:48.228072 == TX Byte 0 ==
5683 06:02:48.231485 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5684 06:02:48.237828 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5685 06:02:48.238340 == TX Byte 1 ==
5686 06:02:48.241023 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5687 06:02:48.247809 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5688 06:02:48.248368
5689 06:02:48.248744 [DATLAT]
5690 06:02:48.249096 Freq=933, CH1 RK0
5691 06:02:48.249438
5692 06:02:48.250816 DATLAT Default: 0xd
5693 06:02:48.251286 0, 0xFFFF, sum = 0
5694 06:02:48.254142 1, 0xFFFF, sum = 0
5695 06:02:48.254621 2, 0xFFFF, sum = 0
5696 06:02:48.257852 3, 0xFFFF, sum = 0
5697 06:02:48.258371 4, 0xFFFF, sum = 0
5698 06:02:48.261076 5, 0xFFFF, sum = 0
5699 06:02:48.264593 6, 0xFFFF, sum = 0
5700 06:02:48.265169 7, 0xFFFF, sum = 0
5701 06:02:48.268011 8, 0xFFFF, sum = 0
5702 06:02:48.268512 9, 0xFFFF, sum = 0
5703 06:02:48.271056 10, 0x0, sum = 1
5704 06:02:48.271635 11, 0x0, sum = 2
5705 06:02:48.272025 12, 0x0, sum = 3
5706 06:02:48.274196 13, 0x0, sum = 4
5707 06:02:48.274672 best_step = 11
5708 06:02:48.275047
5709 06:02:48.277678 ==
5710 06:02:48.278301 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 06:02:48.284055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 06:02:48.284531 ==
5713 06:02:48.284901 RX Vref Scan: 1
5714 06:02:48.285253
5715 06:02:48.287758 RX Vref 0 -> 0, step: 1
5716 06:02:48.288333
5717 06:02:48.290902 RX Delay -53 -> 252, step: 4
5718 06:02:48.291373
5719 06:02:48.294152 Set Vref, RX VrefLevel [Byte0]: 54
5720 06:02:48.297704 [Byte1]: 53
5721 06:02:48.298301
5722 06:02:48.300879 Final RX Vref Byte 0 = 54 to rank0
5723 06:02:48.304148 Final RX Vref Byte 1 = 53 to rank0
5724 06:02:48.307405 Final RX Vref Byte 0 = 54 to rank1
5725 06:02:48.311144 Final RX Vref Byte 1 = 53 to rank1==
5726 06:02:48.313926 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 06:02:48.317541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 06:02:48.318066 ==
5729 06:02:48.320993 DQS Delay:
5730 06:02:48.321589 DQS0 = 0, DQS1 = 0
5731 06:02:48.324106 DQM Delay:
5732 06:02:48.324672 DQM0 = 104, DQM1 = 97
5733 06:02:48.325056 DQ Delay:
5734 06:02:48.327302 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5735 06:02:48.334320 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5736 06:02:48.334812 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =92
5737 06:02:48.340740 DQ12 =106, DQ13 =102, DQ14 =106, DQ15 =102
5738 06:02:48.341298
5739 06:02:48.341675
5740 06:02:48.347298 [DQSOSCAuto] RK0, (LSB)MR18= 0x1931, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5741 06:02:48.350863 CH1 RK0: MR19=505, MR18=1931
5742 06:02:48.357210 CH1_RK0: MR19=0x505, MR18=0x1931, DQSOSC=406, MR23=63, INC=65, DEC=43
5743 06:02:48.357749
5744 06:02:48.360330 ----->DramcWriteLeveling(PI) begin...
5745 06:02:48.360809 ==
5746 06:02:48.364315 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 06:02:48.367009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 06:02:48.367487 ==
5749 06:02:48.370735 Write leveling (Byte 0): 27 => 27
5750 06:02:48.373879 Write leveling (Byte 1): 26 => 26
5751 06:02:48.377455 DramcWriteLeveling(PI) end<-----
5752 06:02:48.378068
5753 06:02:48.378447 ==
5754 06:02:48.380950 Dram Type= 6, Freq= 0, CH_1, rank 1
5755 06:02:48.383898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 06:02:48.384377 ==
5757 06:02:48.387106 [Gating] SW mode calibration
5758 06:02:48.394245 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5759 06:02:48.400332 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5760 06:02:48.403627 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5761 06:02:48.410251 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 06:02:48.413657 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 06:02:48.416961 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 06:02:48.423707 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 06:02:48.426748 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 06:02:48.430010 0 14 24 | B1->B0 | 3030 3333 | 0 1 | (1 0) (1 0)
5767 06:02:48.437046 0 14 28 | B1->B0 | 2323 2a2a | 0 1 | (1 0) (1 0)
5768 06:02:48.439939 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5769 06:02:48.443536 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 06:02:48.449865 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 06:02:48.453451 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 06:02:48.456439 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 06:02:48.463736 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 06:02:48.467021 0 15 24 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5775 06:02:48.470074 0 15 28 | B1->B0 | 3c3c 3434 | 0 1 | (1 1) (0 0)
5776 06:02:48.476422 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5777 06:02:48.480178 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 06:02:48.483389 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 06:02:48.486917 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 06:02:48.493608 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 06:02:48.496704 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5782 06:02:48.499750 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5783 06:02:48.506358 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5784 06:02:48.509681 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 06:02:48.513301 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 06:02:48.519849 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 06:02:48.523136 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 06:02:48.526468 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 06:02:48.533038 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 06:02:48.536233 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 06:02:48.539610 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 06:02:48.546460 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 06:02:48.549652 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 06:02:48.553418 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 06:02:48.559436 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 06:02:48.563105 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 06:02:48.566312 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 06:02:48.573172 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 06:02:48.576206 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 06:02:48.579372 Total UI for P1: 0, mck2ui 16
5801 06:02:48.582601 best dqsien dly found for B0: ( 1, 2, 26)
5802 06:02:48.586310 Total UI for P1: 0, mck2ui 16
5803 06:02:48.589484 best dqsien dly found for B1: ( 1, 2, 26)
5804 06:02:48.592500 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5805 06:02:48.596545 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5806 06:02:48.597121
5807 06:02:48.599248 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5808 06:02:48.602561 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5809 06:02:48.605971 [Gating] SW calibration Done
5810 06:02:48.606456 ==
5811 06:02:48.609307 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 06:02:48.612866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 06:02:48.615953 ==
5814 06:02:48.616445 RX Vref Scan: 0
5815 06:02:48.616827
5816 06:02:48.618997 RX Vref 0 -> 0, step: 1
5817 06:02:48.619495
5818 06:02:48.622461 RX Delay -80 -> 252, step: 8
5819 06:02:48.625649 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5820 06:02:48.629351 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5821 06:02:48.632346 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5822 06:02:48.635494 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5823 06:02:48.639276 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5824 06:02:48.645804 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5825 06:02:48.649172 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5826 06:02:48.652262 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5827 06:02:48.655851 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5828 06:02:48.658895 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5829 06:02:48.662300 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5830 06:02:48.668701 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5831 06:02:48.672098 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5832 06:02:48.675783 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5833 06:02:48.678910 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5834 06:02:48.682128 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5835 06:02:48.682753 ==
5836 06:02:48.685740 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 06:02:48.692467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 06:02:48.693056 ==
5839 06:02:48.693442 DQS Delay:
5840 06:02:48.695272 DQS0 = 0, DQS1 = 0
5841 06:02:48.695752 DQM Delay:
5842 06:02:48.696133 DQM0 = 101, DQM1 = 96
5843 06:02:48.698512 DQ Delay:
5844 06:02:48.702052 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5845 06:02:48.705465 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5846 06:02:48.708713 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5847 06:02:48.712438 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5848 06:02:48.712991
5849 06:02:48.713434
5850 06:02:48.713806 ==
5851 06:02:48.715563 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 06:02:48.718695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 06:02:48.719175 ==
5854 06:02:48.719548
5855 06:02:48.720055
5856 06:02:48.721790 TX Vref Scan disable
5857 06:02:48.725157 == TX Byte 0 ==
5858 06:02:48.728458 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5859 06:02:48.731914 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5860 06:02:48.735305 == TX Byte 1 ==
5861 06:02:48.738399 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5862 06:02:48.741863 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5863 06:02:48.742381 ==
5864 06:02:48.745038 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 06:02:48.751567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 06:02:48.752064 ==
5867 06:02:48.752448
5868 06:02:48.752800
5869 06:02:48.753136 TX Vref Scan disable
5870 06:02:48.755772 == TX Byte 0 ==
5871 06:02:48.759017 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5872 06:02:48.765452 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5873 06:02:48.765795 == TX Byte 1 ==
5874 06:02:48.768790 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5875 06:02:48.775898 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5876 06:02:48.776337
5877 06:02:48.776618 [DATLAT]
5878 06:02:48.776870 Freq=933, CH1 RK1
5879 06:02:48.777113
5880 06:02:48.779203 DATLAT Default: 0xb
5881 06:02:48.779647 0, 0xFFFF, sum = 0
5882 06:02:48.782114 1, 0xFFFF, sum = 0
5883 06:02:48.782460 2, 0xFFFF, sum = 0
5884 06:02:48.785636 3, 0xFFFF, sum = 0
5885 06:02:48.788655 4, 0xFFFF, sum = 0
5886 06:02:48.788995 5, 0xFFFF, sum = 0
5887 06:02:48.792026 6, 0xFFFF, sum = 0
5888 06:02:48.792368 7, 0xFFFF, sum = 0
5889 06:02:48.795373 8, 0xFFFF, sum = 0
5890 06:02:48.795715 9, 0xFFFF, sum = 0
5891 06:02:48.798897 10, 0x0, sum = 1
5892 06:02:48.799241 11, 0x0, sum = 2
5893 06:02:48.799515 12, 0x0, sum = 3
5894 06:02:48.802429 13, 0x0, sum = 4
5895 06:02:48.802771 best_step = 11
5896 06:02:48.803043
5897 06:02:48.803294 ==
5898 06:02:48.805736 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 06:02:48.811906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 06:02:48.812247 ==
5901 06:02:48.812515 RX Vref Scan: 0
5902 06:02:48.812765
5903 06:02:48.815583 RX Vref 0 -> 0, step: 1
5904 06:02:48.815940
5905 06:02:48.818725 RX Delay -53 -> 252, step: 4
5906 06:02:48.822125 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5907 06:02:48.828694 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5908 06:02:48.832033 iDelay=199, Bit 2, Center 92 (11 ~ 174) 164
5909 06:02:48.835265 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5910 06:02:48.838741 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5911 06:02:48.841960 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5912 06:02:48.848358 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5913 06:02:48.852047 iDelay=199, Bit 7, Center 100 (19 ~ 182) 164
5914 06:02:48.855008 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5915 06:02:48.858508 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5916 06:02:48.861769 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5917 06:02:48.865189 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5918 06:02:48.871500 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5919 06:02:48.875143 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5920 06:02:48.878124 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5921 06:02:48.881569 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5922 06:02:48.882000 ==
5923 06:02:48.884835 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 06:02:48.891353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 06:02:48.891879 ==
5926 06:02:48.892164 DQS Delay:
5927 06:02:48.895565 DQS0 = 0, DQS1 = 0
5928 06:02:48.896010 DQM Delay:
5929 06:02:48.898165 DQM0 = 104, DQM1 = 97
5930 06:02:48.898503 DQ Delay:
5931 06:02:48.901413 DQ0 =108, DQ1 =98, DQ2 =92, DQ3 =102
5932 06:02:48.904631 DQ4 =106, DQ5 =116, DQ6 =112, DQ7 =100
5933 06:02:48.907846 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =90
5934 06:02:48.911575 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
5935 06:02:48.911925
5936 06:02:48.912192
5937 06:02:48.921103 [DQSOSCAuto] RK1, (LSB)MR18= 0x1ffb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 412 ps
5938 06:02:48.921522 CH1 RK1: MR19=504, MR18=1FFB
5939 06:02:48.928012 CH1_RK1: MR19=0x504, MR18=0x1FFB, DQSOSC=412, MR23=63, INC=63, DEC=42
5940 06:02:48.931085 [RxdqsGatingPostProcess] freq 933
5941 06:02:48.937612 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5942 06:02:48.941019 best DQS0 dly(2T, 0.5T) = (0, 10)
5943 06:02:48.944570 best DQS1 dly(2T, 0.5T) = (0, 10)
5944 06:02:48.947506 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5945 06:02:48.951213 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5946 06:02:48.954364 best DQS0 dly(2T, 0.5T) = (0, 10)
5947 06:02:48.954825 best DQS1 dly(2T, 0.5T) = (0, 10)
5948 06:02:48.957523 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5949 06:02:48.960696 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5950 06:02:48.964240 Pre-setting of DQS Precalculation
5951 06:02:48.970877 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5952 06:02:48.977378 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5953 06:02:48.984071 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5954 06:02:48.984478
5955 06:02:48.984746
5956 06:02:48.987257 [Calibration Summary] 1866 Mbps
5957 06:02:48.987669 CH 0, Rank 0
5958 06:02:48.990786 SW Impedance : PASS
5959 06:02:48.994300 DUTY Scan : NO K
5960 06:02:48.994741 ZQ Calibration : PASS
5961 06:02:48.997387 Jitter Meter : NO K
5962 06:02:49.000579 CBT Training : PASS
5963 06:02:49.000927 Write leveling : PASS
5964 06:02:49.003881 RX DQS gating : PASS
5965 06:02:49.007226 RX DQ/DQS(RDDQC) : PASS
5966 06:02:49.007664 TX DQ/DQS : PASS
5967 06:02:49.010898 RX DATLAT : PASS
5968 06:02:49.014074 RX DQ/DQS(Engine): PASS
5969 06:02:49.014516 TX OE : NO K
5970 06:02:49.017431 All Pass.
5971 06:02:49.017847
5972 06:02:49.018294 CH 0, Rank 1
5973 06:02:49.020365 SW Impedance : PASS
5974 06:02:49.020753 DUTY Scan : NO K
5975 06:02:49.024134 ZQ Calibration : PASS
5976 06:02:49.027126 Jitter Meter : NO K
5977 06:02:49.027556 CBT Training : PASS
5978 06:02:49.030211 Write leveling : PASS
5979 06:02:49.033561 RX DQS gating : PASS
5980 06:02:49.034009 RX DQ/DQS(RDDQC) : PASS
5981 06:02:49.037305 TX DQ/DQS : PASS
5982 06:02:49.040634 RX DATLAT : PASS
5983 06:02:49.041143 RX DQ/DQS(Engine): PASS
5984 06:02:49.043829 TX OE : NO K
5985 06:02:49.044264 All Pass.
5986 06:02:49.044607
5987 06:02:49.044869 CH 1, Rank 0
5988 06:02:49.046861 SW Impedance : PASS
5989 06:02:49.050404 DUTY Scan : NO K
5990 06:02:49.050731 ZQ Calibration : PASS
5991 06:02:49.053456 Jitter Meter : NO K
5992 06:02:49.056836 CBT Training : PASS
5993 06:02:49.057259 Write leveling : PASS
5994 06:02:49.060577 RX DQS gating : PASS
5995 06:02:49.063856 RX DQ/DQS(RDDQC) : PASS
5996 06:02:49.064288 TX DQ/DQS : PASS
5997 06:02:49.067277 RX DATLAT : PASS
5998 06:02:49.070096 RX DQ/DQS(Engine): PASS
5999 06:02:49.070569 TX OE : NO K
6000 06:02:49.073716 All Pass.
6001 06:02:49.074306
6002 06:02:49.074659 CH 1, Rank 1
6003 06:02:49.077040 SW Impedance : PASS
6004 06:02:49.077589 DUTY Scan : NO K
6005 06:02:49.080056 ZQ Calibration : PASS
6006 06:02:49.083731 Jitter Meter : NO K
6007 06:02:49.084264 CBT Training : PASS
6008 06:02:49.087067 Write leveling : PASS
6009 06:02:49.090303 RX DQS gating : PASS
6010 06:02:49.090857 RX DQ/DQS(RDDQC) : PASS
6011 06:02:49.093335 TX DQ/DQS : PASS
6012 06:02:49.096705 RX DATLAT : PASS
6013 06:02:49.097182 RX DQ/DQS(Engine): PASS
6014 06:02:49.099987 TX OE : NO K
6015 06:02:49.100465 All Pass.
6016 06:02:49.100845
6017 06:02:49.103283 DramC Write-DBI off
6018 06:02:49.106619 PER_BANK_REFRESH: Hybrid Mode
6019 06:02:49.107096 TX_TRACKING: ON
6020 06:02:49.117323 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6021 06:02:49.120069 [FAST_K] Save calibration result to emmc
6022 06:02:49.124043 dramc_set_vcore_voltage set vcore to 650000
6023 06:02:49.124640 Read voltage for 400, 6
6024 06:02:49.127058 Vio18 = 0
6025 06:02:49.127530 Vcore = 650000
6026 06:02:49.127908 Vdram = 0
6027 06:02:49.130135 Vddq = 0
6028 06:02:49.130609 Vmddr = 0
6029 06:02:49.133512 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6030 06:02:49.140011 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6031 06:02:49.143462 MEM_TYPE=3, freq_sel=20
6032 06:02:49.146697 sv_algorithm_assistance_LP4_800
6033 06:02:49.150148 ============ PULL DRAM RESETB DOWN ============
6034 06:02:49.153545 ========== PULL DRAM RESETB DOWN end =========
6035 06:02:49.159957 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6036 06:02:49.163436 ===================================
6037 06:02:49.163868 LPDDR4 DRAM CONFIGURATION
6038 06:02:49.166653 ===================================
6039 06:02:49.169983 EX_ROW_EN[0] = 0x0
6040 06:02:49.170452 EX_ROW_EN[1] = 0x0
6041 06:02:49.173155 LP4Y_EN = 0x0
6042 06:02:49.173599 WORK_FSP = 0x0
6043 06:02:49.176823 WL = 0x2
6044 06:02:49.177333 RL = 0x2
6045 06:02:49.179840 BL = 0x2
6046 06:02:49.183182 RPST = 0x0
6047 06:02:49.183611 RD_PRE = 0x0
6048 06:02:49.186714 WR_PRE = 0x1
6049 06:02:49.187147 WR_PST = 0x0
6050 06:02:49.190090 DBI_WR = 0x0
6051 06:02:49.190522 DBI_RD = 0x0
6052 06:02:49.193407 OTF = 0x1
6053 06:02:49.196803 ===================================
6054 06:02:49.199831 ===================================
6055 06:02:49.200332 ANA top config
6056 06:02:49.203627 ===================================
6057 06:02:49.206455 DLL_ASYNC_EN = 0
6058 06:02:49.210442 ALL_SLAVE_EN = 1
6059 06:02:49.210951 NEW_RANK_MODE = 1
6060 06:02:49.213598 DLL_IDLE_MODE = 1
6061 06:02:49.216991 LP45_APHY_COMB_EN = 1
6062 06:02:49.220205 TX_ODT_DIS = 1
6063 06:02:49.220749 NEW_8X_MODE = 1
6064 06:02:49.223543 ===================================
6065 06:02:49.226717 ===================================
6066 06:02:49.230187 data_rate = 800
6067 06:02:49.233271 CKR = 1
6068 06:02:49.236816 DQ_P2S_RATIO = 4
6069 06:02:49.240129 ===================================
6070 06:02:49.243565 CA_P2S_RATIO = 4
6071 06:02:49.246733 DQ_CA_OPEN = 0
6072 06:02:49.247213 DQ_SEMI_OPEN = 1
6073 06:02:49.250184 CA_SEMI_OPEN = 1
6074 06:02:49.253264 CA_FULL_RATE = 0
6075 06:02:49.256807 DQ_CKDIV4_EN = 0
6076 06:02:49.259784 CA_CKDIV4_EN = 1
6077 06:02:49.263084 CA_PREDIV_EN = 0
6078 06:02:49.263563 PH8_DLY = 0
6079 06:02:49.266885 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6080 06:02:49.269931 DQ_AAMCK_DIV = 0
6081 06:02:49.273245 CA_AAMCK_DIV = 0
6082 06:02:49.276267 CA_ADMCK_DIV = 4
6083 06:02:49.279756 DQ_TRACK_CA_EN = 0
6084 06:02:49.280320 CA_PICK = 800
6085 06:02:49.283170 CA_MCKIO = 400
6086 06:02:49.286724 MCKIO_SEMI = 400
6087 06:02:49.289691 PLL_FREQ = 3016
6088 06:02:49.293205 DQ_UI_PI_RATIO = 32
6089 06:02:49.296800 CA_UI_PI_RATIO = 32
6090 06:02:49.300155 ===================================
6091 06:02:49.303070 ===================================
6092 06:02:49.306283 memory_type:LPDDR4
6093 06:02:49.306756 GP_NUM : 10
6094 06:02:49.309533 SRAM_EN : 1
6095 06:02:49.310035 MD32_EN : 0
6096 06:02:49.313182 ===================================
6097 06:02:49.316569 [ANA_INIT] >>>>>>>>>>>>>>
6098 06:02:49.319815 <<<<<< [CONFIGURE PHASE]: ANA_TX
6099 06:02:49.323365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6100 06:02:49.326067 ===================================
6101 06:02:49.329860 data_rate = 800,PCW = 0X7400
6102 06:02:49.332844 ===================================
6103 06:02:49.336031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6104 06:02:49.339492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6105 06:02:49.352759 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6106 06:02:49.356293 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6107 06:02:49.359821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6108 06:02:49.362934 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6109 06:02:49.366030 [ANA_INIT] flow start
6110 06:02:49.369503 [ANA_INIT] PLL >>>>>>>>
6111 06:02:49.369926 [ANA_INIT] PLL <<<<<<<<
6112 06:02:49.372884 [ANA_INIT] MIDPI >>>>>>>>
6113 06:02:49.376253 [ANA_INIT] MIDPI <<<<<<<<
6114 06:02:49.376799 [ANA_INIT] DLL >>>>>>>>
6115 06:02:49.379143 [ANA_INIT] flow end
6116 06:02:49.383014 ============ LP4 DIFF to SE enter ============
6117 06:02:49.389161 ============ LP4 DIFF to SE exit ============
6118 06:02:49.389663 [ANA_INIT] <<<<<<<<<<<<<
6119 06:02:49.392844 [Flow] Enable top DCM control >>>>>
6120 06:02:49.396216 [Flow] Enable top DCM control <<<<<
6121 06:02:49.399110 Enable DLL master slave shuffle
6122 06:02:49.405649 ==============================================================
6123 06:02:49.406291 Gating Mode config
6124 06:02:49.412584 ==============================================================
6125 06:02:49.415947 Config description:
6126 06:02:49.422747 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6127 06:02:49.429162 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6128 06:02:49.435870 SELPH_MODE 0: By rank 1: By Phase
6129 06:02:49.442290 ==============================================================
6130 06:02:49.442818 GAT_TRACK_EN = 0
6131 06:02:49.445597 RX_GATING_MODE = 2
6132 06:02:49.449055 RX_GATING_TRACK_MODE = 2
6133 06:02:49.452684 SELPH_MODE = 1
6134 06:02:49.455673 PICG_EARLY_EN = 1
6135 06:02:49.458885 VALID_LAT_VALUE = 1
6136 06:02:49.465644 ==============================================================
6137 06:02:49.469090 Enter into Gating configuration >>>>
6138 06:02:49.472322 Exit from Gating configuration <<<<
6139 06:02:49.475644 Enter into DVFS_PRE_config >>>>>
6140 06:02:49.486180 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6141 06:02:49.489376 Exit from DVFS_PRE_config <<<<<
6142 06:02:49.492646 Enter into PICG configuration >>>>
6143 06:02:49.495757 Exit from PICG configuration <<<<
6144 06:02:49.499151 [RX_INPUT] configuration >>>>>
6145 06:02:49.499622 [RX_INPUT] configuration <<<<<
6146 06:02:49.505564 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6147 06:02:49.512685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6148 06:02:49.515502 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6149 06:02:49.522326 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6150 06:02:49.528672 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6151 06:02:49.535926 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6152 06:02:49.538897 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6153 06:02:49.542510 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6154 06:02:49.548690 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6155 06:02:49.552489 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6156 06:02:49.555578 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6157 06:02:49.562363 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6158 06:02:49.565475 ===================================
6159 06:02:49.565973 LPDDR4 DRAM CONFIGURATION
6160 06:02:49.568829 ===================================
6161 06:02:49.572162 EX_ROW_EN[0] = 0x0
6162 06:02:49.572638 EX_ROW_EN[1] = 0x0
6163 06:02:49.575877 LP4Y_EN = 0x0
6164 06:02:49.576451 WORK_FSP = 0x0
6165 06:02:49.578672 WL = 0x2
6166 06:02:49.579148 RL = 0x2
6167 06:02:49.581891 BL = 0x2
6168 06:02:49.585704 RPST = 0x0
6169 06:02:49.586276 RD_PRE = 0x0
6170 06:02:49.589051 WR_PRE = 0x1
6171 06:02:49.589632 WR_PST = 0x0
6172 06:02:49.592195 DBI_WR = 0x0
6173 06:02:49.592764 DBI_RD = 0x0
6174 06:02:49.595449 OTF = 0x1
6175 06:02:49.598541 ===================================
6176 06:02:49.601955 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6177 06:02:49.605552 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6178 06:02:49.608859 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6179 06:02:49.611759 ===================================
6180 06:02:49.615113 LPDDR4 DRAM CONFIGURATION
6181 06:02:49.618516 ===================================
6182 06:02:49.621832 EX_ROW_EN[0] = 0x10
6183 06:02:49.622423 EX_ROW_EN[1] = 0x0
6184 06:02:49.625256 LP4Y_EN = 0x0
6185 06:02:49.625827 WORK_FSP = 0x0
6186 06:02:49.628352 WL = 0x2
6187 06:02:49.628828 RL = 0x2
6188 06:02:49.631676 BL = 0x2
6189 06:02:49.632149 RPST = 0x0
6190 06:02:49.635228 RD_PRE = 0x0
6191 06:02:49.638132 WR_PRE = 0x1
6192 06:02:49.638605 WR_PST = 0x0
6193 06:02:49.641667 DBI_WR = 0x0
6194 06:02:49.642164 DBI_RD = 0x0
6195 06:02:49.644989 OTF = 0x1
6196 06:02:49.648600 ===================================
6197 06:02:49.651624 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6198 06:02:49.656949 nWR fixed to 30
6199 06:02:49.660355 [ModeRegInit_LP4] CH0 RK0
6200 06:02:49.660828 [ModeRegInit_LP4] CH0 RK1
6201 06:02:49.663572 [ModeRegInit_LP4] CH1 RK0
6202 06:02:49.666990 [ModeRegInit_LP4] CH1 RK1
6203 06:02:49.667529 match AC timing 19
6204 06:02:49.674028 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6205 06:02:49.677178 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6206 06:02:49.680092 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6207 06:02:49.687174 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6208 06:02:49.690323 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6209 06:02:49.690795 ==
6210 06:02:49.693407 Dram Type= 6, Freq= 0, CH_0, rank 0
6211 06:02:49.697026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6212 06:02:49.697573 ==
6213 06:02:49.703354 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6214 06:02:49.710166 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6215 06:02:49.713293 [CA 0] Center 36 (8~64) winsize 57
6216 06:02:49.717083 [CA 1] Center 36 (8~64) winsize 57
6217 06:02:49.720459 [CA 2] Center 36 (8~64) winsize 57
6218 06:02:49.721035 [CA 3] Center 36 (8~64) winsize 57
6219 06:02:49.723383 [CA 4] Center 36 (8~64) winsize 57
6220 06:02:49.726969 [CA 5] Center 36 (8~64) winsize 57
6221 06:02:49.727443
6222 06:02:49.730142 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6223 06:02:49.733390
6224 06:02:49.736861 [CATrainingPosCal] consider 1 rank data
6225 06:02:49.737350 u2DelayCellTimex100 = 270/100 ps
6226 06:02:49.743733 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 06:02:49.746976 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 06:02:49.750188 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 06:02:49.753626 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 06:02:49.756606 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 06:02:49.760322 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 06:02:49.760797
6233 06:02:49.763491 CA PerBit enable=1, Macro0, CA PI delay=36
6234 06:02:49.763965
6235 06:02:49.766857 [CBTSetCACLKResult] CA Dly = 36
6236 06:02:49.770043 CS Dly: 1 (0~32)
6237 06:02:49.770533 ==
6238 06:02:49.773335 Dram Type= 6, Freq= 0, CH_0, rank 1
6239 06:02:49.776676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6240 06:02:49.777219 ==
6241 06:02:49.783629 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6242 06:02:49.786471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6243 06:02:49.790067 [CA 0] Center 36 (8~64) winsize 57
6244 06:02:49.793150 [CA 1] Center 36 (8~64) winsize 57
6245 06:02:49.796255 [CA 2] Center 36 (8~64) winsize 57
6246 06:02:49.799742 [CA 3] Center 36 (8~64) winsize 57
6247 06:02:49.803098 [CA 4] Center 36 (8~64) winsize 57
6248 06:02:49.806664 [CA 5] Center 36 (8~64) winsize 57
6249 06:02:49.807209
6250 06:02:49.810060 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6251 06:02:49.810532
6252 06:02:49.813154 [CATrainingPosCal] consider 2 rank data
6253 06:02:49.816396 u2DelayCellTimex100 = 270/100 ps
6254 06:02:49.819680 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 06:02:49.823123 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 06:02:49.826533 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 06:02:49.832987 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 06:02:49.836244 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 06:02:49.839602 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 06:02:49.840073
6261 06:02:49.843058 CA PerBit enable=1, Macro0, CA PI delay=36
6262 06:02:49.843528
6263 06:02:49.846263 [CBTSetCACLKResult] CA Dly = 36
6264 06:02:49.846689 CS Dly: 1 (0~32)
6265 06:02:49.847028
6266 06:02:49.849694 ----->DramcWriteLeveling(PI) begin...
6267 06:02:49.850154 ==
6268 06:02:49.852960 Dram Type= 6, Freq= 0, CH_0, rank 0
6269 06:02:49.859562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 06:02:49.860000 ==
6271 06:02:49.862794 Write leveling (Byte 0): 40 => 8
6272 06:02:49.866378 Write leveling (Byte 1): 32 => 0
6273 06:02:49.866877 DramcWriteLeveling(PI) end<-----
6274 06:02:49.867219
6275 06:02:49.869678 ==
6276 06:02:49.873190 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 06:02:49.876294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 06:02:49.876728 ==
6279 06:02:49.879633 [Gating] SW mode calibration
6280 06:02:49.886155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6281 06:02:49.890087 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6282 06:02:49.896282 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6283 06:02:49.899605 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6284 06:02:49.903291 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6285 06:02:49.909332 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 06:02:49.912602 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 06:02:49.916217 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 06:02:49.922955 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 06:02:49.926174 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 06:02:49.929755 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6291 06:02:49.933100 Total UI for P1: 0, mck2ui 16
6292 06:02:49.936316 best dqsien dly found for B0: ( 0, 14, 24)
6293 06:02:49.939308 Total UI for P1: 0, mck2ui 16
6294 06:02:49.942740 best dqsien dly found for B1: ( 0, 14, 24)
6295 06:02:49.946271 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6296 06:02:49.949332 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6297 06:02:49.949792
6298 06:02:49.956101 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6299 06:02:49.959398 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6300 06:02:49.959874 [Gating] SW calibration Done
6301 06:02:49.962798 ==
6302 06:02:49.963259 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 06:02:49.969482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 06:02:49.970076 ==
6305 06:02:49.970455 RX Vref Scan: 0
6306 06:02:49.970799
6307 06:02:49.972632 RX Vref 0 -> 0, step: 1
6308 06:02:49.973086
6309 06:02:49.976330 RX Delay -410 -> 252, step: 16
6310 06:02:49.979613 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6311 06:02:49.982852 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6312 06:02:49.989684 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6313 06:02:49.992989 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6314 06:02:49.996323 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6315 06:02:49.999425 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6316 06:02:50.006002 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6317 06:02:50.008936 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6318 06:02:50.012407 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6319 06:02:50.016191 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6320 06:02:50.022526 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6321 06:02:50.026175 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6322 06:02:50.029030 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6323 06:02:50.035631 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6324 06:02:50.039349 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6325 06:02:50.042546 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6326 06:02:50.043100 ==
6327 06:02:50.045902 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 06:02:50.048740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 06:02:50.049326 ==
6330 06:02:50.052710 DQS Delay:
6331 06:02:50.053275 DQS0 = 27, DQS1 = 43
6332 06:02:50.055862 DQM Delay:
6333 06:02:50.056414 DQM0 = 12, DQM1 = 12
6334 06:02:50.056778 DQ Delay:
6335 06:02:50.058864 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6336 06:02:50.062105 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6337 06:02:50.065711 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6338 06:02:50.069204 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6339 06:02:50.069660
6340 06:02:50.070050
6341 06:02:50.070387 ==
6342 06:02:50.072117 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 06:02:50.079075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 06:02:50.079537 ==
6345 06:02:50.079899
6346 06:02:50.080236
6347 06:02:50.080555 TX Vref Scan disable
6348 06:02:50.082342 == TX Byte 0 ==
6349 06:02:50.085485 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6350 06:02:50.089357 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6351 06:02:50.092628 == TX Byte 1 ==
6352 06:02:50.095486 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6353 06:02:50.099046 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6354 06:02:50.099603 ==
6355 06:02:50.102488 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 06:02:50.109134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 06:02:50.109744 ==
6358 06:02:50.110195
6359 06:02:50.110574
6360 06:02:50.110904 TX Vref Scan disable
6361 06:02:50.112452 == TX Byte 0 ==
6362 06:02:50.115730 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 06:02:50.119397 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 06:02:50.122113 == TX Byte 1 ==
6365 06:02:50.125446 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6366 06:02:50.129137 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6367 06:02:50.132242
6368 06:02:50.132702 [DATLAT]
6369 06:02:50.133065 Freq=400, CH0 RK0
6370 06:02:50.133407
6371 06:02:50.135813 DATLAT Default: 0xf
6372 06:02:50.136400 0, 0xFFFF, sum = 0
6373 06:02:50.138962 1, 0xFFFF, sum = 0
6374 06:02:50.139439 2, 0xFFFF, sum = 0
6375 06:02:50.142114 3, 0xFFFF, sum = 0
6376 06:02:50.142598 4, 0xFFFF, sum = 0
6377 06:02:50.145396 5, 0xFFFF, sum = 0
6378 06:02:50.145881 6, 0xFFFF, sum = 0
6379 06:02:50.148723 7, 0xFFFF, sum = 0
6380 06:02:50.152029 8, 0xFFFF, sum = 0
6381 06:02:50.152466 9, 0xFFFF, sum = 0
6382 06:02:50.155427 10, 0xFFFF, sum = 0
6383 06:02:50.155866 11, 0xFFFF, sum = 0
6384 06:02:50.158781 12, 0xFFFF, sum = 0
6385 06:02:50.159221 13, 0x0, sum = 1
6386 06:02:50.162350 14, 0x0, sum = 2
6387 06:02:50.162789 15, 0x0, sum = 3
6388 06:02:50.165513 16, 0x0, sum = 4
6389 06:02:50.165983 best_step = 14
6390 06:02:50.166330
6391 06:02:50.166653 ==
6392 06:02:50.168727 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 06:02:50.172247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 06:02:50.172681 ==
6395 06:02:50.175625 RX Vref Scan: 1
6396 06:02:50.176168
6397 06:02:50.178657 RX Vref 0 -> 0, step: 1
6398 06:02:50.179088
6399 06:02:50.179431 RX Delay -327 -> 252, step: 8
6400 06:02:50.179849
6401 06:02:50.182332 Set Vref, RX VrefLevel [Byte0]: 60
6402 06:02:50.185598 [Byte1]: 50
6403 06:02:50.190665
6404 06:02:50.191237 Final RX Vref Byte 0 = 60 to rank0
6405 06:02:50.194005 Final RX Vref Byte 1 = 50 to rank0
6406 06:02:50.197498 Final RX Vref Byte 0 = 60 to rank1
6407 06:02:50.200759 Final RX Vref Byte 1 = 50 to rank1==
6408 06:02:50.203770 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 06:02:50.210498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 06:02:50.211006 ==
6411 06:02:50.211355 DQS Delay:
6412 06:02:50.213708 DQS0 = 24, DQS1 = 48
6413 06:02:50.214187 DQM Delay:
6414 06:02:50.214537 DQM0 = 7, DQM1 = 15
6415 06:02:50.217315 DQ Delay:
6416 06:02:50.220826 DQ0 =4, DQ1 =4, DQ2 =4, DQ3 =4
6417 06:02:50.221334 DQ4 =4, DQ5 =0, DQ6 =20, DQ7 =16
6418 06:02:50.223628 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6419 06:02:50.227243 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6420 06:02:50.227678
6421 06:02:50.228019
6422 06:02:50.237178 [DQSOSCAuto] RK0, (LSB)MR18= 0xaca4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6423 06:02:50.240224 CH0 RK0: MR19=C0C, MR18=ACA4
6424 06:02:50.247056 CH0_RK0: MR19=0xC0C, MR18=0xACA4, DQSOSC=388, MR23=63, INC=392, DEC=261
6425 06:02:50.247494 ==
6426 06:02:50.250467 Dram Type= 6, Freq= 0, CH_0, rank 1
6427 06:02:50.253772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 06:02:50.254237 ==
6429 06:02:50.257010 [Gating] SW mode calibration
6430 06:02:50.263778 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6431 06:02:50.266883 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6432 06:02:50.274059 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6433 06:02:50.276974 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6434 06:02:50.280209 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6435 06:02:50.287271 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 06:02:50.290303 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 06:02:50.293830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 06:02:50.300496 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 06:02:50.303523 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 06:02:50.306771 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6441 06:02:50.310280 Total UI for P1: 0, mck2ui 16
6442 06:02:50.313811 best dqsien dly found for B0: ( 0, 14, 24)
6443 06:02:50.316996 Total UI for P1: 0, mck2ui 16
6444 06:02:50.320389 best dqsien dly found for B1: ( 0, 14, 24)
6445 06:02:50.323578 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6446 06:02:50.326839 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6447 06:02:50.330313
6448 06:02:50.333550 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6449 06:02:50.336901 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6450 06:02:50.340541 [Gating] SW calibration Done
6451 06:02:50.341083 ==
6452 06:02:50.343622 Dram Type= 6, Freq= 0, CH_0, rank 1
6453 06:02:50.346712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 06:02:50.347149 ==
6455 06:02:50.347494 RX Vref Scan: 0
6456 06:02:50.347818
6457 06:02:50.349809 RX Vref 0 -> 0, step: 1
6458 06:02:50.350263
6459 06:02:50.353453 RX Delay -410 -> 252, step: 16
6460 06:02:50.356906 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6461 06:02:50.363226 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6462 06:02:50.366826 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6463 06:02:50.369747 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6464 06:02:50.373161 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6465 06:02:50.380247 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6466 06:02:50.383593 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6467 06:02:50.386731 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6468 06:02:50.390092 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6469 06:02:50.396783 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6470 06:02:50.400054 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6471 06:02:50.403564 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6472 06:02:50.406775 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6473 06:02:50.412873 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6474 06:02:50.416840 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6475 06:02:50.420106 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6476 06:02:50.420645 ==
6477 06:02:50.423342 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 06:02:50.426643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 06:02:50.430365 ==
6480 06:02:50.430903 DQS Delay:
6481 06:02:50.431248 DQS0 = 27, DQS1 = 43
6482 06:02:50.433195 DQM Delay:
6483 06:02:50.433742 DQM0 = 9, DQM1 = 14
6484 06:02:50.436704 DQ Delay:
6485 06:02:50.437136 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6486 06:02:50.439862 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6487 06:02:50.443524 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6488 06:02:50.446873 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6489 06:02:50.447420
6490 06:02:50.447767
6491 06:02:50.448085 ==
6492 06:02:50.449805 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 06:02:50.456420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 06:02:50.456966 ==
6495 06:02:50.457319
6496 06:02:50.457639
6497 06:02:50.459368 TX Vref Scan disable
6498 06:02:50.459801 == TX Byte 0 ==
6499 06:02:50.463021 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6500 06:02:50.466337 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6501 06:02:50.469977 == TX Byte 1 ==
6502 06:02:50.472966 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6503 06:02:50.476531 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6504 06:02:50.479719 ==
6505 06:02:50.483114 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 06:02:50.486361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 06:02:50.486941 ==
6508 06:02:50.487322
6509 06:02:50.487668
6510 06:02:50.489466 TX Vref Scan disable
6511 06:02:50.490074 == TX Byte 0 ==
6512 06:02:50.492848 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6513 06:02:50.499429 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6514 06:02:50.500021 == TX Byte 1 ==
6515 06:02:50.502545 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6516 06:02:50.509352 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6517 06:02:50.509826
6518 06:02:50.510246 [DATLAT]
6519 06:02:50.510598 Freq=400, CH0 RK1
6520 06:02:50.510937
6521 06:02:50.512314 DATLAT Default: 0xe
6522 06:02:50.512806 0, 0xFFFF, sum = 0
6523 06:02:50.515878 1, 0xFFFF, sum = 0
6524 06:02:50.516361 2, 0xFFFF, sum = 0
6525 06:02:50.519013 3, 0xFFFF, sum = 0
6526 06:02:50.522877 4, 0xFFFF, sum = 0
6527 06:02:50.523471 5, 0xFFFF, sum = 0
6528 06:02:50.526126 6, 0xFFFF, sum = 0
6529 06:02:50.526705 7, 0xFFFF, sum = 0
6530 06:02:50.529456 8, 0xFFFF, sum = 0
6531 06:02:50.529974 9, 0xFFFF, sum = 0
6532 06:02:50.532641 10, 0xFFFF, sum = 0
6533 06:02:50.533233 11, 0xFFFF, sum = 0
6534 06:02:50.535970 12, 0xFFFF, sum = 0
6535 06:02:50.536455 13, 0x0, sum = 1
6536 06:02:50.539192 14, 0x0, sum = 2
6537 06:02:50.539707 15, 0x0, sum = 3
6538 06:02:50.542542 16, 0x0, sum = 4
6539 06:02:50.543131 best_step = 14
6540 06:02:50.543509
6541 06:02:50.543862 ==
6542 06:02:50.545613 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 06:02:50.549331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 06:02:50.549915 ==
6545 06:02:50.552713 RX Vref Scan: 0
6546 06:02:50.553294
6547 06:02:50.556050 RX Vref 0 -> 0, step: 1
6548 06:02:50.556632
6549 06:02:50.557012 RX Delay -327 -> 252, step: 8
6550 06:02:50.564784 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6551 06:02:50.568080 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6552 06:02:50.571179 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6553 06:02:50.574852 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6554 06:02:50.581425 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6555 06:02:50.584529 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6556 06:02:50.587927 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6557 06:02:50.591161 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6558 06:02:50.598103 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6559 06:02:50.601298 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6560 06:02:50.604482 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6561 06:02:50.611086 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6562 06:02:50.614384 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6563 06:02:50.618401 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6564 06:02:50.621167 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6565 06:02:50.628118 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6566 06:02:50.628694 ==
6567 06:02:50.631067 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 06:02:50.634684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 06:02:50.635281 ==
6570 06:02:50.635667 DQS Delay:
6571 06:02:50.637678 DQS0 = 28, DQS1 = 44
6572 06:02:50.638210 DQM Delay:
6573 06:02:50.641220 DQM0 = 9, DQM1 = 15
6574 06:02:50.641689 DQ Delay:
6575 06:02:50.644581 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6576 06:02:50.648067 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6577 06:02:50.651060 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6578 06:02:50.654528 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6579 06:02:50.655099
6580 06:02:50.655471
6581 06:02:50.661302 [DQSOSCAuto] RK1, (LSB)MR18= 0xb366, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6582 06:02:50.664457 CH0 RK1: MR19=C0C, MR18=B366
6583 06:02:50.670984 CH0_RK1: MR19=0xC0C, MR18=0xB366, DQSOSC=387, MR23=63, INC=394, DEC=262
6584 06:02:50.674820 [RxdqsGatingPostProcess] freq 400
6585 06:02:50.680884 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6586 06:02:50.681449 best DQS0 dly(2T, 0.5T) = (0, 10)
6587 06:02:50.684148 best DQS1 dly(2T, 0.5T) = (0, 10)
6588 06:02:50.687678 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6589 06:02:50.690686 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6590 06:02:50.694208 best DQS0 dly(2T, 0.5T) = (0, 10)
6591 06:02:50.697698 best DQS1 dly(2T, 0.5T) = (0, 10)
6592 06:02:50.701048 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6593 06:02:50.703895 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6594 06:02:50.707337 Pre-setting of DQS Precalculation
6595 06:02:50.714202 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6596 06:02:50.714778 ==
6597 06:02:50.716970 Dram Type= 6, Freq= 0, CH_1, rank 0
6598 06:02:50.721085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6599 06:02:50.721661 ==
6600 06:02:50.727256 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6601 06:02:50.730462 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6602 06:02:50.734189 [CA 0] Center 36 (8~64) winsize 57
6603 06:02:50.736877 [CA 1] Center 36 (8~64) winsize 57
6604 06:02:50.740227 [CA 2] Center 36 (8~64) winsize 57
6605 06:02:50.743517 [CA 3] Center 36 (8~64) winsize 57
6606 06:02:50.747122 [CA 4] Center 36 (8~64) winsize 57
6607 06:02:50.750328 [CA 5] Center 36 (8~64) winsize 57
6608 06:02:50.750902
6609 06:02:50.753639 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6610 06:02:50.754252
6611 06:02:50.757183 [CATrainingPosCal] consider 1 rank data
6612 06:02:50.760216 u2DelayCellTimex100 = 270/100 ps
6613 06:02:50.763521 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 06:02:50.766590 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 06:02:50.773442 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 06:02:50.777104 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 06:02:50.780235 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 06:02:50.783278 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 06:02:50.783857
6620 06:02:50.787069 CA PerBit enable=1, Macro0, CA PI delay=36
6621 06:02:50.787655
6622 06:02:50.790082 [CBTSetCACLKResult] CA Dly = 36
6623 06:02:50.790661 CS Dly: 1 (0~32)
6624 06:02:50.791040 ==
6625 06:02:50.793411 Dram Type= 6, Freq= 0, CH_1, rank 1
6626 06:02:50.800241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6627 06:02:50.800825 ==
6628 06:02:50.803237 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6629 06:02:50.809925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6630 06:02:50.813512 [CA 0] Center 36 (8~64) winsize 57
6631 06:02:50.816569 [CA 1] Center 36 (8~64) winsize 57
6632 06:02:50.819983 [CA 2] Center 36 (8~64) winsize 57
6633 06:02:50.823258 [CA 3] Center 36 (8~64) winsize 57
6634 06:02:50.826390 [CA 4] Center 36 (8~64) winsize 57
6635 06:02:50.829977 [CA 5] Center 36 (8~64) winsize 57
6636 06:02:50.830456
6637 06:02:50.833341 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6638 06:02:50.833979
6639 06:02:50.836643 [CATrainingPosCal] consider 2 rank data
6640 06:02:50.840185 u2DelayCellTimex100 = 270/100 ps
6641 06:02:50.843289 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 06:02:50.846290 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 06:02:50.849620 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 06:02:50.853053 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 06:02:50.856183 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 06:02:50.862779 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 06:02:50.863250
6648 06:02:50.866325 CA PerBit enable=1, Macro0, CA PI delay=36
6649 06:02:50.866794
6650 06:02:50.869993 [CBTSetCACLKResult] CA Dly = 36
6651 06:02:50.870560 CS Dly: 1 (0~32)
6652 06:02:50.870935
6653 06:02:50.873396 ----->DramcWriteLeveling(PI) begin...
6654 06:02:50.874019 ==
6655 06:02:50.876239 Dram Type= 6, Freq= 0, CH_1, rank 0
6656 06:02:50.879604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 06:02:50.883133 ==
6658 06:02:50.883704 Write leveling (Byte 0): 40 => 8
6659 06:02:50.886779 Write leveling (Byte 1): 32 => 0
6660 06:02:50.889795 DramcWriteLeveling(PI) end<-----
6661 06:02:50.890433
6662 06:02:50.890811 ==
6663 06:02:50.893022 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 06:02:50.899861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 06:02:50.900351 ==
6666 06:02:50.900725 [Gating] SW mode calibration
6667 06:02:50.910030 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6668 06:02:50.912807 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6669 06:02:50.916020 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6670 06:02:50.922617 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6671 06:02:50.926379 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6672 06:02:50.929665 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 06:02:50.936210 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 06:02:50.939161 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 06:02:50.942682 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 06:02:50.949218 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 06:02:50.952736 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6678 06:02:50.956247 Total UI for P1: 0, mck2ui 16
6679 06:02:50.959398 best dqsien dly found for B0: ( 0, 14, 24)
6680 06:02:50.962647 Total UI for P1: 0, mck2ui 16
6681 06:02:50.966372 best dqsien dly found for B1: ( 0, 14, 24)
6682 06:02:50.969135 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6683 06:02:50.972922 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6684 06:02:50.973624
6685 06:02:50.976168 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6686 06:02:50.979401 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6687 06:02:50.982600 [Gating] SW calibration Done
6688 06:02:50.983080 ==
6689 06:02:50.986309 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 06:02:50.992460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 06:02:50.993044 ==
6692 06:02:50.993423 RX Vref Scan: 0
6693 06:02:50.993778
6694 06:02:50.996125 RX Vref 0 -> 0, step: 1
6695 06:02:50.996694
6696 06:02:50.999334 RX Delay -410 -> 252, step: 16
6697 06:02:51.002485 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6698 06:02:51.005750 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6699 06:02:51.009364 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6700 06:02:51.015725 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6701 06:02:51.019315 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6702 06:02:51.022538 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6703 06:02:51.026005 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6704 06:02:51.032743 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6705 06:02:51.035619 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6706 06:02:51.039149 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6707 06:02:51.042829 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6708 06:02:51.049223 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6709 06:02:51.052386 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6710 06:02:51.055702 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6711 06:02:51.062418 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6712 06:02:51.066113 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6713 06:02:51.066692 ==
6714 06:02:51.069025 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 06:02:51.072630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 06:02:51.073202 ==
6717 06:02:51.075725 DQS Delay:
6718 06:02:51.076320 DQS0 = 19, DQS1 = 43
6719 06:02:51.076698 DQM Delay:
6720 06:02:51.078926 DQM0 = 1, DQM1 = 20
6721 06:02:51.079397 DQ Delay:
6722 06:02:51.082518 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6723 06:02:51.086205 DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =0
6724 06:02:51.089084 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =24
6725 06:02:51.092627 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6726 06:02:51.093197
6727 06:02:51.093574
6728 06:02:51.093922 ==
6729 06:02:51.095877 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 06:02:51.098912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 06:02:51.099396 ==
6732 06:02:51.099772
6733 06:02:51.100118
6734 06:02:51.102256 TX Vref Scan disable
6735 06:02:51.105414 == TX Byte 0 ==
6736 06:02:51.108818 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6737 06:02:51.112476 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6738 06:02:51.115754 == TX Byte 1 ==
6739 06:02:51.118897 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6740 06:02:51.122438 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6741 06:02:51.122986 ==
6742 06:02:51.125419 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 06:02:51.128893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 06:02:51.129462 ==
6745 06:02:51.132496
6746 06:02:51.133036
6747 06:02:51.133408 TX Vref Scan disable
6748 06:02:51.135567 == TX Byte 0 ==
6749 06:02:51.138581 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 06:02:51.142368 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 06:02:51.145737 == TX Byte 1 ==
6752 06:02:51.148761 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6753 06:02:51.152261 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6754 06:02:51.152729
6755 06:02:51.153116 [DATLAT]
6756 06:02:51.155318 Freq=400, CH1 RK0
6757 06:02:51.155786
6758 06:02:51.158728 DATLAT Default: 0xf
6759 06:02:51.159195 0, 0xFFFF, sum = 0
6760 06:02:51.162246 1, 0xFFFF, sum = 0
6761 06:02:51.162722 2, 0xFFFF, sum = 0
6762 06:02:51.165427 3, 0xFFFF, sum = 0
6763 06:02:51.165906 4, 0xFFFF, sum = 0
6764 06:02:51.168738 5, 0xFFFF, sum = 0
6765 06:02:51.169214 6, 0xFFFF, sum = 0
6766 06:02:51.172351 7, 0xFFFF, sum = 0
6767 06:02:51.172826 8, 0xFFFF, sum = 0
6768 06:02:51.175529 9, 0xFFFF, sum = 0
6769 06:02:51.176143 10, 0xFFFF, sum = 0
6770 06:02:51.178961 11, 0xFFFF, sum = 0
6771 06:02:51.179440 12, 0xFFFF, sum = 0
6772 06:02:51.182144 13, 0x0, sum = 1
6773 06:02:51.182697 14, 0x0, sum = 2
6774 06:02:51.185326 15, 0x0, sum = 3
6775 06:02:51.185755 16, 0x0, sum = 4
6776 06:02:51.188700 best_step = 14
6777 06:02:51.189121
6778 06:02:51.189457 ==
6779 06:02:51.192121 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 06:02:51.195362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 06:02:51.195788 ==
6782 06:02:51.198779 RX Vref Scan: 1
6783 06:02:51.199201
6784 06:02:51.199535 RX Vref 0 -> 0, step: 1
6785 06:02:51.199847
6786 06:02:51.201922 RX Delay -327 -> 252, step: 8
6787 06:02:51.202375
6788 06:02:51.204792 Set Vref, RX VrefLevel [Byte0]: 54
6789 06:02:51.208330 [Byte1]: 53
6790 06:02:51.212644
6791 06:02:51.212727 Final RX Vref Byte 0 = 54 to rank0
6792 06:02:51.215769 Final RX Vref Byte 1 = 53 to rank0
6793 06:02:51.219661 Final RX Vref Byte 0 = 54 to rank1
6794 06:02:51.222472 Final RX Vref Byte 1 = 53 to rank1==
6795 06:02:51.225838 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 06:02:51.232885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 06:02:51.232970 ==
6798 06:02:51.233038 DQS Delay:
6799 06:02:51.233100 DQS0 = 28, DQS1 = 40
6800 06:02:51.236195 DQM Delay:
6801 06:02:51.236279 DQM0 = 8, DQM1 = 13
6802 06:02:51.239177 DQ Delay:
6803 06:02:51.239261 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6804 06:02:51.242631 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6805 06:02:51.245851 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6806 06:02:51.249125 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6807 06:02:51.249209
6808 06:02:51.249276
6809 06:02:51.259073 [DQSOSCAuto] RK0, (LSB)MR18= 0x95cf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6810 06:02:51.262347 CH1 RK0: MR19=C0C, MR18=95CF
6811 06:02:51.268937 CH1_RK0: MR19=0xC0C, MR18=0x95CF, DQSOSC=384, MR23=63, INC=400, DEC=267
6812 06:02:51.269023 ==
6813 06:02:51.272617 Dram Type= 6, Freq= 0, CH_1, rank 1
6814 06:02:51.275806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 06:02:51.275891 ==
6816 06:02:51.279229 [Gating] SW mode calibration
6817 06:02:51.285654 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6818 06:02:51.289085 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6819 06:02:51.295629 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6820 06:02:51.298895 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6821 06:02:51.302412 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6822 06:02:51.309106 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 06:02:51.312193 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 06:02:51.315320 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 06:02:51.322310 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 06:02:51.325540 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 06:02:51.328602 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6828 06:02:51.332132 Total UI for P1: 0, mck2ui 16
6829 06:02:51.335264 best dqsien dly found for B0: ( 0, 14, 24)
6830 06:02:51.338864 Total UI for P1: 0, mck2ui 16
6831 06:02:51.342088 best dqsien dly found for B1: ( 0, 14, 24)
6832 06:02:51.345228 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6833 06:02:51.349000 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6834 06:02:51.349085
6835 06:02:51.355394 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6836 06:02:51.358593 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6837 06:02:51.361837 [Gating] SW calibration Done
6838 06:02:51.361967 ==
6839 06:02:51.365301 Dram Type= 6, Freq= 0, CH_1, rank 1
6840 06:02:51.368616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 06:02:51.368701 ==
6842 06:02:51.368768 RX Vref Scan: 0
6843 06:02:51.368831
6844 06:02:51.371836 RX Vref 0 -> 0, step: 1
6845 06:02:51.371920
6846 06:02:51.375353 RX Delay -410 -> 252, step: 16
6847 06:02:51.378472 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6848 06:02:51.385207 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6849 06:02:51.388619 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6850 06:02:51.391893 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6851 06:02:51.395198 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6852 06:02:51.401524 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6853 06:02:51.405231 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6854 06:02:51.408374 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6855 06:02:51.411517 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6856 06:02:51.418538 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6857 06:02:51.421740 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6858 06:02:51.425014 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6859 06:02:51.428507 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6860 06:02:51.434829 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6861 06:02:51.438344 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6862 06:02:51.441856 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6863 06:02:51.441970 ==
6864 06:02:51.444841 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 06:02:51.448135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 06:02:51.451782 ==
6867 06:02:51.451866 DQS Delay:
6868 06:02:51.451933 DQS0 = 35, DQS1 = 43
6869 06:02:51.455077 DQM Delay:
6870 06:02:51.455161 DQM0 = 16, DQM1 = 18
6871 06:02:51.458308 DQ Delay:
6872 06:02:51.461454 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6873 06:02:51.461539 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6874 06:02:51.464934 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6875 06:02:51.468335 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6876 06:02:51.468421
6877 06:02:51.471398
6878 06:02:51.471482 ==
6879 06:02:51.474991 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 06:02:51.478198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 06:02:51.478309 ==
6882 06:02:51.478404
6883 06:02:51.478494
6884 06:02:51.481342 TX Vref Scan disable
6885 06:02:51.481427 == TX Byte 0 ==
6886 06:02:51.484672 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6887 06:02:51.491674 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6888 06:02:51.491758 == TX Byte 1 ==
6889 06:02:51.494860 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6890 06:02:51.501630 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6891 06:02:51.501714 ==
6892 06:02:51.504663 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 06:02:51.508134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 06:02:51.508218 ==
6895 06:02:51.508284
6896 06:02:51.508345
6897 06:02:51.511501 TX Vref Scan disable
6898 06:02:51.511584 == TX Byte 0 ==
6899 06:02:51.514626 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6900 06:02:51.521435 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6901 06:02:51.521519 == TX Byte 1 ==
6902 06:02:51.524694 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6903 06:02:51.531248 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6904 06:02:51.531342
6905 06:02:51.531439 [DATLAT]
6906 06:02:51.531530 Freq=400, CH1 RK1
6907 06:02:51.531630
6908 06:02:51.534753 DATLAT Default: 0xe
6909 06:02:51.537912 0, 0xFFFF, sum = 0
6910 06:02:51.538050 1, 0xFFFF, sum = 0
6911 06:02:51.541153 2, 0xFFFF, sum = 0
6912 06:02:51.541237 3, 0xFFFF, sum = 0
6913 06:02:51.544655 4, 0xFFFF, sum = 0
6914 06:02:51.544740 5, 0xFFFF, sum = 0
6915 06:02:51.547737 6, 0xFFFF, sum = 0
6916 06:02:51.547822 7, 0xFFFF, sum = 0
6917 06:02:51.551413 8, 0xFFFF, sum = 0
6918 06:02:51.551498 9, 0xFFFF, sum = 0
6919 06:02:51.554695 10, 0xFFFF, sum = 0
6920 06:02:51.554780 11, 0xFFFF, sum = 0
6921 06:02:51.557765 12, 0xFFFF, sum = 0
6922 06:02:51.557849 13, 0x0, sum = 1
6923 06:02:51.561114 14, 0x0, sum = 2
6924 06:02:51.561199 15, 0x0, sum = 3
6925 06:02:51.564550 16, 0x0, sum = 4
6926 06:02:51.564635 best_step = 14
6927 06:02:51.564700
6928 06:02:51.564761 ==
6929 06:02:51.567883 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 06:02:51.571371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 06:02:51.574701 ==
6932 06:02:51.574784 RX Vref Scan: 0
6933 06:02:51.574851
6934 06:02:51.577954 RX Vref 0 -> 0, step: 1
6935 06:02:51.578037
6936 06:02:51.580740 RX Delay -327 -> 252, step: 8
6937 06:02:51.587668 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6938 06:02:51.591049 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6939 06:02:51.594459 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6940 06:02:51.597427 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6941 06:02:51.604124 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6942 06:02:51.607697 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6943 06:02:51.611093 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6944 06:02:51.614742 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6945 06:02:51.617880 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6946 06:02:51.624565 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6947 06:02:51.627872 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6948 06:02:51.631089 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6949 06:02:51.634322 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6950 06:02:51.640898 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6951 06:02:51.644166 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6952 06:02:51.647459 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6953 06:02:51.647544 ==
6954 06:02:51.651012 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 06:02:51.657636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 06:02:51.657721 ==
6957 06:02:51.657788 DQS Delay:
6958 06:02:51.660692 DQS0 = 32, DQS1 = 36
6959 06:02:51.660779 DQM Delay:
6960 06:02:51.664291 DQM0 = 12, DQM1 = 10
6961 06:02:51.664372 DQ Delay:
6962 06:02:51.668041 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6963 06:02:51.670589 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =8
6964 06:02:51.670669 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6965 06:02:51.677567 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6966 06:02:51.677654
6967 06:02:51.677741
6968 06:02:51.683771 [DQSOSCAuto] RK1, (LSB)MR18= 0xab54, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6969 06:02:51.687526 CH1 RK1: MR19=C0C, MR18=AB54
6970 06:02:51.693635 CH1_RK1: MR19=0xC0C, MR18=0xAB54, DQSOSC=388, MR23=63, INC=392, DEC=261
6971 06:02:51.697229 [RxdqsGatingPostProcess] freq 400
6972 06:02:51.700429 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6973 06:02:51.703732 best DQS0 dly(2T, 0.5T) = (0, 10)
6974 06:02:51.706839 best DQS1 dly(2T, 0.5T) = (0, 10)
6975 06:02:51.710192 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6976 06:02:51.713848 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6977 06:02:51.717114 best DQS0 dly(2T, 0.5T) = (0, 10)
6978 06:02:51.720322 best DQS1 dly(2T, 0.5T) = (0, 10)
6979 06:02:51.723791 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6980 06:02:51.726968 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6981 06:02:51.730111 Pre-setting of DQS Precalculation
6982 06:02:51.733676 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6983 06:02:51.743302 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6984 06:02:51.750139 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6985 06:02:51.750221
6986 06:02:51.750305
6987 06:02:51.753359 [Calibration Summary] 800 Mbps
6988 06:02:51.753436 CH 0, Rank 0
6989 06:02:51.756724 SW Impedance : PASS
6990 06:02:51.756802 DUTY Scan : NO K
6991 06:02:51.759936 ZQ Calibration : PASS
6992 06:02:51.763319 Jitter Meter : NO K
6993 06:02:51.763398 CBT Training : PASS
6994 06:02:51.766541 Write leveling : PASS
6995 06:02:51.769896 RX DQS gating : PASS
6996 06:02:51.769998 RX DQ/DQS(RDDQC) : PASS
6997 06:02:51.773653 TX DQ/DQS : PASS
6998 06:02:51.776566 RX DATLAT : PASS
6999 06:02:51.776649 RX DQ/DQS(Engine): PASS
7000 06:02:51.780090 TX OE : NO K
7001 06:02:51.780171 All Pass.
7002 06:02:51.780253
7003 06:02:51.783167 CH 0, Rank 1
7004 06:02:51.783248 SW Impedance : PASS
7005 06:02:51.786715 DUTY Scan : NO K
7006 06:02:51.786792 ZQ Calibration : PASS
7007 06:02:51.790302 Jitter Meter : NO K
7008 06:02:51.793451 CBT Training : PASS
7009 06:02:51.793530 Write leveling : NO K
7010 06:02:51.796538 RX DQS gating : PASS
7011 06:02:51.800120 RX DQ/DQS(RDDQC) : PASS
7012 06:02:51.800197 TX DQ/DQS : PASS
7013 06:02:51.803262 RX DATLAT : PASS
7014 06:02:51.806730 RX DQ/DQS(Engine): PASS
7015 06:02:51.806807 TX OE : NO K
7016 06:02:51.809860 All Pass.
7017 06:02:51.809972
7018 06:02:51.810058 CH 1, Rank 0
7019 06:02:51.813304 SW Impedance : PASS
7020 06:02:51.813379 DUTY Scan : NO K
7021 06:02:51.816385 ZQ Calibration : PASS
7022 06:02:51.820046 Jitter Meter : NO K
7023 06:02:51.820128 CBT Training : PASS
7024 06:02:51.823018 Write leveling : PASS
7025 06:02:51.826637 RX DQS gating : PASS
7026 06:02:51.826715 RX DQ/DQS(RDDQC) : PASS
7027 06:02:51.829573 TX DQ/DQS : PASS
7028 06:02:51.833249 RX DATLAT : PASS
7029 06:02:51.833329 RX DQ/DQS(Engine): PASS
7030 06:02:51.836663 TX OE : NO K
7031 06:02:51.836745 All Pass.
7032 06:02:51.836827
7033 06:02:51.839806 CH 1, Rank 1
7034 06:02:51.839885 SW Impedance : PASS
7035 06:02:51.843059 DUTY Scan : NO K
7036 06:02:51.843136 ZQ Calibration : PASS
7037 06:02:51.846588 Jitter Meter : NO K
7038 06:02:51.849461 CBT Training : PASS
7039 06:02:51.849536 Write leveling : NO K
7040 06:02:51.853092 RX DQS gating : PASS
7041 06:02:51.856480 RX DQ/DQS(RDDQC) : PASS
7042 06:02:51.856557 TX DQ/DQS : PASS
7043 06:02:51.859722 RX DATLAT : PASS
7044 06:02:51.863013 RX DQ/DQS(Engine): PASS
7045 06:02:51.863092 TX OE : NO K
7046 06:02:51.866330 All Pass.
7047 06:02:51.866412
7048 06:02:51.866493 DramC Write-DBI off
7049 06:02:51.869503 PER_BANK_REFRESH: Hybrid Mode
7050 06:02:51.869582 TX_TRACKING: ON
7051 06:02:51.879451 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7052 06:02:51.883007 [FAST_K] Save calibration result to emmc
7053 06:02:51.886089 dramc_set_vcore_voltage set vcore to 725000
7054 06:02:51.889399 Read voltage for 1600, 0
7055 06:02:51.889490 Vio18 = 0
7056 06:02:51.892675 Vcore = 725000
7057 06:02:51.892754 Vdram = 0
7058 06:02:51.892838 Vddq = 0
7059 06:02:51.896253 Vmddr = 0
7060 06:02:51.899416 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7061 06:02:51.905925 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7062 06:02:51.906062 MEM_TYPE=3, freq_sel=13
7063 06:02:51.909506 sv_algorithm_assistance_LP4_3733
7064 06:02:51.915878 ============ PULL DRAM RESETB DOWN ============
7065 06:02:51.919407 ========== PULL DRAM RESETB DOWN end =========
7066 06:02:51.922581 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7067 06:02:51.925999 ===================================
7068 06:02:51.929338 LPDDR4 DRAM CONFIGURATION
7069 06:02:51.932719 ===================================
7070 06:02:51.932811 EX_ROW_EN[0] = 0x0
7071 06:02:51.936411 EX_ROW_EN[1] = 0x0
7072 06:02:51.939461 LP4Y_EN = 0x0
7073 06:02:51.939544 WORK_FSP = 0x1
7074 06:02:51.942737 WL = 0x5
7075 06:02:51.942810 RL = 0x5
7076 06:02:51.946177 BL = 0x2
7077 06:02:51.946249 RPST = 0x0
7078 06:02:51.949149 RD_PRE = 0x0
7079 06:02:51.949224 WR_PRE = 0x1
7080 06:02:51.952365 WR_PST = 0x1
7081 06:02:51.952436 DBI_WR = 0x0
7082 06:02:51.956088 DBI_RD = 0x0
7083 06:02:51.956186 OTF = 0x1
7084 06:02:51.959342 ===================================
7085 06:02:51.962684 ===================================
7086 06:02:51.965862 ANA top config
7087 06:02:51.969039 ===================================
7088 06:02:51.969111 DLL_ASYNC_EN = 0
7089 06:02:51.972637 ALL_SLAVE_EN = 0
7090 06:02:51.975864 NEW_RANK_MODE = 1
7091 06:02:51.979568 DLL_IDLE_MODE = 1
7092 06:02:51.982370 LP45_APHY_COMB_EN = 1
7093 06:02:51.982441 TX_ODT_DIS = 0
7094 06:02:51.985771 NEW_8X_MODE = 1
7095 06:02:51.989286 ===================================
7096 06:02:51.992493 ===================================
7097 06:02:51.995634 data_rate = 3200
7098 06:02:51.998895 CKR = 1
7099 06:02:52.002557 DQ_P2S_RATIO = 8
7100 06:02:52.005843 ===================================
7101 06:02:52.005914 CA_P2S_RATIO = 8
7102 06:02:52.009023 DQ_CA_OPEN = 0
7103 06:02:52.012573 DQ_SEMI_OPEN = 0
7104 06:02:52.015818 CA_SEMI_OPEN = 0
7105 06:02:52.019075 CA_FULL_RATE = 0
7106 06:02:52.022487 DQ_CKDIV4_EN = 0
7107 06:02:52.022561 CA_CKDIV4_EN = 0
7108 06:02:52.025474 CA_PREDIV_EN = 0
7109 06:02:52.028923 PH8_DLY = 12
7110 06:02:52.032372 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7111 06:02:52.035885 DQ_AAMCK_DIV = 4
7112 06:02:52.038913 CA_AAMCK_DIV = 4
7113 06:02:52.039021 CA_ADMCK_DIV = 4
7114 06:02:52.041972 DQ_TRACK_CA_EN = 0
7115 06:02:52.045563 CA_PICK = 1600
7116 06:02:52.048850 CA_MCKIO = 1600
7117 06:02:52.052325 MCKIO_SEMI = 0
7118 06:02:52.055409 PLL_FREQ = 3068
7119 06:02:52.058931 DQ_UI_PI_RATIO = 32
7120 06:02:52.061799 CA_UI_PI_RATIO = 0
7121 06:02:52.065187 ===================================
7122 06:02:52.068516 ===================================
7123 06:02:52.068594 memory_type:LPDDR4
7124 06:02:52.072326 GP_NUM : 10
7125 06:02:52.075156 SRAM_EN : 1
7126 06:02:52.075231 MD32_EN : 0
7127 06:02:52.078355 ===================================
7128 06:02:52.081651 [ANA_INIT] >>>>>>>>>>>>>>
7129 06:02:52.085017 <<<<<< [CONFIGURE PHASE]: ANA_TX
7130 06:02:52.088678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7131 06:02:52.091875 ===================================
7132 06:02:52.095243 data_rate = 3200,PCW = 0X7600
7133 06:02:52.098527 ===================================
7134 06:02:52.101865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7135 06:02:52.105488 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7136 06:02:52.111757 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7137 06:02:52.114958 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7138 06:02:52.118308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7139 06:02:52.121525 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7140 06:02:52.125212 [ANA_INIT] flow start
7141 06:02:52.128325 [ANA_INIT] PLL >>>>>>>>
7142 06:02:52.128398 [ANA_INIT] PLL <<<<<<<<
7143 06:02:52.131715 [ANA_INIT] MIDPI >>>>>>>>
7144 06:02:52.134866 [ANA_INIT] MIDPI <<<<<<<<
7145 06:02:52.134937 [ANA_INIT] DLL >>>>>>>>
7146 06:02:52.138257 [ANA_INIT] DLL <<<<<<<<
7147 06:02:52.141640 [ANA_INIT] flow end
7148 06:02:52.144857 ============ LP4 DIFF to SE enter ============
7149 06:02:52.148375 ============ LP4 DIFF to SE exit ============
7150 06:02:52.151743 [ANA_INIT] <<<<<<<<<<<<<
7151 06:02:52.154783 [Flow] Enable top DCM control >>>>>
7152 06:02:52.158164 [Flow] Enable top DCM control <<<<<
7153 06:02:52.161427 Enable DLL master slave shuffle
7154 06:02:52.165088 ==============================================================
7155 06:02:52.167988 Gating Mode config
7156 06:02:52.174906 ==============================================================
7157 06:02:52.174990 Config description:
7158 06:02:52.184780 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7159 06:02:52.191308 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7160 06:02:52.195004 SELPH_MODE 0: By rank 1: By Phase
7161 06:02:52.201581 ==============================================================
7162 06:02:52.204800 GAT_TRACK_EN = 1
7163 06:02:52.208186 RX_GATING_MODE = 2
7164 06:02:52.211380 RX_GATING_TRACK_MODE = 2
7165 06:02:52.214742 SELPH_MODE = 1
7166 06:02:52.218306 PICG_EARLY_EN = 1
7167 06:02:52.221504 VALID_LAT_VALUE = 1
7168 06:02:52.224954 ==============================================================
7169 06:02:52.228147 Enter into Gating configuration >>>>
7170 06:02:52.231407 Exit from Gating configuration <<<<
7171 06:02:52.234779 Enter into DVFS_PRE_config >>>>>
7172 06:02:52.247854 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7173 06:02:52.247941 Exit from DVFS_PRE_config <<<<<
7174 06:02:52.251157 Enter into PICG configuration >>>>
7175 06:02:52.254464 Exit from PICG configuration <<<<
7176 06:02:52.258164 [RX_INPUT] configuration >>>>>
7177 06:02:52.261141 [RX_INPUT] configuration <<<<<
7178 06:02:52.267978 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7179 06:02:52.271055 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7180 06:02:52.277804 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7181 06:02:52.284802 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7182 06:02:52.291309 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7183 06:02:52.298062 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7184 06:02:52.301287 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7185 06:02:52.304467 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7186 06:02:52.307692 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7187 06:02:52.314597 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7188 06:02:52.318034 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7189 06:02:52.321330 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7190 06:02:52.324834 ===================================
7191 06:02:52.327752 LPDDR4 DRAM CONFIGURATION
7192 06:02:52.331152 ===================================
7193 06:02:52.331235 EX_ROW_EN[0] = 0x0
7194 06:02:52.334473 EX_ROW_EN[1] = 0x0
7195 06:02:52.337770 LP4Y_EN = 0x0
7196 06:02:52.337853 WORK_FSP = 0x1
7197 06:02:52.340940 WL = 0x5
7198 06:02:52.341022 RL = 0x5
7199 06:02:52.344328 BL = 0x2
7200 06:02:52.344411 RPST = 0x0
7201 06:02:52.347941 RD_PRE = 0x0
7202 06:02:52.348024 WR_PRE = 0x1
7203 06:02:52.350886 WR_PST = 0x1
7204 06:02:52.350968 DBI_WR = 0x0
7205 06:02:52.354554 DBI_RD = 0x0
7206 06:02:52.354637 OTF = 0x1
7207 06:02:52.357755 ===================================
7208 06:02:52.361255 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7209 06:02:52.367797 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7210 06:02:52.370885 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7211 06:02:52.374354 ===================================
7212 06:02:52.377551 LPDDR4 DRAM CONFIGURATION
7213 06:02:52.380923 ===================================
7214 06:02:52.381006 EX_ROW_EN[0] = 0x10
7215 06:02:52.384320 EX_ROW_EN[1] = 0x0
7216 06:02:52.384403 LP4Y_EN = 0x0
7217 06:02:52.387626 WORK_FSP = 0x1
7218 06:02:52.387708 WL = 0x5
7219 06:02:52.390947 RL = 0x5
7220 06:02:52.394018 BL = 0x2
7221 06:02:52.394101 RPST = 0x0
7222 06:02:52.397826 RD_PRE = 0x0
7223 06:02:52.397935 WR_PRE = 0x1
7224 06:02:52.400809 WR_PST = 0x1
7225 06:02:52.400891 DBI_WR = 0x0
7226 06:02:52.404231 DBI_RD = 0x0
7227 06:02:52.404313 OTF = 0x1
7228 06:02:52.407298 ===================================
7229 06:02:52.414104 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7230 06:02:52.414187 ==
7231 06:02:52.417588 Dram Type= 6, Freq= 0, CH_0, rank 0
7232 06:02:52.420847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7233 06:02:52.420931 ==
7234 06:02:52.424199 [Duty_Offset_Calibration]
7235 06:02:52.427499 B0:2 B1:0 CA:1
7236 06:02:52.427608
7237 06:02:52.430392 [DutyScan_Calibration_Flow] k_type=0
7238 06:02:52.438354
7239 06:02:52.438462 ==CLK 0==
7240 06:02:52.441521 Final CLK duty delay cell = -4
7241 06:02:52.445147 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7242 06:02:52.448542 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7243 06:02:52.451780 [-4] AVG Duty = 4937%(X100)
7244 06:02:52.451888
7245 06:02:52.454984 CH0 CLK Duty spec in!! Max-Min= 187%
7246 06:02:52.458185 [DutyScan_Calibration_Flow] ====Done====
7247 06:02:52.458268
7248 06:02:52.461675 [DutyScan_Calibration_Flow] k_type=1
7249 06:02:52.477789
7250 06:02:52.477872 ==DQS 0 ==
7251 06:02:52.481332 Final DQS duty delay cell = 0
7252 06:02:52.484528 [0] MAX Duty = 5249%(X100), DQS PI = 34
7253 06:02:52.487809 [0] MIN Duty = 4969%(X100), DQS PI = 0
7254 06:02:52.487887 [0] AVG Duty = 5109%(X100)
7255 06:02:52.491018
7256 06:02:52.491092 ==DQS 1 ==
7257 06:02:52.494812 Final DQS duty delay cell = -4
7258 06:02:52.497792 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7259 06:02:52.501098 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7260 06:02:52.504208 [-4] AVG Duty = 5000%(X100)
7261 06:02:52.504307
7262 06:02:52.507935 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7263 06:02:52.508036
7264 06:02:52.510829 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7265 06:02:52.514172 [DutyScan_Calibration_Flow] ====Done====
7266 06:02:52.514249
7267 06:02:52.517728 [DutyScan_Calibration_Flow] k_type=3
7268 06:02:52.534923
7269 06:02:52.535028 ==DQM 0 ==
7270 06:02:52.538534 Final DQM duty delay cell = 0
7271 06:02:52.541439 [0] MAX Duty = 5093%(X100), DQS PI = 26
7272 06:02:52.544987 [0] MIN Duty = 4813%(X100), DQS PI = 50
7273 06:02:52.548444 [0] AVG Duty = 4953%(X100)
7274 06:02:52.548547
7275 06:02:52.548642 ==DQM 1 ==
7276 06:02:52.551733 Final DQM duty delay cell = 0
7277 06:02:52.555064 [0] MAX Duty = 5249%(X100), DQS PI = 30
7278 06:02:52.558428 [0] MIN Duty = 5000%(X100), DQS PI = 20
7279 06:02:52.561427 [0] AVG Duty = 5124%(X100)
7280 06:02:52.561527
7281 06:02:52.564850 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7282 06:02:52.564952
7283 06:02:52.568069 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7284 06:02:52.571601 [DutyScan_Calibration_Flow] ====Done====
7285 06:02:52.571675
7286 06:02:52.575073 [DutyScan_Calibration_Flow] k_type=2
7287 06:02:52.592196
7288 06:02:52.592300 ==DQ 0 ==
7289 06:02:52.595674 Final DQ duty delay cell = 0
7290 06:02:52.598816 [0] MAX Duty = 5124%(X100), DQS PI = 32
7291 06:02:52.602390 [0] MIN Duty = 5000%(X100), DQS PI = 0
7292 06:02:52.602496 [0] AVG Duty = 5062%(X100)
7293 06:02:52.602587
7294 06:02:52.605541 ==DQ 1 ==
7295 06:02:52.608808 Final DQ duty delay cell = 0
7296 06:02:52.612211 [0] MAX Duty = 4969%(X100), DQS PI = 44
7297 06:02:52.615681 [0] MIN Duty = 4875%(X100), DQS PI = 10
7298 06:02:52.615783 [0] AVG Duty = 4922%(X100)
7299 06:02:52.615877
7300 06:02:52.618811 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7301 06:02:52.622247
7302 06:02:52.625320 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7303 06:02:52.628837 [DutyScan_Calibration_Flow] ====Done====
7304 06:02:52.628938 ==
7305 06:02:52.631985 Dram Type= 6, Freq= 0, CH_1, rank 0
7306 06:02:52.635515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7307 06:02:52.635615 ==
7308 06:02:52.638440 [Duty_Offset_Calibration]
7309 06:02:52.638541 B0:0 B1:-1 CA:2
7310 06:02:52.638633
7311 06:02:52.642128 [DutyScan_Calibration_Flow] k_type=0
7312 06:02:52.652595
7313 06:02:52.652673 ==CLK 0==
7314 06:02:52.656072 Final CLK duty delay cell = 0
7315 06:02:52.659168 [0] MAX Duty = 5156%(X100), DQS PI = 10
7316 06:02:52.662590 [0] MIN Duty = 4906%(X100), DQS PI = 46
7317 06:02:52.662689 [0] AVG Duty = 5031%(X100)
7318 06:02:52.665678
7319 06:02:52.669125 CH1 CLK Duty spec in!! Max-Min= 250%
7320 06:02:52.672214 [DutyScan_Calibration_Flow] ====Done====
7321 06:02:52.672286
7322 06:02:52.675622 [DutyScan_Calibration_Flow] k_type=1
7323 06:02:52.692405
7324 06:02:52.692478 ==DQS 0 ==
7325 06:02:52.695222 Final DQS duty delay cell = 0
7326 06:02:52.698682 [0] MAX Duty = 5093%(X100), DQS PI = 26
7327 06:02:52.702325 [0] MIN Duty = 4969%(X100), DQS PI = 0
7328 06:02:52.705520 [0] AVG Duty = 5031%(X100)
7329 06:02:52.705620
7330 06:02:52.705712 ==DQS 1 ==
7331 06:02:52.709194 Final DQS duty delay cell = 0
7332 06:02:52.712188 [0] MAX Duty = 5187%(X100), DQS PI = 0
7333 06:02:52.715617 [0] MIN Duty = 4844%(X100), DQS PI = 32
7334 06:02:52.715717 [0] AVG Duty = 5015%(X100)
7335 06:02:52.718606
7336 06:02:52.721944 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7337 06:02:52.722052
7338 06:02:52.725655 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7339 06:02:52.728864 [DutyScan_Calibration_Flow] ====Done====
7340 06:02:52.728962
7341 06:02:52.732078 [DutyScan_Calibration_Flow] k_type=3
7342 06:02:52.749640
7343 06:02:52.749739 ==DQM 0 ==
7344 06:02:52.753441 Final DQM duty delay cell = 4
7345 06:02:52.756391 [4] MAX Duty = 5156%(X100), DQS PI = 24
7346 06:02:52.759915 [4] MIN Duty = 5000%(X100), DQS PI = 30
7347 06:02:52.763048 [4] AVG Duty = 5078%(X100)
7348 06:02:52.763149
7349 06:02:52.763242 ==DQM 1 ==
7350 06:02:52.766594 Final DQM duty delay cell = 0
7351 06:02:52.769685 [0] MAX Duty = 5281%(X100), DQS PI = 58
7352 06:02:52.773089 [0] MIN Duty = 4907%(X100), DQS PI = 34
7353 06:02:52.776329 [0] AVG Duty = 5094%(X100)
7354 06:02:52.776400
7355 06:02:52.779887 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7356 06:02:52.779960
7357 06:02:52.783095 CH1 DQM 1 Duty spec in!! Max-Min= 374%
7358 06:02:52.786266 [DutyScan_Calibration_Flow] ====Done====
7359 06:02:52.786340
7360 06:02:52.789845 [DutyScan_Calibration_Flow] k_type=2
7361 06:02:52.806793
7362 06:02:52.806895 ==DQ 0 ==
7363 06:02:52.810084 Final DQ duty delay cell = 0
7364 06:02:52.813347 [0] MAX Duty = 5093%(X100), DQS PI = 18
7365 06:02:52.816833 [0] MIN Duty = 4969%(X100), DQS PI = 2
7366 06:02:52.816909 [0] AVG Duty = 5031%(X100)
7367 06:02:52.816999
7368 06:02:52.820065 ==DQ 1 ==
7369 06:02:52.823318 Final DQ duty delay cell = 0
7370 06:02:52.826883 [0] MAX Duty = 5062%(X100), DQS PI = 4
7371 06:02:52.829878 [0] MIN Duty = 4813%(X100), DQS PI = 34
7372 06:02:52.830009 [0] AVG Duty = 4937%(X100)
7373 06:02:52.830072
7374 06:02:52.833232 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7375 06:02:52.833305
7376 06:02:52.836569 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7377 06:02:52.843385 [DutyScan_Calibration_Flow] ====Done====
7378 06:02:52.846852 nWR fixed to 30
7379 06:02:52.846931 [ModeRegInit_LP4] CH0 RK0
7380 06:02:52.849890 [ModeRegInit_LP4] CH0 RK1
7381 06:02:52.853170 [ModeRegInit_LP4] CH1 RK0
7382 06:02:52.853252 [ModeRegInit_LP4] CH1 RK1
7383 06:02:52.856416 match AC timing 5
7384 06:02:52.859740 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7385 06:02:52.863338 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7386 06:02:52.869829 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7387 06:02:52.873087 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7388 06:02:52.880335 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7389 06:02:52.880462 [MiockJmeterHQA]
7390 06:02:52.880551
7391 06:02:52.882996 [DramcMiockJmeter] u1RxGatingPI = 0
7392 06:02:52.886313 0 : 4254, 4029
7393 06:02:52.886385 4 : 4368, 4143
7394 06:02:52.886448 8 : 4252, 4027
7395 06:02:52.889778 12 : 4368, 4137
7396 06:02:52.889847 16 : 4257, 4027
7397 06:02:52.893252 20 : 4257, 4027
7398 06:02:52.893347 24 : 4252, 4026
7399 06:02:52.896279 28 : 4366, 4138
7400 06:02:52.896368 32 : 4365, 4137
7401 06:02:52.900016 36 : 4363, 4137
7402 06:02:52.900111 40 : 4255, 4029
7403 06:02:52.900415 44 : 4252, 4027
7404 06:02:52.902878 48 : 4363, 4138
7405 06:02:52.902983 52 : 4252, 4026
7406 06:02:52.906439 56 : 4366, 4139
7407 06:02:52.906557 60 : 4252, 4027
7408 06:02:52.909635 64 : 4252, 4027
7409 06:02:52.909794 68 : 4250, 4027
7410 06:02:52.909895 72 : 4252, 4029
7411 06:02:52.912786 76 : 4360, 4137
7412 06:02:52.912919 80 : 4252, 4029
7413 06:02:52.916482 84 : 4361, 4137
7414 06:02:52.916582 88 : 4363, 3295
7415 06:02:52.919561 92 : 4253, 0
7416 06:02:52.919681 96 : 4361, 0
7417 06:02:52.919780 100 : 4252, 0
7418 06:02:52.922755 104 : 4250, 0
7419 06:02:52.922872 108 : 4250, 0
7420 06:02:52.926342 112 : 4250, 0
7421 06:02:52.926421 116 : 4250, 0
7422 06:02:52.926486 120 : 4252, 0
7423 06:02:52.929705 124 : 4361, 0
7424 06:02:52.929814 128 : 4361, 0
7425 06:02:52.929911 132 : 4250, 0
7426 06:02:52.933067 136 : 4255, 0
7427 06:02:52.933167 140 : 4360, 0
7428 06:02:52.936379 144 : 4250, 0
7429 06:02:52.936509 148 : 4255, 0
7430 06:02:52.936630 152 : 4250, 0
7431 06:02:52.939725 156 : 4250, 0
7432 06:02:52.939840 160 : 4252, 0
7433 06:02:52.942769 164 : 4250, 0
7434 06:02:52.942872 168 : 4250, 0
7435 06:02:52.942962 172 : 4252, 0
7436 06:02:52.946392 176 : 4361, 0
7437 06:02:52.946482 180 : 4250, 0
7438 06:02:52.949477 184 : 4361, 0
7439 06:02:52.949629 188 : 4252, 0
7440 06:02:52.949749 192 : 4360, 0
7441 06:02:52.952555 196 : 4360, 0
7442 06:02:52.952656 200 : 4250, 23
7443 06:02:52.955944 204 : 4363, 2665
7444 06:02:52.956087 208 : 4249, 4027
7445 06:02:52.959662 212 : 4250, 4027
7446 06:02:52.959764 216 : 4363, 4140
7447 06:02:52.959857 220 : 4253, 4029
7448 06:02:52.962741 224 : 4250, 4027
7449 06:02:52.962815 228 : 4250, 4027
7450 06:02:52.965815 232 : 4252, 4029
7451 06:02:52.965922 236 : 4253, 4029
7452 06:02:52.969219 240 : 4363, 4139
7453 06:02:52.969296 244 : 4250, 4026
7454 06:02:52.972369 248 : 4250, 4027
7455 06:02:52.972447 252 : 4250, 4027
7456 06:02:52.975786 256 : 4363, 4139
7457 06:02:52.975863 260 : 4360, 4138
7458 06:02:52.979024 264 : 4248, 4024
7459 06:02:52.979097 268 : 4363, 4139
7460 06:02:52.982719 272 : 4253, 4029
7461 06:02:52.982792 276 : 4250, 4027
7462 06:02:52.985861 280 : 4250, 4026
7463 06:02:52.985963 284 : 4250, 4027
7464 06:02:52.986028 288 : 4253, 4029
7465 06:02:52.989026 292 : 4363, 4139
7466 06:02:52.989097 296 : 4250, 4026
7467 06:02:52.992603 300 : 4250, 4027
7468 06:02:52.992679 304 : 4250, 4027
7469 06:02:52.996013 308 : 4363, 4139
7470 06:02:52.996087 312 : 4360, 3956
7471 06:02:52.999058 316 : 4250, 1911
7472 06:02:52.999130
7473 06:02:52.999192 MIOCK jitter meter ch=0
7474 06:02:52.999254
7475 06:02:53.002270 1T = (316-92) = 224 dly cells
7476 06:02:53.009170 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7477 06:02:53.009251 ==
7478 06:02:53.012709 Dram Type= 6, Freq= 0, CH_0, rank 0
7479 06:02:53.015742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7480 06:02:53.015844 ==
7481 06:02:53.022356 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7482 06:02:53.025934 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7483 06:02:53.029252 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7484 06:02:53.035593 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7485 06:02:53.045511 [CA 0] Center 43 (13~73) winsize 61
7486 06:02:53.049067 [CA 1] Center 43 (13~73) winsize 61
7487 06:02:53.052285 [CA 2] Center 38 (8~68) winsize 61
7488 06:02:53.055662 [CA 3] Center 37 (8~67) winsize 60
7489 06:02:53.058942 [CA 4] Center 36 (7~66) winsize 60
7490 06:02:53.062527 [CA 5] Center 35 (5~65) winsize 61
7491 06:02:53.062610
7492 06:02:53.065454 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7493 06:02:53.065537
7494 06:02:53.069075 [CATrainingPosCal] consider 1 rank data
7495 06:02:53.072313 u2DelayCellTimex100 = 290/100 ps
7496 06:02:53.075511 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7497 06:02:53.082038 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7498 06:02:53.085778 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7499 06:02:53.088906 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7500 06:02:53.092089 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7501 06:02:53.095598 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7502 06:02:53.095681
7503 06:02:53.098784 CA PerBit enable=1, Macro0, CA PI delay=35
7504 06:02:53.098867
7505 06:02:53.102047 [CBTSetCACLKResult] CA Dly = 35
7506 06:02:53.105840 CS Dly: 10 (0~41)
7507 06:02:53.108883 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7508 06:02:53.112113 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7509 06:02:53.112197 ==
7510 06:02:53.115649 Dram Type= 6, Freq= 0, CH_0, rank 1
7511 06:02:53.118964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7512 06:02:53.119049 ==
7513 06:02:53.125423 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7514 06:02:53.128626 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7515 06:02:53.135555 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7516 06:02:53.138570 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7517 06:02:53.149176 [CA 0] Center 43 (13~74) winsize 62
7518 06:02:53.152418 [CA 1] Center 43 (13~73) winsize 61
7519 06:02:53.155919 [CA 2] Center 38 (9~68) winsize 60
7520 06:02:53.158888 [CA 3] Center 38 (9~68) winsize 60
7521 06:02:53.162437 [CA 4] Center 36 (7~66) winsize 60
7522 06:02:53.165781 [CA 5] Center 36 (6~66) winsize 61
7523 06:02:53.165865
7524 06:02:53.169078 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7525 06:02:53.169161
7526 06:02:53.172449 [CATrainingPosCal] consider 2 rank data
7527 06:02:53.175594 u2DelayCellTimex100 = 290/100 ps
7528 06:02:53.179158 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7529 06:02:53.185464 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7530 06:02:53.188838 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7531 06:02:53.192349 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7532 06:02:53.195527 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7533 06:02:53.198631 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7534 06:02:53.198714
7535 06:02:53.202399 CA PerBit enable=1, Macro0, CA PI delay=35
7536 06:02:53.202482
7537 06:02:53.205409 [CBTSetCACLKResult] CA Dly = 35
7538 06:02:53.208629 CS Dly: 11 (0~44)
7539 06:02:53.211886 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7540 06:02:53.215451 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7541 06:02:53.215534
7542 06:02:53.218545 ----->DramcWriteLeveling(PI) begin...
7543 06:02:53.218631 ==
7544 06:02:53.222220 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 06:02:53.228535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 06:02:53.228620 ==
7547 06:02:53.231920 Write leveling (Byte 0): 38 => 38
7548 06:02:53.232003 Write leveling (Byte 1): 31 => 31
7549 06:02:53.235112 DramcWriteLeveling(PI) end<-----
7550 06:02:53.235195
7551 06:02:53.238705 ==
7552 06:02:53.238789 Dram Type= 6, Freq= 0, CH_0, rank 0
7553 06:02:53.245047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7554 06:02:53.245162 ==
7555 06:02:53.248495 [Gating] SW mode calibration
7556 06:02:53.255318 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7557 06:02:53.258379 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7558 06:02:53.264991 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 06:02:53.268351 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 06:02:53.271549 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7561 06:02:53.278014 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7562 06:02:53.281625 1 4 16 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
7563 06:02:53.285030 1 4 20 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7564 06:02:53.291422 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7565 06:02:53.294817 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7566 06:02:53.298239 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7567 06:02:53.304673 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7568 06:02:53.308253 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7569 06:02:53.311335 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7570 06:02:53.317988 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7571 06:02:53.321425 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
7572 06:02:53.324566 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 06:02:53.331172 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 06:02:53.334548 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 06:02:53.338012 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 06:02:53.344554 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7577 06:02:53.347704 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7578 06:02:53.351336 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7579 06:02:53.357606 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7580 06:02:53.360856 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 06:02:53.364549 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 06:02:53.371294 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 06:02:53.374460 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 06:02:53.377423 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7585 06:02:53.380806 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7586 06:02:53.387557 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7587 06:02:53.390937 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7588 06:02:53.394151 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7589 06:02:53.400931 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 06:02:53.404573 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 06:02:53.407736 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 06:02:53.413856 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 06:02:53.417300 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 06:02:53.420970 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 06:02:53.427358 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 06:02:53.430690 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 06:02:53.433742 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 06:02:53.440536 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 06:02:53.443811 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 06:02:53.447273 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7601 06:02:53.453802 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7602 06:02:53.457384 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7603 06:02:53.460621 Total UI for P1: 0, mck2ui 16
7604 06:02:53.463775 best dqsien dly found for B0: ( 1, 9, 10)
7605 06:02:53.467303 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7606 06:02:53.473863 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 06:02:53.473984 Total UI for P1: 0, mck2ui 16
7608 06:02:53.480372 best dqsien dly found for B1: ( 1, 9, 18)
7609 06:02:53.483573 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7610 06:02:53.487154 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7611 06:02:53.487238
7612 06:02:53.490285 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7613 06:02:53.493463 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7614 06:02:53.496833 [Gating] SW calibration Done
7615 06:02:53.496917 ==
7616 06:02:53.500346 Dram Type= 6, Freq= 0, CH_0, rank 0
7617 06:02:53.503858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 06:02:53.503942 ==
7619 06:02:53.507107 RX Vref Scan: 0
7620 06:02:53.507190
7621 06:02:53.507256 RX Vref 0 -> 0, step: 1
7622 06:02:53.507318
7623 06:02:53.510176 RX Delay 0 -> 252, step: 8
7624 06:02:53.513535 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7625 06:02:53.519988 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7626 06:02:53.523494 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7627 06:02:53.526545 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7628 06:02:53.530243 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7629 06:02:53.533639 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7630 06:02:53.540049 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7631 06:02:53.543145 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7632 06:02:53.547106 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7633 06:02:53.549831 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7634 06:02:53.553465 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7635 06:02:53.560024 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7636 06:02:53.563048 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7637 06:02:53.566625 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7638 06:02:53.569862 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7639 06:02:53.573367 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7640 06:02:53.576628 ==
7641 06:02:53.576712 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 06:02:53.583323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 06:02:53.583406 ==
7644 06:02:53.583503 DQS Delay:
7645 06:02:53.586418 DQS0 = 0, DQS1 = 0
7646 06:02:53.586501 DQM Delay:
7647 06:02:53.589705 DQM0 = 137, DQM1 = 127
7648 06:02:53.589788 DQ Delay:
7649 06:02:53.593027 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7650 06:02:53.596359 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7651 06:02:53.599710 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7652 06:02:53.603394 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7653 06:02:53.603477
7654 06:02:53.603543
7655 06:02:53.603603 ==
7656 06:02:53.606287 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 06:02:53.613001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 06:02:53.613085 ==
7659 06:02:53.613152
7660 06:02:53.613212
7661 06:02:53.613270 TX Vref Scan disable
7662 06:02:53.616730 == TX Byte 0 ==
7663 06:02:53.619968 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7664 06:02:53.623376 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7665 06:02:53.627138 == TX Byte 1 ==
7666 06:02:53.629755 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7667 06:02:53.636340 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7668 06:02:53.636424 ==
7669 06:02:53.639631 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 06:02:53.642969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 06:02:53.643053 ==
7672 06:02:53.656104
7673 06:02:53.659553 TX Vref early break, caculate TX vref
7674 06:02:53.662654 TX Vref=16, minBit 0, minWin=23, winSum=375
7675 06:02:53.665996 TX Vref=18, minBit 0, minWin=23, winSum=383
7676 06:02:53.669535 TX Vref=20, minBit 7, minWin=23, winSum=399
7677 06:02:53.672486 TX Vref=22, minBit 7, minWin=24, winSum=407
7678 06:02:53.675869 TX Vref=24, minBit 4, minWin=24, winSum=414
7679 06:02:53.682281 TX Vref=26, minBit 7, minWin=25, winSum=423
7680 06:02:53.685956 TX Vref=28, minBit 4, minWin=25, winSum=432
7681 06:02:53.689118 TX Vref=30, minBit 2, minWin=26, winSum=427
7682 06:02:53.692707 TX Vref=32, minBit 1, minWin=25, winSum=415
7683 06:02:53.695570 TX Vref=34, minBit 7, minWin=24, winSum=407
7684 06:02:53.702747 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 30
7685 06:02:53.702821
7686 06:02:53.706044 Final TX Range 0 Vref 30
7687 06:02:53.706114
7688 06:02:53.706182 ==
7689 06:02:53.708823 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 06:02:53.712285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 06:02:53.712357 ==
7692 06:02:53.712418
7693 06:02:53.712475
7694 06:02:53.715666 TX Vref Scan disable
7695 06:02:53.722680 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7696 06:02:53.722771 == TX Byte 0 ==
7697 06:02:53.725740 u2DelayCellOfst[0]=13 cells (4 PI)
7698 06:02:53.728842 u2DelayCellOfst[1]=20 cells (6 PI)
7699 06:02:53.732155 u2DelayCellOfst[2]=13 cells (4 PI)
7700 06:02:53.735735 u2DelayCellOfst[3]=13 cells (4 PI)
7701 06:02:53.738702 u2DelayCellOfst[4]=10 cells (3 PI)
7702 06:02:53.742050 u2DelayCellOfst[5]=0 cells (0 PI)
7703 06:02:53.745821 u2DelayCellOfst[6]=20 cells (6 PI)
7704 06:02:53.748799 u2DelayCellOfst[7]=16 cells (5 PI)
7705 06:02:53.752145 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7706 06:02:53.755754 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7707 06:02:53.758710 == TX Byte 1 ==
7708 06:02:53.758782 u2DelayCellOfst[8]=0 cells (0 PI)
7709 06:02:53.762234 u2DelayCellOfst[9]=0 cells (0 PI)
7710 06:02:53.765553 u2DelayCellOfst[10]=3 cells (1 PI)
7711 06:02:53.769008 u2DelayCellOfst[11]=0 cells (0 PI)
7712 06:02:53.772254 u2DelayCellOfst[12]=10 cells (3 PI)
7713 06:02:53.775503 u2DelayCellOfst[13]=6 cells (2 PI)
7714 06:02:53.779101 u2DelayCellOfst[14]=13 cells (4 PI)
7715 06:02:53.782227 u2DelayCellOfst[15]=10 cells (3 PI)
7716 06:02:53.785157 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7717 06:02:53.792028 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7718 06:02:53.792114 DramC Write-DBI on
7719 06:02:53.792180 ==
7720 06:02:53.795721 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 06:02:53.798797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 06:02:53.802165 ==
7723 06:02:53.802248
7724 06:02:53.802314
7725 06:02:53.802375 TX Vref Scan disable
7726 06:02:53.805336 == TX Byte 0 ==
7727 06:02:53.808706 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7728 06:02:53.812289 == TX Byte 1 ==
7729 06:02:53.815402 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7730 06:02:53.815485 DramC Write-DBI off
7731 06:02:53.818628
7732 06:02:53.818711 [DATLAT]
7733 06:02:53.818776 Freq=1600, CH0 RK0
7734 06:02:53.818838
7735 06:02:53.822252 DATLAT Default: 0xf
7736 06:02:53.822335 0, 0xFFFF, sum = 0
7737 06:02:53.825456 1, 0xFFFF, sum = 0
7738 06:02:53.825540 2, 0xFFFF, sum = 0
7739 06:02:53.828621 3, 0xFFFF, sum = 0
7740 06:02:53.831840 4, 0xFFFF, sum = 0
7741 06:02:53.831925 5, 0xFFFF, sum = 0
7742 06:02:53.835504 6, 0xFFFF, sum = 0
7743 06:02:53.835592 7, 0xFFFF, sum = 0
7744 06:02:53.838557 8, 0xFFFF, sum = 0
7745 06:02:53.838635 9, 0xFFFF, sum = 0
7746 06:02:53.842005 10, 0xFFFF, sum = 0
7747 06:02:53.842093 11, 0xFFFF, sum = 0
7748 06:02:53.845540 12, 0xFFFF, sum = 0
7749 06:02:53.845660 13, 0xFFFF, sum = 0
7750 06:02:53.848653 14, 0x0, sum = 1
7751 06:02:53.848740 15, 0x0, sum = 2
7752 06:02:53.852106 16, 0x0, sum = 3
7753 06:02:53.852193 17, 0x0, sum = 4
7754 06:02:53.855278 best_step = 15
7755 06:02:53.855364
7756 06:02:53.855450 ==
7757 06:02:53.858547 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 06:02:53.862218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 06:02:53.862306 ==
7760 06:02:53.862410 RX Vref Scan: 1
7761 06:02:53.865273
7762 06:02:53.865359 Set Vref Range= 24 -> 127
7763 06:02:53.865445
7764 06:02:53.868866 RX Vref 24 -> 127, step: 1
7765 06:02:53.868953
7766 06:02:53.871995 RX Delay 19 -> 252, step: 4
7767 06:02:53.872082
7768 06:02:53.875392 Set Vref, RX VrefLevel [Byte0]: 24
7769 06:02:53.878622 [Byte1]: 24
7770 06:02:53.878709
7771 06:02:53.881724 Set Vref, RX VrefLevel [Byte0]: 25
7772 06:02:53.885137 [Byte1]: 25
7773 06:02:53.885222
7774 06:02:53.888482 Set Vref, RX VrefLevel [Byte0]: 26
7775 06:02:53.891755 [Byte1]: 26
7776 06:02:53.895556
7777 06:02:53.895641 Set Vref, RX VrefLevel [Byte0]: 27
7778 06:02:53.898974 [Byte1]: 27
7779 06:02:53.903474
7780 06:02:53.903558 Set Vref, RX VrefLevel [Byte0]: 28
7781 06:02:53.906448 [Byte1]: 28
7782 06:02:53.910764
7783 06:02:53.910848 Set Vref, RX VrefLevel [Byte0]: 29
7784 06:02:53.914380 [Byte1]: 29
7785 06:02:53.918349
7786 06:02:53.918433 Set Vref, RX VrefLevel [Byte0]: 30
7787 06:02:53.922249 [Byte1]: 30
7788 06:02:53.926217
7789 06:02:53.926300 Set Vref, RX VrefLevel [Byte0]: 31
7790 06:02:53.929327 [Byte1]: 31
7791 06:02:53.933477
7792 06:02:53.933561 Set Vref, RX VrefLevel [Byte0]: 32
7793 06:02:53.937312 [Byte1]: 32
7794 06:02:53.941032
7795 06:02:53.941131 Set Vref, RX VrefLevel [Byte0]: 33
7796 06:02:53.944682 [Byte1]: 33
7797 06:02:53.948864
7798 06:02:53.948949 Set Vref, RX VrefLevel [Byte0]: 34
7799 06:02:53.952367 [Byte1]: 34
7800 06:02:53.956461
7801 06:02:53.956546 Set Vref, RX VrefLevel [Byte0]: 35
7802 06:02:53.959769 [Byte1]: 35
7803 06:02:53.963836
7804 06:02:53.963920 Set Vref, RX VrefLevel [Byte0]: 36
7805 06:02:53.967138 [Byte1]: 36
7806 06:02:53.971340
7807 06:02:53.971424 Set Vref, RX VrefLevel [Byte0]: 37
7808 06:02:53.974873 [Byte1]: 37
7809 06:02:53.978972
7810 06:02:53.979055 Set Vref, RX VrefLevel [Byte0]: 38
7811 06:02:53.982521 [Byte1]: 38
7812 06:02:53.986807
7813 06:02:53.986891 Set Vref, RX VrefLevel [Byte0]: 39
7814 06:02:53.989910 [Byte1]: 39
7815 06:02:53.994337
7816 06:02:53.994421 Set Vref, RX VrefLevel [Byte0]: 40
7817 06:02:53.997445 [Byte1]: 40
7818 06:02:54.001716
7819 06:02:54.001799 Set Vref, RX VrefLevel [Byte0]: 41
7820 06:02:54.004880 [Byte1]: 41
7821 06:02:54.009252
7822 06:02:54.009337 Set Vref, RX VrefLevel [Byte0]: 42
7823 06:02:54.012508 [Byte1]: 42
7824 06:02:54.017020
7825 06:02:54.017104 Set Vref, RX VrefLevel [Byte0]: 43
7826 06:02:54.020033 [Byte1]: 43
7827 06:02:54.024584
7828 06:02:54.024668 Set Vref, RX VrefLevel [Byte0]: 44
7829 06:02:54.027828 [Byte1]: 44
7830 06:02:54.031855
7831 06:02:54.031939 Set Vref, RX VrefLevel [Byte0]: 45
7832 06:02:54.035144 [Byte1]: 45
7833 06:02:54.039890
7834 06:02:54.039974 Set Vref, RX VrefLevel [Byte0]: 46
7835 06:02:54.043192 [Byte1]: 46
7836 06:02:54.047308
7837 06:02:54.047392 Set Vref, RX VrefLevel [Byte0]: 47
7838 06:02:54.050344 [Byte1]: 47
7839 06:02:54.054881
7840 06:02:54.054965 Set Vref, RX VrefLevel [Byte0]: 48
7841 06:02:54.058058 [Byte1]: 48
7842 06:02:54.062414
7843 06:02:54.062498 Set Vref, RX VrefLevel [Byte0]: 49
7844 06:02:54.065495 [Byte1]: 49
7845 06:02:54.069896
7846 06:02:54.070020 Set Vref, RX VrefLevel [Byte0]: 50
7847 06:02:54.073031 [Byte1]: 50
7848 06:02:54.077638
7849 06:02:54.077722 Set Vref, RX VrefLevel [Byte0]: 51
7850 06:02:54.080786 [Byte1]: 51
7851 06:02:54.085158
7852 06:02:54.085242 Set Vref, RX VrefLevel [Byte0]: 52
7853 06:02:54.088250 [Byte1]: 52
7854 06:02:54.092412
7855 06:02:54.092496 Set Vref, RX VrefLevel [Byte0]: 53
7856 06:02:54.095727 [Byte1]: 53
7857 06:02:54.100280
7858 06:02:54.100364 Set Vref, RX VrefLevel [Byte0]: 54
7859 06:02:54.103404 [Byte1]: 54
7860 06:02:54.107634
7861 06:02:54.107718 Set Vref, RX VrefLevel [Byte0]: 55
7862 06:02:54.111006 [Byte1]: 55
7863 06:02:54.115454
7864 06:02:54.115538 Set Vref, RX VrefLevel [Byte0]: 56
7865 06:02:54.118417 [Byte1]: 56
7866 06:02:54.122965
7867 06:02:54.123050 Set Vref, RX VrefLevel [Byte0]: 57
7868 06:02:54.126240 [Byte1]: 57
7869 06:02:54.130409
7870 06:02:54.130492 Set Vref, RX VrefLevel [Byte0]: 58
7871 06:02:54.133678 [Byte1]: 58
7872 06:02:54.138368
7873 06:02:54.138452 Set Vref, RX VrefLevel [Byte0]: 59
7874 06:02:54.141203 [Byte1]: 59
7875 06:02:54.145913
7876 06:02:54.146036 Set Vref, RX VrefLevel [Byte0]: 60
7877 06:02:54.148905 [Byte1]: 60
7878 06:02:54.153433
7879 06:02:54.153518 Set Vref, RX VrefLevel [Byte0]: 61
7880 06:02:54.156466 [Byte1]: 61
7881 06:02:54.160545
7882 06:02:54.160628 Set Vref, RX VrefLevel [Byte0]: 62
7883 06:02:54.164319 [Byte1]: 62
7884 06:02:54.168403
7885 06:02:54.168487 Set Vref, RX VrefLevel [Byte0]: 63
7886 06:02:54.171671 [Byte1]: 63
7887 06:02:54.175778
7888 06:02:54.175862 Set Vref, RX VrefLevel [Byte0]: 64
7889 06:02:54.179351 [Byte1]: 64
7890 06:02:54.183431
7891 06:02:54.186660 Set Vref, RX VrefLevel [Byte0]: 65
7892 06:02:54.186745 [Byte1]: 65
7893 06:02:54.191054
7894 06:02:54.191163 Set Vref, RX VrefLevel [Byte0]: 66
7895 06:02:54.194334 [Byte1]: 66
7896 06:02:54.198561
7897 06:02:54.198645 Set Vref, RX VrefLevel [Byte0]: 67
7898 06:02:54.202153 [Byte1]: 67
7899 06:02:54.206394
7900 06:02:54.206478 Set Vref, RX VrefLevel [Byte0]: 68
7901 06:02:54.209688 [Byte1]: 68
7902 06:02:54.213962
7903 06:02:54.214045 Set Vref, RX VrefLevel [Byte0]: 69
7904 06:02:54.217062 [Byte1]: 69
7905 06:02:54.221406
7906 06:02:54.221513 Set Vref, RX VrefLevel [Byte0]: 70
7907 06:02:54.224875 [Byte1]: 70
7908 06:02:54.229053
7909 06:02:54.229139 Set Vref, RX VrefLevel [Byte0]: 71
7910 06:02:54.232470 [Byte1]: 71
7911 06:02:54.236683
7912 06:02:54.236767 Set Vref, RX VrefLevel [Byte0]: 72
7913 06:02:54.239765 [Byte1]: 72
7914 06:02:54.244035
7915 06:02:54.244119 Set Vref, RX VrefLevel [Byte0]: 73
7916 06:02:54.247344 [Byte1]: 73
7917 06:02:54.251770
7918 06:02:54.251854 Set Vref, RX VrefLevel [Byte0]: 74
7919 06:02:54.254793 [Byte1]: 74
7920 06:02:54.259271
7921 06:02:54.259355 Set Vref, RX VrefLevel [Byte0]: 75
7922 06:02:54.262393 [Byte1]: 75
7923 06:02:54.267083
7924 06:02:54.267166 Set Vref, RX VrefLevel [Byte0]: 76
7925 06:02:54.270430 [Byte1]: 76
7926 06:02:54.274366
7927 06:02:54.274450 Set Vref, RX VrefLevel [Byte0]: 77
7928 06:02:54.277536 [Byte1]: 77
7929 06:02:54.281888
7930 06:02:54.282012 Set Vref, RX VrefLevel [Byte0]: 78
7931 06:02:54.285394 [Byte1]: 78
7932 06:02:54.289758
7933 06:02:54.289842 Final RX Vref Byte 0 = 59 to rank0
7934 06:02:54.292864 Final RX Vref Byte 1 = 61 to rank0
7935 06:02:54.296414 Final RX Vref Byte 0 = 59 to rank1
7936 06:02:54.299496 Final RX Vref Byte 1 = 61 to rank1==
7937 06:02:54.302929 Dram Type= 6, Freq= 0, CH_0, rank 0
7938 06:02:54.309497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7939 06:02:54.309581 ==
7940 06:02:54.309648 DQS Delay:
7941 06:02:54.309711 DQS0 = 0, DQS1 = 0
7942 06:02:54.312668 DQM Delay:
7943 06:02:54.312755 DQM0 = 136, DQM1 = 125
7944 06:02:54.315850 DQ Delay:
7945 06:02:54.319306 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7946 06:02:54.322569 DQ4 =138, DQ5 =126, DQ6 =146, DQ7 =144
7947 06:02:54.325978 DQ8 =116, DQ9 =112, DQ10 =128, DQ11 =118
7948 06:02:54.329081 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =134
7949 06:02:54.329166
7950 06:02:54.329237
7951 06:02:54.329340
7952 06:02:54.332655 [DramC_TX_OE_Calibration] TA2
7953 06:02:54.335910 Original DQ_B0 (3 6) =30, OEN = 27
7954 06:02:54.338983 Original DQ_B1 (3 6) =30, OEN = 27
7955 06:02:54.342468 24, 0x0, End_B0=24 End_B1=24
7956 06:02:54.342554 25, 0x0, End_B0=25 End_B1=25
7957 06:02:54.345996 26, 0x0, End_B0=26 End_B1=26
7958 06:02:54.349313 27, 0x0, End_B0=27 End_B1=27
7959 06:02:54.352352 28, 0x0, End_B0=28 End_B1=28
7960 06:02:54.355861 29, 0x0, End_B0=29 End_B1=29
7961 06:02:54.355947 30, 0x0, End_B0=30 End_B1=30
7962 06:02:54.359092 31, 0x4141, End_B0=30 End_B1=30
7963 06:02:54.362288 Byte0 end_step=30 best_step=27
7964 06:02:54.365977 Byte1 end_step=30 best_step=27
7965 06:02:54.369189 Byte0 TX OE(2T, 0.5T) = (3, 3)
7966 06:02:54.372549 Byte1 TX OE(2T, 0.5T) = (3, 3)
7967 06:02:54.372633
7968 06:02:54.372700
7969 06:02:54.379442 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7970 06:02:54.382422 CH0 RK0: MR19=303, MR18=1E1C
7971 06:02:54.388978 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
7972 06:02:54.389063
7973 06:02:54.392308 ----->DramcWriteLeveling(PI) begin...
7974 06:02:54.392393 ==
7975 06:02:54.395819 Dram Type= 6, Freq= 0, CH_0, rank 1
7976 06:02:54.398813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7977 06:02:54.398898 ==
7978 06:02:54.401979 Write leveling (Byte 0): 37 => 37
7979 06:02:54.405726 Write leveling (Byte 1): 30 => 30
7980 06:02:54.408948 DramcWriteLeveling(PI) end<-----
7981 06:02:54.409032
7982 06:02:54.409097 ==
7983 06:02:54.412364 Dram Type= 6, Freq= 0, CH_0, rank 1
7984 06:02:54.415494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7985 06:02:54.415579 ==
7986 06:02:54.418679 [Gating] SW mode calibration
7987 06:02:54.425606 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7988 06:02:54.432394 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7989 06:02:54.435921 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 06:02:54.438749 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 06:02:54.445514 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 06:02:54.448954 1 4 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
7993 06:02:54.451997 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7994 06:02:54.458966 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 06:02:54.462098 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 06:02:54.465248 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 06:02:54.471847 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 06:02:54.475416 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 06:02:54.478465 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8000 06:02:54.485722 1 5 12 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (1 0)
8001 06:02:54.488967 1 5 16 | B1->B0 | 2828 2323 | 0 0 | (0 1) (1 0)
8002 06:02:54.492017 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 06:02:54.498765 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 06:02:54.502095 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 06:02:54.505303 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 06:02:54.512032 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 06:02:54.515581 1 6 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8008 06:02:54.518727 1 6 12 | B1->B0 | 2d2d 4141 | 0 0 | (0 0) (0 0)
8009 06:02:54.525535 1 6 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8010 06:02:54.529095 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 06:02:54.531926 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 06:02:54.538909 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 06:02:54.542036 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 06:02:54.545657 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 06:02:54.548676 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 06:02:54.555809 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8017 06:02:54.558602 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8018 06:02:54.562237 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8019 06:02:54.568864 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 06:02:54.571885 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 06:02:54.575146 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 06:02:54.582220 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 06:02:54.585452 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 06:02:54.588732 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 06:02:54.595551 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 06:02:54.598841 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 06:02:54.601868 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 06:02:54.608534 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 06:02:54.612011 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 06:02:54.615343 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 06:02:54.622266 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8032 06:02:54.625717 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8033 06:02:54.628971 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8034 06:02:54.632201 Total UI for P1: 0, mck2ui 16
8035 06:02:54.636068 best dqsien dly found for B0: ( 1, 9, 10)
8036 06:02:54.638798 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 06:02:54.642094 Total UI for P1: 0, mck2ui 16
8038 06:02:54.645574 best dqsien dly found for B1: ( 1, 9, 14)
8039 06:02:54.648636 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8040 06:02:54.655240 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8041 06:02:54.655324
8042 06:02:54.658368 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8043 06:02:54.661623 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8044 06:02:54.665144 [Gating] SW calibration Done
8045 06:02:54.665228 ==
8046 06:02:54.668530 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 06:02:54.671888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 06:02:54.671973 ==
8049 06:02:54.675335 RX Vref Scan: 0
8050 06:02:54.675418
8051 06:02:54.675485 RX Vref 0 -> 0, step: 1
8052 06:02:54.675546
8053 06:02:54.678234 RX Delay 0 -> 252, step: 8
8054 06:02:54.681646 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8055 06:02:54.684988 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8056 06:02:54.691813 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8057 06:02:54.695043 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8058 06:02:54.698603 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8059 06:02:54.701557 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8060 06:02:54.705356 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8061 06:02:54.711885 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8062 06:02:54.715194 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8063 06:02:54.718405 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8064 06:02:54.721774 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8065 06:02:54.725151 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8066 06:02:54.731681 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8067 06:02:54.735125 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8068 06:02:54.738325 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8069 06:02:54.741632 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8070 06:02:54.741716 ==
8071 06:02:54.744965 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 06:02:54.751424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 06:02:54.751509 ==
8074 06:02:54.751575 DQS Delay:
8075 06:02:54.754803 DQS0 = 0, DQS1 = 0
8076 06:02:54.754887 DQM Delay:
8077 06:02:54.754953 DQM0 = 136, DQM1 = 124
8078 06:02:54.758379 DQ Delay:
8079 06:02:54.761662 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8080 06:02:54.765021 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8081 06:02:54.768043 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8082 06:02:54.771370 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8083 06:02:54.771454
8084 06:02:54.771520
8085 06:02:54.771582 ==
8086 06:02:54.774692 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 06:02:54.781611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 06:02:54.781727 ==
8089 06:02:54.781794
8090 06:02:54.781856
8091 06:02:54.781915 TX Vref Scan disable
8092 06:02:54.784975 == TX Byte 0 ==
8093 06:02:54.788218 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8094 06:02:54.791370 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8095 06:02:54.794764 == TX Byte 1 ==
8096 06:02:54.798095 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8097 06:02:54.801609 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8098 06:02:54.805029 ==
8099 06:02:54.808160 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 06:02:54.811312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 06:02:54.811397 ==
8102 06:02:54.825484
8103 06:02:54.829211 TX Vref early break, caculate TX vref
8104 06:02:54.832069 TX Vref=16, minBit 0, minWin=23, winSum=391
8105 06:02:54.835568 TX Vref=18, minBit 0, minWin=24, winSum=397
8106 06:02:54.838945 TX Vref=20, minBit 8, minWin=24, winSum=409
8107 06:02:54.842202 TX Vref=22, minBit 8, minWin=24, winSum=412
8108 06:02:54.845642 TX Vref=24, minBit 1, minWin=25, winSum=420
8109 06:02:54.852351 TX Vref=26, minBit 0, minWin=25, winSum=430
8110 06:02:54.855658 TX Vref=28, minBit 0, minWin=26, winSum=430
8111 06:02:54.858812 TX Vref=30, minBit 0, minWin=26, winSum=425
8112 06:02:54.862105 TX Vref=32, minBit 0, minWin=25, winSum=418
8113 06:02:54.865362 TX Vref=34, minBit 4, minWin=24, winSum=409
8114 06:02:54.868937 TX Vref=36, minBit 2, minWin=24, winSum=400
8115 06:02:54.875489 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8116 06:02:54.875575
8117 06:02:54.879098 Final TX Range 0 Vref 28
8118 06:02:54.879183
8119 06:02:54.879249 ==
8120 06:02:54.882335 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 06:02:54.885537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 06:02:54.885621 ==
8123 06:02:54.885688
8124 06:02:54.885749
8125 06:02:54.888893 TX Vref Scan disable
8126 06:02:54.895149 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8127 06:02:54.895234 == TX Byte 0 ==
8128 06:02:54.898708 u2DelayCellOfst[0]=16 cells (5 PI)
8129 06:02:54.901777 u2DelayCellOfst[1]=20 cells (6 PI)
8130 06:02:54.904976 u2DelayCellOfst[2]=16 cells (5 PI)
8131 06:02:54.908568 u2DelayCellOfst[3]=16 cells (5 PI)
8132 06:02:54.911662 u2DelayCellOfst[4]=10 cells (3 PI)
8133 06:02:54.914985 u2DelayCellOfst[5]=0 cells (0 PI)
8134 06:02:54.918493 u2DelayCellOfst[6]=20 cells (6 PI)
8135 06:02:54.921883 u2DelayCellOfst[7]=20 cells (6 PI)
8136 06:02:54.925032 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8137 06:02:54.928225 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8138 06:02:54.931675 == TX Byte 1 ==
8139 06:02:54.934917 u2DelayCellOfst[8]=0 cells (0 PI)
8140 06:02:54.938531 u2DelayCellOfst[9]=3 cells (1 PI)
8141 06:02:54.938615 u2DelayCellOfst[10]=6 cells (2 PI)
8142 06:02:54.941703 u2DelayCellOfst[11]=3 cells (1 PI)
8143 06:02:54.945148 u2DelayCellOfst[12]=13 cells (4 PI)
8144 06:02:54.948406 u2DelayCellOfst[13]=13 cells (4 PI)
8145 06:02:54.952181 u2DelayCellOfst[14]=16 cells (5 PI)
8146 06:02:54.955201 u2DelayCellOfst[15]=10 cells (3 PI)
8147 06:02:54.958579 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8148 06:02:54.964939 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8149 06:02:54.965040 DramC Write-DBI on
8150 06:02:54.965107 ==
8151 06:02:54.968170 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 06:02:54.974778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 06:02:54.974863 ==
8154 06:02:54.974929
8155 06:02:54.974991
8156 06:02:54.975051 TX Vref Scan disable
8157 06:02:54.978995 == TX Byte 0 ==
8158 06:02:54.982290 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8159 06:02:54.985706 == TX Byte 1 ==
8160 06:02:54.989199 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8161 06:02:54.989283 DramC Write-DBI off
8162 06:02:54.992472
8163 06:02:54.992556 [DATLAT]
8164 06:02:54.992622 Freq=1600, CH0 RK1
8165 06:02:54.992685
8166 06:02:54.995659 DATLAT Default: 0xf
8167 06:02:54.995743 0, 0xFFFF, sum = 0
8168 06:02:54.999060 1, 0xFFFF, sum = 0
8169 06:02:54.999146 2, 0xFFFF, sum = 0
8170 06:02:55.002157 3, 0xFFFF, sum = 0
8171 06:02:55.005634 4, 0xFFFF, sum = 0
8172 06:02:55.005719 5, 0xFFFF, sum = 0
8173 06:02:55.008956 6, 0xFFFF, sum = 0
8174 06:02:55.009042 7, 0xFFFF, sum = 0
8175 06:02:55.012082 8, 0xFFFF, sum = 0
8176 06:02:55.012167 9, 0xFFFF, sum = 0
8177 06:02:55.015765 10, 0xFFFF, sum = 0
8178 06:02:55.015851 11, 0xFFFF, sum = 0
8179 06:02:55.018827 12, 0xFFFF, sum = 0
8180 06:02:55.018912 13, 0xFFFF, sum = 0
8181 06:02:55.022280 14, 0x0, sum = 1
8182 06:02:55.022365 15, 0x0, sum = 2
8183 06:02:55.025428 16, 0x0, sum = 3
8184 06:02:55.025513 17, 0x0, sum = 4
8185 06:02:55.028785 best_step = 15
8186 06:02:55.028870
8187 06:02:55.028936 ==
8188 06:02:55.032439 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 06:02:55.035645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 06:02:55.035730 ==
8191 06:02:55.035796 RX Vref Scan: 0
8192 06:02:55.038922
8193 06:02:55.039006 RX Vref 0 -> 0, step: 1
8194 06:02:55.039073
8195 06:02:55.042153 RX Delay 11 -> 252, step: 4
8196 06:02:55.045771 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8197 06:02:55.051938 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8198 06:02:55.055471 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8199 06:02:55.058793 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8200 06:02:55.061819 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8201 06:02:55.065484 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8202 06:02:55.071850 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8203 06:02:55.075334 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8204 06:02:55.078582 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8205 06:02:55.081798 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8206 06:02:55.085495 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8207 06:02:55.092180 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8208 06:02:55.095102 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8209 06:02:55.098678 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8210 06:02:55.101800 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8211 06:02:55.105044 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8212 06:02:55.108368 ==
8213 06:02:55.111893 Dram Type= 6, Freq= 0, CH_0, rank 1
8214 06:02:55.115297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8215 06:02:55.115382 ==
8216 06:02:55.115449 DQS Delay:
8217 06:02:55.118339 DQS0 = 0, DQS1 = 0
8218 06:02:55.118424 DQM Delay:
8219 06:02:55.121708 DQM0 = 133, DQM1 = 123
8220 06:02:55.121819 DQ Delay:
8221 06:02:55.125014 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8222 06:02:55.128141 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8223 06:02:55.131451 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8224 06:02:55.134791 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8225 06:02:55.134876
8226 06:02:55.134942
8227 06:02:55.135003
8228 06:02:55.138381 [DramC_TX_OE_Calibration] TA2
8229 06:02:55.141353 Original DQ_B0 (3 6) =30, OEN = 27
8230 06:02:55.144980 Original DQ_B1 (3 6) =30, OEN = 27
8231 06:02:55.148319 24, 0x0, End_B0=24 End_B1=24
8232 06:02:55.151411 25, 0x0, End_B0=25 End_B1=25
8233 06:02:55.151497 26, 0x0, End_B0=26 End_B1=26
8234 06:02:55.155155 27, 0x0, End_B0=27 End_B1=27
8235 06:02:55.158439 28, 0x0, End_B0=28 End_B1=28
8236 06:02:55.161720 29, 0x0, End_B0=29 End_B1=29
8237 06:02:55.165078 30, 0x0, End_B0=30 End_B1=30
8238 06:02:55.165164 31, 0x4141, End_B0=30 End_B1=30
8239 06:02:55.168358 Byte0 end_step=30 best_step=27
8240 06:02:55.171561 Byte1 end_step=30 best_step=27
8241 06:02:55.174570 Byte0 TX OE(2T, 0.5T) = (3, 3)
8242 06:02:55.178129 Byte1 TX OE(2T, 0.5T) = (3, 3)
8243 06:02:55.178214
8244 06:02:55.178280
8245 06:02:55.184731 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 395 ps
8246 06:02:55.188162 CH0 RK1: MR19=303, MR18=1D0A
8247 06:02:55.194431 CH0_RK1: MR19=0x303, MR18=0x1D0A, DQSOSC=395, MR23=63, INC=23, DEC=15
8248 06:02:55.197794 [RxdqsGatingPostProcess] freq 1600
8249 06:02:55.204589 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8250 06:02:55.204674 best DQS0 dly(2T, 0.5T) = (1, 1)
8251 06:02:55.208164 best DQS1 dly(2T, 0.5T) = (1, 1)
8252 06:02:55.211308 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8253 06:02:55.214408 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8254 06:02:55.217771 best DQS0 dly(2T, 0.5T) = (1, 1)
8255 06:02:55.221151 best DQS1 dly(2T, 0.5T) = (1, 1)
8256 06:02:55.224199 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8257 06:02:55.227828 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8258 06:02:55.231250 Pre-setting of DQS Precalculation
8259 06:02:55.234378 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8260 06:02:55.234462 ==
8261 06:02:55.238065 Dram Type= 6, Freq= 0, CH_1, rank 0
8262 06:02:55.244368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 06:02:55.244460 ==
8264 06:02:55.247808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8265 06:02:55.254164 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8266 06:02:55.257782 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8267 06:02:55.264148 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8268 06:02:55.271927 [CA 0] Center 40 (11~70) winsize 60
8269 06:02:55.275138 [CA 1] Center 40 (10~71) winsize 62
8270 06:02:55.278623 [CA 2] Center 37 (8~66) winsize 59
8271 06:02:55.281860 [CA 3] Center 36 (7~66) winsize 60
8272 06:02:55.285354 [CA 4] Center 36 (6~67) winsize 62
8273 06:02:55.288504 [CA 5] Center 35 (6~65) winsize 60
8274 06:02:55.288588
8275 06:02:55.292077 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8276 06:02:55.292161
8277 06:02:55.295142 [CATrainingPosCal] consider 1 rank data
8278 06:02:55.298936 u2DelayCellTimex100 = 290/100 ps
8279 06:02:55.302083 CA0 delay=40 (11~70),Diff = 5 PI (16 cell)
8280 06:02:55.308523 CA1 delay=40 (10~71),Diff = 5 PI (16 cell)
8281 06:02:55.311832 CA2 delay=37 (8~66),Diff = 2 PI (6 cell)
8282 06:02:55.315198 CA3 delay=36 (7~66),Diff = 1 PI (3 cell)
8283 06:02:55.318537 CA4 delay=36 (6~67),Diff = 1 PI (3 cell)
8284 06:02:55.321888 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
8285 06:02:55.322014
8286 06:02:55.325082 CA PerBit enable=1, Macro0, CA PI delay=35
8287 06:02:55.325167
8288 06:02:55.328293 [CBTSetCACLKResult] CA Dly = 35
8289 06:02:55.331612 CS Dly: 9 (0~40)
8290 06:02:55.335206 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8291 06:02:55.338245 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8292 06:02:55.338330 ==
8293 06:02:55.341558 Dram Type= 6, Freq= 0, CH_1, rank 1
8294 06:02:55.344861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 06:02:55.348052 ==
8296 06:02:55.351397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8297 06:02:55.355101 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8298 06:02:55.361481 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8299 06:02:55.364810 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8300 06:02:55.375443 [CA 0] Center 42 (13~72) winsize 60
8301 06:02:55.378410 [CA 1] Center 42 (12~72) winsize 61
8302 06:02:55.381625 [CA 2] Center 38 (9~68) winsize 60
8303 06:02:55.384901 [CA 3] Center 37 (8~67) winsize 60
8304 06:02:55.388372 [CA 4] Center 38 (8~68) winsize 61
8305 06:02:55.391701 [CA 5] Center 37 (7~67) winsize 61
8306 06:02:55.391783
8307 06:02:55.394965 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8308 06:02:55.395047
8309 06:02:55.398518 [CATrainingPosCal] consider 2 rank data
8310 06:02:55.401376 u2DelayCellTimex100 = 290/100 ps
8311 06:02:55.404793 CA0 delay=41 (13~70),Diff = 5 PI (16 cell)
8312 06:02:55.411806 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8313 06:02:55.414777 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8314 06:02:55.418313 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8315 06:02:55.421158 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8316 06:02:55.424701 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8317 06:02:55.424805
8318 06:02:55.428148 CA PerBit enable=1, Macro0, CA PI delay=36
8319 06:02:55.428247
8320 06:02:55.431393 [CBTSetCACLKResult] CA Dly = 36
8321 06:02:55.434653 CS Dly: 10 (0~42)
8322 06:02:55.438192 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8323 06:02:55.441419 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8324 06:02:55.441519
8325 06:02:55.444417 ----->DramcWriteLeveling(PI) begin...
8326 06:02:55.444513 ==
8327 06:02:55.448165 Dram Type= 6, Freq= 0, CH_1, rank 0
8328 06:02:55.454344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 06:02:55.454417 ==
8330 06:02:55.457902 Write leveling (Byte 0): 24 => 24
8331 06:02:55.458017 Write leveling (Byte 1): 27 => 27
8332 06:02:55.461161 DramcWriteLeveling(PI) end<-----
8333 06:02:55.461258
8334 06:02:55.461345 ==
8335 06:02:55.464465 Dram Type= 6, Freq= 0, CH_1, rank 0
8336 06:02:55.471341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8337 06:02:55.471415 ==
8338 06:02:55.474541 [Gating] SW mode calibration
8339 06:02:55.480908 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8340 06:02:55.484302 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8341 06:02:55.491516 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 06:02:55.494307 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 06:02:55.497854 1 4 8 | B1->B0 | 2828 2e2e | 0 0 | (0 0) (0 0)
8344 06:02:55.504515 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 06:02:55.507769 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 06:02:55.510936 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 06:02:55.517750 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 06:02:55.521003 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 06:02:55.524386 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 06:02:55.530987 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8351 06:02:55.534156 1 5 8 | B1->B0 | 2f2f 2929 | 0 0 | (0 1) (1 0)
8352 06:02:55.537465 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8353 06:02:55.541009 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 06:02:55.547620 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 06:02:55.550908 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 06:02:55.554001 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 06:02:55.560752 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 06:02:55.563947 1 6 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
8359 06:02:55.567348 1 6 8 | B1->B0 | 3e3e 4343 | 0 0 | (0 0) (0 0)
8360 06:02:55.573853 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 06:02:55.577756 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 06:02:55.580538 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 06:02:55.587126 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 06:02:55.590329 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 06:02:55.594004 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 06:02:55.600785 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 06:02:55.603920 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8368 06:02:55.607141 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8369 06:02:55.613686 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8370 06:02:55.617101 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 06:02:55.620309 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 06:02:55.627029 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 06:02:55.630272 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 06:02:55.633735 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 06:02:55.640667 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 06:02:55.643796 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 06:02:55.647072 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 06:02:55.653558 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 06:02:55.657075 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 06:02:55.660160 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 06:02:55.667043 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 06:02:55.670347 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 06:02:55.673836 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8384 06:02:55.680110 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8385 06:02:55.683536 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 06:02:55.686899 Total UI for P1: 0, mck2ui 16
8387 06:02:55.690141 best dqsien dly found for B0: ( 1, 9, 10)
8388 06:02:55.693653 Total UI for P1: 0, mck2ui 16
8389 06:02:55.696868 best dqsien dly found for B1: ( 1, 9, 10)
8390 06:02:55.700204 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8391 06:02:55.703504 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8392 06:02:55.703578
8393 06:02:55.706775 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8394 06:02:55.709995 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8395 06:02:55.713646 [Gating] SW calibration Done
8396 06:02:55.713725 ==
8397 06:02:55.716843 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 06:02:55.720352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 06:02:55.720428 ==
8400 06:02:55.723320 RX Vref Scan: 0
8401 06:02:55.723402
8402 06:02:55.726643 RX Vref 0 -> 0, step: 1
8403 06:02:55.726719
8404 06:02:55.726799 RX Delay 0 -> 252, step: 8
8405 06:02:55.733669 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8406 06:02:55.736576 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8407 06:02:55.740143 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8408 06:02:55.743975 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8409 06:02:55.746909 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8410 06:02:55.750144 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8411 06:02:55.756510 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8412 06:02:55.760157 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8413 06:02:55.763635 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8414 06:02:55.766664 iDelay=200, Bit 9, Center 123 (80 ~ 167) 88
8415 06:02:55.770283 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8416 06:02:55.776925 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8417 06:02:55.780016 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8418 06:02:55.783165 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8419 06:02:55.786708 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8420 06:02:55.793170 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8421 06:02:55.793248 ==
8422 06:02:55.796752 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 06:02:55.800382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 06:02:55.800457 ==
8425 06:02:55.800538 DQS Delay:
8426 06:02:55.803423 DQS0 = 0, DQS1 = 0
8427 06:02:55.803496 DQM Delay:
8428 06:02:55.806978 DQM0 = 138, DQM1 = 131
8429 06:02:55.807051 DQ Delay:
8430 06:02:55.809862 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8431 06:02:55.813614 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8432 06:02:55.816505 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
8433 06:02:55.820166 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8434 06:02:55.820239
8435 06:02:55.820318
8436 06:02:55.820397 ==
8437 06:02:55.823303 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 06:02:55.829833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 06:02:55.829914 ==
8440 06:02:55.830017
8441 06:02:55.830094
8442 06:02:55.830170 TX Vref Scan disable
8443 06:02:55.833570 == TX Byte 0 ==
8444 06:02:55.836690 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8445 06:02:55.843368 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8446 06:02:55.843444 == TX Byte 1 ==
8447 06:02:55.846810 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8448 06:02:55.853403 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8449 06:02:55.853483 ==
8450 06:02:55.856734 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 06:02:55.860090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 06:02:55.860171 ==
8453 06:02:55.872096
8454 06:02:55.875520 TX Vref early break, caculate TX vref
8455 06:02:55.878794 TX Vref=16, minBit 10, minWin=22, winSum=374
8456 06:02:55.882064 TX Vref=18, minBit 15, minWin=22, winSum=382
8457 06:02:55.885693 TX Vref=20, minBit 15, minWin=23, winSum=393
8458 06:02:55.888758 TX Vref=22, minBit 10, minWin=23, winSum=400
8459 06:02:55.895722 TX Vref=24, minBit 15, minWin=24, winSum=413
8460 06:02:55.899080 TX Vref=26, minBit 14, minWin=24, winSum=421
8461 06:02:55.902546 TX Vref=28, minBit 14, minWin=25, winSum=424
8462 06:02:55.905822 TX Vref=30, minBit 8, minWin=25, winSum=417
8463 06:02:55.909013 TX Vref=32, minBit 13, minWin=24, winSum=412
8464 06:02:55.912326 TX Vref=34, minBit 12, minWin=23, winSum=399
8465 06:02:55.919077 [TxChooseVref] Worse bit 14, Min win 25, Win sum 424, Final Vref 28
8466 06:02:55.919161
8467 06:02:55.922304 Final TX Range 0 Vref 28
8468 06:02:55.922386
8469 06:02:55.922469 ==
8470 06:02:55.925676 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 06:02:55.929089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 06:02:55.929171 ==
8473 06:02:55.929253
8474 06:02:55.929330
8475 06:02:55.932013 TX Vref Scan disable
8476 06:02:55.938602 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8477 06:02:55.938686 == TX Byte 0 ==
8478 06:02:55.941970 u2DelayCellOfst[0]=16 cells (5 PI)
8479 06:02:55.945933 u2DelayCellOfst[1]=10 cells (3 PI)
8480 06:02:55.948542 u2DelayCellOfst[2]=0 cells (0 PI)
8481 06:02:55.952075 u2DelayCellOfst[3]=3 cells (1 PI)
8482 06:02:55.955482 u2DelayCellOfst[4]=6 cells (2 PI)
8483 06:02:55.959088 u2DelayCellOfst[5]=16 cells (5 PI)
8484 06:02:55.961925 u2DelayCellOfst[6]=16 cells (5 PI)
8485 06:02:55.965451 u2DelayCellOfst[7]=3 cells (1 PI)
8486 06:02:55.968673 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8487 06:02:55.972050 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8488 06:02:55.975211 == TX Byte 1 ==
8489 06:02:55.978751 u2DelayCellOfst[8]=0 cells (0 PI)
8490 06:02:55.981673 u2DelayCellOfst[9]=3 cells (1 PI)
8491 06:02:55.981758 u2DelayCellOfst[10]=13 cells (4 PI)
8492 06:02:55.985114 u2DelayCellOfst[11]=3 cells (1 PI)
8493 06:02:55.988648 u2DelayCellOfst[12]=16 cells (5 PI)
8494 06:02:55.991769 u2DelayCellOfst[13]=16 cells (5 PI)
8495 06:02:55.995100 u2DelayCellOfst[14]=20 cells (6 PI)
8496 06:02:55.998308 u2DelayCellOfst[15]=16 cells (5 PI)
8497 06:02:56.005006 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8498 06:02:56.008199 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8499 06:02:56.008282 DramC Write-DBI on
8500 06:02:56.008348 ==
8501 06:02:56.012004 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 06:02:56.018116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 06:02:56.018199 ==
8504 06:02:56.018264
8505 06:02:56.018325
8506 06:02:56.018384 TX Vref Scan disable
8507 06:02:56.022407 == TX Byte 0 ==
8508 06:02:56.025773 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8509 06:02:56.029035 == TX Byte 1 ==
8510 06:02:56.032378 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8511 06:02:56.032461 DramC Write-DBI off
8512 06:02:56.035442
8513 06:02:56.035523 [DATLAT]
8514 06:02:56.035589 Freq=1600, CH1 RK0
8515 06:02:56.035650
8516 06:02:56.038887 DATLAT Default: 0xf
8517 06:02:56.038969 0, 0xFFFF, sum = 0
8518 06:02:56.042445 1, 0xFFFF, sum = 0
8519 06:02:56.042529 2, 0xFFFF, sum = 0
8520 06:02:56.045813 3, 0xFFFF, sum = 0
8521 06:02:56.049069 4, 0xFFFF, sum = 0
8522 06:02:56.049153 5, 0xFFFF, sum = 0
8523 06:02:56.052245 6, 0xFFFF, sum = 0
8524 06:02:56.052367 7, 0xFFFF, sum = 0
8525 06:02:56.055852 8, 0xFFFF, sum = 0
8526 06:02:56.055965 9, 0xFFFF, sum = 0
8527 06:02:56.058921 10, 0xFFFF, sum = 0
8528 06:02:56.059003 11, 0xFFFF, sum = 0
8529 06:02:56.062177 12, 0xFFFF, sum = 0
8530 06:02:56.062251 13, 0xFFFF, sum = 0
8531 06:02:56.065482 14, 0x0, sum = 1
8532 06:02:56.065588 15, 0x0, sum = 2
8533 06:02:56.068699 16, 0x0, sum = 3
8534 06:02:56.068799 17, 0x0, sum = 4
8535 06:02:56.072028 best_step = 15
8536 06:02:56.072134
8537 06:02:56.072224 ==
8538 06:02:56.075379 Dram Type= 6, Freq= 0, CH_1, rank 0
8539 06:02:56.079022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8540 06:02:56.079127 ==
8541 06:02:56.081919 RX Vref Scan: 1
8542 06:02:56.082026
8543 06:02:56.082116 Set Vref Range= 24 -> 127
8544 06:02:56.082208
8545 06:02:56.085553 RX Vref 24 -> 127, step: 1
8546 06:02:56.085626
8547 06:02:56.088937 RX Delay 19 -> 252, step: 4
8548 06:02:56.089015
8549 06:02:56.091914 Set Vref, RX VrefLevel [Byte0]: 24
8550 06:02:56.095462 [Byte1]: 24
8551 06:02:56.095549
8552 06:02:56.098714 Set Vref, RX VrefLevel [Byte0]: 25
8553 06:02:56.102307 [Byte1]: 25
8554 06:02:56.102392
8555 06:02:56.105444 Set Vref, RX VrefLevel [Byte0]: 26
8556 06:02:56.108841 [Byte1]: 26
8557 06:02:56.114675
8558 06:02:56.114752 Set Vref, RX VrefLevel [Byte0]: 27
8559 06:02:56.115854 [Byte1]: 27
8560 06:02:56.120248
8561 06:02:56.120330 Set Vref, RX VrefLevel [Byte0]: 28
8562 06:02:56.123647 [Byte1]: 28
8563 06:02:56.127766
8564 06:02:56.127849 Set Vref, RX VrefLevel [Byte0]: 29
8565 06:02:56.134367 [Byte1]: 29
8566 06:02:56.134450
8567 06:02:56.137683 Set Vref, RX VrefLevel [Byte0]: 30
8568 06:02:56.140991 [Byte1]: 30
8569 06:02:56.141074
8570 06:02:56.144480 Set Vref, RX VrefLevel [Byte0]: 31
8571 06:02:56.147895 [Byte1]: 31
8572 06:02:56.147979
8573 06:02:56.150938 Set Vref, RX VrefLevel [Byte0]: 32
8574 06:02:56.154438 [Byte1]: 32
8575 06:02:56.157935
8576 06:02:56.158041 Set Vref, RX VrefLevel [Byte0]: 33
8577 06:02:56.161475 [Byte1]: 33
8578 06:02:56.165835
8579 06:02:56.165971 Set Vref, RX VrefLevel [Byte0]: 34
8580 06:02:56.169136 [Byte1]: 34
8581 06:02:56.173305
8582 06:02:56.173389 Set Vref, RX VrefLevel [Byte0]: 35
8583 06:02:56.176482 [Byte1]: 35
8584 06:02:56.180870
8585 06:02:56.180954 Set Vref, RX VrefLevel [Byte0]: 36
8586 06:02:56.184288 [Byte1]: 36
8587 06:02:56.188333
8588 06:02:56.188417 Set Vref, RX VrefLevel [Byte0]: 37
8589 06:02:56.191532 [Byte1]: 37
8590 06:02:56.195897
8591 06:02:56.195980 Set Vref, RX VrefLevel [Byte0]: 38
8592 06:02:56.199399 [Byte1]: 38
8593 06:02:56.203881
8594 06:02:56.203964 Set Vref, RX VrefLevel [Byte0]: 39
8595 06:02:56.207209 [Byte1]: 39
8596 06:02:56.210898
8597 06:02:56.210982 Set Vref, RX VrefLevel [Byte0]: 40
8598 06:02:56.214533 [Byte1]: 40
8599 06:02:56.218802
8600 06:02:56.218885 Set Vref, RX VrefLevel [Byte0]: 41
8601 06:02:56.222121 [Byte1]: 41
8602 06:02:56.226084
8603 06:02:56.226168 Set Vref, RX VrefLevel [Byte0]: 42
8604 06:02:56.229724 [Byte1]: 42
8605 06:02:56.233733
8606 06:02:56.233817 Set Vref, RX VrefLevel [Byte0]: 43
8607 06:02:56.237033 [Byte1]: 43
8608 06:02:56.241777
8609 06:02:56.241861 Set Vref, RX VrefLevel [Byte0]: 44
8610 06:02:56.244873 [Byte1]: 44
8611 06:02:56.248969
8612 06:02:56.249053 Set Vref, RX VrefLevel [Byte0]: 45
8613 06:02:56.252218 [Byte1]: 45
8614 06:02:56.256657
8615 06:02:56.256741 Set Vref, RX VrefLevel [Byte0]: 46
8616 06:02:56.259709 [Byte1]: 46
8617 06:02:56.264219
8618 06:02:56.264302 Set Vref, RX VrefLevel [Byte0]: 47
8619 06:02:56.267612 [Byte1]: 47
8620 06:02:56.271639
8621 06:02:56.271722 Set Vref, RX VrefLevel [Byte0]: 48
8622 06:02:56.274844 [Byte1]: 48
8623 06:02:56.279415
8624 06:02:56.279505 Set Vref, RX VrefLevel [Byte0]: 49
8625 06:02:56.282572 [Byte1]: 49
8626 06:02:56.286782
8627 06:02:56.286866 Set Vref, RX VrefLevel [Byte0]: 50
8628 06:02:56.290144 [Byte1]: 50
8629 06:02:56.294490
8630 06:02:56.294573 Set Vref, RX VrefLevel [Byte0]: 51
8631 06:02:56.297983 [Byte1]: 51
8632 06:02:56.301962
8633 06:02:56.302060 Set Vref, RX VrefLevel [Byte0]: 52
8634 06:02:56.305408 [Byte1]: 52
8635 06:02:56.309543
8636 06:02:56.309652 Set Vref, RX VrefLevel [Byte0]: 53
8637 06:02:56.312967 [Byte1]: 53
8638 06:02:56.317143
8639 06:02:56.317254 Set Vref, RX VrefLevel [Byte0]: 54
8640 06:02:56.320487 [Byte1]: 54
8641 06:02:56.324479
8642 06:02:56.324585 Set Vref, RX VrefLevel [Byte0]: 55
8643 06:02:56.328087 [Byte1]: 55
8644 06:02:56.332450
8645 06:02:56.332549 Set Vref, RX VrefLevel [Byte0]: 56
8646 06:02:56.335423 [Byte1]: 56
8647 06:02:56.339833
8648 06:02:56.339904 Set Vref, RX VrefLevel [Byte0]: 57
8649 06:02:56.342891 [Byte1]: 57
8650 06:02:56.347148
8651 06:02:56.347220 Set Vref, RX VrefLevel [Byte0]: 58
8652 06:02:56.350933 [Byte1]: 58
8653 06:02:56.354887
8654 06:02:56.354986 Set Vref, RX VrefLevel [Byte0]: 59
8655 06:02:56.358453 [Byte1]: 59
8656 06:02:56.362380
8657 06:02:56.362455 Set Vref, RX VrefLevel [Byte0]: 60
8658 06:02:56.365673 [Byte1]: 60
8659 06:02:56.370048
8660 06:02:56.370122 Set Vref, RX VrefLevel [Byte0]: 61
8661 06:02:56.373144 [Byte1]: 61
8662 06:02:56.377864
8663 06:02:56.377998 Set Vref, RX VrefLevel [Byte0]: 62
8664 06:02:56.381173 [Byte1]: 62
8665 06:02:56.385203
8666 06:02:56.385277 Set Vref, RX VrefLevel [Byte0]: 63
8667 06:02:56.388580 [Byte1]: 63
8668 06:02:56.392874
8669 06:02:56.392971 Set Vref, RX VrefLevel [Byte0]: 64
8670 06:02:56.396622 [Byte1]: 64
8671 06:02:56.400365
8672 06:02:56.400479 Set Vref, RX VrefLevel [Byte0]: 65
8673 06:02:56.403460 [Byte1]: 65
8674 06:02:56.407747
8675 06:02:56.407816 Set Vref, RX VrefLevel [Byte0]: 66
8676 06:02:56.411184 [Byte1]: 66
8677 06:02:56.415521
8678 06:02:56.415601 Set Vref, RX VrefLevel [Byte0]: 67
8679 06:02:56.418657 [Byte1]: 67
8680 06:02:56.423126
8681 06:02:56.423204 Set Vref, RX VrefLevel [Byte0]: 68
8682 06:02:56.426176 [Byte1]: 68
8683 06:02:56.430646
8684 06:02:56.430715 Set Vref, RX VrefLevel [Byte0]: 69
8685 06:02:56.433911 [Byte1]: 69
8686 06:02:56.438145
8687 06:02:56.438213 Set Vref, RX VrefLevel [Byte0]: 70
8688 06:02:56.441442 [Byte1]: 70
8689 06:02:56.445832
8690 06:02:56.445929 Set Vref, RX VrefLevel [Byte0]: 71
8691 06:02:56.449293 [Byte1]: 71
8692 06:02:56.453433
8693 06:02:56.453528 Set Vref, RX VrefLevel [Byte0]: 72
8694 06:02:56.456388 [Byte1]: 72
8695 06:02:56.461183
8696 06:02:56.461281 Set Vref, RX VrefLevel [Byte0]: 73
8697 06:02:56.464371 [Byte1]: 73
8698 06:02:56.468230
8699 06:02:56.468301 Final RX Vref Byte 0 = 57 to rank0
8700 06:02:56.471850 Final RX Vref Byte 1 = 57 to rank0
8701 06:02:56.475320 Final RX Vref Byte 0 = 57 to rank1
8702 06:02:56.478909 Final RX Vref Byte 1 = 57 to rank1==
8703 06:02:56.481712 Dram Type= 6, Freq= 0, CH_1, rank 0
8704 06:02:56.488248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8705 06:02:56.488334 ==
8706 06:02:56.488397 DQS Delay:
8707 06:02:56.488456 DQS0 = 0, DQS1 = 0
8708 06:02:56.492493 DQM Delay:
8709 06:02:56.492587 DQM0 = 133, DQM1 = 128
8710 06:02:56.494897 DQ Delay:
8711 06:02:56.498290 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8712 06:02:56.501668 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8713 06:02:56.505003 DQ8 =116, DQ9 =116, DQ10 =132, DQ11 =122
8714 06:02:56.508519 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =136
8715 06:02:56.508604
8716 06:02:56.508670
8717 06:02:56.508732
8718 06:02:56.511447 [DramC_TX_OE_Calibration] TA2
8719 06:02:56.514935 Original DQ_B0 (3 6) =30, OEN = 27
8720 06:02:56.518262 Original DQ_B1 (3 6) =30, OEN = 27
8721 06:02:56.521788 24, 0x0, End_B0=24 End_B1=24
8722 06:02:56.521874 25, 0x0, End_B0=25 End_B1=25
8723 06:02:56.525080 26, 0x0, End_B0=26 End_B1=26
8724 06:02:56.528316 27, 0x0, End_B0=27 End_B1=27
8725 06:02:56.531507 28, 0x0, End_B0=28 End_B1=28
8726 06:02:56.531600 29, 0x0, End_B0=29 End_B1=29
8727 06:02:56.534930 30, 0x0, End_B0=30 End_B1=30
8728 06:02:56.538157 31, 0x4545, End_B0=30 End_B1=30
8729 06:02:56.541558 Byte0 end_step=30 best_step=27
8730 06:02:56.544986 Byte1 end_step=30 best_step=27
8731 06:02:56.548445 Byte0 TX OE(2T, 0.5T) = (3, 3)
8732 06:02:56.548530 Byte1 TX OE(2T, 0.5T) = (3, 3)
8733 06:02:56.551897
8734 06:02:56.551980
8735 06:02:56.558345 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8736 06:02:56.561462 CH1 RK0: MR19=303, MR18=1826
8737 06:02:56.568312 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8738 06:02:56.568397
8739 06:02:56.571748 ----->DramcWriteLeveling(PI) begin...
8740 06:02:56.571833 ==
8741 06:02:56.574910 Dram Type= 6, Freq= 0, CH_1, rank 1
8742 06:02:56.578224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 06:02:56.578309 ==
8744 06:02:56.581410 Write leveling (Byte 0): 23 => 23
8745 06:02:56.584884 Write leveling (Byte 1): 29 => 29
8746 06:02:56.587986 DramcWriteLeveling(PI) end<-----
8747 06:02:56.588070
8748 06:02:56.588136 ==
8749 06:02:56.591536 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 06:02:56.594931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 06:02:56.595016 ==
8752 06:02:56.598578 [Gating] SW mode calibration
8753 06:02:56.604730 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8754 06:02:56.611530 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8755 06:02:56.614882 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 06:02:56.617908 1 4 4 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
8757 06:02:56.624450 1 4 8 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8758 06:02:56.627963 1 4 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8759 06:02:56.631292 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 06:02:56.637837 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 06:02:56.641122 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 06:02:56.644479 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 06:02:56.651364 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 06:02:56.654650 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8765 06:02:56.657687 1 5 8 | B1->B0 | 2727 3434 | 0 1 | (1 0) (1 0)
8766 06:02:56.664490 1 5 12 | B1->B0 | 2323 3232 | 0 0 | (1 0) (0 1)
8767 06:02:56.667726 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 06:02:56.671096 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 06:02:56.678059 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 06:02:56.681220 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 06:02:56.684531 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 06:02:56.690975 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 06:02:56.694451 1 6 8 | B1->B0 | 4444 2828 | 0 0 | (0 0) (0 0)
8774 06:02:56.697808 1 6 12 | B1->B0 | 4646 4241 | 0 1 | (0 0) (0 0)
8775 06:02:56.704735 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 06:02:56.707483 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 06:02:56.710971 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 06:02:56.717623 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 06:02:56.720820 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 06:02:56.724621 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 06:02:56.730620 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8782 06:02:56.734434 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8783 06:02:56.737239 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8784 06:02:56.740848 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 06:02:56.747372 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 06:02:56.750784 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 06:02:56.753972 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 06:02:56.760760 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 06:02:56.763865 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 06:02:56.767387 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 06:02:56.773847 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 06:02:56.777417 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 06:02:56.780642 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 06:02:56.786911 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 06:02:56.790267 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 06:02:56.793865 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 06:02:56.800206 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8798 06:02:56.803467 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 06:02:56.806758 Total UI for P1: 0, mck2ui 16
8800 06:02:56.810417 best dqsien dly found for B0: ( 1, 9, 8)
8801 06:02:56.813577 Total UI for P1: 0, mck2ui 16
8802 06:02:56.817140 best dqsien dly found for B1: ( 1, 9, 8)
8803 06:02:56.820118 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8804 06:02:56.823441 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8805 06:02:56.823525
8806 06:02:56.826824 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8807 06:02:56.829931 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8808 06:02:56.833618 [Gating] SW calibration Done
8809 06:02:56.833703 ==
8810 06:02:56.836815 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 06:02:56.843306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 06:02:56.843390 ==
8813 06:02:56.843456 RX Vref Scan: 0
8814 06:02:56.843517
8815 06:02:56.846698 RX Vref 0 -> 0, step: 1
8816 06:02:56.846780
8817 06:02:56.850151 RX Delay 0 -> 252, step: 8
8818 06:02:56.853229 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8819 06:02:56.856961 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8820 06:02:56.860084 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8821 06:02:56.863178 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8822 06:02:56.870257 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8823 06:02:56.873423 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8824 06:02:56.876858 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8825 06:02:56.880332 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8826 06:02:56.883317 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8827 06:02:56.886535 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8828 06:02:56.893099 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8829 06:02:56.896756 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8830 06:02:56.899647 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8831 06:02:56.903145 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8832 06:02:56.909823 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8833 06:02:56.913349 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8834 06:02:56.913432 ==
8835 06:02:56.916549 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 06:02:56.919600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 06:02:56.919684 ==
8838 06:02:56.919750 DQS Delay:
8839 06:02:56.922923 DQS0 = 0, DQS1 = 0
8840 06:02:56.923005 DQM Delay:
8841 06:02:56.926324 DQM0 = 137, DQM1 = 131
8842 06:02:56.926406 DQ Delay:
8843 06:02:56.929771 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8844 06:02:56.933049 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8845 06:02:56.936349 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =127
8846 06:02:56.943062 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8847 06:02:56.943144
8848 06:02:56.943209
8849 06:02:56.943269 ==
8850 06:02:56.946223 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 06:02:56.949990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 06:02:56.950073 ==
8853 06:02:56.950144
8854 06:02:56.950206
8855 06:02:56.952943 TX Vref Scan disable
8856 06:02:56.953025 == TX Byte 0 ==
8857 06:02:56.959451 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8858 06:02:56.962915 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8859 06:02:56.962998 == TX Byte 1 ==
8860 06:02:56.969482 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8861 06:02:56.972953 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8862 06:02:56.973035 ==
8863 06:02:56.976368 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 06:02:56.979665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 06:02:56.979748 ==
8866 06:02:56.994594
8867 06:02:56.998148 TX Vref early break, caculate TX vref
8868 06:02:57.001328 TX Vref=16, minBit 9, minWin=22, winSum=379
8869 06:02:57.004496 TX Vref=18, minBit 8, minWin=23, winSum=388
8870 06:02:57.007926 TX Vref=20, minBit 9, minWin=23, winSum=395
8871 06:02:57.011384 TX Vref=22, minBit 9, minWin=23, winSum=403
8872 06:02:57.014754 TX Vref=24, minBit 8, minWin=24, winSum=409
8873 06:02:57.021388 TX Vref=26, minBit 8, minWin=25, winSum=417
8874 06:02:57.024563 TX Vref=28, minBit 9, minWin=24, winSum=416
8875 06:02:57.028069 TX Vref=30, minBit 0, minWin=25, winSum=414
8876 06:02:57.031062 TX Vref=32, minBit 8, minWin=24, winSum=403
8877 06:02:57.034425 TX Vref=34, minBit 9, minWin=23, winSum=397
8878 06:02:57.038235 TX Vref=36, minBit 8, minWin=23, winSum=391
8879 06:02:57.044897 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 26
8880 06:02:57.044981
8881 06:02:57.047983 Final TX Range 0 Vref 26
8882 06:02:57.048066
8883 06:02:57.048132 ==
8884 06:02:57.051336 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 06:02:57.054204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 06:02:57.054313 ==
8887 06:02:57.054392
8888 06:02:57.054454
8889 06:02:57.057806 TX Vref Scan disable
8890 06:02:57.064227 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8891 06:02:57.064313 == TX Byte 0 ==
8892 06:02:57.067504 u2DelayCellOfst[0]=16 cells (5 PI)
8893 06:02:57.070733 u2DelayCellOfst[1]=10 cells (3 PI)
8894 06:02:57.074339 u2DelayCellOfst[2]=0 cells (0 PI)
8895 06:02:57.077297 u2DelayCellOfst[3]=3 cells (1 PI)
8896 06:02:57.080873 u2DelayCellOfst[4]=6 cells (2 PI)
8897 06:02:57.084136 u2DelayCellOfst[5]=16 cells (5 PI)
8898 06:02:57.087396 u2DelayCellOfst[6]=16 cells (5 PI)
8899 06:02:57.090821 u2DelayCellOfst[7]=3 cells (1 PI)
8900 06:02:57.093927 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8901 06:02:57.097215 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8902 06:02:57.100801 == TX Byte 1 ==
8903 06:02:57.103857 u2DelayCellOfst[8]=0 cells (0 PI)
8904 06:02:57.107398 u2DelayCellOfst[9]=3 cells (1 PI)
8905 06:02:57.107480 u2DelayCellOfst[10]=6 cells (2 PI)
8906 06:02:57.111069 u2DelayCellOfst[11]=3 cells (1 PI)
8907 06:02:57.113936 u2DelayCellOfst[12]=10 cells (3 PI)
8908 06:02:57.117210 u2DelayCellOfst[13]=13 cells (4 PI)
8909 06:02:57.120459 u2DelayCellOfst[14]=16 cells (5 PI)
8910 06:02:57.124069 u2DelayCellOfst[15]=16 cells (5 PI)
8911 06:02:57.130559 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8912 06:02:57.133907 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8913 06:02:57.134029 DramC Write-DBI on
8914 06:02:57.134095 ==
8915 06:02:57.136979 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 06:02:57.143867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 06:02:57.143951 ==
8918 06:02:57.144017
8919 06:02:57.144078
8920 06:02:57.144135 TX Vref Scan disable
8921 06:02:57.147888 == TX Byte 0 ==
8922 06:02:57.151205 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8923 06:02:57.154801 == TX Byte 1 ==
8924 06:02:57.157665 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8925 06:02:57.160899 DramC Write-DBI off
8926 06:02:57.160981
8927 06:02:57.161047 [DATLAT]
8928 06:02:57.161108 Freq=1600, CH1 RK1
8929 06:02:57.161167
8930 06:02:57.164371 DATLAT Default: 0xf
8931 06:02:57.164479 0, 0xFFFF, sum = 0
8932 06:02:57.167594 1, 0xFFFF, sum = 0
8933 06:02:57.170836 2, 0xFFFF, sum = 0
8934 06:02:57.170921 3, 0xFFFF, sum = 0
8935 06:02:57.174149 4, 0xFFFF, sum = 0
8936 06:02:57.174233 5, 0xFFFF, sum = 0
8937 06:02:57.177649 6, 0xFFFF, sum = 0
8938 06:02:57.177733 7, 0xFFFF, sum = 0
8939 06:02:57.180750 8, 0xFFFF, sum = 0
8940 06:02:57.180833 9, 0xFFFF, sum = 0
8941 06:02:57.183996 10, 0xFFFF, sum = 0
8942 06:02:57.184079 11, 0xFFFF, sum = 0
8943 06:02:57.187790 12, 0xFFFF, sum = 0
8944 06:02:57.187873 13, 0xFFFF, sum = 0
8945 06:02:57.191049 14, 0x0, sum = 1
8946 06:02:57.191133 15, 0x0, sum = 2
8947 06:02:57.194405 16, 0x0, sum = 3
8948 06:02:57.194489 17, 0x0, sum = 4
8949 06:02:57.197402 best_step = 15
8950 06:02:57.197484
8951 06:02:57.197548 ==
8952 06:02:57.200986 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 06:02:57.204114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 06:02:57.204197 ==
8955 06:02:57.207707 RX Vref Scan: 0
8956 06:02:57.207790
8957 06:02:57.207855 RX Vref 0 -> 0, step: 1
8958 06:02:57.207916
8959 06:02:57.210990 RX Delay 19 -> 252, step: 4
8960 06:02:57.213891 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8961 06:02:57.220582 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8962 06:02:57.224265 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8963 06:02:57.227361 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8964 06:02:57.230634 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8965 06:02:57.234027 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8966 06:02:57.237033 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8967 06:02:57.244024 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8968 06:02:57.247384 iDelay=195, Bit 8, Center 114 (63 ~ 166) 104
8969 06:02:57.250828 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8970 06:02:57.253686 iDelay=195, Bit 10, Center 128 (79 ~ 178) 100
8971 06:02:57.257266 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8972 06:02:57.263889 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8973 06:02:57.267027 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
8974 06:02:57.270408 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8975 06:02:57.273745 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8976 06:02:57.273828 ==
8977 06:02:57.277362 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 06:02:57.283870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 06:02:57.283954 ==
8980 06:02:57.284019 DQS Delay:
8981 06:02:57.287009 DQS0 = 0, DQS1 = 0
8982 06:02:57.287092 DQM Delay:
8983 06:02:57.290314 DQM0 = 133, DQM1 = 129
8984 06:02:57.290396 DQ Delay:
8985 06:02:57.293732 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8986 06:02:57.296824 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
8987 06:02:57.300406 DQ8 =114, DQ9 =120, DQ10 =128, DQ11 =126
8988 06:02:57.303574 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =140
8989 06:02:57.303656
8990 06:02:57.303721
8991 06:02:57.303782
8992 06:02:57.306953 [DramC_TX_OE_Calibration] TA2
8993 06:02:57.310453 Original DQ_B0 (3 6) =30, OEN = 27
8994 06:02:57.313829 Original DQ_B1 (3 6) =30, OEN = 27
8995 06:02:57.316876 24, 0x0, End_B0=24 End_B1=24
8996 06:02:57.320256 25, 0x0, End_B0=25 End_B1=25
8997 06:02:57.320340 26, 0x0, End_B0=26 End_B1=26
8998 06:02:57.323641 27, 0x0, End_B0=27 End_B1=27
8999 06:02:57.327021 28, 0x0, End_B0=28 End_B1=28
9000 06:02:57.330254 29, 0x0, End_B0=29 End_B1=29
9001 06:02:57.330339 30, 0x0, End_B0=30 End_B1=30
9002 06:02:57.333405 31, 0x4141, End_B0=30 End_B1=30
9003 06:02:57.336677 Byte0 end_step=30 best_step=27
9004 06:02:57.340326 Byte1 end_step=30 best_step=27
9005 06:02:57.343400 Byte0 TX OE(2T, 0.5T) = (3, 3)
9006 06:02:57.346645 Byte1 TX OE(2T, 0.5T) = (3, 3)
9007 06:02:57.346727
9008 06:02:57.346792
9009 06:02:57.353477 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 395 ps
9010 06:02:57.356505 CH1 RK1: MR19=303, MR18=1D08
9011 06:02:57.363202 CH1_RK1: MR19=0x303, MR18=0x1D08, DQSOSC=395, MR23=63, INC=23, DEC=15
9012 06:02:57.366658 [RxdqsGatingPostProcess] freq 1600
9013 06:02:57.370246 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9014 06:02:57.373701 best DQS0 dly(2T, 0.5T) = (1, 1)
9015 06:02:57.376448 best DQS1 dly(2T, 0.5T) = (1, 1)
9016 06:02:57.379968 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9017 06:02:57.383300 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9018 06:02:57.386575 best DQS0 dly(2T, 0.5T) = (1, 1)
9019 06:02:57.390070 best DQS1 dly(2T, 0.5T) = (1, 1)
9020 06:02:57.393432 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9021 06:02:57.396482 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9022 06:02:57.399738 Pre-setting of DQS Precalculation
9023 06:02:57.403004 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9024 06:02:57.409918 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9025 06:02:57.419892 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9026 06:02:57.419997
9027 06:02:57.420092
9028 06:02:57.423087 [Calibration Summary] 3200 Mbps
9029 06:02:57.423195 CH 0, Rank 0
9030 06:02:57.426719 SW Impedance : PASS
9031 06:02:57.426798 DUTY Scan : NO K
9032 06:02:57.429989 ZQ Calibration : PASS
9033 06:02:57.430092 Jitter Meter : NO K
9034 06:02:57.432952 CBT Training : PASS
9035 06:02:57.436750 Write leveling : PASS
9036 06:02:57.436853 RX DQS gating : PASS
9037 06:02:57.439877 RX DQ/DQS(RDDQC) : PASS
9038 06:02:57.443111 TX DQ/DQS : PASS
9039 06:02:57.443191 RX DATLAT : PASS
9040 06:02:57.446367 RX DQ/DQS(Engine): PASS
9041 06:02:57.450007 TX OE : PASS
9042 06:02:57.450089 All Pass.
9043 06:02:57.450153
9044 06:02:57.450212 CH 0, Rank 1
9045 06:02:57.453027 SW Impedance : PASS
9046 06:02:57.456462 DUTY Scan : NO K
9047 06:02:57.456538 ZQ Calibration : PASS
9048 06:02:57.459619 Jitter Meter : NO K
9049 06:02:57.462739 CBT Training : PASS
9050 06:02:57.462818 Write leveling : PASS
9051 06:02:57.466090 RX DQS gating : PASS
9052 06:02:57.469767 RX DQ/DQS(RDDQC) : PASS
9053 06:02:57.469870 TX DQ/DQS : PASS
9054 06:02:57.472686 RX DATLAT : PASS
9055 06:02:57.476537 RX DQ/DQS(Engine): PASS
9056 06:02:57.476641 TX OE : PASS
9057 06:02:57.476736 All Pass.
9058 06:02:57.479514
9059 06:02:57.479594 CH 1, Rank 0
9060 06:02:57.482849 SW Impedance : PASS
9061 06:02:57.482926 DUTY Scan : NO K
9062 06:02:57.486085 ZQ Calibration : PASS
9063 06:02:57.486190 Jitter Meter : NO K
9064 06:02:57.489516 CBT Training : PASS
9065 06:02:57.492630 Write leveling : PASS
9066 06:02:57.492707 RX DQS gating : PASS
9067 06:02:57.496125 RX DQ/DQS(RDDQC) : PASS
9068 06:02:57.499221 TX DQ/DQS : PASS
9069 06:02:57.499324 RX DATLAT : PASS
9070 06:02:57.502753 RX DQ/DQS(Engine): PASS
9071 06:02:57.506238 TX OE : PASS
9072 06:02:57.506340 All Pass.
9073 06:02:57.506432
9074 06:02:57.506522 CH 1, Rank 1
9075 06:02:57.509240 SW Impedance : PASS
9076 06:02:57.512942 DUTY Scan : NO K
9077 06:02:57.513045 ZQ Calibration : PASS
9078 06:02:57.516382 Jitter Meter : NO K
9079 06:02:57.519290 CBT Training : PASS
9080 06:02:57.519365 Write leveling : PASS
9081 06:02:57.522502 RX DQS gating : PASS
9082 06:02:57.525854 RX DQ/DQS(RDDQC) : PASS
9083 06:02:57.525964 TX DQ/DQS : PASS
9084 06:02:57.529169 RX DATLAT : PASS
9085 06:02:57.532505 RX DQ/DQS(Engine): PASS
9086 06:02:57.532613 TX OE : PASS
9087 06:02:57.532706 All Pass.
9088 06:02:57.536374
9089 06:02:57.536475 DramC Write-DBI on
9090 06:02:57.539353 PER_BANK_REFRESH: Hybrid Mode
9091 06:02:57.539429 TX_TRACKING: ON
9092 06:02:57.548895 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9093 06:02:57.555899 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9094 06:02:57.565656 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9095 06:02:57.568895 [FAST_K] Save calibration result to emmc
9096 06:02:57.572366 sync common calibartion params.
9097 06:02:57.572445 sync cbt_mode0:1, 1:1
9098 06:02:57.575424 dram_init: ddr_geometry: 2
9099 06:02:57.579015 dram_init: ddr_geometry: 2
9100 06:02:57.579122 dram_init: ddr_geometry: 2
9101 06:02:57.582366 0:dram_rank_size:100000000
9102 06:02:57.585452 1:dram_rank_size:100000000
9103 06:02:57.589069 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9104 06:02:57.592235 DFS_SHUFFLE_HW_MODE: ON
9105 06:02:57.595567 dramc_set_vcore_voltage set vcore to 725000
9106 06:02:57.599041 Read voltage for 1600, 0
9107 06:02:57.599117 Vio18 = 0
9108 06:02:57.602226 Vcore = 725000
9109 06:02:57.602326 Vdram = 0
9110 06:02:57.602418 Vddq = 0
9111 06:02:57.602506 Vmddr = 0
9112 06:02:57.605517 switch to 3200 Mbps bootup
9113 06:02:57.608943 [DramcRunTimeConfig]
9114 06:02:57.609046 PHYPLL
9115 06:02:57.612117 DPM_CONTROL_AFTERK: ON
9116 06:02:57.612195 PER_BANK_REFRESH: ON
9117 06:02:57.615844 REFRESH_OVERHEAD_REDUCTION: ON
9118 06:02:57.619286 CMD_PICG_NEW_MODE: OFF
9119 06:02:57.619362 XRTWTW_NEW_MODE: ON
9120 06:02:57.622612 XRTRTR_NEW_MODE: ON
9121 06:02:57.622690 TX_TRACKING: ON
9122 06:02:57.625844 RDSEL_TRACKING: OFF
9123 06:02:57.629363 DQS Precalculation for DVFS: ON
9124 06:02:57.629468 RX_TRACKING: OFF
9125 06:02:57.629561 HW_GATING DBG: ON
9126 06:02:57.632095 ZQCS_ENABLE_LP4: ON
9127 06:02:57.635759 RX_PICG_NEW_MODE: ON
9128 06:02:57.635863 TX_PICG_NEW_MODE: ON
9129 06:02:57.638680 ENABLE_RX_DCM_DPHY: ON
9130 06:02:57.642393 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9131 06:02:57.642472 DUMMY_READ_FOR_TRACKING: OFF
9132 06:02:57.645581 !!! SPM_CONTROL_AFTERK: OFF
9133 06:02:57.648834 !!! SPM could not control APHY
9134 06:02:57.652472 IMPEDANCE_TRACKING: ON
9135 06:02:57.652574 TEMP_SENSOR: ON
9136 06:02:57.655687 HW_SAVE_FOR_SR: OFF
9137 06:02:57.658965 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9138 06:02:57.662438 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9139 06:02:57.662515 Read ODT Tracking: ON
9140 06:02:57.665565 Refresh Rate DeBounce: ON
9141 06:02:57.669120 DFS_NO_QUEUE_FLUSH: ON
9142 06:02:57.672223 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9143 06:02:57.672325 ENABLE_DFS_RUNTIME_MRW: OFF
9144 06:02:57.675383 DDR_RESERVE_NEW_MODE: ON
9145 06:02:57.678680 MR_CBT_SWITCH_FREQ: ON
9146 06:02:57.678784 =========================
9147 06:02:57.698805 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9148 06:02:57.701904 dram_init: ddr_geometry: 2
9149 06:02:57.720217 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9150 06:02:57.723514 dram_init: dram init end (result: 0)
9151 06:02:57.730379 DRAM-K: Full calibration passed in 24503 msecs
9152 06:02:57.733691 MRC: failed to locate region type 0.
9153 06:02:57.733795 DRAM rank0 size:0x100000000,
9154 06:02:57.736893 DRAM rank1 size=0x100000000
9155 06:02:57.746616 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9156 06:02:57.753562 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9157 06:02:57.759775 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9158 06:02:57.766835 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9159 06:02:57.769852 DRAM rank0 size:0x100000000,
9160 06:02:57.772933 DRAM rank1 size=0x100000000
9161 06:02:57.773017 CBMEM:
9162 06:02:57.776755 IMD: root @ 0xfffff000 254 entries.
9163 06:02:57.779926 IMD: root @ 0xffffec00 62 entries.
9164 06:02:57.783225 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9165 06:02:57.789649 WARNING: RO_VPD is uninitialized or empty.
9166 06:02:57.793004 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9167 06:02:57.800303 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9168 06:02:57.813105 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9169 06:02:57.824626 BS: romstage times (exec / console): total (unknown) / 24000 ms
9170 06:02:57.824704
9171 06:02:57.824771
9172 06:02:57.834352 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9173 06:02:57.837837 ARM64: Exception handlers installed.
9174 06:02:57.841049 ARM64: Testing exception
9175 06:02:57.844132 ARM64: Done test exception
9176 06:02:57.844230 Enumerating buses...
9177 06:02:57.847533 Show all devs... Before device enumeration.
9178 06:02:57.850700 Root Device: enabled 1
9179 06:02:57.854276 CPU_CLUSTER: 0: enabled 1
9180 06:02:57.854372 CPU: 00: enabled 1
9181 06:02:57.857786 Compare with tree...
9182 06:02:57.857886 Root Device: enabled 1
9183 06:02:57.860984 CPU_CLUSTER: 0: enabled 1
9184 06:02:57.864382 CPU: 00: enabled 1
9185 06:02:57.864484 Root Device scanning...
9186 06:02:57.867715 scan_static_bus for Root Device
9187 06:02:57.871008 CPU_CLUSTER: 0 enabled
9188 06:02:57.874017 scan_static_bus for Root Device done
9189 06:02:57.877452 scan_bus: bus Root Device finished in 8 msecs
9190 06:02:57.877548 done
9191 06:02:57.883955 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9192 06:02:57.887225 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9193 06:02:57.893900 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9194 06:02:57.897198 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9195 06:02:57.900566 Allocating resources...
9196 06:02:57.904298 Reading resources...
9197 06:02:57.907229 Root Device read_resources bus 0 link: 0
9198 06:02:57.907301 DRAM rank0 size:0x100000000,
9199 06:02:57.910403 DRAM rank1 size=0x100000000
9200 06:02:57.914124 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9201 06:02:57.917213 CPU: 00 missing read_resources
9202 06:02:57.920481 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9203 06:02:57.927052 Root Device read_resources bus 0 link: 0 done
9204 06:02:57.927126 Done reading resources.
9205 06:02:57.933863 Show resources in subtree (Root Device)...After reading.
9206 06:02:57.937188 Root Device child on link 0 CPU_CLUSTER: 0
9207 06:02:57.940458 CPU_CLUSTER: 0 child on link 0 CPU: 00
9208 06:02:57.950693 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9209 06:02:57.950796 CPU: 00
9210 06:02:57.953973 Root Device assign_resources, bus 0 link: 0
9211 06:02:57.957097 CPU_CLUSTER: 0 missing set_resources
9212 06:02:57.963912 Root Device assign_resources, bus 0 link: 0 done
9213 06:02:57.964015 Done setting resources.
9214 06:02:57.970335 Show resources in subtree (Root Device)...After assigning values.
9215 06:02:57.973625 Root Device child on link 0 CPU_CLUSTER: 0
9216 06:02:57.977310 CPU_CLUSTER: 0 child on link 0 CPU: 00
9217 06:02:57.986978 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9218 06:02:57.987054 CPU: 00
9219 06:02:57.990676 Done allocating resources.
9220 06:02:57.993647 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9221 06:02:57.996860 Enabling resources...
9222 06:02:57.996956 done.
9223 06:02:58.003604 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9224 06:02:58.003702 Initializing devices...
9225 06:02:58.006966 Root Device init
9226 06:02:58.007046 init hardware done!
9227 06:02:58.010383 0x00000018: ctrlr->caps
9228 06:02:58.014162 52.000 MHz: ctrlr->f_max
9229 06:02:58.014236 0.400 MHz: ctrlr->f_min
9230 06:02:58.017026 0x40ff8080: ctrlr->voltages
9231 06:02:58.017129 sclk: 390625
9232 06:02:58.020458 Bus Width = 1
9233 06:02:58.020557 sclk: 390625
9234 06:02:58.023449 Bus Width = 1
9235 06:02:58.023552 Early init status = 3
9236 06:02:58.030355 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9237 06:02:58.033652 in-header: 03 fc 00 00 01 00 00 00
9238 06:02:58.033729 in-data: 00
9239 06:02:58.040316 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9240 06:02:58.043347 in-header: 03 fd 00 00 00 00 00 00
9241 06:02:58.046783 in-data:
9242 06:02:58.050305 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9243 06:02:58.053372 in-header: 03 fc 00 00 01 00 00 00
9244 06:02:58.056624 in-data: 00
9245 06:02:58.059957 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9246 06:02:58.065215 in-header: 03 fd 00 00 00 00 00 00
9247 06:02:58.068705 in-data:
9248 06:02:58.071725 [SSUSB] Setting up USB HOST controller...
9249 06:02:58.075314 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9250 06:02:58.078461 [SSUSB] phy power-on done.
9251 06:02:58.081720 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9252 06:02:58.088302 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9253 06:02:58.091610 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9254 06:02:58.098592 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9255 06:02:58.104740 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9256 06:02:58.111567 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9257 06:02:58.118094 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9258 06:02:58.124906 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9259 06:02:58.127983 SPM: binary array size = 0x9dc
9260 06:02:58.131729 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9261 06:02:58.138046 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9262 06:02:58.144806 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9263 06:02:58.148000 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9264 06:02:58.154532 configure_display: Starting display init
9265 06:02:58.188272 anx7625_power_on_init: Init interface.
9266 06:02:58.191692 anx7625_disable_pd_protocol: Disabled PD feature.
9267 06:02:58.194881 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9268 06:02:58.222806 anx7625_start_dp_work: Secure OCM version=00
9269 06:02:58.225854 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9270 06:02:58.240631 sp_tx_get_edid_block: EDID Block = 1
9271 06:02:58.343334 Extracted contents:
9272 06:02:58.346710 header: 00 ff ff ff ff ff ff 00
9273 06:02:58.349891 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9274 06:02:58.353192 version: 01 04
9275 06:02:58.356695 basic params: 95 1f 11 78 0a
9276 06:02:58.360099 chroma info: 76 90 94 55 54 90 27 21 50 54
9277 06:02:58.363464 established: 00 00 00
9278 06:02:58.370023 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9279 06:02:58.373261 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9280 06:02:58.380231 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9281 06:02:58.386607 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9282 06:02:58.393244 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9283 06:02:58.396377 extensions: 00
9284 06:02:58.396461 checksum: fb
9285 06:02:58.396527
9286 06:02:58.400061 Manufacturer: IVO Model 57d Serial Number 0
9287 06:02:58.403289 Made week 0 of 2020
9288 06:02:58.403372 EDID version: 1.4
9289 06:02:58.406624 Digital display
9290 06:02:58.410098 6 bits per primary color channel
9291 06:02:58.410183 DisplayPort interface
9292 06:02:58.413277 Maximum image size: 31 cm x 17 cm
9293 06:02:58.416274 Gamma: 220%
9294 06:02:58.416356 Check DPMS levels
9295 06:02:58.419814 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9296 06:02:58.423240 First detailed timing is preferred timing
9297 06:02:58.426379 Established timings supported:
9298 06:02:58.429862 Standard timings supported:
9299 06:02:58.429967 Detailed timings
9300 06:02:58.436403 Hex of detail: 383680a07038204018303c0035ae10000019
9301 06:02:58.439744 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9302 06:02:58.446654 0780 0798 07c8 0820 hborder 0
9303 06:02:58.449946 0438 043b 0447 0458 vborder 0
9304 06:02:58.453101 -hsync -vsync
9305 06:02:58.453182 Did detailed timing
9306 06:02:58.456831 Hex of detail: 000000000000000000000000000000000000
9307 06:02:58.459843 Manufacturer-specified data, tag 0
9308 06:02:58.466588 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9309 06:02:58.466670 ASCII string: InfoVision
9310 06:02:58.473452 Hex of detail: 000000fe00523134304e574635205248200a
9311 06:02:58.473535 ASCII string: R140NWF5 RH
9312 06:02:58.476430 Checksum
9313 06:02:58.476513 Checksum: 0xfb (valid)
9314 06:02:58.483362 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9315 06:02:58.486477 DSI data_rate: 832800000 bps
9316 06:02:58.490089 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9317 06:02:58.493007 anx7625_parse_edid: pixelclock(138800).
9318 06:02:58.500064 hactive(1920), hsync(48), hfp(24), hbp(88)
9319 06:02:58.503339 vactive(1080), vsync(12), vfp(3), vbp(17)
9320 06:02:58.506383 anx7625_dsi_config: config dsi.
9321 06:02:58.513136 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9322 06:02:58.525509 anx7625_dsi_config: success to config DSI
9323 06:02:58.529107 anx7625_dp_start: MIPI phy setup OK.
9324 06:02:58.532096 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9325 06:02:58.535614 mtk_ddp_mode_set invalid vrefresh 60
9326 06:02:58.539213 main_disp_path_setup
9327 06:02:58.539291 ovl_layer_smi_id_en
9328 06:02:58.542338 ovl_layer_smi_id_en
9329 06:02:58.542416 ccorr_config
9330 06:02:58.542479 aal_config
9331 06:02:58.545437 gamma_config
9332 06:02:58.545504 postmask_config
9333 06:02:58.548771 dither_config
9334 06:02:58.552123 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9335 06:02:58.558652 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9336 06:02:58.561914 Root Device init finished in 552 msecs
9337 06:02:58.562045 CPU_CLUSTER: 0 init
9338 06:02:58.572183 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9339 06:02:58.575507 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9340 06:02:58.578996 APU_MBOX 0x190000b0 = 0x10001
9341 06:02:58.582045 APU_MBOX 0x190001b0 = 0x10001
9342 06:02:58.585259 APU_MBOX 0x190005b0 = 0x10001
9343 06:02:58.588548 APU_MBOX 0x190006b0 = 0x10001
9344 06:02:58.591945 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9345 06:02:58.604437 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9346 06:02:58.616909 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9347 06:02:58.623692 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9348 06:02:58.635108 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9349 06:02:58.644461 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9350 06:02:58.647640 CPU_CLUSTER: 0 init finished in 81 msecs
9351 06:02:58.651121 Devices initialized
9352 06:02:58.654379 Show all devs... After init.
9353 06:02:58.654457 Root Device: enabled 1
9354 06:02:58.657702 CPU_CLUSTER: 0: enabled 1
9355 06:02:58.660923 CPU: 00: enabled 1
9356 06:02:58.664330 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9357 06:02:58.667737 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9358 06:02:58.670866 ELOG: NV offset 0x57f000 size 0x1000
9359 06:02:58.677743 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9360 06:02:58.683983 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9361 06:02:58.687525 ELOG: Event(17) added with size 13 at 2023-12-25 06:02:16 UTC
9362 06:02:58.690670 out: cmd=0x121: 03 db 21 01 00 00 00 00
9363 06:02:58.694748 in-header: 03 31 00 00 2c 00 00 00
9364 06:02:58.707797 in-data: 2e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9365 06:02:58.714451 ELOG: Event(A1) added with size 10 at 2023-12-25 06:02:16 UTC
9366 06:02:58.721246 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9367 06:02:58.727680 ELOG: Event(A0) added with size 9 at 2023-12-25 06:02:16 UTC
9368 06:02:58.731103 elog_add_boot_reason: Logged dev mode boot
9369 06:02:58.734400 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9370 06:02:58.737708 Finalize devices...
9371 06:02:58.737783 Devices finalized
9372 06:02:58.744703 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9373 06:02:58.747631 Writing coreboot table at 0xffe64000
9374 06:02:58.751699 0. 000000000010a000-0000000000113fff: RAMSTAGE
9375 06:02:58.754559 1. 0000000040000000-00000000400fffff: RAM
9376 06:02:58.757783 2. 0000000040100000-000000004032afff: RAMSTAGE
9377 06:02:58.764461 3. 000000004032b000-00000000545fffff: RAM
9378 06:02:58.767795 4. 0000000054600000-000000005465ffff: BL31
9379 06:02:58.770722 5. 0000000054660000-00000000ffe63fff: RAM
9380 06:02:58.777694 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9381 06:02:58.780788 7. 0000000100000000-000000023fffffff: RAM
9382 06:02:58.780870 Passing 5 GPIOs to payload:
9383 06:02:58.787771 NAME | PORT | POLARITY | VALUE
9384 06:02:58.791009 EC in RW | 0x000000aa | low | undefined
9385 06:02:58.797709 EC interrupt | 0x00000005 | low | undefined
9386 06:02:58.800898 TPM interrupt | 0x000000ab | high | undefined
9387 06:02:58.804109 SD card detect | 0x00000011 | high | undefined
9388 06:02:58.810731 speaker enable | 0x00000093 | high | undefined
9389 06:02:58.814110 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9390 06:02:58.817245 in-header: 03 f9 00 00 02 00 00 00
9391 06:02:58.817322 in-data: 02 00
9392 06:02:58.820903 ADC[4]: Raw value=901032 ID=7
9393 06:02:58.824097 ADC[3]: Raw value=213179 ID=1
9394 06:02:58.824175 RAM Code: 0x71
9395 06:02:58.827213 ADC[6]: Raw value=74502 ID=0
9396 06:02:58.831129 ADC[5]: Raw value=212072 ID=1
9397 06:02:58.831208 SKU Code: 0x1
9398 06:02:58.837596 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 584a
9399 06:02:58.840648 coreboot table: 964 bytes.
9400 06:02:58.843892 IMD ROOT 0. 0xfffff000 0x00001000
9401 06:02:58.847532 IMD SMALL 1. 0xffffe000 0x00001000
9402 06:02:58.850692 RO MCACHE 2. 0xffffc000 0x00001104
9403 06:02:58.854106 CONSOLE 3. 0xfff7c000 0x00080000
9404 06:02:58.857657 FMAP 4. 0xfff7b000 0x00000452
9405 06:02:58.860714 TIME STAMP 5. 0xfff7a000 0x00000910
9406 06:02:58.863983 VBOOT WORK 6. 0xfff66000 0x00014000
9407 06:02:58.867443 RAMOOPS 7. 0xffe66000 0x00100000
9408 06:02:58.870392 COREBOOT 8. 0xffe64000 0x00002000
9409 06:02:58.870468 IMD small region:
9410 06:02:58.873923 IMD ROOT 0. 0xffffec00 0x00000400
9411 06:02:58.877266 VPD 1. 0xffffeb80 0x0000006c
9412 06:02:58.880311 MMC STATUS 2. 0xffffeb60 0x00000004
9413 06:02:58.887166 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9414 06:02:58.887242 Probing TPM: done!
9415 06:02:58.894076 Connected to device vid:did:rid of 1ae0:0028:00
9416 06:02:58.904062 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9417 06:02:58.908434 Initialized TPM device CR50 revision 0
9418 06:02:58.908518 Checking cr50 for pending updates
9419 06:02:58.914088 Reading cr50 TPM mode
9420 06:02:58.922449 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9421 06:02:58.929226 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9422 06:02:58.969273 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9423 06:02:58.972748 Checking segment from ROM address 0x40100000
9424 06:02:58.975740 Checking segment from ROM address 0x4010001c
9425 06:02:58.982445 Loading segment from ROM address 0x40100000
9426 06:02:58.982529 code (compression=0)
9427 06:02:58.992403 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9428 06:02:58.999186 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9429 06:02:58.999272 it's not compressed!
9430 06:02:59.005829 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9431 06:02:59.009185 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9432 06:02:59.029480 Loading segment from ROM address 0x4010001c
9433 06:02:59.029565 Entry Point 0x80000000
9434 06:02:59.033171 Loaded segments
9435 06:02:59.036267 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9436 06:02:59.043138 Jumping to boot code at 0x80000000(0xffe64000)
9437 06:02:59.049708 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9438 06:02:59.056495 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9439 06:02:59.064176 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9440 06:02:59.067737 Checking segment from ROM address 0x40100000
9441 06:02:59.070783 Checking segment from ROM address 0x4010001c
9442 06:02:59.077803 Loading segment from ROM address 0x40100000
9443 06:02:59.077890 code (compression=1)
9444 06:02:59.084691 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9445 06:02:59.094291 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9446 06:02:59.094377 using LZMA
9447 06:02:59.102544 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9448 06:02:59.109372 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9449 06:02:59.112633 Loading segment from ROM address 0x4010001c
9450 06:02:59.112717 Entry Point 0x54601000
9451 06:02:59.115883 Loaded segments
9452 06:02:59.119395 NOTICE: MT8192 bl31_setup
9453 06:02:59.125995 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9454 06:02:59.129388 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9455 06:02:59.132824 WARNING: region 0:
9456 06:02:59.136121 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9457 06:02:59.136200 WARNING: region 1:
9458 06:02:59.142710 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9459 06:02:59.146374 WARNING: region 2:
9460 06:02:59.149368 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9461 06:02:59.152812 WARNING: region 3:
9462 06:02:59.156128 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9463 06:02:59.159496 WARNING: region 4:
9464 06:02:59.162700 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9465 06:02:59.166142 WARNING: region 5:
9466 06:02:59.169553 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9467 06:02:59.172838 WARNING: region 6:
9468 06:02:59.176109 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 06:02:59.176182 WARNING: region 7:
9470 06:02:59.183060 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 06:02:59.189778 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9472 06:02:59.192791 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9473 06:02:59.196114 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9474 06:02:59.202948 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9475 06:02:59.206221 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9476 06:02:59.210203 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9477 06:02:59.216470 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9478 06:02:59.219553 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9479 06:02:59.223099 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9480 06:02:59.230121 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9481 06:02:59.233472 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9482 06:02:59.236887 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9483 06:02:59.243425 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9484 06:02:59.246803 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9485 06:02:59.253300 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9486 06:02:59.256834 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9487 06:02:59.259954 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9488 06:02:59.266732 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9489 06:02:59.269815 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9490 06:02:59.273095 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9491 06:02:59.279659 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9492 06:02:59.283086 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9493 06:02:59.289899 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9494 06:02:59.293208 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9495 06:02:59.296435 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9496 06:02:59.303151 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9497 06:02:59.306377 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9498 06:02:59.313418 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9499 06:02:59.317160 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9500 06:02:59.320184 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9501 06:02:59.326969 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9502 06:02:59.330170 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9503 06:02:59.333635 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9504 06:02:59.340747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9505 06:02:59.343270 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9506 06:02:59.347138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9507 06:02:59.350243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9508 06:02:59.356554 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9509 06:02:59.359980 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9510 06:02:59.363722 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9511 06:02:59.366895 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9512 06:02:59.373624 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9513 06:02:59.376905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9514 06:02:59.380290 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9515 06:02:59.384133 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9516 06:02:59.390750 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9517 06:02:59.393744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9518 06:02:59.397131 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9519 06:02:59.403987 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9520 06:02:59.406864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9521 06:02:59.410649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9522 06:02:59.417119 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9523 06:02:59.420709 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9524 06:02:59.427190 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9525 06:02:59.430637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9526 06:02:59.437342 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9527 06:02:59.440536 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9528 06:02:59.443883 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9529 06:02:59.450416 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9530 06:02:59.454121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9531 06:02:59.460840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9532 06:02:59.463794 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9533 06:02:59.470816 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9534 06:02:59.474160 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9535 06:02:59.476981 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9536 06:02:59.483889 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9537 06:02:59.487777 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9538 06:02:59.494285 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9539 06:02:59.497876 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9540 06:02:59.500713 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9541 06:02:59.507514 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9542 06:02:59.511030 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9543 06:02:59.518039 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9544 06:02:59.520993 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9545 06:02:59.527608 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9546 06:02:59.530813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9547 06:02:59.534105 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9548 06:02:59.540906 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9549 06:02:59.544480 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9550 06:02:59.550969 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9551 06:02:59.554504 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9552 06:02:59.561720 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9553 06:02:59.564727 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9554 06:02:59.567900 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9555 06:02:59.574522 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9556 06:02:59.578278 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9557 06:02:59.584853 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9558 06:02:59.588111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9559 06:02:59.594767 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9560 06:02:59.598486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9561 06:02:59.601570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9562 06:02:59.608307 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9563 06:02:59.611382 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9564 06:02:59.618014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9565 06:02:59.621575 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9566 06:02:59.628059 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9567 06:02:59.631503 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9568 06:02:59.634930 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9569 06:02:59.638061 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9570 06:02:59.644693 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9571 06:02:59.648186 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9572 06:02:59.651581 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9573 06:02:59.658387 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9574 06:02:59.661411 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9575 06:02:59.665085 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9576 06:02:59.671500 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9577 06:02:59.674805 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9578 06:02:59.681934 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9579 06:02:59.685088 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9580 06:02:59.688387 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9581 06:02:59.695188 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9582 06:02:59.698819 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9583 06:02:59.701719 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9584 06:02:59.708465 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9585 06:02:59.711775 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9586 06:02:59.718922 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9587 06:02:59.721757 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9588 06:02:59.725148 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9589 06:02:59.731931 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9590 06:02:59.735002 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9591 06:02:59.738322 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9592 06:02:59.741816 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9593 06:02:59.745213 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9594 06:02:59.751825 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9595 06:02:59.755045 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9596 06:02:59.758396 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9597 06:02:59.765287 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9598 06:02:59.768763 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9599 06:02:59.775428 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9600 06:02:59.778838 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9601 06:02:59.782246 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9602 06:02:59.788868 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9603 06:02:59.792232 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9604 06:02:59.798819 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9605 06:02:59.801880 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9606 06:02:59.805653 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9607 06:02:59.812129 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9608 06:02:59.815362 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9609 06:02:59.818633 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9610 06:02:59.825233 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9611 06:02:59.828557 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9612 06:02:59.835318 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9613 06:02:59.838812 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9614 06:02:59.842162 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9615 06:02:59.848963 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9616 06:02:59.852095 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9617 06:02:59.855535 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9618 06:02:59.862070 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9619 06:02:59.865560 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9620 06:02:59.872201 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9621 06:02:59.875486 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9622 06:02:59.878874 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9623 06:02:59.885695 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9624 06:02:59.889262 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9625 06:02:59.895879 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9626 06:02:59.898967 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9627 06:02:59.902663 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9628 06:02:59.909103 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9629 06:02:59.912244 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9630 06:02:59.915621 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9631 06:02:59.922099 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9632 06:02:59.925428 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9633 06:02:59.932041 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9634 06:02:59.936209 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9635 06:02:59.942066 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9636 06:02:59.945038 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9637 06:02:59.948753 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9638 06:02:59.955465 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9639 06:02:59.958398 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9640 06:02:59.962071 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9641 06:02:59.968648 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9642 06:02:59.971696 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9643 06:02:59.978726 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9644 06:02:59.982405 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9645 06:02:59.985252 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9646 06:02:59.992080 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9647 06:02:59.995143 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9648 06:03:00.002045 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9649 06:03:00.005278 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9650 06:03:00.008609 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9651 06:03:00.015334 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9652 06:03:00.018524 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9653 06:03:00.022419 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9654 06:03:00.028225 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9655 06:03:00.031653 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9656 06:03:00.038061 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9657 06:03:00.041677 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9658 06:03:00.045073 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9659 06:03:00.052047 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9660 06:03:00.054798 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9661 06:03:00.061313 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9662 06:03:00.064737 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9663 06:03:00.071479 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9664 06:03:00.074867 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9665 06:03:00.077924 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9666 06:03:00.084552 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9667 06:03:00.088260 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9668 06:03:00.094766 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9669 06:03:00.097963 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9670 06:03:00.101297 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9671 06:03:00.107815 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9672 06:03:00.111507 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9673 06:03:00.118177 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9674 06:03:00.121375 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9675 06:03:00.128155 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9676 06:03:00.131565 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9677 06:03:00.134685 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9678 06:03:00.141414 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9679 06:03:00.144809 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9680 06:03:00.151518 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9681 06:03:00.154554 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9682 06:03:00.157856 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9683 06:03:00.164590 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9684 06:03:00.167947 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9685 06:03:00.174834 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9686 06:03:00.178108 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9687 06:03:00.181236 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9688 06:03:00.188080 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9689 06:03:00.191230 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9690 06:03:00.198251 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9691 06:03:00.201445 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9692 06:03:00.208074 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9693 06:03:00.211187 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9694 06:03:00.214306 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9695 06:03:00.221891 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9696 06:03:00.224505 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9697 06:03:00.231001 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9698 06:03:00.234253 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9699 06:03:00.237764 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9700 06:03:00.244671 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9701 06:03:00.248000 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9702 06:03:00.250697 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9703 06:03:00.254245 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9704 06:03:00.261184 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9705 06:03:00.264125 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9706 06:03:00.267511 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9707 06:03:00.274448 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9708 06:03:00.277416 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9709 06:03:00.280918 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9710 06:03:00.287450 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9711 06:03:00.290837 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9712 06:03:00.297684 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9713 06:03:00.301348 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9714 06:03:00.304371 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9715 06:03:00.310838 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9716 06:03:00.314303 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9717 06:03:00.317535 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9718 06:03:00.324085 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9719 06:03:00.327403 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9720 06:03:00.330841 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9721 06:03:00.337760 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9722 06:03:00.340712 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9723 06:03:00.347198 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9724 06:03:00.350494 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9725 06:03:00.354071 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9726 06:03:00.360278 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9727 06:03:00.363820 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9728 06:03:00.367299 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9729 06:03:00.374055 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9730 06:03:00.376928 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9731 06:03:00.380593 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9732 06:03:00.386887 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9733 06:03:00.390383 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9734 06:03:00.396910 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9735 06:03:00.400420 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9736 06:03:00.403690 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9737 06:03:00.410292 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9738 06:03:00.413828 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9739 06:03:00.417100 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9740 06:03:00.423722 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9741 06:03:00.427167 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9742 06:03:00.430288 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9743 06:03:00.433346 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9744 06:03:00.436753 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9745 06:03:00.443449 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9746 06:03:00.446597 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9747 06:03:00.449846 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9748 06:03:00.453418 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9749 06:03:00.459957 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9750 06:03:00.463359 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9751 06:03:00.466505 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9752 06:03:00.473253 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9753 06:03:00.476696 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9754 06:03:00.479745 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9755 06:03:00.486584 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9756 06:03:00.489922 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9757 06:03:00.496391 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9758 06:03:00.499623 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9759 06:03:00.506825 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9760 06:03:00.509537 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9761 06:03:00.513301 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9762 06:03:00.519963 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9763 06:03:00.522906 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9764 06:03:00.529765 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9765 06:03:00.532778 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9766 06:03:00.536310 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9767 06:03:00.542828 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9768 06:03:00.546155 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9769 06:03:00.553008 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9770 06:03:00.556451 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9771 06:03:00.559354 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9772 06:03:00.566183 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9773 06:03:00.569646 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9774 06:03:00.575984 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9775 06:03:00.579763 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9776 06:03:00.582679 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9777 06:03:00.589533 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9778 06:03:00.592778 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9779 06:03:00.599356 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9780 06:03:00.602539 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9781 06:03:00.609328 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9782 06:03:00.612815 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9783 06:03:00.616085 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9784 06:03:00.622594 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9785 06:03:00.626032 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9786 06:03:00.632471 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9787 06:03:00.635514 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9788 06:03:00.639072 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9789 06:03:00.645700 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9790 06:03:00.649134 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9791 06:03:00.655609 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9792 06:03:00.659036 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9793 06:03:00.662183 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9794 06:03:00.669388 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9795 06:03:00.672712 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9796 06:03:00.679157 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9797 06:03:00.682715 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9798 06:03:00.685686 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9799 06:03:00.692334 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9800 06:03:00.695854 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9801 06:03:00.702426 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9802 06:03:00.705917 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9803 06:03:00.708946 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9804 06:03:00.715994 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9805 06:03:00.719080 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9806 06:03:00.725844 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9807 06:03:00.729210 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9808 06:03:00.732465 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9809 06:03:00.738712 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9810 06:03:00.742001 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9811 06:03:00.749094 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9812 06:03:00.752572 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9813 06:03:00.758908 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9814 06:03:00.762257 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9815 06:03:00.765292 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9816 06:03:00.772370 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9817 06:03:00.775465 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9818 06:03:00.782096 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9819 06:03:00.785485 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9820 06:03:00.788841 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9821 06:03:00.795220 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9822 06:03:00.798904 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9823 06:03:00.805405 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9824 06:03:00.808581 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9825 06:03:00.812115 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9826 06:03:00.818536 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9827 06:03:00.821450 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9828 06:03:00.828543 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9829 06:03:00.831956 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9830 06:03:00.838080 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9831 06:03:00.841527 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9832 06:03:00.845352 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9833 06:03:00.851752 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9834 06:03:00.854814 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9835 06:03:00.861873 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9836 06:03:00.864740 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9837 06:03:00.871846 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9838 06:03:00.874590 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9839 06:03:00.881789 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9840 06:03:00.885115 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9841 06:03:00.888228 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9842 06:03:00.894954 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9843 06:03:00.898061 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9844 06:03:00.904940 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9845 06:03:00.908220 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9846 06:03:00.914763 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9847 06:03:00.917971 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9848 06:03:00.921482 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9849 06:03:00.927883 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9850 06:03:00.931328 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9851 06:03:00.938296 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9852 06:03:00.941314 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9853 06:03:00.947995 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9854 06:03:00.951305 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9855 06:03:00.958228 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9856 06:03:00.961454 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9857 06:03:00.964670 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9858 06:03:00.971553 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9859 06:03:00.974770 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9860 06:03:00.981770 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9861 06:03:00.984848 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9862 06:03:00.988213 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9863 06:03:00.994803 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9864 06:03:00.997925 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9865 06:03:01.004775 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9866 06:03:01.007940 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9867 06:03:01.014656 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9868 06:03:01.017842 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9869 06:03:01.021309 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9870 06:03:01.028072 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9871 06:03:01.031276 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9872 06:03:01.037777 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9873 06:03:01.041389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9874 06:03:01.044614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9875 06:03:01.050902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9876 06:03:01.054295 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9877 06:03:01.061206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9878 06:03:01.064346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9879 06:03:01.071431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9880 06:03:01.074437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9881 06:03:01.081040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9882 06:03:01.084318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9883 06:03:01.090708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9884 06:03:01.094079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9885 06:03:01.100688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9886 06:03:01.104431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9887 06:03:01.110545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9888 06:03:01.114466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9889 06:03:01.120629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9890 06:03:01.123728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9891 06:03:01.130538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9892 06:03:01.133590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9893 06:03:01.140261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9894 06:03:01.143451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9895 06:03:01.150154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9896 06:03:01.153587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9897 06:03:01.159967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9898 06:03:01.163698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9899 06:03:01.170165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9900 06:03:01.173317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9901 06:03:01.180714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9902 06:03:01.183678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9903 06:03:01.190301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9904 06:03:01.193237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9905 06:03:01.199827 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9906 06:03:01.200358 INFO: [APUAPC] vio 0
9907 06:03:01.206829 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9908 06:03:01.210123 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9909 06:03:01.213239 INFO: [APUAPC] D0_APC_0: 0x400510
9910 06:03:01.216396 INFO: [APUAPC] D0_APC_1: 0x0
9911 06:03:01.219665 INFO: [APUAPC] D0_APC_2: 0x1540
9912 06:03:01.223280 INFO: [APUAPC] D0_APC_3: 0x0
9913 06:03:01.226448 INFO: [APUAPC] D1_APC_0: 0xffffffff
9914 06:03:01.229761 INFO: [APUAPC] D1_APC_1: 0xffffffff
9915 06:03:01.233289 INFO: [APUAPC] D1_APC_2: 0x3fffff
9916 06:03:01.236316 INFO: [APUAPC] D1_APC_3: 0x0
9917 06:03:01.239675 INFO: [APUAPC] D2_APC_0: 0xffffffff
9918 06:03:01.243230 INFO: [APUAPC] D2_APC_1: 0xffffffff
9919 06:03:01.246276 INFO: [APUAPC] D2_APC_2: 0x3fffff
9920 06:03:01.249710 INFO: [APUAPC] D2_APC_3: 0x0
9921 06:03:01.252971 INFO: [APUAPC] D3_APC_0: 0xffffffff
9922 06:03:01.256323 INFO: [APUAPC] D3_APC_1: 0xffffffff
9923 06:03:01.259539 INFO: [APUAPC] D3_APC_2: 0x3fffff
9924 06:03:01.262761 INFO: [APUAPC] D3_APC_3: 0x0
9925 06:03:01.266136 INFO: [APUAPC] D4_APC_0: 0xffffffff
9926 06:03:01.269563 INFO: [APUAPC] D4_APC_1: 0xffffffff
9927 06:03:01.273068 INFO: [APUAPC] D4_APC_2: 0x3fffff
9928 06:03:01.273630 INFO: [APUAPC] D4_APC_3: 0x0
9929 06:03:01.276253 INFO: [APUAPC] D5_APC_0: 0xffffffff
9930 06:03:01.283028 INFO: [APUAPC] D5_APC_1: 0xffffffff
9931 06:03:01.286161 INFO: [APUAPC] D5_APC_2: 0x3fffff
9932 06:03:01.286636 INFO: [APUAPC] D5_APC_3: 0x0
9933 06:03:01.289482 INFO: [APUAPC] D6_APC_0: 0xffffffff
9934 06:03:01.292854 INFO: [APUAPC] D6_APC_1: 0xffffffff
9935 06:03:01.296089 INFO: [APUAPC] D6_APC_2: 0x3fffff
9936 06:03:01.299660 INFO: [APUAPC] D6_APC_3: 0x0
9937 06:03:01.302933 INFO: [APUAPC] D7_APC_0: 0xffffffff
9938 06:03:01.306313 INFO: [APUAPC] D7_APC_1: 0xffffffff
9939 06:03:01.309470 INFO: [APUAPC] D7_APC_2: 0x3fffff
9940 06:03:01.312902 INFO: [APUAPC] D7_APC_3: 0x0
9941 06:03:01.316150 INFO: [APUAPC] D8_APC_0: 0xffffffff
9942 06:03:01.319247 INFO: [APUAPC] D8_APC_1: 0xffffffff
9943 06:03:01.322807 INFO: [APUAPC] D8_APC_2: 0x3fffff
9944 06:03:01.325888 INFO: [APUAPC] D8_APC_3: 0x0
9945 06:03:01.329702 INFO: [APUAPC] D9_APC_0: 0xffffffff
9946 06:03:01.332652 INFO: [APUAPC] D9_APC_1: 0xffffffff
9947 06:03:01.335728 INFO: [APUAPC] D9_APC_2: 0x3fffff
9948 06:03:01.339528 INFO: [APUAPC] D9_APC_3: 0x0
9949 06:03:01.342559 INFO: [APUAPC] D10_APC_0: 0xffffffff
9950 06:03:01.345990 INFO: [APUAPC] D10_APC_1: 0xffffffff
9951 06:03:01.349302 INFO: [APUAPC] D10_APC_2: 0x3fffff
9952 06:03:01.352294 INFO: [APUAPC] D10_APC_3: 0x0
9953 06:03:01.355701 INFO: [APUAPC] D11_APC_0: 0xffffffff
9954 06:03:01.359124 INFO: [APUAPC] D11_APC_1: 0xffffffff
9955 06:03:01.362296 INFO: [APUAPC] D11_APC_2: 0x3fffff
9956 06:03:01.366052 INFO: [APUAPC] D11_APC_3: 0x0
9957 06:03:01.368817 INFO: [APUAPC] D12_APC_0: 0xffffffff
9958 06:03:01.372369 INFO: [APUAPC] D12_APC_1: 0xffffffff
9959 06:03:01.375722 INFO: [APUAPC] D12_APC_2: 0x3fffff
9960 06:03:01.378983 INFO: [APUAPC] D12_APC_3: 0x0
9961 06:03:01.382275 INFO: [APUAPC] D13_APC_0: 0xffffffff
9962 06:03:01.385478 INFO: [APUAPC] D13_APC_1: 0xffffffff
9963 06:03:01.388812 INFO: [APUAPC] D13_APC_2: 0x3fffff
9964 06:03:01.392506 INFO: [APUAPC] D13_APC_3: 0x0
9965 06:03:01.395750 INFO: [APUAPC] D14_APC_0: 0xffffffff
9966 06:03:01.399294 INFO: [APUAPC] D14_APC_1: 0xffffffff
9967 06:03:01.402753 INFO: [APUAPC] D14_APC_2: 0x3fffff
9968 06:03:01.406426 INFO: [APUAPC] D14_APC_3: 0x0
9969 06:03:01.409372 INFO: [APUAPC] D15_APC_0: 0xffffffff
9970 06:03:01.412619 INFO: [APUAPC] D15_APC_1: 0xffffffff
9971 06:03:01.416109 INFO: [APUAPC] D15_APC_2: 0x3fffff
9972 06:03:01.419498 INFO: [APUAPC] D15_APC_3: 0x0
9973 06:03:01.422534 INFO: [APUAPC] APC_CON: 0x4
9974 06:03:01.425995 INFO: [NOCDAPC] D0_APC_0: 0x0
9975 06:03:01.429391 INFO: [NOCDAPC] D0_APC_1: 0x0
9976 06:03:01.432908 INFO: [NOCDAPC] D1_APC_0: 0x0
9977 06:03:01.435920 INFO: [NOCDAPC] D1_APC_1: 0xfff
9978 06:03:01.436397 INFO: [NOCDAPC] D2_APC_0: 0x0
9979 06:03:01.439234 INFO: [NOCDAPC] D2_APC_1: 0xfff
9980 06:03:01.442118 INFO: [NOCDAPC] D3_APC_0: 0x0
9981 06:03:01.445736 INFO: [NOCDAPC] D3_APC_1: 0xfff
9982 06:03:01.449289 INFO: [NOCDAPC] D4_APC_0: 0x0
9983 06:03:01.452280 INFO: [NOCDAPC] D4_APC_1: 0xfff
9984 06:03:01.455612 INFO: [NOCDAPC] D5_APC_0: 0x0
9985 06:03:01.458754 INFO: [NOCDAPC] D5_APC_1: 0xfff
9986 06:03:01.462479 INFO: [NOCDAPC] D6_APC_0: 0x0
9987 06:03:01.465487 INFO: [NOCDAPC] D6_APC_1: 0xfff
9988 06:03:01.465919 INFO: [NOCDAPC] D7_APC_0: 0x0
9989 06:03:01.469111 INFO: [NOCDAPC] D7_APC_1: 0xfff
9990 06:03:01.472617 INFO: [NOCDAPC] D8_APC_0: 0x0
9991 06:03:01.475839 INFO: [NOCDAPC] D8_APC_1: 0xfff
9992 06:03:01.479249 INFO: [NOCDAPC] D9_APC_0: 0x0
9993 06:03:01.482511 INFO: [NOCDAPC] D9_APC_1: 0xfff
9994 06:03:01.486015 INFO: [NOCDAPC] D10_APC_0: 0x0
9995 06:03:01.489357 INFO: [NOCDAPC] D10_APC_1: 0xfff
9996 06:03:01.492731 INFO: [NOCDAPC] D11_APC_0: 0x0
9997 06:03:01.495425 INFO: [NOCDAPC] D11_APC_1: 0xfff
9998 06:03:01.499204 INFO: [NOCDAPC] D12_APC_0: 0x0
9999 06:03:01.502600 INFO: [NOCDAPC] D12_APC_1: 0xfff
10000 06:03:01.505738 INFO: [NOCDAPC] D13_APC_0: 0x0
10001 06:03:01.506321 INFO: [NOCDAPC] D13_APC_1: 0xfff
10002 06:03:01.509108 INFO: [NOCDAPC] D14_APC_0: 0x0
10003 06:03:01.512835 INFO: [NOCDAPC] D14_APC_1: 0xfff
10004 06:03:01.515937 INFO: [NOCDAPC] D15_APC_0: 0x0
10005 06:03:01.519089 INFO: [NOCDAPC] D15_APC_1: 0xfff
10006 06:03:01.522222 INFO: [NOCDAPC] APC_CON: 0x4
10007 06:03:01.525560 INFO: [APUAPC] set_apusys_apc done
10008 06:03:01.529069 INFO: [DEVAPC] devapc_init done
10009 06:03:01.532373 INFO: GICv3 without legacy support detected.
10010 06:03:01.535639 INFO: ARM GICv3 driver initialized in EL3
10011 06:03:01.541854 INFO: Maximum SPI INTID supported: 639
10012 06:03:01.545542 INFO: BL31: Initializing runtime services
10013 06:03:01.551999 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10014 06:03:01.552480 INFO: SPM: enable CPC mode
10015 06:03:01.558468 INFO: mcdi ready for mcusys-off-idle and system suspend
10016 06:03:01.561926 INFO: BL31: Preparing for EL3 exit to normal world
10017 06:03:01.565173 INFO: Entry point address = 0x80000000
10018 06:03:01.569044 INFO: SPSR = 0x8
10019 06:03:01.574477
10020 06:03:01.574897
10021 06:03:01.575236
10022 06:03:01.577852 Starting depthcharge on Spherion...
10023 06:03:01.578308
10024 06:03:01.578648 Wipe memory regions:
10025 06:03:01.579007
10026 06:03:01.581336 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10027 06:03:01.581850 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10028 06:03:01.582276 Setting prompt string to ['asurada:']
10029 06:03:01.582666 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10030 06:03:01.583316 [0x00000040000000, 0x00000054600000)
10031 06:03:01.703498
10032 06:03:01.704051 [0x00000054660000, 0x00000080000000)
10033 06:03:01.964325
10034 06:03:01.965003 [0x000000821a7280, 0x000000ffe64000)
10035 06:03:02.708784
10036 06:03:02.709350 [0x00000100000000, 0x00000240000000)
10037 06:03:04.598807
10038 06:03:04.601867 Initializing XHCI USB controller at 0x11200000.
10039 06:03:05.640014
10040 06:03:05.643441 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10041 06:03:05.644004
10042 06:03:05.644372
10043 06:03:05.644716
10044 06:03:05.645513 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10046 06:03:05.746861 asurada: tftpboot 192.168.201.1 12379474/tftp-deploy-ibdd2s4k/kernel/image.itb 12379474/tftp-deploy-ibdd2s4k/kernel/cmdline
10047 06:03:05.747521 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10048 06:03:05.748005 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10049 06:03:05.752927 tftpboot 192.168.201.1 12379474/tftp-deploy-ibdd2s4k/kernel/image.ittp-deploy-ibdd2s4k/kernel/cmdline
10050 06:03:05.753503
10051 06:03:05.753880 Waiting for link
10052 06:03:05.913461
10053 06:03:05.914071 R8152: Initializing
10054 06:03:05.914457
10055 06:03:05.917019 Version 9 (ocp_data = 6010)
10056 06:03:05.917586
10057 06:03:05.920104 R8152: Done initializing
10058 06:03:05.920681
10059 06:03:05.921061 Adding net device
10060 06:03:07.787760
10061 06:03:07.788358 done.
10062 06:03:07.788976
10063 06:03:07.789764 MAC: 00:e0:4c:72:2d:d6
10064 06:03:07.790575
10065 06:03:07.791621 Sending DHCP discover... done.
10066 06:03:07.792017
10067 06:03:07.794168 Waiting for reply... done.
10068 06:03:07.794695
10069 06:03:07.797570 Sending DHCP request... done.
10070 06:03:07.798074
10071 06:03:07.802853 Waiting for reply... done.
10072 06:03:07.803340
10073 06:03:07.803706 My ip is 192.168.201.21
10074 06:03:07.804051
10075 06:03:07.806088 The DHCP server ip is 192.168.201.1
10076 06:03:07.806556
10077 06:03:07.812916 TFTP server IP predefined by user: 192.168.201.1
10078 06:03:07.813488
10079 06:03:07.819429 Bootfile predefined by user: 12379474/tftp-deploy-ibdd2s4k/kernel/image.itb
10080 06:03:07.819901
10081 06:03:07.820268 Sending tftp read request... done.
10082 06:03:07.822627
10083 06:03:07.826928 Waiting for the transfer...
10084 06:03:07.827496
10085 06:03:08.160690 00000000 ################################################################
10086 06:03:08.160820
10087 06:03:08.416581 00080000 ################################################################
10088 06:03:08.416720
10089 06:03:08.664892 00100000 ################################################################
10090 06:03:08.665018
10091 06:03:08.913803 00180000 ################################################################
10092 06:03:08.913928
10093 06:03:09.164238 00200000 ################################################################
10094 06:03:09.164389
10095 06:03:09.419478 00280000 ################################################################
10096 06:03:09.419627
10097 06:03:09.668204 00300000 ################################################################
10098 06:03:09.668345
10099 06:03:09.931027 00380000 ################################################################
10100 06:03:09.931204
10101 06:03:10.183120 00400000 ################################################################
10102 06:03:10.183270
10103 06:03:10.432049 00480000 ################################################################
10104 06:03:10.432191
10105 06:03:10.681098 00500000 ################################################################
10106 06:03:10.681263
10107 06:03:10.932719 00580000 ################################################################
10108 06:03:10.932906
10109 06:03:11.210839 00600000 ################################################################
10110 06:03:11.211037
10111 06:03:11.587921 00680000 ################################################################
10112 06:03:11.588583
10113 06:03:11.973862 00700000 ################################################################
10114 06:03:11.974035
10115 06:03:12.272692 00780000 ################################################################
10116 06:03:12.272832
10117 06:03:12.615153 00800000 ################################################################
10118 06:03:12.615692
10119 06:03:12.945075 00880000 ################################################################
10120 06:03:12.945226
10121 06:03:13.254637 00900000 ################################################################
10122 06:03:13.254776
10123 06:03:13.525881 00980000 ################################################################
10124 06:03:13.526044
10125 06:03:13.803574 00a00000 ################################################################
10126 06:03:13.803718
10127 06:03:14.083257 00a80000 ################################################################
10128 06:03:14.083424
10129 06:03:14.362705 00b00000 ################################################################
10130 06:03:14.362859
10131 06:03:14.622898 00b80000 ################################################################
10132 06:03:14.623050
10133 06:03:14.871725 00c00000 ################################################################
10134 06:03:14.871869
10135 06:03:15.160633 00c80000 ################################################################
10136 06:03:15.160775
10137 06:03:15.440116 00d00000 ################################################################
10138 06:03:15.440267
10139 06:03:15.697900 00d80000 ################################################################
10140 06:03:15.698070
10141 06:03:15.958488 00e00000 ################################################################
10142 06:03:15.958634
10143 06:03:16.251004 00e80000 ################################################################
10144 06:03:16.251161
10145 06:03:16.526906 00f00000 ################################################################
10146 06:03:16.527061
10147 06:03:16.784762 00f80000 ################################################################
10148 06:03:16.784914
10149 06:03:17.039738 01000000 ################################################################
10150 06:03:17.039881
10151 06:03:17.289323 01080000 ################################################################
10152 06:03:17.289501
10153 06:03:17.555454 01100000 ################################################################
10154 06:03:17.555587
10155 06:03:17.803220 01180000 ################################################################
10156 06:03:17.803367
10157 06:03:18.062589 01200000 ################################################################
10158 06:03:18.062731
10159 06:03:18.346107 01280000 ################################################################
10160 06:03:18.346254
10161 06:03:18.632080 01300000 ################################################################
10162 06:03:18.632230
10163 06:03:18.879442 01380000 ################################################################
10164 06:03:18.879588
10165 06:03:19.128757 01400000 ################################################################
10166 06:03:19.128905
10167 06:03:19.376531 01480000 ################################################################
10168 06:03:19.376684
10169 06:03:19.624985 01500000 ################################################################
10170 06:03:19.625134
10171 06:03:19.873001 01580000 ################################################################
10172 06:03:19.873174
10173 06:03:20.128437 01600000 ################################################################
10174 06:03:20.128619
10175 06:03:20.376712 01680000 ################################################################
10176 06:03:20.376888
10177 06:03:20.625303 01700000 ################################################################
10178 06:03:20.625455
10179 06:03:20.873959 01780000 ################################################################
10180 06:03:20.874109
10181 06:03:21.122766 01800000 ################################################################
10182 06:03:21.122942
10183 06:03:21.371080 01880000 ################################################################
10184 06:03:21.371231
10185 06:03:21.620350 01900000 ################################################################
10186 06:03:21.620570
10187 06:03:21.871339 01980000 ################################################################
10188 06:03:21.871486
10189 06:03:22.120155 01a00000 ################################################################
10190 06:03:22.120297
10191 06:03:22.369761 01a80000 ################################################################
10192 06:03:22.369893
10193 06:03:22.630184 01b00000 ################################################################
10194 06:03:22.630327
10195 06:03:22.882359 01b80000 ################################################################
10196 06:03:22.882512
10197 06:03:23.131025 01c00000 ################################################################
10198 06:03:23.131160
10199 06:03:23.395719 01c80000 ################################################################
10200 06:03:23.395871
10201 06:03:23.644802 01d00000 ################################################################
10202 06:03:23.644941
10203 06:03:23.894766 01d80000 ################################################################
10204 06:03:23.894912
10205 06:03:24.144405 01e00000 ################################################################
10206 06:03:24.144541
10207 06:03:24.393580 01e80000 ################################################################
10208 06:03:24.393713
10209 06:03:24.641920 01f00000 ################################################################
10210 06:03:24.642050
10211 06:03:24.889883 01f80000 ################################################################
10212 06:03:24.890021
10213 06:03:25.138521 02000000 ################################################################
10214 06:03:25.138658
10215 06:03:25.387370 02080000 ################################################################
10216 06:03:25.387501
10217 06:03:25.636231 02100000 ################################################################
10218 06:03:25.636357
10219 06:03:25.883627 02180000 ################################################################
10220 06:03:25.883759
10221 06:03:26.132302 02200000 ################################################################
10222 06:03:26.132431
10223 06:03:26.380795 02280000 ################################################################
10224 06:03:26.380921
10225 06:03:26.629586 02300000 ################################################################
10226 06:03:26.629712
10227 06:03:26.896211 02380000 ################################################################
10228 06:03:26.896342
10229 06:03:27.186174 02400000 ################################################################
10230 06:03:27.186308
10231 06:03:27.470703 02480000 ################################################################
10232 06:03:27.470848
10233 06:03:27.751273 02500000 ################################################################
10234 06:03:27.751427
10235 06:03:28.013047 02580000 ################################################################
10236 06:03:28.013180
10237 06:03:28.262161 02600000 ################################################################
10238 06:03:28.262284
10239 06:03:28.510395 02680000 ################################################################
10240 06:03:28.510512
10241 06:03:28.759497 02700000 ################################################################
10242 06:03:28.759615
10243 06:03:29.008786 02780000 ################################################################
10244 06:03:29.008938
10245 06:03:29.257777 02800000 ################################################################
10246 06:03:29.257908
10247 06:03:29.506388 02880000 ################################################################
10248 06:03:29.506520
10249 06:03:29.755959 02900000 ################################################################
10250 06:03:29.756082
10251 06:03:30.003778 02980000 ################################################################
10252 06:03:30.003908
10253 06:03:30.252988 02a00000 ################################################################
10254 06:03:30.253128
10255 06:03:30.501703 02a80000 ################################################################
10256 06:03:30.501859
10257 06:03:30.750514 02b00000 ################################################################
10258 06:03:30.750666
10259 06:03:30.998617 02b80000 ################################################################
10260 06:03:30.998772
10261 06:03:31.272142 02c00000 ################################################################
10262 06:03:31.272322
10263 06:03:31.524033 02c80000 ################################################################
10264 06:03:31.524184
10265 06:03:31.794894 02d00000 ################################################################
10266 06:03:31.795054
10267 06:03:32.095081 02d80000 ################################################################
10268 06:03:32.095231
10269 06:03:32.382713 02e00000 ################################################################
10270 06:03:32.382868
10271 06:03:32.645499 02e80000 ################################################################
10272 06:03:32.645673
10273 06:03:32.904546 02f00000 ################################################################
10274 06:03:32.904685
10275 06:03:33.200877 02f80000 ################################################################
10276 06:03:33.201020
10277 06:03:33.555950 03000000 ################################################################
10278 06:03:33.556089
10279 06:03:33.850406 03080000 ################################################################
10280 06:03:33.850543
10281 06:03:34.150306 03100000 ################################################################
10282 06:03:34.150444
10283 06:03:34.449970 03180000 ################################################################
10284 06:03:34.450101
10285 06:03:34.741947 03200000 ################################################################
10286 06:03:34.742112
10287 06:03:35.024585 03280000 ################################################################
10288 06:03:35.024719
10289 06:03:35.274266 03300000 ################################################################
10290 06:03:35.274405
10291 06:03:35.523747 03380000 ################################################################
10292 06:03:35.523879
10293 06:03:35.773750 03400000 ################################################################
10294 06:03:35.773878
10295 06:03:36.022691 03480000 ################################################################
10296 06:03:36.022815
10297 06:03:36.272271 03500000 ################################################################
10298 06:03:36.272434
10299 06:03:36.533446 03580000 ################################################################
10300 06:03:36.533577
10301 06:03:36.782730 03600000 ################################################################
10302 06:03:36.782853
10303 06:03:37.036932 03680000 ################################################################
10304 06:03:37.037065
10305 06:03:37.286658 03700000 ################################################################
10306 06:03:37.286798
10307 06:03:37.536050 03780000 ################################################################
10308 06:03:37.536178
10309 06:03:37.784886 03800000 ################################################################
10310 06:03:37.785007
10311 06:03:38.034361 03880000 ################################################################
10312 06:03:38.034490
10313 06:03:38.284256 03900000 ################################################################
10314 06:03:38.284393
10315 06:03:38.533842 03980000 ################################################################
10316 06:03:38.534037
10317 06:03:38.783873 03a00000 ################################################################
10318 06:03:38.784034
10319 06:03:39.032874 03a80000 ################################################################
10320 06:03:39.033038
10321 06:03:39.281746 03b00000 ################################################################
10322 06:03:39.281878
10323 06:03:39.533410 03b80000 ################################################################
10324 06:03:39.533567
10325 06:03:39.819568 03c00000 ################################################################
10326 06:03:39.819722
10327 06:03:40.098419 03c80000 ################################################################
10328 06:03:40.098549
10329 06:03:40.376449 03d00000 ################################################################
10330 06:03:40.376594
10331 06:03:40.661861 03d80000 ################################################################
10332 06:03:40.662053
10333 06:03:40.942070 03e00000 ################################################################
10334 06:03:40.942199
10335 06:03:41.218953 03e80000 ################################################################
10336 06:03:41.219091
10337 06:03:41.502269 03f00000 ################################################################
10338 06:03:41.502401
10339 06:03:41.848919 03f80000 ################################################################
10340 06:03:41.849442
10341 06:03:42.127303 04000000 ################################################################
10342 06:03:42.127454
10343 06:03:42.306108 04080000 ########################################### done.
10344 06:03:42.306236
10345 06:03:42.309711 The bootfile was 67983714 bytes long.
10346 06:03:42.309881
10347 06:03:42.312708 Sending tftp read request... done.
10348 06:03:42.312875
10349 06:03:42.312976 Waiting for the transfer...
10350 06:03:42.313056
10351 06:03:42.315938 00000000 # done.
10352 06:03:42.316043
10353 06:03:42.322878 Command line loaded dynamically from TFTP file: 12379474/tftp-deploy-ibdd2s4k/kernel/cmdline
10354 06:03:42.323076
10355 06:03:42.336518 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10356 06:03:42.336744
10357 06:03:42.339516 Loading FIT.
10358 06:03:42.339758
10359 06:03:42.342665 Image ramdisk-1 has 56452572 bytes.
10360 06:03:42.342926
10361 06:03:42.343080 Image fdt-1 has 47278 bytes.
10362 06:03:42.343220
10363 06:03:42.345858 Image kernel-1 has 11481830 bytes.
10364 06:03:42.346083
10365 06:03:42.356148 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10366 06:03:42.356494
10367 06:03:42.372966 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10368 06:03:42.373578
10369 06:03:42.379612 Choosing best match conf-1 for compat google,spherion-rev2.
10370 06:03:42.383089
10371 06:03:42.387593 Connected to device vid:did:rid of 1ae0:0028:00
10372 06:03:42.394832
10373 06:03:42.398234 tpm_get_response: command 0x17b, return code 0x0
10374 06:03:42.398732
10375 06:03:42.401045 ec_init: CrosEC protocol v3 supported (256, 248)
10376 06:03:42.405531
10377 06:03:42.408671 tpm_cleanup: add release locality here.
10378 06:03:42.409260
10379 06:03:42.409640 Shutting down all USB controllers.
10380 06:03:42.411864
10381 06:03:42.412338 Removing current net device
10382 06:03:42.412718
10383 06:03:42.418785 Exiting depthcharge with code 4 at timestamp: 70142668
10384 06:03:42.419371
10385 06:03:42.421678 LZMA decompressing kernel-1 to 0x821a6718
10386 06:03:42.422216
10387 06:03:42.424796 LZMA decompressing kernel-1 to 0x40000000
10388 06:03:43.862240
10389 06:03:43.862835 jumping to kernel
10390 06:03:43.865145 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10391 06:03:43.865780 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10392 06:03:43.866296 Setting prompt string to ['Linux version [0-9]']
10393 06:03:43.866776 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10394 06:03:43.867248 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10395 06:03:43.944687
10396 06:03:43.948201 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10397 06:03:43.951693 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10398 06:03:43.952251 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10399 06:03:43.952724 Setting prompt string to []
10400 06:03:43.953274 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10401 06:03:43.953754 Using line separator: #'\n'#
10402 06:03:43.954284 No login prompt set.
10403 06:03:43.954771 Parsing kernel messages
10404 06:03:43.955192 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10405 06:03:43.956015 [login-action] Waiting for messages, (timeout 00:03:43)
10406 06:03:43.971210 [ 0.000000] Linux version 6.1.67-cip12 (KernelCI@build-j59664-arm64-gcc-10-defconfig-arm64-chromebook-fgc24) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023
10407 06:03:43.974801 [ 0.000000] random: crng init done
10408 06:03:43.981143 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10409 06:03:43.984630 [ 0.000000] efi: UEFI not found.
10410 06:03:43.991522 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10411 06:03:43.997739 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10412 06:03:44.007581 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10413 06:03:44.017590 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10414 06:03:44.024136 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10415 06:03:44.030707 [ 0.000000] printk: bootconsole [mtk8250] enabled
10416 06:03:44.036998 [ 0.000000] NUMA: No NUMA configuration found
10417 06:03:44.043697 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10418 06:03:44.047106 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10419 06:03:44.050840 [ 0.000000] Zone ranges:
10420 06:03:44.057025 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10421 06:03:44.060473 [ 0.000000] DMA32 empty
10422 06:03:44.067284 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10423 06:03:44.070431 [ 0.000000] Movable zone start for each node
10424 06:03:44.073645 [ 0.000000] Early memory node ranges
10425 06:03:44.080287 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10426 06:03:44.086931 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10427 06:03:44.093693 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10428 06:03:44.100048 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10429 06:03:44.106845 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10430 06:03:44.113445 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10431 06:03:44.169420 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10432 06:03:44.176380 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10433 06:03:44.182854 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10434 06:03:44.185909 [ 0.000000] psci: probing for conduit method from DT.
10435 06:03:44.192899 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10436 06:03:44.195724 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10437 06:03:44.202532 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10438 06:03:44.205755 [ 0.000000] psci: SMC Calling Convention v1.2
10439 06:03:44.212686 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10440 06:03:44.215570 [ 0.000000] Detected VIPT I-cache on CPU0
10441 06:03:44.222261 [ 0.000000] CPU features: detected: GIC system register CPU interface
10442 06:03:44.228563 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10443 06:03:44.235495 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10444 06:03:44.241721 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10445 06:03:44.248690 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10446 06:03:44.258350 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10447 06:03:44.261436 [ 0.000000] alternatives: applying boot alternatives
10448 06:03:44.267933 [ 0.000000] Fallback order for Node 0: 0
10449 06:03:44.274943 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10450 06:03:44.278151 [ 0.000000] Policy zone: Normal
10451 06:03:44.290984 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10452 06:03:44.301259 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10453 06:03:44.313825 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10454 06:03:44.323405 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10455 06:03:44.330114 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10456 06:03:44.333770 <6>[ 0.000000] software IO TLB: area num 8.
10457 06:03:44.391185 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10458 06:03:44.540406 <6>[ 0.000000] Memory: 7913588K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 439180K reserved, 32768K cma-reserved)
10459 06:03:44.546821 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10460 06:03:44.553524 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10461 06:03:44.557157 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10462 06:03:44.563961 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10463 06:03:44.569911 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10464 06:03:44.573632 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10465 06:03:44.583739 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10466 06:03:44.590244 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10467 06:03:44.593377 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10468 06:03:44.601374 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10469 06:03:44.604687 <6>[ 0.000000] GICv3: 608 SPIs implemented
10470 06:03:44.611400 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10471 06:03:44.614833 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10472 06:03:44.618125 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10473 06:03:44.627602 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10474 06:03:44.637361 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10475 06:03:44.650998 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10476 06:03:44.657812 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10477 06:03:44.666913 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10478 06:03:44.679807 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10479 06:03:44.687023 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10480 06:03:44.693583 <6>[ 0.009179] Console: colour dummy device 80x25
10481 06:03:44.703144 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10482 06:03:44.710203 <6>[ 0.024410] pid_max: default: 32768 minimum: 301
10483 06:03:44.713267 <6>[ 0.029282] LSM: Security Framework initializing
10484 06:03:44.719841 <6>[ 0.034220] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10485 06:03:44.729875 <6>[ 0.042035] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10486 06:03:44.736390 <6>[ 0.051443] cblist_init_generic: Setting adjustable number of callback queues.
10487 06:03:44.743045 <6>[ 0.058886] cblist_init_generic: Setting shift to 3 and lim to 1.
10488 06:03:44.753128 <6>[ 0.065225] cblist_init_generic: Setting adjustable number of callback queues.
10489 06:03:44.756976 <6>[ 0.072699] cblist_init_generic: Setting shift to 3 and lim to 1.
10490 06:03:44.763387 <6>[ 0.079100] rcu: Hierarchical SRCU implementation.
10491 06:03:44.769667 <6>[ 0.084146] rcu: Max phase no-delay instances is 1000.
10492 06:03:44.776678 <6>[ 0.091189] EFI services will not be available.
10493 06:03:44.779595 <6>[ 0.096145] smp: Bringing up secondary CPUs ...
10494 06:03:44.787488 <6>[ 0.101192] Detected VIPT I-cache on CPU1
10495 06:03:44.794321 <6>[ 0.101261] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10496 06:03:44.801426 <6>[ 0.101291] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10497 06:03:44.804286 <6>[ 0.101634] Detected VIPT I-cache on CPU2
10498 06:03:44.811157 <6>[ 0.101687] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10499 06:03:44.817694 <6>[ 0.101704] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10500 06:03:44.824577 <6>[ 0.101963] Detected VIPT I-cache on CPU3
10501 06:03:44.830841 <6>[ 0.102010] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10502 06:03:44.837467 <6>[ 0.102024] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10503 06:03:44.841085 <6>[ 0.102324] CPU features: detected: Spectre-v4
10504 06:03:44.847710 <6>[ 0.102331] CPU features: detected: Spectre-BHB
10505 06:03:44.850780 <6>[ 0.102336] Detected PIPT I-cache on CPU4
10506 06:03:44.857824 <6>[ 0.102393] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10507 06:03:44.864410 <6>[ 0.102409] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10508 06:03:44.867696 <6>[ 0.102701] Detected PIPT I-cache on CPU5
10509 06:03:44.877435 <6>[ 0.102761] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10510 06:03:44.884141 <6>[ 0.102778] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10511 06:03:44.887176 <6>[ 0.103060] Detected PIPT I-cache on CPU6
10512 06:03:44.894086 <6>[ 0.103125] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10513 06:03:44.900804 <6>[ 0.103141] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10514 06:03:44.907710 <6>[ 0.103437] Detected PIPT I-cache on CPU7
10515 06:03:44.913872 <6>[ 0.103503] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10516 06:03:44.920713 <6>[ 0.103518] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10517 06:03:44.923954 <6>[ 0.103566] smp: Brought up 1 node, 8 CPUs
10518 06:03:44.930574 <6>[ 0.244851] SMP: Total of 8 processors activated.
10519 06:03:44.933772 <6>[ 0.249802] CPU features: detected: 32-bit EL0 Support
10520 06:03:44.944146 <6>[ 0.255198] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10521 06:03:44.950151 <6>[ 0.264054] CPU features: detected: Common not Private translations
10522 06:03:44.953603 <6>[ 0.270570] CPU features: detected: CRC32 instructions
10523 06:03:44.960116 <6>[ 0.275921] CPU features: detected: RCpc load-acquire (LDAPR)
10524 06:03:44.966974 <6>[ 0.281918] CPU features: detected: LSE atomic instructions
10525 06:03:44.973634 <6>[ 0.287700] CPU features: detected: Privileged Access Never
10526 06:03:44.977147 <6>[ 0.293479] CPU features: detected: RAS Extension Support
10527 06:03:44.987336 <6>[ 0.299123] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10528 06:03:44.990204 <6>[ 0.306342] CPU: All CPU(s) started at EL2
10529 06:03:44.996468 <6>[ 0.310658] alternatives: applying system-wide alternatives
10530 06:03:45.005522 <6>[ 0.321373] devtmpfs: initialized
10531 06:03:45.017783 <6>[ 0.330272] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10532 06:03:45.027769 <6>[ 0.340237] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10533 06:03:45.034283 <6>[ 0.348473] pinctrl core: initialized pinctrl subsystem
10534 06:03:45.037267 <6>[ 0.355139] DMI not present or invalid.
10535 06:03:45.043897 <6>[ 0.359548] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10536 06:03:45.054480 <6>[ 0.366413] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10537 06:03:45.060592 <6>[ 0.373995] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10538 06:03:45.070396 <6>[ 0.382221] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10539 06:03:45.073690 <6>[ 0.390460] audit: initializing netlink subsys (disabled)
10540 06:03:45.083618 <5>[ 0.396153] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10541 06:03:45.089987 <6>[ 0.396854] thermal_sys: Registered thermal governor 'step_wise'
10542 06:03:45.096857 <6>[ 0.404118] thermal_sys: Registered thermal governor 'power_allocator'
10543 06:03:45.100285 <6>[ 0.410372] cpuidle: using governor menu
10544 06:03:45.107084 <6>[ 0.421329] NET: Registered PF_QIPCRTR protocol family
10545 06:03:45.113082 <6>[ 0.426803] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10546 06:03:45.119802 <6>[ 0.433903] ASID allocator initialised with 32768 entries
10547 06:03:45.122897 <6>[ 0.440466] Serial: AMBA PL011 UART driver
10548 06:03:45.133346 <4>[ 0.449231] Trying to register duplicate clock ID: 134
10549 06:03:45.187329 <6>[ 0.506698] KASLR enabled
10550 06:03:45.201659 <6>[ 0.514426] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10551 06:03:45.208399 <6>[ 0.521438] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10552 06:03:45.215302 <6>[ 0.527927] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10553 06:03:45.221622 <6>[ 0.534932] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10554 06:03:45.228367 <6>[ 0.541420] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10555 06:03:45.235153 <6>[ 0.548425] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10556 06:03:45.241909 <6>[ 0.554913] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10557 06:03:45.248481 <6>[ 0.561921] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10558 06:03:45.251413 <6>[ 0.569412] ACPI: Interpreter disabled.
10559 06:03:45.259924 <6>[ 0.575805] iommu: Default domain type: Translated
10560 06:03:45.266830 <6>[ 0.580914] iommu: DMA domain TLB invalidation policy: strict mode
10561 06:03:45.269710 <5>[ 0.587571] SCSI subsystem initialized
10562 06:03:45.276690 <6>[ 0.591733] usbcore: registered new interface driver usbfs
10563 06:03:45.283165 <6>[ 0.597467] usbcore: registered new interface driver hub
10564 06:03:45.286508 <6>[ 0.603020] usbcore: registered new device driver usb
10565 06:03:45.293199 <6>[ 0.609110] pps_core: LinuxPPS API ver. 1 registered
10566 06:03:45.302845 <6>[ 0.614302] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10567 06:03:45.306462 <6>[ 0.623646] PTP clock support registered
10568 06:03:45.309389 <6>[ 0.627887] EDAC MC: Ver: 3.0.0
10569 06:03:45.316650 <6>[ 0.633032] FPGA manager framework
10570 06:03:45.323878 <6>[ 0.636709] Advanced Linux Sound Architecture Driver Initialized.
10571 06:03:45.326755 <6>[ 0.643441] vgaarb: loaded
10572 06:03:45.333685 <6>[ 0.646585] clocksource: Switched to clocksource arch_sys_counter
10573 06:03:45.336835 <5>[ 0.653016] VFS: Disk quotas dquot_6.6.0
10574 06:03:45.343627 <6>[ 0.657200] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10575 06:03:45.346407 <6>[ 0.664386] pnp: PnP ACPI: disabled
10576 06:03:45.355364 <6>[ 0.671078] NET: Registered PF_INET protocol family
10577 06:03:45.361839 <6>[ 0.676355] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10578 06:03:45.376034 <6>[ 0.688661] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10579 06:03:45.386106 <6>[ 0.697475] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10580 06:03:45.393172 <6>[ 0.705446] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10581 06:03:45.399359 <6>[ 0.714146] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10582 06:03:45.411418 <6>[ 0.723892] TCP: Hash tables configured (established 65536 bind 65536)
10583 06:03:45.417657 <6>[ 0.730752] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10584 06:03:45.424638 <6>[ 0.737952] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10585 06:03:45.430874 <6>[ 0.745651] NET: Registered PF_UNIX/PF_LOCAL protocol family
10586 06:03:45.437758 <6>[ 0.751819] RPC: Registered named UNIX socket transport module.
10587 06:03:45.440805 <6>[ 0.757970] RPC: Registered udp transport module.
10588 06:03:45.447418 <6>[ 0.762904] RPC: Registered tcp transport module.
10589 06:03:45.454513 <6>[ 0.767837] RPC: Registered tcp NFSv4.1 backchannel transport module.
10590 06:03:45.457760 <6>[ 0.774504] PCI: CLS 0 bytes, default 64
10591 06:03:45.460995 <6>[ 0.778967] Unpacking initramfs...
10592 06:03:45.470889 <6>[ 0.782697] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10593 06:03:45.477519 <6>[ 0.791362] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10594 06:03:45.484386 <6>[ 0.800219] kvm [1]: IPA Size Limit: 40 bits
10595 06:03:45.487527 <6>[ 0.804746] kvm [1]: GICv3: no GICV resource entry
10596 06:03:45.494541 <6>[ 0.809768] kvm [1]: disabling GICv2 emulation
10597 06:03:45.500917 <6>[ 0.814453] kvm [1]: GIC system register CPU interface enabled
10598 06:03:45.504043 <6>[ 0.820627] kvm [1]: vgic interrupt IRQ18
10599 06:03:45.510489 <6>[ 0.826638] kvm [1]: VHE mode initialized successfully
10600 06:03:45.517198 <5>[ 0.833032] Initialise system trusted keyrings
10601 06:03:45.523617 <6>[ 0.837830] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10602 06:03:45.531791 <6>[ 0.847937] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10603 06:03:45.538514 <5>[ 0.854323] NFS: Registering the id_resolver key type
10604 06:03:45.542066 <5>[ 0.859623] Key type id_resolver registered
10605 06:03:45.548860 <5>[ 0.864037] Key type id_legacy registered
10606 06:03:45.555005 <6>[ 0.868328] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10607 06:03:45.562057 <6>[ 0.875247] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10608 06:03:45.568283 <6>[ 0.882959] 9p: Installing v9fs 9p2000 file system support
10609 06:03:45.605305 <5>[ 0.920818] Key type asymmetric registered
10610 06:03:45.608517 <5>[ 0.925150] Asymmetric key parser 'x509' registered
10611 06:03:45.618378 <6>[ 0.930287] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10612 06:03:45.621488 <6>[ 0.937899] io scheduler mq-deadline registered
10613 06:03:45.624550 <6>[ 0.942661] io scheduler kyber registered
10614 06:03:45.643510 <6>[ 0.959815] EINJ: ACPI disabled.
10615 06:03:45.675735 <4>[ 0.985235] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10616 06:03:45.685832 <4>[ 0.995853] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10617 06:03:45.700270 <6>[ 1.016238] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10618 06:03:45.708349 <6>[ 1.024192] printk: console [ttyS0] disabled
10619 06:03:45.736150 <6>[ 1.048838] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10620 06:03:45.742540 <6>[ 1.058307] printk: console [ttyS0] enabled
10621 06:03:45.745731 <6>[ 1.058307] printk: console [ttyS0] enabled
10622 06:03:45.752680 <6>[ 1.067201] printk: bootconsole [mtk8250] disabled
10623 06:03:45.756667 <6>[ 1.067201] printk: bootconsole [mtk8250] disabled
10624 06:03:45.762802 <6>[ 1.078238] SuperH (H)SCI(F) driver initialized
10625 06:03:45.765918 <6>[ 1.083519] msm_serial: driver initialized
10626 06:03:45.779714 <6>[ 1.092433] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10627 06:03:45.789865 <6>[ 1.100981] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10628 06:03:45.796239 <6>[ 1.109524] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10629 06:03:45.806260 <6>[ 1.118154] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10630 06:03:45.816288 <6>[ 1.126861] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10631 06:03:45.822436 <6>[ 1.135573] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10632 06:03:45.832943 <6>[ 1.144112] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10633 06:03:45.839459 <6>[ 1.152909] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10634 06:03:45.849152 <6>[ 1.161451] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10635 06:03:45.861020 <6>[ 1.177004] loop: module loaded
10636 06:03:45.867476 <6>[ 1.182866] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10637 06:03:45.890063 <4>[ 1.205986] mtk-pmic-keys: Failed to locate of_node [id: -1]
10638 06:03:45.896756 <6>[ 1.212742] megasas: 07.719.03.00-rc1
10639 06:03:45.906282 <6>[ 1.222276] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10640 06:03:45.914343 <6>[ 1.229989] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10641 06:03:45.930784 <6>[ 1.246534] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10642 06:03:45.986799 <6>[ 1.296198] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10643 06:03:47.855528 <6>[ 3.171732] Freeing initrd memory: 55128K
10644 06:03:47.865920 <6>[ 3.182240] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10645 06:03:47.876721 <6>[ 3.193134] tun: Universal TUN/TAP device driver, 1.6
10646 06:03:47.880104 <6>[ 3.199202] thunder_xcv, ver 1.0
10647 06:03:47.883378 <6>[ 3.202706] thunder_bgx, ver 1.0
10648 06:03:47.886524 <6>[ 3.206197] nicpf, ver 1.0
10649 06:03:47.897067 <6>[ 3.210204] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10650 06:03:47.900376 <6>[ 3.217679] hns3: Copyright (c) 2017 Huawei Corporation.
10651 06:03:47.906990 <6>[ 3.223266] hclge is initializing
10652 06:03:47.910470 <6>[ 3.226846] e1000: Intel(R) PRO/1000 Network Driver
10653 06:03:47.916856 <6>[ 3.231975] e1000: Copyright (c) 1999-2006 Intel Corporation.
10654 06:03:47.920296 <6>[ 3.237991] e1000e: Intel(R) PRO/1000 Network Driver
10655 06:03:47.927349 <6>[ 3.243206] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10656 06:03:47.933900 <6>[ 3.249390] igb: Intel(R) Gigabit Ethernet Network Driver
10657 06:03:47.940157 <6>[ 3.255041] igb: Copyright (c) 2007-2014 Intel Corporation.
10658 06:03:47.946902 <6>[ 3.260879] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10659 06:03:47.953605 <6>[ 3.267396] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10660 06:03:47.956870 <6>[ 3.273859] sky2: driver version 1.30
10661 06:03:47.963117 <6>[ 3.278854] VFIO - User Level meta-driver version: 0.3
10662 06:03:47.970967 <6>[ 3.287114] usbcore: registered new interface driver usb-storage
10663 06:03:47.977501 <6>[ 3.293555] usbcore: registered new device driver onboard-usb-hub
10664 06:03:47.986514 <6>[ 3.302681] mt6397-rtc mt6359-rtc: registered as rtc0
10665 06:03:47.996624 <6>[ 3.308141] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-25T06:03:06 UTC (1703484186)
10666 06:03:47.999624 <6>[ 3.317703] i2c_dev: i2c /dev entries driver
10667 06:03:48.016562 <6>[ 3.329351] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10668 06:03:48.036300 <6>[ 3.352347] cpu cpu0: EM: created perf domain
10669 06:03:48.039350 <6>[ 3.357265] cpu cpu4: EM: created perf domain
10670 06:03:48.046689 <6>[ 3.362834] sdhci: Secure Digital Host Controller Interface driver
10671 06:03:48.053268 <6>[ 3.369265] sdhci: Copyright(c) Pierre Ossman
10672 06:03:48.059963 <6>[ 3.374221] Synopsys Designware Multimedia Card Interface Driver
10673 06:03:48.066508 <6>[ 3.380864] sdhci-pltfm: SDHCI platform and OF driver helper
10674 06:03:48.069852 <6>[ 3.380881] mmc0: CQHCI version 5.10
10675 06:03:48.076543 <6>[ 3.390891] ledtrig-cpu: registered to indicate activity on CPUs
10676 06:03:48.083212 <6>[ 3.397885] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10677 06:03:48.089902 <6>[ 3.404939] usbcore: registered new interface driver usbhid
10678 06:03:48.093211 <6>[ 3.410761] usbhid: USB HID core driver
10679 06:03:48.099443 <6>[ 3.414955] spi_master spi0: will run message pump with realtime priority
10680 06:03:48.142096 <6>[ 3.451667] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10681 06:03:48.160876 <6>[ 3.466867] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10682 06:03:48.167329 <6>[ 3.481837] cros-ec-spi spi0.0: Chrome EC device registered
10683 06:03:48.170527 <6>[ 3.481941] mmc0: Command Queue Engine enabled
10684 06:03:48.177818 <6>[ 3.492414] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10685 06:03:48.184371 <6>[ 3.499693] mmcblk0: mmc0:0001 DA4128 116 GiB
10686 06:03:48.194454 <6>[ 3.510742] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10687 06:03:48.202293 <6>[ 3.518550] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10688 06:03:48.212162 <6>[ 3.523643] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10689 06:03:48.215169 <6>[ 3.524468] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10690 06:03:48.221883 <6>[ 3.534449] NET: Registered PF_PACKET protocol family
10691 06:03:48.228790 <6>[ 3.539075] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10692 06:03:48.231688 <6>[ 3.543678] 9pnet: Installing 9P2000 support
10693 06:03:48.238644 <5>[ 3.554692] Key type dns_resolver registered
10694 06:03:48.242116 <6>[ 3.559658] registered taskstats version 1
10695 06:03:48.248869 <5>[ 3.564041] Loading compiled-in X.509 certificates
10696 06:03:48.278840 <4>[ 3.588174] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10697 06:03:48.288521 <4>[ 3.598974] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10698 06:03:48.295324 <3>[ 3.609530] debugfs: File 'uA_load' in directory '/' already present!
10699 06:03:48.301734 <3>[ 3.616302] debugfs: File 'min_uV' in directory '/' already present!
10700 06:03:48.308540 <3>[ 3.622928] debugfs: File 'max_uV' in directory '/' already present!
10701 06:03:48.315086 <3>[ 3.629557] debugfs: File 'constraint_flags' in directory '/' already present!
10702 06:03:48.326578 <3>[ 3.639332] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10703 06:03:48.336320 <6>[ 3.652943] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10704 06:03:48.343174 <6>[ 3.659623] xhci-mtk 11200000.usb: xHCI Host Controller
10705 06:03:48.350154 <6>[ 3.665114] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10706 06:03:48.359994 <6>[ 3.672949] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10707 06:03:48.366416 <6>[ 3.682369] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10708 06:03:48.373825 <6>[ 3.688430] xhci-mtk 11200000.usb: xHCI Host Controller
10709 06:03:48.380217 <6>[ 3.693907] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10710 06:03:48.386711 <6>[ 3.701553] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10711 06:03:48.393021 <6>[ 3.709227] hub 1-0:1.0: USB hub found
10712 06:03:48.396836 <6>[ 3.713237] hub 1-0:1.0: 1 port detected
10713 06:03:48.403240 <6>[ 3.717509] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10714 06:03:48.409790 <6>[ 3.726071] hub 2-0:1.0: USB hub found
10715 06:03:48.413021 <6>[ 3.730077] hub 2-0:1.0: 1 port detected
10716 06:03:48.421233 <6>[ 3.737689] mtk-msdc 11f70000.mmc: Got CD GPIO
10717 06:03:48.436769 <6>[ 3.750027] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10718 06:03:48.443700 <6>[ 3.758083] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10719 06:03:48.453733 <4>[ 3.765987] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10720 06:03:48.463756 <6>[ 3.775516] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10721 06:03:48.470413 <6>[ 3.783593] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10722 06:03:48.477058 <6>[ 3.791796] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10723 06:03:48.487140 <6>[ 3.799747] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10724 06:03:48.493862 <6>[ 3.807566] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10725 06:03:48.503866 <6>[ 3.815384] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10726 06:03:48.513874 <6>[ 3.825771] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10727 06:03:48.520073 <6>[ 3.834161] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10728 06:03:48.530395 <6>[ 3.842500] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10729 06:03:48.536608 <6>[ 3.850841] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10730 06:03:48.546500 <6>[ 3.859180] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10731 06:03:48.553233 <6>[ 3.867519] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10732 06:03:48.563070 <6>[ 3.875858] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10733 06:03:48.570044 <6>[ 3.884196] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10734 06:03:48.579977 <6>[ 3.892534] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10735 06:03:48.586858 <6>[ 3.900872] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10736 06:03:48.596459 <6>[ 3.909216] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10737 06:03:48.603219 <6>[ 3.917556] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10738 06:03:48.612976 <6>[ 3.925894] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10739 06:03:48.622740 <6>[ 3.934232] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10740 06:03:48.629377 <6>[ 3.942577] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10741 06:03:48.635911 <6>[ 3.951321] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10742 06:03:48.642121 <6>[ 3.958463] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10743 06:03:48.648876 <6>[ 3.965218] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10744 06:03:48.658504 <6>[ 3.971966] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10745 06:03:48.665537 <6>[ 3.978906] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10746 06:03:48.672625 <6>[ 3.985744] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10747 06:03:48.681918 <6>[ 3.994876] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10748 06:03:48.691944 <6>[ 4.003995] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10749 06:03:48.701914 <6>[ 4.013290] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10750 06:03:48.711412 <6>[ 4.022762] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10751 06:03:48.718463 <6>[ 4.032228] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10752 06:03:48.728371 <6>[ 4.041349] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10753 06:03:48.739138 <6>[ 4.050818] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10754 06:03:48.748003 <6>[ 4.059935] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10755 06:03:48.757988 <6>[ 4.069228] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10756 06:03:48.767947 <6>[ 4.079388] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10757 06:03:48.778370 <6>[ 4.090827] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10758 06:03:48.801763 <6>[ 4.114891] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10759 06:03:48.830292 <6>[ 4.146230] hub 2-1:1.0: USB hub found
10760 06:03:48.833322 <6>[ 4.150695] hub 2-1:1.0: 3 ports detected
10761 06:03:48.841982 <6>[ 4.158040] hub 2-1:1.0: USB hub found
10762 06:03:48.845168 <6>[ 4.162364] hub 2-1:1.0: 3 ports detected
10763 06:03:48.953460 <6>[ 4.266855] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10764 06:03:49.108704 <6>[ 4.425057] hub 1-1:1.0: USB hub found
10765 06:03:49.112050 <6>[ 4.429523] hub 1-1:1.0: 4 ports detected
10766 06:03:49.122316 <6>[ 4.438359] hub 1-1:1.0: USB hub found
10767 06:03:49.125714 <6>[ 4.443030] hub 1-1:1.0: 4 ports detected
10768 06:03:49.194149 <6>[ 4.507077] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10769 06:03:49.445714 <6>[ 4.758901] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10770 06:03:49.578444 <6>[ 4.894854] hub 1-1.4:1.0: USB hub found
10771 06:03:49.581716 <6>[ 4.899540] hub 1-1.4:1.0: 2 ports detected
10772 06:03:49.591719 <6>[ 4.908252] hub 1-1.4:1.0: USB hub found
10773 06:03:49.595331 <6>[ 4.912966] hub 1-1.4:1.0: 2 ports detected
10774 06:03:49.893583 <6>[ 5.206883] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10775 06:03:50.085497 <6>[ 5.398879] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10776 06:04:01.078762 <6>[ 16.399887] ALSA device list:
10777 06:04:01.085210 <6>[ 16.403172] No soundcards found.
10778 06:04:01.093450 <6>[ 16.411166] Freeing unused kernel memory: 8448K
10779 06:04:01.096833 <6>[ 16.416262] Run /init as init process
10780 06:04:01.146876 <6>[ 16.464640] NET: Registered PF_INET6 protocol family
10781 06:04:01.153629 <6>[ 16.471016] Segment Routing with IPv6
10782 06:04:01.157050 <6>[ 16.474963] In-situ OAM (IOAM) with IPv6
10783 06:04:01.191693 <30>[ 16.489686] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10784 06:04:01.195205 <30>[ 16.513745] systemd[1]: Detected architecture arm64.
10785 06:04:01.198193
10786 06:04:01.201853 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10787 06:04:01.202356
10788 06:04:01.221420 <30>[ 16.539008] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10789 06:04:01.344329 <30>[ 16.658804] systemd[1]: Queued start job for default target Graphical Interface.
10790 06:04:01.374069 <30>[ 16.691584] systemd[1]: Created slice system-getty.slice.
10791 06:04:01.380463 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10792 06:04:01.397822 <30>[ 16.715451] systemd[1]: Created slice system-modprobe.slice.
10793 06:04:01.404200 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10794 06:04:01.425673 <30>[ 16.739987] systemd[1]: Created slice system-serial\x2dgetty.slice.
10795 06:04:01.431812 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10796 06:04:01.446133 <30>[ 16.763997] systemd[1]: Created slice User and Session Slice.
10797 06:04:01.453091 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10798 06:04:01.473419 <30>[ 16.787469] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10799 06:04:01.482904 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10800 06:04:01.501310 <30>[ 16.815562] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10801 06:04:01.507621 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10802 06:04:01.532149 <30>[ 16.843323] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10803 06:04:01.538731 <30>[ 16.855602] systemd[1]: Reached target Local Encrypted Volumes.
10804 06:04:01.545624 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10805 06:04:01.561539 <30>[ 16.879357] systemd[1]: Reached target Paths.
10806 06:04:01.568038 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10807 06:04:01.581882 <30>[ 16.899309] systemd[1]: Reached target Remote File Systems.
10808 06:04:01.587809 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10809 06:04:01.605593 <30>[ 16.923234] systemd[1]: Reached target Slices.
10810 06:04:01.612310 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10811 06:04:01.625003 <30>[ 16.942920] systemd[1]: Reached target Swap.
10812 06:04:01.628298 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10813 06:04:01.649171 <30>[ 16.963378] systemd[1]: Listening on initctl Compatibility Named Pipe.
10814 06:04:01.655293 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10815 06:04:01.662284 <30>[ 16.978544] systemd[1]: Listening on Journal Audit Socket.
10816 06:04:01.668628 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10817 06:04:01.681796 <30>[ 16.999419] systemd[1]: Listening on Journal Socket (/dev/log).
10818 06:04:01.687968 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10819 06:04:01.706182 <30>[ 17.024098] systemd[1]: Listening on Journal Socket.
10820 06:04:01.712760 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10821 06:04:01.725604 <30>[ 17.043483] systemd[1]: Listening on udev Control Socket.
10822 06:04:01.732154 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10823 06:04:01.749910 <30>[ 17.067898] systemd[1]: Listening on udev Kernel Socket.
10824 06:04:01.756652 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10825 06:04:01.809473 <30>[ 17.127356] systemd[1]: Mounting Huge Pages File System...
10826 06:04:01.815932 Mounting [0;1;39mHuge Pages File System[0m...
10827 06:04:01.830665 <30>[ 17.148788] systemd[1]: Mounting POSIX Message Queue File System...
10828 06:04:01.838104 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10829 06:04:01.855150 <30>[ 17.172927] systemd[1]: Mounting Kernel Debug File System...
10830 06:04:01.861519 Mounting [0;1;39mKernel Debug File System[0m...
10831 06:04:01.880477 <30>[ 17.195109] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10832 06:04:01.913064 <30>[ 17.227592] systemd[1]: Starting Create list of static device nodes for the current kernel...
10833 06:04:01.920052 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10834 06:04:01.941714 <30>[ 17.259386] systemd[1]: Starting Load Kernel Module configfs...
10835 06:04:01.948125 Starting [0;1;39mLoad Kernel Module configfs[0m...
10836 06:04:01.965603 <30>[ 17.283509] systemd[1]: Starting Load Kernel Module drm...
10837 06:04:01.972192 Starting [0;1;39mLoad Kernel Module drm[0m...
10838 06:04:01.988692 <30>[ 17.303182] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10839 06:04:02.002798 <30>[ 17.320661] systemd[1]: Starting Journal Service...
10840 06:04:02.006389 Starting [0;1;39mJournal Service[0m...
10841 06:04:02.025597 <30>[ 17.343399] systemd[1]: Starting Load Kernel Modules...
10842 06:04:02.031860 Starting [0;1;39mLoad Kernel Modules[0m...
10843 06:04:02.052641 <30>[ 17.367158] systemd[1]: Starting Remount Root and Kernel File Systems...
10844 06:04:02.059138 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10845 06:04:02.076646 <30>[ 17.394402] systemd[1]: Starting Coldplug All udev Devices...
10846 06:04:02.083021 Starting [0;1;39mColdplug All udev Devices[0m...
10847 06:04:02.101846 <30>[ 17.419739] systemd[1]: Started Journal Service.
10848 06:04:02.108652 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10849 06:04:02.123483 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10850 06:04:02.141996 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10851 06:04:02.158633 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10852 06:04:02.178578 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10853 06:04:02.198826 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10854 06:04:02.219438 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10855 06:04:02.239335 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10856 06:04:02.263869 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10857 06:04:02.277209 See 'systemctl status systemd-remount-fs.service' for details.
10858 06:04:02.318025 Mounting [0;1;39mKernel Configuration File System[0m...
10859 06:04:02.335163 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10860 06:04:02.350135 <46>[ 17.664476] systemd-journald[173]: Received client request to flush runtime journal.
10861 06:04:02.359076 Starting [0;1;39mLoad/Save Random Seed[0m...
10862 06:04:02.378382 Starting [0;1;39mApply Kernel Variables[0m...
10863 06:04:02.403317 Starting [0;1;39mCreate System Users[0m...
10864 06:04:02.426853 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10865 06:04:02.446470 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10866 06:04:02.470234 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10867 06:04:02.483101 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10868 06:04:02.498903 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10869 06:04:02.514087 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10870 06:04:02.565768 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10871 06:04:02.585733 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10872 06:04:02.597279 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10873 06:04:02.613080 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10874 06:04:02.654071 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10875 06:04:02.676960 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10876 06:04:02.694040 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10877 06:04:02.714534 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10878 06:04:02.771850 Starting [0;1;39mNetwork Time Synchronization[0m...
10879 06:04:02.794293 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10880 06:04:02.832635 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10881 06:04:02.848454 <6>[ 18.162893] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10882 06:04:02.868589 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10883 06:04:02.894465 <3>[ 18.208810] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10884 06:04:02.900545 <3>[ 18.217032] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10885 06:04:02.910571 <4>[ 18.223033] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10886 06:04:02.917406 <3>[ 18.225134] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10887 06:04:02.924033 <4>[ 18.238743] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10888 06:04:02.933754 <6>[ 18.241074] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10889 06:04:02.936751 <6>[ 18.248146] remoteproc remoteproc0: scp is available
10890 06:04:02.943917 <6>[ 18.248322] remoteproc remoteproc0: powering up scp
10891 06:04:02.950212 <6>[ 18.255810] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10892 06:04:02.960335 <6>[ 18.261217] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10893 06:04:02.969926 <6>[ 18.266129] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10894 06:04:02.973849 <6>[ 18.274819] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10895 06:04:02.983702 <3>[ 18.279180] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10896 06:04:02.990557 <3>[ 18.279204] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10897 06:04:03.000311 <3>[ 18.279210] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10898 06:04:03.007063 <3>[ 18.279220] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10899 06:04:03.017012 <3>[ 18.279224] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10900 06:04:03.023784 <3>[ 18.282735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10901 06:04:03.030172 <3>[ 18.299247] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10902 06:04:03.036369 <6>[ 18.335528] mc: Linux media interface: v0.10
10903 06:04:03.042946 <3>[ 18.338321] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10904 06:04:03.053013 <6>[ 18.349113] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10905 06:04:03.059790 <3>[ 18.354554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10906 06:04:03.070035 <3>[ 18.354706] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10907 06:04:03.073161 <6>[ 18.356797] usbcore: registered new interface driver r8152
10908 06:04:03.083639 <4>[ 18.371790] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10909 06:04:03.086965 <4>[ 18.371790] Fallback method does not support PEC.
10910 06:04:03.096913 <3>[ 18.375161] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10911 06:04:03.106539 <6>[ 18.389111] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10912 06:04:03.113384 <3>[ 18.391197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10913 06:04:03.119809 <6>[ 18.404570] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10914 06:04:03.129651 <3>[ 18.410582] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 06:04:03.136450 <3>[ 18.410596] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10916 06:04:03.146330 <3>[ 18.410677] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 06:04:03.152844 <6>[ 18.459734] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10918 06:04:03.159352 <6>[ 18.467802] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10919 06:04:03.166110 <6>[ 18.467864] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10920 06:04:03.172767 <6>[ 18.467874] remoteproc remoteproc0: remote processor scp is now up
10921 06:04:03.179373 <6>[ 18.467888] pci_bus 0000:00: root bus resource [bus 00-ff]
10922 06:04:03.186412 <6>[ 18.467896] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10923 06:04:03.197317 <6>[ 18.467899] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10924 06:04:03.203604 <6>[ 18.467936] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10925 06:04:03.210150 <6>[ 18.467949] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10926 06:04:03.217192 <6>[ 18.468016] pci 0000:00:00.0: supports D1 D2
10927 06:04:03.223458 <6>[ 18.468017] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10928 06:04:03.230386 <6>[ 18.469031] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10929 06:04:03.236557 <6>[ 18.469130] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10930 06:04:03.243526 <6>[ 18.469154] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10931 06:04:03.252923 <6>[ 18.469170] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10932 06:04:03.259805 <6>[ 18.469185] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10933 06:04:03.263293 <6>[ 18.469294] pci 0000:01:00.0: supports D1 D2
10934 06:04:03.269530 <6>[ 18.469296] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10935 06:04:03.276090 <6>[ 18.482780] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10936 06:04:03.286385 <3>[ 18.490926] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 06:04:03.296115 <6>[ 18.493290] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10938 06:04:03.306209 <6>[ 18.493581] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10939 06:04:03.312942 <6>[ 18.497815] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10940 06:04:03.319307 <6>[ 18.503481] videodev: Linux video capture interface: v2.00
10941 06:04:03.325965 <6>[ 18.510367] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10942 06:04:03.330214 <6>[ 18.532158] Bluetooth: Core ver 2.22
10943 06:04:03.340505 <6>[ 18.532763] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10944 06:04:03.347799 <6>[ 18.533777] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10945 06:04:03.354480 <6>[ 18.534183] usbcore: registered new interface driver cdc_ether
10946 06:04:03.361223 <3>[ 18.535371] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 06:04:03.371100 <4>[ 18.539237] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10948 06:04:03.374692 <6>[ 18.539824] NET: Registered PF_BLUETOOTH protocol family
10949 06:04:03.381478 <6>[ 18.539829] Bluetooth: HCI device and connection manager initialized
10950 06:04:03.388400 <6>[ 18.539857] Bluetooth: HCI socket layer initialized
10951 06:04:03.394881 <6>[ 18.539864] Bluetooth: L2CAP socket layer initialized
10952 06:04:03.398368 <6>[ 18.539883] Bluetooth: SCO socket layer initialized
10953 06:04:03.405579 <6>[ 18.541004] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10954 06:04:03.415861 <6>[ 18.545461] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10955 06:04:03.422496 <6>[ 18.545672] usbcore: registered new interface driver r8153_ecm
10956 06:04:03.429424 <4>[ 18.553451] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10957 06:04:03.436327 <6>[ 18.559711] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10958 06:04:03.442964 <6>[ 18.576406] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10959 06:04:03.450026 <6>[ 18.582122] pci 0000:00:00.0: PCI bridge to [bus 01]
10960 06:04:03.456551 <6>[ 18.587594] usbcore: registered new interface driver btusb
10961 06:04:03.467117 <4>[ 18.588227] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10962 06:04:03.470394 <3>[ 18.588243] Bluetooth: hci0: Failed to load firmware file (-2)
10963 06:04:03.477010 <3>[ 18.588405] Bluetooth: hci0: Failed to set up firmware (-2)
10964 06:04:03.486988 <4>[ 18.588409] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10965 06:04:03.500744 <6>[ 18.588722] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10966 06:04:03.507121 <6>[ 18.588808] usbcore: registered new interface driver uvcvideo
10967 06:04:03.513827 <6>[ 18.593511] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10968 06:04:03.520324 <6>[ 18.593859] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10969 06:04:03.527179 <6>[ 18.594458] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10970 06:04:03.530827 <6>[ 18.622819] r8152 2-1.3:1.0 eth0: v1.12.13
10971 06:04:03.536901 <6>[ 18.628757] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10972 06:04:03.543632 <6>[ 18.642312] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10973 06:04:03.550491 <6>[ 18.650393] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10974 06:04:03.560052 <3>[ 18.669553] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 06:04:03.566939 <3>[ 18.670555] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10976 06:04:03.576892 <3>[ 18.673397] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 06:04:03.584469 <3>[ 18.674164] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10978 06:04:03.594462 <3>[ 18.697560] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 06:04:03.601098 <5>[ 18.701823] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10980 06:04:03.608265 <3>[ 18.727285] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 06:04:03.614740 <5>[ 18.737409] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10982 06:04:03.625395 <3>[ 18.760344] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 06:04:03.635132 <4>[ 18.760545] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10984 06:04:03.642444 <3>[ 18.789123] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 06:04:03.649349 <6>[ 18.795067] cfg80211: failed to load regulatory.db
10986 06:04:03.655813 <6>[ 18.877501] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10987 06:04:03.662900 <6>[ 18.978525] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10988 06:04:03.669204 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10989 06:04:03.685345 [[0;32m OK [0m] Finished [0;1;39mLoad/Save <6>[ 19.002897] mt7921e 0000:01:00.0: ASIC revision: 79610010
10990 06:04:03.691904 Screen …s of leds:white:kbd_backlight[0m.
10991 06:04:03.730921 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10992 06:04:03.765180 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10993 06:04:03.788442 <6>[ 19.102991] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10994 06:04:03.791430 <6>[ 19.102991]
10995 06:04:03.899235 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10996 06:04:03.912817 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10997 06:04:03.932161 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10998 06:04:03.945325 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10999 06:04:03.964771 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11000 06:04:03.984808 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11001 06:04:03.996725 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11002 06:04:04.016576 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11003 06:04:04.029202 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11004 06:04:04.044687 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11005 06:04:04.056395 <6>[ 19.371513] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11006 06:04:04.066740 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11007 06:04:04.097586 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11008 06:04:04.125260 Starting [0;1;39mUser Login Management[0m...
11009 06:04:04.143683 Starting [0;1;39mPermit User Sessions[0m...
11010 06:04:04.159167 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11011 06:04:04.181266 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11012 06:04:04.205858 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11013 06:04:04.221395 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11014 06:04:04.273734 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11015 06:04:04.294173 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11016 06:04:04.311286 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11017 06:04:04.331031 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11018 06:04:04.349928 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11019 06:04:04.386647 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11020 06:04:04.425869 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11021 06:04:04.456899
11022 06:04:04.457515
11023 06:04:04.460082 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11024 06:04:04.460647
11025 06:04:04.463739 debian-bullseye-arm64 login: root (automatic login)
11026 06:04:04.464312
11027 06:04:04.464689
11028 06:04:04.479145 Linux debian-bullseye-arm64 6.1.67-cip12 #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023 aarch64
11029 06:04:04.479737
11030 06:04:04.486064 The programs included with the Debian GNU/Linux system are free software;
11031 06:04:04.492464 the exact distribution terms for each program are described in the
11032 06:04:04.495510 individual files in /usr/share/doc/*/copyright.
11033 06:04:04.495986
11034 06:04:04.502423 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11035 06:04:04.505486 permitted by applicable law.
11036 06:04:04.507030 Matched prompt #10: / #
11038 06:04:04.508164 Setting prompt string to ['/ #']
11039 06:04:04.508641 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11041 06:04:04.509768 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11042 06:04:04.510329 start: 2.2.6 expect-shell-connection (timeout 00:03:22) [common]
11043 06:04:04.510740 Setting prompt string to ['/ #']
11044 06:04:04.511099 Forcing a shell prompt, looking for ['/ #']
11046 06:04:04.561989 / #
11047 06:04:04.562688 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11048 06:04:04.563152 Waiting using forced prompt support (timeout 00:02:30)
11049 06:04:04.568609
11050 06:04:04.569548 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11051 06:04:04.570126 start: 2.2.7 export-device-env (timeout 00:03:22) [common]
11052 06:04:04.570639 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11053 06:04:04.571129 end: 2.2 depthcharge-retry (duration 00:01:38) [common]
11054 06:04:04.571599 end: 2 depthcharge-action (duration 00:01:38) [common]
11055 06:04:04.572160 start: 3 lava-test-retry (timeout 00:08:00) [common]
11056 06:04:04.572650 start: 3.1 lava-test-shell (timeout 00:08:00) [common]
11057 06:04:04.573072 Using namespace: common
11059 06:04:04.674390 / # #
11060 06:04:04.675059 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11061 06:04:04.681339 #
11062 06:04:04.682238 Using /lava-12379474
11064 06:04:04.783617 / # export SHELL=/bin/sh
11065 06:04:04.790138 export SHELL=/bin/sh
11067 06:04:04.891811 / # . /lava-12379474/environment
11068 06:04:04.898100 . /lava-12379474/environment
11070 06:04:04.999726 / # /lava-12379474/bin/lava-test-runner /lava-12379474/0
11071 06:04:05.000362 Test shell timeout: 10s (minimum of the action and connection timeout)
11072 06:04:05.002194 <6>[ 20.227543] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11073 06:04:05.006293 /lava-12379474/bin/lava-test-runner /lava-12379474/0
11074 06:04:05.032467 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 20.349498] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 12379474_1.5.2.3.1>
11075 06:04:05.033329 Received signal: <STARTRUN> 0_igt-gpu-panfrost 12379474_1.5.2.3.1
11076 06:04:05.033770 Starting test lava.0_igt-gpu-panfrost (12379474_1.5.2.3.1)
11077 06:04:05.034506 Skipping test definition patterns.
11078 06:04:05.035829 nfrost
11079 06:04:05.039114 + cd /lava-12379474/0/tests/0_igt-gpu-panfrost
11080 06:04:05.039695 + cat uuid
11081 06:04:05.042629 + UUID=12379474_1.5.2.3.1
11082 06:04:05.043205 + set +x
11083 06:04:05.052499 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11084 06:04:05.065884 <8>[ 20.384090] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11085 06:04:05.066782 Received signal: <TESTSET> START panfrost_gem_new
11086 06:04:05.067222 Starting test_set panfrost_gem_new
11087 06:04:05.093621 <14>[ 20.411877] [IGT] panfrost_gem_new: executing
11088 06:04:05.103997 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.420140] [IGT] panfrost_gem_new: exiting, ret=77
11089 06:04:05.104580 .1.67-cip12 aarch64)
11090 06:04:05.116821 Test requirement not met in function drm_open_driver, file<8>[ 20.432059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11091 06:04:05.117671 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11093 06:04:05.120244 ../lib/drmtest.c:621:
11094 06:04:05.120830 Test requirement: !(fd<0)
11095 06:04:05.126704 No known gpu found for chipset flags 0x32 (panfrost)
11096 06:04:05.133418 Last errno: 2, No such file or director<14>[ 20.452281] [IGT] panfrost_gem_new: executing
11097 06:04:05.134041 y
11098 06:04:05.142974 [1mSubtest gem-new-4096: SKI<14>[ 20.459516] [IGT] panfrost_gem_new: exiting, ret=77
11099 06:04:05.143560 P (0.000s)[0m
11100 06:04:05.149517 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11101 06:04:05.156662 Test requi<8>[ 20.472368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11102 06:04:05.157518 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11104 06:04:05.162777 rement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11105 06:04:05.166099 Test requirement: !(fd<0)
11106 06:04:05.169563 No known gpu found for chipset flags 0x32 (panfrost)
11107 06:04:05.172937 Last errno: 2, No such file or directory
11108 06:04:05.179253 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11109 06:04:05.182687 <14>[ 20.502546] [IGT] panfrost_gem_new: executing
11110 06:04:05.192780 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.510322] [IGT] panfrost_gem_new: exiting, ret=77
11111 06:04:05.196196 rch64) (Linux: 6.1.67-cip12 aarch64)
11112 06:04:05.206122 Test requirement not met in function drm_o<8>[ 20.521484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11113 06:04:05.206965 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11115 06:04:05.212640 pen_driver, file ../lib/drmtest.<8>[ 20.531894] <LAVA_SIGNAL_TESTSET STOP>
11116 06:04:05.213121 c:621:
11117 06:04:05.213753 Received signal: <TESTSET> STOP
11118 06:04:05.214200 Closing test_set panfrost_gem_new
11119 06:04:05.216208 Test requirement: !(fd<0)
11120 06:04:05.222430 No known gpu found for chipset flags 0x32 (panfrost)
11121 06:04:05.225828 Last errno: 2, No such file or directory
11122 06:04:05.235638 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m<8>[ 20.551482] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11123 06:04:05.236220
11124 06:04:05.236867 Received signal: <TESTSET> START panfrost_get_param
11125 06:04:05.237248 Starting test_set panfrost_get_param
11126 06:04:05.250730 <14>[ 20.569155] [IGT] panfrost_get_param: executing
11127 06:04:05.260775 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.576295] [IGT] panfrost_get_param: exiting, ret=77
11128 06:04:05.264039 rch64) (Linux: 6.1.67-cip12 aarch64)
11129 06:04:05.273919 Test requirement not met in function drm_o<8>[ 20.588906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11130 06:04:05.274778 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11132 06:04:05.277352 pen_driver, file ../lib/drmtest.c:621:
11133 06:04:05.277828 Test requirement: !(fd<0)
11134 06:04:05.284206 No known gpu found for chipset flags 0x32 (panfrost)
11135 06:04:05.290801 Last errno: 2, No such <14>[ 20.608416] [IGT] panfrost_get_param: executing
11136 06:04:05.293895 file or directory
11137 06:04:05.297296 [1mSubtest b<14>[ 20.615936] [IGT] panfrost_get_param: exiting, ret=77
11138 06:04:05.300716 ase-params: SKIP (0.000s)[0m
11139 06:04:05.313800 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch<8>[ 20.629035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11140 06:04:05.314410 64)
11141 06:04:05.315072 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11143 06:04:05.320678 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11144 06:04:05.323791 Test requirement: !(fd<0)
11145 06:04:05.330877 No known gpu found for chipset<14>[ 20.649300] [IGT] panfrost_get_param: executing
11146 06:04:05.334273 flags 0x32 (panfrost)
11147 06:04:05.340949 Last err<14>[ 20.657016] [IGT] panfrost_get_param: exiting, ret=77
11148 06:04:05.343767 no: 2, No such file or directory
11149 06:04:05.353523 [1mSubtest get-bad-param: SKI<8>[ 20.667650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11150 06:04:05.354118 P (0.000s)[0m
11151 06:04:05.354780 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11153 06:04:05.357180 <8>[ 20.677309] <LAVA_SIGNAL_TESTSET STOP>
11154 06:04:05.358048 Received signal: <TESTSET> STOP
11155 06:04:05.358449 Closing test_set panfrost_get_param
11156 06:04:05.363270 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11157 06:04:05.370416 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11158 06:04:05.379719 Test requirement: !(fd<0<8>[ 20.696319] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11159 06:04:05.380311 )
11160 06:04:05.380950 Received signal: <TESTSET> START panfrost_prime
11161 06:04:05.381327 Starting test_set panfrost_prime
11162 06:04:05.383331 No known gpu found for chipset flags 0x32 (panfrost)
11163 06:04:05.386434 Last errno: 2, No such file or directory
11164 06:04:05.393246 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11165 06:04:05.396626 <14>[ 20.714802] [IGT] panfrost_prime: executing
11166 06:04:05.403231 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.721598] [IGT] panfrost_prime: exiting, ret=77
11167 06:04:05.406362 rch64) (Linux: 6.1.67-cip12 aarch64)
11168 06:04:05.416486 Test requirement not met i<8>[ 20.731938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11169 06:04:05.417339 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11171 06:04:05.422935 n function drm_open_driver, file<8>[ 20.741816] <LAVA_SIGNAL_TESTSET STOP>
11172 06:04:05.423787 Received signal: <TESTSET> STOP
11173 06:04:05.424196 Closing test_set panfrost_prime
11174 06:04:05.426133 ../lib/drmtest.c:621:
11175 06:04:05.429293 Test requirement: !(fd<0)
11176 06:04:05.433003 No known gpu found for chipset flags 0x32 (panfrost)
11177 06:04:05.436246 Last errno: 2, No such file or directory
11178 06:04:05.446174 [1mSubtest gem-prime-import:<8>[ 20.762055] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11179 06:04:05.446750 SKIP (0.000s)[0m
11180 06:04:05.447413 Received signal: <TESTSET> START panfrost_submit
11181 06:04:05.447812 Starting test_set panfrost_submit
11182 06:04:05.461868 <14>[ 20.780397] [IGT] panfrost_submit: executing
11183 06:04:05.468948 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.787258] [IGT] panfrost_submit: exiting, ret=77
11184 06:04:05.472149 rch64) (Linux: 6.1.67-cip12 aarch64)
11185 06:04:05.482304 Test requirement not met i<8>[ 20.797898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11186 06:04:05.483156 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11188 06:04:05.488745 n function drm_open_driver, file ../lib/drmtest.c:621:
11189 06:04:05.489315 Test requirement: !(fd<0)
11190 06:04:05.495183 No known gpu found for chipset flags 0x32 (panfrost)
11191 06:04:05.498545 Last er<14>[ 20.817874] [IGT] panfrost_submit: executing
11192 06:04:05.508371 rno: 2, No such file or director<14>[ 20.824757] [IGT] panfrost_submit: exiting, ret=77
11193 06:04:05.508943 y
11194 06:04:05.511829 [1mSubtest pan-submit: SKIP (0.000s)[0m
11195 06:04:05.521563 IGT-Version: 1.27.<8>[ 20.835567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11196 06:04:05.522442 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11198 06:04:05.525164 1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11199 06:04:05.531696 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11200 06:04:05.538235 Test requi<14>[ 20.856179] [IGT] panfrost_submit: executing
11201 06:04:05.538808 rement: !(fd<0)
11202 06:04:05.544922 No known gpu fo<14>[ 20.863247] [IGT] panfrost_submit: exiting, ret=77
11203 06:04:05.548152 und for chipset flags 0x32 (panfrost)
11204 06:04:05.558532 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11206 06:04:05.561275 Last errno: 2, No such fi<8>[ 20.873965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11207 06:04:05.561763 le or directory
11208 06:04:05.564441 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11209 06:04:05.570957 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11210 06:04:05.578090 Te<14>[ 20.895045] [IGT] panfrost_submit: executing
11211 06:04:05.584644 st requirement not met in functi<14>[ 20.902387] [IGT] panfrost_submit: exiting, ret=77
11212 06:04:05.587640 on drm_open_driver, file ../lib/drmtest.c:621:
11213 06:04:05.597825 Test requirement<8>[ 20.913256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11214 06:04:05.598746 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11216 06:04:05.601076 : !(fd<0)
11217 06:04:05.604363 No known gpu found for chipset flags 0x32 (panfrost)
11218 06:04:05.607604 Last errno: 2, No such file or directory
11219 06:04:05.617690 [1mSubtest pan-submit-error-bad-in-s<14>[ 20.934412] [IGT] panfrost_submit: executing
11220 06:04:05.618312 yncs: SKIP (0.000s)[0m
11221 06:04:05.624466 IGT-Ver<14>[ 20.941812] [IGT] panfrost_submit: exiting, ret=77
11222 06:04:05.630910 sion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11223 06:04:05.637602 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11225 06:04:05.640410 T<8>[ 20.952279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11226 06:04:05.647197 est requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11227 06:04:05.647770 Test requirement: !(fd<0)
11228 06:04:05.657134 No known gpu found for chipset flags<14>[ 20.973905] [IGT] panfrost_submit: executing
11229 06:04:05.657716 0x32 (panfrost)
11230 06:04:05.663455 Last errno: 2,<14>[ 20.981438] [IGT] panfrost_submit: exiting, ret=77
11231 06:04:05.666761 No such file or directory
11232 06:04:05.676907 [1mSubtest pan-submit-error-bad-bo-<8>[ 20.992040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11233 06:04:05.677763 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11235 06:04:05.680038 handles: SKIP (0.000s)[0m
11236 06:04:05.686806 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11237 06:04:05.696912 Test requirement not met in function drm_open_<14>[ 21.013668] [IGT] panfrost_submit: executing
11238 06:04:05.703028 driver, file ../lib/drmtest.c:62<14>[ 21.020634] [IGT] panfrost_submit: exiting, ret=77
11239 06:04:05.703593 1:
11240 06:04:05.706615 Test requirement: !(fd<0)
11241 06:04:05.716932 No known gpu found for chipset fl<8>[ 21.031394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11242 06:04:05.717520 ags 0x32 (panfrost)
11243 06:04:05.718177 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11245 06:04:05.719680 Last errno: 2, No such file or directory
11246 06:04:05.726483 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11247 06:04:05.733493 IGT-Version: 1.<14>[ 21.050689] [IGT] panfrost_submit: executing
11248 06:04:05.739703 27.1-g621c2d3 (aarch64) (Linux: <14>[ 21.058042] [IGT] panfrost_submit: exiting, ret=77
11249 06:04:05.742896 6.1.67-cip12 aarch64)
11250 06:04:05.752903 Test requirement not met in function drm_<8>[ 21.068630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11251 06:04:05.753784 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11253 06:04:05.755836 open_driver, file ../lib/drmtest.c:621:
11254 06:04:05.759569 Test requirement: !(fd<0)
11255 06:04:05.765611 No known gpu found for chipset flags 0x32 (panfrost)
11256 06:04:05.772848 Last errno: 2, No such<14>[ 21.089427] [IGT] panfrost_submit: executing
11257 06:04:05.773440 file or directory
11258 06:04:05.779280 [1mSubtest <14>[ 21.096751] [IGT] panfrost_submit: exiting, ret=77
11259 06:04:05.782486 pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11260 06:04:05.792279 IGT-Version: 1<8>[ 21.107478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11261 06:04:05.793172 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11263 06:04:05.798966 .27.1-g621c2d3 (aarch64) (Linux:<8>[ 21.117630] <LAVA_SIGNAL_TESTSET STOP>
11264 06:04:05.799850 Received signal: <TESTSET> STOP
11265 06:04:05.800279 Closing test_set panfrost_submit
11266 06:04:05.808926 6.1.67-cip12 aa<8>[ 21.123971] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 12379474_1.5.2.3.1>
11267 06:04:05.809532 rch64)
11268 06:04:05.810348 Received signal: <ENDRUN> 0_igt-gpu-panfrost 12379474_1.5.2.3.1
11269 06:04:05.810853 Ending use of test pattern.
11270 06:04:05.811278 Ending test lava.0_igt-gpu-panfrost (12379474_1.5.2.3.1), duration 0.78
11272 06:04:05.815574 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11273 06:04:05.818958 Test requirement: !(fd<0)
11274 06:04:05.821762 No known gpu found for chipset flags 0x32 (panfrost)
11275 06:04:05.825998 Last errno: 2, No such file or directory
11276 06:04:05.828859 [1mSubtest pan-reset: SKIP (0.000s)[0m
11277 06:04:05.835400 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11278 06:04:05.841967 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11279 06:04:05.845214 Test requirement: !(fd<0)
11280 06:04:05.851907 No known gpu found for chipset flags 0x32 (panfrost)
11281 06:04:05.855329 Last errno: 2, No such file or directory
11282 06:04:05.858517 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11283 06:04:05.865085 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12 aarch64)
11284 06:04:05.871991 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11285 06:04:05.874724 Test requirement: !(fd<0)
11286 06:04:05.878230 No known gpu found for chipset flags 0x32 (panfrost)
11287 06:04:05.881698 Last errno: 2, No such file or directory
11288 06:04:05.887970 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11289 06:04:05.888540 + set +x
11290 06:04:05.891885 <LAVA_TEST_RUNNER EXIT>
11291 06:04:05.892744 ok: lava_test_shell seems to have completed
11292 06:04:05.894514 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11293 06:04:05.895065 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11294 06:04:05.895542 end: 3 lava-test-retry (duration 00:00:01) [common]
11295 06:04:05.896038 start: 4 finalize (timeout 00:07:59) [common]
11296 06:04:05.896543 start: 4.1 power-off (timeout 00:00:30) [common]
11297 06:04:05.897360 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11298 06:04:05.984495 >> Command sent successfully.
11299 06:04:05.995639 Returned 0 in 0 seconds
11300 06:04:06.097057 end: 4.1 power-off (duration 00:00:00) [common]
11302 06:04:06.098838 start: 4.2 read-feedback (timeout 00:07:59) [common]
11303 06:04:06.100122 Listened to connection for namespace 'common' for up to 1s
11304 06:04:07.100929 Finalising connection for namespace 'common'
11305 06:04:07.101617 Disconnecting from shell: Finalise
11306 06:04:07.102099 / #
11307 06:04:07.203222 end: 4.2 read-feedback (duration 00:00:01) [common]
11308 06:04:07.203944 end: 4 finalize (duration 00:00:01) [common]
11309 06:04:07.204553 Cleaning after the job
11310 06:04:07.205106 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379474/tftp-deploy-ibdd2s4k/ramdisk
11311 06:04:07.233827 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379474/tftp-deploy-ibdd2s4k/kernel
11312 06:04:07.250606 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379474/tftp-deploy-ibdd2s4k/dtb
11313 06:04:07.250897 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379474/tftp-deploy-ibdd2s4k/modules
11314 06:04:07.259599 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12379474
11315 06:04:07.357329 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12379474
11316 06:04:07.357513 Job finished correctly