Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 17
- Kernel Errors: 35
- Errors: 0
1 06:00:52.337023 lava-dispatcher, installed at version: 2023.10
2 06:00:52.337264 start: 0 validate
3 06:00:52.337429 Start time: 2023-12-25 06:00:52.337420+00:00 (UTC)
4 06:00:52.337619 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:00:52.337898 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Finitrd.cpio.gz exists
6 06:00:52.608614 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:00:52.609365 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:00:52.878159 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:00:52.878921 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:00:53.149261 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:00:53.150152 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:00:53.412491 Using caching service: 'http://localhost/cache/?uri=%s'
13 06:00:53.413311 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 06:00:53.690377 validate duration: 1.35
16 06:00:53.691637 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:00:53.692180 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:00:53.692671 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:00:53.693362 Not decompressing ramdisk as can be used compressed.
20 06:00:53.693827 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/initrd.cpio.gz
21 06:00:53.694181 saving as /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/ramdisk/initrd.cpio.gz
22 06:00:53.694543 total size: 5628325 (5 MB)
23 06:00:53.699859 progress 0 % (0 MB)
24 06:00:53.709209 progress 5 % (0 MB)
25 06:00:53.716392 progress 10 % (0 MB)
26 06:00:53.720802 progress 15 % (0 MB)
27 06:00:53.724878 progress 20 % (1 MB)
28 06:00:53.728035 progress 25 % (1 MB)
29 06:00:53.731077 progress 30 % (1 MB)
30 06:00:53.733836 progress 35 % (1 MB)
31 06:00:53.736104 progress 40 % (2 MB)
32 06:00:53.738492 progress 45 % (2 MB)
33 06:00:53.740497 progress 50 % (2 MB)
34 06:00:53.742687 progress 55 % (2 MB)
35 06:00:53.744656 progress 60 % (3 MB)
36 06:00:53.746425 progress 65 % (3 MB)
37 06:00:53.748318 progress 70 % (3 MB)
38 06:00:53.749912 progress 75 % (4 MB)
39 06:00:53.751685 progress 80 % (4 MB)
40 06:00:53.753187 progress 85 % (4 MB)
41 06:00:53.754814 progress 90 % (4 MB)
42 06:00:53.756426 progress 95 % (5 MB)
43 06:00:53.757864 progress 100 % (5 MB)
44 06:00:53.758067 5 MB downloaded in 0.06 s (84.46 MB/s)
45 06:00:53.758216 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:00:53.758448 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:00:53.758531 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:00:53.758621 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:00:53.758815 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 06:00:53.758884 saving as /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/kernel/Image
52 06:00:53.758943 total size: 50024960 (47 MB)
53 06:00:53.759003 No compression specified
54 06:00:53.760042 progress 0 % (0 MB)
55 06:00:53.772780 progress 5 % (2 MB)
56 06:00:53.785678 progress 10 % (4 MB)
57 06:00:53.798475 progress 15 % (7 MB)
58 06:00:53.811390 progress 20 % (9 MB)
59 06:00:53.824336 progress 25 % (11 MB)
60 06:00:53.837225 progress 30 % (14 MB)
61 06:00:53.850010 progress 35 % (16 MB)
62 06:00:53.862567 progress 40 % (19 MB)
63 06:00:53.875276 progress 45 % (21 MB)
64 06:00:53.888220 progress 50 % (23 MB)
65 06:00:53.901088 progress 55 % (26 MB)
66 06:00:53.913787 progress 60 % (28 MB)
67 06:00:53.926602 progress 65 % (31 MB)
68 06:00:53.939376 progress 70 % (33 MB)
69 06:00:53.952206 progress 75 % (35 MB)
70 06:00:53.964946 progress 80 % (38 MB)
71 06:00:53.977964 progress 85 % (40 MB)
72 06:00:53.990612 progress 90 % (42 MB)
73 06:00:54.003323 progress 95 % (45 MB)
74 06:00:54.015937 progress 100 % (47 MB)
75 06:00:54.016142 47 MB downloaded in 0.26 s (185.49 MB/s)
76 06:00:54.016291 end: 1.2.1 http-download (duration 00:00:00) [common]
78 06:00:54.016519 end: 1.2 download-retry (duration 00:00:00) [common]
79 06:00:54.016603 start: 1.3 download-retry (timeout 00:10:00) [common]
80 06:00:54.016690 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 06:00:54.016888 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 06:00:54.016959 saving as /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/dtb/mt8192-asurada-spherion-r0.dtb
83 06:00:54.017019 total size: 47278 (0 MB)
84 06:00:54.017078 No compression specified
85 06:00:54.018163 progress 69 % (0 MB)
86 06:00:54.018429 progress 100 % (0 MB)
87 06:00:54.018579 0 MB downloaded in 0.00 s (28.93 MB/s)
88 06:00:54.018697 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:00:54.018928 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:00:54.019017 start: 1.4 download-retry (timeout 00:10:00) [common]
92 06:00:54.019096 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 06:00:54.019205 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/full.rootfs.tar.xz
94 06:00:54.019270 saving as /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/nfsrootfs/full.rootfs.tar
95 06:00:54.019326 total size: 198084472 (188 MB)
96 06:00:54.019385 Using unxz to decompress xz
97 06:00:54.023629 progress 0 % (0 MB)
98 06:00:54.578618 progress 5 % (9 MB)
99 06:00:55.067117 progress 10 % (18 MB)
100 06:00:55.648779 progress 15 % (28 MB)
101 06:00:55.933563 progress 20 % (37 MB)
102 06:00:56.391569 progress 25 % (47 MB)
103 06:00:56.962306 progress 30 % (56 MB)
104 06:00:57.515132 progress 35 % (66 MB)
105 06:00:58.070705 progress 40 % (75 MB)
106 06:00:58.644359 progress 45 % (85 MB)
107 06:00:59.243237 progress 50 % (94 MB)
108 06:00:59.845697 progress 55 % (103 MB)
109 06:01:00.496425 progress 60 % (113 MB)
110 06:01:00.866445 progress 65 % (122 MB)
111 06:01:00.958136 progress 70 % (132 MB)
112 06:01:01.098222 progress 75 % (141 MB)
113 06:01:01.173131 progress 80 % (151 MB)
114 06:01:01.222231 progress 85 % (160 MB)
115 06:01:01.316346 progress 90 % (170 MB)
116 06:01:01.674557 progress 95 % (179 MB)
117 06:01:02.255314 progress 100 % (188 MB)
118 06:01:02.259994 188 MB downloaded in 8.24 s (22.92 MB/s)
119 06:01:02.260293 end: 1.4.1 http-download (duration 00:00:08) [common]
121 06:01:02.260697 end: 1.4 download-retry (duration 00:00:08) [common]
122 06:01:02.260860 start: 1.5 download-retry (timeout 00:09:51) [common]
123 06:01:02.260977 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 06:01:02.261168 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 06:01:02.261263 saving as /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/modules/modules.tar
126 06:01:02.261354 total size: 8619328 (8 MB)
127 06:01:02.261445 Using unxz to decompress xz
128 06:01:02.266088 progress 0 % (0 MB)
129 06:01:02.287116 progress 5 % (0 MB)
130 06:01:02.310543 progress 10 % (0 MB)
131 06:01:02.334001 progress 15 % (1 MB)
132 06:01:02.357383 progress 20 % (1 MB)
133 06:01:02.381529 progress 25 % (2 MB)
134 06:01:02.407394 progress 30 % (2 MB)
135 06:01:02.433239 progress 35 % (2 MB)
136 06:01:02.456441 progress 40 % (3 MB)
137 06:01:02.480664 progress 45 % (3 MB)
138 06:01:02.506118 progress 50 % (4 MB)
139 06:01:02.530241 progress 55 % (4 MB)
140 06:01:02.554636 progress 60 % (4 MB)
141 06:01:02.579755 progress 65 % (5 MB)
142 06:01:02.606759 progress 70 % (5 MB)
143 06:01:02.630062 progress 75 % (6 MB)
144 06:01:02.657307 progress 80 % (6 MB)
145 06:01:02.684100 progress 85 % (7 MB)
146 06:01:02.709165 progress 90 % (7 MB)
147 06:01:02.738731 progress 95 % (7 MB)
148 06:01:02.767954 progress 100 % (8 MB)
149 06:01:02.772575 8 MB downloaded in 0.51 s (16.08 MB/s)
150 06:01:02.772827 end: 1.5.1 http-download (duration 00:00:01) [common]
152 06:01:02.773091 end: 1.5 download-retry (duration 00:00:01) [common]
153 06:01:02.773182 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 06:01:02.773280 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 06:01:06.487404 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12379472/extract-nfsrootfs-l133z4kz
156 06:01:06.487613 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 06:01:06.487711 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 06:01:06.487882 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8
159 06:01:06.488016 makedir: /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin
160 06:01:06.488122 makedir: /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/tests
161 06:01:06.488220 makedir: /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/results
162 06:01:06.488322 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-add-keys
163 06:01:06.488466 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-add-sources
164 06:01:06.488596 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-background-process-start
165 06:01:06.489236 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-background-process-stop
166 06:01:06.489374 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-common-functions
167 06:01:06.489502 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-echo-ipv4
168 06:01:06.489633 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-install-packages
169 06:01:06.489760 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-installed-packages
170 06:01:06.489884 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-os-build
171 06:01:06.490008 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-probe-channel
172 06:01:06.490131 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-probe-ip
173 06:01:06.490255 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-target-ip
174 06:01:06.490379 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-target-mac
175 06:01:06.490503 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-target-storage
176 06:01:06.490629 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-test-case
177 06:01:06.490756 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-test-event
178 06:01:06.490881 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-test-feedback
179 06:01:06.491006 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-test-raise
180 06:01:06.491132 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-test-reference
181 06:01:06.491257 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-test-runner
182 06:01:06.491387 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-test-set
183 06:01:06.491514 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-test-shell
184 06:01:06.491643 Updating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-add-keys (debian)
185 06:01:06.491796 Updating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-add-sources (debian)
186 06:01:06.491937 Updating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-install-packages (debian)
187 06:01:06.492077 Updating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-installed-packages (debian)
188 06:01:06.492216 Updating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/bin/lava-os-build (debian)
189 06:01:06.492339 Creating /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/environment
190 06:01:06.492450 LAVA metadata
191 06:01:06.492531 - LAVA_JOB_ID=12379472
192 06:01:06.492634 - LAVA_DISPATCHER_IP=192.168.201.1
193 06:01:06.492816 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 06:01:06.492893 skipped lava-vland-overlay
195 06:01:06.492993 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 06:01:06.493092 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 06:01:06.493200 skipped lava-multinode-overlay
198 06:01:06.493319 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 06:01:06.493441 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 06:01:06.493530 Loading test definitions
201 06:01:06.493666 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 06:01:06.493774 Using /lava-12379472 at stage 0
203 06:01:06.494161 uuid=12379472_1.6.2.3.1 testdef=None
204 06:01:06.494284 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 06:01:06.494411 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 06:01:06.495037 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 06:01:06.495401 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 06:01:06.495975 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 06:01:06.496329 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 06:01:06.497135 runner path: /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/0/tests/0_timesync-off test_uuid 12379472_1.6.2.3.1
213 06:01:06.497327 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 06:01:06.497581 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 06:01:06.497688 Using /lava-12379472 at stage 0
217 06:01:06.497837 Fetching tests from https://github.com/kernelci/test-definitions.git
218 06:01:06.497950 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/0/tests/1_kselftest-alsa'
219 06:01:10.641739 Running '/usr/bin/git checkout kernelci.org
220 06:01:10.788953 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 06:01:10.789704 uuid=12379472_1.6.2.3.5 testdef=None
222 06:01:10.789864 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 06:01:10.790120 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 06:01:10.790877 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 06:01:10.791107 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 06:01:10.792100 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 06:01:10.792331 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 06:01:10.793299 runner path: /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/0/tests/1_kselftest-alsa test_uuid 12379472_1.6.2.3.5
232 06:01:10.793390 BOARD='mt8192-asurada-spherion-r0'
233 06:01:10.793455 BRANCH='cip'
234 06:01:10.793515 SKIPFILE='/dev/null'
235 06:01:10.793573 SKIP_INSTALL='True'
236 06:01:10.793628 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 06:01:10.793687 TST_CASENAME=''
238 06:01:10.793742 TST_CMDFILES='alsa'
239 06:01:10.793885 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 06:01:10.794086 Creating lava-test-runner.conf files
242 06:01:10.794151 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379472/lava-overlay-tywwttx8/lava-12379472/0 for stage 0
243 06:01:10.794242 - 0_timesync-off
244 06:01:10.794312 - 1_kselftest-alsa
245 06:01:10.794409 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 06:01:10.794499 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 06:01:18.278345 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 06:01:18.278502 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 06:01:18.278595 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 06:01:18.278697 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 06:01:18.278787 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 06:01:18.450128 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 06:01:18.450527 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 06:01:18.450739 extracting modules file /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379472/extract-nfsrootfs-l133z4kz
255 06:01:18.669395 extracting modules file /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379472/extract-overlay-ramdisk-7qq4vi_x/ramdisk
256 06:01:18.894262 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 06:01:18.894416 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 06:01:18.894515 [common] Applying overlay to NFS
259 06:01:18.894588 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379472/compress-overlay-wlqjgord/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12379472/extract-nfsrootfs-l133z4kz
260 06:01:19.811537 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 06:01:19.811706 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 06:01:19.811798 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 06:01:19.811887 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 06:01:19.811971 Building ramdisk /var/lib/lava/dispatcher/tmp/12379472/extract-overlay-ramdisk-7qq4vi_x/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12379472/extract-overlay-ramdisk-7qq4vi_x/ramdisk
265 06:01:20.177140 >> 130540 blocks
266 06:01:22.235048 rename /var/lib/lava/dispatcher/tmp/12379472/extract-overlay-ramdisk-7qq4vi_x/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/ramdisk/ramdisk.cpio.gz
267 06:01:22.235506 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 06:01:22.235639 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 06:01:22.235737 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 06:01:22.235848 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/kernel/Image'
271 06:01:34.302136 Returned 0 in 12 seconds
272 06:01:34.403275 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/kernel/image.itb
273 06:01:34.788797 output: FIT description: Kernel Image image with one or more FDT blobs
274 06:01:34.789169 output: Created: Mon Dec 25 06:01:34 2023
275 06:01:34.789244 output: Image 0 (kernel-1)
276 06:01:34.789308 output: Description:
277 06:01:34.789371 output: Created: Mon Dec 25 06:01:34 2023
278 06:01:34.789430 output: Type: Kernel Image
279 06:01:34.789492 output: Compression: lzma compressed
280 06:01:34.789546 output: Data Size: 11481830 Bytes = 11212.72 KiB = 10.95 MiB
281 06:01:34.789603 output: Architecture: AArch64
282 06:01:34.789659 output: OS: Linux
283 06:01:34.789716 output: Load Address: 0x00000000
284 06:01:34.789769 output: Entry Point: 0x00000000
285 06:01:34.789825 output: Hash algo: crc32
286 06:01:34.789881 output: Hash value: a47c00f1
287 06:01:34.789934 output: Image 1 (fdt-1)
288 06:01:34.789987 output: Description: mt8192-asurada-spherion-r0
289 06:01:34.790038 output: Created: Mon Dec 25 06:01:34 2023
290 06:01:34.790090 output: Type: Flat Device Tree
291 06:01:34.790141 output: Compression: uncompressed
292 06:01:34.790191 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 06:01:34.790242 output: Architecture: AArch64
294 06:01:34.790292 output: Hash algo: crc32
295 06:01:34.790342 output: Hash value: cc4352de
296 06:01:34.790393 output: Image 2 (ramdisk-1)
297 06:01:34.790444 output: Description: unavailable
298 06:01:34.790494 output: Created: Mon Dec 25 06:01:34 2023
299 06:01:34.790545 output: Type: RAMDisk Image
300 06:01:34.790596 output: Compression: Unknown Compression
301 06:01:34.790647 output: Data Size: 18763977 Bytes = 18324.20 KiB = 17.89 MiB
302 06:01:34.790698 output: Architecture: AArch64
303 06:01:34.790748 output: OS: Linux
304 06:01:34.790799 output: Load Address: unavailable
305 06:01:34.790849 output: Entry Point: unavailable
306 06:01:34.790900 output: Hash algo: crc32
307 06:01:34.790950 output: Hash value: 61974897
308 06:01:34.791001 output: Default Configuration: 'conf-1'
309 06:01:34.791053 output: Configuration 0 (conf-1)
310 06:01:34.791103 output: Description: mt8192-asurada-spherion-r0
311 06:01:34.791154 output: Kernel: kernel-1
312 06:01:34.791205 output: Init Ramdisk: ramdisk-1
313 06:01:34.791255 output: FDT: fdt-1
314 06:01:34.791306 output: Loadables: kernel-1
315 06:01:34.791356 output:
316 06:01:34.791554 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 06:01:34.791650 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 06:01:34.791749 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 06:01:34.791842 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 06:01:34.791919 No LXC device requested
321 06:01:34.791996 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 06:01:34.792077 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 06:01:34.792155 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 06:01:34.792229 Checking files for TFTP limit of 4294967296 bytes.
325 06:01:34.792751 end: 1 tftp-deploy (duration 00:00:41) [common]
326 06:01:34.792894 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 06:01:34.792981 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 06:01:34.793110 substitutions:
329 06:01:34.793176 - {DTB}: 12379472/tftp-deploy-7wlokvlu/dtb/mt8192-asurada-spherion-r0.dtb
330 06:01:34.793237 - {INITRD}: 12379472/tftp-deploy-7wlokvlu/ramdisk/ramdisk.cpio.gz
331 06:01:34.793295 - {KERNEL}: 12379472/tftp-deploy-7wlokvlu/kernel/Image
332 06:01:34.793351 - {LAVA_MAC}: None
333 06:01:34.793405 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12379472/extract-nfsrootfs-l133z4kz
334 06:01:34.793460 - {NFS_SERVER_IP}: 192.168.201.1
335 06:01:34.793513 - {PRESEED_CONFIG}: None
336 06:01:34.793566 - {PRESEED_LOCAL}: None
337 06:01:34.793619 - {RAMDISK}: 12379472/tftp-deploy-7wlokvlu/ramdisk/ramdisk.cpio.gz
338 06:01:34.793673 - {ROOT_PART}: None
339 06:01:34.793725 - {ROOT}: None
340 06:01:34.793778 - {SERVER_IP}: 192.168.201.1
341 06:01:34.793830 - {TEE}: None
342 06:01:34.793883 Parsed boot commands:
343 06:01:34.793935 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 06:01:34.794118 Parsed boot commands: tftpboot 192.168.201.1 12379472/tftp-deploy-7wlokvlu/kernel/image.itb 12379472/tftp-deploy-7wlokvlu/kernel/cmdline
345 06:01:34.794204 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 06:01:34.794289 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 06:01:34.794380 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 06:01:34.794464 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 06:01:34.794537 Not connected, no need to disconnect.
350 06:01:34.794610 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 06:01:34.794687 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 06:01:34.794756 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 06:01:34.798705 Setting prompt string to ['lava-test: # ']
354 06:01:34.799065 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 06:01:34.799172 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 06:01:34.799273 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 06:01:34.799405 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 06:01:34.799653 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 06:01:39.956059 >> Command sent successfully.
360 06:01:39.967825 Returned 0 in 5 seconds
361 06:01:40.069248 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 06:01:40.070924 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 06:01:40.071499 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 06:01:40.072082 Setting prompt string to 'Starting depthcharge on Spherion...'
366 06:01:40.072470 Changing prompt to 'Starting depthcharge on Spherion...'
367 06:01:40.073052 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 06:01:40.074421 [Enter `^Ec?' for help]
369 06:01:40.243895
370 06:01:40.244555
371 06:01:40.245012 F0: 102B 0000
372 06:01:40.245393
373 06:01:40.245735 F3: 1001 0000 [0200]
374 06:01:40.246063
375 06:01:40.247825 F3: 1001 0000
376 06:01:40.248292
377 06:01:40.248667 F7: 102D 0000
378 06:01:40.249052
379 06:01:40.249380 F1: 0000 0000
380 06:01:40.249703
381 06:01:40.251318 V0: 0000 0000 [0001]
382 06:01:40.251782
383 06:01:40.252148 00: 0007 8000
384 06:01:40.252515
385 06:01:40.255323 01: 0000 0000
386 06:01:40.255912
387 06:01:40.256281 BP: 0C00 0209 [0000]
388 06:01:40.256625
389 06:01:40.256998 G0: 1182 0000
390 06:01:40.257340
391 06:01:40.258557 EC: 0000 0021 [4000]
392 06:01:40.259023
393 06:01:40.263870 S7: 0000 0000 [0000]
394 06:01:40.264436
395 06:01:40.264908 CC: 0000 0000 [0001]
396 06:01:40.265392
397 06:01:40.265747 T0: 0000 0040 [010F]
398 06:01:40.266086
399 06:01:40.266781 Jump to BL
400 06:01:40.267152
401 06:01:40.290513
402 06:01:40.291072
403 06:01:40.291444
404 06:01:40.297141 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 06:01:40.300509 ARM64: Exception handlers installed.
406 06:01:40.304054 ARM64: Testing exception
407 06:01:40.307486 ARM64: Done test exception
408 06:01:40.314164 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 06:01:40.324120 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 06:01:40.331171 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 06:01:40.341315 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 06:01:40.348166 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 06:01:40.358135 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 06:01:40.368855 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 06:01:40.375504 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 06:01:40.393641 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 06:01:40.396839 WDT: Last reset was cold boot
418 06:01:40.400134 SPI1(PAD0) initialized at 2873684 Hz
419 06:01:40.403490 SPI5(PAD0) initialized at 992727 Hz
420 06:01:40.406894 VBOOT: Loading verstage.
421 06:01:40.413491 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 06:01:40.416871 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 06:01:40.420212 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 06:01:40.423714 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 06:01:40.430799 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 06:01:40.437251 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 06:01:40.448469 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 06:01:40.449117
429 06:01:40.449496
430 06:01:40.458177 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 06:01:40.461981 ARM64: Exception handlers installed.
432 06:01:40.464855 ARM64: Testing exception
433 06:01:40.465430 ARM64: Done test exception
434 06:01:40.472035 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 06:01:40.475037 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 06:01:40.489377 Probing TPM: . done!
437 06:01:40.489954 TPM ready after 0 ms
438 06:01:40.495782 Connected to device vid:did:rid of 1ae0:0028:00
439 06:01:40.505803 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 06:01:40.545597 Initialized TPM device CR50 revision 0
441 06:01:40.557178 tlcl_send_startup: Startup return code is 0
442 06:01:40.557754 TPM: setup succeeded
443 06:01:40.568677 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 06:01:40.577595 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 06:01:40.587229 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 06:01:40.596415 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 06:01:40.600036 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 06:01:40.603308 in-header: 03 07 00 00 08 00 00 00
449 06:01:40.606510 in-data: aa e4 47 04 13 02 00 00
450 06:01:40.609717 Chrome EC: UHEPI supported
451 06:01:40.616803 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 06:01:40.619939 in-header: 03 9d 00 00 08 00 00 00
453 06:01:40.622822 in-data: 10 20 20 08 00 00 00 00
454 06:01:40.623291 Phase 1
455 06:01:40.629744 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 06:01:40.636472 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 06:01:40.639654 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 06:01:40.643266 Recovery requested (1009000e)
459 06:01:40.647340 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 06:01:40.655768 tlcl_extend: response is 0
461 06:01:40.664300 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 06:01:40.669907 tlcl_extend: response is 0
463 06:01:40.676039 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 06:01:40.697008 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 06:01:40.703466 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 06:01:40.704063
467 06:01:40.704445
468 06:01:40.713645 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 06:01:40.716759 ARM64: Exception handlers installed.
470 06:01:40.720104 ARM64: Testing exception
471 06:01:40.720685 ARM64: Done test exception
472 06:01:40.742690 pmic_efuse_setting: Set efuses in 11 msecs
473 06:01:40.745809 pmwrap_interface_init: Select PMIF_VLD_RDY
474 06:01:40.752869 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 06:01:40.756421 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 06:01:40.760314 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 06:01:40.767929 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 06:01:40.771037 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 06:01:40.775106 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 06:01:40.782101 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 06:01:40.784852 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 06:01:40.788240 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 06:01:40.795028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 06:01:40.798381 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 06:01:40.804947 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 06:01:40.808654 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 06:01:40.815062 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 06:01:40.821630 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 06:01:40.824870 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 06:01:40.832296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 06:01:40.839490 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 06:01:40.842736 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 06:01:40.849621 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 06:01:40.852899 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 06:01:40.859484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 06:01:40.866260 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 06:01:40.869193 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 06:01:40.876372 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 06:01:40.882777 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 06:01:40.886178 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 06:01:40.892868 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 06:01:40.895906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 06:01:40.902541 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 06:01:40.906009 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 06:01:40.912668 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 06:01:40.915585 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 06:01:40.922506 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 06:01:40.925925 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 06:01:40.932452 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 06:01:40.935789 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 06:01:40.942387 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 06:01:40.945387 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 06:01:40.949038 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 06:01:40.955447 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 06:01:40.959021 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 06:01:40.962413 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 06:01:40.969078 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 06:01:40.972146 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 06:01:40.975419 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 06:01:40.979267 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 06:01:40.985656 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 06:01:40.988684 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 06:01:40.992390 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 06:01:40.995480 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 06:01:41.005507 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 06:01:41.012281 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 06:01:41.019102 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 06:01:41.025711 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 06:01:41.035554 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 06:01:41.039066 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 06:01:41.045758 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 06:01:41.048514 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 06:01:41.055517 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 06:01:41.062251 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 06:01:41.065336 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 06:01:41.068781 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 06:01:41.079373 [RTC]rtc_get_frequency_meter,154: input=15, output=764
538 06:01:41.089268 [RTC]rtc_get_frequency_meter,154: input=23, output=948
539 06:01:41.098633 [RTC]rtc_get_frequency_meter,154: input=19, output=854
540 06:01:41.108076 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 06:01:41.117698 [RTC]rtc_get_frequency_meter,154: input=16, output=786
542 06:01:41.126766 [RTC]rtc_get_frequency_meter,154: input=16, output=787
543 06:01:41.136998 [RTC]rtc_get_frequency_meter,154: input=17, output=810
544 06:01:41.140022 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 06:01:41.147147 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 06:01:41.150459 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 06:01:41.153706 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 06:01:41.160281 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 06:01:41.163715 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 06:01:41.167030 ADC[4]: Raw value=669695 ID=5
551 06:01:41.167538 ADC[3]: Raw value=212549 ID=1
552 06:01:41.170431 RAM Code: 0x51
553 06:01:41.173593 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 06:01:41.179969 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 06:01:41.186935 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 06:01:41.193538 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 06:01:41.196927 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 06:01:41.200082 in-header: 03 07 00 00 08 00 00 00
559 06:01:41.203527 in-data: aa e4 47 04 13 02 00 00
560 06:01:41.206794 Chrome EC: UHEPI supported
561 06:01:41.213322 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 06:01:41.216560 in-header: 03 d5 00 00 08 00 00 00
563 06:01:41.219792 in-data: 98 20 60 08 00 00 00 00
564 06:01:41.223237 MRC: failed to locate region type 0.
565 06:01:41.229884 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 06:01:41.230465 DRAM-K: Running full calibration
567 06:01:41.236619 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 06:01:41.239765 header.status = 0x0
569 06:01:41.243406 header.version = 0x6 (expected: 0x6)
570 06:01:41.246744 header.size = 0xd00 (expected: 0xd00)
571 06:01:41.247315 header.flags = 0x0
572 06:01:41.253201 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 06:01:41.271752 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 06:01:41.278212 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 06:01:41.281643 dram_init: ddr_geometry: 0
576 06:01:41.282223 [EMI] MDL number = 0
577 06:01:41.285020 [EMI] Get MDL freq = 0
578 06:01:41.288373 dram_init: ddr_type: 0
579 06:01:41.288888 is_discrete_lpddr4: 1
580 06:01:41.291917 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 06:01:41.292386
582 06:01:41.292814
583 06:01:41.295537 [Bian_co] ETT version 0.0.0.1
584 06:01:41.298923 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 06:01:41.299490
586 06:01:41.305599 dramc_set_vcore_voltage set vcore to 650000
587 06:01:41.306153 Read voltage for 800, 4
588 06:01:41.308670 Vio18 = 0
589 06:01:41.309184 Vcore = 650000
590 06:01:41.309560 Vdram = 0
591 06:01:41.309905 Vddq = 0
592 06:01:41.312142 Vmddr = 0
593 06:01:41.312611 dram_init: config_dvfs: 1
594 06:01:41.319097 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 06:01:41.325434 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 06:01:41.329002 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 06:01:41.332159 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 06:01:41.335665 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 06:01:41.338571 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 06:01:41.342406 MEM_TYPE=3, freq_sel=18
601 06:01:41.345700 sv_algorithm_assistance_LP4_1600
602 06:01:41.348931 ============ PULL DRAM RESETB DOWN ============
603 06:01:41.352135 ========== PULL DRAM RESETB DOWN end =========
604 06:01:41.358808 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 06:01:41.362177 ===================================
606 06:01:41.362752 LPDDR4 DRAM CONFIGURATION
607 06:01:41.365246 ===================================
608 06:01:41.368619 EX_ROW_EN[0] = 0x0
609 06:01:41.372169 EX_ROW_EN[1] = 0x0
610 06:01:41.372806 LP4Y_EN = 0x0
611 06:01:41.375301 WORK_FSP = 0x0
612 06:01:41.375770 WL = 0x2
613 06:01:41.378481 RL = 0x2
614 06:01:41.378953 BL = 0x2
615 06:01:41.381857 RPST = 0x0
616 06:01:41.382325 RD_PRE = 0x0
617 06:01:41.385108 WR_PRE = 0x1
618 06:01:41.385579 WR_PST = 0x0
619 06:01:41.388930 DBI_WR = 0x0
620 06:01:41.389404 DBI_RD = 0x0
621 06:01:41.391804 OTF = 0x1
622 06:01:41.395333 ===================================
623 06:01:41.398507 ===================================
624 06:01:41.398979 ANA top config
625 06:01:41.401850 ===================================
626 06:01:41.405358 DLL_ASYNC_EN = 0
627 06:01:41.408986 ALL_SLAVE_EN = 1
628 06:01:41.409547 NEW_RANK_MODE = 1
629 06:01:41.411830 DLL_IDLE_MODE = 1
630 06:01:41.415489 LP45_APHY_COMB_EN = 1
631 06:01:41.418707 TX_ODT_DIS = 1
632 06:01:41.422145 NEW_8X_MODE = 1
633 06:01:41.425453 ===================================
634 06:01:41.426156 ===================================
635 06:01:41.428658 data_rate = 1600
636 06:01:41.432258 CKR = 1
637 06:01:41.435449 DQ_P2S_RATIO = 8
638 06:01:41.438916 ===================================
639 06:01:41.442370 CA_P2S_RATIO = 8
640 06:01:41.445246 DQ_CA_OPEN = 0
641 06:01:41.445716 DQ_SEMI_OPEN = 0
642 06:01:41.448568 CA_SEMI_OPEN = 0
643 06:01:41.452394 CA_FULL_RATE = 0
644 06:01:41.455602 DQ_CKDIV4_EN = 1
645 06:01:41.458914 CA_CKDIV4_EN = 1
646 06:01:41.462221 CA_PREDIV_EN = 0
647 06:01:41.462843 PH8_DLY = 0
648 06:01:41.465192 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 06:01:41.468748 DQ_AAMCK_DIV = 4
650 06:01:41.472190 CA_AAMCK_DIV = 4
651 06:01:41.475033 CA_ADMCK_DIV = 4
652 06:01:41.478478 DQ_TRACK_CA_EN = 0
653 06:01:41.481767 CA_PICK = 800
654 06:01:41.482243 CA_MCKIO = 800
655 06:01:41.485061 MCKIO_SEMI = 0
656 06:01:41.488529 PLL_FREQ = 3068
657 06:01:41.491856 DQ_UI_PI_RATIO = 32
658 06:01:41.495066 CA_UI_PI_RATIO = 0
659 06:01:41.498702 ===================================
660 06:01:41.501669 ===================================
661 06:01:41.505106 memory_type:LPDDR4
662 06:01:41.505577 GP_NUM : 10
663 06:01:41.508522 SRAM_EN : 1
664 06:01:41.509034 MD32_EN : 0
665 06:01:41.511836 ===================================
666 06:01:41.515158 [ANA_INIT] >>>>>>>>>>>>>>
667 06:01:41.518429 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 06:01:41.521563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 06:01:41.525168 ===================================
670 06:01:41.528540 data_rate = 1600,PCW = 0X7600
671 06:01:41.532006 ===================================
672 06:01:41.535068 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 06:01:41.538460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 06:01:41.545372 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 06:01:41.551892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 06:01:41.555208 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 06:01:41.558249 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 06:01:41.558824 [ANA_INIT] flow start
679 06:01:41.561541 [ANA_INIT] PLL >>>>>>>>
680 06:01:41.565317 [ANA_INIT] PLL <<<<<<<<
681 06:01:41.565904 [ANA_INIT] MIDPI >>>>>>>>
682 06:01:41.568335 [ANA_INIT] MIDPI <<<<<<<<
683 06:01:41.571935 [ANA_INIT] DLL >>>>>>>>
684 06:01:41.572515 [ANA_INIT] flow end
685 06:01:41.578248 ============ LP4 DIFF to SE enter ============
686 06:01:41.581436 ============ LP4 DIFF to SE exit ============
687 06:01:41.581911 [ANA_INIT] <<<<<<<<<<<<<
688 06:01:41.584881 [Flow] Enable top DCM control >>>>>
689 06:01:41.588664 [Flow] Enable top DCM control <<<<<
690 06:01:41.591433 Enable DLL master slave shuffle
691 06:01:41.598218 ==============================================================
692 06:01:41.598777 Gating Mode config
693 06:01:41.604761 ==============================================================
694 06:01:41.608088 Config description:
695 06:01:41.618153 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 06:01:41.625026 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 06:01:41.628280 SELPH_MODE 0: By rank 1: By Phase
698 06:01:41.634986 ==============================================================
699 06:01:41.638451 GAT_TRACK_EN = 1
700 06:01:41.641789 RX_GATING_MODE = 2
701 06:01:41.642362 RX_GATING_TRACK_MODE = 2
702 06:01:41.644928 SELPH_MODE = 1
703 06:01:41.648095 PICG_EARLY_EN = 1
704 06:01:41.651560 VALID_LAT_VALUE = 1
705 06:01:41.658447 ==============================================================
706 06:01:41.661673 Enter into Gating configuration >>>>
707 06:01:41.665014 Exit from Gating configuration <<<<
708 06:01:41.668475 Enter into DVFS_PRE_config >>>>>
709 06:01:41.678184 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 06:01:41.681478 Exit from DVFS_PRE_config <<<<<
711 06:01:41.685093 Enter into PICG configuration >>>>
712 06:01:41.687892 Exit from PICG configuration <<<<
713 06:01:41.691081 [RX_INPUT] configuration >>>>>
714 06:01:41.694691 [RX_INPUT] configuration <<<<<
715 06:01:41.698031 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 06:01:41.704954 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 06:01:41.711693 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 06:01:41.715084 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 06:01:41.721294 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 06:01:41.728225 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 06:01:41.731353 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 06:01:41.734702 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 06:01:41.741321 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 06:01:41.744654 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 06:01:41.748096 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 06:01:41.754719 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 06:01:41.757555 ===================================
728 06:01:41.758031 LPDDR4 DRAM CONFIGURATION
729 06:01:41.761555 ===================================
730 06:01:41.764627 EX_ROW_EN[0] = 0x0
731 06:01:41.767881 EX_ROW_EN[1] = 0x0
732 06:01:41.768449 LP4Y_EN = 0x0
733 06:01:41.770923 WORK_FSP = 0x0
734 06:01:41.771394 WL = 0x2
735 06:01:41.774405 RL = 0x2
736 06:01:41.774877 BL = 0x2
737 06:01:41.777628 RPST = 0x0
738 06:01:41.778124 RD_PRE = 0x0
739 06:01:41.781348 WR_PRE = 0x1
740 06:01:41.781822 WR_PST = 0x0
741 06:01:41.784527 DBI_WR = 0x0
742 06:01:41.785165 DBI_RD = 0x0
743 06:01:41.788296 OTF = 0x1
744 06:01:41.791435 ===================================
745 06:01:41.794435 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 06:01:41.797891 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 06:01:41.804635 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 06:01:41.807990 ===================================
749 06:01:41.808562 LPDDR4 DRAM CONFIGURATION
750 06:01:41.811331 ===================================
751 06:01:41.814416 EX_ROW_EN[0] = 0x10
752 06:01:41.814917 EX_ROW_EN[1] = 0x0
753 06:01:41.817776 LP4Y_EN = 0x0
754 06:01:41.818249 WORK_FSP = 0x0
755 06:01:41.820996 WL = 0x2
756 06:01:41.821467 RL = 0x2
757 06:01:41.824612 BL = 0x2
758 06:01:41.827829 RPST = 0x0
759 06:01:41.828299 RD_PRE = 0x0
760 06:01:41.831405 WR_PRE = 0x1
761 06:01:41.831976 WR_PST = 0x0
762 06:01:41.834673 DBI_WR = 0x0
763 06:01:41.835147 DBI_RD = 0x0
764 06:01:41.838014 OTF = 0x1
765 06:01:41.841067 ===================================
766 06:01:41.844785 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 06:01:41.850004 nWR fixed to 40
768 06:01:41.853116 [ModeRegInit_LP4] CH0 RK0
769 06:01:41.853590 [ModeRegInit_LP4] CH0 RK1
770 06:01:41.856880 [ModeRegInit_LP4] CH1 RK0
771 06:01:41.859855 [ModeRegInit_LP4] CH1 RK1
772 06:01:41.860420 match AC timing 12
773 06:01:41.866661 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 06:01:41.869782 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 06:01:41.873462 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 06:01:41.879769 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 06:01:41.883258 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 06:01:41.883836 [EMI DOE] emi_dcm 0
779 06:01:41.889869 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 06:01:41.890445 ==
781 06:01:41.892959 Dram Type= 6, Freq= 0, CH_0, rank 0
782 06:01:41.896447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 06:01:41.896978 ==
784 06:01:41.902903 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 06:01:41.909530 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 06:01:41.917186 [CA 0] Center 37 (7~68) winsize 62
787 06:01:41.920671 [CA 1] Center 37 (7~68) winsize 62
788 06:01:41.923898 [CA 2] Center 35 (5~66) winsize 62
789 06:01:41.927133 [CA 3] Center 35 (5~66) winsize 62
790 06:01:41.930323 [CA 4] Center 34 (3~65) winsize 63
791 06:01:41.933971 [CA 5] Center 33 (3~64) winsize 62
792 06:01:41.934598
793 06:01:41.937443 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 06:01:41.938016
795 06:01:41.940545 [CATrainingPosCal] consider 1 rank data
796 06:01:41.943516 u2DelayCellTimex100 = 270/100 ps
797 06:01:41.947243 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 06:01:41.950399 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 06:01:41.957274 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 06:01:41.960424 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
801 06:01:41.963820 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 06:01:41.967101 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 06:01:41.967673
804 06:01:41.970112 CA PerBit enable=1, Macro0, CA PI delay=33
805 06:01:41.970581
806 06:01:41.973430 [CBTSetCACLKResult] CA Dly = 33
807 06:01:41.973894 CS Dly: 5 (0~36)
808 06:01:41.977051 ==
809 06:01:41.980393 Dram Type= 6, Freq= 0, CH_0, rank 1
810 06:01:41.983733 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 06:01:41.984200 ==
812 06:01:41.987067 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 06:01:41.993756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 06:01:42.003283 [CA 0] Center 37 (7~68) winsize 62
815 06:01:42.006675 [CA 1] Center 37 (6~68) winsize 63
816 06:01:42.009703 [CA 2] Center 35 (4~66) winsize 63
817 06:01:42.012955 [CA 3] Center 35 (4~66) winsize 63
818 06:01:42.016449 [CA 4] Center 34 (4~64) winsize 61
819 06:01:42.020014 [CA 5] Center 34 (3~65) winsize 63
820 06:01:42.020574
821 06:01:42.023148 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 06:01:42.023613
823 06:01:42.026231 [CATrainingPosCal] consider 2 rank data
824 06:01:42.029965 u2DelayCellTimex100 = 270/100 ps
825 06:01:42.032931 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 06:01:42.036619 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 06:01:42.043208 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 06:01:42.046577 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
829 06:01:42.049823 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
830 06:01:42.052837 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 06:01:42.053319
832 06:01:42.056421 CA PerBit enable=1, Macro0, CA PI delay=33
833 06:01:42.057040
834 06:01:42.059767 [CBTSetCACLKResult] CA Dly = 33
835 06:01:42.060231 CS Dly: 5 (0~37)
836 06:01:42.063158
837 06:01:42.066238 ----->DramcWriteLeveling(PI) begin...
838 06:01:42.066712 ==
839 06:01:42.069755 Dram Type= 6, Freq= 0, CH_0, rank 0
840 06:01:42.072909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 06:01:42.073381 ==
842 06:01:42.076250 Write leveling (Byte 0): 30 => 30
843 06:01:42.080023 Write leveling (Byte 1): 30 => 30
844 06:01:42.082965 DramcWriteLeveling(PI) end<-----
845 06:01:42.083533
846 06:01:42.083906 ==
847 06:01:42.086212 Dram Type= 6, Freq= 0, CH_0, rank 0
848 06:01:42.089699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 06:01:42.090270 ==
850 06:01:42.092863 [Gating] SW mode calibration
851 06:01:42.099652 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 06:01:42.106312 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 06:01:42.109477 0 6 0 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
854 06:01:42.112953 0 6 4 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (0 0)
855 06:01:42.119554 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 06:01:42.123030 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 06:01:42.126052 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 06:01:42.129680 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 06:01:42.136373 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 06:01:42.139307 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 06:01:42.142803 0 7 0 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (0 0)
862 06:01:42.149361 0 7 4 | B1->B0 | 3d3d 4343 | 0 0 | (0 0) (0 0)
863 06:01:42.152742 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 06:01:42.155925 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 06:01:42.162872 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 06:01:42.165970 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 06:01:42.169374 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 06:01:42.176045 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 06:01:42.179349 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 06:01:42.182597 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
871 06:01:42.189363 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 06:01:42.192426 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 06:01:42.196188 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 06:01:42.202360 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 06:01:42.205578 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 06:01:42.208922 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 06:01:42.215704 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 06:01:42.218906 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 06:01:42.222177 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 06:01:42.228668 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 06:01:42.232281 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 06:01:42.235745 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 06:01:42.242304 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 06:01:42.245413 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 06:01:42.249109 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
886 06:01:42.255787 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 06:01:42.256427 Total UI for P1: 0, mck2ui 16
888 06:01:42.258952 best dqsien dly found for B0: ( 0, 10, 0)
889 06:01:42.262656 Total UI for P1: 0, mck2ui 16
890 06:01:42.265559 best dqsien dly found for B1: ( 0, 10, 0)
891 06:01:42.268965 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
892 06:01:42.275566 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
893 06:01:42.276123
894 06:01:42.279214 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 06:01:42.282347 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
896 06:01:42.285453 [Gating] SW calibration Done
897 06:01:42.285919 ==
898 06:01:42.289594 Dram Type= 6, Freq= 0, CH_0, rank 0
899 06:01:42.292921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 06:01:42.293422 ==
901 06:01:42.293831 RX Vref Scan: 0
902 06:01:42.294179
903 06:01:42.295967 RX Vref 0 -> 0, step: 1
904 06:01:42.296682
905 06:01:42.299327 RX Delay -130 -> 252, step: 16
906 06:01:42.302869 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 06:01:42.306326 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 06:01:42.312655 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 06:01:42.316427 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 06:01:42.319353 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 06:01:42.322704 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 06:01:42.326238 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 06:01:42.329805 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 06:01:42.336288 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
915 06:01:42.339456 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 06:01:42.342655 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 06:01:42.346176 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 06:01:42.352673 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 06:01:42.356222 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 06:01:42.359295 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 06:01:42.362629 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 06:01:42.363207 ==
923 06:01:42.366107 Dram Type= 6, Freq= 0, CH_0, rank 0
924 06:01:42.369103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 06:01:42.372808 ==
926 06:01:42.373394 DQS Delay:
927 06:01:42.373884 DQS0 = 0, DQS1 = 0
928 06:01:42.375796 DQM Delay:
929 06:01:42.376255 DQM0 = 82, DQM1 = 74
930 06:01:42.379467 DQ Delay:
931 06:01:42.380033 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
932 06:01:42.382984 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
933 06:01:42.385939 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
934 06:01:42.389257 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 06:01:42.389785
936 06:01:42.392625
937 06:01:42.393224 ==
938 06:01:42.396126 Dram Type= 6, Freq= 0, CH_0, rank 0
939 06:01:42.399485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 06:01:42.399954 ==
941 06:01:42.400321
942 06:01:42.400661
943 06:01:42.402917 TX Vref Scan disable
944 06:01:42.403598 == TX Byte 0 ==
945 06:01:42.409233 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
946 06:01:42.412897 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
947 06:01:42.413460 == TX Byte 1 ==
948 06:01:42.419484 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
949 06:01:42.422482 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
950 06:01:42.422947 ==
951 06:01:42.426308 Dram Type= 6, Freq= 0, CH_0, rank 0
952 06:01:42.429377 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 06:01:42.429842 ==
954 06:01:42.442648 TX Vref=22, minBit 0, minWin=27, winSum=444
955 06:01:42.446237 TX Vref=24, minBit 0, minWin=27, winSum=446
956 06:01:42.449575 TX Vref=26, minBit 3, minWin=27, winSum=452
957 06:01:42.452480 TX Vref=28, minBit 0, minWin=27, winSum=454
958 06:01:42.455992 TX Vref=30, minBit 4, minWin=27, winSum=454
959 06:01:42.459326 TX Vref=32, minBit 1, minWin=27, winSum=453
960 06:01:42.465930 [TxChooseVref] Worse bit 0, Min win 27, Win sum 454, Final Vref 28
961 06:01:42.466517
962 06:01:42.469352 Final TX Range 1 Vref 28
963 06:01:42.469918
964 06:01:42.470284 ==
965 06:01:42.472688 Dram Type= 6, Freq= 0, CH_0, rank 0
966 06:01:42.475746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 06:01:42.476212 ==
968 06:01:42.476575
969 06:01:42.476973
970 06:01:42.479406 TX Vref Scan disable
971 06:01:42.482719 == TX Byte 0 ==
972 06:01:42.485840 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
973 06:01:42.489124 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
974 06:01:42.492538 == TX Byte 1 ==
975 06:01:42.495958 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
976 06:01:42.499235 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
977 06:01:42.499700
978 06:01:42.502386 [DATLAT]
979 06:01:42.502850 Freq=800, CH0 RK0
980 06:01:42.503220
981 06:01:42.505867 DATLAT Default: 0xa
982 06:01:42.506327 0, 0xFFFF, sum = 0
983 06:01:42.509073 1, 0xFFFF, sum = 0
984 06:01:42.509662 2, 0xFFFF, sum = 0
985 06:01:42.512258 3, 0xFFFF, sum = 0
986 06:01:42.512757 4, 0xFFFF, sum = 0
987 06:01:42.515763 5, 0xFFFF, sum = 0
988 06:01:42.516233 6, 0xFFFF, sum = 0
989 06:01:42.519139 7, 0xFFFF, sum = 0
990 06:01:42.519607 8, 0x0, sum = 1
991 06:01:42.522300 9, 0x0, sum = 2
992 06:01:42.522769 10, 0x0, sum = 3
993 06:01:42.525944 11, 0x0, sum = 4
994 06:01:42.526518 best_step = 9
995 06:01:42.526886
996 06:01:42.527223 ==
997 06:01:42.529212 Dram Type= 6, Freq= 0, CH_0, rank 0
998 06:01:42.535908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 06:01:42.536556 ==
1000 06:01:42.537099 RX Vref Scan: 1
1001 06:01:42.537558
1002 06:01:42.538970 Set Vref Range= 32 -> 127
1003 06:01:42.539447
1004 06:01:42.542451 RX Vref 32 -> 127, step: 1
1005 06:01:42.543026
1006 06:01:42.543521 RX Delay -111 -> 252, step: 8
1007 06:01:42.546059
1008 06:01:42.546658 Set Vref, RX VrefLevel [Byte0]: 32
1009 06:01:42.549024 [Byte1]: 32
1010 06:01:42.553185
1011 06:01:42.553664 Set Vref, RX VrefLevel [Byte0]: 33
1012 06:01:42.556805 [Byte1]: 33
1013 06:01:42.560762
1014 06:01:42.561374 Set Vref, RX VrefLevel [Byte0]: 34
1015 06:01:42.564337 [Byte1]: 34
1016 06:01:42.568904
1017 06:01:42.569466 Set Vref, RX VrefLevel [Byte0]: 35
1018 06:01:42.571755 [Byte1]: 35
1019 06:01:42.576127
1020 06:01:42.576591 Set Vref, RX VrefLevel [Byte0]: 36
1021 06:01:42.579499 [Byte1]: 36
1022 06:01:42.583934
1023 06:01:42.584395 Set Vref, RX VrefLevel [Byte0]: 37
1024 06:01:42.587395 [Byte1]: 37
1025 06:01:42.591528
1026 06:01:42.592006 Set Vref, RX VrefLevel [Byte0]: 38
1027 06:01:42.595073 [Byte1]: 38
1028 06:01:42.599133
1029 06:01:42.599592 Set Vref, RX VrefLevel [Byte0]: 39
1030 06:01:42.602305 [Byte1]: 39
1031 06:01:42.606930
1032 06:01:42.607503 Set Vref, RX VrefLevel [Byte0]: 40
1033 06:01:42.610002 [Byte1]: 40
1034 06:01:42.614719
1035 06:01:42.615278 Set Vref, RX VrefLevel [Byte0]: 41
1036 06:01:42.617573 [Byte1]: 41
1037 06:01:42.622320
1038 06:01:42.622894 Set Vref, RX VrefLevel [Byte0]: 42
1039 06:01:42.625373 [Byte1]: 42
1040 06:01:42.629691
1041 06:01:42.630252 Set Vref, RX VrefLevel [Byte0]: 43
1042 06:01:42.633478 [Byte1]: 43
1043 06:01:42.637486
1044 06:01:42.638186 Set Vref, RX VrefLevel [Byte0]: 44
1045 06:01:42.640937 [Byte1]: 44
1046 06:01:42.645200
1047 06:01:42.645761 Set Vref, RX VrefLevel [Byte0]: 45
1048 06:01:42.648600 [Byte1]: 45
1049 06:01:42.652924
1050 06:01:42.653477 Set Vref, RX VrefLevel [Byte0]: 46
1051 06:01:42.656378 [Byte1]: 46
1052 06:01:42.660505
1053 06:01:42.661095 Set Vref, RX VrefLevel [Byte0]: 47
1054 06:01:42.663793 [Byte1]: 47
1055 06:01:42.668929
1056 06:01:42.669557 Set Vref, RX VrefLevel [Byte0]: 48
1057 06:01:42.671262 [Byte1]: 48
1058 06:01:42.675692
1059 06:01:42.676250 Set Vref, RX VrefLevel [Byte0]: 49
1060 06:01:42.678841 [Byte1]: 49
1061 06:01:42.683379
1062 06:01:42.683939 Set Vref, RX VrefLevel [Byte0]: 50
1063 06:01:42.686633 [Byte1]: 50
1064 06:01:42.691029
1065 06:01:42.691485 Set Vref, RX VrefLevel [Byte0]: 51
1066 06:01:42.694127 [Byte1]: 51
1067 06:01:42.698511
1068 06:01:42.699215 Set Vref, RX VrefLevel [Byte0]: 52
1069 06:01:42.701976 [Byte1]: 52
1070 06:01:42.705949
1071 06:01:42.706420 Set Vref, RX VrefLevel [Byte0]: 53
1072 06:01:42.709359 [Byte1]: 53
1073 06:01:42.713935
1074 06:01:42.714508 Set Vref, RX VrefLevel [Byte0]: 54
1075 06:01:42.717105 [Byte1]: 54
1076 06:01:42.721475
1077 06:01:42.722049 Set Vref, RX VrefLevel [Byte0]: 55
1078 06:01:42.725132 [Byte1]: 55
1079 06:01:42.729019
1080 06:01:42.729479 Set Vref, RX VrefLevel [Byte0]: 56
1081 06:01:42.732774 [Byte1]: 56
1082 06:01:42.737168
1083 06:01:42.737730 Set Vref, RX VrefLevel [Byte0]: 57
1084 06:01:42.740267 [Byte1]: 57
1085 06:01:42.744778
1086 06:01:42.745331 Set Vref, RX VrefLevel [Byte0]: 58
1087 06:01:42.747778 [Byte1]: 58
1088 06:01:42.752293
1089 06:01:42.752899 Set Vref, RX VrefLevel [Byte0]: 59
1090 06:01:42.755361 [Byte1]: 59
1091 06:01:42.759563
1092 06:01:42.760100 Set Vref, RX VrefLevel [Byte0]: 60
1093 06:01:42.763351 [Byte1]: 60
1094 06:01:42.767488
1095 06:01:42.768045 Set Vref, RX VrefLevel [Byte0]: 61
1096 06:01:42.770507 [Byte1]: 61
1097 06:01:42.775282
1098 06:01:42.775837 Set Vref, RX VrefLevel [Byte0]: 62
1099 06:01:42.778081 [Byte1]: 62
1100 06:01:42.782561
1101 06:01:42.783017 Set Vref, RX VrefLevel [Byte0]: 63
1102 06:01:42.785766 [Byte1]: 63
1103 06:01:42.790479
1104 06:01:42.791040 Set Vref, RX VrefLevel [Byte0]: 64
1105 06:01:42.793428 [Byte1]: 64
1106 06:01:42.798139
1107 06:01:42.798744 Set Vref, RX VrefLevel [Byte0]: 65
1108 06:01:42.801234 [Byte1]: 65
1109 06:01:42.805786
1110 06:01:42.806248 Set Vref, RX VrefLevel [Byte0]: 66
1111 06:01:42.809032 [Byte1]: 66
1112 06:01:42.813342
1113 06:01:42.813898 Set Vref, RX VrefLevel [Byte0]: 67
1114 06:01:42.816465 [Byte1]: 67
1115 06:01:42.821117
1116 06:01:42.821676 Set Vref, RX VrefLevel [Byte0]: 68
1117 06:01:42.827465 [Byte1]: 68
1118 06:01:42.828024
1119 06:01:42.830712 Set Vref, RX VrefLevel [Byte0]: 69
1120 06:01:42.834076 [Byte1]: 69
1121 06:01:42.834766
1122 06:01:42.837269 Set Vref, RX VrefLevel [Byte0]: 70
1123 06:01:42.841062 [Byte1]: 70
1124 06:01:42.841627
1125 06:01:42.844672 Set Vref, RX VrefLevel [Byte0]: 71
1126 06:01:42.847591 [Byte1]: 71
1127 06:01:42.851482
1128 06:01:42.852037 Set Vref, RX VrefLevel [Byte0]: 72
1129 06:01:42.854685 [Byte1]: 72
1130 06:01:42.859490
1131 06:01:42.860100 Set Vref, RX VrefLevel [Byte0]: 73
1132 06:01:42.862670 [Byte1]: 73
1133 06:01:42.866812
1134 06:01:42.867386 Set Vref, RX VrefLevel [Byte0]: 74
1135 06:01:42.870152 [Byte1]: 74
1136 06:01:42.874420
1137 06:01:42.874979 Set Vref, RX VrefLevel [Byte0]: 75
1138 06:01:42.877711 [Byte1]: 75
1139 06:01:42.882130
1140 06:01:42.882697 Final RX Vref Byte 0 = 55 to rank0
1141 06:01:42.885195 Final RX Vref Byte 1 = 57 to rank0
1142 06:01:42.888619 Final RX Vref Byte 0 = 55 to rank1
1143 06:01:42.892351 Final RX Vref Byte 1 = 57 to rank1==
1144 06:01:42.895198 Dram Type= 6, Freq= 0, CH_0, rank 0
1145 06:01:42.901833 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1146 06:01:42.902381 ==
1147 06:01:42.902761 DQS Delay:
1148 06:01:42.903100 DQS0 = 0, DQS1 = 0
1149 06:01:42.905299 DQM Delay:
1150 06:01:42.905758 DQM0 = 83, DQM1 = 74
1151 06:01:42.908532 DQ Delay:
1152 06:01:42.911943 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1153 06:01:42.912400 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1154 06:01:42.915416 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1155 06:01:42.921914 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1156 06:01:42.922461
1157 06:01:42.922825
1158 06:01:42.928668 [DQSOSCAuto] RK0, (LSB)MR18= 0x3333, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1159 06:01:42.932137 CH0 RK0: MR19=606, MR18=3333
1160 06:01:42.938618 CH0_RK0: MR19=0x606, MR18=0x3333, DQSOSC=396, MR23=63, INC=94, DEC=62
1161 06:01:42.939188
1162 06:01:42.941778 ----->DramcWriteLeveling(PI) begin...
1163 06:01:42.942247 ==
1164 06:01:42.945172 Dram Type= 6, Freq= 0, CH_0, rank 1
1165 06:01:42.948422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1166 06:01:42.948969 ==
1167 06:01:42.952118 Write leveling (Byte 0): 29 => 29
1168 06:01:42.955174 Write leveling (Byte 1): 29 => 29
1169 06:01:42.958703 DramcWriteLeveling(PI) end<-----
1170 06:01:42.959161
1171 06:01:42.959520 ==
1172 06:01:42.962106 Dram Type= 6, Freq= 0, CH_0, rank 1
1173 06:01:42.965507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1174 06:01:42.966073 ==
1175 06:01:42.968814 [Gating] SW mode calibration
1176 06:01:42.975568 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1177 06:01:42.981750 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1178 06:01:42.985404 0 6 0 | B1->B0 | 3232 3131 | 1 0 | (1 0) (0 0)
1179 06:01:42.988533 0 6 4 | B1->B0 | 2323 2323 | 0 1 | (1 0) (1 0)
1180 06:01:42.995439 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 06:01:42.998763 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 06:01:43.001872 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 06:01:43.008739 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 06:01:43.011759 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 06:01:43.015305 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 06:01:43.022321 0 7 0 | B1->B0 | 2d2d 2c2c | 0 0 | (0 0) (0 0)
1187 06:01:43.025192 0 7 4 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
1188 06:01:43.028784 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 06:01:43.035539 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 06:01:43.038703 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 06:01:43.041947 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 06:01:43.048741 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 06:01:43.051725 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 06:01:43.055031 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1195 06:01:43.058498 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1196 06:01:43.065134 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 06:01:43.068542 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 06:01:43.071945 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 06:01:43.078449 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 06:01:43.081623 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 06:01:43.085227 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 06:01:43.091836 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 06:01:43.094987 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 06:01:43.098401 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 06:01:43.105265 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 06:01:43.108387 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 06:01:43.112035 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 06:01:43.118405 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 06:01:43.121622 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1210 06:01:43.125127 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1211 06:01:43.131299 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 06:01:43.131770 Total UI for P1: 0, mck2ui 16
1213 06:01:43.138245 best dqsien dly found for B0: ( 0, 9, 30)
1214 06:01:43.138805 Total UI for P1: 0, mck2ui 16
1215 06:01:43.145141 best dqsien dly found for B1: ( 0, 10, 0)
1216 06:01:43.148402 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1217 06:01:43.151812 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1218 06:01:43.152370
1219 06:01:43.154536 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1220 06:01:43.158055 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1221 06:01:43.161318 [Gating] SW calibration Done
1222 06:01:43.161783 ==
1223 06:01:43.164621 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 06:01:43.209038 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1225 06:01:43.209600 ==
1226 06:01:43.209965 RX Vref Scan: 0
1227 06:01:43.210305
1228 06:01:43.210625 RX Vref 0 -> 0, step: 1
1229 06:01:43.210941
1230 06:01:43.211253 RX Delay -130 -> 252, step: 16
1231 06:01:43.211923 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1232 06:01:43.212267 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1233 06:01:43.212579 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1234 06:01:43.212955 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1235 06:01:43.213266 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1236 06:01:43.213564 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1237 06:01:43.213863 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1238 06:01:43.214160 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1239 06:01:43.243682 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1240 06:01:43.244245 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1241 06:01:43.244613 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1242 06:01:43.245022 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1243 06:01:43.245705 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1244 06:01:43.246065 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1245 06:01:43.246396 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1246 06:01:43.246712 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1247 06:01:43.247027 ==
1248 06:01:43.247339 Dram Type= 6, Freq= 0, CH_0, rank 1
1249 06:01:43.247705 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1250 06:01:43.248029 ==
1251 06:01:43.248338 DQS Delay:
1252 06:01:43.251068 DQS0 = 0, DQS1 = 0
1253 06:01:43.251527 DQM Delay:
1254 06:01:43.253866 DQM0 = 83, DQM1 = 74
1255 06:01:43.254330 DQ Delay:
1256 06:01:43.257248 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1257 06:01:43.260903 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101
1258 06:01:43.264139 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1259 06:01:43.267520 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1260 06:01:43.268076
1261 06:01:43.268440
1262 06:01:43.268823 ==
1263 06:01:43.270791 Dram Type= 6, Freq= 0, CH_0, rank 1
1264 06:01:43.274612 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1265 06:01:43.275174 ==
1266 06:01:43.277391
1267 06:01:43.277880
1268 06:01:43.278245 TX Vref Scan disable
1269 06:01:43.280796 == TX Byte 0 ==
1270 06:01:43.284190 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1271 06:01:43.287153 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1272 06:01:43.290982 == TX Byte 1 ==
1273 06:01:43.294041 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1274 06:01:43.297343 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1275 06:01:43.297904 ==
1276 06:01:43.300673 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 06:01:43.307270 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1278 06:01:43.307834 ==
1279 06:01:43.319150 TX Vref=22, minBit 2, minWin=27, winSum=449
1280 06:01:43.322430 TX Vref=24, minBit 2, minWin=28, winSum=455
1281 06:01:43.325404 TX Vref=26, minBit 2, minWin=28, winSum=457
1282 06:01:43.328972 TX Vref=28, minBit 2, minWin=28, winSum=457
1283 06:01:43.332437 TX Vref=30, minBit 4, minWin=28, winSum=459
1284 06:01:43.335709 TX Vref=32, minBit 0, minWin=28, winSum=456
1285 06:01:43.342623 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 30
1286 06:01:43.343184
1287 06:01:43.345633 Final TX Range 1 Vref 30
1288 06:01:43.346093
1289 06:01:43.346497 ==
1290 06:01:43.349182 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 06:01:43.352473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1292 06:01:43.353129 ==
1293 06:01:43.353503
1294 06:01:43.355897
1295 06:01:43.356449 TX Vref Scan disable
1296 06:01:43.358977 == TX Byte 0 ==
1297 06:01:43.362162 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1298 06:01:43.365884 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1299 06:01:43.369079 == TX Byte 1 ==
1300 06:01:43.372330 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1301 06:01:43.378696 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1302 06:01:43.379246
1303 06:01:43.379611 [DATLAT]
1304 06:01:43.379947 Freq=800, CH0 RK1
1305 06:01:43.380341
1306 06:01:43.382104 DATLAT Default: 0x9
1307 06:01:43.382573 0, 0xFFFF, sum = 0
1308 06:01:43.385647 1, 0xFFFF, sum = 0
1309 06:01:43.386247 2, 0xFFFF, sum = 0
1310 06:01:43.388636 3, 0xFFFF, sum = 0
1311 06:01:43.389147 4, 0xFFFF, sum = 0
1312 06:01:43.392266 5, 0xFFFF, sum = 0
1313 06:01:43.395425 6, 0xFFFF, sum = 0
1314 06:01:43.395900 7, 0xFFFF, sum = 0
1315 06:01:43.396386 8, 0x0, sum = 1
1316 06:01:43.398941 9, 0x0, sum = 2
1317 06:01:43.399511 10, 0x0, sum = 3
1318 06:01:43.401941 11, 0x0, sum = 4
1319 06:01:43.402406 best_step = 9
1320 06:01:43.402770
1321 06:01:43.403107 ==
1322 06:01:43.405335 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 06:01:43.412371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1324 06:01:43.412972 ==
1325 06:01:43.413349 RX Vref Scan: 0
1326 06:01:43.413689
1327 06:01:43.415460 RX Vref 0 -> 0, step: 1
1328 06:01:43.415918
1329 06:01:43.419014 RX Delay -95 -> 252, step: 8
1330 06:01:43.422388 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1331 06:01:43.425443 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1332 06:01:43.432433 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1333 06:01:43.435698 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1334 06:01:43.438866 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1335 06:01:43.442323 iDelay=217, Bit 5, Center 72 (-47 ~ 192) 240
1336 06:01:43.445329 iDelay=217, Bit 6, Center 96 (-23 ~ 216) 240
1337 06:01:43.449036 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1338 06:01:43.455717 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1339 06:01:43.459284 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1340 06:01:43.462028 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1341 06:01:43.465515 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1342 06:01:43.468855 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1343 06:01:43.475533 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1344 06:01:43.478907 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1345 06:01:43.482209 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1346 06:01:43.482770 ==
1347 06:01:43.485430 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 06:01:43.488943 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1349 06:01:43.492405 ==
1350 06:01:43.493010 DQS Delay:
1351 06:01:43.493390 DQS0 = 0, DQS1 = 0
1352 06:01:43.495464 DQM Delay:
1353 06:01:43.495927 DQM0 = 85, DQM1 = 74
1354 06:01:43.498697 DQ Delay:
1355 06:01:43.499173 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1356 06:01:43.502120 DQ4 =88, DQ5 =72, DQ6 =96, DQ7 =96
1357 06:01:43.505513 DQ8 =64, DQ9 =60, DQ10 =72, DQ11 =64
1358 06:01:43.509039 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1359 06:01:43.509663
1360 06:01:43.510043
1361 06:01:43.518490 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1362 06:01:43.522054 CH0 RK1: MR19=606, MR18=3E3E
1363 06:01:43.528554 CH0_RK1: MR19=0x606, MR18=0x3E3E, DQSOSC=394, MR23=63, INC=95, DEC=63
1364 06:01:43.529068 [RxdqsGatingPostProcess] freq 800
1365 06:01:43.535140 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1366 06:01:43.538802 Pre-setting of DQS Precalculation
1367 06:01:43.541808 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1368 06:01:43.545168 ==
1369 06:01:43.545444 Dram Type= 6, Freq= 0, CH_1, rank 0
1370 06:01:43.551626 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1371 06:01:43.551898 ==
1372 06:01:43.555012 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1373 06:01:43.561519 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1374 06:01:43.571345 [CA 0] Center 37 (6~68) winsize 63
1375 06:01:43.574861 [CA 1] Center 37 (6~68) winsize 63
1376 06:01:43.577845 [CA 2] Center 34 (4~65) winsize 62
1377 06:01:43.581364 [CA 3] Center 34 (4~65) winsize 62
1378 06:01:43.584864 [CA 4] Center 33 (3~64) winsize 62
1379 06:01:43.588188 [CA 5] Center 33 (3~64) winsize 62
1380 06:01:43.588782
1381 06:01:43.591682 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1382 06:01:43.592255
1383 06:01:43.594657 [CATrainingPosCal] consider 1 rank data
1384 06:01:43.598198 u2DelayCellTimex100 = 270/100 ps
1385 06:01:43.601407 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1386 06:01:43.604871 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1387 06:01:43.611559 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1388 06:01:43.614548 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1389 06:01:43.618009 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1390 06:01:43.621332 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1391 06:01:43.621829
1392 06:01:43.624816 CA PerBit enable=1, Macro0, CA PI delay=33
1393 06:01:43.625375
1394 06:01:43.628149 [CBTSetCACLKResult] CA Dly = 33
1395 06:01:43.628700 CS Dly: 5 (0~36)
1396 06:01:43.631409 ==
1397 06:01:43.631974 Dram Type= 6, Freq= 0, CH_1, rank 1
1398 06:01:43.638045 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1399 06:01:43.638612 ==
1400 06:01:43.641069 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1401 06:01:43.648143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1402 06:01:43.657396 [CA 0] Center 37 (6~68) winsize 63
1403 06:01:43.660588 [CA 1] Center 37 (6~68) winsize 63
1404 06:01:43.664455 [CA 2] Center 34 (4~65) winsize 62
1405 06:01:43.667246 [CA 3] Center 34 (4~65) winsize 62
1406 06:01:43.670480 [CA 4] Center 33 (3~64) winsize 62
1407 06:01:43.673768 [CA 5] Center 32 (2~63) winsize 62
1408 06:01:43.674254
1409 06:01:43.677275 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1410 06:01:43.677732
1411 06:01:43.681142 [CATrainingPosCal] consider 2 rank data
1412 06:01:43.683654 u2DelayCellTimex100 = 270/100 ps
1413 06:01:43.687367 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1414 06:01:43.693759 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1415 06:01:43.697056 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1416 06:01:43.700691 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1417 06:01:43.703549 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1418 06:01:43.707047 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1419 06:01:43.707509
1420 06:01:43.710331 CA PerBit enable=1, Macro0, CA PI delay=33
1421 06:01:43.710790
1422 06:01:43.713468 [CBTSetCACLKResult] CA Dly = 33
1423 06:01:43.713929 CS Dly: 5 (0~37)
1424 06:01:43.717124
1425 06:01:43.720468 ----->DramcWriteLeveling(PI) begin...
1426 06:01:43.721104 ==
1427 06:01:43.723750 Dram Type= 6, Freq= 0, CH_1, rank 0
1428 06:01:43.727204 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1429 06:01:43.727763 ==
1430 06:01:43.730199 Write leveling (Byte 0): 24 => 24
1431 06:01:43.733529 Write leveling (Byte 1): 24 => 24
1432 06:01:43.737029 DramcWriteLeveling(PI) end<-----
1433 06:01:43.737585
1434 06:01:43.737952 ==
1435 06:01:43.740395 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 06:01:43.743811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1437 06:01:43.744374 ==
1438 06:01:43.747147 [Gating] SW mode calibration
1439 06:01:43.753825 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1440 06:01:43.760548 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1441 06:01:43.763457 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1442 06:01:43.767449 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 06:01:43.770467 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 06:01:43.777305 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 06:01:43.780410 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 06:01:43.783675 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 06:01:43.790314 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 06:01:43.793247 0 6 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1449 06:01:43.796988 0 7 0 | B1->B0 | 2e2e 4343 | 1 0 | (0 0) (0 0)
1450 06:01:43.803393 0 7 4 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
1451 06:01:43.806686 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1452 06:01:43.810080 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1453 06:01:43.817302 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1454 06:01:43.820130 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1455 06:01:43.823609 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1456 06:01:43.830144 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1457 06:01:43.833567 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1458 06:01:43.836971 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 06:01:43.843525 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 06:01:43.846622 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 06:01:43.850227 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 06:01:43.856969 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 06:01:43.860210 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 06:01:43.863462 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 06:01:43.870146 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 06:01:43.873266 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 06:01:43.876945 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 06:01:43.883489 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 06:01:43.886493 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1470 06:01:43.890190 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1471 06:01:43.893441 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1472 06:01:43.900124 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1473 06:01:43.903257 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1474 06:01:43.906890 Total UI for P1: 0, mck2ui 16
1475 06:01:43.910123 best dqsien dly found for B0: ( 0, 9, 28)
1476 06:01:43.913252 Total UI for P1: 0, mck2ui 16
1477 06:01:43.916509 best dqsien dly found for B1: ( 0, 9, 30)
1478 06:01:43.920270 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1479 06:01:43.923488 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1480 06:01:43.924049
1481 06:01:43.926625 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1482 06:01:43.929919 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1483 06:01:43.933115 [Gating] SW calibration Done
1484 06:01:43.933578 ==
1485 06:01:43.936892 Dram Type= 6, Freq= 0, CH_1, rank 0
1486 06:01:43.943715 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1487 06:01:43.944442 ==
1488 06:01:43.944920 RX Vref Scan: 0
1489 06:01:43.945275
1490 06:01:43.946534 RX Vref 0 -> 0, step: 1
1491 06:01:43.946990
1492 06:01:43.950248 RX Delay -130 -> 252, step: 16
1493 06:01:43.953815 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1494 06:01:43.956890 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1495 06:01:43.959928 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1496 06:01:43.963362 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1497 06:01:43.970395 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1498 06:01:43.973158 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1499 06:01:43.976432 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1500 06:01:43.979948 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1501 06:01:43.983395 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1502 06:01:43.990103 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1503 06:01:43.993104 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1504 06:01:43.996794 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1505 06:01:43.999901 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1506 06:01:44.006423 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1507 06:01:44.009699 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1508 06:01:44.013036 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1509 06:01:44.013497 ==
1510 06:01:44.016829 Dram Type= 6, Freq= 0, CH_1, rank 0
1511 06:01:44.020111 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1512 06:01:44.020694 ==
1513 06:01:44.023284 DQS Delay:
1514 06:01:44.023845 DQS0 = 0, DQS1 = 0
1515 06:01:44.026196 DQM Delay:
1516 06:01:44.026706 DQM0 = 84, DQM1 = 76
1517 06:01:44.027100 DQ Delay:
1518 06:01:44.029794 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1519 06:01:44.032930 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =85
1520 06:01:44.036331 DQ8 =53, DQ9 =69, DQ10 =77, DQ11 =69
1521 06:01:44.039591 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1522 06:01:44.040155
1523 06:01:44.040520
1524 06:01:44.042945 ==
1525 06:01:44.043509 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 06:01:44.049376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1527 06:01:44.049931 ==
1528 06:01:44.050295
1529 06:01:44.050635
1530 06:01:44.053133 TX Vref Scan disable
1531 06:01:44.053769 == TX Byte 0 ==
1532 06:01:44.056384 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1533 06:01:44.062709 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1534 06:01:44.063275 == TX Byte 1 ==
1535 06:01:44.066036 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1536 06:01:44.072830 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1537 06:01:44.073392 ==
1538 06:01:44.076198 Dram Type= 6, Freq= 0, CH_1, rank 0
1539 06:01:44.079145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1540 06:01:44.079611 ==
1541 06:01:44.092457 TX Vref=22, minBit 2, minWin=27, winSum=446
1542 06:01:44.095756 TX Vref=24, minBit 3, minWin=27, winSum=451
1543 06:01:44.099046 TX Vref=26, minBit 3, minWin=27, winSum=452
1544 06:01:44.102245 TX Vref=28, minBit 0, minWin=28, winSum=457
1545 06:01:44.105729 TX Vref=30, minBit 0, minWin=28, winSum=458
1546 06:01:44.112030 TX Vref=32, minBit 0, minWin=28, winSum=457
1547 06:01:44.115965 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
1548 06:01:44.116557
1549 06:01:44.118984 Final TX Range 1 Vref 30
1550 06:01:44.119554
1551 06:01:44.119921 ==
1552 06:01:44.122169 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 06:01:44.125334 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1554 06:01:44.125798 ==
1555 06:01:44.128817
1556 06:01:44.129316
1557 06:01:44.129691 TX Vref Scan disable
1558 06:01:44.132210 == TX Byte 0 ==
1559 06:01:44.135561 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1560 06:01:44.142363 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1561 06:01:44.142936 == TX Byte 1 ==
1562 06:01:44.145474 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1563 06:01:44.152035 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1564 06:01:44.152602
1565 06:01:44.153013 [DATLAT]
1566 06:01:44.153409 Freq=800, CH1 RK0
1567 06:01:44.153758
1568 06:01:44.155513 DATLAT Default: 0xa
1569 06:01:44.156081 0, 0xFFFF, sum = 0
1570 06:01:44.158480 1, 0xFFFF, sum = 0
1571 06:01:44.161999 2, 0xFFFF, sum = 0
1572 06:01:44.162575 3, 0xFFFF, sum = 0
1573 06:01:44.165189 4, 0xFFFF, sum = 0
1574 06:01:44.165651 5, 0xFFFF, sum = 0
1575 06:01:44.168737 6, 0xFFFF, sum = 0
1576 06:01:44.169307 7, 0xFFFF, sum = 0
1577 06:01:44.172016 8, 0x0, sum = 1
1578 06:01:44.172579 9, 0x0, sum = 2
1579 06:01:44.173006 10, 0x0, sum = 3
1580 06:01:44.175036 11, 0x0, sum = 4
1581 06:01:44.175503 best_step = 9
1582 06:01:44.175862
1583 06:01:44.176238 ==
1584 06:01:44.178498 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 06:01:44.185544 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1586 06:01:44.186128 ==
1587 06:01:44.186505 RX Vref Scan: 1
1588 06:01:44.186846
1589 06:01:44.188540 Set Vref Range= 32 -> 127
1590 06:01:44.189049
1591 06:01:44.191901 RX Vref 32 -> 127, step: 1
1592 06:01:44.192548
1593 06:01:44.195075 RX Delay -111 -> 252, step: 8
1594 06:01:44.195532
1595 06:01:44.198593 Set Vref, RX VrefLevel [Byte0]: 32
1596 06:01:44.201673 [Byte1]: 32
1597 06:01:44.202218
1598 06:01:44.204803 Set Vref, RX VrefLevel [Byte0]: 33
1599 06:01:44.208053 [Byte1]: 33
1600 06:01:44.208592
1601 06:01:44.211726 Set Vref, RX VrefLevel [Byte0]: 34
1602 06:01:44.215116 [Byte1]: 34
1603 06:01:44.218258
1604 06:01:44.218715 Set Vref, RX VrefLevel [Byte0]: 35
1605 06:01:44.221890 [Byte1]: 35
1606 06:01:44.226129
1607 06:01:44.226685 Set Vref, RX VrefLevel [Byte0]: 36
1608 06:01:44.229210 [Byte1]: 36
1609 06:01:44.233573
1610 06:01:44.234027 Set Vref, RX VrefLevel [Byte0]: 37
1611 06:01:44.237197 [Byte1]: 37
1612 06:01:44.241652
1613 06:01:44.242207 Set Vref, RX VrefLevel [Byte0]: 38
1614 06:01:44.244826 [Byte1]: 38
1615 06:01:44.249084
1616 06:01:44.249645 Set Vref, RX VrefLevel [Byte0]: 39
1617 06:01:44.252208 [Byte1]: 39
1618 06:01:44.256798
1619 06:01:44.257360 Set Vref, RX VrefLevel [Byte0]: 40
1620 06:01:44.259995 [Byte1]: 40
1621 06:01:44.264320
1622 06:01:44.264928 Set Vref, RX VrefLevel [Byte0]: 41
1623 06:01:44.267871 [Byte1]: 41
1624 06:01:44.271844
1625 06:01:44.272398 Set Vref, RX VrefLevel [Byte0]: 42
1626 06:01:44.275165 [Byte1]: 42
1627 06:01:44.279736
1628 06:01:44.280302 Set Vref, RX VrefLevel [Byte0]: 43
1629 06:01:44.283018 [Byte1]: 43
1630 06:01:44.287179
1631 06:01:44.287747 Set Vref, RX VrefLevel [Byte0]: 44
1632 06:01:44.290443 [Byte1]: 44
1633 06:01:44.294862
1634 06:01:44.295324 Set Vref, RX VrefLevel [Byte0]: 45
1635 06:01:44.298053 [Byte1]: 45
1636 06:01:44.302501
1637 06:01:44.302958 Set Vref, RX VrefLevel [Byte0]: 46
1638 06:01:44.305872 [Byte1]: 46
1639 06:01:44.310274
1640 06:01:44.310738 Set Vref, RX VrefLevel [Byte0]: 47
1641 06:01:44.313279 [Byte1]: 47
1642 06:01:44.317817
1643 06:01:44.318283 Set Vref, RX VrefLevel [Byte0]: 48
1644 06:01:44.321011 [Byte1]: 48
1645 06:01:44.325470
1646 06:01:44.326040 Set Vref, RX VrefLevel [Byte0]: 49
1647 06:01:44.328655 [Byte1]: 49
1648 06:01:44.333371
1649 06:01:44.333932 Set Vref, RX VrefLevel [Byte0]: 50
1650 06:01:44.336377 [Byte1]: 50
1651 06:01:44.341040
1652 06:01:44.341598 Set Vref, RX VrefLevel [Byte0]: 51
1653 06:01:44.344011 [Byte1]: 51
1654 06:01:44.348619
1655 06:01:44.349213 Set Vref, RX VrefLevel [Byte0]: 52
1656 06:01:44.352026 [Byte1]: 52
1657 06:01:44.356161
1658 06:01:44.356758 Set Vref, RX VrefLevel [Byte0]: 53
1659 06:01:44.359499 [Byte1]: 53
1660 06:01:44.363960
1661 06:01:44.364424 Set Vref, RX VrefLevel [Byte0]: 54
1662 06:01:44.367673 [Byte1]: 54
1663 06:01:44.371655
1664 06:01:44.372215 Set Vref, RX VrefLevel [Byte0]: 55
1665 06:01:44.374972 [Byte1]: 55
1666 06:01:44.379152
1667 06:01:44.379930 Set Vref, RX VrefLevel [Byte0]: 56
1668 06:01:44.382246 [Byte1]: 56
1669 06:01:44.386946
1670 06:01:44.387508 Set Vref, RX VrefLevel [Byte0]: 57
1671 06:01:44.389746 [Byte1]: 57
1672 06:01:44.394229
1673 06:01:44.394795 Set Vref, RX VrefLevel [Byte0]: 58
1674 06:01:44.397483 [Byte1]: 58
1675 06:01:44.401771
1676 06:01:44.402233 Set Vref, RX VrefLevel [Byte0]: 59
1677 06:01:44.405508 [Byte1]: 59
1678 06:01:44.409546
1679 06:01:44.410228 Set Vref, RX VrefLevel [Byte0]: 60
1680 06:01:44.412840 [Byte1]: 60
1681 06:01:44.417405
1682 06:01:44.417978 Set Vref, RX VrefLevel [Byte0]: 61
1683 06:01:44.420370 [Byte1]: 61
1684 06:01:44.424918
1685 06:01:44.425479 Set Vref, RX VrefLevel [Byte0]: 62
1686 06:01:44.428321 [Byte1]: 62
1687 06:01:44.432304
1688 06:01:44.435700 Set Vref, RX VrefLevel [Byte0]: 63
1689 06:01:44.439095 [Byte1]: 63
1690 06:01:44.439666
1691 06:01:44.442281 Set Vref, RX VrefLevel [Byte0]: 64
1692 06:01:44.445704 [Byte1]: 64
1693 06:01:44.446287
1694 06:01:44.449097 Set Vref, RX VrefLevel [Byte0]: 65
1695 06:01:44.452460 [Byte1]: 65
1696 06:01:44.455797
1697 06:01:44.456360 Set Vref, RX VrefLevel [Byte0]: 66
1698 06:01:44.459044 [Byte1]: 66
1699 06:01:44.463041
1700 06:01:44.463506 Set Vref, RX VrefLevel [Byte0]: 67
1701 06:01:44.466660 [Byte1]: 67
1702 06:01:44.470848
1703 06:01:44.471416 Set Vref, RX VrefLevel [Byte0]: 68
1704 06:01:44.474261 [Byte1]: 68
1705 06:01:44.478469
1706 06:01:44.479028 Set Vref, RX VrefLevel [Byte0]: 69
1707 06:01:44.481662 [Byte1]: 69
1708 06:01:44.486361
1709 06:01:44.486921 Set Vref, RX VrefLevel [Byte0]: 70
1710 06:01:44.489209 [Byte1]: 70
1711 06:01:44.493530
1712 06:01:44.493986 Set Vref, RX VrefLevel [Byte0]: 71
1713 06:01:44.497075 [Byte1]: 71
1714 06:01:44.501440
1715 06:01:44.501897 Set Vref, RX VrefLevel [Byte0]: 72
1716 06:01:44.504762 [Byte1]: 72
1717 06:01:44.509110
1718 06:01:44.509685 Set Vref, RX VrefLevel [Byte0]: 73
1719 06:01:44.512368 [Byte1]: 73
1720 06:01:44.516855
1721 06:01:44.517415 Set Vref, RX VrefLevel [Byte0]: 74
1722 06:01:44.520061 [Byte1]: 74
1723 06:01:44.524426
1724 06:01:44.525037 Set Vref, RX VrefLevel [Byte0]: 75
1725 06:01:44.527598 [Byte1]: 75
1726 06:01:44.531984
1727 06:01:44.532476 Set Vref, RX VrefLevel [Byte0]: 76
1728 06:01:44.535557 [Byte1]: 76
1729 06:01:44.539505
1730 06:01:44.540064 Set Vref, RX VrefLevel [Byte0]: 77
1731 06:01:44.543025 [Byte1]: 77
1732 06:01:44.547330
1733 06:01:44.547894 Set Vref, RX VrefLevel [Byte0]: 78
1734 06:01:44.550743 [Byte1]: 78
1735 06:01:44.554725
1736 06:01:44.555230 Final RX Vref Byte 0 = 61 to rank0
1737 06:01:44.558376 Final RX Vref Byte 1 = 58 to rank0
1738 06:01:44.561676 Final RX Vref Byte 0 = 61 to rank1
1739 06:01:44.565200 Final RX Vref Byte 1 = 58 to rank1==
1740 06:01:44.568452 Dram Type= 6, Freq= 0, CH_1, rank 0
1741 06:01:44.574616 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1742 06:01:44.575174 ==
1743 06:01:44.575540 DQS Delay:
1744 06:01:44.575873 DQS0 = 0, DQS1 = 0
1745 06:01:44.578094 DQM Delay:
1746 06:01:44.578558 DQM0 = 80, DQM1 = 74
1747 06:01:44.581368 DQ Delay:
1748 06:01:44.584845 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1749 06:01:44.585434 DQ4 =80, DQ5 =88, DQ6 =88, DQ7 =76
1750 06:01:44.588552 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1751 06:01:44.594885 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1752 06:01:44.595453
1753 06:01:44.595819
1754 06:01:44.601604 [DQSOSCAuto] RK0, (LSB)MR18= 0x4848, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1755 06:01:44.604698 CH1 RK0: MR19=606, MR18=4848
1756 06:01:44.611386 CH1_RK0: MR19=0x606, MR18=0x4848, DQSOSC=391, MR23=63, INC=96, DEC=64
1757 06:01:44.611933
1758 06:01:44.614990 ----->DramcWriteLeveling(PI) begin...
1759 06:01:44.615559 ==
1760 06:01:44.618055 Dram Type= 6, Freq= 0, CH_1, rank 1
1761 06:01:44.621645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1762 06:01:44.622208 ==
1763 06:01:44.624950 Write leveling (Byte 0): 25 => 25
1764 06:01:44.628202 Write leveling (Byte 1): 26 => 26
1765 06:01:44.631681 DramcWriteLeveling(PI) end<-----
1766 06:01:44.632351
1767 06:01:44.632777 ==
1768 06:01:44.634920 Dram Type= 6, Freq= 0, CH_1, rank 1
1769 06:01:44.638257 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1770 06:01:44.638866 ==
1771 06:01:44.641461 [Gating] SW mode calibration
1772 06:01:44.648148 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1773 06:01:44.654590 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1774 06:01:44.658027 0 6 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (1 0)
1775 06:01:44.661841 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1776 06:01:44.667995 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1777 06:01:44.671194 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1778 06:01:44.674609 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1779 06:01:44.681347 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1780 06:01:44.684751 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1781 06:01:44.688015 0 6 28 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
1782 06:01:44.694373 0 7 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
1783 06:01:44.697734 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1784 06:01:44.701332 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1785 06:01:44.708082 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1786 06:01:44.711154 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1787 06:01:44.714146 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1788 06:01:44.720841 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1789 06:01:44.724181 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1790 06:01:44.727667 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1791 06:01:44.734171 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 06:01:44.737670 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 06:01:44.740866 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 06:01:44.747931 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1795 06:01:44.751141 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1796 06:01:44.754464 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1797 06:01:44.760834 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1798 06:01:44.764050 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1799 06:01:44.767421 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1800 06:01:44.770727 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1801 06:01:44.777562 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1802 06:01:44.780881 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1803 06:01:44.784047 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1804 06:01:44.790679 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1805 06:01:44.794006 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1806 06:01:44.797137 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1807 06:01:44.800690 Total UI for P1: 0, mck2ui 16
1808 06:01:44.804225 best dqsien dly found for B0: ( 0, 9, 28)
1809 06:01:44.811022 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1810 06:01:44.811630 Total UI for P1: 0, mck2ui 16
1811 06:01:44.817409 best dqsien dly found for B1: ( 0, 10, 0)
1812 06:01:44.820589 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1813 06:01:44.824211 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1814 06:01:44.824830
1815 06:01:44.827616 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1816 06:01:44.830801 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1817 06:01:44.833924 [Gating] SW calibration Done
1818 06:01:44.834388 ==
1819 06:01:44.837255 Dram Type= 6, Freq= 0, CH_1, rank 1
1820 06:01:44.840658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1821 06:01:44.841173 ==
1822 06:01:44.843866 RX Vref Scan: 0
1823 06:01:44.844328
1824 06:01:44.844697 RX Vref 0 -> 0, step: 1
1825 06:01:44.845093
1826 06:01:44.847425 RX Delay -130 -> 252, step: 16
1827 06:01:44.853924 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1828 06:01:44.857371 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1829 06:01:44.860782 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1830 06:01:44.863924 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1831 06:01:44.867308 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1832 06:01:44.873900 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1833 06:01:44.877129 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1834 06:01:44.880913 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1835 06:01:44.883771 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1836 06:01:44.886932 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1837 06:01:44.893926 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1838 06:01:44.897227 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1839 06:01:44.900944 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1840 06:01:44.903823 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1841 06:01:44.906998 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1842 06:01:44.913871 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1843 06:01:44.914420 ==
1844 06:01:44.916934 Dram Type= 6, Freq= 0, CH_1, rank 1
1845 06:01:44.920475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1846 06:01:44.921074 ==
1847 06:01:44.921492 DQS Delay:
1848 06:01:44.923626 DQS0 = 0, DQS1 = 0
1849 06:01:44.924085 DQM Delay:
1850 06:01:44.927290 DQM0 = 86, DQM1 = 74
1851 06:01:44.927929 DQ Delay:
1852 06:01:44.930432 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1853 06:01:44.933594 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1854 06:01:44.937342 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1855 06:01:44.940253 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1856 06:01:44.940790
1857 06:01:44.941159
1858 06:01:44.941505 ==
1859 06:01:44.943647 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 06:01:44.947109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1861 06:01:44.947674 ==
1862 06:01:44.950262
1863 06:01:44.950723
1864 06:01:44.951089 TX Vref Scan disable
1865 06:01:44.953695 == TX Byte 0 ==
1866 06:01:44.956893 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1867 06:01:44.960265 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1868 06:01:44.963778 == TX Byte 1 ==
1869 06:01:44.966663 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1870 06:01:44.970232 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1871 06:01:44.970798 ==
1872 06:01:44.973389 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 06:01:44.980397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1874 06:01:44.981005 ==
1875 06:01:44.991955 TX Vref=22, minBit 8, minWin=27, winSum=449
1876 06:01:44.995219 TX Vref=24, minBit 8, minWin=27, winSum=451
1877 06:01:44.998918 TX Vref=26, minBit 0, minWin=28, winSum=456
1878 06:01:45.001883 TX Vref=28, minBit 8, minWin=27, winSum=455
1879 06:01:45.005177 TX Vref=30, minBit 9, minWin=27, winSum=457
1880 06:01:45.011862 TX Vref=32, minBit 9, minWin=27, winSum=454
1881 06:01:45.015343 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 26
1882 06:01:45.015813
1883 06:01:45.018812 Final TX Range 1 Vref 26
1884 06:01:45.019374
1885 06:01:45.019850 ==
1886 06:01:45.021781 Dram Type= 6, Freq= 0, CH_1, rank 1
1887 06:01:45.025163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1888 06:01:45.025629 ==
1889 06:01:45.028231
1890 06:01:45.028693
1891 06:01:45.029108 TX Vref Scan disable
1892 06:01:45.031907 == TX Byte 0 ==
1893 06:01:45.035129 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1894 06:01:45.041757 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1895 06:01:45.042312 == TX Byte 1 ==
1896 06:01:45.044988 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1897 06:01:45.051641 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1898 06:01:45.052198
1899 06:01:45.052567 [DATLAT]
1900 06:01:45.052950 Freq=800, CH1 RK1
1901 06:01:45.053283
1902 06:01:45.055170 DATLAT Default: 0x9
1903 06:01:45.055630 0, 0xFFFF, sum = 0
1904 06:01:45.058620 1, 0xFFFF, sum = 0
1905 06:01:45.059088 2, 0xFFFF, sum = 0
1906 06:01:45.061680 3, 0xFFFF, sum = 0
1907 06:01:45.062309 4, 0xFFFF, sum = 0
1908 06:01:45.065219 5, 0xFFFF, sum = 0
1909 06:01:45.068871 6, 0xFFFF, sum = 0
1910 06:01:45.069453 7, 0xFFFF, sum = 0
1911 06:01:45.069830 8, 0x0, sum = 1
1912 06:01:45.071773 9, 0x0, sum = 2
1913 06:01:45.072242 10, 0x0, sum = 3
1914 06:01:45.075383 11, 0x0, sum = 4
1915 06:01:45.075954 best_step = 9
1916 06:01:45.076318
1917 06:01:45.076655 ==
1918 06:01:45.078583 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 06:01:45.085012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1920 06:01:45.085562 ==
1921 06:01:45.085934 RX Vref Scan: 0
1922 06:01:45.086335
1923 06:01:45.088240 RX Vref 0 -> 0, step: 1
1924 06:01:45.088735
1925 06:01:45.092051 RX Delay -111 -> 252, step: 8
1926 06:01:45.095362 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1927 06:01:45.098700 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1928 06:01:45.105505 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1929 06:01:45.109108 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1930 06:01:45.111880 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1931 06:01:45.115060 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1932 06:01:45.118627 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1933 06:01:45.125464 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1934 06:01:45.128771 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1935 06:01:45.132008 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1936 06:01:45.135560 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1937 06:01:45.138809 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1938 06:01:45.142202 iDelay=209, Bit 12, Center 88 (-31 ~ 208) 240
1939 06:01:45.148814 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1940 06:01:45.151944 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1941 06:01:45.155201 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1942 06:01:45.155762 ==
1943 06:01:45.158764 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 06:01:45.161559 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1945 06:01:45.165273 ==
1946 06:01:45.165835 DQS Delay:
1947 06:01:45.166207 DQS0 = 0, DQS1 = 0
1948 06:01:45.168326 DQM Delay:
1949 06:01:45.168848 DQM0 = 85, DQM1 = 75
1950 06:01:45.172076 DQ Delay:
1951 06:01:45.174994 DQ0 =84, DQ1 =80, DQ2 =76, DQ3 =84
1952 06:01:45.175492 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
1953 06:01:45.178292 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1954 06:01:45.181665 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =84
1955 06:01:45.185230
1956 06:01:45.185691
1957 06:01:45.191922 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1958 06:01:45.195122 CH1 RK1: MR19=606, MR18=3C3C
1959 06:01:45.201835 CH1_RK1: MR19=0x606, MR18=0x3C3C, DQSOSC=394, MR23=63, INC=95, DEC=63
1960 06:01:45.204913 [RxdqsGatingPostProcess] freq 800
1961 06:01:45.208409 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1962 06:01:45.211897 Pre-setting of DQS Precalculation
1963 06:01:45.218481 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1964 06:01:45.224704 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1965 06:01:45.231549 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1966 06:01:45.232115
1967 06:01:45.232483
1968 06:01:45.234606 [Calibration Summary] 1600 Mbps
1969 06:01:45.235071 CH 0, Rank 0
1970 06:01:45.238184 SW Impedance : PASS
1971 06:01:45.238649 DUTY Scan : NO K
1972 06:01:45.241422 ZQ Calibration : PASS
1973 06:01:45.244598 Jitter Meter : NO K
1974 06:01:45.245138 CBT Training : PASS
1975 06:01:45.248680 Write leveling : PASS
1976 06:01:45.251746 RX DQS gating : PASS
1977 06:01:45.252306 RX DQ/DQS(RDDQC) : PASS
1978 06:01:45.255209 TX DQ/DQS : PASS
1979 06:01:45.258139 RX DATLAT : PASS
1980 06:01:45.258604 RX DQ/DQS(Engine): PASS
1981 06:01:45.261382 TX OE : NO K
1982 06:01:45.261849 All Pass.
1983 06:01:45.262218
1984 06:01:45.264777 CH 0, Rank 1
1985 06:01:45.265254 SW Impedance : PASS
1986 06:01:45.267956 DUTY Scan : NO K
1987 06:01:45.271836 ZQ Calibration : PASS
1988 06:01:45.272396 Jitter Meter : NO K
1989 06:01:45.274845 CBT Training : PASS
1990 06:01:45.278290 Write leveling : PASS
1991 06:01:45.278756 RX DQS gating : PASS
1992 06:01:45.281404 RX DQ/DQS(RDDQC) : PASS
1993 06:01:45.281872 TX DQ/DQS : PASS
1994 06:01:45.284885 RX DATLAT : PASS
1995 06:01:45.288212 RX DQ/DQS(Engine): PASS
1996 06:01:45.288811 TX OE : NO K
1997 06:01:45.291837 All Pass.
1998 06:01:45.292478
1999 06:01:45.292907 CH 1, Rank 0
2000 06:01:45.294908 SW Impedance : PASS
2001 06:01:45.295371 DUTY Scan : NO K
2002 06:01:45.298188 ZQ Calibration : PASS
2003 06:01:45.301430 Jitter Meter : NO K
2004 06:01:45.302056 CBT Training : PASS
2005 06:01:45.304916 Write leveling : PASS
2006 06:01:45.308410 RX DQS gating : PASS
2007 06:01:45.309013 RX DQ/DQS(RDDQC) : PASS
2008 06:01:45.311701 TX DQ/DQS : PASS
2009 06:01:45.314711 RX DATLAT : PASS
2010 06:01:45.315180 RX DQ/DQS(Engine): PASS
2011 06:01:45.318185 TX OE : NO K
2012 06:01:45.318746 All Pass.
2013 06:01:45.319111
2014 06:01:45.321399 CH 1, Rank 1
2015 06:01:45.321863 SW Impedance : PASS
2016 06:01:45.324473 DUTY Scan : NO K
2017 06:01:45.328082 ZQ Calibration : PASS
2018 06:01:45.328649 Jitter Meter : NO K
2019 06:01:45.331845 CBT Training : PASS
2020 06:01:45.332408 Write leveling : PASS
2021 06:01:45.334471 RX DQS gating : PASS
2022 06:01:45.338331 RX DQ/DQS(RDDQC) : PASS
2023 06:01:45.338890 TX DQ/DQS : PASS
2024 06:01:45.341347 RX DATLAT : PASS
2025 06:01:45.344873 RX DQ/DQS(Engine): PASS
2026 06:01:45.345435 TX OE : NO K
2027 06:01:45.347941 All Pass.
2028 06:01:45.348496
2029 06:01:45.348903 DramC Write-DBI off
2030 06:01:45.351339 PER_BANK_REFRESH: Hybrid Mode
2031 06:01:45.354396 TX_TRACKING: ON
2032 06:01:45.357868 [GetDramInforAfterCalByMRR] Vendor 6.
2033 06:01:45.361125 [GetDramInforAfterCalByMRR] Revision 606.
2034 06:01:45.364696 [GetDramInforAfterCalByMRR] Revision 2 0.
2035 06:01:45.365300 MR0 0x3939
2036 06:01:45.365675 MR8 0x1111
2037 06:01:45.368045 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2038 06:01:45.371651
2039 06:01:45.372215 MR0 0x3939
2040 06:01:45.372590 MR8 0x1111
2041 06:01:45.375090 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2042 06:01:45.375716
2043 06:01:45.384583 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2044 06:01:45.388153 [FAST_K] Save calibration result to emmc
2045 06:01:45.391446 [FAST_K] Save calibration result to emmc
2046 06:01:45.394798 dram_init: config_dvfs: 1
2047 06:01:45.398165 dramc_set_vcore_voltage set vcore to 662500
2048 06:01:45.401344 Read voltage for 1200, 2
2049 06:01:45.401810 Vio18 = 0
2050 06:01:45.402181 Vcore = 662500
2051 06:01:45.404739 Vdram = 0
2052 06:01:45.405205 Vddq = 0
2053 06:01:45.405572 Vmddr = 0
2054 06:01:45.411272 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2055 06:01:45.414776 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2056 06:01:45.418089 MEM_TYPE=3, freq_sel=15
2057 06:01:45.421122 sv_algorithm_assistance_LP4_1600
2058 06:01:45.424627 ============ PULL DRAM RESETB DOWN ============
2059 06:01:45.428056 ========== PULL DRAM RESETB DOWN end =========
2060 06:01:45.434360 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2061 06:01:45.437886 ===================================
2062 06:01:45.441334 LPDDR4 DRAM CONFIGURATION
2063 06:01:45.441897 ===================================
2064 06:01:45.444551 EX_ROW_EN[0] = 0x0
2065 06:01:45.448128 EX_ROW_EN[1] = 0x0
2066 06:01:45.448684 LP4Y_EN = 0x0
2067 06:01:45.451110 WORK_FSP = 0x0
2068 06:01:45.451668 WL = 0x4
2069 06:01:45.454743 RL = 0x4
2070 06:01:45.455303 BL = 0x2
2071 06:01:45.458025 RPST = 0x0
2072 06:01:45.458603 RD_PRE = 0x0
2073 06:01:45.461103 WR_PRE = 0x1
2074 06:01:45.461572 WR_PST = 0x0
2075 06:01:45.464471 DBI_WR = 0x0
2076 06:01:45.465069 DBI_RD = 0x0
2077 06:01:45.467819 OTF = 0x1
2078 06:01:45.470899 ===================================
2079 06:01:45.474523 ===================================
2080 06:01:45.475079 ANA top config
2081 06:01:45.477697 ===================================
2082 06:01:45.481218 DLL_ASYNC_EN = 0
2083 06:01:45.484446 ALL_SLAVE_EN = 0
2084 06:01:45.487628 NEW_RANK_MODE = 1
2085 06:01:45.488091 DLL_IDLE_MODE = 1
2086 06:01:45.490966 LP45_APHY_COMB_EN = 1
2087 06:01:45.494728 TX_ODT_DIS = 1
2088 06:01:45.497791 NEW_8X_MODE = 1
2089 06:01:45.501306 ===================================
2090 06:01:45.504688 ===================================
2091 06:01:45.507674 data_rate = 2400
2092 06:01:45.508228 CKR = 1
2093 06:01:45.511112 DQ_P2S_RATIO = 8
2094 06:01:45.514442 ===================================
2095 06:01:45.518107 CA_P2S_RATIO = 8
2096 06:01:45.520922 DQ_CA_OPEN = 0
2097 06:01:45.524261 DQ_SEMI_OPEN = 0
2098 06:01:45.524778 CA_SEMI_OPEN = 0
2099 06:01:45.527570 CA_FULL_RATE = 0
2100 06:01:45.531170 DQ_CKDIV4_EN = 0
2101 06:01:45.534086 CA_CKDIV4_EN = 0
2102 06:01:45.538079 CA_PREDIV_EN = 0
2103 06:01:45.541088 PH8_DLY = 17
2104 06:01:45.541647 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2105 06:01:45.544510 DQ_AAMCK_DIV = 4
2106 06:01:45.547885 CA_AAMCK_DIV = 4
2107 06:01:45.551177 CA_ADMCK_DIV = 4
2108 06:01:45.554185 DQ_TRACK_CA_EN = 0
2109 06:01:45.557663 CA_PICK = 1200
2110 06:01:45.561090 CA_MCKIO = 1200
2111 06:01:45.561653 MCKIO_SEMI = 0
2112 06:01:45.564758 PLL_FREQ = 2366
2113 06:01:45.567502 DQ_UI_PI_RATIO = 32
2114 06:01:45.570662 CA_UI_PI_RATIO = 0
2115 06:01:45.574478 ===================================
2116 06:01:45.577602 ===================================
2117 06:01:45.580982 memory_type:LPDDR4
2118 06:01:45.581537 GP_NUM : 10
2119 06:01:45.584419 SRAM_EN : 1
2120 06:01:45.587711 MD32_EN : 0
2121 06:01:45.591089 ===================================
2122 06:01:45.591649 [ANA_INIT] >>>>>>>>>>>>>>
2123 06:01:45.594290 <<<<<< [CONFIGURE PHASE]: ANA_TX
2124 06:01:45.597429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2125 06:01:45.600771 ===================================
2126 06:01:45.604325 data_rate = 2400,PCW = 0X5b00
2127 06:01:45.607306 ===================================
2128 06:01:45.611106 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2129 06:01:45.617263 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2130 06:01:45.620790 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2131 06:01:45.627200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2132 06:01:45.630861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2133 06:01:45.633928 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2134 06:01:45.634396 [ANA_INIT] flow start
2135 06:01:45.637332 [ANA_INIT] PLL >>>>>>>>
2136 06:01:45.641109 [ANA_INIT] PLL <<<<<<<<
2137 06:01:45.641669 [ANA_INIT] MIDPI >>>>>>>>
2138 06:01:45.643937 [ANA_INIT] MIDPI <<<<<<<<
2139 06:01:45.647216 [ANA_INIT] DLL >>>>>>>>
2140 06:01:45.651010 [ANA_INIT] DLL <<<<<<<<
2141 06:01:45.651565 [ANA_INIT] flow end
2142 06:01:45.653921 ============ LP4 DIFF to SE enter ============
2143 06:01:45.660828 ============ LP4 DIFF to SE exit ============
2144 06:01:45.661438 [ANA_INIT] <<<<<<<<<<<<<
2145 06:01:45.664098 [Flow] Enable top DCM control >>>>>
2146 06:01:45.667642 [Flow] Enable top DCM control <<<<<
2147 06:01:45.670927 Enable DLL master slave shuffle
2148 06:01:45.677525 ==============================================================
2149 06:01:45.678093 Gating Mode config
2150 06:01:45.684204 ==============================================================
2151 06:01:45.687418 Config description:
2152 06:01:45.697455 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2153 06:01:45.703982 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2154 06:01:45.707272 SELPH_MODE 0: By rank 1: By Phase
2155 06:01:45.713843 ==============================================================
2156 06:01:45.717172 GAT_TRACK_EN = 1
2157 06:01:45.717652 RX_GATING_MODE = 2
2158 06:01:45.720171 RX_GATING_TRACK_MODE = 2
2159 06:01:45.724083 SELPH_MODE = 1
2160 06:01:45.727151 PICG_EARLY_EN = 1
2161 06:01:45.730413 VALID_LAT_VALUE = 1
2162 06:01:45.736844 ==============================================================
2163 06:01:45.740638 Enter into Gating configuration >>>>
2164 06:01:45.743747 Exit from Gating configuration <<<<
2165 06:01:45.747333 Enter into DVFS_PRE_config >>>>>
2166 06:01:45.757176 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2167 06:01:45.760503 Exit from DVFS_PRE_config <<<<<
2168 06:01:45.763731 Enter into PICG configuration >>>>
2169 06:01:45.767176 Exit from PICG configuration <<<<
2170 06:01:45.770486 [RX_INPUT] configuration >>>>>
2171 06:01:45.773788 [RX_INPUT] configuration <<<<<
2172 06:01:45.777179 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2173 06:01:45.784038 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2174 06:01:45.790416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2175 06:01:45.793448 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2176 06:01:45.800323 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2177 06:01:45.806943 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2178 06:01:45.810433 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2179 06:01:45.813602 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2180 06:01:45.820373 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2181 06:01:45.823598 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2182 06:01:45.827328 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2183 06:01:45.833282 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2184 06:01:45.836510 ===================================
2185 06:01:45.837031 LPDDR4 DRAM CONFIGURATION
2186 06:01:45.840469 ===================================
2187 06:01:45.843449 EX_ROW_EN[0] = 0x0
2188 06:01:45.844076 EX_ROW_EN[1] = 0x0
2189 06:01:45.846548 LP4Y_EN = 0x0
2190 06:01:45.850203 WORK_FSP = 0x0
2191 06:01:45.850768 WL = 0x4
2192 06:01:45.853335 RL = 0x4
2193 06:01:45.853803 BL = 0x2
2194 06:01:45.856682 RPST = 0x0
2195 06:01:45.857182 RD_PRE = 0x0
2196 06:01:45.860087 WR_PRE = 0x1
2197 06:01:45.860548 WR_PST = 0x0
2198 06:01:45.863411 DBI_WR = 0x0
2199 06:01:45.863875 DBI_RD = 0x0
2200 06:01:45.866839 OTF = 0x1
2201 06:01:45.870142 ===================================
2202 06:01:45.873222 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2203 06:01:45.876545 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2204 06:01:45.880031 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2205 06:01:45.883338 ===================================
2206 06:01:45.887101 LPDDR4 DRAM CONFIGURATION
2207 06:01:45.889950 ===================================
2208 06:01:45.893240 EX_ROW_EN[0] = 0x10
2209 06:01:45.893855 EX_ROW_EN[1] = 0x0
2210 06:01:45.896461 LP4Y_EN = 0x0
2211 06:01:45.896997 WORK_FSP = 0x0
2212 06:01:45.899854 WL = 0x4
2213 06:01:45.900314 RL = 0x4
2214 06:01:45.903297 BL = 0x2
2215 06:01:45.903859 RPST = 0x0
2216 06:01:45.906508 RD_PRE = 0x0
2217 06:01:45.909858 WR_PRE = 0x1
2218 06:01:45.910320 WR_PST = 0x0
2219 06:01:45.913426 DBI_WR = 0x0
2220 06:01:45.913999 DBI_RD = 0x0
2221 06:01:45.916610 OTF = 0x1
2222 06:01:45.919863 ===================================
2223 06:01:45.923362 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2224 06:01:45.926665 ==
2225 06:01:45.927228 Dram Type= 6, Freq= 0, CH_0, rank 0
2226 06:01:45.933114 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2227 06:01:45.933580 ==
2228 06:01:45.936326 [Duty_Offset_Calibration]
2229 06:01:45.937007 B0:0 B1:2 CA:1
2230 06:01:45.937398
2231 06:01:45.939732 [DutyScan_Calibration_Flow] k_type=0
2232 06:01:45.949376
2233 06:01:45.949935 ==CLK 0==
2234 06:01:45.952420 Final CLK duty delay cell = 0
2235 06:01:45.955690 [0] MAX Duty = 5093%(X100), DQS PI = 12
2236 06:01:45.959303 [0] MIN Duty = 4938%(X100), DQS PI = 52
2237 06:01:45.959861 [0] AVG Duty = 5015%(X100)
2238 06:01:45.962622
2239 06:01:45.966187 CH0 CLK Duty spec in!! Max-Min= 155%
2240 06:01:45.969112 [DutyScan_Calibration_Flow] ====Done====
2241 06:01:45.969573
2242 06:01:45.972534 [DutyScan_Calibration_Flow] k_type=1
2243 06:01:45.988702
2244 06:01:45.989300 ==DQS 0 ==
2245 06:01:45.991950 Final DQS duty delay cell = 0
2246 06:01:45.995303 [0] MAX Duty = 5125%(X100), DQS PI = 30
2247 06:01:45.998676 [0] MIN Duty = 5031%(X100), DQS PI = 4
2248 06:01:45.999256 [0] AVG Duty = 5078%(X100)
2249 06:01:46.001750
2250 06:01:46.002210 ==DQS 1 ==
2251 06:01:46.004932 Final DQS duty delay cell = 0
2252 06:01:46.008472 [0] MAX Duty = 5031%(X100), DQS PI = 54
2253 06:01:46.011901 [0] MIN Duty = 4906%(X100), DQS PI = 16
2254 06:01:46.015155 [0] AVG Duty = 4968%(X100)
2255 06:01:46.015618
2256 06:01:46.018257 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2257 06:01:46.018954
2258 06:01:46.021691 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2259 06:01:46.025405 [DutyScan_Calibration_Flow] ====Done====
2260 06:01:46.025966
2261 06:01:46.028435 [DutyScan_Calibration_Flow] k_type=3
2262 06:01:46.045942
2263 06:01:46.046496 ==DQM 0 ==
2264 06:01:46.049094 Final DQM duty delay cell = 0
2265 06:01:46.052241 [0] MAX Duty = 5124%(X100), DQS PI = 20
2266 06:01:46.055795 [0] MIN Duty = 4969%(X100), DQS PI = 40
2267 06:01:46.059148 [0] AVG Duty = 5046%(X100)
2268 06:01:46.059710
2269 06:01:46.060075 ==DQM 1 ==
2270 06:01:46.062176 Final DQM duty delay cell = 4
2271 06:01:46.065765 [4] MAX Duty = 5156%(X100), DQS PI = 50
2272 06:01:46.068698 [4] MIN Duty = 5000%(X100), DQS PI = 18
2273 06:01:46.072231 [4] AVG Duty = 5078%(X100)
2274 06:01:46.072685
2275 06:01:46.075674 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2276 06:01:46.076382
2277 06:01:46.079003 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2278 06:01:46.082350 [DutyScan_Calibration_Flow] ====Done====
2279 06:01:46.082913
2280 06:01:46.085430 [DutyScan_Calibration_Flow] k_type=2
2281 06:01:46.101076
2282 06:01:46.101678 ==DQ 0 ==
2283 06:01:46.104235 Final DQ duty delay cell = -4
2284 06:01:46.107211 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2285 06:01:46.110965 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2286 06:01:46.113953 [-4] AVG Duty = 4937%(X100)
2287 06:01:46.114429
2288 06:01:46.114790 ==DQ 1 ==
2289 06:01:46.117158 Final DQ duty delay cell = -4
2290 06:01:46.120400 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2291 06:01:46.123917 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2292 06:01:46.127346 [-4] AVG Duty = 4984%(X100)
2293 06:01:46.127904
2294 06:01:46.130595 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2295 06:01:46.131058
2296 06:01:46.133732 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2297 06:01:46.137210 [DutyScan_Calibration_Flow] ====Done====
2298 06:01:46.137732 ==
2299 06:01:46.141031 Dram Type= 6, Freq= 0, CH_1, rank 0
2300 06:01:46.143835 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2301 06:01:46.144393 ==
2302 06:01:46.147184 [Duty_Offset_Calibration]
2303 06:01:46.147740 B0:0 B1:5 CA:-5
2304 06:01:46.148107
2305 06:01:46.150380 [DutyScan_Calibration_Flow] k_type=0
2306 06:01:46.161464
2307 06:01:46.162022 ==CLK 0==
2308 06:01:46.164573 Final CLK duty delay cell = 0
2309 06:01:46.168143 [0] MAX Duty = 5094%(X100), DQS PI = 24
2310 06:01:46.171760 [0] MIN Duty = 4876%(X100), DQS PI = 52
2311 06:01:46.172315 [0] AVG Duty = 4985%(X100)
2312 06:01:46.174681
2313 06:01:46.178078 CH1 CLK Duty spec in!! Max-Min= 218%
2314 06:01:46.181150 [DutyScan_Calibration_Flow] ====Done====
2315 06:01:46.181610
2316 06:01:46.184611 [DutyScan_Calibration_Flow] k_type=1
2317 06:01:46.199991
2318 06:01:46.200555 ==DQS 0 ==
2319 06:01:46.203350 Final DQS duty delay cell = 0
2320 06:01:46.206405 [0] MAX Duty = 5125%(X100), DQS PI = 16
2321 06:01:46.209633 [0] MIN Duty = 4875%(X100), DQS PI = 40
2322 06:01:46.213182 [0] AVG Duty = 5000%(X100)
2323 06:01:46.213738
2324 06:01:46.214104 ==DQS 1 ==
2325 06:01:46.216354 Final DQS duty delay cell = -4
2326 06:01:46.219628 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2327 06:01:46.223042 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2328 06:01:46.226775 [-4] AVG Duty = 4953%(X100)
2329 06:01:46.227341
2330 06:01:46.229446 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2331 06:01:46.229903
2332 06:01:46.232837 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2333 06:01:46.236240 [DutyScan_Calibration_Flow] ====Done====
2334 06:01:46.236694
2335 06:01:46.239780 [DutyScan_Calibration_Flow] k_type=3
2336 06:01:46.255304
2337 06:01:46.255863 ==DQM 0 ==
2338 06:01:46.258132 Final DQM duty delay cell = -4
2339 06:01:46.261675 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2340 06:01:46.264828 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2341 06:01:46.268337 [-4] AVG Duty = 4969%(X100)
2342 06:01:46.269012
2343 06:01:46.269392 ==DQM 1 ==
2344 06:01:46.271887 Final DQM duty delay cell = -4
2345 06:01:46.274841 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2346 06:01:46.278146 [-4] MIN Duty = 4906%(X100), DQS PI = 58
2347 06:01:46.281664 [-4] AVG Duty = 5000%(X100)
2348 06:01:46.282222
2349 06:01:46.284995 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2350 06:01:46.285566
2351 06:01:46.288271 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2352 06:01:46.291786 [DutyScan_Calibration_Flow] ====Done====
2353 06:01:46.292342
2354 06:01:46.294725 [DutyScan_Calibration_Flow] k_type=2
2355 06:01:46.312134
2356 06:01:46.312687 ==DQ 0 ==
2357 06:01:46.315392 Final DQ duty delay cell = 0
2358 06:01:46.318851 [0] MAX Duty = 5062%(X100), DQS PI = 0
2359 06:01:46.322311 [0] MIN Duty = 4969%(X100), DQS PI = 42
2360 06:01:46.322773 [0] AVG Duty = 5015%(X100)
2361 06:01:46.323136
2362 06:01:46.325397 ==DQ 1 ==
2363 06:01:46.328623 Final DQ duty delay cell = 0
2364 06:01:46.332114 [0] MAX Duty = 5031%(X100), DQS PI = 8
2365 06:01:46.335172 [0] MIN Duty = 4876%(X100), DQS PI = 30
2366 06:01:46.335625 [0] AVG Duty = 4953%(X100)
2367 06:01:46.335980
2368 06:01:46.338521 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2369 06:01:46.338990
2370 06:01:46.342013 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2371 06:01:46.348867 [DutyScan_Calibration_Flow] ====Done====
2372 06:01:46.351860 nWR fixed to 30
2373 06:01:46.352414 [ModeRegInit_LP4] CH0 RK0
2374 06:01:46.355296 [ModeRegInit_LP4] CH0 RK1
2375 06:01:46.358506 [ModeRegInit_LP4] CH1 RK0
2376 06:01:46.358962 [ModeRegInit_LP4] CH1 RK1
2377 06:01:46.361803 match AC timing 6
2378 06:01:46.365171 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2379 06:01:46.368687 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2380 06:01:46.375368 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2381 06:01:46.378754 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2382 06:01:46.385039 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2383 06:01:46.385527 ==
2384 06:01:46.388249 Dram Type= 6, Freq= 0, CH_0, rank 0
2385 06:01:46.391980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2386 06:01:46.392534 ==
2387 06:01:46.398323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2388 06:01:46.401679 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2389 06:01:46.412026 [CA 0] Center 39 (9~70) winsize 62
2390 06:01:46.414981 [CA 1] Center 39 (8~70) winsize 63
2391 06:01:46.418393 [CA 2] Center 36 (5~67) winsize 63
2392 06:01:46.421755 [CA 3] Center 35 (4~66) winsize 63
2393 06:01:46.425044 [CA 4] Center 34 (3~65) winsize 63
2394 06:01:46.428628 [CA 5] Center 33 (3~64) winsize 62
2395 06:01:46.429234
2396 06:01:46.431835 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2397 06:01:46.432292
2398 06:01:46.435198 [CATrainingPosCal] consider 1 rank data
2399 06:01:46.438117 u2DelayCellTimex100 = 270/100 ps
2400 06:01:46.441699 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2401 06:01:46.448549 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2402 06:01:46.451725 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2403 06:01:46.454866 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2404 06:01:46.458235 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2405 06:01:46.461689 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2406 06:01:46.462146
2407 06:01:46.464835 CA PerBit enable=1, Macro0, CA PI delay=33
2408 06:01:46.465294
2409 06:01:46.468256 [CBTSetCACLKResult] CA Dly = 33
2410 06:01:46.468877 CS Dly: 7 (0~38)
2411 06:01:46.471468 ==
2412 06:01:46.474886 Dram Type= 6, Freq= 0, CH_0, rank 1
2413 06:01:46.478209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2414 06:01:46.478763 ==
2415 06:01:46.481362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2416 06:01:46.488061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2417 06:01:46.497655 [CA 0] Center 39 (8~70) winsize 63
2418 06:01:46.500525 [CA 1] Center 38 (8~69) winsize 62
2419 06:01:46.504130 [CA 2] Center 36 (5~67) winsize 63
2420 06:01:46.507105 [CA 3] Center 35 (4~66) winsize 63
2421 06:01:46.510771 [CA 4] Center 33 (3~64) winsize 62
2422 06:01:46.513999 [CA 5] Center 34 (3~65) winsize 63
2423 06:01:46.514557
2424 06:01:46.517323 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2425 06:01:46.517879
2426 06:01:46.520416 [CATrainingPosCal] consider 2 rank data
2427 06:01:46.523720 u2DelayCellTimex100 = 270/100 ps
2428 06:01:46.526999 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2429 06:01:46.530369 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2430 06:01:46.536990 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2431 06:01:46.540813 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2432 06:01:46.544261 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2433 06:01:46.547294 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2434 06:01:46.547843
2435 06:01:46.550680 CA PerBit enable=1, Macro0, CA PI delay=33
2436 06:01:46.551238
2437 06:01:46.553737 [CBTSetCACLKResult] CA Dly = 33
2438 06:01:46.554194 CS Dly: 7 (0~39)
2439 06:01:46.554556
2440 06:01:46.557232 ----->DramcWriteLeveling(PI) begin...
2441 06:01:46.560592 ==
2442 06:01:46.563994 Dram Type= 6, Freq= 0, CH_0, rank 0
2443 06:01:46.567008 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2444 06:01:46.567474 ==
2445 06:01:46.570523 Write leveling (Byte 0): 27 => 27
2446 06:01:46.574246 Write leveling (Byte 1): 26 => 26
2447 06:01:46.577467 DramcWriteLeveling(PI) end<-----
2448 06:01:46.578150
2449 06:01:46.578525 ==
2450 06:01:46.580444 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 06:01:46.583719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2452 06:01:46.584177 ==
2453 06:01:46.587269 [Gating] SW mode calibration
2454 06:01:46.593829 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2455 06:01:46.600451 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2456 06:01:46.603806 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2457 06:01:46.607163 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2458 06:01:46.610622 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2459 06:01:46.617425 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2460 06:01:46.621137 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2461 06:01:46.624080 0 11 20 | B1->B0 | 3131 2c2c | 1 0 | (1 0) (0 0)
2462 06:01:46.630406 0 11 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2463 06:01:46.633794 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2464 06:01:46.637201 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2465 06:01:46.643612 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2466 06:01:46.647196 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2467 06:01:46.650397 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2468 06:01:46.656918 0 12 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2469 06:01:46.660496 0 12 20 | B1->B0 | 3a3a 3d3d | 1 0 | (0 0) (0 0)
2470 06:01:46.663535 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2471 06:01:46.670235 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2472 06:01:46.673676 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2473 06:01:46.676959 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2474 06:01:46.683606 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2475 06:01:46.686947 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2476 06:01:46.689994 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2477 06:01:46.696877 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2478 06:01:46.700456 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2479 06:01:46.703494 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 06:01:46.710201 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 06:01:46.713609 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 06:01:46.716814 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2483 06:01:46.720289 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2484 06:01:46.726627 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2485 06:01:46.729976 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2486 06:01:46.733207 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2487 06:01:46.740258 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2488 06:01:46.743656 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2489 06:01:46.747138 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2490 06:01:46.753708 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2491 06:01:46.757039 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2492 06:01:46.760326 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2493 06:01:46.766988 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2494 06:01:46.767552 Total UI for P1: 0, mck2ui 16
2495 06:01:46.773698 best dqsien dly found for B0: ( 0, 15, 18)
2496 06:01:46.777100 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2497 06:01:46.780269 Total UI for P1: 0, mck2ui 16
2498 06:01:46.783543 best dqsien dly found for B1: ( 0, 15, 20)
2499 06:01:46.786701 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2500 06:01:46.790120 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2501 06:01:46.790583
2502 06:01:46.793626 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2503 06:01:46.796940 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2504 06:01:46.800267 [Gating] SW calibration Done
2505 06:01:46.800864 ==
2506 06:01:46.803729 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 06:01:46.806631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2508 06:01:46.810126 ==
2509 06:01:46.810713 RX Vref Scan: 0
2510 06:01:46.811084
2511 06:01:46.813467 RX Vref 0 -> 0, step: 1
2512 06:01:46.813923
2513 06:01:46.816808 RX Delay -40 -> 252, step: 8
2514 06:01:46.819926 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2515 06:01:46.823611 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2516 06:01:46.826736 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2517 06:01:46.829968 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2518 06:01:46.836568 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2519 06:01:46.840109 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2520 06:01:46.843752 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2521 06:01:46.846919 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2522 06:01:46.850371 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2523 06:01:46.853554 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2524 06:01:46.860119 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2525 06:01:46.863514 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2526 06:01:46.868181 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2527 06:01:46.870260 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2528 06:01:46.873349 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2529 06:01:46.880557 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2530 06:01:46.881144 ==
2531 06:01:46.883274 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 06:01:46.886626 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2533 06:01:46.887091 ==
2534 06:01:46.887455 DQS Delay:
2535 06:01:46.890013 DQS0 = 0, DQS1 = 0
2536 06:01:46.890471 DQM Delay:
2537 06:01:46.893409 DQM0 = 116, DQM1 = 106
2538 06:01:46.893869 DQ Delay:
2539 06:01:46.896992 DQ0 =111, DQ1 =115, DQ2 =119, DQ3 =111
2540 06:01:46.900423 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2541 06:01:46.903774 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2542 06:01:46.906929 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =119
2543 06:01:46.907430
2544 06:01:46.907795
2545 06:01:46.909984 ==
2546 06:01:46.913631 Dram Type= 6, Freq= 0, CH_0, rank 0
2547 06:01:46.916775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2548 06:01:46.917243 ==
2549 06:01:46.917609
2550 06:01:46.917951
2551 06:01:46.920080 TX Vref Scan disable
2552 06:01:46.920541 == TX Byte 0 ==
2553 06:01:46.923373 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2554 06:01:46.930349 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2555 06:01:46.930814 == TX Byte 1 ==
2556 06:01:46.933289 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2557 06:01:46.940241 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2558 06:01:46.940990 ==
2559 06:01:46.943537 Dram Type= 6, Freq= 0, CH_0, rank 0
2560 06:01:46.946606 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2561 06:01:46.947172 ==
2562 06:01:46.958555 TX Vref=22, minBit 9, minWin=25, winSum=417
2563 06:01:46.962168 TX Vref=24, minBit 10, minWin=24, winSum=422
2564 06:01:46.965609 TX Vref=26, minBit 10, minWin=25, winSum=430
2565 06:01:46.968587 TX Vref=28, minBit 8, minWin=26, winSum=430
2566 06:01:46.971978 TX Vref=30, minBit 8, minWin=26, winSum=431
2567 06:01:46.978685 TX Vref=32, minBit 8, minWin=26, winSum=431
2568 06:01:46.982027 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 30
2569 06:01:46.982490
2570 06:01:46.985300 Final TX Range 1 Vref 30
2571 06:01:46.985766
2572 06:01:46.986132 ==
2573 06:01:46.988934 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 06:01:46.991903 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2575 06:01:46.992365 ==
2576 06:01:46.995398
2577 06:01:46.995857
2578 06:01:46.996221 TX Vref Scan disable
2579 06:01:46.998486 == TX Byte 0 ==
2580 06:01:47.002281 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2581 06:01:47.005193 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2582 06:01:47.008780 == TX Byte 1 ==
2583 06:01:47.012082 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2584 06:01:47.015381 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2585 06:01:47.015925
2586 06:01:47.018925 [DATLAT]
2587 06:01:47.019483 Freq=1200, CH0 RK0
2588 06:01:47.019853
2589 06:01:47.022354 DATLAT Default: 0xd
2590 06:01:47.022917 0, 0xFFFF, sum = 0
2591 06:01:47.025403 1, 0xFFFF, sum = 0
2592 06:01:47.025872 2, 0xFFFF, sum = 0
2593 06:01:47.028472 3, 0xFFFF, sum = 0
2594 06:01:47.028978 4, 0xFFFF, sum = 0
2595 06:01:47.032140 5, 0xFFFF, sum = 0
2596 06:01:47.032614 6, 0xFFFF, sum = 0
2597 06:01:47.035154 7, 0xFFFF, sum = 0
2598 06:01:47.038616 8, 0xFFFF, sum = 0
2599 06:01:47.039085 9, 0xFFFF, sum = 0
2600 06:01:47.042187 10, 0xFFFF, sum = 0
2601 06:01:47.042750 11, 0x0, sum = 1
2602 06:01:47.043125 12, 0x0, sum = 2
2603 06:01:47.045305 13, 0x0, sum = 3
2604 06:01:47.045775 14, 0x0, sum = 4
2605 06:01:47.048803 best_step = 12
2606 06:01:47.049267
2607 06:01:47.049633 ==
2608 06:01:47.052071 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 06:01:47.055346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2610 06:01:47.055816 ==
2611 06:01:47.058803 RX Vref Scan: 1
2612 06:01:47.059262
2613 06:01:47.059623 Set Vref Range= 32 -> 127
2614 06:01:47.061940
2615 06:01:47.062397 RX Vref 32 -> 127, step: 1
2616 06:01:47.062766
2617 06:01:47.065305 RX Delay -21 -> 252, step: 4
2618 06:01:47.065896
2619 06:01:47.068629 Set Vref, RX VrefLevel [Byte0]: 32
2620 06:01:47.071974 [Byte1]: 32
2621 06:01:47.072436
2622 06:01:47.075336 Set Vref, RX VrefLevel [Byte0]: 33
2623 06:01:47.078671 [Byte1]: 33
2624 06:01:47.083191
2625 06:01:47.083648 Set Vref, RX VrefLevel [Byte0]: 34
2626 06:01:47.086280 [Byte1]: 34
2627 06:01:47.091173
2628 06:01:47.091658 Set Vref, RX VrefLevel [Byte0]: 35
2629 06:01:47.094515 [Byte1]: 35
2630 06:01:47.099088
2631 06:01:47.099546 Set Vref, RX VrefLevel [Byte0]: 36
2632 06:01:47.102118 [Byte1]: 36
2633 06:01:47.107163
2634 06:01:47.107768 Set Vref, RX VrefLevel [Byte0]: 37
2635 06:01:47.110359 [Byte1]: 37
2636 06:01:47.114964
2637 06:01:47.115518 Set Vref, RX VrefLevel [Byte0]: 38
2638 06:01:47.118411 [Byte1]: 38
2639 06:01:47.122770
2640 06:01:47.123318 Set Vref, RX VrefLevel [Byte0]: 39
2641 06:01:47.126056 [Byte1]: 39
2642 06:01:47.131090
2643 06:01:47.131707 Set Vref, RX VrefLevel [Byte0]: 40
2644 06:01:47.133863 [Byte1]: 40
2645 06:01:47.138714
2646 06:01:47.139185 Set Vref, RX VrefLevel [Byte0]: 41
2647 06:01:47.142054 [Byte1]: 41
2648 06:01:47.146358
2649 06:01:47.146819 Set Vref, RX VrefLevel [Byte0]: 42
2650 06:01:47.149905 [Byte1]: 42
2651 06:01:47.154837
2652 06:01:47.155407 Set Vref, RX VrefLevel [Byte0]: 43
2653 06:01:47.157639 [Byte1]: 43
2654 06:01:47.162692
2655 06:01:47.163248 Set Vref, RX VrefLevel [Byte0]: 44
2656 06:01:47.165728 [Byte1]: 44
2657 06:01:47.170125
2658 06:01:47.170597 Set Vref, RX VrefLevel [Byte0]: 45
2659 06:01:47.173849 [Byte1]: 45
2660 06:01:47.178207
2661 06:01:47.178761 Set Vref, RX VrefLevel [Byte0]: 46
2662 06:01:47.181295 [Byte1]: 46
2663 06:01:47.186260
2664 06:01:47.186818 Set Vref, RX VrefLevel [Byte0]: 47
2665 06:01:47.189439 [Byte1]: 47
2666 06:01:47.193866
2667 06:01:47.194326 Set Vref, RX VrefLevel [Byte0]: 48
2668 06:01:47.197249 [Byte1]: 48
2669 06:01:47.201899
2670 06:01:47.202457 Set Vref, RX VrefLevel [Byte0]: 49
2671 06:01:47.205568 [Byte1]: 49
2672 06:01:47.210000
2673 06:01:47.210558 Set Vref, RX VrefLevel [Byte0]: 50
2674 06:01:47.213274 [Byte1]: 50
2675 06:01:47.217904
2676 06:01:47.218465 Set Vref, RX VrefLevel [Byte0]: 51
2677 06:01:47.221187 [Byte1]: 51
2678 06:01:47.225727
2679 06:01:47.226190 Set Vref, RX VrefLevel [Byte0]: 52
2680 06:01:47.229320 [Byte1]: 52
2681 06:01:47.233709
2682 06:01:47.234317 Set Vref, RX VrefLevel [Byte0]: 53
2683 06:01:47.236969 [Byte1]: 53
2684 06:01:47.241871
2685 06:01:47.242427 Set Vref, RX VrefLevel [Byte0]: 54
2686 06:01:47.244821 [Byte1]: 54
2687 06:01:47.249605
2688 06:01:47.250194 Set Vref, RX VrefLevel [Byte0]: 55
2689 06:01:47.253040 [Byte1]: 55
2690 06:01:47.257714
2691 06:01:47.258303 Set Vref, RX VrefLevel [Byte0]: 56
2692 06:01:47.260786 [Byte1]: 56
2693 06:01:47.265365
2694 06:01:47.265826 Set Vref, RX VrefLevel [Byte0]: 57
2695 06:01:47.268957 [Byte1]: 57
2696 06:01:47.273608
2697 06:01:47.274167 Set Vref, RX VrefLevel [Byte0]: 58
2698 06:01:47.276610 [Byte1]: 58
2699 06:01:47.281181
2700 06:01:47.281609 Set Vref, RX VrefLevel [Byte0]: 59
2701 06:01:47.284529 [Byte1]: 59
2702 06:01:47.289174
2703 06:01:47.289786 Set Vref, RX VrefLevel [Byte0]: 60
2704 06:01:47.292854 [Byte1]: 60
2705 06:01:47.297031
2706 06:01:47.297582 Set Vref, RX VrefLevel [Byte0]: 61
2707 06:01:47.300124 [Byte1]: 61
2708 06:01:47.305022
2709 06:01:47.305593 Set Vref, RX VrefLevel [Byte0]: 62
2710 06:01:47.308174 [Byte1]: 62
2711 06:01:47.313023
2712 06:01:47.313583 Set Vref, RX VrefLevel [Byte0]: 63
2713 06:01:47.316373 [Byte1]: 63
2714 06:01:47.321331
2715 06:01:47.321885 Set Vref, RX VrefLevel [Byte0]: 64
2716 06:01:47.324254 [Byte1]: 64
2717 06:01:47.328644
2718 06:01:47.329164 Set Vref, RX VrefLevel [Byte0]: 65
2719 06:01:47.332181 [Byte1]: 65
2720 06:01:47.336858
2721 06:01:47.337516 Set Vref, RX VrefLevel [Byte0]: 66
2722 06:01:47.340163 [Byte1]: 66
2723 06:01:47.344328
2724 06:01:47.344832 Final RX Vref Byte 0 = 48 to rank0
2725 06:01:47.348016 Final RX Vref Byte 1 = 51 to rank0
2726 06:01:47.351360 Final RX Vref Byte 0 = 48 to rank1
2727 06:01:47.354627 Final RX Vref Byte 1 = 51 to rank1==
2728 06:01:47.358004 Dram Type= 6, Freq= 0, CH_0, rank 0
2729 06:01:47.364562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2730 06:01:47.365064 ==
2731 06:01:47.365430 DQS Delay:
2732 06:01:47.365770 DQS0 = 0, DQS1 = 0
2733 06:01:47.367985 DQM Delay:
2734 06:01:47.368445 DQM0 = 114, DQM1 = 106
2735 06:01:47.371510 DQ Delay:
2736 06:01:47.374743 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =110
2737 06:01:47.378104 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2738 06:01:47.381284 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =100
2739 06:01:47.384744 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
2740 06:01:47.385312
2741 06:01:47.385678
2742 06:01:47.390992 [DQSOSCAuto] RK0, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2743 06:01:47.394710 CH0 RK0: MR19=404, MR18=606
2744 06:01:47.401378 CH0_RK0: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
2745 06:01:47.401935
2746 06:01:47.404513 ----->DramcWriteLeveling(PI) begin...
2747 06:01:47.405078 ==
2748 06:01:47.407914 Dram Type= 6, Freq= 0, CH_0, rank 1
2749 06:01:47.411199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2750 06:01:47.411662 ==
2751 06:01:47.414433 Write leveling (Byte 0): 27 => 27
2752 06:01:47.417854 Write leveling (Byte 1): 26 => 26
2753 06:01:47.421371 DramcWriteLeveling(PI) end<-----
2754 06:01:47.421931
2755 06:01:47.422296 ==
2756 06:01:47.424582 Dram Type= 6, Freq= 0, CH_0, rank 1
2757 06:01:47.427838 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2758 06:01:47.431671 ==
2759 06:01:47.432246 [Gating] SW mode calibration
2760 06:01:47.441250 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2761 06:01:47.444879 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2762 06:01:47.448192 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2763 06:01:47.454565 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2764 06:01:47.457791 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2765 06:01:47.461245 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2766 06:01:47.467993 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2767 06:01:47.471343 0 11 20 | B1->B0 | 3030 2525 | 0 0 | (1 0) (0 0)
2768 06:01:47.474519 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2769 06:01:47.481209 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2770 06:01:47.484432 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2771 06:01:47.487585 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2772 06:01:47.494227 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2773 06:01:47.497374 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2774 06:01:47.501165 0 12 16 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
2775 06:01:47.507707 0 12 20 | B1->B0 | 3d3d 4646 | 1 0 | (1 1) (0 0)
2776 06:01:47.511290 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2777 06:01:47.514318 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2778 06:01:47.521117 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2779 06:01:47.524166 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2780 06:01:47.527469 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2781 06:01:47.534258 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2782 06:01:47.537393 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2783 06:01:47.541062 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2784 06:01:47.544264 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 06:01:47.550981 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 06:01:47.554379 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2787 06:01:47.557757 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2788 06:01:47.564459 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2789 06:01:47.567901 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2790 06:01:47.571080 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2791 06:01:47.577703 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2792 06:01:47.581006 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2793 06:01:47.584214 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2794 06:01:47.590891 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2795 06:01:47.594320 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2796 06:01:47.597889 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2797 06:01:47.604589 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2798 06:01:47.607844 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2799 06:01:47.611533 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2800 06:01:47.617652 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2801 06:01:47.618211 Total UI for P1: 0, mck2ui 16
2802 06:01:47.621403 best dqsien dly found for B0: ( 0, 15, 18)
2803 06:01:47.624197 Total UI for P1: 0, mck2ui 16
2804 06:01:47.627745 best dqsien dly found for B1: ( 0, 15, 20)
2805 06:01:47.634097 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2806 06:01:47.637393 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2807 06:01:47.637973
2808 06:01:47.640775 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2809 06:01:47.644058 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2810 06:01:47.647595 [Gating] SW calibration Done
2811 06:01:47.648158 ==
2812 06:01:47.650717 Dram Type= 6, Freq= 0, CH_0, rank 1
2813 06:01:47.653983 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2814 06:01:47.654540 ==
2815 06:01:47.657381 RX Vref Scan: 0
2816 06:01:47.657936
2817 06:01:47.658303 RX Vref 0 -> 0, step: 1
2818 06:01:47.658715
2819 06:01:47.660890 RX Delay -40 -> 252, step: 8
2820 06:01:47.664061 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2821 06:01:47.670450 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2822 06:01:47.673710 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2823 06:01:47.677174 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2824 06:01:47.680667 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2825 06:01:47.683683 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2826 06:01:47.690399 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2827 06:01:47.693930 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2828 06:01:47.697168 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2829 06:01:47.700291 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2830 06:01:47.704061 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2831 06:01:47.710365 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2832 06:01:47.713610 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2833 06:01:47.716937 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2834 06:01:47.720476 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2835 06:01:47.723752 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2836 06:01:47.726947 ==
2837 06:01:47.727514 Dram Type= 6, Freq= 0, CH_0, rank 1
2838 06:01:47.733620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2839 06:01:47.734166 ==
2840 06:01:47.734534 DQS Delay:
2841 06:01:47.736832 DQS0 = 0, DQS1 = 0
2842 06:01:47.737290 DQM Delay:
2843 06:01:47.740125 DQM0 = 115, DQM1 = 106
2844 06:01:47.740581 DQ Delay:
2845 06:01:47.743528 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2846 06:01:47.746664 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2847 06:01:47.750344 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2848 06:01:47.753635 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2849 06:01:47.754188
2850 06:01:47.754555
2851 06:01:47.754889 ==
2852 06:01:47.756814 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 06:01:47.763443 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2854 06:01:47.763988 ==
2855 06:01:47.764354
2856 06:01:47.764694
2857 06:01:47.765087 TX Vref Scan disable
2858 06:01:47.766776 == TX Byte 0 ==
2859 06:01:47.770477 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2860 06:01:47.773282 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2861 06:01:47.776980 == TX Byte 1 ==
2862 06:01:47.780452 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2863 06:01:47.783558 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2864 06:01:47.787054 ==
2865 06:01:47.790141 Dram Type= 6, Freq= 0, CH_0, rank 1
2866 06:01:47.793362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2867 06:01:47.793923 ==
2868 06:01:47.804589 TX Vref=22, minBit 10, minWin=25, winSum=416
2869 06:01:47.807894 TX Vref=24, minBit 1, minWin=26, winSum=426
2870 06:01:47.811188 TX Vref=26, minBit 15, minWin=25, winSum=425
2871 06:01:47.814468 TX Vref=28, minBit 10, minWin=25, winSum=431
2872 06:01:47.817803 TX Vref=30, minBit 10, minWin=25, winSum=436
2873 06:01:47.824463 TX Vref=32, minBit 8, minWin=26, winSum=433
2874 06:01:47.827528 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 32
2875 06:01:47.828213
2876 06:01:47.831069 Final TX Range 1 Vref 32
2877 06:01:47.831623
2878 06:01:47.831993 ==
2879 06:01:47.834215 Dram Type= 6, Freq= 0, CH_0, rank 1
2880 06:01:47.837540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2881 06:01:47.840890 ==
2882 06:01:47.841353
2883 06:01:47.841773
2884 06:01:47.842131 TX Vref Scan disable
2885 06:01:47.844667 == TX Byte 0 ==
2886 06:01:47.847810 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2887 06:01:47.851613 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2888 06:01:47.855077 == TX Byte 1 ==
2889 06:01:47.857970 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2890 06:01:47.864741 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2891 06:01:47.865309
2892 06:01:47.865676 [DATLAT]
2893 06:01:47.866015 Freq=1200, CH0 RK1
2894 06:01:47.866347
2895 06:01:47.868293 DATLAT Default: 0xc
2896 06:01:47.868893 0, 0xFFFF, sum = 0
2897 06:01:47.871091 1, 0xFFFF, sum = 0
2898 06:01:47.871557 2, 0xFFFF, sum = 0
2899 06:01:47.874622 3, 0xFFFF, sum = 0
2900 06:01:47.875188 4, 0xFFFF, sum = 0
2901 06:01:47.877921 5, 0xFFFF, sum = 0
2902 06:01:47.881486 6, 0xFFFF, sum = 0
2903 06:01:47.882053 7, 0xFFFF, sum = 0
2904 06:01:47.884479 8, 0xFFFF, sum = 0
2905 06:01:47.885090 9, 0xFFFF, sum = 0
2906 06:01:47.887858 10, 0xFFFF, sum = 0
2907 06:01:47.888433 11, 0x0, sum = 1
2908 06:01:47.891247 12, 0x0, sum = 2
2909 06:01:47.891685 13, 0x0, sum = 3
2910 06:01:47.892043 14, 0x0, sum = 4
2911 06:01:47.894640 best_step = 12
2912 06:01:47.895208
2913 06:01:47.895578 ==
2914 06:01:47.897560 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 06:01:47.901260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2916 06:01:47.901828 ==
2917 06:01:47.904155 RX Vref Scan: 0
2918 06:01:47.904613
2919 06:01:47.907422 RX Vref 0 -> 0, step: 1
2920 06:01:47.907885
2921 06:01:47.908245 RX Delay -21 -> 252, step: 4
2922 06:01:47.915360 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2923 06:01:47.918195 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2924 06:01:47.921567 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2925 06:01:47.925151 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2926 06:01:47.928155 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2927 06:01:47.935379 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2928 06:01:47.938143 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2929 06:01:47.941289 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2930 06:01:47.944648 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2931 06:01:47.948225 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2932 06:01:47.954895 iDelay=199, Bit 10, Center 108 (43 ~ 174) 132
2933 06:01:47.958045 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2934 06:01:47.961583 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2935 06:01:47.964862 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
2936 06:01:47.968324 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2937 06:01:47.974804 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2938 06:01:47.975356 ==
2939 06:01:47.978075 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 06:01:47.981617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2941 06:01:47.982173 ==
2942 06:01:47.982548 DQS Delay:
2943 06:01:47.984854 DQS0 = 0, DQS1 = 0
2944 06:01:47.985440 DQM Delay:
2945 06:01:47.987975 DQM0 = 115, DQM1 = 106
2946 06:01:47.988527 DQ Delay:
2947 06:01:47.991373 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2948 06:01:47.994803 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2949 06:01:47.997995 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =96
2950 06:01:48.001378 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =114
2951 06:01:48.001931
2952 06:01:48.002299
2953 06:01:48.011391 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2954 06:01:48.014477 CH0 RK1: MR19=404, MR18=E0E
2955 06:01:48.018077 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2956 06:01:48.021440 [RxdqsGatingPostProcess] freq 1200
2957 06:01:48.027947 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2958 06:01:48.031061 Pre-setting of DQS Precalculation
2959 06:01:48.034398 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2960 06:01:48.037761 ==
2961 06:01:48.038223 Dram Type= 6, Freq= 0, CH_1, rank 0
2962 06:01:48.044513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2963 06:01:48.045035 ==
2964 06:01:48.048178 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2965 06:01:48.054762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2966 06:01:48.063588 [CA 0] Center 37 (7~68) winsize 62
2967 06:01:48.066756 [CA 1] Center 37 (7~68) winsize 62
2968 06:01:48.070246 [CA 2] Center 34 (4~65) winsize 62
2969 06:01:48.073458 [CA 3] Center 33 (3~64) winsize 62
2970 06:01:48.076996 [CA 4] Center 32 (2~63) winsize 62
2971 06:01:48.079993 [CA 5] Center 32 (2~63) winsize 62
2972 06:01:48.080541
2973 06:01:48.083224 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2974 06:01:48.083686
2975 06:01:48.086494 [CATrainingPosCal] consider 1 rank data
2976 06:01:48.089878 u2DelayCellTimex100 = 270/100 ps
2977 06:01:48.093173 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2978 06:01:48.099565 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2979 06:01:48.103245 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2980 06:01:48.106141 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2981 06:01:48.109916 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2982 06:01:48.113049 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2983 06:01:48.113609
2984 06:01:48.116311 CA PerBit enable=1, Macro0, CA PI delay=32
2985 06:01:48.116897
2986 06:01:48.119633 [CBTSetCACLKResult] CA Dly = 32
2987 06:01:48.120217 CS Dly: 5 (0~36)
2988 06:01:48.122701 ==
2989 06:01:48.126559 Dram Type= 6, Freq= 0, CH_1, rank 1
2990 06:01:48.129515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2991 06:01:48.130090 ==
2992 06:01:48.132818 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2993 06:01:48.139410 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2994 06:01:48.148569 [CA 0] Center 37 (6~68) winsize 63
2995 06:01:48.152052 [CA 1] Center 37 (6~68) winsize 63
2996 06:01:48.155553 [CA 2] Center 34 (3~65) winsize 63
2997 06:01:48.158555 [CA 3] Center 34 (4~64) winsize 61
2998 06:01:48.161746 [CA 4] Center 32 (2~63) winsize 62
2999 06:01:48.165288 [CA 5] Center 31 (1~62) winsize 62
3000 06:01:48.165851
3001 06:01:48.168573 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3002 06:01:48.169145
3003 06:01:48.171868 [CATrainingPosCal] consider 2 rank data
3004 06:01:48.175360 u2DelayCellTimex100 = 270/100 ps
3005 06:01:48.178629 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
3006 06:01:48.181780 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
3007 06:01:48.188683 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
3008 06:01:48.192090 CA3 delay=34 (4~64),Diff = 2 PI (9 cell)
3009 06:01:48.195272 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3010 06:01:48.198442 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
3011 06:01:48.199021
3012 06:01:48.201629 CA PerBit enable=1, Macro0, CA PI delay=32
3013 06:01:48.202091
3014 06:01:48.204816 [CBTSetCACLKResult] CA Dly = 32
3015 06:01:48.205280 CS Dly: 6 (0~38)
3016 06:01:48.205649
3017 06:01:48.209688 ----->DramcWriteLeveling(PI) begin...
3018 06:01:48.211922 ==
3019 06:01:48.214906 Dram Type= 6, Freq= 0, CH_1, rank 0
3020 06:01:48.218252 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3021 06:01:48.218884 ==
3022 06:01:48.221655 Write leveling (Byte 0): 23 => 23
3023 06:01:48.224977 Write leveling (Byte 1): 23 => 23
3024 06:01:48.228291 DramcWriteLeveling(PI) end<-----
3025 06:01:48.228888
3026 06:01:48.229278 ==
3027 06:01:48.231341 Dram Type= 6, Freq= 0, CH_1, rank 0
3028 06:01:48.234943 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3029 06:01:48.235428 ==
3030 06:01:48.238165 [Gating] SW mode calibration
3031 06:01:48.245017 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3032 06:01:48.251823 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3033 06:01:48.255116 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3034 06:01:48.258119 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3035 06:01:48.265106 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3036 06:01:48.268562 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3037 06:01:48.271628 0 11 16 | B1->B0 | 3030 2424 | 1 0 | (1 1) (1 0)
3038 06:01:48.274986 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3039 06:01:48.282117 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3040 06:01:48.284854 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3041 06:01:48.288225 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3042 06:01:48.294734 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3043 06:01:48.297961 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3044 06:01:48.301464 0 12 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3045 06:01:48.308264 0 12 16 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
3046 06:01:48.311430 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3047 06:01:48.314433 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3048 06:01:48.321394 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3049 06:01:48.324784 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3050 06:01:48.328238 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3051 06:01:48.334734 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3052 06:01:48.337918 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3053 06:01:48.341116 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3054 06:01:48.347767 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3055 06:01:48.351403 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 06:01:48.354456 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 06:01:48.361158 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3058 06:01:48.364468 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3059 06:01:48.367714 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3060 06:01:48.374527 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3061 06:01:48.377707 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3062 06:01:48.381690 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3063 06:01:48.387768 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3064 06:01:48.390894 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3065 06:01:48.394578 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3066 06:01:48.401050 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3067 06:01:48.404357 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3068 06:01:48.407880 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3069 06:01:48.414419 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3070 06:01:48.417692 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3071 06:01:48.420898 Total UI for P1: 0, mck2ui 16
3072 06:01:48.424464 best dqsien dly found for B0: ( 0, 15, 16)
3073 06:01:48.427795 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3074 06:01:48.430850 Total UI for P1: 0, mck2ui 16
3075 06:01:48.434606 best dqsien dly found for B1: ( 0, 15, 18)
3076 06:01:48.437496 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3077 06:01:48.440835 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3078 06:01:48.441301
3079 06:01:48.444288 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3080 06:01:48.451189 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3081 06:01:48.451756 [Gating] SW calibration Done
3082 06:01:48.452130 ==
3083 06:01:48.454176 Dram Type= 6, Freq= 0, CH_1, rank 0
3084 06:01:48.460987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3085 06:01:48.461564 ==
3086 06:01:48.461939 RX Vref Scan: 0
3087 06:01:48.462285
3088 06:01:48.464336 RX Vref 0 -> 0, step: 1
3089 06:01:48.464953
3090 06:01:48.467612 RX Delay -40 -> 252, step: 8
3091 06:01:48.471107 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3092 06:01:48.474293 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3093 06:01:48.477579 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3094 06:01:48.481033 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3095 06:01:48.487682 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3096 06:01:48.490866 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3097 06:01:48.494568 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3098 06:01:48.497516 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3099 06:01:48.501133 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3100 06:01:48.507521 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3101 06:01:48.511181 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3102 06:01:48.514289 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3103 06:01:48.517587 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3104 06:01:48.521359 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3105 06:01:48.527669 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3106 06:01:48.530888 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3107 06:01:48.531375 ==
3108 06:01:48.534047 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 06:01:48.537792 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3110 06:01:48.538350 ==
3111 06:01:48.540747 DQS Delay:
3112 06:01:48.541217 DQS0 = 0, DQS1 = 0
3113 06:01:48.541581 DQM Delay:
3114 06:01:48.544212 DQM0 = 115, DQM1 = 108
3115 06:01:48.544813 DQ Delay:
3116 06:01:48.547908 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3117 06:01:48.551054 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3118 06:01:48.554311 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
3119 06:01:48.560976 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3120 06:01:48.561538
3121 06:01:48.561901
3122 06:01:48.562238 ==
3123 06:01:48.564352 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 06:01:48.567677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3125 06:01:48.568238 ==
3126 06:01:48.568607
3127 06:01:48.568995
3128 06:01:48.570975 TX Vref Scan disable
3129 06:01:48.571535 == TX Byte 0 ==
3130 06:01:48.577563 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3131 06:01:48.581106 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3132 06:01:48.581664 == TX Byte 1 ==
3133 06:01:48.587455 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3134 06:01:48.590894 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3135 06:01:48.591360 ==
3136 06:01:48.593968 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 06:01:48.597851 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3138 06:01:48.598416 ==
3139 06:01:48.609669 TX Vref=22, minBit 9, minWin=25, winSum=416
3140 06:01:48.613137 TX Vref=24, minBit 9, minWin=25, winSum=421
3141 06:01:48.616109 TX Vref=26, minBit 15, minWin=25, winSum=429
3142 06:01:48.619618 TX Vref=28, minBit 2, minWin=26, winSum=429
3143 06:01:48.623320 TX Vref=30, minBit 8, minWin=26, winSum=435
3144 06:01:48.629821 TX Vref=32, minBit 14, minWin=25, winSum=429
3145 06:01:48.632939 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
3146 06:01:48.633407
3147 06:01:48.636332 Final TX Range 1 Vref 30
3148 06:01:48.636828
3149 06:01:48.637198 ==
3150 06:01:48.639543 Dram Type= 6, Freq= 0, CH_1, rank 0
3151 06:01:48.643318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3152 06:01:48.643929 ==
3153 06:01:48.646362
3154 06:01:48.646956
3155 06:01:48.647332 TX Vref Scan disable
3156 06:01:48.649341 == TX Byte 0 ==
3157 06:01:48.653095 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3158 06:01:48.656197 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3159 06:01:48.659481 == TX Byte 1 ==
3160 06:01:48.662929 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3161 06:01:48.666200 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3162 06:01:48.669710
3163 06:01:48.670260 [DATLAT]
3164 06:01:48.670625 Freq=1200, CH1 RK0
3165 06:01:48.670971
3166 06:01:48.673008 DATLAT Default: 0xd
3167 06:01:48.673570 0, 0xFFFF, sum = 0
3168 06:01:48.676224 1, 0xFFFF, sum = 0
3169 06:01:48.676837 2, 0xFFFF, sum = 0
3170 06:01:48.679552 3, 0xFFFF, sum = 0
3171 06:01:48.680114 4, 0xFFFF, sum = 0
3172 06:01:48.682958 5, 0xFFFF, sum = 0
3173 06:01:48.686116 6, 0xFFFF, sum = 0
3174 06:01:48.686710 7, 0xFFFF, sum = 0
3175 06:01:48.689464 8, 0xFFFF, sum = 0
3176 06:01:48.690008 9, 0xFFFF, sum = 0
3177 06:01:48.692993 10, 0xFFFF, sum = 0
3178 06:01:48.693560 11, 0x0, sum = 1
3179 06:01:48.696263 12, 0x0, sum = 2
3180 06:01:48.696867 13, 0x0, sum = 3
3181 06:01:48.697247 14, 0x0, sum = 4
3182 06:01:48.699741 best_step = 12
3183 06:01:48.700321
3184 06:01:48.700789 ==
3185 06:01:48.702915 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 06:01:48.706297 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3187 06:01:48.706864 ==
3188 06:01:48.709658 RX Vref Scan: 1
3189 06:01:48.710222
3190 06:01:48.713037 Set Vref Range= 32 -> 127
3191 06:01:48.713596
3192 06:01:48.713962 RX Vref 32 -> 127, step: 1
3193 06:01:48.714308
3194 06:01:48.716108 RX Delay -21 -> 252, step: 4
3195 06:01:48.716569
3196 06:01:48.719420 Set Vref, RX VrefLevel [Byte0]: 32
3197 06:01:48.722713 [Byte1]: 32
3198 06:01:48.726159
3199 06:01:48.726619 Set Vref, RX VrefLevel [Byte0]: 33
3200 06:01:48.729837 [Byte1]: 33
3201 06:01:48.733901
3202 06:01:48.734580 Set Vref, RX VrefLevel [Byte0]: 34
3203 06:01:48.737553 [Byte1]: 34
3204 06:01:48.741932
3205 06:01:48.742395 Set Vref, RX VrefLevel [Byte0]: 35
3206 06:01:48.745805 [Byte1]: 35
3207 06:01:48.749961
3208 06:01:48.750703 Set Vref, RX VrefLevel [Byte0]: 36
3209 06:01:48.753308 [Byte1]: 36
3210 06:01:48.757733
3211 06:01:48.758241 Set Vref, RX VrefLevel [Byte0]: 37
3212 06:01:48.760930 [Byte1]: 37
3213 06:01:48.765818
3214 06:01:48.766382 Set Vref, RX VrefLevel [Byte0]: 38
3215 06:01:48.769303 [Byte1]: 38
3216 06:01:48.773665
3217 06:01:48.774232 Set Vref, RX VrefLevel [Byte0]: 39
3218 06:01:48.777181 [Byte1]: 39
3219 06:01:48.781661
3220 06:01:48.782233 Set Vref, RX VrefLevel [Byte0]: 40
3221 06:01:48.785132 [Byte1]: 40
3222 06:01:48.789610
3223 06:01:48.790077 Set Vref, RX VrefLevel [Byte0]: 41
3224 06:01:48.792831 [Byte1]: 41
3225 06:01:48.797669
3226 06:01:48.798235 Set Vref, RX VrefLevel [Byte0]: 42
3227 06:01:48.800746 [Byte1]: 42
3228 06:01:48.805475
3229 06:01:48.806039 Set Vref, RX VrefLevel [Byte0]: 43
3230 06:01:48.808882 [Byte1]: 43
3231 06:01:48.813437
3232 06:01:48.814005 Set Vref, RX VrefLevel [Byte0]: 44
3233 06:01:48.816901 [Byte1]: 44
3234 06:01:48.821269
3235 06:01:48.821840 Set Vref, RX VrefLevel [Byte0]: 45
3236 06:01:48.824602 [Byte1]: 45
3237 06:01:48.829147
3238 06:01:48.829703 Set Vref, RX VrefLevel [Byte0]: 46
3239 06:01:48.832441 [Byte1]: 46
3240 06:01:48.836928
3241 06:01:48.837394 Set Vref, RX VrefLevel [Byte0]: 47
3242 06:01:48.840380 [Byte1]: 47
3243 06:01:48.845141
3244 06:01:48.845697 Set Vref, RX VrefLevel [Byte0]: 48
3245 06:01:48.848150 [Byte1]: 48
3246 06:01:48.853179
3247 06:01:48.853740 Set Vref, RX VrefLevel [Byte0]: 49
3248 06:01:48.859685 [Byte1]: 49
3249 06:01:48.860247
3250 06:01:48.863077 Set Vref, RX VrefLevel [Byte0]: 50
3251 06:01:48.865995 [Byte1]: 50
3252 06:01:48.866458
3253 06:01:48.869638 Set Vref, RX VrefLevel [Byte0]: 51
3254 06:01:48.872799 [Byte1]: 51
3255 06:01:48.876805
3256 06:01:48.877366 Set Vref, RX VrefLevel [Byte0]: 52
3257 06:01:48.880069 [Byte1]: 52
3258 06:01:48.884690
3259 06:01:48.885291 Set Vref, RX VrefLevel [Byte0]: 53
3260 06:01:48.887726 [Byte1]: 53
3261 06:01:48.892525
3262 06:01:48.893132 Set Vref, RX VrefLevel [Byte0]: 54
3263 06:01:48.896097 [Byte1]: 54
3264 06:01:48.900476
3265 06:01:48.901171 Set Vref, RX VrefLevel [Byte0]: 55
3266 06:01:48.904314 [Byte1]: 55
3267 06:01:48.908595
3268 06:01:48.909187 Set Vref, RX VrefLevel [Byte0]: 56
3269 06:01:48.911866 [Byte1]: 56
3270 06:01:48.916498
3271 06:01:48.916995 Set Vref, RX VrefLevel [Byte0]: 57
3272 06:01:48.919794 [Byte1]: 57
3273 06:01:48.924206
3274 06:01:48.924811 Set Vref, RX VrefLevel [Byte0]: 58
3275 06:01:48.927456 [Byte1]: 58
3276 06:01:48.931973
3277 06:01:48.932585 Set Vref, RX VrefLevel [Byte0]: 59
3278 06:01:48.935225 [Byte1]: 59
3279 06:01:48.940060
3280 06:01:48.940578 Set Vref, RX VrefLevel [Byte0]: 60
3281 06:01:48.943127 [Byte1]: 60
3282 06:01:48.947855
3283 06:01:48.948418 Set Vref, RX VrefLevel [Byte0]: 61
3284 06:01:48.951408 [Byte1]: 61
3285 06:01:48.955908
3286 06:01:48.956466 Set Vref, RX VrefLevel [Byte0]: 62
3287 06:01:48.958972 [Byte1]: 62
3288 06:01:48.963755
3289 06:01:48.964214 Set Vref, RX VrefLevel [Byte0]: 63
3290 06:01:48.967164 [Byte1]: 63
3291 06:01:48.972045
3292 06:01:48.972509 Set Vref, RX VrefLevel [Byte0]: 64
3293 06:01:48.975274 [Byte1]: 64
3294 06:01:48.979634
3295 06:01:48.980202 Set Vref, RX VrefLevel [Byte0]: 65
3296 06:01:48.982860 [Byte1]: 65
3297 06:01:48.987546
3298 06:01:48.988008 Set Vref, RX VrefLevel [Byte0]: 66
3299 06:01:48.990918 [Byte1]: 66
3300 06:01:48.995404
3301 06:01:48.995965 Final RX Vref Byte 0 = 56 to rank0
3302 06:01:48.999055 Final RX Vref Byte 1 = 47 to rank0
3303 06:01:49.001913 Final RX Vref Byte 0 = 56 to rank1
3304 06:01:49.005663 Final RX Vref Byte 1 = 47 to rank1==
3305 06:01:49.009106 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 06:01:49.015444 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3307 06:01:49.016010 ==
3308 06:01:49.016382 DQS Delay:
3309 06:01:49.016765 DQS0 = 0, DQS1 = 0
3310 06:01:49.018880 DQM Delay:
3311 06:01:49.019439 DQM0 = 115, DQM1 = 104
3312 06:01:49.021897 DQ Delay:
3313 06:01:49.025465 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3314 06:01:49.028615 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3315 06:01:49.031936 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3316 06:01:49.035187 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =114
3317 06:01:49.035650
3318 06:01:49.036037
3319 06:01:49.041916 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3320 06:01:49.045607 CH1 RK0: MR19=404, MR18=1717
3321 06:01:49.052198 CH1_RK0: MR19=0x404, MR18=0x1717, DQSOSC=401, MR23=63, INC=40, DEC=27
3322 06:01:49.052808
3323 06:01:49.055776 ----->DramcWriteLeveling(PI) begin...
3324 06:01:49.056355 ==
3325 06:01:49.058644 Dram Type= 6, Freq= 0, CH_1, rank 1
3326 06:01:49.061852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3327 06:01:49.065635 ==
3328 06:01:49.066184 Write leveling (Byte 0): 22 => 22
3329 06:01:49.068556 Write leveling (Byte 1): 22 => 22
3330 06:01:49.071869 DramcWriteLeveling(PI) end<-----
3331 06:01:49.072333
3332 06:01:49.072704 ==
3333 06:01:49.075412 Dram Type= 6, Freq= 0, CH_1, rank 1
3334 06:01:49.082082 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3335 06:01:49.082645 ==
3336 06:01:49.083016 [Gating] SW mode calibration
3337 06:01:49.091913 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3338 06:01:49.094883 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3339 06:01:49.101767 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3340 06:01:49.104972 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3341 06:01:49.108561 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3342 06:01:49.111971 0 11 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
3343 06:01:49.118486 0 11 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
3344 06:01:49.121533 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3345 06:01:49.125333 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3346 06:01:49.131767 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3347 06:01:49.135107 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3348 06:01:49.138633 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3349 06:01:49.145201 0 12 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
3350 06:01:49.148484 0 12 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
3351 06:01:49.151832 0 12 16 | B1->B0 | 3e3d 4646 | 1 0 | (0 0) (0 0)
3352 06:01:49.158530 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3353 06:01:49.161783 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3354 06:01:49.165197 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3355 06:01:49.171969 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3356 06:01:49.175171 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3357 06:01:49.178347 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3358 06:01:49.185339 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3359 06:01:49.188621 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3360 06:01:49.191595 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3361 06:01:49.194964 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 06:01:49.201559 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3363 06:01:49.205064 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3364 06:01:49.208511 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3365 06:01:49.215524 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3366 06:01:49.218699 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3367 06:01:49.221869 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3368 06:01:49.228696 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3369 06:01:49.232169 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3370 06:01:49.235394 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3371 06:01:49.242079 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3372 06:01:49.245379 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3373 06:01:49.248749 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3374 06:01:49.255046 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3375 06:01:49.258418 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3376 06:01:49.262115 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3377 06:01:49.265089 Total UI for P1: 0, mck2ui 16
3378 06:01:49.268412 best dqsien dly found for B0: ( 0, 15, 14)
3379 06:01:49.275082 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3380 06:01:49.275560 Total UI for P1: 0, mck2ui 16
3381 06:01:49.278403 best dqsien dly found for B1: ( 0, 15, 18)
3382 06:01:49.284916 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3383 06:01:49.288701 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3384 06:01:49.289319
3385 06:01:49.291841 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3386 06:01:49.294944 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3387 06:01:49.298625 [Gating] SW calibration Done
3388 06:01:49.299179 ==
3389 06:01:49.301761 Dram Type= 6, Freq= 0, CH_1, rank 1
3390 06:01:49.304976 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3391 06:01:49.305437 ==
3392 06:01:49.308592 RX Vref Scan: 0
3393 06:01:49.309172
3394 06:01:49.309540 RX Vref 0 -> 0, step: 1
3395 06:01:49.309879
3396 06:01:49.311782 RX Delay -40 -> 252, step: 8
3397 06:01:49.315145 iDelay=208, Bit 0, Center 115 (40 ~ 191) 152
3398 06:01:49.321567 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3399 06:01:49.324770 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3400 06:01:49.328598 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3401 06:01:49.331785 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3402 06:01:49.334869 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3403 06:01:49.341484 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3404 06:01:49.344861 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3405 06:01:49.348683 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3406 06:01:49.351853 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3407 06:01:49.355078 iDelay=208, Bit 10, Center 103 (32 ~ 175) 144
3408 06:01:49.361349 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3409 06:01:49.364952 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3410 06:01:49.368231 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3411 06:01:49.371593 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3412 06:01:49.374717 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3413 06:01:49.375185 ==
3414 06:01:49.378224 Dram Type= 6, Freq= 0, CH_1, rank 1
3415 06:01:49.384772 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3416 06:01:49.385327 ==
3417 06:01:49.385691 DQS Delay:
3418 06:01:49.387847 DQS0 = 0, DQS1 = 0
3419 06:01:49.388301 DQM Delay:
3420 06:01:49.391380 DQM0 = 116, DQM1 = 105
3421 06:01:49.391837 DQ Delay:
3422 06:01:49.394711 DQ0 =115, DQ1 =115, DQ2 =103, DQ3 =115
3423 06:01:49.398276 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3424 06:01:49.401458 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3425 06:01:49.404778 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3426 06:01:49.405343
3427 06:01:49.405705
3428 06:01:49.406038 ==
3429 06:01:49.407960 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 06:01:49.414777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3431 06:01:49.415333 ==
3432 06:01:49.415703
3433 06:01:49.416038
3434 06:01:49.416359 TX Vref Scan disable
3435 06:01:49.417873 == TX Byte 0 ==
3436 06:01:49.421271 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3437 06:01:49.424701 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3438 06:01:49.428358 == TX Byte 1 ==
3439 06:01:49.431375 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3440 06:01:49.434783 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3441 06:01:49.437770 ==
3442 06:01:49.438341 Dram Type= 6, Freq= 0, CH_1, rank 1
3443 06:01:49.444476 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3444 06:01:49.444988 ==
3445 06:01:49.455514 TX Vref=22, minBit 9, minWin=25, winSum=420
3446 06:01:49.458673 TX Vref=24, minBit 3, minWin=26, winSum=428
3447 06:01:49.462266 TX Vref=26, minBit 3, minWin=26, winSum=428
3448 06:01:49.465179 TX Vref=28, minBit 3, minWin=26, winSum=429
3449 06:01:49.468632 TX Vref=30, minBit 0, minWin=26, winSum=431
3450 06:01:49.475223 TX Vref=32, minBit 0, minWin=26, winSum=432
3451 06:01:49.478638 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 32
3452 06:01:49.479204
3453 06:01:49.481785 Final TX Range 1 Vref 32
3454 06:01:49.482338
3455 06:01:49.482698 ==
3456 06:01:49.485126 Dram Type= 6, Freq= 0, CH_1, rank 1
3457 06:01:49.488258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3458 06:01:49.488768 ==
3459 06:01:49.491380
3460 06:01:49.491837
3461 06:01:49.492201 TX Vref Scan disable
3462 06:01:49.495020 == TX Byte 0 ==
3463 06:01:49.498580 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3464 06:01:49.501635 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3465 06:01:49.505148 == TX Byte 1 ==
3466 06:01:49.508422 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3467 06:01:49.511750 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3468 06:01:49.515308
3469 06:01:49.515862 [DATLAT]
3470 06:01:49.516232 Freq=1200, CH1 RK1
3471 06:01:49.516575
3472 06:01:49.518395 DATLAT Default: 0xc
3473 06:01:49.518855 0, 0xFFFF, sum = 0
3474 06:01:49.521611 1, 0xFFFF, sum = 0
3475 06:01:49.522077 2, 0xFFFF, sum = 0
3476 06:01:49.524914 3, 0xFFFF, sum = 0
3477 06:01:49.528671 4, 0xFFFF, sum = 0
3478 06:01:49.529296 5, 0xFFFF, sum = 0
3479 06:01:49.531811 6, 0xFFFF, sum = 0
3480 06:01:49.532382 7, 0xFFFF, sum = 0
3481 06:01:49.534850 8, 0xFFFF, sum = 0
3482 06:01:49.535312 9, 0xFFFF, sum = 0
3483 06:01:49.538153 10, 0xFFFF, sum = 0
3484 06:01:49.538684 11, 0x0, sum = 1
3485 06:01:49.541786 12, 0x0, sum = 2
3486 06:01:49.542253 13, 0x0, sum = 3
3487 06:01:49.544926 14, 0x0, sum = 4
3488 06:01:49.545407 best_step = 12
3489 06:01:49.545770
3490 06:01:49.546119 ==
3491 06:01:49.548269 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 06:01:49.551474 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3493 06:01:49.552032 ==
3494 06:01:49.555083 RX Vref Scan: 0
3495 06:01:49.555751
3496 06:01:49.558147 RX Vref 0 -> 0, step: 1
3497 06:01:49.558606
3498 06:01:49.558964 RX Delay -29 -> 252, step: 4
3499 06:01:49.565737 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3500 06:01:49.568677 iDelay=199, Bit 1, Center 110 (39 ~ 182) 144
3501 06:01:49.572308 iDelay=199, Bit 2, Center 106 (39 ~ 174) 136
3502 06:01:49.575373 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3503 06:01:49.578840 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3504 06:01:49.585418 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3505 06:01:49.588884 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3506 06:01:49.591842 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3507 06:01:49.595085 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3508 06:01:49.598773 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3509 06:01:49.605450 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3510 06:01:49.608499 iDelay=199, Bit 11, Center 96 (31 ~ 162) 132
3511 06:01:49.611976 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3512 06:01:49.615493 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3513 06:01:49.618632 iDelay=199, Bit 14, Center 114 (47 ~ 182) 136
3514 06:01:49.625392 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3515 06:01:49.625952 ==
3516 06:01:49.628750 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 06:01:49.632039 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3518 06:01:49.632603 ==
3519 06:01:49.633020 DQS Delay:
3520 06:01:49.635324 DQS0 = 0, DQS1 = 0
3521 06:01:49.635882 DQM Delay:
3522 06:01:49.638479 DQM0 = 114, DQM1 = 103
3523 06:01:49.638943 DQ Delay:
3524 06:01:49.642166 DQ0 =114, DQ1 =110, DQ2 =106, DQ3 =112
3525 06:01:49.645174 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3526 06:01:49.648695 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =96
3527 06:01:49.651789 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =110
3528 06:01:49.652250
3529 06:01:49.652610
3530 06:01:49.661979 [DQSOSCAuto] RK1, (LSB)MR18= 0x303, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
3531 06:01:49.665340 CH1 RK1: MR19=404, MR18=303
3532 06:01:49.668664 CH1_RK1: MR19=0x404, MR18=0x303, DQSOSC=408, MR23=63, INC=39, DEC=26
3533 06:01:49.672295 [RxdqsGatingPostProcess] freq 1200
3534 06:01:49.679021 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3535 06:01:49.682245 Pre-setting of DQS Precalculation
3536 06:01:49.685678 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3537 06:01:49.695142 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3538 06:01:49.701946 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3539 06:01:49.702528
3540 06:01:49.702929
3541 06:01:49.704985 [Calibration Summary] 2400 Mbps
3542 06:01:49.705443 CH 0, Rank 0
3543 06:01:49.708799 SW Impedance : PASS
3544 06:01:49.709409 DUTY Scan : NO K
3545 06:01:49.711739 ZQ Calibration : PASS
3546 06:01:49.714911 Jitter Meter : NO K
3547 06:01:49.715339 CBT Training : PASS
3548 06:01:49.718440 Write leveling : PASS
3549 06:01:49.721796 RX DQS gating : PASS
3550 06:01:49.722382 RX DQ/DQS(RDDQC) : PASS
3551 06:01:49.725251 TX DQ/DQS : PASS
3552 06:01:49.728843 RX DATLAT : PASS
3553 06:01:49.729403 RX DQ/DQS(Engine): PASS
3554 06:01:49.731653 TX OE : NO K
3555 06:01:49.732112 All Pass.
3556 06:01:49.732475
3557 06:01:49.734891 CH 0, Rank 1
3558 06:01:49.735343 SW Impedance : PASS
3559 06:01:49.738369 DUTY Scan : NO K
3560 06:01:49.738843 ZQ Calibration : PASS
3561 06:01:49.741709 Jitter Meter : NO K
3562 06:01:49.745301 CBT Training : PASS
3563 06:01:49.745758 Write leveling : PASS
3564 06:01:49.748463 RX DQS gating : PASS
3565 06:01:49.751580 RX DQ/DQS(RDDQC) : PASS
3566 06:01:49.752036 TX DQ/DQS : PASS
3567 06:01:49.755062 RX DATLAT : PASS
3568 06:01:49.758526 RX DQ/DQS(Engine): PASS
3569 06:01:49.759084 TX OE : NO K
3570 06:01:49.761914 All Pass.
3571 06:01:49.762474
3572 06:01:49.762841 CH 1, Rank 0
3573 06:01:49.764948 SW Impedance : PASS
3574 06:01:49.765405 DUTY Scan : NO K
3575 06:01:49.768198 ZQ Calibration : PASS
3576 06:01:49.771821 Jitter Meter : NO K
3577 06:01:49.772373 CBT Training : PASS
3578 06:01:49.775149 Write leveling : PASS
3579 06:01:49.778070 RX DQS gating : PASS
3580 06:01:49.778527 RX DQ/DQS(RDDQC) : PASS
3581 06:01:49.781849 TX DQ/DQS : PASS
3582 06:01:49.782591 RX DATLAT : PASS
3583 06:01:49.784853 RX DQ/DQS(Engine): PASS
3584 06:01:49.788455 TX OE : NO K
3585 06:01:49.789089 All Pass.
3586 06:01:49.789509
3587 06:01:49.789848 CH 1, Rank 1
3588 06:01:49.791610 SW Impedance : PASS
3589 06:01:49.794941 DUTY Scan : NO K
3590 06:01:49.795399 ZQ Calibration : PASS
3591 06:01:49.798439 Jitter Meter : NO K
3592 06:01:49.801850 CBT Training : PASS
3593 06:01:49.802400 Write leveling : PASS
3594 06:01:49.804656 RX DQS gating : PASS
3595 06:01:49.808523 RX DQ/DQS(RDDQC) : PASS
3596 06:01:49.809132 TX DQ/DQS : PASS
3597 06:01:49.811492 RX DATLAT : PASS
3598 06:01:49.814766 RX DQ/DQS(Engine): PASS
3599 06:01:49.815223 TX OE : NO K
3600 06:01:49.818077 All Pass.
3601 06:01:49.818530
3602 06:01:49.818885 DramC Write-DBI off
3603 06:01:49.821619 PER_BANK_REFRESH: Hybrid Mode
3604 06:01:49.822177 TX_TRACKING: ON
3605 06:01:49.831401 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3606 06:01:49.834621 [FAST_K] Save calibration result to emmc
3607 06:01:49.837938 dramc_set_vcore_voltage set vcore to 650000
3608 06:01:49.841759 Read voltage for 600, 5
3609 06:01:49.842235 Vio18 = 0
3610 06:01:49.845164 Vcore = 650000
3611 06:01:49.845635 Vdram = 0
3612 06:01:49.846116 Vddq = 0
3613 06:01:49.846568 Vmddr = 0
3614 06:01:49.851748 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3615 06:01:49.858526 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3616 06:01:49.859124 MEM_TYPE=3, freq_sel=19
3617 06:01:49.861346 sv_algorithm_assistance_LP4_1600
3618 06:01:49.864751 ============ PULL DRAM RESETB DOWN ============
3619 06:01:49.871709 ========== PULL DRAM RESETB DOWN end =========
3620 06:01:49.874939 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3621 06:01:49.877820 ===================================
3622 06:01:49.881558 LPDDR4 DRAM CONFIGURATION
3623 06:01:49.884953 ===================================
3624 06:01:49.885542 EX_ROW_EN[0] = 0x0
3625 06:01:49.888052 EX_ROW_EN[1] = 0x0
3626 06:01:49.888668 LP4Y_EN = 0x0
3627 06:01:49.891279 WORK_FSP = 0x0
3628 06:01:49.894811 WL = 0x2
3629 06:01:49.895425 RL = 0x2
3630 06:01:49.898120 BL = 0x2
3631 06:01:49.898685 RPST = 0x0
3632 06:01:49.901153 RD_PRE = 0x0
3633 06:01:49.901631 WR_PRE = 0x1
3634 06:01:49.904489 WR_PST = 0x0
3635 06:01:49.905110 DBI_WR = 0x0
3636 06:01:49.907969 DBI_RD = 0x0
3637 06:01:49.908541 OTF = 0x1
3638 06:01:49.911024 ===================================
3639 06:01:49.914690 ===================================
3640 06:01:49.917583 ANA top config
3641 06:01:49.921354 ===================================
3642 06:01:49.921933 DLL_ASYNC_EN = 0
3643 06:01:49.924313 ALL_SLAVE_EN = 1
3644 06:01:49.927841 NEW_RANK_MODE = 1
3645 06:01:49.931333 DLL_IDLE_MODE = 1
3646 06:01:49.931908 LP45_APHY_COMB_EN = 1
3647 06:01:49.934487 TX_ODT_DIS = 1
3648 06:01:49.937582 NEW_8X_MODE = 1
3649 06:01:49.940786 ===================================
3650 06:01:49.944027 ===================================
3651 06:01:49.947839 data_rate = 1200
3652 06:01:49.951188 CKR = 1
3653 06:01:49.954312 DQ_P2S_RATIO = 8
3654 06:01:49.957276 ===================================
3655 06:01:49.957757 CA_P2S_RATIO = 8
3656 06:01:49.960644 DQ_CA_OPEN = 0
3657 06:01:49.964179 DQ_SEMI_OPEN = 0
3658 06:01:49.967284 CA_SEMI_OPEN = 0
3659 06:01:49.970955 CA_FULL_RATE = 0
3660 06:01:49.974227 DQ_CKDIV4_EN = 1
3661 06:01:49.974804 CA_CKDIV4_EN = 1
3662 06:01:49.977059 CA_PREDIV_EN = 0
3663 06:01:49.980357 PH8_DLY = 0
3664 06:01:49.983910 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3665 06:01:49.987227 DQ_AAMCK_DIV = 4
3666 06:01:49.990177 CA_AAMCK_DIV = 4
3667 06:01:49.990661 CA_ADMCK_DIV = 4
3668 06:01:49.993708 DQ_TRACK_CA_EN = 0
3669 06:01:49.996883 CA_PICK = 600
3670 06:01:50.000226 CA_MCKIO = 600
3671 06:01:50.003362 MCKIO_SEMI = 0
3672 06:01:50.006863 PLL_FREQ = 2288
3673 06:01:50.010016 DQ_UI_PI_RATIO = 32
3674 06:01:50.013692 CA_UI_PI_RATIO = 0
3675 06:01:50.016770 ===================================
3676 06:01:50.019950 ===================================
3677 06:01:50.020418 memory_type:LPDDR4
3678 06:01:50.023568 GP_NUM : 10
3679 06:01:50.024133 SRAM_EN : 1
3680 06:01:50.027017 MD32_EN : 0
3681 06:01:50.030038 ===================================
3682 06:01:50.033668 [ANA_INIT] >>>>>>>>>>>>>>
3683 06:01:50.036966 <<<<<< [CONFIGURE PHASE]: ANA_TX
3684 06:01:50.039861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3685 06:01:50.043325 ===================================
3686 06:01:50.046802 data_rate = 1200,PCW = 0X5800
3687 06:01:50.049988 ===================================
3688 06:01:50.053400 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3689 06:01:50.056517 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3690 06:01:50.063132 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3691 06:01:50.066548 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3692 06:01:50.070053 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3693 06:01:50.073290 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3694 06:01:50.076528 [ANA_INIT] flow start
3695 06:01:50.079912 [ANA_INIT] PLL >>>>>>>>
3696 06:01:50.080377 [ANA_INIT] PLL <<<<<<<<
3697 06:01:50.083047 [ANA_INIT] MIDPI >>>>>>>>
3698 06:01:50.086325 [ANA_INIT] MIDPI <<<<<<<<
3699 06:01:50.086792 [ANA_INIT] DLL >>>>>>>>
3700 06:01:50.089692 [ANA_INIT] flow end
3701 06:01:50.093159 ============ LP4 DIFF to SE enter ============
3702 06:01:50.099763 ============ LP4 DIFF to SE exit ============
3703 06:01:50.100340 [ANA_INIT] <<<<<<<<<<<<<
3704 06:01:50.102819 [Flow] Enable top DCM control >>>>>
3705 06:01:50.106311 [Flow] Enable top DCM control <<<<<
3706 06:01:50.109538 Enable DLL master slave shuffle
3707 06:01:50.116438 ==============================================================
3708 06:01:50.117061 Gating Mode config
3709 06:01:50.122796 ==============================================================
3710 06:01:50.125915 Config description:
3711 06:01:50.135843 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3712 06:01:50.142252 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3713 06:01:50.145528 SELPH_MODE 0: By rank 1: By Phase
3714 06:01:50.152395 ==============================================================
3715 06:01:50.155818 GAT_TRACK_EN = 1
3716 06:01:50.159173 RX_GATING_MODE = 2
3717 06:01:50.159761 RX_GATING_TRACK_MODE = 2
3718 06:01:50.162353 SELPH_MODE = 1
3719 06:01:50.165321 PICG_EARLY_EN = 1
3720 06:01:50.168822 VALID_LAT_VALUE = 1
3721 06:01:50.175556 ==============================================================
3722 06:01:50.178799 Enter into Gating configuration >>>>
3723 06:01:50.182053 Exit from Gating configuration <<<<
3724 06:01:50.185456 Enter into DVFS_PRE_config >>>>>
3725 06:01:50.195703 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3726 06:01:50.198837 Exit from DVFS_PRE_config <<<<<
3727 06:01:50.202167 Enter into PICG configuration >>>>
3728 06:01:50.205460 Exit from PICG configuration <<<<
3729 06:01:50.208688 [RX_INPUT] configuration >>>>>
3730 06:01:50.212357 [RX_INPUT] configuration <<<<<
3731 06:01:50.215148 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3732 06:01:50.221830 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3733 06:01:50.228602 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3734 06:01:50.235198 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3735 06:01:50.238418 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3736 06:01:50.245454 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3737 06:01:50.248780 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3738 06:01:50.255337 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3739 06:01:50.258734 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3740 06:01:50.261795 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3741 06:01:50.265025 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3742 06:01:50.271866 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3743 06:01:50.275007 ===================================
3744 06:01:50.275575 LPDDR4 DRAM CONFIGURATION
3745 06:01:50.278366 ===================================
3746 06:01:50.281644 EX_ROW_EN[0] = 0x0
3747 06:01:50.285128 EX_ROW_EN[1] = 0x0
3748 06:01:50.285688 LP4Y_EN = 0x0
3749 06:01:50.288590 WORK_FSP = 0x0
3750 06:01:50.289187 WL = 0x2
3751 06:01:50.291814 RL = 0x2
3752 06:01:50.292406 BL = 0x2
3753 06:01:50.294605 RPST = 0x0
3754 06:01:50.295062 RD_PRE = 0x0
3755 06:01:50.298135 WR_PRE = 0x1
3756 06:01:50.298700 WR_PST = 0x0
3757 06:01:50.301328 DBI_WR = 0x0
3758 06:01:50.301839 DBI_RD = 0x0
3759 06:01:50.304865 OTF = 0x1
3760 06:01:50.307926 ===================================
3761 06:01:50.311241 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3762 06:01:50.314334 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3763 06:01:50.321015 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3764 06:01:50.324763 ===================================
3765 06:01:50.325329 LPDDR4 DRAM CONFIGURATION
3766 06:01:50.327995 ===================================
3767 06:01:50.330914 EX_ROW_EN[0] = 0x10
3768 06:01:50.334584 EX_ROW_EN[1] = 0x0
3769 06:01:50.335042 LP4Y_EN = 0x0
3770 06:01:50.337767 WORK_FSP = 0x0
3771 06:01:50.338289 WL = 0x2
3772 06:01:50.341177 RL = 0x2
3773 06:01:50.341815 BL = 0x2
3774 06:01:50.344359 RPST = 0x0
3775 06:01:50.344872 RD_PRE = 0x0
3776 06:01:50.347652 WR_PRE = 0x1
3777 06:01:50.348113 WR_PST = 0x0
3778 06:01:50.351194 DBI_WR = 0x0
3779 06:01:50.351655 DBI_RD = 0x0
3780 06:01:50.354615 OTF = 0x1
3781 06:01:50.357958 ===================================
3782 06:01:50.364441 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3783 06:01:50.367851 nWR fixed to 30
3784 06:01:50.370678 [ModeRegInit_LP4] CH0 RK0
3785 06:01:50.371137 [ModeRegInit_LP4] CH0 RK1
3786 06:01:50.374116 [ModeRegInit_LP4] CH1 RK0
3787 06:01:50.377547 [ModeRegInit_LP4] CH1 RK1
3788 06:01:50.378010 match AC timing 16
3789 06:01:50.384336 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3790 06:01:50.387672 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3791 06:01:50.390883 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3792 06:01:50.397456 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3793 06:01:50.400656 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3794 06:01:50.401253 ==
3795 06:01:50.404119 Dram Type= 6, Freq= 0, CH_0, rank 0
3796 06:01:50.407319 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3797 06:01:50.407788 ==
3798 06:01:50.413745 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3799 06:01:50.420242 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3800 06:01:50.423796 [CA 0] Center 35 (5~66) winsize 62
3801 06:01:50.426980 [CA 1] Center 35 (5~66) winsize 62
3802 06:01:50.430389 [CA 2] Center 34 (4~65) winsize 62
3803 06:01:50.433474 [CA 3] Center 34 (3~65) winsize 63
3804 06:01:50.437039 [CA 4] Center 33 (3~64) winsize 62
3805 06:01:50.440277 [CA 5] Center 33 (3~64) winsize 62
3806 06:01:50.440790
3807 06:01:50.443265 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3808 06:01:50.443811
3809 06:01:50.446652 [CATrainingPosCal] consider 1 rank data
3810 06:01:50.450093 u2DelayCellTimex100 = 270/100 ps
3811 06:01:50.453415 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3812 06:01:50.456489 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3813 06:01:50.460117 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3814 06:01:50.462943 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3815 06:01:50.469448 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3816 06:01:50.472942 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3817 06:01:50.473407
3818 06:01:50.476394 CA PerBit enable=1, Macro0, CA PI delay=33
3819 06:01:50.477020
3820 06:01:50.479417 [CBTSetCACLKResult] CA Dly = 33
3821 06:01:50.479881 CS Dly: 5 (0~36)
3822 06:01:50.480246 ==
3823 06:01:50.483104 Dram Type= 6, Freq= 0, CH_0, rank 1
3824 06:01:50.489670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3825 06:01:50.490257 ==
3826 06:01:50.493074 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3827 06:01:50.499555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3828 06:01:50.502795 [CA 0] Center 35 (5~66) winsize 62
3829 06:01:50.505899 [CA 1] Center 35 (5~66) winsize 62
3830 06:01:50.509319 [CA 2] Center 34 (4~65) winsize 62
3831 06:01:50.513108 [CA 3] Center 34 (3~65) winsize 63
3832 06:01:50.515922 [CA 4] Center 33 (3~64) winsize 62
3833 06:01:50.519554 [CA 5] Center 33 (3~64) winsize 62
3834 06:01:50.520119
3835 06:01:50.522873 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3836 06:01:50.523454
3837 06:01:50.525781 [CATrainingPosCal] consider 2 rank data
3838 06:01:50.529274 u2DelayCellTimex100 = 270/100 ps
3839 06:01:50.532369 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3840 06:01:50.538744 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3841 06:01:50.542355 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3842 06:01:50.545433 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3843 06:01:50.548752 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3844 06:01:50.552408 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3845 06:01:50.553070
3846 06:01:50.555662 CA PerBit enable=1, Macro0, CA PI delay=33
3847 06:01:50.556224
3848 06:01:50.558881 [CBTSetCACLKResult] CA Dly = 33
3849 06:01:50.562202 CS Dly: 5 (0~36)
3850 06:01:50.562682
3851 06:01:50.565235 ----->DramcWriteLeveling(PI) begin...
3852 06:01:50.565721 ==
3853 06:01:50.568900 Dram Type= 6, Freq= 0, CH_0, rank 0
3854 06:01:50.572003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3855 06:01:50.572577 ==
3856 06:01:50.575255 Write leveling (Byte 0): 31 => 31
3857 06:01:50.578630 Write leveling (Byte 1): 32 => 32
3858 06:01:50.581761 DramcWriteLeveling(PI) end<-----
3859 06:01:50.582229
3860 06:01:50.582601 ==
3861 06:01:50.589856 Dram Type= 6, Freq= 0, CH_0, rank 0
3862 06:01:50.590313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3863 06:01:50.590683 ==
3864 06:01:50.591421 [Gating] SW mode calibration
3865 06:01:50.598564 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3866 06:01:50.604979 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3867 06:01:50.608345 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3868 06:01:50.611468 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3869 06:01:50.618156 0 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
3870 06:01:50.621357 0 5 12 | B1->B0 | 2828 2424 | 0 0 | (1 1) (0 0)
3871 06:01:50.624974 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3872 06:01:50.631372 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3873 06:01:50.634490 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3874 06:01:50.637879 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3875 06:01:50.644546 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3876 06:01:50.648083 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3877 06:01:50.651266 0 6 8 | B1->B0 | 2a2a 2f2f | 0 0 | (0 0) (0 0)
3878 06:01:50.657635 0 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3879 06:01:50.661173 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3880 06:01:50.664512 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3881 06:01:50.671150 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3882 06:01:50.674553 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3883 06:01:50.677322 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3884 06:01:50.683983 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3885 06:01:50.687267 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3886 06:01:50.690622 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3887 06:01:50.697405 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 06:01:50.700644 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 06:01:50.704014 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3890 06:01:50.710556 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3891 06:01:50.713852 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3892 06:01:50.717034 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3893 06:01:50.723731 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3894 06:01:50.727110 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3895 06:01:50.730405 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3896 06:01:50.737485 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3897 06:01:50.740579 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3898 06:01:50.743566 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3899 06:01:50.750085 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3900 06:01:50.753313 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3901 06:01:50.756968 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3902 06:01:50.763526 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3903 06:01:50.764085 Total UI for P1: 0, mck2ui 16
3904 06:01:50.769585 best dqsien dly found for B0: ( 0, 9, 8)
3905 06:01:50.770135 Total UI for P1: 0, mck2ui 16
3906 06:01:50.776369 best dqsien dly found for B1: ( 0, 9, 8)
3907 06:01:50.779980 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3908 06:01:50.783417 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3909 06:01:50.784001
3910 06:01:50.786692 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3911 06:01:50.789840 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3912 06:01:50.793001 [Gating] SW calibration Done
3913 06:01:50.793466 ==
3914 06:01:50.796569 Dram Type= 6, Freq= 0, CH_0, rank 0
3915 06:01:50.800219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3916 06:01:50.800836 ==
3917 06:01:50.803172 RX Vref Scan: 0
3918 06:01:50.803734
3919 06:01:50.804105 RX Vref 0 -> 0, step: 1
3920 06:01:50.804455
3921 06:01:50.806470 RX Delay -230 -> 252, step: 16
3922 06:01:50.809577 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
3923 06:01:50.816606 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3924 06:01:50.820027 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3925 06:01:50.823104 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3926 06:01:50.826431 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3927 06:01:50.833291 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3928 06:01:50.836222 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3929 06:01:50.839500 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3930 06:01:50.843002 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3931 06:01:50.846048 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3932 06:01:50.852808 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3933 06:01:50.856069 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3934 06:01:50.859654 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3935 06:01:50.863057 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3936 06:01:50.869645 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3937 06:01:50.872650 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3938 06:01:50.873164 ==
3939 06:01:50.876280 Dram Type= 6, Freq= 0, CH_0, rank 0
3940 06:01:50.879604 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3941 06:01:50.880166 ==
3942 06:01:50.882652 DQS Delay:
3943 06:01:50.883116 DQS0 = 0, DQS1 = 0
3944 06:01:50.883484 DQM Delay:
3945 06:01:50.886030 DQM0 = 41, DQM1 = 33
3946 06:01:50.886631 DQ Delay:
3947 06:01:50.889088 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
3948 06:01:50.892434 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3949 06:01:50.895761 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3950 06:01:50.899038 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3951 06:01:50.899504
3952 06:01:50.899868
3953 06:01:50.900206 ==
3954 06:01:50.902491 Dram Type= 6, Freq= 0, CH_0, rank 0
3955 06:01:50.909320 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3956 06:01:50.909869 ==
3957 06:01:50.910238
3958 06:01:50.910579
3959 06:01:50.912177 TX Vref Scan disable
3960 06:01:50.912642 == TX Byte 0 ==
3961 06:01:50.915702 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3962 06:01:50.921948 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3963 06:01:50.922516 == TX Byte 1 ==
3964 06:01:50.928617 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3965 06:01:50.931777 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3966 06:01:50.932245 ==
3967 06:01:50.935449 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 06:01:50.938704 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3969 06:01:50.939175 ==
3970 06:01:50.939543
3971 06:01:50.939882
3972 06:01:50.941968 TX Vref Scan disable
3973 06:01:50.944921 == TX Byte 0 ==
3974 06:01:50.948277 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3975 06:01:50.951874 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3976 06:01:50.955055 == TX Byte 1 ==
3977 06:01:50.958364 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3978 06:01:50.961466 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3979 06:01:50.962107
3980 06:01:50.964852 [DATLAT]
3981 06:01:50.965318 Freq=600, CH0 RK0
3982 06:01:50.965690
3983 06:01:50.968185 DATLAT Default: 0x9
3984 06:01:50.968795 0, 0xFFFF, sum = 0
3985 06:01:50.971738 1, 0xFFFF, sum = 0
3986 06:01:50.972305 2, 0xFFFF, sum = 0
3987 06:01:50.974797 3, 0xFFFF, sum = 0
3988 06:01:50.975269 4, 0xFFFF, sum = 0
3989 06:01:50.977981 5, 0xFFFF, sum = 0
3990 06:01:50.978455 6, 0xFFFF, sum = 0
3991 06:01:50.981397 7, 0x0, sum = 1
3992 06:01:50.981869 8, 0x0, sum = 2
3993 06:01:50.985017 9, 0x0, sum = 3
3994 06:01:50.985591 10, 0x0, sum = 4
3995 06:01:50.988204 best_step = 8
3996 06:01:50.988813
3997 06:01:50.989190 ==
3998 06:01:50.991555 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 06:01:50.994687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4000 06:01:50.995158 ==
4001 06:01:50.997655 RX Vref Scan: 1
4002 06:01:50.998176
4003 06:01:50.998548 RX Vref 0 -> 0, step: 1
4004 06:01:50.998894
4005 06:01:51.001409 RX Delay -195 -> 252, step: 8
4006 06:01:51.001988
4007 06:01:51.004666 Set Vref, RX VrefLevel [Byte0]: 48
4008 06:01:51.007810 [Byte1]: 51
4009 06:01:51.012026
4010 06:01:51.012599 Final RX Vref Byte 0 = 48 to rank0
4011 06:01:51.015325 Final RX Vref Byte 1 = 51 to rank0
4012 06:01:51.018424 Final RX Vref Byte 0 = 48 to rank1
4013 06:01:51.021558 Final RX Vref Byte 1 = 51 to rank1==
4014 06:01:51.025123 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 06:01:51.031868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4016 06:01:51.032595 ==
4017 06:01:51.033024 DQS Delay:
4018 06:01:51.033376 DQS0 = 0, DQS1 = 0
4019 06:01:51.034709 DQM Delay:
4020 06:01:51.035170 DQM0 = 40, DQM1 = 30
4021 06:01:51.038319 DQ Delay:
4022 06:01:51.041396 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4023 06:01:51.044591 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4024 06:01:51.047990 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
4025 06:01:51.051449 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4026 06:01:51.052019
4027 06:01:51.052391
4028 06:01:51.057922 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d4d, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
4029 06:01:51.061401 CH0 RK0: MR19=808, MR18=4D4D
4030 06:01:51.067917 CH0_RK0: MR19=0x808, MR18=0x4D4D, DQSOSC=395, MR23=63, INC=168, DEC=112
4031 06:01:51.068543
4032 06:01:51.071711 ----->DramcWriteLeveling(PI) begin...
4033 06:01:51.072276 ==
4034 06:01:51.074533 Dram Type= 6, Freq= 0, CH_0, rank 1
4035 06:01:51.077959 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4036 06:01:51.078528 ==
4037 06:01:51.081353 Write leveling (Byte 0): 31 => 31
4038 06:01:51.084638 Write leveling (Byte 1): 31 => 31
4039 06:01:51.087772 DramcWriteLeveling(PI) end<-----
4040 06:01:51.088335
4041 06:01:51.088740 ==
4042 06:01:51.091293 Dram Type= 6, Freq= 0, CH_0, rank 1
4043 06:01:51.094562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4044 06:01:51.095124 ==
4045 06:01:51.098097 [Gating] SW mode calibration
4046 06:01:51.104505 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4047 06:01:51.111040 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4048 06:01:51.114251 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 06:01:51.120954 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4050 06:01:51.124357 0 5 8 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 1)
4051 06:01:51.127476 0 5 12 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
4052 06:01:51.133982 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 06:01:51.137328 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 06:01:51.140949 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 06:01:51.147071 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 06:01:51.150686 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 06:01:51.154133 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 06:01:51.160670 0 6 8 | B1->B0 | 2828 2e2e | 0 0 | (0 0) (0 0)
4059 06:01:51.164035 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4060 06:01:51.167185 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 06:01:51.173747 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 06:01:51.177265 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 06:01:51.180435 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 06:01:51.187260 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 06:01:51.190590 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 06:01:51.193633 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4067 06:01:51.200237 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4068 06:01:51.203572 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 06:01:51.206800 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 06:01:51.210498 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 06:01:51.217108 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 06:01:51.220227 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 06:01:51.223432 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 06:01:51.230268 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 06:01:51.233896 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 06:01:51.236803 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 06:01:51.243327 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 06:01:51.246436 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 06:01:51.249851 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 06:01:51.256291 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 06:01:51.260540 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 06:01:51.263194 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4083 06:01:51.269858 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4084 06:01:51.272924 Total UI for P1: 0, mck2ui 16
4085 06:01:51.276481 best dqsien dly found for B0: ( 0, 9, 8)
4086 06:01:51.279921 Total UI for P1: 0, mck2ui 16
4087 06:01:51.282838 best dqsien dly found for B1: ( 0, 9, 8)
4088 06:01:51.286409 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4089 06:01:51.289469 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4090 06:01:51.290039
4091 06:01:51.292632 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4092 06:01:51.295991 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4093 06:01:51.299298 [Gating] SW calibration Done
4094 06:01:51.299763 ==
4095 06:01:51.302954 Dram Type= 6, Freq= 0, CH_0, rank 1
4096 06:01:51.306203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4097 06:01:51.306673 ==
4098 06:01:51.309439 RX Vref Scan: 0
4099 06:01:51.310006
4100 06:01:51.310380 RX Vref 0 -> 0, step: 1
4101 06:01:51.312674
4102 06:01:51.313161 RX Delay -230 -> 252, step: 16
4103 06:01:51.319542 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4104 06:01:51.322442 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4105 06:01:51.326035 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4106 06:01:51.329367 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4107 06:01:51.335950 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4108 06:01:51.339366 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4109 06:01:51.342670 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4110 06:01:51.346179 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4111 06:01:51.349094 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4112 06:01:51.355770 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4113 06:01:51.358939 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4114 06:01:51.362412 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4115 06:01:51.365444 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4116 06:01:51.372282 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4117 06:01:51.375575 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4118 06:01:51.379057 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4119 06:01:51.379632 ==
4120 06:01:51.382162 Dram Type= 6, Freq= 0, CH_0, rank 1
4121 06:01:51.385565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4122 06:01:51.388981 ==
4123 06:01:51.389545 DQS Delay:
4124 06:01:51.389919 DQS0 = 0, DQS1 = 0
4125 06:01:51.392067 DQM Delay:
4126 06:01:51.392528 DQM0 = 42, DQM1 = 33
4127 06:01:51.395424 DQ Delay:
4128 06:01:51.398435 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =41
4129 06:01:51.398955 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4130 06:01:51.402148 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4131 06:01:51.408680 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4132 06:01:51.409299
4133 06:01:51.409675
4134 06:01:51.410016 ==
4135 06:01:51.411945 Dram Type= 6, Freq= 0, CH_0, rank 1
4136 06:01:51.415512 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4137 06:01:51.416090 ==
4138 06:01:51.416463
4139 06:01:51.416848
4140 06:01:51.418288 TX Vref Scan disable
4141 06:01:51.418751 == TX Byte 0 ==
4142 06:01:51.424982 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4143 06:01:51.428478 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4144 06:01:51.429088 == TX Byte 1 ==
4145 06:01:51.435107 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4146 06:01:51.438494 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4147 06:01:51.439067 ==
4148 06:01:51.441351 Dram Type= 6, Freq= 0, CH_0, rank 1
4149 06:01:51.444961 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4150 06:01:51.445546 ==
4151 06:01:51.445923
4152 06:01:51.448091
4153 06:01:51.448555 TX Vref Scan disable
4154 06:01:51.451659 == TX Byte 0 ==
4155 06:01:51.455207 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4156 06:01:51.458175 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4157 06:01:51.461338 == TX Byte 1 ==
4158 06:01:51.464675 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4159 06:01:51.471061 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4160 06:01:51.471536
4161 06:01:51.471903 [DATLAT]
4162 06:01:51.472247 Freq=600, CH0 RK1
4163 06:01:51.472582
4164 06:01:51.474710 DATLAT Default: 0x8
4165 06:01:51.475177 0, 0xFFFF, sum = 0
4166 06:01:51.478163 1, 0xFFFF, sum = 0
4167 06:01:51.478642 2, 0xFFFF, sum = 0
4168 06:01:51.481331 3, 0xFFFF, sum = 0
4169 06:01:51.484687 4, 0xFFFF, sum = 0
4170 06:01:51.485512 5, 0xFFFF, sum = 0
4171 06:01:51.487907 6, 0xFFFF, sum = 0
4172 06:01:51.488484 7, 0x0, sum = 1
4173 06:01:51.488922 8, 0x0, sum = 2
4174 06:01:51.491363 9, 0x0, sum = 3
4175 06:01:51.491952 10, 0x0, sum = 4
4176 06:01:51.494606 best_step = 8
4177 06:01:51.495066
4178 06:01:51.495486 ==
4179 06:01:51.497674 Dram Type= 6, Freq= 0, CH_0, rank 1
4180 06:01:51.501043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4181 06:01:51.501607 ==
4182 06:01:51.504313 RX Vref Scan: 0
4183 06:01:51.504825
4184 06:01:51.505203 RX Vref 0 -> 0, step: 1
4185 06:01:51.505548
4186 06:01:51.507749 RX Delay -195 -> 252, step: 8
4187 06:01:51.515328 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4188 06:01:51.518694 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4189 06:01:51.521720 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4190 06:01:51.525041 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4191 06:01:51.531700 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4192 06:01:51.535409 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4193 06:01:51.538698 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4194 06:01:51.541878 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4195 06:01:51.545006 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4196 06:01:51.551271 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4197 06:01:51.554932 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4198 06:01:51.558093 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4199 06:01:51.561322 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4200 06:01:51.567883 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4201 06:01:51.571475 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4202 06:01:51.574984 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4203 06:01:51.575562 ==
4204 06:01:51.577823 Dram Type= 6, Freq= 0, CH_0, rank 1
4205 06:01:51.584476 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4206 06:01:51.585033 ==
4207 06:01:51.585480 DQS Delay:
4208 06:01:51.585848 DQS0 = 0, DQS1 = 0
4209 06:01:51.588118 DQM Delay:
4210 06:01:51.588579 DQM0 = 41, DQM1 = 32
4211 06:01:51.591679 DQ Delay:
4212 06:01:51.594634 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4213 06:01:51.595102 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4214 06:01:51.597785 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4215 06:01:51.604588 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4216 06:01:51.605255
4217 06:01:51.605635
4218 06:01:51.611255 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b5b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4219 06:01:51.614316 CH0 RK1: MR19=808, MR18=5B5B
4220 06:01:51.621154 CH0_RK1: MR19=0x808, MR18=0x5B5B, DQSOSC=392, MR23=63, INC=170, DEC=113
4221 06:01:51.624265 [RxdqsGatingPostProcess] freq 600
4222 06:01:51.627894 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4223 06:01:51.631206 Pre-setting of DQS Precalculation
4224 06:01:51.637459 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4225 06:01:51.638034 ==
4226 06:01:51.640907 Dram Type= 6, Freq= 0, CH_1, rank 0
4227 06:01:51.643964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4228 06:01:51.644434 ==
4229 06:01:51.650685 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4230 06:01:51.657216 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4231 06:01:51.660742 [CA 0] Center 35 (5~66) winsize 62
4232 06:01:51.664112 [CA 1] Center 35 (5~66) winsize 62
4233 06:01:51.667428 [CA 2] Center 33 (3~64) winsize 62
4234 06:01:51.670860 [CA 3] Center 33 (3~64) winsize 62
4235 06:01:51.673715 [CA 4] Center 33 (2~64) winsize 63
4236 06:01:51.677267 [CA 5] Center 33 (2~64) winsize 63
4237 06:01:51.677873
4238 06:01:51.680545 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4239 06:01:51.681151
4240 06:01:51.683737 [CATrainingPosCal] consider 1 rank data
4241 06:01:51.686785 u2DelayCellTimex100 = 270/100 ps
4242 06:01:51.690419 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4243 06:01:51.693778 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4244 06:01:51.697062 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4245 06:01:51.700115 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4246 06:01:51.703499 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4247 06:01:51.706866 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4248 06:01:51.707332
4249 06:01:51.713456 CA PerBit enable=1, Macro0, CA PI delay=33
4250 06:01:51.714018
4251 06:01:51.714387 [CBTSetCACLKResult] CA Dly = 33
4252 06:01:51.717047 CS Dly: 4 (0~35)
4253 06:01:51.717626 ==
4254 06:01:51.719840 Dram Type= 6, Freq= 0, CH_1, rank 1
4255 06:01:51.723104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4256 06:01:51.723573 ==
4257 06:01:51.730059 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4258 06:01:51.736818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4259 06:01:51.739916 [CA 0] Center 35 (5~66) winsize 62
4260 06:01:51.743518 [CA 1] Center 34 (4~65) winsize 62
4261 06:01:51.746546 [CA 2] Center 33 (3~64) winsize 62
4262 06:01:51.749734 [CA 3] Center 33 (3~64) winsize 62
4263 06:01:51.753062 [CA 4] Center 32 (2~63) winsize 62
4264 06:01:51.756516 [CA 5] Center 32 (2~63) winsize 62
4265 06:01:51.757182
4266 06:01:51.759505 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4267 06:01:51.759969
4268 06:01:51.763240 [CATrainingPosCal] consider 2 rank data
4269 06:01:51.766329 u2DelayCellTimex100 = 270/100 ps
4270 06:01:51.769416 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4271 06:01:51.773193 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4272 06:01:51.776280 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4273 06:01:51.779459 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4274 06:01:51.786197 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4275 06:01:51.789335 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4276 06:01:51.789908
4277 06:01:51.792504 CA PerBit enable=1, Macro0, CA PI delay=32
4278 06:01:51.793127
4279 06:01:51.795912 [CBTSetCACLKResult] CA Dly = 32
4280 06:01:51.796396 CS Dly: 4 (0~35)
4281 06:01:51.796911
4282 06:01:51.799125 ----->DramcWriteLeveling(PI) begin...
4283 06:01:51.799647 ==
4284 06:01:51.802945 Dram Type= 6, Freq= 0, CH_1, rank 0
4285 06:01:51.809458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4286 06:01:51.810050 ==
4287 06:01:51.812480 Write leveling (Byte 0): 27 => 27
4288 06:01:51.813080 Write leveling (Byte 1): 27 => 27
4289 06:01:51.815609 DramcWriteLeveling(PI) end<-----
4290 06:01:51.816073
4291 06:01:51.818880 ==
4292 06:01:51.819361 Dram Type= 6, Freq= 0, CH_1, rank 0
4293 06:01:51.825551 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4294 06:01:51.826108 ==
4295 06:01:51.829207 [Gating] SW mode calibration
4296 06:01:51.835849 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4297 06:01:51.838746 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4298 06:01:51.845297 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4299 06:01:51.848916 0 5 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
4300 06:01:51.852528 0 5 8 | B1->B0 | 3333 2a2a | 0 0 | (1 1) (1 1)
4301 06:01:51.858694 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4302 06:01:51.862231 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4303 06:01:51.865331 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4304 06:01:51.872427 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4305 06:01:51.875504 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4306 06:01:51.878367 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4307 06:01:51.884885 0 6 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4308 06:01:51.888879 0 6 8 | B1->B0 | 3737 4342 | 0 1 | (0 0) (0 0)
4309 06:01:51.891461 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4310 06:01:51.898629 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4311 06:01:51.901637 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4312 06:01:51.905101 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4313 06:01:51.911763 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4314 06:01:51.915166 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4315 06:01:51.918203 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4316 06:01:51.924772 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4317 06:01:51.928380 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 06:01:51.931439 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 06:01:51.938331 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 06:01:51.941165 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 06:01:51.944631 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4322 06:01:51.950789 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4323 06:01:51.954369 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4324 06:01:51.957497 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4325 06:01:51.964136 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4326 06:01:51.967529 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4327 06:01:51.970848 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4328 06:01:51.977515 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4329 06:01:51.980871 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4330 06:01:51.984319 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4331 06:01:51.990683 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4332 06:01:51.994180 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4333 06:01:51.997563 Total UI for P1: 0, mck2ui 16
4334 06:01:52.000500 best dqsien dly found for B0: ( 0, 9, 4)
4335 06:01:52.003871 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4336 06:01:52.007134 Total UI for P1: 0, mck2ui 16
4337 06:01:52.010341 best dqsien dly found for B1: ( 0, 9, 8)
4338 06:01:52.013884 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4339 06:01:52.016821 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4340 06:01:52.017290
4341 06:01:52.023841 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4342 06:01:52.027167 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4343 06:01:52.027728 [Gating] SW calibration Done
4344 06:01:52.030143 ==
4345 06:01:52.030608 Dram Type= 6, Freq= 0, CH_1, rank 0
4346 06:01:52.036934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4347 06:01:52.037517 ==
4348 06:01:52.037892 RX Vref Scan: 0
4349 06:01:52.038240
4350 06:01:52.040481 RX Vref 0 -> 0, step: 1
4351 06:01:52.041100
4352 06:01:52.043638 RX Delay -230 -> 252, step: 16
4353 06:01:52.046765 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4354 06:01:52.049972 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4355 06:01:52.056774 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4356 06:01:52.060453 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4357 06:01:52.063076 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4358 06:01:52.066727 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4359 06:01:52.069878 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4360 06:01:52.076602 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4361 06:01:52.079818 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4362 06:01:52.082987 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4363 06:01:52.086358 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4364 06:01:52.093239 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4365 06:01:52.096504 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4366 06:01:52.099548 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4367 06:01:52.103209 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4368 06:01:52.109705 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4369 06:01:52.110282 ==
4370 06:01:52.112755 Dram Type= 6, Freq= 0, CH_1, rank 0
4371 06:01:52.115998 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4372 06:01:52.116460 ==
4373 06:01:52.116862 DQS Delay:
4374 06:01:52.119354 DQS0 = 0, DQS1 = 0
4375 06:01:52.119814 DQM Delay:
4376 06:01:52.122636 DQM0 = 38, DQM1 = 30
4377 06:01:52.123098 DQ Delay:
4378 06:01:52.126291 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4379 06:01:52.129334 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4380 06:01:52.132814 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4381 06:01:52.136281 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4382 06:01:52.136889
4383 06:01:52.137311
4384 06:01:52.137656 ==
4385 06:01:52.139400 Dram Type= 6, Freq= 0, CH_1, rank 0
4386 06:01:52.142554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4387 06:01:52.145808 ==
4388 06:01:52.146267
4389 06:01:52.146629
4390 06:01:52.146964 TX Vref Scan disable
4391 06:01:52.149437 == TX Byte 0 ==
4392 06:01:52.152337 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4393 06:01:52.159134 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4394 06:01:52.159697 == TX Byte 1 ==
4395 06:01:52.162244 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4396 06:01:52.169000 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4397 06:01:52.169571 ==
4398 06:01:52.172358 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 06:01:52.176090 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4400 06:01:52.176662 ==
4401 06:01:52.177092
4402 06:01:52.177434
4403 06:01:52.178984 TX Vref Scan disable
4404 06:01:52.182522 == TX Byte 0 ==
4405 06:01:52.185435 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4406 06:01:52.189079 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4407 06:01:52.192437 == TX Byte 1 ==
4408 06:01:52.195281 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4409 06:01:52.198754 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4410 06:01:52.199326
4411 06:01:52.199688 [DATLAT]
4412 06:01:52.202055 Freq=600, CH1 RK0
4413 06:01:52.202619
4414 06:01:52.205439 DATLAT Default: 0x9
4415 06:01:52.206006 0, 0xFFFF, sum = 0
4416 06:01:52.208740 1, 0xFFFF, sum = 0
4417 06:01:52.209319 2, 0xFFFF, sum = 0
4418 06:01:52.211994 3, 0xFFFF, sum = 0
4419 06:01:52.212566 4, 0xFFFF, sum = 0
4420 06:01:52.215302 5, 0xFFFF, sum = 0
4421 06:01:52.215874 6, 0xFFFF, sum = 0
4422 06:01:52.218717 7, 0x0, sum = 1
4423 06:01:52.219283 8, 0x0, sum = 2
4424 06:01:52.219656 9, 0x0, sum = 3
4425 06:01:52.222016 10, 0x0, sum = 4
4426 06:01:52.222585 best_step = 8
4427 06:01:52.222952
4428 06:01:52.224912 ==
4429 06:01:52.225413 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 06:01:52.231706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4431 06:01:52.232339 ==
4432 06:01:52.232757 RX Vref Scan: 1
4433 06:01:52.233110
4434 06:01:52.235329 RX Vref 0 -> 0, step: 1
4435 06:01:52.235889
4436 06:01:52.238568 RX Delay -195 -> 252, step: 8
4437 06:01:52.239138
4438 06:01:52.241808 Set Vref, RX VrefLevel [Byte0]: 56
4439 06:01:52.245036 [Byte1]: 47
4440 06:01:52.245500
4441 06:01:52.248150 Final RX Vref Byte 0 = 56 to rank0
4442 06:01:52.251592 Final RX Vref Byte 1 = 47 to rank0
4443 06:01:52.254749 Final RX Vref Byte 0 = 56 to rank1
4444 06:01:52.258298 Final RX Vref Byte 1 = 47 to rank1==
4445 06:01:52.261394 Dram Type= 6, Freq= 0, CH_1, rank 0
4446 06:01:52.264644 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4447 06:01:52.267968 ==
4448 06:01:52.268540 DQS Delay:
4449 06:01:52.268979 DQS0 = 0, DQS1 = 0
4450 06:01:52.271166 DQM Delay:
4451 06:01:52.271627 DQM0 = 37, DQM1 = 31
4452 06:01:52.274720 DQ Delay:
4453 06:01:52.275290 DQ0 =44, DQ1 =28, DQ2 =28, DQ3 =36
4454 06:01:52.277939 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4455 06:01:52.281545 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4456 06:01:52.284967 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4457 06:01:52.285561
4458 06:01:52.287801
4459 06:01:52.294487 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c6c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4460 06:01:52.297616 CH1 RK0: MR19=808, MR18=6C6C
4461 06:01:52.304447 CH1_RK0: MR19=0x808, MR18=0x6C6C, DQSOSC=389, MR23=63, INC=173, DEC=115
4462 06:01:52.305061
4463 06:01:52.307744 ----->DramcWriteLeveling(PI) begin...
4464 06:01:52.308320 ==
4465 06:01:52.310793 Dram Type= 6, Freq= 0, CH_1, rank 1
4466 06:01:52.314039 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4467 06:01:52.314507 ==
4468 06:01:52.317372 Write leveling (Byte 0): 26 => 26
4469 06:01:52.320501 Write leveling (Byte 1): 30 => 30
4470 06:01:52.324374 DramcWriteLeveling(PI) end<-----
4471 06:01:52.324989
4472 06:01:52.325367 ==
4473 06:01:52.327489 Dram Type= 6, Freq= 0, CH_1, rank 1
4474 06:01:52.330544 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4475 06:01:52.331016 ==
4476 06:01:52.334237 [Gating] SW mode calibration
4477 06:01:52.340837 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4478 06:01:52.347192 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4479 06:01:52.350673 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4480 06:01:52.356980 0 5 4 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
4481 06:01:52.360476 0 5 8 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4482 06:01:52.363677 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 06:01:52.370671 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 06:01:52.373644 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 06:01:52.377293 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 06:01:52.380529 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 06:01:52.386653 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 06:01:52.390345 0 6 4 | B1->B0 | 2626 2e2e | 0 0 | (1 1) (0 0)
4489 06:01:52.396980 0 6 8 | B1->B0 | 3434 4141 | 0 0 | (0 0) (0 0)
4490 06:01:52.400172 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 06:01:52.403368 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 06:01:52.410149 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 06:01:52.413427 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 06:01:52.416320 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 06:01:52.423216 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 06:01:52.426437 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4497 06:01:52.429703 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 06:01:52.436315 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 06:01:52.439869 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 06:01:52.443279 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 06:01:52.449439 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 06:01:52.452744 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 06:01:52.456012 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 06:01:52.463069 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 06:01:52.466212 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 06:01:52.469282 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 06:01:52.472916 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 06:01:52.479188 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 06:01:52.482829 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 06:01:52.486016 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 06:01:52.492783 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4512 06:01:52.495628 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4513 06:01:52.502065 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4514 06:01:52.502534 Total UI for P1: 0, mck2ui 16
4515 06:01:52.505659 best dqsien dly found for B0: ( 0, 9, 2)
4516 06:01:52.512601 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 06:01:52.515563 Total UI for P1: 0, mck2ui 16
4518 06:01:52.519291 best dqsien dly found for B1: ( 0, 9, 8)
4519 06:01:52.522221 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4520 06:01:52.525858 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4521 06:01:52.526415
4522 06:01:52.529045 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4523 06:01:52.532771 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4524 06:01:52.535573 [Gating] SW calibration Done
4525 06:01:52.536133 ==
4526 06:01:52.538772 Dram Type= 6, Freq= 0, CH_1, rank 1
4527 06:01:52.542090 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4528 06:01:52.542654 ==
4529 06:01:52.545639 RX Vref Scan: 0
4530 06:01:52.546203
4531 06:01:52.546572 RX Vref 0 -> 0, step: 1
4532 06:01:52.548822
4533 06:01:52.549412 RX Delay -230 -> 252, step: 16
4534 06:01:52.555086 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4535 06:01:52.558659 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4536 06:01:52.561951 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4537 06:01:52.564837 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4538 06:01:52.571766 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4539 06:01:52.575199 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4540 06:01:52.578202 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4541 06:01:52.581448 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4542 06:01:52.587967 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4543 06:01:52.591317 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4544 06:01:52.594760 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4545 06:01:52.597901 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4546 06:01:52.601494 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4547 06:01:52.608030 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4548 06:01:52.611228 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4549 06:01:52.614936 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4550 06:01:52.615417 ==
4551 06:01:52.618027 Dram Type= 6, Freq= 0, CH_1, rank 1
4552 06:01:52.624458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4553 06:01:52.625087 ==
4554 06:01:52.625468 DQS Delay:
4555 06:01:52.625812 DQS0 = 0, DQS1 = 0
4556 06:01:52.628177 DQM Delay:
4557 06:01:52.628672 DQM0 = 39, DQM1 = 34
4558 06:01:52.631195 DQ Delay:
4559 06:01:52.634304 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4560 06:01:52.637638 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4561 06:01:52.640961 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4562 06:01:52.644823 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4563 06:01:52.645514
4564 06:01:52.645896
4565 06:01:52.646239 ==
4566 06:01:52.647556 Dram Type= 6, Freq= 0, CH_1, rank 1
4567 06:01:52.650844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4568 06:01:52.651311 ==
4569 06:01:52.651678
4570 06:01:52.652020
4571 06:01:52.654222 TX Vref Scan disable
4572 06:01:52.657508 == TX Byte 0 ==
4573 06:01:52.660775 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4574 06:01:52.664292 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4575 06:01:52.667776 == TX Byte 1 ==
4576 06:01:52.670923 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4577 06:01:52.673963 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4578 06:01:52.674431 ==
4579 06:01:52.677413 Dram Type= 6, Freq= 0, CH_1, rank 1
4580 06:01:52.680312 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4581 06:01:52.684193 ==
4582 06:01:52.684790
4583 06:01:52.685164
4584 06:01:52.685501 TX Vref Scan disable
4585 06:01:52.687792 == TX Byte 0 ==
4586 06:01:52.691174 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4587 06:01:52.697644 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4588 06:01:52.698302 == TX Byte 1 ==
4589 06:01:52.701042 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4590 06:01:52.707659 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4591 06:01:52.708220
4592 06:01:52.708586 [DATLAT]
4593 06:01:52.708980 Freq=600, CH1 RK1
4594 06:01:52.709317
4595 06:01:52.711016 DATLAT Default: 0x8
4596 06:01:52.711603 0, 0xFFFF, sum = 0
4597 06:01:52.714386 1, 0xFFFF, sum = 0
4598 06:01:52.717613 2, 0xFFFF, sum = 0
4599 06:01:52.718180 3, 0xFFFF, sum = 0
4600 06:01:52.720812 4, 0xFFFF, sum = 0
4601 06:01:52.721375 5, 0xFFFF, sum = 0
4602 06:01:52.723989 6, 0xFFFF, sum = 0
4603 06:01:52.724459 7, 0x0, sum = 1
4604 06:01:52.724881 8, 0x0, sum = 2
4605 06:01:52.727176 9, 0x0, sum = 3
4606 06:01:52.727648 10, 0x0, sum = 4
4607 06:01:52.730856 best_step = 8
4608 06:01:52.731417
4609 06:01:52.731788 ==
4610 06:01:52.734247 Dram Type= 6, Freq= 0, CH_1, rank 1
4611 06:01:52.737429 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4612 06:01:52.737987 ==
4613 06:01:52.740620 RX Vref Scan: 0
4614 06:01:52.741209
4615 06:01:52.741580 RX Vref 0 -> 0, step: 1
4616 06:01:52.741923
4617 06:01:52.743858 RX Delay -195 -> 252, step: 8
4618 06:01:52.751265 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4619 06:01:52.754546 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4620 06:01:52.757775 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4621 06:01:52.761102 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4622 06:01:52.768634 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4623 06:01:52.771571 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4624 06:01:52.774407 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4625 06:01:52.778281 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4626 06:01:52.784592 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4627 06:01:52.787680 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4628 06:01:52.791139 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4629 06:01:52.794676 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4630 06:01:52.800809 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4631 06:01:52.804699 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4632 06:01:52.807609 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4633 06:01:52.811171 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4634 06:01:52.811810 ==
4635 06:01:52.814121 Dram Type= 6, Freq= 0, CH_1, rank 1
4636 06:01:52.820996 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4637 06:01:52.821715 ==
4638 06:01:52.822103 DQS Delay:
4639 06:01:52.824049 DQS0 = 0, DQS1 = 0
4640 06:01:52.824512 DQM Delay:
4641 06:01:52.824919 DQM0 = 37, DQM1 = 29
4642 06:01:52.827204 DQ Delay:
4643 06:01:52.830965 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4644 06:01:52.834180 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =36
4645 06:01:52.837457 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4646 06:01:52.841101 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4647 06:01:52.841660
4648 06:01:52.842031
4649 06:01:52.847022 [DQSOSCAuto] RK1, (LSB)MR18= 0x5555, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4650 06:01:52.850678 CH1 RK1: MR19=808, MR18=5555
4651 06:01:52.857164 CH1_RK1: MR19=0x808, MR18=0x5555, DQSOSC=393, MR23=63, INC=169, DEC=113
4652 06:01:52.860855 [RxdqsGatingPostProcess] freq 600
4653 06:01:52.863834 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4654 06:01:52.867360 Pre-setting of DQS Precalculation
4655 06:01:52.873780 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4656 06:01:52.880832 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4657 06:01:52.886964 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4658 06:01:52.887534
4659 06:01:52.887902
4660 06:01:52.890273 [Calibration Summary] 1200 Mbps
4661 06:01:52.890740 CH 0, Rank 0
4662 06:01:52.893667 SW Impedance : PASS
4663 06:01:52.897104 DUTY Scan : NO K
4664 06:01:52.897736 ZQ Calibration : PASS
4665 06:01:52.900639 Jitter Meter : NO K
4666 06:01:52.903521 CBT Training : PASS
4667 06:01:52.903987 Write leveling : PASS
4668 06:01:52.907222 RX DQS gating : PASS
4669 06:01:52.910024 RX DQ/DQS(RDDQC) : PASS
4670 06:01:52.910493 TX DQ/DQS : PASS
4671 06:01:52.913714 RX DATLAT : PASS
4672 06:01:52.916918 RX DQ/DQS(Engine): PASS
4673 06:01:52.917423 TX OE : NO K
4674 06:01:52.917810 All Pass.
4675 06:01:52.920411
4676 06:01:52.921020 CH 0, Rank 1
4677 06:01:52.923628 SW Impedance : PASS
4678 06:01:52.924091 DUTY Scan : NO K
4679 06:01:52.926524 ZQ Calibration : PASS
4680 06:01:52.930346 Jitter Meter : NO K
4681 06:01:52.930905 CBT Training : PASS
4682 06:01:52.933224 Write leveling : PASS
4683 06:01:52.933691 RX DQS gating : PASS
4684 06:01:52.936590 RX DQ/DQS(RDDQC) : PASS
4685 06:01:52.940294 TX DQ/DQS : PASS
4686 06:01:52.940896 RX DATLAT : PASS
4687 06:01:52.943635 RX DQ/DQS(Engine): PASS
4688 06:01:52.946709 TX OE : NO K
4689 06:01:52.947177 All Pass.
4690 06:01:52.947544
4691 06:01:52.947883 CH 1, Rank 0
4692 06:01:52.950108 SW Impedance : PASS
4693 06:01:52.953487 DUTY Scan : NO K
4694 06:01:52.953953 ZQ Calibration : PASS
4695 06:01:52.956647 Jitter Meter : NO K
4696 06:01:52.959705 CBT Training : PASS
4697 06:01:52.960171 Write leveling : PASS
4698 06:01:52.963376 RX DQS gating : PASS
4699 06:01:52.966316 RX DQ/DQS(RDDQC) : PASS
4700 06:01:52.966780 TX DQ/DQS : PASS
4701 06:01:52.969538 RX DATLAT : PASS
4702 06:01:52.972877 RX DQ/DQS(Engine): PASS
4703 06:01:52.973345 TX OE : NO K
4704 06:01:52.976946 All Pass.
4705 06:01:52.977502
4706 06:01:52.977870 CH 1, Rank 1
4707 06:01:52.979843 SW Impedance : PASS
4708 06:01:52.980399 DUTY Scan : NO K
4709 06:01:52.983281 ZQ Calibration : PASS
4710 06:01:52.986179 Jitter Meter : NO K
4711 06:01:52.986645 CBT Training : PASS
4712 06:01:52.989564 Write leveling : PASS
4713 06:01:52.990120 RX DQS gating : PASS
4714 06:01:52.993005 RX DQ/DQS(RDDQC) : PASS
4715 06:01:52.996504 TX DQ/DQS : PASS
4716 06:01:52.997111 RX DATLAT : PASS
4717 06:01:52.999407 RX DQ/DQS(Engine): PASS
4718 06:01:53.002772 TX OE : NO K
4719 06:01:53.003239 All Pass.
4720 06:01:53.003609
4721 06:01:53.006007 DramC Write-DBI off
4722 06:01:53.006473 PER_BANK_REFRESH: Hybrid Mode
4723 06:01:53.009327 TX_TRACKING: ON
4724 06:01:53.019664 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4725 06:01:53.022609 [FAST_K] Save calibration result to emmc
4726 06:01:53.026128 dramc_set_vcore_voltage set vcore to 662500
4727 06:01:53.026689 Read voltage for 933, 3
4728 06:01:53.029398 Vio18 = 0
4729 06:01:53.029964 Vcore = 662500
4730 06:01:53.030333 Vdram = 0
4731 06:01:53.032542 Vddq = 0
4732 06:01:53.033042 Vmddr = 0
4733 06:01:53.036112 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4734 06:01:53.042650 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4735 06:01:53.045732 MEM_TYPE=3, freq_sel=17
4736 06:01:53.049037 sv_algorithm_assistance_LP4_1600
4737 06:01:53.052374 ============ PULL DRAM RESETB DOWN ============
4738 06:01:53.055798 ========== PULL DRAM RESETB DOWN end =========
4739 06:01:53.062740 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4740 06:01:53.066113 ===================================
4741 06:01:53.066686 LPDDR4 DRAM CONFIGURATION
4742 06:01:53.068937 ===================================
4743 06:01:53.072467 EX_ROW_EN[0] = 0x0
4744 06:01:53.073093 EX_ROW_EN[1] = 0x0
4745 06:01:53.075822 LP4Y_EN = 0x0
4746 06:01:53.079254 WORK_FSP = 0x0
4747 06:01:53.079828 WL = 0x3
4748 06:01:53.082512 RL = 0x3
4749 06:01:53.083084 BL = 0x2
4750 06:01:53.085507 RPST = 0x0
4751 06:01:53.085975 RD_PRE = 0x0
4752 06:01:53.088904 WR_PRE = 0x1
4753 06:01:53.089398 WR_PST = 0x0
4754 06:01:53.092077 DBI_WR = 0x0
4755 06:01:53.092542 DBI_RD = 0x0
4756 06:01:53.095523 OTF = 0x1
4757 06:01:53.098856 ===================================
4758 06:01:53.102161 ===================================
4759 06:01:53.102742 ANA top config
4760 06:01:53.105315 ===================================
4761 06:01:53.108768 DLL_ASYNC_EN = 0
4762 06:01:53.111966 ALL_SLAVE_EN = 1
4763 06:01:53.115379 NEW_RANK_MODE = 1
4764 06:01:53.115977 DLL_IDLE_MODE = 1
4765 06:01:53.118981 LP45_APHY_COMB_EN = 1
4766 06:01:53.122062 TX_ODT_DIS = 1
4767 06:01:53.125388 NEW_8X_MODE = 1
4768 06:01:53.128551 ===================================
4769 06:01:53.132049 ===================================
4770 06:01:53.135488 data_rate = 1866
4771 06:01:53.136072 CKR = 1
4772 06:01:53.138089 DQ_P2S_RATIO = 8
4773 06:01:53.141626 ===================================
4774 06:01:53.144759 CA_P2S_RATIO = 8
4775 06:01:53.147900 DQ_CA_OPEN = 0
4776 06:01:53.151442 DQ_SEMI_OPEN = 0
4777 06:01:53.154700 CA_SEMI_OPEN = 0
4778 06:01:53.155183 CA_FULL_RATE = 0
4779 06:01:53.158278 DQ_CKDIV4_EN = 1
4780 06:01:53.161446 CA_CKDIV4_EN = 1
4781 06:01:53.164903 CA_PREDIV_EN = 0
4782 06:01:53.168200 PH8_DLY = 0
4783 06:01:53.171567 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4784 06:01:53.172133 DQ_AAMCK_DIV = 4
4785 06:01:53.174671 CA_AAMCK_DIV = 4
4786 06:01:53.178095 CA_ADMCK_DIV = 4
4787 06:01:53.181223 DQ_TRACK_CA_EN = 0
4788 06:01:53.184789 CA_PICK = 933
4789 06:01:53.187999 CA_MCKIO = 933
4790 06:01:53.191444 MCKIO_SEMI = 0
4791 06:01:53.192003 PLL_FREQ = 3732
4792 06:01:53.194284 DQ_UI_PI_RATIO = 32
4793 06:01:53.197940 CA_UI_PI_RATIO = 0
4794 06:01:53.200913 ===================================
4795 06:01:53.204393 ===================================
4796 06:01:53.207664 memory_type:LPDDR4
4797 06:01:53.211066 GP_NUM : 10
4798 06:01:53.211659 SRAM_EN : 1
4799 06:01:53.214083 MD32_EN : 0
4800 06:01:53.217617 ===================================
4801 06:01:53.218207 [ANA_INIT] >>>>>>>>>>>>>>
4802 06:01:53.220565 <<<<<< [CONFIGURE PHASE]: ANA_TX
4803 06:01:53.223912 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4804 06:01:53.227286 ===================================
4805 06:01:53.230508 data_rate = 1866,PCW = 0X8f00
4806 06:01:53.234015 ===================================
4807 06:01:53.237353 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4808 06:01:53.244103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4809 06:01:53.247202 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4810 06:01:53.253983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4811 06:01:53.257349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4812 06:01:53.260493 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4813 06:01:53.263964 [ANA_INIT] flow start
4814 06:01:53.264522 [ANA_INIT] PLL >>>>>>>>
4815 06:01:53.267214 [ANA_INIT] PLL <<<<<<<<
4816 06:01:53.270595 [ANA_INIT] MIDPI >>>>>>>>
4817 06:01:53.271059 [ANA_INIT] MIDPI <<<<<<<<
4818 06:01:53.273616 [ANA_INIT] DLL >>>>>>>>
4819 06:01:53.277183 [ANA_INIT] flow end
4820 06:01:53.280619 ============ LP4 DIFF to SE enter ============
4821 06:01:53.284334 ============ LP4 DIFF to SE exit ============
4822 06:01:53.286934 [ANA_INIT] <<<<<<<<<<<<<
4823 06:01:53.290522 [Flow] Enable top DCM control >>>>>
4824 06:01:53.293953 [Flow] Enable top DCM control <<<<<
4825 06:01:53.296829 Enable DLL master slave shuffle
4826 06:01:53.300289 ==============================================================
4827 06:01:53.303316 Gating Mode config
4828 06:01:53.310235 ==============================================================
4829 06:01:53.310794 Config description:
4830 06:01:53.320027 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4831 06:01:53.326607 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4832 06:01:53.333413 SELPH_MODE 0: By rank 1: By Phase
4833 06:01:53.336803 ==============================================================
4834 06:01:53.339818 GAT_TRACK_EN = 1
4835 06:01:53.343229 RX_GATING_MODE = 2
4836 06:01:53.346398 RX_GATING_TRACK_MODE = 2
4837 06:01:53.349455 SELPH_MODE = 1
4838 06:01:53.353186 PICG_EARLY_EN = 1
4839 06:01:53.356252 VALID_LAT_VALUE = 1
4840 06:01:53.359433 ==============================================================
4841 06:01:53.363079 Enter into Gating configuration >>>>
4842 06:01:53.366645 Exit from Gating configuration <<<<
4843 06:01:53.369470 Enter into DVFS_PRE_config >>>>>
4844 06:01:53.383022 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4845 06:01:53.385945 Exit from DVFS_PRE_config <<<<<
4846 06:01:53.389439 Enter into PICG configuration >>>>
4847 06:01:53.393024 Exit from PICG configuration <<<<
4848 06:01:53.393589 [RX_INPUT] configuration >>>>>
4849 06:01:53.396374 [RX_INPUT] configuration <<<<<
4850 06:01:53.402624 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4851 06:01:53.405995 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4852 06:01:53.412862 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4853 06:01:53.419572 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4854 06:01:53.425561 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4855 06:01:53.432541 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4856 06:01:53.435839 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4857 06:01:53.439217 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4858 06:01:53.445380 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4859 06:01:53.449004 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4860 06:01:53.452227 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4861 06:01:53.455795 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4862 06:01:53.458944 ===================================
4863 06:01:53.462692 LPDDR4 DRAM CONFIGURATION
4864 06:01:53.465545 ===================================
4865 06:01:53.468940 EX_ROW_EN[0] = 0x0
4866 06:01:53.469511 EX_ROW_EN[1] = 0x0
4867 06:01:53.472410 LP4Y_EN = 0x0
4868 06:01:53.473025 WORK_FSP = 0x0
4869 06:01:53.475554 WL = 0x3
4870 06:01:53.476109 RL = 0x3
4871 06:01:53.479378 BL = 0x2
4872 06:01:53.479936 RPST = 0x0
4873 06:01:53.482157 RD_PRE = 0x0
4874 06:01:53.482615 WR_PRE = 0x1
4875 06:01:53.485547 WR_PST = 0x0
4876 06:01:53.489107 DBI_WR = 0x0
4877 06:01:53.489664 DBI_RD = 0x0
4878 06:01:53.492128 OTF = 0x1
4879 06:01:53.495617 ===================================
4880 06:01:53.498847 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4881 06:01:53.501882 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4882 06:01:53.505235 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4883 06:01:53.508793 ===================================
4884 06:01:53.511762 LPDDR4 DRAM CONFIGURATION
4885 06:01:53.515209 ===================================
4886 06:01:53.518412 EX_ROW_EN[0] = 0x10
4887 06:01:53.518867 EX_ROW_EN[1] = 0x0
4888 06:01:53.521602 LP4Y_EN = 0x0
4889 06:01:53.522062 WORK_FSP = 0x0
4890 06:01:53.525036 WL = 0x3
4891 06:01:53.525491 RL = 0x3
4892 06:01:53.528318 BL = 0x2
4893 06:01:53.528806 RPST = 0x0
4894 06:01:53.531847 RD_PRE = 0x0
4895 06:01:53.532434 WR_PRE = 0x1
4896 06:01:53.535182 WR_PST = 0x0
4897 06:01:53.535756 DBI_WR = 0x0
4898 06:01:53.538206 DBI_RD = 0x0
4899 06:01:53.541638 OTF = 0x1
4900 06:01:53.544872 ===================================
4901 06:01:53.548317 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4902 06:01:53.553319 nWR fixed to 30
4903 06:01:53.556805 [ModeRegInit_LP4] CH0 RK0
4904 06:01:53.557371 [ModeRegInit_LP4] CH0 RK1
4905 06:01:53.559903 [ModeRegInit_LP4] CH1 RK0
4906 06:01:53.563765 [ModeRegInit_LP4] CH1 RK1
4907 06:01:53.564359 match AC timing 8
4908 06:01:53.569811 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4909 06:01:53.573252 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4910 06:01:53.576814 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4911 06:01:53.583237 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4912 06:01:53.586492 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4913 06:01:53.587016 ==
4914 06:01:53.589701 Dram Type= 6, Freq= 0, CH_0, rank 0
4915 06:01:53.593304 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4916 06:01:53.593864 ==
4917 06:01:53.599863 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4918 06:01:53.606868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4919 06:01:53.609978 [CA 0] Center 38 (8~69) winsize 62
4920 06:01:53.612924 [CA 1] Center 38 (8~69) winsize 62
4921 06:01:53.616582 [CA 2] Center 36 (6~67) winsize 62
4922 06:01:53.619654 [CA 3] Center 35 (5~66) winsize 62
4923 06:01:53.622975 [CA 4] Center 35 (5~65) winsize 61
4924 06:01:53.626284 [CA 5] Center 34 (4~65) winsize 62
4925 06:01:53.626837
4926 06:01:53.629476 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4927 06:01:53.630031
4928 06:01:53.633067 [CATrainingPosCal] consider 1 rank data
4929 06:01:53.636169 u2DelayCellTimex100 = 270/100 ps
4930 06:01:53.639562 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4931 06:01:53.643064 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4932 06:01:53.646460 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4933 06:01:53.649304 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4934 06:01:53.652651 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4935 06:01:53.659434 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4936 06:01:53.660004
4937 06:01:53.662798 CA PerBit enable=1, Macro0, CA PI delay=34
4938 06:01:53.663383
4939 06:01:53.666173 [CBTSetCACLKResult] CA Dly = 34
4940 06:01:53.666635 CS Dly: 7 (0~38)
4941 06:01:53.667003 ==
4942 06:01:53.669125 Dram Type= 6, Freq= 0, CH_0, rank 1
4943 06:01:53.672496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4944 06:01:53.676334 ==
4945 06:01:53.679368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4946 06:01:53.686055 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4947 06:01:53.689107 [CA 0] Center 38 (8~69) winsize 62
4948 06:01:53.692558 [CA 1] Center 38 (7~69) winsize 63
4949 06:01:53.695575 [CA 2] Center 36 (5~67) winsize 63
4950 06:01:53.699193 [CA 3] Center 35 (5~66) winsize 62
4951 06:01:53.702192 [CA 4] Center 34 (4~65) winsize 62
4952 06:01:53.705768 [CA 5] Center 34 (4~65) winsize 62
4953 06:01:53.706326
4954 06:01:53.708980 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4955 06:01:53.709536
4956 06:01:53.712537 [CATrainingPosCal] consider 2 rank data
4957 06:01:53.715653 u2DelayCellTimex100 = 270/100 ps
4958 06:01:53.719009 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4959 06:01:53.722417 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4960 06:01:53.725925 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4961 06:01:53.732168 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4962 06:01:53.735428 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4963 06:01:53.738830 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4964 06:01:53.739421
4965 06:01:53.742089 CA PerBit enable=1, Macro0, CA PI delay=34
4966 06:01:53.742651
4967 06:01:53.745193 [CBTSetCACLKResult] CA Dly = 34
4968 06:01:53.745662 CS Dly: 7 (0~39)
4969 06:01:53.746028
4970 06:01:53.748752 ----->DramcWriteLeveling(PI) begin...
4971 06:01:53.749225 ==
4972 06:01:53.752197 Dram Type= 6, Freq= 0, CH_0, rank 0
4973 06:01:53.758562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4974 06:01:53.759111 ==
4975 06:01:53.761815 Write leveling (Byte 0): 28 => 28
4976 06:01:53.765080 Write leveling (Byte 1): 28 => 28
4977 06:01:53.765547 DramcWriteLeveling(PI) end<-----
4978 06:01:53.768613
4979 06:01:53.769132 ==
4980 06:01:53.771624 Dram Type= 6, Freq= 0, CH_0, rank 0
4981 06:01:53.775112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4982 06:01:53.775592 ==
4983 06:01:53.778878 [Gating] SW mode calibration
4984 06:01:53.785639 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4985 06:01:53.788494 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4986 06:01:53.795280 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4987 06:01:53.798222 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4988 06:01:53.801638 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4989 06:01:53.808444 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4990 06:01:53.811906 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4991 06:01:53.814747 0 10 20 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
4992 06:01:53.821526 0 10 24 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (1 0)
4993 06:01:53.824969 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4994 06:01:53.828321 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4995 06:01:53.834915 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4996 06:01:53.838074 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4997 06:01:53.841645 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4998 06:01:53.848370 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4999 06:01:53.851316 0 11 20 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (0 0)
5000 06:01:53.855065 0 11 24 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5001 06:01:53.861913 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5002 06:01:53.864688 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5003 06:01:53.868018 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5004 06:01:53.874360 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5005 06:01:53.878136 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5006 06:01:53.880912 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5007 06:01:53.887658 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5008 06:01:53.890922 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5009 06:01:53.894526 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 06:01:53.901181 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5011 06:01:53.904370 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5012 06:01:53.907989 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5013 06:01:53.914388 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5014 06:01:53.917632 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5015 06:01:53.921102 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5016 06:01:53.927705 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5017 06:01:53.930550 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5018 06:01:53.934425 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5019 06:01:53.940669 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5020 06:01:53.944006 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5021 06:01:53.947283 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5022 06:01:53.953631 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5023 06:01:53.957107 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5024 06:01:53.960611 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5025 06:01:53.967118 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5026 06:01:53.967688 Total UI for P1: 0, mck2ui 16
5027 06:01:53.973437 best dqsien dly found for B0: ( 0, 14, 22)
5028 06:01:53.973915 Total UI for P1: 0, mck2ui 16
5029 06:01:53.980305 best dqsien dly found for B1: ( 0, 14, 22)
5030 06:01:53.983504 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5031 06:01:53.987058 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5032 06:01:53.987662
5033 06:01:53.990003 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5034 06:01:53.993248 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5035 06:01:53.997322 [Gating] SW calibration Done
5036 06:01:53.997878 ==
5037 06:01:54.000094 Dram Type= 6, Freq= 0, CH_0, rank 0
5038 06:01:54.003247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5039 06:01:54.003746 ==
5040 06:01:54.006895 RX Vref Scan: 0
5041 06:01:54.007457
5042 06:01:54.007820 RX Vref 0 -> 0, step: 1
5043 06:01:54.008159
5044 06:01:54.010064 RX Delay -80 -> 252, step: 8
5045 06:01:54.016866 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5046 06:01:54.020123 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5047 06:01:54.023453 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5048 06:01:54.026799 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5049 06:01:54.030047 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5050 06:01:54.033175 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5051 06:01:54.036441 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5052 06:01:54.043071 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5053 06:01:54.046486 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5054 06:01:54.049572 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5055 06:01:54.052929 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5056 06:01:54.056300 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5057 06:01:54.062784 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5058 06:01:54.066264 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5059 06:01:54.069408 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5060 06:01:54.072571 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5061 06:01:54.073102 ==
5062 06:01:54.076045 Dram Type= 6, Freq= 0, CH_0, rank 0
5063 06:01:54.082471 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5064 06:01:54.082948 ==
5065 06:01:54.083438 DQS Delay:
5066 06:01:54.085578 DQS0 = 0, DQS1 = 0
5067 06:01:54.086066 DQM Delay:
5068 06:01:54.086543 DQM0 = 95, DQM1 = 87
5069 06:01:54.088827 DQ Delay:
5070 06:01:54.092339 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5071 06:01:54.095670 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5072 06:01:54.098806 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5073 06:01:54.102240 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5074 06:01:54.102733
5075 06:01:54.103156
5076 06:01:54.103522 ==
5077 06:01:54.105507 Dram Type= 6, Freq= 0, CH_0, rank 0
5078 06:01:54.108798 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5079 06:01:54.109267 ==
5080 06:01:54.109633
5081 06:01:54.109985
5082 06:01:54.112462 TX Vref Scan disable
5083 06:01:54.113136 == TX Byte 0 ==
5084 06:01:54.118972 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5085 06:01:54.122310 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5086 06:01:54.122885 == TX Byte 1 ==
5087 06:01:54.128761 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5088 06:01:54.132011 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5089 06:01:54.132473 ==
5090 06:01:54.135512 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 06:01:54.138610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5092 06:01:54.139074 ==
5093 06:01:54.142111
5094 06:01:54.142674
5095 06:01:54.143043 TX Vref Scan disable
5096 06:01:54.145519 == TX Byte 0 ==
5097 06:01:54.148789 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5098 06:01:54.151993 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5099 06:01:54.155575 == TX Byte 1 ==
5100 06:01:54.158647 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5101 06:01:54.165120 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5102 06:01:54.165677
5103 06:01:54.166044 [DATLAT]
5104 06:01:54.166385 Freq=933, CH0 RK0
5105 06:01:54.166714
5106 06:01:54.168463 DATLAT Default: 0xd
5107 06:01:54.168983 0, 0xFFFF, sum = 0
5108 06:01:54.171672 1, 0xFFFF, sum = 0
5109 06:01:54.172142 2, 0xFFFF, sum = 0
5110 06:01:54.175302 3, 0xFFFF, sum = 0
5111 06:01:54.178645 4, 0xFFFF, sum = 0
5112 06:01:54.179224 5, 0xFFFF, sum = 0
5113 06:01:54.181650 6, 0xFFFF, sum = 0
5114 06:01:54.182121 7, 0xFFFF, sum = 0
5115 06:01:54.185110 8, 0xFFFF, sum = 0
5116 06:01:54.185577 9, 0xFFFF, sum = 0
5117 06:01:54.188220 10, 0x0, sum = 1
5118 06:01:54.188682 11, 0x0, sum = 2
5119 06:01:54.191638 12, 0x0, sum = 3
5120 06:01:54.192105 13, 0x0, sum = 4
5121 06:01:54.192479 best_step = 11
5122 06:01:54.192877
5123 06:01:54.195423 ==
5124 06:01:54.198305 Dram Type= 6, Freq= 0, CH_0, rank 0
5125 06:01:54.201573 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5126 06:01:54.202141 ==
5127 06:01:54.202515 RX Vref Scan: 1
5128 06:01:54.202857
5129 06:01:54.204917 RX Vref 0 -> 0, step: 1
5130 06:01:54.205381
5131 06:01:54.207982 RX Delay -69 -> 252, step: 4
5132 06:01:54.208542
5133 06:01:54.211433 Set Vref, RX VrefLevel [Byte0]: 48
5134 06:01:54.214533 [Byte1]: 51
5135 06:01:54.217965
5136 06:01:54.218532 Final RX Vref Byte 0 = 48 to rank0
5137 06:01:54.221039 Final RX Vref Byte 1 = 51 to rank0
5138 06:01:54.224574 Final RX Vref Byte 0 = 48 to rank1
5139 06:01:54.227791 Final RX Vref Byte 1 = 51 to rank1==
5140 06:01:54.231176 Dram Type= 6, Freq= 0, CH_0, rank 0
5141 06:01:54.237911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5142 06:01:54.238458 ==
5143 06:01:54.238828 DQS Delay:
5144 06:01:54.239174 DQS0 = 0, DQS1 = 0
5145 06:01:54.241213 DQM Delay:
5146 06:01:54.241678 DQM0 = 97, DQM1 = 87
5147 06:01:54.244754 DQ Delay:
5148 06:01:54.247346 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =96
5149 06:01:54.250794 DQ4 =102, DQ5 =88, DQ6 =106, DQ7 =104
5150 06:01:54.254172 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =80
5151 06:01:54.257668 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =96
5152 06:01:54.258230
5153 06:01:54.258601
5154 06:01:54.264056 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 413 ps
5155 06:01:54.267457 CH0 RK0: MR19=505, MR18=1A1A
5156 06:01:54.273815 CH0_RK0: MR19=0x505, MR18=0x1A1A, DQSOSC=413, MR23=63, INC=63, DEC=42
5157 06:01:54.274285
5158 06:01:54.277115 ----->DramcWriteLeveling(PI) begin...
5159 06:01:54.277588 ==
5160 06:01:54.280515 Dram Type= 6, Freq= 0, CH_0, rank 1
5161 06:01:54.284034 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5162 06:01:54.284597 ==
5163 06:01:54.287094 Write leveling (Byte 0): 30 => 30
5164 06:01:54.290519 Write leveling (Byte 1): 24 => 24
5165 06:01:54.293562 DramcWriteLeveling(PI) end<-----
5166 06:01:54.294028
5167 06:01:54.294393 ==
5168 06:01:54.297374 Dram Type= 6, Freq= 0, CH_0, rank 1
5169 06:01:54.300435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5170 06:01:54.303593 ==
5171 06:01:54.304060 [Gating] SW mode calibration
5172 06:01:54.313514 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5173 06:01:54.317031 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5174 06:01:54.320294 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 06:01:54.327116 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 06:01:54.330028 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 06:01:54.333216 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 06:01:54.340202 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 06:01:54.343719 0 10 20 | B1->B0 | 3232 2d2d | 1 1 | (1 1) (1 1)
5180 06:01:54.346691 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5181 06:01:54.353416 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 06:01:54.356658 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 06:01:54.360167 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 06:01:54.366635 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 06:01:54.369676 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 06:01:54.372822 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 06:01:54.379680 0 11 20 | B1->B0 | 2929 3333 | 0 0 | (0 0) (0 0)
5188 06:01:54.382869 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5189 06:01:54.386169 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 06:01:54.393103 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 06:01:54.396027 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 06:01:54.399543 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 06:01:54.406138 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 06:01:54.409544 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 06:01:54.412546 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5196 06:01:54.419395 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5197 06:01:54.422768 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 06:01:54.425978 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 06:01:54.432463 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 06:01:54.435527 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 06:01:54.439196 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 06:01:54.445468 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 06:01:54.449027 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 06:01:54.452121 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 06:01:54.458732 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 06:01:54.462343 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 06:01:54.465709 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 06:01:54.472278 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 06:01:54.475454 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 06:01:54.478895 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 06:01:54.485293 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5212 06:01:54.485846 Total UI for P1: 0, mck2ui 16
5213 06:01:54.492112 best dqsien dly found for B0: ( 0, 14, 18)
5214 06:01:54.495253 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 06:01:54.498510 Total UI for P1: 0, mck2ui 16
5216 06:01:54.501742 best dqsien dly found for B1: ( 0, 14, 20)
5217 06:01:54.505264 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5218 06:01:54.508783 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5219 06:01:54.509342
5220 06:01:54.512196 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5221 06:01:54.515500 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5222 06:01:54.518265 [Gating] SW calibration Done
5223 06:01:54.518732 ==
5224 06:01:54.521941 Dram Type= 6, Freq= 0, CH_0, rank 1
5225 06:01:54.528110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5226 06:01:54.528695 ==
5227 06:01:54.529134 RX Vref Scan: 0
5228 06:01:54.529483
5229 06:01:54.531330 RX Vref 0 -> 0, step: 1
5230 06:01:54.531737
5231 06:01:54.534867 RX Delay -80 -> 252, step: 8
5232 06:01:54.538347 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5233 06:01:54.541640 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5234 06:01:54.544654 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5235 06:01:54.548076 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5236 06:01:54.551400 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5237 06:01:54.558101 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5238 06:01:54.561447 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5239 06:01:54.564630 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5240 06:01:54.567589 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5241 06:01:54.571067 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5242 06:01:54.577925 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5243 06:01:54.580949 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5244 06:01:54.584340 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5245 06:01:54.587963 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5246 06:01:54.590894 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5247 06:01:54.597418 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5248 06:01:54.597963 ==
5249 06:01:54.600947 Dram Type= 6, Freq= 0, CH_0, rank 1
5250 06:01:54.604138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5251 06:01:54.604683 ==
5252 06:01:54.605157 DQS Delay:
5253 06:01:54.607639 DQS0 = 0, DQS1 = 0
5254 06:01:54.608196 DQM Delay:
5255 06:01:54.610921 DQM0 = 95, DQM1 = 88
5256 06:01:54.611479 DQ Delay:
5257 06:01:54.614265 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =87
5258 06:01:54.617253 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5259 06:01:54.620787 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5260 06:01:54.623841 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5261 06:01:54.624308
5262 06:01:54.624674
5263 06:01:54.625054 ==
5264 06:01:54.627429 Dram Type= 6, Freq= 0, CH_0, rank 1
5265 06:01:54.630739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5266 06:01:54.633987 ==
5267 06:01:54.634452
5268 06:01:54.634817
5269 06:01:54.635158 TX Vref Scan disable
5270 06:01:54.637021 == TX Byte 0 ==
5271 06:01:54.640664 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5272 06:01:54.644071 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5273 06:01:54.647146 == TX Byte 1 ==
5274 06:01:54.650406 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5275 06:01:54.653844 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5276 06:01:54.656892 ==
5277 06:01:54.660226 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 06:01:54.663660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5279 06:01:54.664228 ==
5280 06:01:54.664599
5281 06:01:54.665154
5282 06:01:54.666828 TX Vref Scan disable
5283 06:01:54.667295 == TX Byte 0 ==
5284 06:01:54.673362 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5285 06:01:54.676885 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5286 06:01:54.677446 == TX Byte 1 ==
5287 06:01:54.683555 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5288 06:01:54.686733 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5289 06:01:54.687348
5290 06:01:54.687738 [DATLAT]
5291 06:01:54.689979 Freq=933, CH0 RK1
5292 06:01:54.690449
5293 06:01:54.690811 DATLAT Default: 0xb
5294 06:01:54.693376 0, 0xFFFF, sum = 0
5295 06:01:54.693852 1, 0xFFFF, sum = 0
5296 06:01:54.696633 2, 0xFFFF, sum = 0
5297 06:01:54.697151 3, 0xFFFF, sum = 0
5298 06:01:54.700159 4, 0xFFFF, sum = 0
5299 06:01:54.703189 5, 0xFFFF, sum = 0
5300 06:01:54.703663 6, 0xFFFF, sum = 0
5301 06:01:54.706728 7, 0xFFFF, sum = 0
5302 06:01:54.707216 8, 0xFFFF, sum = 0
5303 06:01:54.709764 9, 0xFFFF, sum = 0
5304 06:01:54.710310 10, 0x0, sum = 1
5305 06:01:54.713596 11, 0x0, sum = 2
5306 06:01:54.714072 12, 0x0, sum = 3
5307 06:01:54.714449 13, 0x0, sum = 4
5308 06:01:54.716413 best_step = 11
5309 06:01:54.716924
5310 06:01:54.717299 ==
5311 06:01:54.719897 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 06:01:54.723254 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5313 06:01:54.723818 ==
5314 06:01:54.726670 RX Vref Scan: 0
5315 06:01:54.727229
5316 06:01:54.727606 RX Vref 0 -> 0, step: 1
5317 06:01:54.729446
5318 06:01:54.729910 RX Delay -69 -> 252, step: 4
5319 06:01:54.737661 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5320 06:01:54.740636 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5321 06:01:54.743907 iDelay=203, Bit 2, Center 98 (7 ~ 190) 184
5322 06:01:54.747077 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5323 06:01:54.751233 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5324 06:01:54.754061 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5325 06:01:54.760383 iDelay=203, Bit 6, Center 104 (15 ~ 194) 180
5326 06:01:54.763694 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5327 06:01:54.766759 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5328 06:01:54.770403 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5329 06:01:54.777038 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5330 06:01:54.780553 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5331 06:01:54.783725 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5332 06:01:54.786940 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5333 06:01:54.790019 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5334 06:01:54.793543 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5335 06:01:54.796493 ==
5336 06:01:54.797051 Dram Type= 6, Freq= 0, CH_0, rank 1
5337 06:01:54.803253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5338 06:01:54.803872 ==
5339 06:01:54.804372 DQS Delay:
5340 06:01:54.806711 DQS0 = 0, DQS1 = 0
5341 06:01:54.807178 DQM Delay:
5342 06:01:54.809981 DQM0 = 97, DQM1 = 86
5343 06:01:54.810445 DQ Delay:
5344 06:01:54.813547 DQ0 =92, DQ1 =98, DQ2 =98, DQ3 =92
5345 06:01:54.816882 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =108
5346 06:01:54.819931 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5347 06:01:54.823442 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =96
5348 06:01:54.824122
5349 06:01:54.824502
5350 06:01:54.829859 [DQSOSCAuto] RK1, (LSB)MR18= 0x2828, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5351 06:01:54.833064 CH0 RK1: MR19=505, MR18=2828
5352 06:01:54.840153 CH0_RK1: MR19=0x505, MR18=0x2828, DQSOSC=409, MR23=63, INC=64, DEC=43
5353 06:01:54.843327 [RxdqsGatingPostProcess] freq 933
5354 06:01:54.849723 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5355 06:01:54.850193 Pre-setting of DQS Precalculation
5356 06:01:54.856351 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5357 06:01:54.857184 ==
5358 06:01:54.859650 Dram Type= 6, Freq= 0, CH_1, rank 0
5359 06:01:54.862831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5360 06:01:54.863350 ==
5361 06:01:54.869435 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5362 06:01:54.875925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5363 06:01:54.879401 [CA 0] Center 37 (7~68) winsize 62
5364 06:01:54.882787 [CA 1] Center 37 (6~68) winsize 63
5365 06:01:54.885949 [CA 2] Center 34 (4~65) winsize 62
5366 06:01:54.889138 [CA 3] Center 34 (4~65) winsize 62
5367 06:01:54.892746 [CA 4] Center 32 (2~63) winsize 62
5368 06:01:54.896188 [CA 5] Center 33 (3~64) winsize 62
5369 06:01:54.896860
5370 06:01:54.899424 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5371 06:01:54.899981
5372 06:01:54.902606 [CATrainingPosCal] consider 1 rank data
5373 06:01:54.905647 u2DelayCellTimex100 = 270/100 ps
5374 06:01:54.909167 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5375 06:01:54.912511 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5376 06:01:54.915649 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5377 06:01:54.919089 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5378 06:01:54.925583 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5379 06:01:54.928797 CA5 delay=33 (3~64),Diff = 1 PI (6 cell)
5380 06:01:54.929264
5381 06:01:54.932497 CA PerBit enable=1, Macro0, CA PI delay=32
5382 06:01:54.933103
5383 06:01:54.935438 [CBTSetCACLKResult] CA Dly = 32
5384 06:01:54.935906 CS Dly: 5 (0~36)
5385 06:01:54.936318 ==
5386 06:01:54.938917 Dram Type= 6, Freq= 0, CH_1, rank 1
5387 06:01:54.945524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5388 06:01:54.946086 ==
5389 06:01:54.948664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5390 06:01:54.955130 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5391 06:01:54.958572 [CA 0] Center 37 (6~68) winsize 63
5392 06:01:54.961682 [CA 1] Center 37 (6~68) winsize 63
5393 06:01:54.965257 [CA 2] Center 34 (4~65) winsize 62
5394 06:01:54.968269 [CA 3] Center 34 (4~64) winsize 61
5395 06:01:54.971816 [CA 4] Center 33 (3~63) winsize 61
5396 06:01:54.975133 [CA 5] Center 33 (3~63) winsize 61
5397 06:01:54.975599
5398 06:01:54.978522 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5399 06:01:54.979081
5400 06:01:54.981568 [CATrainingPosCal] consider 2 rank data
5401 06:01:54.985043 u2DelayCellTimex100 = 270/100 ps
5402 06:01:54.988475 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5403 06:01:54.991641 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5404 06:01:54.998573 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5405 06:01:55.001455 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5406 06:01:55.005165 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5407 06:01:55.008423 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5408 06:01:55.009035
5409 06:01:55.011776 CA PerBit enable=1, Macro0, CA PI delay=33
5410 06:01:55.012336
5411 06:01:55.015006 [CBTSetCACLKResult] CA Dly = 33
5412 06:01:55.015465 CS Dly: 5 (0~37)
5413 06:01:55.015825
5414 06:01:55.021141 ----->DramcWriteLeveling(PI) begin...
5415 06:01:55.021693 ==
5416 06:01:55.025027 Dram Type= 6, Freq= 0, CH_1, rank 0
5417 06:01:55.027947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5418 06:01:55.028510 ==
5419 06:01:55.031149 Write leveling (Byte 0): 24 => 24
5420 06:01:55.034470 Write leveling (Byte 1): 24 => 24
5421 06:01:55.038226 DramcWriteLeveling(PI) end<-----
5422 06:01:55.038837
5423 06:01:55.039210 ==
5424 06:01:55.041427 Dram Type= 6, Freq= 0, CH_1, rank 0
5425 06:01:55.044422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5426 06:01:55.044926 ==
5427 06:01:55.047786 [Gating] SW mode calibration
5428 06:01:55.054550 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5429 06:01:55.061106 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5430 06:01:55.064565 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5431 06:01:55.067736 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5432 06:01:55.074478 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5433 06:01:55.077709 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5434 06:01:55.080903 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5435 06:01:55.087696 0 10 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
5436 06:01:55.090633 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5437 06:01:55.094377 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5438 06:01:55.100643 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5439 06:01:55.103857 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5440 06:01:55.107529 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5441 06:01:55.113831 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5442 06:01:55.117234 0 11 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5443 06:01:55.120789 0 11 20 | B1->B0 | 2a2a 4444 | 0 0 | (0 0) (0 0)
5444 06:01:55.127429 0 11 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5445 06:01:55.130209 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5446 06:01:55.133831 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5447 06:01:55.140462 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5448 06:01:55.143707 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5449 06:01:55.146735 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5450 06:01:55.153446 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5451 06:01:55.157111 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5452 06:01:55.160117 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 06:01:55.167116 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 06:01:55.170221 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 06:01:55.173388 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 06:01:55.180117 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 06:01:55.182975 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 06:01:55.186402 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5459 06:01:55.193110 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5460 06:01:55.196500 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5461 06:01:55.199705 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5462 06:01:55.206153 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5463 06:01:55.209660 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5464 06:01:55.213234 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5465 06:01:55.219665 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5466 06:01:55.222695 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5467 06:01:55.226281 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5468 06:01:55.229419 Total UI for P1: 0, mck2ui 16
5469 06:01:55.232897 best dqsien dly found for B0: ( 0, 14, 16)
5470 06:01:55.236310 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5471 06:01:55.239733 Total UI for P1: 0, mck2ui 16
5472 06:01:55.242823 best dqsien dly found for B1: ( 0, 14, 18)
5473 06:01:55.249352 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5474 06:01:55.252605 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5475 06:01:55.253120
5476 06:01:55.255733 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5477 06:01:55.259059 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5478 06:01:55.262428 [Gating] SW calibration Done
5479 06:01:55.262893 ==
5480 06:01:55.266017 Dram Type= 6, Freq= 0, CH_1, rank 0
5481 06:01:55.269102 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5482 06:01:55.269668 ==
5483 06:01:55.272519 RX Vref Scan: 0
5484 06:01:55.273125
5485 06:01:55.273506 RX Vref 0 -> 0, step: 1
5486 06:01:55.274039
5487 06:01:55.275723 RX Delay -80 -> 252, step: 8
5488 06:01:55.278923 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5489 06:01:55.285656 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5490 06:01:55.288941 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5491 06:01:55.292261 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5492 06:01:55.295635 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5493 06:01:55.299016 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5494 06:01:55.302710 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5495 06:01:55.308904 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5496 06:01:55.312447 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5497 06:01:55.316415 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5498 06:01:55.318941 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5499 06:01:55.322158 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5500 06:01:55.328781 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5501 06:01:55.332162 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5502 06:01:55.335439 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5503 06:01:55.338857 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5504 06:01:55.339422 ==
5505 06:01:55.341957 Dram Type= 6, Freq= 0, CH_1, rank 0
5506 06:01:55.345309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5507 06:01:55.348849 ==
5508 06:01:55.349333 DQS Delay:
5509 06:01:55.349705 DQS0 = 0, DQS1 = 0
5510 06:01:55.351925 DQM Delay:
5511 06:01:55.352404 DQM0 = 95, DQM1 = 89
5512 06:01:55.355427 DQ Delay:
5513 06:01:55.358415 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5514 06:01:55.361874 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =95
5515 06:01:55.365202 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5516 06:01:55.368509 DQ12 =103, DQ13 =103, DQ14 =91, DQ15 =95
5517 06:01:55.369170
5518 06:01:55.369552
5519 06:01:55.369893 ==
5520 06:01:55.371552 Dram Type= 6, Freq= 0, CH_1, rank 0
5521 06:01:55.375137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5522 06:01:55.375606 ==
5523 06:01:55.375972
5524 06:01:55.376312
5525 06:01:55.378695 TX Vref Scan disable
5526 06:01:55.379417 == TX Byte 0 ==
5527 06:01:55.384905 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5528 06:01:55.388454 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5529 06:01:55.388972 == TX Byte 1 ==
5530 06:01:55.395252 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5531 06:01:55.398536 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5532 06:01:55.399163 ==
5533 06:01:55.401929 Dram Type= 6, Freq= 0, CH_1, rank 0
5534 06:01:55.404695 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5535 06:01:55.405231 ==
5536 06:01:55.405653
5537 06:01:55.408249
5538 06:01:55.408848 TX Vref Scan disable
5539 06:01:55.411430 == TX Byte 0 ==
5540 06:01:55.414594 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5541 06:01:55.418029 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5542 06:01:55.421313 == TX Byte 1 ==
5543 06:01:55.424748 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5544 06:01:55.428082 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5545 06:01:55.431357
5546 06:01:55.431981 [DATLAT]
5547 06:01:55.432357 Freq=933, CH1 RK0
5548 06:01:55.432702
5549 06:01:55.434631 DATLAT Default: 0xd
5550 06:01:55.435087 0, 0xFFFF, sum = 0
5551 06:01:55.438198 1, 0xFFFF, sum = 0
5552 06:01:55.438769 2, 0xFFFF, sum = 0
5553 06:01:55.441399 3, 0xFFFF, sum = 0
5554 06:01:55.444520 4, 0xFFFF, sum = 0
5555 06:01:55.445174 5, 0xFFFF, sum = 0
5556 06:01:55.448083 6, 0xFFFF, sum = 0
5557 06:01:55.448697 7, 0xFFFF, sum = 0
5558 06:01:55.450899 8, 0xFFFF, sum = 0
5559 06:01:55.451382 9, 0xFFFF, sum = 0
5560 06:01:55.454176 10, 0x0, sum = 1
5561 06:01:55.454640 11, 0x0, sum = 2
5562 06:01:55.457584 12, 0x0, sum = 3
5563 06:01:55.458049 13, 0x0, sum = 4
5564 06:01:55.458417 best_step = 11
5565 06:01:55.458769
5566 06:01:55.461064 ==
5567 06:01:55.464482 Dram Type= 6, Freq= 0, CH_1, rank 0
5568 06:01:55.467396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5569 06:01:55.467866 ==
5570 06:01:55.468233 RX Vref Scan: 1
5571 06:01:55.468577
5572 06:01:55.470643 RX Vref 0 -> 0, step: 1
5573 06:01:55.471111
5574 06:01:55.474020 RX Delay -69 -> 252, step: 4
5575 06:01:55.474541
5576 06:01:55.477529 Set Vref, RX VrefLevel [Byte0]: 56
5577 06:01:55.481228 [Byte1]: 47
5578 06:01:55.481794
5579 06:01:55.484410 Final RX Vref Byte 0 = 56 to rank0
5580 06:01:55.487794 Final RX Vref Byte 1 = 47 to rank0
5581 06:01:55.490794 Final RX Vref Byte 0 = 56 to rank1
5582 06:01:55.494521 Final RX Vref Byte 1 = 47 to rank1==
5583 06:01:55.497604 Dram Type= 6, Freq= 0, CH_1, rank 0
5584 06:01:55.500791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5585 06:01:55.504109 ==
5586 06:01:55.504775 DQS Delay:
5587 06:01:55.505172 DQS0 = 0, DQS1 = 0
5588 06:01:55.507574 DQM Delay:
5589 06:01:55.508133 DQM0 = 94, DQM1 = 88
5590 06:01:55.510815 DQ Delay:
5591 06:01:55.513992 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5592 06:01:55.517416 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5593 06:01:55.517986 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80
5594 06:01:55.523757 DQ12 =94, DQ13 =100, DQ14 =96, DQ15 =98
5595 06:01:55.524216
5596 06:01:55.524575
5597 06:01:55.530750 [DQSOSCAuto] RK0, (LSB)MR18= 0x3131, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5598 06:01:55.533763 CH1 RK0: MR19=505, MR18=3131
5599 06:01:55.540547 CH1_RK0: MR19=0x505, MR18=0x3131, DQSOSC=406, MR23=63, INC=65, DEC=43
5600 06:01:55.541163
5601 06:01:55.543850 ----->DramcWriteLeveling(PI) begin...
5602 06:01:55.544317 ==
5603 06:01:55.547158 Dram Type= 6, Freq= 0, CH_1, rank 1
5604 06:01:55.550262 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5605 06:01:55.550729 ==
5606 06:01:55.553590 Write leveling (Byte 0): 23 => 23
5607 06:01:55.557120 Write leveling (Byte 1): 24 => 24
5608 06:01:55.560091 DramcWriteLeveling(PI) end<-----
5609 06:01:55.560547
5610 06:01:55.560965 ==
5611 06:01:55.563714 Dram Type= 6, Freq= 0, CH_1, rank 1
5612 06:01:55.566871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5613 06:01:55.567334 ==
5614 06:01:55.570193 [Gating] SW mode calibration
5615 06:01:55.577006 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5616 06:01:55.583539 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5617 06:01:55.586607 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 06:01:55.593329 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 06:01:55.597048 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 06:01:55.600009 0 10 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5621 06:01:55.606549 0 10 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
5622 06:01:55.610114 0 10 20 | B1->B0 | 3131 2323 | 0 0 | (1 1) (0 0)
5623 06:01:55.613632 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 06:01:55.620153 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 06:01:55.623358 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 06:01:55.626709 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 06:01:55.633126 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 06:01:55.636202 0 11 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5629 06:01:55.639797 0 11 16 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
5630 06:01:55.646346 0 11 20 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
5631 06:01:55.649774 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 06:01:55.652990 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 06:01:55.656538 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 06:01:55.663140 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 06:01:55.666268 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 06:01:55.669520 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 06:01:55.676000 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 06:01:55.679542 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 06:01:55.682879 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 06:01:55.689388 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 06:01:55.692498 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 06:01:55.696106 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 06:01:55.702603 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 06:01:55.705802 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 06:01:55.708972 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 06:01:55.715670 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 06:01:55.719028 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 06:01:55.722210 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 06:01:55.729337 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 06:01:55.732322 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 06:01:55.735678 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 06:01:55.742303 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 06:01:55.745581 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5654 06:01:55.748866 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 06:01:55.752154 Total UI for P1: 0, mck2ui 16
5656 06:01:55.755531 best dqsien dly found for B0: ( 0, 14, 16)
5657 06:01:55.758781 Total UI for P1: 0, mck2ui 16
5658 06:01:55.762089 best dqsien dly found for B1: ( 0, 14, 18)
5659 06:01:55.765266 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5660 06:01:55.768651 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5661 06:01:55.771931
5662 06:01:55.775805 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5663 06:01:55.778362 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5664 06:01:55.782108 [Gating] SW calibration Done
5665 06:01:55.782664 ==
5666 06:01:55.785405 Dram Type= 6, Freq= 0, CH_1, rank 1
5667 06:01:55.788398 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5668 06:01:55.788899 ==
5669 06:01:55.789274 RX Vref Scan: 0
5670 06:01:55.792181
5671 06:01:55.792795 RX Vref 0 -> 0, step: 1
5672 06:01:55.793306
5673 06:01:55.795291 RX Delay -80 -> 252, step: 8
5674 06:01:55.799008 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5675 06:01:55.801804 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5676 06:01:55.808583 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5677 06:01:55.811942 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5678 06:01:55.815199 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5679 06:01:55.818408 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5680 06:01:55.821616 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5681 06:01:55.825444 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5682 06:01:55.831905 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5683 06:01:55.835128 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5684 06:01:55.838417 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5685 06:01:55.841835 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5686 06:01:55.845019 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5687 06:01:55.851546 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5688 06:01:55.854974 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5689 06:01:55.858217 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5690 06:01:55.858793 ==
5691 06:01:55.861305 Dram Type= 6, Freq= 0, CH_1, rank 1
5692 06:01:55.864876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5693 06:01:55.865449 ==
5694 06:01:55.868117 DQS Delay:
5695 06:01:55.868683 DQS0 = 0, DQS1 = 0
5696 06:01:55.869102 DQM Delay:
5697 06:01:55.871211 DQM0 = 96, DQM1 = 86
5698 06:01:55.871836 DQ Delay:
5699 06:01:55.874396 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =95
5700 06:01:55.877674 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5701 06:01:55.881067 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =75
5702 06:01:55.884449 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5703 06:01:55.884993
5704 06:01:55.885361
5705 06:01:55.887662 ==
5706 06:01:55.888129 Dram Type= 6, Freq= 0, CH_1, rank 1
5707 06:01:55.894050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5708 06:01:55.894522 ==
5709 06:01:55.894895
5710 06:01:55.895238
5711 06:01:55.897282 TX Vref Scan disable
5712 06:01:55.897750 == TX Byte 0 ==
5713 06:01:55.900650 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5714 06:01:55.907290 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5715 06:01:55.907867 == TX Byte 1 ==
5716 06:01:55.910845 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5717 06:01:55.917710 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5718 06:01:55.918288 ==
5719 06:01:55.920678 Dram Type= 6, Freq= 0, CH_1, rank 1
5720 06:01:55.924080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5721 06:01:55.924541 ==
5722 06:01:55.924956
5723 06:01:55.925297
5724 06:01:55.927570 TX Vref Scan disable
5725 06:01:55.930680 == TX Byte 0 ==
5726 06:01:55.933849 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5727 06:01:55.937155 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5728 06:01:55.940356 == TX Byte 1 ==
5729 06:01:55.943823 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5730 06:01:55.946952 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5731 06:01:55.947419
5732 06:01:55.950035 [DATLAT]
5733 06:01:55.950809 Freq=933, CH1 RK1
5734 06:01:55.951310
5735 06:01:55.953516 DATLAT Default: 0xb
5736 06:01:55.953983 0, 0xFFFF, sum = 0
5737 06:01:55.957229 1, 0xFFFF, sum = 0
5738 06:01:55.957703 2, 0xFFFF, sum = 0
5739 06:01:55.960277 3, 0xFFFF, sum = 0
5740 06:01:55.960911 4, 0xFFFF, sum = 0
5741 06:01:55.963625 5, 0xFFFF, sum = 0
5742 06:01:55.964202 6, 0xFFFF, sum = 0
5743 06:01:55.967082 7, 0xFFFF, sum = 0
5744 06:01:55.967659 8, 0xFFFF, sum = 0
5745 06:01:55.970427 9, 0xFFFF, sum = 0
5746 06:01:55.970901 10, 0x0, sum = 1
5747 06:01:55.973158 11, 0x0, sum = 2
5748 06:01:55.973631 12, 0x0, sum = 3
5749 06:01:55.976460 13, 0x0, sum = 4
5750 06:01:55.976993 best_step = 11
5751 06:01:55.977381
5752 06:01:55.977724 ==
5753 06:01:55.979872 Dram Type= 6, Freq= 0, CH_1, rank 1
5754 06:01:55.986847 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5755 06:01:55.987421 ==
5756 06:01:55.987799 RX Vref Scan: 0
5757 06:01:55.988149
5758 06:01:55.990140 RX Vref 0 -> 0, step: 1
5759 06:01:55.990724
5760 06:01:55.993279 RX Delay -69 -> 252, step: 4
5761 06:01:55.997076 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5762 06:01:56.000220 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5763 06:01:56.006686 iDelay=203, Bit 2, Center 86 (-9 ~ 182) 192
5764 06:01:56.009797 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5765 06:01:56.013366 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5766 06:01:56.016483 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5767 06:01:56.019690 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5768 06:01:56.026518 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5769 06:01:56.029566 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5770 06:01:56.033022 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5771 06:01:56.036491 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5772 06:01:56.039846 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5773 06:01:56.045911 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5774 06:01:56.049725 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5775 06:01:56.052944 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5776 06:01:56.056304 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5777 06:01:56.056920 ==
5778 06:01:56.059594 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 06:01:56.062423 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5780 06:01:56.062896 ==
5781 06:01:56.066163 DQS Delay:
5782 06:01:56.066732 DQS0 = 0, DQS1 = 0
5783 06:01:56.069437 DQM Delay:
5784 06:01:56.070005 DQM0 = 96, DQM1 = 87
5785 06:01:56.070376 DQ Delay:
5786 06:01:56.072397 DQ0 =98, DQ1 =92, DQ2 =86, DQ3 =92
5787 06:01:56.075811 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5788 06:01:56.079482 DQ8 =74, DQ9 =76, DQ10 =86, DQ11 =80
5789 06:01:56.082562 DQ12 =98, DQ13 =96, DQ14 =94, DQ15 =96
5790 06:01:56.086223
5791 06:01:56.086794
5792 06:01:56.092576 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5793 06:01:56.095721 CH1 RK1: MR19=505, MR18=2020
5794 06:01:56.102238 CH1_RK1: MR19=0x505, MR18=0x2020, DQSOSC=411, MR23=63, INC=64, DEC=42
5795 06:01:56.105519 [RxdqsGatingPostProcess] freq 933
5796 06:01:56.109022 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5797 06:01:56.112192 Pre-setting of DQS Precalculation
5798 06:01:56.118799 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5799 06:01:56.125447 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5800 06:01:56.132064 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5801 06:01:56.132641
5802 06:01:56.133062
5803 06:01:56.135179 [Calibration Summary] 1866 Mbps
5804 06:01:56.135710 CH 0, Rank 0
5805 06:01:56.138634 SW Impedance : PASS
5806 06:01:56.141993 DUTY Scan : NO K
5807 06:01:56.142563 ZQ Calibration : PASS
5808 06:01:56.145531 Jitter Meter : NO K
5809 06:01:56.148576 CBT Training : PASS
5810 06:01:56.149197 Write leveling : PASS
5811 06:01:56.152365 RX DQS gating : PASS
5812 06:01:56.155177 RX DQ/DQS(RDDQC) : PASS
5813 06:01:56.155671 TX DQ/DQS : PASS
5814 06:01:56.158505 RX DATLAT : PASS
5815 06:01:56.161465 RX DQ/DQS(Engine): PASS
5816 06:01:56.161932 TX OE : NO K
5817 06:01:56.165084 All Pass.
5818 06:01:56.165653
5819 06:01:56.166022 CH 0, Rank 1
5820 06:01:56.168560 SW Impedance : PASS
5821 06:01:56.169178 DUTY Scan : NO K
5822 06:01:56.172306 ZQ Calibration : PASS
5823 06:01:56.172938 Jitter Meter : NO K
5824 06:01:56.175265 CBT Training : PASS
5825 06:01:56.178416 Write leveling : PASS
5826 06:01:56.178984 RX DQS gating : PASS
5827 06:01:56.181691 RX DQ/DQS(RDDQC) : PASS
5828 06:01:56.184986 TX DQ/DQS : PASS
5829 06:01:56.185574 RX DATLAT : PASS
5830 06:01:56.188139 RX DQ/DQS(Engine): PASS
5831 06:01:56.191631 TX OE : NO K
5832 06:01:56.192206 All Pass.
5833 06:01:56.192578
5834 06:01:56.192983 CH 1, Rank 0
5835 06:01:56.194793 SW Impedance : PASS
5836 06:01:56.198182 DUTY Scan : NO K
5837 06:01:56.198756 ZQ Calibration : PASS
5838 06:01:56.201283 Jitter Meter : NO K
5839 06:01:56.204760 CBT Training : PASS
5840 06:01:56.205252 Write leveling : PASS
5841 06:01:56.207835 RX DQS gating : PASS
5842 06:01:56.211361 RX DQ/DQS(RDDQC) : PASS
5843 06:01:56.211933 TX DQ/DQS : PASS
5844 06:01:56.214593 RX DATLAT : PASS
5845 06:01:56.217845 RX DQ/DQS(Engine): PASS
5846 06:01:56.218413 TX OE : NO K
5847 06:01:56.221007 All Pass.
5848 06:01:56.221471
5849 06:01:56.221837 CH 1, Rank 1
5850 06:01:56.224241 SW Impedance : PASS
5851 06:01:56.224742 DUTY Scan : NO K
5852 06:01:56.227753 ZQ Calibration : PASS
5853 06:01:56.231125 Jitter Meter : NO K
5854 06:01:56.231702 CBT Training : PASS
5855 06:01:56.234162 Write leveling : PASS
5856 06:01:56.237648 RX DQS gating : PASS
5857 06:01:56.238113 RX DQ/DQS(RDDQC) : PASS
5858 06:01:56.240872 TX DQ/DQS : PASS
5859 06:01:56.241340 RX DATLAT : PASS
5860 06:01:56.244503 RX DQ/DQS(Engine): PASS
5861 06:01:56.247878 TX OE : NO K
5862 06:01:56.248438 All Pass.
5863 06:01:56.248842
5864 06:01:56.250820 DramC Write-DBI off
5865 06:01:56.254337 PER_BANK_REFRESH: Hybrid Mode
5866 06:01:56.254932 TX_TRACKING: ON
5867 06:01:56.264121 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5868 06:01:56.267215 [FAST_K] Save calibration result to emmc
5869 06:01:56.270690 dramc_set_vcore_voltage set vcore to 650000
5870 06:01:56.273879 Read voltage for 400, 6
5871 06:01:56.274616 Vio18 = 0
5872 06:01:56.275012 Vcore = 650000
5873 06:01:56.277015 Vdram = 0
5874 06:01:56.277475 Vddq = 0
5875 06:01:56.277839 Vmddr = 0
5876 06:01:56.284075 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5877 06:01:56.287442 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5878 06:01:56.290460 MEM_TYPE=3, freq_sel=20
5879 06:01:56.293800 sv_algorithm_assistance_LP4_800
5880 06:01:56.297033 ============ PULL DRAM RESETB DOWN ============
5881 06:01:56.300570 ========== PULL DRAM RESETB DOWN end =========
5882 06:01:56.306965 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5883 06:01:56.310114 ===================================
5884 06:01:56.310578 LPDDR4 DRAM CONFIGURATION
5885 06:01:56.313485 ===================================
5886 06:01:56.317181 EX_ROW_EN[0] = 0x0
5887 06:01:56.320361 EX_ROW_EN[1] = 0x0
5888 06:01:56.320962 LP4Y_EN = 0x0
5889 06:01:56.323321 WORK_FSP = 0x0
5890 06:01:56.323842 WL = 0x2
5891 06:01:56.327006 RL = 0x2
5892 06:01:56.327571 BL = 0x2
5893 06:01:56.330207 RPST = 0x0
5894 06:01:56.330772 RD_PRE = 0x0
5895 06:01:56.333503 WR_PRE = 0x1
5896 06:01:56.334068 WR_PST = 0x0
5897 06:01:56.336642 DBI_WR = 0x0
5898 06:01:56.337246 DBI_RD = 0x0
5899 06:01:56.340325 OTF = 0x1
5900 06:01:56.343538 ===================================
5901 06:01:56.346611 ===================================
5902 06:01:56.347074 ANA top config
5903 06:01:56.349874 ===================================
5904 06:01:56.353624 DLL_ASYNC_EN = 0
5905 06:01:56.356664 ALL_SLAVE_EN = 1
5906 06:01:56.360018 NEW_RANK_MODE = 1
5907 06:01:56.360584 DLL_IDLE_MODE = 1
5908 06:01:56.363116 LP45_APHY_COMB_EN = 1
5909 06:01:56.366577 TX_ODT_DIS = 1
5910 06:01:56.369889 NEW_8X_MODE = 1
5911 06:01:56.373197 ===================================
5912 06:01:56.376191 ===================================
5913 06:01:56.379634 data_rate = 800
5914 06:01:56.380192 CKR = 1
5915 06:01:56.382944 DQ_P2S_RATIO = 4
5916 06:01:56.386298 ===================================
5917 06:01:56.389488 CA_P2S_RATIO = 4
5918 06:01:56.392905 DQ_CA_OPEN = 0
5919 06:01:56.396403 DQ_SEMI_OPEN = 1
5920 06:01:56.399637 CA_SEMI_OPEN = 1
5921 06:01:56.400198 CA_FULL_RATE = 0
5922 06:01:56.402954 DQ_CKDIV4_EN = 0
5923 06:01:56.406145 CA_CKDIV4_EN = 1
5924 06:01:56.409454 CA_PREDIV_EN = 0
5925 06:01:56.412878 PH8_DLY = 0
5926 06:01:56.416268 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5927 06:01:56.416898 DQ_AAMCK_DIV = 0
5928 06:01:56.419362 CA_AAMCK_DIV = 0
5929 06:01:56.422369 CA_ADMCK_DIV = 4
5930 06:01:56.425907 DQ_TRACK_CA_EN = 0
5931 06:01:56.429184 CA_PICK = 800
5932 06:01:56.432459 CA_MCKIO = 400
5933 06:01:56.435982 MCKIO_SEMI = 400
5934 06:01:56.439184 PLL_FREQ = 3016
5935 06:01:56.439741 DQ_UI_PI_RATIO = 32
5936 06:01:56.442240 CA_UI_PI_RATIO = 32
5937 06:01:56.445598 ===================================
5938 06:01:56.449130 ===================================
5939 06:01:56.452179 memory_type:LPDDR4
5940 06:01:56.455284 GP_NUM : 10
5941 06:01:56.455741 SRAM_EN : 1
5942 06:01:56.458997 MD32_EN : 0
5943 06:01:56.461939 ===================================
5944 06:01:56.465629 [ANA_INIT] >>>>>>>>>>>>>>
5945 06:01:56.466191 <<<<<< [CONFIGURE PHASE]: ANA_TX
5946 06:01:56.468857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5947 06:01:56.471944 ===================================
5948 06:01:56.475210 data_rate = 800,PCW = 0X7400
5949 06:01:56.478458 ===================================
5950 06:01:56.482399 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5951 06:01:56.488752 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5952 06:01:56.498472 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5953 06:01:56.505121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5954 06:01:56.508549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5955 06:01:56.511633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5956 06:01:56.515676 [ANA_INIT] flow start
5957 06:01:56.516240 [ANA_INIT] PLL >>>>>>>>
5958 06:01:56.518369 [ANA_INIT] PLL <<<<<<<<
5959 06:01:56.521906 [ANA_INIT] MIDPI >>>>>>>>
5960 06:01:56.522471 [ANA_INIT] MIDPI <<<<<<<<
5961 06:01:56.524960 [ANA_INIT] DLL >>>>>>>>
5962 06:01:56.528479 [ANA_INIT] flow end
5963 06:01:56.531568 ============ LP4 DIFF to SE enter ============
5964 06:01:56.534883 ============ LP4 DIFF to SE exit ============
5965 06:01:56.538444 [ANA_INIT] <<<<<<<<<<<<<
5966 06:01:56.541545 [Flow] Enable top DCM control >>>>>
5967 06:01:56.544692 [Flow] Enable top DCM control <<<<<
5968 06:01:56.548446 Enable DLL master slave shuffle
5969 06:01:56.551455 ==============================================================
5970 06:01:56.554587 Gating Mode config
5971 06:01:56.561360 ==============================================================
5972 06:01:56.561928 Config description:
5973 06:01:56.571438 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5974 06:01:56.577692 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5975 06:01:56.584545 SELPH_MODE 0: By rank 1: By Phase
5976 06:01:56.587796 ==============================================================
5977 06:01:56.591188 GAT_TRACK_EN = 0
5978 06:01:56.594122 RX_GATING_MODE = 2
5979 06:01:56.597683 RX_GATING_TRACK_MODE = 2
5980 06:01:56.601172 SELPH_MODE = 1
5981 06:01:56.604146 PICG_EARLY_EN = 1
5982 06:01:56.607627 VALID_LAT_VALUE = 1
5983 06:01:56.610835 ==============================================================
5984 06:01:56.614230 Enter into Gating configuration >>>>
5985 06:01:56.617887 Exit from Gating configuration <<<<
5986 06:01:56.620635 Enter into DVFS_PRE_config >>>>>
5987 06:01:56.634011 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5988 06:01:56.637391 Exit from DVFS_PRE_config <<<<<
5989 06:01:56.640666 Enter into PICG configuration >>>>
5990 06:01:56.641269 Exit from PICG configuration <<<<
5991 06:01:56.643911 [RX_INPUT] configuration >>>>>
5992 06:01:56.647508 [RX_INPUT] configuration <<<<<
5993 06:01:56.653902 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5994 06:01:56.656966 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5995 06:01:56.663969 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5996 06:01:56.670459 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5997 06:01:56.677042 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5998 06:01:56.683359 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5999 06:01:56.687093 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6000 06:01:56.690187 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6001 06:01:56.696618 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6002 06:01:56.699990 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6003 06:01:56.703328 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6004 06:01:56.706303 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6005 06:01:56.709654 ===================================
6006 06:01:56.713329 LPDDR4 DRAM CONFIGURATION
6007 06:01:56.716479 ===================================
6008 06:01:56.719760 EX_ROW_EN[0] = 0x0
6009 06:01:56.720189 EX_ROW_EN[1] = 0x0
6010 06:01:56.723069 LP4Y_EN = 0x0
6011 06:01:56.723534 WORK_FSP = 0x0
6012 06:01:56.726483 WL = 0x2
6013 06:01:56.726947 RL = 0x2
6014 06:01:56.730009 BL = 0x2
6015 06:01:56.730587 RPST = 0x0
6016 06:01:56.733047 RD_PRE = 0x0
6017 06:01:56.733677 WR_PRE = 0x1
6018 06:01:56.736584 WR_PST = 0x0
6019 06:01:56.739806 DBI_WR = 0x0
6020 06:01:56.740367 DBI_RD = 0x0
6021 06:01:56.743066 OTF = 0x1
6022 06:01:56.746296 ===================================
6023 06:01:56.749886 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6024 06:01:56.752836 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6025 06:01:56.756137 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6026 06:01:56.759768 ===================================
6027 06:01:56.762790 LPDDR4 DRAM CONFIGURATION
6028 06:01:56.766235 ===================================
6029 06:01:56.769687 EX_ROW_EN[0] = 0x10
6030 06:01:56.770248 EX_ROW_EN[1] = 0x0
6031 06:01:56.773362 LP4Y_EN = 0x0
6032 06:01:56.773921 WORK_FSP = 0x0
6033 06:01:56.775989 WL = 0x2
6034 06:01:56.776453 RL = 0x2
6035 06:01:56.779236 BL = 0x2
6036 06:01:56.779700 RPST = 0x0
6037 06:01:56.782790 RD_PRE = 0x0
6038 06:01:56.783394 WR_PRE = 0x1
6039 06:01:56.786049 WR_PST = 0x0
6040 06:01:56.786610 DBI_WR = 0x0
6041 06:01:56.789748 DBI_RD = 0x0
6042 06:01:56.792414 OTF = 0x1
6043 06:01:56.795835 ===================================
6044 06:01:56.799031 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6045 06:01:56.804579 nWR fixed to 30
6046 06:01:56.807622 [ModeRegInit_LP4] CH0 RK0
6047 06:01:56.808090 [ModeRegInit_LP4] CH0 RK1
6048 06:01:56.811119 [ModeRegInit_LP4] CH1 RK0
6049 06:01:56.814505 [ModeRegInit_LP4] CH1 RK1
6050 06:01:56.815232 match AC timing 18
6051 06:01:56.820640 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6052 06:01:56.823983 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6053 06:01:56.827700 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6054 06:01:56.833805 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6055 06:01:56.837416 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6056 06:01:56.837982 ==
6057 06:01:56.841101 Dram Type= 6, Freq= 0, CH_0, rank 0
6058 06:01:56.844245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6059 06:01:56.844872 ==
6060 06:01:56.850494 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6061 06:01:56.857255 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6062 06:01:56.860422 [CA 0] Center 36 (8~64) winsize 57
6063 06:01:56.863809 [CA 1] Center 36 (8~64) winsize 57
6064 06:01:56.867284 [CA 2] Center 36 (8~64) winsize 57
6065 06:01:56.870450 [CA 3] Center 36 (8~64) winsize 57
6066 06:01:56.873749 [CA 4] Center 36 (8~64) winsize 57
6067 06:01:56.874311 [CA 5] Center 36 (8~64) winsize 57
6068 06:01:56.877309
6069 06:01:56.880327 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6070 06:01:56.880858
6071 06:01:56.883533 [CATrainingPosCal] consider 1 rank data
6072 06:01:56.887122 u2DelayCellTimex100 = 270/100 ps
6073 06:01:56.890080 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6074 06:01:56.893735 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6075 06:01:56.896978 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6076 06:01:56.900024 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6077 06:01:56.903779 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6078 06:01:56.906920 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6079 06:01:56.907389
6080 06:01:56.910076 CA PerBit enable=1, Macro0, CA PI delay=36
6081 06:01:56.910541
6082 06:01:56.913550 [CBTSetCACLKResult] CA Dly = 36
6083 06:01:56.916926 CS Dly: 1 (0~32)
6084 06:01:56.917483 ==
6085 06:01:56.920162 Dram Type= 6, Freq= 0, CH_0, rank 1
6086 06:01:56.923482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6087 06:01:56.924077 ==
6088 06:01:56.930151 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6089 06:01:56.936618 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6090 06:01:56.939848 [CA 0] Center 36 (8~64) winsize 57
6091 06:01:56.943335 [CA 1] Center 36 (8~64) winsize 57
6092 06:01:56.943805 [CA 2] Center 36 (8~64) winsize 57
6093 06:01:56.946260 [CA 3] Center 36 (8~64) winsize 57
6094 06:01:56.949645 [CA 4] Center 36 (8~64) winsize 57
6095 06:01:56.953127 [CA 5] Center 36 (8~64) winsize 57
6096 06:01:56.953691
6097 06:01:56.956371 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6098 06:01:56.959794
6099 06:01:56.962657 [CATrainingPosCal] consider 2 rank data
6100 06:01:56.963127 u2DelayCellTimex100 = 270/100 ps
6101 06:01:56.969629 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6102 06:01:56.972845 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6103 06:01:56.976249 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6104 06:01:56.979245 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6105 06:01:56.982855 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6106 06:01:56.986220 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6107 06:01:56.986787
6108 06:01:56.989317 CA PerBit enable=1, Macro0, CA PI delay=36
6109 06:01:56.989783
6110 06:01:56.992309 [CBTSetCACLKResult] CA Dly = 36
6111 06:01:56.995938 CS Dly: 1 (0~32)
6112 06:01:56.996401
6113 06:01:56.999470 ----->DramcWriteLeveling(PI) begin...
6114 06:01:57.000040 ==
6115 06:01:57.002735 Dram Type= 6, Freq= 0, CH_0, rank 0
6116 06:01:57.005870 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6117 06:01:57.006406 ==
6118 06:01:57.009168 Write leveling (Byte 0): 32 => 0
6119 06:01:57.012428 Write leveling (Byte 1): 32 => 0
6120 06:01:57.016141 DramcWriteLeveling(PI) end<-----
6121 06:01:57.016771
6122 06:01:57.017156 ==
6123 06:01:57.019078 Dram Type= 6, Freq= 0, CH_0, rank 0
6124 06:01:57.022375 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6125 06:01:57.022846 ==
6126 06:01:57.025967 [Gating] SW mode calibration
6127 06:01:57.032176 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6128 06:01:57.038841 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6129 06:01:57.042440 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6130 06:01:57.045459 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6131 06:01:57.052203 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6132 06:01:57.056052 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6133 06:01:57.058828 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6134 06:01:57.065404 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6135 06:01:57.068946 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6136 06:01:57.072200 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6137 06:01:57.078524 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6138 06:01:57.079288 Total UI for P1: 0, mck2ui 16
6139 06:01:57.085214 best dqsien dly found for B0: ( 0, 10, 16)
6140 06:01:57.085766 Total UI for P1: 0, mck2ui 16
6141 06:01:57.092073 best dqsien dly found for B1: ( 0, 10, 24)
6142 06:01:57.095239 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6143 06:01:57.098684 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6144 06:01:57.099247
6145 06:01:57.102098 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6146 06:01:57.105357 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6147 06:01:57.108668 [Gating] SW calibration Done
6148 06:01:57.109213 ==
6149 06:01:57.111606 Dram Type= 6, Freq= 0, CH_0, rank 0
6150 06:01:57.115213 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6151 06:01:57.115796 ==
6152 06:01:57.118503 RX Vref Scan: 0
6153 06:01:57.118966
6154 06:01:57.119332 RX Vref 0 -> 0, step: 1
6155 06:01:57.121635
6156 06:01:57.122349 RX Delay -410 -> 252, step: 16
6157 06:01:57.128780 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6158 06:01:57.131766 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6159 06:01:57.134876 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6160 06:01:57.138105 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6161 06:01:57.144952 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6162 06:01:57.148313 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6163 06:01:57.151180 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6164 06:01:57.157692 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6165 06:01:57.161435 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6166 06:01:57.164677 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6167 06:01:57.167886 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6168 06:01:57.174207 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6169 06:01:57.177821 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6170 06:01:57.181030 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6171 06:01:57.184456 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6172 06:01:57.190948 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6173 06:01:57.191580 ==
6174 06:01:57.194145 Dram Type= 6, Freq= 0, CH_0, rank 0
6175 06:01:57.197388 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6176 06:01:57.197859 ==
6177 06:01:57.198229 DQS Delay:
6178 06:01:57.200610 DQS0 = 43, DQS1 = 59
6179 06:01:57.201116 DQM Delay:
6180 06:01:57.204127 DQM0 = 5, DQM1 = 16
6181 06:01:57.204595 DQ Delay:
6182 06:01:57.207505 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6183 06:01:57.210900 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6184 06:01:57.214119 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6185 06:01:57.217554 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6186 06:01:57.218022
6187 06:01:57.218387
6188 06:01:57.218726 ==
6189 06:01:57.220770 Dram Type= 6, Freq= 0, CH_0, rank 0
6190 06:01:57.224202 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6191 06:01:57.224817 ==
6192 06:01:57.225203
6193 06:01:57.225543
6194 06:01:57.227361 TX Vref Scan disable
6195 06:01:57.227862 == TX Byte 0 ==
6196 06:01:57.234099 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6197 06:01:57.237463 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6198 06:01:57.240579 == TX Byte 1 ==
6199 06:01:57.244031 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6200 06:01:57.247662 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6201 06:01:57.248242 ==
6202 06:01:57.250773 Dram Type= 6, Freq= 0, CH_0, rank 0
6203 06:01:57.253889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6204 06:01:57.257277 ==
6205 06:01:57.257853
6206 06:01:57.258223
6207 06:01:57.258564 TX Vref Scan disable
6208 06:01:57.260640 == TX Byte 0 ==
6209 06:01:57.264097 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6210 06:01:57.267407 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6211 06:01:57.270681 == TX Byte 1 ==
6212 06:01:57.273806 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6213 06:01:57.277151 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6214 06:01:57.277622
6215 06:01:57.279984 [DATLAT]
6216 06:01:57.280449 Freq=400, CH0 RK0
6217 06:01:57.280875
6218 06:01:57.283402 DATLAT Default: 0xf
6219 06:01:57.283865 0, 0xFFFF, sum = 0
6220 06:01:57.286951 1, 0xFFFF, sum = 0
6221 06:01:57.287552 2, 0xFFFF, sum = 0
6222 06:01:57.290415 3, 0xFFFF, sum = 0
6223 06:01:57.290988 4, 0xFFFF, sum = 0
6224 06:01:57.293451 5, 0xFFFF, sum = 0
6225 06:01:57.293947 6, 0xFFFF, sum = 0
6226 06:01:57.296662 7, 0xFFFF, sum = 0
6227 06:01:57.297227 8, 0xFFFF, sum = 0
6228 06:01:57.300246 9, 0xFFFF, sum = 0
6229 06:01:57.300858 10, 0xFFFF, sum = 0
6230 06:01:57.303724 11, 0xFFFF, sum = 0
6231 06:01:57.306956 12, 0x0, sum = 1
6232 06:01:57.307630 13, 0x0, sum = 2
6233 06:01:57.308195 14, 0x0, sum = 3
6234 06:01:57.309906 15, 0x0, sum = 4
6235 06:01:57.310377 best_step = 13
6236 06:01:57.310743
6237 06:01:57.311081 ==
6238 06:01:57.313334 Dram Type= 6, Freq= 0, CH_0, rank 0
6239 06:01:57.319928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6240 06:01:57.320493 ==
6241 06:01:57.320972 RX Vref Scan: 1
6242 06:01:57.321340
6243 06:01:57.323164 RX Vref 0 -> 0, step: 1
6244 06:01:57.323726
6245 06:01:57.326825 RX Delay -359 -> 252, step: 8
6246 06:01:57.327387
6247 06:01:57.329584 Set Vref, RX VrefLevel [Byte0]: 48
6248 06:01:57.332970 [Byte1]: 51
6249 06:01:57.336776
6250 06:01:57.340078 Final RX Vref Byte 0 = 48 to rank0
6251 06:01:57.340649 Final RX Vref Byte 1 = 51 to rank0
6252 06:01:57.343067 Final RX Vref Byte 0 = 48 to rank1
6253 06:01:57.346368 Final RX Vref Byte 1 = 51 to rank1==
6254 06:01:57.349917 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 06:01:57.356319 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6256 06:01:57.356860 ==
6257 06:01:57.357273 DQS Delay:
6258 06:01:57.359973 DQS0 = 52, DQS1 = 68
6259 06:01:57.360532 DQM Delay:
6260 06:01:57.360947 DQM0 = 10, DQM1 = 17
6261 06:01:57.363065 DQ Delay:
6262 06:01:57.366647 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6263 06:01:57.369875 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6264 06:01:57.370435 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6265 06:01:57.372971 DQ12 =28, DQ13 =24, DQ14 =28, DQ15 =28
6266 06:01:57.376285
6267 06:01:57.376888
6268 06:01:57.382886 [DQSOSCAuto] RK0, (LSB)MR18= 0xa3a3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6269 06:01:57.386335 CH0 RK0: MR19=C0C, MR18=A3A3
6270 06:01:57.392930 CH0_RK0: MR19=0xC0C, MR18=0xA3A3, DQSOSC=389, MR23=63, INC=390, DEC=260
6271 06:01:57.393403 ==
6272 06:01:57.396204 Dram Type= 6, Freq= 0, CH_0, rank 1
6273 06:01:57.399881 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6274 06:01:57.400467 ==
6275 06:01:57.402983 [Gating] SW mode calibration
6276 06:01:57.409326 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6277 06:01:57.416167 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6278 06:01:57.420029 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6279 06:01:57.422739 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6280 06:01:57.429097 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 06:01:57.432417 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6282 06:01:57.435957 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 06:01:57.442395 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 06:01:57.445440 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 06:01:57.448959 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6286 06:01:57.455701 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 06:01:57.456260 Total UI for P1: 0, mck2ui 16
6288 06:01:57.462380 best dqsien dly found for B0: ( 0, 10, 16)
6289 06:01:57.462965 Total UI for P1: 0, mck2ui 16
6290 06:01:57.468585 best dqsien dly found for B1: ( 0, 10, 24)
6291 06:01:57.471991 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6292 06:01:57.475394 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6293 06:01:57.475955
6294 06:01:57.478220 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6295 06:01:57.481592 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6296 06:01:57.484945 [Gating] SW calibration Done
6297 06:01:57.485437 ==
6298 06:01:57.488564 Dram Type= 6, Freq= 0, CH_0, rank 1
6299 06:01:57.491900 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6300 06:01:57.492363 ==
6301 06:01:57.494981 RX Vref Scan: 0
6302 06:01:57.495708
6303 06:01:57.497990 RX Vref 0 -> 0, step: 1
6304 06:01:57.498448
6305 06:01:57.498808 RX Delay -410 -> 252, step: 16
6306 06:01:57.505048 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6307 06:01:57.508086 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6308 06:01:57.511377 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6309 06:01:57.518018 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6310 06:01:57.521271 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6311 06:01:57.524549 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6312 06:01:57.528128 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6313 06:01:57.534455 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6314 06:01:57.537608 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6315 06:01:57.541261 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6316 06:01:57.544788 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6317 06:01:57.551109 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6318 06:01:57.554148 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6319 06:01:57.557729 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6320 06:01:57.561140 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6321 06:01:57.567445 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6322 06:01:57.568010 ==
6323 06:01:57.570966 Dram Type= 6, Freq= 0, CH_0, rank 1
6324 06:01:57.573974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6325 06:01:57.574437 ==
6326 06:01:57.574806 DQS Delay:
6327 06:01:57.577529 DQS0 = 43, DQS1 = 59
6328 06:01:57.578210 DQM Delay:
6329 06:01:57.580510 DQM0 = 6, DQM1 = 14
6330 06:01:57.581014 DQ Delay:
6331 06:01:57.583675 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6332 06:01:57.587493 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6333 06:01:57.590670 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6334 06:01:57.593938 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6335 06:01:57.594402
6336 06:01:57.594772
6337 06:01:57.595112 ==
6338 06:01:57.597369 Dram Type= 6, Freq= 0, CH_0, rank 1
6339 06:01:57.600508 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6340 06:01:57.601148 ==
6341 06:01:57.601527
6342 06:01:57.603766
6343 06:01:57.604318 TX Vref Scan disable
6344 06:01:57.606961 == TX Byte 0 ==
6345 06:01:57.610332 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6346 06:01:57.613570 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6347 06:01:57.616897 == TX Byte 1 ==
6348 06:01:57.620631 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6349 06:01:57.623717 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6350 06:01:57.624303 ==
6351 06:01:57.626992 Dram Type= 6, Freq= 0, CH_0, rank 1
6352 06:01:57.630324 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6353 06:01:57.630892 ==
6354 06:01:57.633233
6355 06:01:57.633687
6356 06:01:57.634049 TX Vref Scan disable
6357 06:01:57.636698 == TX Byte 0 ==
6358 06:01:57.640491 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6359 06:01:57.643245 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6360 06:01:57.646700 == TX Byte 1 ==
6361 06:01:57.649974 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6362 06:01:57.653140 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6363 06:01:57.653648
6364 06:01:57.654009 [DATLAT]
6365 06:01:57.656402 Freq=400, CH0 RK1
6366 06:01:57.656895
6367 06:01:57.659657 DATLAT Default: 0xd
6368 06:01:57.660107 0, 0xFFFF, sum = 0
6369 06:01:57.662979 1, 0xFFFF, sum = 0
6370 06:01:57.663442 2, 0xFFFF, sum = 0
6371 06:01:57.666172 3, 0xFFFF, sum = 0
6372 06:01:57.666632 4, 0xFFFF, sum = 0
6373 06:01:57.669752 5, 0xFFFF, sum = 0
6374 06:01:57.670318 6, 0xFFFF, sum = 0
6375 06:01:57.673099 7, 0xFFFF, sum = 0
6376 06:01:57.673665 8, 0xFFFF, sum = 0
6377 06:01:57.676347 9, 0xFFFF, sum = 0
6378 06:01:57.676944 10, 0xFFFF, sum = 0
6379 06:01:57.679373 11, 0xFFFF, sum = 0
6380 06:01:57.679832 12, 0x0, sum = 1
6381 06:01:57.682717 13, 0x0, sum = 2
6382 06:01:57.683179 14, 0x0, sum = 3
6383 06:01:57.686071 15, 0x0, sum = 4
6384 06:01:57.686634 best_step = 13
6385 06:01:57.686999
6386 06:01:57.687332 ==
6387 06:01:57.689414 Dram Type= 6, Freq= 0, CH_0, rank 1
6388 06:01:57.695903 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6389 06:01:57.696509 ==
6390 06:01:57.697127 RX Vref Scan: 0
6391 06:01:57.697771
6392 06:01:57.699111 RX Vref 0 -> 0, step: 1
6393 06:01:57.699564
6394 06:01:57.702985 RX Delay -359 -> 252, step: 8
6395 06:01:57.709042 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6396 06:01:57.712341 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6397 06:01:57.715911 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6398 06:01:57.719257 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6399 06:01:57.725757 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6400 06:01:57.729044 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6401 06:01:57.732160 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6402 06:01:57.735668 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6403 06:01:57.742409 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6404 06:01:57.745605 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6405 06:01:57.749081 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6406 06:01:57.752489 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6407 06:01:57.758665 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6408 06:01:57.762186 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6409 06:01:57.765571 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6410 06:01:57.772107 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6411 06:01:57.772680 ==
6412 06:01:57.775461 Dram Type= 6, Freq= 0, CH_0, rank 1
6413 06:01:57.778685 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6414 06:01:57.779243 ==
6415 06:01:57.779609 DQS Delay:
6416 06:01:57.781911 DQS0 = 52, DQS1 = 64
6417 06:01:57.782430 DQM Delay:
6418 06:01:57.785184 DQM0 = 10, DQM1 = 15
6419 06:01:57.785641 DQ Delay:
6420 06:01:57.788862 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4
6421 06:01:57.792485 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6422 06:01:57.795376 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6423 06:01:57.798542 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6424 06:01:57.799001
6425 06:01:57.799360
6426 06:01:57.805094 [DQSOSCAuto] RK1, (LSB)MR18= 0xc4c4, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6427 06:01:57.808639 CH0 RK1: MR19=C0C, MR18=C4C4
6428 06:01:57.815070 CH0_RK1: MR19=0xC0C, MR18=0xC4C4, DQSOSC=385, MR23=63, INC=398, DEC=265
6429 06:01:57.818520 [RxdqsGatingPostProcess] freq 400
6430 06:01:57.825015 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6431 06:01:57.828606 Pre-setting of DQS Precalculation
6432 06:01:57.831541 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6433 06:01:57.832100 ==
6434 06:01:57.834892 Dram Type= 6, Freq= 0, CH_1, rank 0
6435 06:01:57.838245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6436 06:01:57.838810 ==
6437 06:01:57.845251 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6438 06:01:57.851245 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6439 06:01:57.854532 [CA 0] Center 36 (8~64) winsize 57
6440 06:01:57.857824 [CA 1] Center 36 (8~64) winsize 57
6441 06:01:57.861289 [CA 2] Center 36 (8~64) winsize 57
6442 06:01:57.864614 [CA 3] Center 36 (8~64) winsize 57
6443 06:01:57.867795 [CA 4] Center 36 (8~64) winsize 57
6444 06:01:57.871434 [CA 5] Center 36 (8~64) winsize 57
6445 06:01:57.871996
6446 06:01:57.874750 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6447 06:01:57.875323
6448 06:01:57.877962 [CATrainingPosCal] consider 1 rank data
6449 06:01:57.881090 u2DelayCellTimex100 = 270/100 ps
6450 06:01:57.884267 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6451 06:01:57.887911 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6452 06:01:57.891587 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6453 06:01:57.894920 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6454 06:01:57.897564 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6455 06:01:57.901106 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6456 06:01:57.901673
6457 06:01:57.904353 CA PerBit enable=1, Macro0, CA PI delay=36
6458 06:01:57.907565
6459 06:01:57.908116 [CBTSetCACLKResult] CA Dly = 36
6460 06:01:57.910851 CS Dly: 1 (0~32)
6461 06:01:57.911312 ==
6462 06:01:57.914510 Dram Type= 6, Freq= 0, CH_1, rank 1
6463 06:01:57.917655 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6464 06:01:57.918221 ==
6465 06:01:57.924083 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6466 06:01:57.930979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6467 06:01:57.934067 [CA 0] Center 36 (8~64) winsize 57
6468 06:01:57.937177 [CA 1] Center 36 (8~64) winsize 57
6469 06:01:57.940879 [CA 2] Center 36 (8~64) winsize 57
6470 06:01:57.941513 [CA 3] Center 36 (8~64) winsize 57
6471 06:01:57.944046 [CA 4] Center 36 (8~64) winsize 57
6472 06:01:57.947384 [CA 5] Center 36 (8~64) winsize 57
6473 06:01:57.947965
6474 06:01:57.954109 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6475 06:01:57.954697
6476 06:01:57.957271 [CATrainingPosCal] consider 2 rank data
6477 06:01:57.960621 u2DelayCellTimex100 = 270/100 ps
6478 06:01:57.963832 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6479 06:01:57.966800 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6480 06:01:57.970295 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6481 06:01:57.973373 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6482 06:01:57.976912 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6483 06:01:57.979905 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6484 06:01:57.980363
6485 06:01:57.983253 CA PerBit enable=1, Macro0, CA PI delay=36
6486 06:01:57.983740
6487 06:01:57.986583 [CBTSetCACLKResult] CA Dly = 36
6488 06:01:57.990623 CS Dly: 1 (0~32)
6489 06:01:57.991187
6490 06:01:57.993425 ----->DramcWriteLeveling(PI) begin...
6491 06:01:57.993888 ==
6492 06:01:57.996809 Dram Type= 6, Freq= 0, CH_1, rank 0
6493 06:01:57.999989 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6494 06:01:58.000842 ==
6495 06:01:58.003391 Write leveling (Byte 0): 32 => 0
6496 06:01:58.006461 Write leveling (Byte 1): 32 => 0
6497 06:01:58.009717 DramcWriteLeveling(PI) end<-----
6498 06:01:58.010176
6499 06:01:58.010532 ==
6500 06:01:58.013300 Dram Type= 6, Freq= 0, CH_1, rank 0
6501 06:01:58.016750 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6502 06:01:58.017322 ==
6503 06:01:58.019635 [Gating] SW mode calibration
6504 06:01:58.026293 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6505 06:01:58.033188 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6506 06:01:58.036391 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6507 06:01:58.039722 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6508 06:01:58.046100 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6509 06:01:58.049585 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6510 06:01:58.052930 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 06:01:58.059524 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 06:01:58.063028 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 06:01:58.065915 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6514 06:01:58.072757 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6515 06:01:58.075987 Total UI for P1: 0, mck2ui 16
6516 06:01:58.079645 best dqsien dly found for B0: ( 0, 10, 16)
6517 06:01:58.082423 Total UI for P1: 0, mck2ui 16
6518 06:01:58.085720 best dqsien dly found for B1: ( 0, 10, 16)
6519 06:01:58.089008 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6520 06:01:58.092578 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6521 06:01:58.093320
6522 06:01:58.095900 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6523 06:01:58.098838 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6524 06:01:58.102128 [Gating] SW calibration Done
6525 06:01:58.102591 ==
6526 06:01:58.105406 Dram Type= 6, Freq= 0, CH_1, rank 0
6527 06:01:58.108863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6528 06:01:58.112167 ==
6529 06:01:58.112630 RX Vref Scan: 0
6530 06:01:58.113058
6531 06:01:58.115713 RX Vref 0 -> 0, step: 1
6532 06:01:58.116270
6533 06:01:58.119018 RX Delay -410 -> 252, step: 16
6534 06:01:58.121933 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6535 06:01:58.125442 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6536 06:01:58.128657 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6537 06:01:58.135484 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6538 06:01:58.138759 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6539 06:01:58.142089 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6540 06:01:58.145490 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6541 06:01:58.152139 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6542 06:01:58.155471 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6543 06:01:58.158479 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6544 06:01:58.161702 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6545 06:01:58.168659 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6546 06:01:58.171699 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6547 06:01:58.175229 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6548 06:01:58.181852 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6549 06:01:58.184922 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6550 06:01:58.185559 ==
6551 06:01:58.188205 Dram Type= 6, Freq= 0, CH_1, rank 0
6552 06:01:58.191514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6553 06:01:58.192077 ==
6554 06:01:58.195326 DQS Delay:
6555 06:01:58.195886 DQS0 = 43, DQS1 = 59
6556 06:01:58.196258 DQM Delay:
6557 06:01:58.198374 DQM0 = 6, DQM1 = 15
6558 06:01:58.198839 DQ Delay:
6559 06:01:58.201750 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6560 06:01:58.204799 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6561 06:01:58.208467 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6562 06:01:58.211405 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6563 06:01:58.211866
6564 06:01:58.212224
6565 06:01:58.212657 ==
6566 06:01:58.214888 Dram Type= 6, Freq= 0, CH_1, rank 0
6567 06:01:58.218397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6568 06:01:58.218960 ==
6569 06:01:58.221374
6570 06:01:58.221831
6571 06:01:58.222193 TX Vref Scan disable
6572 06:01:58.224988 == TX Byte 0 ==
6573 06:01:58.227878 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6574 06:01:58.231063 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6575 06:01:58.234837 == TX Byte 1 ==
6576 06:01:58.237817 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6577 06:01:58.241331 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6578 06:01:58.241795 ==
6579 06:01:58.244966 Dram Type= 6, Freq= 0, CH_1, rank 0
6580 06:01:58.251463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6581 06:01:58.252026 ==
6582 06:01:58.252391
6583 06:01:58.252799
6584 06:01:58.253143 TX Vref Scan disable
6585 06:01:58.254463 == TX Byte 0 ==
6586 06:01:58.257873 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6587 06:01:58.261056 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6588 06:01:58.264342 == TX Byte 1 ==
6589 06:01:58.267998 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6590 06:01:58.271511 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6591 06:01:58.272073
6592 06:01:58.274513 [DATLAT]
6593 06:01:58.274976 Freq=400, CH1 RK0
6594 06:01:58.275340
6595 06:01:58.277893 DATLAT Default: 0xf
6596 06:01:58.278577 0, 0xFFFF, sum = 0
6597 06:01:58.280936 1, 0xFFFF, sum = 0
6598 06:01:58.281407 2, 0xFFFF, sum = 0
6599 06:01:58.284409 3, 0xFFFF, sum = 0
6600 06:01:58.284924 4, 0xFFFF, sum = 0
6601 06:01:58.287394 5, 0xFFFF, sum = 0
6602 06:01:58.287864 6, 0xFFFF, sum = 0
6603 06:01:58.290931 7, 0xFFFF, sum = 0
6604 06:01:58.294085 8, 0xFFFF, sum = 0
6605 06:01:58.294555 9, 0xFFFF, sum = 0
6606 06:01:58.297437 10, 0xFFFF, sum = 0
6607 06:01:58.297904 11, 0xFFFF, sum = 0
6608 06:01:58.300678 12, 0x0, sum = 1
6609 06:01:58.301194 13, 0x0, sum = 2
6610 06:01:58.303883 14, 0x0, sum = 3
6611 06:01:58.304351 15, 0x0, sum = 4
6612 06:01:58.304769 best_step = 13
6613 06:01:58.305123
6614 06:01:58.307358 ==
6615 06:01:58.310558 Dram Type= 6, Freq= 0, CH_1, rank 0
6616 06:01:58.313818 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6617 06:01:58.314287 ==
6618 06:01:58.314653 RX Vref Scan: 1
6619 06:01:58.314995
6620 06:01:58.317134 RX Vref 0 -> 0, step: 1
6621 06:01:58.317599
6622 06:01:58.320372 RX Delay -359 -> 252, step: 8
6623 06:01:58.320893
6624 06:01:58.323629 Set Vref, RX VrefLevel [Byte0]: 56
6625 06:01:58.326998 [Byte1]: 47
6626 06:01:58.331219
6627 06:01:58.331638 Final RX Vref Byte 0 = 56 to rank0
6628 06:01:58.334590 Final RX Vref Byte 1 = 47 to rank0
6629 06:01:58.337471 Final RX Vref Byte 0 = 56 to rank1
6630 06:01:58.340903 Final RX Vref Byte 1 = 47 to rank1==
6631 06:01:58.344435 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 06:01:58.351024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6633 06:01:58.351585 ==
6634 06:01:58.351953 DQS Delay:
6635 06:01:58.354260 DQS0 = 48, DQS1 = 68
6636 06:01:58.354816 DQM Delay:
6637 06:01:58.355186 DQM0 = 7, DQM1 = 20
6638 06:01:58.357526 DQ Delay:
6639 06:01:58.360846 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6640 06:01:58.361320 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6641 06:01:58.364570 DQ8 =0, DQ9 =12, DQ10 =24, DQ11 =12
6642 06:01:58.367349 DQ12 =28, DQ13 =28, DQ14 =28, DQ15 =28
6643 06:01:58.367907
6644 06:01:58.370994
6645 06:01:58.377284 [DQSOSCAuto] RK0, (LSB)MR18= 0xd7d7, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6646 06:01:58.380544 CH1 RK0: MR19=C0C, MR18=D7D7
6647 06:01:58.387084 CH1_RK0: MR19=0xC0C, MR18=0xD7D7, DQSOSC=383, MR23=63, INC=402, DEC=268
6648 06:01:58.387565 ==
6649 06:01:58.390880 Dram Type= 6, Freq= 0, CH_1, rank 1
6650 06:01:58.393917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6651 06:01:58.394386 ==
6652 06:01:58.397239 [Gating] SW mode calibration
6653 06:01:58.403835 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6654 06:01:58.410287 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6655 06:01:58.413382 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 06:01:58.417152 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6657 06:01:58.423881 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 06:01:58.426938 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6659 06:01:58.430444 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 06:01:58.436954 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 06:01:58.440329 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 06:01:58.443532 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6663 06:01:58.450005 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 06:01:58.450548 Total UI for P1: 0, mck2ui 16
6665 06:01:58.453497 best dqsien dly found for B0: ( 0, 10, 16)
6666 06:01:58.456817 Total UI for P1: 0, mck2ui 16
6667 06:01:58.459923 best dqsien dly found for B1: ( 0, 10, 16)
6668 06:01:58.466773 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6669 06:01:58.470365 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6670 06:01:58.470924
6671 06:01:58.473150 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6672 06:01:58.476650 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6673 06:01:58.480140 [Gating] SW calibration Done
6674 06:01:58.480761 ==
6675 06:01:58.483167 Dram Type= 6, Freq= 0, CH_1, rank 1
6676 06:01:58.486459 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6677 06:01:58.487055 ==
6678 06:01:58.489712 RX Vref Scan: 0
6679 06:01:58.490170
6680 06:01:58.490534 RX Vref 0 -> 0, step: 1
6681 06:01:58.490873
6682 06:01:58.493285 RX Delay -410 -> 252, step: 16
6683 06:01:58.499856 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6684 06:01:58.503251 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6685 06:01:58.506214 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6686 06:01:58.510187 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6687 06:01:58.516200 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6688 06:01:58.519773 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6689 06:01:58.523009 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6690 06:01:58.526164 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6691 06:01:58.532855 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6692 06:01:58.536297 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6693 06:01:58.539531 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6694 06:01:58.542849 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6695 06:01:58.549701 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6696 06:01:58.552556 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6697 06:01:58.555701 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6698 06:01:58.559462 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6699 06:01:58.562625 ==
6700 06:01:58.566038 Dram Type= 6, Freq= 0, CH_1, rank 1
6701 06:01:58.569294 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6702 06:01:58.569860 ==
6703 06:01:58.570234 DQS Delay:
6704 06:01:58.572623 DQS0 = 35, DQS1 = 59
6705 06:01:58.573239 DQM Delay:
6706 06:01:58.576047 DQM0 = 3, DQM1 = 18
6707 06:01:58.576610 DQ Delay:
6708 06:01:58.579299 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6709 06:01:58.582607 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6710 06:01:58.585582 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6711 06:01:58.589501 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6712 06:01:58.589965
6713 06:01:58.590329
6714 06:01:58.590666 ==
6715 06:01:58.592398 Dram Type= 6, Freq= 0, CH_1, rank 1
6716 06:01:58.595581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6717 06:01:58.596048 ==
6718 06:01:58.596416
6719 06:01:58.596802
6720 06:01:58.599122 TX Vref Scan disable
6721 06:01:58.599585 == TX Byte 0 ==
6722 06:01:58.602311 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6723 06:01:58.609049 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6724 06:01:58.609514 == TX Byte 1 ==
6725 06:01:58.612184 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6726 06:01:58.618798 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6727 06:01:58.619360 ==
6728 06:01:58.622152 Dram Type= 6, Freq= 0, CH_1, rank 1
6729 06:01:58.625422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6730 06:01:58.625886 ==
6731 06:01:58.626252
6732 06:01:58.626593
6733 06:01:58.628835 TX Vref Scan disable
6734 06:01:58.629295 == TX Byte 0 ==
6735 06:01:58.635531 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6736 06:01:58.639121 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6737 06:01:58.639691 == TX Byte 1 ==
6738 06:01:58.645669 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6739 06:01:58.648994 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6740 06:01:58.649573
6741 06:01:58.649943 [DATLAT]
6742 06:01:58.652285 Freq=400, CH1 RK1
6743 06:01:58.652890
6744 06:01:58.653265 DATLAT Default: 0xd
6745 06:01:58.655285 0, 0xFFFF, sum = 0
6746 06:01:58.655755 1, 0xFFFF, sum = 0
6747 06:01:58.658442 2, 0xFFFF, sum = 0
6748 06:01:58.658913 3, 0xFFFF, sum = 0
6749 06:01:58.661762 4, 0xFFFF, sum = 0
6750 06:01:58.662242 5, 0xFFFF, sum = 0
6751 06:01:58.665562 6, 0xFFFF, sum = 0
6752 06:01:58.666132 7, 0xFFFF, sum = 0
6753 06:01:58.668563 8, 0xFFFF, sum = 0
6754 06:01:58.669350 9, 0xFFFF, sum = 0
6755 06:01:58.671994 10, 0xFFFF, sum = 0
6756 06:01:58.675231 11, 0xFFFF, sum = 0
6757 06:01:58.675795 12, 0x0, sum = 1
6758 06:01:58.676172 13, 0x0, sum = 2
6759 06:01:58.678384 14, 0x0, sum = 3
6760 06:01:58.678950 15, 0x0, sum = 4
6761 06:01:58.681499 best_step = 13
6762 06:01:58.681961
6763 06:01:58.682322 ==
6764 06:01:58.685089 Dram Type= 6, Freq= 0, CH_1, rank 1
6765 06:01:58.688118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6766 06:01:58.688850 ==
6767 06:01:58.691781 RX Vref Scan: 0
6768 06:01:58.692239
6769 06:01:58.692599 RX Vref 0 -> 0, step: 1
6770 06:01:58.692994
6771 06:01:58.694752 RX Delay -359 -> 252, step: 8
6772 06:01:58.703384 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6773 06:01:58.707097 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6774 06:01:58.709755 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6775 06:01:58.713188 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6776 06:01:58.720334 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6777 06:01:58.723576 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6778 06:01:58.726434 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6779 06:01:58.729954 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6780 06:01:58.736834 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6781 06:01:58.739650 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6782 06:01:58.743253 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6783 06:01:58.749788 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6784 06:01:58.753151 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6785 06:01:58.756553 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6786 06:01:58.759778 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6787 06:01:58.766320 iDelay=225, Bit 15, Center -44 (-287 ~ 200) 488
6788 06:01:58.766870 ==
6789 06:01:58.769573 Dram Type= 6, Freq= 0, CH_1, rank 1
6790 06:01:58.772979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6791 06:01:58.773534 ==
6792 06:01:58.773900 DQS Delay:
6793 06:01:58.776248 DQS0 = 48, DQS1 = 64
6794 06:01:58.776848 DQM Delay:
6795 06:01:58.779610 DQM0 = 9, DQM1 = 15
6796 06:01:58.780163 DQ Delay:
6797 06:01:58.782971 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6798 06:01:58.786106 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6799 06:01:58.789404 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6800 06:01:58.792637 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6801 06:01:58.793158
6802 06:01:58.793522
6803 06:01:58.799295 [DQSOSCAuto] RK1, (LSB)MR18= 0xa9a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6804 06:01:58.803115 CH1 RK1: MR19=C0C, MR18=A9A9
6805 06:01:58.809279 CH1_RK1: MR19=0xC0C, MR18=0xA9A9, DQSOSC=388, MR23=63, INC=392, DEC=261
6806 06:01:58.812440 [RxdqsGatingPostProcess] freq 400
6807 06:01:58.819369 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6808 06:01:58.822397 Pre-setting of DQS Precalculation
6809 06:01:58.825830 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6810 06:01:58.832507 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6811 06:01:58.838752 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6812 06:01:58.839300
6813 06:01:58.842322
6814 06:01:58.842781 [Calibration Summary] 800 Mbps
6815 06:01:58.845472 CH 0, Rank 0
6816 06:01:58.845932 SW Impedance : PASS
6817 06:01:58.849296 DUTY Scan : NO K
6818 06:01:58.852181 ZQ Calibration : PASS
6819 06:01:58.852644 Jitter Meter : NO K
6820 06:01:58.855660 CBT Training : PASS
6821 06:01:58.858875 Write leveling : PASS
6822 06:01:58.859340 RX DQS gating : PASS
6823 06:01:58.861878 RX DQ/DQS(RDDQC) : PASS
6824 06:01:58.865643 TX DQ/DQS : PASS
6825 06:01:58.866204 RX DATLAT : PASS
6826 06:01:58.868521 RX DQ/DQS(Engine): PASS
6827 06:01:58.872233 TX OE : NO K
6828 06:01:58.872845 All Pass.
6829 06:01:58.873220
6830 06:01:58.873558 CH 0, Rank 1
6831 06:01:58.875364 SW Impedance : PASS
6832 06:01:58.875921 DUTY Scan : NO K
6833 06:01:58.878772 ZQ Calibration : PASS
6834 06:01:58.881940 Jitter Meter : NO K
6835 06:01:58.882401 CBT Training : PASS
6836 06:01:58.885416 Write leveling : NO K
6837 06:01:58.888683 RX DQS gating : PASS
6838 06:01:58.889465 RX DQ/DQS(RDDQC) : PASS
6839 06:01:58.892141 TX DQ/DQS : PASS
6840 06:01:58.895144 RX DATLAT : PASS
6841 06:01:58.895702 RX DQ/DQS(Engine): PASS
6842 06:01:58.898448 TX OE : NO K
6843 06:01:58.898912 All Pass.
6844 06:01:58.899282
6845 06:01:58.902003 CH 1, Rank 0
6846 06:01:58.902560 SW Impedance : PASS
6847 06:01:58.905103 DUTY Scan : NO K
6848 06:01:58.908548 ZQ Calibration : PASS
6849 06:01:58.909098 Jitter Meter : NO K
6850 06:01:58.912093 CBT Training : PASS
6851 06:01:58.915127 Write leveling : PASS
6852 06:01:58.915730 RX DQS gating : PASS
6853 06:01:58.918370 RX DQ/DQS(RDDQC) : PASS
6854 06:01:58.921451 TX DQ/DQS : PASS
6855 06:01:58.922048 RX DATLAT : PASS
6856 06:01:58.925171 RX DQ/DQS(Engine): PASS
6857 06:01:58.929143 TX OE : NO K
6858 06:01:58.929763 All Pass.
6859 06:01:58.930301
6860 06:01:58.930673 CH 1, Rank 1
6861 06:01:58.931425 SW Impedance : PASS
6862 06:01:58.935116 DUTY Scan : NO K
6863 06:01:58.935672 ZQ Calibration : PASS
6864 06:01:58.938243 Jitter Meter : NO K
6865 06:01:58.938705 CBT Training : PASS
6866 06:01:58.941566 Write leveling : NO K
6867 06:01:58.944985 RX DQS gating : PASS
6868 06:01:58.945540 RX DQ/DQS(RDDQC) : PASS
6869 06:01:58.948280 TX DQ/DQS : PASS
6870 06:01:58.951619 RX DATLAT : PASS
6871 06:01:58.952180 RX DQ/DQS(Engine): PASS
6872 06:01:58.954865 TX OE : NO K
6873 06:01:58.955423 All Pass.
6874 06:01:58.955789
6875 06:01:58.958152 DramC Write-DBI off
6876 06:01:58.961362 PER_BANK_REFRESH: Hybrid Mode
6877 06:01:58.961825 TX_TRACKING: ON
6878 06:01:58.971698 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6879 06:01:58.974506 [FAST_K] Save calibration result to emmc
6880 06:01:58.978078 dramc_set_vcore_voltage set vcore to 725000
6881 06:01:58.981231 Read voltage for 1600, 0
6882 06:01:58.981810 Vio18 = 0
6883 06:01:58.982180 Vcore = 725000
6884 06:01:58.984597 Vdram = 0
6885 06:01:58.985207 Vddq = 0
6886 06:01:58.985576 Vmddr = 0
6887 06:01:58.991272 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6888 06:01:58.994716 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6889 06:01:58.997653 MEM_TYPE=3, freq_sel=13
6890 06:01:59.001524 sv_algorithm_assistance_LP4_3733
6891 06:01:59.004279 ============ PULL DRAM RESETB DOWN ============
6892 06:01:59.011257 ========== PULL DRAM RESETB DOWN end =========
6893 06:01:59.014389 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6894 06:01:59.017914 ===================================
6895 06:01:59.021054 LPDDR4 DRAM CONFIGURATION
6896 06:01:59.024839 ===================================
6897 06:01:59.025403 EX_ROW_EN[0] = 0x0
6898 06:01:59.027664 EX_ROW_EN[1] = 0x0
6899 06:01:59.028224 LP4Y_EN = 0x0
6900 06:01:59.031070 WORK_FSP = 0x1
6901 06:01:59.031626 WL = 0x5
6902 06:01:59.034522 RL = 0x5
6903 06:01:59.035218 BL = 0x2
6904 06:01:59.037423 RPST = 0x0
6905 06:01:59.037885 RD_PRE = 0x0
6906 06:01:59.041138 WR_PRE = 0x1
6907 06:01:59.044149 WR_PST = 0x1
6908 06:01:59.044744 DBI_WR = 0x0
6909 06:01:59.047383 DBI_RD = 0x0
6910 06:01:59.047893 OTF = 0x1
6911 06:01:59.050551 ===================================
6912 06:01:59.053966 ===================================
6913 06:01:59.057296 ANA top config
6914 06:01:59.057855 ===================================
6915 06:01:59.060545 DLL_ASYNC_EN = 0
6916 06:01:59.064084 ALL_SLAVE_EN = 0
6917 06:01:59.067368 NEW_RANK_MODE = 1
6918 06:01:59.070434 DLL_IDLE_MODE = 1
6919 06:01:59.070899 LP45_APHY_COMB_EN = 1
6920 06:01:59.074043 TX_ODT_DIS = 0
6921 06:01:59.077513 NEW_8X_MODE = 1
6922 06:01:59.080608 ===================================
6923 06:01:59.083886 ===================================
6924 06:01:59.087418 data_rate = 3200
6925 06:01:59.090281 CKR = 1
6926 06:01:59.093924 DQ_P2S_RATIO = 8
6927 06:01:59.097441 ===================================
6928 06:01:59.097905 CA_P2S_RATIO = 8
6929 06:01:59.100130 DQ_CA_OPEN = 0
6930 06:01:59.103609 DQ_SEMI_OPEN = 0
6931 06:01:59.106816 CA_SEMI_OPEN = 0
6932 06:01:59.110118 CA_FULL_RATE = 0
6933 06:01:59.113498 DQ_CKDIV4_EN = 0
6934 06:01:59.113967 CA_CKDIV4_EN = 0
6935 06:01:59.116893 CA_PREDIV_EN = 0
6936 06:01:59.120303 PH8_DLY = 12
6937 06:01:59.123843 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6938 06:01:59.126852 DQ_AAMCK_DIV = 4
6939 06:01:59.130231 CA_AAMCK_DIV = 4
6940 06:01:59.130792 CA_ADMCK_DIV = 4
6941 06:01:59.133531 DQ_TRACK_CA_EN = 0
6942 06:01:59.136849 CA_PICK = 1600
6943 06:01:59.140007 CA_MCKIO = 1600
6944 06:01:59.143232 MCKIO_SEMI = 0
6945 06:01:59.146605 PLL_FREQ = 3068
6946 06:01:59.149843 DQ_UI_PI_RATIO = 32
6947 06:01:59.150406 CA_UI_PI_RATIO = 0
6948 06:01:59.153370 ===================================
6949 06:01:59.156564 ===================================
6950 06:01:59.160110 memory_type:LPDDR4
6951 06:01:59.163337 GP_NUM : 10
6952 06:01:59.163915 SRAM_EN : 1
6953 06:01:59.166431 MD32_EN : 0
6954 06:01:59.169730 ===================================
6955 06:01:59.173000 [ANA_INIT] >>>>>>>>>>>>>>
6956 06:01:59.176661 <<<<<< [CONFIGURE PHASE]: ANA_TX
6957 06:01:59.179885 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6958 06:01:59.182843 ===================================
6959 06:01:59.183311 data_rate = 3200,PCW = 0X7600
6960 06:01:59.186049 ===================================
6961 06:01:59.192658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6962 06:01:59.196397 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6963 06:01:59.203049 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6964 06:01:59.206178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6965 06:01:59.209301 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6966 06:01:59.212733 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6967 06:01:59.216177 [ANA_INIT] flow start
6968 06:01:59.219580 [ANA_INIT] PLL >>>>>>>>
6969 06:01:59.220160 [ANA_INIT] PLL <<<<<<<<
6970 06:01:59.222666 [ANA_INIT] MIDPI >>>>>>>>
6971 06:01:59.225876 [ANA_INIT] MIDPI <<<<<<<<
6972 06:01:59.226341 [ANA_INIT] DLL >>>>>>>>
6973 06:01:59.229400 [ANA_INIT] DLL <<<<<<<<
6974 06:01:59.233068 [ANA_INIT] flow end
6975 06:01:59.235981 ============ LP4 DIFF to SE enter ============
6976 06:01:59.239218 ============ LP4 DIFF to SE exit ============
6977 06:01:59.242357 [ANA_INIT] <<<<<<<<<<<<<
6978 06:01:59.245900 [Flow] Enable top DCM control >>>>>
6979 06:01:59.249348 [Flow] Enable top DCM control <<<<<
6980 06:01:59.253030 Enable DLL master slave shuffle
6981 06:01:59.256004 ==============================================================
6982 06:01:59.259467 Gating Mode config
6983 06:01:59.265884 ==============================================================
6984 06:01:59.266442 Config description:
6985 06:01:59.276033 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6986 06:01:59.282314 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6987 06:01:59.289225 SELPH_MODE 0: By rank 1: By Phase
6988 06:01:59.292183 ==============================================================
6989 06:01:59.295745 GAT_TRACK_EN = 1
6990 06:01:59.299029 RX_GATING_MODE = 2
6991 06:01:59.302062 RX_GATING_TRACK_MODE = 2
6992 06:01:59.305423 SELPH_MODE = 1
6993 06:01:59.308966 PICG_EARLY_EN = 1
6994 06:01:59.312017 VALID_LAT_VALUE = 1
6995 06:01:59.315545 ==============================================================
6996 06:01:59.318613 Enter into Gating configuration >>>>
6997 06:01:59.321758 Exit from Gating configuration <<<<
6998 06:01:59.325364 Enter into DVFS_PRE_config >>>>>
6999 06:01:59.338667 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7000 06:01:59.341756 Exit from DVFS_PRE_config <<<<<
7001 06:01:59.345080 Enter into PICG configuration >>>>
7002 06:01:59.348673 Exit from PICG configuration <<<<
7003 06:01:59.349438 [RX_INPUT] configuration >>>>>
7004 06:01:59.352045 [RX_INPUT] configuration <<<<<
7005 06:01:59.358184 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7006 06:01:59.361523 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7007 06:01:59.368284 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7008 06:01:59.375188 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7009 06:01:59.381217 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7010 06:01:59.387815 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7011 06:01:59.391626 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7012 06:01:59.394443 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7013 06:01:59.401226 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7014 06:01:59.404501 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7015 06:01:59.408031 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7016 06:01:59.411097 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7017 06:01:59.414285 ===================================
7018 06:01:59.417928 LPDDR4 DRAM CONFIGURATION
7019 06:01:59.420824 ===================================
7020 06:01:59.424314 EX_ROW_EN[0] = 0x0
7021 06:01:59.424817 EX_ROW_EN[1] = 0x0
7022 06:01:59.427482 LP4Y_EN = 0x0
7023 06:01:59.427939 WORK_FSP = 0x1
7024 06:01:59.430792 WL = 0x5
7025 06:01:59.431355 RL = 0x5
7026 06:01:59.434310 BL = 0x2
7027 06:01:59.437467 RPST = 0x0
7028 06:01:59.438024 RD_PRE = 0x0
7029 06:01:59.440617 WR_PRE = 0x1
7030 06:01:59.441248 WR_PST = 0x1
7031 06:01:59.443987 DBI_WR = 0x0
7032 06:01:59.444461 DBI_RD = 0x0
7033 06:01:59.447332 OTF = 0x1
7034 06:01:59.450477 ===================================
7035 06:01:59.453781 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7036 06:01:59.457309 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7037 06:01:59.460577 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7038 06:01:59.464201 ===================================
7039 06:01:59.467384 LPDDR4 DRAM CONFIGURATION
7040 06:01:59.470304 ===================================
7041 06:01:59.473745 EX_ROW_EN[0] = 0x10
7042 06:01:59.474304 EX_ROW_EN[1] = 0x0
7043 06:01:59.477066 LP4Y_EN = 0x0
7044 06:01:59.477622 WORK_FSP = 0x1
7045 06:01:59.480431 WL = 0x5
7046 06:01:59.481042 RL = 0x5
7047 06:01:59.483581 BL = 0x2
7048 06:01:59.484042 RPST = 0x0
7049 06:01:59.487113 RD_PRE = 0x0
7050 06:01:59.490534 WR_PRE = 0x1
7051 06:01:59.491118 WR_PST = 0x1
7052 06:01:59.493463 DBI_WR = 0x0
7053 06:01:59.494046 DBI_RD = 0x0
7054 06:01:59.496837 OTF = 0x1
7055 06:01:59.500123 ===================================
7056 06:01:59.503273 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7057 06:01:59.506983 ==
7058 06:01:59.510107 Dram Type= 6, Freq= 0, CH_0, rank 0
7059 06:01:59.513219 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7060 06:01:59.513685 ==
7061 06:01:59.516508 [Duty_Offset_Calibration]
7062 06:01:59.517011 B0:0 B1:2 CA:1
7063 06:01:59.517378
7064 06:01:59.519844 [DutyScan_Calibration_Flow] k_type=0
7065 06:01:59.530475
7066 06:01:59.531033 ==CLK 0==
7067 06:01:59.533293 Final CLK duty delay cell = 0
7068 06:01:59.536697 [0] MAX Duty = 5156%(X100), DQS PI = 22
7069 06:01:59.540198 [0] MIN Duty = 4938%(X100), DQS PI = 54
7070 06:01:59.543250 [0] AVG Duty = 5047%(X100)
7071 06:01:59.543760
7072 06:01:59.546714 CH0 CLK Duty spec in!! Max-Min= 218%
7073 06:01:59.549718 [DutyScan_Calibration_Flow] ====Done====
7074 06:01:59.550180
7075 06:01:59.553061 [DutyScan_Calibration_Flow] k_type=1
7076 06:01:59.570304
7077 06:01:59.570875 ==DQS 0 ==
7078 06:01:59.573546 Final DQS duty delay cell = 0
7079 06:01:59.576850 [0] MAX Duty = 5156%(X100), DQS PI = 34
7080 06:01:59.580244 [0] MIN Duty = 5031%(X100), DQS PI = 8
7081 06:01:59.583514 [0] AVG Duty = 5093%(X100)
7082 06:01:59.584068
7083 06:01:59.584431 ==DQS 1 ==
7084 06:01:59.586864 Final DQS duty delay cell = 0
7085 06:01:59.590256 [0] MAX Duty = 5031%(X100), DQS PI = 4
7086 06:01:59.593094 [0] MIN Duty = 4876%(X100), DQS PI = 16
7087 06:01:59.596392 [0] AVG Duty = 4953%(X100)
7088 06:01:59.596908
7089 06:01:59.600242 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7090 06:01:59.600878
7091 06:01:59.603182 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7092 06:01:59.606385 [DutyScan_Calibration_Flow] ====Done====
7093 06:01:59.606855
7094 06:01:59.609477 [DutyScan_Calibration_Flow] k_type=3
7095 06:01:59.627136
7096 06:01:59.627700 ==DQM 0 ==
7097 06:01:59.630452 Final DQM duty delay cell = 0
7098 06:01:59.633748 [0] MAX Duty = 5187%(X100), DQS PI = 24
7099 06:01:59.637174 [0] MIN Duty = 4907%(X100), DQS PI = 42
7100 06:01:59.640519 [0] AVG Duty = 5047%(X100)
7101 06:01:59.641133
7102 06:01:59.641506 ==DQM 1 ==
7103 06:01:59.643473 Final DQM duty delay cell = 0
7104 06:01:59.646704 [0] MAX Duty = 5031%(X100), DQS PI = 4
7105 06:01:59.650443 [0] MIN Duty = 4782%(X100), DQS PI = 14
7106 06:01:59.653397 [0] AVG Duty = 4906%(X100)
7107 06:01:59.653862
7108 06:01:59.657193 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7109 06:01:59.657768
7110 06:01:59.660066 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7111 06:01:59.663208 [DutyScan_Calibration_Flow] ====Done====
7112 06:01:59.663690
7113 06:01:59.666685 [DutyScan_Calibration_Flow] k_type=2
7114 06:01:59.683583
7115 06:01:59.684152 ==DQ 0 ==
7116 06:01:59.686552 Final DQ duty delay cell = 0
7117 06:01:59.689941 [0] MAX Duty = 5218%(X100), DQS PI = 18
7118 06:01:59.693336 [0] MIN Duty = 4938%(X100), DQS PI = 56
7119 06:01:59.694051 [0] AVG Duty = 5078%(X100)
7120 06:01:59.696801
7121 06:01:59.697364 ==DQ 1 ==
7122 06:01:59.700172 Final DQ duty delay cell = -4
7123 06:01:59.703354 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7124 06:01:59.706856 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7125 06:01:59.709736 [-4] AVG Duty = 4969%(X100)
7126 06:01:59.710197
7127 06:01:59.712818 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7128 06:01:59.713279
7129 06:01:59.716172 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7130 06:01:59.719425 [DutyScan_Calibration_Flow] ====Done====
7131 06:01:59.719889 ==
7132 06:01:59.723007 Dram Type= 6, Freq= 0, CH_1, rank 0
7133 06:01:59.726355 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7134 06:01:59.726939 ==
7135 06:01:59.729315 [Duty_Offset_Calibration]
7136 06:01:59.729779 B0:0 B1:4 CA:-5
7137 06:01:59.732964
7138 06:01:59.736129 [DutyScan_Calibration_Flow] k_type=0
7139 06:01:59.744243
7140 06:01:59.744857 ==CLK 0==
7141 06:01:59.747576 Final CLK duty delay cell = 0
7142 06:01:59.751081 [0] MAX Duty = 5187%(X100), DQS PI = 22
7143 06:01:59.754272 [0] MIN Duty = 4906%(X100), DQS PI = 50
7144 06:01:59.757336 [0] AVG Duty = 5046%(X100)
7145 06:01:59.757904
7146 06:01:59.760688 CH1 CLK Duty spec in!! Max-Min= 281%
7147 06:01:59.763884 [DutyScan_Calibration_Flow] ====Done====
7148 06:01:59.764348
7149 06:01:59.767477 [DutyScan_Calibration_Flow] k_type=1
7150 06:01:59.783007
7151 06:01:59.783587 ==DQS 0 ==
7152 06:01:59.786138 Final DQS duty delay cell = 0
7153 06:01:59.789632 [0] MAX Duty = 5156%(X100), DQS PI = 18
7154 06:01:59.793053 [0] MIN Duty = 4876%(X100), DQS PI = 44
7155 06:01:59.796286 [0] AVG Duty = 5016%(X100)
7156 06:01:59.796892
7157 06:01:59.797275 ==DQS 1 ==
7158 06:01:59.799665 Final DQS duty delay cell = -4
7159 06:01:59.802647 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7160 06:01:59.805952 [-4] MIN Duty = 4875%(X100), DQS PI = 38
7161 06:01:59.809201 [-4] AVG Duty = 4937%(X100)
7162 06:01:59.809668
7163 06:01:59.812439 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7164 06:01:59.813005
7165 06:01:59.815943 CH1 DQS 1 Duty spec in!! Max-Min= 125%
7166 06:01:59.819535 [DutyScan_Calibration_Flow] ====Done====
7167 06:01:59.820109
7168 06:01:59.822821 [DutyScan_Calibration_Flow] k_type=3
7169 06:01:59.838911
7170 06:01:59.839555 ==DQM 0 ==
7171 06:01:59.841877 Final DQM duty delay cell = -4
7172 06:01:59.845112 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7173 06:01:59.848795 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7174 06:01:59.851655 [-4] AVG Duty = 4937%(X100)
7175 06:01:59.852167
7176 06:01:59.852663 ==DQM 1 ==
7177 06:01:59.855285 Final DQM duty delay cell = -4
7178 06:01:59.858409 [-4] MAX Duty = 5062%(X100), DQS PI = 14
7179 06:01:59.861744 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7180 06:01:59.864863 [-4] AVG Duty = 4984%(X100)
7181 06:01:59.865445
7182 06:01:59.868317 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7183 06:01:59.868957
7184 06:01:59.871754 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7185 06:01:59.874940 [DutyScan_Calibration_Flow] ====Done====
7186 06:01:59.875528
7187 06:01:59.878039 [DutyScan_Calibration_Flow] k_type=2
7188 06:01:59.896188
7189 06:01:59.896815 ==DQ 0 ==
7190 06:01:59.899436 Final DQ duty delay cell = 0
7191 06:01:59.902994 [0] MAX Duty = 5093%(X100), DQS PI = 20
7192 06:01:59.906077 [0] MIN Duty = 4969%(X100), DQS PI = 46
7193 06:01:59.906563 [0] AVG Duty = 5031%(X100)
7194 06:01:59.909367
7195 06:01:59.909845 ==DQ 1 ==
7196 06:01:59.912656 Final DQ duty delay cell = 0
7197 06:01:59.916142 [0] MAX Duty = 5031%(X100), DQS PI = 4
7198 06:01:59.919626 [0] MIN Duty = 4876%(X100), DQS PI = 28
7199 06:01:59.920245 [0] AVG Duty = 4953%(X100)
7200 06:01:59.922700
7201 06:01:59.925798 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7202 06:01:59.926282
7203 06:01:59.929300 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7204 06:01:59.932465 [DutyScan_Calibration_Flow] ====Done====
7205 06:01:59.936241 nWR fixed to 30
7206 06:01:59.936878 [ModeRegInit_LP4] CH0 RK0
7207 06:01:59.939459 [ModeRegInit_LP4] CH0 RK1
7208 06:01:59.942782 [ModeRegInit_LP4] CH1 RK0
7209 06:01:59.945814 [ModeRegInit_LP4] CH1 RK1
7210 06:01:59.946404 match AC timing 4
7211 06:01:59.952748 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7212 06:01:59.955722 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7213 06:01:59.959187 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7214 06:01:59.965638 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7215 06:01:59.969307 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7216 06:01:59.969892 [MiockJmeterHQA]
7217 06:01:59.970398
7218 06:01:59.972523 [DramcMiockJmeter] u1RxGatingPI = 0
7219 06:01:59.975813 0 : 4255, 4029
7220 06:01:59.976410 4 : 4255, 4029
7221 06:01:59.979177 8 : 4368, 4140
7222 06:01:59.979769 12 : 4258, 4029
7223 06:01:59.980275 16 : 4257, 4029
7224 06:01:59.982200 20 : 4363, 4137
7225 06:01:59.982689 24 : 4253, 4026
7226 06:01:59.985628 28 : 4252, 4027
7227 06:01:59.986221 32 : 4252, 4027
7228 06:01:59.989081 36 : 4253, 4026
7229 06:01:59.989680 40 : 4363, 4138
7230 06:01:59.992024 44 : 4253, 4026
7231 06:01:59.992512 48 : 4363, 4137
7232 06:01:59.993052 52 : 4252, 4027
7233 06:01:59.995629 56 : 4255, 4029
7234 06:01:59.996120 60 : 4250, 4027
7235 06:01:59.998694 64 : 4361, 4137
7236 06:01:59.999183 68 : 4250, 4026
7237 06:02:00.002215 72 : 4250, 4027
7238 06:02:00.002745 76 : 4250, 4027
7239 06:02:00.005290 80 : 4250, 4027
7240 06:02:00.005778 84 : 4250, 4027
7241 06:02:00.006271 88 : 4250, 4026
7242 06:02:00.008565 92 : 4360, 4138
7243 06:02:00.009094 96 : 4249, 4027
7244 06:02:00.011758 100 : 4361, 2505
7245 06:02:00.012245 104 : 4360, 0
7246 06:02:00.015368 108 : 4247, 0
7247 06:02:00.015964 112 : 4363, 0
7248 06:02:00.016465 116 : 4360, 0
7249 06:02:00.018561 120 : 4361, 0
7250 06:02:00.019049 124 : 4250, 0
7251 06:02:00.021909 128 : 4250, 0
7252 06:02:00.022550 132 : 4251, 0
7253 06:02:00.023050 136 : 4250, 0
7254 06:02:00.024944 140 : 4250, 0
7255 06:02:00.025442 144 : 4250, 0
7256 06:02:00.028398 148 : 4252, 0
7257 06:02:00.028924 152 : 4250, 0
7258 06:02:00.029422 156 : 4360, 0
7259 06:02:00.031604 160 : 4250, 0
7260 06:02:00.032096 164 : 4361, 0
7261 06:02:00.032589 168 : 4360, 0
7262 06:02:00.035087 172 : 4361, 0
7263 06:02:00.035692 176 : 4250, 0
7264 06:02:00.038140 180 : 4250, 0
7265 06:02:00.038629 184 : 4250, 0
7266 06:02:00.039122 188 : 4250, 0
7267 06:02:00.041252 192 : 4250, 0
7268 06:02:00.041746 196 : 4250, 0
7269 06:02:00.044747 200 : 4250, 0
7270 06:02:00.045345 204 : 4361, 0
7271 06:02:00.045845 208 : 4361, 0
7272 06:02:00.048224 212 : 4250, 0
7273 06:02:00.048866 216 : 4250, 0
7274 06:02:00.051575 220 : 4360, 664
7275 06:02:00.052167 224 : 4251, 3999
7276 06:02:00.054448 228 : 4250, 4027
7277 06:02:00.054989 232 : 4250, 4026
7278 06:02:00.058091 236 : 4250, 4027
7279 06:02:00.058686 240 : 4250, 4027
7280 06:02:00.059199 244 : 4250, 4026
7281 06:02:00.061130 248 : 4253, 4029
7282 06:02:00.061623 252 : 4360, 4138
7283 06:02:00.065277 256 : 4361, 4137
7284 06:02:00.065879 260 : 4248, 4024
7285 06:02:00.067747 264 : 4361, 4137
7286 06:02:00.068238 268 : 4361, 4138
7287 06:02:00.071004 272 : 4250, 4027
7288 06:02:00.071494 276 : 4250, 4026
7289 06:02:00.074688 280 : 4250, 4026
7290 06:02:00.075287 284 : 4250, 4027
7291 06:02:00.078112 288 : 4250, 4027
7292 06:02:00.078633 292 : 4250, 4027
7293 06:02:00.081566 296 : 4250, 4026
7294 06:02:00.082175 300 : 4250, 4027
7295 06:02:00.084372 304 : 4360, 4138
7296 06:02:00.084894 308 : 4361, 4137
7297 06:02:00.085393 312 : 4250, 4026
7298 06:02:00.087690 316 : 4361, 4137
7299 06:02:00.088177 320 : 4361, 4138
7300 06:02:00.091452 324 : 4250, 4027
7301 06:02:00.092046 328 : 4250, 4027
7302 06:02:00.094326 332 : 4250, 4026
7303 06:02:00.094816 336 : 4250, 3852
7304 06:02:00.097712 340 : 4250, 1909
7305 06:02:00.098200
7306 06:02:00.098689 MIOCK jitter meter ch=0
7307 06:02:00.100862
7308 06:02:00.101333 1T = (340-104) = 236 dly cells
7309 06:02:00.107597 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7310 06:02:00.108161 ==
7311 06:02:00.111013 Dram Type= 6, Freq= 0, CH_0, rank 0
7312 06:02:00.114138 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7313 06:02:00.114610 ==
7314 06:02:00.120895 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7315 06:02:00.124103 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7316 06:02:00.130603 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7317 06:02:00.133720 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7318 06:02:00.143901 [CA 0] Center 42 (12~73) winsize 62
7319 06:02:00.146917 [CA 1] Center 42 (12~73) winsize 62
7320 06:02:00.150325 [CA 2] Center 39 (9~69) winsize 61
7321 06:02:00.153623 [CA 3] Center 38 (9~68) winsize 60
7322 06:02:00.157031 [CA 4] Center 37 (7~67) winsize 61
7323 06:02:00.160264 [CA 5] Center 36 (6~66) winsize 61
7324 06:02:00.160853
7325 06:02:00.163295 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7326 06:02:00.163774
7327 06:02:00.166934 [CATrainingPosCal] consider 1 rank data
7328 06:02:00.169928 u2DelayCellTimex100 = 275/100 ps
7329 06:02:00.173492 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7330 06:02:00.180043 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7331 06:02:00.183118 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7332 06:02:00.186292 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7333 06:02:00.189635 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7334 06:02:00.193123 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7335 06:02:00.193592
7336 06:02:00.196206 CA PerBit enable=1, Macro0, CA PI delay=36
7337 06:02:00.196935
7338 06:02:00.199811 [CBTSetCACLKResult] CA Dly = 36
7339 06:02:00.202860 CS Dly: 10 (0~41)
7340 06:02:00.206327 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7341 06:02:00.209403 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7342 06:02:00.209869 ==
7343 06:02:00.212818 Dram Type= 6, Freq= 0, CH_0, rank 1
7344 06:02:00.219720 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7345 06:02:00.220294 ==
7346 06:02:00.223452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7347 06:02:00.229500 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7348 06:02:00.232651 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7349 06:02:00.239207 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7350 06:02:00.246137 [CA 0] Center 42 (12~73) winsize 62
7351 06:02:00.249488 [CA 1] Center 41 (11~72) winsize 62
7352 06:02:00.252818 [CA 2] Center 38 (8~68) winsize 61
7353 06:02:00.256362 [CA 3] Center 37 (7~67) winsize 61
7354 06:02:00.259609 [CA 4] Center 35 (5~65) winsize 61
7355 06:02:00.262636 [CA 5] Center 35 (5~66) winsize 62
7356 06:02:00.263106
7357 06:02:00.266310 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7358 06:02:00.266883
7359 06:02:00.269511 [CATrainingPosCal] consider 2 rank data
7360 06:02:00.272655 u2DelayCellTimex100 = 275/100 ps
7361 06:02:00.276143 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7362 06:02:00.282816 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7363 06:02:00.285814 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7364 06:02:00.289197 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7365 06:02:00.292938 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7366 06:02:00.296256 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7367 06:02:00.297180
7368 06:02:00.299456 CA PerBit enable=1, Macro0, CA PI delay=36
7369 06:02:00.299920
7370 06:02:00.302352 [CBTSetCACLKResult] CA Dly = 36
7371 06:02:00.305840 CS Dly: 11 (0~43)
7372 06:02:00.308997 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7373 06:02:00.312212 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7374 06:02:00.312672
7375 06:02:00.315659 ----->DramcWriteLeveling(PI) begin...
7376 06:02:00.316127 ==
7377 06:02:00.319028 Dram Type= 6, Freq= 0, CH_0, rank 0
7378 06:02:00.325380 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7379 06:02:00.325850 ==
7380 06:02:00.328899 Write leveling (Byte 0): 28 => 28
7381 06:02:00.329360 Write leveling (Byte 1): 25 => 25
7382 06:02:00.332168 DramcWriteLeveling(PI) end<-----
7383 06:02:00.332628
7384 06:02:00.335493 ==
7385 06:02:00.335954 Dram Type= 6, Freq= 0, CH_0, rank 0
7386 06:02:00.342404 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7387 06:02:00.342971 ==
7388 06:02:00.345499 [Gating] SW mode calibration
7389 06:02:00.352265 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7390 06:02:00.355464 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7391 06:02:00.362160 0 12 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7392 06:02:00.365377 0 12 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
7393 06:02:00.368959 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7394 06:02:00.375395 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7395 06:02:00.378638 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7396 06:02:00.382113 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7397 06:02:00.388485 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7398 06:02:00.391850 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7399 06:02:00.395281 0 13 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
7400 06:02:00.402002 0 13 4 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
7401 06:02:00.404856 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7402 06:02:00.408449 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7403 06:02:00.414809 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7404 06:02:00.418213 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7405 06:02:00.421676 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7406 06:02:00.428307 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7407 06:02:00.431446 0 14 0 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7408 06:02:00.434971 0 14 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7409 06:02:00.441638 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7410 06:02:00.445016 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7411 06:02:00.448459 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7412 06:02:00.454770 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7413 06:02:00.458030 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7414 06:02:00.461165 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7415 06:02:00.467726 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7416 06:02:00.471070 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7417 06:02:00.474519 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7418 06:02:00.481355 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7419 06:02:00.484610 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7420 06:02:00.487721 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7421 06:02:00.494552 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7422 06:02:00.497633 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7423 06:02:00.501219 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7424 06:02:00.507696 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7425 06:02:00.510936 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7426 06:02:00.513949 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7427 06:02:00.520974 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7428 06:02:00.524269 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7429 06:02:00.527251 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7430 06:02:00.534095 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7431 06:02:00.537648 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7432 06:02:00.540820 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7433 06:02:00.543981 Total UI for P1: 0, mck2ui 16
7434 06:02:00.547331 best dqsien dly found for B0: ( 1, 0, 30)
7435 06:02:00.550772 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7436 06:02:00.557280 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7437 06:02:00.560140 Total UI for P1: 0, mck2ui 16
7438 06:02:00.564007 best dqsien dly found for B1: ( 1, 1, 6)
7439 06:02:00.567214 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7440 06:02:00.570551 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7441 06:02:00.571016
7442 06:02:00.573642 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7443 06:02:00.577175 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7444 06:02:00.580355 [Gating] SW calibration Done
7445 06:02:00.580978 ==
7446 06:02:00.583906 Dram Type= 6, Freq= 0, CH_0, rank 0
7447 06:02:00.586999 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7448 06:02:00.587466 ==
7449 06:02:00.590498 RX Vref Scan: 0
7450 06:02:00.591067
7451 06:02:00.593362 RX Vref 0 -> 0, step: 1
7452 06:02:00.593825
7453 06:02:00.594184 RX Delay 0 -> 252, step: 8
7454 06:02:00.600141 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7455 06:02:00.603505 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7456 06:02:00.606966 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7457 06:02:00.610197 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7458 06:02:00.613360 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7459 06:02:00.620138 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7460 06:02:00.623750 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7461 06:02:00.626579 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
7462 06:02:00.630363 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7463 06:02:00.633259 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7464 06:02:00.639874 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7465 06:02:00.643055 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7466 06:02:00.646564 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7467 06:02:00.649750 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7468 06:02:00.652780 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7469 06:02:00.659865 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7470 06:02:00.660444 ==
7471 06:02:00.662860 Dram Type= 6, Freq= 0, CH_0, rank 0
7472 06:02:00.666260 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7473 06:02:00.666757 ==
7474 06:02:00.667131 DQS Delay:
7475 06:02:00.669689 DQS0 = 0, DQS1 = 0
7476 06:02:00.670260 DQM Delay:
7477 06:02:00.672811 DQM0 = 130, DQM1 = 124
7478 06:02:00.673381 DQ Delay:
7479 06:02:00.675932 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7480 06:02:00.679513 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7481 06:02:00.683030 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7482 06:02:00.686019 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7483 06:02:00.689500
7484 06:02:00.689964
7485 06:02:00.690331 ==
7486 06:02:00.692859 Dram Type= 6, Freq= 0, CH_0, rank 0
7487 06:02:00.696015 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7488 06:02:00.696486 ==
7489 06:02:00.696908
7490 06:02:00.697258
7491 06:02:00.699608 TX Vref Scan disable
7492 06:02:00.700268 == TX Byte 0 ==
7493 06:02:00.705841 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7494 06:02:00.708791 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7495 06:02:00.709282 == TX Byte 1 ==
7496 06:02:00.715733 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7497 06:02:00.718872 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7498 06:02:00.719335 ==
7499 06:02:00.722167 Dram Type= 6, Freq= 0, CH_0, rank 0
7500 06:02:00.725458 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7501 06:02:00.725922 ==
7502 06:02:00.739531
7503 06:02:00.742737 TX Vref early break, caculate TX vref
7504 06:02:00.746104 TX Vref=16, minBit 8, minWin=22, winSum=371
7505 06:02:00.748969 TX Vref=18, minBit 10, minWin=22, winSum=380
7506 06:02:00.752598 TX Vref=20, minBit 10, minWin=22, winSum=388
7507 06:02:00.755833 TX Vref=22, minBit 10, minWin=23, winSum=397
7508 06:02:00.762555 TX Vref=24, minBit 8, minWin=24, winSum=409
7509 06:02:00.765519 TX Vref=26, minBit 8, minWin=24, winSum=413
7510 06:02:00.769160 TX Vref=28, minBit 8, minWin=25, winSum=417
7511 06:02:00.772455 TX Vref=30, minBit 6, minWin=24, winSum=408
7512 06:02:00.775401 TX Vref=32, minBit 0, minWin=24, winSum=400
7513 06:02:00.778810 TX Vref=34, minBit 8, minWin=23, winSum=391
7514 06:02:00.785580 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28
7515 06:02:00.786141
7516 06:02:00.788646 Final TX Range 0 Vref 28
7517 06:02:00.789137
7518 06:02:00.789499 ==
7519 06:02:00.792404 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 06:02:00.795495 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7521 06:02:00.796058 ==
7522 06:02:00.796426
7523 06:02:00.796805
7524 06:02:00.798439 TX Vref Scan disable
7525 06:02:00.805024 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7526 06:02:00.805486 == TX Byte 0 ==
7527 06:02:00.808340 u2DelayCellOfst[0]=14 cells (4 PI)
7528 06:02:00.811849 u2DelayCellOfst[1]=17 cells (5 PI)
7529 06:02:00.814991 u2DelayCellOfst[2]=14 cells (4 PI)
7530 06:02:00.818263 u2DelayCellOfst[3]=10 cells (3 PI)
7531 06:02:00.821527 u2DelayCellOfst[4]=10 cells (3 PI)
7532 06:02:00.824835 u2DelayCellOfst[5]=0 cells (0 PI)
7533 06:02:00.828231 u2DelayCellOfst[6]=17 cells (5 PI)
7534 06:02:00.831403 u2DelayCellOfst[7]=17 cells (5 PI)
7535 06:02:00.835109 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7536 06:02:00.838383 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7537 06:02:00.841676 == TX Byte 1 ==
7538 06:02:00.844851 u2DelayCellOfst[8]=0 cells (0 PI)
7539 06:02:00.848159 u2DelayCellOfst[9]=0 cells (0 PI)
7540 06:02:00.851498 u2DelayCellOfst[10]=7 cells (2 PI)
7541 06:02:00.854899 u2DelayCellOfst[11]=0 cells (0 PI)
7542 06:02:00.858301 u2DelayCellOfst[12]=10 cells (3 PI)
7543 06:02:00.858860 u2DelayCellOfst[13]=10 cells (3 PI)
7544 06:02:00.861310 u2DelayCellOfst[14]=14 cells (4 PI)
7545 06:02:00.864819 u2DelayCellOfst[15]=10 cells (3 PI)
7546 06:02:00.871517 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7547 06:02:00.874528 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7548 06:02:00.874995 DramC Write-DBI on
7549 06:02:00.877832 ==
7550 06:02:00.881331 Dram Type= 6, Freq= 0, CH_0, rank 0
7551 06:02:00.884862 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7552 06:02:00.885499 ==
7553 06:02:00.885875
7554 06:02:00.886213
7555 06:02:00.887557 TX Vref Scan disable
7556 06:02:00.888057 == TX Byte 0 ==
7557 06:02:00.894270 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7558 06:02:00.894830 == TX Byte 1 ==
7559 06:02:00.897627 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7560 06:02:00.900762 DramC Write-DBI off
7561 06:02:00.901232
7562 06:02:00.901592 [DATLAT]
7563 06:02:00.904004 Freq=1600, CH0 RK0
7564 06:02:00.904571
7565 06:02:00.905001 DATLAT Default: 0xf
7566 06:02:00.907290 0, 0xFFFF, sum = 0
7567 06:02:00.907762 1, 0xFFFF, sum = 0
7568 06:02:00.910911 2, 0xFFFF, sum = 0
7569 06:02:00.913855 3, 0xFFFF, sum = 0
7570 06:02:00.914326 4, 0xFFFF, sum = 0
7571 06:02:00.917143 5, 0xFFFF, sum = 0
7572 06:02:00.917610 6, 0xFFFF, sum = 0
7573 06:02:00.921079 7, 0xFFFF, sum = 0
7574 06:02:00.921652 8, 0xFFFF, sum = 0
7575 06:02:00.924009 9, 0xFFFF, sum = 0
7576 06:02:00.924589 10, 0xFFFF, sum = 0
7577 06:02:00.927166 11, 0xFFFF, sum = 0
7578 06:02:00.927689 12, 0x8FFF, sum = 0
7579 06:02:00.930573 13, 0x0, sum = 1
7580 06:02:00.931153 14, 0x0, sum = 2
7581 06:02:00.933306 15, 0x0, sum = 3
7582 06:02:00.933774 16, 0x0, sum = 4
7583 06:02:00.936949 best_step = 14
7584 06:02:00.937423
7585 06:02:00.937785 ==
7586 06:02:00.940256 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 06:02:00.943433 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7588 06:02:00.943997 ==
7589 06:02:00.946691 RX Vref Scan: 1
7590 06:02:00.947316
7591 06:02:00.947914 Set Vref Range= 24 -> 127
7592 06:02:00.948428
7593 06:02:00.950062 RX Vref 24 -> 127, step: 1
7594 06:02:00.950523
7595 06:02:00.953521 RX Delay 11 -> 252, step: 4
7596 06:02:00.954067
7597 06:02:00.956781 Set Vref, RX VrefLevel [Byte0]: 24
7598 06:02:00.959782 [Byte1]: 24
7599 06:02:00.960233
7600 06:02:00.963395 Set Vref, RX VrefLevel [Byte0]: 25
7601 06:02:00.966598 [Byte1]: 25
7602 06:02:00.970461
7603 06:02:00.971014 Set Vref, RX VrefLevel [Byte0]: 26
7604 06:02:00.973506 [Byte1]: 26
7605 06:02:00.977650
7606 06:02:00.978212 Set Vref, RX VrefLevel [Byte0]: 27
7607 06:02:00.980929 [Byte1]: 27
7608 06:02:00.985441
7609 06:02:00.986003 Set Vref, RX VrefLevel [Byte0]: 28
7610 06:02:00.988529 [Byte1]: 28
7611 06:02:00.993072
7612 06:02:00.993632 Set Vref, RX VrefLevel [Byte0]: 29
7613 06:02:00.996664 [Byte1]: 29
7614 06:02:01.000799
7615 06:02:01.001602 Set Vref, RX VrefLevel [Byte0]: 30
7616 06:02:01.003720 [Byte1]: 30
7617 06:02:01.008205
7618 06:02:01.008840 Set Vref, RX VrefLevel [Byte0]: 31
7619 06:02:01.011872 [Byte1]: 31
7620 06:02:01.015791
7621 06:02:01.016443 Set Vref, RX VrefLevel [Byte0]: 32
7622 06:02:01.018826 [Byte1]: 32
7623 06:02:01.023338
7624 06:02:01.023905 Set Vref, RX VrefLevel [Byte0]: 33
7625 06:02:01.027169 [Byte1]: 33
7626 06:02:01.031288
7627 06:02:01.031855 Set Vref, RX VrefLevel [Byte0]: 34
7628 06:02:01.034573 [Byte1]: 34
7629 06:02:01.038722
7630 06:02:01.039285 Set Vref, RX VrefLevel [Byte0]: 35
7631 06:02:01.041723 [Byte1]: 35
7632 06:02:01.045945
7633 06:02:01.046496 Set Vref, RX VrefLevel [Byte0]: 36
7634 06:02:01.049284 [Byte1]: 36
7635 06:02:01.053643
7636 06:02:01.054206 Set Vref, RX VrefLevel [Byte0]: 37
7637 06:02:01.057007 [Byte1]: 37
7638 06:02:01.061309
7639 06:02:01.061767 Set Vref, RX VrefLevel [Byte0]: 38
7640 06:02:01.064552 [Byte1]: 38
7641 06:02:01.069305
7642 06:02:01.069868 Set Vref, RX VrefLevel [Byte0]: 39
7643 06:02:01.072232 [Byte1]: 39
7644 06:02:01.076864
7645 06:02:01.077432 Set Vref, RX VrefLevel [Byte0]: 40
7646 06:02:01.079826 [Byte1]: 40
7647 06:02:01.084406
7648 06:02:01.085028 Set Vref, RX VrefLevel [Byte0]: 41
7649 06:02:01.087734 [Byte1]: 41
7650 06:02:01.091833
7651 06:02:01.092385 Set Vref, RX VrefLevel [Byte0]: 42
7652 06:02:01.095088 [Byte1]: 42
7653 06:02:01.099368
7654 06:02:01.099926 Set Vref, RX VrefLevel [Byte0]: 43
7655 06:02:01.102906 [Byte1]: 43
7656 06:02:01.107245
7657 06:02:01.107801 Set Vref, RX VrefLevel [Byte0]: 44
7658 06:02:01.110189 [Byte1]: 44
7659 06:02:01.114536
7660 06:02:01.115035 Set Vref, RX VrefLevel [Byte0]: 45
7661 06:02:01.117985 [Byte1]: 45
7662 06:02:01.122475
7663 06:02:01.123188 Set Vref, RX VrefLevel [Byte0]: 46
7664 06:02:01.125347 [Byte1]: 46
7665 06:02:01.129715
7666 06:02:01.130179 Set Vref, RX VrefLevel [Byte0]: 47
7667 06:02:01.133157 [Byte1]: 47
7668 06:02:01.137627
7669 06:02:01.138189 Set Vref, RX VrefLevel [Byte0]: 48
7670 06:02:01.141103 [Byte1]: 48
7671 06:02:01.145105
7672 06:02:01.145665 Set Vref, RX VrefLevel [Byte0]: 49
7673 06:02:01.148641 [Byte1]: 49
7674 06:02:01.152930
7675 06:02:01.153490 Set Vref, RX VrefLevel [Byte0]: 50
7676 06:02:01.156107 [Byte1]: 50
7677 06:02:01.160529
7678 06:02:01.161159 Set Vref, RX VrefLevel [Byte0]: 51
7679 06:02:01.163856 [Byte1]: 51
7680 06:02:01.168053
7681 06:02:01.168619 Set Vref, RX VrefLevel [Byte0]: 52
7682 06:02:01.171334 [Byte1]: 52
7683 06:02:01.175558
7684 06:02:01.176016 Set Vref, RX VrefLevel [Byte0]: 53
7685 06:02:01.179141 [Byte1]: 53
7686 06:02:01.183358
7687 06:02:01.183926 Set Vref, RX VrefLevel [Byte0]: 54
7688 06:02:01.186428 [Byte1]: 54
7689 06:02:01.190953
7690 06:02:01.191508 Set Vref, RX VrefLevel [Byte0]: 55
7691 06:02:01.194160 [Byte1]: 55
7692 06:02:01.198442
7693 06:02:01.199009 Set Vref, RX VrefLevel [Byte0]: 56
7694 06:02:01.201717 [Byte1]: 56
7695 06:02:01.206125
7696 06:02:01.206595 Set Vref, RX VrefLevel [Byte0]: 57
7697 06:02:01.209222 [Byte1]: 57
7698 06:02:01.213623
7699 06:02:01.214076 Set Vref, RX VrefLevel [Byte0]: 58
7700 06:02:01.216654 [Byte1]: 58
7701 06:02:01.221073
7702 06:02:01.221482 Set Vref, RX VrefLevel [Byte0]: 59
7703 06:02:01.224798 [Byte1]: 59
7704 06:02:01.229198
7705 06:02:01.229653 Set Vref, RX VrefLevel [Byte0]: 60
7706 06:02:01.232338 [Byte1]: 60
7707 06:02:01.236619
7708 06:02:01.237366 Set Vref, RX VrefLevel [Byte0]: 61
7709 06:02:01.240037 [Byte1]: 61
7710 06:02:01.244234
7711 06:02:01.244838 Set Vref, RX VrefLevel [Byte0]: 62
7712 06:02:01.247206 [Byte1]: 62
7713 06:02:01.251534
7714 06:02:01.252091 Set Vref, RX VrefLevel [Byte0]: 63
7715 06:02:01.254849 [Byte1]: 63
7716 06:02:01.259634
7717 06:02:01.260191 Set Vref, RX VrefLevel [Byte0]: 64
7718 06:02:01.262653 [Byte1]: 64
7719 06:02:01.267112
7720 06:02:01.267672 Set Vref, RX VrefLevel [Byte0]: 65
7721 06:02:01.270385 [Byte1]: 65
7722 06:02:01.274526
7723 06:02:01.275086 Set Vref, RX VrefLevel [Byte0]: 66
7724 06:02:01.277925 [Byte1]: 66
7725 06:02:01.282109
7726 06:02:01.282667 Set Vref, RX VrefLevel [Byte0]: 67
7727 06:02:01.285412 [Byte1]: 67
7728 06:02:01.289923
7729 06:02:01.290480 Set Vref, RX VrefLevel [Byte0]: 68
7730 06:02:01.293360 [Byte1]: 68
7731 06:02:01.297464
7732 06:02:01.298021 Set Vref, RX VrefLevel [Byte0]: 69
7733 06:02:01.300730 [Byte1]: 69
7734 06:02:01.305016
7735 06:02:01.305480 Set Vref, RX VrefLevel [Byte0]: 70
7736 06:02:01.308499 [Byte1]: 70
7737 06:02:01.312983
7738 06:02:01.313556 Final RX Vref Byte 0 = 53 to rank0
7739 06:02:01.315751 Final RX Vref Byte 1 = 56 to rank0
7740 06:02:01.319231 Final RX Vref Byte 0 = 53 to rank1
7741 06:02:01.322461 Final RX Vref Byte 1 = 56 to rank1==
7742 06:02:01.325824 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 06:02:01.332351 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7744 06:02:01.332895 ==
7745 06:02:01.333284 DQS Delay:
7746 06:02:01.333623 DQS0 = 0, DQS1 = 0
7747 06:02:01.335793 DQM Delay:
7748 06:02:01.336246 DQM0 = 126, DQM1 = 120
7749 06:02:01.339277 DQ Delay:
7750 06:02:01.342499 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7751 06:02:01.346003 DQ4 =130, DQ5 =116, DQ6 =136, DQ7 =134
7752 06:02:01.348972 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7753 06:02:01.352516 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7754 06:02:01.353161
7755 06:02:01.353608
7756 06:02:01.353953
7757 06:02:01.355794 [DramC_TX_OE_Calibration] TA2
7758 06:02:01.358842 Original DQ_B0 (3 6) =30, OEN = 27
7759 06:02:01.362413 Original DQ_B1 (3 6) =30, OEN = 27
7760 06:02:01.365538 24, 0x0, End_B0=24 End_B1=24
7761 06:02:01.366105 25, 0x0, End_B0=25 End_B1=25
7762 06:02:01.368870 26, 0x0, End_B0=26 End_B1=26
7763 06:02:01.372213 27, 0x0, End_B0=27 End_B1=27
7764 06:02:01.375573 28, 0x0, End_B0=28 End_B1=28
7765 06:02:01.378949 29, 0x0, End_B0=29 End_B1=29
7766 06:02:01.379524 30, 0x0, End_B0=30 End_B1=30
7767 06:02:01.382232 31, 0x4141, End_B0=30 End_B1=30
7768 06:02:01.385513 Byte0 end_step=30 best_step=27
7769 06:02:01.388812 Byte1 end_step=30 best_step=27
7770 06:02:01.392144 Byte0 TX OE(2T, 0.5T) = (3, 3)
7771 06:02:01.395321 Byte1 TX OE(2T, 0.5T) = (3, 3)
7772 06:02:01.395883
7773 06:02:01.396243
7774 06:02:01.401859 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7775 06:02:01.405151 CH0 RK0: MR19=303, MR18=1D1D
7776 06:02:01.412020 CH0_RK0: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
7777 06:02:01.412585
7778 06:02:01.415464 ----->DramcWriteLeveling(PI) begin...
7779 06:02:01.416047 ==
7780 06:02:01.418548 Dram Type= 6, Freq= 0, CH_0, rank 1
7781 06:02:01.421629 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7782 06:02:01.422092 ==
7783 06:02:01.425072 Write leveling (Byte 0): 28 => 28
7784 06:02:01.428675 Write leveling (Byte 1): 26 => 26
7785 06:02:01.432050 DramcWriteLeveling(PI) end<-----
7786 06:02:01.432609
7787 06:02:01.433034 ==
7788 06:02:01.435168 Dram Type= 6, Freq= 0, CH_0, rank 1
7789 06:02:01.438364 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7790 06:02:01.438931 ==
7791 06:02:01.441530 [Gating] SW mode calibration
7792 06:02:01.448452 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7793 06:02:01.454933 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7794 06:02:01.458267 0 12 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7795 06:02:01.464895 0 12 4 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
7796 06:02:01.468017 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7797 06:02:01.471714 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7798 06:02:01.478006 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7799 06:02:01.481351 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7800 06:02:01.484762 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7801 06:02:01.491437 0 12 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7802 06:02:01.494373 0 13 0 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
7803 06:02:01.497652 0 13 4 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7804 06:02:01.504090 0 13 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7805 06:02:01.507559 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7806 06:02:01.510883 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7807 06:02:01.517492 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7808 06:02:01.520986 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7809 06:02:01.524259 0 13 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7810 06:02:01.530489 0 14 0 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7811 06:02:01.533941 0 14 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7812 06:02:01.537108 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7813 06:02:01.543768 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7814 06:02:01.546854 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7815 06:02:01.550232 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7816 06:02:01.556903 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7817 06:02:01.560475 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7818 06:02:01.563579 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7819 06:02:01.570295 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7820 06:02:01.573674 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7821 06:02:01.576662 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 06:02:01.583499 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 06:02:01.586416 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 06:02:01.589998 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 06:02:01.596273 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7826 06:02:01.599920 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7827 06:02:01.603218 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7828 06:02:01.609955 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7829 06:02:01.612930 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7830 06:02:01.616527 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7831 06:02:01.623188 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7832 06:02:01.626077 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7833 06:02:01.629256 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7834 06:02:01.636174 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7835 06:02:01.639687 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7836 06:02:01.642945 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7837 06:02:01.646196 Total UI for P1: 0, mck2ui 16
7838 06:02:01.649301 best dqsien dly found for B0: ( 1, 1, 0)
7839 06:02:01.652666 Total UI for P1: 0, mck2ui 16
7840 06:02:01.655970 best dqsien dly found for B1: ( 1, 1, 2)
7841 06:02:01.659291 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7842 06:02:01.662536 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7843 06:02:01.663020
7844 06:02:01.665826 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7845 06:02:01.672810 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7846 06:02:01.673480 [Gating] SW calibration Done
7847 06:02:01.673916 ==
7848 06:02:01.675945 Dram Type= 6, Freq= 0, CH_0, rank 1
7849 06:02:01.682301 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7850 06:02:01.682765 ==
7851 06:02:01.683153 RX Vref Scan: 0
7852 06:02:01.683492
7853 06:02:01.685853 RX Vref 0 -> 0, step: 1
7854 06:02:01.686310
7855 06:02:01.688853 RX Delay 0 -> 252, step: 8
7856 06:02:01.692520 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7857 06:02:01.695624 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7858 06:02:01.698671 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7859 06:02:01.705419 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7860 06:02:01.709096 iDelay=200, Bit 4, Center 135 (72 ~ 199) 128
7861 06:02:01.712364 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7862 06:02:01.715327 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7863 06:02:01.718674 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7864 06:02:01.725706 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7865 06:02:01.728764 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7866 06:02:01.731884 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7867 06:02:01.735292 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7868 06:02:01.738419 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7869 06:02:01.745174 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7870 06:02:01.748405 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7871 06:02:01.752340 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7872 06:02:01.752948 ==
7873 06:02:01.754826 Dram Type= 6, Freq= 0, CH_0, rank 1
7874 06:02:01.758115 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7875 06:02:01.761705 ==
7876 06:02:01.762318 DQS Delay:
7877 06:02:01.762691 DQS0 = 0, DQS1 = 0
7878 06:02:01.764671 DQM Delay:
7879 06:02:01.765160 DQM0 = 130, DQM1 = 124
7880 06:02:01.767861 DQ Delay:
7881 06:02:01.771670 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7882 06:02:01.774598 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7883 06:02:01.777979 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7884 06:02:01.781661 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7885 06:02:01.782223
7886 06:02:01.782589
7887 06:02:01.782927 ==
7888 06:02:01.784536 Dram Type= 6, Freq= 0, CH_0, rank 1
7889 06:02:01.788123 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7890 06:02:01.788582 ==
7891 06:02:01.791267
7892 06:02:01.791720
7893 06:02:01.792075 TX Vref Scan disable
7894 06:02:01.794510 == TX Byte 0 ==
7895 06:02:01.797992 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7896 06:02:01.801106 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7897 06:02:01.804495 == TX Byte 1 ==
7898 06:02:01.807729 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7899 06:02:01.811051 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7900 06:02:01.811536 ==
7901 06:02:01.814549 Dram Type= 6, Freq= 0, CH_0, rank 1
7902 06:02:01.820822 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7903 06:02:01.821288 ==
7904 06:02:01.834024
7905 06:02:01.837081 TX Vref early break, caculate TX vref
7906 06:02:01.840661 TX Vref=16, minBit 11, minWin=22, winSum=375
7907 06:02:01.844003 TX Vref=18, minBit 1, minWin=22, winSum=386
7908 06:02:01.847227 TX Vref=20, minBit 8, minWin=23, winSum=394
7909 06:02:01.850329 TX Vref=22, minBit 9, minWin=23, winSum=395
7910 06:02:01.853630 TX Vref=24, minBit 8, minWin=24, winSum=410
7911 06:02:01.860645 TX Vref=26, minBit 11, minWin=24, winSum=412
7912 06:02:01.863825 TX Vref=28, minBit 8, minWin=24, winSum=414
7913 06:02:01.867197 TX Vref=30, minBit 8, minWin=24, winSum=412
7914 06:02:01.870344 TX Vref=32, minBit 1, minWin=24, winSum=403
7915 06:02:01.873413 TX Vref=34, minBit 8, minWin=22, winSum=395
7916 06:02:01.877573 TX Vref=36, minBit 8, minWin=22, winSum=387
7917 06:02:01.883956 [TxChooseVref] Worse bit 8, Min win 24, Win sum 414, Final Vref 28
7918 06:02:01.884520
7919 06:02:01.887011 Final TX Range 0 Vref 28
7920 06:02:01.887583
7921 06:02:01.887946 ==
7922 06:02:01.890036 Dram Type= 6, Freq= 0, CH_0, rank 1
7923 06:02:01.893644 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7924 06:02:01.894289 ==
7925 06:02:01.897047
7926 06:02:01.897601
7927 06:02:01.897964 TX Vref Scan disable
7928 06:02:01.903705 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7929 06:02:01.904271 == TX Byte 0 ==
7930 06:02:01.907377 u2DelayCellOfst[0]=14 cells (4 PI)
7931 06:02:01.910007 u2DelayCellOfst[1]=21 cells (6 PI)
7932 06:02:01.913086 u2DelayCellOfst[2]=14 cells (4 PI)
7933 06:02:01.916767 u2DelayCellOfst[3]=14 cells (4 PI)
7934 06:02:01.919849 u2DelayCellOfst[4]=10 cells (3 PI)
7935 06:02:01.923340 u2DelayCellOfst[5]=0 cells (0 PI)
7936 06:02:01.926548 u2DelayCellOfst[6]=17 cells (5 PI)
7937 06:02:01.929980 u2DelayCellOfst[7]=17 cells (5 PI)
7938 06:02:01.933314 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7939 06:02:01.936592 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7940 06:02:01.939605 == TX Byte 1 ==
7941 06:02:01.943193 u2DelayCellOfst[8]=0 cells (0 PI)
7942 06:02:01.946270 u2DelayCellOfst[9]=0 cells (0 PI)
7943 06:02:01.949636 u2DelayCellOfst[10]=10 cells (3 PI)
7944 06:02:01.953215 u2DelayCellOfst[11]=3 cells (1 PI)
7945 06:02:01.956619 u2DelayCellOfst[12]=14 cells (4 PI)
7946 06:02:01.960066 u2DelayCellOfst[13]=14 cells (4 PI)
7947 06:02:01.962921 u2DelayCellOfst[14]=17 cells (5 PI)
7948 06:02:01.963477 u2DelayCellOfst[15]=14 cells (4 PI)
7949 06:02:01.969665 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7950 06:02:01.973383 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7951 06:02:01.976287 DramC Write-DBI on
7952 06:02:01.976899 ==
7953 06:02:01.979513 Dram Type= 6, Freq= 0, CH_0, rank 1
7954 06:02:01.982733 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7955 06:02:01.983296 ==
7956 06:02:01.983662
7957 06:02:01.983996
7958 06:02:01.986120 TX Vref Scan disable
7959 06:02:01.986677 == TX Byte 0 ==
7960 06:02:01.992668 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7961 06:02:01.993280 == TX Byte 1 ==
7962 06:02:01.996083 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7963 06:02:01.999344 DramC Write-DBI off
7964 06:02:01.999905
7965 06:02:02.000268 [DATLAT]
7966 06:02:02.002701 Freq=1600, CH0 RK1
7967 06:02:02.003287
7968 06:02:02.003653 DATLAT Default: 0xe
7969 06:02:02.005753 0, 0xFFFF, sum = 0
7970 06:02:02.006219 1, 0xFFFF, sum = 0
7971 06:02:02.009151 2, 0xFFFF, sum = 0
7972 06:02:02.009661 3, 0xFFFF, sum = 0
7973 06:02:02.012572 4, 0xFFFF, sum = 0
7974 06:02:02.016064 5, 0xFFFF, sum = 0
7975 06:02:02.016629 6, 0xFFFF, sum = 0
7976 06:02:02.019235 7, 0xFFFF, sum = 0
7977 06:02:02.019823 8, 0xFFFF, sum = 0
7978 06:02:02.022384 9, 0xFFFF, sum = 0
7979 06:02:02.022850 10, 0xFFFF, sum = 0
7980 06:02:02.025741 11, 0xFFFF, sum = 0
7981 06:02:02.026210 12, 0x8FFF, sum = 0
7982 06:02:02.028935 13, 0x0, sum = 1
7983 06:02:02.029401 14, 0x0, sum = 2
7984 06:02:02.032257 15, 0x0, sum = 3
7985 06:02:02.032879 16, 0x0, sum = 4
7986 06:02:02.035464 best_step = 14
7987 06:02:02.035918
7988 06:02:02.036275 ==
7989 06:02:02.038876 Dram Type= 6, Freq= 0, CH_0, rank 1
7990 06:02:02.042278 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7991 06:02:02.042845 ==
7992 06:02:02.045442 RX Vref Scan: 0
7993 06:02:02.046009
7994 06:02:02.046372 RX Vref 0 -> 0, step: 1
7995 06:02:02.046712
7996 06:02:02.048776 RX Delay 11 -> 252, step: 4
7997 06:02:02.051932 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7998 06:02:02.058318 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7999 06:02:02.061958 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
8000 06:02:02.065601 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8001 06:02:02.068441 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8002 06:02:02.071635 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
8003 06:02:02.078427 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
8004 06:02:02.081981 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
8005 06:02:02.085270 iDelay=195, Bit 8, Center 106 (51 ~ 162) 112
8006 06:02:02.088977 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
8007 06:02:02.092166 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8008 06:02:02.098503 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8009 06:02:02.101634 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8010 06:02:02.105363 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
8011 06:02:02.108205 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8012 06:02:02.115136 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8013 06:02:02.115679 ==
8014 06:02:02.118111 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 06:02:02.121663 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8016 06:02:02.122222 ==
8017 06:02:02.122592 DQS Delay:
8018 06:02:02.124571 DQS0 = 0, DQS1 = 0
8019 06:02:02.125098 DQM Delay:
8020 06:02:02.128019 DQM0 = 127, DQM1 = 120
8021 06:02:02.128618 DQ Delay:
8022 06:02:02.131438 DQ0 =122, DQ1 =130, DQ2 =126, DQ3 =122
8023 06:02:02.134518 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
8024 06:02:02.137921 DQ8 =106, DQ9 =106, DQ10 =122, DQ11 =112
8025 06:02:02.141104 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
8026 06:02:02.141566
8027 06:02:02.144748
8028 06:02:02.145310
8029 06:02:02.145676 [DramC_TX_OE_Calibration] TA2
8030 06:02:02.147869 Original DQ_B0 (3 6) =30, OEN = 27
8031 06:02:02.151046 Original DQ_B1 (3 6) =30, OEN = 27
8032 06:02:02.154442 24, 0x0, End_B0=24 End_B1=24
8033 06:02:02.157845 25, 0x0, End_B0=25 End_B1=25
8034 06:02:02.161535 26, 0x0, End_B0=26 End_B1=26
8035 06:02:02.162104 27, 0x0, End_B0=27 End_B1=27
8036 06:02:02.164539 28, 0x0, End_B0=28 End_B1=28
8037 06:02:02.167685 29, 0x0, End_B0=29 End_B1=29
8038 06:02:02.170998 30, 0x0, End_B0=30 End_B1=30
8039 06:02:02.174120 31, 0x5151, End_B0=30 End_B1=30
8040 06:02:02.174688 Byte0 end_step=30 best_step=27
8041 06:02:02.177361 Byte1 end_step=30 best_step=27
8042 06:02:02.180876 Byte0 TX OE(2T, 0.5T) = (3, 3)
8043 06:02:02.184056 Byte1 TX OE(2T, 0.5T) = (3, 3)
8044 06:02:02.184518
8045 06:02:02.184935
8046 06:02:02.194022 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8047 06:02:02.194491 CH0 RK1: MR19=303, MR18=2222
8048 06:02:02.200689 CH0_RK1: MR19=0x303, MR18=0x2222, DQSOSC=392, MR23=63, INC=24, DEC=16
8049 06:02:02.204220 [RxdqsGatingPostProcess] freq 1600
8050 06:02:02.210629 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8051 06:02:02.213817 Pre-setting of DQS Precalculation
8052 06:02:02.217346 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8053 06:02:02.217907 ==
8054 06:02:02.220210 Dram Type= 6, Freq= 0, CH_1, rank 0
8055 06:02:02.227054 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8056 06:02:02.227617 ==
8057 06:02:02.229986 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8058 06:02:02.237101 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8059 06:02:02.240139 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8060 06:02:02.247062 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8061 06:02:02.254093 [CA 0] Center 41 (11~71) winsize 61
8062 06:02:02.256668 [CA 1] Center 41 (11~72) winsize 62
8063 06:02:02.260193 [CA 2] Center 37 (8~67) winsize 60
8064 06:02:02.263167 [CA 3] Center 36 (7~66) winsize 60
8065 06:02:02.266572 [CA 4] Center 34 (4~64) winsize 61
8066 06:02:02.270516 [CA 5] Center 34 (5~64) winsize 60
8067 06:02:02.270979
8068 06:02:02.273419 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8069 06:02:02.273977
8070 06:02:02.280180 [CATrainingPosCal] consider 1 rank data
8071 06:02:02.280768 u2DelayCellTimex100 = 275/100 ps
8072 06:02:02.286657 CA0 delay=41 (11~71),Diff = 7 PI (24 cell)
8073 06:02:02.289915 CA1 delay=41 (11~72),Diff = 7 PI (24 cell)
8074 06:02:02.292865 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8075 06:02:02.296795 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8076 06:02:02.299882 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8077 06:02:02.303319 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8078 06:02:02.303882
8079 06:02:02.306188 CA PerBit enable=1, Macro0, CA PI delay=34
8080 06:02:02.306650
8081 06:02:02.309795 [CBTSetCACLKResult] CA Dly = 34
8082 06:02:02.312908 CS Dly: 8 (0~39)
8083 06:02:02.316523 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8084 06:02:02.319481 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8085 06:02:02.319950 ==
8086 06:02:02.322807 Dram Type= 6, Freq= 0, CH_1, rank 1
8087 06:02:02.329347 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8088 06:02:02.329926 ==
8089 06:02:02.332518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8090 06:02:02.339279 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8091 06:02:02.342532 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8092 06:02:02.349182 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8093 06:02:02.356226 [CA 0] Center 41 (11~71) winsize 61
8094 06:02:02.359584 [CA 1] Center 41 (11~71) winsize 61
8095 06:02:02.362590 [CA 2] Center 36 (7~66) winsize 60
8096 06:02:02.365862 [CA 3] Center 35 (6~65) winsize 60
8097 06:02:02.369171 [CA 4] Center 34 (5~64) winsize 60
8098 06:02:02.372553 [CA 5] Center 34 (5~64) winsize 60
8099 06:02:02.373178
8100 06:02:02.376075 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8101 06:02:02.376637
8102 06:02:02.379073 [CATrainingPosCal] consider 2 rank data
8103 06:02:02.382428 u2DelayCellTimex100 = 275/100 ps
8104 06:02:02.389097 CA0 delay=41 (11~71),Diff = 7 PI (24 cell)
8105 06:02:02.392084 CA1 delay=41 (11~71),Diff = 7 PI (24 cell)
8106 06:02:02.395531 CA2 delay=37 (8~66),Diff = 3 PI (10 cell)
8107 06:02:02.398903 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8108 06:02:02.402277 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8109 06:02:02.405212 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8110 06:02:02.405677
8111 06:02:02.408803 CA PerBit enable=1, Macro0, CA PI delay=34
8112 06:02:02.409362
8113 06:02:02.411834 [CBTSetCACLKResult] CA Dly = 34
8114 06:02:02.415409 CS Dly: 9 (0~41)
8115 06:02:02.418316 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8116 06:02:02.421876 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8117 06:02:02.422438
8118 06:02:02.425056 ----->DramcWriteLeveling(PI) begin...
8119 06:02:02.425528 ==
8120 06:02:02.428405 Dram Type= 6, Freq= 0, CH_1, rank 0
8121 06:02:02.435105 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8122 06:02:02.435622 ==
8123 06:02:02.438319 Write leveling (Byte 0): 22 => 22
8124 06:02:02.441398 Write leveling (Byte 1): 21 => 21
8125 06:02:02.444900 DramcWriteLeveling(PI) end<-----
8126 06:02:02.445455
8127 06:02:02.445824 ==
8128 06:02:02.448426 Dram Type= 6, Freq= 0, CH_1, rank 0
8129 06:02:02.451475 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8130 06:02:02.452043 ==
8131 06:02:02.454719 [Gating] SW mode calibration
8132 06:02:02.461356 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8133 06:02:02.467851 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8134 06:02:02.471391 0 12 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8135 06:02:02.474717 0 12 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8136 06:02:02.481267 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8137 06:02:02.484791 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8138 06:02:02.487910 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8139 06:02:02.491106 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8140 06:02:02.497737 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8141 06:02:02.500766 0 12 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8142 06:02:02.504325 0 13 0 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0)
8143 06:02:02.510824 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8144 06:02:02.514548 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8145 06:02:02.517419 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8146 06:02:02.524282 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8147 06:02:02.527730 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8148 06:02:02.531164 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8149 06:02:02.537805 0 13 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
8150 06:02:02.540682 0 14 0 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
8151 06:02:02.544256 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8152 06:02:02.550681 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8153 06:02:02.554190 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8154 06:02:02.557551 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8155 06:02:02.564334 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8156 06:02:02.567365 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8157 06:02:02.571030 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8158 06:02:02.577514 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8159 06:02:02.580993 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8160 06:02:02.583797 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 06:02:02.590331 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 06:02:02.593725 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 06:02:02.597276 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8164 06:02:02.603823 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8165 06:02:02.607198 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8166 06:02:02.610106 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8167 06:02:02.616980 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8168 06:02:02.620508 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8169 06:02:02.623492 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8170 06:02:02.630242 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8171 06:02:02.633267 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8172 06:02:02.636676 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8173 06:02:02.643444 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8174 06:02:02.646705 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8175 06:02:02.649651 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8176 06:02:02.653080 Total UI for P1: 0, mck2ui 16
8177 06:02:02.656295 best dqsien dly found for B0: ( 1, 0, 28)
8178 06:02:02.663640 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8179 06:02:02.664258 Total UI for P1: 0, mck2ui 16
8180 06:02:02.669469 best dqsien dly found for B1: ( 1, 1, 2)
8181 06:02:02.672925 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8182 06:02:02.676490 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8183 06:02:02.677094
8184 06:02:02.679664 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8185 06:02:02.682989 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8186 06:02:02.686137 [Gating] SW calibration Done
8187 06:02:02.686705 ==
8188 06:02:02.689225 Dram Type= 6, Freq= 0, CH_1, rank 0
8189 06:02:02.692814 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8190 06:02:02.693382 ==
8191 06:02:02.695978 RX Vref Scan: 0
8192 06:02:02.696538
8193 06:02:02.696944 RX Vref 0 -> 0, step: 1
8194 06:02:02.697285
8195 06:02:02.699114 RX Delay 0 -> 252, step: 8
8196 06:02:02.702466 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8197 06:02:02.709257 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8198 06:02:02.712182 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8199 06:02:02.715800 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8200 06:02:02.718963 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8201 06:02:02.722310 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8202 06:02:02.728978 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8203 06:02:02.732278 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8204 06:02:02.735847 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8205 06:02:02.738553 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8206 06:02:02.742045 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8207 06:02:02.748620 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8208 06:02:02.752162 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8209 06:02:02.755154 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8210 06:02:02.758261 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8211 06:02:02.764697 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8212 06:02:02.765288 ==
8213 06:02:02.768059 Dram Type= 6, Freq= 0, CH_1, rank 0
8214 06:02:02.771768 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8215 06:02:02.772331 ==
8216 06:02:02.772696 DQS Delay:
8217 06:02:02.774849 DQS0 = 0, DQS1 = 0
8218 06:02:02.775303 DQM Delay:
8219 06:02:02.778030 DQM0 = 129, DQM1 = 126
8220 06:02:02.778508 DQ Delay:
8221 06:02:02.781702 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8222 06:02:02.784630 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8223 06:02:02.788298 DQ8 =107, DQ9 =119, DQ10 =127, DQ11 =115
8224 06:02:02.791468 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8225 06:02:02.795048
8226 06:02:02.795624
8227 06:02:02.796108 ==
8228 06:02:02.798067 Dram Type= 6, Freq= 0, CH_1, rank 0
8229 06:02:02.801206 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8230 06:02:02.801683 ==
8231 06:02:02.802162
8232 06:02:02.802610
8233 06:02:02.804393 TX Vref Scan disable
8234 06:02:02.804895 == TX Byte 0 ==
8235 06:02:02.811019 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8236 06:02:02.814450 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8237 06:02:02.814927 == TX Byte 1 ==
8238 06:02:02.821120 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8239 06:02:02.824376 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8240 06:02:02.824907 ==
8241 06:02:02.827707 Dram Type= 6, Freq= 0, CH_1, rank 0
8242 06:02:02.831032 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8243 06:02:02.831606 ==
8244 06:02:02.844193
8245 06:02:02.847593 TX Vref early break, caculate TX vref
8246 06:02:02.850786 TX Vref=16, minBit 0, minWin=21, winSum=364
8247 06:02:02.854038 TX Vref=18, minBit 0, minWin=21, winSum=375
8248 06:02:02.857636 TX Vref=20, minBit 0, minWin=23, winSum=386
8249 06:02:02.860782 TX Vref=22, minBit 1, minWin=23, winSum=391
8250 06:02:02.863760 TX Vref=24, minBit 1, minWin=24, winSum=402
8251 06:02:02.871068 TX Vref=26, minBit 3, minWin=24, winSum=415
8252 06:02:02.874143 TX Vref=28, minBit 0, minWin=25, winSum=411
8253 06:02:02.877300 TX Vref=30, minBit 1, minWin=24, winSum=405
8254 06:02:02.880658 TX Vref=32, minBit 1, minWin=23, winSum=395
8255 06:02:02.883791 TX Vref=34, minBit 3, minWin=23, winSum=389
8256 06:02:02.890155 [TxChooseVref] Worse bit 0, Min win 25, Win sum 411, Final Vref 28
8257 06:02:02.890717
8258 06:02:02.893806 Final TX Range 0 Vref 28
8259 06:02:02.894281
8260 06:02:02.894760 ==
8261 06:02:02.897145 Dram Type= 6, Freq= 0, CH_1, rank 0
8262 06:02:02.900544 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8263 06:02:02.901198 ==
8264 06:02:02.901684
8265 06:02:02.902136
8266 06:02:02.903469 TX Vref Scan disable
8267 06:02:02.910076 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8268 06:02:02.910640 == TX Byte 0 ==
8269 06:02:02.913633 u2DelayCellOfst[0]=14 cells (4 PI)
8270 06:02:02.916612 u2DelayCellOfst[1]=10 cells (3 PI)
8271 06:02:02.920147 u2DelayCellOfst[2]=0 cells (0 PI)
8272 06:02:02.923266 u2DelayCellOfst[3]=3 cells (1 PI)
8273 06:02:02.926500 u2DelayCellOfst[4]=7 cells (2 PI)
8274 06:02:02.930170 u2DelayCellOfst[5]=14 cells (4 PI)
8275 06:02:02.933173 u2DelayCellOfst[6]=14 cells (4 PI)
8276 06:02:02.936634 u2DelayCellOfst[7]=7 cells (2 PI)
8277 06:02:02.939693 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8278 06:02:02.942950 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8279 06:02:02.946815 == TX Byte 1 ==
8280 06:02:02.947374 u2DelayCellOfst[8]=0 cells (0 PI)
8281 06:02:02.949771 u2DelayCellOfst[9]=7 cells (2 PI)
8282 06:02:02.953500 u2DelayCellOfst[10]=10 cells (3 PI)
8283 06:02:02.956769 u2DelayCellOfst[11]=3 cells (1 PI)
8284 06:02:02.960125 u2DelayCellOfst[12]=17 cells (5 PI)
8285 06:02:02.963491 u2DelayCellOfst[13]=21 cells (6 PI)
8286 06:02:02.966648 u2DelayCellOfst[14]=21 cells (6 PI)
8287 06:02:02.969893 u2DelayCellOfst[15]=17 cells (5 PI)
8288 06:02:02.973672 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8289 06:02:02.980102 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8290 06:02:02.980651 DramC Write-DBI on
8291 06:02:02.981053 ==
8292 06:02:02.983270 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 06:02:02.986654 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8294 06:02:02.989909 ==
8295 06:02:02.990468
8296 06:02:02.990834
8297 06:02:02.991172 TX Vref Scan disable
8298 06:02:02.993573 == TX Byte 0 ==
8299 06:02:02.996870 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8300 06:02:02.999965 == TX Byte 1 ==
8301 06:02:03.003679 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8302 06:02:03.006502 DramC Write-DBI off
8303 06:02:03.007009
8304 06:02:03.007379 [DATLAT]
8305 06:02:03.007719 Freq=1600, CH1 RK0
8306 06:02:03.008152
8307 06:02:03.009685 DATLAT Default: 0xf
8308 06:02:03.010150 0, 0xFFFF, sum = 0
8309 06:02:03.013219 1, 0xFFFF, sum = 0
8310 06:02:03.016508 2, 0xFFFF, sum = 0
8311 06:02:03.017015 3, 0xFFFF, sum = 0
8312 06:02:03.019862 4, 0xFFFF, sum = 0
8313 06:02:03.020329 5, 0xFFFF, sum = 0
8314 06:02:03.023019 6, 0xFFFF, sum = 0
8315 06:02:03.023489 7, 0xFFFF, sum = 0
8316 06:02:03.026234 8, 0xFFFF, sum = 0
8317 06:02:03.026699 9, 0xFFFF, sum = 0
8318 06:02:03.029656 10, 0xFFFF, sum = 0
8319 06:02:03.030127 11, 0xFFFF, sum = 0
8320 06:02:03.032779 12, 0x8FFF, sum = 0
8321 06:02:03.033249 13, 0x0, sum = 1
8322 06:02:03.036200 14, 0x0, sum = 2
8323 06:02:03.036830 15, 0x0, sum = 3
8324 06:02:03.039658 16, 0x0, sum = 4
8325 06:02:03.040234 best_step = 14
8326 06:02:03.040604
8327 06:02:03.041016 ==
8328 06:02:03.042746 Dram Type= 6, Freq= 0, CH_1, rank 0
8329 06:02:03.046296 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8330 06:02:03.049634 ==
8331 06:02:03.050293 RX Vref Scan: 1
8332 06:02:03.050678
8333 06:02:03.052640 Set Vref Range= 24 -> 127
8334 06:02:03.053144
8335 06:02:03.056229 RX Vref 24 -> 127, step: 1
8336 06:02:03.056865
8337 06:02:03.057248 RX Delay 3 -> 252, step: 4
8338 06:02:03.057712
8339 06:02:03.059503 Set Vref, RX VrefLevel [Byte0]: 24
8340 06:02:03.062791 [Byte1]: 24
8341 06:02:03.066330
8342 06:02:03.066793 Set Vref, RX VrefLevel [Byte0]: 25
8343 06:02:03.070091 [Byte1]: 25
8344 06:02:03.074749
8345 06:02:03.075308 Set Vref, RX VrefLevel [Byte0]: 26
8346 06:02:03.077824 [Byte1]: 26
8347 06:02:03.082145
8348 06:02:03.082697 Set Vref, RX VrefLevel [Byte0]: 27
8349 06:02:03.085481 [Byte1]: 27
8350 06:02:03.089697
8351 06:02:03.090314 Set Vref, RX VrefLevel [Byte0]: 28
8352 06:02:03.092943 [Byte1]: 28
8353 06:02:03.097086
8354 06:02:03.097548 Set Vref, RX VrefLevel [Byte0]: 29
8355 06:02:03.100558 [Byte1]: 29
8356 06:02:03.105005
8357 06:02:03.105566 Set Vref, RX VrefLevel [Byte0]: 30
8358 06:02:03.108405 [Byte1]: 30
8359 06:02:03.112450
8360 06:02:03.112971 Set Vref, RX VrefLevel [Byte0]: 31
8361 06:02:03.115537 [Byte1]: 31
8362 06:02:03.119909
8363 06:02:03.120366 Set Vref, RX VrefLevel [Byte0]: 32
8364 06:02:03.123153 [Byte1]: 32
8365 06:02:03.127632
8366 06:02:03.128091 Set Vref, RX VrefLevel [Byte0]: 33
8367 06:02:03.131473 [Byte1]: 33
8368 06:02:03.135383
8369 06:02:03.135843 Set Vref, RX VrefLevel [Byte0]: 34
8370 06:02:03.138837 [Byte1]: 34
8371 06:02:03.143156
8372 06:02:03.143708 Set Vref, RX VrefLevel [Byte0]: 35
8373 06:02:03.146804 [Byte1]: 35
8374 06:02:03.150924
8375 06:02:03.151479 Set Vref, RX VrefLevel [Byte0]: 36
8376 06:02:03.153807 [Byte1]: 36
8377 06:02:03.158278
8378 06:02:03.158893 Set Vref, RX VrefLevel [Byte0]: 37
8379 06:02:03.161533 [Byte1]: 37
8380 06:02:03.165969
8381 06:02:03.166384 Set Vref, RX VrefLevel [Byte0]: 38
8382 06:02:03.169107 [Byte1]: 38
8383 06:02:03.173588
8384 06:02:03.174004 Set Vref, RX VrefLevel [Byte0]: 39
8385 06:02:03.177292 [Byte1]: 39
8386 06:02:03.181256
8387 06:02:03.181767 Set Vref, RX VrefLevel [Byte0]: 40
8388 06:02:03.184517 [Byte1]: 40
8389 06:02:03.188926
8390 06:02:03.189433 Set Vref, RX VrefLevel [Byte0]: 41
8391 06:02:03.192566 [Byte1]: 41
8392 06:02:03.196816
8393 06:02:03.197326 Set Vref, RX VrefLevel [Byte0]: 42
8394 06:02:03.200129 [Byte1]: 42
8395 06:02:03.204792
8396 06:02:03.205299 Set Vref, RX VrefLevel [Byte0]: 43
8397 06:02:03.207628 [Byte1]: 43
8398 06:02:03.212026
8399 06:02:03.212574 Set Vref, RX VrefLevel [Byte0]: 44
8400 06:02:03.215428 [Byte1]: 44
8401 06:02:03.219586
8402 06:02:03.220144 Set Vref, RX VrefLevel [Byte0]: 45
8403 06:02:03.223136 [Byte1]: 45
8404 06:02:03.227433
8405 06:02:03.227999 Set Vref, RX VrefLevel [Byte0]: 46
8406 06:02:03.230788 [Byte1]: 46
8407 06:02:03.234960
8408 06:02:03.235517 Set Vref, RX VrefLevel [Byte0]: 47
8409 06:02:03.238688 [Byte1]: 47
8410 06:02:03.242698
8411 06:02:03.243280 Set Vref, RX VrefLevel [Byte0]: 48
8412 06:02:03.246100 [Byte1]: 48
8413 06:02:03.250270
8414 06:02:03.250856 Set Vref, RX VrefLevel [Byte0]: 49
8415 06:02:03.253661 [Byte1]: 49
8416 06:02:03.258018
8417 06:02:03.258585 Set Vref, RX VrefLevel [Byte0]: 50
8418 06:02:03.261378 [Byte1]: 50
8419 06:02:03.265424
8420 06:02:03.265986 Set Vref, RX VrefLevel [Byte0]: 51
8421 06:02:03.269072 [Byte1]: 51
8422 06:02:03.273133
8423 06:02:03.273596 Set Vref, RX VrefLevel [Byte0]: 52
8424 06:02:03.276585 [Byte1]: 52
8425 06:02:03.281008
8426 06:02:03.281570 Set Vref, RX VrefLevel [Byte0]: 53
8427 06:02:03.284030 [Byte1]: 53
8428 06:02:03.288479
8429 06:02:03.289095 Set Vref, RX VrefLevel [Byte0]: 54
8430 06:02:03.291864 [Byte1]: 54
8431 06:02:03.296184
8432 06:02:03.296801 Set Vref, RX VrefLevel [Byte0]: 55
8433 06:02:03.299395 [Byte1]: 55
8434 06:02:03.303836
8435 06:02:03.304403 Set Vref, RX VrefLevel [Byte0]: 56
8436 06:02:03.307135 [Byte1]: 56
8437 06:02:03.311288
8438 06:02:03.311754 Set Vref, RX VrefLevel [Byte0]: 57
8439 06:02:03.314643 [Byte1]: 57
8440 06:02:03.319213
8441 06:02:03.319774 Set Vref, RX VrefLevel [Byte0]: 58
8442 06:02:03.322349 [Byte1]: 58
8443 06:02:03.326777
8444 06:02:03.327337 Set Vref, RX VrefLevel [Byte0]: 59
8445 06:02:03.330008 [Byte1]: 59
8446 06:02:03.334612
8447 06:02:03.335170 Set Vref, RX VrefLevel [Byte0]: 60
8448 06:02:03.337646 [Byte1]: 60
8449 06:02:03.342317
8450 06:02:03.342867 Set Vref, RX VrefLevel [Byte0]: 61
8451 06:02:03.345511 [Byte1]: 61
8452 06:02:03.349872
8453 06:02:03.350424 Set Vref, RX VrefLevel [Byte0]: 62
8454 06:02:03.353016 [Byte1]: 62
8455 06:02:03.357438
8456 06:02:03.357996 Set Vref, RX VrefLevel [Byte0]: 63
8457 06:02:03.360649 [Byte1]: 63
8458 06:02:03.365121
8459 06:02:03.365683 Set Vref, RX VrefLevel [Byte0]: 64
8460 06:02:03.368503 [Byte1]: 64
8461 06:02:03.373078
8462 06:02:03.373633 Set Vref, RX VrefLevel [Byte0]: 65
8463 06:02:03.376267 [Byte1]: 65
8464 06:02:03.380456
8465 06:02:03.381080 Set Vref, RX VrefLevel [Byte0]: 66
8466 06:02:03.384048 [Byte1]: 66
8467 06:02:03.388223
8468 06:02:03.389030 Set Vref, RX VrefLevel [Byte0]: 67
8469 06:02:03.391176 [Byte1]: 67
8470 06:02:03.395695
8471 06:02:03.396250 Set Vref, RX VrefLevel [Byte0]: 68
8472 06:02:03.399078 [Byte1]: 68
8473 06:02:03.403342
8474 06:02:03.403896 Set Vref, RX VrefLevel [Byte0]: 69
8475 06:02:03.406504 [Byte1]: 69
8476 06:02:03.411149
8477 06:02:03.411702 Set Vref, RX VrefLevel [Byte0]: 70
8478 06:02:03.414421 [Byte1]: 70
8479 06:02:03.418414
8480 06:02:03.418892 Set Vref, RX VrefLevel [Byte0]: 71
8481 06:02:03.421575 [Byte1]: 71
8482 06:02:03.426441
8483 06:02:03.427009 Set Vref, RX VrefLevel [Byte0]: 72
8484 06:02:03.429624 [Byte1]: 72
8485 06:02:03.434220
8486 06:02:03.434965 Set Vref, RX VrefLevel [Byte0]: 73
8487 06:02:03.436922 [Byte1]: 73
8488 06:02:03.441512
8489 06:02:03.444515 Set Vref, RX VrefLevel [Byte0]: 74
8490 06:02:03.448123 [Byte1]: 74
8491 06:02:03.448678
8492 06:02:03.451188 Set Vref, RX VrefLevel [Byte0]: 75
8493 06:02:03.454592 [Byte1]: 75
8494 06:02:03.455052
8495 06:02:03.457963 Set Vref, RX VrefLevel [Byte0]: 76
8496 06:02:03.461332 [Byte1]: 76
8497 06:02:03.465052
8498 06:02:03.465601 Set Vref, RX VrefLevel [Byte0]: 77
8499 06:02:03.468023 [Byte1]: 77
8500 06:02:03.472256
8501 06:02:03.472895 Final RX Vref Byte 0 = 59 to rank0
8502 06:02:03.475781 Final RX Vref Byte 1 = 53 to rank0
8503 06:02:03.478818 Final RX Vref Byte 0 = 59 to rank1
8504 06:02:03.482182 Final RX Vref Byte 1 = 53 to rank1==
8505 06:02:03.485408 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 06:02:03.492072 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8507 06:02:03.492634 ==
8508 06:02:03.493064 DQS Delay:
8509 06:02:03.495021 DQS0 = 0, DQS1 = 0
8510 06:02:03.495484 DQM Delay:
8511 06:02:03.495845 DQM0 = 128, DQM1 = 124
8512 06:02:03.498250 DQ Delay:
8513 06:02:03.501820 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
8514 06:02:03.505090 DQ4 =128, DQ5 =138, DQ6 =138, DQ7 =126
8515 06:02:03.508372 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8516 06:02:03.511846 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8517 06:02:03.512408
8518 06:02:03.512850
8519 06:02:03.513206
8520 06:02:03.515201 [DramC_TX_OE_Calibration] TA2
8521 06:02:03.518328 Original DQ_B0 (3 6) =30, OEN = 27
8522 06:02:03.521414 Original DQ_B1 (3 6) =30, OEN = 27
8523 06:02:03.524859 24, 0x0, End_B0=24 End_B1=24
8524 06:02:03.525332 25, 0x0, End_B0=25 End_B1=25
8525 06:02:03.528278 26, 0x0, End_B0=26 End_B1=26
8526 06:02:03.531352 27, 0x0, End_B0=27 End_B1=27
8527 06:02:03.535027 28, 0x0, End_B0=28 End_B1=28
8528 06:02:03.538136 29, 0x0, End_B0=29 End_B1=29
8529 06:02:03.538610 30, 0x0, End_B0=30 End_B1=30
8530 06:02:03.541461 31, 0x4141, End_B0=30 End_B1=30
8531 06:02:03.544904 Byte0 end_step=30 best_step=27
8532 06:02:03.547974 Byte1 end_step=30 best_step=27
8533 06:02:03.551590 Byte0 TX OE(2T, 0.5T) = (3, 3)
8534 06:02:03.554665 Byte1 TX OE(2T, 0.5T) = (3, 3)
8535 06:02:03.555131
8536 06:02:03.555495
8537 06:02:03.561218 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8538 06:02:03.564919 CH1 RK0: MR19=303, MR18=2626
8539 06:02:03.571175 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8540 06:02:03.571740
8541 06:02:03.574631 ----->DramcWriteLeveling(PI) begin...
8542 06:02:03.575197 ==
8543 06:02:03.577607 Dram Type= 6, Freq= 0, CH_1, rank 1
8544 06:02:03.581142 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8545 06:02:03.581708 ==
8546 06:02:03.584480 Write leveling (Byte 0): 22 => 22
8547 06:02:03.587962 Write leveling (Byte 1): 20 => 20
8548 06:02:03.591014 DramcWriteLeveling(PI) end<-----
8549 06:02:03.591482
8550 06:02:03.591849 ==
8551 06:02:03.594111 Dram Type= 6, Freq= 0, CH_1, rank 1
8552 06:02:03.597598 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8553 06:02:03.601204 ==
8554 06:02:03.601765 [Gating] SW mode calibration
8555 06:02:03.607901 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8556 06:02:03.614376 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8557 06:02:03.617684 0 12 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
8558 06:02:03.624059 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8559 06:02:03.627673 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8560 06:02:03.630931 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8561 06:02:03.637309 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8562 06:02:03.640670 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8563 06:02:03.644036 0 12 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8564 06:02:03.650461 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8565 06:02:03.653695 0 13 0 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
8566 06:02:03.657334 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8567 06:02:03.663700 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8568 06:02:03.667225 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8569 06:02:03.670357 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8570 06:02:03.677567 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8571 06:02:03.680603 0 13 24 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8572 06:02:03.683428 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8573 06:02:03.689962 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8574 06:02:03.693386 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8575 06:02:03.696485 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8576 06:02:03.703375 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8577 06:02:03.706769 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8578 06:02:03.710104 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8579 06:02:03.716511 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8580 06:02:03.719745 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8581 06:02:03.723161 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8582 06:02:03.729691 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8583 06:02:03.733113 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8584 06:02:03.736361 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8585 06:02:03.743259 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8586 06:02:03.746177 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8587 06:02:03.749438 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8588 06:02:03.756225 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8589 06:02:03.759778 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8590 06:02:03.762666 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8591 06:02:03.769287 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8592 06:02:03.772845 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8593 06:02:03.776230 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8594 06:02:03.782766 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8595 06:02:03.786297 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8596 06:02:03.789200 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8597 06:02:03.792816 Total UI for P1: 0, mck2ui 16
8598 06:02:03.795816 best dqsien dly found for B0: ( 1, 0, 22)
8599 06:02:03.802519 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8600 06:02:03.805695 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8601 06:02:03.808802 Total UI for P1: 0, mck2ui 16
8602 06:02:03.812763 best dqsien dly found for B1: ( 1, 1, 0)
8603 06:02:03.815636 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8604 06:02:03.818823 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8605 06:02:03.819852
8606 06:02:03.822136 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8607 06:02:03.825460 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8608 06:02:03.828769 [Gating] SW calibration Done
8609 06:02:03.829238 ==
8610 06:02:03.832161 Dram Type= 6, Freq= 0, CH_1, rank 1
8611 06:02:03.835467 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8612 06:02:03.836045 ==
8613 06:02:03.838749 RX Vref Scan: 0
8614 06:02:03.839213
8615 06:02:03.842563 RX Vref 0 -> 0, step: 1
8616 06:02:03.843139
8617 06:02:03.843507 RX Delay 0 -> 252, step: 8
8618 06:02:03.848593 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8619 06:02:03.851898 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8620 06:02:03.855258 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8621 06:02:03.858779 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8622 06:02:03.862004 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8623 06:02:03.868763 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8624 06:02:03.871920 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8625 06:02:03.875465 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8626 06:02:03.878345 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8627 06:02:03.881664 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8628 06:02:03.888469 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8629 06:02:03.891650 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8630 06:02:03.894605 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8631 06:02:03.898358 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8632 06:02:03.904762 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8633 06:02:03.908163 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8634 06:02:03.908781 ==
8635 06:02:03.911340 Dram Type= 6, Freq= 0, CH_1, rank 1
8636 06:02:03.914638 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8637 06:02:03.915106 ==
8638 06:02:03.918136 DQS Delay:
8639 06:02:03.918600 DQS0 = 0, DQS1 = 0
8640 06:02:03.918967 DQM Delay:
8641 06:02:03.921593 DQM0 = 131, DQM1 = 124
8642 06:02:03.922076 DQ Delay:
8643 06:02:03.924408 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8644 06:02:03.927670 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8645 06:02:03.931219 DQ8 =107, DQ9 =111, DQ10 =123, DQ11 =115
8646 06:02:03.937650 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8647 06:02:03.938117
8648 06:02:03.938488
8649 06:02:03.938829 ==
8650 06:02:03.940785 Dram Type= 6, Freq= 0, CH_1, rank 1
8651 06:02:03.944362 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8652 06:02:03.944871 ==
8653 06:02:03.945247
8654 06:02:03.945585
8655 06:02:03.947665 TX Vref Scan disable
8656 06:02:03.948130 == TX Byte 0 ==
8657 06:02:03.954006 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8658 06:02:03.958044 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8659 06:02:03.958615 == TX Byte 1 ==
8660 06:02:03.964393 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8661 06:02:03.967538 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8662 06:02:03.968109 ==
8663 06:02:03.970754 Dram Type= 6, Freq= 0, CH_1, rank 1
8664 06:02:03.974107 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8665 06:02:03.974682 ==
8666 06:02:03.989178
8667 06:02:03.992291 TX Vref early break, caculate TX vref
8668 06:02:03.995585 TX Vref=16, minBit 3, minWin=21, winSum=374
8669 06:02:03.998734 TX Vref=18, minBit 0, minWin=22, winSum=383
8670 06:02:04.002248 TX Vref=20, minBit 0, minWin=23, winSum=396
8671 06:02:04.005590 TX Vref=22, minBit 3, minWin=24, winSum=405
8672 06:02:04.008871 TX Vref=24, minBit 4, minWin=24, winSum=410
8673 06:02:04.015365 TX Vref=26, minBit 5, minWin=24, winSum=417
8674 06:02:04.018800 TX Vref=28, minBit 0, minWin=25, winSum=420
8675 06:02:04.021784 TX Vref=30, minBit 0, minWin=24, winSum=416
8676 06:02:04.025439 TX Vref=32, minBit 0, minWin=24, winSum=410
8677 06:02:04.028493 TX Vref=34, minBit 1, minWin=23, winSum=401
8678 06:02:04.032070 TX Vref=36, minBit 0, minWin=22, winSum=390
8679 06:02:04.038200 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8680 06:02:04.038671
8681 06:02:04.042021 Final TX Range 0 Vref 28
8682 06:02:04.042600
8683 06:02:04.042968 ==
8684 06:02:04.044862 Dram Type= 6, Freq= 0, CH_1, rank 1
8685 06:02:04.048477 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8686 06:02:04.049099 ==
8687 06:02:04.051496
8688 06:02:04.051956
8689 06:02:04.052319 TX Vref Scan disable
8690 06:02:04.058438 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8691 06:02:04.059014 == TX Byte 0 ==
8692 06:02:04.061666 u2DelayCellOfst[0]=17 cells (5 PI)
8693 06:02:04.065086 u2DelayCellOfst[1]=10 cells (3 PI)
8694 06:02:04.068756 u2DelayCellOfst[2]=0 cells (0 PI)
8695 06:02:04.071604 u2DelayCellOfst[3]=10 cells (3 PI)
8696 06:02:04.075133 u2DelayCellOfst[4]=10 cells (3 PI)
8697 06:02:04.078393 u2DelayCellOfst[5]=17 cells (5 PI)
8698 06:02:04.081849 u2DelayCellOfst[6]=17 cells (5 PI)
8699 06:02:04.085258 u2DelayCellOfst[7]=7 cells (2 PI)
8700 06:02:04.088485 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8701 06:02:04.091715 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8702 06:02:04.095334 == TX Byte 1 ==
8703 06:02:04.098224 u2DelayCellOfst[8]=0 cells (0 PI)
8704 06:02:04.101543 u2DelayCellOfst[9]=7 cells (2 PI)
8705 06:02:04.104848 u2DelayCellOfst[10]=10 cells (3 PI)
8706 06:02:04.108018 u2DelayCellOfst[11]=3 cells (1 PI)
8707 06:02:04.108584 u2DelayCellOfst[12]=14 cells (4 PI)
8708 06:02:04.111322 u2DelayCellOfst[13]=17 cells (5 PI)
8709 06:02:04.114754 u2DelayCellOfst[14]=17 cells (5 PI)
8710 06:02:04.117815 u2DelayCellOfst[15]=17 cells (5 PI)
8711 06:02:04.124812 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8712 06:02:04.127981 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8713 06:02:04.128559 DramC Write-DBI on
8714 06:02:04.131202 ==
8715 06:02:04.134908 Dram Type= 6, Freq= 0, CH_1, rank 1
8716 06:02:04.137764 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8717 06:02:04.138232 ==
8718 06:02:04.138598
8719 06:02:04.138934
8720 06:02:04.141218 TX Vref Scan disable
8721 06:02:04.141681 == TX Byte 0 ==
8722 06:02:04.147817 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8723 06:02:04.148403 == TX Byte 1 ==
8724 06:02:04.151260 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8725 06:02:04.154221 DramC Write-DBI off
8726 06:02:04.154687
8727 06:02:04.155051 [DATLAT]
8728 06:02:04.157561 Freq=1600, CH1 RK1
8729 06:02:04.158027
8730 06:02:04.158394 DATLAT Default: 0xe
8731 06:02:04.160812 0, 0xFFFF, sum = 0
8732 06:02:04.161286 1, 0xFFFF, sum = 0
8733 06:02:04.164122 2, 0xFFFF, sum = 0
8734 06:02:04.164592 3, 0xFFFF, sum = 0
8735 06:02:04.167984 4, 0xFFFF, sum = 0
8736 06:02:04.168588 5, 0xFFFF, sum = 0
8737 06:02:04.170786 6, 0xFFFF, sum = 0
8738 06:02:04.171259 7, 0xFFFF, sum = 0
8739 06:02:04.174165 8, 0xFFFF, sum = 0
8740 06:02:04.177669 9, 0xFFFF, sum = 0
8741 06:02:04.178247 10, 0xFFFF, sum = 0
8742 06:02:04.180800 11, 0xFFFF, sum = 0
8743 06:02:04.181273 12, 0x8F7F, sum = 0
8744 06:02:04.184035 13, 0x0, sum = 1
8745 06:02:04.184606 14, 0x0, sum = 2
8746 06:02:04.187544 15, 0x0, sum = 3
8747 06:02:04.188121 16, 0x0, sum = 4
8748 06:02:04.188499 best_step = 14
8749 06:02:04.190723
8750 06:02:04.191292 ==
8751 06:02:04.194043 Dram Type= 6, Freq= 0, CH_1, rank 1
8752 06:02:04.197406 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8753 06:02:04.197981 ==
8754 06:02:04.198347 RX Vref Scan: 0
8755 06:02:04.198684
8756 06:02:04.200607 RX Vref 0 -> 0, step: 1
8757 06:02:04.201211
8758 06:02:04.203900 RX Delay 3 -> 252, step: 4
8759 06:02:04.207268 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8760 06:02:04.213767 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8761 06:02:04.217578 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8762 06:02:04.220514 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8763 06:02:04.223555 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8764 06:02:04.226920 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8765 06:02:04.233537 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8766 06:02:04.236683 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8767 06:02:04.240272 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8768 06:02:04.243961 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8769 06:02:04.246765 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8770 06:02:04.253240 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8771 06:02:04.257097 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8772 06:02:04.260151 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8773 06:02:04.263360 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8774 06:02:04.266845 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8775 06:02:04.269856 ==
8776 06:02:04.273442 Dram Type= 6, Freq= 0, CH_1, rank 1
8777 06:02:04.276618 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8778 06:02:04.277216 ==
8779 06:02:04.277588 DQS Delay:
8780 06:02:04.279784 DQS0 = 0, DQS1 = 0
8781 06:02:04.280330 DQM Delay:
8782 06:02:04.283274 DQM0 = 127, DQM1 = 122
8783 06:02:04.283852 DQ Delay:
8784 06:02:04.286295 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8785 06:02:04.289922 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8786 06:02:04.293252 DQ8 =106, DQ9 =110, DQ10 =122, DQ11 =114
8787 06:02:04.296404 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8788 06:02:04.297005
8789 06:02:04.297375
8790 06:02:04.297713
8791 06:02:04.299520 [DramC_TX_OE_Calibration] TA2
8792 06:02:04.303125 Original DQ_B0 (3 6) =30, OEN = 27
8793 06:02:04.306530 Original DQ_B1 (3 6) =30, OEN = 27
8794 06:02:04.309629 24, 0x0, End_B0=24 End_B1=24
8795 06:02:04.313099 25, 0x0, End_B0=25 End_B1=25
8796 06:02:04.313700 26, 0x0, End_B0=26 End_B1=26
8797 06:02:04.316419 27, 0x0, End_B0=27 End_B1=27
8798 06:02:04.319770 28, 0x0, End_B0=28 End_B1=28
8799 06:02:04.323291 29, 0x0, End_B0=29 End_B1=29
8800 06:02:04.326210 30, 0x0, End_B0=30 End_B1=30
8801 06:02:04.326683 31, 0x4141, End_B0=30 End_B1=30
8802 06:02:04.329406 Byte0 end_step=30 best_step=27
8803 06:02:04.333123 Byte1 end_step=30 best_step=27
8804 06:02:04.336131 Byte0 TX OE(2T, 0.5T) = (3, 3)
8805 06:02:04.339599 Byte1 TX OE(2T, 0.5T) = (3, 3)
8806 06:02:04.340168
8807 06:02:04.340536
8808 06:02:04.345801 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8809 06:02:04.349407 CH1 RK1: MR19=303, MR18=1C1C
8810 06:02:04.356110 CH1_RK1: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8811 06:02:04.359478 [RxdqsGatingPostProcess] freq 1600
8812 06:02:04.366008 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8813 06:02:04.369327 Pre-setting of DQS Precalculation
8814 06:02:04.372523 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8815 06:02:04.379327 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8816 06:02:04.385727 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8817 06:02:04.386300
8818 06:02:04.388997
8819 06:02:04.389560 [Calibration Summary] 3200 Mbps
8820 06:02:04.392273 CH 0, Rank 0
8821 06:02:04.392890 SW Impedance : PASS
8822 06:02:04.395862 DUTY Scan : NO K
8823 06:02:04.398934 ZQ Calibration : PASS
8824 06:02:04.399400 Jitter Meter : NO K
8825 06:02:04.402332 CBT Training : PASS
8826 06:02:04.405678 Write leveling : PASS
8827 06:02:04.406247 RX DQS gating : PASS
8828 06:02:04.408900 RX DQ/DQS(RDDQC) : PASS
8829 06:02:04.412235 TX DQ/DQS : PASS
8830 06:02:04.412842 RX DATLAT : PASS
8831 06:02:04.415678 RX DQ/DQS(Engine): PASS
8832 06:02:04.419025 TX OE : PASS
8833 06:02:04.419597 All Pass.
8834 06:02:04.419968
8835 06:02:04.420308 CH 0, Rank 1
8836 06:02:04.422080 SW Impedance : PASS
8837 06:02:04.425439 DUTY Scan : NO K
8838 06:02:04.425906 ZQ Calibration : PASS
8839 06:02:04.428697 Jitter Meter : NO K
8840 06:02:04.429200 CBT Training : PASS
8841 06:02:04.431976 Write leveling : PASS
8842 06:02:04.435703 RX DQS gating : PASS
8843 06:02:04.436274 RX DQ/DQS(RDDQC) : PASS
8844 06:02:04.438971 TX DQ/DQS : PASS
8845 06:02:04.442204 RX DATLAT : PASS
8846 06:02:04.442773 RX DQ/DQS(Engine): PASS
8847 06:02:04.445345 TX OE : PASS
8848 06:02:04.445814 All Pass.
8849 06:02:04.446181
8850 06:02:04.448671 CH 1, Rank 0
8851 06:02:04.449171 SW Impedance : PASS
8852 06:02:04.452111 DUTY Scan : NO K
8853 06:02:04.455172 ZQ Calibration : PASS
8854 06:02:04.455640 Jitter Meter : NO K
8855 06:02:04.459063 CBT Training : PASS
8856 06:02:04.462085 Write leveling : PASS
8857 06:02:04.462657 RX DQS gating : PASS
8858 06:02:04.465254 RX DQ/DQS(RDDQC) : PASS
8859 06:02:04.468497 TX DQ/DQS : PASS
8860 06:02:04.469116 RX DATLAT : PASS
8861 06:02:04.471578 RX DQ/DQS(Engine): PASS
8862 06:02:04.474917 TX OE : PASS
8863 06:02:04.475387 All Pass.
8864 06:02:04.475753
8865 06:02:04.476094 CH 1, Rank 1
8866 06:02:04.478193 SW Impedance : PASS
8867 06:02:04.481702 DUTY Scan : NO K
8868 06:02:04.482348 ZQ Calibration : PASS
8869 06:02:04.484974 Jitter Meter : NO K
8870 06:02:04.488429 CBT Training : PASS
8871 06:02:04.489035 Write leveling : PASS
8872 06:02:04.491825 RX DQS gating : PASS
8873 06:02:04.494784 RX DQ/DQS(RDDQC) : PASS
8874 06:02:04.495291 TX DQ/DQS : PASS
8875 06:02:04.497928 RX DATLAT : PASS
8876 06:02:04.498397 RX DQ/DQS(Engine): PASS
8877 06:02:04.501239 TX OE : PASS
8878 06:02:04.501706 All Pass.
8879 06:02:04.502073
8880 06:02:04.504703 DramC Write-DBI on
8881 06:02:04.508095 PER_BANK_REFRESH: Hybrid Mode
8882 06:02:04.508791 TX_TRACKING: ON
8883 06:02:04.518082 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8884 06:02:04.525125 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8885 06:02:04.534600 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8886 06:02:04.537610 [FAST_K] Save calibration result to emmc
8887 06:02:04.541046 sync common calibartion params.
8888 06:02:04.541509 sync cbt_mode0:0, 1:0
8889 06:02:04.544788 dram_init: ddr_geometry: 0
8890 06:02:04.547512 dram_init: ddr_geometry: 0
8891 06:02:04.547976 dram_init: ddr_geometry: 0
8892 06:02:04.551317 0:dram_rank_size:80000000
8893 06:02:04.554034 1:dram_rank_size:80000000
8894 06:02:04.557746 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8895 06:02:04.561281 DFS_SHUFFLE_HW_MODE: ON
8896 06:02:04.564068 dramc_set_vcore_voltage set vcore to 725000
8897 06:02:04.567708 Read voltage for 1600, 0
8898 06:02:04.568276 Vio18 = 0
8899 06:02:04.570774 Vcore = 725000
8900 06:02:04.571241 Vdram = 0
8901 06:02:04.571607 Vddq = 0
8902 06:02:04.571945 Vmddr = 0
8903 06:02:04.573902 switch to 3200 Mbps bootup
8904 06:02:04.577560 [DramcRunTimeConfig]
8905 06:02:04.578128 PHYPLL
8906 06:02:04.580570 DPM_CONTROL_AFTERK: ON
8907 06:02:04.581073 PER_BANK_REFRESH: ON
8908 06:02:04.583784 REFRESH_OVERHEAD_REDUCTION: ON
8909 06:02:04.587461 CMD_PICG_NEW_MODE: OFF
8910 06:02:04.588034 XRTWTW_NEW_MODE: ON
8911 06:02:04.590703 XRTRTR_NEW_MODE: ON
8912 06:02:04.591273 TX_TRACKING: ON
8913 06:02:04.593775 RDSEL_TRACKING: OFF
8914 06:02:04.597122 DQS Precalculation for DVFS: ON
8915 06:02:04.597694 RX_TRACKING: OFF
8916 06:02:04.600517 HW_GATING DBG: ON
8917 06:02:04.601126 ZQCS_ENABLE_LP4: ON
8918 06:02:04.603754 RX_PICG_NEW_MODE: ON
8919 06:02:04.604218 TX_PICG_NEW_MODE: ON
8920 06:02:04.606929 ENABLE_RX_DCM_DPHY: ON
8921 06:02:04.610152 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8922 06:02:04.613560 DUMMY_READ_FOR_TRACKING: OFF
8923 06:02:04.614026 !!! SPM_CONTROL_AFTERK: OFF
8924 06:02:04.616806 !!! SPM could not control APHY
8925 06:02:04.620528 IMPEDANCE_TRACKING: ON
8926 06:02:04.621190 TEMP_SENSOR: ON
8927 06:02:04.624191 HW_SAVE_FOR_SR: OFF
8928 06:02:04.626873 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8929 06:02:04.630309 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8930 06:02:04.630884 Read ODT Tracking: ON
8931 06:02:04.633324 Refresh Rate DeBounce: ON
8932 06:02:04.636781 DFS_NO_QUEUE_FLUSH: ON
8933 06:02:04.640155 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8934 06:02:04.640775 ENABLE_DFS_RUNTIME_MRW: OFF
8935 06:02:04.643539 DDR_RESERVE_NEW_MODE: ON
8936 06:02:04.646817 MR_CBT_SWITCH_FREQ: ON
8937 06:02:04.647388 =========================
8938 06:02:04.667119 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8939 06:02:04.670065 dram_init: ddr_geometry: 0
8940 06:02:04.688266 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8941 06:02:04.691938 dram_init: dram init end (result: 0)
8942 06:02:04.698171 DRAM-K: Full calibration passed in 23455 msecs
8943 06:02:04.701457 MRC: failed to locate region type 0.
8944 06:02:04.702018 DRAM rank0 size:0x80000000,
8945 06:02:04.704778 DRAM rank1 size=0x80000000
8946 06:02:04.714548 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8947 06:02:04.721299 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8948 06:02:04.727581 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8949 06:02:04.734449 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8950 06:02:04.737515 DRAM rank0 size:0x80000000,
8951 06:02:04.740781 DRAM rank1 size=0x80000000
8952 06:02:04.741260 CBMEM:
8953 06:02:04.744293 IMD: root @ 0xfffff000 254 entries.
8954 06:02:04.747617 IMD: root @ 0xffffec00 62 entries.
8955 06:02:04.750901 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8956 06:02:04.754145 WARNING: RO_VPD is uninitialized or empty.
8957 06:02:04.760870 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8958 06:02:04.767855 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8959 06:02:04.781146 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8960 06:02:04.792107 BS: romstage times (exec / console): total (unknown) / 22989 ms
8961 06:02:04.792672
8962 06:02:04.793119
8963 06:02:04.801826 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8964 06:02:04.805109 ARM64: Exception handlers installed.
8965 06:02:04.808903 ARM64: Testing exception
8966 06:02:04.812284 ARM64: Done test exception
8967 06:02:04.812947 Enumerating buses...
8968 06:02:04.814978 Show all devs... Before device enumeration.
8969 06:02:04.818386 Root Device: enabled 1
8970 06:02:04.821779 CPU_CLUSTER: 0: enabled 1
8971 06:02:04.822337 CPU: 00: enabled 1
8972 06:02:04.825012 Compare with tree...
8973 06:02:04.825566 Root Device: enabled 1
8974 06:02:04.828409 CPU_CLUSTER: 0: enabled 1
8975 06:02:04.832227 CPU: 00: enabled 1
8976 06:02:04.832893 Root Device scanning...
8977 06:02:04.835121 scan_static_bus for Root Device
8978 06:02:04.838268 CPU_CLUSTER: 0 enabled
8979 06:02:04.841831 scan_static_bus for Root Device done
8980 06:02:04.844957 scan_bus: bus Root Device finished in 8 msecs
8981 06:02:04.845427 done
8982 06:02:04.851339 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8983 06:02:04.855070 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8984 06:02:04.861368 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8985 06:02:04.864688 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8986 06:02:04.868125 Allocating resources...
8987 06:02:04.871409 Reading resources...
8988 06:02:04.874882 Root Device read_resources bus 0 link: 0
8989 06:02:04.875443 DRAM rank0 size:0x80000000,
8990 06:02:04.878035 DRAM rank1 size=0x80000000
8991 06:02:04.881091 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8992 06:02:04.884527 CPU: 00 missing read_resources
8993 06:02:04.891191 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8994 06:02:04.894400 Root Device read_resources bus 0 link: 0 done
8995 06:02:04.894867 Done reading resources.
8996 06:02:04.901375 Show resources in subtree (Root Device)...After reading.
8997 06:02:04.904558 Root Device child on link 0 CPU_CLUSTER: 0
8998 06:02:04.908052 CPU_CLUSTER: 0 child on link 0 CPU: 00
8999 06:02:04.917660 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9000 06:02:04.918225 CPU: 00
9001 06:02:04.920892 Root Device assign_resources, bus 0 link: 0
9002 06:02:04.924757 CPU_CLUSTER: 0 missing set_resources
9003 06:02:04.930798 Root Device assign_resources, bus 0 link: 0 done
9004 06:02:04.931268 Done setting resources.
9005 06:02:04.937216 Show resources in subtree (Root Device)...After assigning values.
9006 06:02:04.940774 Root Device child on link 0 CPU_CLUSTER: 0
9007 06:02:04.944383 CPU_CLUSTER: 0 child on link 0 CPU: 00
9008 06:02:04.954004 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9009 06:02:04.954556 CPU: 00
9010 06:02:04.957214 Done allocating resources.
9011 06:02:04.964057 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9012 06:02:04.964626 Enabling resources...
9013 06:02:04.965042 done.
9014 06:02:04.970461 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9015 06:02:04.971022 Initializing devices...
9016 06:02:04.973609 Root Device init
9017 06:02:04.974072 init hardware done!
9018 06:02:04.977024 0x00000018: ctrlr->caps
9019 06:02:04.980772 52.000 MHz: ctrlr->f_max
9020 06:02:04.981355 0.400 MHz: ctrlr->f_min
9021 06:02:04.983661 0x40ff8080: ctrlr->voltages
9022 06:02:04.986922 sclk: 390625
9023 06:02:04.987478 Bus Width = 1
9024 06:02:04.987848 sclk: 390625
9025 06:02:04.990642 Bus Width = 1
9026 06:02:04.991199 Early init status = 3
9027 06:02:04.996903 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9028 06:02:05.000341 in-header: 03 fc 00 00 01 00 00 00
9029 06:02:05.003771 in-data: 00
9030 06:02:05.006871 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9031 06:02:05.010566 in-header: 03 fd 00 00 00 00 00 00
9032 06:02:05.013779 in-data:
9033 06:02:05.017323 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9034 06:02:05.020856 in-header: 03 fc 00 00 01 00 00 00
9035 06:02:05.024010 in-data: 00
9036 06:02:05.026958 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9037 06:02:05.031918 in-header: 03 fd 00 00 00 00 00 00
9038 06:02:05.035186 in-data:
9039 06:02:05.038290 [SSUSB] Setting up USB HOST controller...
9040 06:02:05.041652 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9041 06:02:05.045112 [SSUSB] phy power-on done.
9042 06:02:05.048374 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9043 06:02:05.054802 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9044 06:02:05.058054 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9045 06:02:05.064697 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9046 06:02:05.071370 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9047 06:02:05.077932 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9048 06:02:05.084744 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9049 06:02:05.091474 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9050 06:02:05.094663 SPM: binary array size = 0x9dc
9051 06:02:05.097848 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9052 06:02:05.104374 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9053 06:02:05.111340 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9054 06:02:05.117679 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9055 06:02:05.121281 configure_display: Starting display init
9056 06:02:05.155015 anx7625_power_on_init: Init interface.
9057 06:02:05.158338 anx7625_disable_pd_protocol: Disabled PD feature.
9058 06:02:05.161458 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9059 06:02:05.189511 anx7625_start_dp_work: Secure OCM version=00
9060 06:02:05.193003 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9061 06:02:05.207716 sp_tx_get_edid_block: EDID Block = 1
9062 06:02:05.310464 Extracted contents:
9063 06:02:05.313345 header: 00 ff ff ff ff ff ff 00
9064 06:02:05.316744 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9065 06:02:05.319925 version: 01 04
9066 06:02:05.323349 basic params: 95 1f 11 78 0a
9067 06:02:05.326362 chroma info: 76 90 94 55 54 90 27 21 50 54
9068 06:02:05.329662 established: 00 00 00
9069 06:02:05.336431 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9070 06:02:05.342855 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9071 06:02:05.346205 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9072 06:02:05.352981 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9073 06:02:05.359565 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9074 06:02:05.362880 extensions: 00
9075 06:02:05.363438 checksum: fb
9076 06:02:05.363804
9077 06:02:05.369139 Manufacturer: IVO Model 57d Serial Number 0
9078 06:02:05.369687 Made week 0 of 2020
9079 06:02:05.372549 EDID version: 1.4
9080 06:02:05.373052 Digital display
9081 06:02:05.376285 6 bits per primary color channel
9082 06:02:05.379196 DisplayPort interface
9083 06:02:05.379751 Maximum image size: 31 cm x 17 cm
9084 06:02:05.382187 Gamma: 220%
9085 06:02:05.382647 Check DPMS levels
9086 06:02:05.389369 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9087 06:02:05.392305 First detailed timing is preferred timing
9088 06:02:05.395947 Established timings supported:
9089 06:02:05.396515 Standard timings supported:
9090 06:02:05.399062 Detailed timings
9091 06:02:05.402145 Hex of detail: 383680a07038204018303c0035ae10000019
9092 06:02:05.408691 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9093 06:02:05.412090 0780 0798 07c8 0820 hborder 0
9094 06:02:05.415240 0438 043b 0447 0458 vborder 0
9095 06:02:05.418710 -hsync -vsync
9096 06:02:05.419199 Did detailed timing
9097 06:02:05.425199 Hex of detail: 000000000000000000000000000000000000
9098 06:02:05.428553 Manufacturer-specified data, tag 0
9099 06:02:05.431804 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9100 06:02:05.435073 ASCII string: InfoVision
9101 06:02:05.438538 Hex of detail: 000000fe00523134304e574635205248200a
9102 06:02:05.441496 ASCII string: R140NWF5 RH
9103 06:02:05.441964 Checksum
9104 06:02:05.444859 Checksum: 0xfb (valid)
9105 06:02:05.448223 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9106 06:02:05.451853 DSI data_rate: 832800000 bps
9107 06:02:05.458055 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9108 06:02:05.461501 anx7625_parse_edid: pixelclock(138800).
9109 06:02:05.464971 hactive(1920), hsync(48), hfp(24), hbp(88)
9110 06:02:05.468178 vactive(1080), vsync(12), vfp(3), vbp(17)
9111 06:02:05.471266 anx7625_dsi_config: config dsi.
9112 06:02:05.478004 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9113 06:02:05.491934 anx7625_dsi_config: success to config DSI
9114 06:02:05.495405 anx7625_dp_start: MIPI phy setup OK.
9115 06:02:05.498838 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9116 06:02:05.502008 mtk_ddp_mode_set invalid vrefresh 60
9117 06:02:05.505193 main_disp_path_setup
9118 06:02:05.505660 ovl_layer_smi_id_en
9119 06:02:05.508574 ovl_layer_smi_id_en
9120 06:02:05.509178 ccorr_config
9121 06:02:05.509550 aal_config
9122 06:02:05.511890 gamma_config
9123 06:02:05.512351 postmask_config
9124 06:02:05.515236 dither_config
9125 06:02:05.518385 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9126 06:02:05.525177 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9127 06:02:05.528334 Root Device init finished in 551 msecs
9128 06:02:05.531499 CPU_CLUSTER: 0 init
9129 06:02:05.538274 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9130 06:02:05.544678 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9131 06:02:05.545185 APU_MBOX 0x190000b0 = 0x10001
9132 06:02:05.548482 APU_MBOX 0x190001b0 = 0x10001
9133 06:02:05.551346 APU_MBOX 0x190005b0 = 0x10001
9134 06:02:05.554981 APU_MBOX 0x190006b0 = 0x10001
9135 06:02:05.561324 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9136 06:02:05.570893 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9137 06:02:05.583378 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9138 06:02:05.589987 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9139 06:02:05.601767 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9140 06:02:05.610775 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9141 06:02:05.613994 CPU_CLUSTER: 0 init finished in 81 msecs
9142 06:02:05.617173 Devices initialized
9143 06:02:05.620860 Show all devs... After init.
9144 06:02:05.621413 Root Device: enabled 1
9145 06:02:05.624148 CPU_CLUSTER: 0: enabled 1
9146 06:02:05.627477 CPU: 00: enabled 1
9147 06:02:05.630620 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9148 06:02:05.633942 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9149 06:02:05.637032 ELOG: NV offset 0x57f000 size 0x1000
9150 06:02:05.644252 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9151 06:02:05.650388 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9152 06:02:05.654372 ELOG: Event(17) added with size 13 at 2023-12-25 06:02:05 UTC
9153 06:02:05.660846 out: cmd=0x121: 03 db 21 01 00 00 00 00
9154 06:02:05.663750 in-header: 03 d7 00 00 2c 00 00 00
9155 06:02:05.673749 in-data: 8c 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9156 06:02:05.680319 ELOG: Event(A1) added with size 10 at 2023-12-25 06:02:05 UTC
9157 06:02:05.687040 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9158 06:02:05.693656 ELOG: Event(A0) added with size 9 at 2023-12-25 06:02:05 UTC
9159 06:02:05.696601 elog_add_boot_reason: Logged dev mode boot
9160 06:02:05.703602 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9161 06:02:05.704163 Finalize devices...
9162 06:02:05.706752 Devices finalized
9163 06:02:05.710025 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9164 06:02:05.713378 Writing coreboot table at 0xffe64000
9165 06:02:05.716264 0. 000000000010a000-0000000000113fff: RAMSTAGE
9166 06:02:05.723345 1. 0000000040000000-00000000400fffff: RAM
9167 06:02:05.726779 2. 0000000040100000-000000004032afff: RAMSTAGE
9168 06:02:05.729644 3. 000000004032b000-00000000545fffff: RAM
9169 06:02:05.732817 4. 0000000054600000-000000005465ffff: BL31
9170 06:02:05.736119 5. 0000000054660000-00000000ffe63fff: RAM
9171 06:02:05.742556 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9172 06:02:05.745930 7. 0000000100000000-000000013fffffff: RAM
9173 06:02:05.749545 Passing 5 GPIOs to payload:
9174 06:02:05.752829 NAME | PORT | POLARITY | VALUE
9175 06:02:05.759080 EC in RW | 0x000000aa | low | undefined
9176 06:02:05.763071 EC interrupt | 0x00000005 | low | undefined
9177 06:02:05.765906 TPM interrupt | 0x000000ab | high | undefined
9178 06:02:05.772603 SD card detect | 0x00000011 | high | undefined
9179 06:02:05.775812 speaker enable | 0x00000093 | high | undefined
9180 06:02:05.778819 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9181 06:02:05.782404 in-header: 03 f8 00 00 02 00 00 00
9182 06:02:05.785506 in-data: 03 00
9183 06:02:05.789070 ADC[4]: Raw value=669327 ID=5
9184 06:02:05.792377 ADC[3]: Raw value=212917 ID=1
9185 06:02:05.793004 RAM Code: 0x51
9186 06:02:05.795681 ADC[6]: Raw value=74778 ID=0
9187 06:02:05.799265 ADC[5]: Raw value=211444 ID=1
9188 06:02:05.799817 SKU Code: 0x1
9189 06:02:05.805683 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 97e2
9190 06:02:05.806247 coreboot table: 964 bytes.
9191 06:02:05.808568 IMD ROOT 0. 0xfffff000 0x00001000
9192 06:02:05.812307 IMD SMALL 1. 0xffffe000 0x00001000
9193 06:02:05.815468 RO MCACHE 2. 0xffffc000 0x00001104
9194 06:02:05.818663 CONSOLE 3. 0xfff7c000 0x00080000
9195 06:02:05.821846 FMAP 4. 0xfff7b000 0x00000452
9196 06:02:05.825299 TIME STAMP 5. 0xfff7a000 0x00000910
9197 06:02:05.828469 VBOOT WORK 6. 0xfff66000 0x00014000
9198 06:02:05.832076 RAMOOPS 7. 0xffe66000 0x00100000
9199 06:02:05.835228 COREBOOT 8. 0xffe64000 0x00002000
9200 06:02:05.838452 IMD small region:
9201 06:02:05.841409 IMD ROOT 0. 0xffffec00 0x00000400
9202 06:02:05.844801 VPD 1. 0xffffeb80 0x0000006c
9203 06:02:05.848211 MMC STATUS 2. 0xffffeb60 0x00000004
9204 06:02:05.854976 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9205 06:02:05.855531 Probing TPM: done!
9206 06:02:05.861656 Connected to device vid:did:rid of 1ae0:0028:00
9207 06:02:05.868410 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9208 06:02:05.871538 Initialized TPM device CR50 revision 0
9209 06:02:05.875011 Checking cr50 for pending updates
9210 06:02:05.880536 Reading cr50 TPM mode
9211 06:02:05.889118 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9212 06:02:05.895683 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9213 06:02:05.935976 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9214 06:02:05.939336 Checking segment from ROM address 0x40100000
9215 06:02:05.942932 Checking segment from ROM address 0x4010001c
9216 06:02:05.949266 Loading segment from ROM address 0x40100000
9217 06:02:05.949820 code (compression=0)
9218 06:02:05.958946 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9219 06:02:05.965666 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9220 06:02:05.966231 it's not compressed!
9221 06:02:05.972139 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9222 06:02:05.978736 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9223 06:02:05.996340 Loading segment from ROM address 0x4010001c
9224 06:02:05.996943 Entry Point 0x80000000
9225 06:02:05.999444 Loaded segments
9226 06:02:06.003017 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9227 06:02:06.009506 Jumping to boot code at 0x80000000(0xffe64000)
9228 06:02:06.016325 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9229 06:02:06.022678 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9230 06:02:06.030562 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9231 06:02:06.033879 Checking segment from ROM address 0x40100000
9232 06:02:06.037157 Checking segment from ROM address 0x4010001c
9233 06:02:06.043952 Loading segment from ROM address 0x40100000
9234 06:02:06.044523 code (compression=1)
9235 06:02:06.050675 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9236 06:02:06.060297 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9237 06:02:06.060886 using LZMA
9238 06:02:06.068867 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9239 06:02:06.075715 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9240 06:02:06.078885 Loading segment from ROM address 0x4010001c
9241 06:02:06.079362 Entry Point 0x54601000
9242 06:02:06.082419 Loaded segments
9243 06:02:06.085540 NOTICE: MT8192 bl31_setup
9244 06:02:06.092470 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9245 06:02:06.095919 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9246 06:02:06.099375 WARNING: region 0:
9247 06:02:06.102361 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9248 06:02:06.102828 WARNING: region 1:
9249 06:02:06.108963 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9250 06:02:06.112467 WARNING: region 2:
9251 06:02:06.116123 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9252 06:02:06.119346 WARNING: region 3:
9253 06:02:06.122433 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9254 06:02:06.125723 WARNING: region 4:
9255 06:02:06.132313 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9256 06:02:06.132904 WARNING: region 5:
9257 06:02:06.135385 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9258 06:02:06.139151 WARNING: region 6:
9259 06:02:06.142217 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9260 06:02:06.145440 WARNING: region 7:
9261 06:02:06.148637 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9262 06:02:06.155388 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9263 06:02:06.159005 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9264 06:02:06.162215 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9265 06:02:06.168634 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9266 06:02:06.172342 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9267 06:02:06.179027 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9268 06:02:06.182227 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9269 06:02:06.185619 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9270 06:02:06.192461 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9271 06:02:06.195210 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9272 06:02:06.198757 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9273 06:02:06.205492 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9274 06:02:06.208682 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9275 06:02:06.215692 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9276 06:02:06.218550 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9277 06:02:06.221903 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9278 06:02:06.228877 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9279 06:02:06.231829 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9280 06:02:06.235235 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9281 06:02:06.241940 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9282 06:02:06.245411 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9283 06:02:06.251642 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9284 06:02:06.255067 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9285 06:02:06.258502 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9286 06:02:06.265157 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9287 06:02:06.268083 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9288 06:02:06.275040 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9289 06:02:06.278235 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9290 06:02:06.284793 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9291 06:02:06.288170 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9292 06:02:06.291354 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9293 06:02:06.298153 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9294 06:02:06.301516 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9295 06:02:06.304621 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9296 06:02:06.308490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9297 06:02:06.314688 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9298 06:02:06.317803 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9299 06:02:06.321233 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9300 06:02:06.324835 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9301 06:02:06.331268 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9302 06:02:06.334737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9303 06:02:06.337966 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9304 06:02:06.340955 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9305 06:02:06.347820 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9306 06:02:06.351141 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9307 06:02:06.354633 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9308 06:02:06.361184 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9309 06:02:06.364337 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9310 06:02:06.367637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9311 06:02:06.374575 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9312 06:02:06.378001 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9313 06:02:06.381292 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9314 06:02:06.387876 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9315 06:02:06.391122 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9316 06:02:06.397477 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9317 06:02:06.401116 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9318 06:02:06.407745 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9319 06:02:06.411345 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9320 06:02:06.417470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9321 06:02:06.421096 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9322 06:02:06.424258 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9323 06:02:06.430951 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9324 06:02:06.434326 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9325 06:02:06.440843 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9326 06:02:06.444029 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9327 06:02:06.451024 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9328 06:02:06.453967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9329 06:02:06.457356 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9330 06:02:06.463961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9331 06:02:06.467564 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9332 06:02:06.474157 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9333 06:02:06.477629 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9334 06:02:06.484300 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9335 06:02:06.487624 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9336 06:02:06.490531 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9337 06:02:06.497515 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9338 06:02:06.500458 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9339 06:02:06.507639 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9340 06:02:06.510429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9341 06:02:06.517283 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9342 06:02:06.520498 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9343 06:02:06.527426 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9344 06:02:06.530399 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9345 06:02:06.534079 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9346 06:02:06.540553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9347 06:02:06.544094 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9348 06:02:06.550555 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9349 06:02:06.554046 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9350 06:02:06.560539 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9351 06:02:06.564085 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9352 06:02:06.567208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9353 06:02:06.573622 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9354 06:02:06.576754 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9355 06:02:06.583804 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9356 06:02:06.587123 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9357 06:02:06.593474 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9358 06:02:06.597067 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9359 06:02:06.600114 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9360 06:02:06.603221 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9361 06:02:06.610093 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9362 06:02:06.613272 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9363 06:02:06.616562 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9364 06:02:06.623273 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9365 06:02:06.626681 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9366 06:02:06.633162 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9367 06:02:06.636480 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9368 06:02:06.639912 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9369 06:02:06.646750 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9370 06:02:06.650043 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9371 06:02:06.656828 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9372 06:02:06.659796 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9373 06:02:06.663296 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9374 06:02:06.669801 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9375 06:02:06.673135 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9376 06:02:06.679940 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9377 06:02:06.683156 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9378 06:02:06.686536 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9379 06:02:06.693176 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9380 06:02:06.696407 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9381 06:02:06.699789 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9382 06:02:06.702890 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9383 06:02:06.709514 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9384 06:02:06.712940 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9385 06:02:06.716400 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9386 06:02:06.723110 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9387 06:02:06.726469 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9388 06:02:06.729512 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9389 06:02:06.736240 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9390 06:02:06.739560 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9391 06:02:06.745849 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9392 06:02:06.749308 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9393 06:02:06.752745 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9394 06:02:06.759454 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9395 06:02:06.762855 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9396 06:02:06.766057 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9397 06:02:06.772659 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9398 06:02:06.775903 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9399 06:02:06.782714 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9400 06:02:06.786119 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9401 06:02:06.789432 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9402 06:02:06.796203 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9403 06:02:06.799091 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9404 06:02:06.806174 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9405 06:02:06.809399 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9406 06:02:06.812631 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9407 06:02:06.819017 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9408 06:02:06.822434 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9409 06:02:06.829393 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9410 06:02:06.832533 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9411 06:02:06.835846 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9412 06:02:06.842375 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9413 06:02:06.845586 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9414 06:02:06.848838 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9415 06:02:06.856208 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9416 06:02:06.859116 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9417 06:02:06.865631 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9418 06:02:06.869320 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9419 06:02:06.872424 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9420 06:02:06.879041 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9421 06:02:06.882140 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9422 06:02:06.889013 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9423 06:02:06.892393 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9424 06:02:06.895252 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9425 06:02:06.901993 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9426 06:02:06.905416 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9427 06:02:06.912262 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9428 06:02:06.915342 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9429 06:02:06.918351 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9430 06:02:06.925085 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9431 06:02:06.928594 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9432 06:02:06.935202 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9433 06:02:06.938167 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9434 06:02:06.941420 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9435 06:02:06.948283 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9436 06:02:06.951416 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9437 06:02:06.958026 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9438 06:02:06.961314 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9439 06:02:06.964604 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9440 06:02:06.971415 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9441 06:02:06.974576 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9442 06:02:06.981399 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9443 06:02:06.984501 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9444 06:02:06.987813 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9445 06:02:06.994425 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9446 06:02:06.997786 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9447 06:02:07.004500 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9448 06:02:07.007751 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9449 06:02:07.010959 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9450 06:02:07.017462 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9451 06:02:07.020742 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9452 06:02:07.027453 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9453 06:02:07.030581 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9454 06:02:07.037386 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9455 06:02:07.040772 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9456 06:02:07.043858 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9457 06:02:07.050754 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9458 06:02:07.053563 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9459 06:02:07.060348 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9460 06:02:07.063836 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9461 06:02:07.070449 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9462 06:02:07.073547 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9463 06:02:07.077048 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9464 06:02:07.083511 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9465 06:02:07.086739 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9466 06:02:07.093302 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9467 06:02:07.096927 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9468 06:02:07.103291 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9469 06:02:07.106590 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9470 06:02:07.110074 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9471 06:02:07.116478 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9472 06:02:07.119836 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9473 06:02:07.126180 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9474 06:02:07.129573 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9475 06:02:07.136605 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9476 06:02:07.139746 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9477 06:02:07.142613 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9478 06:02:07.149294 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9479 06:02:07.152496 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9480 06:02:07.159180 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9481 06:02:07.162473 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9482 06:02:07.169552 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9483 06:02:07.172577 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9484 06:02:07.176028 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9485 06:02:07.182414 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9486 06:02:07.185716 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9487 06:02:07.192638 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9488 06:02:07.195774 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9489 06:02:07.199060 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9490 06:02:07.205674 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9491 06:02:07.209002 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9492 06:02:07.212601 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9493 06:02:07.215580 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9494 06:02:07.222246 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9495 06:02:07.225286 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9496 06:02:07.228877 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9497 06:02:07.235412 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9498 06:02:07.238588 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9499 06:02:07.245206 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9500 06:02:07.249165 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9501 06:02:07.251827 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9502 06:02:07.258393 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9503 06:02:07.261984 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9504 06:02:07.265287 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9505 06:02:07.271329 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9506 06:02:07.274614 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9507 06:02:07.281548 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9508 06:02:07.284551 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9509 06:02:07.287726 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9510 06:02:07.294680 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9511 06:02:07.297645 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9512 06:02:07.301189 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9513 06:02:07.307887 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9514 06:02:07.311513 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9515 06:02:07.314433 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9516 06:02:07.320688 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9517 06:02:07.324210 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9518 06:02:07.331150 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9519 06:02:07.334180 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9520 06:02:07.337390 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9521 06:02:07.343870 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9522 06:02:07.347492 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9523 06:02:07.353888 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9524 06:02:07.357104 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9525 06:02:07.360585 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9526 06:02:07.367169 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9527 06:02:07.370257 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9528 06:02:07.373600 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9529 06:02:07.380558 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9530 06:02:07.383535 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9531 06:02:07.386781 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9532 06:02:07.393503 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9533 06:02:07.397140 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9534 06:02:07.400126 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9535 06:02:07.403927 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9536 06:02:07.407150 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9537 06:02:07.413686 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9538 06:02:07.416958 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9539 06:02:07.420149 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9540 06:02:07.426571 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9541 06:02:07.429791 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9542 06:02:07.433377 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9543 06:02:07.436895 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9544 06:02:07.442929 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9545 06:02:07.446250 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9546 06:02:07.453417 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9547 06:02:07.456458 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9548 06:02:07.462796 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9549 06:02:07.465856 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9550 06:02:07.469513 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9551 06:02:07.475941 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9552 06:02:07.479328 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9553 06:02:07.486086 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9554 06:02:07.489340 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9555 06:02:07.492362 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9556 06:02:07.499450 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9557 06:02:07.502592 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9558 06:02:07.509166 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9559 06:02:07.512513 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9560 06:02:07.518736 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9561 06:02:07.522120 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9562 06:02:07.525584 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9563 06:02:07.532133 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9564 06:02:07.535111 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9565 06:02:07.541927 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9566 06:02:07.545062 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9567 06:02:07.548629 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9568 06:02:07.555326 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9569 06:02:07.558774 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9570 06:02:07.565143 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9571 06:02:07.568467 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9572 06:02:07.575961 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9573 06:02:07.578171 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9574 06:02:07.581336 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9575 06:02:07.587989 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9576 06:02:07.591633 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9577 06:02:07.598103 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9578 06:02:07.601485 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9579 06:02:07.608359 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9580 06:02:07.611311 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9581 06:02:07.614501 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9582 06:02:07.621562 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9583 06:02:07.624361 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9584 06:02:07.630772 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9585 06:02:07.634148 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9586 06:02:07.637643 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9587 06:02:07.643831 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9588 06:02:07.647573 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9589 06:02:07.654330 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9590 06:02:07.657278 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9591 06:02:07.660483 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9592 06:02:07.667479 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9593 06:02:07.670299 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9594 06:02:07.677360 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9595 06:02:07.680349 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9596 06:02:07.687014 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9597 06:02:07.690157 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9598 06:02:07.697012 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9599 06:02:07.699944 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9600 06:02:07.703820 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9601 06:02:07.710225 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9602 06:02:07.713382 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9603 06:02:07.720045 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9604 06:02:07.723586 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9605 06:02:07.726464 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9606 06:02:07.733053 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9607 06:02:07.736834 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9608 06:02:07.743092 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9609 06:02:07.746168 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9610 06:02:07.749671 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9611 06:02:07.756396 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9612 06:02:07.760002 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9613 06:02:07.766084 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9614 06:02:07.769369 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9615 06:02:07.773050 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9616 06:02:07.779288 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9617 06:02:07.783061 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9618 06:02:07.789416 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9619 06:02:07.792808 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9620 06:02:07.799423 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9621 06:02:07.802499 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9622 06:02:07.809101 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9623 06:02:07.812271 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9624 06:02:07.815930 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9625 06:02:07.822139 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9626 06:02:07.825512 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9627 06:02:07.832504 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9628 06:02:07.835609 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9629 06:02:07.842175 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9630 06:02:07.845368 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9631 06:02:07.848898 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9632 06:02:07.855669 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9633 06:02:07.858913 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9634 06:02:07.865400 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9635 06:02:07.868430 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9636 06:02:07.875624 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9637 06:02:07.878413 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9638 06:02:07.885188 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9639 06:02:07.888406 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9640 06:02:07.891809 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9641 06:02:07.898418 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9642 06:02:07.901662 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9643 06:02:07.908473 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9644 06:02:07.911872 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9645 06:02:07.918371 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9646 06:02:07.921531 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9647 06:02:07.928216 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9648 06:02:07.931249 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9649 06:02:07.934561 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9650 06:02:07.941512 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9651 06:02:07.944619 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9652 06:02:07.951666 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9653 06:02:07.954680 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9654 06:02:07.961450 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9655 06:02:07.964396 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9656 06:02:07.971269 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9657 06:02:07.974409 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9658 06:02:07.977911 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9659 06:02:07.984040 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9660 06:02:07.987794 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9661 06:02:07.994282 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9662 06:02:07.997611 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9663 06:02:08.004350 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9664 06:02:08.007495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9665 06:02:08.010803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9666 06:02:08.017395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9667 06:02:08.020750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9668 06:02:08.027026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9669 06:02:08.030502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9670 06:02:08.036907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9671 06:02:08.040502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9672 06:02:08.047292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9673 06:02:08.050828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9674 06:02:08.057037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9675 06:02:08.060192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9676 06:02:08.066817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9677 06:02:08.070263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9678 06:02:08.076793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9679 06:02:08.079880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9680 06:02:08.086977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9681 06:02:08.090010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9682 06:02:08.096797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9683 06:02:08.100208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9684 06:02:08.106429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9685 06:02:08.109632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9686 06:02:08.116365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9687 06:02:08.119675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9688 06:02:08.126229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9689 06:02:08.129377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9690 06:02:08.136063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9691 06:02:08.140115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9692 06:02:08.145862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9693 06:02:08.149016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9694 06:02:08.156029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9695 06:02:08.159070 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9696 06:02:08.165494 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9697 06:02:08.165964 INFO: [APUAPC] vio 0
9698 06:02:08.172386 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9699 06:02:08.176053 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9700 06:02:08.179330 INFO: [APUAPC] D0_APC_0: 0x400510
9701 06:02:08.182392 INFO: [APUAPC] D0_APC_1: 0x0
9702 06:02:08.185443 INFO: [APUAPC] D0_APC_2: 0x1540
9703 06:02:08.188986 INFO: [APUAPC] D0_APC_3: 0x0
9704 06:02:08.192639 INFO: [APUAPC] D1_APC_0: 0xffffffff
9705 06:02:08.195653 INFO: [APUAPC] D1_APC_1: 0xffffffff
9706 06:02:08.199086 INFO: [APUAPC] D1_APC_2: 0x3fffff
9707 06:02:08.202245 INFO: [APUAPC] D1_APC_3: 0x0
9708 06:02:08.205670 INFO: [APUAPC] D2_APC_0: 0xffffffff
9709 06:02:08.208911 INFO: [APUAPC] D2_APC_1: 0xffffffff
9710 06:02:08.212464 INFO: [APUAPC] D2_APC_2: 0x3fffff
9711 06:02:08.215403 INFO: [APUAPC] D2_APC_3: 0x0
9712 06:02:08.218728 INFO: [APUAPC] D3_APC_0: 0xffffffff
9713 06:02:08.222135 INFO: [APUAPC] D3_APC_1: 0xffffffff
9714 06:02:08.225544 INFO: [APUAPC] D3_APC_2: 0x3fffff
9715 06:02:08.228750 INFO: [APUAPC] D3_APC_3: 0x0
9716 06:02:08.231983 INFO: [APUAPC] D4_APC_0: 0xffffffff
9717 06:02:08.235416 INFO: [APUAPC] D4_APC_1: 0xffffffff
9718 06:02:08.238470 INFO: [APUAPC] D4_APC_2: 0x3fffff
9719 06:02:08.242045 INFO: [APUAPC] D4_APC_3: 0x0
9720 06:02:08.245071 INFO: [APUAPC] D5_APC_0: 0xffffffff
9721 06:02:08.248551 INFO: [APUAPC] D5_APC_1: 0xffffffff
9722 06:02:08.251424 INFO: [APUAPC] D5_APC_2: 0x3fffff
9723 06:02:08.254938 INFO: [APUAPC] D5_APC_3: 0x0
9724 06:02:08.258045 INFO: [APUAPC] D6_APC_0: 0xffffffff
9725 06:02:08.261316 INFO: [APUAPC] D6_APC_1: 0xffffffff
9726 06:02:08.264987 INFO: [APUAPC] D6_APC_2: 0x3fffff
9727 06:02:08.265552 INFO: [APUAPC] D6_APC_3: 0x0
9728 06:02:08.268034 INFO: [APUAPC] D7_APC_0: 0xffffffff
9729 06:02:08.274811 INFO: [APUAPC] D7_APC_1: 0xffffffff
9730 06:02:08.278235 INFO: [APUAPC] D7_APC_2: 0x3fffff
9731 06:02:08.278812 INFO: [APUAPC] D7_APC_3: 0x0
9732 06:02:08.281167 INFO: [APUAPC] D8_APC_0: 0xffffffff
9733 06:02:08.288038 INFO: [APUAPC] D8_APC_1: 0xffffffff
9734 06:02:08.291054 INFO: [APUAPC] D8_APC_2: 0x3fffff
9735 06:02:08.291640 INFO: [APUAPC] D8_APC_3: 0x0
9736 06:02:08.294343 INFO: [APUAPC] D9_APC_0: 0xffffffff
9737 06:02:08.297617 INFO: [APUAPC] D9_APC_1: 0xffffffff
9738 06:02:08.300928 INFO: [APUAPC] D9_APC_2: 0x3fffff
9739 06:02:08.304483 INFO: [APUAPC] D9_APC_3: 0x0
9740 06:02:08.307530 INFO: [APUAPC] D10_APC_0: 0xffffffff
9741 06:02:08.311331 INFO: [APUAPC] D10_APC_1: 0xffffffff
9742 06:02:08.314263 INFO: [APUAPC] D10_APC_2: 0x3fffff
9743 06:02:08.317670 INFO: [APUAPC] D10_APC_3: 0x0
9744 06:02:08.320803 INFO: [APUAPC] D11_APC_0: 0xffffffff
9745 06:02:08.324487 INFO: [APUAPC] D11_APC_1: 0xffffffff
9746 06:02:08.330963 INFO: [APUAPC] D11_APC_2: 0x3fffff
9747 06:02:08.331573 INFO: [APUAPC] D11_APC_3: 0x0
9748 06:02:08.334082 INFO: [APUAPC] D12_APC_0: 0xffffffff
9749 06:02:08.340737 INFO: [APUAPC] D12_APC_1: 0xffffffff
9750 06:02:08.343979 INFO: [APUAPC] D12_APC_2: 0x3fffff
9751 06:02:08.344607 INFO: [APUAPC] D12_APC_3: 0x0
9752 06:02:08.347108 INFO: [APUAPC] D13_APC_0: 0xffffffff
9753 06:02:08.353954 INFO: [APUAPC] D13_APC_1: 0xffffffff
9754 06:02:08.357161 INFO: [APUAPC] D13_APC_2: 0x3fffff
9755 06:02:08.357635 INFO: [APUAPC] D13_APC_3: 0x0
9756 06:02:08.363798 INFO: [APUAPC] D14_APC_0: 0xffffffff
9757 06:02:08.367291 INFO: [APUAPC] D14_APC_1: 0xffffffff
9758 06:02:08.370794 INFO: [APUAPC] D14_APC_2: 0x3fffff
9759 06:02:08.371645 INFO: [APUAPC] D14_APC_3: 0x0
9760 06:02:08.377023 INFO: [APUAPC] D15_APC_0: 0xffffffff
9761 06:02:08.380448 INFO: [APUAPC] D15_APC_1: 0xffffffff
9762 06:02:08.383558 INFO: [APUAPC] D15_APC_2: 0x3fffff
9763 06:02:08.386862 INFO: [APUAPC] D15_APC_3: 0x0
9764 06:02:08.387333 INFO: [APUAPC] APC_CON: 0x4
9765 06:02:08.390176 INFO: [NOCDAPC] D0_APC_0: 0x0
9766 06:02:08.393640 INFO: [NOCDAPC] D0_APC_1: 0x0
9767 06:02:08.396829 INFO: [NOCDAPC] D1_APC_0: 0x0
9768 06:02:08.400575 INFO: [NOCDAPC] D1_APC_1: 0xfff
9769 06:02:08.403391 INFO: [NOCDAPC] D2_APC_0: 0x0
9770 06:02:08.406655 INFO: [NOCDAPC] D2_APC_1: 0xfff
9771 06:02:08.410312 INFO: [NOCDAPC] D3_APC_0: 0x0
9772 06:02:08.413335 INFO: [NOCDAPC] D3_APC_1: 0xfff
9773 06:02:08.416808 INFO: [NOCDAPC] D4_APC_0: 0x0
9774 06:02:08.417270 INFO: [NOCDAPC] D4_APC_1: 0xfff
9775 06:02:08.419944 INFO: [NOCDAPC] D5_APC_0: 0x0
9776 06:02:08.423027 INFO: [NOCDAPC] D5_APC_1: 0xfff
9777 06:02:08.426457 INFO: [NOCDAPC] D6_APC_0: 0x0
9778 06:02:08.429936 INFO: [NOCDAPC] D6_APC_1: 0xfff
9779 06:02:08.433155 INFO: [NOCDAPC] D7_APC_0: 0x0
9780 06:02:08.436383 INFO: [NOCDAPC] D7_APC_1: 0xfff
9781 06:02:08.439904 INFO: [NOCDAPC] D8_APC_0: 0x0
9782 06:02:08.443012 INFO: [NOCDAPC] D8_APC_1: 0xfff
9783 06:02:08.446175 INFO: [NOCDAPC] D9_APC_0: 0x0
9784 06:02:08.449746 INFO: [NOCDAPC] D9_APC_1: 0xfff
9785 06:02:08.452912 INFO: [NOCDAPC] D10_APC_0: 0x0
9786 06:02:08.453374 INFO: [NOCDAPC] D10_APC_1: 0xfff
9787 06:02:08.456401 INFO: [NOCDAPC] D11_APC_0: 0x0
9788 06:02:08.459692 INFO: [NOCDAPC] D11_APC_1: 0xfff
9789 06:02:08.463066 INFO: [NOCDAPC] D12_APC_0: 0x0
9790 06:02:08.465903 INFO: [NOCDAPC] D12_APC_1: 0xfff
9791 06:02:08.469437 INFO: [NOCDAPC] D13_APC_0: 0x0
9792 06:02:08.472886 INFO: [NOCDAPC] D13_APC_1: 0xfff
9793 06:02:08.476341 INFO: [NOCDAPC] D14_APC_0: 0x0
9794 06:02:08.479258 INFO: [NOCDAPC] D14_APC_1: 0xfff
9795 06:02:08.482721 INFO: [NOCDAPC] D15_APC_0: 0x0
9796 06:02:08.485900 INFO: [NOCDAPC] D15_APC_1: 0xfff
9797 06:02:08.489300 INFO: [NOCDAPC] APC_CON: 0x4
9798 06:02:08.492670 INFO: [APUAPC] set_apusys_apc done
9799 06:02:08.495782 INFO: [DEVAPC] devapc_init done
9800 06:02:08.499044 INFO: GICv3 without legacy support detected.
9801 06:02:08.502552 INFO: ARM GICv3 driver initialized in EL3
9802 06:02:08.506113 INFO: Maximum SPI INTID supported: 639
9803 06:02:08.509285 INFO: BL31: Initializing runtime services
9804 06:02:08.515573 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9805 06:02:08.518836 INFO: SPM: enable CPC mode
9806 06:02:08.526030 INFO: mcdi ready for mcusys-off-idle and system suspend
9807 06:02:08.529119 INFO: BL31: Preparing for EL3 exit to normal world
9808 06:02:08.532272 INFO: Entry point address = 0x80000000
9809 06:02:08.535436 INFO: SPSR = 0x8
9810 06:02:08.540636
9811 06:02:08.541423
9812 06:02:08.541921
9813 06:02:08.543677 Starting depthcharge on Spherion...
9814 06:02:08.544237
9815 06:02:08.544668 Wipe memory regions:
9816 06:02:08.545092
9817 06:02:08.547847 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9818 06:02:08.548377 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9819 06:02:08.548879 Setting prompt string to ['asurada:']
9820 06:02:08.549608 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9821 06:02:08.550635 [0x00000040000000, 0x00000054600000)
9822 06:02:08.669340
9823 06:02:08.669888 [0x00000054660000, 0x00000080000000)
9824 06:02:08.929808
9825 06:02:08.930371 [0x000000821a7280, 0x000000ffe64000)
9826 06:02:09.674881
9827 06:02:09.675445 [0x00000100000000, 0x00000140000000)
9828 06:02:10.056038
9829 06:02:10.059262 Initializing XHCI USB controller at 0x11200000.
9830 06:02:11.096814
9831 06:02:11.100151 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9832 06:02:11.100754
9833 06:02:11.101133
9834 06:02:11.101470
9835 06:02:11.102282 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9837 06:02:11.203549 asurada: tftpboot 192.168.201.1 12379472/tftp-deploy-7wlokvlu/kernel/image.itb 12379472/tftp-deploy-7wlokvlu/kernel/cmdline
9838 06:02:11.204211 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9839 06:02:11.204837 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9840 06:02:11.209020 tftpboot 192.168.201.1 12379472/tftp-deploy-7wlokvlu/kernel/image.ittp-deploy-7wlokvlu/kernel/cmdline
9841 06:02:11.209518
9842 06:02:11.209889 Waiting for link
9843 06:02:11.369383
9844 06:02:11.369941 R8152: Initializing
9845 06:02:11.370313
9846 06:02:11.373078 Version 9 (ocp_data = 6010)
9847 06:02:11.373655
9848 06:02:11.376447 R8152: Done initializing
9849 06:02:11.377040
9850 06:02:11.377417 Adding net device
9851 06:02:13.373874
9852 06:02:13.374456 done.
9853 06:02:13.375018
9854 06:02:13.375384 MAC: 00:e0:4c:68:03:bd
9855 06:02:13.375721
9856 06:02:13.376782 Sending DHCP discover... done.
9857 06:02:13.377255
9858 06:02:13.380202 Waiting for reply... done.
9859 06:02:13.380662
9860 06:02:13.383392 Sending DHCP request... done.
9861 06:02:13.383864
9862 06:02:13.386735 Waiting for reply... done.
9863 06:02:13.387186
9864 06:02:13.387542 My ip is 192.168.201.16
9865 06:02:13.387878
9866 06:02:13.389972 The DHCP server ip is 192.168.201.1
9867 06:02:13.390426
9868 06:02:13.397000 TFTP server IP predefined by user: 192.168.201.1
9869 06:02:13.397555
9870 06:02:13.403665 Bootfile predefined by user: 12379472/tftp-deploy-7wlokvlu/kernel/image.itb
9871 06:02:13.404226
9872 06:02:13.406582 Sending tftp read request... done.
9873 06:02:13.406973
9874 06:02:13.412952 Waiting for the transfer...
9875 06:02:13.413447
9876 06:02:13.791545 00000000 ################################################################
9877 06:02:13.791694
9878 06:02:14.079626 00080000 ################################################################
9879 06:02:14.079767
9880 06:02:14.361225 00100000 ################################################################
9881 06:02:14.361358
9882 06:02:14.650331 00180000 ################################################################
9883 06:02:14.650475
9884 06:02:14.941586 00200000 ################################################################
9885 06:02:14.941723
9886 06:02:15.241371 00280000 ################################################################
9887 06:02:15.241518
9888 06:02:15.613208 00300000 ################################################################
9889 06:02:15.613732
9890 06:02:15.962827 00380000 ################################################################
9891 06:02:15.962970
9892 06:02:16.328373 00400000 ################################################################
9893 06:02:16.328939
9894 06:02:16.696082 00480000 ################################################################
9895 06:02:16.696622
9896 06:02:17.068495 00500000 ################################################################
9897 06:02:17.069203
9898 06:02:17.447578 00580000 ################################################################
9899 06:02:17.447753
9900 06:02:17.744049 00600000 ################################################################
9901 06:02:17.744187
9902 06:02:18.045653 00680000 ################################################################
9903 06:02:18.045792
9904 06:02:18.335395 00700000 ################################################################
9905 06:02:18.335532
9906 06:02:18.614619 00780000 ################################################################
9907 06:02:18.614786
9908 06:02:18.895058 00800000 ################################################################
9909 06:02:18.895224
9910 06:02:19.175105 00880000 ################################################################
9911 06:02:19.175272
9912 06:02:19.455737 00900000 ################################################################
9913 06:02:19.455877
9914 06:02:19.733672 00980000 ################################################################
9915 06:02:19.733842
9916 06:02:20.029642 00a00000 ################################################################
9917 06:02:20.029782
9918 06:02:20.312632 00a80000 ################################################################
9919 06:02:20.312821
9920 06:02:20.593465 00b00000 ################################################################
9921 06:02:20.593633
9922 06:02:20.880956 00b80000 ################################################################
9923 06:02:20.881098
9924 06:02:21.216976 00c00000 ################################################################
9925 06:02:21.217511
9926 06:02:21.599385 00c80000 ################################################################
9927 06:02:21.599920
9928 06:02:21.926262 00d00000 ################################################################
9929 06:02:21.926410
9930 06:02:22.216447 00d80000 ################################################################
9931 06:02:22.216607
9932 06:02:22.601212 00e00000 ################################################################
9933 06:02:22.601723
9934 06:02:22.986773 00e80000 ################################################################
9935 06:02:22.987384
9936 06:02:23.377252 00f00000 ################################################################
9937 06:02:23.377777
9938 06:02:23.667861 00f80000 ################################################################
9939 06:02:23.668025
9940 06:02:23.970476 01000000 ################################################################
9941 06:02:23.971192
9942 06:02:24.388005 01080000 ################################################################
9943 06:02:24.388552
9944 06:02:24.755586 01100000 ################################################################
9945 06:02:24.755729
9946 06:02:25.050610 01180000 ################################################################
9947 06:02:25.050760
9948 06:02:25.442574 01200000 ################################################################
9949 06:02:25.443249
9950 06:02:25.774869 01280000 ################################################################
9951 06:02:25.775006
9952 06:02:26.075921 01300000 ################################################################
9953 06:02:26.076060
9954 06:02:26.376051 01380000 ################################################################
9955 06:02:26.376195
9956 06:02:26.752048 01400000 ################################################################
9957 06:02:26.752560
9958 06:02:27.128223 01480000 ################################################################
9959 06:02:27.128773
9960 06:02:27.509889 01500000 ################################################################
9961 06:02:27.510412
9962 06:02:27.889174 01580000 ################################################################
9963 06:02:27.889686
9964 06:02:28.274181 01600000 ################################################################
9965 06:02:28.274700
9966 06:02:28.654144 01680000 ################################################################
9967 06:02:28.654664
9968 06:02:29.046674 01700000 ################################################################
9969 06:02:29.047182
9970 06:02:29.433779 01780000 ################################################################
9971 06:02:29.434332
9972 06:02:29.810671 01800000 ################################################################
9973 06:02:29.811216
9974 06:02:30.190419 01880000 ################################################################
9975 06:02:30.191009
9976 06:02:30.573635 01900000 ################################################################
9977 06:02:30.574284
9978 06:02:30.962396 01980000 ################################################################
9979 06:02:30.962938
9980 06:02:31.358177 01a00000 ################################################################
9981 06:02:31.358694
9982 06:02:31.754410 01a80000 ################################################################
9983 06:02:31.754926
9984 06:02:32.141436 01b00000 ################################################################
9985 06:02:32.141994
9986 06:02:32.521831 01b80000 ################################################################
9987 06:02:32.522399
9988 06:02:32.908466 01c00000 ################################################################
9989 06:02:32.909062
9990 06:02:33.215285 01c80000 ################################################### done.
9991 06:02:33.215833
9992 06:02:33.218704 The bootfile was 30295122 bytes long.
9993 06:02:33.219171
9994 06:02:33.222220 Sending tftp read request... done.
9995 06:02:33.222712
9996 06:02:33.225427 Waiting for the transfer...
9997 06:02:33.225886
9998 06:02:33.226248 00000000 # done.
9999 06:02:33.226593
10000 06:02:33.235437 Command line loaded dynamically from TFTP file: 12379472/tftp-deploy-7wlokvlu/kernel/cmdline
10001 06:02:33.235859
10002 06:02:33.255220 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12379472/extract-nfsrootfs-l133z4kz,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10003 06:02:33.258560
10004 06:02:33.258982 Loading FIT.
10005 06:02:33.259312
10006 06:02:33.262069 Image ramdisk-1 has 18763977 bytes.
10007 06:02:33.262592
10008 06:02:33.265095 Image fdt-1 has 47278 bytes.
10009 06:02:33.265511
10010 06:02:33.265843 Image kernel-1 has 11481830 bytes.
10011 06:02:33.268415
10012 06:02:33.275019 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10013 06:02:33.275445
10014 06:02:33.295479 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10015 06:02:33.296020
10016 06:02:33.298416 Choosing best match conf-1 for compat google,spherion-rev3.
10017 06:02:33.303253
10018 06:02:33.307507 Connected to device vid:did:rid of 1ae0:0028:00
10019 06:02:33.314254
10020 06:02:33.317523 tpm_get_response: command 0x17b, return code 0x0
10021 06:02:33.317987
10022 06:02:33.320799 ec_init: CrosEC protocol v3 supported (256, 248)
10023 06:02:33.325139
10024 06:02:33.328687 tpm_cleanup: add release locality here.
10025 06:02:33.329314
10026 06:02:33.329707 Shutting down all USB controllers.
10027 06:02:33.331663
10028 06:02:33.332123 Removing current net device
10029 06:02:33.332492
10030 06:02:33.338303 Exiting depthcharge with code 4 at timestamp: 53044435
10031 06:02:33.338860
10032 06:02:33.341512 LZMA decompressing kernel-1 to 0x821a6718
10033 06:02:33.341982
10034 06:02:33.344971 LZMA decompressing kernel-1 to 0x40000000
10035 06:02:34.781106
10036 06:02:34.781724 jumping to kernel
10037 06:02:34.783523 end: 2.2.4 bootloader-commands (duration 00:00:26) [common]
10038 06:02:34.784049 start: 2.2.5 auto-login-action (timeout 00:04:00) [common]
10039 06:02:34.784454 Setting prompt string to ['Linux version [0-9]']
10040 06:02:34.784912 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10041 06:02:34.785311 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10042 06:02:34.831525
10043 06:02:34.834420 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10044 06:02:34.838425 start: 2.2.5.1 login-action (timeout 00:04:00) [common]
10045 06:02:34.839002 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10046 06:02:34.839399 Setting prompt string to []
10047 06:02:34.839826 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10048 06:02:34.840211 Using line separator: #'\n'#
10049 06:02:34.840538 No login prompt set.
10050 06:02:34.840953 Parsing kernel messages
10051 06:02:34.841272 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10052 06:02:34.841857 [login-action] Waiting for messages, (timeout 00:04:00)
10053 06:02:34.857637 [ 0.000000] Linux version 6.1.67-cip12 (KernelCI@build-j59664-arm64-gcc-10-defconfig-arm64-chromebook-fgc24) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023
10054 06:02:34.860884 [ 0.000000] random: crng init done
10055 06:02:34.867533 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10056 06:02:34.870966 [ 0.000000] efi: UEFI not found.
10057 06:02:34.877033 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10058 06:02:34.887251 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10059 06:02:34.893824 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10060 06:02:34.903956 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10061 06:02:34.910538 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10062 06:02:34.917177 [ 0.000000] printk: bootconsole [mtk8250] enabled
10063 06:02:34.923566 [ 0.000000] NUMA: No NUMA configuration found
10064 06:02:34.930057 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10065 06:02:34.933435 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d3a00-0x13f7d5fff]
10066 06:02:34.937094 [ 0.000000] Zone ranges:
10067 06:02:34.943645 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10068 06:02:34.946783 [ 0.000000] DMA32 empty
10069 06:02:34.953397 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10070 06:02:34.956782 [ 0.000000] Movable zone start for each node
10071 06:02:34.960271 [ 0.000000] Early memory node ranges
10072 06:02:34.966430 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10073 06:02:34.973278 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10074 06:02:34.979856 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10075 06:02:34.986329 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10076 06:02:34.993139 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10077 06:02:34.999306 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10078 06:02:35.029918 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10079 06:02:35.036280 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10080 06:02:35.043273 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10081 06:02:35.046082 [ 0.000000] psci: probing for conduit method from DT.
10082 06:02:35.052687 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10083 06:02:35.055918 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10084 06:02:35.062660 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10085 06:02:35.066069 [ 0.000000] psci: SMC Calling Convention v1.2
10086 06:02:35.072784 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10087 06:02:35.076005 [ 0.000000] Detected VIPT I-cache on CPU0
10088 06:02:35.082518 [ 0.000000] CPU features: detected: GIC system register CPU interface
10089 06:02:35.089206 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10090 06:02:35.095915 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10091 06:02:35.102132 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10092 06:02:35.112614 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10093 06:02:35.118596 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10094 06:02:35.121782 [ 0.000000] alternatives: applying boot alternatives
10095 06:02:35.128557 [ 0.000000] Fallback order for Node 0: 0
10096 06:02:35.135221 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10097 06:02:35.138424 [ 0.000000] Policy zone: Normal
10098 06:02:35.161523 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12379472/extract-nfsrootfs-l133z4kz,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10099 06:02:35.171982 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10100 06:02:35.181324 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10101 06:02:35.188199 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10102 06:02:35.194700 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10103 06:02:35.201201 <6>[ 0.000000] software IO TLB: area num 8.
10104 06:02:35.256410 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10105 06:02:35.336853 <6>[ 0.000000] Memory: 3835984K/4191232K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 322480K reserved, 32768K cma-reserved)
10106 06:02:35.343507 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10107 06:02:35.350013 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10108 06:02:35.353418 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10109 06:02:35.359893 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10110 06:02:35.366572 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10111 06:02:35.369768 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10112 06:02:35.379854 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10113 06:02:35.386274 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10114 06:02:35.393534 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10115 06:02:35.399389 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10116 06:02:35.402788 <6>[ 0.000000] GICv3: 608 SPIs implemented
10117 06:02:35.405949 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10118 06:02:35.412749 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10119 06:02:35.416012 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10120 06:02:35.422773 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10121 06:02:35.436160 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10122 06:02:35.449155 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10123 06:02:35.455608 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10124 06:02:35.462994 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10125 06:02:35.476503 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10126 06:02:35.483199 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10127 06:02:35.489689 <6>[ 0.009229] Console: colour dummy device 80x25
10128 06:02:35.499740 <6>[ 0.013955] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10129 06:02:35.506243 <6>[ 0.024396] pid_max: default: 32768 minimum: 301
10130 06:02:35.509415 <6>[ 0.029268] LSM: Security Framework initializing
10131 06:02:35.516389 <6>[ 0.034180] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10132 06:02:35.526122 <6>[ 0.041787] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10133 06:02:35.532933 <6>[ 0.051033] cblist_init_generic: Setting adjustable number of callback queues.
10134 06:02:35.539383 <6>[ 0.058521] cblist_init_generic: Setting shift to 3 and lim to 1.
10135 06:02:35.549150 <6>[ 0.064859] cblist_init_generic: Setting adjustable number of callback queues.
10136 06:02:35.552427 <6>[ 0.072286] cblist_init_generic: Setting shift to 3 and lim to 1.
10137 06:02:35.559144 <6>[ 0.078686] rcu: Hierarchical SRCU implementation.
10138 06:02:35.566206 <6>[ 0.083733] rcu: Max phase no-delay instances is 1000.
10139 06:02:35.572514 <6>[ 0.090740] EFI services will not be available.
10140 06:02:35.575682 <6>[ 0.095693] smp: Bringing up secondary CPUs ...
10141 06:02:35.583907 <6>[ 0.100737] Detected VIPT I-cache on CPU1
10142 06:02:35.590587 <6>[ 0.100804] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10143 06:02:35.597083 <6>[ 0.100834] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10144 06:02:35.600341 <6>[ 0.101167] Detected VIPT I-cache on CPU2
10145 06:02:35.607165 <6>[ 0.101216] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10146 06:02:35.616888 <6>[ 0.101232] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10147 06:02:35.620036 <6>[ 0.101488] Detected VIPT I-cache on CPU3
10148 06:02:35.626390 <6>[ 0.101535] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10149 06:02:35.633054 <6>[ 0.101549] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10150 06:02:35.639822 <6>[ 0.101852] CPU features: detected: Spectre-v4
10151 06:02:35.643073 <6>[ 0.101858] CPU features: detected: Spectre-BHB
10152 06:02:35.646373 <6>[ 0.101863] Detected PIPT I-cache on CPU4
10153 06:02:35.652846 <6>[ 0.101919] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10154 06:02:35.659420 <6>[ 0.101935] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10155 06:02:35.666348 <6>[ 0.102229] Detected PIPT I-cache on CPU5
10156 06:02:35.672697 <6>[ 0.102290] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10157 06:02:35.679392 <6>[ 0.102307] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10158 06:02:35.682357 <6>[ 0.102585] Detected PIPT I-cache on CPU6
10159 06:02:35.689331 <6>[ 0.102647] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10160 06:02:35.695885 <6>[ 0.102663] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10161 06:02:35.702236 <6>[ 0.102963] Detected PIPT I-cache on CPU7
10162 06:02:35.709172 <6>[ 0.103028] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10163 06:02:35.715695 <6>[ 0.103044] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10164 06:02:35.718670 <6>[ 0.103091] smp: Brought up 1 node, 8 CPUs
10165 06:02:35.725245 <6>[ 0.244348] SMP: Total of 8 processors activated.
10166 06:02:35.728766 <6>[ 0.249269] CPU features: detected: 32-bit EL0 Support
10167 06:02:35.738591 <6>[ 0.254631] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10168 06:02:35.745468 <6>[ 0.263432] CPU features: detected: Common not Private translations
10169 06:02:35.751902 <6>[ 0.269907] CPU features: detected: CRC32 instructions
10170 06:02:35.755371 <6>[ 0.275292] CPU features: detected: RCpc load-acquire (LDAPR)
10171 06:02:35.761870 <6>[ 0.281289] CPU features: detected: LSE atomic instructions
10172 06:02:35.768169 <6>[ 0.287070] CPU features: detected: Privileged Access Never
10173 06:02:35.775282 <6>[ 0.292850] CPU features: detected: RAS Extension Support
10174 06:02:35.781395 <6>[ 0.298459] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10175 06:02:35.784888 <6>[ 0.305722] CPU: All CPU(s) started at EL2
10176 06:02:35.791289 <6>[ 0.310038] alternatives: applying system-wide alternatives
10177 06:02:35.800440 <6>[ 0.319956] devtmpfs: initialized
10178 06:02:35.815442 <6>[ 0.328122] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10179 06:02:35.821808 <6>[ 0.338087] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10180 06:02:35.828356 <6>[ 0.346346] pinctrl core: initialized pinctrl subsystem
10181 06:02:35.832136 <6>[ 0.353010] DMI not present or invalid.
10182 06:02:35.838481 <6>[ 0.357329] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10183 06:02:35.848377 <6>[ 0.364189] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10184 06:02:35.854748 <6>[ 0.371638] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10185 06:02:35.864575 <6>[ 0.379723] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10186 06:02:35.868120 <6>[ 0.387873] audit: initializing netlink subsys (disabled)
10187 06:02:35.878071 <5>[ 0.393569] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10188 06:02:35.884767 <6>[ 0.394269] thermal_sys: Registered thermal governor 'step_wise'
10189 06:02:35.891087 <6>[ 0.401535] thermal_sys: Registered thermal governor 'power_allocator'
10190 06:02:35.894324 <6>[ 0.407783] cpuidle: using governor menu
10191 06:02:35.900877 <6>[ 0.418740] NET: Registered PF_QIPCRTR protocol family
10192 06:02:35.907664 <6>[ 0.424210] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10193 06:02:35.910976 <6>[ 0.431308] ASID allocator initialised with 32768 entries
10194 06:02:35.918466 <6>[ 0.437850] Serial: AMBA PL011 UART driver
10195 06:02:35.926900 <4>[ 0.446600] Trying to register duplicate clock ID: 134
10196 06:02:35.981281 <6>[ 0.504114] KASLR enabled
10197 06:02:35.995584 <6>[ 0.511753] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10198 06:02:36.001921 <6>[ 0.518767] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10199 06:02:36.008866 <6>[ 0.525258] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10200 06:02:36.015725 <6>[ 0.532265] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10201 06:02:36.021818 <6>[ 0.538754] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10202 06:02:36.028309 <6>[ 0.545762] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10203 06:02:36.035300 <6>[ 0.552247] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10204 06:02:36.041667 <6>[ 0.559252] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10205 06:02:36.044812 <6>[ 0.566672] ACPI: Interpreter disabled.
10206 06:02:36.053510 <6>[ 0.573058] iommu: Default domain type: Translated
10207 06:02:36.060275 <6>[ 0.578184] iommu: DMA domain TLB invalidation policy: strict mode
10208 06:02:36.063451 <5>[ 0.584838] SCSI subsystem initialized
10209 06:02:36.070311 <6>[ 0.589092] usbcore: registered new interface driver usbfs
10210 06:02:36.076876 <6>[ 0.594822] usbcore: registered new interface driver hub
10211 06:02:36.079883 <6>[ 0.600375] usbcore: registered new device driver usb
10212 06:02:36.086929 <6>[ 0.606493] pps_core: LinuxPPS API ver. 1 registered
10213 06:02:36.096861 <6>[ 0.611685] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10214 06:02:36.100330 <6>[ 0.621031] PTP clock support registered
10215 06:02:36.103131 <6>[ 0.625273] EDAC MC: Ver: 3.0.0
10216 06:02:36.110989 <6>[ 0.630441] FPGA manager framework
10217 06:02:36.114556 <6>[ 0.634113] Advanced Linux Sound Architecture Driver Initialized.
10218 06:02:36.117763 <6>[ 0.640869] vgaarb: loaded
10219 06:02:36.124884 <6>[ 0.644014] clocksource: Switched to clocksource arch_sys_counter
10220 06:02:36.131373 <5>[ 0.650455] VFS: Disk quotas dquot_6.6.0
10221 06:02:36.137968 <6>[ 0.654642] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10222 06:02:36.141524 <6>[ 0.661828] pnp: PnP ACPI: disabled
10223 06:02:36.149085 <6>[ 0.668473] NET: Registered PF_INET protocol family
10224 06:02:36.155842 <6>[ 0.673850] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10225 06:02:36.167663 <6>[ 0.683854] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10226 06:02:36.177392 <6>[ 0.692635] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10227 06:02:36.184454 <6>[ 0.700601] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10228 06:02:36.190720 <6>[ 0.709006] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10229 06:02:36.201544 <6>[ 0.717670] TCP: Hash tables configured (established 32768 bind 32768)
10230 06:02:36.208290 <6>[ 0.724529] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10231 06:02:36.214721 <6>[ 0.731549] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10232 06:02:36.221043 <6>[ 0.739069] NET: Registered PF_UNIX/PF_LOCAL protocol family
10233 06:02:36.228004 <6>[ 0.745213] RPC: Registered named UNIX socket transport module.
10234 06:02:36.231173 <6>[ 0.751364] RPC: Registered udp transport module.
10235 06:02:36.238050 <6>[ 0.756295] RPC: Registered tcp transport module.
10236 06:02:36.244344 <6>[ 0.761227] RPC: Registered tcp NFSv4.1 backchannel transport module.
10237 06:02:36.247585 <6>[ 0.767892] PCI: CLS 0 bytes, default 64
10238 06:02:36.250855 <6>[ 0.772248] Unpacking initramfs...
10239 06:02:36.260976 <6>[ 0.775966] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10240 06:02:36.267772 <6>[ 0.784606] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10241 06:02:36.274143 <6>[ 0.793401] kvm [1]: IPA Size Limit: 40 bits
10242 06:02:36.277404 <6>[ 0.797929] kvm [1]: GICv3: no GICV resource entry
10243 06:02:36.283936 <6>[ 0.802948] kvm [1]: disabling GICv2 emulation
10244 06:02:36.290859 <6>[ 0.807632] kvm [1]: GIC system register CPU interface enabled
10245 06:02:36.294518 <6>[ 0.813798] kvm [1]: vgic interrupt IRQ18
10246 06:02:36.300619 <6>[ 0.818160] kvm [1]: VHE mode initialized successfully
10247 06:02:36.304164 <5>[ 0.824588] Initialise system trusted keyrings
10248 06:02:36.310539 <6>[ 0.829431] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10249 06:02:36.319925 <6>[ 0.839466] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10250 06:02:36.326691 <5>[ 0.845837] NFS: Registering the id_resolver key type
10251 06:02:36.329759 <5>[ 0.851138] Key type id_resolver registered
10252 06:02:36.336540 <5>[ 0.855551] Key type id_legacy registered
10253 06:02:36.343012 <6>[ 0.859828] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10254 06:02:36.349638 <6>[ 0.866747] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10255 06:02:36.356242 <6>[ 0.874460] 9p: Installing v9fs 9p2000 file system support
10256 06:02:36.392993 <5>[ 0.912443] Key type asymmetric registered
10257 06:02:36.396248 <5>[ 0.916774] Asymmetric key parser 'x509' registered
10258 06:02:36.406057 <6>[ 0.921914] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10259 06:02:36.409389 <6>[ 0.929531] io scheduler mq-deadline registered
10260 06:02:36.412649 <6>[ 0.934291] io scheduler kyber registered
10261 06:02:36.431541 <6>[ 0.951119] EINJ: ACPI disabled.
10262 06:02:36.463232 <4>[ 0.976128] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10263 06:02:36.473021 <4>[ 0.986733] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10264 06:02:36.487626 <6>[ 1.007400] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10265 06:02:36.495551 <6>[ 1.015362] printk: console [ttyS0] disabled
10266 06:02:36.523754 <6>[ 1.040022] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10267 06:02:36.530145 <6>[ 1.049491] printk: console [ttyS0] enabled
10268 06:02:36.533710 <6>[ 1.049491] printk: console [ttyS0] enabled
10269 06:02:36.540424 <6>[ 1.058384] printk: bootconsole [mtk8250] disabled
10270 06:02:36.543698 <6>[ 1.058384] printk: bootconsole [mtk8250] disabled
10271 06:02:36.550310 <6>[ 1.069431] SuperH (H)SCI(F) driver initialized
10272 06:02:36.553736 <6>[ 1.074725] msm_serial: driver initialized
10273 06:02:36.567205 <6>[ 1.083636] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10274 06:02:36.577455 <6>[ 1.092186] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10275 06:02:36.584160 <6>[ 1.100729] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10276 06:02:36.594063 <6>[ 1.109357] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10277 06:02:36.600468 <6>[ 1.118064] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10278 06:02:36.610532 <6>[ 1.126777] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10279 06:02:36.620478 <6>[ 1.135317] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10280 06:02:36.627792 <6>[ 1.144111] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10281 06:02:36.637250 <6>[ 1.152654] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10282 06:02:36.648459 <6>[ 1.168064] loop: module loaded
10283 06:02:36.655006 <6>[ 1.173968] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10284 06:02:36.677404 <4>[ 1.197141] mtk-pmic-keys: Failed to locate of_node [id: -1]
10285 06:02:36.684506 <6>[ 1.203861] megasas: 07.719.03.00-rc1
10286 06:02:36.693559 <6>[ 1.213250] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10287 06:02:36.700187 <6>[ 1.219489] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10288 06:02:36.716442 <6>[ 1.236015] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10289 06:02:36.772419 <6>[ 1.285263] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10290 06:02:37.034859 <6>[ 1.554417] Freeing initrd memory: 18320K
10291 06:02:37.046313 <6>[ 1.566052] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10292 06:02:37.057552 <6>[ 1.577166] tun: Universal TUN/TAP device driver, 1.6
10293 06:02:37.061227 <6>[ 1.583237] thunder_xcv, ver 1.0
10294 06:02:37.064794 <6>[ 1.586761] thunder_bgx, ver 1.0
10295 06:02:37.067753 <6>[ 1.590259] nicpf, ver 1.0
10296 06:02:37.077739 <6>[ 1.594295] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10297 06:02:37.081227 <6>[ 1.601771] hns3: Copyright (c) 2017 Huawei Corporation.
10298 06:02:37.087980 <6>[ 1.607360] hclge is initializing
10299 06:02:37.091342 <6>[ 1.610940] e1000: Intel(R) PRO/1000 Network Driver
10300 06:02:37.097972 <6>[ 1.616069] e1000: Copyright (c) 1999-2006 Intel Corporation.
10301 06:02:37.100933 <6>[ 1.622080] e1000e: Intel(R) PRO/1000 Network Driver
10302 06:02:37.108128 <6>[ 1.627296] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10303 06:02:37.114415 <6>[ 1.633480] igb: Intel(R) Gigabit Ethernet Network Driver
10304 06:02:37.121228 <6>[ 1.639131] igb: Copyright (c) 2007-2014 Intel Corporation.
10305 06:02:37.127768 <6>[ 1.644971] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10306 06:02:37.134442 <6>[ 1.651488] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10307 06:02:37.137767 <6>[ 1.657955] sky2: driver version 1.30
10308 06:02:37.144485 <6>[ 1.662955] VFIO - User Level meta-driver version: 0.3
10309 06:02:37.151768 <6>[ 1.671204] usbcore: registered new interface driver usb-storage
10310 06:02:37.158393 <6>[ 1.677654] usbcore: registered new device driver onboard-usb-hub
10311 06:02:37.167401 <6>[ 1.686818] mt6397-rtc mt6359-rtc: registered as rtc0
10312 06:02:37.177266 <6>[ 1.692284] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-25T06:02:37 UTC (1703484157)
10313 06:02:37.180387 <6>[ 1.701844] i2c_dev: i2c /dev entries driver
10314 06:02:37.197369 <6>[ 1.713633] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10315 06:02:37.216934 <6>[ 1.736591] cpu cpu0: EM: created perf domain
10316 06:02:37.220115 <6>[ 1.741491] cpu cpu4: EM: created perf domain
10317 06:02:37.227257 <6>[ 1.747008] sdhci: Secure Digital Host Controller Interface driver
10318 06:02:37.233777 <6>[ 1.753438] sdhci: Copyright(c) Pierre Ossman
10319 06:02:37.240606 <6>[ 1.758347] Synopsys Designware Multimedia Card Interface Driver
10320 06:02:37.247348 <6>[ 1.764936] sdhci-pltfm: SDHCI platform and OF driver helper
10321 06:02:37.250526 <6>[ 1.765017] mmc0: CQHCI version 5.10
10322 06:02:37.257454 <6>[ 1.775072] ledtrig-cpu: registered to indicate activity on CPUs
10323 06:02:37.263839 <6>[ 1.781869] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10324 06:02:37.270591 <6>[ 1.788893] usbcore: registered new interface driver usbhid
10325 06:02:37.273756 <6>[ 1.794713] usbhid: USB HID core driver
10326 06:02:37.280405 <6>[ 1.798874] spi_master spi0: will run message pump with realtime priority
10327 06:02:37.321057 <6>[ 1.834328] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10328 06:02:37.339969 <6>[ 1.849658] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10329 06:02:37.343422 <6>[ 1.863265] mmc0: Command Queue Engine enabled
10330 06:02:37.350259 <6>[ 1.868037] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10331 06:02:37.357104 <6>[ 1.874954] cros-ec-spi spi0.0: Chrome EC device registered
10332 06:02:37.360441 <6>[ 1.875222] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10333 06:02:37.370097 <6>[ 1.889662] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10334 06:02:37.377122 <6>[ 1.896870] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10335 06:02:37.383889 <6>[ 1.902704] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10336 06:02:37.390075 <6>[ 1.908580] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10337 06:02:37.404633 <6>[ 1.921299] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10338 06:02:37.412017 <6>[ 1.931668] NET: Registered PF_PACKET protocol family
10339 06:02:37.415657 <6>[ 1.937057] 9pnet: Installing 9P2000 support
10340 06:02:37.421895 <5>[ 1.941622] Key type dns_resolver registered
10341 06:02:37.425156 <6>[ 1.946575] registered taskstats version 1
10342 06:02:37.431815 <5>[ 1.950958] Loading compiled-in X.509 certificates
10343 06:02:37.460632 <4>[ 1.973471] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10344 06:02:37.470788 <4>[ 1.984410] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10345 06:02:37.477243 <3>[ 1.994958] debugfs: File 'uA_load' in directory '/' already present!
10346 06:02:37.483976 <3>[ 2.001664] debugfs: File 'min_uV' in directory '/' already present!
10347 06:02:37.490312 <3>[ 2.008273] debugfs: File 'max_uV' in directory '/' already present!
10348 06:02:37.497163 <3>[ 2.014882] debugfs: File 'constraint_flags' in directory '/' already present!
10349 06:02:37.508106 <3>[ 2.024527] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10350 06:02:37.521617 <6>[ 2.041491] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10351 06:02:37.528688 <6>[ 2.048391] xhci-mtk 11200000.usb: xHCI Host Controller
10352 06:02:37.535441 <6>[ 2.053887] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10353 06:02:37.545464 <6>[ 2.061729] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10354 06:02:37.552123 <6>[ 2.071159] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10355 06:02:37.558691 <6>[ 2.077238] xhci-mtk 11200000.usb: xHCI Host Controller
10356 06:02:37.565285 <6>[ 2.082723] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10357 06:02:37.572223 <6>[ 2.090373] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10358 06:02:37.578759 <6>[ 2.098089] hub 1-0:1.0: USB hub found
10359 06:02:37.581909 <6>[ 2.102100] hub 1-0:1.0: 1 port detected
10360 06:02:37.588508 <6>[ 2.106365] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10361 06:02:37.595292 <6>[ 2.114909] hub 2-0:1.0: USB hub found
10362 06:02:37.598426 <6>[ 2.118917] hub 2-0:1.0: 1 port detected
10363 06:02:37.605647 <6>[ 2.125250] mtk-msdc 11f70000.mmc: Got CD GPIO
10364 06:02:37.617437 <6>[ 2.133689] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10365 06:02:37.624115 <6>[ 2.141707] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10366 06:02:37.634002 <4>[ 2.149604] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10367 06:02:37.643932 <6>[ 2.159124] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10368 06:02:37.650578 <6>[ 2.167201] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10369 06:02:37.657289 <6>[ 2.175215] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10370 06:02:37.666914 <6>[ 2.183133] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10371 06:02:37.673387 <6>[ 2.190950] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10372 06:02:37.683643 <6>[ 2.198767] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10373 06:02:37.693799 <6>[ 2.209156] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10374 06:02:37.700356 <6>[ 2.217513] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10375 06:02:37.710284 <6>[ 2.225854] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10376 06:02:37.716971 <6>[ 2.234192] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10377 06:02:37.726669 <6>[ 2.242529] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10378 06:02:37.733155 <6>[ 2.250868] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10379 06:02:37.743561 <6>[ 2.259207] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10380 06:02:37.750084 <6>[ 2.267545] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10381 06:02:37.759876 <6>[ 2.275883] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10382 06:02:37.766621 <6>[ 2.284223] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10383 06:02:37.776142 <6>[ 2.292563] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10384 06:02:37.783119 <6>[ 2.300900] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10385 06:02:37.793051 <6>[ 2.309238] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10386 06:02:37.802855 <6>[ 2.317575] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10387 06:02:37.809520 <6>[ 2.325913] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10388 06:02:37.815964 <6>[ 2.334670] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10389 06:02:37.822496 <6>[ 2.341829] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10390 06:02:37.829245 <6>[ 2.348572] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10391 06:02:37.835447 <6>[ 2.355307] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10392 06:02:37.845846 <6>[ 2.362209] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10393 06:02:37.852445 <6>[ 2.369042] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10394 06:02:37.862223 <6>[ 2.378169] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10395 06:02:37.872205 <6>[ 2.387288] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10396 06:02:37.881958 <6>[ 2.396583] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10397 06:02:37.891982 <6>[ 2.406052] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10398 06:02:37.898511 <6>[ 2.415519] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10399 06:02:37.908541 <6>[ 2.424638] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10400 06:02:37.918843 <6>[ 2.434104] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10401 06:02:37.928497 <6>[ 2.443222] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10402 06:02:37.938609 <6>[ 2.452514] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10403 06:02:37.948273 <6>[ 2.462673] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10404 06:02:37.958136 <6>[ 2.474260] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10405 06:02:37.965041 <6>[ 2.484113] Trying to probe devices needed for running init ...
10406 06:02:37.988211 <6>[ 2.504517] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10407 06:02:38.016204 <6>[ 2.535568] hub 2-1:1.0: USB hub found
10408 06:02:38.019132 <6>[ 2.539969] hub 2-1:1.0: 3 ports detected
10409 06:02:38.027748 <6>[ 2.547368] hub 2-1:1.0: USB hub found
10410 06:02:38.031304 <6>[ 2.551741] hub 2-1:1.0: 3 ports detected
10411 06:02:38.139898 <6>[ 2.656293] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10412 06:02:38.293250 <6>[ 2.812756] hub 1-1:1.0: USB hub found
10413 06:02:38.296547 <6>[ 2.817140] hub 1-1:1.0: 4 ports detected
10414 06:02:38.305666 <6>[ 2.825336] hub 1-1:1.0: USB hub found
10415 06:02:38.308961 <6>[ 2.829809] hub 1-1:1.0: 4 ports detected
10416 06:02:38.375894 <6>[ 2.892477] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10417 06:02:38.631515 <6>[ 3.148305] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10418 06:02:38.764266 <6>[ 3.283973] hub 1-1.4:1.0: USB hub found
10419 06:02:38.767415 <6>[ 3.288619] hub 1-1.4:1.0: 2 ports detected
10420 06:02:38.776140 <6>[ 3.295928] hub 1-1.4:1.0: USB hub found
10421 06:02:38.779411 <6>[ 3.300517] hub 1-1.4:1.0: 2 ports detected
10422 06:02:39.075695 <6>[ 3.592322] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10423 06:02:39.267882 <6>[ 3.784342] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10424 06:02:50.241047 <6>[ 14.765319] ALSA device list:
10425 06:02:50.247020 <6>[ 14.768615] No soundcards found.
10426 06:02:50.255478 <6>[ 14.776397] Freeing unused kernel memory: 8448K
10427 06:02:50.258442 <6>[ 14.781461] Run /init as init process
10428 06:02:50.269687 Loading, please wait...
10429 06:02:50.294601 Starting systemd-udevd version 252.19-1~deb12u1
10430 06:02:50.489892 <6>[ 15.007679] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10431 06:02:50.507893 <6>[ 15.028931] remoteproc remoteproc0: scp is available
10432 06:02:50.519869 <6>[ 15.037483] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10433 06:02:50.523176 <6>[ 15.043784] remoteproc remoteproc0: powering up scp
10434 06:02:50.532816 <6>[ 15.045405] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10435 06:02:50.543027 <6>[ 15.050450] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10436 06:02:50.546545 <6>[ 15.050496] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10437 06:02:50.556148 <6>[ 15.059167] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10438 06:02:50.562804 <3>[ 15.081892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10439 06:02:50.572783 <3>[ 15.090126] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10440 06:02:50.579338 <6>[ 15.090687] usbcore: registered new interface driver r8152
10441 06:02:50.585721 <3>[ 15.098217] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10442 06:02:50.592811 <4>[ 15.099604] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10443 06:02:50.602573 <3>[ 15.102372] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10444 06:02:50.609268 <3>[ 15.102688] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10445 06:02:50.618869 <3>[ 15.102694] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10446 06:02:50.625926 <3>[ 15.102698] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10447 06:02:50.632698 <3>[ 15.102701] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10448 06:02:50.642264 <3>[ 15.123241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10449 06:02:50.645415 <6>[ 15.129008] mc: Linux media interface: v0.10
10450 06:02:50.655385 <4>[ 15.130469] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10451 06:02:50.661835 <3>[ 15.136748] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10452 06:02:50.668493 <6>[ 15.172056] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10453 06:02:50.678359 <3>[ 15.172626] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10454 06:02:50.685065 <6>[ 15.184561] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10455 06:02:50.691824 <3>[ 15.187991] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10456 06:02:50.698704 <6>[ 15.195016] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10457 06:02:50.708823 <6>[ 15.195059] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10458 06:02:50.715916 <6>[ 15.195067] remoteproc remoteproc0: remote processor scp is now up
10459 06:02:50.721917 <4>[ 15.197570] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10460 06:02:50.729055 <4>[ 15.197570] Fallback method does not support PEC.
10461 06:02:50.735570 <3>[ 15.203759] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10462 06:02:50.745423 <6>[ 15.205154] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10463 06:02:50.752183 <6>[ 15.207501] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10464 06:02:50.759401 <6>[ 15.208956] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10465 06:02:50.765431 <6>[ 15.208960] pci_bus 0000:00: root bus resource [bus 00-ff]
10466 06:02:50.772083 <6>[ 15.208963] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10467 06:02:50.782534 <6>[ 15.208965] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10468 06:02:50.788758 <6>[ 15.208991] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10469 06:02:50.795950 <6>[ 15.209004] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10470 06:02:50.801857 <6>[ 15.209070] pci 0000:00:00.0: supports D1 D2
10471 06:02:50.808749 <6>[ 15.209071] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10472 06:02:50.815283 <6>[ 15.209924] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10473 06:02:50.822071 <6>[ 15.209989] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10474 06:02:50.828587 <6>[ 15.210014] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10475 06:02:50.838390 <6>[ 15.210028] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10476 06:02:50.845290 <6>[ 15.210043] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10477 06:02:50.848175 <6>[ 15.210144] pci 0000:01:00.0: supports D1 D2
10478 06:02:50.855708 <6>[ 15.210146] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10479 06:02:50.865174 <6>[ 15.213204] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10480 06:02:50.875224 <3>[ 15.218918] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10481 06:02:50.881421 <3>[ 15.218921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10482 06:02:50.891341 <3>[ 15.218925] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10483 06:02:50.898066 <6>[ 15.220040] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10484 06:02:50.904564 <6>[ 15.220057] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10485 06:02:50.914493 <6>[ 15.220059] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10486 06:02:50.920975 <6>[ 15.220066] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10487 06:02:50.930909 <6>[ 15.220079] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10488 06:02:50.937611 <6>[ 15.220091] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10489 06:02:50.944045 <6>[ 15.220102] pci 0000:00:00.0: PCI bridge to [bus 01]
10490 06:02:50.950594 <6>[ 15.220107] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10491 06:02:50.957408 <6>[ 15.220185] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10492 06:02:50.964060 <6>[ 15.220615] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10493 06:02:50.970517 <6>[ 15.220970] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10494 06:02:50.977147 <4>[ 15.221900] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10495 06:02:50.986926 <4>[ 15.221905] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10496 06:02:50.993511 <3>[ 15.225857] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10497 06:02:51.003668 <6>[ 15.226143] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10498 06:02:51.013668 <3>[ 15.234469] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10499 06:02:51.019914 <3>[ 15.234487] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10500 06:02:51.029909 <6>[ 15.238692] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10501 06:02:51.036880 <6>[ 15.263670] videodev: Linux video capture interface: v2.00
10502 06:02:51.043309 <3>[ 15.265673] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10503 06:02:51.052898 <5>[ 15.266420] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10504 06:02:51.059467 <6>[ 15.279921] usbcore: registered new interface driver cdc_ether
10505 06:02:51.063140 <6>[ 15.279950] Bluetooth: Core ver 2.22
10506 06:02:51.066146 <6>[ 15.280147] NET: Registered PF_BLUETOOTH protocol family
10507 06:02:51.073066 <6>[ 15.280149] Bluetooth: HCI device and connection manager initialized
10508 06:02:51.079487 <6>[ 15.280168] Bluetooth: HCI socket layer initialized
10509 06:02:51.086044 <6>[ 15.280173] Bluetooth: L2CAP socket layer initialized
10510 06:02:51.089360 <6>[ 15.280189] Bluetooth: SCO socket layer initialized
10511 06:02:51.096026 <5>[ 15.284718] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10512 06:02:51.105733 <4>[ 15.284775] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10513 06:02:51.109178 <6>[ 15.284781] cfg80211: failed to load regulatory.db
10514 06:02:51.115518 <6>[ 15.328598] usbcore: registered new interface driver btusb
10515 06:02:51.125620 <4>[ 15.329319] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10516 06:02:51.132007 <3>[ 15.329328] Bluetooth: hci0: Failed to load firmware file (-2)
10517 06:02:51.139079 <3>[ 15.329331] Bluetooth: hci0: Failed to set up firmware (-2)
10518 06:02:51.148458 <4>[ 15.329334] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10519 06:02:51.152338 <6>[ 15.334384] r8152 2-1.3:1.0 eth0: v1.12.13
10520 06:02:51.158514 <6>[ 15.344705] usbcore: registered new interface driver r8153_ecm
10521 06:02:51.165347 <6>[ 15.357821] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10522 06:02:51.171870 <6>[ 15.372436] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10523 06:02:51.181737 <6>[ 15.377715] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10524 06:02:51.184888 <6>[ 15.378556] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10525 06:02:51.198257 <6>[ 15.378618] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10526 06:02:51.204887 <6>[ 15.378772] usbcore: registered new interface driver uvcvideo
10527 06:02:51.211288 <6>[ 15.730969] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10528 06:02:51.236225 <6>[ 15.757596] mt7921e 0000:01:00.0: ASIC revision: 79610010
10529 06:02:51.337414 <6>[ 15.855428] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10530 06:02:51.340787 <6>[ 15.855428]
10531 06:02:51.356185 Begin: Loading essential drivers ... done.
10532 06:02:51.359446 Begin: Running /scripts/init-premount ... done.
10533 06:02:51.365563 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10534 06:02:51.375867 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10535 06:02:51.378924 Device /sys/class/net/enx00e04c6803bd found
10536 06:02:51.379387 done.
10537 06:02:51.385907 Begin: Waiting up to 180 secs for any network device to become available ... done.
10538 06:02:51.422344 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10539 06:02:51.607784 <6>[ 16.125707] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10540 06:02:52.350258 <6>[ 16.871586] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10541 06:02:52.474958 <6>[ 16.996239] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10542 06:02:52.670717 IP-Config: no response after 2 secs - giving up
10543 06:02:52.711067 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10544 06:02:53.429751 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10545 06:02:53.433593 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10546 06:02:53.439814 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10547 06:02:53.449511 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10548 06:02:53.456562 host : mt8192-asurada-spherion-r0-cbg-4
10549 06:02:53.462683 domain : lava-rack
10550 06:02:53.466036 rootserver: 192.168.201.1 rootpath:
10551 06:02:53.466593 filename :
10552 06:02:53.555574 done.
10553 06:02:53.562967 Begin: Running /scripts/nfs-bottom ... done.
10554 06:02:53.578263 Begin: Running /scripts/init-bottom ... done.
10555 06:02:54.909260 <6>[ 19.430925] NET: Registered PF_INET6 protocol family
10556 06:02:54.917139 <6>[ 19.438673] Segment Routing with IPv6
10557 06:02:54.920116 <6>[ 19.442704] In-situ OAM (IOAM) with IPv6
10558 06:02:55.123522 <30>[ 19.615495] systemd[1]: systemd 252.19-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10559 06:02:55.126408 <30>[ 19.648602] systemd[1]: Detected architecture arm64.
10560 06:02:55.143452
10561 06:02:55.146738 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10562 06:02:55.147300
10563 06:02:55.172508 <30>[ 19.694092] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10564 06:02:56.270527 <30>[ 20.789220] systemd[1]: Queued start job for default target graphical.target.
10565 06:02:56.298517 <30>[ 20.817104] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10566 06:02:56.305139 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10567 06:02:56.327409 <30>[ 20.846138] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10568 06:02:56.337184 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10569 06:02:56.355518 <30>[ 20.873999] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10570 06:02:56.365424 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10571 06:02:56.383894 <30>[ 20.902494] systemd[1]: Created slice user.slice - User and Session Slice.
10572 06:02:56.390333 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10573 06:02:56.413961 <30>[ 20.929182] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10574 06:02:56.423682 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10575 06:02:56.441336 <30>[ 20.956545] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10576 06:02:56.447843 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10577 06:02:56.476288 <30>[ 20.984985] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10578 06:02:56.486603 <30>[ 21.005039] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10579 06:02:56.493642 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10580 06:02:56.513581 <30>[ 21.032348] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10581 06:02:56.523690 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10582 06:02:56.538529 <30>[ 21.060462] systemd[1]: Reached target paths.target - Path Units.
10583 06:02:56.545226 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10584 06:02:56.566331 <30>[ 21.084798] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10585 06:02:56.572691 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10586 06:02:56.586390 <30>[ 21.108292] systemd[1]: Reached target slices.target - Slice Units.
10587 06:02:56.596434 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10588 06:02:56.611084 <30>[ 21.132818] systemd[1]: Reached target swap.target - Swaps.
10589 06:02:56.617907 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10590 06:02:56.638198 <30>[ 21.156811] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10591 06:02:56.648354 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10592 06:02:56.666429 <30>[ 21.185250] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10593 06:02:56.677037 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10594 06:02:56.697294 <30>[ 21.215777] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10595 06:02:56.707033 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10596 06:02:56.723639 <30>[ 21.242019] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10597 06:02:56.733583 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10598 06:02:56.750455 <30>[ 21.268938] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10599 06:02:56.757189 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10600 06:02:56.775830 <30>[ 21.293958] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10601 06:02:56.785040 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10602 06:02:56.805029 <30>[ 21.323411] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10603 06:02:56.814564 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10604 06:02:56.830550 <30>[ 21.348780] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10605 06:02:56.840093 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10606 06:02:56.889897 <30>[ 21.408551] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10607 06:02:56.896364 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10608 06:02:56.917998 <30>[ 21.436891] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10609 06:02:56.924606 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10610 06:02:56.950112 <30>[ 21.468993] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10611 06:02:56.956627 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10612 06:02:56.985033 <30>[ 21.496934] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10613 06:02:57.022634 <30>[ 21.541180] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10614 06:02:57.032236 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10615 06:02:57.055219 <30>[ 21.573932] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10616 06:02:57.061727 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10617 06:02:57.086755 <30>[ 21.605721] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10618 06:02:57.093717 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10619 06:02:57.119089 <30>[ 21.637961] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10620 06:02:57.129047 Starting [0;1;39mmodpr<6>[ 21.648323] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10621 06:02:57.135581 obe@drm.service[0m - Load Kernel Module drm...
10622 06:02:57.159533 <30>[ 21.677985] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10623 06:02:57.169245 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10624 06:02:57.191796 <30>[ 21.710325] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10625 06:02:57.198132 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10626 06:02:57.223326 <30>[ 21.742187] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10627 06:02:57.230094 Startin<6>[ 21.750964] fuse: init (API version 7.37)
10628 06:02:57.236521 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10629 06:02:57.263458 <30>[ 21.781915] systemd[1]: Starting systemd-journald.service - Journal Service...
10630 06:02:57.269652 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10631 06:02:57.301559 <30>[ 21.820366] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10632 06:02:57.308004 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10633 06:02:57.334045 <30>[ 21.849600] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10634 06:02:57.340832 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10635 06:02:57.366583 <30>[ 21.885811] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10636 06:02:57.376515 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10637 06:02:57.398658 <30>[ 21.917179] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10638 06:02:57.412247 Starting [0;1;39msyste<3>[ 21.927892] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10639 06:02:57.415291 md-udev-trig…[0m - Coldplug All udev Devices...
10640 06:02:57.441483 <3>[ 21.959961] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10641 06:02:57.447719 <30>[ 21.961531] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10642 06:02:57.457758 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10643 06:02:57.474127 <30>[ 21.993086] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10644 06:02:57.484187 <3>[ 21.993783] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10645 06:02:57.490511 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10646 06:02:57.511646 <3>[ 22.030132] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10647 06:02:57.521137 <30>[ 22.039752] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10648 06:02:57.528090 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10649 06:02:57.541843 <3>[ 22.060597] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10650 06:02:57.552729 <30>[ 22.071319] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10651 06:02:57.563748 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10652 06:02:57.569929 <3>[ 22.088089] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10653 06:02:57.580359 <30>[ 22.099388] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10654 06:02:57.587190 <30>[ 22.107446] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10655 06:02:57.597741 [[0;32m OK [<3>[ 22.117449] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10656 06:02:57.607342 0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10657 06:02:57.623656 <30>[ 22.142344] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10658 06:02:57.630249 <3>[ 22.146118] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10659 06:02:57.640159 <30>[ 22.150576] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10660 06:02:57.647214 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10661 06:02:57.662255 <3>[ 22.180841] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10662 06:02:57.673069 <30>[ 22.191848] systemd[1]: modprobe@drm.service: Deactivated successfully.
10663 06:02:57.680222 <30>[ 22.199470] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10664 06:02:57.693355 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m -<3>[ 22.211582] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10665 06:02:57.696729 Load Kernel Module drm.
10666 06:02:57.714639 <30>[ 22.233283] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10667 06:02:57.724684 <30>[ 22.241541] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10668 06:02:57.731499 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10669 06:02:57.751451 <30>[ 22.270039] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10670 06:02:57.758236 <30>[ 22.277828] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10671 06:02:57.768082 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10672 06:02:57.786392 <30>[ 22.305269] systemd[1]: Started systemd-journald.service - Journal Service.
10673 06:02:57.793187 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10674 06:02:57.814769 <4>[ 22.326608] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10675 06:02:57.821110 <3>[ 22.342273] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10676 06:02:57.831446 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10677 06:02:57.852454 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10678 06:02:57.874344 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10679 06:02:57.895588 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10680 06:02:57.914867 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10681 06:02:57.936509 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10682 06:02:58.001947 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10683 06:02:58.026461 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10684 06:02:58.073982 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10685 06:02:58.099896 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10686 06:02:58.132860 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10687 06:02:58.156430 <46>[ 22.675615] systemd-journald[299]: Received client request to flush runtime journal.
10688 06:02:58.162809 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10689 06:02:58.200278 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10690 06:02:58.218163 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10691 06:02:58.243479 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10692 06:02:58.267789 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10693 06:02:58.935900 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10694 06:02:58.989846 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10695 06:02:59.583929 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10696 06:02:59.631637 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10697 06:02:59.649973 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10698 06:02:59.669476 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10699 06:02:59.717719 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
10700 06:02:59.738057 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10701 06:02:59.762676 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10702 06:02:59.794310 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
10703 06:02:59.809776 See 'systemctl status systemd-binfmt.service' for details.
10704 06:02:59.960410 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10705 06:03:00.016093 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10706 06:03:00.042261 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10707 06:03:00.371231 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10708 06:03:00.431035 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10709 06:03:00.567797 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10710 06:03:00.585790 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10711 06:03:00.603099 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10712 06:03:00.626247 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10713 06:03:00.646878 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10714 06:03:00.681496 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10715 06:03:00.734528 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10716 06:03:00.768394 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10717 06:03:00.791115 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10718 06:03:00.810917 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10719 06:03:00.851664 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10720 06:03:00.910356 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10721 06:03:00.929970 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10722 06:03:00.949416 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10723 06:03:00.969585 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10724 06:03:00.994161 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10725 06:03:01.016622 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10726 06:03:01.033572 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10727 06:03:01.053413 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10728 06:03:01.073701 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10729 06:03:01.089843 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10730 06:03:01.107711 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10731 06:03:01.125251 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10732 06:03:01.141482 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10733 06:03:01.178842 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10734 06:03:01.216843 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10735 06:03:01.327482 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10736 06:03:01.352963 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10737 06:03:01.552843 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10738 06:03:01.594044 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10739 06:03:01.640442 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10740 06:03:01.658065 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10741 06:03:01.674707 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10742 06:03:01.711532 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10743 06:03:01.734845 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10744 06:03:01.765866 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10745 06:03:01.788284 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10746 06:03:01.854153 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
10747 06:03:01.873610 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10748 06:03:01.919933 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10749 06:03:02.015777 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
10750 06:03:02.104024
10751 06:03:02.104570
10752 06:03:02.107031 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10753 06:03:02.107498
10754 06:03:02.110242 debian-bookworm-arm64 login: root (automatic login)
10755 06:03:02.110702
10756 06:03:02.111065
10757 06:03:02.430976 Linux debian-bookworm-arm64 6.1.67-cip12 #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023 aarch64
10758 06:03:02.431123
10759 06:03:02.437442 The programs included with the Debian GNU/Linux system are free software;
10760 06:03:02.443797 the exact distribution terms for each program are described in the
10761 06:03:02.447502 individual files in /usr/share/doc/*/copyright.
10762 06:03:02.447584
10763 06:03:02.453986 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10764 06:03:02.457111 permitted by applicable law.
10765 06:03:03.540285 Matched prompt #10: / #
10767 06:03:03.541534 Setting prompt string to ['/ #']
10768 06:03:03.541975 end: 2.2.5.1 login-action (duration 00:00:29) [common]
10770 06:03:03.542960 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
10771 06:03:03.543618 start: 2.2.6 expect-shell-connection (timeout 00:03:31) [common]
10772 06:03:03.544031 Setting prompt string to ['/ #']
10773 06:03:03.544356 Forcing a shell prompt, looking for ['/ #']
10775 06:03:03.594981 / #
10776 06:03:03.595383 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10777 06:03:03.595644 Waiting using forced prompt support (timeout 00:02:30)
10778 06:03:03.600815
10779 06:03:03.601524 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10780 06:03:03.601882 start: 2.2.7 export-device-env (timeout 00:03:31) [common]
10782 06:03:03.702925 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12379472/extract-nfsrootfs-l133z4kz'
10783 06:03:03.709624 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12379472/extract-nfsrootfs-l133z4kz'
10785 06:03:03.811395 / # export NFS_SERVER_IP='192.168.201.1'
10786 06:03:03.817607 export NFS_SERVER_IP='192.168.201.1'
10787 06:03:03.818462 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10788 06:03:03.819006 end: 2.2 depthcharge-retry (duration 00:01:29) [common]
10789 06:03:03.819521 end: 2 depthcharge-action (duration 00:01:29) [common]
10790 06:03:03.820020 start: 3 lava-test-retry (timeout 00:07:50) [common]
10791 06:03:03.820562 start: 3.1 lava-test-shell (timeout 00:07:50) [common]
10792 06:03:03.821236 Using namespace: common
10794 06:03:03.922622 / # #
10795 06:03:03.923315 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10796 06:03:03.928875 #
10797 06:03:03.929770 Using /lava-12379472
10799 06:03:04.031184 / # export SHELL=/bin/bash
10800 06:03:04.037381 export SHELL=/bin/bash
10802 06:03:04.139201 / # . /lava-12379472/environment
10803 06:03:04.145446 . /lava-12379472/environment
10805 06:03:04.252950 / # /lava-12379472/bin/lava-test-runner /lava-12379472/0
10806 06:03:04.253719 Test shell timeout: 10s (minimum of the action and connection timeout)
10807 06:03:04.258970 /lava-12379472/bin/lava-test-runner /lava-12379472/0
10808 06:03:04.528063 + export TESTRUN_ID=0_timesync-off
10809 06:03:04.531167 + TESTRUN_ID=0_timesync-off
10810 06:03:04.534558 + cd /lava-12379472/0/tests/0_timesync-off
10811 06:03:04.537488 ++ cat uuid
10812 06:03:04.544294 + UUID=12379472_1.6.2.3.1
10813 06:03:04.544750 + set +x
10814 06:03:04.550563 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12379472_1.6.2.3.1>
10815 06:03:04.551265 Received signal: <STARTRUN> 0_timesync-off 12379472_1.6.2.3.1
10816 06:03:04.551649 Starting test lava.0_timesync-off (12379472_1.6.2.3.1)
10817 06:03:04.552076 Skipping test definition patterns.
10818 06:03:04.553886 + systemctl stop systemd-timesyncd
10819 06:03:04.631773 + set +x
10820 06:03:04.634881 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12379472_1.6.2.3.1>
10821 06:03:04.635619 Received signal: <ENDRUN> 0_timesync-off 12379472_1.6.2.3.1
10822 06:03:04.636082 Ending use of test pattern.
10823 06:03:04.636443 Ending test lava.0_timesync-off (12379472_1.6.2.3.1), duration 0.08
10825 06:03:04.700831 + export TESTRUN_ID=1_kselftest-alsa
10826 06:03:04.703856 + TESTRUN_ID=1_kselftest-alsa
10827 06:03:04.710451 + cd /lava-12379472/0/tests/1_kselftest-alsa
10828 06:03:04.710901 ++ cat uuid
10829 06:03:04.715945 + UUID=12379472_1.6.2.3.5
10830 06:03:04.716386 + set +x
10831 06:03:04.722370 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 12379472_1.6.2.3.5>
10832 06:03:04.723072 Received signal: <STARTRUN> 1_kselftest-alsa 12379472_1.6.2.3.5
10833 06:03:04.723427 Starting test lava.1_kselftest-alsa (12379472_1.6.2.3.5)
10834 06:03:04.723839 Skipping test definition patterns.
10835 06:03:04.725784 + cd ./automated/linux/kselftest/
10836 06:03:04.752138 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10837 06:03:04.793622 INFO: install_deps skipped
10838 06:03:05.296699 --2023-12-25 06:03:05-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10839 06:03:05.309422 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10840 06:03:05.442456 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10841 06:03:05.575313 HTTP request sent, awaiting response... 200 OK
10842 06:03:05.578685 Length: 2966180 (2.8M) [application/octet-stream]
10843 06:03:05.582221 Saving to: 'kselftest.tar.xz'
10844 06:03:05.582789
10845 06:03:05.583156
10846 06:03:05.842037 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10847 06:03:06.108847 kselftest.tar.xz 1%[ ] 47.81K 186KB/s
10848 06:03:06.455411 kselftest.tar.xz 7%[> ] 217.50K 420KB/s
10849 06:03:06.806826 kselftest.tar.xz 28%[====> ] 826.96K 966KB/s
10850 06:03:06.909810 kselftest.tar.xz 50%[=========> ] 1.43M 1.19MB/s
10851 06:03:06.916256 kselftest.tar.xz 100%[===================>] 2.83M 2.18MB/s in 1.3s
10852 06:03:06.916339
10853 06:03:07.174364 2023-12-25 06:03:07 (2.18 MB/s) - 'kselftest.tar.xz' saved [2966180/2966180]
10854 06:03:07.174530
10855 06:03:12.678563 skiplist:
10856 06:03:12.681740 ========================================
10857 06:03:12.685049 ========================================
10858 06:03:12.723014 alsa:mixer-test
10859 06:03:12.741692 ============== Tests to run ===============
10860 06:03:12.741775 alsa:mixer-test
10861 06:03:12.745059 ===========End Tests to run ===============
10862 06:03:12.748271 shardfile-alsa pass
10863 06:03:12.851275 <12>[ 37.375096] kselftest: Running tests in alsa
10864 06:03:12.861361 TAP version 13
10865 06:03:12.876761 1..1
10866 06:03:12.891795 # selftests: alsa: mixer-test
10867 06:03:13.404590 # TAP version 13
10868 06:03:13.405199 # 1..0
10869 06:03:13.410849 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
10870 06:03:13.414129 ok 1 selftests: alsa: mixer-test
10871 06:03:14.142961 alsa_mixer-test pass
10872 06:03:14.187207 + ../../utils/send-to-lava.sh ./output/result.txt
10873 06:03:14.251402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
10874 06:03:14.251739 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
10876 06:03:14.296401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
10877 06:03:14.296650 + set +x
10878 06:03:14.297074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
10880 06:03:14.303050 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 12379472_1.6.2.3.5>
10881 06:03:14.303591 Received signal: <ENDRUN> 1_kselftest-alsa 12379472_1.6.2.3.5
10882 06:03:14.303858 Ending use of test pattern.
10883 06:03:14.304085 Ending test lava.1_kselftest-alsa (12379472_1.6.2.3.5), duration 9.58
10885 06:03:14.306674 <LAVA_TEST_RUNNER EXIT>
10886 06:03:14.307424 ok: lava_test_shell seems to have completed
10887 06:03:14.307902 alsa_mixer-test: pass
shardfile-alsa: pass
10888 06:03:14.308288 end: 3.1 lava-test-shell (duration 00:00:10) [common]
10889 06:03:14.308674 end: 3 lava-test-retry (duration 00:00:10) [common]
10890 06:03:14.309120 start: 4 finalize (timeout 00:07:39) [common]
10891 06:03:14.309638 start: 4.1 power-off (timeout 00:00:30) [common]
10892 06:03:14.310480 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10893 06:03:14.402190 >> Command sent successfully.
10894 06:03:14.414418 Returned 0 in 0 seconds
10895 06:03:14.515829 end: 4.1 power-off (duration 00:00:00) [common]
10897 06:03:14.517735 start: 4.2 read-feedback (timeout 00:07:39) [common]
10898 06:03:14.519100 Listened to connection for namespace 'common' for up to 1s
10899 06:03:15.519810 Finalising connection for namespace 'common'
10900 06:03:15.520532 Disconnecting from shell: Finalise
10901 06:03:15.521087 / #
10902 06:03:15.622130 end: 4.2 read-feedback (duration 00:00:01) [common]
10903 06:03:15.622964 end: 4 finalize (duration 00:00:01) [common]
10904 06:03:15.623603 Cleaning after the job
10905 06:03:15.624206 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/ramdisk
10906 06:03:15.639140 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/kernel
10907 06:03:15.676574 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/dtb
10908 06:03:15.676901 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/nfsrootfs
10909 06:03:15.780397 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379472/tftp-deploy-7wlokvlu/modules
10910 06:03:15.787350 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12379472
10911 06:03:16.432776 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12379472
10912 06:03:16.432959 Job finished correctly