Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 17
- Kernel Errors: 36
- Errors: 0
1 05:54:51.977899 lava-dispatcher, installed at version: 2023.10
2 05:54:51.978125 start: 0 validate
3 05:54:51.978253 Start time: 2023-12-25 05:54:51.978245+00:00 (UTC)
4 05:54:51.978376 Using caching service: 'http://localhost/cache/?uri=%s'
5 05:54:51.978502 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 05:54:52.241038 Using caching service: 'http://localhost/cache/?uri=%s'
7 05:54:52.241749 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 05:54:52.504963 Using caching service: 'http://localhost/cache/?uri=%s'
9 05:54:52.505723 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 05:54:52.777183 Using caching service: 'http://localhost/cache/?uri=%s'
11 05:54:52.777962 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:54:53.049555 Using caching service: 'http://localhost/cache/?uri=%s'
13 05:54:53.050340 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 05:54:53.328479 validate duration: 1.35
16 05:54:53.329775 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:54:53.330324 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:54:53.330816 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:54:53.331426 Not decompressing ramdisk as can be used compressed.
20 05:54:53.331941 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 05:54:53.332313 saving as /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/ramdisk/initrd.cpio.gz
22 05:54:53.332680 total size: 4665395 (4 MB)
23 05:54:53.337997 progress 0 % (0 MB)
24 05:54:53.346616 progress 5 % (0 MB)
25 05:54:53.354025 progress 10 % (0 MB)
26 05:54:53.358860 progress 15 % (0 MB)
27 05:54:53.362692 progress 20 % (0 MB)
28 05:54:53.365930 progress 25 % (1 MB)
29 05:54:53.368796 progress 30 % (1 MB)
30 05:54:53.371379 progress 35 % (1 MB)
31 05:54:53.373666 progress 40 % (1 MB)
32 05:54:53.376074 progress 45 % (2 MB)
33 05:54:53.378026 progress 50 % (2 MB)
34 05:54:53.379983 progress 55 % (2 MB)
35 05:54:53.381737 progress 60 % (2 MB)
36 05:54:53.383443 progress 65 % (2 MB)
37 05:54:53.385154 progress 70 % (3 MB)
38 05:54:53.386671 progress 75 % (3 MB)
39 05:54:53.388187 progress 80 % (3 MB)
40 05:54:53.389932 progress 85 % (3 MB)
41 05:54:53.391335 progress 90 % (4 MB)
42 05:54:53.392730 progress 95 % (4 MB)
43 05:54:53.394124 progress 100 % (4 MB)
44 05:54:53.394294 4 MB downloaded in 0.06 s (72.18 MB/s)
45 05:54:53.394460 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:54:53.394721 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:54:53.394815 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:54:53.394906 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:54:53.395049 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 05:54:53.395136 saving as /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/kernel/Image
52 05:54:53.395197 total size: 50024960 (47 MB)
53 05:54:53.395259 No compression specified
54 05:54:53.396352 progress 0 % (0 MB)
55 05:54:53.409247 progress 5 % (2 MB)
56 05:54:53.421803 progress 10 % (4 MB)
57 05:54:53.434561 progress 15 % (7 MB)
58 05:54:53.447376 progress 20 % (9 MB)
59 05:54:53.460083 progress 25 % (11 MB)
60 05:54:53.472916 progress 30 % (14 MB)
61 05:54:53.485996 progress 35 % (16 MB)
62 05:54:53.499000 progress 40 % (19 MB)
63 05:54:53.511669 progress 45 % (21 MB)
64 05:54:53.524497 progress 50 % (23 MB)
65 05:54:53.537116 progress 55 % (26 MB)
66 05:54:53.549635 progress 60 % (28 MB)
67 05:54:53.562501 progress 65 % (31 MB)
68 05:54:53.575271 progress 70 % (33 MB)
69 05:54:53.587886 progress 75 % (35 MB)
70 05:54:53.600989 progress 80 % (38 MB)
71 05:54:53.613722 progress 85 % (40 MB)
72 05:54:53.626485 progress 90 % (42 MB)
73 05:54:53.639055 progress 95 % (45 MB)
74 05:54:53.651513 progress 100 % (47 MB)
75 05:54:53.651715 47 MB downloaded in 0.26 s (185.98 MB/s)
76 05:54:53.651861 end: 1.2.1 http-download (duration 00:00:00) [common]
78 05:54:53.652089 end: 1.2 download-retry (duration 00:00:00) [common]
79 05:54:53.652172 start: 1.3 download-retry (timeout 00:10:00) [common]
80 05:54:53.652258 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 05:54:53.652394 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 05:54:53.652464 saving as /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/dtb/mt8192-asurada-spherion-r0.dtb
83 05:54:53.652523 total size: 47278 (0 MB)
84 05:54:53.652582 No compression specified
85 05:54:53.653714 progress 69 % (0 MB)
86 05:54:53.653986 progress 100 % (0 MB)
87 05:54:53.654138 0 MB downloaded in 0.00 s (27.94 MB/s)
88 05:54:53.654256 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:54:53.654503 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:54:53.654588 start: 1.4 download-retry (timeout 00:10:00) [common]
92 05:54:53.654666 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 05:54:53.654777 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 05:54:53.654842 saving as /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/nfsrootfs/full.rootfs.tar
95 05:54:53.654901 total size: 200813988 (191 MB)
96 05:54:53.654959 Using unxz to decompress xz
97 05:54:53.659129 progress 0 % (0 MB)
98 05:54:54.185793 progress 5 % (9 MB)
99 05:54:54.696113 progress 10 % (19 MB)
100 05:54:55.273768 progress 15 % (28 MB)
101 05:54:55.644495 progress 20 % (38 MB)
102 05:54:55.964898 progress 25 % (47 MB)
103 05:54:56.548155 progress 30 % (57 MB)
104 05:54:57.093740 progress 35 % (67 MB)
105 05:54:57.681496 progress 40 % (76 MB)
106 05:54:58.231459 progress 45 % (86 MB)
107 05:54:58.807061 progress 50 % (95 MB)
108 05:54:59.426581 progress 55 % (105 MB)
109 05:55:00.082877 progress 60 % (114 MB)
110 05:55:00.199726 progress 65 % (124 MB)
111 05:55:00.338361 progress 70 % (134 MB)
112 05:55:00.433959 progress 75 % (143 MB)
113 05:55:00.504181 progress 80 % (153 MB)
114 05:55:00.571755 progress 85 % (162 MB)
115 05:55:00.672111 progress 90 % (172 MB)
116 05:55:00.948201 progress 95 % (181 MB)
117 05:55:01.520932 progress 100 % (191 MB)
118 05:55:01.526047 191 MB downloaded in 7.87 s (24.33 MB/s)
119 05:55:01.526300 end: 1.4.1 http-download (duration 00:00:08) [common]
121 05:55:01.526550 end: 1.4 download-retry (duration 00:00:08) [common]
122 05:55:01.526637 start: 1.5 download-retry (timeout 00:09:52) [common]
123 05:55:01.526721 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 05:55:01.526878 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 05:55:01.526945 saving as /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/modules/modules.tar
126 05:55:01.527005 total size: 8619328 (8 MB)
127 05:55:01.527066 Using unxz to decompress xz
128 05:55:01.531166 progress 0 % (0 MB)
129 05:55:01.551706 progress 5 % (0 MB)
130 05:55:01.574594 progress 10 % (0 MB)
131 05:55:01.597992 progress 15 % (1 MB)
132 05:55:01.621269 progress 20 % (1 MB)
133 05:55:01.645174 progress 25 % (2 MB)
134 05:55:01.670529 progress 30 % (2 MB)
135 05:55:01.696510 progress 35 % (2 MB)
136 05:55:01.719768 progress 40 % (3 MB)
137 05:55:01.743768 progress 45 % (3 MB)
138 05:55:01.768605 progress 50 % (4 MB)
139 05:55:01.797190 progress 55 % (4 MB)
140 05:55:01.822022 progress 60 % (4 MB)
141 05:55:01.847262 progress 65 % (5 MB)
142 05:55:01.873728 progress 70 % (5 MB)
143 05:55:01.896941 progress 75 % (6 MB)
144 05:55:01.924800 progress 80 % (6 MB)
145 05:55:01.951448 progress 85 % (7 MB)
146 05:55:01.977391 progress 90 % (7 MB)
147 05:55:02.008092 progress 95 % (7 MB)
148 05:55:02.039121 progress 100 % (8 MB)
149 05:55:02.043909 8 MB downloaded in 0.52 s (15.90 MB/s)
150 05:55:02.044156 end: 1.5.1 http-download (duration 00:00:01) [common]
152 05:55:02.044512 end: 1.5 download-retry (duration 00:00:01) [common]
153 05:55:02.044634 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 05:55:02.044760 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 05:55:05.516641 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12379428/extract-nfsrootfs-vcgwrj83
156 05:55:05.516884 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 05:55:05.516992 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 05:55:05.517158 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9
159 05:55:05.517296 makedir: /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin
160 05:55:05.517415 makedir: /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/tests
161 05:55:05.517525 makedir: /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/results
162 05:55:05.517625 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-add-keys
163 05:55:05.517809 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-add-sources
164 05:55:05.517939 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-background-process-start
165 05:55:05.518066 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-background-process-stop
166 05:55:05.518193 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-common-functions
167 05:55:05.518346 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-echo-ipv4
168 05:55:05.518470 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-install-packages
169 05:55:05.518594 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-installed-packages
170 05:55:05.518716 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-os-build
171 05:55:05.518840 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-probe-channel
172 05:55:05.518963 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-probe-ip
173 05:55:05.519093 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-target-ip
174 05:55:05.519216 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-target-mac
175 05:55:05.519338 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-target-storage
176 05:55:05.519463 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-test-case
177 05:55:05.519589 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-test-event
178 05:55:05.519712 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-test-feedback
179 05:55:05.519833 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-test-raise
180 05:55:05.519956 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-test-reference
181 05:55:05.520081 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-test-runner
182 05:55:05.520205 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-test-set
183 05:55:05.520327 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-test-shell
184 05:55:05.520452 Updating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-add-keys (debian)
185 05:55:05.520600 Updating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-add-sources (debian)
186 05:55:05.520781 Updating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-install-packages (debian)
187 05:55:05.520919 Updating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-installed-packages (debian)
188 05:55:05.521055 Updating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/bin/lava-os-build (debian)
189 05:55:05.521174 Creating /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/environment
190 05:55:05.521267 LAVA metadata
191 05:55:05.521335 - LAVA_JOB_ID=12379428
192 05:55:05.521396 - LAVA_DISPATCHER_IP=192.168.201.1
193 05:55:05.521491 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 05:55:05.521555 skipped lava-vland-overlay
195 05:55:05.521625 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 05:55:05.521701 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 05:55:05.521759 skipped lava-multinode-overlay
198 05:55:05.521828 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 05:55:05.521914 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 05:55:05.521986 Loading test definitions
201 05:55:05.522069 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 05:55:05.522139 Using /lava-12379428 at stage 0
203 05:55:05.522418 uuid=12379428_1.6.2.3.1 testdef=None
204 05:55:05.522503 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 05:55:05.522585 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 05:55:05.523033 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 05:55:05.523245 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 05:55:05.523797 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 05:55:05.524017 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 05:55:05.524547 runner path: /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/0/tests/0_timesync-off test_uuid 12379428_1.6.2.3.1
213 05:55:05.524697 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 05:55:05.525253 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 05:55:05.525324 Using /lava-12379428 at stage 0
217 05:55:05.525418 Fetching tests from https://github.com/kernelci/test-definitions.git
218 05:55:05.525495 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/0/tests/1_kselftest-arm64'
219 05:55:10.528843 Running '/usr/bin/git checkout kernelci.org
220 05:55:10.674372 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 05:55:10.675123 uuid=12379428_1.6.2.3.5 testdef=None
222 05:55:10.675275 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 05:55:10.675519 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 05:55:10.676246 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 05:55:10.676476 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 05:55:10.677514 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 05:55:10.677764 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 05:55:10.678677 runner path: /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/0/tests/1_kselftest-arm64 test_uuid 12379428_1.6.2.3.5
232 05:55:10.678773 BOARD='mt8192-asurada-spherion-r0'
233 05:55:10.678835 BRANCH='cip'
234 05:55:10.678892 SKIPFILE='/dev/null'
235 05:55:10.678948 SKIP_INSTALL='True'
236 05:55:10.679002 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 05:55:10.679058 TST_CASENAME=''
238 05:55:10.679111 TST_CMDFILES='arm64'
239 05:55:10.679249 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 05:55:10.679444 Creating lava-test-runner.conf files
242 05:55:10.679506 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379428/lava-overlay-d04wndj9/lava-12379428/0 for stage 0
243 05:55:10.679598 - 0_timesync-off
244 05:55:10.679665 - 1_kselftest-arm64
245 05:55:10.679759 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 05:55:10.679841 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 05:55:18.066415 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 05:55:18.066570 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 05:55:18.066666 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 05:55:18.066767 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 05:55:18.066855 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 05:55:18.185706 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 05:55:18.186094 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 05:55:18.186208 extracting modules file /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379428/extract-nfsrootfs-vcgwrj83
255 05:55:18.404606 extracting modules file /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379428/extract-overlay-ramdisk-v8gc_0td/ramdisk
256 05:55:18.632847 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 05:55:18.633019 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 05:55:18.633109 [common] Applying overlay to NFS
259 05:55:18.633179 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379428/compress-overlay-qphlybfg/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12379428/extract-nfsrootfs-vcgwrj83
260 05:55:19.542864 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 05:55:19.543030 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 05:55:19.543124 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 05:55:19.543212 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 05:55:19.543292 Building ramdisk /var/lib/lava/dispatcher/tmp/12379428/extract-overlay-ramdisk-v8gc_0td/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12379428/extract-overlay-ramdisk-v8gc_0td/ramdisk
265 05:55:19.866205 >> 119415 blocks
266 05:55:21.767808 rename /var/lib/lava/dispatcher/tmp/12379428/extract-overlay-ramdisk-v8gc_0td/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/ramdisk/ramdisk.cpio.gz
267 05:55:21.768256 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 05:55:21.768375 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 05:55:21.768475 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 05:55:21.768579 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/kernel/Image'
271 05:55:33.807830 Returned 0 in 12 seconds
272 05:55:33.908884 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/kernel/image.itb
273 05:55:34.255807 output: FIT description: Kernel Image image with one or more FDT blobs
274 05:55:34.256187 output: Created: Mon Dec 25 05:55:34 2023
275 05:55:34.256263 output: Image 0 (kernel-1)
276 05:55:34.256326 output: Description:
277 05:55:34.256389 output: Created: Mon Dec 25 05:55:34 2023
278 05:55:34.256449 output: Type: Kernel Image
279 05:55:34.256507 output: Compression: lzma compressed
280 05:55:34.256563 output: Data Size: 11481830 Bytes = 11212.72 KiB = 10.95 MiB
281 05:55:34.256623 output: Architecture: AArch64
282 05:55:34.256680 output: OS: Linux
283 05:55:34.256797 output: Load Address: 0x00000000
284 05:55:34.256856 output: Entry Point: 0x00000000
285 05:55:34.256913 output: Hash algo: crc32
286 05:55:34.256967 output: Hash value: a47c00f1
287 05:55:34.257023 output: Image 1 (fdt-1)
288 05:55:34.257076 output: Description: mt8192-asurada-spherion-r0
289 05:55:34.257127 output: Created: Mon Dec 25 05:55:34 2023
290 05:55:34.257179 output: Type: Flat Device Tree
291 05:55:34.257230 output: Compression: uncompressed
292 05:55:34.257282 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 05:55:34.257333 output: Architecture: AArch64
294 05:55:34.257385 output: Hash algo: crc32
295 05:55:34.257436 output: Hash value: cc4352de
296 05:55:34.257487 output: Image 2 (ramdisk-1)
297 05:55:34.257537 output: Description: unavailable
298 05:55:34.257589 output: Created: Mon Dec 25 05:55:34 2023
299 05:55:34.257640 output: Type: RAMDisk Image
300 05:55:34.257691 output: Compression: Unknown Compression
301 05:55:34.257742 output: Data Size: 17796979 Bytes = 17379.86 KiB = 16.97 MiB
302 05:55:34.257794 output: Architecture: AArch64
303 05:55:34.257844 output: OS: Linux
304 05:55:34.257895 output: Load Address: unavailable
305 05:55:34.257946 output: Entry Point: unavailable
306 05:55:34.257997 output: Hash algo: crc32
307 05:55:34.258047 output: Hash value: b745bfac
308 05:55:34.258098 output: Default Configuration: 'conf-1'
309 05:55:34.258149 output: Configuration 0 (conf-1)
310 05:55:34.258200 output: Description: mt8192-asurada-spherion-r0
311 05:55:34.258252 output: Kernel: kernel-1
312 05:55:34.258303 output: Init Ramdisk: ramdisk-1
313 05:55:34.258353 output: FDT: fdt-1
314 05:55:34.258404 output: Loadables: kernel-1
315 05:55:34.258455 output:
316 05:55:34.258648 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 05:55:34.258741 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 05:55:34.258842 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 05:55:34.258934 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 05:55:34.259013 No LXC device requested
321 05:55:34.259105 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 05:55:34.259188 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 05:55:34.259276 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 05:55:34.259348 Checking files for TFTP limit of 4294967296 bytes.
325 05:55:34.259874 end: 1 tftp-deploy (duration 00:00:41) [common]
326 05:55:34.259975 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 05:55:34.260062 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 05:55:34.260192 substitutions:
329 05:55:34.260257 - {DTB}: 12379428/tftp-deploy-k5yrtuvm/dtb/mt8192-asurada-spherion-r0.dtb
330 05:55:34.260320 - {INITRD}: 12379428/tftp-deploy-k5yrtuvm/ramdisk/ramdisk.cpio.gz
331 05:55:34.260377 - {KERNEL}: 12379428/tftp-deploy-k5yrtuvm/kernel/Image
332 05:55:34.260432 - {LAVA_MAC}: None
333 05:55:34.260487 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12379428/extract-nfsrootfs-vcgwrj83
334 05:55:34.260541 - {NFS_SERVER_IP}: 192.168.201.1
335 05:55:34.260594 - {PRESEED_CONFIG}: None
336 05:55:34.260646 - {PRESEED_LOCAL}: None
337 05:55:34.260699 - {RAMDISK}: 12379428/tftp-deploy-k5yrtuvm/ramdisk/ramdisk.cpio.gz
338 05:55:34.260810 - {ROOT_PART}: None
339 05:55:34.260865 - {ROOT}: None
340 05:55:34.260918 - {SERVER_IP}: 192.168.201.1
341 05:55:34.260971 - {TEE}: None
342 05:55:34.261024 Parsed boot commands:
343 05:55:34.261076 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 05:55:34.261271 Parsed boot commands: tftpboot 192.168.201.1 12379428/tftp-deploy-k5yrtuvm/kernel/image.itb 12379428/tftp-deploy-k5yrtuvm/kernel/cmdline
345 05:55:34.261358 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 05:55:34.261442 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 05:55:34.261529 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 05:55:34.261615 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 05:55:34.261689 Not connected, no need to disconnect.
350 05:55:34.261762 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 05:55:34.261849 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 05:55:34.261935 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 05:55:34.265998 Setting prompt string to ['lava-test: # ']
354 05:55:34.266396 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 05:55:34.266507 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 05:55:34.266612 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 05:55:34.266744 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 05:55:34.266973 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 05:55:39.413846 >> Command sent successfully.
360 05:55:39.419473 Returned 0 in 5 seconds
361 05:55:39.520290 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 05:55:39.521882 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 05:55:39.522489 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 05:55:39.522980 Setting prompt string to 'Starting depthcharge on Spherion...'
366 05:55:39.523357 Changing prompt to 'Starting depthcharge on Spherion...'
367 05:55:39.523781 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 05:55:39.525149 [Enter `^Ec?' for help]
369 05:55:39.701442
370 05:55:39.702022
371 05:55:39.702398 F0: 102B 0000
372 05:55:39.702717
373 05:55:39.703012 F3: 1001 0000 [0200]
374 05:55:39.703304
375 05:55:39.705170 F3: 1001 0000
376 05:55:39.705602
377 05:55:39.705936 F7: 102D 0000
378 05:55:39.706245
379 05:55:39.706535 F1: 0000 0000
380 05:55:39.708454
381 05:55:39.708975 V0: 0000 0000 [0001]
382 05:55:39.709310
383 05:55:39.709618 00: 0007 8000
384 05:55:39.709937
385 05:55:39.712308 01: 0000 0000
386 05:55:39.712898
387 05:55:39.713242 BP: 0C00 0209 [0000]
388 05:55:39.713555
389 05:55:39.715884 G0: 1182 0000
390 05:55:39.716509
391 05:55:39.717007 EC: 0000 0021 [4000]
392 05:55:39.717337
393 05:55:39.718750 S7: 0000 0000 [0000]
394 05:55:39.719169
395 05:55:39.719507 CC: 0000 0000 [0001]
396 05:55:39.719818
397 05:55:39.722712 T0: 0000 0040 [010F]
398 05:55:39.723359
399 05:55:39.723763 Jump to BL
400 05:55:39.724085
401 05:55:39.747934
402 05:55:39.748456
403 05:55:39.748842
404 05:55:39.754492 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 05:55:39.758391 ARM64: Exception handlers installed.
406 05:55:39.761422 ARM64: Testing exception
407 05:55:39.764856 ARM64: Done test exception
408 05:55:39.771274 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 05:55:39.781416 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 05:55:39.788814 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 05:55:39.798908 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 05:55:39.805853 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 05:55:39.815890 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 05:55:39.825867 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 05:55:39.832779 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 05:55:39.851192 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 05:55:39.854781 WDT: Last reset was cold boot
418 05:55:39.858107 SPI1(PAD0) initialized at 2873684 Hz
419 05:55:39.861234 SPI5(PAD0) initialized at 992727 Hz
420 05:55:39.864645 VBOOT: Loading verstage.
421 05:55:39.871017 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 05:55:39.874288 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 05:55:39.877833 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 05:55:39.880606 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 05:55:39.888806 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 05:55:39.895180 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 05:55:39.905642 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 05:55:39.906233
429 05:55:39.906602
430 05:55:39.915940 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 05:55:39.919584 ARM64: Exception handlers installed.
432 05:55:39.922893 ARM64: Testing exception
433 05:55:39.923462 ARM64: Done test exception
434 05:55:39.929141 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 05:55:39.932569 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 05:55:39.947127 Probing TPM: . done!
437 05:55:39.947696 TPM ready after 0 ms
438 05:55:39.953487 Connected to device vid:did:rid of 1ae0:0028:00
439 05:55:39.963442 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 05:55:40.002580 Initialized TPM device CR50 revision 0
441 05:55:40.014823 tlcl_send_startup: Startup return code is 0
442 05:55:40.015387 TPM: setup succeeded
443 05:55:40.025903 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 05:55:40.034993 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 05:55:40.044989 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 05:55:40.053981 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 05:55:40.057271 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 05:55:40.060377 in-header: 03 07 00 00 08 00 00 00
449 05:55:40.064148 in-data: aa e4 47 04 13 02 00 00
450 05:55:40.067250 Chrome EC: UHEPI supported
451 05:55:40.073732 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 05:55:40.076875 in-header: 03 9d 00 00 08 00 00 00
453 05:55:40.080479 in-data: 10 20 20 08 00 00 00 00
454 05:55:40.081018 Phase 1
455 05:55:40.087416 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 05:55:40.094034 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 05:55:40.097452 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 05:55:40.100241 Recovery requested (1009000e)
459 05:55:40.104003 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 05:55:40.113321 tlcl_extend: response is 0
461 05:55:40.121725 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 05:55:40.127093 tlcl_extend: response is 0
463 05:55:40.133766 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 05:55:40.154131 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 05:55:40.161279 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 05:55:40.161861
467 05:55:40.162240
468 05:55:40.170978 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 05:55:40.174121 ARM64: Exception handlers installed.
470 05:55:40.177148 ARM64: Testing exception
471 05:55:40.177617 ARM64: Done test exception
472 05:55:40.200173 pmic_efuse_setting: Set efuses in 11 msecs
473 05:55:40.203938 pmwrap_interface_init: Select PMIF_VLD_RDY
474 05:55:40.210088 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 05:55:40.213652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 05:55:40.217232 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 05:55:40.224867 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 05:55:40.228435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 05:55:40.232477 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 05:55:40.239283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 05:55:40.242603 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 05:55:40.245702 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 05:55:40.252554 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 05:55:40.255939 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 05:55:40.262539 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 05:55:40.265569 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 05:55:40.272346 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 05:55:40.278644 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 05:55:40.282525 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 05:55:40.289363 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 05:55:40.296301 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 05:55:40.299743 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 05:55:40.306327 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 05:55:40.313506 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 05:55:40.316700 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 05:55:40.322966 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 05:55:40.329544 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 05:55:40.333456 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 05:55:40.339940 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 05:55:40.343246 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 05:55:40.349559 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 05:55:40.352864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 05:55:40.359555 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 05:55:40.362937 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 05:55:40.369383 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 05:55:40.372426 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 05:55:40.379949 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 05:55:40.382722 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 05:55:40.389352 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 05:55:40.392651 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 05:55:40.399185 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 05:55:40.402669 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 05:55:40.406333 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 05:55:40.412619 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 05:55:40.416318 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 05:55:40.419840 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 05:55:40.425609 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 05:55:40.429587 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 05:55:40.433072 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 05:55:40.439275 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 05:55:40.442718 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 05:55:40.446130 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 05:55:40.449580 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 05:55:40.455801 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 05:55:40.462985 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 05:55:40.472371 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 05:55:40.475780 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 05:55:40.482845 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 05:55:40.492531 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 05:55:40.495768 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 05:55:40.502351 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 05:55:40.505898 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 05:55:40.512415 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 05:55:40.518895 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 05:55:40.522375 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 05:55:40.525684 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 05:55:40.536973 [RTC]rtc_get_frequency_meter,154: input=15, output=764
538 05:55:40.546779 [RTC]rtc_get_frequency_meter,154: input=23, output=948
539 05:55:40.555947 [RTC]rtc_get_frequency_meter,154: input=19, output=856
540 05:55:40.565377 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 05:55:40.574969 [RTC]rtc_get_frequency_meter,154: input=16, output=785
542 05:55:40.584430 [RTC]rtc_get_frequency_meter,154: input=16, output=787
543 05:55:40.594164 [RTC]rtc_get_frequency_meter,154: input=17, output=810
544 05:55:40.597344 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 05:55:40.604347 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 05:55:40.607917 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 05:55:40.611317 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 05:55:40.617840 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 05:55:40.621338 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 05:55:40.624350 ADC[4]: Raw value=670432 ID=5
551 05:55:40.624882 ADC[3]: Raw value=212549 ID=1
552 05:55:40.627668 RAM Code: 0x51
553 05:55:40.631077 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 05:55:40.638181 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 05:55:40.644328 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 05:55:40.651241 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 05:55:40.654288 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 05:55:40.657639 in-header: 03 07 00 00 08 00 00 00
559 05:55:40.660968 in-data: aa e4 47 04 13 02 00 00
560 05:55:40.664587 Chrome EC: UHEPI supported
561 05:55:40.670763 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 05:55:40.674321 in-header: 03 d5 00 00 08 00 00 00
563 05:55:40.677737 in-data: 98 20 60 08 00 00 00 00
564 05:55:40.681033 MRC: failed to locate region type 0.
565 05:55:40.687719 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 05:55:40.691162 DRAM-K: Running full calibration
567 05:55:40.697401 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 05:55:40.697984 header.status = 0x0
569 05:55:40.700873 header.version = 0x6 (expected: 0x6)
570 05:55:40.704533 header.size = 0xd00 (expected: 0xd00)
571 05:55:40.707616 header.flags = 0x0
572 05:55:40.710984 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 05:55:40.730176 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 05:55:40.736339 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 05:55:40.739563 dram_init: ddr_geometry: 0
576 05:55:40.743201 [EMI] MDL number = 0
577 05:55:40.743781 [EMI] Get MDL freq = 0
578 05:55:40.746976 dram_init: ddr_type: 0
579 05:55:40.747581 is_discrete_lpddr4: 1
580 05:55:40.750560 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 05:55:40.751151
582 05:55:40.751639
583 05:55:40.753982 [Bian_co] ETT version 0.0.0.1
584 05:55:40.757383 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 05:55:40.757866
586 05:55:40.764415 dramc_set_vcore_voltage set vcore to 650000
587 05:55:40.765056 Read voltage for 800, 4
588 05:55:40.767537 Vio18 = 0
589 05:55:40.768115 Vcore = 650000
590 05:55:40.768602 Vdram = 0
591 05:55:40.769111 Vddq = 0
592 05:55:40.770670 Vmddr = 0
593 05:55:40.771188 dram_init: config_dvfs: 1
594 05:55:40.777351 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 05:55:40.783997 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 05:55:40.787461 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 05:55:40.790635 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 05:55:40.794044 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 05:55:40.797395 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 05:55:40.800559 MEM_TYPE=3, freq_sel=18
601 05:55:40.804263 sv_algorithm_assistance_LP4_1600
602 05:55:40.806943 ============ PULL DRAM RESETB DOWN ============
603 05:55:40.810659 ========== PULL DRAM RESETB DOWN end =========
604 05:55:40.816933 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 05:55:40.820177 ===================================
606 05:55:40.820645 LPDDR4 DRAM CONFIGURATION
607 05:55:40.823833 ===================================
608 05:55:40.826747 EX_ROW_EN[0] = 0x0
609 05:55:40.830137 EX_ROW_EN[1] = 0x0
610 05:55:40.830604 LP4Y_EN = 0x0
611 05:55:40.833704 WORK_FSP = 0x0
612 05:55:40.834338 WL = 0x2
613 05:55:40.837038 RL = 0x2
614 05:55:40.837506 BL = 0x2
615 05:55:40.840295 RPST = 0x0
616 05:55:40.840827 RD_PRE = 0x0
617 05:55:40.843654 WR_PRE = 0x1
618 05:55:40.844222 WR_PST = 0x0
619 05:55:40.846800 DBI_WR = 0x0
620 05:55:40.847269 DBI_RD = 0x0
621 05:55:40.850248 OTF = 0x1
622 05:55:40.853631 ===================================
623 05:55:40.856673 ===================================
624 05:55:40.857195 ANA top config
625 05:55:40.860419 ===================================
626 05:55:40.863767 DLL_ASYNC_EN = 0
627 05:55:40.866820 ALL_SLAVE_EN = 1
628 05:55:40.867295 NEW_RANK_MODE = 1
629 05:55:40.870384 DLL_IDLE_MODE = 1
630 05:55:40.873556 LP45_APHY_COMB_EN = 1
631 05:55:40.876947 TX_ODT_DIS = 1
632 05:55:40.880301 NEW_8X_MODE = 1
633 05:55:40.883642 ===================================
634 05:55:40.884112 ===================================
635 05:55:40.887157 data_rate = 1600
636 05:55:40.890386 CKR = 1
637 05:55:40.893632 DQ_P2S_RATIO = 8
638 05:55:40.897131 ===================================
639 05:55:40.900429 CA_P2S_RATIO = 8
640 05:55:40.904035 DQ_CA_OPEN = 0
641 05:55:40.906770 DQ_SEMI_OPEN = 0
642 05:55:40.907341 CA_SEMI_OPEN = 0
643 05:55:40.910002 CA_FULL_RATE = 0
644 05:55:40.913918 DQ_CKDIV4_EN = 1
645 05:55:40.917300 CA_CKDIV4_EN = 1
646 05:55:40.920231 CA_PREDIV_EN = 0
647 05:55:40.923729 PH8_DLY = 0
648 05:55:40.924298 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 05:55:40.926932 DQ_AAMCK_DIV = 4
650 05:55:40.930501 CA_AAMCK_DIV = 4
651 05:55:40.933873 CA_ADMCK_DIV = 4
652 05:55:40.936901 DQ_TRACK_CA_EN = 0
653 05:55:40.937474 CA_PICK = 800
654 05:55:40.940546 CA_MCKIO = 800
655 05:55:40.943977 MCKIO_SEMI = 0
656 05:55:40.947487 PLL_FREQ = 3068
657 05:55:40.950053 DQ_UI_PI_RATIO = 32
658 05:55:40.953951 CA_UI_PI_RATIO = 0
659 05:55:40.957421 ===================================
660 05:55:40.960044 ===================================
661 05:55:40.964114 memory_type:LPDDR4
662 05:55:40.964690 GP_NUM : 10
663 05:55:40.966782 SRAM_EN : 1
664 05:55:40.967251 MD32_EN : 0
665 05:55:40.970083 ===================================
666 05:55:40.973665 [ANA_INIT] >>>>>>>>>>>>>>
667 05:55:40.976938 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 05:55:40.980048 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 05:55:40.983547 ===================================
670 05:55:40.987167 data_rate = 1600,PCW = 0X7600
671 05:55:40.990212 ===================================
672 05:55:40.993591 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 05:55:40.996880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 05:55:41.003015 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 05:55:41.009750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 05:55:41.012971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 05:55:41.016818 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 05:55:41.017415 [ANA_INIT] flow start
679 05:55:41.019719 [ANA_INIT] PLL >>>>>>>>
680 05:55:41.023509 [ANA_INIT] PLL <<<<<<<<
681 05:55:41.024089 [ANA_INIT] MIDPI >>>>>>>>
682 05:55:41.026385 [ANA_INIT] MIDPI <<<<<<<<
683 05:55:41.030039 [ANA_INIT] DLL >>>>>>>>
684 05:55:41.030621 [ANA_INIT] flow end
685 05:55:41.033227 ============ LP4 DIFF to SE enter ============
686 05:55:41.040002 ============ LP4 DIFF to SE exit ============
687 05:55:41.040639 [ANA_INIT] <<<<<<<<<<<<<
688 05:55:41.043709 [Flow] Enable top DCM control >>>>>
689 05:55:41.046303 [Flow] Enable top DCM control <<<<<
690 05:55:41.049649 Enable DLL master slave shuffle
691 05:55:41.056614 ==============================================================
692 05:55:41.057231 Gating Mode config
693 05:55:41.063457 ==============================================================
694 05:55:41.066422 Config description:
695 05:55:41.076673 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 05:55:41.083177 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 05:55:41.086288 SELPH_MODE 0: By rank 1: By Phase
698 05:55:41.093327 ==============================================================
699 05:55:41.096764 GAT_TRACK_EN = 1
700 05:55:41.097533 RX_GATING_MODE = 2
701 05:55:41.099796 RX_GATING_TRACK_MODE = 2
702 05:55:41.103295 SELPH_MODE = 1
703 05:55:41.106593 PICG_EARLY_EN = 1
704 05:55:41.109833 VALID_LAT_VALUE = 1
705 05:55:41.116430 ==============================================================
706 05:55:41.119743 Enter into Gating configuration >>>>
707 05:55:41.123530 Exit from Gating configuration <<<<
708 05:55:41.126355 Enter into DVFS_PRE_config >>>>>
709 05:55:41.136355 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 05:55:41.139735 Exit from DVFS_PRE_config <<<<<
711 05:55:41.143113 Enter into PICG configuration >>>>
712 05:55:41.146220 Exit from PICG configuration <<<<
713 05:55:41.149908 [RX_INPUT] configuration >>>>>
714 05:55:41.152926 [RX_INPUT] configuration <<<<<
715 05:55:41.156954 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 05:55:41.162923 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 05:55:41.169831 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 05:55:41.173143 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 05:55:41.179667 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 05:55:41.185929 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 05:55:41.189408 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 05:55:41.196797 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 05:55:41.199667 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 05:55:41.202855 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 05:55:41.206407 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 05:55:41.212993 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 05:55:41.216529 ===================================
728 05:55:41.217148 LPDDR4 DRAM CONFIGURATION
729 05:55:41.219736 ===================================
730 05:55:41.222837 EX_ROW_EN[0] = 0x0
731 05:55:41.226005 EX_ROW_EN[1] = 0x0
732 05:55:41.226480 LP4Y_EN = 0x0
733 05:55:41.229538 WORK_FSP = 0x0
734 05:55:41.230015 WL = 0x2
735 05:55:41.233190 RL = 0x2
736 05:55:41.233785 BL = 0x2
737 05:55:41.236065 RPST = 0x0
738 05:55:41.236669 RD_PRE = 0x0
739 05:55:41.239455 WR_PRE = 0x1
740 05:55:41.239930 WR_PST = 0x0
741 05:55:41.242976 DBI_WR = 0x0
742 05:55:41.243548 DBI_RD = 0x0
743 05:55:41.246202 OTF = 0x1
744 05:55:41.249485 ===================================
745 05:55:41.253138 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 05:55:41.256072 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 05:55:41.262744 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 05:55:41.266443 ===================================
749 05:55:41.267018 LPDDR4 DRAM CONFIGURATION
750 05:55:41.269493 ===================================
751 05:55:41.272380 EX_ROW_EN[0] = 0x10
752 05:55:41.273004 EX_ROW_EN[1] = 0x0
753 05:55:41.276415 LP4Y_EN = 0x0
754 05:55:41.277048 WORK_FSP = 0x0
755 05:55:41.279286 WL = 0x2
756 05:55:41.282533 RL = 0x2
757 05:55:41.283012 BL = 0x2
758 05:55:41.286156 RPST = 0x0
759 05:55:41.286631 RD_PRE = 0x0
760 05:55:41.288914 WR_PRE = 0x1
761 05:55:41.289392 WR_PST = 0x0
762 05:55:41.292629 DBI_WR = 0x0
763 05:55:41.293281 DBI_RD = 0x0
764 05:55:41.295729 OTF = 0x1
765 05:55:41.299563 ===================================
766 05:55:41.305529 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 05:55:41.309207 nWR fixed to 40
768 05:55:41.309689 [ModeRegInit_LP4] CH0 RK0
769 05:55:41.312117 [ModeRegInit_LP4] CH0 RK1
770 05:55:41.315965 [ModeRegInit_LP4] CH1 RK0
771 05:55:41.316543 [ModeRegInit_LP4] CH1 RK1
772 05:55:41.319120 match AC timing 12
773 05:55:41.322401 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 05:55:41.325997 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 05:55:41.332405 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 05:55:41.336148 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 05:55:41.342948 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 05:55:41.343530 [EMI DOE] emi_dcm 0
779 05:55:41.345745 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 05:55:41.349160 ==
781 05:55:41.352818 Dram Type= 6, Freq= 0, CH_0, rank 0
782 05:55:41.355596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 05:55:41.356177 ==
784 05:55:41.359471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 05:55:41.365969 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 05:55:41.375460 [CA 0] Center 37 (7~68) winsize 62
787 05:55:41.378699 [CA 1] Center 37 (7~68) winsize 62
788 05:55:41.381902 [CA 2] Center 35 (5~66) winsize 62
789 05:55:41.385601 [CA 3] Center 35 (4~66) winsize 63
790 05:55:41.389037 [CA 4] Center 34 (4~65) winsize 62
791 05:55:41.392092 [CA 5] Center 34 (4~64) winsize 61
792 05:55:41.392670
793 05:55:41.395475 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 05:55:41.396071
795 05:55:41.398581 [CATrainingPosCal] consider 1 rank data
796 05:55:41.401826 u2DelayCellTimex100 = 270/100 ps
797 05:55:41.405311 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
798 05:55:41.408507 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
799 05:55:41.415548 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
800 05:55:41.418683 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
801 05:55:41.422075 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
802 05:55:41.425754 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
803 05:55:41.426341
804 05:55:41.428883 CA PerBit enable=1, Macro0, CA PI delay=34
805 05:55:41.429357
806 05:55:41.432562 [CBTSetCACLKResult] CA Dly = 34
807 05:55:41.433062 CS Dly: 5 (0~36)
808 05:55:41.433437 ==
809 05:55:41.435795 Dram Type= 6, Freq= 0, CH_0, rank 1
810 05:55:41.442197 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 05:55:41.442777 ==
812 05:55:41.445941 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 05:55:41.451926 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 05:55:41.461141 [CA 0] Center 37 (7~68) winsize 62
815 05:55:41.465024 [CA 1] Center 37 (7~68) winsize 62
816 05:55:41.468089 [CA 2] Center 35 (5~66) winsize 62
817 05:55:41.471459 [CA 3] Center 35 (4~66) winsize 63
818 05:55:41.475056 [CA 4] Center 33 (3~64) winsize 62
819 05:55:41.478234 [CA 5] Center 34 (3~65) winsize 63
820 05:55:41.478816
821 05:55:41.481185 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 05:55:41.481656
823 05:55:41.484867 [CATrainingPosCal] consider 2 rank data
824 05:55:41.487863 u2DelayCellTimex100 = 270/100 ps
825 05:55:41.491645 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
826 05:55:41.494903 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
827 05:55:41.501463 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
828 05:55:41.504660 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
829 05:55:41.508216 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
830 05:55:41.511355 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
831 05:55:41.511828
832 05:55:41.514900 CA PerBit enable=1, Macro0, CA PI delay=34
833 05:55:41.515478
834 05:55:41.518165 [CBTSetCACLKResult] CA Dly = 34
835 05:55:41.518740 CS Dly: 5 (0~37)
836 05:55:41.519117
837 05:55:41.521258 ----->DramcWriteLeveling(PI) begin...
838 05:55:41.524394 ==
839 05:55:41.524918 Dram Type= 6, Freq= 0, CH_0, rank 0
840 05:55:41.531808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 05:55:41.532384 ==
842 05:55:41.535209 Write leveling (Byte 0): 28 => 28
843 05:55:41.537761 Write leveling (Byte 1): 30 => 30
844 05:55:41.541543 DramcWriteLeveling(PI) end<-----
845 05:55:41.542130
846 05:55:41.542503 ==
847 05:55:41.545015 Dram Type= 6, Freq= 0, CH_0, rank 0
848 05:55:41.548118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 05:55:41.548767 ==
850 05:55:41.551009 [Gating] SW mode calibration
851 05:55:41.557664 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 05:55:41.564672 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 05:55:41.567878 0 6 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
854 05:55:41.570829 0 6 4 | B1->B0 | 2b2b 2424 | 0 0 | (1 1) (1 1)
855 05:55:41.574294 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 05:55:41.581248 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 05:55:41.584224 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 05:55:41.587807 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 05:55:41.594496 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 05:55:41.597714 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 05:55:41.601041 0 7 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
862 05:55:41.607676 0 7 4 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
863 05:55:41.610580 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 05:55:41.613935 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 05:55:41.621104 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 05:55:41.623782 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 05:55:41.627209 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 05:55:41.633995 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 05:55:41.637205 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 05:55:41.640467 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 05:55:41.647245 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 05:55:41.650917 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 05:55:41.654148 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 05:55:41.660823 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 05:55:41.664332 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 05:55:41.667441 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 05:55:41.673676 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 05:55:41.677421 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 05:55:41.680403 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 05:55:41.687118 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 05:55:41.690605 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 05:55:41.693603 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 05:55:41.700575 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 05:55:41.704050 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 05:55:41.707271 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
886 05:55:41.710545 Total UI for P1: 0, mck2ui 16
887 05:55:41.713689 best dqsien dly found for B1: ( 0, 9, 30)
888 05:55:41.717259 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 05:55:41.721182 Total UI for P1: 0, mck2ui 16
890 05:55:41.723531 best dqsien dly found for B0: ( 0, 10, 0)
891 05:55:41.727155 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
892 05:55:41.734204 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
893 05:55:41.734787
894 05:55:41.736891 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 05:55:41.740307 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
896 05:55:41.743906 [Gating] SW calibration Done
897 05:55:41.744497 ==
898 05:55:41.747896 Dram Type= 6, Freq= 0, CH_0, rank 0
899 05:55:41.751222 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 05:55:41.751812 ==
901 05:55:41.752309 RX Vref Scan: 0
902 05:55:41.752897
903 05:55:41.754379 RX Vref 0 -> 0, step: 1
904 05:55:41.754854
905 05:55:41.757452 RX Delay -130 -> 252, step: 16
906 05:55:41.761190 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 05:55:41.764584 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 05:55:41.771232 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 05:55:41.774313 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 05:55:41.777432 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 05:55:41.780676 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 05:55:41.784223 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 05:55:41.787257 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 05:55:41.794381 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
915 05:55:41.797478 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 05:55:41.800449 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 05:55:41.804066 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 05:55:41.810740 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
919 05:55:41.814183 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 05:55:41.817416 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 05:55:41.820906 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 05:55:41.821367 ==
923 05:55:41.824422 Dram Type= 6, Freq= 0, CH_0, rank 0
924 05:55:41.827127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 05:55:41.830660 ==
926 05:55:41.831216 DQS Delay:
927 05:55:41.831581 DQS0 = 0, DQS1 = 0
928 05:55:41.834206 DQM Delay:
929 05:55:41.834893 DQM0 = 82, DQM1 = 73
930 05:55:41.837358 DQ Delay:
931 05:55:41.840961 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
932 05:55:41.841510 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
933 05:55:41.844370 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
934 05:55:41.847813 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
935 05:55:41.850272
936 05:55:41.850887
937 05:55:41.851263 ==
938 05:55:41.854036 Dram Type= 6, Freq= 0, CH_0, rank 0
939 05:55:41.857402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 05:55:41.858012 ==
941 05:55:41.858383
942 05:55:41.858854
943 05:55:41.860639 TX Vref Scan disable
944 05:55:41.861267 == TX Byte 0 ==
945 05:55:41.867298 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
946 05:55:41.870683 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
947 05:55:41.871250 == TX Byte 1 ==
948 05:55:41.877655 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
949 05:55:41.880880 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
950 05:55:41.881441 ==
951 05:55:41.884445 Dram Type= 6, Freq= 0, CH_0, rank 0
952 05:55:41.887134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 05:55:41.887628 ==
954 05:55:41.900762 TX Vref=22, minBit 0, minWin=27, winSum=440
955 05:55:41.904451 TX Vref=24, minBit 2, minWin=27, winSum=448
956 05:55:41.907423 TX Vref=26, minBit 3, minWin=27, winSum=450
957 05:55:41.910519 TX Vref=28, minBit 0, minWin=28, winSum=456
958 05:55:41.914271 TX Vref=30, minBit 1, minWin=28, winSum=455
959 05:55:41.917479 TX Vref=32, minBit 1, minWin=27, winSum=452
960 05:55:41.923866 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
961 05:55:41.924407
962 05:55:41.927496 Final TX Range 1 Vref 28
963 05:55:41.928077
964 05:55:41.928684 ==
965 05:55:41.931023 Dram Type= 6, Freq= 0, CH_0, rank 0
966 05:55:41.934600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 05:55:41.935075 ==
968 05:55:41.935448
969 05:55:41.937058
970 05:55:41.937522 TX Vref Scan disable
971 05:55:41.941099 == TX Byte 0 ==
972 05:55:41.944442 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
973 05:55:41.947746 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
974 05:55:41.951230 == TX Byte 1 ==
975 05:55:41.953895 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
976 05:55:41.957405 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
977 05:55:41.957991
978 05:55:41.961055 [DATLAT]
979 05:55:41.961718 Freq=800, CH0 RK0
980 05:55:41.962100
981 05:55:41.963961 DATLAT Default: 0xa
982 05:55:41.964425 0, 0xFFFF, sum = 0
983 05:55:41.968262 1, 0xFFFF, sum = 0
984 05:55:41.968899 2, 0xFFFF, sum = 0
985 05:55:41.970565 3, 0xFFFF, sum = 0
986 05:55:41.971064 4, 0xFFFF, sum = 0
987 05:55:41.974218 5, 0xFFFF, sum = 0
988 05:55:41.974845 6, 0xFFFF, sum = 0
989 05:55:41.977464 7, 0xFFFF, sum = 0
990 05:55:41.978040 8, 0x0, sum = 1
991 05:55:41.981020 9, 0x0, sum = 2
992 05:55:41.981593 10, 0x0, sum = 3
993 05:55:41.984244 11, 0x0, sum = 4
994 05:55:41.984774 best_step = 9
995 05:55:41.985379
996 05:55:41.985870 ==
997 05:55:41.987100 Dram Type= 6, Freq= 0, CH_0, rank 0
998 05:55:41.994392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 05:55:41.994972 ==
1000 05:55:41.995467 RX Vref Scan: 1
1001 05:55:41.995925
1002 05:55:41.997303 Set Vref Range= 32 -> 127
1003 05:55:41.997779
1004 05:55:42.000671 RX Vref 32 -> 127, step: 1
1005 05:55:42.001190
1006 05:55:42.003783 RX Delay -111 -> 252, step: 8
1007 05:55:42.004260
1008 05:55:42.004792 Set Vref, RX VrefLevel [Byte0]: 32
1009 05:55:42.007203 [Byte1]: 32
1010 05:55:42.011430
1011 05:55:42.011905 Set Vref, RX VrefLevel [Byte0]: 33
1012 05:55:42.014981 [Byte1]: 33
1013 05:55:42.019100
1014 05:55:42.019637 Set Vref, RX VrefLevel [Byte0]: 34
1015 05:55:42.022929 [Byte1]: 34
1016 05:55:42.026847
1017 05:55:42.027334 Set Vref, RX VrefLevel [Byte0]: 35
1018 05:55:42.030201 [Byte1]: 35
1019 05:55:42.034769
1020 05:55:42.035373 Set Vref, RX VrefLevel [Byte0]: 36
1021 05:55:42.037830 [Byte1]: 36
1022 05:55:42.042414
1023 05:55:42.042884 Set Vref, RX VrefLevel [Byte0]: 37
1024 05:55:42.045658 [Byte1]: 37
1025 05:55:42.050083
1026 05:55:42.050668 Set Vref, RX VrefLevel [Byte0]: 38
1027 05:55:42.053314 [Byte1]: 38
1028 05:55:42.057792
1029 05:55:42.058357 Set Vref, RX VrefLevel [Byte0]: 39
1030 05:55:42.060847 [Byte1]: 39
1031 05:55:42.065032
1032 05:55:42.065598 Set Vref, RX VrefLevel [Byte0]: 40
1033 05:55:42.068650 [Byte1]: 40
1034 05:55:42.072813
1035 05:55:42.073284 Set Vref, RX VrefLevel [Byte0]: 41
1036 05:55:42.075826 [Byte1]: 41
1037 05:55:42.080538
1038 05:55:42.081169 Set Vref, RX VrefLevel [Byte0]: 42
1039 05:55:42.084089 [Byte1]: 42
1040 05:55:42.088003
1041 05:55:42.088472 Set Vref, RX VrefLevel [Byte0]: 43
1042 05:55:42.091761 [Byte1]: 43
1043 05:55:42.096117
1044 05:55:42.096678 Set Vref, RX VrefLevel [Byte0]: 44
1045 05:55:42.099216 [Byte1]: 44
1046 05:55:42.103059
1047 05:55:42.103535 Set Vref, RX VrefLevel [Byte0]: 45
1048 05:55:42.106372 [Byte1]: 45
1049 05:55:42.111272
1050 05:55:42.111848 Set Vref, RX VrefLevel [Byte0]: 46
1051 05:55:42.114427 [Byte1]: 46
1052 05:55:42.118808
1053 05:55:42.119376 Set Vref, RX VrefLevel [Byte0]: 47
1054 05:55:42.122187 [Byte1]: 47
1055 05:55:42.125936
1056 05:55:42.126406 Set Vref, RX VrefLevel [Byte0]: 48
1057 05:55:42.129809 [Byte1]: 48
1058 05:55:42.134075
1059 05:55:42.134640 Set Vref, RX VrefLevel [Byte0]: 49
1060 05:55:42.137051 [Byte1]: 49
1061 05:55:42.141519
1062 05:55:42.141984 Set Vref, RX VrefLevel [Byte0]: 50
1063 05:55:42.144879 [Byte1]: 50
1064 05:55:42.149091
1065 05:55:42.152790 Set Vref, RX VrefLevel [Byte0]: 51
1066 05:55:42.155679 [Byte1]: 51
1067 05:55:42.156249
1068 05:55:42.159342 Set Vref, RX VrefLevel [Byte0]: 52
1069 05:55:42.162182 [Byte1]: 52
1070 05:55:42.162647
1071 05:55:42.165790 Set Vref, RX VrefLevel [Byte0]: 53
1072 05:55:42.169160 [Byte1]: 53
1073 05:55:42.169728
1074 05:55:42.172577 Set Vref, RX VrefLevel [Byte0]: 54
1075 05:55:42.175939 [Byte1]: 54
1076 05:55:42.179567
1077 05:55:42.180026 Set Vref, RX VrefLevel [Byte0]: 55
1078 05:55:42.183240 [Byte1]: 55
1079 05:55:42.187477
1080 05:55:42.188021 Set Vref, RX VrefLevel [Byte0]: 56
1081 05:55:42.190683 [Byte1]: 56
1082 05:55:42.195109
1083 05:55:42.195667 Set Vref, RX VrefLevel [Byte0]: 57
1084 05:55:42.198514 [Byte1]: 57
1085 05:55:42.202409
1086 05:55:42.202891 Set Vref, RX VrefLevel [Byte0]: 58
1087 05:55:42.205805 [Byte1]: 58
1088 05:55:42.210327
1089 05:55:42.210886 Set Vref, RX VrefLevel [Byte0]: 59
1090 05:55:42.213488 [Byte1]: 59
1091 05:55:42.218501
1092 05:55:42.219058 Set Vref, RX VrefLevel [Byte0]: 60
1093 05:55:42.221594 [Byte1]: 60
1094 05:55:42.225836
1095 05:55:42.226398 Set Vref, RX VrefLevel [Byte0]: 61
1096 05:55:42.228800 [Byte1]: 61
1097 05:55:42.233191
1098 05:55:42.233750 Set Vref, RX VrefLevel [Byte0]: 62
1099 05:55:42.236962 [Byte1]: 62
1100 05:55:42.240946
1101 05:55:42.241509 Set Vref, RX VrefLevel [Byte0]: 63
1102 05:55:42.244010 [Byte1]: 63
1103 05:55:42.248487
1104 05:55:42.249103 Set Vref, RX VrefLevel [Byte0]: 64
1105 05:55:42.251793 [Byte1]: 64
1106 05:55:42.256205
1107 05:55:42.256666 Set Vref, RX VrefLevel [Byte0]: 65
1108 05:55:42.259319 [Byte1]: 65
1109 05:55:42.264151
1110 05:55:42.264750 Set Vref, RX VrefLevel [Byte0]: 66
1111 05:55:42.267181 [Byte1]: 66
1112 05:55:42.271536
1113 05:55:42.272107 Set Vref, RX VrefLevel [Byte0]: 67
1114 05:55:42.274807 [Byte1]: 67
1115 05:55:42.279200
1116 05:55:42.279780 Set Vref, RX VrefLevel [Byte0]: 68
1117 05:55:42.282184 [Byte1]: 68
1118 05:55:42.286609
1119 05:55:42.287309 Set Vref, RX VrefLevel [Byte0]: 69
1120 05:55:42.290000 [Byte1]: 69
1121 05:55:42.294428
1122 05:55:42.294988 Set Vref, RX VrefLevel [Byte0]: 70
1123 05:55:42.298057 [Byte1]: 70
1124 05:55:42.302288
1125 05:55:42.302850 Set Vref, RX VrefLevel [Byte0]: 71
1126 05:55:42.305478 [Byte1]: 71
1127 05:55:42.309535
1128 05:55:42.310011 Set Vref, RX VrefLevel [Byte0]: 72
1129 05:55:42.312688 [Byte1]: 72
1130 05:55:42.317408
1131 05:55:42.317970 Set Vref, RX VrefLevel [Byte0]: 73
1132 05:55:42.320429 [Byte1]: 73
1133 05:55:42.325219
1134 05:55:42.325779 Set Vref, RX VrefLevel [Byte0]: 74
1135 05:55:42.328420 [Byte1]: 74
1136 05:55:42.332812
1137 05:55:42.333394 Set Vref, RX VrefLevel [Byte0]: 75
1138 05:55:42.336136 [Byte1]: 75
1139 05:55:42.340056
1140 05:55:42.340518 Set Vref, RX VrefLevel [Byte0]: 76
1141 05:55:42.343655 [Byte1]: 76
1142 05:55:42.347947
1143 05:55:42.348510 Final RX Vref Byte 0 = 55 to rank0
1144 05:55:42.351250 Final RX Vref Byte 1 = 55 to rank0
1145 05:55:42.354659 Final RX Vref Byte 0 = 55 to rank1
1146 05:55:42.357780 Final RX Vref Byte 1 = 55 to rank1==
1147 05:55:42.360979 Dram Type= 6, Freq= 0, CH_0, rank 0
1148 05:55:42.368235 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1149 05:55:42.368861 ==
1150 05:55:42.369242 DQS Delay:
1151 05:55:42.369585 DQS0 = 0, DQS1 = 0
1152 05:55:42.370898 DQM Delay:
1153 05:55:42.371360 DQM0 = 83, DQM1 = 73
1154 05:55:42.374604 DQ Delay:
1155 05:55:42.377843 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1156 05:55:42.381358 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1157 05:55:42.381928 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1158 05:55:42.387701 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1159 05:55:42.388304
1160 05:55:42.388683
1161 05:55:42.394361 [DQSOSCAuto] RK0, (LSB)MR18= 0x3232, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1162 05:55:42.398541 CH0 RK0: MR19=606, MR18=3232
1163 05:55:42.404493 CH0_RK0: MR19=0x606, MR18=0x3232, DQSOSC=397, MR23=63, INC=93, DEC=62
1164 05:55:42.405062
1165 05:55:42.408071 ----->DramcWriteLeveling(PI) begin...
1166 05:55:42.408539 ==
1167 05:55:42.411910 Dram Type= 6, Freq= 0, CH_0, rank 1
1168 05:55:42.414310 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1169 05:55:42.414778 ==
1170 05:55:42.417513 Write leveling (Byte 0): 31 => 31
1171 05:55:42.421327 Write leveling (Byte 1): 27 => 27
1172 05:55:42.424439 DramcWriteLeveling(PI) end<-----
1173 05:55:42.424945
1174 05:55:42.425316 ==
1175 05:55:42.428197 Dram Type= 6, Freq= 0, CH_0, rank 1
1176 05:55:42.431015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1177 05:55:42.431479 ==
1178 05:55:42.434923 [Gating] SW mode calibration
1179 05:55:42.441338 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1180 05:55:42.448094 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1181 05:55:42.451394 0 6 0 | B1->B0 | 3232 3434 | 0 0 | (0 1) (0 0)
1182 05:55:42.454342 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1183 05:55:42.461112 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 05:55:42.464503 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 05:55:42.467523 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 05:55:42.474859 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 05:55:42.478189 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 05:55:42.481458 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 05:55:42.487969 0 7 0 | B1->B0 | 2d2d 2f2f | 0 0 | (0 0) (0 0)
1190 05:55:42.491582 0 7 4 | B1->B0 | 3e3e 4444 | 1 0 | (0 0) (0 0)
1191 05:55:42.494348 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 05:55:42.501240 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 05:55:42.504799 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 05:55:42.507902 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 05:55:42.511455 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 05:55:42.517955 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 05:55:42.520998 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 05:55:42.524645 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1199 05:55:42.531189 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 05:55:42.534796 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 05:55:42.538351 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 05:55:42.544424 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 05:55:42.547945 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 05:55:42.551634 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 05:55:42.557639 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 05:55:42.561508 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 05:55:42.564907 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 05:55:42.571254 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 05:55:42.574305 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 05:55:42.578259 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 05:55:42.584497 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 05:55:42.587525 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 05:55:42.591562 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1214 05:55:42.597673 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 05:55:42.598139 Total UI for P1: 0, mck2ui 16
1216 05:55:42.601461 best dqsien dly found for B0: ( 0, 10, 0)
1217 05:55:42.604315 Total UI for P1: 0, mck2ui 16
1218 05:55:42.607919 best dqsien dly found for B1: ( 0, 10, 0)
1219 05:55:42.611224 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1220 05:55:42.618003 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1221 05:55:42.618471
1222 05:55:42.621013 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1223 05:55:42.665396 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1224 05:55:42.666005 [Gating] SW calibration Done
1225 05:55:42.666433 ==
1226 05:55:42.666824 Dram Type= 6, Freq= 0, CH_0, rank 1
1227 05:55:42.667213 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1228 05:55:42.667550 ==
1229 05:55:42.667872 RX Vref Scan: 0
1230 05:55:42.668192
1231 05:55:42.668504 RX Vref 0 -> 0, step: 1
1232 05:55:42.668870
1233 05:55:42.669597 RX Delay -130 -> 252, step: 16
1234 05:55:42.669961 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1235 05:55:42.670285 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1236 05:55:42.670598 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1237 05:55:42.670901 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1238 05:55:42.671205 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1239 05:55:42.671505 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1240 05:55:42.699849 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1241 05:55:42.700458 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1242 05:55:42.700886 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1243 05:55:42.701595 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1244 05:55:42.701957 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1245 05:55:42.702299 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1246 05:55:42.702626 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1247 05:55:42.702939 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1248 05:55:42.704231 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1249 05:55:42.704693 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1250 05:55:42.707529 ==
1251 05:55:42.708087 Dram Type= 6, Freq= 0, CH_0, rank 1
1252 05:55:42.714125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1253 05:55:42.714671 ==
1254 05:55:42.715058 DQS Delay:
1255 05:55:42.717018 DQS0 = 0, DQS1 = 0
1256 05:55:42.717480 DQM Delay:
1257 05:55:42.720661 DQM0 = 83, DQM1 = 74
1258 05:55:42.721453 DQ Delay:
1259 05:55:42.724017 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
1260 05:55:42.727315 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1261 05:55:42.730607 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1262 05:55:42.733953 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1263 05:55:42.734513
1264 05:55:42.734874
1265 05:55:42.735209 ==
1266 05:55:42.737246 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 05:55:42.740600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1268 05:55:42.741214 ==
1269 05:55:42.741587
1270 05:55:42.741925
1271 05:55:42.743926 TX Vref Scan disable
1272 05:55:42.747458 == TX Byte 0 ==
1273 05:55:42.750267 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1274 05:55:42.754257 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1275 05:55:42.757790 == TX Byte 1 ==
1276 05:55:42.760495 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1277 05:55:42.763919 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1278 05:55:42.764664 ==
1279 05:55:42.767484 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 05:55:42.770891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1281 05:55:42.773625 ==
1282 05:55:42.785433 TX Vref=22, minBit 5, minWin=27, winSum=447
1283 05:55:42.788794 TX Vref=24, minBit 7, minWin=27, winSum=445
1284 05:55:42.791932 TX Vref=26, minBit 14, minWin=27, winSum=454
1285 05:55:42.795491 TX Vref=28, minBit 2, minWin=28, winSum=455
1286 05:55:42.798622 TX Vref=30, minBit 0, minWin=28, winSum=454
1287 05:55:42.805359 TX Vref=32, minBit 0, minWin=28, winSum=454
1288 05:55:42.808476 [TxChooseVref] Worse bit 2, Min win 28, Win sum 455, Final Vref 28
1289 05:55:42.808987
1290 05:55:42.811983 Final TX Range 1 Vref 28
1291 05:55:42.812401
1292 05:55:42.812812 ==
1293 05:55:42.815066 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 05:55:42.818656 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1295 05:55:42.819165 ==
1296 05:55:42.821711
1297 05:55:42.822169
1298 05:55:42.822532 TX Vref Scan disable
1299 05:55:42.825078 == TX Byte 0 ==
1300 05:55:42.828929 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1301 05:55:42.831959 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1302 05:55:42.835424 == TX Byte 1 ==
1303 05:55:42.838818 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1304 05:55:42.842346 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1305 05:55:42.845084
1306 05:55:42.845538 [DATLAT]
1307 05:55:42.845902 Freq=800, CH0 RK1
1308 05:55:42.846245
1309 05:55:42.848748 DATLAT Default: 0x9
1310 05:55:42.849292 0, 0xFFFF, sum = 0
1311 05:55:42.851688 1, 0xFFFF, sum = 0
1312 05:55:42.852153 2, 0xFFFF, sum = 0
1313 05:55:42.855168 3, 0xFFFF, sum = 0
1314 05:55:42.855705 4, 0xFFFF, sum = 0
1315 05:55:42.858565 5, 0xFFFF, sum = 0
1316 05:55:42.861663 6, 0xFFFF, sum = 0
1317 05:55:42.862159 7, 0xFFFF, sum = 0
1318 05:55:42.862538 8, 0x0, sum = 1
1319 05:55:42.865417 9, 0x0, sum = 2
1320 05:55:42.865899 10, 0x0, sum = 3
1321 05:55:42.868634 11, 0x0, sum = 4
1322 05:55:42.869141 best_step = 9
1323 05:55:42.869507
1324 05:55:42.869914 ==
1325 05:55:42.871918 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 05:55:42.878375 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1327 05:55:42.878895 ==
1328 05:55:42.879265 RX Vref Scan: 0
1329 05:55:42.879609
1330 05:55:42.881432 RX Vref 0 -> 0, step: 1
1331 05:55:42.881960
1332 05:55:42.885234 RX Delay -111 -> 252, step: 8
1333 05:55:42.888292 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1334 05:55:42.892000 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1335 05:55:42.898700 iDelay=217, Bit 2, Center 80 (-39 ~ 200) 240
1336 05:55:42.901521 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1337 05:55:42.904856 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1338 05:55:42.908641 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1339 05:55:42.911795 iDelay=217, Bit 6, Center 96 (-23 ~ 216) 240
1340 05:55:42.918012 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1341 05:55:42.921772 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1342 05:55:42.924918 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1343 05:55:42.928446 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1344 05:55:42.931655 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1345 05:55:42.938200 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1346 05:55:42.942139 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1347 05:55:42.944916 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1348 05:55:42.948051 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1349 05:55:42.948608 ==
1350 05:55:42.951494 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 05:55:42.958155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1352 05:55:42.958839 ==
1353 05:55:42.959370 DQS Delay:
1354 05:55:42.961401 DQS0 = 0, DQS1 = 0
1355 05:55:42.961861 DQM Delay:
1356 05:55:42.962232 DQM0 = 85, DQM1 = 74
1357 05:55:42.964806 DQ Delay:
1358 05:55:42.968159 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =80
1359 05:55:42.971398 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1360 05:55:42.974351 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1361 05:55:42.977954 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1362 05:55:42.978409
1363 05:55:42.978765
1364 05:55:42.984526 [DQSOSCAuto] RK1, (LSB)MR18= 0x4545, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1365 05:55:42.987876 CH0 RK1: MR19=606, MR18=4545
1366 05:55:42.994575 CH0_RK1: MR19=0x606, MR18=0x4545, DQSOSC=392, MR23=63, INC=96, DEC=64
1367 05:55:42.997913 [RxdqsGatingPostProcess] freq 800
1368 05:55:43.000922 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1369 05:55:43.004816 Pre-setting of DQS Precalculation
1370 05:55:43.011287 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1371 05:55:43.011567 ==
1372 05:55:43.014539 Dram Type= 6, Freq= 0, CH_1, rank 0
1373 05:55:43.017664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1374 05:55:43.017901 ==
1375 05:55:43.024331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1376 05:55:43.027931 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1377 05:55:43.038214 [CA 0] Center 36 (6~67) winsize 62
1378 05:55:43.041342 [CA 1] Center 36 (5~67) winsize 63
1379 05:55:43.044502 [CA 2] Center 34 (4~65) winsize 62
1380 05:55:43.048117 [CA 3] Center 34 (4~65) winsize 62
1381 05:55:43.051142 [CA 4] Center 33 (3~64) winsize 62
1382 05:55:43.054952 [CA 5] Center 33 (3~64) winsize 62
1383 05:55:43.055501
1384 05:55:43.057760 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1385 05:55:43.058175
1386 05:55:43.061401 [CATrainingPosCal] consider 1 rank data
1387 05:55:43.064557 u2DelayCellTimex100 = 270/100 ps
1388 05:55:43.068048 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1389 05:55:43.071562 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1390 05:55:43.077992 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1391 05:55:43.081395 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1392 05:55:43.084661 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1393 05:55:43.088284 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1394 05:55:43.088901
1395 05:55:43.091572 CA PerBit enable=1, Macro0, CA PI delay=33
1396 05:55:43.092030
1397 05:55:43.094958 [CBTSetCACLKResult] CA Dly = 33
1398 05:55:43.095544 CS Dly: 4 (0~35)
1399 05:55:43.095913 ==
1400 05:55:43.097854 Dram Type= 6, Freq= 0, CH_1, rank 1
1401 05:55:43.104828 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1402 05:55:43.105289 ==
1403 05:55:43.107733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1404 05:55:43.114648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1405 05:55:43.123760 [CA 0] Center 36 (6~67) winsize 62
1406 05:55:43.126937 [CA 1] Center 36 (5~67) winsize 63
1407 05:55:43.130556 [CA 2] Center 34 (4~65) winsize 62
1408 05:55:43.133631 [CA 3] Center 34 (3~65) winsize 63
1409 05:55:43.137232 [CA 4] Center 33 (3~64) winsize 62
1410 05:55:43.140533 [CA 5] Center 33 (3~64) winsize 62
1411 05:55:43.141396
1412 05:55:43.143655 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1413 05:55:43.144302
1414 05:55:43.147178 [CATrainingPosCal] consider 2 rank data
1415 05:55:43.150662 u2DelayCellTimex100 = 270/100 ps
1416 05:55:43.153736 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1417 05:55:43.157034 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1418 05:55:43.163815 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1419 05:55:43.167288 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1420 05:55:43.170746 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1421 05:55:43.173950 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1422 05:55:43.174502
1423 05:55:43.177275 CA PerBit enable=1, Macro0, CA PI delay=33
1424 05:55:43.177829
1425 05:55:43.180561 [CBTSetCACLKResult] CA Dly = 33
1426 05:55:43.181126 CS Dly: 4 (0~36)
1427 05:55:43.181490
1428 05:55:43.183792 ----->DramcWriteLeveling(PI) begin...
1429 05:55:43.187300 ==
1430 05:55:43.190479 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 05:55:43.193573 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1432 05:55:43.194030 ==
1433 05:55:43.196944 Write leveling (Byte 0): 24 => 24
1434 05:55:43.200281 Write leveling (Byte 1): 24 => 24
1435 05:55:43.203646 DramcWriteLeveling(PI) end<-----
1436 05:55:43.204105
1437 05:55:43.204460 ==
1438 05:55:43.206856 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 05:55:43.210257 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1440 05:55:43.210714 ==
1441 05:55:43.213626 [Gating] SW mode calibration
1442 05:55:43.220490 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1443 05:55:43.227159 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1444 05:55:43.230050 0 6 0 | B1->B0 | 3232 2525 | 0 0 | (0 1) (0 0)
1445 05:55:43.233218 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 05:55:43.239795 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 05:55:43.243051 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 05:55:43.246972 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 05:55:43.250001 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 05:55:43.256874 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 05:55:43.260630 0 6 28 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
1452 05:55:43.263459 0 7 0 | B1->B0 | 3030 3f3f | 1 0 | (0 0) (0 0)
1453 05:55:43.270104 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1454 05:55:43.273286 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1455 05:55:43.277034 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1456 05:55:43.283576 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1457 05:55:43.286326 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1458 05:55:43.289737 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1459 05:55:43.296468 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1460 05:55:43.300052 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1461 05:55:43.303057 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 05:55:43.309764 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 05:55:43.313021 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 05:55:43.316396 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 05:55:43.323235 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 05:55:43.326306 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 05:55:43.329845 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 05:55:43.336830 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 05:55:43.340002 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1470 05:55:43.342939 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1471 05:55:43.349721 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1472 05:55:43.353236 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1473 05:55:43.356818 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1474 05:55:43.360230 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1475 05:55:43.366835 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1476 05:55:43.369598 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1477 05:55:43.373218 Total UI for P1: 0, mck2ui 16
1478 05:55:43.376788 best dqsien dly found for B0: ( 0, 9, 28)
1479 05:55:43.379878 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1480 05:55:43.383184 Total UI for P1: 0, mck2ui 16
1481 05:55:43.386448 best dqsien dly found for B1: ( 0, 10, 0)
1482 05:55:43.389873 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1483 05:55:43.393314 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1484 05:55:43.396940
1485 05:55:43.399711 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1486 05:55:43.403269 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1487 05:55:43.406742 [Gating] SW calibration Done
1488 05:55:43.407311 ==
1489 05:55:43.409950 Dram Type= 6, Freq= 0, CH_1, rank 0
1490 05:55:43.413093 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1491 05:55:43.413664 ==
1492 05:55:43.414149 RX Vref Scan: 0
1493 05:55:43.416156
1494 05:55:43.416625 RX Vref 0 -> 0, step: 1
1495 05:55:43.417145
1496 05:55:43.419794 RX Delay -130 -> 252, step: 16
1497 05:55:43.422973 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1498 05:55:43.426281 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1499 05:55:43.432863 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1500 05:55:43.436279 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1501 05:55:43.439350 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1502 05:55:43.442835 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1503 05:55:43.446544 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1504 05:55:43.453202 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1505 05:55:43.456311 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1506 05:55:43.459090 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1507 05:55:43.462718 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1508 05:55:43.466087 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1509 05:55:43.472766 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1510 05:55:43.476250 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1511 05:55:43.479850 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1512 05:55:43.483615 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1513 05:55:43.484169 ==
1514 05:55:43.486243 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 05:55:43.493179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1516 05:55:43.493905 ==
1517 05:55:43.494351 DQS Delay:
1518 05:55:43.494703 DQS0 = 0, DQS1 = 0
1519 05:55:43.496382 DQM Delay:
1520 05:55:43.496879 DQM0 = 81, DQM1 = 72
1521 05:55:43.499468 DQ Delay:
1522 05:55:43.502869 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1523 05:55:43.506347 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1524 05:55:43.506801 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1525 05:55:43.513246 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1526 05:55:43.513856
1527 05:55:43.514223
1528 05:55:43.514555 ==
1529 05:55:43.516487 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 05:55:43.519417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1531 05:55:43.519873 ==
1532 05:55:43.520233
1533 05:55:43.520597
1534 05:55:43.523062 TX Vref Scan disable
1535 05:55:43.523608 == TX Byte 0 ==
1536 05:55:43.529384 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1537 05:55:43.533009 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1538 05:55:43.533463 == TX Byte 1 ==
1539 05:55:43.539294 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1540 05:55:43.542463 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1541 05:55:43.542924 ==
1542 05:55:43.545915 Dram Type= 6, Freq= 0, CH_1, rank 0
1543 05:55:43.549168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1544 05:55:43.549724 ==
1545 05:55:43.562960 TX Vref=22, minBit 1, minWin=27, winSum=448
1546 05:55:43.566559 TX Vref=24, minBit 0, minWin=28, winSum=453
1547 05:55:43.569591 TX Vref=26, minBit 2, minWin=28, winSum=456
1548 05:55:43.572843 TX Vref=28, minBit 2, minWin=28, winSum=461
1549 05:55:43.576762 TX Vref=30, minBit 9, minWin=28, winSum=462
1550 05:55:43.579842 TX Vref=32, minBit 8, minWin=28, winSum=461
1551 05:55:43.585984 [TxChooseVref] Worse bit 9, Min win 28, Win sum 462, Final Vref 30
1552 05:55:43.586549
1553 05:55:43.589349 Final TX Range 1 Vref 30
1554 05:55:43.589811
1555 05:55:43.590195 ==
1556 05:55:43.592778 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 05:55:43.595990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1558 05:55:43.596456 ==
1559 05:55:43.599139
1560 05:55:43.599598
1561 05:55:43.599963 TX Vref Scan disable
1562 05:55:43.602794 == TX Byte 0 ==
1563 05:55:43.606098 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1564 05:55:43.609303 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1565 05:55:43.612580 == TX Byte 1 ==
1566 05:55:43.615974 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1567 05:55:43.623057 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1568 05:55:43.623629
1569 05:55:43.624000 [DATLAT]
1570 05:55:43.624337 Freq=800, CH1 RK0
1571 05:55:43.624665
1572 05:55:43.626348 DATLAT Default: 0xa
1573 05:55:43.626807 0, 0xFFFF, sum = 0
1574 05:55:43.629622 1, 0xFFFF, sum = 0
1575 05:55:43.630088 2, 0xFFFF, sum = 0
1576 05:55:43.632884 3, 0xFFFF, sum = 0
1577 05:55:43.633355 4, 0xFFFF, sum = 0
1578 05:55:43.636239 5, 0xFFFF, sum = 0
1579 05:55:43.636862 6, 0xFFFF, sum = 0
1580 05:55:43.639354 7, 0xFFFF, sum = 0
1581 05:55:43.639821 8, 0x0, sum = 1
1582 05:55:43.642782 9, 0x0, sum = 2
1583 05:55:43.643279 10, 0x0, sum = 3
1584 05:55:43.646472 11, 0x0, sum = 4
1585 05:55:43.646988 best_step = 9
1586 05:55:43.647542
1587 05:55:43.647918 ==
1588 05:55:43.649493 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 05:55:43.656102 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1590 05:55:43.656565 ==
1591 05:55:43.657158 RX Vref Scan: 1
1592 05:55:43.657523
1593 05:55:43.659430 Set Vref Range= 32 -> 127
1594 05:55:43.659890
1595 05:55:43.662703 RX Vref 32 -> 127, step: 1
1596 05:55:43.663272
1597 05:55:43.665815 RX Delay -111 -> 252, step: 8
1598 05:55:43.666291
1599 05:55:43.669180 Set Vref, RX VrefLevel [Byte0]: 32
1600 05:55:43.672265 [Byte1]: 32
1601 05:55:43.672766
1602 05:55:43.676635 Set Vref, RX VrefLevel [Byte0]: 33
1603 05:55:43.679068 [Byte1]: 33
1604 05:55:43.679537
1605 05:55:43.682391 Set Vref, RX VrefLevel [Byte0]: 34
1606 05:55:43.685750 [Byte1]: 34
1607 05:55:43.686201
1608 05:55:43.689093 Set Vref, RX VrefLevel [Byte0]: 35
1609 05:55:43.692187 [Byte1]: 35
1610 05:55:43.696529
1611 05:55:43.697118 Set Vref, RX VrefLevel [Byte0]: 36
1612 05:55:43.700160 [Byte1]: 36
1613 05:55:43.704213
1614 05:55:43.704667 Set Vref, RX VrefLevel [Byte0]: 37
1615 05:55:43.707538 [Byte1]: 37
1616 05:55:43.712032
1617 05:55:43.712519 Set Vref, RX VrefLevel [Byte0]: 38
1618 05:55:43.715176 [Byte1]: 38
1619 05:55:43.719872
1620 05:55:43.720435 Set Vref, RX VrefLevel [Byte0]: 39
1621 05:55:43.723107 [Byte1]: 39
1622 05:55:43.727831
1623 05:55:43.728392 Set Vref, RX VrefLevel [Byte0]: 40
1624 05:55:43.730904 [Byte1]: 40
1625 05:55:43.735381
1626 05:55:43.735933 Set Vref, RX VrefLevel [Byte0]: 41
1627 05:55:43.737962 [Byte1]: 41
1628 05:55:43.742338
1629 05:55:43.742828 Set Vref, RX VrefLevel [Byte0]: 42
1630 05:55:43.745585 [Byte1]: 42
1631 05:55:43.750158
1632 05:55:43.750707 Set Vref, RX VrefLevel [Byte0]: 43
1633 05:55:43.753343 [Byte1]: 43
1634 05:55:43.757788
1635 05:55:43.758241 Set Vref, RX VrefLevel [Byte0]: 44
1636 05:55:43.761261 [Byte1]: 44
1637 05:55:43.765313
1638 05:55:43.765811 Set Vref, RX VrefLevel [Byte0]: 45
1639 05:55:43.768785 [Byte1]: 45
1640 05:55:43.773480
1641 05:55:43.774031 Set Vref, RX VrefLevel [Byte0]: 46
1642 05:55:43.776679 [Byte1]: 46
1643 05:55:43.780928
1644 05:55:43.781381 Set Vref, RX VrefLevel [Byte0]: 47
1645 05:55:43.784036 [Byte1]: 47
1646 05:55:43.788430
1647 05:55:43.791872 Set Vref, RX VrefLevel [Byte0]: 48
1648 05:55:43.792622 [Byte1]: 48
1649 05:55:43.795922
1650 05:55:43.796398 Set Vref, RX VrefLevel [Byte0]: 49
1651 05:55:43.799555 [Byte1]: 49
1652 05:55:43.803863
1653 05:55:43.804406 Set Vref, RX VrefLevel [Byte0]: 50
1654 05:55:43.806810 [Byte1]: 50
1655 05:55:43.811288
1656 05:55:43.811766 Set Vref, RX VrefLevel [Byte0]: 51
1657 05:55:43.815187 [Byte1]: 51
1658 05:55:43.819327
1659 05:55:43.819964 Set Vref, RX VrefLevel [Byte0]: 52
1660 05:55:43.822434 [Byte1]: 52
1661 05:55:43.826919
1662 05:55:43.827393 Set Vref, RX VrefLevel [Byte0]: 53
1663 05:55:43.829761 [Byte1]: 53
1664 05:55:43.834554
1665 05:55:43.835127 Set Vref, RX VrefLevel [Byte0]: 54
1666 05:55:43.837913 [Byte1]: 54
1667 05:55:43.842426
1668 05:55:43.843021 Set Vref, RX VrefLevel [Byte0]: 55
1669 05:55:43.845316 [Byte1]: 55
1670 05:55:43.849767
1671 05:55:43.850312 Set Vref, RX VrefLevel [Byte0]: 56
1672 05:55:43.852832 [Byte1]: 56
1673 05:55:43.857307
1674 05:55:43.857864 Set Vref, RX VrefLevel [Byte0]: 57
1675 05:55:43.860888 [Byte1]: 57
1676 05:55:43.865058
1677 05:55:43.865616 Set Vref, RX VrefLevel [Byte0]: 58
1678 05:55:43.868068 [Byte1]: 58
1679 05:55:43.872833
1680 05:55:43.873448 Set Vref, RX VrefLevel [Byte0]: 59
1681 05:55:43.875701 [Byte1]: 59
1682 05:55:43.880575
1683 05:55:43.881211 Set Vref, RX VrefLevel [Byte0]: 60
1684 05:55:43.883727 [Byte1]: 60
1685 05:55:43.887868
1686 05:55:43.888385 Set Vref, RX VrefLevel [Byte0]: 61
1687 05:55:43.891035 [Byte1]: 61
1688 05:55:43.895547
1689 05:55:43.896192 Set Vref, RX VrefLevel [Byte0]: 62
1690 05:55:43.898713 [Byte1]: 62
1691 05:55:43.902900
1692 05:55:43.903397 Set Vref, RX VrefLevel [Byte0]: 63
1693 05:55:43.906626 [Byte1]: 63
1694 05:55:43.910956
1695 05:55:43.911312 Set Vref, RX VrefLevel [Byte0]: 64
1696 05:55:43.913990 [Byte1]: 64
1697 05:55:43.918409
1698 05:55:43.918649 Set Vref, RX VrefLevel [Byte0]: 65
1699 05:55:43.921491 [Byte1]: 65
1700 05:55:43.925574
1701 05:55:43.925763 Set Vref, RX VrefLevel [Byte0]: 66
1702 05:55:43.929407 [Byte1]: 66
1703 05:55:43.933259
1704 05:55:43.933450 Set Vref, RX VrefLevel [Byte0]: 67
1705 05:55:43.936557 [Byte1]: 67
1706 05:55:43.940949
1707 05:55:43.941139 Set Vref, RX VrefLevel [Byte0]: 68
1708 05:55:43.944115 [Byte1]: 68
1709 05:55:43.948646
1710 05:55:43.948871 Set Vref, RX VrefLevel [Byte0]: 69
1711 05:55:43.952236 [Byte1]: 69
1712 05:55:43.956174
1713 05:55:43.956418 Set Vref, RX VrefLevel [Byte0]: 70
1714 05:55:43.959904 [Byte1]: 70
1715 05:55:43.963939
1716 05:55:43.964126 Set Vref, RX VrefLevel [Byte0]: 71
1717 05:55:43.967177 [Byte1]: 71
1718 05:55:43.971765
1719 05:55:43.971954 Set Vref, RX VrefLevel [Byte0]: 72
1720 05:55:43.975215 [Byte1]: 72
1721 05:55:43.979150
1722 05:55:43.979340 Set Vref, RX VrefLevel [Byte0]: 73
1723 05:55:43.982814 [Byte1]: 73
1724 05:55:43.986750
1725 05:55:43.986940 Set Vref, RX VrefLevel [Byte0]: 74
1726 05:55:43.990314 [Byte1]: 74
1727 05:55:43.995018
1728 05:55:43.995213 Set Vref, RX VrefLevel [Byte0]: 75
1729 05:55:43.998162 [Byte1]: 75
1730 05:55:44.002149
1731 05:55:44.002338 Set Vref, RX VrefLevel [Byte0]: 76
1732 05:55:44.005752 [Byte1]: 76
1733 05:55:44.010086
1734 05:55:44.010372 Final RX Vref Byte 0 = 61 to rank0
1735 05:55:44.013344 Final RX Vref Byte 1 = 54 to rank0
1736 05:55:44.016906 Final RX Vref Byte 0 = 61 to rank1
1737 05:55:44.020276 Final RX Vref Byte 1 = 54 to rank1==
1738 05:55:44.023914 Dram Type= 6, Freq= 0, CH_1, rank 0
1739 05:55:44.030065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1740 05:55:44.030530 ==
1741 05:55:44.030900 DQS Delay:
1742 05:55:44.031301 DQS0 = 0, DQS1 = 0
1743 05:55:44.033327 DQM Delay:
1744 05:55:44.033791 DQM0 = 79, DQM1 = 72
1745 05:55:44.037040 DQ Delay:
1746 05:55:44.040471 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1747 05:55:44.040993 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1748 05:55:44.043605 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1749 05:55:44.047119 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1750 05:55:44.050711
1751 05:55:44.051262
1752 05:55:44.057143 [DQSOSCAuto] RK0, (LSB)MR18= 0x4848, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1753 05:55:44.060762 CH1 RK0: MR19=606, MR18=4848
1754 05:55:44.067264 CH1_RK0: MR19=0x606, MR18=0x4848, DQSOSC=391, MR23=63, INC=96, DEC=64
1755 05:55:44.067817
1756 05:55:44.070347 ----->DramcWriteLeveling(PI) begin...
1757 05:55:44.070940 ==
1758 05:55:44.073603 Dram Type= 6, Freq= 0, CH_1, rank 1
1759 05:55:44.077024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1760 05:55:44.077485 ==
1761 05:55:44.080306 Write leveling (Byte 0): 25 => 25
1762 05:55:44.084035 Write leveling (Byte 1): 25 => 25
1763 05:55:44.087116 DramcWriteLeveling(PI) end<-----
1764 05:55:44.087573
1765 05:55:44.087939 ==
1766 05:55:44.090139 Dram Type= 6, Freq= 0, CH_1, rank 1
1767 05:55:44.093987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1768 05:55:44.094546 ==
1769 05:55:44.096663 [Gating] SW mode calibration
1770 05:55:44.103678 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1771 05:55:44.110245 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1772 05:55:44.113705 0 6 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1773 05:55:44.116790 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1774 05:55:44.123488 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1775 05:55:44.126809 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1776 05:55:44.130316 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1777 05:55:44.136766 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1778 05:55:44.139999 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1779 05:55:44.143646 0 6 28 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
1780 05:55:44.150493 0 7 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1781 05:55:44.153699 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1782 05:55:44.156830 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1783 05:55:44.163833 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1784 05:55:44.166717 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1785 05:55:44.169915 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1786 05:55:44.176851 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1787 05:55:44.180230 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1788 05:55:44.183486 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1789 05:55:44.186603 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 05:55:44.193340 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 05:55:44.196782 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 05:55:44.199834 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 05:55:44.206846 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 05:55:44.210176 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1795 05:55:44.213148 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1796 05:55:44.220139 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1797 05:55:44.223128 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1798 05:55:44.226895 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1799 05:55:44.233275 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1800 05:55:44.236698 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1801 05:55:44.240413 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1802 05:55:44.246802 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1803 05:55:44.250393 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1804 05:55:44.253513 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1805 05:55:44.260566 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1806 05:55:44.261162 Total UI for P1: 0, mck2ui 16
1807 05:55:44.263794 best dqsien dly found for B0: ( 0, 9, 30)
1808 05:55:44.266868 Total UI for P1: 0, mck2ui 16
1809 05:55:44.270076 best dqsien dly found for B1: ( 0, 10, 0)
1810 05:55:44.277020 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1811 05:55:44.280536 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1812 05:55:44.281153
1813 05:55:44.283873 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1814 05:55:44.287142 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1815 05:55:44.290247 [Gating] SW calibration Done
1816 05:55:44.290703 ==
1817 05:55:44.293360 Dram Type= 6, Freq= 0, CH_1, rank 1
1818 05:55:44.296436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1819 05:55:44.296934 ==
1820 05:55:44.300279 RX Vref Scan: 0
1821 05:55:44.300777
1822 05:55:44.301152 RX Vref 0 -> 0, step: 1
1823 05:55:44.301679
1824 05:55:44.303397 RX Delay -130 -> 252, step: 16
1825 05:55:44.306537 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1826 05:55:44.313252 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1827 05:55:44.316393 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1828 05:55:44.320191 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1829 05:55:44.323357 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1830 05:55:44.326592 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1831 05:55:44.333120 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1832 05:55:44.336449 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1833 05:55:44.340105 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1834 05:55:44.343181 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1835 05:55:44.346511 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1836 05:55:44.352973 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1837 05:55:44.356481 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1838 05:55:44.359791 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1839 05:55:44.363095 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1840 05:55:44.366403 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1841 05:55:44.369560 ==
1842 05:55:44.370018 Dram Type= 6, Freq= 0, CH_1, rank 1
1843 05:55:44.376496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1844 05:55:44.377111 ==
1845 05:55:44.377485 DQS Delay:
1846 05:55:44.379798 DQS0 = 0, DQS1 = 0
1847 05:55:44.380253 DQM Delay:
1848 05:55:44.383086 DQM0 = 82, DQM1 = 70
1849 05:55:44.383640 DQ Delay:
1850 05:55:44.386302 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1851 05:55:44.389715 DQ4 =77, DQ5 =101, DQ6 =85, DQ7 =77
1852 05:55:44.393050 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1853 05:55:44.396447 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1854 05:55:44.396961
1855 05:55:44.397333
1856 05:55:44.397672 ==
1857 05:55:44.399746 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 05:55:44.403112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1859 05:55:44.403750 ==
1860 05:55:44.404265
1861 05:55:44.404614
1862 05:55:44.406255 TX Vref Scan disable
1863 05:55:44.410021 == TX Byte 0 ==
1864 05:55:44.413203 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1865 05:55:44.416247 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1866 05:55:44.419890 == TX Byte 1 ==
1867 05:55:44.423295 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1868 05:55:44.426494 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1869 05:55:44.426956 ==
1870 05:55:44.430053 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 05:55:44.433170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1872 05:55:44.436408 ==
1873 05:55:44.447277 TX Vref=22, minBit 8, minWin=27, winSum=447
1874 05:55:44.450759 TX Vref=24, minBit 0, minWin=28, winSum=453
1875 05:55:44.453695 TX Vref=26, minBit 3, minWin=28, winSum=456
1876 05:55:44.456826 TX Vref=28, minBit 3, minWin=28, winSum=456
1877 05:55:44.460626 TX Vref=30, minBit 0, minWin=28, winSum=457
1878 05:55:44.463674 TX Vref=32, minBit 0, minWin=28, winSum=454
1879 05:55:44.470523 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1880 05:55:44.470978
1881 05:55:44.473938 Final TX Range 1 Vref 30
1882 05:55:44.474393
1883 05:55:44.474748 ==
1884 05:55:44.477077 Dram Type= 6, Freq= 0, CH_1, rank 1
1885 05:55:44.480920 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1886 05:55:44.481476 ==
1887 05:55:44.481903
1888 05:55:44.483794
1889 05:55:44.484379 TX Vref Scan disable
1890 05:55:44.486847 == TX Byte 0 ==
1891 05:55:44.490215 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1892 05:55:44.497343 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1893 05:55:44.497796 == TX Byte 1 ==
1894 05:55:44.500505 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1895 05:55:44.507079 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1896 05:55:44.507640
1897 05:55:44.508004 [DATLAT]
1898 05:55:44.508341 Freq=800, CH1 RK1
1899 05:55:44.508668
1900 05:55:44.510630 DATLAT Default: 0x9
1901 05:55:44.511140 0, 0xFFFF, sum = 0
1902 05:55:44.513850 1, 0xFFFF, sum = 0
1903 05:55:44.514309 2, 0xFFFF, sum = 0
1904 05:55:44.517287 3, 0xFFFF, sum = 0
1905 05:55:44.517749 4, 0xFFFF, sum = 0
1906 05:55:44.520527 5, 0xFFFF, sum = 0
1907 05:55:44.521028 6, 0xFFFF, sum = 0
1908 05:55:44.523877 7, 0xFFFF, sum = 0
1909 05:55:44.524340 8, 0x0, sum = 1
1910 05:55:44.527337 9, 0x0, sum = 2
1911 05:55:44.527798 10, 0x0, sum = 3
1912 05:55:44.530642 11, 0x0, sum = 4
1913 05:55:44.531203 best_step = 9
1914 05:55:44.531568
1915 05:55:44.531964 ==
1916 05:55:44.533554 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 05:55:44.540566 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1918 05:55:44.541209 ==
1919 05:55:44.541582 RX Vref Scan: 0
1920 05:55:44.542004
1921 05:55:44.543907 RX Vref 0 -> 0, step: 1
1922 05:55:44.544363
1923 05:55:44.547213 RX Delay -111 -> 252, step: 8
1924 05:55:44.550643 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1925 05:55:44.553966 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1926 05:55:44.560405 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1927 05:55:44.563773 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1928 05:55:44.567204 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1929 05:55:44.570301 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1930 05:55:44.573793 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1931 05:55:44.577012 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1932 05:55:44.583651 iDelay=209, Bit 8, Center 56 (-63 ~ 176) 240
1933 05:55:44.587353 iDelay=209, Bit 9, Center 60 (-63 ~ 184) 248
1934 05:55:44.590637 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1935 05:55:44.593944 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1936 05:55:44.600503 iDelay=209, Bit 12, Center 84 (-39 ~ 208) 248
1937 05:55:44.603429 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1938 05:55:44.606838 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1939 05:55:44.610300 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1940 05:55:44.610868 ==
1941 05:55:44.613437 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 05:55:44.620657 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1943 05:55:44.621290 ==
1944 05:55:44.621690 DQS Delay:
1945 05:55:44.622030 DQS0 = 0, DQS1 = 0
1946 05:55:44.623464 DQM Delay:
1947 05:55:44.623958 DQM0 = 82, DQM1 = 72
1948 05:55:44.626836 DQ Delay:
1949 05:55:44.630250 DQ0 =84, DQ1 =80, DQ2 =72, DQ3 =80
1950 05:55:44.630720 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =80
1951 05:55:44.633408 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1952 05:55:44.637281 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
1953 05:55:44.640460
1954 05:55:44.641149
1955 05:55:44.646827 [DQSOSCAuto] RK1, (LSB)MR18= 0x3939, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1956 05:55:44.649969 CH1 RK1: MR19=606, MR18=3939
1957 05:55:44.656859 CH1_RK1: MR19=0x606, MR18=0x3939, DQSOSC=395, MR23=63, INC=94, DEC=63
1958 05:55:44.660541 [RxdqsGatingPostProcess] freq 800
1959 05:55:44.664013 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1960 05:55:44.667409 Pre-setting of DQS Precalculation
1961 05:55:44.673390 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1962 05:55:44.680090 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1963 05:55:44.686783 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1964 05:55:44.687328
1965 05:55:44.687691
1966 05:55:44.690146 [Calibration Summary] 1600 Mbps
1967 05:55:44.690602 CH 0, Rank 0
1968 05:55:44.693314 SW Impedance : PASS
1969 05:55:44.693768 DUTY Scan : NO K
1970 05:55:44.696677 ZQ Calibration : PASS
1971 05:55:44.699883 Jitter Meter : NO K
1972 05:55:44.700351 CBT Training : PASS
1973 05:55:44.703191 Write leveling : PASS
1974 05:55:44.706656 RX DQS gating : PASS
1975 05:55:44.707115 RX DQ/DQS(RDDQC) : PASS
1976 05:55:44.710186 TX DQ/DQS : PASS
1977 05:55:44.713500 RX DATLAT : PASS
1978 05:55:44.713960 RX DQ/DQS(Engine): PASS
1979 05:55:44.717103 TX OE : NO K
1980 05:55:44.717673 All Pass.
1981 05:55:44.718041
1982 05:55:44.720030 CH 0, Rank 1
1983 05:55:44.720483 SW Impedance : PASS
1984 05:55:44.723456 DUTY Scan : NO K
1985 05:55:44.726633 ZQ Calibration : PASS
1986 05:55:44.727087 Jitter Meter : NO K
1987 05:55:44.729728 CBT Training : PASS
1988 05:55:44.733513 Write leveling : PASS
1989 05:55:44.734064 RX DQS gating : PASS
1990 05:55:44.736571 RX DQ/DQS(RDDQC) : PASS
1991 05:55:44.737083 TX DQ/DQS : PASS
1992 05:55:44.739757 RX DATLAT : PASS
1993 05:55:44.743731 RX DQ/DQS(Engine): PASS
1994 05:55:44.744282 TX OE : NO K
1995 05:55:44.746362 All Pass.
1996 05:55:44.746749
1997 05:55:44.747089 CH 1, Rank 0
1998 05:55:44.750161 SW Impedance : PASS
1999 05:55:44.750690 DUTY Scan : NO K
2000 05:55:44.753133 ZQ Calibration : PASS
2001 05:55:44.756431 Jitter Meter : NO K
2002 05:55:44.757041 CBT Training : PASS
2003 05:55:44.760239 Write leveling : PASS
2004 05:55:44.763096 RX DQS gating : PASS
2005 05:55:44.763645 RX DQ/DQS(RDDQC) : PASS
2006 05:55:44.766311 TX DQ/DQS : PASS
2007 05:55:44.770515 RX DATLAT : PASS
2008 05:55:44.771067 RX DQ/DQS(Engine): PASS
2009 05:55:44.772921 TX OE : NO K
2010 05:55:44.773379 All Pass.
2011 05:55:44.773741
2012 05:55:44.777078 CH 1, Rank 1
2013 05:55:44.777629 SW Impedance : PASS
2014 05:55:44.780077 DUTY Scan : NO K
2015 05:55:44.783086 ZQ Calibration : PASS
2016 05:55:44.783541 Jitter Meter : NO K
2017 05:55:44.786612 CBT Training : PASS
2018 05:55:44.787165 Write leveling : PASS
2019 05:55:44.789863 RX DQS gating : PASS
2020 05:55:44.793155 RX DQ/DQS(RDDQC) : PASS
2021 05:55:44.793610 TX DQ/DQS : PASS
2022 05:55:44.796946 RX DATLAT : PASS
2023 05:55:44.799929 RX DQ/DQS(Engine): PASS
2024 05:55:44.800418 TX OE : NO K
2025 05:55:44.803064 All Pass.
2026 05:55:44.803516
2027 05:55:44.803951 DramC Write-DBI off
2028 05:55:44.806522 PER_BANK_REFRESH: Hybrid Mode
2029 05:55:44.809590 TX_TRACKING: ON
2030 05:55:44.813053 [GetDramInforAfterCalByMRR] Vendor 6.
2031 05:55:44.816585 [GetDramInforAfterCalByMRR] Revision 606.
2032 05:55:44.819952 [GetDramInforAfterCalByMRR] Revision 2 0.
2033 05:55:44.820542 MR0 0x3939
2034 05:55:44.820969 MR8 0x1111
2035 05:55:44.822978 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2036 05:55:44.826166
2037 05:55:44.826621 MR0 0x3939
2038 05:55:44.826981 MR8 0x1111
2039 05:55:44.829597 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2040 05:55:44.830053
2041 05:55:44.839550 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2042 05:55:44.842957 [FAST_K] Save calibration result to emmc
2043 05:55:44.846728 [FAST_K] Save calibration result to emmc
2044 05:55:44.849466 dram_init: config_dvfs: 1
2045 05:55:44.852743 dramc_set_vcore_voltage set vcore to 662500
2046 05:55:44.856488 Read voltage for 1200, 2
2047 05:55:44.857098 Vio18 = 0
2048 05:55:44.857474 Vcore = 662500
2049 05:55:44.859519 Vdram = 0
2050 05:55:44.859993 Vddq = 0
2051 05:55:44.860406 Vmddr = 0
2052 05:55:44.866947 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2053 05:55:44.869679 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2054 05:55:44.873403 MEM_TYPE=3, freq_sel=15
2055 05:55:44.876240 sv_algorithm_assistance_LP4_1600
2056 05:55:44.879727 ============ PULL DRAM RESETB DOWN ============
2057 05:55:44.882772 ========== PULL DRAM RESETB DOWN end =========
2058 05:55:44.889618 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2059 05:55:44.892683 ===================================
2060 05:55:44.896641 LPDDR4 DRAM CONFIGURATION
2061 05:55:44.899327 ===================================
2062 05:55:44.899784 EX_ROW_EN[0] = 0x0
2063 05:55:44.903225 EX_ROW_EN[1] = 0x0
2064 05:55:44.903676 LP4Y_EN = 0x0
2065 05:55:44.905863 WORK_FSP = 0x0
2066 05:55:44.906310 WL = 0x4
2067 05:55:44.909508 RL = 0x4
2068 05:55:44.909960 BL = 0x2
2069 05:55:44.912459 RPST = 0x0
2070 05:55:44.913136 RD_PRE = 0x0
2071 05:55:44.916464 WR_PRE = 0x1
2072 05:55:44.917069 WR_PST = 0x0
2073 05:55:44.919251 DBI_WR = 0x0
2074 05:55:44.919702 DBI_RD = 0x0
2075 05:55:44.922544 OTF = 0x1
2076 05:55:44.925956 ===================================
2077 05:55:44.929091 ===================================
2078 05:55:44.929634 ANA top config
2079 05:55:44.932661 ===================================
2080 05:55:44.935831 DLL_ASYNC_EN = 0
2081 05:55:44.939729 ALL_SLAVE_EN = 0
2082 05:55:44.942938 NEW_RANK_MODE = 1
2083 05:55:44.943402 DLL_IDLE_MODE = 1
2084 05:55:44.946006 LP45_APHY_COMB_EN = 1
2085 05:55:44.949386 TX_ODT_DIS = 1
2086 05:55:44.953179 NEW_8X_MODE = 1
2087 05:55:44.955958 ===================================
2088 05:55:44.959289 ===================================
2089 05:55:44.963051 data_rate = 2400
2090 05:55:44.963605 CKR = 1
2091 05:55:44.966505 DQ_P2S_RATIO = 8
2092 05:55:44.969110 ===================================
2093 05:55:44.972409 CA_P2S_RATIO = 8
2094 05:55:44.975767 DQ_CA_OPEN = 0
2095 05:55:44.979413 DQ_SEMI_OPEN = 0
2096 05:55:44.982463 CA_SEMI_OPEN = 0
2097 05:55:44.982921 CA_FULL_RATE = 0
2098 05:55:44.985800 DQ_CKDIV4_EN = 0
2099 05:55:44.989054 CA_CKDIV4_EN = 0
2100 05:55:44.992966 CA_PREDIV_EN = 0
2101 05:55:44.996527 PH8_DLY = 17
2102 05:55:44.999789 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2103 05:55:45.000243 DQ_AAMCK_DIV = 4
2104 05:55:45.002588 CA_AAMCK_DIV = 4
2105 05:55:45.005838 CA_ADMCK_DIV = 4
2106 05:55:45.009065 DQ_TRACK_CA_EN = 0
2107 05:55:45.012479 CA_PICK = 1200
2108 05:55:45.015858 CA_MCKIO = 1200
2109 05:55:45.019510 MCKIO_SEMI = 0
2110 05:55:45.019965 PLL_FREQ = 2366
2111 05:55:45.022326 DQ_UI_PI_RATIO = 32
2112 05:55:45.026034 CA_UI_PI_RATIO = 0
2113 05:55:45.029240 ===================================
2114 05:55:45.032429 ===================================
2115 05:55:45.035805 memory_type:LPDDR4
2116 05:55:45.036344 GP_NUM : 10
2117 05:55:45.039072 SRAM_EN : 1
2118 05:55:45.042518 MD32_EN : 0
2119 05:55:45.045600 ===================================
2120 05:55:45.046172 [ANA_INIT] >>>>>>>>>>>>>>
2121 05:55:45.048943 <<<<<< [CONFIGURE PHASE]: ANA_TX
2122 05:55:45.052164 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2123 05:55:45.055931 ===================================
2124 05:55:45.059347 data_rate = 2400,PCW = 0X5b00
2125 05:55:45.062348 ===================================
2126 05:55:45.065664 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2127 05:55:45.072572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2128 05:55:45.075705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2129 05:55:45.082337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2130 05:55:45.085946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2131 05:55:45.089065 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2132 05:55:45.089486 [ANA_INIT] flow start
2133 05:55:45.092284 [ANA_INIT] PLL >>>>>>>>
2134 05:55:45.096116 [ANA_INIT] PLL <<<<<<<<
2135 05:55:45.099194 [ANA_INIT] MIDPI >>>>>>>>
2136 05:55:45.099813 [ANA_INIT] MIDPI <<<<<<<<
2137 05:55:45.102532 [ANA_INIT] DLL >>>>>>>>
2138 05:55:45.105506 [ANA_INIT] DLL <<<<<<<<
2139 05:55:45.105971 [ANA_INIT] flow end
2140 05:55:45.108696 ============ LP4 DIFF to SE enter ============
2141 05:55:45.116182 ============ LP4 DIFF to SE exit ============
2142 05:55:45.116791 [ANA_INIT] <<<<<<<<<<<<<
2143 05:55:45.119199 [Flow] Enable top DCM control >>>>>
2144 05:55:45.122322 [Flow] Enable top DCM control <<<<<
2145 05:55:45.125728 Enable DLL master slave shuffle
2146 05:55:45.132040 ==============================================================
2147 05:55:45.132497 Gating Mode config
2148 05:55:45.139451 ==============================================================
2149 05:55:45.141946 Config description:
2150 05:55:45.152454 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2151 05:55:45.158814 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2152 05:55:45.162113 SELPH_MODE 0: By rank 1: By Phase
2153 05:55:45.169298 ==============================================================
2154 05:55:45.172748 GAT_TRACK_EN = 1
2155 05:55:45.173302 RX_GATING_MODE = 2
2156 05:55:45.176005 RX_GATING_TRACK_MODE = 2
2157 05:55:45.178920 SELPH_MODE = 1
2158 05:55:45.182379 PICG_EARLY_EN = 1
2159 05:55:45.185639 VALID_LAT_VALUE = 1
2160 05:55:45.191799 ==============================================================
2161 05:55:45.195816 Enter into Gating configuration >>>>
2162 05:55:45.198892 Exit from Gating configuration <<<<
2163 05:55:45.202157 Enter into DVFS_PRE_config >>>>>
2164 05:55:45.212561 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2165 05:55:45.215762 Exit from DVFS_PRE_config <<<<<
2166 05:55:45.218607 Enter into PICG configuration >>>>
2167 05:55:45.222172 Exit from PICG configuration <<<<
2168 05:55:45.225146 [RX_INPUT] configuration >>>>>
2169 05:55:45.228885 [RX_INPUT] configuration <<<<<
2170 05:55:45.232413 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2171 05:55:45.238893 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2172 05:55:45.245685 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2173 05:55:45.248899 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2174 05:55:45.255838 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2175 05:55:45.261948 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2176 05:55:45.265342 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2177 05:55:45.268941 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2178 05:55:45.275307 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2179 05:55:45.278957 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2180 05:55:45.282069 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2181 05:55:45.288566 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2182 05:55:45.291588 ===================================
2183 05:55:45.292105 LPDDR4 DRAM CONFIGURATION
2184 05:55:45.295398 ===================================
2185 05:55:45.298800 EX_ROW_EN[0] = 0x0
2186 05:55:45.301677 EX_ROW_EN[1] = 0x0
2187 05:55:45.302136 LP4Y_EN = 0x0
2188 05:55:45.305136 WORK_FSP = 0x0
2189 05:55:45.305590 WL = 0x4
2190 05:55:45.308232 RL = 0x4
2191 05:55:45.308687 BL = 0x2
2192 05:55:45.311618 RPST = 0x0
2193 05:55:45.312084 RD_PRE = 0x0
2194 05:55:45.315467 WR_PRE = 0x1
2195 05:55:45.315917 WR_PST = 0x0
2196 05:55:45.318343 DBI_WR = 0x0
2197 05:55:45.318796 DBI_RD = 0x0
2198 05:55:45.321779 OTF = 0x1
2199 05:55:45.325023 ===================================
2200 05:55:45.328592 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2201 05:55:45.331818 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2202 05:55:45.338528 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2203 05:55:45.338989 ===================================
2204 05:55:45.341739 LPDDR4 DRAM CONFIGURATION
2205 05:55:45.344904 ===================================
2206 05:55:45.348243 EX_ROW_EN[0] = 0x10
2207 05:55:45.348845 EX_ROW_EN[1] = 0x0
2208 05:55:45.351537 LP4Y_EN = 0x0
2209 05:55:45.351990 WORK_FSP = 0x0
2210 05:55:45.355431 WL = 0x4
2211 05:55:45.355987 RL = 0x4
2212 05:55:45.358389 BL = 0x2
2213 05:55:45.361530 RPST = 0x0
2214 05:55:45.362079 RD_PRE = 0x0
2215 05:55:45.365272 WR_PRE = 0x1
2216 05:55:45.365857 WR_PST = 0x0
2217 05:55:45.368033 DBI_WR = 0x0
2218 05:55:45.368483 DBI_RD = 0x0
2219 05:55:45.371651 OTF = 0x1
2220 05:55:45.375092 ===================================
2221 05:55:45.378388 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2222 05:55:45.382147 ==
2223 05:55:45.382694 Dram Type= 6, Freq= 0, CH_0, rank 0
2224 05:55:45.388137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2225 05:55:45.388601 ==
2226 05:55:45.391760 [Duty_Offset_Calibration]
2227 05:55:45.392216 B0:0 B1:2 CA:1
2228 05:55:45.392583
2229 05:55:45.394693 [DutyScan_Calibration_Flow] k_type=0
2230 05:55:45.404442
2231 05:55:45.405027 ==CLK 0==
2232 05:55:45.408203 Final CLK duty delay cell = 0
2233 05:55:45.411108 [0] MAX Duty = 5093%(X100), DQS PI = 12
2234 05:55:45.414448 [0] MIN Duty = 4938%(X100), DQS PI = 54
2235 05:55:45.414904 [0] AVG Duty = 5015%(X100)
2236 05:55:45.417608
2237 05:55:45.420849 CH0 CLK Duty spec in!! Max-Min= 155%
2238 05:55:45.424223 [DutyScan_Calibration_Flow] ====Done====
2239 05:55:45.424681
2240 05:55:45.428009 [DutyScan_Calibration_Flow] k_type=1
2241 05:55:45.443973
2242 05:55:45.444525 ==DQS 0 ==
2243 05:55:45.446900 Final DQS duty delay cell = 0
2244 05:55:45.450437 [0] MAX Duty = 5125%(X100), DQS PI = 30
2245 05:55:45.453715 [0] MIN Duty = 5031%(X100), DQS PI = 6
2246 05:55:45.454406 [0] AVG Duty = 5078%(X100)
2247 05:55:45.456795
2248 05:55:45.457362 ==DQS 1 ==
2249 05:55:45.460148 Final DQS duty delay cell = 0
2250 05:55:45.463705 [0] MAX Duty = 5031%(X100), DQS PI = 54
2251 05:55:45.467214 [0] MIN Duty = 4906%(X100), DQS PI = 14
2252 05:55:45.467809 [0] AVG Duty = 4968%(X100)
2253 05:55:45.470921
2254 05:55:45.474097 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2255 05:55:45.474822
2256 05:55:45.477038 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2257 05:55:45.480990 [DutyScan_Calibration_Flow] ====Done====
2258 05:55:45.481546
2259 05:55:45.483687 [DutyScan_Calibration_Flow] k_type=3
2260 05:55:45.500676
2261 05:55:45.501275 ==DQM 0 ==
2262 05:55:45.504443 Final DQM duty delay cell = 0
2263 05:55:45.507936 [0] MAX Duty = 5124%(X100), DQS PI = 20
2264 05:55:45.510788 [0] MIN Duty = 4969%(X100), DQS PI = 40
2265 05:55:45.511248 [0] AVG Duty = 5046%(X100)
2266 05:55:45.514122
2267 05:55:45.514578 ==DQM 1 ==
2268 05:55:45.517804 Final DQM duty delay cell = 4
2269 05:55:45.521110 [4] MAX Duty = 5187%(X100), DQS PI = 54
2270 05:55:45.523926 [4] MIN Duty = 5000%(X100), DQS PI = 16
2271 05:55:45.524745 [4] AVG Duty = 5093%(X100)
2272 05:55:45.527562
2273 05:55:45.530868 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2274 05:55:45.531323
2275 05:55:45.534241 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2276 05:55:45.537359 [DutyScan_Calibration_Flow] ====Done====
2277 05:55:45.537815
2278 05:55:45.541336 [DutyScan_Calibration_Flow] k_type=2
2279 05:55:45.555752
2280 05:55:45.556351 ==DQ 0 ==
2281 05:55:45.559291 Final DQ duty delay cell = -4
2282 05:55:45.562414 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2283 05:55:45.565661 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2284 05:55:45.569444 [-4] AVG Duty = 4937%(X100)
2285 05:55:45.569991
2286 05:55:45.570357 ==DQ 1 ==
2287 05:55:45.572603 Final DQ duty delay cell = -4
2288 05:55:45.575910 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2289 05:55:45.579256 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2290 05:55:45.582778 [-4] AVG Duty = 4969%(X100)
2291 05:55:45.583331
2292 05:55:45.585774 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2293 05:55:45.586326
2294 05:55:45.588846 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2295 05:55:45.592932 [DutyScan_Calibration_Flow] ====Done====
2296 05:55:45.593387 ==
2297 05:55:45.595531 Dram Type= 6, Freq= 0, CH_1, rank 0
2298 05:55:45.599318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2299 05:55:45.599874 ==
2300 05:55:45.602517 [Duty_Offset_Calibration]
2301 05:55:45.602973 B0:0 B1:4 CA:-5
2302 05:55:45.603334
2303 05:55:45.605660 [DutyScan_Calibration_Flow] k_type=0
2304 05:55:45.616818
2305 05:55:45.617375 ==CLK 0==
2306 05:55:45.619889 Final CLK duty delay cell = 0
2307 05:55:45.623037 [0] MAX Duty = 5094%(X100), DQS PI = 24
2308 05:55:45.626504 [0] MIN Duty = 4875%(X100), DQS PI = 46
2309 05:55:45.626981 [0] AVG Duty = 4984%(X100)
2310 05:55:45.629656
2311 05:55:45.633076 CH1 CLK Duty spec in!! Max-Min= 219%
2312 05:55:45.636216 [DutyScan_Calibration_Flow] ====Done====
2313 05:55:45.636679
2314 05:55:45.639832 [DutyScan_Calibration_Flow] k_type=1
2315 05:55:45.655322
2316 05:55:45.655881 ==DQS 0 ==
2317 05:55:45.658065 Final DQS duty delay cell = 0
2318 05:55:45.661895 [0] MAX Duty = 5125%(X100), DQS PI = 16
2319 05:55:45.664816 [0] MIN Duty = 4875%(X100), DQS PI = 40
2320 05:55:45.668493 [0] AVG Duty = 5000%(X100)
2321 05:55:45.669098
2322 05:55:45.669462 ==DQS 1 ==
2323 05:55:45.671982 Final DQS duty delay cell = -4
2324 05:55:45.674848 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2325 05:55:45.678361 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2326 05:55:45.681625 [-4] AVG Duty = 4953%(X100)
2327 05:55:45.682095
2328 05:55:45.685219 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2329 05:55:45.685797
2330 05:55:45.688136 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2331 05:55:45.691488 [DutyScan_Calibration_Flow] ====Done====
2332 05:55:45.691959
2333 05:55:45.694695 [DutyScan_Calibration_Flow] k_type=3
2334 05:55:45.710169
2335 05:55:45.710730 ==DQM 0 ==
2336 05:55:45.713266 Final DQM duty delay cell = -4
2337 05:55:45.716857 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2338 05:55:45.719996 [-4] MIN Duty = 4875%(X100), DQS PI = 38
2339 05:55:45.723587 [-4] AVG Duty = 4968%(X100)
2340 05:55:45.724148
2341 05:55:45.724512 ==DQM 1 ==
2342 05:55:45.726487 Final DQM duty delay cell = -4
2343 05:55:45.730246 [-4] MAX Duty = 5093%(X100), DQS PI = 20
2344 05:55:45.733241 [-4] MIN Duty = 4907%(X100), DQS PI = 60
2345 05:55:45.736599 [-4] AVG Duty = 5000%(X100)
2346 05:55:45.737112
2347 05:55:45.740165 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2348 05:55:45.740761
2349 05:55:45.743186 CH1 DQM 1 Duty spec in!! Max-Min= 186%
2350 05:55:45.746497 [DutyScan_Calibration_Flow] ====Done====
2351 05:55:45.746952
2352 05:55:45.749738 [DutyScan_Calibration_Flow] k_type=2
2353 05:55:45.766997
2354 05:55:45.767542 ==DQ 0 ==
2355 05:55:45.770525 Final DQ duty delay cell = 0
2356 05:55:45.773874 [0] MAX Duty = 5093%(X100), DQS PI = 0
2357 05:55:45.777095 [0] MIN Duty = 4969%(X100), DQS PI = 42
2358 05:55:45.777594 [0] AVG Duty = 5031%(X100)
2359 05:55:45.777960
2360 05:55:45.780229 ==DQ 1 ==
2361 05:55:45.784156 Final DQ duty delay cell = 0
2362 05:55:45.787170 [0] MAX Duty = 5000%(X100), DQS PI = 8
2363 05:55:45.790240 [0] MIN Duty = 4875%(X100), DQS PI = 30
2364 05:55:45.790688 [0] AVG Duty = 4937%(X100)
2365 05:55:45.791108
2366 05:55:45.793612 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2367 05:55:45.794120
2368 05:55:45.800511 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2369 05:55:45.803629 [DutyScan_Calibration_Flow] ====Done====
2370 05:55:45.807029 nWR fixed to 30
2371 05:55:45.807536 [ModeRegInit_LP4] CH0 RK0
2372 05:55:45.810633 [ModeRegInit_LP4] CH0 RK1
2373 05:55:45.813361 [ModeRegInit_LP4] CH1 RK0
2374 05:55:45.817063 [ModeRegInit_LP4] CH1 RK1
2375 05:55:45.817542 match AC timing 6
2376 05:55:45.820467 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2377 05:55:45.826760 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2378 05:55:45.829947 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2379 05:55:45.833416 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2380 05:55:45.840316 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2381 05:55:45.841053 ==
2382 05:55:45.843586 Dram Type= 6, Freq= 0, CH_0, rank 0
2383 05:55:45.846863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2384 05:55:45.847319 ==
2385 05:55:45.853563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2386 05:55:45.860313 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2387 05:55:45.866588 [CA 0] Center 39 (9~70) winsize 62
2388 05:55:45.870617 [CA 1] Center 39 (8~70) winsize 63
2389 05:55:45.873302 [CA 2] Center 36 (5~67) winsize 63
2390 05:55:45.876824 [CA 3] Center 35 (5~66) winsize 62
2391 05:55:45.880289 [CA 4] Center 34 (3~65) winsize 63
2392 05:55:45.883235 [CA 5] Center 33 (3~64) winsize 62
2393 05:55:45.883692
2394 05:55:45.887003 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2395 05:55:45.887562
2396 05:55:45.890087 [CATrainingPosCal] consider 1 rank data
2397 05:55:45.893548 u2DelayCellTimex100 = 270/100 ps
2398 05:55:45.896944 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2399 05:55:45.900666 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2400 05:55:45.906611 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2401 05:55:45.910244 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2402 05:55:45.913352 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2403 05:55:45.916522 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2404 05:55:45.917016
2405 05:55:45.920345 CA PerBit enable=1, Macro0, CA PI delay=33
2406 05:55:45.920850
2407 05:55:45.923464 [CBTSetCACLKResult] CA Dly = 33
2408 05:55:45.924023 CS Dly: 7 (0~38)
2409 05:55:45.926579 ==
2410 05:55:45.927032 Dram Type= 6, Freq= 0, CH_0, rank 1
2411 05:55:45.934066 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2412 05:55:45.934623 ==
2413 05:55:45.936827 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2414 05:55:45.943600 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2415 05:55:45.952461 [CA 0] Center 39 (8~70) winsize 63
2416 05:55:45.956048 [CA 1] Center 39 (8~70) winsize 63
2417 05:55:45.958978 [CA 2] Center 36 (5~67) winsize 63
2418 05:55:45.962669 [CA 3] Center 35 (4~66) winsize 63
2419 05:55:45.965850 [CA 4] Center 33 (3~64) winsize 62
2420 05:55:45.968866 [CA 5] Center 34 (3~65) winsize 63
2421 05:55:45.969416
2422 05:55:45.972082 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2423 05:55:45.972625
2424 05:55:45.975503 [CATrainingPosCal] consider 2 rank data
2425 05:55:45.978900 u2DelayCellTimex100 = 270/100 ps
2426 05:55:45.982448 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2427 05:55:45.989034 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2428 05:55:45.992375 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2429 05:55:45.995252 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2430 05:55:45.998620 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2431 05:55:46.001964 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2432 05:55:46.002415
2433 05:55:46.005681 CA PerBit enable=1, Macro0, CA PI delay=33
2434 05:55:46.006233
2435 05:55:46.008688 [CBTSetCACLKResult] CA Dly = 33
2436 05:55:46.011918 CS Dly: 7 (0~39)
2437 05:55:46.012364
2438 05:55:46.015185 ----->DramcWriteLeveling(PI) begin...
2439 05:55:46.015639 ==
2440 05:55:46.018592 Dram Type= 6, Freq= 0, CH_0, rank 0
2441 05:55:46.022019 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2442 05:55:46.022472 ==
2443 05:55:46.025522 Write leveling (Byte 0): 29 => 29
2444 05:55:46.028863 Write leveling (Byte 1): 26 => 26
2445 05:55:46.031684 DramcWriteLeveling(PI) end<-----
2446 05:55:46.032141
2447 05:55:46.032499 ==
2448 05:55:46.035247 Dram Type= 6, Freq= 0, CH_0, rank 0
2449 05:55:46.038328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2450 05:55:46.038831 ==
2451 05:55:46.041772 [Gating] SW mode calibration
2452 05:55:46.048555 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2453 05:55:46.055048 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2454 05:55:46.058221 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2455 05:55:46.061746 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2456 05:55:46.068597 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2457 05:55:46.071717 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2458 05:55:46.075178 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2459 05:55:46.081577 0 11 20 | B1->B0 | 2e2e 2727 | 1 1 | (1 0) (1 0)
2460 05:55:46.085158 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2461 05:55:46.088543 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2462 05:55:46.094630 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2463 05:55:46.098403 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2464 05:55:46.101446 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2465 05:55:46.108505 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2466 05:55:46.111243 0 12 16 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
2467 05:55:46.114705 0 12 20 | B1->B0 | 3737 4444 | 0 0 | (1 1) (0 0)
2468 05:55:46.121459 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2469 05:55:46.124548 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2470 05:55:46.128077 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2471 05:55:46.131337 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2472 05:55:46.138103 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2473 05:55:46.141502 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2474 05:55:46.144940 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2475 05:55:46.151903 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2476 05:55:46.154553 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2477 05:55:46.157954 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 05:55:46.164350 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 05:55:46.168374 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 05:55:46.171532 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 05:55:46.177879 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 05:55:46.181590 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2483 05:55:46.184824 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2484 05:55:46.191354 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2485 05:55:46.194968 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2486 05:55:46.198482 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2487 05:55:46.204665 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2488 05:55:46.208040 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2489 05:55:46.211518 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2490 05:55:46.218481 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2491 05:55:46.221329 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2492 05:55:46.225234 Total UI for P1: 0, mck2ui 16
2493 05:55:46.228548 best dqsien dly found for B0: ( 0, 15, 18)
2494 05:55:46.231087 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2495 05:55:46.234406 Total UI for P1: 0, mck2ui 16
2496 05:55:46.237639 best dqsien dly found for B1: ( 0, 15, 20)
2497 05:55:46.241298 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2498 05:55:46.244274 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2499 05:55:46.244788
2500 05:55:46.247857 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2501 05:55:46.254904 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2502 05:55:46.255469 [Gating] SW calibration Done
2503 05:55:46.255839 ==
2504 05:55:46.257977 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 05:55:46.264776 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2506 05:55:46.265334 ==
2507 05:55:46.265701 RX Vref Scan: 0
2508 05:55:46.266037
2509 05:55:46.268022 RX Vref 0 -> 0, step: 1
2510 05:55:46.268571
2511 05:55:46.271024 RX Delay -40 -> 252, step: 8
2512 05:55:46.274816 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2513 05:55:46.277944 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2514 05:55:46.281425 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2515 05:55:46.288384 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2516 05:55:46.291347 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2517 05:55:46.294780 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2518 05:55:46.298138 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2519 05:55:46.301433 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2520 05:55:46.307921 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2521 05:55:46.310859 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2522 05:55:46.314379 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2523 05:55:46.317771 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2524 05:55:46.321218 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2525 05:55:46.327906 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2526 05:55:46.331156 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2527 05:55:46.334076 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2528 05:55:46.334653 ==
2529 05:55:46.337585 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 05:55:46.341256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2531 05:55:46.341716 ==
2532 05:55:46.344193 DQS Delay:
2533 05:55:46.344649 DQS0 = 0, DQS1 = 0
2534 05:55:46.347558 DQM Delay:
2535 05:55:46.348068 DQM0 = 115, DQM1 = 105
2536 05:55:46.348433 DQ Delay:
2537 05:55:46.350861 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2538 05:55:46.354344 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2539 05:55:46.361213 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2540 05:55:46.364362 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2541 05:55:46.364862
2542 05:55:46.365225
2543 05:55:46.365559 ==
2544 05:55:46.367695 Dram Type= 6, Freq= 0, CH_0, rank 0
2545 05:55:46.371104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2546 05:55:46.371565 ==
2547 05:55:46.371927
2548 05:55:46.372261
2549 05:55:46.374291 TX Vref Scan disable
2550 05:55:46.374747 == TX Byte 0 ==
2551 05:55:46.380567 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2552 05:55:46.384223 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2553 05:55:46.384836 == TX Byte 1 ==
2554 05:55:46.391023 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2555 05:55:46.394413 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2556 05:55:46.394874 ==
2557 05:55:46.397497 Dram Type= 6, Freq= 0, CH_0, rank 0
2558 05:55:46.400525 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2559 05:55:46.401035 ==
2560 05:55:46.413697 TX Vref=22, minBit 10, minWin=25, winSum=414
2561 05:55:46.417258 TX Vref=24, minBit 8, minWin=25, winSum=420
2562 05:55:46.420370 TX Vref=26, minBit 10, minWin=25, winSum=428
2563 05:55:46.423617 TX Vref=28, minBit 11, minWin=25, winSum=431
2564 05:55:46.426956 TX Vref=30, minBit 10, minWin=26, winSum=435
2565 05:55:46.433563 TX Vref=32, minBit 10, minWin=26, winSum=435
2566 05:55:46.436872 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 30
2567 05:55:46.437335
2568 05:55:46.440422 Final TX Range 1 Vref 30
2569 05:55:46.440910
2570 05:55:46.441275 ==
2571 05:55:46.443756 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 05:55:46.447579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2573 05:55:46.450423 ==
2574 05:55:46.450973
2575 05:55:46.451334
2576 05:55:46.451668 TX Vref Scan disable
2577 05:55:46.454164 == TX Byte 0 ==
2578 05:55:46.457330 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2579 05:55:46.461041 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2580 05:55:46.464156 == TX Byte 1 ==
2581 05:55:46.467355 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2582 05:55:46.471113 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2583 05:55:46.474512
2584 05:55:46.475062 [DATLAT]
2585 05:55:46.475430 Freq=1200, CH0 RK0
2586 05:55:46.475775
2587 05:55:46.477534 DATLAT Default: 0xd
2588 05:55:46.477993 0, 0xFFFF, sum = 0
2589 05:55:46.481194 1, 0xFFFF, sum = 0
2590 05:55:46.481756 2, 0xFFFF, sum = 0
2591 05:55:46.484577 3, 0xFFFF, sum = 0
2592 05:55:46.485188 4, 0xFFFF, sum = 0
2593 05:55:46.487551 5, 0xFFFF, sum = 0
2594 05:55:46.491167 6, 0xFFFF, sum = 0
2595 05:55:46.491731 7, 0xFFFF, sum = 0
2596 05:55:46.493852 8, 0xFFFF, sum = 0
2597 05:55:46.494321 9, 0xFFFF, sum = 0
2598 05:55:46.497765 10, 0xFFFF, sum = 0
2599 05:55:46.498235 11, 0x0, sum = 1
2600 05:55:46.500842 12, 0x0, sum = 2
2601 05:55:46.501309 13, 0x0, sum = 3
2602 05:55:46.501682 14, 0x0, sum = 4
2603 05:55:46.503954 best_step = 12
2604 05:55:46.504412
2605 05:55:46.504840 ==
2606 05:55:46.507496 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 05:55:46.510512 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2608 05:55:46.511061 ==
2609 05:55:46.513995 RX Vref Scan: 1
2610 05:55:46.514604
2611 05:55:46.517233 Set Vref Range= 32 -> 127
2612 05:55:46.517649
2613 05:55:46.517979 RX Vref 32 -> 127, step: 1
2614 05:55:46.518290
2615 05:55:46.520892 RX Delay -21 -> 252, step: 4
2616 05:55:46.521314
2617 05:55:46.524028 Set Vref, RX VrefLevel [Byte0]: 32
2618 05:55:46.527203 [Byte1]: 32
2619 05:55:46.531191
2620 05:55:46.531721 Set Vref, RX VrefLevel [Byte0]: 33
2621 05:55:46.534206 [Byte1]: 33
2622 05:55:46.538825
2623 05:55:46.539353 Set Vref, RX VrefLevel [Byte0]: 34
2624 05:55:46.542634 [Byte1]: 34
2625 05:55:46.547078
2626 05:55:46.547590 Set Vref, RX VrefLevel [Byte0]: 35
2627 05:55:46.550361 [Byte1]: 35
2628 05:55:46.554687
2629 05:55:46.555102 Set Vref, RX VrefLevel [Byte0]: 36
2630 05:55:46.558250 [Byte1]: 36
2631 05:55:46.562734
2632 05:55:46.563261 Set Vref, RX VrefLevel [Byte0]: 37
2633 05:55:46.565922 [Byte1]: 37
2634 05:55:46.570627
2635 05:55:46.571157 Set Vref, RX VrefLevel [Byte0]: 38
2636 05:55:46.573549 [Byte1]: 38
2637 05:55:46.578495
2638 05:55:46.579025 Set Vref, RX VrefLevel [Byte0]: 39
2639 05:55:46.581912 [Byte1]: 39
2640 05:55:46.586297
2641 05:55:46.586889 Set Vref, RX VrefLevel [Byte0]: 40
2642 05:55:46.589603 [Byte1]: 40
2643 05:55:46.594043
2644 05:55:46.594476 Set Vref, RX VrefLevel [Byte0]: 41
2645 05:55:46.597519 [Byte1]: 41
2646 05:55:46.602380
2647 05:55:46.602906 Set Vref, RX VrefLevel [Byte0]: 42
2648 05:55:46.605399 [Byte1]: 42
2649 05:55:46.610300
2650 05:55:46.610863 Set Vref, RX VrefLevel [Byte0]: 43
2651 05:55:46.613270 [Byte1]: 43
2652 05:55:46.617676
2653 05:55:46.618104 Set Vref, RX VrefLevel [Byte0]: 44
2654 05:55:46.620971 [Byte1]: 44
2655 05:55:46.626033
2656 05:55:46.626559 Set Vref, RX VrefLevel [Byte0]: 45
2657 05:55:46.629185 [Byte1]: 45
2658 05:55:46.633575
2659 05:55:46.634018 Set Vref, RX VrefLevel [Byte0]: 46
2660 05:55:46.636929 [Byte1]: 46
2661 05:55:46.641518
2662 05:55:46.641950 Set Vref, RX VrefLevel [Byte0]: 47
2663 05:55:46.644918 [Byte1]: 47
2664 05:55:46.649717
2665 05:55:46.650247 Set Vref, RX VrefLevel [Byte0]: 48
2666 05:55:46.653380 [Byte1]: 48
2667 05:55:46.657857
2668 05:55:46.658409 Set Vref, RX VrefLevel [Byte0]: 49
2669 05:55:46.660667 [Byte1]: 49
2670 05:55:46.665569
2671 05:55:46.666091 Set Vref, RX VrefLevel [Byte0]: 50
2672 05:55:46.668628 [Byte1]: 50
2673 05:55:46.673479
2674 05:55:46.674003 Set Vref, RX VrefLevel [Byte0]: 51
2675 05:55:46.678656 [Byte1]: 51
2676 05:55:46.681238
2677 05:55:46.681764 Set Vref, RX VrefLevel [Byte0]: 52
2678 05:55:46.684943 [Byte1]: 52
2679 05:55:46.689365
2680 05:55:46.689795 Set Vref, RX VrefLevel [Byte0]: 53
2681 05:55:46.695323 [Byte1]: 53
2682 05:55:46.695757
2683 05:55:46.699521 Set Vref, RX VrefLevel [Byte0]: 54
2684 05:55:46.702765 [Byte1]: 54
2685 05:55:46.703292
2686 05:55:46.705982 Set Vref, RX VrefLevel [Byte0]: 55
2687 05:55:46.709358 [Byte1]: 55
2688 05:55:46.712883
2689 05:55:46.713315 Set Vref, RX VrefLevel [Byte0]: 56
2690 05:55:46.716303 [Byte1]: 56
2691 05:55:46.720906
2692 05:55:46.721436 Set Vref, RX VrefLevel [Byte0]: 57
2693 05:55:46.724318 [Byte1]: 57
2694 05:55:46.728646
2695 05:55:46.729122 Set Vref, RX VrefLevel [Byte0]: 58
2696 05:55:46.731955 [Byte1]: 58
2697 05:55:46.736878
2698 05:55:46.737396 Set Vref, RX VrefLevel [Byte0]: 59
2699 05:55:46.740222 [Byte1]: 59
2700 05:55:46.744874
2701 05:55:46.745394 Set Vref, RX VrefLevel [Byte0]: 60
2702 05:55:46.747972 [Byte1]: 60
2703 05:55:46.752802
2704 05:55:46.753324 Set Vref, RX VrefLevel [Byte0]: 61
2705 05:55:46.755911 [Byte1]: 61
2706 05:55:46.760942
2707 05:55:46.761475 Set Vref, RX VrefLevel [Byte0]: 62
2708 05:55:46.764004 [Byte1]: 62
2709 05:55:46.768504
2710 05:55:46.769086 Set Vref, RX VrefLevel [Byte0]: 63
2711 05:55:46.771641 [Byte1]: 63
2712 05:55:46.776855
2713 05:55:46.777418 Set Vref, RX VrefLevel [Byte0]: 64
2714 05:55:46.779581 [Byte1]: 64
2715 05:55:46.784370
2716 05:55:46.784973 Set Vref, RX VrefLevel [Byte0]: 65
2717 05:55:46.787537 [Byte1]: 65
2718 05:55:46.792419
2719 05:55:46.792960 Final RX Vref Byte 0 = 52 to rank0
2720 05:55:46.795449 Final RX Vref Byte 1 = 48 to rank0
2721 05:55:46.798880 Final RX Vref Byte 0 = 52 to rank1
2722 05:55:46.802112 Final RX Vref Byte 1 = 48 to rank1==
2723 05:55:46.805642 Dram Type= 6, Freq= 0, CH_0, rank 0
2724 05:55:46.811907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2725 05:55:46.812428 ==
2726 05:55:46.813048 DQS Delay:
2727 05:55:46.813465 DQS0 = 0, DQS1 = 0
2728 05:55:46.815163 DQM Delay:
2729 05:55:46.815522 DQM0 = 114, DQM1 = 105
2730 05:55:46.818781 DQ Delay:
2731 05:55:46.822028 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2732 05:55:46.825340 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2733 05:55:46.828919 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2734 05:55:46.832128 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2735 05:55:46.832548
2736 05:55:46.832925
2737 05:55:46.838779 [DQSOSCAuto] RK0, (LSB)MR18= 0x101, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
2738 05:55:46.842190 CH0 RK0: MR19=404, MR18=101
2739 05:55:46.848652 CH0_RK0: MR19=0x404, MR18=0x101, DQSOSC=409, MR23=63, INC=39, DEC=26
2740 05:55:46.849180
2741 05:55:46.852097 ----->DramcWriteLeveling(PI) begin...
2742 05:55:46.852654 ==
2743 05:55:46.855485 Dram Type= 6, Freq= 0, CH_0, rank 1
2744 05:55:46.858842 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2745 05:55:46.862248 ==
2746 05:55:46.862814 Write leveling (Byte 0): 27 => 27
2747 05:55:46.865244 Write leveling (Byte 1): 25 => 25
2748 05:55:46.868843 DramcWriteLeveling(PI) end<-----
2749 05:55:46.869403
2750 05:55:46.869768 ==
2751 05:55:46.871540 Dram Type= 6, Freq= 0, CH_0, rank 1
2752 05:55:46.878569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2753 05:55:46.879117 ==
2754 05:55:46.879486 [Gating] SW mode calibration
2755 05:55:46.888149 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2756 05:55:46.891751 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2757 05:55:46.895074 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2758 05:55:46.901926 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2759 05:55:46.905174 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2760 05:55:46.908444 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2761 05:55:46.914861 0 11 16 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
2762 05:55:46.918742 0 11 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
2763 05:55:46.922047 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2764 05:55:46.928522 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2765 05:55:46.931641 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2766 05:55:46.934998 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2767 05:55:46.941754 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2768 05:55:46.944847 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2769 05:55:46.948561 0 12 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2770 05:55:46.954919 0 12 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2771 05:55:46.958935 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2772 05:55:46.961833 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2773 05:55:46.968555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2774 05:55:46.971548 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2775 05:55:46.975249 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2776 05:55:46.981602 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2777 05:55:46.984819 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2778 05:55:46.988334 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2779 05:55:46.995038 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 05:55:46.998467 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 05:55:47.001472 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 05:55:47.008518 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 05:55:47.011328 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 05:55:47.014683 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 05:55:47.017992 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 05:55:47.024377 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2787 05:55:47.027652 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2788 05:55:47.031092 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2789 05:55:47.037752 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2790 05:55:47.041196 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2791 05:55:47.044661 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2792 05:55:47.051567 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2793 05:55:47.054741 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2794 05:55:47.058108 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2795 05:55:47.061031 Total UI for P1: 0, mck2ui 16
2796 05:55:47.064554 best dqsien dly found for B0: ( 0, 15, 16)
2797 05:55:47.071860 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2798 05:55:47.072462 Total UI for P1: 0, mck2ui 16
2799 05:55:47.078134 best dqsien dly found for B1: ( 0, 15, 18)
2800 05:55:47.081452 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2801 05:55:47.084555 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2802 05:55:47.085208
2803 05:55:47.087916 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2804 05:55:47.091381 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2805 05:55:47.094714 [Gating] SW calibration Done
2806 05:55:47.095170 ==
2807 05:55:47.097929 Dram Type= 6, Freq= 0, CH_0, rank 1
2808 05:55:47.101610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2809 05:55:47.102169 ==
2810 05:55:47.104818 RX Vref Scan: 0
2811 05:55:47.105368
2812 05:55:47.105727 RX Vref 0 -> 0, step: 1
2813 05:55:47.106059
2814 05:55:47.108178 RX Delay -40 -> 252, step: 8
2815 05:55:47.114301 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2816 05:55:47.117478 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2817 05:55:47.120823 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2818 05:55:47.124484 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2819 05:55:47.127737 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2820 05:55:47.131381 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2821 05:55:47.137485 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2822 05:55:47.140818 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2823 05:55:47.144613 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2824 05:55:47.147871 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2825 05:55:47.150829 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2826 05:55:47.157544 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2827 05:55:47.160756 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2828 05:55:47.164295 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2829 05:55:47.167964 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2830 05:55:47.171037 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2831 05:55:47.174499 ==
2832 05:55:47.178023 Dram Type= 6, Freq= 0, CH_0, rank 1
2833 05:55:47.181275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2834 05:55:47.181833 ==
2835 05:55:47.182198 DQS Delay:
2836 05:55:47.184364 DQS0 = 0, DQS1 = 0
2837 05:55:47.184864 DQM Delay:
2838 05:55:47.187954 DQM0 = 114, DQM1 = 107
2839 05:55:47.188505 DQ Delay:
2840 05:55:47.190879 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2841 05:55:47.194520 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2842 05:55:47.197680 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2843 05:55:47.201344 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2844 05:55:47.201900
2845 05:55:47.202260
2846 05:55:47.202591 ==
2847 05:55:47.204189 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 05:55:47.211571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2849 05:55:47.212127 ==
2850 05:55:47.212491
2851 05:55:47.212947
2852 05:55:47.213506 TX Vref Scan disable
2853 05:55:47.214283 == TX Byte 0 ==
2854 05:55:47.217417 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2855 05:55:47.221344 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2856 05:55:47.224044 == TX Byte 1 ==
2857 05:55:47.227513 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2858 05:55:47.230930 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2859 05:55:47.234435 ==
2860 05:55:47.237860 Dram Type= 6, Freq= 0, CH_0, rank 1
2861 05:55:47.240555 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2862 05:55:47.241116 ==
2863 05:55:47.252336 TX Vref=22, minBit 8, minWin=25, winSum=419
2864 05:55:47.255438 TX Vref=24, minBit 1, minWin=26, winSum=427
2865 05:55:47.258876 TX Vref=26, minBit 1, minWin=26, winSum=428
2866 05:55:47.262739 TX Vref=28, minBit 8, minWin=26, winSum=430
2867 05:55:47.265173 TX Vref=30, minBit 8, minWin=26, winSum=434
2868 05:55:47.268505 TX Vref=32, minBit 8, minWin=26, winSum=433
2869 05:55:47.275440 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
2870 05:55:47.275995
2871 05:55:47.278517 Final TX Range 1 Vref 30
2872 05:55:47.279086
2873 05:55:47.279455 ==
2874 05:55:47.281719 Dram Type= 6, Freq= 0, CH_0, rank 1
2875 05:55:47.285205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2876 05:55:47.285626 ==
2877 05:55:47.288479
2878 05:55:47.288935
2879 05:55:47.289265 TX Vref Scan disable
2880 05:55:47.292184 == TX Byte 0 ==
2881 05:55:47.295153 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2882 05:55:47.298816 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2883 05:55:47.302123 == TX Byte 1 ==
2884 05:55:47.305637 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2885 05:55:47.308449 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2886 05:55:47.308895
2887 05:55:47.311967 [DATLAT]
2888 05:55:47.312378 Freq=1200, CH0 RK1
2889 05:55:47.312742
2890 05:55:47.315189 DATLAT Default: 0xc
2891 05:55:47.315787 0, 0xFFFF, sum = 0
2892 05:55:47.318368 1, 0xFFFF, sum = 0
2893 05:55:47.318786 2, 0xFFFF, sum = 0
2894 05:55:47.321912 3, 0xFFFF, sum = 0
2895 05:55:47.322330 4, 0xFFFF, sum = 0
2896 05:55:47.325204 5, 0xFFFF, sum = 0
2897 05:55:47.325624 6, 0xFFFF, sum = 0
2898 05:55:47.328662 7, 0xFFFF, sum = 0
2899 05:55:47.329223 8, 0xFFFF, sum = 0
2900 05:55:47.332353 9, 0xFFFF, sum = 0
2901 05:55:47.335841 10, 0xFFFF, sum = 0
2902 05:55:47.336357 11, 0x0, sum = 1
2903 05:55:47.336695 12, 0x0, sum = 2
2904 05:55:47.338714 13, 0x0, sum = 3
2905 05:55:47.339135 14, 0x0, sum = 4
2906 05:55:47.342172 best_step = 12
2907 05:55:47.342580
2908 05:55:47.342906 ==
2909 05:55:47.345518 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 05:55:47.349169 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2911 05:55:47.349697 ==
2912 05:55:47.352130 RX Vref Scan: 0
2913 05:55:47.352638
2914 05:55:47.353039 RX Vref 0 -> 0, step: 1
2915 05:55:47.355076
2916 05:55:47.355488 RX Delay -21 -> 252, step: 4
2917 05:55:47.362622 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2918 05:55:47.365384 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2919 05:55:47.369310 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2920 05:55:47.372402 iDelay=199, Bit 3, Center 110 (39 ~ 182) 144
2921 05:55:47.375832 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2922 05:55:47.382486 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2923 05:55:47.385877 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2924 05:55:47.388889 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2925 05:55:47.392228 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2926 05:55:47.395690 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2927 05:55:47.401943 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2928 05:55:47.405617 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2929 05:55:47.408829 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2930 05:55:47.412366 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2931 05:55:47.415532 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2932 05:55:47.422498 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2933 05:55:47.423019 ==
2934 05:55:47.425708 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 05:55:47.429177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2936 05:55:47.429694 ==
2937 05:55:47.430111 DQS Delay:
2938 05:55:47.432038 DQS0 = 0, DQS1 = 0
2939 05:55:47.432449 DQM Delay:
2940 05:55:47.436050 DQM0 = 115, DQM1 = 105
2941 05:55:47.436560 DQ Delay:
2942 05:55:47.438861 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =110
2943 05:55:47.442156 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =124
2944 05:55:47.445367 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2945 05:55:47.448794 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2946 05:55:47.449318
2947 05:55:47.449655
2948 05:55:47.458914 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2949 05:55:47.461729 CH0 RK1: MR19=404, MR18=E0E
2950 05:55:47.465453 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2951 05:55:47.468768 [RxdqsGatingPostProcess] freq 1200
2952 05:55:47.475508 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2953 05:55:47.478609 Pre-setting of DQS Precalculation
2954 05:55:47.481897 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2955 05:55:47.485217 ==
2956 05:55:47.485630 Dram Type= 6, Freq= 0, CH_1, rank 0
2957 05:55:47.492250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2958 05:55:47.492826 ==
2959 05:55:47.495435 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2960 05:55:47.501797 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2961 05:55:47.510741 [CA 0] Center 37 (7~68) winsize 62
2962 05:55:47.514015 [CA 1] Center 37 (7~68) winsize 62
2963 05:55:47.516975 [CA 2] Center 34 (4~65) winsize 62
2964 05:55:47.520159 [CA 3] Center 33 (3~64) winsize 62
2965 05:55:47.523559 [CA 4] Center 32 (1~63) winsize 63
2966 05:55:47.527227 [CA 5] Center 32 (2~63) winsize 62
2967 05:55:47.527685
2968 05:55:47.530744 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2969 05:55:47.531215
2970 05:55:47.533817 [CATrainingPosCal] consider 1 rank data
2971 05:55:47.537616 u2DelayCellTimex100 = 270/100 ps
2972 05:55:47.540915 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2973 05:55:47.543975 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2974 05:55:47.550506 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2975 05:55:47.553657 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2976 05:55:47.556992 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2977 05:55:47.560867 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2978 05:55:47.561420
2979 05:55:47.564117 CA PerBit enable=1, Macro0, CA PI delay=32
2980 05:55:47.564675
2981 05:55:47.567305 [CBTSetCACLKResult] CA Dly = 32
2982 05:55:47.567762 CS Dly: 5 (0~36)
2983 05:55:47.570654 ==
2984 05:55:47.571109 Dram Type= 6, Freq= 0, CH_1, rank 1
2985 05:55:47.576991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2986 05:55:47.577452 ==
2987 05:55:47.580391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2988 05:55:47.587150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2989 05:55:47.596133 [CA 0] Center 37 (7~68) winsize 62
2990 05:55:47.599420 [CA 1] Center 37 (7~68) winsize 62
2991 05:55:47.602733 [CA 2] Center 33 (3~64) winsize 62
2992 05:55:47.605916 [CA 3] Center 33 (3~64) winsize 62
2993 05:55:47.609344 [CA 4] Center 32 (2~63) winsize 62
2994 05:55:47.612888 [CA 5] Center 32 (2~63) winsize 62
2995 05:55:47.613344
2996 05:55:47.615879 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2997 05:55:47.616359
2998 05:55:47.619244 [CATrainingPosCal] consider 2 rank data
2999 05:55:47.622439 u2DelayCellTimex100 = 270/100 ps
3000 05:55:47.625988 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
3001 05:55:47.629137 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
3002 05:55:47.635966 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
3003 05:55:47.638958 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
3004 05:55:47.642626 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3005 05:55:47.645732 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3006 05:55:47.646144
3007 05:55:47.648995 CA PerBit enable=1, Macro0, CA PI delay=32
3008 05:55:47.649406
3009 05:55:47.652813 [CBTSetCACLKResult] CA Dly = 32
3010 05:55:47.653429 CS Dly: 6 (0~38)
3011 05:55:47.653896
3012 05:55:47.656130 ----->DramcWriteLeveling(PI) begin...
3013 05:55:47.659271 ==
3014 05:55:47.662722 Dram Type= 6, Freq= 0, CH_1, rank 0
3015 05:55:47.666125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3016 05:55:47.666537 ==
3017 05:55:47.669145 Write leveling (Byte 0): 20 => 20
3018 05:55:47.672492 Write leveling (Byte 1): 23 => 23
3019 05:55:47.675806 DramcWriteLeveling(PI) end<-----
3020 05:55:47.676221
3021 05:55:47.676545 ==
3022 05:55:47.679057 Dram Type= 6, Freq= 0, CH_1, rank 0
3023 05:55:47.682155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3024 05:55:47.682816 ==
3025 05:55:47.685495 [Gating] SW mode calibration
3026 05:55:47.692487 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3027 05:55:47.698518 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3028 05:55:47.702522 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3029 05:55:47.705109 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3030 05:55:47.712002 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3031 05:55:47.715718 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3032 05:55:47.718635 0 11 16 | B1->B0 | 3030 2424 | 0 0 | (0 1) (1 0)
3033 05:55:47.725373 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3034 05:55:47.728627 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3035 05:55:47.732380 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3036 05:55:47.739208 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3037 05:55:47.741843 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3038 05:55:47.745393 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3039 05:55:47.748680 0 12 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3040 05:55:47.755610 0 12 16 | B1->B0 | 3535 4343 | 0 0 | (0 0) (0 0)
3041 05:55:47.758898 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3042 05:55:47.762146 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3043 05:55:47.768484 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3044 05:55:47.772501 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3045 05:55:47.775814 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3046 05:55:47.781988 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3047 05:55:47.785667 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3048 05:55:47.788854 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3049 05:55:47.795487 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3050 05:55:47.798508 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 05:55:47.802169 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 05:55:47.808784 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 05:55:47.812191 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 05:55:47.815271 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 05:55:47.822069 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 05:55:47.825411 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 05:55:47.829027 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3058 05:55:47.835484 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3059 05:55:47.838644 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3060 05:55:47.842367 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3061 05:55:47.845672 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3062 05:55:47.851869 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3063 05:55:47.855078 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3064 05:55:47.858649 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3065 05:55:47.865057 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3066 05:55:47.868442 Total UI for P1: 0, mck2ui 16
3067 05:55:47.871819 best dqsien dly found for B0: ( 0, 15, 14)
3068 05:55:47.874992 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3069 05:55:47.878351 Total UI for P1: 0, mck2ui 16
3070 05:55:47.881826 best dqsien dly found for B1: ( 0, 15, 18)
3071 05:55:47.885282 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3072 05:55:47.888275 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3073 05:55:47.888919
3074 05:55:47.891459 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3075 05:55:47.895100 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3076 05:55:47.898270 [Gating] SW calibration Done
3077 05:55:47.898840 ==
3078 05:55:47.901444 Dram Type= 6, Freq= 0, CH_1, rank 0
3079 05:55:47.908859 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3080 05:55:47.909393 ==
3081 05:55:47.909730 RX Vref Scan: 0
3082 05:55:47.910037
3083 05:55:47.911549 RX Vref 0 -> 0, step: 1
3084 05:55:47.911960
3085 05:55:47.915617 RX Delay -40 -> 252, step: 8
3086 05:55:47.918055 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3087 05:55:47.921420 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3088 05:55:47.925155 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3089 05:55:47.931622 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3090 05:55:47.935216 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3091 05:55:47.938210 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3092 05:55:47.941583 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3093 05:55:47.944892 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3094 05:55:47.948151 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3095 05:55:47.955161 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3096 05:55:47.958539 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3097 05:55:47.961271 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3098 05:55:47.964948 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3099 05:55:47.968396 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3100 05:55:47.974677 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3101 05:55:47.977926 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3102 05:55:47.978473 ==
3103 05:55:47.981280 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 05:55:47.984461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3105 05:55:47.984950 ==
3106 05:55:47.988744 DQS Delay:
3107 05:55:47.989319 DQS0 = 0, DQS1 = 0
3108 05:55:47.989693 DQM Delay:
3109 05:55:47.992022 DQM0 = 116, DQM1 = 107
3110 05:55:47.992587 DQ Delay:
3111 05:55:47.994746 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3112 05:55:47.998597 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3113 05:55:48.001464 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3114 05:55:48.008243 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3115 05:55:48.008931
3116 05:55:48.009494
3117 05:55:48.009859 ==
3118 05:55:48.011315 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 05:55:48.014692 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3120 05:55:48.015273 ==
3121 05:55:48.015647
3122 05:55:48.015986
3123 05:55:48.017920 TX Vref Scan disable
3124 05:55:48.018380 == TX Byte 0 ==
3125 05:55:48.024876 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3126 05:55:48.027749 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3127 05:55:48.028214 == TX Byte 1 ==
3128 05:55:48.034675 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3129 05:55:48.037810 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3130 05:55:48.038373 ==
3131 05:55:48.040990 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 05:55:48.044962 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3133 05:55:48.045525 ==
3134 05:55:48.057633 TX Vref=22, minBit 1, minWin=25, winSum=408
3135 05:55:48.060585 TX Vref=24, minBit 15, minWin=25, winSum=420
3136 05:55:48.064031 TX Vref=26, minBit 3, minWin=25, winSum=420
3137 05:55:48.067728 TX Vref=28, minBit 1, minWin=26, winSum=427
3138 05:55:48.070926 TX Vref=30, minBit 9, minWin=25, winSum=426
3139 05:55:48.077425 TX Vref=32, minBit 9, minWin=26, winSum=426
3140 05:55:48.080682 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
3141 05:55:48.081302
3142 05:55:48.083935 Final TX Range 1 Vref 28
3143 05:55:48.084501
3144 05:55:48.084918 ==
3145 05:55:48.087416 Dram Type= 6, Freq= 0, CH_1, rank 0
3146 05:55:48.090907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3147 05:55:48.091482 ==
3148 05:55:48.091853
3149 05:55:48.093872
3150 05:55:48.094331 TX Vref Scan disable
3151 05:55:48.097364 == TX Byte 0 ==
3152 05:55:48.101132 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3153 05:55:48.104573 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3154 05:55:48.108099 == TX Byte 1 ==
3155 05:55:48.111115 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3156 05:55:48.114455 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3157 05:55:48.115026
3158 05:55:48.117688 [DATLAT]
3159 05:55:48.118412 Freq=1200, CH1 RK0
3160 05:55:48.118803
3161 05:55:48.120975 DATLAT Default: 0xd
3162 05:55:48.121438 0, 0xFFFF, sum = 0
3163 05:55:48.123883 1, 0xFFFF, sum = 0
3164 05:55:48.124354 2, 0xFFFF, sum = 0
3165 05:55:48.127362 3, 0xFFFF, sum = 0
3166 05:55:48.127832 4, 0xFFFF, sum = 0
3167 05:55:48.130691 5, 0xFFFF, sum = 0
3168 05:55:48.131157 6, 0xFFFF, sum = 0
3169 05:55:48.134379 7, 0xFFFF, sum = 0
3170 05:55:48.134847 8, 0xFFFF, sum = 0
3171 05:55:48.137268 9, 0xFFFF, sum = 0
3172 05:55:48.137911 10, 0xFFFF, sum = 0
3173 05:55:48.140673 11, 0x0, sum = 1
3174 05:55:48.141179 12, 0x0, sum = 2
3175 05:55:48.143842 13, 0x0, sum = 3
3176 05:55:48.144309 14, 0x0, sum = 4
3177 05:55:48.147835 best_step = 12
3178 05:55:48.148398
3179 05:55:48.148824 ==
3180 05:55:48.150752 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 05:55:48.154221 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3182 05:55:48.154790 ==
3183 05:55:48.157402 RX Vref Scan: 1
3184 05:55:48.157863
3185 05:55:48.158234 Set Vref Range= 32 -> 127
3186 05:55:48.160305
3187 05:55:48.160801 RX Vref 32 -> 127, step: 1
3188 05:55:48.161178
3189 05:55:48.164000 RX Delay -29 -> 252, step: 4
3190 05:55:48.164568
3191 05:55:48.167617 Set Vref, RX VrefLevel [Byte0]: 32
3192 05:55:48.170845 [Byte1]: 32
3193 05:55:48.174090
3194 05:55:48.174709 Set Vref, RX VrefLevel [Byte0]: 33
3195 05:55:48.177419 [Byte1]: 33
3196 05:55:48.181817
3197 05:55:48.182379 Set Vref, RX VrefLevel [Byte0]: 34
3198 05:55:48.185163 [Byte1]: 34
3199 05:55:48.190209
3200 05:55:48.190774 Set Vref, RX VrefLevel [Byte0]: 35
3201 05:55:48.193157 [Byte1]: 35
3202 05:55:48.197777
3203 05:55:48.198365 Set Vref, RX VrefLevel [Byte0]: 36
3204 05:55:48.200832 [Byte1]: 36
3205 05:55:48.206191
3206 05:55:48.206834 Set Vref, RX VrefLevel [Byte0]: 37
3207 05:55:48.209147 [Byte1]: 37
3208 05:55:48.213538
3209 05:55:48.214099 Set Vref, RX VrefLevel [Byte0]: 38
3210 05:55:48.217106 [Byte1]: 38
3211 05:55:48.221545
3212 05:55:48.222006 Set Vref, RX VrefLevel [Byte0]: 39
3213 05:55:48.224834 [Byte1]: 39
3214 05:55:48.230101
3215 05:55:48.230675 Set Vref, RX VrefLevel [Byte0]: 40
3216 05:55:48.233047 [Byte1]: 40
3217 05:55:48.237490
3218 05:55:48.238090 Set Vref, RX VrefLevel [Byte0]: 41
3219 05:55:48.240618 [Byte1]: 41
3220 05:55:48.245821
3221 05:55:48.246280 Set Vref, RX VrefLevel [Byte0]: 42
3222 05:55:48.248862 [Byte1]: 42
3223 05:55:48.253551
3224 05:55:48.254010 Set Vref, RX VrefLevel [Byte0]: 43
3225 05:55:48.256887 [Byte1]: 43
3226 05:55:48.261133
3227 05:55:48.261593 Set Vref, RX VrefLevel [Byte0]: 44
3228 05:55:48.264864 [Byte1]: 44
3229 05:55:48.269333
3230 05:55:48.269894 Set Vref, RX VrefLevel [Byte0]: 45
3231 05:55:48.272508 [Byte1]: 45
3232 05:55:48.277651
3233 05:55:48.278286 Set Vref, RX VrefLevel [Byte0]: 46
3234 05:55:48.280763 [Byte1]: 46
3235 05:55:48.285555
3236 05:55:48.286120 Set Vref, RX VrefLevel [Byte0]: 47
3237 05:55:48.288688 [Byte1]: 47
3238 05:55:48.293092
3239 05:55:48.293555 Set Vref, RX VrefLevel [Byte0]: 48
3240 05:55:48.296262 [Byte1]: 48
3241 05:55:48.300974
3242 05:55:48.301436 Set Vref, RX VrefLevel [Byte0]: 49
3243 05:55:48.304386 [Byte1]: 49
3244 05:55:48.308896
3245 05:55:48.312169 Set Vref, RX VrefLevel [Byte0]: 50
3246 05:55:48.315758 [Byte1]: 50
3247 05:55:48.316328
3248 05:55:48.318809 Set Vref, RX VrefLevel [Byte0]: 51
3249 05:55:48.322675 [Byte1]: 51
3250 05:55:48.323272
3251 05:55:48.325691 Set Vref, RX VrefLevel [Byte0]: 52
3252 05:55:48.328895 [Byte1]: 52
3253 05:55:48.333004
3254 05:55:48.333465 Set Vref, RX VrefLevel [Byte0]: 53
3255 05:55:48.336352 [Byte1]: 53
3256 05:55:48.340762
3257 05:55:48.341229 Set Vref, RX VrefLevel [Byte0]: 54
3258 05:55:48.344509 [Byte1]: 54
3259 05:55:48.348779
3260 05:55:48.349359 Set Vref, RX VrefLevel [Byte0]: 55
3261 05:55:48.352346 [Byte1]: 55
3262 05:55:48.357125
3263 05:55:48.357688 Set Vref, RX VrefLevel [Byte0]: 56
3264 05:55:48.360198 [Byte1]: 56
3265 05:55:48.364766
3266 05:55:48.365232 Set Vref, RX VrefLevel [Byte0]: 57
3267 05:55:48.367823 [Byte1]: 57
3268 05:55:48.372825
3269 05:55:48.373287 Set Vref, RX VrefLevel [Byte0]: 58
3270 05:55:48.376016 [Byte1]: 58
3271 05:55:48.381004
3272 05:55:48.381467 Set Vref, RX VrefLevel [Byte0]: 59
3273 05:55:48.383841 [Byte1]: 59
3274 05:55:48.389094
3275 05:55:48.389656 Set Vref, RX VrefLevel [Byte0]: 60
3276 05:55:48.391993 [Byte1]: 60
3277 05:55:48.396522
3278 05:55:48.397020 Set Vref, RX VrefLevel [Byte0]: 61
3279 05:55:48.399847 [Byte1]: 61
3280 05:55:48.405246
3281 05:55:48.405807 Set Vref, RX VrefLevel [Byte0]: 62
3282 05:55:48.407907 [Byte1]: 62
3283 05:55:48.412939
3284 05:55:48.413508 Set Vref, RX VrefLevel [Byte0]: 63
3285 05:55:48.416373 [Byte1]: 63
3286 05:55:48.420797
3287 05:55:48.421598 Set Vref, RX VrefLevel [Byte0]: 64
3288 05:55:48.423623 [Byte1]: 64
3289 05:55:48.428814
3290 05:55:48.429381 Set Vref, RX VrefLevel [Byte0]: 65
3291 05:55:48.431735 [Byte1]: 65
3292 05:55:48.436217
3293 05:55:48.436678 Set Vref, RX VrefLevel [Byte0]: 66
3294 05:55:48.439879 [Byte1]: 66
3295 05:55:48.444372
3296 05:55:48.444874 Final RX Vref Byte 0 = 55 to rank0
3297 05:55:48.447829 Final RX Vref Byte 1 = 49 to rank0
3298 05:55:48.451655 Final RX Vref Byte 0 = 55 to rank1
3299 05:55:48.454714 Final RX Vref Byte 1 = 49 to rank1==
3300 05:55:48.457699 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 05:55:48.464638 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3302 05:55:48.465267 ==
3303 05:55:48.465641 DQS Delay:
3304 05:55:48.465983 DQS0 = 0, DQS1 = 0
3305 05:55:48.468399 DQM Delay:
3306 05:55:48.469026 DQM0 = 115, DQM1 = 105
3307 05:55:48.471034 DQ Delay:
3308 05:55:48.474695 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3309 05:55:48.477466 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3310 05:55:48.481101 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3311 05:55:48.484254 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3312 05:55:48.484851
3313 05:55:48.485222
3314 05:55:48.491156 [DQSOSCAuto] RK0, (LSB)MR18= 0x1818, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3315 05:55:48.494020 CH1 RK0: MR19=404, MR18=1818
3316 05:55:48.501052 CH1_RK0: MR19=0x404, MR18=0x1818, DQSOSC=400, MR23=63, INC=40, DEC=27
3317 05:55:48.501569
3318 05:55:48.503851 ----->DramcWriteLeveling(PI) begin...
3319 05:55:48.504320 ==
3320 05:55:48.508041 Dram Type= 6, Freq= 0, CH_1, rank 1
3321 05:55:48.511268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3322 05:55:48.514519 ==
3323 05:55:48.515071 Write leveling (Byte 0): 22 => 22
3324 05:55:48.517216 Write leveling (Byte 1): 22 => 22
3325 05:55:48.520908 DramcWriteLeveling(PI) end<-----
3326 05:55:48.521711
3327 05:55:48.522158 ==
3328 05:55:48.524416 Dram Type= 6, Freq= 0, CH_1, rank 1
3329 05:55:48.530826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3330 05:55:48.531409 ==
3331 05:55:48.531780 [Gating] SW mode calibration
3332 05:55:48.540981 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3333 05:55:48.543961 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3334 05:55:48.547761 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3335 05:55:48.554455 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3336 05:55:48.557438 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3337 05:55:48.560685 0 11 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
3338 05:55:48.567804 0 11 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
3339 05:55:48.570866 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3340 05:55:48.574507 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3341 05:55:48.580640 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3342 05:55:48.584261 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3343 05:55:48.587426 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3344 05:55:48.594418 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3345 05:55:48.597699 0 12 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
3346 05:55:48.600421 0 12 16 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
3347 05:55:48.607430 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3348 05:55:48.610838 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3349 05:55:48.613975 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3350 05:55:48.621013 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3351 05:55:48.624095 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3352 05:55:48.627225 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3353 05:55:48.634030 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3354 05:55:48.637173 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3355 05:55:48.640645 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3356 05:55:48.647334 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 05:55:48.650704 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 05:55:48.653936 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 05:55:48.657278 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 05:55:48.663809 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 05:55:48.667214 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 05:55:48.670394 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3363 05:55:48.677593 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3364 05:55:48.680377 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3365 05:55:48.683629 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3366 05:55:48.690523 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3367 05:55:48.693775 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3368 05:55:48.696936 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3369 05:55:48.703875 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3370 05:55:48.707466 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3371 05:55:48.710826 Total UI for P1: 0, mck2ui 16
3372 05:55:48.714031 best dqsien dly found for B0: ( 0, 15, 10)
3373 05:55:48.717344 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3374 05:55:48.720757 Total UI for P1: 0, mck2ui 16
3375 05:55:48.724102 best dqsien dly found for B1: ( 0, 15, 16)
3376 05:55:48.727571 best DQS0 dly(MCK, UI, PI) = (0, 15, 10)
3377 05:55:48.730870 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3378 05:55:48.731402
3379 05:55:48.737340 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 10)
3380 05:55:48.740565 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3381 05:55:48.741188 [Gating] SW calibration Done
3382 05:55:48.743926 ==
3383 05:55:48.747468 Dram Type= 6, Freq= 0, CH_1, rank 1
3384 05:55:48.750259 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3385 05:55:48.750669 ==
3386 05:55:48.751044 RX Vref Scan: 0
3387 05:55:48.751353
3388 05:55:48.753785 RX Vref 0 -> 0, step: 1
3389 05:55:48.754227
3390 05:55:48.757344 RX Delay -40 -> 252, step: 8
3391 05:55:48.760824 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3392 05:55:48.763839 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3393 05:55:48.767773 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3394 05:55:48.773744 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
3395 05:55:48.777681 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3396 05:55:48.780803 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3397 05:55:48.783934 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3398 05:55:48.787355 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3399 05:55:48.793932 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3400 05:55:48.797151 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3401 05:55:48.800250 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3402 05:55:48.803516 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3403 05:55:48.807241 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3404 05:55:48.813732 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3405 05:55:48.816893 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3406 05:55:48.820829 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
3407 05:55:48.821340 ==
3408 05:55:48.823724 Dram Type= 6, Freq= 0, CH_1, rank 1
3409 05:55:48.826831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3410 05:55:48.827245 ==
3411 05:55:48.830741 DQS Delay:
3412 05:55:48.831250 DQS0 = 0, DQS1 = 0
3413 05:55:48.833521 DQM Delay:
3414 05:55:48.833964 DQM0 = 117, DQM1 = 107
3415 05:55:48.837232 DQ Delay:
3416 05:55:48.841011 DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =119
3417 05:55:48.843965 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3418 05:55:48.847230 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =103
3419 05:55:48.850727 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
3420 05:55:48.851139
3421 05:55:48.851462
3422 05:55:48.851765 ==
3423 05:55:48.853806 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 05:55:48.857143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3425 05:55:48.857663 ==
3426 05:55:48.857995
3427 05:55:48.858296
3428 05:55:48.860673 TX Vref Scan disable
3429 05:55:48.863637 == TX Byte 0 ==
3430 05:55:48.867272 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3431 05:55:48.870298 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3432 05:55:48.873468 == TX Byte 1 ==
3433 05:55:48.876671 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3434 05:55:48.880487 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3435 05:55:48.881091 ==
3436 05:55:48.883706 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 05:55:48.887003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3438 05:55:48.890413 ==
3439 05:55:48.900215 TX Vref=22, minBit 9, minWin=25, winSum=422
3440 05:55:48.903510 TX Vref=24, minBit 0, minWin=26, winSum=425
3441 05:55:48.906533 TX Vref=26, minBit 0, minWin=26, winSum=428
3442 05:55:48.909611 TX Vref=28, minBit 8, minWin=26, winSum=436
3443 05:55:48.913309 TX Vref=30, minBit 9, minWin=26, winSum=432
3444 05:55:48.919909 TX Vref=32, minBit 0, minWin=26, winSum=432
3445 05:55:48.923179 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 28
3446 05:55:48.923731
3447 05:55:48.926180 Final TX Range 1 Vref 28
3448 05:55:48.926648
3449 05:55:48.926978 ==
3450 05:55:48.930062 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 05:55:48.932798 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3452 05:55:48.933236 ==
3453 05:55:48.936127
3454 05:55:48.936666
3455 05:55:48.937203 TX Vref Scan disable
3456 05:55:48.940103 == TX Byte 0 ==
3457 05:55:48.943415 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3458 05:55:48.946433 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3459 05:55:48.949572 == TX Byte 1 ==
3460 05:55:48.953166 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3461 05:55:48.959855 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3462 05:55:48.960344
3463 05:55:48.960671 [DATLAT]
3464 05:55:48.961039 Freq=1200, CH1 RK1
3465 05:55:48.961336
3466 05:55:48.963455 DATLAT Default: 0xc
3467 05:55:48.963960 0, 0xFFFF, sum = 0
3468 05:55:48.966646 1, 0xFFFF, sum = 0
3469 05:55:48.967168 2, 0xFFFF, sum = 0
3470 05:55:48.969669 3, 0xFFFF, sum = 0
3471 05:55:48.972851 4, 0xFFFF, sum = 0
3472 05:55:48.973303 5, 0xFFFF, sum = 0
3473 05:55:48.975965 6, 0xFFFF, sum = 0
3474 05:55:48.976428 7, 0xFFFF, sum = 0
3475 05:55:48.979638 8, 0xFFFF, sum = 0
3476 05:55:48.980158 9, 0xFFFF, sum = 0
3477 05:55:48.982586 10, 0xFFFF, sum = 0
3478 05:55:48.983156 11, 0x0, sum = 1
3479 05:55:48.986025 12, 0x0, sum = 2
3480 05:55:48.986541 13, 0x0, sum = 3
3481 05:55:48.989389 14, 0x0, sum = 4
3482 05:55:48.989911 best_step = 12
3483 05:55:48.990240
3484 05:55:48.990542 ==
3485 05:55:48.992869 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 05:55:48.996263 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3487 05:55:48.996848 ==
3488 05:55:48.999211 RX Vref Scan: 0
3489 05:55:48.999624
3490 05:55:49.002745 RX Vref 0 -> 0, step: 1
3491 05:55:49.003158
3492 05:55:49.003482 RX Delay -29 -> 252, step: 4
3493 05:55:49.010309 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3494 05:55:49.013771 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3495 05:55:49.016691 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3496 05:55:49.020303 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3497 05:55:49.023570 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3498 05:55:49.030224 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3499 05:55:49.033461 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3500 05:55:49.036801 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3501 05:55:49.039969 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3502 05:55:49.043365 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3503 05:55:49.049849 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3504 05:55:49.053088 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3505 05:55:49.056426 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3506 05:55:49.059729 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3507 05:55:49.063311 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3508 05:55:49.069938 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3509 05:55:49.070046 ==
3510 05:55:49.073384 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 05:55:49.076675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3512 05:55:49.076766 ==
3513 05:55:49.076833 DQS Delay:
3514 05:55:49.080179 DQS0 = 0, DQS1 = 0
3515 05:55:49.080261 DQM Delay:
3516 05:55:49.083156 DQM0 = 115, DQM1 = 104
3517 05:55:49.083238 DQ Delay:
3518 05:55:49.086240 DQ0 =114, DQ1 =112, DQ2 =108, DQ3 =112
3519 05:55:49.089844 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3520 05:55:49.093063 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98
3521 05:55:49.096229 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =112
3522 05:55:49.096310
3523 05:55:49.096373
3524 05:55:49.106682 [DQSOSCAuto] RK1, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3525 05:55:49.110171 CH1 RK1: MR19=404, MR18=909
3526 05:55:49.113158 CH1_RK1: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
3527 05:55:49.116758 [RxdqsGatingPostProcess] freq 1200
3528 05:55:49.123130 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3529 05:55:49.126299 Pre-setting of DQS Precalculation
3530 05:55:49.129946 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3531 05:55:49.140024 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3532 05:55:49.146798 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3533 05:55:49.147057
3534 05:55:49.147208
3535 05:55:49.150402 [Calibration Summary] 2400 Mbps
3536 05:55:49.150607 CH 0, Rank 0
3537 05:55:49.153200 SW Impedance : PASS
3538 05:55:49.153441 DUTY Scan : NO K
3539 05:55:49.156403 ZQ Calibration : PASS
3540 05:55:49.159921 Jitter Meter : NO K
3541 05:55:49.160318 CBT Training : PASS
3542 05:55:49.163426 Write leveling : PASS
3543 05:55:49.166529 RX DQS gating : PASS
3544 05:55:49.167020 RX DQ/DQS(RDDQC) : PASS
3545 05:55:49.169964 TX DQ/DQS : PASS
3546 05:55:49.170444 RX DATLAT : PASS
3547 05:55:49.173272 RX DQ/DQS(Engine): PASS
3548 05:55:49.176652 TX OE : NO K
3549 05:55:49.177252 All Pass.
3550 05:55:49.177616
3551 05:55:49.177945 CH 0, Rank 1
3552 05:55:49.180104 SW Impedance : PASS
3553 05:55:49.183292 DUTY Scan : NO K
3554 05:55:49.183769 ZQ Calibration : PASS
3555 05:55:49.186889 Jitter Meter : NO K
3556 05:55:49.190143 CBT Training : PASS
3557 05:55:49.190693 Write leveling : PASS
3558 05:55:49.193365 RX DQS gating : PASS
3559 05:55:49.196555 RX DQ/DQS(RDDQC) : PASS
3560 05:55:49.197202 TX DQ/DQS : PASS
3561 05:55:49.199785 RX DATLAT : PASS
3562 05:55:49.203129 RX DQ/DQS(Engine): PASS
3563 05:55:49.203585 TX OE : NO K
3564 05:55:49.206641 All Pass.
3565 05:55:49.207195
3566 05:55:49.207554 CH 1, Rank 0
3567 05:55:49.209680 SW Impedance : PASS
3568 05:55:49.210132 DUTY Scan : NO K
3569 05:55:49.213163 ZQ Calibration : PASS
3570 05:55:49.216761 Jitter Meter : NO K
3571 05:55:49.217223 CBT Training : PASS
3572 05:55:49.220441 Write leveling : PASS
3573 05:55:49.223133 RX DQS gating : PASS
3574 05:55:49.223599 RX DQ/DQS(RDDQC) : PASS
3575 05:55:49.226493 TX DQ/DQS : PASS
3576 05:55:49.226948 RX DATLAT : PASS
3577 05:55:49.229919 RX DQ/DQS(Engine): PASS
3578 05:55:49.232923 TX OE : NO K
3579 05:55:49.233407 All Pass.
3580 05:55:49.233778
3581 05:55:49.234112 CH 1, Rank 1
3582 05:55:49.236929 SW Impedance : PASS
3583 05:55:49.240194 DUTY Scan : NO K
3584 05:55:49.240783 ZQ Calibration : PASS
3585 05:55:49.243508 Jitter Meter : NO K
3586 05:55:49.246459 CBT Training : PASS
3587 05:55:49.246917 Write leveling : PASS
3588 05:55:49.250173 RX DQS gating : PASS
3589 05:55:49.253301 RX DQ/DQS(RDDQC) : PASS
3590 05:55:49.253857 TX DQ/DQS : PASS
3591 05:55:49.256563 RX DATLAT : PASS
3592 05:55:49.257080 RX DQ/DQS(Engine): PASS
3593 05:55:49.260045 TX OE : NO K
3594 05:55:49.260498 All Pass.
3595 05:55:49.260976
3596 05:55:49.263070 DramC Write-DBI off
3597 05:55:49.266494 PER_BANK_REFRESH: Hybrid Mode
3598 05:55:49.266946 TX_TRACKING: ON
3599 05:55:49.276777 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3600 05:55:49.279989 [FAST_K] Save calibration result to emmc
3601 05:55:49.283180 dramc_set_vcore_voltage set vcore to 650000
3602 05:55:49.286874 Read voltage for 600, 5
3603 05:55:49.287417 Vio18 = 0
3604 05:55:49.289832 Vcore = 650000
3605 05:55:49.290284 Vdram = 0
3606 05:55:49.290640 Vddq = 0
3607 05:55:49.291054 Vmddr = 0
3608 05:55:49.296921 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3609 05:55:49.302926 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3610 05:55:49.303509 MEM_TYPE=3, freq_sel=19
3611 05:55:49.306681 sv_algorithm_assistance_LP4_1600
3612 05:55:49.309937 ============ PULL DRAM RESETB DOWN ============
3613 05:55:49.316265 ========== PULL DRAM RESETB DOWN end =========
3614 05:55:49.319827 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3615 05:55:49.322993 ===================================
3616 05:55:49.326206 LPDDR4 DRAM CONFIGURATION
3617 05:55:49.329481 ===================================
3618 05:55:49.329934 EX_ROW_EN[0] = 0x0
3619 05:55:49.332502 EX_ROW_EN[1] = 0x0
3620 05:55:49.333008 LP4Y_EN = 0x0
3621 05:55:49.336509 WORK_FSP = 0x0
3622 05:55:49.339191 WL = 0x2
3623 05:55:49.339645 RL = 0x2
3624 05:55:49.342603 BL = 0x2
3625 05:55:49.343055 RPST = 0x0
3626 05:55:49.345811 RD_PRE = 0x0
3627 05:55:49.346282 WR_PRE = 0x1
3628 05:55:49.349517 WR_PST = 0x0
3629 05:55:49.349971 DBI_WR = 0x0
3630 05:55:49.352673 DBI_RD = 0x0
3631 05:55:49.353180 OTF = 0x1
3632 05:55:49.356160 ===================================
3633 05:55:49.359632 ===================================
3634 05:55:49.362772 ANA top config
3635 05:55:49.365813 ===================================
3636 05:55:49.366474 DLL_ASYNC_EN = 0
3637 05:55:49.369058 ALL_SLAVE_EN = 1
3638 05:55:49.372206 NEW_RANK_MODE = 1
3639 05:55:49.375930 DLL_IDLE_MODE = 1
3640 05:55:49.379158 LP45_APHY_COMB_EN = 1
3641 05:55:49.379738 TX_ODT_DIS = 1
3642 05:55:49.382501 NEW_8X_MODE = 1
3643 05:55:49.385825 ===================================
3644 05:55:49.389234 ===================================
3645 05:55:49.392636 data_rate = 1200
3646 05:55:49.395811 CKR = 1
3647 05:55:49.398580 DQ_P2S_RATIO = 8
3648 05:55:49.402035 ===================================
3649 05:55:49.402499 CA_P2S_RATIO = 8
3650 05:55:49.405897 DQ_CA_OPEN = 0
3651 05:55:49.409207 DQ_SEMI_OPEN = 0
3652 05:55:49.412232 CA_SEMI_OPEN = 0
3653 05:55:49.415433 CA_FULL_RATE = 0
3654 05:55:49.418702 DQ_CKDIV4_EN = 1
3655 05:55:49.422026 CA_CKDIV4_EN = 1
3656 05:55:49.422597 CA_PREDIV_EN = 0
3657 05:55:49.424999 PH8_DLY = 0
3658 05:55:49.428549 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3659 05:55:49.431788 DQ_AAMCK_DIV = 4
3660 05:55:49.434821 CA_AAMCK_DIV = 4
3661 05:55:49.435281 CA_ADMCK_DIV = 4
3662 05:55:49.438334 DQ_TRACK_CA_EN = 0
3663 05:55:49.441662 CA_PICK = 600
3664 05:55:49.445427 CA_MCKIO = 600
3665 05:55:49.449028 MCKIO_SEMI = 0
3666 05:55:49.451909 PLL_FREQ = 2288
3667 05:55:49.455006 DQ_UI_PI_RATIO = 32
3668 05:55:49.455468 CA_UI_PI_RATIO = 0
3669 05:55:49.458347 ===================================
3670 05:55:49.461773 ===================================
3671 05:55:49.465174 memory_type:LPDDR4
3672 05:55:49.468446 GP_NUM : 10
3673 05:55:49.468952 SRAM_EN : 1
3674 05:55:49.471762 MD32_EN : 0
3675 05:55:49.474998 ===================================
3676 05:55:49.478514 [ANA_INIT] >>>>>>>>>>>>>>
3677 05:55:49.481559 <<<<<< [CONFIGURE PHASE]: ANA_TX
3678 05:55:49.485019 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3679 05:55:49.488514 ===================================
3680 05:55:49.489148 data_rate = 1200,PCW = 0X5800
3681 05:55:49.491688 ===================================
3682 05:55:49.498786 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3683 05:55:49.501677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3684 05:55:49.508455 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3685 05:55:49.511794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3686 05:55:49.514735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3687 05:55:49.517832 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3688 05:55:49.521387 [ANA_INIT] flow start
3689 05:55:49.524477 [ANA_INIT] PLL >>>>>>>>
3690 05:55:49.525076 [ANA_INIT] PLL <<<<<<<<
3691 05:55:49.527641 [ANA_INIT] MIDPI >>>>>>>>
3692 05:55:49.531003 [ANA_INIT] MIDPI <<<<<<<<
3693 05:55:49.531453 [ANA_INIT] DLL >>>>>>>>
3694 05:55:49.534216 [ANA_INIT] flow end
3695 05:55:49.537722 ============ LP4 DIFF to SE enter ============
3696 05:55:49.544468 ============ LP4 DIFF to SE exit ============
3697 05:55:49.544975 [ANA_INIT] <<<<<<<<<<<<<
3698 05:55:49.548077 [Flow] Enable top DCM control >>>>>
3699 05:55:49.550875 [Flow] Enable top DCM control <<<<<
3700 05:55:49.554275 Enable DLL master slave shuffle
3701 05:55:49.561202 ==============================================================
3702 05:55:49.561659 Gating Mode config
3703 05:55:49.567728 ==============================================================
3704 05:55:49.571137 Config description:
3705 05:55:49.577735 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3706 05:55:49.584489 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3707 05:55:49.590962 SELPH_MODE 0: By rank 1: By Phase
3708 05:55:49.597714 ==============================================================
3709 05:55:49.598276 GAT_TRACK_EN = 1
3710 05:55:49.600780 RX_GATING_MODE = 2
3711 05:55:49.604252 RX_GATING_TRACK_MODE = 2
3712 05:55:49.607821 SELPH_MODE = 1
3713 05:55:49.610991 PICG_EARLY_EN = 1
3714 05:55:49.614295 VALID_LAT_VALUE = 1
3715 05:55:49.620467 ==============================================================
3716 05:55:49.624065 Enter into Gating configuration >>>>
3717 05:55:49.627019 Exit from Gating configuration <<<<
3718 05:55:49.630381 Enter into DVFS_PRE_config >>>>>
3719 05:55:49.640689 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3720 05:55:49.643704 Exit from DVFS_PRE_config <<<<<
3721 05:55:49.646813 Enter into PICG configuration >>>>
3722 05:55:49.650631 Exit from PICG configuration <<<<
3723 05:55:49.653921 [RX_INPUT] configuration >>>>>
3724 05:55:49.657039 [RX_INPUT] configuration <<<<<
3725 05:55:49.660594 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3726 05:55:49.667118 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3727 05:55:49.674530 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3728 05:55:49.677275 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3729 05:55:49.683472 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3730 05:55:49.690748 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3731 05:55:49.693448 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3732 05:55:49.700092 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3733 05:55:49.703379 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3734 05:55:49.706685 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3735 05:55:49.710133 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3736 05:55:49.716624 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3737 05:55:49.720056 ===================================
3738 05:55:49.720611 LPDDR4 DRAM CONFIGURATION
3739 05:55:49.723575 ===================================
3740 05:55:49.726703 EX_ROW_EN[0] = 0x0
3741 05:55:49.730033 EX_ROW_EN[1] = 0x0
3742 05:55:49.730490 LP4Y_EN = 0x0
3743 05:55:49.733150 WORK_FSP = 0x0
3744 05:55:49.733604 WL = 0x2
3745 05:55:49.736874 RL = 0x2
3746 05:55:49.737328 BL = 0x2
3747 05:55:49.740093 RPST = 0x0
3748 05:55:49.740643 RD_PRE = 0x0
3749 05:55:49.743108 WR_PRE = 0x1
3750 05:55:49.743574 WR_PST = 0x0
3751 05:55:49.746353 DBI_WR = 0x0
3752 05:55:49.746900 DBI_RD = 0x0
3753 05:55:49.749674 OTF = 0x1
3754 05:55:49.753008 ===================================
3755 05:55:49.756853 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3756 05:55:49.759741 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3757 05:55:49.766620 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3758 05:55:49.769582 ===================================
3759 05:55:49.770036 LPDDR4 DRAM CONFIGURATION
3760 05:55:49.772780 ===================================
3761 05:55:49.776077 EX_ROW_EN[0] = 0x10
3762 05:55:49.779607 EX_ROW_EN[1] = 0x0
3763 05:55:49.780063 LP4Y_EN = 0x0
3764 05:55:49.782670 WORK_FSP = 0x0
3765 05:55:49.783124 WL = 0x2
3766 05:55:49.786032 RL = 0x2
3767 05:55:49.786482 BL = 0x2
3768 05:55:49.789604 RPST = 0x0
3769 05:55:49.790159 RD_PRE = 0x0
3770 05:55:49.792659 WR_PRE = 0x1
3771 05:55:49.793362 WR_PST = 0x0
3772 05:55:49.796241 DBI_WR = 0x0
3773 05:55:49.796837 DBI_RD = 0x0
3774 05:55:49.799401 OTF = 0x1
3775 05:55:49.802366 ===================================
3776 05:55:49.809180 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3777 05:55:49.812926 nWR fixed to 30
3778 05:55:49.813384 [ModeRegInit_LP4] CH0 RK0
3779 05:55:49.816037 [ModeRegInit_LP4] CH0 RK1
3780 05:55:49.819538 [ModeRegInit_LP4] CH1 RK0
3781 05:55:49.822498 [ModeRegInit_LP4] CH1 RK1
3782 05:55:49.823048 match AC timing 16
3783 05:55:49.828690 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3784 05:55:49.832114 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3785 05:55:49.835988 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3786 05:55:49.842962 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3787 05:55:49.845581 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3788 05:55:49.846038 ==
3789 05:55:49.849061 Dram Type= 6, Freq= 0, CH_0, rank 0
3790 05:55:49.852459 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3791 05:55:49.853105 ==
3792 05:55:49.859176 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3793 05:55:49.865697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3794 05:55:49.868906 [CA 0] Center 36 (6~66) winsize 61
3795 05:55:49.872019 [CA 1] Center 36 (6~66) winsize 61
3796 05:55:49.875436 [CA 2] Center 34 (4~65) winsize 62
3797 05:55:49.878499 [CA 3] Center 34 (3~65) winsize 63
3798 05:55:49.882066 [CA 4] Center 33 (3~64) winsize 62
3799 05:55:49.885111 [CA 5] Center 33 (3~64) winsize 62
3800 05:55:49.885573
3801 05:55:49.888912 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3802 05:55:49.889495
3803 05:55:49.891492 [CATrainingPosCal] consider 1 rank data
3804 05:55:49.895195 u2DelayCellTimex100 = 270/100 ps
3805 05:55:49.898922 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3806 05:55:49.901719 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3807 05:55:49.905364 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3808 05:55:49.908820 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3809 05:55:49.911916 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3810 05:55:49.915241 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3811 05:55:49.918521
3812 05:55:49.921649 CA PerBit enable=1, Macro0, CA PI delay=33
3813 05:55:49.922109
3814 05:55:49.925008 [CBTSetCACLKResult] CA Dly = 33
3815 05:55:49.925464 CS Dly: 5 (0~36)
3816 05:55:49.925821 ==
3817 05:55:49.928380 Dram Type= 6, Freq= 0, CH_0, rank 1
3818 05:55:49.931436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3819 05:55:49.931894 ==
3820 05:55:49.938567 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3821 05:55:49.944480 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3822 05:55:49.948465 [CA 0] Center 36 (6~66) winsize 61
3823 05:55:49.951430 [CA 1] Center 35 (5~66) winsize 62
3824 05:55:49.954994 [CA 2] Center 34 (4~65) winsize 62
3825 05:55:49.958787 [CA 3] Center 34 (4~65) winsize 62
3826 05:55:49.961381 [CA 4] Center 33 (3~64) winsize 62
3827 05:55:49.964939 [CA 5] Center 33 (3~64) winsize 62
3828 05:55:49.965534
3829 05:55:49.968275 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3830 05:55:49.968961
3831 05:55:49.971153 [CATrainingPosCal] consider 2 rank data
3832 05:55:49.974846 u2DelayCellTimex100 = 270/100 ps
3833 05:55:49.978105 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3834 05:55:49.981294 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3835 05:55:49.984832 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3836 05:55:49.987931 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3837 05:55:49.995064 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3838 05:55:49.997771 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3839 05:55:49.998342
3840 05:55:50.000967 CA PerBit enable=1, Macro0, CA PI delay=33
3841 05:55:50.001419
3842 05:55:50.004346 [CBTSetCACLKResult] CA Dly = 33
3843 05:55:50.004860 CS Dly: 5 (0~36)
3844 05:55:50.005232
3845 05:55:50.007747 ----->DramcWriteLeveling(PI) begin...
3846 05:55:50.008331 ==
3847 05:55:50.011053 Dram Type= 6, Freq= 0, CH_0, rank 0
3848 05:55:50.018162 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3849 05:55:50.018716 ==
3850 05:55:50.021037 Write leveling (Byte 0): 32 => 32
3851 05:55:50.024462 Write leveling (Byte 1): 30 => 30
3852 05:55:50.025094 DramcWriteLeveling(PI) end<-----
3853 05:55:50.025466
3854 05:55:50.027618 ==
3855 05:55:50.028118 Dram Type= 6, Freq= 0, CH_0, rank 0
3856 05:55:50.034465 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3857 05:55:50.034925 ==
3858 05:55:50.037698 [Gating] SW mode calibration
3859 05:55:50.044610 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3860 05:55:50.047565 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3861 05:55:50.054171 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3862 05:55:50.057665 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3863 05:55:50.061395 0 5 8 | B1->B0 | 3434 2f2f | 0 1 | (1 1) (1 0)
3864 05:55:50.067897 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3865 05:55:50.071341 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3866 05:55:50.074074 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3867 05:55:50.081079 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3868 05:55:50.084048 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3869 05:55:50.087584 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3870 05:55:50.094002 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3871 05:55:50.097677 0 6 8 | B1->B0 | 2b2b 2f2f | 0 1 | (0 0) (0 0)
3872 05:55:50.100879 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3873 05:55:50.107418 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3874 05:55:50.110674 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3875 05:55:50.113972 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3876 05:55:50.117237 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3877 05:55:50.124151 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3878 05:55:50.127038 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3879 05:55:50.130551 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3880 05:55:50.136853 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3881 05:55:50.140846 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 05:55:50.144204 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 05:55:50.150778 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 05:55:50.153809 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 05:55:50.156835 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 05:55:50.163455 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 05:55:50.166858 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 05:55:50.170204 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 05:55:50.177150 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3890 05:55:50.180425 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3891 05:55:50.183724 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3892 05:55:50.190233 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3893 05:55:50.193478 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3894 05:55:50.196639 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3895 05:55:50.203485 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3896 05:55:50.206657 Total UI for P1: 0, mck2ui 16
3897 05:55:50.210046 best dqsien dly found for B0: ( 0, 9, 6)
3898 05:55:50.212792 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3899 05:55:50.216629 Total UI for P1: 0, mck2ui 16
3900 05:55:50.219799 best dqsien dly found for B1: ( 0, 9, 8)
3901 05:55:50.223168 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3902 05:55:50.226022 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3903 05:55:50.226476
3904 05:55:50.229603 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3905 05:55:50.233402 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3906 05:55:50.236516 [Gating] SW calibration Done
3907 05:55:50.237106 ==
3908 05:55:50.239561 Dram Type= 6, Freq= 0, CH_0, rank 0
3909 05:55:50.246266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3910 05:55:50.246723 ==
3911 05:55:50.247104 RX Vref Scan: 0
3912 05:55:50.247498
3913 05:55:50.249313 RX Vref 0 -> 0, step: 1
3914 05:55:50.249766
3915 05:55:50.252329 RX Delay -230 -> 252, step: 16
3916 05:55:50.255900 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3917 05:55:50.259414 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3918 05:55:50.262296 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3919 05:55:50.269472 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3920 05:55:50.272649 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3921 05:55:50.276086 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3922 05:55:50.279376 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3923 05:55:50.285935 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3924 05:55:50.289253 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3925 05:55:50.292329 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3926 05:55:50.295748 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3927 05:55:50.302165 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3928 05:55:50.305561 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3929 05:55:50.308883 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3930 05:55:50.312075 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3931 05:55:50.319148 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3932 05:55:50.319708 ==
3933 05:55:50.322056 Dram Type= 6, Freq= 0, CH_0, rank 0
3934 05:55:50.325481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3935 05:55:50.325938 ==
3936 05:55:50.326297 DQS Delay:
3937 05:55:50.328788 DQS0 = 0, DQS1 = 0
3938 05:55:50.329242 DQM Delay:
3939 05:55:50.331953 DQM0 = 37, DQM1 = 33
3940 05:55:50.332408 DQ Delay:
3941 05:55:50.335169 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3942 05:55:50.338392 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
3943 05:55:50.342241 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3944 05:55:50.345285 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3945 05:55:50.345757
3946 05:55:50.346116
3947 05:55:50.346444 ==
3948 05:55:50.348324 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 05:55:50.351600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3950 05:55:50.352055 ==
3951 05:55:50.352414
3952 05:55:50.355232
3953 05:55:50.355757 TX Vref Scan disable
3954 05:55:50.358305 == TX Byte 0 ==
3955 05:55:50.361766 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3956 05:55:50.364859 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3957 05:55:50.368393 == TX Byte 1 ==
3958 05:55:50.371784 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3959 05:55:50.374790 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3960 05:55:50.375245 ==
3961 05:55:50.377807 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 05:55:50.385169 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3963 05:55:50.385721 ==
3964 05:55:50.386083
3965 05:55:50.386415
3966 05:55:50.387742 TX Vref Scan disable
3967 05:55:50.388195 == TX Byte 0 ==
3968 05:55:50.394602 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3969 05:55:50.398268 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3970 05:55:50.398821 == TX Byte 1 ==
3971 05:55:50.404780 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3972 05:55:50.408081 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3973 05:55:50.408535
3974 05:55:50.408952 [DATLAT]
3975 05:55:50.411321 Freq=600, CH0 RK0
3976 05:55:50.411874
3977 05:55:50.412232 DATLAT Default: 0x9
3978 05:55:50.414024 0, 0xFFFF, sum = 0
3979 05:55:50.414487 1, 0xFFFF, sum = 0
3980 05:55:50.417579 2, 0xFFFF, sum = 0
3981 05:55:50.421153 3, 0xFFFF, sum = 0
3982 05:55:50.421727 4, 0xFFFF, sum = 0
3983 05:55:50.424417 5, 0xFFFF, sum = 0
3984 05:55:50.425034 6, 0xFFFF, sum = 0
3985 05:55:50.427453 7, 0x0, sum = 1
3986 05:55:50.428013 8, 0x0, sum = 2
3987 05:55:50.428381 9, 0x0, sum = 3
3988 05:55:50.431147 10, 0x0, sum = 4
3989 05:55:50.431839 best_step = 8
3990 05:55:50.432227
3991 05:55:50.432607 ==
3992 05:55:50.433963 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 05:55:50.440796 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3994 05:55:50.441374 ==
3995 05:55:50.441742 RX Vref Scan: 1
3996 05:55:50.442079
3997 05:55:50.444316 RX Vref 0 -> 0, step: 1
3998 05:55:50.444992
3999 05:55:50.447652 RX Delay -195 -> 252, step: 8
4000 05:55:50.448141
4001 05:55:50.450757 Set Vref, RX VrefLevel [Byte0]: 52
4002 05:55:50.454019 [Byte1]: 48
4003 05:55:50.454472
4004 05:55:50.457042 Final RX Vref Byte 0 = 52 to rank0
4005 05:55:50.460703 Final RX Vref Byte 1 = 48 to rank0
4006 05:55:50.463907 Final RX Vref Byte 0 = 52 to rank1
4007 05:55:50.467427 Final RX Vref Byte 1 = 48 to rank1==
4008 05:55:50.470755 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 05:55:50.473728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4010 05:55:50.474230 ==
4011 05:55:50.477519 DQS Delay:
4012 05:55:50.477973 DQS0 = 0, DQS1 = 0
4013 05:55:50.480444 DQM Delay:
4014 05:55:50.480941 DQM0 = 39, DQM1 = 30
4015 05:55:50.481305 DQ Delay:
4016 05:55:50.484078 DQ0 =32, DQ1 =40, DQ2 =40, DQ3 =36
4017 05:55:50.487158 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =52
4018 05:55:50.490730 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4019 05:55:50.493979 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4020 05:55:50.494536
4021 05:55:50.494928
4022 05:55:50.503334 [DQSOSCAuto] RK0, (LSB)MR18= 0x5959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4023 05:55:50.507036 CH0 RK0: MR19=808, MR18=5959
4024 05:55:50.513449 CH0_RK0: MR19=0x808, MR18=0x5959, DQSOSC=393, MR23=63, INC=169, DEC=113
4025 05:55:50.513998
4026 05:55:50.516904 ----->DramcWriteLeveling(PI) begin...
4027 05:55:50.517462 ==
4028 05:55:50.520247 Dram Type= 6, Freq= 0, CH_0, rank 1
4029 05:55:50.523529 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4030 05:55:50.523990 ==
4031 05:55:50.526973 Write leveling (Byte 0): 28 => 28
4032 05:55:50.529760 Write leveling (Byte 1): 29 => 29
4033 05:55:50.533251 DramcWriteLeveling(PI) end<-----
4034 05:55:50.533706
4035 05:55:50.534061 ==
4036 05:55:50.536590 Dram Type= 6, Freq= 0, CH_0, rank 1
4037 05:55:50.539791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4038 05:55:50.540376 ==
4039 05:55:50.542791 [Gating] SW mode calibration
4040 05:55:50.549572 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4041 05:55:50.556115 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4042 05:55:50.559284 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 05:55:50.563001 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 05:55:50.569769 0 5 8 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 1)
4045 05:55:50.572805 0 5 12 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
4046 05:55:50.576029 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 05:55:50.582372 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 05:55:50.586012 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 05:55:50.589510 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 05:55:50.596302 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 05:55:50.599206 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 05:55:50.602491 0 6 8 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 0)
4053 05:55:50.609367 0 6 12 | B1->B0 | 4242 4545 | 0 0 | (0 0) (0 0)
4054 05:55:50.612363 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 05:55:50.615887 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 05:55:50.622954 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 05:55:50.625811 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 05:55:50.629011 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 05:55:50.636189 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 05:55:50.639530 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 05:55:50.642320 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 05:55:50.648919 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 05:55:50.652197 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 05:55:50.655896 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 05:55:50.662362 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 05:55:50.665433 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 05:55:50.669062 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 05:55:50.675165 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 05:55:50.678288 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 05:55:50.681952 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 05:55:50.688905 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 05:55:50.691740 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 05:55:50.694735 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 05:55:50.701804 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 05:55:50.705023 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 05:55:50.708354 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4077 05:55:50.711464 Total UI for P1: 0, mck2ui 16
4078 05:55:50.714942 best dqsien dly found for B0: ( 0, 9, 6)
4079 05:55:50.721095 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 05:55:50.721422 Total UI for P1: 0, mck2ui 16
4081 05:55:50.728025 best dqsien dly found for B1: ( 0, 9, 8)
4082 05:55:50.730690 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4083 05:55:50.734185 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4084 05:55:50.734423
4085 05:55:50.737789 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4086 05:55:50.741025 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4087 05:55:50.744267 [Gating] SW calibration Done
4088 05:55:50.744511 ==
4089 05:55:50.747495 Dram Type= 6, Freq= 0, CH_0, rank 1
4090 05:55:50.751064 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4091 05:55:50.751303 ==
4092 05:55:50.754137 RX Vref Scan: 0
4093 05:55:50.754376
4094 05:55:50.754515 RX Vref 0 -> 0, step: 1
4095 05:55:50.754640
4096 05:55:50.757170 RX Delay -230 -> 252, step: 16
4097 05:55:50.764053 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4098 05:55:50.767489 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4099 05:55:50.771073 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4100 05:55:50.773933 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4101 05:55:50.777423 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4102 05:55:50.784535 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4103 05:55:50.787323 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4104 05:55:50.790551 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4105 05:55:50.794214 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4106 05:55:50.800686 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4107 05:55:50.803541 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4108 05:55:50.806991 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4109 05:55:50.810530 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4110 05:55:50.816964 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4111 05:55:50.819980 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4112 05:55:50.823572 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4113 05:55:50.824148 ==
4114 05:55:50.826685 Dram Type= 6, Freq= 0, CH_0, rank 1
4115 05:55:50.833515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4116 05:55:50.834097 ==
4117 05:55:50.834465 DQS Delay:
4118 05:55:50.834800 DQS0 = 0, DQS1 = 0
4119 05:55:50.836542 DQM Delay:
4120 05:55:50.837122 DQM0 = 41, DQM1 = 34
4121 05:55:50.839795 DQ Delay:
4122 05:55:50.843945 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4123 05:55:50.846479 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4124 05:55:50.849923 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4125 05:55:50.853356 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4126 05:55:50.853914
4127 05:55:50.854278
4128 05:55:50.854607 ==
4129 05:55:50.856399 Dram Type= 6, Freq= 0, CH_0, rank 1
4130 05:55:50.859954 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4131 05:55:50.860409 ==
4132 05:55:50.860799
4133 05:55:50.861133
4134 05:55:50.863317 TX Vref Scan disable
4135 05:55:50.863771 == TX Byte 0 ==
4136 05:55:50.870036 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4137 05:55:50.873451 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4138 05:55:50.874061 == TX Byte 1 ==
4139 05:55:50.880144 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4140 05:55:50.883001 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4141 05:55:50.883613 ==
4142 05:55:50.886141 Dram Type= 6, Freq= 0, CH_0, rank 1
4143 05:55:50.889719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4144 05:55:50.890343 ==
4145 05:55:50.890712
4146 05:55:50.892973
4147 05:55:50.893469 TX Vref Scan disable
4148 05:55:50.896239 == TX Byte 0 ==
4149 05:55:50.899577 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4150 05:55:50.906401 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4151 05:55:50.906857 == TX Byte 1 ==
4152 05:55:50.910031 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4153 05:55:50.916370 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4154 05:55:50.916969
4155 05:55:50.917334 [DATLAT]
4156 05:55:50.917670 Freq=600, CH0 RK1
4157 05:55:50.917994
4158 05:55:50.919744 DATLAT Default: 0x8
4159 05:55:50.922374 0, 0xFFFF, sum = 0
4160 05:55:50.922835 1, 0xFFFF, sum = 0
4161 05:55:50.926468 2, 0xFFFF, sum = 0
4162 05:55:50.927032 3, 0xFFFF, sum = 0
4163 05:55:50.929429 4, 0xFFFF, sum = 0
4164 05:55:50.929892 5, 0xFFFF, sum = 0
4165 05:55:50.933060 6, 0xFFFF, sum = 0
4166 05:55:50.933710 7, 0x0, sum = 1
4167 05:55:50.936044 8, 0x0, sum = 2
4168 05:55:50.936508 9, 0x0, sum = 3
4169 05:55:50.936942 10, 0x0, sum = 4
4170 05:55:50.939384 best_step = 8
4171 05:55:50.939934
4172 05:55:50.940294 ==
4173 05:55:50.942809 Dram Type= 6, Freq= 0, CH_0, rank 1
4174 05:55:50.945836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4175 05:55:50.946296 ==
4176 05:55:50.948847 RX Vref Scan: 0
4177 05:55:50.949374
4178 05:55:50.949747 RX Vref 0 -> 0, step: 1
4179 05:55:50.952054
4180 05:55:50.952547 RX Delay -179 -> 252, step: 8
4181 05:55:50.960177 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4182 05:55:50.963329 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4183 05:55:50.966650 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4184 05:55:50.969916 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4185 05:55:50.976391 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4186 05:55:50.980252 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4187 05:55:50.983284 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4188 05:55:50.986162 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4189 05:55:50.992949 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4190 05:55:50.996185 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4191 05:55:50.999516 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4192 05:55:51.002768 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4193 05:55:51.006117 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4194 05:55:51.012863 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4195 05:55:51.016270 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4196 05:55:51.019637 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4197 05:55:51.020220 ==
4198 05:55:51.022685 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 05:55:51.029581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4200 05:55:51.030201 ==
4201 05:55:51.030575 DQS Delay:
4202 05:55:51.030913 DQS0 = 0, DQS1 = 0
4203 05:55:51.033333 DQM Delay:
4204 05:55:51.033789 DQM0 = 41, DQM1 = 33
4205 05:55:51.035926 DQ Delay:
4206 05:55:51.039339 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4207 05:55:51.042595 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4208 05:55:51.045820 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =24
4209 05:55:51.049185 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4210 05:55:51.049724
4211 05:55:51.050086
4212 05:55:51.055876 [DQSOSCAuto] RK1, (LSB)MR18= 0x6363, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4213 05:55:51.059299 CH0 RK1: MR19=808, MR18=6363
4214 05:55:51.065646 CH0_RK1: MR19=0x808, MR18=0x6363, DQSOSC=391, MR23=63, INC=171, DEC=114
4215 05:55:51.069025 [RxdqsGatingPostProcess] freq 600
4216 05:55:51.072125 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4217 05:55:51.075609 Pre-setting of DQS Precalculation
4218 05:55:51.082558 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4219 05:55:51.083278 ==
4220 05:55:51.085358 Dram Type= 6, Freq= 0, CH_1, rank 0
4221 05:55:51.088791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4222 05:55:51.089259 ==
4223 05:55:51.095154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4224 05:55:51.101894 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4225 05:55:51.105288 [CA 0] Center 35 (5~66) winsize 62
4226 05:55:51.108992 [CA 1] Center 35 (5~66) winsize 62
4227 05:55:51.111896 [CA 2] Center 33 (3~64) winsize 62
4228 05:55:51.115173 [CA 3] Center 33 (3~64) winsize 62
4229 05:55:51.118688 [CA 4] Center 33 (2~64) winsize 63
4230 05:55:51.121620 [CA 5] Center 33 (2~64) winsize 63
4231 05:55:51.122080
4232 05:55:51.125411 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4233 05:55:51.125868
4234 05:55:51.128513 [CATrainingPosCal] consider 1 rank data
4235 05:55:51.131827 u2DelayCellTimex100 = 270/100 ps
4236 05:55:51.134972 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4237 05:55:51.138176 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4238 05:55:51.141422 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4239 05:55:51.145074 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4240 05:55:51.147991 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4241 05:55:51.151480 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4242 05:55:51.151933
4243 05:55:51.157939 CA PerBit enable=1, Macro0, CA PI delay=33
4244 05:55:51.158547
4245 05:55:51.161373 [CBTSetCACLKResult] CA Dly = 33
4246 05:55:51.161830 CS Dly: 4 (0~35)
4247 05:55:51.162193 ==
4248 05:55:51.164756 Dram Type= 6, Freq= 0, CH_1, rank 1
4249 05:55:51.168128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4250 05:55:51.168691 ==
4251 05:55:51.174664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4252 05:55:51.181570 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4253 05:55:51.184219 [CA 0] Center 35 (5~66) winsize 62
4254 05:55:51.187866 [CA 1] Center 34 (4~65) winsize 62
4255 05:55:51.191021 [CA 2] Center 33 (3~64) winsize 62
4256 05:55:51.194433 [CA 3] Center 33 (3~64) winsize 62
4257 05:55:51.197897 [CA 4] Center 32 (2~63) winsize 62
4258 05:55:51.200936 [CA 5] Center 32 (2~63) winsize 62
4259 05:55:51.201501
4260 05:55:51.204076 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4261 05:55:51.204585
4262 05:55:51.207723 [CATrainingPosCal] consider 2 rank data
4263 05:55:51.210805 u2DelayCellTimex100 = 270/100 ps
4264 05:55:51.214000 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4265 05:55:51.217444 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4266 05:55:51.220505 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4267 05:55:51.224103 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4268 05:55:51.230565 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4269 05:55:51.233637 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4270 05:55:51.234095
4271 05:55:51.237099 CA PerBit enable=1, Macro0, CA PI delay=32
4272 05:55:51.237585
4273 05:55:51.240656 [CBTSetCACLKResult] CA Dly = 32
4274 05:55:51.241263 CS Dly: 4 (0~36)
4275 05:55:51.241638
4276 05:55:51.244054 ----->DramcWriteLeveling(PI) begin...
4277 05:55:51.244624 ==
4278 05:55:51.247281 Dram Type= 6, Freq= 0, CH_1, rank 0
4279 05:55:51.254170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4280 05:55:51.254729 ==
4281 05:55:51.257028 Write leveling (Byte 0): 27 => 27
4282 05:55:51.260535 Write leveling (Byte 1): 28 => 28
4283 05:55:51.261164 DramcWriteLeveling(PI) end<-----
4284 05:55:51.261538
4285 05:55:51.263634 ==
4286 05:55:51.267638 Dram Type= 6, Freq= 0, CH_1, rank 0
4287 05:55:51.270792 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4288 05:55:51.271351 ==
4289 05:55:51.274168 [Gating] SW mode calibration
4290 05:55:51.280652 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4291 05:55:51.283787 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4292 05:55:51.290195 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4293 05:55:51.293642 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4294 05:55:51.296951 0 5 8 | B1->B0 | 2f2f 2a2a | 0 0 | (0 0) (0 0)
4295 05:55:51.303449 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4296 05:55:51.306846 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4297 05:55:51.310457 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4298 05:55:51.316685 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4299 05:55:51.320220 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4300 05:55:51.323357 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4301 05:55:51.329844 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4302 05:55:51.333131 0 6 8 | B1->B0 | 3636 3f3f | 0 0 | (0 0) (0 0)
4303 05:55:51.336553 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4304 05:55:51.343391 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4305 05:55:51.346302 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4306 05:55:51.350007 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4307 05:55:51.356247 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4308 05:55:51.359688 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4309 05:55:51.363248 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4310 05:55:51.369582 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4311 05:55:51.372836 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 05:55:51.376137 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 05:55:51.382940 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 05:55:51.386472 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 05:55:51.389434 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 05:55:51.396555 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 05:55:51.399247 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 05:55:51.402941 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 05:55:51.409392 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 05:55:51.412760 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 05:55:51.416210 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4322 05:55:51.422795 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4323 05:55:51.425754 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4324 05:55:51.429364 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4325 05:55:51.435789 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4326 05:55:51.439249 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4327 05:55:51.442420 Total UI for P1: 0, mck2ui 16
4328 05:55:51.445807 best dqsien dly found for B0: ( 0, 9, 4)
4329 05:55:51.449122 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4330 05:55:51.452091 Total UI for P1: 0, mck2ui 16
4331 05:55:51.455480 best dqsien dly found for B1: ( 0, 9, 8)
4332 05:55:51.458936 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4333 05:55:51.462057 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4334 05:55:51.462519
4335 05:55:51.465640 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4336 05:55:51.472264 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4337 05:55:51.472861 [Gating] SW calibration Done
4338 05:55:51.473239 ==
4339 05:55:51.475452 Dram Type= 6, Freq= 0, CH_1, rank 0
4340 05:55:51.482231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4341 05:55:51.482778 ==
4342 05:55:51.483147 RX Vref Scan: 0
4343 05:55:51.483488
4344 05:55:51.485659 RX Vref 0 -> 0, step: 1
4345 05:55:51.486118
4346 05:55:51.488602 RX Delay -230 -> 252, step: 16
4347 05:55:51.492171 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4348 05:55:51.495644 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4349 05:55:51.499058 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4350 05:55:51.505438 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4351 05:55:51.508817 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4352 05:55:51.512454 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4353 05:55:51.515223 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4354 05:55:51.522049 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4355 05:55:51.525229 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4356 05:55:51.528748 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4357 05:55:51.531784 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4358 05:55:51.538436 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4359 05:55:51.542081 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4360 05:55:51.544743 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4361 05:55:51.548009 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4362 05:55:51.555205 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4363 05:55:51.555664 ==
4364 05:55:51.558099 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 05:55:51.561163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4366 05:55:51.561625 ==
4367 05:55:51.561988 DQS Delay:
4368 05:55:51.564353 DQS0 = 0, DQS1 = 0
4369 05:55:51.564841 DQM Delay:
4370 05:55:51.568397 DQM0 = 39, DQM1 = 33
4371 05:55:51.569006 DQ Delay:
4372 05:55:51.571815 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4373 05:55:51.574756 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4374 05:55:51.578207 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4375 05:55:51.581397 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4376 05:55:51.581954
4377 05:55:51.582329
4378 05:55:51.582665 ==
4379 05:55:51.584922 Dram Type= 6, Freq= 0, CH_1, rank 0
4380 05:55:51.588008 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4381 05:55:51.588495 ==
4382 05:55:51.588900
4383 05:55:51.591247
4384 05:55:51.591698 TX Vref Scan disable
4385 05:55:51.595021 == TX Byte 0 ==
4386 05:55:51.597812 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4387 05:55:51.601098 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4388 05:55:51.604692 == TX Byte 1 ==
4389 05:55:51.607683 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4390 05:55:51.610984 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4391 05:55:51.611444 ==
4392 05:55:51.614891 Dram Type= 6, Freq= 0, CH_1, rank 0
4393 05:55:51.621346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4394 05:55:51.621805 ==
4395 05:55:51.622166
4396 05:55:51.622500
4397 05:55:51.622818 TX Vref Scan disable
4398 05:55:51.625379 == TX Byte 0 ==
4399 05:55:51.628599 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4400 05:55:51.635310 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4401 05:55:51.635860 == TX Byte 1 ==
4402 05:55:51.638929 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4403 05:55:51.645384 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4404 05:55:51.645847
4405 05:55:51.646221 [DATLAT]
4406 05:55:51.646559 Freq=600, CH1 RK0
4407 05:55:51.646916
4408 05:55:51.648843 DATLAT Default: 0x9
4409 05:55:51.649299 0, 0xFFFF, sum = 0
4410 05:55:51.652212 1, 0xFFFF, sum = 0
4411 05:55:51.655856 2, 0xFFFF, sum = 0
4412 05:55:51.656425 3, 0xFFFF, sum = 0
4413 05:55:51.658755 4, 0xFFFF, sum = 0
4414 05:55:51.659218 5, 0xFFFF, sum = 0
4415 05:55:51.661847 6, 0xFFFF, sum = 0
4416 05:55:51.662311 7, 0x0, sum = 1
4417 05:55:51.662682 8, 0x0, sum = 2
4418 05:55:51.665542 9, 0x0, sum = 3
4419 05:55:51.666003 10, 0x0, sum = 4
4420 05:55:51.668479 best_step = 8
4421 05:55:51.668965
4422 05:55:51.669325 ==
4423 05:55:51.672874 Dram Type= 6, Freq= 0, CH_1, rank 0
4424 05:55:51.675348 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4425 05:55:51.675907 ==
4426 05:55:51.678396 RX Vref Scan: 1
4427 05:55:51.678854
4428 05:55:51.679211 RX Vref 0 -> 0, step: 1
4429 05:55:51.679545
4430 05:55:51.681659 RX Delay -195 -> 252, step: 8
4431 05:55:51.682160
4432 05:55:51.684776 Set Vref, RX VrefLevel [Byte0]: 55
4433 05:55:51.688587 [Byte1]: 49
4434 05:55:51.692900
4435 05:55:51.693461 Final RX Vref Byte 0 = 55 to rank0
4436 05:55:51.695777 Final RX Vref Byte 1 = 49 to rank0
4437 05:55:51.699154 Final RX Vref Byte 0 = 55 to rank1
4438 05:55:51.702812 Final RX Vref Byte 1 = 49 to rank1==
4439 05:55:51.705705 Dram Type= 6, Freq= 0, CH_1, rank 0
4440 05:55:51.712294 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4441 05:55:51.712788 ==
4442 05:55:51.713368 DQS Delay:
4443 05:55:51.715769 DQS0 = 0, DQS1 = 0
4444 05:55:51.716400 DQM Delay:
4445 05:55:51.716827 DQM0 = 38, DQM1 = 31
4446 05:55:51.719064 DQ Delay:
4447 05:55:51.722575 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4448 05:55:51.725625 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4449 05:55:51.728887 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4450 05:55:51.732285 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4451 05:55:51.732782
4452 05:55:51.733156
4453 05:55:51.739136 [DQSOSCAuto] RK0, (LSB)MR18= 0x7878, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4454 05:55:51.741812 CH1 RK0: MR19=808, MR18=7878
4455 05:55:51.748924 CH1_RK0: MR19=0x808, MR18=0x7878, DQSOSC=387, MR23=63, INC=175, DEC=116
4456 05:55:51.749383
4457 05:55:51.752242 ----->DramcWriteLeveling(PI) begin...
4458 05:55:51.752703 ==
4459 05:55:51.755644 Dram Type= 6, Freq= 0, CH_1, rank 1
4460 05:55:51.758911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4461 05:55:51.759377 ==
4462 05:55:51.761873 Write leveling (Byte 0): 28 => 28
4463 05:55:51.765312 Write leveling (Byte 1): 28 => 28
4464 05:55:51.769319 DramcWriteLeveling(PI) end<-----
4465 05:55:51.769933
4466 05:55:51.770311 ==
4467 05:55:51.772455 Dram Type= 6, Freq= 0, CH_1, rank 1
4468 05:55:51.775498 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4469 05:55:51.776075 ==
4470 05:55:51.778746 [Gating] SW mode calibration
4471 05:55:51.785655 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4472 05:55:51.792009 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4473 05:55:51.795105 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 05:55:51.801522 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4475 05:55:51.805069 0 5 8 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4476 05:55:51.808514 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 05:55:51.815099 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 05:55:51.818617 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 05:55:51.821410 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 05:55:51.827993 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 05:55:51.831297 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 05:55:51.834766 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
4483 05:55:51.841307 0 6 8 | B1->B0 | 3434 4040 | 1 1 | (0 0) (0 0)
4484 05:55:51.845015 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
4485 05:55:51.847863 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 05:55:51.855145 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 05:55:51.857997 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 05:55:51.861638 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 05:55:51.868014 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 05:55:51.871895 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4491 05:55:51.874842 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 05:55:51.878150 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 05:55:51.884814 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 05:55:51.888151 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 05:55:51.891409 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 05:55:51.898037 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 05:55:51.901483 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 05:55:51.904632 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 05:55:51.911282 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 05:55:51.914385 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 05:55:51.917939 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 05:55:51.924235 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 05:55:51.927735 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 05:55:51.931042 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 05:55:51.937426 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 05:55:51.940800 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4507 05:55:51.944136 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 05:55:51.947641 Total UI for P1: 0, mck2ui 16
4509 05:55:51.950521 best dqsien dly found for B0: ( 0, 9, 4)
4510 05:55:51.954097 Total UI for P1: 0, mck2ui 16
4511 05:55:51.957252 best dqsien dly found for B1: ( 0, 9, 6)
4512 05:55:51.960787 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4513 05:55:51.963673 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4514 05:55:51.964135
4515 05:55:51.970438 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4516 05:55:51.973580 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4517 05:55:51.976940 [Gating] SW calibration Done
4518 05:55:51.977399 ==
4519 05:55:51.980616 Dram Type= 6, Freq= 0, CH_1, rank 1
4520 05:55:51.983909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4521 05:55:51.984372 ==
4522 05:55:51.984780 RX Vref Scan: 0
4523 05:55:51.985136
4524 05:55:51.987249 RX Vref 0 -> 0, step: 1
4525 05:55:51.987705
4526 05:55:51.990318 RX Delay -230 -> 252, step: 16
4527 05:55:51.993705 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4528 05:55:52.000700 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4529 05:55:52.003774 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4530 05:55:52.006706 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4531 05:55:52.010277 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4532 05:55:52.013384 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4533 05:55:52.020243 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4534 05:55:52.023819 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4535 05:55:52.026598 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4536 05:55:52.029820 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4537 05:55:52.036846 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4538 05:55:52.040135 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4539 05:55:52.043115 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4540 05:55:52.046838 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4541 05:55:52.053024 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4542 05:55:52.056467 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4543 05:55:52.057035 ==
4544 05:55:52.059540 Dram Type= 6, Freq= 0, CH_1, rank 1
4545 05:55:52.062884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4546 05:55:52.063362 ==
4547 05:55:52.066457 DQS Delay:
4548 05:55:52.066913 DQS0 = 0, DQS1 = 0
4549 05:55:52.067272 DQM Delay:
4550 05:55:52.069825 DQM0 = 41, DQM1 = 35
4551 05:55:52.070283 DQ Delay:
4552 05:55:52.072904 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4553 05:55:52.076623 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4554 05:55:52.079630 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4555 05:55:52.082699 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4556 05:55:52.083156
4557 05:55:52.083511
4558 05:55:52.083843 ==
4559 05:55:52.086098 Dram Type= 6, Freq= 0, CH_1, rank 1
4560 05:55:52.092552 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4561 05:55:52.093178 ==
4562 05:55:52.093547
4563 05:55:52.093879
4564 05:55:52.094198 TX Vref Scan disable
4565 05:55:52.096294 == TX Byte 0 ==
4566 05:55:52.099787 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4567 05:55:52.106480 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4568 05:55:52.107028 == TX Byte 1 ==
4569 05:55:52.109572 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4570 05:55:52.116629 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4571 05:55:52.117240 ==
4572 05:55:52.120154 Dram Type= 6, Freq= 0, CH_1, rank 1
4573 05:55:52.122921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4574 05:55:52.123383 ==
4575 05:55:52.123742
4576 05:55:52.124075
4577 05:55:52.125973 TX Vref Scan disable
4578 05:55:52.129275 == TX Byte 0 ==
4579 05:55:52.132822 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4580 05:55:52.136035 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4581 05:55:52.139504 == TX Byte 1 ==
4582 05:55:52.142599 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4583 05:55:52.145995 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4584 05:55:52.146559
4585 05:55:52.146931 [DATLAT]
4586 05:55:52.149144 Freq=600, CH1 RK1
4587 05:55:52.149607
4588 05:55:52.152681 DATLAT Default: 0x8
4589 05:55:52.153188 0, 0xFFFF, sum = 0
4590 05:55:52.155715 1, 0xFFFF, sum = 0
4591 05:55:52.156271 2, 0xFFFF, sum = 0
4592 05:55:52.159342 3, 0xFFFF, sum = 0
4593 05:55:52.159809 4, 0xFFFF, sum = 0
4594 05:55:52.162681 5, 0xFFFF, sum = 0
4595 05:55:52.163151 6, 0xFFFF, sum = 0
4596 05:55:52.165649 7, 0x0, sum = 1
4597 05:55:52.166115 8, 0x0, sum = 2
4598 05:55:52.166485 9, 0x0, sum = 3
4599 05:55:52.169225 10, 0x0, sum = 4
4600 05:55:52.169686 best_step = 8
4601 05:55:52.170048
4602 05:55:52.170383 ==
4603 05:55:52.172306 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 05:55:52.179090 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4605 05:55:52.179643 ==
4606 05:55:52.180007 RX Vref Scan: 0
4607 05:55:52.180345
4608 05:55:52.182424 RX Vref 0 -> 0, step: 1
4609 05:55:52.182889
4610 05:55:52.186719 RX Delay -195 -> 252, step: 8
4611 05:55:52.192365 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4612 05:55:52.195608 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4613 05:55:52.199304 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4614 05:55:52.202765 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4615 05:55:52.205484 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4616 05:55:52.212652 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4617 05:55:52.215710 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4618 05:55:52.218895 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4619 05:55:52.222008 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4620 05:55:52.228644 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4621 05:55:52.232034 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4622 05:55:52.235451 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4623 05:55:52.238788 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4624 05:55:52.245001 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4625 05:55:52.248574 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4626 05:55:52.251716 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4627 05:55:52.252295 ==
4628 05:55:52.255435 Dram Type= 6, Freq= 0, CH_1, rank 1
4629 05:55:52.258635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4630 05:55:52.259101 ==
4631 05:55:52.261901 DQS Delay:
4632 05:55:52.262358 DQS0 = 0, DQS1 = 0
4633 05:55:52.265126 DQM Delay:
4634 05:55:52.265585 DQM0 = 37, DQM1 = 29
4635 05:55:52.265948 DQ Delay:
4636 05:55:52.268498 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4637 05:55:52.272057 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4638 05:55:52.275626 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4639 05:55:52.278539 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4640 05:55:52.279099
4641 05:55:52.279467
4642 05:55:52.288634 [DQSOSCAuto] RK1, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4643 05:55:52.291696 CH1 RK1: MR19=808, MR18=5454
4644 05:55:52.298413 CH1_RK1: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113
4645 05:55:52.298976 [RxdqsGatingPostProcess] freq 600
4646 05:55:52.304770 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4647 05:55:52.307983 Pre-setting of DQS Precalculation
4648 05:55:52.311560 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4649 05:55:52.321266 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4650 05:55:52.327820 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4651 05:55:52.328284
4652 05:55:52.328642
4653 05:55:52.331549 [Calibration Summary] 1200 Mbps
4654 05:55:52.332112 CH 0, Rank 0
4655 05:55:52.334570 SW Impedance : PASS
4656 05:55:52.337553 DUTY Scan : NO K
4657 05:55:52.338009 ZQ Calibration : PASS
4658 05:55:52.341486 Jitter Meter : NO K
4659 05:55:52.341966 CBT Training : PASS
4660 05:55:52.344401 Write leveling : PASS
4661 05:55:52.347677 RX DQS gating : PASS
4662 05:55:52.348145 RX DQ/DQS(RDDQC) : PASS
4663 05:55:52.351108 TX DQ/DQS : PASS
4664 05:55:52.354848 RX DATLAT : PASS
4665 05:55:52.355400 RX DQ/DQS(Engine): PASS
4666 05:55:52.358147 TX OE : NO K
4667 05:55:52.358704 All Pass.
4668 05:55:52.359065
4669 05:55:52.361241 CH 0, Rank 1
4670 05:55:52.361692 SW Impedance : PASS
4671 05:55:52.364363 DUTY Scan : NO K
4672 05:55:52.367388 ZQ Calibration : PASS
4673 05:55:52.367856 Jitter Meter : NO K
4674 05:55:52.371091 CBT Training : PASS
4675 05:55:52.374199 Write leveling : PASS
4676 05:55:52.374656 RX DQS gating : PASS
4677 05:55:52.378059 RX DQ/DQS(RDDQC) : PASS
4678 05:55:52.380828 TX DQ/DQS : PASS
4679 05:55:52.381283 RX DATLAT : PASS
4680 05:55:52.384351 RX DQ/DQS(Engine): PASS
4681 05:55:52.387512 TX OE : NO K
4682 05:55:52.387968 All Pass.
4683 05:55:52.388323
4684 05:55:52.388649 CH 1, Rank 0
4685 05:55:52.390714 SW Impedance : PASS
4686 05:55:52.394154 DUTY Scan : NO K
4687 05:55:52.394608 ZQ Calibration : PASS
4688 05:55:52.397220 Jitter Meter : NO K
4689 05:55:52.397673 CBT Training : PASS
4690 05:55:52.400517 Write leveling : PASS
4691 05:55:52.403813 RX DQS gating : PASS
4692 05:55:52.404364 RX DQ/DQS(RDDQC) : PASS
4693 05:55:52.407338 TX DQ/DQS : PASS
4694 05:55:52.410974 RX DATLAT : PASS
4695 05:55:52.411536 RX DQ/DQS(Engine): PASS
4696 05:55:52.413951 TX OE : NO K
4697 05:55:52.414526 All Pass.
4698 05:55:52.414894
4699 05:55:52.417372 CH 1, Rank 1
4700 05:55:52.417958 SW Impedance : PASS
4701 05:55:52.420983 DUTY Scan : NO K
4702 05:55:52.423675 ZQ Calibration : PASS
4703 05:55:52.424129 Jitter Meter : NO K
4704 05:55:52.427082 CBT Training : PASS
4705 05:55:52.430372 Write leveling : PASS
4706 05:55:52.430915 RX DQS gating : PASS
4707 05:55:52.433535 RX DQ/DQS(RDDQC) : PASS
4708 05:55:52.437001 TX DQ/DQS : PASS
4709 05:55:52.437598 RX DATLAT : PASS
4710 05:55:52.440243 RX DQ/DQS(Engine): PASS
4711 05:55:52.443469 TX OE : NO K
4712 05:55:52.443925 All Pass.
4713 05:55:52.444283
4714 05:55:52.446767 DramC Write-DBI off
4715 05:55:52.447219 PER_BANK_REFRESH: Hybrid Mode
4716 05:55:52.450032 TX_TRACKING: ON
4717 05:55:52.456701 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4718 05:55:52.463411 [FAST_K] Save calibration result to emmc
4719 05:55:52.467093 dramc_set_vcore_voltage set vcore to 662500
4720 05:55:52.467715 Read voltage for 933, 3
4721 05:55:52.469781 Vio18 = 0
4722 05:55:52.470233 Vcore = 662500
4723 05:55:52.470590 Vdram = 0
4724 05:55:52.473520 Vddq = 0
4725 05:55:52.474075 Vmddr = 0
4726 05:55:52.476936 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4727 05:55:52.482872 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4728 05:55:52.486525 MEM_TYPE=3, freq_sel=17
4729 05:55:52.489462 sv_algorithm_assistance_LP4_1600
4730 05:55:52.492838 ============ PULL DRAM RESETB DOWN ============
4731 05:55:52.496622 ========== PULL DRAM RESETB DOWN end =========
4732 05:55:52.503160 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4733 05:55:52.506070 ===================================
4734 05:55:52.506536 LPDDR4 DRAM CONFIGURATION
4735 05:55:52.510064 ===================================
4736 05:55:52.513279 EX_ROW_EN[0] = 0x0
4737 05:55:52.513834 EX_ROW_EN[1] = 0x0
4738 05:55:52.516031 LP4Y_EN = 0x0
4739 05:55:52.516587 WORK_FSP = 0x0
4740 05:55:52.519684 WL = 0x3
4741 05:55:52.522977 RL = 0x3
4742 05:55:52.523438 BL = 0x2
4743 05:55:52.526168 RPST = 0x0
4744 05:55:52.526682 RD_PRE = 0x0
4745 05:55:52.529637 WR_PRE = 0x1
4746 05:55:52.530097 WR_PST = 0x0
4747 05:55:52.532475 DBI_WR = 0x0
4748 05:55:52.532982 DBI_RD = 0x0
4749 05:55:52.535894 OTF = 0x1
4750 05:55:52.539370 ===================================
4751 05:55:52.542887 ===================================
4752 05:55:52.543587 ANA top config
4753 05:55:52.545957 ===================================
4754 05:55:52.548949 DLL_ASYNC_EN = 0
4755 05:55:52.552351 ALL_SLAVE_EN = 1
4756 05:55:52.552970 NEW_RANK_MODE = 1
4757 05:55:52.555678 DLL_IDLE_MODE = 1
4758 05:55:52.559165 LP45_APHY_COMB_EN = 1
4759 05:55:52.562471 TX_ODT_DIS = 1
4760 05:55:52.565439 NEW_8X_MODE = 1
4761 05:55:52.569187 ===================================
4762 05:55:52.572408 ===================================
4763 05:55:52.572915 data_rate = 1866
4764 05:55:52.575506 CKR = 1
4765 05:55:52.579128 DQ_P2S_RATIO = 8
4766 05:55:52.582485 ===================================
4767 05:55:52.585529 CA_P2S_RATIO = 8
4768 05:55:52.588853 DQ_CA_OPEN = 0
4769 05:55:52.592042 DQ_SEMI_OPEN = 0
4770 05:55:52.592500 CA_SEMI_OPEN = 0
4771 05:55:52.595458 CA_FULL_RATE = 0
4772 05:55:52.598844 DQ_CKDIV4_EN = 1
4773 05:55:52.601795 CA_CKDIV4_EN = 1
4774 05:55:52.605015 CA_PREDIV_EN = 0
4775 05:55:52.608330 PH8_DLY = 0
4776 05:55:52.611840 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4777 05:55:52.612392 DQ_AAMCK_DIV = 4
4778 05:55:52.615284 CA_AAMCK_DIV = 4
4779 05:55:52.618799 CA_ADMCK_DIV = 4
4780 05:55:52.621710 DQ_TRACK_CA_EN = 0
4781 05:55:52.625013 CA_PICK = 933
4782 05:55:52.628171 CA_MCKIO = 933
4783 05:55:52.628633 MCKIO_SEMI = 0
4784 05:55:52.631925 PLL_FREQ = 3732
4785 05:55:52.635172 DQ_UI_PI_RATIO = 32
4786 05:55:52.637851 CA_UI_PI_RATIO = 0
4787 05:55:52.641479 ===================================
4788 05:55:52.644537 ===================================
4789 05:55:52.647916 memory_type:LPDDR4
4790 05:55:52.648464 GP_NUM : 10
4791 05:55:52.651207 SRAM_EN : 1
4792 05:55:52.654495 MD32_EN : 0
4793 05:55:52.658262 ===================================
4794 05:55:52.658716 [ANA_INIT] >>>>>>>>>>>>>>
4795 05:55:52.661286 <<<<<< [CONFIGURE PHASE]: ANA_TX
4796 05:55:52.664539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4797 05:55:52.667829 ===================================
4798 05:55:52.671596 data_rate = 1866,PCW = 0X8f00
4799 05:55:52.674512 ===================================
4800 05:55:52.677912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4801 05:55:52.684576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4802 05:55:52.688349 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4803 05:55:52.694551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4804 05:55:52.697862 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4805 05:55:52.700766 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4806 05:55:52.703997 [ANA_INIT] flow start
4807 05:55:52.704449 [ANA_INIT] PLL >>>>>>>>
4808 05:55:52.707674 [ANA_INIT] PLL <<<<<<<<
4809 05:55:52.711555 [ANA_INIT] MIDPI >>>>>>>>
4810 05:55:52.712366 [ANA_INIT] MIDPI <<<<<<<<
4811 05:55:52.714558 [ANA_INIT] DLL >>>>>>>>
4812 05:55:52.717305 [ANA_INIT] flow end
4813 05:55:52.721108 ============ LP4 DIFF to SE enter ============
4814 05:55:52.724488 ============ LP4 DIFF to SE exit ============
4815 05:55:52.727518 [ANA_INIT] <<<<<<<<<<<<<
4816 05:55:52.730644 [Flow] Enable top DCM control >>>>>
4817 05:55:52.734095 [Flow] Enable top DCM control <<<<<
4818 05:55:52.737336 Enable DLL master slave shuffle
4819 05:55:52.740531 ==============================================================
4820 05:55:52.743588 Gating Mode config
4821 05:55:52.750688 ==============================================================
4822 05:55:52.751152 Config description:
4823 05:55:52.760695 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4824 05:55:52.767016 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4825 05:55:52.773593 SELPH_MODE 0: By rank 1: By Phase
4826 05:55:52.776888 ==============================================================
4827 05:55:52.780373 GAT_TRACK_EN = 1
4828 05:55:52.783775 RX_GATING_MODE = 2
4829 05:55:52.787020 RX_GATING_TRACK_MODE = 2
4830 05:55:52.789864 SELPH_MODE = 1
4831 05:55:52.793571 PICG_EARLY_EN = 1
4832 05:55:52.796561 VALID_LAT_VALUE = 1
4833 05:55:52.799988 ==============================================================
4834 05:55:52.803033 Enter into Gating configuration >>>>
4835 05:55:52.806460 Exit from Gating configuration <<<<
4836 05:55:52.810083 Enter into DVFS_PRE_config >>>>>
4837 05:55:52.823121 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4838 05:55:52.826219 Exit from DVFS_PRE_config <<<<<
4839 05:55:52.829975 Enter into PICG configuration >>>>
4840 05:55:52.833211 Exit from PICG configuration <<<<
4841 05:55:52.833673 [RX_INPUT] configuration >>>>>
4842 05:55:52.836599 [RX_INPUT] configuration <<<<<
4843 05:55:52.843065 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4844 05:55:52.846410 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4845 05:55:52.852567 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4846 05:55:52.859644 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4847 05:55:52.865673 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4848 05:55:52.872634 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4849 05:55:52.876067 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4850 05:55:52.879244 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4851 05:55:52.885838 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4852 05:55:52.889135 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4853 05:55:52.892743 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4854 05:55:52.899193 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4855 05:55:52.902359 ===================================
4856 05:55:52.902878 LPDDR4 DRAM CONFIGURATION
4857 05:55:52.905496 ===================================
4858 05:55:52.909293 EX_ROW_EN[0] = 0x0
4859 05:55:52.909832 EX_ROW_EN[1] = 0x0
4860 05:55:52.912862 LP4Y_EN = 0x0
4861 05:55:52.913415 WORK_FSP = 0x0
4862 05:55:52.915752 WL = 0x3
4863 05:55:52.916305 RL = 0x3
4864 05:55:52.918840 BL = 0x2
4865 05:55:52.922049 RPST = 0x0
4866 05:55:52.922511 RD_PRE = 0x0
4867 05:55:52.925745 WR_PRE = 0x1
4868 05:55:52.926298 WR_PST = 0x0
4869 05:55:52.928685 DBI_WR = 0x0
4870 05:55:52.929177 DBI_RD = 0x0
4871 05:55:52.932103 OTF = 0x1
4872 05:55:52.935012 ===================================
4873 05:55:52.938585 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4874 05:55:52.941806 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4875 05:55:52.948175 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4876 05:55:52.951606 ===================================
4877 05:55:52.952196 LPDDR4 DRAM CONFIGURATION
4878 05:55:52.955054 ===================================
4879 05:55:52.958062 EX_ROW_EN[0] = 0x10
4880 05:55:52.958519 EX_ROW_EN[1] = 0x0
4881 05:55:52.961627 LP4Y_EN = 0x0
4882 05:55:52.962102 WORK_FSP = 0x0
4883 05:55:52.964790 WL = 0x3
4884 05:55:52.965253 RL = 0x3
4885 05:55:52.968690 BL = 0x2
4886 05:55:52.971383 RPST = 0x0
4887 05:55:52.971843 RD_PRE = 0x0
4888 05:55:52.974955 WR_PRE = 0x1
4889 05:55:52.975416 WR_PST = 0x0
4890 05:55:52.978162 DBI_WR = 0x0
4891 05:55:52.978624 DBI_RD = 0x0
4892 05:55:52.981366 OTF = 0x1
4893 05:55:52.984808 ===================================
4894 05:55:52.988066 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4895 05:55:52.994433 nWR fixed to 30
4896 05:55:52.996914 [ModeRegInit_LP4] CH0 RK0
4897 05:55:52.997378 [ModeRegInit_LP4] CH0 RK1
4898 05:55:53.000285 [ModeRegInit_LP4] CH1 RK0
4899 05:55:53.003606 [ModeRegInit_LP4] CH1 RK1
4900 05:55:53.004200 match AC timing 8
4901 05:55:53.010362 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4902 05:55:53.014104 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4903 05:55:53.016971 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4904 05:55:53.023468 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4905 05:55:53.027135 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4906 05:55:53.027695 ==
4907 05:55:53.030107 Dram Type= 6, Freq= 0, CH_0, rank 0
4908 05:55:53.033063 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4909 05:55:53.033527 ==
4910 05:55:53.040076 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4911 05:55:53.046427 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4912 05:55:53.049724 [CA 0] Center 38 (8~69) winsize 62
4913 05:55:53.052947 [CA 1] Center 38 (8~69) winsize 62
4914 05:55:53.056412 [CA 2] Center 36 (5~67) winsize 63
4915 05:55:53.059800 [CA 3] Center 36 (5~67) winsize 63
4916 05:55:53.062915 [CA 4] Center 34 (4~65) winsize 62
4917 05:55:53.066399 [CA 5] Center 34 (4~65) winsize 62
4918 05:55:53.066860
4919 05:55:53.069895 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4920 05:55:53.070357
4921 05:55:53.072870 [CATrainingPosCal] consider 1 rank data
4922 05:55:53.076809 u2DelayCellTimex100 = 270/100 ps
4923 05:55:53.079640 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4924 05:55:53.082799 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4925 05:55:53.086363 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4926 05:55:53.089509 CA3 delay=36 (5~67),Diff = 2 PI (12 cell)
4927 05:55:53.096349 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4928 05:55:53.099445 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4929 05:55:53.099934
4930 05:55:53.102900 CA PerBit enable=1, Macro0, CA PI delay=34
4931 05:55:53.103384
4932 05:55:53.106228 [CBTSetCACLKResult] CA Dly = 34
4933 05:55:53.106690 CS Dly: 7 (0~38)
4934 05:55:53.107054 ==
4935 05:55:53.109655 Dram Type= 6, Freq= 0, CH_0, rank 1
4936 05:55:53.115952 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4937 05:55:53.116488 ==
4938 05:55:53.119385 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4939 05:55:53.126114 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4940 05:55:53.129418 [CA 0] Center 38 (8~69) winsize 62
4941 05:55:53.132284 [CA 1] Center 38 (8~69) winsize 62
4942 05:55:53.135650 [CA 2] Center 36 (6~67) winsize 62
4943 05:55:53.139054 [CA 3] Center 35 (5~66) winsize 62
4944 05:55:53.142531 [CA 4] Center 34 (4~65) winsize 62
4945 05:55:53.145466 [CA 5] Center 34 (4~65) winsize 62
4946 05:55:53.146079
4947 05:55:53.148794 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4948 05:55:53.149471
4949 05:55:53.152013 [CATrainingPosCal] consider 2 rank data
4950 05:55:53.155716 u2DelayCellTimex100 = 270/100 ps
4951 05:55:53.158917 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4952 05:55:53.162393 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4953 05:55:53.168789 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4954 05:55:53.172225 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4955 05:55:53.175381 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4956 05:55:53.178708 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4957 05:55:53.179173
4958 05:55:53.182317 CA PerBit enable=1, Macro0, CA PI delay=34
4959 05:55:53.182992
4960 05:55:53.185535 [CBTSetCACLKResult] CA Dly = 34
4961 05:55:53.185995 CS Dly: 7 (0~38)
4962 05:55:53.186366
4963 05:55:53.191669 ----->DramcWriteLeveling(PI) begin...
4964 05:55:53.192138 ==
4965 05:55:53.195092 Dram Type= 6, Freq= 0, CH_0, rank 0
4966 05:55:53.198533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4967 05:55:53.199093 ==
4968 05:55:53.201519 Write leveling (Byte 0): 31 => 31
4969 05:55:53.204850 Write leveling (Byte 1): 27 => 27
4970 05:55:53.208312 DramcWriteLeveling(PI) end<-----
4971 05:55:53.208827
4972 05:55:53.209285 ==
4973 05:55:53.211942 Dram Type= 6, Freq= 0, CH_0, rank 0
4974 05:55:53.215054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4975 05:55:53.215519 ==
4976 05:55:53.218244 [Gating] SW mode calibration
4977 05:55:53.224762 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4978 05:55:53.231597 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4979 05:55:53.234757 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4980 05:55:53.237869 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4981 05:55:53.244753 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4982 05:55:53.247973 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4983 05:55:53.251313 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4984 05:55:53.257898 0 10 20 | B1->B0 | 3434 3333 | 1 1 | (1 0) (0 0)
4985 05:55:53.261188 0 10 24 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
4986 05:55:53.264386 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4987 05:55:53.271403 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4988 05:55:53.274712 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4989 05:55:53.277672 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4990 05:55:53.284307 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4991 05:55:53.287557 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4992 05:55:53.291029 0 11 20 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (0 0)
4993 05:55:53.297553 0 11 24 | B1->B0 | 3939 4545 | 1 0 | (0 0) (0 0)
4994 05:55:53.301065 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4995 05:55:53.304621 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4996 05:55:53.310694 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4997 05:55:53.314338 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4998 05:55:53.317593 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4999 05:55:53.324231 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5000 05:55:53.328013 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5001 05:55:53.330875 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5002 05:55:53.337458 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 05:55:53.340769 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 05:55:53.344222 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 05:55:53.350750 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 05:55:53.353834 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 05:55:53.357434 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 05:55:53.360617 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 05:55:53.367442 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 05:55:53.370099 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5011 05:55:53.376915 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5012 05:55:53.380882 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5013 05:55:53.383597 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5014 05:55:53.390718 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5015 05:55:53.393444 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5016 05:55:53.396484 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5017 05:55:53.403431 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5018 05:55:53.404012 Total UI for P1: 0, mck2ui 16
5019 05:55:53.406804 best dqsien dly found for B0: ( 0, 14, 20)
5020 05:55:53.409890 Total UI for P1: 0, mck2ui 16
5021 05:55:53.413275 best dqsien dly found for B1: ( 0, 14, 20)
5022 05:55:53.419632 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5023 05:55:53.423183 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5024 05:55:53.423601
5025 05:55:53.426476 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5026 05:55:53.429511 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5027 05:55:53.433312 [Gating] SW calibration Done
5028 05:55:53.433838 ==
5029 05:55:53.436865 Dram Type= 6, Freq= 0, CH_0, rank 0
5030 05:55:53.439827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5031 05:55:53.440246 ==
5032 05:55:53.443592 RX Vref Scan: 0
5033 05:55:53.444128
5034 05:55:53.444465 RX Vref 0 -> 0, step: 1
5035 05:55:53.444813
5036 05:55:53.446510 RX Delay -80 -> 252, step: 8
5037 05:55:53.449487 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5038 05:55:53.455958 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5039 05:55:53.459275 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5040 05:55:53.463021 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5041 05:55:53.466669 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5042 05:55:53.469376 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5043 05:55:53.472609 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5044 05:55:53.479442 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5045 05:55:53.482923 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5046 05:55:53.486196 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5047 05:55:53.488977 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5048 05:55:53.492240 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5049 05:55:53.499063 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5050 05:55:53.502380 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5051 05:55:53.506222 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5052 05:55:53.509249 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5053 05:55:53.509714 ==
5054 05:55:53.512524 Dram Type= 6, Freq= 0, CH_0, rank 0
5055 05:55:53.515789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5056 05:55:53.516345 ==
5057 05:55:53.519144 DQS Delay:
5058 05:55:53.519693 DQS0 = 0, DQS1 = 0
5059 05:55:53.522415 DQM Delay:
5060 05:55:53.522981 DQM0 = 98, DQM1 = 89
5061 05:55:53.525413 DQ Delay:
5062 05:55:53.525870 DQ0 =95, DQ1 =95, DQ2 =99, DQ3 =91
5063 05:55:53.529116 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5064 05:55:53.532452 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
5065 05:55:53.535628 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5066 05:55:53.538840
5067 05:55:53.539312
5068 05:55:53.539674 ==
5069 05:55:53.542069 Dram Type= 6, Freq= 0, CH_0, rank 0
5070 05:55:53.545629 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5071 05:55:53.546184 ==
5072 05:55:53.546555
5073 05:55:53.546897
5074 05:55:53.548528 TX Vref Scan disable
5075 05:55:53.549211 == TX Byte 0 ==
5076 05:55:53.555425 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5077 05:55:53.558443 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5078 05:55:53.559001 == TX Byte 1 ==
5079 05:55:53.565421 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5080 05:55:53.568452 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5081 05:55:53.569074 ==
5082 05:55:53.571507 Dram Type= 6, Freq= 0, CH_0, rank 0
5083 05:55:53.575309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5084 05:55:53.575869 ==
5085 05:55:53.576241
5086 05:55:53.578332
5087 05:55:53.578792 TX Vref Scan disable
5088 05:55:53.581865 == TX Byte 0 ==
5089 05:55:53.585307 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5090 05:55:53.588166 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5091 05:55:53.591646 == TX Byte 1 ==
5092 05:55:53.595151 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5093 05:55:53.601375 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5094 05:55:53.601837
5095 05:55:53.602199 [DATLAT]
5096 05:55:53.602540 Freq=933, CH0 RK0
5097 05:55:53.602870
5098 05:55:53.604970 DATLAT Default: 0xd
5099 05:55:53.605528 0, 0xFFFF, sum = 0
5100 05:55:53.607820 1, 0xFFFF, sum = 0
5101 05:55:53.611171 2, 0xFFFF, sum = 0
5102 05:55:53.611738 3, 0xFFFF, sum = 0
5103 05:55:53.614753 4, 0xFFFF, sum = 0
5104 05:55:53.615221 5, 0xFFFF, sum = 0
5105 05:55:53.617687 6, 0xFFFF, sum = 0
5106 05:55:53.618155 7, 0xFFFF, sum = 0
5107 05:55:53.621140 8, 0xFFFF, sum = 0
5108 05:55:53.621623 9, 0xFFFF, sum = 0
5109 05:55:53.624498 10, 0x0, sum = 1
5110 05:55:53.625121 11, 0x0, sum = 2
5111 05:55:53.628108 12, 0x0, sum = 3
5112 05:55:53.628585 13, 0x0, sum = 4
5113 05:55:53.629066 best_step = 11
5114 05:55:53.629418
5115 05:55:53.631056 ==
5116 05:55:53.634370 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 05:55:53.637606 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5118 05:55:53.638070 ==
5119 05:55:53.638437 RX Vref Scan: 1
5120 05:55:53.638775
5121 05:55:53.640769 RX Vref 0 -> 0, step: 1
5122 05:55:53.641234
5123 05:55:53.644422 RX Delay -61 -> 252, step: 4
5124 05:55:53.645211
5125 05:55:53.647454 Set Vref, RX VrefLevel [Byte0]: 52
5126 05:55:53.650947 [Byte1]: 48
5127 05:55:53.651414
5128 05:55:53.654156 Final RX Vref Byte 0 = 52 to rank0
5129 05:55:53.657622 Final RX Vref Byte 1 = 48 to rank0
5130 05:55:53.660443 Final RX Vref Byte 0 = 52 to rank1
5131 05:55:53.664178 Final RX Vref Byte 1 = 48 to rank1==
5132 05:55:53.667634 Dram Type= 6, Freq= 0, CH_0, rank 0
5133 05:55:53.674220 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5134 05:55:53.674685 ==
5135 05:55:53.675051 DQS Delay:
5136 05:55:53.675389 DQS0 = 0, DQS1 = 0
5137 05:55:53.677024 DQM Delay:
5138 05:55:53.677528 DQM0 = 96, DQM1 = 86
5139 05:55:53.680046 DQ Delay:
5140 05:55:53.683684 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5141 05:55:53.686983 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =102
5142 05:55:53.690534 DQ8 =78, DQ9 =70, DQ10 =84, DQ11 =78
5143 05:55:53.693678 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5144 05:55:53.694139
5145 05:55:53.694504
5146 05:55:53.700577 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 413 ps
5147 05:55:53.704051 CH0 RK0: MR19=505, MR18=1919
5148 05:55:53.710130 CH0_RK0: MR19=0x505, MR18=0x1919, DQSOSC=413, MR23=63, INC=63, DEC=42
5149 05:55:53.710671
5150 05:55:53.713663 ----->DramcWriteLeveling(PI) begin...
5151 05:55:53.714155 ==
5152 05:55:53.716799 Dram Type= 6, Freq= 0, CH_0, rank 1
5153 05:55:53.719913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5154 05:55:53.720477 ==
5155 05:55:53.723357 Write leveling (Byte 0): 31 => 31
5156 05:55:53.726557 Write leveling (Byte 1): 27 => 27
5157 05:55:53.729891 DramcWriteLeveling(PI) end<-----
5158 05:55:53.730350
5159 05:55:53.730794 ==
5160 05:55:53.733356 Dram Type= 6, Freq= 0, CH_0, rank 1
5161 05:55:53.736811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5162 05:55:53.739790 ==
5163 05:55:53.740265 [Gating] SW mode calibration
5164 05:55:53.746867 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5165 05:55:53.753096 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5166 05:55:53.756447 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 05:55:53.763047 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 05:55:53.766559 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 05:55:53.769866 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 05:55:53.776265 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5171 05:55:53.779683 0 10 20 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 0)
5172 05:55:53.783103 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5173 05:55:53.789711 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 05:55:53.792458 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 05:55:53.796040 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 05:55:53.802491 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 05:55:53.805989 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 05:55:53.809596 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 05:55:53.815928 0 11 20 | B1->B0 | 2e2e 3838 | 0 0 | (0 0) (0 0)
5180 05:55:53.819321 0 11 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5181 05:55:53.822530 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 05:55:53.829375 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 05:55:53.832622 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 05:55:53.835635 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 05:55:53.842253 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 05:55:53.845742 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 05:55:53.848733 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5188 05:55:53.855625 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 05:55:53.858908 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 05:55:53.862023 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 05:55:53.868636 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 05:55:53.872138 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 05:55:53.875595 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 05:55:53.881828 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 05:55:53.885006 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 05:55:53.888533 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 05:55:53.894741 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 05:55:53.898409 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 05:55:53.901606 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 05:55:53.908530 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 05:55:53.911824 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 05:55:53.914784 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 05:55:53.921749 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5204 05:55:53.924696 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5205 05:55:53.928275 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 05:55:53.931583 Total UI for P1: 0, mck2ui 16
5207 05:55:53.934800 best dqsien dly found for B0: ( 0, 14, 22)
5208 05:55:53.938346 Total UI for P1: 0, mck2ui 16
5209 05:55:53.941559 best dqsien dly found for B1: ( 0, 14, 22)
5210 05:55:53.945057 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5211 05:55:53.947562 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5212 05:55:53.948024
5213 05:55:53.954833 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5214 05:55:53.957757 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5215 05:55:53.960919 [Gating] SW calibration Done
5216 05:55:53.961380 ==
5217 05:55:53.964180 Dram Type= 6, Freq= 0, CH_0, rank 1
5218 05:55:53.967800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5219 05:55:53.968263 ==
5220 05:55:53.968628 RX Vref Scan: 0
5221 05:55:53.969030
5222 05:55:53.970785 RX Vref 0 -> 0, step: 1
5223 05:55:53.971265
5224 05:55:53.974356 RX Delay -80 -> 252, step: 8
5225 05:55:53.977617 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5226 05:55:53.981278 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5227 05:55:53.987754 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5228 05:55:53.991364 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5229 05:55:53.994400 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5230 05:55:53.997648 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5231 05:55:54.001039 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5232 05:55:54.004204 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5233 05:55:54.010645 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5234 05:55:54.014225 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5235 05:55:54.017372 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5236 05:55:54.020761 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5237 05:55:54.024254 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5238 05:55:54.031141 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5239 05:55:54.033789 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5240 05:55:54.037307 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5241 05:55:54.037934 ==
5242 05:55:54.040537 Dram Type= 6, Freq= 0, CH_0, rank 1
5243 05:55:54.043863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5244 05:55:54.044439 ==
5245 05:55:54.047113 DQS Delay:
5246 05:55:54.047575 DQS0 = 0, DQS1 = 0
5247 05:55:54.047939 DQM Delay:
5248 05:55:54.050563 DQM0 = 95, DQM1 = 86
5249 05:55:54.051044 DQ Delay:
5250 05:55:54.053740 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5251 05:55:54.057216 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5252 05:55:54.060118 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5253 05:55:54.063607 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5254 05:55:54.064063
5255 05:55:54.064425
5256 05:55:54.067175 ==
5257 05:55:54.067628 Dram Type= 6, Freq= 0, CH_0, rank 1
5258 05:55:54.073617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5259 05:55:54.074376 ==
5260 05:55:54.074768
5261 05:55:54.075106
5262 05:55:54.076943 TX Vref Scan disable
5263 05:55:54.077399 == TX Byte 0 ==
5264 05:55:54.080301 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5265 05:55:54.086923 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5266 05:55:54.087507 == TX Byte 1 ==
5267 05:55:54.093392 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5268 05:55:54.096626 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5269 05:55:54.097213 ==
5270 05:55:54.099879 Dram Type= 6, Freq= 0, CH_0, rank 1
5271 05:55:54.103183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5272 05:55:54.103741 ==
5273 05:55:54.104104
5274 05:55:54.104436
5275 05:55:54.106364 TX Vref Scan disable
5276 05:55:54.109748 == TX Byte 0 ==
5277 05:55:54.113438 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5278 05:55:54.116684 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5279 05:55:54.119433 == TX Byte 1 ==
5280 05:55:54.122892 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5281 05:55:54.126359 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5282 05:55:54.126821
5283 05:55:54.129335 [DATLAT]
5284 05:55:54.129792 Freq=933, CH0 RK1
5285 05:55:54.130157
5286 05:55:54.132663 DATLAT Default: 0xb
5287 05:55:54.133191 0, 0xFFFF, sum = 0
5288 05:55:54.135853 1, 0xFFFF, sum = 0
5289 05:55:54.136337 2, 0xFFFF, sum = 0
5290 05:55:54.139486 3, 0xFFFF, sum = 0
5291 05:55:54.139945 4, 0xFFFF, sum = 0
5292 05:55:54.142698 5, 0xFFFF, sum = 0
5293 05:55:54.143162 6, 0xFFFF, sum = 0
5294 05:55:54.145762 7, 0xFFFF, sum = 0
5295 05:55:54.146261 8, 0xFFFF, sum = 0
5296 05:55:54.149251 9, 0xFFFF, sum = 0
5297 05:55:54.149716 10, 0x0, sum = 1
5298 05:55:54.152685 11, 0x0, sum = 2
5299 05:55:54.153150 12, 0x0, sum = 3
5300 05:55:54.155518 13, 0x0, sum = 4
5301 05:55:54.155840 best_step = 11
5302 05:55:54.156093
5303 05:55:54.156329 ==
5304 05:55:54.158896 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 05:55:54.165383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5306 05:55:54.165582 ==
5307 05:55:54.165732 RX Vref Scan: 0
5308 05:55:54.165872
5309 05:55:54.168881 RX Vref 0 -> 0, step: 1
5310 05:55:54.169037
5311 05:55:54.172424 RX Delay -69 -> 252, step: 4
5312 05:55:54.175629 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5313 05:55:54.178847 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5314 05:55:54.184990 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5315 05:55:54.188588 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5316 05:55:54.191631 iDelay=203, Bit 4, Center 100 (7 ~ 194) 188
5317 05:55:54.195136 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5318 05:55:54.198602 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5319 05:55:54.205005 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5320 05:55:54.208339 iDelay=203, Bit 8, Center 74 (-13 ~ 162) 176
5321 05:55:54.211458 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5322 05:55:54.214810 iDelay=203, Bit 10, Center 90 (-1 ~ 182) 184
5323 05:55:54.218119 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5324 05:55:54.225024 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5325 05:55:54.228181 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5326 05:55:54.231879 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5327 05:55:54.234998 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5328 05:55:54.235146 ==
5329 05:55:54.238216 Dram Type= 6, Freq= 0, CH_0, rank 1
5330 05:55:54.241973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5331 05:55:54.242158 ==
5332 05:55:54.244959 DQS Delay:
5333 05:55:54.245108 DQS0 = 0, DQS1 = 0
5334 05:55:54.247928 DQM Delay:
5335 05:55:54.248069 DQM0 = 97, DQM1 = 86
5336 05:55:54.251288 DQ Delay:
5337 05:55:54.251417 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5338 05:55:54.254770 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =108
5339 05:55:54.257889 DQ8 =74, DQ9 =72, DQ10 =90, DQ11 =78
5340 05:55:54.264458 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =96
5341 05:55:54.264777
5342 05:55:54.265061
5343 05:55:54.271272 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5344 05:55:54.274527 CH0 RK1: MR19=505, MR18=2E2E
5345 05:55:54.281252 CH0_RK1: MR19=0x505, MR18=0x2E2E, DQSOSC=407, MR23=63, INC=65, DEC=43
5346 05:55:54.284815 [RxdqsGatingPostProcess] freq 933
5347 05:55:54.287899 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5348 05:55:54.291047 Pre-setting of DQS Precalculation
5349 05:55:54.297939 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5350 05:55:54.298496 ==
5351 05:55:54.301047 Dram Type= 6, Freq= 0, CH_1, rank 0
5352 05:55:54.304335 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5353 05:55:54.304848 ==
5354 05:55:54.310986 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5355 05:55:54.317955 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5356 05:55:54.320820 [CA 0] Center 37 (6~68) winsize 63
5357 05:55:54.323725 [CA 1] Center 37 (6~68) winsize 63
5358 05:55:54.327927 [CA 2] Center 34 (4~65) winsize 62
5359 05:55:54.330623 [CA 3] Center 34 (4~65) winsize 62
5360 05:55:54.333977 [CA 4] Center 33 (2~64) winsize 63
5361 05:55:54.337279 [CA 5] Center 33 (2~64) winsize 63
5362 05:55:54.337734
5363 05:55:54.340622 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5364 05:55:54.341118
5365 05:55:54.344100 [CATrainingPosCal] consider 1 rank data
5366 05:55:54.347399 u2DelayCellTimex100 = 270/100 ps
5367 05:55:54.350284 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5368 05:55:54.353571 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5369 05:55:54.357085 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5370 05:55:54.360040 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5371 05:55:54.363254 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5372 05:55:54.367137 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5373 05:55:54.367458
5374 05:55:54.373425 CA PerBit enable=1, Macro0, CA PI delay=33
5375 05:55:54.373868
5376 05:55:54.374181 [CBTSetCACLKResult] CA Dly = 33
5377 05:55:54.376595 CS Dly: 5 (0~36)
5378 05:55:54.376949 ==
5379 05:55:54.379886 Dram Type= 6, Freq= 0, CH_1, rank 1
5380 05:55:54.383739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5381 05:55:54.384214 ==
5382 05:55:54.390078 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5383 05:55:54.397100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5384 05:55:54.400313 [CA 0] Center 37 (6~68) winsize 63
5385 05:55:54.403312 [CA 1] Center 37 (6~68) winsize 63
5386 05:55:54.406900 [CA 2] Center 34 (4~65) winsize 62
5387 05:55:54.409744 [CA 3] Center 34 (4~64) winsize 61
5388 05:55:54.413594 [CA 4] Center 33 (3~64) winsize 62
5389 05:55:54.416613 [CA 5] Center 32 (2~63) winsize 62
5390 05:55:54.417154
5391 05:55:54.419882 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5392 05:55:54.420337
5393 05:55:54.423223 [CATrainingPosCal] consider 2 rank data
5394 05:55:54.426574 u2DelayCellTimex100 = 270/100 ps
5395 05:55:54.429846 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5396 05:55:54.433192 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5397 05:55:54.436378 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5398 05:55:54.439600 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5399 05:55:54.443139 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5400 05:55:54.449628 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5401 05:55:54.450174
5402 05:55:54.452876 CA PerBit enable=1, Macro0, CA PI delay=32
5403 05:55:54.453549
5404 05:55:54.456049 [CBTSetCACLKResult] CA Dly = 32
5405 05:55:54.456688 CS Dly: 5 (0~37)
5406 05:55:54.457322
5407 05:55:54.459581 ----->DramcWriteLeveling(PI) begin...
5408 05:55:54.460047 ==
5409 05:55:54.462814 Dram Type= 6, Freq= 0, CH_1, rank 0
5410 05:55:54.469576 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5411 05:55:54.470127 ==
5412 05:55:54.473145 Write leveling (Byte 0): 25 => 25
5413 05:55:54.473711 Write leveling (Byte 1): 25 => 25
5414 05:55:54.476158 DramcWriteLeveling(PI) end<-----
5415 05:55:54.476615
5416 05:55:54.477042 ==
5417 05:55:54.479592 Dram Type= 6, Freq= 0, CH_1, rank 0
5418 05:55:54.485959 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5419 05:55:54.486541 ==
5420 05:55:54.489429 [Gating] SW mode calibration
5421 05:55:54.496173 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5422 05:55:54.499351 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5423 05:55:54.506071 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5424 05:55:54.509242 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5425 05:55:54.512405 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5426 05:55:54.519154 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5427 05:55:54.522448 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5428 05:55:54.525632 0 10 20 | B1->B0 | 3232 2424 | 0 0 | (0 0) (0 0)
5429 05:55:54.532202 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5430 05:55:54.535469 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5431 05:55:54.538530 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5432 05:55:54.545272 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5433 05:55:54.548747 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5434 05:55:54.551774 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5435 05:55:54.558490 0 11 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5436 05:55:54.561451 0 11 20 | B1->B0 | 2d2d 4242 | 0 0 | (0 0) (0 0)
5437 05:55:54.565189 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5438 05:55:54.571724 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 05:55:54.574976 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 05:55:54.578411 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5441 05:55:54.584932 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5442 05:55:54.588273 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5443 05:55:54.591950 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5444 05:55:54.598481 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5445 05:55:54.601398 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 05:55:54.604669 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 05:55:54.611530 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 05:55:54.615006 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 05:55:54.618056 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 05:55:54.624504 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 05:55:54.627920 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 05:55:54.631262 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 05:55:54.637939 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 05:55:54.640857 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 05:55:54.644049 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 05:55:54.650820 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 05:55:54.654039 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 05:55:54.657425 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5459 05:55:54.664354 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5460 05:55:54.667825 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5461 05:55:54.670760 Total UI for P1: 0, mck2ui 16
5462 05:55:54.674393 best dqsien dly found for B0: ( 0, 14, 16)
5463 05:55:54.677696 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5464 05:55:54.680759 Total UI for P1: 0, mck2ui 16
5465 05:55:54.684053 best dqsien dly found for B1: ( 0, 14, 20)
5466 05:55:54.687247 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5467 05:55:54.690708 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5468 05:55:54.691310
5469 05:55:54.697161 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5470 05:55:54.700847 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5471 05:55:54.703940 [Gating] SW calibration Done
5472 05:55:54.704488 ==
5473 05:55:54.706809 Dram Type= 6, Freq= 0, CH_1, rank 0
5474 05:55:54.710673 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5475 05:55:54.711254 ==
5476 05:55:54.711745 RX Vref Scan: 0
5477 05:55:54.712205
5478 05:55:54.713614 RX Vref 0 -> 0, step: 1
5479 05:55:54.714089
5480 05:55:54.716792 RX Delay -80 -> 252, step: 8
5481 05:55:54.720782 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5482 05:55:54.724020 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5483 05:55:54.730748 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5484 05:55:54.733499 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5485 05:55:54.736829 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5486 05:55:54.740471 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5487 05:55:54.743360 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5488 05:55:54.746420 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5489 05:55:54.753113 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5490 05:55:54.756214 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5491 05:55:54.759553 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5492 05:55:54.763030 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5493 05:55:54.766518 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5494 05:55:54.773163 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5495 05:55:54.776660 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5496 05:55:54.779753 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5497 05:55:54.780395 ==
5498 05:55:54.783291 Dram Type= 6, Freq= 0, CH_1, rank 0
5499 05:55:54.786318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5500 05:55:54.786897 ==
5501 05:55:54.789568 DQS Delay:
5502 05:55:54.790044 DQS0 = 0, DQS1 = 0
5503 05:55:54.792875 DQM Delay:
5504 05:55:54.793351 DQM0 = 95, DQM1 = 89
5505 05:55:54.793834 DQ Delay:
5506 05:55:54.796692 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5507 05:55:54.799694 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5508 05:55:54.803190 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5509 05:55:54.806186 DQ12 =99, DQ13 =103, DQ14 =95, DQ15 =99
5510 05:55:54.806652
5511 05:55:54.807012
5512 05:55:54.809179 ==
5513 05:55:54.812800 Dram Type= 6, Freq= 0, CH_1, rank 0
5514 05:55:54.816056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5515 05:55:54.816521 ==
5516 05:55:54.817022
5517 05:55:54.817384
5518 05:55:54.819534 TX Vref Scan disable
5519 05:55:54.820011 == TX Byte 0 ==
5520 05:55:54.826097 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5521 05:55:54.829542 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5522 05:55:54.830058 == TX Byte 1 ==
5523 05:55:54.835557 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5524 05:55:54.839056 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5525 05:55:54.839521 ==
5526 05:55:54.842645 Dram Type= 6, Freq= 0, CH_1, rank 0
5527 05:55:54.845466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5528 05:55:54.845993 ==
5529 05:55:54.846364
5530 05:55:54.846702
5531 05:55:54.848743 TX Vref Scan disable
5532 05:55:54.852524 == TX Byte 0 ==
5533 05:55:54.855887 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5534 05:55:54.858604 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5535 05:55:54.862423 == TX Byte 1 ==
5536 05:55:54.865634 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5537 05:55:54.868904 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5538 05:55:54.869516
5539 05:55:54.872041 [DATLAT]
5540 05:55:54.872586 Freq=933, CH1 RK0
5541 05:55:54.873041
5542 05:55:54.875068 DATLAT Default: 0xd
5543 05:55:54.875529 0, 0xFFFF, sum = 0
5544 05:55:54.878471 1, 0xFFFF, sum = 0
5545 05:55:54.878939 2, 0xFFFF, sum = 0
5546 05:55:54.882145 3, 0xFFFF, sum = 0
5547 05:55:54.882612 4, 0xFFFF, sum = 0
5548 05:55:54.885340 5, 0xFFFF, sum = 0
5549 05:55:54.885806 6, 0xFFFF, sum = 0
5550 05:55:54.888779 7, 0xFFFF, sum = 0
5551 05:55:54.889247 8, 0xFFFF, sum = 0
5552 05:55:54.891948 9, 0xFFFF, sum = 0
5553 05:55:54.892414 10, 0x0, sum = 1
5554 05:55:54.895343 11, 0x0, sum = 2
5555 05:55:54.895809 12, 0x0, sum = 3
5556 05:55:54.898070 13, 0x0, sum = 4
5557 05:55:54.898493 best_step = 11
5558 05:55:54.898822
5559 05:55:54.899131 ==
5560 05:55:54.901751 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 05:55:54.908170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5562 05:55:54.908685 ==
5563 05:55:54.909175 RX Vref Scan: 1
5564 05:55:54.909497
5565 05:55:54.911630 RX Vref 0 -> 0, step: 1
5566 05:55:54.912047
5567 05:55:54.915098 RX Delay -69 -> 252, step: 4
5568 05:55:54.915515
5569 05:55:54.918283 Set Vref, RX VrefLevel [Byte0]: 55
5570 05:55:54.921381 [Byte1]: 49
5571 05:55:54.921799
5572 05:55:54.925172 Final RX Vref Byte 0 = 55 to rank0
5573 05:55:54.928451 Final RX Vref Byte 1 = 49 to rank0
5574 05:55:54.931637 Final RX Vref Byte 0 = 55 to rank1
5575 05:55:54.934887 Final RX Vref Byte 1 = 49 to rank1==
5576 05:55:54.938105 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 05:55:54.941127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5578 05:55:54.941617 ==
5579 05:55:54.944957 DQS Delay:
5580 05:55:54.945374 DQS0 = 0, DQS1 = 0
5581 05:55:54.948316 DQM Delay:
5582 05:55:54.948947 DQM0 = 94, DQM1 = 88
5583 05:55:54.949400 DQ Delay:
5584 05:55:54.951284 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =92
5585 05:55:54.954532 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5586 05:55:54.957701 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5587 05:55:54.961239 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5588 05:55:54.961659
5589 05:55:54.964857
5590 05:55:54.971089 [DQSOSCAuto] RK0, (LSB)MR18= 0x3232, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5591 05:55:54.974679 CH1 RK0: MR19=505, MR18=3232
5592 05:55:54.981216 CH1_RK0: MR19=0x505, MR18=0x3232, DQSOSC=406, MR23=63, INC=65, DEC=43
5593 05:55:54.981635
5594 05:55:54.984138 ----->DramcWriteLeveling(PI) begin...
5595 05:55:54.984559 ==
5596 05:55:54.987600 Dram Type= 6, Freq= 0, CH_1, rank 1
5597 05:55:54.990945 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5598 05:55:54.991456 ==
5599 05:55:54.994106 Write leveling (Byte 0): 22 => 22
5600 05:55:54.997773 Write leveling (Byte 1): 26 => 26
5601 05:55:55.000896 DramcWriteLeveling(PI) end<-----
5602 05:55:55.001405
5603 05:55:55.001739 ==
5604 05:55:55.004137 Dram Type= 6, Freq= 0, CH_1, rank 1
5605 05:55:55.007356 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5606 05:55:55.007844 ==
5607 05:55:55.010754 [Gating] SW mode calibration
5608 05:55:55.017382 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5609 05:55:55.023643 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5610 05:55:55.027656 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 05:55:55.033766 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 05:55:55.037118 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 05:55:55.040323 0 10 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5614 05:55:55.047236 0 10 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
5615 05:55:55.050244 0 10 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5616 05:55:55.053502 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 05:55:55.059645 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 05:55:55.063370 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 05:55:55.066531 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 05:55:55.073250 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 05:55:55.076915 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 05:55:55.080048 0 11 16 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
5623 05:55:55.083219 0 11 20 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
5624 05:55:55.089656 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 05:55:55.093209 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 05:55:55.096595 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 05:55:55.102945 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 05:55:55.106415 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 05:55:55.109379 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 05:55:55.116393 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5631 05:55:55.119509 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5632 05:55:55.123054 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 05:55:55.129646 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 05:55:55.133017 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 05:55:55.136035 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 05:55:55.142947 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 05:55:55.146348 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 05:55:55.149496 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 05:55:55.156002 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 05:55:55.159350 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 05:55:55.162918 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 05:55:55.169388 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 05:55:55.172182 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 05:55:55.175578 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 05:55:55.182081 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 05:55:55.185474 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5647 05:55:55.188897 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 05:55:55.192282 Total UI for P1: 0, mck2ui 16
5649 05:55:55.195209 best dqsien dly found for B0: ( 0, 14, 16)
5650 05:55:55.198749 Total UI for P1: 0, mck2ui 16
5651 05:55:55.201904 best dqsien dly found for B1: ( 0, 14, 16)
5652 05:55:55.205271 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5653 05:55:55.211711 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5654 05:55:55.212198
5655 05:55:55.215215 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5656 05:55:55.218674 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5657 05:55:55.221688 [Gating] SW calibration Done
5658 05:55:55.222241 ==
5659 05:55:55.225279 Dram Type= 6, Freq= 0, CH_1, rank 1
5660 05:55:55.228341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5661 05:55:55.228838 ==
5662 05:55:55.231888 RX Vref Scan: 0
5663 05:55:55.232467
5664 05:55:55.232890 RX Vref 0 -> 0, step: 1
5665 05:55:55.233241
5666 05:55:55.235073 RX Delay -80 -> 252, step: 8
5667 05:55:55.238153 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5668 05:55:55.244653 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5669 05:55:55.248184 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5670 05:55:55.251353 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5671 05:55:55.255200 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5672 05:55:55.257954 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5673 05:55:55.261182 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5674 05:55:55.268140 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5675 05:55:55.271071 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5676 05:55:55.274609 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5677 05:55:55.277964 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5678 05:55:55.281205 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5679 05:55:55.287479 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5680 05:55:55.291201 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5681 05:55:55.294137 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5682 05:55:55.297691 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5683 05:55:55.298152 ==
5684 05:55:55.301015 Dram Type= 6, Freq= 0, CH_1, rank 1
5685 05:55:55.304371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5686 05:55:55.307359 ==
5687 05:55:55.307813 DQS Delay:
5688 05:55:55.308175 DQS0 = 0, DQS1 = 0
5689 05:55:55.310657 DQM Delay:
5690 05:55:55.311115 DQM0 = 95, DQM1 = 87
5691 05:55:55.314505 DQ Delay:
5692 05:55:55.315282 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =91
5693 05:55:55.317345 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5694 05:55:55.320789 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5695 05:55:55.327958 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5696 05:55:55.328523
5697 05:55:55.328917
5698 05:55:55.329253 ==
5699 05:55:55.330929 Dram Type= 6, Freq= 0, CH_1, rank 1
5700 05:55:55.334576 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5701 05:55:55.335148 ==
5702 05:55:55.335517
5703 05:55:55.335851
5704 05:55:55.337336 TX Vref Scan disable
5705 05:55:55.337793 == TX Byte 0 ==
5706 05:55:55.343696 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5707 05:55:55.347447 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5708 05:55:55.348012 == TX Byte 1 ==
5709 05:55:55.353927 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5710 05:55:55.356799 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5711 05:55:55.357261 ==
5712 05:55:55.360244 Dram Type= 6, Freq= 0, CH_1, rank 1
5713 05:55:55.363722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5714 05:55:55.364295 ==
5715 05:55:55.364662
5716 05:55:55.366668
5717 05:55:55.367123 TX Vref Scan disable
5718 05:55:55.370234 == TX Byte 0 ==
5719 05:55:55.373580 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5720 05:55:55.376926 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5721 05:55:55.380252 == TX Byte 1 ==
5722 05:55:55.383797 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5723 05:55:55.386664 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5724 05:55:55.390651
5725 05:55:55.391206 [DATLAT]
5726 05:55:55.391568 Freq=933, CH1 RK1
5727 05:55:55.391907
5728 05:55:55.393602 DATLAT Default: 0xb
5729 05:55:55.394056 0, 0xFFFF, sum = 0
5730 05:55:55.396688 1, 0xFFFF, sum = 0
5731 05:55:55.397183 2, 0xFFFF, sum = 0
5732 05:55:55.400204 3, 0xFFFF, sum = 0
5733 05:55:55.400837 4, 0xFFFF, sum = 0
5734 05:55:55.403457 5, 0xFFFF, sum = 0
5735 05:55:55.406596 6, 0xFFFF, sum = 0
5736 05:55:55.407164 7, 0xFFFF, sum = 0
5737 05:55:55.409537 8, 0xFFFF, sum = 0
5738 05:55:55.410002 9, 0xFFFF, sum = 0
5739 05:55:55.413196 10, 0x0, sum = 1
5740 05:55:55.413662 11, 0x0, sum = 2
5741 05:55:55.416108 12, 0x0, sum = 3
5742 05:55:55.416572 13, 0x0, sum = 4
5743 05:55:55.416992 best_step = 11
5744 05:55:55.417334
5745 05:55:55.419358 ==
5746 05:55:55.423238 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 05:55:55.426253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5748 05:55:55.426712 ==
5749 05:55:55.427074 RX Vref Scan: 0
5750 05:55:55.427413
5751 05:55:55.429415 RX Vref 0 -> 0, step: 1
5752 05:55:55.429873
5753 05:55:55.432860 RX Delay -69 -> 252, step: 4
5754 05:55:55.439542 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5755 05:55:55.443090 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5756 05:55:55.446272 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5757 05:55:55.449410 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5758 05:55:55.452637 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5759 05:55:55.455936 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5760 05:55:55.462990 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5761 05:55:55.465894 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5762 05:55:55.468875 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5763 05:55:55.472463 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5764 05:55:55.475758 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5765 05:55:55.482360 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5766 05:55:55.485488 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5767 05:55:55.488746 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5768 05:55:55.492159 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5769 05:55:55.495405 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5770 05:55:55.495823 ==
5771 05:55:55.498843 Dram Type= 6, Freq= 0, CH_1, rank 1
5772 05:55:55.505775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5773 05:55:55.506195 ==
5774 05:55:55.506526 DQS Delay:
5775 05:55:55.509112 DQS0 = 0, DQS1 = 0
5776 05:55:55.509620 DQM Delay:
5777 05:55:55.509955 DQM0 = 96, DQM1 = 87
5778 05:55:55.511926 DQ Delay:
5779 05:55:55.515196 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5780 05:55:55.518584 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5781 05:55:55.522003 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5782 05:55:55.525300 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5783 05:55:55.525716
5784 05:55:55.526042
5785 05:55:55.532180 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5786 05:55:55.535350 CH1 RK1: MR19=505, MR18=1E1E
5787 05:55:55.541545 CH1_RK1: MR19=0x505, MR18=0x1E1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5788 05:55:55.544905 [RxdqsGatingPostProcess] freq 933
5789 05:55:55.548259 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5790 05:55:55.551429 Pre-setting of DQS Precalculation
5791 05:55:55.558425 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5792 05:55:55.565041 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5793 05:55:55.571876 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5794 05:55:55.572396
5795 05:55:55.572774
5796 05:55:55.574920 [Calibration Summary] 1866 Mbps
5797 05:55:55.578274 CH 0, Rank 0
5798 05:55:55.578689 SW Impedance : PASS
5799 05:55:55.581498 DUTY Scan : NO K
5800 05:55:55.584852 ZQ Calibration : PASS
5801 05:55:55.585268 Jitter Meter : NO K
5802 05:55:55.588277 CBT Training : PASS
5803 05:55:55.588835 Write leveling : PASS
5804 05:55:55.591814 RX DQS gating : PASS
5805 05:55:55.594755 RX DQ/DQS(RDDQC) : PASS
5806 05:55:55.595304 TX DQ/DQS : PASS
5807 05:55:55.598273 RX DATLAT : PASS
5808 05:55:55.600903 RX DQ/DQS(Engine): PASS
5809 05:55:55.601320 TX OE : NO K
5810 05:55:55.604272 All Pass.
5811 05:55:55.604683
5812 05:55:55.605079 CH 0, Rank 1
5813 05:55:55.607821 SW Impedance : PASS
5814 05:55:55.608233 DUTY Scan : NO K
5815 05:55:55.611301 ZQ Calibration : PASS
5816 05:55:55.614696 Jitter Meter : NO K
5817 05:55:55.615110 CBT Training : PASS
5818 05:55:55.617604 Write leveling : PASS
5819 05:55:55.621192 RX DQS gating : PASS
5820 05:55:55.621607 RX DQ/DQS(RDDQC) : PASS
5821 05:55:55.624517 TX DQ/DQS : PASS
5822 05:55:55.628130 RX DATLAT : PASS
5823 05:55:55.628633 RX DQ/DQS(Engine): PASS
5824 05:55:55.630823 TX OE : NO K
5825 05:55:55.631243 All Pass.
5826 05:55:55.631574
5827 05:55:55.634044 CH 1, Rank 0
5828 05:55:55.634454 SW Impedance : PASS
5829 05:55:55.637594 DUTY Scan : NO K
5830 05:55:55.640533 ZQ Calibration : PASS
5831 05:55:55.640992 Jitter Meter : NO K
5832 05:55:55.644402 CBT Training : PASS
5833 05:55:55.647511 Write leveling : PASS
5834 05:55:55.648033 RX DQS gating : PASS
5835 05:55:55.650906 RX DQ/DQS(RDDQC) : PASS
5836 05:55:55.653909 TX DQ/DQS : PASS
5837 05:55:55.654401 RX DATLAT : PASS
5838 05:55:55.657055 RX DQ/DQS(Engine): PASS
5839 05:55:55.657465 TX OE : NO K
5840 05:55:55.660567 All Pass.
5841 05:55:55.661103
5842 05:55:55.661439 CH 1, Rank 1
5843 05:55:55.663630 SW Impedance : PASS
5844 05:55:55.664044 DUTY Scan : NO K
5845 05:55:55.667248 ZQ Calibration : PASS
5846 05:55:55.670278 Jitter Meter : NO K
5847 05:55:55.670693 CBT Training : PASS
5848 05:55:55.673836 Write leveling : PASS
5849 05:55:55.676951 RX DQS gating : PASS
5850 05:55:55.677367 RX DQ/DQS(RDDQC) : PASS
5851 05:55:55.680159 TX DQ/DQS : PASS
5852 05:55:55.683636 RX DATLAT : PASS
5853 05:55:55.684046 RX DQ/DQS(Engine): PASS
5854 05:55:55.686866 TX OE : NO K
5855 05:55:55.687282 All Pass.
5856 05:55:55.687646
5857 05:55:55.690281 DramC Write-DBI off
5858 05:55:55.693644 PER_BANK_REFRESH: Hybrid Mode
5859 05:55:55.694057 TX_TRACKING: ON
5860 05:55:55.703624 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5861 05:55:55.707128 [FAST_K] Save calibration result to emmc
5862 05:55:55.710477 dramc_set_vcore_voltage set vcore to 650000
5863 05:55:55.713099 Read voltage for 400, 6
5864 05:55:55.713515 Vio18 = 0
5865 05:55:55.716763 Vcore = 650000
5866 05:55:55.717281 Vdram = 0
5867 05:55:55.717616 Vddq = 0
5868 05:55:55.717923 Vmddr = 0
5869 05:55:55.723409 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5870 05:55:55.730089 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5871 05:55:55.730605 MEM_TYPE=3, freq_sel=20
5872 05:55:55.733133 sv_algorithm_assistance_LP4_800
5873 05:55:55.736850 ============ PULL DRAM RESETB DOWN ============
5874 05:55:55.743126 ========== PULL DRAM RESETB DOWN end =========
5875 05:55:55.746187 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5876 05:55:55.749322 ===================================
5877 05:55:55.752959 LPDDR4 DRAM CONFIGURATION
5878 05:55:55.756589 ===================================
5879 05:55:55.757055 EX_ROW_EN[0] = 0x0
5880 05:55:55.759926 EX_ROW_EN[1] = 0x0
5881 05:55:55.760566 LP4Y_EN = 0x0
5882 05:55:55.762802 WORK_FSP = 0x0
5883 05:55:55.763309 WL = 0x2
5884 05:55:55.766378 RL = 0x2
5885 05:55:55.766902 BL = 0x2
5886 05:55:55.769300 RPST = 0x0
5887 05:55:55.772694 RD_PRE = 0x0
5888 05:55:55.773167 WR_PRE = 0x1
5889 05:55:55.776268 WR_PST = 0x0
5890 05:55:55.776828 DBI_WR = 0x0
5891 05:55:55.779877 DBI_RD = 0x0
5892 05:55:55.780389 OTF = 0x1
5893 05:55:55.782344 ===================================
5894 05:55:55.786199 ===================================
5895 05:55:55.789122 ANA top config
5896 05:55:55.792664 ===================================
5897 05:55:55.793245 DLL_ASYNC_EN = 0
5898 05:55:55.795749 ALL_SLAVE_EN = 1
5899 05:55:55.799030 NEW_RANK_MODE = 1
5900 05:55:55.802559 DLL_IDLE_MODE = 1
5901 05:55:55.802973 LP45_APHY_COMB_EN = 1
5902 05:55:55.806334 TX_ODT_DIS = 1
5903 05:55:55.809272 NEW_8X_MODE = 1
5904 05:55:55.812401 ===================================
5905 05:55:55.815427 ===================================
5906 05:55:55.818869 data_rate = 800
5907 05:55:55.822646 CKR = 1
5908 05:55:55.825446 DQ_P2S_RATIO = 4
5909 05:55:55.828961 ===================================
5910 05:55:55.829530 CA_P2S_RATIO = 4
5911 05:55:55.832612 DQ_CA_OPEN = 0
5912 05:55:55.835645 DQ_SEMI_OPEN = 1
5913 05:55:55.838898 CA_SEMI_OPEN = 1
5914 05:55:55.842342 CA_FULL_RATE = 0
5915 05:55:55.845662 DQ_CKDIV4_EN = 0
5916 05:55:55.846180 CA_CKDIV4_EN = 1
5917 05:55:55.848797 CA_PREDIV_EN = 0
5918 05:55:55.851931 PH8_DLY = 0
5919 05:55:55.855336 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5920 05:55:55.858618 DQ_AAMCK_DIV = 0
5921 05:55:55.861764 CA_AAMCK_DIV = 0
5922 05:55:55.862179 CA_ADMCK_DIV = 4
5923 05:55:55.864868 DQ_TRACK_CA_EN = 0
5924 05:55:55.868487 CA_PICK = 800
5925 05:55:55.871941 CA_MCKIO = 400
5926 05:55:55.875198 MCKIO_SEMI = 400
5927 05:55:55.878179 PLL_FREQ = 3016
5928 05:55:55.881818 DQ_UI_PI_RATIO = 32
5929 05:55:55.885188 CA_UI_PI_RATIO = 32
5930 05:55:55.888120 ===================================
5931 05:55:55.891770 ===================================
5932 05:55:55.892184 memory_type:LPDDR4
5933 05:55:55.894691 GP_NUM : 10
5934 05:55:55.898228 SRAM_EN : 1
5935 05:55:55.898640 MD32_EN : 0
5936 05:55:55.901633 ===================================
5937 05:55:55.905127 [ANA_INIT] >>>>>>>>>>>>>>
5938 05:55:55.908249 <<<<<< [CONFIGURE PHASE]: ANA_TX
5939 05:55:55.911221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5940 05:55:55.915232 ===================================
5941 05:55:55.915748 data_rate = 800,PCW = 0X7400
5942 05:55:55.918274 ===================================
5943 05:55:55.924965 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5944 05:55:55.928246 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5945 05:55:55.941492 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5946 05:55:55.944784 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5947 05:55:55.947558 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5948 05:55:55.950765 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5949 05:55:55.954318 [ANA_INIT] flow start
5950 05:55:55.954736 [ANA_INIT] PLL >>>>>>>>
5951 05:55:55.957631 [ANA_INIT] PLL <<<<<<<<
5952 05:55:55.960820 [ANA_INIT] MIDPI >>>>>>>>
5953 05:55:55.965207 [ANA_INIT] MIDPI <<<<<<<<
5954 05:55:55.965623 [ANA_INIT] DLL >>>>>>>>
5955 05:55:55.967769 [ANA_INIT] flow end
5956 05:55:55.971001 ============ LP4 DIFF to SE enter ============
5957 05:55:55.974332 ============ LP4 DIFF to SE exit ============
5958 05:55:55.977375 [ANA_INIT] <<<<<<<<<<<<<
5959 05:55:55.980741 [Flow] Enable top DCM control >>>>>
5960 05:55:55.984153 [Flow] Enable top DCM control <<<<<
5961 05:55:55.987358 Enable DLL master slave shuffle
5962 05:55:55.994183 ==============================================================
5963 05:55:55.994698 Gating Mode config
5964 05:55:56.000529 ==============================================================
5965 05:55:56.001048 Config description:
5966 05:55:56.010690 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5967 05:55:56.017188 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5968 05:55:56.023824 SELPH_MODE 0: By rank 1: By Phase
5969 05:55:56.027318 ==============================================================
5970 05:55:56.030376 GAT_TRACK_EN = 0
5971 05:55:56.033884 RX_GATING_MODE = 2
5972 05:55:56.036972 RX_GATING_TRACK_MODE = 2
5973 05:55:56.040470 SELPH_MODE = 1
5974 05:55:56.043839 PICG_EARLY_EN = 1
5975 05:55:56.047319 VALID_LAT_VALUE = 1
5976 05:55:56.053638 ==============================================================
5977 05:55:56.056636 Enter into Gating configuration >>>>
5978 05:55:56.060377 Exit from Gating configuration <<<<
5979 05:55:56.063591 Enter into DVFS_PRE_config >>>>>
5980 05:55:56.073137 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5981 05:55:56.076805 Exit from DVFS_PRE_config <<<<<
5982 05:55:56.079876 Enter into PICG configuration >>>>
5983 05:55:56.083216 Exit from PICG configuration <<<<
5984 05:55:56.086409 [RX_INPUT] configuration >>>>>
5985 05:55:56.086812 [RX_INPUT] configuration <<<<<
5986 05:55:56.093281 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5987 05:55:56.099869 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5988 05:55:56.102847 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5989 05:55:56.109612 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5990 05:55:56.116026 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5991 05:55:56.123185 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5992 05:55:56.126012 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5993 05:55:56.129439 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5994 05:55:56.136289 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5995 05:55:56.139387 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5996 05:55:56.143100 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5997 05:55:56.149256 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5998 05:55:56.152787 ===================================
5999 05:55:56.153343 LPDDR4 DRAM CONFIGURATION
6000 05:55:56.155513 ===================================
6001 05:55:56.159690 EX_ROW_EN[0] = 0x0
6002 05:55:56.162677 EX_ROW_EN[1] = 0x0
6003 05:55:56.163130 LP4Y_EN = 0x0
6004 05:55:56.165937 WORK_FSP = 0x0
6005 05:55:56.166392 WL = 0x2
6006 05:55:56.168995 RL = 0x2
6007 05:55:56.169448 BL = 0x2
6008 05:55:56.172158 RPST = 0x0
6009 05:55:56.172609 RD_PRE = 0x0
6010 05:55:56.175512 WR_PRE = 0x1
6011 05:55:56.175962 WR_PST = 0x0
6012 05:55:56.179333 DBI_WR = 0x0
6013 05:55:56.179895 DBI_RD = 0x0
6014 05:55:56.182465 OTF = 0x1
6015 05:55:56.186054 ===================================
6016 05:55:56.188844 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6017 05:55:56.191931 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6018 05:55:56.199022 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6019 05:55:56.201863 ===================================
6020 05:55:56.202419 LPDDR4 DRAM CONFIGURATION
6021 05:55:56.205372 ===================================
6022 05:55:56.208631 EX_ROW_EN[0] = 0x10
6023 05:55:56.211936 EX_ROW_EN[1] = 0x0
6024 05:55:56.212387 LP4Y_EN = 0x0
6025 05:55:56.215302 WORK_FSP = 0x0
6026 05:55:56.215754 WL = 0x2
6027 05:55:56.218444 RL = 0x2
6028 05:55:56.218852 BL = 0x2
6029 05:55:56.222128 RPST = 0x0
6030 05:55:56.222641 RD_PRE = 0x0
6031 05:55:56.225259 WR_PRE = 0x1
6032 05:55:56.225669 WR_PST = 0x0
6033 05:55:56.228632 DBI_WR = 0x0
6034 05:55:56.229070 DBI_RD = 0x0
6035 05:55:56.232045 OTF = 0x1
6036 05:55:56.235219 ===================================
6037 05:55:56.242044 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6038 05:55:56.245095 nWR fixed to 30
6039 05:55:56.248759 [ModeRegInit_LP4] CH0 RK0
6040 05:55:56.249289 [ModeRegInit_LP4] CH0 RK1
6041 05:55:56.251884 [ModeRegInit_LP4] CH1 RK0
6042 05:55:56.255275 [ModeRegInit_LP4] CH1 RK1
6043 05:55:56.255801 match AC timing 18
6044 05:55:56.261692 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6045 05:55:56.264663 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6046 05:55:56.267779 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6047 05:55:56.274692 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6048 05:55:56.278373 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6049 05:55:56.278963 ==
6050 05:55:56.281236 Dram Type= 6, Freq= 0, CH_0, rank 0
6051 05:55:56.284690 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6052 05:55:56.285226 ==
6053 05:55:56.291488 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6054 05:55:56.297963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6055 05:55:56.301013 [CA 0] Center 36 (8~64) winsize 57
6056 05:55:56.304417 [CA 1] Center 36 (8~64) winsize 57
6057 05:55:56.307663 [CA 2] Center 36 (8~64) winsize 57
6058 05:55:56.308430 [CA 3] Center 36 (8~64) winsize 57
6059 05:55:56.311060 [CA 4] Center 36 (8~64) winsize 57
6060 05:55:56.314099 [CA 5] Center 36 (8~64) winsize 57
6061 05:55:56.314595
6062 05:55:56.321049 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6063 05:55:56.321505
6064 05:55:56.324303 [CATrainingPosCal] consider 1 rank data
6065 05:55:56.327774 u2DelayCellTimex100 = 270/100 ps
6066 05:55:56.331119 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6067 05:55:56.334114 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6068 05:55:56.337575 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6069 05:55:56.340883 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6070 05:55:56.344191 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6071 05:55:56.347558 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6072 05:55:56.348020
6073 05:55:56.350805 CA PerBit enable=1, Macro0, CA PI delay=36
6074 05:55:56.351358
6075 05:55:56.353939 [CBTSetCACLKResult] CA Dly = 36
6076 05:55:56.357548 CS Dly: 1 (0~32)
6077 05:55:56.358010 ==
6078 05:55:56.360914 Dram Type= 6, Freq= 0, CH_0, rank 1
6079 05:55:56.363909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6080 05:55:56.364380 ==
6081 05:55:56.370550 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6082 05:55:56.377271 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6083 05:55:56.380418 [CA 0] Center 36 (8~64) winsize 57
6084 05:55:56.381009 [CA 1] Center 36 (8~64) winsize 57
6085 05:55:56.383544 [CA 2] Center 36 (8~64) winsize 57
6086 05:55:56.386933 [CA 3] Center 36 (8~64) winsize 57
6087 05:55:56.390627 [CA 4] Center 36 (8~64) winsize 57
6088 05:55:56.393422 [CA 5] Center 36 (8~64) winsize 57
6089 05:55:56.393874
6090 05:55:56.397077 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6091 05:55:56.397529
6092 05:55:56.400336 [CATrainingPosCal] consider 2 rank data
6093 05:55:56.403429 u2DelayCellTimex100 = 270/100 ps
6094 05:55:56.407168 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6095 05:55:56.413540 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6096 05:55:56.417064 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6097 05:55:56.420021 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6098 05:55:56.423556 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6099 05:55:56.427116 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6100 05:55:56.427678
6101 05:55:56.430061 CA PerBit enable=1, Macro0, CA PI delay=36
6102 05:55:56.430516
6103 05:55:56.433722 [CBTSetCACLKResult] CA Dly = 36
6104 05:55:56.434273 CS Dly: 1 (0~32)
6105 05:55:56.436984
6106 05:55:56.440180 ----->DramcWriteLeveling(PI) begin...
6107 05:55:56.440643 ==
6108 05:55:56.443409 Dram Type= 6, Freq= 0, CH_0, rank 0
6109 05:55:56.446412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6110 05:55:56.446877 ==
6111 05:55:56.449867 Write leveling (Byte 0): 32 => 0
6112 05:55:56.453323 Write leveling (Byte 1): 32 => 0
6113 05:55:56.456404 DramcWriteLeveling(PI) end<-----
6114 05:55:56.456976
6115 05:55:56.457344 ==
6116 05:55:56.459434 Dram Type= 6, Freq= 0, CH_0, rank 0
6117 05:55:56.462902 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6118 05:55:56.463379 ==
6119 05:55:56.466125 [Gating] SW mode calibration
6120 05:55:56.473313 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6121 05:55:56.479531 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6122 05:55:56.482958 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6123 05:55:56.485845 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6124 05:55:56.493104 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6125 05:55:56.496302 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6126 05:55:56.499334 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6127 05:55:56.506184 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6128 05:55:56.508964 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6129 05:55:56.512517 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6130 05:55:56.518910 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6131 05:55:56.519370 Total UI for P1: 0, mck2ui 16
6132 05:55:56.525681 best dqsien dly found for B0: ( 0, 10, 16)
6133 05:55:56.526247 Total UI for P1: 0, mck2ui 16
6134 05:55:56.532382 best dqsien dly found for B1: ( 0, 10, 24)
6135 05:55:56.535438 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6136 05:55:56.539132 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6137 05:55:56.539613
6138 05:55:56.541910 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6139 05:55:56.545328 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6140 05:55:56.549232 [Gating] SW calibration Done
6141 05:55:56.549784 ==
6142 05:55:56.552346 Dram Type= 6, Freq= 0, CH_0, rank 0
6143 05:55:56.555102 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6144 05:55:56.555604 ==
6145 05:55:56.558452 RX Vref Scan: 0
6146 05:55:56.558905
6147 05:55:56.561768 RX Vref 0 -> 0, step: 1
6148 05:55:56.562397
6149 05:55:56.562770 RX Delay -410 -> 252, step: 16
6150 05:55:56.568443 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6151 05:55:56.571728 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6152 05:55:56.575365 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6153 05:55:56.578492 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6154 05:55:56.585421 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6155 05:55:56.588622 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6156 05:55:56.592208 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6157 05:55:56.594938 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6158 05:55:56.601739 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6159 05:55:56.605351 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6160 05:55:56.608390 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6161 05:55:56.614684 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6162 05:55:56.618405 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6163 05:55:56.621774 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6164 05:55:56.624645 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6165 05:55:56.631239 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6166 05:55:56.631789 ==
6167 05:55:56.634770 Dram Type= 6, Freq= 0, CH_0, rank 0
6168 05:55:56.637975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6169 05:55:56.638438 ==
6170 05:55:56.638799 DQS Delay:
6171 05:55:56.641336 DQS0 = 51, DQS1 = 59
6172 05:55:56.641796 DQM Delay:
6173 05:55:56.644809 DQM0 = 11, DQM1 = 11
6174 05:55:56.645296 DQ Delay:
6175 05:55:56.647738 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6176 05:55:56.650899 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6177 05:55:56.654412 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6178 05:55:56.657407 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6179 05:55:56.657863
6180 05:55:56.658222
6181 05:55:56.658554 ==
6182 05:55:56.660869 Dram Type= 6, Freq= 0, CH_0, rank 0
6183 05:55:56.664281 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6184 05:55:56.664769 ==
6185 05:55:56.665142
6186 05:55:56.665606
6187 05:55:56.667697 TX Vref Scan disable
6188 05:55:56.670889 == TX Byte 0 ==
6189 05:55:56.674225 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6190 05:55:56.677775 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6191 05:55:56.681112 == TX Byte 1 ==
6192 05:55:56.684085 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6193 05:55:56.687275 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6194 05:55:56.687688 ==
6195 05:55:56.690730 Dram Type= 6, Freq= 0, CH_0, rank 0
6196 05:55:56.697313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6197 05:55:56.697856 ==
6198 05:55:56.698219
6199 05:55:56.698549
6200 05:55:56.698865 TX Vref Scan disable
6201 05:55:56.700579 == TX Byte 0 ==
6202 05:55:56.704309 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6203 05:55:56.707537 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6204 05:55:56.710660 == TX Byte 1 ==
6205 05:55:56.713676 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6206 05:55:56.717302 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6207 05:55:56.717855
6208 05:55:56.720396 [DATLAT]
6209 05:55:56.720882 Freq=400, CH0 RK0
6210 05:55:56.721253
6211 05:55:56.723381 DATLAT Default: 0xf
6212 05:55:56.723834 0, 0xFFFF, sum = 0
6213 05:55:56.727341 1, 0xFFFF, sum = 0
6214 05:55:56.727910 2, 0xFFFF, sum = 0
6215 05:55:56.730472 3, 0xFFFF, sum = 0
6216 05:55:56.731034 4, 0xFFFF, sum = 0
6217 05:55:56.733877 5, 0xFFFF, sum = 0
6218 05:55:56.734449 6, 0xFFFF, sum = 0
6219 05:55:56.737436 7, 0xFFFF, sum = 0
6220 05:55:56.738009 8, 0xFFFF, sum = 0
6221 05:55:56.740248 9, 0xFFFF, sum = 0
6222 05:55:56.743856 10, 0xFFFF, sum = 0
6223 05:55:56.744414 11, 0xFFFF, sum = 0
6224 05:55:56.746546 12, 0x0, sum = 1
6225 05:55:56.747004 13, 0x0, sum = 2
6226 05:55:56.750518 14, 0x0, sum = 3
6227 05:55:56.750975 15, 0x0, sum = 4
6228 05:55:56.751340 best_step = 13
6229 05:55:56.751669
6230 05:55:56.753478 ==
6231 05:55:56.756397 Dram Type= 6, Freq= 0, CH_0, rank 0
6232 05:55:56.760298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6233 05:55:56.760835 ==
6234 05:55:56.761212 RX Vref Scan: 1
6235 05:55:56.761548
6236 05:55:56.763066 RX Vref 0 -> 0, step: 1
6237 05:55:56.763516
6238 05:55:56.766343 RX Delay -359 -> 252, step: 8
6239 05:55:56.766792
6240 05:55:56.769662 Set Vref, RX VrefLevel [Byte0]: 52
6241 05:55:56.773345 [Byte1]: 48
6242 05:55:56.777032
6243 05:55:56.777482 Final RX Vref Byte 0 = 52 to rank0
6244 05:55:56.779943 Final RX Vref Byte 1 = 48 to rank0
6245 05:55:56.783503 Final RX Vref Byte 0 = 52 to rank1
6246 05:55:56.786878 Final RX Vref Byte 1 = 48 to rank1==
6247 05:55:56.790930 Dram Type= 6, Freq= 0, CH_0, rank 0
6248 05:55:56.796820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6249 05:55:56.797317 ==
6250 05:55:56.797644 DQS Delay:
6251 05:55:56.799915 DQS0 = 52, DQS1 = 68
6252 05:55:56.800349 DQM Delay:
6253 05:55:56.800676 DQM0 = 9, DQM1 = 17
6254 05:55:56.803678 DQ Delay:
6255 05:55:56.806974 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6256 05:55:56.807482 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6257 05:55:56.810019 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6258 05:55:56.813398 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6259 05:55:56.813808
6260 05:55:56.814128
6261 05:55:56.823527 [DQSOSCAuto] RK0, (LSB)MR18= 0x9393, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
6262 05:55:56.826689 CH0 RK0: MR19=C0C, MR18=9393
6263 05:55:56.833390 CH0_RK0: MR19=0xC0C, MR18=0x9393, DQSOSC=391, MR23=63, INC=386, DEC=257
6264 05:55:56.833887 ==
6265 05:55:56.836843 Dram Type= 6, Freq= 0, CH_0, rank 1
6266 05:55:56.840150 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6267 05:55:56.840660 ==
6268 05:55:56.844003 [Gating] SW mode calibration
6269 05:55:56.849955 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6270 05:55:56.853482 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6271 05:55:56.859997 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 05:55:56.863050 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 05:55:56.866823 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 05:55:56.873094 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6275 05:55:56.876534 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 05:55:56.879921 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 05:55:56.886643 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 05:55:56.889745 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6279 05:55:56.893175 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 05:55:56.896467 Total UI for P1: 0, mck2ui 16
6281 05:55:56.899566 best dqsien dly found for B0: ( 0, 10, 16)
6282 05:55:56.903349 Total UI for P1: 0, mck2ui 16
6283 05:55:56.905977 best dqsien dly found for B1: ( 0, 10, 24)
6284 05:55:56.909552 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6285 05:55:56.913183 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6286 05:55:56.916624
6287 05:55:56.919658 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6288 05:55:56.923395 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6289 05:55:56.926354 [Gating] SW calibration Done
6290 05:55:56.926765 ==
6291 05:55:56.929418 Dram Type= 6, Freq= 0, CH_0, rank 1
6292 05:55:56.932895 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6293 05:55:56.933341 ==
6294 05:55:56.933681 RX Vref Scan: 0
6295 05:55:56.936422
6296 05:55:56.936874 RX Vref 0 -> 0, step: 1
6297 05:55:56.937304
6298 05:55:56.939316 RX Delay -410 -> 252, step: 16
6299 05:55:56.942633 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6300 05:55:56.949392 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6301 05:55:56.953204 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6302 05:55:56.956244 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6303 05:55:56.959563 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6304 05:55:56.965862 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6305 05:55:56.969366 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6306 05:55:56.972347 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6307 05:55:56.975966 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6308 05:55:56.982459 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6309 05:55:56.986108 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6310 05:55:56.988965 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6311 05:55:56.992702 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6312 05:55:56.999282 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6313 05:55:57.002615 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6314 05:55:57.005823 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6315 05:55:57.006307 ==
6316 05:55:57.009384 Dram Type= 6, Freq= 0, CH_0, rank 1
6317 05:55:57.015928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6318 05:55:57.016423 ==
6319 05:55:57.016785 DQS Delay:
6320 05:55:57.019106 DQS0 = 43, DQS1 = 59
6321 05:55:57.019514 DQM Delay:
6322 05:55:57.019839 DQM0 = 7, DQM1 = 15
6323 05:55:57.022310 DQ Delay:
6324 05:55:57.025967 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6325 05:55:57.026376 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6326 05:55:57.029044 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6327 05:55:57.032451 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6328 05:55:57.035855
6329 05:55:57.036261
6330 05:55:57.036654 ==
6331 05:55:57.039057 Dram Type= 6, Freq= 0, CH_0, rank 1
6332 05:55:57.042066 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6333 05:55:57.042487 ==
6334 05:55:57.042816
6335 05:55:57.043118
6336 05:55:57.045374 TX Vref Scan disable
6337 05:55:57.045784 == TX Byte 0 ==
6338 05:55:57.048806 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6339 05:55:57.055182 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6340 05:55:57.055595 == TX Byte 1 ==
6341 05:55:57.058899 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6342 05:55:57.065597 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6343 05:55:57.066014 ==
6344 05:55:57.068798 Dram Type= 6, Freq= 0, CH_0, rank 1
6345 05:55:57.072279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6346 05:55:57.072967 ==
6347 05:55:57.073424
6348 05:55:57.073755
6349 05:55:57.075011 TX Vref Scan disable
6350 05:55:57.075421 == TX Byte 0 ==
6351 05:55:57.078773 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6352 05:55:57.085395 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6353 05:55:57.085905 == TX Byte 1 ==
6354 05:55:57.088266 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6355 05:55:57.095116 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6356 05:55:57.095643
6357 05:55:57.095973 [DATLAT]
6358 05:55:57.098612 Freq=400, CH0 RK1
6359 05:55:57.099024
6360 05:55:57.099347 DATLAT Default: 0xd
6361 05:55:57.101641 0, 0xFFFF, sum = 0
6362 05:55:57.102057 1, 0xFFFF, sum = 0
6363 05:55:57.104906 2, 0xFFFF, sum = 0
6364 05:55:57.105322 3, 0xFFFF, sum = 0
6365 05:55:57.108419 4, 0xFFFF, sum = 0
6366 05:55:57.108878 5, 0xFFFF, sum = 0
6367 05:55:57.111469 6, 0xFFFF, sum = 0
6368 05:55:57.111881 7, 0xFFFF, sum = 0
6369 05:55:57.114618 8, 0xFFFF, sum = 0
6370 05:55:57.115071 9, 0xFFFF, sum = 0
6371 05:55:57.118183 10, 0xFFFF, sum = 0
6372 05:55:57.118687 11, 0xFFFF, sum = 0
6373 05:55:57.121594 12, 0x0, sum = 1
6374 05:55:57.122033 13, 0x0, sum = 2
6375 05:55:57.124571 14, 0x0, sum = 3
6376 05:55:57.124889 15, 0x0, sum = 4
6377 05:55:57.128014 best_step = 13
6378 05:55:57.128331
6379 05:55:57.128702 ==
6380 05:55:57.131348 Dram Type= 6, Freq= 0, CH_0, rank 1
6381 05:55:57.134325 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6382 05:55:57.134618 ==
6383 05:55:57.137792 RX Vref Scan: 0
6384 05:55:57.138080
6385 05:55:57.138307 RX Vref 0 -> 0, step: 1
6386 05:55:57.138517
6387 05:55:57.141067 RX Delay -359 -> 252, step: 8
6388 05:55:57.149411 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6389 05:55:57.152375 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6390 05:55:57.155739 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6391 05:55:57.159385 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6392 05:55:57.165711 iDelay=217, Bit 4, Center -40 (-295 ~ 216) 512
6393 05:55:57.169241 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6394 05:55:57.172490 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6395 05:55:57.175800 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6396 05:55:57.182425 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6397 05:55:57.186002 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6398 05:55:57.189069 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6399 05:55:57.196158 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6400 05:55:57.199059 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6401 05:55:57.202838 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6402 05:55:57.205674 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6403 05:55:57.212212 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6404 05:55:57.212816 ==
6405 05:55:57.215352 Dram Type= 6, Freq= 0, CH_0, rank 1
6406 05:55:57.218777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6407 05:55:57.219330 ==
6408 05:55:57.219689 DQS Delay:
6409 05:55:57.222067 DQS0 = 52, DQS1 = 64
6410 05:55:57.222518 DQM Delay:
6411 05:55:57.225879 DQM0 = 9, DQM1 = 14
6412 05:55:57.226407 DQ Delay:
6413 05:55:57.228806 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6414 05:55:57.232237 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6415 05:55:57.235168 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6416 05:55:57.238587 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6417 05:55:57.239041
6418 05:55:57.239396
6419 05:55:57.245676 [DQSOSCAuto] RK1, (LSB)MR18= 0xb3b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6420 05:55:57.248451 CH0 RK1: MR19=C0C, MR18=B3B3
6421 05:55:57.255586 CH0_RK1: MR19=0xC0C, MR18=0xB3B3, DQSOSC=387, MR23=63, INC=394, DEC=262
6422 05:55:57.258156 [RxdqsGatingPostProcess] freq 400
6423 05:55:57.265327 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6424 05:55:57.268686 Pre-setting of DQS Precalculation
6425 05:55:57.271884 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6426 05:55:57.272430 ==
6427 05:55:57.275295 Dram Type= 6, Freq= 0, CH_1, rank 0
6428 05:55:57.278656 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6429 05:55:57.279210 ==
6430 05:55:57.284864 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6431 05:55:57.292288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6432 05:55:57.295017 [CA 0] Center 36 (8~64) winsize 57
6433 05:55:57.298065 [CA 1] Center 36 (8~64) winsize 57
6434 05:55:57.301564 [CA 2] Center 36 (8~64) winsize 57
6435 05:55:57.304998 [CA 3] Center 36 (8~64) winsize 57
6436 05:55:57.308286 [CA 4] Center 36 (8~64) winsize 57
6437 05:55:57.311808 [CA 5] Center 36 (8~64) winsize 57
6438 05:55:57.312359
6439 05:55:57.314635 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6440 05:55:57.315087
6441 05:55:57.317980 [CATrainingPosCal] consider 1 rank data
6442 05:55:57.321099 u2DelayCellTimex100 = 270/100 ps
6443 05:55:57.324855 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6444 05:55:57.327918 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6445 05:55:57.330936 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6446 05:55:57.334355 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6447 05:55:57.337821 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6448 05:55:57.341434 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6449 05:55:57.341981
6450 05:55:57.347879 CA PerBit enable=1, Macro0, CA PI delay=36
6451 05:55:57.348430
6452 05:55:57.348837 [CBTSetCACLKResult] CA Dly = 36
6453 05:55:57.350938 CS Dly: 1 (0~32)
6454 05:55:57.351469 ==
6455 05:55:57.354220 Dram Type= 6, Freq= 0, CH_1, rank 1
6456 05:55:57.357276 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6457 05:55:57.357761 ==
6458 05:55:57.363992 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6459 05:55:57.370768 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6460 05:55:57.374388 [CA 0] Center 36 (8~64) winsize 57
6461 05:55:57.377275 [CA 1] Center 36 (8~64) winsize 57
6462 05:55:57.380414 [CA 2] Center 36 (8~64) winsize 57
6463 05:55:57.384405 [CA 3] Center 36 (8~64) winsize 57
6464 05:55:57.385015 [CA 4] Center 36 (8~64) winsize 57
6465 05:55:57.387460 [CA 5] Center 36 (8~64) winsize 57
6466 05:55:57.388126
6467 05:55:57.393753 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6468 05:55:57.394208
6469 05:55:57.397218 [CATrainingPosCal] consider 2 rank data
6470 05:55:57.400509 u2DelayCellTimex100 = 270/100 ps
6471 05:55:57.403529 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6472 05:55:57.407280 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6473 05:55:57.410371 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6474 05:55:57.413695 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6475 05:55:57.416915 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6476 05:55:57.420087 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6477 05:55:57.420652
6478 05:55:57.423493 CA PerBit enable=1, Macro0, CA PI delay=36
6479 05:55:57.423908
6480 05:55:57.426547 [CBTSetCACLKResult] CA Dly = 36
6481 05:55:57.429892 CS Dly: 1 (0~32)
6482 05:55:57.430303
6483 05:55:57.433346 ----->DramcWriteLeveling(PI) begin...
6484 05:55:57.433767 ==
6485 05:55:57.436763 Dram Type= 6, Freq= 0, CH_1, rank 0
6486 05:55:57.440185 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6487 05:55:57.440607 ==
6488 05:55:57.443316 Write leveling (Byte 0): 32 => 0
6489 05:55:57.446501 Write leveling (Byte 1): 32 => 0
6490 05:55:57.449413 DramcWriteLeveling(PI) end<-----
6491 05:55:57.449963
6492 05:55:57.450438 ==
6493 05:55:57.453221 Dram Type= 6, Freq= 0, CH_1, rank 0
6494 05:55:57.456701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6495 05:55:57.457332 ==
6496 05:55:57.459607 [Gating] SW mode calibration
6497 05:55:57.466120 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6498 05:55:57.473071 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6499 05:55:57.476531 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 05:55:57.483022 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6501 05:55:57.485928 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 05:55:57.489453 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 05:55:57.496056 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 05:55:57.499221 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 05:55:57.502720 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 05:55:57.509681 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6507 05:55:57.512732 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6508 05:55:57.515472 Total UI for P1: 0, mck2ui 16
6509 05:55:57.519134 best dqsien dly found for B0: ( 0, 10, 16)
6510 05:55:57.522306 Total UI for P1: 0, mck2ui 16
6511 05:55:57.525459 best dqsien dly found for B1: ( 0, 10, 16)
6512 05:55:57.529113 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6513 05:55:57.532247 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6514 05:55:57.532863
6515 05:55:57.536173 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6516 05:55:57.538657 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6517 05:55:57.542030 [Gating] SW calibration Done
6518 05:55:57.542488 ==
6519 05:55:57.545222 Dram Type= 6, Freq= 0, CH_1, rank 0
6520 05:55:57.552210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6521 05:55:57.552829 ==
6522 05:55:57.553343 RX Vref Scan: 0
6523 05:55:57.553854
6524 05:55:57.555310 RX Vref 0 -> 0, step: 1
6525 05:55:57.555769
6526 05:55:57.558749 RX Delay -410 -> 252, step: 16
6527 05:55:57.562051 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6528 05:55:57.565158 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6529 05:55:57.571732 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6530 05:55:57.575056 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6531 05:55:57.578546 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6532 05:55:57.581591 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6533 05:55:57.588304 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6534 05:55:57.591964 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6535 05:55:57.594912 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6536 05:55:57.597973 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6537 05:55:57.604697 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6538 05:55:57.607925 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6539 05:55:57.611280 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6540 05:55:57.614999 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6541 05:55:57.621439 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6542 05:55:57.625063 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6543 05:55:57.625526 ==
6544 05:55:57.628104 Dram Type= 6, Freq= 0, CH_1, rank 0
6545 05:55:57.631352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6546 05:55:57.631923 ==
6547 05:55:57.634616 DQS Delay:
6548 05:55:57.635182 DQS0 = 43, DQS1 = 59
6549 05:55:57.638228 DQM Delay:
6550 05:55:57.638686 DQM0 = 6, DQM1 = 15
6551 05:55:57.639049 DQ Delay:
6552 05:55:57.641306 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6553 05:55:57.644393 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6554 05:55:57.648057 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6555 05:55:57.651203 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6556 05:55:57.651761
6557 05:55:57.652131
6558 05:55:57.652468 ==
6559 05:55:57.654614 Dram Type= 6, Freq= 0, CH_1, rank 0
6560 05:55:57.661298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6561 05:55:57.661840 ==
6562 05:55:57.662209
6563 05:55:57.662548
6564 05:55:57.662870 TX Vref Scan disable
6565 05:55:57.664864 == TX Byte 0 ==
6566 05:55:57.667497 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6567 05:55:57.671354 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6568 05:55:57.674509 == TX Byte 1 ==
6569 05:55:57.677240 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6570 05:55:57.681054 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6571 05:55:57.684066 ==
6572 05:55:57.687628 Dram Type= 6, Freq= 0, CH_1, rank 0
6573 05:55:57.690723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6574 05:55:57.691373 ==
6575 05:55:57.691927
6576 05:55:57.692293
6577 05:55:57.694258 TX Vref Scan disable
6578 05:55:57.694813 == TX Byte 0 ==
6579 05:55:57.697201 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6580 05:55:57.703647 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6581 05:55:57.704205 == TX Byte 1 ==
6582 05:55:57.707099 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6583 05:55:57.713709 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6584 05:55:57.714273
6585 05:55:57.714642 [DATLAT]
6586 05:55:57.714983 Freq=400, CH1 RK0
6587 05:55:57.717063
6588 05:55:57.717521 DATLAT Default: 0xf
6589 05:55:57.720146 0, 0xFFFF, sum = 0
6590 05:55:57.720612 1, 0xFFFF, sum = 0
6591 05:55:57.723558 2, 0xFFFF, sum = 0
6592 05:55:57.724032 3, 0xFFFF, sum = 0
6593 05:55:57.726843 4, 0xFFFF, sum = 0
6594 05:55:57.727563 5, 0xFFFF, sum = 0
6595 05:55:57.730671 6, 0xFFFF, sum = 0
6596 05:55:57.731241 7, 0xFFFF, sum = 0
6597 05:55:57.733340 8, 0xFFFF, sum = 0
6598 05:55:57.733808 9, 0xFFFF, sum = 0
6599 05:55:57.736897 10, 0xFFFF, sum = 0
6600 05:55:57.737522 11, 0xFFFF, sum = 0
6601 05:55:57.740348 12, 0x0, sum = 1
6602 05:55:57.740969 13, 0x0, sum = 2
6603 05:55:57.743179 14, 0x0, sum = 3
6604 05:55:57.743647 15, 0x0, sum = 4
6605 05:55:57.746445 best_step = 13
6606 05:55:57.746905
6607 05:55:57.747269 ==
6608 05:55:57.750082 Dram Type= 6, Freq= 0, CH_1, rank 0
6609 05:55:57.753710 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6610 05:55:57.754532 ==
6611 05:55:57.756863 RX Vref Scan: 1
6612 05:55:57.757502
6613 05:55:57.758084 RX Vref 0 -> 0, step: 1
6614 05:55:57.758644
6615 05:55:57.759905 RX Delay -359 -> 252, step: 8
6616 05:55:57.760365
6617 05:55:57.763390 Set Vref, RX VrefLevel [Byte0]: 55
6618 05:55:57.766250 [Byte1]: 49
6619 05:55:57.771143
6620 05:55:57.771623 Final RX Vref Byte 0 = 55 to rank0
6621 05:55:57.774701 Final RX Vref Byte 1 = 49 to rank0
6622 05:55:57.777708 Final RX Vref Byte 0 = 55 to rank1
6623 05:55:57.781263 Final RX Vref Byte 1 = 49 to rank1==
6624 05:55:57.784867 Dram Type= 6, Freq= 0, CH_1, rank 0
6625 05:55:57.790859 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6626 05:55:57.791324 ==
6627 05:55:57.791698 DQS Delay:
6628 05:55:57.794164 DQS0 = 48, DQS1 = 64
6629 05:55:57.794624 DQM Delay:
6630 05:55:57.794989 DQM0 = 8, DQM1 = 15
6631 05:55:57.797842 DQ Delay:
6632 05:55:57.801116 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6633 05:55:57.801575 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6634 05:55:57.804391 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6635 05:55:57.807805 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6636 05:55:57.808356
6637 05:55:57.808773
6638 05:55:57.817503 [DQSOSCAuto] RK0, (LSB)MR18= 0xd8d8, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6639 05:55:57.821186 CH1 RK0: MR19=C0C, MR18=D8D8
6640 05:55:57.827875 CH1_RK0: MR19=0xC0C, MR18=0xD8D8, DQSOSC=383, MR23=63, INC=402, DEC=268
6641 05:55:57.828428 ==
6642 05:55:57.830995 Dram Type= 6, Freq= 0, CH_1, rank 1
6643 05:55:57.833733 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6644 05:55:57.834201 ==
6645 05:55:57.837402 [Gating] SW mode calibration
6646 05:55:57.843906 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6647 05:55:57.850530 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6648 05:55:57.854255 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6649 05:55:57.857803 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6650 05:55:57.860518 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6651 05:55:57.867311 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6652 05:55:57.870796 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 05:55:57.873737 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 05:55:57.880575 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 05:55:57.884188 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6656 05:55:57.887634 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 05:55:57.890890 Total UI for P1: 0, mck2ui 16
6658 05:55:57.893925 best dqsien dly found for B0: ( 0, 10, 16)
6659 05:55:57.896703 Total UI for P1: 0, mck2ui 16
6660 05:55:57.900771 best dqsien dly found for B1: ( 0, 10, 16)
6661 05:55:57.903638 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6662 05:55:57.910502 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6663 05:55:57.910960
6664 05:55:57.914036 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6665 05:55:57.916983 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6666 05:55:57.920439 [Gating] SW calibration Done
6667 05:55:57.920940 ==
6668 05:55:57.923602 Dram Type= 6, Freq= 0, CH_1, rank 1
6669 05:55:57.927044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6670 05:55:57.927501 ==
6671 05:55:57.930475 RX Vref Scan: 0
6672 05:55:57.930929
6673 05:55:57.931288 RX Vref 0 -> 0, step: 1
6674 05:55:57.931625
6675 05:55:57.933998 RX Delay -410 -> 252, step: 16
6676 05:55:57.936847 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6677 05:55:57.943915 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6678 05:55:57.946891 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6679 05:55:57.950157 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6680 05:55:57.953492 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6681 05:55:57.959807 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6682 05:55:57.962852 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6683 05:55:57.966404 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6684 05:55:57.970008 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6685 05:55:57.976261 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6686 05:55:57.979950 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6687 05:55:57.983086 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6688 05:55:57.990162 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6689 05:55:57.992643 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6690 05:55:57.996193 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6691 05:55:57.999749 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6692 05:55:58.000164 ==
6693 05:55:58.003131 Dram Type= 6, Freq= 0, CH_1, rank 1
6694 05:55:58.009491 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6695 05:55:58.009951 ==
6696 05:55:58.010315 DQS Delay:
6697 05:55:58.012877 DQS0 = 43, DQS1 = 59
6698 05:55:58.013404 DQM Delay:
6699 05:55:58.016297 DQM0 = 9, DQM1 = 17
6700 05:55:58.016822 DQ Delay:
6701 05:55:58.019571 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6702 05:55:58.022736 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6703 05:55:58.023152 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6704 05:55:58.029297 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6705 05:55:58.029810
6706 05:55:58.030139
6707 05:55:58.030441 ==
6708 05:55:58.032985 Dram Type= 6, Freq= 0, CH_1, rank 1
6709 05:55:58.036276 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6710 05:55:58.036897 ==
6711 05:55:58.037245
6712 05:55:58.037548
6713 05:55:58.039344 TX Vref Scan disable
6714 05:55:58.039778 == TX Byte 0 ==
6715 05:55:58.042574 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6716 05:55:58.049375 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6717 05:55:58.049893 == TX Byte 1 ==
6718 05:55:58.052924 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6719 05:55:58.059431 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6720 05:55:58.059850 ==
6721 05:55:58.062469 Dram Type= 6, Freq= 0, CH_1, rank 1
6722 05:55:58.065739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6723 05:55:58.066158 ==
6724 05:55:58.066487
6725 05:55:58.066793
6726 05:55:58.068858 TX Vref Scan disable
6727 05:55:58.069272 == TX Byte 0 ==
6728 05:55:58.076040 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6729 05:55:58.079254 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6730 05:55:58.079769 == TX Byte 1 ==
6731 05:55:58.085506 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6732 05:55:58.089439 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6733 05:55:58.089961
6734 05:55:58.090294 [DATLAT]
6735 05:55:58.092015 Freq=400, CH1 RK1
6736 05:55:58.092429
6737 05:55:58.092815 DATLAT Default: 0xd
6738 05:55:58.095359 0, 0xFFFF, sum = 0
6739 05:55:58.095775 1, 0xFFFF, sum = 0
6740 05:55:58.099027 2, 0xFFFF, sum = 0
6741 05:55:58.099542 3, 0xFFFF, sum = 0
6742 05:55:58.102254 4, 0xFFFF, sum = 0
6743 05:55:58.102774 5, 0xFFFF, sum = 0
6744 05:55:58.105466 6, 0xFFFF, sum = 0
6745 05:55:58.105884 7, 0xFFFF, sum = 0
6746 05:55:58.108376 8, 0xFFFF, sum = 0
6747 05:55:58.108909 9, 0xFFFF, sum = 0
6748 05:55:58.112192 10, 0xFFFF, sum = 0
6749 05:55:58.115376 11, 0xFFFF, sum = 0
6750 05:55:58.115798 12, 0x0, sum = 1
6751 05:55:58.116130 13, 0x0, sum = 2
6752 05:55:58.118733 14, 0x0, sum = 3
6753 05:55:58.119280 15, 0x0, sum = 4
6754 05:55:58.121970 best_step = 13
6755 05:55:58.122395
6756 05:55:58.122722 ==
6757 05:55:58.125009 Dram Type= 6, Freq= 0, CH_1, rank 1
6758 05:55:58.128601 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6759 05:55:58.129171 ==
6760 05:55:58.131994 RX Vref Scan: 0
6761 05:55:58.132503
6762 05:55:58.132881 RX Vref 0 -> 0, step: 1
6763 05:55:58.133198
6764 05:55:58.135320 RX Delay -359 -> 252, step: 8
6765 05:55:58.143184 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6766 05:55:58.146920 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6767 05:55:58.150087 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6768 05:55:58.153397 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6769 05:55:58.160016 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6770 05:55:58.163279 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6771 05:55:58.166478 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6772 05:55:58.173191 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6773 05:55:58.176435 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6774 05:55:58.179877 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6775 05:55:58.182872 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6776 05:55:58.189762 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6777 05:55:58.193160 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6778 05:55:58.196272 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6779 05:55:58.199638 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6780 05:55:58.205829 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6781 05:55:58.206293 ==
6782 05:55:58.209359 Dram Type= 6, Freq= 0, CH_1, rank 1
6783 05:55:58.212880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6784 05:55:58.213343 ==
6785 05:55:58.213709 DQS Delay:
6786 05:55:58.215853 DQS0 = 48, DQS1 = 64
6787 05:55:58.216319 DQM Delay:
6788 05:55:58.219098 DQM0 = 9, DQM1 = 15
6789 05:55:58.219514 DQ Delay:
6790 05:55:58.222737 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6791 05:55:58.225478 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6792 05:55:58.229180 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6793 05:55:58.232822 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6794 05:55:58.233243
6795 05:55:58.233710
6796 05:55:58.239369 [DQSOSCAuto] RK1, (LSB)MR18= 0xa8a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6797 05:55:58.242692 CH1 RK1: MR19=C0C, MR18=A8A8
6798 05:55:58.249130 CH1_RK1: MR19=0xC0C, MR18=0xA8A8, DQSOSC=388, MR23=63, INC=392, DEC=261
6799 05:55:58.252997 [RxdqsGatingPostProcess] freq 400
6800 05:55:58.259463 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6801 05:55:58.262514 Pre-setting of DQS Precalculation
6802 05:55:58.265576 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6803 05:55:58.272424 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6804 05:55:58.278980 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6805 05:55:58.282136
6806 05:55:58.282592
6807 05:55:58.282952 [Calibration Summary] 800 Mbps
6808 05:55:58.285272 CH 0, Rank 0
6809 05:55:58.285841 SW Impedance : PASS
6810 05:55:58.288669 DUTY Scan : NO K
6811 05:55:58.292113 ZQ Calibration : PASS
6812 05:55:58.292574 Jitter Meter : NO K
6813 05:55:58.295449 CBT Training : PASS
6814 05:55:58.298993 Write leveling : PASS
6815 05:55:58.299551 RX DQS gating : PASS
6816 05:55:58.302088 RX DQ/DQS(RDDQC) : PASS
6817 05:55:58.305197 TX DQ/DQS : PASS
6818 05:55:58.305813 RX DATLAT : PASS
6819 05:55:58.308914 RX DQ/DQS(Engine): PASS
6820 05:55:58.312054 TX OE : NO K
6821 05:55:58.312515 All Pass.
6822 05:55:58.312937
6823 05:55:58.313281 CH 0, Rank 1
6824 05:55:58.315498 SW Impedance : PASS
6825 05:55:58.318641 DUTY Scan : NO K
6826 05:55:58.319103 ZQ Calibration : PASS
6827 05:55:58.321743 Jitter Meter : NO K
6828 05:55:58.325084 CBT Training : PASS
6829 05:55:58.325604 Write leveling : NO K
6830 05:55:58.328819 RX DQS gating : PASS
6831 05:55:58.331782 RX DQ/DQS(RDDQC) : PASS
6832 05:55:58.332345 TX DQ/DQS : PASS
6833 05:55:58.334994 RX DATLAT : PASS
6834 05:55:58.335644 RX DQ/DQS(Engine): PASS
6835 05:55:58.338177 TX OE : NO K
6836 05:55:58.338742 All Pass.
6837 05:55:58.339111
6838 05:55:58.341504 CH 1, Rank 0
6839 05:55:58.341962 SW Impedance : PASS
6840 05:55:58.345088 DUTY Scan : NO K
6841 05:55:58.348004 ZQ Calibration : PASS
6842 05:55:58.348466 Jitter Meter : NO K
6843 05:55:58.351599 CBT Training : PASS
6844 05:55:58.354952 Write leveling : PASS
6845 05:55:58.355512 RX DQS gating : PASS
6846 05:55:58.358203 RX DQ/DQS(RDDQC) : PASS
6847 05:55:58.361476 TX DQ/DQS : PASS
6848 05:55:58.362029 RX DATLAT : PASS
6849 05:55:58.364910 RX DQ/DQS(Engine): PASS
6850 05:55:58.368367 TX OE : NO K
6851 05:55:58.368971 All Pass.
6852 05:55:58.369351
6853 05:55:58.369694 CH 1, Rank 1
6854 05:55:58.371479 SW Impedance : PASS
6855 05:55:58.374532 DUTY Scan : NO K
6856 05:55:58.374988 ZQ Calibration : PASS
6857 05:55:58.378225 Jitter Meter : NO K
6858 05:55:58.381320 CBT Training : PASS
6859 05:55:58.381872 Write leveling : NO K
6860 05:55:58.384470 RX DQS gating : PASS
6861 05:55:58.388021 RX DQ/DQS(RDDQC) : PASS
6862 05:55:58.388620 TX DQ/DQS : PASS
6863 05:55:58.391460 RX DATLAT : PASS
6864 05:55:58.394536 RX DQ/DQS(Engine): PASS
6865 05:55:58.395010 TX OE : NO K
6866 05:55:58.395374 All Pass.
6867 05:55:58.398297
6868 05:55:58.398848 DramC Write-DBI off
6869 05:55:58.401313 PER_BANK_REFRESH: Hybrid Mode
6870 05:55:58.401769 TX_TRACKING: ON
6871 05:55:58.411062 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6872 05:55:58.414337 [FAST_K] Save calibration result to emmc
6873 05:55:58.417501 dramc_set_vcore_voltage set vcore to 725000
6874 05:55:58.421611 Read voltage for 1600, 0
6875 05:55:58.422164 Vio18 = 0
6876 05:55:58.424464 Vcore = 725000
6877 05:55:58.424957 Vdram = 0
6878 05:55:58.425320 Vddq = 0
6879 05:55:58.425654 Vmddr = 0
6880 05:55:58.431262 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6881 05:55:58.437585 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6882 05:55:58.438126 MEM_TYPE=3, freq_sel=13
6883 05:55:58.440977 sv_algorithm_assistance_LP4_3733
6884 05:55:58.444186 ============ PULL DRAM RESETB DOWN ============
6885 05:55:58.451384 ========== PULL DRAM RESETB DOWN end =========
6886 05:55:58.453785 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6887 05:55:58.457260 ===================================
6888 05:55:58.460575 LPDDR4 DRAM CONFIGURATION
6889 05:55:58.464122 ===================================
6890 05:55:58.464670 EX_ROW_EN[0] = 0x0
6891 05:55:58.467107 EX_ROW_EN[1] = 0x0
6892 05:55:58.467561 LP4Y_EN = 0x0
6893 05:55:58.471143 WORK_FSP = 0x1
6894 05:55:58.473672 WL = 0x5
6895 05:55:58.474145 RL = 0x5
6896 05:55:58.477108 BL = 0x2
6897 05:55:58.477562 RPST = 0x0
6898 05:55:58.480652 RD_PRE = 0x0
6899 05:55:58.481142 WR_PRE = 0x1
6900 05:55:58.483877 WR_PST = 0x1
6901 05:55:58.484332 DBI_WR = 0x0
6902 05:55:58.487710 DBI_RD = 0x0
6903 05:55:58.488276 OTF = 0x1
6904 05:55:58.490790 ===================================
6905 05:55:58.494136 ===================================
6906 05:55:58.497193 ANA top config
6907 05:55:58.500604 ===================================
6908 05:55:58.501104 DLL_ASYNC_EN = 0
6909 05:55:58.503680 ALL_SLAVE_EN = 0
6910 05:55:58.506979 NEW_RANK_MODE = 1
6911 05:55:58.510788 DLL_IDLE_MODE = 1
6912 05:55:58.513353 LP45_APHY_COMB_EN = 1
6913 05:55:58.513768 TX_ODT_DIS = 0
6914 05:55:58.516755 NEW_8X_MODE = 1
6915 05:55:58.520258 ===================================
6916 05:55:58.523766 ===================================
6917 05:55:58.526962 data_rate = 3200
6918 05:55:58.530741 CKR = 1
6919 05:55:58.533943 DQ_P2S_RATIO = 8
6920 05:55:58.537139 ===================================
6921 05:55:58.537695 CA_P2S_RATIO = 8
6922 05:55:58.540115 DQ_CA_OPEN = 0
6923 05:55:58.543844 DQ_SEMI_OPEN = 0
6924 05:55:58.547019 CA_SEMI_OPEN = 0
6925 05:55:58.550184 CA_FULL_RATE = 0
6926 05:55:58.553675 DQ_CKDIV4_EN = 0
6927 05:55:58.554225 CA_CKDIV4_EN = 0
6928 05:55:58.556646 CA_PREDIV_EN = 0
6929 05:55:58.560234 PH8_DLY = 12
6930 05:55:58.563712 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6931 05:55:58.566879 DQ_AAMCK_DIV = 4
6932 05:55:58.570332 CA_AAMCK_DIV = 4
6933 05:55:58.570882 CA_ADMCK_DIV = 4
6934 05:55:58.573483 DQ_TRACK_CA_EN = 0
6935 05:55:58.576664 CA_PICK = 1600
6936 05:55:58.580075 CA_MCKIO = 1600
6937 05:55:58.583150 MCKIO_SEMI = 0
6938 05:55:58.586699 PLL_FREQ = 3068
6939 05:55:58.589711 DQ_UI_PI_RATIO = 32
6940 05:55:58.593310 CA_UI_PI_RATIO = 0
6941 05:55:58.596615 ===================================
6942 05:55:58.600138 ===================================
6943 05:55:58.600689 memory_type:LPDDR4
6944 05:55:58.603425 GP_NUM : 10
6945 05:55:58.603974 SRAM_EN : 1
6946 05:55:58.606547 MD32_EN : 0
6947 05:55:58.609843 ===================================
6948 05:55:58.613050 [ANA_INIT] >>>>>>>>>>>>>>
6949 05:55:58.616382 <<<<<< [CONFIGURE PHASE]: ANA_TX
6950 05:55:58.619895 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6951 05:55:58.623219 ===================================
6952 05:55:58.626279 data_rate = 3200,PCW = 0X7600
6953 05:55:58.629858 ===================================
6954 05:55:58.632992 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6955 05:55:58.636613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6956 05:55:58.642863 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6957 05:55:58.645677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6958 05:55:58.649639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6959 05:55:58.652964 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6960 05:55:58.656085 [ANA_INIT] flow start
6961 05:55:58.659296 [ANA_INIT] PLL >>>>>>>>
6962 05:55:58.659840 [ANA_INIT] PLL <<<<<<<<
6963 05:55:58.662788 [ANA_INIT] MIDPI >>>>>>>>
6964 05:55:58.665667 [ANA_INIT] MIDPI <<<<<<<<
6965 05:55:58.669286 [ANA_INIT] DLL >>>>>>>>
6966 05:55:58.669830 [ANA_INIT] DLL <<<<<<<<
6967 05:55:58.672512 [ANA_INIT] flow end
6968 05:55:58.675502 ============ LP4 DIFF to SE enter ============
6969 05:55:58.678855 ============ LP4 DIFF to SE exit ============
6970 05:55:58.682905 [ANA_INIT] <<<<<<<<<<<<<
6971 05:55:58.685474 [Flow] Enable top DCM control >>>>>
6972 05:55:58.688910 [Flow] Enable top DCM control <<<<<
6973 05:55:58.692227 Enable DLL master slave shuffle
6974 05:55:58.698868 ==============================================================
6975 05:55:58.699428 Gating Mode config
6976 05:55:58.705335 ==============================================================
6977 05:55:58.705877 Config description:
6978 05:55:58.715458 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6979 05:55:58.721933 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6980 05:55:58.728887 SELPH_MODE 0: By rank 1: By Phase
6981 05:55:58.732294 ==============================================================
6982 05:55:58.735368 GAT_TRACK_EN = 1
6983 05:55:58.738249 RX_GATING_MODE = 2
6984 05:55:58.741691 RX_GATING_TRACK_MODE = 2
6985 05:55:58.745310 SELPH_MODE = 1
6986 05:55:58.748906 PICG_EARLY_EN = 1
6987 05:55:58.752112 VALID_LAT_VALUE = 1
6988 05:55:58.758656 ==============================================================
6989 05:55:58.761913 Enter into Gating configuration >>>>
6990 05:55:58.765510 Exit from Gating configuration <<<<
6991 05:55:58.766063 Enter into DVFS_PRE_config >>>>>
6992 05:55:58.778012 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6993 05:55:58.781205 Exit from DVFS_PRE_config <<<<<
6994 05:55:58.784551 Enter into PICG configuration >>>>
6995 05:55:58.787973 Exit from PICG configuration <<<<
6996 05:55:58.791311 [RX_INPUT] configuration >>>>>
6997 05:55:58.791869 [RX_INPUT] configuration <<<<<
6998 05:55:58.797847 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6999 05:55:58.804665 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7000 05:55:58.807728 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7001 05:55:58.814092 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7002 05:55:58.820861 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7003 05:55:58.827672 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7004 05:55:58.831029 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7005 05:55:58.834085 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7006 05:55:58.840781 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7007 05:55:58.844028 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7008 05:55:58.847356 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7009 05:55:58.854374 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7010 05:55:58.857284 ===================================
7011 05:55:58.857746 LPDDR4 DRAM CONFIGURATION
7012 05:55:58.861284 ===================================
7013 05:55:58.863962 EX_ROW_EN[0] = 0x0
7014 05:55:58.867479 EX_ROW_EN[1] = 0x0
7015 05:55:58.868100 LP4Y_EN = 0x0
7016 05:55:58.870459 WORK_FSP = 0x1
7017 05:55:58.871016 WL = 0x5
7018 05:55:58.873869 RL = 0x5
7019 05:55:58.874330 BL = 0x2
7020 05:55:58.877286 RPST = 0x0
7021 05:55:58.877746 RD_PRE = 0x0
7022 05:55:58.880834 WR_PRE = 0x1
7023 05:55:58.881381 WR_PST = 0x1
7024 05:55:58.884103 DBI_WR = 0x0
7025 05:55:58.884658 DBI_RD = 0x0
7026 05:55:58.886994 OTF = 0x1
7027 05:55:58.890114 ===================================
7028 05:55:58.893557 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7029 05:55:58.896935 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7030 05:55:58.903790 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7031 05:55:58.906575 ===================================
7032 05:55:58.907034 LPDDR4 DRAM CONFIGURATION
7033 05:55:58.910341 ===================================
7034 05:55:58.913681 EX_ROW_EN[0] = 0x10
7035 05:55:58.917008 EX_ROW_EN[1] = 0x0
7036 05:55:58.917589 LP4Y_EN = 0x0
7037 05:55:58.919973 WORK_FSP = 0x1
7038 05:55:58.920430 WL = 0x5
7039 05:55:58.923523 RL = 0x5
7040 05:55:58.924084 BL = 0x2
7041 05:55:58.926595 RPST = 0x0
7042 05:55:58.927054 RD_PRE = 0x0
7043 05:55:58.929848 WR_PRE = 0x1
7044 05:55:58.930307 WR_PST = 0x1
7045 05:55:58.933492 DBI_WR = 0x0
7046 05:55:58.934250 DBI_RD = 0x0
7047 05:55:58.936437 OTF = 0x1
7048 05:55:58.939962 ===================================
7049 05:55:58.946480 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7050 05:55:58.946944 ==
7051 05:55:58.950281 Dram Type= 6, Freq= 0, CH_0, rank 0
7052 05:55:58.953296 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7053 05:55:58.953762 ==
7054 05:55:58.956605 [Duty_Offset_Calibration]
7055 05:55:58.957202 B0:0 B1:2 CA:1
7056 05:55:58.957577
7057 05:55:58.959868 [DutyScan_Calibration_Flow] k_type=0
7058 05:55:58.970323
7059 05:55:58.971032 ==CLK 0==
7060 05:55:58.973264 Final CLK duty delay cell = 0
7061 05:55:58.977037 [0] MAX Duty = 5156%(X100), DQS PI = 20
7062 05:55:58.980624 [0] MIN Duty = 4938%(X100), DQS PI = 54
7063 05:55:58.983827 [0] AVG Duty = 5047%(X100)
7064 05:55:58.984379
7065 05:55:58.986988 CH0 CLK Duty spec in!! Max-Min= 218%
7066 05:55:58.989830 [DutyScan_Calibration_Flow] ====Done====
7067 05:55:58.990300
7068 05:55:58.993558 [DutyScan_Calibration_Flow] k_type=1
7069 05:55:59.010299
7070 05:55:59.010865 ==DQS 0 ==
7071 05:55:59.013794 Final DQS duty delay cell = 0
7072 05:55:59.017207 [0] MAX Duty = 5156%(X100), DQS PI = 32
7073 05:55:59.020308 [0] MIN Duty = 5031%(X100), DQS PI = 8
7074 05:55:59.023597 [0] AVG Duty = 5093%(X100)
7075 05:55:59.024157
7076 05:55:59.024524 ==DQS 1 ==
7077 05:55:59.026979 Final DQS duty delay cell = 0
7078 05:55:59.029985 [0] MAX Duty = 5031%(X100), DQS PI = 4
7079 05:55:59.033402 [0] MIN Duty = 4876%(X100), DQS PI = 16
7080 05:55:59.033864 [0] AVG Duty = 4953%(X100)
7081 05:55:59.036819
7082 05:55:59.040367 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7083 05:55:59.040985
7084 05:55:59.043180 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7085 05:55:59.046741 [DutyScan_Calibration_Flow] ====Done====
7086 05:55:59.047205
7087 05:55:59.050099 [DutyScan_Calibration_Flow] k_type=3
7088 05:55:59.067455
7089 05:55:59.068068 ==DQM 0 ==
7090 05:55:59.070437 Final DQM duty delay cell = 0
7091 05:55:59.073792 [0] MAX Duty = 5187%(X100), DQS PI = 24
7092 05:55:59.077032 [0] MIN Duty = 4907%(X100), DQS PI = 56
7093 05:55:59.080285 [0] AVG Duty = 5047%(X100)
7094 05:55:59.080791
7095 05:55:59.081173 ==DQM 1 ==
7096 05:55:59.083659 Final DQM duty delay cell = 0
7097 05:55:59.086940 [0] MAX Duty = 5031%(X100), DQS PI = 50
7098 05:55:59.090419 [0] MIN Duty = 4782%(X100), DQS PI = 12
7099 05:55:59.093856 [0] AVG Duty = 4906%(X100)
7100 05:55:59.094414
7101 05:55:59.096741 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7102 05:55:59.097214
7103 05:55:59.100149 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7104 05:55:59.103498 [DutyScan_Calibration_Flow] ====Done====
7105 05:55:59.103958
7106 05:55:59.106618 [DutyScan_Calibration_Flow] k_type=2
7107 05:55:59.123700
7108 05:55:59.124252 ==DQ 0 ==
7109 05:55:59.127491 Final DQ duty delay cell = 0
7110 05:55:59.130339 [0] MAX Duty = 5218%(X100), DQS PI = 18
7111 05:55:59.133983 [0] MIN Duty = 4938%(X100), DQS PI = 56
7112 05:55:59.134539 [0] AVG Duty = 5078%(X100)
7113 05:55:59.136849
7114 05:55:59.137310 ==DQ 1 ==
7115 05:55:59.140548 Final DQ duty delay cell = -4
7116 05:55:59.143672 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7117 05:55:59.146970 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7118 05:55:59.150080 [-4] AVG Duty = 4953%(X100)
7119 05:55:59.150538
7120 05:55:59.153428 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7121 05:55:59.153887
7122 05:55:59.156918 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7123 05:55:59.159987 [DutyScan_Calibration_Flow] ====Done====
7124 05:55:59.160535 ==
7125 05:55:59.163344 Dram Type= 6, Freq= 0, CH_1, rank 0
7126 05:55:59.166868 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7127 05:55:59.167425 ==
7128 05:55:59.169723 [Duty_Offset_Calibration]
7129 05:55:59.170181 B0:0 B1:4 CA:-5
7130 05:55:59.170549
7131 05:55:59.173414 [DutyScan_Calibration_Flow] k_type=0
7132 05:55:59.184428
7133 05:55:59.185041 ==CLK 0==
7134 05:55:59.187658 Final CLK duty delay cell = 0
7135 05:55:59.190897 [0] MAX Duty = 5156%(X100), DQS PI = 20
7136 05:55:59.194420 [0] MIN Duty = 4906%(X100), DQS PI = 50
7137 05:55:59.197417 [0] AVG Duty = 5031%(X100)
7138 05:55:59.197872
7139 05:55:59.200613 CH1 CLK Duty spec in!! Max-Min= 250%
7140 05:55:59.204192 [DutyScan_Calibration_Flow] ====Done====
7141 05:55:59.204833
7142 05:55:59.207627 [DutyScan_Calibration_Flow] k_type=1
7143 05:55:59.223360
7144 05:55:59.223909 ==DQS 0 ==
7145 05:55:59.226502 Final DQS duty delay cell = 0
7146 05:55:59.230232 [0] MAX Duty = 5187%(X100), DQS PI = 20
7147 05:55:59.233333 [0] MIN Duty = 4876%(X100), DQS PI = 42
7148 05:55:59.236356 [0] AVG Duty = 5031%(X100)
7149 05:55:59.236850
7150 05:55:59.237221 ==DQS 1 ==
7151 05:55:59.239895 Final DQS duty delay cell = -4
7152 05:55:59.242982 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7153 05:55:59.246754 [-4] MIN Duty = 4875%(X100), DQS PI = 38
7154 05:55:59.249706 [-4] AVG Duty = 4937%(X100)
7155 05:55:59.250166
7156 05:55:59.252682 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7157 05:55:59.253188
7158 05:55:59.256101 CH1 DQS 1 Duty spec in!! Max-Min= 125%
7159 05:55:59.259675 [DutyScan_Calibration_Flow] ====Done====
7160 05:55:59.260136
7161 05:55:59.262899 [DutyScan_Calibration_Flow] k_type=3
7162 05:55:59.278876
7163 05:55:59.279551 ==DQM 0 ==
7164 05:55:59.282207 Final DQM duty delay cell = -4
7165 05:55:59.285537 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7166 05:55:59.288978 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7167 05:55:59.292354 [-4] AVG Duty = 4937%(X100)
7168 05:55:59.292998
7169 05:55:59.293520 ==DQM 1 ==
7170 05:55:59.295482 Final DQM duty delay cell = -4
7171 05:55:59.298699 [-4] MAX Duty = 5093%(X100), DQS PI = 18
7172 05:55:59.302246 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7173 05:55:59.305195 [-4] AVG Duty = 5000%(X100)
7174 05:55:59.305702
7175 05:55:59.308659 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7176 05:55:59.309217
7177 05:55:59.311696 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7178 05:55:59.315292 [DutyScan_Calibration_Flow] ====Done====
7179 05:55:59.315790
7180 05:55:59.318263 [DutyScan_Calibration_Flow] k_type=2
7181 05:55:59.336659
7182 05:55:59.337331 ==DQ 0 ==
7183 05:55:59.339727 Final DQ duty delay cell = 0
7184 05:55:59.343074 [0] MAX Duty = 5093%(X100), DQS PI = 20
7185 05:55:59.346217 [0] MIN Duty = 4938%(X100), DQS PI = 48
7186 05:55:59.346520 [0] AVG Duty = 5015%(X100)
7187 05:55:59.349400
7188 05:55:59.349622 ==DQ 1 ==
7189 05:55:59.353137 Final DQ duty delay cell = 0
7190 05:55:59.356052 [0] MAX Duty = 5031%(X100), DQS PI = 4
7191 05:55:59.359297 [0] MIN Duty = 4876%(X100), DQS PI = 26
7192 05:55:59.359501 [0] AVG Duty = 4953%(X100)
7193 05:55:59.359686
7194 05:55:59.362829 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7195 05:55:59.366197
7196 05:55:59.369294 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7197 05:55:59.372417 [DutyScan_Calibration_Flow] ====Done====
7198 05:55:59.375937 nWR fixed to 30
7199 05:55:59.376087 [ModeRegInit_LP4] CH0 RK0
7200 05:55:59.379426 [ModeRegInit_LP4] CH0 RK1
7201 05:55:59.382765 [ModeRegInit_LP4] CH1 RK0
7202 05:55:59.385731 [ModeRegInit_LP4] CH1 RK1
7203 05:55:59.385965 match AC timing 4
7204 05:55:59.389239 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7205 05:55:59.395930 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7206 05:55:59.399581 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7207 05:55:59.406003 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7208 05:55:59.409080 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7209 05:55:59.409459 [MiockJmeterHQA]
7210 05:55:59.409756
7211 05:55:59.412889 [DramcMiockJmeter] u1RxGatingPI = 0
7212 05:55:59.415777 0 : 4254, 4029
7213 05:55:59.416242 4 : 4363, 4137
7214 05:55:59.419246 8 : 4252, 4027
7215 05:55:59.419710 12 : 4363, 4138
7216 05:55:59.420078 16 : 4252, 4026
7217 05:55:59.422360 20 : 4252, 4027
7218 05:55:59.422818 24 : 4253, 4026
7219 05:55:59.425808 28 : 4363, 4138
7220 05:55:59.426266 32 : 4365, 4139
7221 05:55:59.429322 36 : 4252, 4027
7222 05:55:59.429780 40 : 4252, 4027
7223 05:55:59.430140 44 : 4253, 4027
7224 05:55:59.432566 48 : 4252, 4027
7225 05:55:59.433005 52 : 4252, 4027
7226 05:55:59.435842 56 : 4363, 4137
7227 05:55:59.436256 60 : 4249, 4027
7228 05:55:59.439062 64 : 4253, 4027
7229 05:55:59.439479 68 : 4250, 4027
7230 05:55:59.442581 72 : 4250, 4027
7231 05:55:59.442993 76 : 4250, 4026
7232 05:55:59.443320 80 : 4360, 4138
7233 05:55:59.445687 84 : 4360, 4138
7234 05:55:59.446100 88 : 4250, 4027
7235 05:55:59.449381 92 : 4250, 4027
7236 05:55:59.449905 96 : 4250, 4026
7237 05:55:59.452629 100 : 4250, 2355
7238 05:55:59.453540 104 : 4250, 0
7239 05:55:59.455489 108 : 4250, 0
7240 05:55:59.456130 112 : 4250, 0
7241 05:55:59.456766 116 : 4250, 0
7242 05:55:59.458900 120 : 4249, 0
7243 05:55:59.459294 124 : 4250, 0
7244 05:55:59.459658 128 : 4250, 0
7245 05:55:59.462186 132 : 4360, 0
7246 05:55:59.462653 136 : 4250, 0
7247 05:55:59.465756 140 : 4250, 0
7248 05:55:59.466323 144 : 4250, 0
7249 05:55:59.466695 148 : 4250, 0
7250 05:55:59.468999 152 : 4250, 0
7251 05:55:59.469668 156 : 4250, 0
7252 05:55:59.472203 160 : 4250, 0
7253 05:55:59.472770 164 : 4250, 0
7254 05:55:59.473300 168 : 4250, 0
7255 05:55:59.475466 172 : 4250, 0
7256 05:55:59.475929 176 : 4250, 0
7257 05:55:59.479025 180 : 4250, 0
7258 05:55:59.479705 184 : 4362, 0
7259 05:55:59.480084 188 : 4361, 0
7260 05:55:59.482605 192 : 4360, 0
7261 05:55:59.483172 196 : 4250, 0
7262 05:55:59.483542 200 : 4250, 0
7263 05:55:59.485411 204 : 4250, 0
7264 05:55:59.485874 208 : 4249, 0
7265 05:55:59.488692 212 : 4250, 0
7266 05:55:59.489262 216 : 4250, 0
7267 05:55:59.491977 220 : 4250, 501
7268 05:55:59.492433 224 : 4250, 3972
7269 05:55:59.492848 228 : 4250, 4027
7270 05:55:59.495185 232 : 4250, 4027
7271 05:55:59.495643 236 : 4252, 4030
7272 05:55:59.498516 240 : 4250, 4027
7273 05:55:59.498976 244 : 4250, 4027
7274 05:55:59.501957 248 : 4360, 4138
7275 05:55:59.502419 252 : 4250, 4027
7276 05:55:59.505163 256 : 4250, 4027
7277 05:55:59.505579 260 : 4361, 4137
7278 05:55:59.508568 264 : 4250, 4027
7279 05:55:59.509013 268 : 4250, 4027
7280 05:55:59.511731 272 : 4360, 4137
7281 05:55:59.512147 276 : 4250, 4026
7282 05:55:59.514917 280 : 4250, 4027
7283 05:55:59.515333 284 : 4249, 4027
7284 05:55:59.515666 288 : 4250, 4027
7285 05:55:59.518345 292 : 4250, 4027
7286 05:55:59.518761 296 : 4250, 4027
7287 05:55:59.522159 300 : 4363, 4138
7288 05:55:59.522580 304 : 4250, 4027
7289 05:55:59.524890 308 : 4250, 4026
7290 05:55:59.525353 312 : 4361, 4137
7291 05:55:59.528694 316 : 4250, 4027
7292 05:55:59.529161 320 : 4250, 4027
7293 05:55:59.531801 324 : 4360, 4137
7294 05:55:59.532222 328 : 4250, 4026
7295 05:55:59.535108 332 : 4250, 4027
7296 05:55:59.535527 336 : 4250, 3930
7297 05:55:59.538209 340 : 4249, 2281
7298 05:55:59.538630 344 : 4250, 0
7299 05:55:59.538964
7300 05:55:59.541354 MIOCK jitter meter ch=0
7301 05:55:59.541767
7302 05:55:59.545015 1T = (344-104) = 240 dly cells
7303 05:55:59.548027 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7304 05:55:59.548567 ==
7305 05:55:59.551639 Dram Type= 6, Freq= 0, CH_0, rank 0
7306 05:55:59.558171 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7307 05:55:59.558589 ==
7308 05:55:59.561494 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7309 05:55:59.567764 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7310 05:55:59.571124 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7311 05:55:59.577720 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7312 05:55:59.584999 [CA 0] Center 41 (11~72) winsize 62
7313 05:55:59.588383 [CA 1] Center 41 (11~72) winsize 62
7314 05:55:59.591790 [CA 2] Center 37 (7~68) winsize 62
7315 05:55:59.594766 [CA 3] Center 37 (7~67) winsize 61
7316 05:55:59.598561 [CA 4] Center 35 (5~66) winsize 62
7317 05:55:59.601335 [CA 5] Center 35 (5~65) winsize 61
7318 05:55:59.601748
7319 05:55:59.604592 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7320 05:55:59.605037
7321 05:55:59.608073 [CATrainingPosCal] consider 1 rank data
7322 05:55:59.611552 u2DelayCellTimex100 = 271/100 ps
7323 05:55:59.614641 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7324 05:55:59.621634 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7325 05:55:59.624669 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7326 05:55:59.628168 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7327 05:55:59.631243 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7328 05:55:59.634686 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7329 05:55:59.635099
7330 05:55:59.638049 CA PerBit enable=1, Macro0, CA PI delay=35
7331 05:55:59.638460
7332 05:55:59.641363 [CBTSetCACLKResult] CA Dly = 35
7333 05:55:59.644487 CS Dly: 11 (0~42)
7334 05:55:59.647785 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7335 05:55:59.651660 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7336 05:55:59.652076 ==
7337 05:55:59.654211 Dram Type= 6, Freq= 0, CH_0, rank 1
7338 05:55:59.657516 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7339 05:55:59.661431 ==
7340 05:55:59.664225 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7341 05:55:59.667733 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7342 05:55:59.674482 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7343 05:55:59.681052 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7344 05:55:59.687357 [CA 0] Center 42 (12~73) winsize 62
7345 05:55:59.690456 [CA 1] Center 42 (12~73) winsize 62
7346 05:55:59.694093 [CA 2] Center 38 (9~68) winsize 60
7347 05:55:59.697281 [CA 3] Center 38 (8~68) winsize 61
7348 05:55:59.701053 [CA 4] Center 36 (6~66) winsize 61
7349 05:55:59.703930 [CA 5] Center 36 (6~66) winsize 61
7350 05:55:59.704388
7351 05:55:59.707735 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7352 05:55:59.708294
7353 05:55:59.710687 [CATrainingPosCal] consider 2 rank data
7354 05:55:59.714265 u2DelayCellTimex100 = 271/100 ps
7355 05:55:59.717331 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7356 05:55:59.724269 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7357 05:55:59.727420 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7358 05:55:59.731078 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7359 05:55:59.733877 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7360 05:55:59.737242 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7361 05:55:59.737696
7362 05:55:59.740323 CA PerBit enable=1, Macro0, CA PI delay=35
7363 05:55:59.740820
7364 05:55:59.743687 [CBTSetCACLKResult] CA Dly = 35
7365 05:55:59.747141 CS Dly: 11 (0~42)
7366 05:55:59.750634 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7367 05:55:59.753584 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7368 05:55:59.753993
7369 05:55:59.757248 ----->DramcWriteLeveling(PI) begin...
7370 05:55:59.757666 ==
7371 05:55:59.760465 Dram Type= 6, Freq= 0, CH_0, rank 0
7372 05:55:59.766761 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7373 05:55:59.767293 ==
7374 05:55:59.770499 Write leveling (Byte 0): 28 => 28
7375 05:55:59.774053 Write leveling (Byte 1): 26 => 26
7376 05:55:59.774463 DramcWriteLeveling(PI) end<-----
7377 05:55:59.774787
7378 05:55:59.777075 ==
7379 05:55:59.779764 Dram Type= 6, Freq= 0, CH_0, rank 0
7380 05:55:59.783754 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7381 05:55:59.784164 ==
7382 05:55:59.786483 [Gating] SW mode calibration
7383 05:55:59.793332 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7384 05:55:59.796516 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7385 05:55:59.803220 0 12 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7386 05:55:59.806555 0 12 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7387 05:55:59.809801 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7388 05:55:59.816566 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7389 05:55:59.819817 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7390 05:55:59.823134 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7391 05:55:59.829318 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7392 05:55:59.833241 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7393 05:55:59.835985 0 13 0 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
7394 05:55:59.842367 0 13 4 | B1->B0 | 3333 2424 | 0 0 | (0 1) (1 0)
7395 05:55:59.846061 0 13 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7396 05:55:59.849226 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7397 05:55:59.856409 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7398 05:55:59.859147 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7399 05:55:59.862170 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7400 05:55:59.868798 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7401 05:55:59.872518 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
7402 05:55:59.875404 0 14 4 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
7403 05:55:59.882089 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7404 05:55:59.885477 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7405 05:55:59.888654 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7406 05:55:59.895529 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7407 05:55:59.898528 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7408 05:55:59.902632 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7409 05:55:59.908788 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7410 05:55:59.912219 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7411 05:55:59.915610 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7412 05:55:59.922515 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 05:55:59.925601 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7414 05:55:59.928596 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 05:55:59.935955 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 05:55:59.938667 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 05:55:59.942391 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7418 05:55:59.948486 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7419 05:55:59.952199 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7420 05:55:59.955287 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7421 05:55:59.961810 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7422 05:55:59.965345 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7423 05:55:59.968385 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7424 05:55:59.974883 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7425 05:55:59.978626 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7426 05:55:59.981405 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7427 05:55:59.988272 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7428 05:55:59.988792 Total UI for P1: 0, mck2ui 16
7429 05:55:59.994821 best dqsien dly found for B0: ( 1, 1, 0)
7430 05:55:59.998095 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7431 05:56:00.001513 Total UI for P1: 0, mck2ui 16
7432 05:56:00.004507 best dqsien dly found for B1: ( 1, 1, 6)
7433 05:56:00.008180 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7434 05:56:00.011341 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7435 05:56:00.011801
7436 05:56:00.014770 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7437 05:56:00.018521 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7438 05:56:00.021354 [Gating] SW calibration Done
7439 05:56:00.021810 ==
7440 05:56:00.024476 Dram Type= 6, Freq= 0, CH_0, rank 0
7441 05:56:00.027934 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7442 05:56:00.028502 ==
7443 05:56:00.031324 RX Vref Scan: 0
7444 05:56:00.031893
7445 05:56:00.034683 RX Vref 0 -> 0, step: 1
7446 05:56:00.035247
7447 05:56:00.035619 RX Delay 0 -> 252, step: 8
7448 05:56:00.041162 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7449 05:56:00.044672 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7450 05:56:00.047880 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7451 05:56:00.051179 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7452 05:56:00.054246 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7453 05:56:00.060910 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7454 05:56:00.064198 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7455 05:56:00.068148 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7456 05:56:00.070751 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7457 05:56:00.074031 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7458 05:56:00.081116 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7459 05:56:00.084053 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7460 05:56:00.087174 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7461 05:56:00.090957 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7462 05:56:00.097243 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7463 05:56:00.100433 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7464 05:56:00.100946 ==
7465 05:56:00.103939 Dram Type= 6, Freq= 0, CH_0, rank 0
7466 05:56:00.107213 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7467 05:56:00.107684 ==
7468 05:56:00.108121 DQS Delay:
7469 05:56:00.110763 DQS0 = 0, DQS1 = 0
7470 05:56:00.111222 DQM Delay:
7471 05:56:00.114200 DQM0 = 130, DQM1 = 124
7472 05:56:00.114736 DQ Delay:
7473 05:56:00.117149 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7474 05:56:00.120691 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7475 05:56:00.123962 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7476 05:56:00.130945 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7477 05:56:00.131517
7478 05:56:00.131884
7479 05:56:00.132222 ==
7480 05:56:00.134203 Dram Type= 6, Freq= 0, CH_0, rank 0
7481 05:56:00.137143 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7482 05:56:00.137626 ==
7483 05:56:00.137999
7484 05:56:00.138340
7485 05:56:00.141069 TX Vref Scan disable
7486 05:56:00.141640 == TX Byte 0 ==
7487 05:56:00.146922 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7488 05:56:00.150633 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7489 05:56:00.151204 == TX Byte 1 ==
7490 05:56:00.157104 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7491 05:56:00.160428 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7492 05:56:00.161063 ==
7493 05:56:00.163505 Dram Type= 6, Freq= 0, CH_0, rank 0
7494 05:56:00.167061 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7495 05:56:00.167636 ==
7496 05:56:00.180611
7497 05:56:00.183701 TX Vref early break, caculate TX vref
7498 05:56:00.187246 TX Vref=16, minBit 9, minWin=21, winSum=371
7499 05:56:00.190915 TX Vref=18, minBit 8, minWin=22, winSum=381
7500 05:56:00.193546 TX Vref=20, minBit 8, minWin=22, winSum=389
7501 05:56:00.197083 TX Vref=22, minBit 8, minWin=23, winSum=398
7502 05:56:00.200097 TX Vref=24, minBit 8, minWin=24, winSum=404
7503 05:56:00.206868 TX Vref=26, minBit 8, minWin=24, winSum=409
7504 05:56:00.210468 TX Vref=28, minBit 8, minWin=25, winSum=416
7505 05:56:00.213852 TX Vref=30, minBit 8, minWin=24, winSum=413
7506 05:56:00.217008 TX Vref=32, minBit 8, minWin=23, winSum=401
7507 05:56:00.220100 TX Vref=34, minBit 8, minWin=23, winSum=390
7508 05:56:00.226591 [TxChooseVref] Worse bit 8, Min win 25, Win sum 416, Final Vref 28
7509 05:56:00.227147
7510 05:56:00.230240 Final TX Range 0 Vref 28
7511 05:56:00.230702
7512 05:56:00.231065 ==
7513 05:56:00.233633 Dram Type= 6, Freq= 0, CH_0, rank 0
7514 05:56:00.237036 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7515 05:56:00.237610 ==
7516 05:56:00.237982
7517 05:56:00.238320
7518 05:56:00.240193 TX Vref Scan disable
7519 05:56:00.246733 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7520 05:56:00.247283 == TX Byte 0 ==
7521 05:56:00.249711 u2DelayCellOfst[0]=10 cells (3 PI)
7522 05:56:00.253474 u2DelayCellOfst[1]=18 cells (5 PI)
7523 05:56:00.257133 u2DelayCellOfst[2]=14 cells (4 PI)
7524 05:56:00.260171 u2DelayCellOfst[3]=10 cells (3 PI)
7525 05:56:00.263241 u2DelayCellOfst[4]=7 cells (2 PI)
7526 05:56:00.266690 u2DelayCellOfst[5]=0 cells (0 PI)
7527 05:56:00.269962 u2DelayCellOfst[6]=18 cells (5 PI)
7528 05:56:00.273153 u2DelayCellOfst[7]=18 cells (5 PI)
7529 05:56:00.276921 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7530 05:56:00.279913 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7531 05:56:00.283000 == TX Byte 1 ==
7532 05:56:00.283486 u2DelayCellOfst[8]=3 cells (1 PI)
7533 05:56:00.286469 u2DelayCellOfst[9]=0 cells (0 PI)
7534 05:56:00.289680 u2DelayCellOfst[10]=14 cells (4 PI)
7535 05:56:00.293144 u2DelayCellOfst[11]=7 cells (2 PI)
7536 05:56:00.296393 u2DelayCellOfst[12]=18 cells (5 PI)
7537 05:56:00.299430 u2DelayCellOfst[13]=14 cells (4 PI)
7538 05:56:00.303002 u2DelayCellOfst[14]=18 cells (5 PI)
7539 05:56:00.306074 u2DelayCellOfst[15]=14 cells (4 PI)
7540 05:56:00.309445 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7541 05:56:00.315983 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7542 05:56:00.316536 DramC Write-DBI on
7543 05:56:00.316950 ==
7544 05:56:00.319412 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 05:56:00.326048 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7546 05:56:00.326594 ==
7547 05:56:00.326962
7548 05:56:00.327400
7549 05:56:00.327740 TX Vref Scan disable
7550 05:56:00.329821 == TX Byte 0 ==
7551 05:56:00.333378 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7552 05:56:00.336868 == TX Byte 1 ==
7553 05:56:00.339953 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7554 05:56:00.342935 DramC Write-DBI off
7555 05:56:00.343397
7556 05:56:00.343763 [DATLAT]
7557 05:56:00.344219 Freq=1600, CH0 RK0
7558 05:56:00.344561
7559 05:56:00.346190 DATLAT Default: 0xf
7560 05:56:00.346650 0, 0xFFFF, sum = 0
7561 05:56:00.350013 1, 0xFFFF, sum = 0
7562 05:56:00.353400 2, 0xFFFF, sum = 0
7563 05:56:00.354044 3, 0xFFFF, sum = 0
7564 05:56:00.356496 4, 0xFFFF, sum = 0
7565 05:56:00.356991 5, 0xFFFF, sum = 0
7566 05:56:00.359963 6, 0xFFFF, sum = 0
7567 05:56:00.360803 7, 0xFFFF, sum = 0
7568 05:56:00.362956 8, 0xFFFF, sum = 0
7569 05:56:00.363521 9, 0xFFFF, sum = 0
7570 05:56:00.366318 10, 0xFFFF, sum = 0
7571 05:56:00.367004 11, 0xFFFF, sum = 0
7572 05:56:00.369603 12, 0x8FFF, sum = 0
7573 05:56:00.370071 13, 0x0, sum = 1
7574 05:56:00.372877 14, 0x0, sum = 2
7575 05:56:00.373346 15, 0x0, sum = 3
7576 05:56:00.376413 16, 0x0, sum = 4
7577 05:56:00.376924 best_step = 14
7578 05:56:00.377297
7579 05:56:00.377634 ==
7580 05:56:00.379614 Dram Type= 6, Freq= 0, CH_0, rank 0
7581 05:56:00.382823 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7582 05:56:00.385944 ==
7583 05:56:00.386406 RX Vref Scan: 1
7584 05:56:00.386773
7585 05:56:00.389757 Set Vref Range= 24 -> 127
7586 05:56:00.390315
7587 05:56:00.392792 RX Vref 24 -> 127, step: 1
7588 05:56:00.393268
7589 05:56:00.393691 RX Delay 11 -> 252, step: 4
7590 05:56:00.394037
7591 05:56:00.396204 Set Vref, RX VrefLevel [Byte0]: 24
7592 05:56:00.399082 [Byte1]: 24
7593 05:56:00.403449
7594 05:56:00.404009 Set Vref, RX VrefLevel [Byte0]: 25
7595 05:56:00.406386 [Byte1]: 25
7596 05:56:00.410823
7597 05:56:00.411402 Set Vref, RX VrefLevel [Byte0]: 26
7598 05:56:00.413990 [Byte1]: 26
7599 05:56:00.418846
7600 05:56:00.419408 Set Vref, RX VrefLevel [Byte0]: 27
7601 05:56:00.421572 [Byte1]: 27
7602 05:56:00.426397
7603 05:56:00.426963 Set Vref, RX VrefLevel [Byte0]: 28
7604 05:56:00.429598 [Byte1]: 28
7605 05:56:00.434058
7606 05:56:00.434621 Set Vref, RX VrefLevel [Byte0]: 29
7607 05:56:00.436770 [Byte1]: 29
7608 05:56:00.441436
7609 05:56:00.442175 Set Vref, RX VrefLevel [Byte0]: 30
7610 05:56:00.444788 [Byte1]: 30
7611 05:56:00.448913
7612 05:56:00.449388 Set Vref, RX VrefLevel [Byte0]: 31
7613 05:56:00.452381 [Byte1]: 31
7614 05:56:00.456393
7615 05:56:00.456937 Set Vref, RX VrefLevel [Byte0]: 32
7616 05:56:00.460085 [Byte1]: 32
7617 05:56:00.464146
7618 05:56:00.464607 Set Vref, RX VrefLevel [Byte0]: 33
7619 05:56:00.467169 [Byte1]: 33
7620 05:56:00.472059
7621 05:56:00.472520 Set Vref, RX VrefLevel [Byte0]: 34
7622 05:56:00.475025 [Byte1]: 34
7623 05:56:00.479844
7624 05:56:00.480518 Set Vref, RX VrefLevel [Byte0]: 35
7625 05:56:00.483101 [Byte1]: 35
7626 05:56:00.487374
7627 05:56:00.487933 Set Vref, RX VrefLevel [Byte0]: 36
7628 05:56:00.490349 [Byte1]: 36
7629 05:56:00.494799
7630 05:56:00.495278 Set Vref, RX VrefLevel [Byte0]: 37
7631 05:56:00.497778 [Byte1]: 37
7632 05:56:00.502612
7633 05:56:00.503170 Set Vref, RX VrefLevel [Byte0]: 38
7634 05:56:00.505295 [Byte1]: 38
7635 05:56:00.509857
7636 05:56:00.510318 Set Vref, RX VrefLevel [Byte0]: 39
7637 05:56:00.513616 [Byte1]: 39
7638 05:56:00.517163
7639 05:56:00.517621 Set Vref, RX VrefLevel [Byte0]: 40
7640 05:56:00.520946 [Byte1]: 40
7641 05:56:00.525262
7642 05:56:00.525723 Set Vref, RX VrefLevel [Byte0]: 41
7643 05:56:00.528123 [Byte1]: 41
7644 05:56:00.533126
7645 05:56:00.533689 Set Vref, RX VrefLevel [Byte0]: 42
7646 05:56:00.536255 [Byte1]: 42
7647 05:56:00.540393
7648 05:56:00.541004 Set Vref, RX VrefLevel [Byte0]: 43
7649 05:56:00.543635 [Byte1]: 43
7650 05:56:00.548000
7651 05:56:00.548511 Set Vref, RX VrefLevel [Byte0]: 44
7652 05:56:00.551205 [Byte1]: 44
7653 05:56:00.555651
7654 05:56:00.556219 Set Vref, RX VrefLevel [Byte0]: 45
7655 05:56:00.558877 [Byte1]: 45
7656 05:56:00.562931
7657 05:56:00.563507 Set Vref, RX VrefLevel [Byte0]: 46
7658 05:56:00.566456 [Byte1]: 46
7659 05:56:00.570744
7660 05:56:00.571205 Set Vref, RX VrefLevel [Byte0]: 47
7661 05:56:00.573984 [Byte1]: 47
7662 05:56:00.578830
7663 05:56:00.579409 Set Vref, RX VrefLevel [Byte0]: 48
7664 05:56:00.581810 [Byte1]: 48
7665 05:56:00.585723
7666 05:56:00.586184 Set Vref, RX VrefLevel [Byte0]: 49
7667 05:56:00.589364 [Byte1]: 49
7668 05:56:00.593991
7669 05:56:00.594538 Set Vref, RX VrefLevel [Byte0]: 50
7670 05:56:00.596665 [Byte1]: 50
7671 05:56:00.601564
7672 05:56:00.602137 Set Vref, RX VrefLevel [Byte0]: 51
7673 05:56:00.604519 [Byte1]: 51
7674 05:56:00.608508
7675 05:56:00.609024 Set Vref, RX VrefLevel [Byte0]: 52
7676 05:56:00.612284 [Byte1]: 52
7677 05:56:00.616455
7678 05:56:00.617002 Set Vref, RX VrefLevel [Byte0]: 53
7679 05:56:00.619568 [Byte1]: 53
7680 05:56:00.624261
7681 05:56:00.624755 Set Vref, RX VrefLevel [Byte0]: 54
7682 05:56:00.627398 [Byte1]: 54
7683 05:56:00.631822
7684 05:56:00.632284 Set Vref, RX VrefLevel [Byte0]: 55
7685 05:56:00.634850 [Byte1]: 55
7686 05:56:00.639071
7687 05:56:00.639531 Set Vref, RX VrefLevel [Byte0]: 56
7688 05:56:00.642691 [Byte1]: 56
7689 05:56:00.646705
7690 05:56:00.647183 Set Vref, RX VrefLevel [Byte0]: 57
7691 05:56:00.649902 [Byte1]: 57
7692 05:56:00.654404
7693 05:56:00.654986 Set Vref, RX VrefLevel [Byte0]: 58
7694 05:56:00.657738 [Byte1]: 58
7695 05:56:00.662439
7696 05:56:00.662999 Set Vref, RX VrefLevel [Byte0]: 59
7697 05:56:00.665345 [Byte1]: 59
7698 05:56:00.669719
7699 05:56:00.670176 Set Vref, RX VrefLevel [Byte0]: 60
7700 05:56:00.672951 [Byte1]: 60
7701 05:56:00.677534
7702 05:56:00.678136 Set Vref, RX VrefLevel [Byte0]: 61
7703 05:56:00.681048 [Byte1]: 61
7704 05:56:00.685043
7705 05:56:00.685508 Set Vref, RX VrefLevel [Byte0]: 62
7706 05:56:00.688111 [Byte1]: 62
7707 05:56:00.692511
7708 05:56:00.693096 Set Vref, RX VrefLevel [Byte0]: 63
7709 05:56:00.696074 [Byte1]: 63
7710 05:56:00.700241
7711 05:56:00.700829 Set Vref, RX VrefLevel [Byte0]: 64
7712 05:56:00.703447 [Byte1]: 64
7713 05:56:00.707997
7714 05:56:00.708456 Set Vref, RX VrefLevel [Byte0]: 65
7715 05:56:00.711105 [Byte1]: 65
7716 05:56:00.715567
7717 05:56:00.716134 Set Vref, RX VrefLevel [Byte0]: 66
7718 05:56:00.718561 [Byte1]: 66
7719 05:56:00.722684
7720 05:56:00.723144 Set Vref, RX VrefLevel [Byte0]: 67
7721 05:56:00.726161 [Byte1]: 67
7722 05:56:00.730771
7723 05:56:00.731230 Set Vref, RX VrefLevel [Byte0]: 68
7724 05:56:00.734114 [Byte1]: 68
7725 05:56:00.738282
7726 05:56:00.738744 Set Vref, RX VrefLevel [Byte0]: 69
7727 05:56:00.741338 [Byte1]: 69
7728 05:56:00.745722
7729 05:56:00.746182 Set Vref, RX VrefLevel [Byte0]: 70
7730 05:56:00.749033 [Byte1]: 70
7731 05:56:00.753416
7732 05:56:00.753879 Final RX Vref Byte 0 = 54 to rank0
7733 05:56:00.756672 Final RX Vref Byte 1 = 55 to rank0
7734 05:56:00.760394 Final RX Vref Byte 0 = 54 to rank1
7735 05:56:00.763263 Final RX Vref Byte 1 = 55 to rank1==
7736 05:56:00.766436 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 05:56:00.772910 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7738 05:56:00.773101 ==
7739 05:56:00.773251 DQS Delay:
7740 05:56:00.773390 DQS0 = 0, DQS1 = 0
7741 05:56:00.776244 DQM Delay:
7742 05:56:00.776434 DQM0 = 126, DQM1 = 121
7743 05:56:00.779629 DQ Delay:
7744 05:56:00.783065 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7745 05:56:00.785935 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7746 05:56:00.789849 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112
7747 05:56:00.792616 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =132
7748 05:56:00.792759
7749 05:56:00.792866
7750 05:56:00.792965
7751 05:56:00.795834 [DramC_TX_OE_Calibration] TA2
7752 05:56:00.799668 Original DQ_B0 (3 6) =30, OEN = 27
7753 05:56:00.803129 Original DQ_B1 (3 6) =30, OEN = 27
7754 05:56:00.805940 24, 0x0, End_B0=24 End_B1=24
7755 05:56:00.806126 25, 0x0, End_B0=25 End_B1=25
7756 05:56:00.809308 26, 0x0, End_B0=26 End_B1=26
7757 05:56:00.812952 27, 0x0, End_B0=27 End_B1=27
7758 05:56:00.816082 28, 0x0, End_B0=28 End_B1=28
7759 05:56:00.819365 29, 0x0, End_B0=29 End_B1=29
7760 05:56:00.819630 30, 0x0, End_B0=30 End_B1=30
7761 05:56:00.822628 31, 0x4545, End_B0=30 End_B1=30
7762 05:56:00.826421 Byte0 end_step=30 best_step=27
7763 05:56:00.829854 Byte1 end_step=30 best_step=27
7764 05:56:00.833008 Byte0 TX OE(2T, 0.5T) = (3, 3)
7765 05:56:00.836260 Byte1 TX OE(2T, 0.5T) = (3, 3)
7766 05:56:00.836657
7767 05:56:00.836929
7768 05:56:00.842670 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
7769 05:56:00.846392 CH0 RK0: MR19=303, MR18=1717
7770 05:56:00.853146 CH0_RK0: MR19=0x303, MR18=0x1717, DQSOSC=398, MR23=63, INC=23, DEC=15
7771 05:56:00.853714
7772 05:56:00.856411 ----->DramcWriteLeveling(PI) begin...
7773 05:56:00.857024 ==
7774 05:56:00.859612 Dram Type= 6, Freq= 0, CH_0, rank 1
7775 05:56:00.862772 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7776 05:56:00.863310 ==
7777 05:56:00.866386 Write leveling (Byte 0): 29 => 29
7778 05:56:00.869427 Write leveling (Byte 1): 27 => 27
7779 05:56:00.872483 DramcWriteLeveling(PI) end<-----
7780 05:56:00.873000
7781 05:56:00.873372 ==
7782 05:56:00.876019 Dram Type= 6, Freq= 0, CH_0, rank 1
7783 05:56:00.879413 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7784 05:56:00.879981 ==
7785 05:56:00.882800 [Gating] SW mode calibration
7786 05:56:00.889169 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7787 05:56:00.895995 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7788 05:56:00.899294 0 12 0 | B1->B0 | 2323 302f | 0 1 | (0 0) (1 1)
7789 05:56:00.905772 0 12 4 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
7790 05:56:00.909295 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7791 05:56:00.912758 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7792 05:56:00.919386 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7793 05:56:00.922151 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7794 05:56:00.925520 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7795 05:56:00.931952 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7796 05:56:00.935437 0 13 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
7797 05:56:00.938862 0 13 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
7798 05:56:00.945432 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7799 05:56:00.948839 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7800 05:56:00.952333 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7801 05:56:00.958711 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7802 05:56:00.962012 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7803 05:56:00.965314 0 13 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7804 05:56:00.971600 0 14 0 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7805 05:56:00.974862 0 14 4 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7806 05:56:00.978552 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7807 05:56:00.984899 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7808 05:56:00.988606 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7809 05:56:00.991648 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7810 05:56:00.995409 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7811 05:56:01.001554 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7812 05:56:01.005040 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7813 05:56:01.008373 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7814 05:56:01.014934 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7815 05:56:01.018208 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 05:56:01.021300 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 05:56:01.027751 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 05:56:01.031463 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 05:56:01.034658 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7820 05:56:01.041203 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7821 05:56:01.044663 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 05:56:01.047880 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 05:56:01.054363 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 05:56:01.058124 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 05:56:01.061214 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7826 05:56:01.067822 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7827 05:56:01.070966 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7828 05:56:01.074527 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7829 05:56:01.080694 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7830 05:56:01.084221 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7831 05:56:01.087482 Total UI for P1: 0, mck2ui 16
7832 05:56:01.090701 best dqsien dly found for B0: ( 1, 1, 0)
7833 05:56:01.094729 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7834 05:56:01.097415 Total UI for P1: 0, mck2ui 16
7835 05:56:01.100701 best dqsien dly found for B1: ( 1, 1, 6)
7836 05:56:01.103683 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7837 05:56:01.107501 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7838 05:56:01.107956
7839 05:56:01.114125 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7840 05:56:01.117189 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7841 05:56:01.117644 [Gating] SW calibration Done
7842 05:56:01.120591 ==
7843 05:56:01.124150 Dram Type= 6, Freq= 0, CH_0, rank 1
7844 05:56:01.127336 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7845 05:56:01.127892 ==
7846 05:56:01.128257 RX Vref Scan: 0
7847 05:56:01.128592
7848 05:56:01.130529 RX Vref 0 -> 0, step: 1
7849 05:56:01.130976
7850 05:56:01.133761 RX Delay 0 -> 252, step: 8
7851 05:56:01.137182 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7852 05:56:01.140557 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7853 05:56:01.143964 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7854 05:56:01.150742 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7855 05:56:01.153907 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7856 05:56:01.157178 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7857 05:56:01.160197 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7858 05:56:01.163305 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7859 05:56:01.169985 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7860 05:56:01.173370 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7861 05:56:01.176788 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7862 05:56:01.180427 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7863 05:56:01.183626 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7864 05:56:01.189980 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7865 05:56:01.193597 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7866 05:56:01.196930 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7867 05:56:01.197398 ==
7868 05:56:01.200069 Dram Type= 6, Freq= 0, CH_0, rank 1
7869 05:56:01.203276 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7870 05:56:01.206570 ==
7871 05:56:01.207031 DQS Delay:
7872 05:56:01.207398 DQS0 = 0, DQS1 = 0
7873 05:56:01.209974 DQM Delay:
7874 05:56:01.210436 DQM0 = 131, DQM1 = 124
7875 05:56:01.213106 DQ Delay:
7876 05:56:01.217109 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =127
7877 05:56:01.220322 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7878 05:56:01.223194 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7879 05:56:01.226903 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7880 05:56:01.227461
7881 05:56:01.227827
7882 05:56:01.228163 ==
7883 05:56:01.229644 Dram Type= 6, Freq= 0, CH_0, rank 1
7884 05:56:01.233239 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7885 05:56:01.236049 ==
7886 05:56:01.236508
7887 05:56:01.236917
7888 05:56:01.237311 TX Vref Scan disable
7889 05:56:01.239540 == TX Byte 0 ==
7890 05:56:01.243006 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7891 05:56:01.246268 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7892 05:56:01.249423 == TX Byte 1 ==
7893 05:56:01.252768 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7894 05:56:01.255939 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7895 05:56:01.259103 ==
7896 05:56:01.262480 Dram Type= 6, Freq= 0, CH_0, rank 1
7897 05:56:01.266147 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7898 05:56:01.266877 ==
7899 05:56:01.278208
7900 05:56:01.281796 TX Vref early break, caculate TX vref
7901 05:56:01.284639 TX Vref=16, minBit 1, minWin=22, winSum=376
7902 05:56:01.288200 TX Vref=18, minBit 9, minWin=22, winSum=378
7903 05:56:01.291305 TX Vref=20, minBit 1, minWin=23, winSum=395
7904 05:56:01.294670 TX Vref=22, minBit 8, minWin=23, winSum=400
7905 05:56:01.297783 TX Vref=24, minBit 1, minWin=24, winSum=406
7906 05:56:01.304698 TX Vref=26, minBit 8, minWin=25, winSum=418
7907 05:56:01.307987 TX Vref=28, minBit 7, minWin=25, winSum=418
7908 05:56:01.311566 TX Vref=30, minBit 8, minWin=24, winSum=413
7909 05:56:01.314766 TX Vref=32, minBit 8, minWin=24, winSum=404
7910 05:56:01.317737 TX Vref=34, minBit 8, minWin=23, winSum=394
7911 05:56:01.324271 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 26
7912 05:56:01.325229
7913 05:56:01.327645 Final TX Range 0 Vref 26
7914 05:56:01.328099
7915 05:56:01.328456 ==
7916 05:56:01.330891 Dram Type= 6, Freq= 0, CH_0, rank 1
7917 05:56:01.334294 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7918 05:56:01.334851 ==
7919 05:56:01.335214
7920 05:56:01.335547
7921 05:56:01.337388 TX Vref Scan disable
7922 05:56:01.344514 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7923 05:56:01.345127 == TX Byte 0 ==
7924 05:56:01.347572 u2DelayCellOfst[0]=14 cells (4 PI)
7925 05:56:01.350702 u2DelayCellOfst[1]=21 cells (6 PI)
7926 05:56:01.354211 u2DelayCellOfst[2]=14 cells (4 PI)
7927 05:56:01.357558 u2DelayCellOfst[3]=14 cells (4 PI)
7928 05:56:01.360978 u2DelayCellOfst[4]=10 cells (3 PI)
7929 05:56:01.364291 u2DelayCellOfst[5]=0 cells (0 PI)
7930 05:56:01.367293 u2DelayCellOfst[6]=18 cells (5 PI)
7931 05:56:01.370646 u2DelayCellOfst[7]=18 cells (5 PI)
7932 05:56:01.373808 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7933 05:56:01.377458 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7934 05:56:01.380611 == TX Byte 1 ==
7935 05:56:01.384184 u2DelayCellOfst[8]=3 cells (1 PI)
7936 05:56:01.384638 u2DelayCellOfst[9]=0 cells (0 PI)
7937 05:56:01.387492 u2DelayCellOfst[10]=10 cells (3 PI)
7938 05:56:01.390688 u2DelayCellOfst[11]=3 cells (1 PI)
7939 05:56:01.394305 u2DelayCellOfst[12]=14 cells (4 PI)
7940 05:56:01.397198 u2DelayCellOfst[13]=14 cells (4 PI)
7941 05:56:01.400785 u2DelayCellOfst[14]=18 cells (5 PI)
7942 05:56:01.403771 u2DelayCellOfst[15]=14 cells (4 PI)
7943 05:56:01.406838 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7944 05:56:01.413872 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7945 05:56:01.414330 DramC Write-DBI on
7946 05:56:01.414689 ==
7947 05:56:01.417330 Dram Type= 6, Freq= 0, CH_0, rank 1
7948 05:56:01.423825 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7949 05:56:01.424304 ==
7950 05:56:01.424675
7951 05:56:01.425056
7952 05:56:01.425404 TX Vref Scan disable
7953 05:56:01.427354 == TX Byte 0 ==
7954 05:56:01.430551 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7955 05:56:01.434348 == TX Byte 1 ==
7956 05:56:01.437375 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7957 05:56:01.440531 DramC Write-DBI off
7958 05:56:01.441133
7959 05:56:01.441498 [DATLAT]
7960 05:56:01.441837 Freq=1600, CH0 RK1
7961 05:56:01.442162
7962 05:56:01.443856 DATLAT Default: 0xe
7963 05:56:01.447447 0, 0xFFFF, sum = 0
7964 05:56:01.447863 1, 0xFFFF, sum = 0
7965 05:56:01.450416 2, 0xFFFF, sum = 0
7966 05:56:01.450883 3, 0xFFFF, sum = 0
7967 05:56:01.454600 4, 0xFFFF, sum = 0
7968 05:56:01.455213 5, 0xFFFF, sum = 0
7969 05:56:01.457164 6, 0xFFFF, sum = 0
7970 05:56:01.457612 7, 0xFFFF, sum = 0
7971 05:56:01.460149 8, 0xFFFF, sum = 0
7972 05:56:01.460561 9, 0xFFFF, sum = 0
7973 05:56:01.464100 10, 0xFFFF, sum = 0
7974 05:56:01.464620 11, 0xFFFF, sum = 0
7975 05:56:01.467365 12, 0xCFFF, sum = 0
7976 05:56:01.467824 13, 0x0, sum = 1
7977 05:56:01.471002 14, 0x0, sum = 2
7978 05:56:01.471567 15, 0x0, sum = 3
7979 05:56:01.473850 16, 0x0, sum = 4
7980 05:56:01.474310 best_step = 14
7981 05:56:01.474666
7982 05:56:01.474995 ==
7983 05:56:01.477078 Dram Type= 6, Freq= 0, CH_0, rank 1
7984 05:56:01.480238 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7985 05:56:01.483338 ==
7986 05:56:01.483788 RX Vref Scan: 0
7987 05:56:01.484140
7988 05:56:01.487055 RX Vref 0 -> 0, step: 1
7989 05:56:01.487463
7990 05:56:01.490013 RX Delay 11 -> 252, step: 4
7991 05:56:01.493354 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7992 05:56:01.497026 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7993 05:56:01.500247 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7994 05:56:01.507169 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7995 05:56:01.510096 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7996 05:56:01.513593 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7997 05:56:01.516809 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7998 05:56:01.519939 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7999 05:56:01.526573 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
8000 05:56:01.529965 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8001 05:56:01.533126 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8002 05:56:01.536387 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8003 05:56:01.540045 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8004 05:56:01.546432 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
8005 05:56:01.549714 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8006 05:56:01.552968 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8007 05:56:01.553424 ==
8008 05:56:01.556611 Dram Type= 6, Freq= 0, CH_0, rank 1
8009 05:56:01.559823 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8010 05:56:01.563008 ==
8011 05:56:01.563463 DQS Delay:
8012 05:56:01.563823 DQS0 = 0, DQS1 = 0
8013 05:56:01.566360 DQM Delay:
8014 05:56:01.566818 DQM0 = 128, DQM1 = 120
8015 05:56:01.569929 DQ Delay:
8016 05:56:01.573154 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
8017 05:56:01.576343 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
8018 05:56:01.579518 DQ8 =108, DQ9 =108, DQ10 =122, DQ11 =112
8019 05:56:01.582896 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
8020 05:56:01.583456
8021 05:56:01.583823
8022 05:56:01.584158
8023 05:56:01.586117 [DramC_TX_OE_Calibration] TA2
8024 05:56:01.589525 Original DQ_B0 (3 6) =30, OEN = 27
8025 05:56:01.592424 Original DQ_B1 (3 6) =30, OEN = 27
8026 05:56:01.596031 24, 0x0, End_B0=24 End_B1=24
8027 05:56:01.596759 25, 0x0, End_B0=25 End_B1=25
8028 05:56:01.599493 26, 0x0, End_B0=26 End_B1=26
8029 05:56:01.602854 27, 0x0, End_B0=27 End_B1=27
8030 05:56:01.605782 28, 0x0, End_B0=28 End_B1=28
8031 05:56:01.609293 29, 0x0, End_B0=29 End_B1=29
8032 05:56:01.609763 30, 0x0, End_B0=30 End_B1=30
8033 05:56:01.612621 31, 0x4141, End_B0=30 End_B1=30
8034 05:56:01.616529 Byte0 end_step=30 best_step=27
8035 05:56:01.619457 Byte1 end_step=30 best_step=27
8036 05:56:01.622599 Byte0 TX OE(2T, 0.5T) = (3, 3)
8037 05:56:01.625636 Byte1 TX OE(2T, 0.5T) = (3, 3)
8038 05:56:01.626098
8039 05:56:01.626460
8040 05:56:01.632661 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8041 05:56:01.635734 CH0 RK1: MR19=303, MR18=1E1E
8042 05:56:01.642357 CH0_RK1: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
8043 05:56:01.645740 [RxdqsGatingPostProcess] freq 1600
8044 05:56:01.648567 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8045 05:56:01.652213 Pre-setting of DQS Precalculation
8046 05:56:01.658726 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8047 05:56:01.659290 ==
8048 05:56:01.662120 Dram Type= 6, Freq= 0, CH_1, rank 0
8049 05:56:01.665786 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8050 05:56:01.666527 ==
8051 05:56:01.671565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8052 05:56:01.675327 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8053 05:56:01.678602 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8054 05:56:01.685102 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8055 05:56:01.693766 [CA 0] Center 41 (11~71) winsize 61
8056 05:56:01.697008 [CA 1] Center 40 (10~71) winsize 62
8057 05:56:01.700073 [CA 2] Center 35 (6~65) winsize 60
8058 05:56:01.703779 [CA 3] Center 35 (6~65) winsize 60
8059 05:56:01.706686 [CA 4] Center 33 (4~63) winsize 60
8060 05:56:01.709950 [CA 5] Center 33 (4~63) winsize 60
8061 05:56:01.710502
8062 05:56:01.713364 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8063 05:56:01.713824
8064 05:56:01.720121 [CATrainingPosCal] consider 1 rank data
8065 05:56:01.720677 u2DelayCellTimex100 = 271/100 ps
8066 05:56:01.726612 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8067 05:56:01.729673 CA1 delay=40 (10~71),Diff = 7 PI (25 cell)
8068 05:56:01.733484 CA2 delay=35 (6~65),Diff = 2 PI (7 cell)
8069 05:56:01.736628 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8070 05:56:01.739714 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8071 05:56:01.743034 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8072 05:56:01.743647
8073 05:56:01.746283 CA PerBit enable=1, Macro0, CA PI delay=33
8074 05:56:01.746956
8075 05:56:01.749439 [CBTSetCACLKResult] CA Dly = 33
8076 05:56:01.753463 CS Dly: 9 (0~40)
8077 05:56:01.756151 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8078 05:56:01.759690 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8079 05:56:01.760257 ==
8080 05:56:01.762674 Dram Type= 6, Freq= 0, CH_1, rank 1
8081 05:56:01.766355 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8082 05:56:01.769831 ==
8083 05:56:01.772805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8084 05:56:01.775879 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8085 05:56:01.782487 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8086 05:56:01.789162 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8087 05:56:01.795990 [CA 0] Center 41 (11~71) winsize 61
8088 05:56:01.799708 [CA 1] Center 41 (11~71) winsize 61
8089 05:56:01.802377 [CA 2] Center 36 (7~66) winsize 60
8090 05:56:01.805551 [CA 3] Center 36 (7~65) winsize 59
8091 05:56:01.809143 [CA 4] Center 34 (5~64) winsize 60
8092 05:56:01.812622 [CA 5] Center 34 (4~64) winsize 61
8093 05:56:01.813289
8094 05:56:01.815691 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8095 05:56:01.816234
8096 05:56:01.819501 [CATrainingPosCal] consider 2 rank data
8097 05:56:01.822125 u2DelayCellTimex100 = 271/100 ps
8098 05:56:01.825598 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8099 05:56:01.832417 CA1 delay=41 (11~71),Diff = 8 PI (28 cell)
8100 05:56:01.835851 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8101 05:56:01.838650 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8102 05:56:01.842006 CA4 delay=34 (5~63),Diff = 1 PI (3 cell)
8103 05:56:01.845447 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8104 05:56:01.846088
8105 05:56:01.848685 CA PerBit enable=1, Macro0, CA PI delay=33
8106 05:56:01.849179
8107 05:56:01.852032 [CBTSetCACLKResult] CA Dly = 33
8108 05:56:01.855349 CS Dly: 9 (0~41)
8109 05:56:01.858724 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8110 05:56:01.862087 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8111 05:56:01.862669
8112 05:56:01.865334 ----->DramcWriteLeveling(PI) begin...
8113 05:56:01.865878 ==
8114 05:56:01.868593 Dram Type= 6, Freq= 0, CH_1, rank 0
8115 05:56:01.874946 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8116 05:56:01.875448 ==
8117 05:56:01.878195 Write leveling (Byte 0): 21 => 21
8118 05:56:01.881755 Write leveling (Byte 1): 21 => 21
8119 05:56:01.882188 DramcWriteLeveling(PI) end<-----
8120 05:56:01.885300
8121 05:56:01.885888 ==
8122 05:56:01.888094 Dram Type= 6, Freq= 0, CH_1, rank 0
8123 05:56:01.891662 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8124 05:56:01.892132 ==
8125 05:56:01.894933 [Gating] SW mode calibration
8126 05:56:01.901411 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8127 05:56:01.908221 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8128 05:56:01.911688 0 12 0 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
8129 05:56:01.914373 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8130 05:56:01.921381 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8131 05:56:01.924545 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8132 05:56:01.927817 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8133 05:56:01.934454 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8134 05:56:01.937620 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8135 05:56:01.940924 0 12 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8136 05:56:01.947270 0 13 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
8137 05:56:01.950887 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8138 05:56:01.953970 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8139 05:56:01.960626 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8140 05:56:01.963879 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8141 05:56:01.967164 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8142 05:56:01.973614 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8143 05:56:01.976678 0 13 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8144 05:56:01.980249 0 14 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8145 05:56:01.986800 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8146 05:56:01.990281 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8147 05:56:01.993406 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8148 05:56:02.000163 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8149 05:56:02.003286 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8150 05:56:02.006553 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8151 05:56:02.013302 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8152 05:56:02.016732 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8153 05:56:02.019929 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8154 05:56:02.026496 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8155 05:56:02.029503 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 05:56:02.033046 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 05:56:02.039434 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 05:56:02.043268 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8159 05:56:02.046310 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8160 05:56:02.052916 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 05:56:02.056482 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 05:56:02.059666 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 05:56:02.066139 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8164 05:56:02.069192 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8165 05:56:02.072737 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8166 05:56:02.076125 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8167 05:56:02.082646 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8168 05:56:02.085868 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8169 05:56:02.089329 Total UI for P1: 0, mck2ui 16
8170 05:56:02.092517 best dqsien dly found for B0: ( 1, 0, 26)
8171 05:56:02.095550 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8172 05:56:02.102344 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8173 05:56:02.105747 Total UI for P1: 0, mck2ui 16
8174 05:56:02.109028 best dqsien dly found for B1: ( 1, 1, 2)
8175 05:56:02.111980 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8176 05:56:02.115801 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8177 05:56:02.116215
8178 05:56:02.118704 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8179 05:56:02.121944 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8180 05:56:02.125626 [Gating] SW calibration Done
8181 05:56:02.126116 ==
8182 05:56:02.128795 Dram Type= 6, Freq= 0, CH_1, rank 0
8183 05:56:02.132321 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8184 05:56:02.132854 ==
8185 05:56:02.136028 RX Vref Scan: 0
8186 05:56:02.136550
8187 05:56:02.138923 RX Vref 0 -> 0, step: 1
8188 05:56:02.139336
8189 05:56:02.139664 RX Delay 0 -> 252, step: 8
8190 05:56:02.145795 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8191 05:56:02.148748 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8192 05:56:02.152077 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8193 05:56:02.154989 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8194 05:56:02.158540 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8195 05:56:02.165293 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8196 05:56:02.168432 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8197 05:56:02.172023 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8198 05:56:02.175100 iDelay=200, Bit 8, Center 107 (56 ~ 159) 104
8199 05:56:02.178248 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8200 05:56:02.185186 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8201 05:56:02.188735 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8202 05:56:02.191627 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8203 05:56:02.194842 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8204 05:56:02.198240 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8205 05:56:02.204656 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8206 05:56:02.205161 ==
8207 05:56:02.208501 Dram Type= 6, Freq= 0, CH_1, rank 0
8208 05:56:02.211733 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8209 05:56:02.212285 ==
8210 05:56:02.212654 DQS Delay:
8211 05:56:02.214555 DQS0 = 0, DQS1 = 0
8212 05:56:02.215026 DQM Delay:
8213 05:56:02.217953 DQM0 = 129, DQM1 = 125
8214 05:56:02.218412 DQ Delay:
8215 05:56:02.221171 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8216 05:56:02.224615 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8217 05:56:02.227881 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8218 05:56:02.234513 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8219 05:56:02.234971
8220 05:56:02.235355
8221 05:56:02.235816 ==
8222 05:56:02.237958 Dram Type= 6, Freq= 0, CH_1, rank 0
8223 05:56:02.241458 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8224 05:56:02.241931 ==
8225 05:56:02.242419
8226 05:56:02.242867
8227 05:56:02.244591 TX Vref Scan disable
8228 05:56:02.245116 == TX Byte 0 ==
8229 05:56:02.251135 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8230 05:56:02.254428 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8231 05:56:02.254902 == TX Byte 1 ==
8232 05:56:02.261258 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8233 05:56:02.264050 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8234 05:56:02.264519 ==
8235 05:56:02.267442 Dram Type= 6, Freq= 0, CH_1, rank 0
8236 05:56:02.271033 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8237 05:56:02.271596 ==
8238 05:56:02.284524
8239 05:56:02.287452 TX Vref early break, caculate TX vref
8240 05:56:02.291092 TX Vref=16, minBit 3, minWin=21, winSum=368
8241 05:56:02.293923 TX Vref=18, minBit 3, minWin=22, winSum=379
8242 05:56:02.297221 TX Vref=20, minBit 3, minWin=22, winSum=386
8243 05:56:02.301037 TX Vref=22, minBit 3, minWin=23, winSum=395
8244 05:56:02.304193 TX Vref=24, minBit 1, minWin=24, winSum=406
8245 05:56:02.310273 TX Vref=26, minBit 3, minWin=24, winSum=413
8246 05:56:02.313973 TX Vref=28, minBit 0, minWin=25, winSum=413
8247 05:56:02.317069 TX Vref=30, minBit 3, minWin=24, winSum=405
8248 05:56:02.320364 TX Vref=32, minBit 1, minWin=24, winSum=396
8249 05:56:02.323462 TX Vref=34, minBit 3, minWin=23, winSum=388
8250 05:56:02.330508 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
8251 05:56:02.330970
8252 05:56:02.333407 Final TX Range 0 Vref 28
8253 05:56:02.333870
8254 05:56:02.334233 ==
8255 05:56:02.337379 Dram Type= 6, Freq= 0, CH_1, rank 0
8256 05:56:02.340617 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8257 05:56:02.341124 ==
8258 05:56:02.341563
8259 05:56:02.341904
8260 05:56:02.343466 TX Vref Scan disable
8261 05:56:02.350084 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8262 05:56:02.350630 == TX Byte 0 ==
8263 05:56:02.353710 u2DelayCellOfst[0]=18 cells (5 PI)
8264 05:56:02.356908 u2DelayCellOfst[1]=14 cells (4 PI)
8265 05:56:02.360312 u2DelayCellOfst[2]=0 cells (0 PI)
8266 05:56:02.364036 u2DelayCellOfst[3]=10 cells (3 PI)
8267 05:56:02.367079 u2DelayCellOfst[4]=10 cells (3 PI)
8268 05:56:02.369876 u2DelayCellOfst[5]=18 cells (5 PI)
8269 05:56:02.373249 u2DelayCellOfst[6]=18 cells (5 PI)
8270 05:56:02.376411 u2DelayCellOfst[7]=10 cells (3 PI)
8271 05:56:02.379751 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8272 05:56:02.383130 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8273 05:56:02.386151 == TX Byte 1 ==
8274 05:56:02.389554 u2DelayCellOfst[8]=0 cells (0 PI)
8275 05:56:02.392682 u2DelayCellOfst[9]=7 cells (2 PI)
8276 05:56:02.396569 u2DelayCellOfst[10]=10 cells (3 PI)
8277 05:56:02.397097 u2DelayCellOfst[11]=7 cells (2 PI)
8278 05:56:02.399225 u2DelayCellOfst[12]=18 cells (5 PI)
8279 05:56:02.402534 u2DelayCellOfst[13]=21 cells (6 PI)
8280 05:56:02.405935 u2DelayCellOfst[14]=21 cells (6 PI)
8281 05:56:02.410131 u2DelayCellOfst[15]=21 cells (6 PI)
8282 05:56:02.416019 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8283 05:56:02.419354 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8284 05:56:02.419810 DramC Write-DBI on
8285 05:56:02.420384 ==
8286 05:56:02.422912 Dram Type= 6, Freq= 0, CH_1, rank 0
8287 05:56:02.429472 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8288 05:56:02.429914 ==
8289 05:56:02.430246
8290 05:56:02.430552
8291 05:56:02.432410 TX Vref Scan disable
8292 05:56:02.432856 == TX Byte 0 ==
8293 05:56:02.435869 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8294 05:56:02.439079 == TX Byte 1 ==
8295 05:56:02.442512 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8296 05:56:02.445875 DramC Write-DBI off
8297 05:56:02.446285
8298 05:56:02.446613 [DATLAT]
8299 05:56:02.449175 Freq=1600, CH1 RK0
8300 05:56:02.449587
8301 05:56:02.449912 DATLAT Default: 0xf
8302 05:56:02.452401 0, 0xFFFF, sum = 0
8303 05:56:02.452865 1, 0xFFFF, sum = 0
8304 05:56:02.455502 2, 0xFFFF, sum = 0
8305 05:56:02.455919 3, 0xFFFF, sum = 0
8306 05:56:02.459170 4, 0xFFFF, sum = 0
8307 05:56:02.459588 5, 0xFFFF, sum = 0
8308 05:56:02.462545 6, 0xFFFF, sum = 0
8309 05:56:02.462962 7, 0xFFFF, sum = 0
8310 05:56:02.465452 8, 0xFFFF, sum = 0
8311 05:56:02.465873 9, 0xFFFF, sum = 0
8312 05:56:02.468832 10, 0xFFFF, sum = 0
8313 05:56:02.472148 11, 0xFFFF, sum = 0
8314 05:56:02.472564 12, 0xF7F, sum = 0
8315 05:56:02.475354 13, 0x0, sum = 1
8316 05:56:02.475769 14, 0x0, sum = 2
8317 05:56:02.476109 15, 0x0, sum = 3
8318 05:56:02.479068 16, 0x0, sum = 4
8319 05:56:02.479486 best_step = 14
8320 05:56:02.479813
8321 05:56:02.481933 ==
8322 05:56:02.482345 Dram Type= 6, Freq= 0, CH_1, rank 0
8323 05:56:02.488692 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8324 05:56:02.489138 ==
8325 05:56:02.489466 RX Vref Scan: 1
8326 05:56:02.489770
8327 05:56:02.491829 Set Vref Range= 24 -> 127
8328 05:56:02.492241
8329 05:56:02.495420 RX Vref 24 -> 127, step: 1
8330 05:56:02.496031
8331 05:56:02.498426 RX Delay 11 -> 252, step: 4
8332 05:56:02.498836
8333 05:56:02.501650 Set Vref, RX VrefLevel [Byte0]: 24
8334 05:56:02.505640 [Byte1]: 24
8335 05:56:02.506309
8336 05:56:02.508238 Set Vref, RX VrefLevel [Byte0]: 25
8337 05:56:02.511724 [Byte1]: 25
8338 05:56:02.512141
8339 05:56:02.514887 Set Vref, RX VrefLevel [Byte0]: 26
8340 05:56:02.518184 [Byte1]: 26
8341 05:56:02.522371
8342 05:56:02.522887 Set Vref, RX VrefLevel [Byte0]: 27
8343 05:56:02.525324 [Byte1]: 27
8344 05:56:02.529978
8345 05:56:02.530513 Set Vref, RX VrefLevel [Byte0]: 28
8346 05:56:02.533314 [Byte1]: 28
8347 05:56:02.537096
8348 05:56:02.537507 Set Vref, RX VrefLevel [Byte0]: 29
8349 05:56:02.540602 [Byte1]: 29
8350 05:56:02.544835
8351 05:56:02.545402 Set Vref, RX VrefLevel [Byte0]: 30
8352 05:56:02.548084 [Byte1]: 30
8353 05:56:02.552293
8354 05:56:02.552742 Set Vref, RX VrefLevel [Byte0]: 31
8355 05:56:02.555554 [Byte1]: 31
8356 05:56:02.560156
8357 05:56:02.560683 Set Vref, RX VrefLevel [Byte0]: 32
8358 05:56:02.563098 [Byte1]: 32
8359 05:56:02.567709
8360 05:56:02.568211 Set Vref, RX VrefLevel [Byte0]: 33
8361 05:56:02.571086 [Byte1]: 33
8362 05:56:02.575241
8363 05:56:02.575649 Set Vref, RX VrefLevel [Byte0]: 34
8364 05:56:02.578806 [Byte1]: 34
8365 05:56:02.582510
8366 05:56:02.582948 Set Vref, RX VrefLevel [Byte0]: 35
8367 05:56:02.585974 [Byte1]: 35
8368 05:56:02.590158
8369 05:56:02.590562 Set Vref, RX VrefLevel [Byte0]: 36
8370 05:56:02.593426 [Byte1]: 36
8371 05:56:02.597527
8372 05:56:02.597747 Set Vref, RX VrefLevel [Byte0]: 37
8373 05:56:02.601178 [Byte1]: 37
8374 05:56:02.605781
8375 05:56:02.605997 Set Vref, RX VrefLevel [Byte0]: 38
8376 05:56:02.608753 [Byte1]: 38
8377 05:56:02.613010
8378 05:56:02.613416 Set Vref, RX VrefLevel [Byte0]: 39
8379 05:56:02.616363 [Byte1]: 39
8380 05:56:02.621013
8381 05:56:02.621615 Set Vref, RX VrefLevel [Byte0]: 40
8382 05:56:02.623847 [Byte1]: 40
8383 05:56:02.628742
8384 05:56:02.629208 Set Vref, RX VrefLevel [Byte0]: 41
8385 05:56:02.631660 [Byte1]: 41
8386 05:56:02.635878
8387 05:56:02.636353 Set Vref, RX VrefLevel [Byte0]: 42
8388 05:56:02.639234 [Byte1]: 42
8389 05:56:02.643443
8390 05:56:02.643854 Set Vref, RX VrefLevel [Byte0]: 43
8391 05:56:02.646982 [Byte1]: 43
8392 05:56:02.651430
8393 05:56:02.651867 Set Vref, RX VrefLevel [Byte0]: 44
8394 05:56:02.654511 [Byte1]: 44
8395 05:56:02.658582
8396 05:56:02.658991 Set Vref, RX VrefLevel [Byte0]: 45
8397 05:56:02.662052 [Byte1]: 45
8398 05:56:02.666644
8399 05:56:02.667197 Set Vref, RX VrefLevel [Byte0]: 46
8400 05:56:02.669729 [Byte1]: 46
8401 05:56:02.674887
8402 05:56:02.675446 Set Vref, RX VrefLevel [Byte0]: 47
8403 05:56:02.677365 [Byte1]: 47
8404 05:56:02.681947
8405 05:56:02.682520 Set Vref, RX VrefLevel [Byte0]: 48
8406 05:56:02.685396 [Byte1]: 48
8407 05:56:02.689584
8408 05:56:02.690137 Set Vref, RX VrefLevel [Byte0]: 49
8409 05:56:02.692871 [Byte1]: 49
8410 05:56:02.697113
8411 05:56:02.700171 Set Vref, RX VrefLevel [Byte0]: 50
8412 05:56:02.703555 [Byte1]: 50
8413 05:56:02.704009
8414 05:56:02.706991 Set Vref, RX VrefLevel [Byte0]: 51
8415 05:56:02.710183 [Byte1]: 51
8416 05:56:02.710757
8417 05:56:02.713521 Set Vref, RX VrefLevel [Byte0]: 52
8418 05:56:02.717034 [Byte1]: 52
8419 05:56:02.717507
8420 05:56:02.719974 Set Vref, RX VrefLevel [Byte0]: 53
8421 05:56:02.723384 [Byte1]: 53
8422 05:56:02.727335
8423 05:56:02.727789 Set Vref, RX VrefLevel [Byte0]: 54
8424 05:56:02.730934 [Byte1]: 54
8425 05:56:02.735184
8426 05:56:02.735642 Set Vref, RX VrefLevel [Byte0]: 55
8427 05:56:02.738751 [Byte1]: 55
8428 05:56:02.742972
8429 05:56:02.743558 Set Vref, RX VrefLevel [Byte0]: 56
8430 05:56:02.746387 [Byte1]: 56
8431 05:56:02.750208
8432 05:56:02.750772 Set Vref, RX VrefLevel [Byte0]: 57
8433 05:56:02.753448 [Byte1]: 57
8434 05:56:02.758191
8435 05:56:02.758738 Set Vref, RX VrefLevel [Byte0]: 58
8436 05:56:02.761150 [Byte1]: 58
8437 05:56:02.765567
8438 05:56:02.766065 Set Vref, RX VrefLevel [Byte0]: 59
8439 05:56:02.768777 [Byte1]: 59
8440 05:56:02.773224
8441 05:56:02.773774 Set Vref, RX VrefLevel [Byte0]: 60
8442 05:56:02.776782 [Byte1]: 60
8443 05:56:02.781352
8444 05:56:02.781903 Set Vref, RX VrefLevel [Byte0]: 61
8445 05:56:02.784092 [Byte1]: 61
8446 05:56:02.788539
8447 05:56:02.789140 Set Vref, RX VrefLevel [Byte0]: 62
8448 05:56:02.791791 [Byte1]: 62
8449 05:56:02.795885
8450 05:56:02.796515 Set Vref, RX VrefLevel [Byte0]: 63
8451 05:56:02.799138 [Byte1]: 63
8452 05:56:02.803637
8453 05:56:02.804195 Set Vref, RX VrefLevel [Byte0]: 64
8454 05:56:02.807276 [Byte1]: 64
8455 05:56:02.811404
8456 05:56:02.811863 Set Vref, RX VrefLevel [Byte0]: 65
8457 05:56:02.814436 [Byte1]: 65
8458 05:56:02.818514
8459 05:56:02.819057 Set Vref, RX VrefLevel [Byte0]: 66
8460 05:56:02.822765 [Byte1]: 66
8461 05:56:02.826655
8462 05:56:02.827114 Set Vref, RX VrefLevel [Byte0]: 67
8463 05:56:02.829529 [Byte1]: 67
8464 05:56:02.833836
8465 05:56:02.834294 Set Vref, RX VrefLevel [Byte0]: 68
8466 05:56:02.837270 [Byte1]: 68
8467 05:56:02.841996
8468 05:56:02.842800 Set Vref, RX VrefLevel [Byte0]: 69
8469 05:56:02.844909 [Byte1]: 69
8470 05:56:02.849623
8471 05:56:02.850097 Set Vref, RX VrefLevel [Byte0]: 70
8472 05:56:02.852497 [Byte1]: 70
8473 05:56:02.857318
8474 05:56:02.857884 Set Vref, RX VrefLevel [Byte0]: 71
8475 05:56:02.860247 [Byte1]: 71
8476 05:56:02.864885
8477 05:56:02.865439 Set Vref, RX VrefLevel [Byte0]: 72
8478 05:56:02.867602 [Byte1]: 72
8479 05:56:02.872050
8480 05:56:02.872512 Set Vref, RX VrefLevel [Byte0]: 73
8481 05:56:02.875879 [Byte1]: 73
8482 05:56:02.879841
8483 05:56:02.880303 Set Vref, RX VrefLevel [Byte0]: 74
8484 05:56:02.883323 [Byte1]: 74
8485 05:56:02.887787
8486 05:56:02.888353 Set Vref, RX VrefLevel [Byte0]: 75
8487 05:56:02.890763 [Byte1]: 75
8488 05:56:02.895167
8489 05:56:02.895727 Set Vref, RX VrefLevel [Byte0]: 76
8490 05:56:02.898149 [Byte1]: 76
8491 05:56:02.902948
8492 05:56:02.903514 Set Vref, RX VrefLevel [Byte0]: 77
8493 05:56:02.906253 [Byte1]: 77
8494 05:56:02.910397
8495 05:56:02.910954 Set Vref, RX VrefLevel [Byte0]: 78
8496 05:56:02.913526 [Byte1]: 78
8497 05:56:02.917841
8498 05:56:02.918304 Set Vref, RX VrefLevel [Byte0]: 79
8499 05:56:02.921218 [Byte1]: 79
8500 05:56:02.925554
8501 05:56:02.926128 Final RX Vref Byte 0 = 63 to rank0
8502 05:56:02.929387 Final RX Vref Byte 1 = 55 to rank0
8503 05:56:02.932229 Final RX Vref Byte 0 = 63 to rank1
8504 05:56:02.935520 Final RX Vref Byte 1 = 55 to rank1==
8505 05:56:02.938625 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 05:56:02.945245 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8507 05:56:02.945791 ==
8508 05:56:02.946157 DQS Delay:
8509 05:56:02.946495 DQS0 = 0, DQS1 = 0
8510 05:56:02.949154 DQM Delay:
8511 05:56:02.949703 DQM0 = 128, DQM1 = 124
8512 05:56:02.952158 DQ Delay:
8513 05:56:02.955365 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
8514 05:56:02.958871 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =124
8515 05:56:02.961792 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8516 05:56:02.965254 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8517 05:56:02.965714
8518 05:56:02.966076
8519 05:56:02.966411
8520 05:56:02.968199 [DramC_TX_OE_Calibration] TA2
8521 05:56:02.971553 Original DQ_B0 (3 6) =30, OEN = 27
8522 05:56:02.974865 Original DQ_B1 (3 6) =30, OEN = 27
8523 05:56:02.978283 24, 0x0, End_B0=24 End_B1=24
8524 05:56:02.978770 25, 0x0, End_B0=25 End_B1=25
8525 05:56:02.981528 26, 0x0, End_B0=26 End_B1=26
8526 05:56:02.984919 27, 0x0, End_B0=27 End_B1=27
8527 05:56:02.988172 28, 0x0, End_B0=28 End_B1=28
8528 05:56:02.991539 29, 0x0, End_B0=29 End_B1=29
8529 05:56:02.992008 30, 0x0, End_B0=30 End_B1=30
8530 05:56:02.995311 31, 0x4141, End_B0=30 End_B1=30
8531 05:56:02.998086 Byte0 end_step=30 best_step=27
8532 05:56:03.001671 Byte1 end_step=30 best_step=27
8533 05:56:03.004886 Byte0 TX OE(2T, 0.5T) = (3, 3)
8534 05:56:03.008578 Byte1 TX OE(2T, 0.5T) = (3, 3)
8535 05:56:03.009183
8536 05:56:03.009553
8537 05:56:03.014933 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8538 05:56:03.018227 CH1 RK0: MR19=303, MR18=2424
8539 05:56:03.024670 CH1_RK0: MR19=0x303, MR18=0x2424, DQSOSC=391, MR23=63, INC=24, DEC=16
8540 05:56:03.025292
8541 05:56:03.028263 ----->DramcWriteLeveling(PI) begin...
8542 05:56:03.028772 ==
8543 05:56:03.031635 Dram Type= 6, Freq= 0, CH_1, rank 1
8544 05:56:03.034702 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8545 05:56:03.035159 ==
8546 05:56:03.038031 Write leveling (Byte 0): 22 => 22
8547 05:56:03.041446 Write leveling (Byte 1): 21 => 21
8548 05:56:03.044501 DramcWriteLeveling(PI) end<-----
8549 05:56:03.045108
8550 05:56:03.045538 ==
8551 05:56:03.048229 Dram Type= 6, Freq= 0, CH_1, rank 1
8552 05:56:03.051304 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8553 05:56:03.051760 ==
8554 05:56:03.054145 [Gating] SW mode calibration
8555 05:56:03.061711 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8556 05:56:03.067410 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8557 05:56:03.071102 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
8558 05:56:03.077707 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8559 05:56:03.080753 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8560 05:56:03.084219 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8561 05:56:03.090696 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8562 05:56:03.094018 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8563 05:56:03.097444 0 12 24 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
8564 05:56:03.104191 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8565 05:56:03.107628 0 13 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
8566 05:56:03.110693 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8567 05:56:03.117058 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8568 05:56:03.120476 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8569 05:56:03.124311 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8570 05:56:03.130768 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8571 05:56:03.133938 0 13 24 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
8572 05:56:03.137190 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8573 05:56:03.143760 0 14 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8574 05:56:03.146857 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8575 05:56:03.150320 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8576 05:56:03.157219 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8577 05:56:03.160469 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8578 05:56:03.163929 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8579 05:56:03.170107 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8580 05:56:03.173686 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8581 05:56:03.176854 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8582 05:56:03.183286 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8583 05:56:03.186441 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8584 05:56:03.190413 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8585 05:56:03.196616 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8586 05:56:03.199804 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8587 05:56:03.203268 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8588 05:56:03.209572 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8589 05:56:03.213198 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8590 05:56:03.216135 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8591 05:56:03.222902 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8592 05:56:03.226010 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8593 05:56:03.229274 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8594 05:56:03.236106 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8595 05:56:03.239566 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8596 05:56:03.243027 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8597 05:56:03.249445 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8598 05:56:03.249910 Total UI for P1: 0, mck2ui 16
8599 05:56:03.252607 best dqsien dly found for B0: ( 1, 0, 26)
8600 05:56:03.259480 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8601 05:56:03.263013 Total UI for P1: 0, mck2ui 16
8602 05:56:03.266246 best dqsien dly found for B1: ( 1, 1, 0)
8603 05:56:03.269388 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8604 05:56:03.272618 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8605 05:56:03.273216
8606 05:56:03.275594 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8607 05:56:03.278976 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8608 05:56:03.282443 [Gating] SW calibration Done
8609 05:56:03.283050 ==
8610 05:56:03.285872 Dram Type= 6, Freq= 0, CH_1, rank 1
8611 05:56:03.289220 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8612 05:56:03.289790 ==
8613 05:56:03.292110 RX Vref Scan: 0
8614 05:56:03.292683
8615 05:56:03.295423 RX Vref 0 -> 0, step: 1
8616 05:56:03.295881
8617 05:56:03.296249 RX Delay 0 -> 252, step: 8
8618 05:56:03.302015 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8619 05:56:03.305795 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8620 05:56:03.308649 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8621 05:56:03.312125 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8622 05:56:03.315110 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8623 05:56:03.321884 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8624 05:56:03.325539 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8625 05:56:03.328795 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8626 05:56:03.332016 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8627 05:56:03.334942 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8628 05:56:03.342051 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8629 05:56:03.344831 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8630 05:56:03.348236 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8631 05:56:03.351522 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8632 05:56:03.354753 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8633 05:56:03.361865 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8634 05:56:03.362431 ==
8635 05:56:03.364918 Dram Type= 6, Freq= 0, CH_1, rank 1
8636 05:56:03.368030 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8637 05:56:03.368506 ==
8638 05:56:03.369033 DQS Delay:
8639 05:56:03.371616 DQS0 = 0, DQS1 = 0
8640 05:56:03.372090 DQM Delay:
8641 05:56:03.374839 DQM0 = 131, DQM1 = 125
8642 05:56:03.375300 DQ Delay:
8643 05:56:03.378108 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =131
8644 05:56:03.381713 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =135
8645 05:56:03.385193 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8646 05:56:03.391544 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8647 05:56:03.392109
8648 05:56:03.392475
8649 05:56:03.392872 ==
8650 05:56:03.394709 Dram Type= 6, Freq= 0, CH_1, rank 1
8651 05:56:03.398019 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8652 05:56:03.398494 ==
8653 05:56:03.398973
8654 05:56:03.399545
8655 05:56:03.401132 TX Vref Scan disable
8656 05:56:03.401589 == TX Byte 0 ==
8657 05:56:03.407985 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8658 05:56:03.411332 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8659 05:56:03.411806 == TX Byte 1 ==
8660 05:56:03.417600 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8661 05:56:03.421312 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8662 05:56:03.421996 ==
8663 05:56:03.424441 Dram Type= 6, Freq= 0, CH_1, rank 1
8664 05:56:03.427720 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8665 05:56:03.428185 ==
8666 05:56:03.441977
8667 05:56:03.445481 TX Vref early break, caculate TX vref
8668 05:56:03.449095 TX Vref=16, minBit 2, minWin=22, winSum=377
8669 05:56:03.452396 TX Vref=18, minBit 0, minWin=23, winSum=386
8670 05:56:03.455522 TX Vref=20, minBit 0, minWin=24, winSum=398
8671 05:56:03.458450 TX Vref=22, minBit 5, minWin=23, winSum=400
8672 05:56:03.462069 TX Vref=24, minBit 0, minWin=23, winSum=407
8673 05:56:03.468585 TX Vref=26, minBit 0, minWin=25, winSum=416
8674 05:56:03.471962 TX Vref=28, minBit 0, minWin=25, winSum=418
8675 05:56:03.475155 TX Vref=30, minBit 0, minWin=25, winSum=415
8676 05:56:03.478288 TX Vref=32, minBit 0, minWin=24, winSum=404
8677 05:56:03.481564 TX Vref=34, minBit 0, minWin=23, winSum=400
8678 05:56:03.484882 TX Vref=36, minBit 0, minWin=23, winSum=391
8679 05:56:03.491659 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8680 05:56:03.492297
8681 05:56:03.494988 Final TX Range 0 Vref 28
8682 05:56:03.495451
8683 05:56:03.495970 ==
8684 05:56:03.498604 Dram Type= 6, Freq= 0, CH_1, rank 1
8685 05:56:03.501396 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8686 05:56:03.501859 ==
8687 05:56:03.502226
8688 05:56:03.505110
8689 05:56:03.505764 TX Vref Scan disable
8690 05:56:03.511531 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8691 05:56:03.511993 == TX Byte 0 ==
8692 05:56:03.514784 u2DelayCellOfst[0]=14 cells (4 PI)
8693 05:56:03.518086 u2DelayCellOfst[1]=7 cells (2 PI)
8694 05:56:03.521261 u2DelayCellOfst[2]=0 cells (0 PI)
8695 05:56:03.524750 u2DelayCellOfst[3]=7 cells (2 PI)
8696 05:56:03.527930 u2DelayCellOfst[4]=7 cells (2 PI)
8697 05:56:03.531400 u2DelayCellOfst[5]=14 cells (4 PI)
8698 05:56:03.534427 u2DelayCellOfst[6]=14 cells (4 PI)
8699 05:56:03.538027 u2DelayCellOfst[7]=3 cells (1 PI)
8700 05:56:03.541499 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8701 05:56:03.544700 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8702 05:56:03.547895 == TX Byte 1 ==
8703 05:56:03.551405 u2DelayCellOfst[8]=0 cells (0 PI)
8704 05:56:03.551984 u2DelayCellOfst[9]=3 cells (1 PI)
8705 05:56:03.554761 u2DelayCellOfst[10]=10 cells (3 PI)
8706 05:56:03.558056 u2DelayCellOfst[11]=0 cells (0 PI)
8707 05:56:03.561194 u2DelayCellOfst[12]=14 cells (4 PI)
8708 05:56:03.564902 u2DelayCellOfst[13]=18 cells (5 PI)
8709 05:56:03.567995 u2DelayCellOfst[14]=18 cells (5 PI)
8710 05:56:03.571040 u2DelayCellOfst[15]=14 cells (4 PI)
8711 05:56:03.578025 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8712 05:56:03.580950 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8713 05:56:03.581416 DramC Write-DBI on
8714 05:56:03.581783 ==
8715 05:56:03.584354 Dram Type= 6, Freq= 0, CH_1, rank 1
8716 05:56:03.590638 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8717 05:56:03.591106 ==
8718 05:56:03.591468
8719 05:56:03.591799
8720 05:56:03.593633 TX Vref Scan disable
8721 05:56:03.594215 == TX Byte 0 ==
8722 05:56:03.600851 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8723 05:56:03.601446 == TX Byte 1 ==
8724 05:56:03.603666 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8725 05:56:03.607065 DramC Write-DBI off
8726 05:56:03.607630
8727 05:56:03.608138 [DATLAT]
8728 05:56:03.611027 Freq=1600, CH1 RK1
8729 05:56:03.611480
8730 05:56:03.611836 DATLAT Default: 0xe
8731 05:56:03.613673 0, 0xFFFF, sum = 0
8732 05:56:03.614134 1, 0xFFFF, sum = 0
8733 05:56:03.617144 2, 0xFFFF, sum = 0
8734 05:56:03.617604 3, 0xFFFF, sum = 0
8735 05:56:03.620514 4, 0xFFFF, sum = 0
8736 05:56:03.621039 5, 0xFFFF, sum = 0
8737 05:56:03.623851 6, 0xFFFF, sum = 0
8738 05:56:03.624308 7, 0xFFFF, sum = 0
8739 05:56:03.627373 8, 0xFFFF, sum = 0
8740 05:56:03.630311 9, 0xFFFF, sum = 0
8741 05:56:03.630870 10, 0xFFFF, sum = 0
8742 05:56:03.633942 11, 0xFFFF, sum = 0
8743 05:56:03.634440 12, 0x8F7F, sum = 0
8744 05:56:03.636676 13, 0x0, sum = 1
8745 05:56:03.637255 14, 0x0, sum = 2
8746 05:56:03.640791 15, 0x0, sum = 3
8747 05:56:03.641361 16, 0x0, sum = 4
8748 05:56:03.641735 best_step = 14
8749 05:56:03.642072
8750 05:56:03.643529 ==
8751 05:56:03.647139 Dram Type= 6, Freq= 0, CH_1, rank 1
8752 05:56:03.650255 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8753 05:56:03.650820 ==
8754 05:56:03.651193 RX Vref Scan: 0
8755 05:56:03.651537
8756 05:56:03.653423 RX Vref 0 -> 0, step: 1
8757 05:56:03.653930
8758 05:56:03.656658 RX Delay 3 -> 252, step: 4
8759 05:56:03.660431 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8760 05:56:03.666647 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8761 05:56:03.669737 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8762 05:56:03.673055 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8763 05:56:03.676327 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8764 05:56:03.679690 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8765 05:56:03.686874 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8766 05:56:03.689695 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8767 05:56:03.692932 iDelay=195, Bit 8, Center 106 (51 ~ 162) 112
8768 05:56:03.696302 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8769 05:56:03.699697 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8770 05:56:03.706401 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8771 05:56:03.709347 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8772 05:56:03.712845 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8773 05:56:03.716343 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8774 05:56:03.719543 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8775 05:56:03.722936 ==
8776 05:56:03.726214 Dram Type= 6, Freq= 0, CH_1, rank 1
8777 05:56:03.729695 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8778 05:56:03.730162 ==
8779 05:56:03.730530 DQS Delay:
8780 05:56:03.732861 DQS0 = 0, DQS1 = 0
8781 05:56:03.733327 DQM Delay:
8782 05:56:03.736200 DQM0 = 127, DQM1 = 123
8783 05:56:03.736663 DQ Delay:
8784 05:56:03.739167 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8785 05:56:03.742690 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8786 05:56:03.746199 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =114
8787 05:56:03.749721 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8788 05:56:03.750186
8789 05:56:03.750549
8790 05:56:03.750882
8791 05:56:03.752380 [DramC_TX_OE_Calibration] TA2
8792 05:56:03.755777 Original DQ_B0 (3 6) =30, OEN = 27
8793 05:56:03.759941 Original DQ_B1 (3 6) =30, OEN = 27
8794 05:56:03.763039 24, 0x0, End_B0=24 End_B1=24
8795 05:56:03.765964 25, 0x0, End_B0=25 End_B1=25
8796 05:56:03.766430 26, 0x0, End_B0=26 End_B1=26
8797 05:56:03.769223 27, 0x0, End_B0=27 End_B1=27
8798 05:56:03.772584 28, 0x0, End_B0=28 End_B1=28
8799 05:56:03.775447 29, 0x0, End_B0=29 End_B1=29
8800 05:56:03.779173 30, 0x0, End_B0=30 End_B1=30
8801 05:56:03.779665 31, 0x5151, End_B0=30 End_B1=30
8802 05:56:03.782371 Byte0 end_step=30 best_step=27
8803 05:56:03.786066 Byte1 end_step=30 best_step=27
8804 05:56:03.788909 Byte0 TX OE(2T, 0.5T) = (3, 3)
8805 05:56:03.792662 Byte1 TX OE(2T, 0.5T) = (3, 3)
8806 05:56:03.793291
8807 05:56:03.793855
8808 05:56:03.798979 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8809 05:56:03.802184 CH1 RK1: MR19=303, MR18=1E1E
8810 05:56:03.808770 CH1_RK1: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
8811 05:56:03.812010 [RxdqsGatingPostProcess] freq 1600
8812 05:56:03.818572 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8813 05:56:03.822010 Pre-setting of DQS Precalculation
8814 05:56:03.825402 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8815 05:56:03.831694 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8816 05:56:03.838377 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8817 05:56:03.841589
8818 05:56:03.842137
8819 05:56:03.842511 [Calibration Summary] 3200 Mbps
8820 05:56:03.844822 CH 0, Rank 0
8821 05:56:03.845283 SW Impedance : PASS
8822 05:56:03.848212 DUTY Scan : NO K
8823 05:56:03.851869 ZQ Calibration : PASS
8824 05:56:03.852437 Jitter Meter : NO K
8825 05:56:03.854995 CBT Training : PASS
8826 05:56:03.858126 Write leveling : PASS
8827 05:56:03.858665 RX DQS gating : PASS
8828 05:56:03.861948 RX DQ/DQS(RDDQC) : PASS
8829 05:56:03.865438 TX DQ/DQS : PASS
8830 05:56:03.866001 RX DATLAT : PASS
8831 05:56:03.868563 RX DQ/DQS(Engine): PASS
8832 05:56:03.871551 TX OE : PASS
8833 05:56:03.872012 All Pass.
8834 05:56:03.872379
8835 05:56:03.872860 CH 0, Rank 1
8836 05:56:03.875020 SW Impedance : PASS
8837 05:56:03.878494 DUTY Scan : NO K
8838 05:56:03.879056 ZQ Calibration : PASS
8839 05:56:03.881315 Jitter Meter : NO K
8840 05:56:03.884898 CBT Training : PASS
8841 05:56:03.885460 Write leveling : PASS
8842 05:56:03.888152 RX DQS gating : PASS
8843 05:56:03.890897 RX DQ/DQS(RDDQC) : PASS
8844 05:56:03.891360 TX DQ/DQS : PASS
8845 05:56:03.894639 RX DATLAT : PASS
8846 05:56:03.895103 RX DQ/DQS(Engine): PASS
8847 05:56:03.898090 TX OE : PASS
8848 05:56:03.898653 All Pass.
8849 05:56:03.899021
8850 05:56:03.901421 CH 1, Rank 0
8851 05:56:03.901986 SW Impedance : PASS
8852 05:56:03.904247 DUTY Scan : NO K
8853 05:56:03.907956 ZQ Calibration : PASS
8854 05:56:03.908525 Jitter Meter : NO K
8855 05:56:03.910968 CBT Training : PASS
8856 05:56:03.914466 Write leveling : PASS
8857 05:56:03.915046 RX DQS gating : PASS
8858 05:56:03.917644 RX DQ/DQS(RDDQC) : PASS
8859 05:56:03.921337 TX DQ/DQS : PASS
8860 05:56:03.921900 RX DATLAT : PASS
8861 05:56:03.924224 RX DQ/DQS(Engine): PASS
8862 05:56:03.927348 TX OE : PASS
8863 05:56:03.927812 All Pass.
8864 05:56:03.928181
8865 05:56:03.928614 CH 1, Rank 1
8866 05:56:03.931105 SW Impedance : PASS
8867 05:56:03.934275 DUTY Scan : NO K
8868 05:56:03.934732 ZQ Calibration : PASS
8869 05:56:03.937509 Jitter Meter : NO K
8870 05:56:03.941376 CBT Training : PASS
8871 05:56:03.941938 Write leveling : PASS
8872 05:56:03.944825 RX DQS gating : PASS
8873 05:56:03.947511 RX DQ/DQS(RDDQC) : PASS
8874 05:56:03.947976 TX DQ/DQS : PASS
8875 05:56:03.950649 RX DATLAT : PASS
8876 05:56:03.954159 RX DQ/DQS(Engine): PASS
8877 05:56:03.954682 TX OE : PASS
8878 05:56:03.955231 All Pass.
8879 05:56:03.957766
8880 05:56:03.958222 DramC Write-DBI on
8881 05:56:03.961364 PER_BANK_REFRESH: Hybrid Mode
8882 05:56:03.961933 TX_TRACKING: ON
8883 05:56:03.970615 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8884 05:56:03.977184 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8885 05:56:03.987438 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8886 05:56:03.990537 [FAST_K] Save calibration result to emmc
8887 05:56:03.993634 sync common calibartion params.
8888 05:56:03.994242 sync cbt_mode0:0, 1:0
8889 05:56:03.997351 dram_init: ddr_geometry: 0
8890 05:56:04.000913 dram_init: ddr_geometry: 0
8891 05:56:04.001474 dram_init: ddr_geometry: 0
8892 05:56:04.004003 0:dram_rank_size:80000000
8893 05:56:04.006855 1:dram_rank_size:80000000
8894 05:56:04.010563 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8895 05:56:04.013431 DFS_SHUFFLE_HW_MODE: ON
8896 05:56:04.017115 dramc_set_vcore_voltage set vcore to 725000
8897 05:56:04.020105 Read voltage for 1600, 0
8898 05:56:04.020563 Vio18 = 0
8899 05:56:04.023965 Vcore = 725000
8900 05:56:04.024525 Vdram = 0
8901 05:56:04.025072 Vddq = 0
8902 05:56:04.025568 Vmddr = 0
8903 05:56:04.026852 switch to 3200 Mbps bootup
8904 05:56:04.029845 [DramcRunTimeConfig]
8905 05:56:04.030303 PHYPLL
8906 05:56:04.033167 DPM_CONTROL_AFTERK: ON
8907 05:56:04.033627 PER_BANK_REFRESH: ON
8908 05:56:04.036942 REFRESH_OVERHEAD_REDUCTION: ON
8909 05:56:04.040281 CMD_PICG_NEW_MODE: OFF
8910 05:56:04.040897 XRTWTW_NEW_MODE: ON
8911 05:56:04.043713 XRTRTR_NEW_MODE: ON
8912 05:56:04.044270 TX_TRACKING: ON
8913 05:56:04.046733 RDSEL_TRACKING: OFF
8914 05:56:04.049790 DQS Precalculation for DVFS: ON
8915 05:56:04.050253 RX_TRACKING: OFF
8916 05:56:04.053366 HW_GATING DBG: ON
8917 05:56:04.053933 ZQCS_ENABLE_LP4: ON
8918 05:56:04.056796 RX_PICG_NEW_MODE: ON
8919 05:56:04.057371 TX_PICG_NEW_MODE: ON
8920 05:56:04.059610 ENABLE_RX_DCM_DPHY: ON
8921 05:56:04.063298 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8922 05:56:04.066278 DUMMY_READ_FOR_TRACKING: OFF
8923 05:56:04.066740 !!! SPM_CONTROL_AFTERK: OFF
8924 05:56:04.069864 !!! SPM could not control APHY
8925 05:56:04.073289 IMPEDANCE_TRACKING: ON
8926 05:56:04.073775 TEMP_SENSOR: ON
8927 05:56:04.076427 HW_SAVE_FOR_SR: OFF
8928 05:56:04.079913 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8929 05:56:04.083233 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8930 05:56:04.083753 Read ODT Tracking: ON
8931 05:56:04.086380 Refresh Rate DeBounce: ON
8932 05:56:04.089304 DFS_NO_QUEUE_FLUSH: ON
8933 05:56:04.092926 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8934 05:56:04.093522 ENABLE_DFS_RUNTIME_MRW: OFF
8935 05:56:04.095980 DDR_RESERVE_NEW_MODE: ON
8936 05:56:04.099082 MR_CBT_SWITCH_FREQ: ON
8937 05:56:04.099640 =========================
8938 05:56:04.119773 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8939 05:56:04.122876 dram_init: ddr_geometry: 0
8940 05:56:04.140938 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8941 05:56:04.144196 dram_init: dram init end (result: 0)
8942 05:56:04.150821 DRAM-K: Full calibration passed in 23449 msecs
8943 05:56:04.154052 MRC: failed to locate region type 0.
8944 05:56:04.154521 DRAM rank0 size:0x80000000,
8945 05:56:04.157503 DRAM rank1 size=0x80000000
8946 05:56:04.167242 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8947 05:56:04.174212 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8948 05:56:04.180641 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8949 05:56:04.187489 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8950 05:56:04.190889 DRAM rank0 size:0x80000000,
8951 05:56:04.194210 DRAM rank1 size=0x80000000
8952 05:56:04.194763 CBMEM:
8953 05:56:04.197341 IMD: root @ 0xfffff000 254 entries.
8954 05:56:04.200608 IMD: root @ 0xffffec00 62 entries.
8955 05:56:04.203945 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8956 05:56:04.207245 WARNING: RO_VPD is uninitialized or empty.
8957 05:56:04.213995 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8958 05:56:04.220266 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8959 05:56:04.233338 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8960 05:56:04.244548 BS: romstage times (exec / console): total (unknown) / 22985 ms
8961 05:56:04.245072
8962 05:56:04.245436
8963 05:56:04.254780 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8964 05:56:04.257908 ARM64: Exception handlers installed.
8965 05:56:04.261738 ARM64: Testing exception
8966 05:56:04.264470 ARM64: Done test exception
8967 05:56:04.264969 Enumerating buses...
8968 05:56:04.268277 Show all devs... Before device enumeration.
8969 05:56:04.271289 Root Device: enabled 1
8970 05:56:04.275095 CPU_CLUSTER: 0: enabled 1
8971 05:56:04.275651 CPU: 00: enabled 1
8972 05:56:04.278438 Compare with tree...
8973 05:56:04.278998 Root Device: enabled 1
8974 05:56:04.281003 CPU_CLUSTER: 0: enabled 1
8975 05:56:04.284844 CPU: 00: enabled 1
8976 05:56:04.285295 Root Device scanning...
8977 05:56:04.288200 scan_static_bus for Root Device
8978 05:56:04.291263 CPU_CLUSTER: 0 enabled
8979 05:56:04.294817 scan_static_bus for Root Device done
8980 05:56:04.297491 scan_bus: bus Root Device finished in 8 msecs
8981 05:56:04.297946 done
8982 05:56:04.304691 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8983 05:56:04.308244 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8984 05:56:04.314795 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8985 05:56:04.317645 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8986 05:56:04.321155 Allocating resources...
8987 05:56:04.324329 Reading resources...
8988 05:56:04.327638 Root Device read_resources bus 0 link: 0
8989 05:56:04.328098 DRAM rank0 size:0x80000000,
8990 05:56:04.330796 DRAM rank1 size=0x80000000
8991 05:56:04.334404 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8992 05:56:04.337364 CPU: 00 missing read_resources
8993 05:56:04.340689 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8994 05:56:04.347123 Root Device read_resources bus 0 link: 0 done
8995 05:56:04.347662 Done reading resources.
8996 05:56:04.354114 Show resources in subtree (Root Device)...After reading.
8997 05:56:04.357549 Root Device child on link 0 CPU_CLUSTER: 0
8998 05:56:04.360862 CPU_CLUSTER: 0 child on link 0 CPU: 00
8999 05:56:04.370384 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9000 05:56:04.370843 CPU: 00
9001 05:56:04.373556 Root Device assign_resources, bus 0 link: 0
9002 05:56:04.377196 CPU_CLUSTER: 0 missing set_resources
9003 05:56:04.383810 Root Device assign_resources, bus 0 link: 0 done
9004 05:56:04.384264 Done setting resources.
9005 05:56:04.390227 Show resources in subtree (Root Device)...After assigning values.
9006 05:56:04.393510 Root Device child on link 0 CPU_CLUSTER: 0
9007 05:56:04.396649 CPU_CLUSTER: 0 child on link 0 CPU: 00
9008 05:56:04.406894 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9009 05:56:04.407460 CPU: 00
9010 05:56:04.409897 Done allocating resources.
9011 05:56:04.416696 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9012 05:56:04.417293 Enabling resources...
9013 05:56:04.417661 done.
9014 05:56:04.423052 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9015 05:56:04.423603 Initializing devices...
9016 05:56:04.426734 Root Device init
9017 05:56:04.427192 init hardware done!
9018 05:56:04.429818 0x00000018: ctrlr->caps
9019 05:56:04.433385 52.000 MHz: ctrlr->f_max
9020 05:56:04.433858 0.400 MHz: ctrlr->f_min
9021 05:56:04.436360 0x40ff8080: ctrlr->voltages
9022 05:56:04.439852 sclk: 390625
9023 05:56:04.440308 Bus Width = 1
9024 05:56:04.440674 sclk: 390625
9025 05:56:04.443048 Bus Width = 1
9026 05:56:04.443597 Early init status = 3
9027 05:56:04.449367 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9028 05:56:04.453052 in-header: 03 fc 00 00 01 00 00 00
9029 05:56:04.455875 in-data: 00
9030 05:56:04.459495 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9031 05:56:04.464199 in-header: 03 fd 00 00 00 00 00 00
9032 05:56:04.467561 in-data:
9033 05:56:04.470414 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9034 05:56:04.474043 in-header: 03 fc 00 00 01 00 00 00
9035 05:56:04.477725 in-data: 00
9036 05:56:04.480815 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9037 05:56:04.486262 in-header: 03 fd 00 00 00 00 00 00
9038 05:56:04.489534 in-data:
9039 05:56:04.492612 [SSUSB] Setting up USB HOST controller...
9040 05:56:04.496288 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9041 05:56:04.499351 [SSUSB] phy power-on done.
9042 05:56:04.502926 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9043 05:56:04.509222 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9044 05:56:04.512765 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9045 05:56:04.519459 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9046 05:56:04.526213 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9047 05:56:04.532814 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9048 05:56:04.538827 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9049 05:56:04.545440 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9050 05:56:04.548679 SPM: binary array size = 0x9dc
9051 05:56:04.552380 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9052 05:56:04.558561 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9053 05:56:04.565020 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9054 05:56:04.572021 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9055 05:56:04.575313 configure_display: Starting display init
9056 05:56:04.609298 anx7625_power_on_init: Init interface.
9057 05:56:04.612470 anx7625_disable_pd_protocol: Disabled PD feature.
9058 05:56:04.615502 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9059 05:56:04.643572 anx7625_start_dp_work: Secure OCM version=00
9060 05:56:04.646972 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9061 05:56:04.661894 sp_tx_get_edid_block: EDID Block = 1
9062 05:56:04.764589 Extracted contents:
9063 05:56:04.767757 header: 00 ff ff ff ff ff ff 00
9064 05:56:04.770929 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9065 05:56:04.774337 version: 01 04
9066 05:56:04.777986 basic params: 95 1f 11 78 0a
9067 05:56:04.780617 chroma info: 76 90 94 55 54 90 27 21 50 54
9068 05:56:04.784179 established: 00 00 00
9069 05:56:04.791201 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9070 05:56:04.794005 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9071 05:56:04.800948 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9072 05:56:04.808140 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9073 05:56:04.813851 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9074 05:56:04.817167 extensions: 00
9075 05:56:04.817628 checksum: fb
9076 05:56:04.817995
9077 05:56:04.820574 Manufacturer: IVO Model 57d Serial Number 0
9078 05:56:04.823793 Made week 0 of 2020
9079 05:56:04.824249 EDID version: 1.4
9080 05:56:04.827276 Digital display
9081 05:56:04.830194 6 bits per primary color channel
9082 05:56:04.830665 DisplayPort interface
9083 05:56:04.833402 Maximum image size: 31 cm x 17 cm
9084 05:56:04.837346 Gamma: 220%
9085 05:56:04.837924 Check DPMS levels
9086 05:56:04.840493 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9087 05:56:04.846890 First detailed timing is preferred timing
9088 05:56:04.847447 Established timings supported:
9089 05:56:04.850388 Standard timings supported:
9090 05:56:04.853365 Detailed timings
9091 05:56:04.856675 Hex of detail: 383680a07038204018303c0035ae10000019
9092 05:56:04.860593 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9093 05:56:04.867063 0780 0798 07c8 0820 hborder 0
9094 05:56:04.870239 0438 043b 0447 0458 vborder 0
9095 05:56:04.873578 -hsync -vsync
9096 05:56:04.874124 Did detailed timing
9097 05:56:04.880179 Hex of detail: 000000000000000000000000000000000000
9098 05:56:04.883118 Manufacturer-specified data, tag 0
9099 05:56:04.886686 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9100 05:56:04.890276 ASCII string: InfoVision
9101 05:56:04.893129 Hex of detail: 000000fe00523134304e574635205248200a
9102 05:56:04.896538 ASCII string: R140NWF5 RH
9103 05:56:04.897140 Checksum
9104 05:56:04.899738 Checksum: 0xfb (valid)
9105 05:56:04.903483 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9106 05:56:04.906391 DSI data_rate: 832800000 bps
9107 05:56:04.913176 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9108 05:56:04.916443 anx7625_parse_edid: pixelclock(138800).
9109 05:56:04.919718 hactive(1920), hsync(48), hfp(24), hbp(88)
9110 05:56:04.923009 vactive(1080), vsync(12), vfp(3), vbp(17)
9111 05:56:04.926532 anx7625_dsi_config: config dsi.
9112 05:56:04.932599 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9113 05:56:04.946661 anx7625_dsi_config: success to config DSI
9114 05:56:04.949367 anx7625_dp_start: MIPI phy setup OK.
9115 05:56:04.952966 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9116 05:56:04.956243 mtk_ddp_mode_set invalid vrefresh 60
9117 05:56:04.959662 main_disp_path_setup
9118 05:56:04.960211 ovl_layer_smi_id_en
9119 05:56:04.962848 ovl_layer_smi_id_en
9120 05:56:04.963413 ccorr_config
9121 05:56:04.963783 aal_config
9122 05:56:04.966543 gamma_config
9123 05:56:04.967096 postmask_config
9124 05:56:04.969373 dither_config
9125 05:56:04.972517 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9126 05:56:04.979245 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9127 05:56:04.982587 Root Device init finished in 552 msecs
9128 05:56:04.985874 CPU_CLUSTER: 0 init
9129 05:56:04.992577 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9130 05:56:04.995945 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9131 05:56:04.999287 APU_MBOX 0x190000b0 = 0x10001
9132 05:56:05.002384 APU_MBOX 0x190001b0 = 0x10001
9133 05:56:05.006014 APU_MBOX 0x190005b0 = 0x10001
9134 05:56:05.009120 APU_MBOX 0x190006b0 = 0x10001
9135 05:56:05.012687 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9136 05:56:05.025354 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9137 05:56:05.037849 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9138 05:56:05.044508 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9139 05:56:05.056110 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9140 05:56:05.065446 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9141 05:56:05.068444 CPU_CLUSTER: 0 init finished in 81 msecs
9142 05:56:05.072111 Devices initialized
9143 05:56:05.075388 Show all devs... After init.
9144 05:56:05.075942 Root Device: enabled 1
9145 05:56:05.078552 CPU_CLUSTER: 0: enabled 1
9146 05:56:05.081943 CPU: 00: enabled 1
9147 05:56:05.084450 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9148 05:56:05.088269 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9149 05:56:05.091483 ELOG: NV offset 0x57f000 size 0x1000
9150 05:56:05.098172 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9151 05:56:05.104799 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9152 05:56:05.108335 ELOG: Event(17) added with size 13 at 2023-12-25 05:56:05 UTC
9153 05:56:05.114565 out: cmd=0x121: 03 db 21 01 00 00 00 00
9154 05:56:05.117998 in-header: 03 da 00 00 2c 00 00 00
9155 05:56:05.128043 in-data: 89 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9156 05:56:05.134457 ELOG: Event(A1) added with size 10 at 2023-12-25 05:56:05 UTC
9157 05:56:05.141223 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9158 05:56:05.148400 ELOG: Event(A0) added with size 9 at 2023-12-25 05:56:05 UTC
9159 05:56:05.151390 elog_add_boot_reason: Logged dev mode boot
9160 05:56:05.157691 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9161 05:56:05.158244 Finalize devices...
9162 05:56:05.160789 Devices finalized
9163 05:56:05.164464 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9164 05:56:05.167548 Writing coreboot table at 0xffe64000
9165 05:56:05.170993 0. 000000000010a000-0000000000113fff: RAMSTAGE
9166 05:56:05.177818 1. 0000000040000000-00000000400fffff: RAM
9167 05:56:05.180983 2. 0000000040100000-000000004032afff: RAMSTAGE
9168 05:56:05.183797 3. 000000004032b000-00000000545fffff: RAM
9169 05:56:05.187561 4. 0000000054600000-000000005465ffff: BL31
9170 05:56:05.190828 5. 0000000054660000-00000000ffe63fff: RAM
9171 05:56:05.197298 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9172 05:56:05.200776 7. 0000000100000000-000000013fffffff: RAM
9173 05:56:05.204178 Passing 5 GPIOs to payload:
9174 05:56:05.207662 NAME | PORT | POLARITY | VALUE
9175 05:56:05.213933 EC in RW | 0x000000aa | low | undefined
9176 05:56:05.216911 EC interrupt | 0x00000005 | low | undefined
9177 05:56:05.220553 TPM interrupt | 0x000000ab | high | undefined
9178 05:56:05.226808 SD card detect | 0x00000011 | high | undefined
9179 05:56:05.230211 speaker enable | 0x00000093 | high | undefined
9180 05:56:05.233913 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9181 05:56:05.237022 in-header: 03 f8 00 00 02 00 00 00
9182 05:56:05.240366 in-data: 03 00
9183 05:56:05.243735 ADC[4]: Raw value=669327 ID=5
9184 05:56:05.244289 ADC[3]: Raw value=212549 ID=1
9185 05:56:05.246908 RAM Code: 0x51
9186 05:56:05.250401 ADC[6]: Raw value=74410 ID=0
9187 05:56:05.251000 ADC[5]: Raw value=211444 ID=1
9188 05:56:05.253390 SKU Code: 0x1
9189 05:56:05.256905 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 97e2
9190 05:56:05.260064 coreboot table: 964 bytes.
9191 05:56:05.263363 IMD ROOT 0. 0xfffff000 0x00001000
9192 05:56:05.267200 IMD SMALL 1. 0xffffe000 0x00001000
9193 05:56:05.270190 RO MCACHE 2. 0xffffc000 0x00001104
9194 05:56:05.273518 CONSOLE 3. 0xfff7c000 0x00080000
9195 05:56:05.276903 FMAP 4. 0xfff7b000 0x00000452
9196 05:56:05.279809 TIME STAMP 5. 0xfff7a000 0x00000910
9197 05:56:05.283514 VBOOT WORK 6. 0xfff66000 0x00014000
9198 05:56:05.286780 RAMOOPS 7. 0xffe66000 0x00100000
9199 05:56:05.290012 COREBOOT 8. 0xffe64000 0x00002000
9200 05:56:05.293702 IMD small region:
9201 05:56:05.296914 IMD ROOT 0. 0xffffec00 0x00000400
9202 05:56:05.299888 VPD 1. 0xffffeb80 0x0000006c
9203 05:56:05.303392 MMC STATUS 2. 0xffffeb60 0x00000004
9204 05:56:05.306786 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9205 05:56:05.309917 Probing TPM: done!
9206 05:56:05.313676 Connected to device vid:did:rid of 1ae0:0028:00
9207 05:56:05.323541 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9208 05:56:05.327532 Initialized TPM device CR50 revision 0
9209 05:56:05.330869 Checking cr50 for pending updates
9210 05:56:05.334256 Reading cr50 TPM mode
9211 05:56:05.342955 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9212 05:56:05.350078 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9213 05:56:05.390029 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9214 05:56:05.393113 Checking segment from ROM address 0x40100000
9215 05:56:05.396640 Checking segment from ROM address 0x4010001c
9216 05:56:05.403592 Loading segment from ROM address 0x40100000
9217 05:56:05.404161 code (compression=0)
9218 05:56:05.413134 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9219 05:56:05.419740 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9220 05:56:05.420344 it's not compressed!
9221 05:56:05.426264 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9222 05:56:05.432696 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9223 05:56:05.450505 Loading segment from ROM address 0x4010001c
9224 05:56:05.451055 Entry Point 0x80000000
9225 05:56:05.453449 Loaded segments
9226 05:56:05.456695 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9227 05:56:05.463791 Jumping to boot code at 0x80000000(0xffe64000)
9228 05:56:05.470261 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9229 05:56:05.477098 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9230 05:56:05.484820 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9231 05:56:05.488049 Checking segment from ROM address 0x40100000
9232 05:56:05.491773 Checking segment from ROM address 0x4010001c
9233 05:56:05.498305 Loading segment from ROM address 0x40100000
9234 05:56:05.498894 code (compression=1)
9235 05:56:05.504994 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9236 05:56:05.514417 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9237 05:56:05.514969 using LZMA
9238 05:56:05.523480 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9239 05:56:05.529582 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9240 05:56:05.532827 Loading segment from ROM address 0x4010001c
9241 05:56:05.533298 Entry Point 0x54601000
9242 05:56:05.536533 Loaded segments
9243 05:56:05.539767 NOTICE: MT8192 bl31_setup
9244 05:56:05.546755 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9245 05:56:05.550049 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9246 05:56:05.553820 WARNING: region 0:
9247 05:56:05.557077 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9248 05:56:05.557604 WARNING: region 1:
9249 05:56:05.563151 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9250 05:56:05.566843 WARNING: region 2:
9251 05:56:05.570222 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9252 05:56:05.573209 WARNING: region 3:
9253 05:56:05.576629 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9254 05:56:05.580650 WARNING: region 4:
9255 05:56:05.586813 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9256 05:56:05.587310 WARNING: region 5:
9257 05:56:05.590262 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9258 05:56:05.593339 WARNING: region 6:
9259 05:56:05.596833 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9260 05:56:05.599810 WARNING: region 7:
9261 05:56:05.603330 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9262 05:56:05.610307 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9263 05:56:05.613716 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9264 05:56:05.616743 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9265 05:56:05.623534 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9266 05:56:05.626886 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9267 05:56:05.630228 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9268 05:56:05.636648 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9269 05:56:05.640194 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9270 05:56:05.646404 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9271 05:56:05.650088 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9272 05:56:05.653285 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9273 05:56:05.660025 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9274 05:56:05.663075 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9275 05:56:05.666584 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9276 05:56:05.673273 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9277 05:56:05.676835 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9278 05:56:05.683259 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9279 05:56:05.686401 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9280 05:56:05.689596 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9281 05:56:05.696558 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9282 05:56:05.699703 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9283 05:56:05.703028 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9284 05:56:05.709606 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9285 05:56:05.712995 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9286 05:56:05.719864 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9287 05:56:05.723095 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9288 05:56:05.726163 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9289 05:56:05.733018 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9290 05:56:05.736249 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9291 05:56:05.742892 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9292 05:56:05.746249 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9293 05:56:05.749544 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9294 05:56:05.756386 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9295 05:56:05.759532 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9296 05:56:05.762819 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9297 05:56:05.766520 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9298 05:56:05.772864 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9299 05:56:05.776193 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9300 05:56:05.779852 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9301 05:56:05.783274 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9302 05:56:05.789831 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9303 05:56:05.792673 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9304 05:56:05.796273 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9305 05:56:05.799651 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9306 05:56:05.806487 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9307 05:56:05.809869 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9308 05:56:05.812922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9309 05:56:05.816393 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9310 05:56:05.822830 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9311 05:56:05.825981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9312 05:56:05.832752 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9313 05:56:05.835997 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9314 05:56:05.842789 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9315 05:56:05.846178 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9316 05:56:05.849443 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9317 05:56:05.856681 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9318 05:56:05.859719 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9319 05:56:05.866468 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9320 05:56:05.869543 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9321 05:56:05.876434 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9322 05:56:05.879593 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9323 05:56:05.885859 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9324 05:56:05.889640 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9325 05:56:05.893285 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9326 05:56:05.899276 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9327 05:56:05.903162 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9328 05:56:05.909518 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9329 05:56:05.913065 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9330 05:56:05.919075 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9331 05:56:05.922580 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9332 05:56:05.925783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9333 05:56:05.932683 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9334 05:56:05.936019 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9335 05:56:05.942282 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9336 05:56:05.946067 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9337 05:56:05.952299 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9338 05:56:05.956456 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9339 05:56:05.959421 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9340 05:56:05.965789 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9341 05:56:05.969238 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9342 05:56:05.975805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9343 05:56:05.979760 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9344 05:56:05.985775 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9345 05:56:05.989538 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9346 05:56:05.993020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9347 05:56:05.999364 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9348 05:56:06.002395 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9349 05:56:06.009526 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9350 05:56:06.012854 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9351 05:56:06.019362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9352 05:56:06.022368 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9353 05:56:06.025962 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9354 05:56:06.032505 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9355 05:56:06.035906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9356 05:56:06.042359 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9357 05:56:06.045495 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9358 05:56:06.052327 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9359 05:56:06.055574 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9360 05:56:06.058947 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9361 05:56:06.062230 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9362 05:56:06.065596 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9363 05:56:06.072480 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9364 05:56:06.075604 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9365 05:56:06.082723 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9366 05:56:06.085956 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9367 05:56:06.092448 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9368 05:56:06.096308 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9369 05:56:06.098964 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9370 05:56:06.105734 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9371 05:56:06.109109 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9372 05:56:06.112404 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9373 05:56:06.119416 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9374 05:56:06.122401 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9375 05:56:06.129205 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9376 05:56:06.132494 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9377 05:56:06.135668 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9378 05:56:06.142154 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9379 05:56:06.145798 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9380 05:56:06.148906 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9381 05:56:06.155964 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9382 05:56:06.158752 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9383 05:56:06.162404 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9384 05:56:06.165593 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9385 05:56:06.172548 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9386 05:56:06.175580 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9387 05:56:06.178998 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9388 05:56:06.185351 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9389 05:56:06.188801 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9390 05:56:06.195626 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9391 05:56:06.198971 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9392 05:56:06.202406 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9393 05:56:06.209011 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9394 05:56:06.212512 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9395 05:56:06.215691 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9396 05:56:06.222368 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9397 05:56:06.225707 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9398 05:56:06.232128 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9399 05:56:06.235179 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9400 05:56:06.238580 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9401 05:56:06.245482 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9402 05:56:06.249061 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9403 05:56:06.255664 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9404 05:56:06.259256 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9405 05:56:06.262707 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9406 05:56:06.269245 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9407 05:56:06.272024 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9408 05:56:06.278810 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9409 05:56:06.282072 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9410 05:56:06.285267 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9411 05:56:06.292132 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9412 05:56:06.295821 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9413 05:56:06.298893 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9414 05:56:06.305410 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9415 05:56:06.308777 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9416 05:56:06.315328 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9417 05:56:06.318684 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9418 05:56:06.322251 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9419 05:56:06.328407 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9420 05:56:06.331986 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9421 05:56:06.338449 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9422 05:56:06.341974 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9423 05:56:06.345350 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9424 05:56:06.351458 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9425 05:56:06.355110 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9426 05:56:06.361875 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9427 05:56:06.365403 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9428 05:56:06.368349 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9429 05:56:06.374817 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9430 05:56:06.378393 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9431 05:56:06.384558 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9432 05:56:06.388051 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9433 05:56:06.391719 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9434 05:56:06.398210 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9435 05:56:06.402008 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9436 05:56:06.407781 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9437 05:56:06.411582 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9438 05:56:06.414945 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9439 05:56:06.421016 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9440 05:56:06.424435 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9441 05:56:06.427646 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9442 05:56:06.434237 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9443 05:56:06.437556 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9444 05:56:06.444354 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9445 05:56:06.447372 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9446 05:56:06.454263 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9447 05:56:06.457595 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9448 05:56:06.460599 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9449 05:56:06.467910 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9450 05:56:06.470724 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9451 05:56:06.477249 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9452 05:56:06.480300 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9453 05:56:06.484313 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9454 05:56:06.491035 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9455 05:56:06.494074 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9456 05:56:06.500625 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9457 05:56:06.503746 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9458 05:56:06.510676 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9459 05:56:06.513687 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9460 05:56:06.517173 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9461 05:56:06.523756 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9462 05:56:06.526881 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9463 05:56:06.533742 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9464 05:56:06.536810 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9465 05:56:06.543294 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9466 05:56:06.546469 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9467 05:56:06.549825 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9468 05:56:06.557022 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9469 05:56:06.559952 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9470 05:56:06.566400 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9471 05:56:06.569554 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9472 05:56:06.573242 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9473 05:56:06.579615 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9474 05:56:06.583267 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9475 05:56:06.589888 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9476 05:56:06.592896 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9477 05:56:06.599409 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9478 05:56:06.603022 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9479 05:56:06.605955 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9480 05:56:06.613035 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9481 05:56:06.616275 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9482 05:56:06.622163 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9483 05:56:06.625422 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9484 05:56:06.632471 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9485 05:56:06.635949 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9486 05:56:06.638799 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9487 05:56:06.645470 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9488 05:56:06.648852 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9489 05:56:06.655978 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9490 05:56:06.658625 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9491 05:56:06.662380 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9492 05:56:06.668591 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9493 05:56:06.671884 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9494 05:56:06.675246 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9495 05:56:06.678821 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9496 05:56:06.685688 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9497 05:56:06.688566 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9498 05:56:06.692421 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9499 05:56:06.698735 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9500 05:56:06.702108 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9501 05:56:06.705311 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9502 05:56:06.711989 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9503 05:56:06.715193 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9504 05:56:06.721988 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9505 05:56:06.724701 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9506 05:56:06.728036 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9507 05:56:06.734772 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9508 05:56:06.738242 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9509 05:56:06.744818 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9510 05:56:06.748119 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9511 05:56:06.751529 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9512 05:56:06.758417 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9513 05:56:06.761431 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9514 05:56:06.764469 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9515 05:56:06.771249 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9516 05:56:06.774996 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9517 05:56:06.777780 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9518 05:56:06.784574 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9519 05:56:06.787990 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9520 05:56:06.791631 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9521 05:56:06.798030 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9522 05:56:06.801181 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9523 05:56:06.808071 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9524 05:56:06.811191 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9525 05:56:06.814276 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9526 05:56:06.821223 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9527 05:56:06.824862 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9528 05:56:06.827387 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9529 05:56:06.834152 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9530 05:56:06.837804 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9531 05:56:06.840839 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9532 05:56:06.847679 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9533 05:56:06.850838 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9534 05:56:06.854179 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9535 05:56:06.857597 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9536 05:56:06.864171 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9537 05:56:06.868007 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9538 05:56:06.870748 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9539 05:56:06.874359 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9540 05:56:06.880454 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9541 05:56:06.884169 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9542 05:56:06.887305 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9543 05:56:06.890614 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9544 05:56:06.897366 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9545 05:56:06.900452 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9546 05:56:06.907333 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9547 05:56:06.910322 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9548 05:56:06.917109 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9549 05:56:06.920185 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9550 05:56:06.923726 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9551 05:56:06.930214 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9552 05:56:06.933942 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9553 05:56:06.940155 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9554 05:56:06.943911 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9555 05:56:06.947022 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9556 05:56:06.953586 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9557 05:56:06.956844 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9558 05:56:06.963839 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9559 05:56:06.967280 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9560 05:56:06.970296 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9561 05:56:06.976462 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9562 05:56:06.979669 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9563 05:56:06.986634 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9564 05:56:06.989811 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9565 05:56:06.996673 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9566 05:56:07.000079 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9567 05:56:07.002889 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9568 05:56:07.009693 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9569 05:56:07.012881 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9570 05:56:07.019652 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9571 05:56:07.022776 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9572 05:56:07.025862 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9573 05:56:07.033183 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9574 05:56:07.036458 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9575 05:56:07.042495 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9576 05:56:07.046206 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9577 05:56:07.049322 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9578 05:56:07.056230 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9579 05:56:07.059675 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9580 05:56:07.066168 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9581 05:56:07.069486 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9582 05:56:07.076205 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9583 05:56:07.078842 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9584 05:56:07.082146 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9585 05:56:07.089123 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9586 05:56:07.092736 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9587 05:56:07.099224 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9588 05:56:07.102511 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9589 05:56:07.105500 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9590 05:56:07.112463 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9591 05:56:07.115933 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9592 05:56:07.122374 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9593 05:56:07.125446 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9594 05:56:07.128998 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9595 05:56:07.135313 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9596 05:56:07.138486 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9597 05:56:07.145331 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9598 05:56:07.148995 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9599 05:56:07.151997 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9600 05:56:07.158982 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9601 05:56:07.161880 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9602 05:56:07.168838 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9603 05:56:07.172306 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9604 05:56:07.178711 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9605 05:56:07.181943 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9606 05:56:07.188234 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9607 05:56:07.191673 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9608 05:56:07.195134 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9609 05:56:07.201617 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9610 05:56:07.205079 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9611 05:56:07.211396 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9612 05:56:07.214749 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9613 05:56:07.217936 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9614 05:56:07.224556 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9615 05:56:07.228319 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9616 05:56:07.234799 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9617 05:56:07.237739 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9618 05:56:07.244623 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9619 05:56:07.247559 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9620 05:56:07.251071 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9621 05:56:07.257379 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9622 05:56:07.260882 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9623 05:56:07.267593 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9624 05:56:07.270977 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9625 05:56:07.277588 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9626 05:56:07.281417 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9627 05:56:07.287163 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9628 05:56:07.291078 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9629 05:56:07.294475 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9630 05:56:07.300684 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9631 05:56:07.304029 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9632 05:56:07.311145 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9633 05:56:07.313797 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9634 05:56:07.320405 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9635 05:56:07.323725 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9636 05:56:07.326714 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9637 05:56:07.333631 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9638 05:56:07.337384 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9639 05:56:07.343678 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9640 05:56:07.347378 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9641 05:56:07.353644 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9642 05:56:07.356848 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9643 05:56:07.363596 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9644 05:56:07.366718 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9645 05:56:07.373086 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9646 05:56:07.376201 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9647 05:56:07.379644 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9648 05:56:07.385946 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9649 05:56:07.389315 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9650 05:56:07.396461 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9651 05:56:07.399720 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9652 05:56:07.406697 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9653 05:56:07.409554 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9654 05:56:07.416695 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9655 05:56:07.419439 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9656 05:56:07.422893 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9657 05:56:07.429726 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9658 05:56:07.433192 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9659 05:56:07.439630 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9660 05:56:07.443007 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9661 05:56:07.449025 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9662 05:56:07.452298 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9663 05:56:07.455621 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9664 05:56:07.462501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9665 05:56:07.465783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9666 05:56:07.472362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9667 05:56:07.475310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9668 05:56:07.481912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9669 05:56:07.485509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9670 05:56:07.491811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9671 05:56:07.495653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9672 05:56:07.502081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9673 05:56:07.505283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9674 05:56:07.512355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9675 05:56:07.515066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9676 05:56:07.518301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9677 05:56:07.525036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9678 05:56:07.528382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9679 05:56:07.535133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9680 05:56:07.538033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9681 05:56:07.544916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9682 05:56:07.548079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9683 05:56:07.554885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9684 05:56:07.557944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9685 05:56:07.564664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9686 05:56:07.567918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9687 05:56:07.574642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9688 05:56:07.578167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9689 05:56:07.584341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9690 05:56:07.587993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9691 05:56:07.594913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9692 05:56:07.601113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9693 05:56:07.604867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9694 05:56:07.611632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9695 05:56:07.614396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9696 05:56:07.617528 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9697 05:56:07.620931 INFO: [APUAPC] vio 0
9698 05:56:07.624323 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9699 05:56:07.631517 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9700 05:56:07.635047 INFO: [APUAPC] D0_APC_0: 0x400510
9701 05:56:07.637584 INFO: [APUAPC] D0_APC_1: 0x0
9702 05:56:07.641232 INFO: [APUAPC] D0_APC_2: 0x1540
9703 05:56:07.641742 INFO: [APUAPC] D0_APC_3: 0x0
9704 05:56:07.647669 INFO: [APUAPC] D1_APC_0: 0xffffffff
9705 05:56:07.650842 INFO: [APUAPC] D1_APC_1: 0xffffffff
9706 05:56:07.653871 INFO: [APUAPC] D1_APC_2: 0x3fffff
9707 05:56:07.654324 INFO: [APUAPC] D1_APC_3: 0x0
9708 05:56:07.657034 INFO: [APUAPC] D2_APC_0: 0xffffffff
9709 05:56:07.663694 INFO: [APUAPC] D2_APC_1: 0xffffffff
9710 05:56:07.667296 INFO: [APUAPC] D2_APC_2: 0x3fffff
9711 05:56:07.667848 INFO: [APUAPC] D2_APC_3: 0x0
9712 05:56:07.670789 INFO: [APUAPC] D3_APC_0: 0xffffffff
9713 05:56:07.673512 INFO: [APUAPC] D3_APC_1: 0xffffffff
9714 05:56:07.677032 INFO: [APUAPC] D3_APC_2: 0x3fffff
9715 05:56:07.680558 INFO: [APUAPC] D3_APC_3: 0x0
9716 05:56:07.683610 INFO: [APUAPC] D4_APC_0: 0xffffffff
9717 05:56:07.686861 INFO: [APUAPC] D4_APC_1: 0xffffffff
9718 05:56:07.690065 INFO: [APUAPC] D4_APC_2: 0x3fffff
9719 05:56:07.693687 INFO: [APUAPC] D4_APC_3: 0x0
9720 05:56:07.696527 INFO: [APUAPC] D5_APC_0: 0xffffffff
9721 05:56:07.700121 INFO: [APUAPC] D5_APC_1: 0xffffffff
9722 05:56:07.703274 INFO: [APUAPC] D5_APC_2: 0x3fffff
9723 05:56:07.707019 INFO: [APUAPC] D5_APC_3: 0x0
9724 05:56:07.710126 INFO: [APUAPC] D6_APC_0: 0xffffffff
9725 05:56:07.713022 INFO: [APUAPC] D6_APC_1: 0xffffffff
9726 05:56:07.717195 INFO: [APUAPC] D6_APC_2: 0x3fffff
9727 05:56:07.720102 INFO: [APUAPC] D6_APC_3: 0x0
9728 05:56:07.723457 INFO: [APUAPC] D7_APC_0: 0xffffffff
9729 05:56:07.726758 INFO: [APUAPC] D7_APC_1: 0xffffffff
9730 05:56:07.729772 INFO: [APUAPC] D7_APC_2: 0x3fffff
9731 05:56:07.732984 INFO: [APUAPC] D7_APC_3: 0x0
9732 05:56:07.736605 INFO: [APUAPC] D8_APC_0: 0xffffffff
9733 05:56:07.739668 INFO: [APUAPC] D8_APC_1: 0xffffffff
9734 05:56:07.743019 INFO: [APUAPC] D8_APC_2: 0x3fffff
9735 05:56:07.746475 INFO: [APUAPC] D8_APC_3: 0x0
9736 05:56:07.749664 INFO: [APUAPC] D9_APC_0: 0xffffffff
9737 05:56:07.752622 INFO: [APUAPC] D9_APC_1: 0xffffffff
9738 05:56:07.755988 INFO: [APUAPC] D9_APC_2: 0x3fffff
9739 05:56:07.759362 INFO: [APUAPC] D9_APC_3: 0x0
9740 05:56:07.762818 INFO: [APUAPC] D10_APC_0: 0xffffffff
9741 05:56:07.765836 INFO: [APUAPC] D10_APC_1: 0xffffffff
9742 05:56:07.769586 INFO: [APUAPC] D10_APC_2: 0x3fffff
9743 05:56:07.772590 INFO: [APUAPC] D10_APC_3: 0x0
9744 05:56:07.776175 INFO: [APUAPC] D11_APC_0: 0xffffffff
9745 05:56:07.779259 INFO: [APUAPC] D11_APC_1: 0xffffffff
9746 05:56:07.782457 INFO: [APUAPC] D11_APC_2: 0x3fffff
9747 05:56:07.785886 INFO: [APUAPC] D11_APC_3: 0x0
9748 05:56:07.789146 INFO: [APUAPC] D12_APC_0: 0xffffffff
9749 05:56:07.792601 INFO: [APUAPC] D12_APC_1: 0xffffffff
9750 05:56:07.795766 INFO: [APUAPC] D12_APC_2: 0x3fffff
9751 05:56:07.798823 INFO: [APUAPC] D12_APC_3: 0x0
9752 05:56:07.801921 INFO: [APUAPC] D13_APC_0: 0xffffffff
9753 05:56:07.805450 INFO: [APUAPC] D13_APC_1: 0xffffffff
9754 05:56:07.808600 INFO: [APUAPC] D13_APC_2: 0x3fffff
9755 05:56:07.812423 INFO: [APUAPC] D13_APC_3: 0x0
9756 05:56:07.815235 INFO: [APUAPC] D14_APC_0: 0xffffffff
9757 05:56:07.818727 INFO: [APUAPC] D14_APC_1: 0xffffffff
9758 05:56:07.821907 INFO: [APUAPC] D14_APC_2: 0x3fffff
9759 05:56:07.825961 INFO: [APUAPC] D14_APC_3: 0x0
9760 05:56:07.828549 INFO: [APUAPC] D15_APC_0: 0xffffffff
9761 05:56:07.832077 INFO: [APUAPC] D15_APC_1: 0xffffffff
9762 05:56:07.835412 INFO: [APUAPC] D15_APC_2: 0x3fffff
9763 05:56:07.838570 INFO: [APUAPC] D15_APC_3: 0x0
9764 05:56:07.841885 INFO: [APUAPC] APC_CON: 0x4
9765 05:56:07.845443 INFO: [NOCDAPC] D0_APC_0: 0x0
9766 05:56:07.848453 INFO: [NOCDAPC] D0_APC_1: 0x0
9767 05:56:07.851924 INFO: [NOCDAPC] D1_APC_0: 0x0
9768 05:56:07.854959 INFO: [NOCDAPC] D1_APC_1: 0xfff
9769 05:56:07.858678 INFO: [NOCDAPC] D2_APC_0: 0x0
9770 05:56:07.861556 INFO: [NOCDAPC] D2_APC_1: 0xfff
9771 05:56:07.862021 INFO: [NOCDAPC] D3_APC_0: 0x0
9772 05:56:07.864837 INFO: [NOCDAPC] D3_APC_1: 0xfff
9773 05:56:07.868673 INFO: [NOCDAPC] D4_APC_0: 0x0
9774 05:56:07.871748 INFO: [NOCDAPC] D4_APC_1: 0xfff
9775 05:56:07.875125 INFO: [NOCDAPC] D5_APC_0: 0x0
9776 05:56:07.877844 INFO: [NOCDAPC] D5_APC_1: 0xfff
9777 05:56:07.881576 INFO: [NOCDAPC] D6_APC_0: 0x0
9778 05:56:07.884908 INFO: [NOCDAPC] D6_APC_1: 0xfff
9779 05:56:07.887947 INFO: [NOCDAPC] D7_APC_0: 0x0
9780 05:56:07.891295 INFO: [NOCDAPC] D7_APC_1: 0xfff
9781 05:56:07.894866 INFO: [NOCDAPC] D8_APC_0: 0x0
9782 05:56:07.895385 INFO: [NOCDAPC] D8_APC_1: 0xfff
9783 05:56:07.897779 INFO: [NOCDAPC] D9_APC_0: 0x0
9784 05:56:07.901340 INFO: [NOCDAPC] D9_APC_1: 0xfff
9785 05:56:07.904543 INFO: [NOCDAPC] D10_APC_0: 0x0
9786 05:56:07.907719 INFO: [NOCDAPC] D10_APC_1: 0xfff
9787 05:56:07.910971 INFO: [NOCDAPC] D11_APC_0: 0x0
9788 05:56:07.914490 INFO: [NOCDAPC] D11_APC_1: 0xfff
9789 05:56:07.917407 INFO: [NOCDAPC] D12_APC_0: 0x0
9790 05:56:07.920948 INFO: [NOCDAPC] D12_APC_1: 0xfff
9791 05:56:07.924165 INFO: [NOCDAPC] D13_APC_0: 0x0
9792 05:56:07.927513 INFO: [NOCDAPC] D13_APC_1: 0xfff
9793 05:56:07.930656 INFO: [NOCDAPC] D14_APC_0: 0x0
9794 05:56:07.934370 INFO: [NOCDAPC] D14_APC_1: 0xfff
9795 05:56:07.937597 INFO: [NOCDAPC] D15_APC_0: 0x0
9796 05:56:07.941214 INFO: [NOCDAPC] D15_APC_1: 0xfff
9797 05:56:07.941440 INFO: [NOCDAPC] APC_CON: 0x4
9798 05:56:07.943841 INFO: [APUAPC] set_apusys_apc done
9799 05:56:07.947120 INFO: [DEVAPC] devapc_init done
9800 05:56:07.953748 INFO: GICv3 without legacy support detected.
9801 05:56:07.956900 INFO: ARM GICv3 driver initialized in EL3
9802 05:56:07.960243 INFO: Maximum SPI INTID supported: 639
9803 05:56:07.963797 INFO: BL31: Initializing runtime services
9804 05:56:07.970295 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9805 05:56:07.973657 INFO: SPM: enable CPC mode
9806 05:56:07.977191 INFO: mcdi ready for mcusys-off-idle and system suspend
9807 05:56:07.984059 INFO: BL31: Preparing for EL3 exit to normal world
9808 05:56:07.986782 INFO: Entry point address = 0x80000000
9809 05:56:07.987013 INFO: SPSR = 0x8
9810 05:56:07.994396
9811 05:56:07.994736
9812 05:56:07.994931
9813 05:56:07.997657 Starting depthcharge on Spherion...
9814 05:56:07.997879
9815 05:56:07.998054 Wipe memory regions:
9816 05:56:07.998217
9817 05:56:07.999593 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9818 05:56:07.999854 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9819 05:56:08.000076 Setting prompt string to ['asurada:']
9820 05:56:08.000292 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9821 05:56:08.000729 [0x00000040000000, 0x00000054600000)
9822 05:56:08.123571
9823 05:56:08.124434 [0x00000054660000, 0x00000080000000)
9824 05:56:08.384215
9825 05:56:08.384817 [0x000000821a7280, 0x000000ffe64000)
9826 05:56:09.129156
9827 05:56:09.129828 [0x00000100000000, 0x00000140000000)
9828 05:56:09.510167
9829 05:56:09.513559 Initializing XHCI USB controller at 0x11200000.
9830 05:56:10.551472
9831 05:56:10.554319 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9832 05:56:10.554882
9833 05:56:10.555245
9834 05:56:10.555585
9835 05:56:10.556430 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9837 05:56:10.657818 asurada: tftpboot 192.168.201.1 12379428/tftp-deploy-k5yrtuvm/kernel/image.itb 12379428/tftp-deploy-k5yrtuvm/kernel/cmdline
9838 05:56:10.658481 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9839 05:56:10.659001 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9840 05:56:10.663918 tftpboot 192.168.201.1 12379428/tftp-deploy-k5yrtuvm/kernel/image.itp-deploy-k5yrtuvm/kernel/cmdline
9841 05:56:10.664491
9842 05:56:10.664900 Waiting for link
9843 05:56:10.824334
9844 05:56:10.824493 R8152: Initializing
9845 05:56:10.824568
9846 05:56:10.827101 Version 9 (ocp_data = 6010)
9847 05:56:10.827259
9848 05:56:10.830514 R8152: Done initializing
9849 05:56:10.830680
9850 05:56:10.830758 Adding net device
9851 05:56:12.964504
9852 05:56:12.965112 done.
9853 05:56:12.965535
9854 05:56:12.965909 MAC: 00:e0:4c:68:03:bd
9855 05:56:12.966332
9856 05:56:12.967557 Sending DHCP discover... done.
9857 05:56:12.968026
9858 05:56:12.970414 Waiting for reply... done.
9859 05:56:12.970495
9860 05:56:12.973610 Sending DHCP request... done.
9861 05:56:12.973690
9862 05:56:12.985011 Waiting for reply... done.
9863 05:56:12.985184
9864 05:56:12.985264 My ip is 192.168.201.16
9865 05:56:12.985334
9866 05:56:12.988259 The DHCP server ip is 192.168.201.1
9867 05:56:12.988410
9868 05:56:12.995000 TFTP server IP predefined by user: 192.168.201.1
9869 05:56:12.995191
9870 05:56:13.001467 Bootfile predefined by user: 12379428/tftp-deploy-k5yrtuvm/kernel/image.itb
9871 05:56:13.001668
9872 05:56:13.004982 Sending tftp read request... done.
9873 05:56:13.005450
9874 05:56:13.011152 Waiting for the transfer...
9875 05:56:13.011602
9876 05:56:13.302001 00000000 ################################################################
9877 05:56:13.302148
9878 05:56:13.580602 00080000 ################################################################
9879 05:56:13.580818
9880 05:56:13.863703 00100000 ################################################################
9881 05:56:13.863847
9882 05:56:14.150164 00180000 ################################################################
9883 05:56:14.150300
9884 05:56:14.433919 00200000 ################################################################
9885 05:56:14.434071
9886 05:56:14.701254 00280000 ################################################################
9887 05:56:14.701400
9888 05:56:14.991318 00300000 ################################################################
9889 05:56:14.991455
9890 05:56:15.273246 00380000 ################################################################
9891 05:56:15.273384
9892 05:56:15.564832 00400000 ################################################################
9893 05:56:15.564973
9894 05:56:15.850928 00480000 ################################################################
9895 05:56:15.851071
9896 05:56:16.143662 00500000 ################################################################
9897 05:56:16.143804
9898 05:56:16.429912 00580000 ################################################################
9899 05:56:16.430049
9900 05:56:16.712497 00600000 ################################################################
9901 05:56:16.712671
9902 05:56:16.992088 00680000 ################################################################
9903 05:56:16.992222
9904 05:56:17.284266 00700000 ################################################################
9905 05:56:17.284431
9906 05:56:17.581597 00780000 ################################################################
9907 05:56:17.581738
9908 05:56:17.869338 00800000 ################################################################
9909 05:56:17.869480
9910 05:56:18.158580 00880000 ################################################################
9911 05:56:18.158726
9912 05:56:18.420937 00900000 ################################################################
9913 05:56:18.421075
9914 05:56:18.703313 00980000 ################################################################
9915 05:56:18.703474
9916 05:56:18.989900 00a00000 ################################################################
9917 05:56:18.990062
9918 05:56:19.266053 00a80000 ################################################################
9919 05:56:19.266191
9920 05:56:19.532283 00b00000 ################################################################
9921 05:56:19.532422
9922 05:56:19.809087 00b80000 ################################################################
9923 05:56:19.809230
9924 05:56:20.082018 00c00000 ################################################################
9925 05:56:20.082180
9926 05:56:20.375496 00c80000 ################################################################
9927 05:56:20.375657
9928 05:56:20.655183 00d00000 ################################################################
9929 05:56:20.655342
9930 05:56:20.910795 00d80000 ################################################################
9931 05:56:20.910927
9932 05:56:21.193519 00e00000 ################################################################
9933 05:56:21.193668
9934 05:56:21.465132 00e80000 ################################################################
9935 05:56:21.465269
9936 05:56:21.745539 00f00000 ################################################################
9937 05:56:21.745677
9938 05:56:22.036058 00f80000 ################################################################
9939 05:56:22.036194
9940 05:56:22.307621 01000000 ################################################################
9941 05:56:22.307768
9942 05:56:22.604047 01080000 ################################################################
9943 05:56:22.604189
9944 05:56:22.866660 01100000 ################################################################
9945 05:56:22.866799
9946 05:56:23.145840 01180000 ################################################################
9947 05:56:23.145978
9948 05:56:23.412740 01200000 ################################################################
9949 05:56:23.412915
9950 05:56:23.694023 01280000 ################################################################
9951 05:56:23.694188
9952 05:56:23.985517 01300000 ################################################################
9953 05:56:23.985656
9954 05:56:24.274383 01380000 ################################################################
9955 05:56:24.274526
9956 05:56:24.565140 01400000 ################################################################
9957 05:56:24.565307
9958 05:56:24.860366 01480000 ################################################################
9959 05:56:24.860507
9960 05:56:25.153455 01500000 ################################################################
9961 05:56:25.153593
9962 05:56:25.430392 01580000 ################################################################
9963 05:56:25.430537
9964 05:56:25.714280 01600000 ################################################################
9965 05:56:25.714422
9966 05:56:26.010151 01680000 ################################################################
9967 05:56:26.010311
9968 05:56:26.301041 01700000 ################################################################
9969 05:56:26.301179
9970 05:56:26.587847 01780000 ################################################################
9971 05:56:26.587989
9972 05:56:26.867056 01800000 ################################################################
9973 05:56:26.867192
9974 05:56:27.157741 01880000 ################################################################
9975 05:56:27.157876
9976 05:56:27.437357 01900000 ################################################################
9977 05:56:27.437491
9978 05:56:27.720778 01980000 ################################################################
9979 05:56:27.720942
9980 05:56:27.995785 01a00000 ################################################################
9981 05:56:27.995920
9982 05:56:28.289555 01a80000 ################################################################
9983 05:56:28.289717
9984 05:56:28.581680 01b00000 ################################################################
9985 05:56:28.581820
9986 05:56:28.846456 01b80000 ############################################################# done.
9987 05:56:28.846603
9988 05:56:28.850115 The bootfile was 29328122 bytes long.
9989 05:56:28.850239
9990 05:56:28.853254 Sending tftp read request... done.
9991 05:56:28.853366
9992 05:56:28.856413 Waiting for the transfer...
9993 05:56:28.856505
9994 05:56:28.856578 00000000 # done.
9995 05:56:28.856648
9996 05:56:28.863599 Command line loaded dynamically from TFTP file: 12379428/tftp-deploy-k5yrtuvm/kernel/cmdline
9997 05:56:28.863799
9998 05:56:28.886387 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12379428/extract-nfsrootfs-vcgwrj83,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9999 05:56:28.886655
10000 05:56:28.886802 Loading FIT.
10001 05:56:28.889311
10002 05:56:28.889511 Image ramdisk-1 has 17796979 bytes.
10003 05:56:28.889669
10004 05:56:28.892870 Image fdt-1 has 47278 bytes.
10005 05:56:28.893115
10006 05:56:28.896771 Image kernel-1 has 11481830 bytes.
10007 05:56:28.897173
10008 05:56:28.906572 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10009 05:56:28.907054
10010 05:56:28.922671 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10011 05:56:28.923172
10012 05:56:28.929587 Choosing best match conf-1 for compat google,spherion-rev3.
10013 05:56:28.933112
10014 05:56:28.937711 Connected to device vid:did:rid of 1ae0:0028:00
10015 05:56:28.945604
10016 05:56:28.948990 tpm_get_response: command 0x17b, return code 0x0
10017 05:56:28.949726
10018 05:56:28.952302 ec_init: CrosEC protocol v3 supported (256, 248)
10019 05:56:28.956280
10020 05:56:28.959790 tpm_cleanup: add release locality here.
10021 05:56:28.960365
10022 05:56:28.960792 Shutting down all USB controllers.
10023 05:56:28.962952
10024 05:56:28.963409 Removing current net device
10025 05:56:28.963774
10026 05:56:28.969701 Exiting depthcharge with code 4 at timestamp: 49218026
10027 05:56:28.970260
10028 05:56:28.973022 LZMA decompressing kernel-1 to 0x821a6718
10029 05:56:28.973485
10030 05:56:28.975712 LZMA decompressing kernel-1 to 0x40000000
10031 05:56:30.411922
10032 05:56:30.412479 jumping to kernel
10033 05:56:30.414294 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10034 05:56:30.414854 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10035 05:56:30.415261 Setting prompt string to ['Linux version [0-9]']
10036 05:56:30.415640 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10037 05:56:30.416016 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10038 05:56:30.463374
10039 05:56:30.466846 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10040 05:56:30.470521 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10041 05:56:30.470846 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10042 05:56:30.471128 Setting prompt string to []
10043 05:56:30.471461 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10044 05:56:30.471753 Using line separator: #'\n'#
10045 05:56:30.472001 No login prompt set.
10046 05:56:30.472286 Parsing kernel messages
10047 05:56:30.472599 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10048 05:56:30.473039 [login-action] Waiting for messages, (timeout 00:04:04)
10049 05:56:30.489610 [ 0.000000] Linux version 6.1.67-cip12 (KernelCI@build-j59664-arm64-gcc-10-defconfig-arm64-chromebook-fgc24) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023
10050 05:56:30.492757 [ 0.000000] random: crng init done
10051 05:56:30.499817 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10052 05:56:30.502844 [ 0.000000] efi: UEFI not found.
10053 05:56:30.509699 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10054 05:56:30.516180 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10055 05:56:30.525879 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10056 05:56:30.535686 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10057 05:56:30.542513 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10058 05:56:30.549033 [ 0.000000] printk: bootconsole [mtk8250] enabled
10059 05:56:30.555808 [ 0.000000] NUMA: No NUMA configuration found
10060 05:56:30.562035 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10061 05:56:30.565597 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d3a00-0x13f7d5fff]
10062 05:56:30.568896 [ 0.000000] Zone ranges:
10063 05:56:30.575515 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10064 05:56:30.578738 [ 0.000000] DMA32 empty
10065 05:56:30.585389 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10066 05:56:30.588633 [ 0.000000] Movable zone start for each node
10067 05:56:30.591687 [ 0.000000] Early memory node ranges
10068 05:56:30.598657 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10069 05:56:30.605306 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10070 05:56:30.611896 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10071 05:56:30.618718 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10072 05:56:30.625107 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10073 05:56:30.631579 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10074 05:56:30.662449 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10075 05:56:30.668640 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10076 05:56:30.674970 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10077 05:56:30.678473 [ 0.000000] psci: probing for conduit method from DT.
10078 05:56:30.685094 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10079 05:56:30.688230 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10080 05:56:30.694571 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10081 05:56:30.698034 [ 0.000000] psci: SMC Calling Convention v1.2
10082 05:56:30.704476 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10083 05:56:30.708325 [ 0.000000] Detected VIPT I-cache on CPU0
10084 05:56:30.714516 [ 0.000000] CPU features: detected: GIC system register CPU interface
10085 05:56:30.721220 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10086 05:56:30.728062 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10087 05:56:30.734354 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10088 05:56:30.744335 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10089 05:56:30.751163 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10090 05:56:30.754518 [ 0.000000] alternatives: applying boot alternatives
10091 05:56:30.760871 [ 0.000000] Fallback order for Node 0: 0
10092 05:56:30.767629 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10093 05:56:30.770495 [ 0.000000] Policy zone: Normal
10094 05:56:30.793923 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12379428/extract-nfsrootfs-vcgwrj83,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10095 05:56:30.803794 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10096 05:56:30.813897 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10097 05:56:30.820227 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10098 05:56:30.826731 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10099 05:56:30.833747 <6>[ 0.000000] software IO TLB: area num 8.
10100 05:56:30.888652 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10101 05:56:30.968397 <6>[ 0.000000] Memory: 3836928K/4191232K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 321536K reserved, 32768K cma-reserved)
10102 05:56:30.974886 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10103 05:56:30.981628 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10104 05:56:30.985150 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10105 05:56:30.991686 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10106 05:56:30.998494 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10107 05:56:31.002062 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10108 05:56:31.011877 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10109 05:56:31.017841 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10110 05:56:31.024957 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10111 05:56:31.030908 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10112 05:56:31.035126 <6>[ 0.000000] GICv3: 608 SPIs implemented
10113 05:56:31.037839 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10114 05:56:31.044522 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10115 05:56:31.047626 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10116 05:56:31.054140 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10117 05:56:31.067506 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10118 05:56:31.080777 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10119 05:56:31.086901 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10120 05:56:31.095174 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10121 05:56:31.108273 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10122 05:56:31.115189 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10123 05:56:31.121406 <6>[ 0.009228] Console: colour dummy device 80x25
10124 05:56:31.131208 <6>[ 0.013982] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10125 05:56:31.138058 <6>[ 0.024488] pid_max: default: 32768 minimum: 301
10126 05:56:31.141386 <6>[ 0.029359] LSM: Security Framework initializing
10127 05:56:31.148509 <6>[ 0.034301] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10128 05:56:31.158009 <6>[ 0.041907] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10129 05:56:31.164235 <6>[ 0.051134] cblist_init_generic: Setting adjustable number of callback queues.
10130 05:56:31.170651 <6>[ 0.058577] cblist_init_generic: Setting shift to 3 and lim to 1.
10131 05:56:31.180881 <6>[ 0.064915] cblist_init_generic: Setting adjustable number of callback queues.
10132 05:56:31.187505 <6>[ 0.072343] cblist_init_generic: Setting shift to 3 and lim to 1.
10133 05:56:31.191003 <6>[ 0.078783] rcu: Hierarchical SRCU implementation.
10134 05:56:31.197292 <6>[ 0.083830] rcu: Max phase no-delay instances is 1000.
10135 05:56:31.203990 <6>[ 0.090850] EFI services will not be available.
10136 05:56:31.207232 <6>[ 0.095806] smp: Bringing up secondary CPUs ...
10137 05:56:31.215293 <6>[ 0.100853] Detected VIPT I-cache on CPU1
10138 05:56:31.221963 <6>[ 0.100921] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10139 05:56:31.228590 <6>[ 0.100951] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10140 05:56:31.232001 <6>[ 0.101279] Detected VIPT I-cache on CPU2
10141 05:56:31.241753 <6>[ 0.101326] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10142 05:56:31.248627 <6>[ 0.101341] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10143 05:56:31.251535 <6>[ 0.101593] Detected VIPT I-cache on CPU3
10144 05:56:31.258413 <6>[ 0.101640] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10145 05:56:31.264699 <6>[ 0.101654] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10146 05:56:31.271515 <6>[ 0.101954] CPU features: detected: Spectre-v4
10147 05:56:31.274780 <6>[ 0.101961] CPU features: detected: Spectre-BHB
10148 05:56:31.277784 <6>[ 0.101966] Detected PIPT I-cache on CPU4
10149 05:56:31.284564 <6>[ 0.102022] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10150 05:56:31.294352 <6>[ 0.102039] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10151 05:56:31.297971 <6>[ 0.102329] Detected PIPT I-cache on CPU5
10152 05:56:31.304448 <6>[ 0.102391] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10153 05:56:31.310908 <6>[ 0.102408] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10154 05:56:31.313922 <6>[ 0.102686] Detected PIPT I-cache on CPU6
10155 05:56:31.323881 <6>[ 0.102749] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10156 05:56:31.330916 <6>[ 0.102765] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10157 05:56:31.333990 <6>[ 0.103065] Detected PIPT I-cache on CPU7
10158 05:56:31.340822 <6>[ 0.103130] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10159 05:56:31.347164 <6>[ 0.103146] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10160 05:56:31.350467 <6>[ 0.103195] smp: Brought up 1 node, 8 CPUs
10161 05:56:31.357502 <6>[ 0.244569] SMP: Total of 8 processors activated.
10162 05:56:31.364145 <6>[ 0.249490] CPU features: detected: 32-bit EL0 Support
10163 05:56:31.370612 <6>[ 0.254853] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10164 05:56:31.377041 <6>[ 0.263654] CPU features: detected: Common not Private translations
10165 05:56:31.383360 <6>[ 0.270170] CPU features: detected: CRC32 instructions
10166 05:56:31.390356 <6>[ 0.275521] CPU features: detected: RCpc load-acquire (LDAPR)
10167 05:56:31.393348 <6>[ 0.281481] CPU features: detected: LSE atomic instructions
10168 05:56:31.399986 <6>[ 0.287299] CPU features: detected: Privileged Access Never
10169 05:56:31.406349 <6>[ 0.293079] CPU features: detected: RAS Extension Support
10170 05:56:31.413084 <6>[ 0.298688] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10171 05:56:31.416217 <6>[ 0.305908] CPU: All CPU(s) started at EL2
10172 05:56:31.422790 <6>[ 0.310224] alternatives: applying system-wide alternatives
10173 05:56:31.432478 <6>[ 0.320135] devtmpfs: initialized
10174 05:56:31.447079 <6>[ 0.328432] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10175 05:56:31.453926 <6>[ 0.338392] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10176 05:56:31.460776 <6>[ 0.346619] pinctrl core: initialized pinctrl subsystem
10177 05:56:31.463532 <6>[ 0.353298] DMI not present or invalid.
10178 05:56:31.470770 <6>[ 0.357706] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10179 05:56:31.480604 <6>[ 0.364567] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10180 05:56:31.487039 <6>[ 0.372009] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10181 05:56:31.497233 <6>[ 0.380100] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10182 05:56:31.500260 <6>[ 0.388254] audit: initializing netlink subsys (disabled)
10183 05:56:31.510831 <5>[ 0.393951] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10184 05:56:31.516660 <6>[ 0.394654] thermal_sys: Registered thermal governor 'step_wise'
10185 05:56:31.523298 <6>[ 0.401919] thermal_sys: Registered thermal governor 'power_allocator'
10186 05:56:31.526738 <6>[ 0.408172] cpuidle: using governor menu
10187 05:56:31.532777 <6>[ 0.419132] NET: Registered PF_QIPCRTR protocol family
10188 05:56:31.539715 <6>[ 0.424631] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10189 05:56:31.542739 <6>[ 0.431736] ASID allocator initialised with 32768 entries
10190 05:56:31.550454 <6>[ 0.438289] Serial: AMBA PL011 UART driver
10191 05:56:31.559608 <4>[ 0.446984] Trying to register duplicate clock ID: 134
10192 05:56:31.614233 <6>[ 0.504786] KASLR enabled
10193 05:56:31.628251 <6>[ 0.512564] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10194 05:56:31.634642 <6>[ 0.519579] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10195 05:56:31.641278 <6>[ 0.526065] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10196 05:56:31.647741 <6>[ 0.533071] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10197 05:56:31.654223 <6>[ 0.539558] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10198 05:56:31.661149 <6>[ 0.546563] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10199 05:56:31.667577 <6>[ 0.553047] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10200 05:56:31.674265 <6>[ 0.560052] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10201 05:56:31.677296 <6>[ 0.567553] ACPI: Interpreter disabled.
10202 05:56:31.685925 <6>[ 0.573956] iommu: Default domain type: Translated
10203 05:56:31.692379 <6>[ 0.579070] iommu: DMA domain TLB invalidation policy: strict mode
10204 05:56:31.696025 <5>[ 0.585735] SCSI subsystem initialized
10205 05:56:31.702692 <6>[ 0.589897] usbcore: registered new interface driver usbfs
10206 05:56:31.709102 <6>[ 0.595628] usbcore: registered new interface driver hub
10207 05:56:31.712881 <6>[ 0.601181] usbcore: registered new device driver usb
10208 05:56:31.719598 <6>[ 0.607282] pps_core: LinuxPPS API ver. 1 registered
10209 05:56:31.729563 <6>[ 0.612473] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10210 05:56:31.732942 <6>[ 0.621822] PTP clock support registered
10211 05:56:31.736441 <6>[ 0.626064] EDAC MC: Ver: 3.0.0
10212 05:56:31.743251 <6>[ 0.631210] FPGA manager framework
10213 05:56:31.749819 <6>[ 0.634890] Advanced Linux Sound Architecture Driver Initialized.
10214 05:56:31.753157 <6>[ 0.641661] vgaarb: loaded
10215 05:56:31.759816 <6>[ 0.644820] clocksource: Switched to clocksource arch_sys_counter
10216 05:56:31.764110 <5>[ 0.651263] VFS: Disk quotas dquot_6.6.0
10217 05:56:31.769532 <6>[ 0.655446] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10218 05:56:31.773042 <6>[ 0.662634] pnp: PnP ACPI: disabled
10219 05:56:31.782007 <6>[ 0.669332] NET: Registered PF_INET protocol family
10220 05:56:31.787870 <6>[ 0.674706] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10221 05:56:31.800286 <6>[ 0.684736] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10222 05:56:31.810024 <6>[ 0.693525] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10223 05:56:31.816683 <6>[ 0.701490] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10224 05:56:31.823495 <6>[ 0.709896] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10225 05:56:31.834008 <6>[ 0.718550] TCP: Hash tables configured (established 32768 bind 32768)
10226 05:56:31.840700 <6>[ 0.725414] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10227 05:56:31.847164 <6>[ 0.732430] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10228 05:56:31.854387 <6>[ 0.739951] NET: Registered PF_UNIX/PF_LOCAL protocol family
10229 05:56:31.860456 <6>[ 0.746073] RPC: Registered named UNIX socket transport module.
10230 05:56:31.863633 <6>[ 0.752228] RPC: Registered udp transport module.
10231 05:56:31.870347 <6>[ 0.757162] RPC: Registered tcp transport module.
10232 05:56:31.877545 <6>[ 0.762094] RPC: Registered tcp NFSv4.1 backchannel transport module.
10233 05:56:31.880780 <6>[ 0.768756] PCI: CLS 0 bytes, default 64
10234 05:56:31.883953 <6>[ 0.773164] Unpacking initramfs...
10235 05:56:31.893450 <6>[ 0.776856] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10236 05:56:31.900192 <6>[ 0.785485] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10237 05:56:31.906873 <6>[ 0.794322] kvm [1]: IPA Size Limit: 40 bits
10238 05:56:31.909678 <6>[ 0.798853] kvm [1]: GICv3: no GICV resource entry
10239 05:56:31.916360 <6>[ 0.803874] kvm [1]: disabling GICv2 emulation
10240 05:56:31.923278 <6>[ 0.808559] kvm [1]: GIC system register CPU interface enabled
10241 05:56:31.926494 <6>[ 0.814721] kvm [1]: vgic interrupt IRQ18
10242 05:56:31.933150 <6>[ 0.819081] kvm [1]: VHE mode initialized successfully
10243 05:56:31.936431 <5>[ 0.825608] Initialise system trusted keyrings
10244 05:56:31.943081 <6>[ 0.830432] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10245 05:56:31.952804 <6>[ 0.840449] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10246 05:56:31.959591 <5>[ 0.846822] NFS: Registering the id_resolver key type
10247 05:56:31.962761 <5>[ 0.852127] Key type id_resolver registered
10248 05:56:31.969184 <5>[ 0.856540] Key type id_legacy registered
10249 05:56:31.975898 <6>[ 0.860826] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10250 05:56:31.982733 <6>[ 0.867749] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10251 05:56:31.988796 <6>[ 0.875475] 9p: Installing v9fs 9p2000 file system support
10252 05:56:32.025477 <5>[ 0.912769] Key type asymmetric registered
10253 05:56:32.028130 <5>[ 0.917100] Asymmetric key parser 'x509' registered
10254 05:56:32.037981 <6>[ 0.922243] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10255 05:56:32.041285 <6>[ 0.929859] io scheduler mq-deadline registered
10256 05:56:32.044613 <6>[ 0.934620] io scheduler kyber registered
10257 05:56:32.064017 <6>[ 0.951812] EINJ: ACPI disabled.
10258 05:56:32.096353 <4>[ 0.977409] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10259 05:56:32.105968 <4>[ 0.988052] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10260 05:56:32.121437 <6>[ 1.009011] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10261 05:56:32.129305 <6>[ 1.017054] printk: console [ttyS0] disabled
10262 05:56:32.157295 <6>[ 1.041700] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10263 05:56:32.164213 <6>[ 1.051172] printk: console [ttyS0] enabled
10264 05:56:32.167583 <6>[ 1.051172] printk: console [ttyS0] enabled
10265 05:56:32.173810 <6>[ 1.060067] printk: bootconsole [mtk8250] disabled
10266 05:56:32.177425 <6>[ 1.060067] printk: bootconsole [mtk8250] disabled
10267 05:56:32.184232 <6>[ 1.071352] SuperH (H)SCI(F) driver initialized
10268 05:56:32.187332 <6>[ 1.076643] msm_serial: driver initialized
10269 05:56:32.201098 <6>[ 1.085720] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10270 05:56:32.211210 <6>[ 1.094268] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10271 05:56:32.218256 <6>[ 1.102813] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10272 05:56:32.227756 <6>[ 1.111442] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10273 05:56:32.237332 <6>[ 1.120154] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10274 05:56:32.244673 <6>[ 1.128868] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10275 05:56:32.254726 <6>[ 1.137414] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10276 05:56:32.260837 <6>[ 1.146233] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10277 05:56:32.270749 <6>[ 1.154777] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10278 05:56:32.282583 <6>[ 1.170485] loop: module loaded
10279 05:56:32.289601 <6>[ 1.176475] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10280 05:56:32.311978 <4>[ 1.199916] mtk-pmic-keys: Failed to locate of_node [id: -1]
10281 05:56:32.319102 <6>[ 1.207042] megasas: 07.719.03.00-rc1
10282 05:56:32.328847 <6>[ 1.216850] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10283 05:56:32.340792 <6>[ 1.228204] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10284 05:56:32.357266 <6>[ 1.244746] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10285 05:56:32.412536 <6>[ 1.293979] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10286 05:56:32.624199 <6>[ 1.512044] Freeing initrd memory: 17376K
10287 05:56:32.634727 <6>[ 1.522486] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10288 05:56:32.645152 <6>[ 1.533361] tun: Universal TUN/TAP device driver, 1.6
10289 05:56:32.648664 <6>[ 1.539419] thunder_xcv, ver 1.0
10290 05:56:32.652207 <6>[ 1.542927] thunder_bgx, ver 1.0
10291 05:56:32.655718 <6>[ 1.546420] nicpf, ver 1.0
10292 05:56:32.665956 <6>[ 1.550447] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10293 05:56:32.669468 <6>[ 1.557923] hns3: Copyright (c) 2017 Huawei Corporation.
10294 05:56:32.675884 <6>[ 1.563511] hclge is initializing
10295 05:56:32.679236 <6>[ 1.567093] e1000: Intel(R) PRO/1000 Network Driver
10296 05:56:32.685804 <6>[ 1.572223] e1000: Copyright (c) 1999-2006 Intel Corporation.
10297 05:56:32.688881 <6>[ 1.578235] e1000e: Intel(R) PRO/1000 Network Driver
10298 05:56:32.695726 <6>[ 1.583450] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10299 05:56:32.702521 <6>[ 1.589635] igb: Intel(R) Gigabit Ethernet Network Driver
10300 05:56:32.709226 <6>[ 1.595285] igb: Copyright (c) 2007-2014 Intel Corporation.
10301 05:56:32.715875 <6>[ 1.601124] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10302 05:56:32.722290 <6>[ 1.607642] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10303 05:56:32.725229 <6>[ 1.614103] sky2: driver version 1.30
10304 05:56:32.732080 <6>[ 1.619100] VFIO - User Level meta-driver version: 0.3
10305 05:56:32.739618 <6>[ 1.627339] usbcore: registered new interface driver usb-storage
10306 05:56:32.746033 <6>[ 1.633788] usbcore: registered new device driver onboard-usb-hub
10307 05:56:32.755586 <6>[ 1.642940] mt6397-rtc mt6359-rtc: registered as rtc0
10308 05:56:32.765073 <6>[ 1.648404] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-25T05:56:32 UTC (1703483792)
10309 05:56:32.768295 <6>[ 1.657971] i2c_dev: i2c /dev entries driver
10310 05:56:32.785037 <6>[ 1.669753] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10311 05:56:32.805962 <6>[ 1.693738] cpu cpu0: EM: created perf domain
10312 05:56:32.808865 <6>[ 1.698633] cpu cpu4: EM: created perf domain
10313 05:56:32.816206 <6>[ 1.704170] sdhci: Secure Digital Host Controller Interface driver
10314 05:56:32.822918 <6>[ 1.710602] sdhci: Copyright(c) Pierre Ossman
10315 05:56:32.829900 <6>[ 1.715518] Synopsys Designware Multimedia Card Interface Driver
10316 05:56:32.836149 <6>[ 1.722107] sdhci-pltfm: SDHCI platform and OF driver helper
10317 05:56:32.839529 <6>[ 1.722262] mmc0: CQHCI version 5.10
10318 05:56:32.846241 <6>[ 1.732202] ledtrig-cpu: registered to indicate activity on CPUs
10319 05:56:32.852603 <6>[ 1.739196] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10320 05:56:32.859343 <6>[ 1.746242] usbcore: registered new interface driver usbhid
10321 05:56:32.863177 <6>[ 1.752063] usbhid: USB HID core driver
10322 05:56:32.869065 <6>[ 1.756258] spi_master spi0: will run message pump with realtime priority
10323 05:56:32.911044 <6>[ 1.791801] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10324 05:56:32.925671 <6>[ 1.806930] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10325 05:56:32.932917 <6>[ 1.820543] mmc0: Command Queue Engine enabled
10326 05:56:32.939944 <6>[ 1.825313] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10327 05:56:32.946144 <6>[ 1.832159] cros-ec-spi spi0.0: Chrome EC device registered
10328 05:56:32.949355 <6>[ 1.832549] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10329 05:56:32.958861 <6>[ 1.846965] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10330 05:56:32.966414 <6>[ 1.854234] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10331 05:56:32.973299 <6>[ 1.860081] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10332 05:56:32.979744 <6>[ 1.865944] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10333 05:56:32.994070 <6>[ 1.879030] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10334 05:56:33.001997 <6>[ 1.890029] NET: Registered PF_PACKET protocol family
10335 05:56:33.005412 <6>[ 1.895409] 9pnet: Installing 9P2000 support
10336 05:56:33.012529 <5>[ 1.899967] Key type dns_resolver registered
10337 05:56:33.015448 <6>[ 1.904999] registered taskstats version 1
10338 05:56:33.022028 <5>[ 1.909370] Loading compiled-in X.509 certificates
10339 05:56:33.053785 <4>[ 1.935189] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10340 05:56:33.064248 <4>[ 1.946069] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10341 05:56:33.070746 <3>[ 1.956613] debugfs: File 'uA_load' in directory '/' already present!
10342 05:56:33.077010 <3>[ 1.963325] debugfs: File 'min_uV' in directory '/' already present!
10343 05:56:33.083753 <3>[ 1.969936] debugfs: File 'max_uV' in directory '/' already present!
10344 05:56:33.090549 <3>[ 1.976544] debugfs: File 'constraint_flags' in directory '/' already present!
10345 05:56:33.101386 <3>[ 1.986085] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10346 05:56:33.116486 <6>[ 2.004025] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10347 05:56:33.123150 <6>[ 2.010905] xhci-mtk 11200000.usb: xHCI Host Controller
10348 05:56:33.129654 <6>[ 2.016451] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10349 05:56:33.139870 <6>[ 2.024326] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10350 05:56:33.146159 <6>[ 2.033777] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10351 05:56:33.153462 <6>[ 2.039885] xhci-mtk 11200000.usb: xHCI Host Controller
10352 05:56:33.159776 <6>[ 2.045374] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10353 05:56:33.166944 <6>[ 2.053031] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10354 05:56:33.172982 <6>[ 2.060898] hub 1-0:1.0: USB hub found
10355 05:56:33.176307 <6>[ 2.064917] hub 1-0:1.0: 1 port detected
10356 05:56:33.186600 <6>[ 2.069232] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10357 05:56:33.189438 <6>[ 2.078059] hub 2-0:1.0: USB hub found
10358 05:56:33.192809 <6>[ 2.082081] hub 2-0:1.0: 1 port detected
10359 05:56:33.200571 <6>[ 2.088608] mtk-msdc 11f70000.mmc: Got CD GPIO
10360 05:56:33.215574 <6>[ 2.099908] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10361 05:56:33.221865 <6>[ 2.107935] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10362 05:56:33.232036 <4>[ 2.115860] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10363 05:56:33.241820 <6>[ 2.125430] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10364 05:56:33.248011 <6>[ 2.133509] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10365 05:56:33.254966 <6>[ 2.141517] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10366 05:56:33.265016 <6>[ 2.149436] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10367 05:56:33.271881 <6>[ 2.157254] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10368 05:56:33.281492 <6>[ 2.165071] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10369 05:56:33.291124 <6>[ 2.175449] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10370 05:56:33.298295 <6>[ 2.183808] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10371 05:56:33.307910 <6>[ 2.192154] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10372 05:56:33.314597 <6>[ 2.200493] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10373 05:56:33.324364 <6>[ 2.208831] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10374 05:56:33.334315 <6>[ 2.217169] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10375 05:56:33.340856 <6>[ 2.225508] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10376 05:56:33.350911 <6>[ 2.233846] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10377 05:56:33.357251 <6>[ 2.242184] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10378 05:56:33.367145 <6>[ 2.250524] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10379 05:56:33.373966 <6>[ 2.258861] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10380 05:56:33.383673 <6>[ 2.267198] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10381 05:56:33.390595 <6>[ 2.275536] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10382 05:56:33.400047 <6>[ 2.283873] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10383 05:56:33.407029 <6>[ 2.292211] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10384 05:56:33.413633 <6>[ 2.300937] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10385 05:56:33.420074 <6>[ 2.308071] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10386 05:56:33.427027 <6>[ 2.314807] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10387 05:56:33.437292 <6>[ 2.321543] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10388 05:56:33.443683 <6>[ 2.328449] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10389 05:56:33.450229 <6>[ 2.335286] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10390 05:56:33.460347 <6>[ 2.344418] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10391 05:56:33.470304 <6>[ 2.353535] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10392 05:56:33.479906 <6>[ 2.362827] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10393 05:56:33.489967 <6>[ 2.372296] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10394 05:56:33.496818 <6>[ 2.381763] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10395 05:56:33.506580 <6>[ 2.390882] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10396 05:56:33.516535 <6>[ 2.400349] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10397 05:56:33.526418 <6>[ 2.409467] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10398 05:56:33.535910 <6>[ 2.418759] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10399 05:56:33.546497 <6>[ 2.428918] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10400 05:56:33.556443 <6>[ 2.440179] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10401 05:56:33.562966 <6>[ 2.449950] Trying to probe devices needed for running init ...
10402 05:56:33.596175 <6>[ 2.481086] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10403 05:56:33.749331 <6>[ 2.636957] hub 1-1:1.0: USB hub found
10404 05:56:33.752382 <6>[ 2.641312] hub 1-1:1.0: 4 ports detected
10405 05:56:33.760327 <6>[ 2.648287] hub 1-1:1.0: USB hub found
10406 05:56:33.763598 <6>[ 2.652639] hub 1-1:1.0: 4 ports detected
10407 05:56:33.880525 <6>[ 2.765277] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10408 05:56:33.906365 <6>[ 2.794492] hub 2-1:1.0: USB hub found
10409 05:56:33.909426 <6>[ 2.798993] hub 2-1:1.0: 3 ports detected
10410 05:56:33.919113 <6>[ 2.806968] hub 2-1:1.0: USB hub found
10411 05:56:33.922417 <6>[ 2.811419] hub 2-1:1.0: 3 ports detected
10412 05:56:34.084343 <6>[ 2.969176] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10413 05:56:34.216499 <6>[ 3.104729] hub 1-1.4:1.0: USB hub found
10414 05:56:34.220211 <6>[ 3.109402] hub 1-1.4:1.0: 2 ports detected
10415 05:56:34.228659 <6>[ 3.116629] hub 1-1.4:1.0: USB hub found
10416 05:56:34.231923 <6>[ 3.121248] hub 1-1.4:1.0: 2 ports detected
10417 05:56:34.296564 <6>[ 3.181261] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10418 05:56:34.528363 <6>[ 3.413128] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10419 05:56:34.720297 <6>[ 3.605112] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10420 05:56:45.841424 <6>[ 14.734089] ALSA device list:
10421 05:56:45.847920 <6>[ 14.737379] No soundcards found.
10422 05:56:45.855389 <6>[ 14.745137] Freeing unused kernel memory: 8448K
10423 05:56:45.858950 <6>[ 14.750226] Run /init as init process
10424 05:56:45.870381 Loading, please wait...
10425 05:56:45.890613 Starting version 247.3-7+deb11u2
10426 05:56:46.054141 <6>[ 14.940503] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10427 05:56:46.065092 <3>[ 14.950951] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10428 05:56:46.071272 <6>[ 14.957997] remoteproc remoteproc0: scp is available
10429 05:56:46.078104 <3>[ 14.959425] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10430 05:56:46.084765 <6>[ 14.965302] remoteproc remoteproc0: powering up scp
10431 05:56:46.091203 <3>[ 14.973340] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10432 05:56:46.101327 <6>[ 14.977756] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10433 05:56:46.107623 <3>[ 14.987464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10434 05:56:46.114199 <6>[ 14.992914] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10435 05:56:46.124329 <6>[ 14.992994] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10436 05:56:46.134110 <6>[ 14.993009] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10437 05:56:46.137604 <6>[ 14.994289] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10438 05:56:46.144693 <4>[ 15.019467] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10439 05:56:46.154318 <3>[ 15.027358] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10440 05:56:46.161102 <3>[ 15.027364] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10441 05:56:46.167509 <6>[ 15.027661] mc: Linux media interface: v0.10
10442 05:56:46.174147 <4>[ 15.044350] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10443 05:56:46.180641 <3>[ 15.048472] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10444 05:56:46.191171 <3>[ 15.048478] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10445 05:56:46.197432 <6>[ 15.053545] videodev: Linux video capture interface: v2.00
10446 05:56:46.204066 <6>[ 15.070240] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10447 05:56:46.210695 <6>[ 15.078476] usbcore: registered new interface driver r8152
10448 05:56:46.217147 <3>[ 15.082447] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10449 05:56:46.227442 <3>[ 15.085684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10450 05:56:46.234172 <4>[ 15.099104] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10451 05:56:46.237691 <4>[ 15.099104] Fallback method does not support PEC.
10452 05:56:46.248101 <3>[ 15.103798] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10453 05:56:46.254494 <3>[ 15.103811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10454 05:56:46.264692 <3>[ 15.104058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10455 05:56:46.271348 <6>[ 15.118108] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10456 05:56:46.278191 <6>[ 15.119402] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10457 05:56:46.284443 <6>[ 15.119443] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10458 05:56:46.291630 <6>[ 15.119450] remoteproc remoteproc0: remote processor scp is now up
10459 05:56:46.301119 <3>[ 15.119967] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10460 05:56:46.307788 <3>[ 15.127172] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10461 05:56:46.314078 <6>[ 15.133601] pci_bus 0000:00: root bus resource [bus 00-ff]
10462 05:56:46.324081 <6>[ 15.133641] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10463 05:56:46.334343 <6>[ 15.133881] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10464 05:56:46.340789 <3>[ 15.141670] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10465 05:56:46.350335 <6>[ 15.143031] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10466 05:56:46.357137 <6>[ 15.144688] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10467 05:56:46.366879 <3>[ 15.146410] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10468 05:56:46.373381 <6>[ 15.149745] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10469 05:56:46.383504 <3>[ 15.157828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10470 05:56:46.390026 <6>[ 15.161125] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10471 05:56:46.400250 <6>[ 15.163937] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10472 05:56:46.409960 <6>[ 15.165282] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10473 05:56:46.416812 <3>[ 15.171723] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10474 05:56:46.426370 <3>[ 15.171786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10475 05:56:46.430016 <6>[ 15.180302] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10476 05:56:46.436572 <6>[ 15.187151] Bluetooth: Core ver 2.22
10477 05:56:46.443188 <4>[ 15.189720] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10478 05:56:46.452671 <4>[ 15.189729] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10479 05:56:46.459280 <6>[ 15.194762] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10480 05:56:46.462694 <6>[ 15.194837] pci 0000:00:00.0: supports D1 D2
10481 05:56:46.469258 <6>[ 15.195095] usbcore: registered new interface driver cdc_ether
10482 05:56:46.475672 <6>[ 15.203639] NET: Registered PF_BLUETOOTH protocol family
10483 05:56:46.482562 <6>[ 15.203645] Bluetooth: HCI device and connection manager initialized
10484 05:56:46.489158 <6>[ 15.203682] Bluetooth: HCI socket layer initialized
10485 05:56:46.492515 <6>[ 15.203688] Bluetooth: L2CAP socket layer initialized
10486 05:56:46.499029 <6>[ 15.203776] usbcore: registered new interface driver r8153_ecm
10487 05:56:46.505639 <6>[ 15.209859] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10488 05:56:46.512590 <6>[ 15.219539] Bluetooth: SCO socket layer initialized
10489 05:56:46.518849 <6>[ 15.229825] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10490 05:56:46.525502 <6>[ 15.246456] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10491 05:56:46.532018 <6>[ 15.253420] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10492 05:56:46.535448 <6>[ 15.256918] r8152 2-1.3:1.0 eth0: v1.12.13
10493 05:56:46.548877 <6>[ 15.263611] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10494 05:56:46.555092 <6>[ 15.265035] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10495 05:56:46.562033 <6>[ 15.269167] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10496 05:56:46.568417 <6>[ 15.270056] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10497 05:56:46.575019 <6>[ 15.277406] usbcore: registered new interface driver uvcvideo
10498 05:56:46.581375 <6>[ 15.284373] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10499 05:56:46.588249 <6>[ 15.284774] usbcore: registered new interface driver btusb
10500 05:56:46.598015 <4>[ 15.285887] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10501 05:56:46.604815 <3>[ 15.285896] Bluetooth: hci0: Failed to load firmware file (-2)
10502 05:56:46.611259 <3>[ 15.285898] Bluetooth: hci0: Failed to set up firmware (-2)
10503 05:56:46.621096 <4>[ 15.285901] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10504 05:56:46.627908 <6>[ 15.515975] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10505 05:56:46.634414 <6>[ 15.523554] pci 0000:01:00.0: supports D1 D2
10506 05:56:46.640878 <6>[ 15.528079] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10507 05:56:46.658557 <6>[ 15.545031] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10508 05:56:46.665699 <6>[ 15.551948] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10509 05:56:46.672118 <6>[ 15.560028] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10510 05:56:46.682081 <6>[ 15.568025] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10511 05:56:46.688354 <6>[ 15.576025] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10512 05:56:46.698491 <6>[ 15.584024] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10513 05:56:46.701646 <6>[ 15.592024] pci 0000:00:00.0: PCI bridge to [bus 01]
10514 05:56:46.712138 <6>[ 15.597239] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10515 05:56:46.718689 <6>[ 15.605366] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10516 05:56:46.725188 <6>[ 15.612182] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10517 05:56:46.731757 <6>[ 15.618880] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10518 05:56:46.754031 <5>[ 15.640234] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10519 05:56:46.773246 <5>[ 15.659238] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10520 05:56:46.779590 <4>[ 15.666193] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10521 05:56:46.786232 <6>[ 15.675095] cfg80211: failed to load regulatory.db
10522 05:56:46.842781 <6>[ 15.729064] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10523 05:56:46.849594 <6>[ 15.736684] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10524 05:56:46.874080 <6>[ 15.763507] mt7921e 0000:01:00.0: ASIC revision: 79610010
10525 05:56:46.978408 <6>[ 15.864791] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10526 05:56:46.981835 <6>[ 15.864791]
10527 05:56:47.001575 Begin: Loading essential drivers ... done.
10528 05:56:47.004319 Begin: Running /scripts/init-premount ... done.
10529 05:56:47.010957 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10530 05:56:47.020795 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10531 05:56:47.023815 Device /sys/class/net/enx00e04c6803bd found
10532 05:56:47.024308 done.
10533 05:56:47.086839 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10534 05:56:47.248693 <6>[ 16.135127] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10535 05:56:48.088216 <6>[ 16.977925] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10536 05:56:48.095129 <6>[ 16.981217] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10537 05:56:48.258615 IP-Config: no response after 2 secs - giving up
10538 05:56:48.299494 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10539 05:56:49.026244 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10540 05:56:49.033370 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10541 05:56:49.039710 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10542 05:56:49.046372 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10543 05:56:49.052825 host : mt8192-asurada-spherion-r0-cbg-4
10544 05:56:49.059842 domain : lava-rack
10545 05:56:49.062911 rootserver: 192.168.201.1 rootpath:
10546 05:56:49.063465 filename :
10547 05:56:49.152091 done.
10548 05:56:49.158908 Begin: Running /scripts/nfs-bottom ... done.
10549 05:56:49.177284 Begin: Running /scripts/init-bottom ... done.
10550 05:56:50.357575 <6>[ 19.247332] NET: Registered PF_INET6 protocol family
10551 05:56:50.365336 <6>[ 19.255100] Segment Routing with IPv6
10552 05:56:50.368130 <6>[ 19.259058] In-situ OAM (IOAM) with IPv6
10553 05:56:50.503406 <30>[ 19.374151] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10554 05:56:50.510019 <30>[ 19.398572] systemd[1]: Detected architecture arm64.
10555 05:56:50.527570
10556 05:56:50.530686 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10557 05:56:50.530819
10558 05:56:50.553240 <30>[ 19.443683] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10559 05:56:51.415885 <30>[ 20.302728] systemd[1]: Queued start job for default target Graphical Interface.
10560 05:56:51.453116 <30>[ 20.343442] systemd[1]: Created slice system-getty.slice.
10561 05:56:51.460029 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10562 05:56:51.476252 <30>[ 20.366502] systemd[1]: Created slice system-modprobe.slice.
10563 05:56:51.483096 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10564 05:56:51.500301 <30>[ 20.390331] systemd[1]: Created slice system-serial\x2dgetty.slice.
10565 05:56:51.507163 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10566 05:56:51.523949 <30>[ 20.414154] systemd[1]: Created slice User and Session Slice.
10567 05:56:51.530509 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10568 05:56:51.551222 <30>[ 20.437931] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10569 05:56:51.560686 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10570 05:56:51.578867 <30>[ 20.465759] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10571 05:56:51.585773 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10572 05:56:51.610245 <30>[ 20.493703] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10573 05:56:51.616993 <30>[ 20.505938] systemd[1]: Reached target Local Encrypted Volumes.
10574 05:56:51.623593 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10575 05:56:51.638910 <30>[ 20.529257] systemd[1]: Reached target Paths.
10576 05:56:51.642246 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10577 05:56:51.658650 <30>[ 20.549108] systemd[1]: Reached target Remote File Systems.
10578 05:56:51.665405 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10579 05:56:51.678642 <30>[ 20.569078] systemd[1]: Reached target Slices.
10580 05:56:51.685034 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10581 05:56:51.699297 <30>[ 20.589095] systemd[1]: Reached target Swap.
10582 05:56:51.702236 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10583 05:56:51.722548 <30>[ 20.609558] systemd[1]: Listening on initctl Compatibility Named Pipe.
10584 05:56:51.729429 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10585 05:56:51.736049 <30>[ 20.625629] systemd[1]: Listening on Journal Audit Socket.
10586 05:56:51.742491 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10587 05:56:51.760498 <30>[ 20.650514] systemd[1]: Listening on Journal Socket (/dev/log).
10588 05:56:51.767478 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10589 05:56:51.783704 <30>[ 20.673650] systemd[1]: Listening on Journal Socket.
10590 05:56:51.789878 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10591 05:56:51.807908 <30>[ 20.694658] systemd[1]: Listening on Network Service Netlink Socket.
10592 05:56:51.814218 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10593 05:56:51.830348 <30>[ 20.720202] systemd[1]: Listening on udev Control Socket.
10594 05:56:51.836554 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10595 05:56:51.851481 <30>[ 20.741595] systemd[1]: Listening on udev Kernel Socket.
10596 05:56:51.857958 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10597 05:56:51.914732 <30>[ 20.805262] systemd[1]: Mounting Huge Pages File System...
10598 05:56:51.921040 Mounting [0;1;39mHuge Pages File System[0m...
10599 05:56:51.941719 <30>[ 20.829364] systemd[1]: Mounting POSIX Message Queue File System...
10600 05:56:51.944954 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10601 05:56:51.966895 <30>[ 20.857452] systemd[1]: Mounting Kernel Debug File System...
10602 05:56:51.973331 Mounting [0;1;39mKernel Debug File System[0m...
10603 05:56:51.990395 <30>[ 20.877674] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10604 05:56:52.042877 <30>[ 20.929939] systemd[1]: Starting Create list of static device nodes for the current kernel...
10605 05:56:52.049342 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10606 05:56:52.071105 <30>[ 20.961793] systemd[1]: Starting Load Kernel Module configfs...
10607 05:56:52.077608 Starting [0;1;39mLoad Kernel Module configfs[0m...
10608 05:56:52.135103 <30>[ 21.025576] systemd[1]: Starting Load Kernel Module drm...
10609 05:56:52.141449 Starting [0;1;39mLoad Kernel Module drm[0m...
10610 05:56:52.159211 <30>[ 21.049839] systemd[1]: Starting Load Kernel Module fuse...
10611 05:56:52.165769 Starting [0;1;39mLoad Kernel Module fuse[0m...
10612 05:56:52.196994 <6>[ 21.087548] fuse: init (API version 7.37)
10613 05:56:52.207739 <30>[ 21.088319] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10614 05:56:52.251863 <30>[ 21.141825] systemd[1]: Starting Journal Service...
10615 05:56:52.257985 Starting [0;1;39mJournal Service[0m...
10616 05:56:52.281690 <30>[ 21.171878] systemd[1]: Starting Load Kernel Modules...
10617 05:56:52.288197 Starting [0;1;39mLoad Kernel Modules[0m...
10618 05:56:52.312415 <30>[ 21.199507] systemd[1]: Starting Remount Root and Kernel File Systems...
10619 05:56:52.318974 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10620 05:56:52.336419 <30>[ 21.226719] systemd[1]: Starting Coldplug All udev Devices...
10621 05:56:52.343019 Starting [0;1;39mColdplug All udev Devices[0m...
10622 05:56:52.369135 <3>[ 21.255932] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10623 05:56:52.375520 <30>[ 21.258967] systemd[1]: Mounted Huge Pages File System.
10624 05:56:52.381954 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10625 05:56:52.396020 <30>[ 21.285772] systemd[1]: Mounted POSIX Message Queue File System.
10626 05:56:52.405696 <3>[ 21.287982] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10627 05:56:52.412613 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10628 05:56:52.427654 <30>[ 21.317845] systemd[1]: Mounted Kernel Debug File System.
10629 05:56:52.434356 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10630 05:56:52.444885 <3>[ 21.332061] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10631 05:56:52.459039 <30>[ 21.345973] systemd[1]: Finished Create list of static device nodes for the current kernel.
10632 05:56:52.472847 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes<3>[ 21.359224] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10633 05:56:52.475720 for the current kernel[0m.
10634 05:56:52.492308 <30>[ 21.382193] systemd[1]: modprobe@configfs.service: Succeeded.
10635 05:56:52.502321 <3>[ 21.388139] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10636 05:56:52.509032 <30>[ 21.389503] systemd[1]: Finished Load Kernel Module configfs.
10637 05:56:52.515653 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10638 05:56:52.528893 <3>[ 21.416007] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10639 05:56:52.536357 <30>[ 21.426665] systemd[1]: modprobe@drm.service: Succeeded.
10640 05:56:52.543092 <30>[ 21.433067] systemd[1]: Finished Load Kernel Module drm.
10641 05:56:52.556693 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m<3>[ 21.443378] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10642 05:56:52.559927 .
10643 05:56:52.576203 <30>[ 21.466121] systemd[1]: modprobe@fuse.service: Succeeded.
10644 05:56:52.583044 <30>[ 21.472431] systemd[1]: Finished Load Kernel Module fuse.
10645 05:56:52.592608 <3>[ 21.472961] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10646 05:56:52.599208 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10647 05:56:52.619568 <3>[ 21.506534] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10648 05:56:52.627347 <30>[ 21.517507] systemd[1]: Finished Load Kernel Modules.
10649 05:56:52.634137 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10650 05:56:52.649654 <3>[ 21.535938] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10651 05:56:52.655684 <30>[ 21.545695] systemd[1]: Finished Remount Root and Kernel File Systems.
10652 05:56:52.665882 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10653 05:56:52.719991 <30>[ 21.610437] systemd[1]: Started Journal Service.
10654 05:56:52.726655 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10655 05:56:52.748032 Mounting [0;1;39mFUSE Control File System[0m...
10656 05:56:52.795587 Mounting [0;1;39mKernel Configuration File System[0m...
10657 05:56:52.822089 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10658 05:56:52.844202 Starting [0;1;39mLoad/Save Random Seed[0m...
10659 05:56:52.864649 Starting [0;1;39mApply Kernel Variables[0m...
10660 05:56:52.876304 <46>[ 21.763511] systemd-journald[289]: Received client request to flush runtime journal.
10661 05:56:52.885768 Starting [0;1;39mCreate System Users[0m...
10662 05:56:52.901965 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10663 05:56:52.920486 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10664 05:56:52.936924 <4>[ 21.816777] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10665 05:56:52.943446 <3>[ 21.832866] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10666 05:56:52.952154 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10667 05:56:52.973031 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10668 05:56:52.986329 See 'systemctl status systemd-udev-trigger.service' for details.
10669 05:56:53.004140 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10670 05:56:54.270400 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10671 05:56:54.291117 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10672 05:56:54.324636 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10673 05:56:54.406364 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10674 05:56:54.419789 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10675 05:56:54.435037 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10676 05:56:54.491452 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10677 05:56:54.518377 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10678 05:56:54.683700 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10679 05:56:54.741135 Starting [0;1;39mNetwork Service[0m...
10680 05:56:54.856865 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10681 05:56:55.076133 Starting [0;1;39mNetwork Time Synchronization[0m...
10682 05:56:55.095807 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10683 05:56:55.393770 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10684 05:56:55.472430 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10685 05:56:55.515887 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10686 05:56:55.589159 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10687 05:56:55.645012 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10688 05:56:55.657674 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10689 05:56:55.674114 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10690 05:56:55.690157 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10691 05:56:55.709622 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10692 05:56:55.753894 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10693 05:56:55.783181 Starting [0;1;39mNetwork Name Resolution[0m...
10694 05:56:55.804240 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10695 05:56:55.819565 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10696 05:56:55.841946 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10697 05:56:55.863843 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10698 05:56:55.889954 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10699 05:56:55.928990 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10700 05:56:55.945558 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10701 05:56:55.961940 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10702 05:56:55.984697 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10703 05:56:55.998005 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10704 05:56:56.014075 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10705 05:56:56.079457 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10706 05:56:56.258362 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10707 05:56:56.386833 Starting [0;1;39mUser Login Management[0m...
10708 05:56:56.407802 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10709 05:56:56.652381 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10710 05:56:56.669617 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10711 05:56:56.685040 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10712 05:56:56.707668 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10713 05:56:56.756572 Starting [0;1;39mPermit User Sessions[0m...
10714 05:56:56.782339 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10715 05:56:56.805677 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10716 05:56:56.849980 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10717 05:56:56.869786 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10718 05:56:56.890402 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10719 05:56:56.910069 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10720 05:56:56.933196 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10721 05:56:56.952666 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10722 05:56:56.996435 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10723 05:56:57.041122 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10724 05:56:57.124263
10725 05:56:57.124415
10726 05:56:57.127782 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10727 05:56:57.127867
10728 05:56:57.130937 debian-bullseye-arm64 login: root (automatic login)
10729 05:56:57.131023
10730 05:56:57.131109
10731 05:56:57.443258 Linux debian-bullseye-arm64 6.1.67-cip12 #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023 aarch64
10732 05:56:57.443409
10733 05:56:57.450280 The programs included with the Debian GNU/Linux system are free software;
10734 05:56:57.456484 the exact distribution terms for each program are described in the
10735 05:56:57.459772 individual files in /usr/share/doc/*/copyright.
10736 05:56:57.459858
10737 05:56:57.466452 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10738 05:56:57.469625 permitted by applicable law.
10739 05:56:58.362682 Matched prompt #10: / #
10741 05:56:58.363036 Setting prompt string to ['/ #']
10742 05:56:58.363151 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10744 05:56:58.363395 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10745 05:56:58.363515 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
10746 05:56:58.363621 Setting prompt string to ['/ #']
10747 05:56:58.363742 Forcing a shell prompt, looking for ['/ #']
10749 05:56:58.414036 / #
10750 05:56:58.414188 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10751 05:56:58.414299 Waiting using forced prompt support (timeout 00:02:30)
10752 05:56:58.419030
10753 05:56:58.419315 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10754 05:56:58.419435 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
10756 05:56:58.519787 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12379428/extract-nfsrootfs-vcgwrj83'
10757 05:56:58.524940 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12379428/extract-nfsrootfs-vcgwrj83'
10759 05:56:58.625466 / # export NFS_SERVER_IP='192.168.201.1'
10760 05:56:58.630555 export NFS_SERVER_IP='192.168.201.1'
10761 05:56:58.630862 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10762 05:56:58.630994 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
10763 05:56:58.631121 end: 2 depthcharge-action (duration 00:01:24) [common]
10764 05:56:58.631239 start: 3 lava-test-retry (timeout 00:07:55) [common]
10765 05:56:58.631356 start: 3.1 lava-test-shell (timeout 00:07:55) [common]
10766 05:56:58.631452 Using namespace: common
10768 05:56:58.731853 / # #
10769 05:56:58.732023 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10770 05:56:58.736905 #
10771 05:56:58.737178 Using /lava-12379428
10773 05:56:58.837529 / # export SHELL=/bin/bash
10774 05:56:58.842664 export SHELL=/bin/bash
10776 05:56:58.943248 / # . /lava-12379428/environment
10777 05:56:58.948475 . /lava-12379428/environment
10779 05:56:59.053951 / # /lava-12379428/bin/lava-test-runner /lava-12379428/0
10780 05:56:59.054125 Test shell timeout: 10s (minimum of the action and connection timeout)
10781 05:56:59.059221 /lava-12379428/bin/lava-test-runner /lava-12379428/0
10782 05:56:59.285169 + export TESTRUN_ID=0_timesync-off
10783 05:56:59.288136 + TESTRUN_ID=0_timesync-off
10784 05:56:59.291377 + cd /lava-12379428/0/tests/0_timesync-off
10785 05:56:59.294474 ++ cat uuid
10786 05:56:59.294556 + UUID=12379428_1.6.2.3.1
10787 05:56:59.297932 + set +x
10788 05:56:59.300971 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12379428_1.6.2.3.1>
10789 05:56:59.301229 Received signal: <STARTRUN> 0_timesync-off 12379428_1.6.2.3.1
10790 05:56:59.301308 Starting test lava.0_timesync-off (12379428_1.6.2.3.1)
10791 05:56:59.301398 Skipping test definition patterns.
10792 05:56:59.304776 + systemctl stop systemd-timesyncd
10793 05:56:59.360636 + set +x
10794 05:56:59.363665 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12379428_1.6.2.3.1>
10795 05:56:59.363929 Received signal: <ENDRUN> 0_timesync-off 12379428_1.6.2.3.1
10796 05:56:59.364014 Ending use of test pattern.
10797 05:56:59.364077 Ending test lava.0_timesync-off (12379428_1.6.2.3.1), duration 0.06
10799 05:56:59.417169 + export TESTRUN_ID=1_kselftest-arm64
10800 05:56:59.417320 + TESTRUN_ID=1_kselftest-arm64
10801 05:56:59.423997 + cd /lava-12379428/0/tests/1_kselftest-arm64
10802 05:56:59.424114 ++ cat uuid
10803 05:56:59.427106 + UUID=12379428_1.6.2.3.5
10804 05:56:59.427187 + set +x
10805 05:56:59.430458 Received signal: <STARTRUN> 1_kselftest-arm64 12379428_1.6.2.3.5
10806 05:56:59.430538 Starting test lava.1_kselftest-arm64 (12379428_1.6.2.3.5)
10807 05:56:59.430622 Skipping test definition patterns.
10808 05:56:59.433994 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 12379428_1.6.2.3.5>
10809 05:56:59.434070 + cd ./automated/linux/kselftest/
10810 05:56:59.460080 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10811 05:56:59.481004 INFO: install_deps skipped
10812 05:56:59.587977 --2023-12-25 05:56:59-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10813 05:56:59.604553 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10814 05:56:59.737605 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10815 05:56:59.870307 HTTP request sent, awaiting response... 200 OK
10816 05:56:59.873315 Length: 2966180 (2.8M) [application/octet-stream]
10817 05:56:59.876850 Saving to: 'kselftest.tar.xz'
10818 05:56:59.876935
10819 05:56:59.877021
10820 05:57:00.136166 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10821 05:57:00.401750 kselftest.tar.xz 1%[ ] 47.81K 177KB/s
10822 05:57:00.719098 kselftest.tar.xz 7%[> ] 216.08K 400KB/s
10823 05:57:00.996370 kselftest.tar.xz 28%[====> ] 839.68K 972KB/s
10824 05:57:01.116321 kselftest.tar.xz 69%[============> ] 1.97M 1.72MB/s
10825 05:57:01.122760 kselftest.tar.xz 100%[===================>] 2.83M 2.23MB/s in 1.3s
10826 05:57:01.122858
10827 05:57:01.379579 2023-12-25 05:57:01 (2.23 MB/s) - 'kselftest.tar.xz' saved [2966180/2966180]
10828 05:57:01.379731
10829 05:57:06.629382 skiplist:
10830 05:57:06.633204 ========================================
10831 05:57:06.635954 ========================================
10832 05:57:06.672076 arm64:tags_test
10833 05:57:06.675297 arm64:run_tags_test.sh
10834 05:57:06.675426 arm64:fake_sigreturn_bad_magic
10835 05:57:06.678491 arm64:fake_sigreturn_bad_size
10836 05:57:06.681938 arm64:fake_sigreturn_bad_size_for_magic0
10837 05:57:06.685411 arm64:fake_sigreturn_duplicated_fpsimd
10838 05:57:06.688602 arm64:fake_sigreturn_misaligned_sp
10839 05:57:06.691691 arm64:fake_sigreturn_missing_fpsimd
10840 05:57:06.694990 arm64:fake_sigreturn_sme_change_vl
10841 05:57:06.698396 arm64:fake_sigreturn_sve_change_vl
10842 05:57:06.701597 arm64:mangle_pstate_invalid_compat_toggle
10843 05:57:06.704908 arm64:mangle_pstate_invalid_daif_bits
10844 05:57:06.708516 arm64:mangle_pstate_invalid_mode_el1h
10845 05:57:06.711600 arm64:mangle_pstate_invalid_mode_el1t
10846 05:57:06.714756 arm64:mangle_pstate_invalid_mode_el2h
10847 05:57:06.718191 arm64:mangle_pstate_invalid_mode_el2t
10848 05:57:06.721557 arm64:mangle_pstate_invalid_mode_el3h
10849 05:57:06.724647 arm64:mangle_pstate_invalid_mode_el3t
10850 05:57:06.728028 arm64:sme_trap_no_sm
10851 05:57:06.731322 arm64:sme_trap_non_streaming
10852 05:57:06.731406 arm64:sme_trap_za
10853 05:57:06.734774 arm64:sme_vl
10854 05:57:06.734858 arm64:ssve_regs
10855 05:57:06.737915 arm64:sve_regs
10856 05:57:06.737999 arm64:sve_vl
10857 05:57:06.738085 arm64:za_no_regs
10858 05:57:06.741145 arm64:za_regs
10859 05:57:06.741229 arm64:pac
10860 05:57:06.744873 arm64:fp-stress
10861 05:57:06.744957 arm64:sve-ptrace
10862 05:57:06.747867 arm64:sve-probe-vls
10863 05:57:06.747951 arm64:vec-syscfg
10864 05:57:06.748037 arm64:za-fork
10865 05:57:06.750954 arm64:za-ptrace
10866 05:57:06.754293 arm64:check_buffer_fill
10867 05:57:06.754377 arm64:check_child_memory
10868 05:57:06.758199 arm64:check_gcr_el1_cswitch
10869 05:57:06.760860 arm64:check_ksm_options
10870 05:57:06.760944 arm64:check_mmap_options
10871 05:57:06.764346 arm64:check_prctl
10872 05:57:06.767394 arm64:check_tags_inclusion
10873 05:57:06.767478 arm64:check_user_mem
10874 05:57:06.770741 arm64:btitest
10875 05:57:06.770825 arm64:nobtitest
10876 05:57:06.770910 arm64:hwcap
10877 05:57:06.774031 arm64:ptrace
10878 05:57:06.774115 arm64:syscall-abi
10879 05:57:06.777467 arm64:tpidr2
10880 05:57:06.780927 ============== Tests to run ===============
10881 05:57:06.781012 arm64:tags_test
10882 05:57:06.784608 arm64:run_tags_test.sh
10883 05:57:06.787416 arm64:fake_sigreturn_bad_magic
10884 05:57:06.787501 arm64:fake_sigreturn_bad_size
10885 05:57:06.793932 arm64:fake_sigreturn_bad_size_for_magic0
10886 05:57:06.797267 arm64:fake_sigreturn_duplicated_fpsimd
10887 05:57:06.800866 arm64:fake_sigreturn_misaligned_sp
10888 05:57:06.804001 arm64:fake_sigreturn_missing_fpsimd
10889 05:57:06.807172 arm64:fake_sigreturn_sme_change_vl
10890 05:57:06.807275 arm64:fake_sigreturn_sve_change_vl
10891 05:57:06.813784 arm64:mangle_pstate_invalid_compat_toggle
10892 05:57:06.816953 arm64:mangle_pstate_invalid_daif_bits
10893 05:57:06.820402 arm64:mangle_pstate_invalid_mode_el1h
10894 05:57:06.823699 arm64:mangle_pstate_invalid_mode_el1t
10895 05:57:06.827340 arm64:mangle_pstate_invalid_mode_el2h
10896 05:57:06.830301 arm64:mangle_pstate_invalid_mode_el2t
10897 05:57:06.834374 arm64:mangle_pstate_invalid_mode_el3h
10898 05:57:06.836716 arm64:mangle_pstate_invalid_mode_el3t
10899 05:57:06.836831 arm64:sme_trap_no_sm
10900 05:57:06.840103 arm64:sme_trap_non_streaming
10901 05:57:06.843553 arm64:sme_trap_za
10902 05:57:06.843637 arm64:sme_vl
10903 05:57:06.843722 arm64:ssve_regs
10904 05:57:06.847038 arm64:sve_regs
10905 05:57:06.847127 arm64:sve_vl
10906 05:57:06.850142 arm64:za_no_regs
10907 05:57:06.850226 arm64:za_regs
10908 05:57:06.850312 arm64:pac
10909 05:57:06.853394 arm64:fp-stress
10910 05:57:06.853478 arm64:sve-ptrace
10911 05:57:06.856710 arm64:sve-probe-vls
10912 05:57:06.856818 arm64:vec-syscfg
10913 05:57:06.860055 arm64:za-fork
10914 05:57:06.860139 arm64:za-ptrace
10915 05:57:06.863293 arm64:check_buffer_fill
10916 05:57:06.866508 arm64:check_child_memory
10917 05:57:06.866592 arm64:check_gcr_el1_cswitch
10918 05:57:06.870024 arm64:check_ksm_options
10919 05:57:06.873202 arm64:check_mmap_options
10920 05:57:06.873287 arm64:check_prctl
10921 05:57:06.876361 arm64:check_tags_inclusion
10922 05:57:06.876445 arm64:check_user_mem
10923 05:57:06.879711 arm64:btitest
10924 05:57:06.879795 arm64:nobtitest
10925 05:57:06.883138 arm64:hwcap
10926 05:57:06.883222 arm64:ptrace
10927 05:57:06.886646 arm64:syscall-abi
10928 05:57:06.886730 arm64:tpidr2
10929 05:57:06.889496 ===========End Tests to run ===============
10930 05:57:06.892861 shardfile-arm64 pass
10931 05:57:07.070614 <12>[ 35.963019] kselftest: Running tests in arm64
10932 05:57:07.079598 TAP version 13
10933 05:57:07.091772 1..48
10934 05:57:07.106190 # selftests: arm64: tags_test
10935 05:57:07.540863 ok 1 selftests: arm64: tags_test
10936 05:57:07.554730 # selftests: arm64: run_tags_test.sh
10937 05:57:07.615030 # --------------------
10938 05:57:07.617921 # running tags test
10939 05:57:07.618003 # --------------------
10940 05:57:07.621316 # [PASS]
10941 05:57:07.624633 ok 2 selftests: arm64: run_tags_test.sh
10942 05:57:07.636655 # selftests: arm64: fake_sigreturn_bad_magic
10943 05:57:07.691921 # Registered handlers for all signals.
10944 05:57:07.695518 # Detected MINSTKSIGSZ:4720
10945 05:57:07.698801 # Testcase initialized.
10946 05:57:07.702047 # uc context validated.
10947 05:57:07.705165 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10948 05:57:07.708614 # Handled SIG_COPYCTX
10949 05:57:07.708761 # Available space:3568
10950 05:57:07.715460 # Using badly built context - ERR: BAD MAGIC !
10951 05:57:07.721728 # SIG_OK -- SP:0xFFFFF4593190 si_addr@:0xfffff4593190 si_code:2 token@:0xfffff4591f30 offset:-4704
10952 05:57:07.725099 # ==>> completed. PASS(1)
10953 05:57:07.731621 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
10954 05:57:07.738638 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF4591F30
10955 05:57:07.741551 ok 3 selftests: arm64: fake_sigreturn_bad_magic
10956 05:57:07.748276 # selftests: arm64: fake_sigreturn_bad_size
10957 05:57:07.760260 # Registered handlers for all signals.
10958 05:57:07.760346 # Detected MINSTKSIGSZ:4720
10959 05:57:07.763329 # Testcase initialized.
10960 05:57:07.766635 # uc context validated.
10961 05:57:07.769986 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10962 05:57:07.773605 # Handled SIG_COPYCTX
10963 05:57:07.773690 # Available space:3568
10964 05:57:07.776603 # uc context validated.
10965 05:57:07.783034 # Using badly built context - ERR: Bad size for esr_context
10966 05:57:07.789782 # SIG_OK -- SP:0xFFFFD7877710 si_addr@:0xffffd7877710 si_code:2 token@:0xffffd78764b0 offset:-4704
10967 05:57:07.793171 # ==>> completed. PASS(1)
10968 05:57:07.799713 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
10969 05:57:07.806447 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD78764B0
10970 05:57:07.809583 ok 4 selftests: arm64: fake_sigreturn_bad_size
10971 05:57:07.816502 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
10972 05:57:07.824233 # Registered handlers for all signals.
10973 05:57:07.824325 # Detected MINSTKSIGSZ:4720
10974 05:57:07.827184 # Testcase initialized.
10975 05:57:07.830430 # uc context validated.
10976 05:57:07.834038 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10977 05:57:07.837198 # Handled SIG_COPYCTX
10978 05:57:07.837288 # Available space:3568
10979 05:57:07.843835 # Using badly built context - ERR: Bad size for terminator
10980 05:57:07.854060 # SIG_OK -- SP:0xFFFFCDFCBAB0 si_addr@:0xffffcdfcbab0 si_code:2 token@:0xffffcdfca850 offset:-4704
10981 05:57:07.854481 # ==>> completed. PASS(1)
10982 05:57:07.864089 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
10983 05:57:07.870372 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCDFCA850
10984 05:57:07.873728 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
10985 05:57:07.880287 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
10986 05:57:07.891625 # Registered handlers for all signals.
10987 05:57:07.892019 # Detected MINSTKSIGSZ:4720
10988 05:57:07.895086 # Testcase initialized.
10989 05:57:07.898189 # uc context validated.
10990 05:57:07.901230 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10991 05:57:07.904539 # Handled SIG_COPYCTX
10992 05:57:07.905011 # Available space:3568
10993 05:57:07.911434 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
10994 05:57:07.921489 # SIG_OK -- SP:0xFFFFDAA6B2C0 si_addr@:0xffffdaa6b2c0 si_code:2 token@:0xffffdaa6a060 offset:-4704
10995 05:57:07.921897 # ==>> completed. PASS(1)
10996 05:57:07.931199 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
10997 05:57:07.938118 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDAA6A060
10998 05:57:07.941160 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
10999 05:57:07.944736 # selftests: arm64: fake_sigreturn_misaligned_sp
11000 05:57:07.971956 # Registered handlers for all signals.
11001 05:57:07.972582 # Detected MINSTKSIGSZ:4720
11002 05:57:07.975228 # Testcase initialized.
11003 05:57:07.978713 # uc context validated.
11004 05:57:07.981834 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11005 05:57:07.985248 # Handled SIG_COPYCTX
11006 05:57:07.992195 # SIG_OK -- SP:0xFFFFFE0560D3 si_addr@:0xfffffe0560d3 si_code:2 token@:0xfffffe0560d3 offset:0
11007 05:57:07.994940 # ==>> completed. PASS(1)
11008 05:57:08.001492 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11009 05:57:08.008013 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFE0560D3
11010 05:57:08.015203 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11011 05:57:08.018608 # selftests: arm64: fake_sigreturn_missing_fpsimd
11012 05:57:08.047406 # Registered handlers for all signals.
11013 05:57:08.047894 # Detected MINSTKSIGSZ:4720
11014 05:57:08.050435 # Testcase initialized.
11015 05:57:08.054024 # uc context validated.
11016 05:57:08.056865 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11017 05:57:08.060462 # Handled SIG_COPYCTX
11018 05:57:08.064179 # Mangling template header. Spare space:4096
11019 05:57:08.067109 # Using badly built context - ERR: Missing FPSIMD
11020 05:57:08.076907 # SIG_OK -- SP:0xFFFFCE708440 si_addr@:0xffffce708440 si_code:2 token@:0xffffce7071e0 offset:-4704
11021 05:57:08.080094 # ==>> completed. PASS(1)
11022 05:57:08.086675 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11023 05:57:08.093209 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCE7071E0
11024 05:57:08.096453 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11025 05:57:08.102930 # selftests: arm64: fake_sigreturn_sme_change_vl
11026 05:57:08.119061 # Registered handlers for all signals.
11027 05:57:08.119654 # Detected MINSTKSIGSZ:4720
11028 05:57:08.122476 # ==>> completed. SKIP.
11029 05:57:08.129025 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11030 05:57:08.132498 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11031 05:57:08.138716 # selftests: arm64: fake_sigreturn_sve_change_vl
11032 05:57:08.201912 # Registered handlers for all signals.
11033 05:57:08.202446 # Detected MINSTKSIGSZ:4720
11034 05:57:08.205276 # ==>> completed. SKIP.
11035 05:57:08.211570 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11036 05:57:08.214853 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11037 05:57:08.222291 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11038 05:57:08.281421 # Registered handlers for all signals.
11039 05:57:08.281950 # Detected MINSTKSIGSZ:4720
11040 05:57:08.284991 # Testcase initialized.
11041 05:57:08.287902 # uc context validated.
11042 05:57:08.288378 # Handled SIG_TRIG
11043 05:57:08.297851 # SIG_OK -- SP:0xFFFFD11B04D0 si_addr@:0xffffd11b04d0 si_code:2 token@:(nil) offset:-281474189952208
11044 05:57:08.301360 # ==>> completed. PASS(1)
11045 05:57:08.308084 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11046 05:57:08.314432 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11047 05:57:08.317500 # selftests: arm64: mangle_pstate_invalid_daif_bits
11048 05:57:08.359892 # Registered handlers for all signals.
11049 05:57:08.360430 # Detected MINSTKSIGSZ:4720
11050 05:57:08.363019 # Testcase initialized.
11051 05:57:08.366225 # uc context validated.
11052 05:57:08.366661 # Handled SIG_TRIG
11053 05:57:08.375987 # SIG_OK -- SP:0xFFFFEEF0DD60 si_addr@:0xffffeef0dd60 si_code:2 token@:(nil) offset:-281474690506080
11054 05:57:08.379509 # ==>> completed. PASS(1)
11055 05:57:08.385905 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11056 05:57:08.389096 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11057 05:57:08.395874 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11058 05:57:08.437095 # Registered handlers for all signals.
11059 05:57:08.437613 # Detected MINSTKSIGSZ:4720
11060 05:57:08.440510 # Testcase initialized.
11061 05:57:08.443447 # uc context validated.
11062 05:57:08.443879 # Handled SIG_TRIG
11063 05:57:08.453564 # SIG_OK -- SP:0xFFFFDFBDF390 si_addr@:0xffffdfbdf390 si_code:2 token@:(nil) offset:-281474435511184
11064 05:57:08.457067 # ==>> completed. PASS(1)
11065 05:57:08.463321 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11066 05:57:08.466577 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11067 05:57:08.473197 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11068 05:57:08.515841 # Registered handlers for all signals.
11069 05:57:08.516357 # Detected MINSTKSIGSZ:4720
11070 05:57:08.519235 # Testcase initialized.
11071 05:57:08.522565 # uc context validated.
11072 05:57:08.522997 # Handled SIG_TRIG
11073 05:57:08.531899 # SIG_OK -- SP:0xFFFFE123AE90 si_addr@:0xffffe123ae90 si_code:2 token@:(nil) offset:-281474458955408
11074 05:57:08.535519 # ==>> completed. PASS(1)
11075 05:57:08.542164 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11076 05:57:08.545165 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11077 05:57:08.551969 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11078 05:57:08.598358 # Registered handlers for all signals.
11079 05:57:08.598879 # Detected MINSTKSIGSZ:4720
11080 05:57:08.601462 # Testcase initialized.
11081 05:57:08.604913 # uc context validated.
11082 05:57:08.605350 # Handled SIG_TRIG
11083 05:57:08.614645 # SIG_OK -- SP:0xFFFFDBEE7ED0 si_addr@:0xffffdbee7ed0 si_code:2 token@:(nil) offset:-281474371583696
11084 05:57:08.618079 # ==>> completed. PASS(1)
11085 05:57:08.624572 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11086 05:57:08.627941 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11087 05:57:08.634919 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11088 05:57:08.674791 # Registered handlers for all signals.
11089 05:57:08.675421 # Detected MINSTKSIGSZ:4720
11090 05:57:08.678261 # Testcase initialized.
11091 05:57:08.681189 # uc context validated.
11092 05:57:08.681622 # Handled SIG_TRIG
11093 05:57:08.691280 # SIG_OK -- SP:0xFFFFCA3C1DE0 si_addr@:0xffffca3c1de0 si_code:2 token@:(nil) offset:-281474074680800
11094 05:57:08.694620 # ==>> completed. PASS(1)
11095 05:57:08.701238 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11096 05:57:08.704648 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11097 05:57:08.710853 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11098 05:57:08.750326 # Registered handlers for all signals.
11099 05:57:08.750769 # Detected MINSTKSIGSZ:4720
11100 05:57:08.753204 # Testcase initialized.
11101 05:57:08.756614 # uc context validated.
11102 05:57:08.757117 # Handled SIG_TRIG
11103 05:57:08.766434 # SIG_OK -- SP:0xFFFFF14EABE0 si_addr@:0xfffff14eabe0 si_code:2 token@:(nil) offset:-281474730208224
11104 05:57:08.769983 # ==>> completed. PASS(1)
11105 05:57:08.776082 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11106 05:57:08.779480 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11107 05:57:08.786230 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11108 05:57:08.839186 # Registered handlers for all signals.
11109 05:57:08.839688 # Detected MINSTKSIGSZ:4720
11110 05:57:08.842303 # Testcase initialized.
11111 05:57:08.845364 # uc context validated.
11112 05:57:08.845884 # Handled SIG_TRIG
11113 05:57:08.855292 # SIG_OK -- SP:0xFFFFE51F1B40 si_addr@:0xffffe51f1b40 si_code:2 token@:(nil) offset:-281474525764416
11114 05:57:08.858365 # ==>> completed. PASS(1)
11115 05:57:08.865173 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11116 05:57:08.868510 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11117 05:57:08.871713 # selftests: arm64: sme_trap_no_sm
11118 05:57:08.917337 # Registered handlers for all signals.
11119 05:57:08.917928 # Detected MINSTKSIGSZ:4720
11120 05:57:08.920202 # ==>> completed. SKIP.
11121 05:57:08.930167 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11122 05:57:08.933510 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11123 05:57:08.936440 # selftests: arm64: sme_trap_non_streaming
11124 05:57:08.999925 # Registered handlers for all signals.
11125 05:57:09.000448 # Detected MINSTKSIGSZ:4720
11126 05:57:09.003028 # ==>> completed. SKIP.
11127 05:57:09.012589 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11128 05:57:09.019290 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11129 05:57:09.022366 # selftests: arm64: sme_trap_za
11130 05:57:09.073389 # Registered handlers for all signals.
11131 05:57:09.073946 # Detected MINSTKSIGSZ:4720
11132 05:57:09.076546 # Testcase initialized.
11133 05:57:09.086372 # SIG_OK -- SP:0xFFFFD90A0F10 si_addr@:0xaaaabb472510 si_code:1 token@:(nil) offset:-187650263164176
11134 05:57:09.086858 # ==>> completed. PASS(1)
11135 05:57:09.096073 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11136 05:57:09.099133 ok 21 selftests: arm64: sme_trap_za
11137 05:57:09.099726 # selftests: arm64: sme_vl
11138 05:57:09.143350 # Registered handlers for all signals.
11139 05:57:09.143859 # Detected MINSTKSIGSZ:4720
11140 05:57:09.146532 # ==>> completed. SKIP.
11141 05:57:09.153315 # # SME VL :: Check that we get the right SME VL reported
11142 05:57:09.156263 ok 22 selftests: arm64: sme_vl # SKIP
11143 05:57:09.160559 # selftests: arm64: ssve_regs
11144 05:57:09.218758 # Registered handlers for all signals.
11145 05:57:09.219289 # Detected MINSTKSIGSZ:4720
11146 05:57:09.221837 # ==>> completed. SKIP.
11147 05:57:09.228487 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11148 05:57:09.234773 ok 23 selftests: arm64: ssve_regs # SKIP
11149 05:57:09.235191 # selftests: arm64: sve_regs
11150 05:57:09.293646 # Registered handlers for all signals.
11151 05:57:09.294243 # Detected MINSTKSIGSZ:4720
11152 05:57:09.296929 # ==>> completed. SKIP.
11153 05:57:09.302810 # # SVE registers :: Check that we get the right SVE registers reported
11154 05:57:09.306240 ok 24 selftests: arm64: sve_regs # SKIP
11155 05:57:09.310384 # selftests: arm64: sve_vl
11156 05:57:09.370999 # Registered handlers for all signals.
11157 05:57:09.371524 # Detected MINSTKSIGSZ:4720
11158 05:57:09.374108 # ==>> completed. SKIP.
11159 05:57:09.380787 # # SVE VL :: Check that we get the right SVE VL reported
11160 05:57:09.383899 ok 25 selftests: arm64: sve_vl # SKIP
11161 05:57:09.390371 # selftests: arm64: za_no_regs
11162 05:57:09.458930 # Registered handlers for all signals.
11163 05:57:09.459435 # Detected MINSTKSIGSZ:4720
11164 05:57:09.462174 # ==>> completed. SKIP.
11165 05:57:09.469352 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11166 05:57:09.472197 ok 26 selftests: arm64: za_no_regs # SKIP
11167 05:57:09.475686 # selftests: arm64: za_regs
11168 05:57:09.531641 # Registered handlers for all signals.
11169 05:57:09.532004 # Detected MINSTKSIGSZ:4720
11170 05:57:09.535001 # ==>> completed. SKIP.
11171 05:57:09.541074 # # ZA register :: Check that we get the right ZA registers reported
11172 05:57:09.544326 ok 27 selftests: arm64: za_regs # SKIP
11173 05:57:09.547960 # selftests: arm64: pac
11174 05:57:09.595826 # TAP version 13
11175 05:57:09.596389 # 1..7
11176 05:57:09.599044 # # Starting 7 tests from 1 test cases.
11177 05:57:09.601735 # # RUN global.corrupt_pac ...
11178 05:57:09.605068 # # SKIP PAUTH not enabled
11179 05:57:09.608413 # # OK global.corrupt_pac
11180 05:57:09.611635 # ok 1 # SKIP PAUTH not enabled
11181 05:57:09.618338 # # RUN global.pac_instructions_not_nop ...
11182 05:57:09.621798 # # SKIP PAUTH not enabled
11183 05:57:09.625074 # # OK global.pac_instructions_not_nop
11184 05:57:09.628134 # ok 2 # SKIP PAUTH not enabled
11185 05:57:09.635107 # # RUN global.pac_instructions_not_nop_generic ...
11186 05:57:09.638410 # # SKIP Generic PAUTH not enabled
11187 05:57:09.641289 # # OK global.pac_instructions_not_nop_generic
11188 05:57:09.647853 # ok 3 # SKIP Generic PAUTH not enabled
11189 05:57:09.651294 # # RUN global.single_thread_different_keys ...
11190 05:57:09.654633 # # SKIP PAUTH not enabled
11191 05:57:09.661215 # # OK global.single_thread_different_keys
11192 05:57:09.661635 # ok 4 # SKIP PAUTH not enabled
11193 05:57:09.668258 # # RUN global.exec_changed_keys ...
11194 05:57:09.671385 # # SKIP PAUTH not enabled
11195 05:57:09.675281 # # OK global.exec_changed_keys
11196 05:57:09.677967 # ok 5 # SKIP PAUTH not enabled
11197 05:57:09.681280 # # RUN global.context_switch_keep_keys ...
11198 05:57:09.684656 # # SKIP PAUTH not enabled
11199 05:57:09.691047 # # OK global.context_switch_keep_keys
11200 05:57:09.691562 # ok 6 # SKIP PAUTH not enabled
11201 05:57:09.697769 # # RUN global.context_switch_keep_keys_generic ...
11202 05:57:09.700978 # # SKIP Generic PAUTH not enabled
11203 05:57:09.707866 # # OK global.context_switch_keep_keys_generic
11204 05:57:09.711215 # ok 7 # SKIP Generic PAUTH not enabled
11205 05:57:09.714131 # # PASSED: 7 / 7 tests passed.
11206 05:57:09.717399 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11207 05:57:09.721124 ok 28 selftests: arm64: pac
11208 05:57:09.724255 # selftests: arm64: fp-stress
11209 05:57:17.029353 <6>[ 45.925799] vpu: disabling
11210 05:57:17.032530 <6>[ 45.928854] vproc2: disabling
11211 05:57:17.036261 <6>[ 45.932125] vproc1: disabling
11212 05:57:17.038882 <6>[ 45.935395] vaud18: disabling
11213 05:57:17.045944 <6>[ 45.938809] vsram_others: disabling
11214 05:57:17.048887 <6>[ 45.942690] va09: disabling
11215 05:57:17.052365 <6>[ 45.945802] vsram_md: disabling
11216 05:57:17.055520 <6>[ 45.949291] Vgpu: disabling
11217 05:57:19.641025 # TAP version 13
11218 05:57:19.641586 # 1..16
11219 05:57:19.644219 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11220 05:57:19.647655 # # Will run for 10s
11221 05:57:19.648114 # # Started FPSIMD-0-0
11222 05:57:19.651222 # # Started FPSIMD-0-1
11223 05:57:19.654369 # # Started FPSIMD-1-0
11224 05:57:19.654934 # # Started FPSIMD-1-1
11225 05:57:19.657598 # # Started FPSIMD-2-0
11226 05:57:19.658062 # # Started FPSIMD-2-1
11227 05:57:19.660553 # # Started FPSIMD-3-0
11228 05:57:19.663839 # # Started FPSIMD-3-1
11229 05:57:19.664302 # # Started FPSIMD-4-0
11230 05:57:19.667130 # # Started FPSIMD-4-1
11231 05:57:19.670423 # # Started FPSIMD-5-0
11232 05:57:19.670885 # # Started FPSIMD-5-1
11233 05:57:19.673699 # # Started FPSIMD-6-0
11234 05:57:19.676958 # # Started FPSIMD-6-1
11235 05:57:19.677418 # # Started FPSIMD-7-0
11236 05:57:19.680349 # # Started FPSIMD-7-1
11237 05:57:19.683775 # # FPSIMD-0-1: Vector length: 128 bits
11238 05:57:19.687329 # # FPSIMD-0-1: PID: 1144
11239 05:57:19.690432 # # FPSIMD-2-0: Vector length: 128 bits
11240 05:57:19.690884 # # FPSIMD-2-0: PID: 1147
11241 05:57:19.693544 # # FPSIMD-1-1: Vector length: 128 bits
11242 05:57:19.696791 # # FPSIMD-1-1: PID: 1146
11243 05:57:19.700242 # # FPSIMD-2-1: Vector length: 128 bits
11244 05:57:19.703498 # # FPSIMD-2-1: PID: 1148
11245 05:57:19.706688 # # FPSIMD-0-0: Vector length: 128 bits
11246 05:57:19.710204 # # FPSIMD-0-0: PID: 1143
11247 05:57:19.713486 # # FPSIMD-1-0: Vector length: 128 bits
11248 05:57:19.713942 # # FPSIMD-1-0: PID: 1145
11249 05:57:19.720100 # # FPSIMD-5-0: Vector length: 128 bits
11250 05:57:19.720564 # # FPSIMD-5-0: PID: 1153
11251 05:57:19.723400 # # FPSIMD-4-0: Vector length: 128 bits
11252 05:57:19.726651 # # FPSIMD-4-0: PID: 1151
11253 05:57:19.729773 # # FPSIMD-3-1: Vector length: 128 bits
11254 05:57:19.733399 # # FPSIMD-3-1: PID: 1150
11255 05:57:19.736735 # # FPSIMD-4-1: Vector length: 128 bits
11256 05:57:19.739740 # # FPSIMD-4-1: PID: 1152
11257 05:57:19.742965 # # FPSIMD-3-0: Vector length: 128 bits
11258 05:57:19.743491 # # FPSIMD-3-0: PID: 1149
11259 05:57:19.749854 # # FPSIMD-6-1: Vector length: 128 bits
11260 05:57:19.750261 # # FPSIMD-6-1: PID: 1156
11261 05:57:19.752872 # # FPSIMD-7-0: Vector length: 128 bits
11262 05:57:19.756431 # # FPSIMD-7-0: PID: 1157
11263 05:57:19.759467 # # FPSIMD-7-1: Vector length: 128 bits
11264 05:57:19.762992 # # FPSIMD-7-1: PID: 1158
11265 05:57:19.766185 # # FPSIMD-5-1: Vector length: 128 bits
11266 05:57:19.769488 # # FPSIMD-5-1: PID: 1154
11267 05:57:19.773172 # # FPSIMD-6-0: Vector length: 128 bits
11268 05:57:19.773581 # # FPSIMD-6-0: PID: 1155
11269 05:57:19.776523 # # Finishing up...
11270 05:57:19.782993 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1130610, signals=10
11271 05:57:19.789471 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1202166, signals=10
11272 05:57:19.799231 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1166588, signals=10
11273 05:57:19.805524 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=2172828, signals=10
11274 05:57:19.812239 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=2162759, signals=10
11275 05:57:19.818885 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=2240126, signals=10
11276 05:57:19.822225 # ok 1 FPSIMD-0-0
11277 05:57:19.822636 # ok 2 FPSIMD-0-1
11278 05:57:19.825498 # ok 3 FPSIMD-1-0
11279 05:57:19.825905 # ok 4 FPSIMD-1-1
11280 05:57:19.828880 # ok 5 FPSIMD-2-0
11281 05:57:19.829292 # ok 6 FPSIMD-2-1
11282 05:57:19.832208 # ok 7 FPSIMD-3-0
11283 05:57:19.832829 # ok 8 FPSIMD-3-1
11284 05:57:19.835667 # ok 9 FPSIMD-4-0
11285 05:57:19.836076 # ok 10 FPSIMD-4-1
11286 05:57:19.839033 # ok 11 FPSIMD-5-0
11287 05:57:19.839569 # ok 12 FPSIMD-5-1
11288 05:57:19.841993 # ok 13 FPSIMD-6-0
11289 05:57:19.842476 # ok 14 FPSIMD-6-1
11290 05:57:19.845485 # ok 15 FPSIMD-7-0
11291 05:57:19.846043 # ok 16 FPSIMD-7-1
11292 05:57:19.852185 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=2201257, signals=10
11293 05:57:19.862047 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1163438, signals=9
11294 05:57:19.868609 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1117742, signals=10
11295 05:57:19.875264 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1121481, signals=10
11296 05:57:19.881683 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1156233, signals=10
11297 05:57:19.888586 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1097371, signals=9
11298 05:57:19.895074 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1186812, signals=10
11299 05:57:19.904835 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1095391, signals=10
11300 05:57:19.911884 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1125622, signals=10
11301 05:57:19.918124 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1156156, signals=9
11302 05:57:19.921553 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11303 05:57:19.924608 ok 29 selftests: arm64: fp-stress
11304 05:57:19.928295 # selftests: arm64: sve-ptrace
11305 05:57:19.931418 # TAP version 13
11306 05:57:19.931880 # 1..4104
11307 05:57:19.935056 # ok 2 # SKIP SVE not available
11308 05:57:19.937972 # # Planned tests != run tests (4104 != 1)
11309 05:57:19.944550 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11310 05:57:19.947874 ok 30 selftests: arm64: sve-ptrace # SKIP
11311 05:57:19.951256 # selftests: arm64: sve-probe-vls
11312 05:57:19.951716 # TAP version 13
11313 05:57:19.952082 # 1..2
11314 05:57:19.954898 # ok 2 # SKIP SVE not available
11315 05:57:19.957800 # # Planned tests != run tests (2 != 1)
11316 05:57:19.964566 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11317 05:57:19.967578 ok 31 selftests: arm64: sve-probe-vls # SKIP
11318 05:57:19.971265 # selftests: arm64: vec-syscfg
11319 05:57:19.971700 # TAP version 13
11320 05:57:19.974505 # 1..20
11321 05:57:19.975020 # ok 1 # SKIP SVE not supported
11322 05:57:19.977876 # ok 2 # SKIP SVE not supported
11323 05:57:19.980822 # ok 3 # SKIP SVE not supported
11324 05:57:19.984338 # ok 4 # SKIP SVE not supported
11325 05:57:19.987335 # ok 5 # SKIP SVE not supported
11326 05:57:19.991005 # ok 6 # SKIP SVE not supported
11327 05:57:19.994159 # ok 7 # SKIP SVE not supported
11328 05:57:19.994583 # ok 8 # SKIP SVE not supported
11329 05:57:19.997433 # ok 9 # SKIP SVE not supported
11330 05:57:20.001176 # ok 10 # SKIP SVE not supported
11331 05:57:20.003867 # ok 11 # SKIP SME not supported
11332 05:57:20.007347 # ok 12 # SKIP SME not supported
11333 05:57:20.010643 # ok 13 # SKIP SME not supported
11334 05:57:20.013809 # ok 14 # SKIP SME not supported
11335 05:57:20.017194 # ok 15 # SKIP SME not supported
11336 05:57:20.020418 # ok 16 # SKIP SME not supported
11337 05:57:20.020885 # ok 17 # SKIP SME not supported
11338 05:57:20.023611 # ok 18 # SKIP SME not supported
11339 05:57:20.027585 # ok 19 # SKIP SME not supported
11340 05:57:20.030132 # ok 20 # SKIP SME not supported
11341 05:57:20.036827 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11342 05:57:20.040126 ok 32 selftests: arm64: vec-syscfg
11343 05:57:20.040546 # selftests: arm64: za-fork
11344 05:57:20.043744 # TAP version 13
11345 05:57:20.044161 # 1..1
11346 05:57:20.046948 # # PID: 1233
11347 05:57:20.047366 # # SME support not present
11348 05:57:20.050373 # ok 0 skipped
11349 05:57:20.053482 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11350 05:57:20.056896 ok 33 selftests: arm64: za-fork
11351 05:57:20.059837 # selftests: arm64: za-ptrace
11352 05:57:20.060255 # TAP version 13
11353 05:57:20.063527 # 1..1
11354 05:57:20.063947 # ok 2 # SKIP SME not available
11355 05:57:20.070293 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11356 05:57:20.073600 ok 34 selftests: arm64: za-ptrace # SKIP
11357 05:57:20.076570 # selftests: arm64: check_buffer_fill
11358 05:57:20.094056 # # SKIP: MTE features unavailable
11359 05:57:20.101311 ok 35 selftests: arm64: check_buffer_fill # SKIP
11360 05:57:20.117587 # selftests: arm64: check_child_memory
11361 05:57:20.170118 # # SKIP: MTE features unavailable
11362 05:57:20.177221 ok 36 selftests: arm64: check_child_memory # SKIP
11363 05:57:20.192799 # selftests: arm64: check_gcr_el1_cswitch
11364 05:57:20.251471 # # SKIP: MTE features unavailable
11365 05:57:20.259627 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11366 05:57:20.275253 # selftests: arm64: check_ksm_options
11367 05:57:20.328312 # # SKIP: MTE features unavailable
11368 05:57:20.335458 ok 38 selftests: arm64: check_ksm_options # SKIP
11369 05:57:20.351394 # selftests: arm64: check_mmap_options
11370 05:57:20.400636 # # SKIP: MTE features unavailable
11371 05:57:20.408218 ok 39 selftests: arm64: check_mmap_options # SKIP
11372 05:57:20.422182 # selftests: arm64: check_prctl
11373 05:57:20.472552 # TAP version 13
11374 05:57:20.473130 # 1..5
11375 05:57:20.475652 # ok 1 check_basic_read
11376 05:57:20.476252 # ok 2 NONE
11377 05:57:20.479132 # ok 3 # SKIP SYNC
11378 05:57:20.479816 # ok 4 # SKIP ASYNC
11379 05:57:20.482400 # ok 5 # SKIP SYNC+ASYNC
11380 05:57:20.485717 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11381 05:57:20.489001 ok 40 selftests: arm64: check_prctl
11382 05:57:20.495329 # selftests: arm64: check_tags_inclusion
11383 05:57:20.559621 # # SKIP: MTE features unavailable
11384 05:57:20.568987 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11385 05:57:20.582818 # selftests: arm64: check_user_mem
11386 05:57:20.651940 # # SKIP: MTE features unavailable
11387 05:57:20.659567 ok 42 selftests: arm64: check_user_mem # SKIP
11388 05:57:20.672458 # selftests: arm64: btitest
11389 05:57:20.728785 # TAP version 13
11390 05:57:20.729037 # 1..18
11391 05:57:20.731772 # # HWCAP_PACA not present
11392 05:57:20.735620 # # HWCAP2_BTI not present
11393 05:57:20.735936 # # Test binary built for BTI
11394 05:57:20.741571 # ok 1 nohint_func/call_using_br_x0 # SKIP
11395 05:57:20.744962 # ok 1 nohint_func/call_using_br_x16 # SKIP
11396 05:57:20.748429 # ok 1 nohint_func/call_using_blr # SKIP
11397 05:57:20.751894 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11398 05:57:20.754864 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11399 05:57:20.761508 # ok 1 bti_none_func/call_using_blr # SKIP
11400 05:57:20.765059 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11401 05:57:20.768439 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11402 05:57:20.771681 # ok 1 bti_c_func/call_using_blr # SKIP
11403 05:57:20.774745 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11404 05:57:20.778348 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11405 05:57:20.781596 # ok 1 bti_j_func/call_using_blr # SKIP
11406 05:57:20.785161 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11407 05:57:20.791533 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11408 05:57:20.794721 # ok 1 bti_jc_func/call_using_blr # SKIP
11409 05:57:20.797916 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11410 05:57:20.801469 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11411 05:57:20.804447 # ok 1 paciasp_func/call_using_blr # SKIP
11412 05:57:20.811430 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11413 05:57:20.814363 # # WARNING - EXPECTED TEST COUNT WRONG
11414 05:57:20.817508 ok 43 selftests: arm64: btitest
11415 05:57:20.821088 # selftests: arm64: nobtitest
11416 05:57:20.821894 # TAP version 13
11417 05:57:20.822587 # 1..18
11418 05:57:20.824377 # # HWCAP_PACA not present
11419 05:57:20.827534 # # HWCAP2_BTI not present
11420 05:57:20.830976 # # Test binary not built for BTI
11421 05:57:20.834227 # ok 1 nohint_func/call_using_br_x0 # SKIP
11422 05:57:20.837390 # ok 1 nohint_func/call_using_br_x16 # SKIP
11423 05:57:20.840874 # ok 1 nohint_func/call_using_blr # SKIP
11424 05:57:20.844061 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11425 05:57:20.850862 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11426 05:57:20.853895 # ok 1 bti_none_func/call_using_blr # SKIP
11427 05:57:20.857312 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11428 05:57:20.860439 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11429 05:57:20.864282 # ok 1 bti_c_func/call_using_blr # SKIP
11430 05:57:20.867212 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11431 05:57:20.870227 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11432 05:57:20.873677 # ok 1 bti_j_func/call_using_blr # SKIP
11433 05:57:20.880337 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11434 05:57:20.883534 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11435 05:57:20.886665 # ok 1 bti_jc_func/call_using_blr # SKIP
11436 05:57:20.889957 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11437 05:57:20.893702 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11438 05:57:20.896767 # ok 1 paciasp_func/call_using_blr # SKIP
11439 05:57:20.903150 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11440 05:57:20.906863 # # WARNING - EXPECTED TEST COUNT WRONG
11441 05:57:20.909945 ok 44 selftests: arm64: nobtitest
11442 05:57:20.913198 # selftests: arm64: hwcap
11443 05:57:20.913610 # TAP version 13
11444 05:57:20.913935 # 1..28
11445 05:57:20.916576 # ok 1 cpuinfo_match_RNG
11446 05:57:20.919737 # # SIGILL reported for RNG
11447 05:57:20.923276 # ok 2 # SKIP sigill_RNG
11448 05:57:20.923763 # ok 3 cpuinfo_match_SME
11449 05:57:20.926543 # ok 4 sigill_SME
11450 05:57:20.926974 # ok 5 cpuinfo_match_SVE
11451 05:57:20.929908 # ok 6 sigill_SVE
11452 05:57:20.933243 # ok 7 cpuinfo_match_SVE 2
11453 05:57:20.933739 # # SIGILL reported for SVE 2
11454 05:57:20.936481 # ok 8 # SKIP sigill_SVE 2
11455 05:57:20.939806 # ok 9 cpuinfo_match_SVE AES
11456 05:57:20.943192 # # SIGILL reported for SVE AES
11457 05:57:20.946356 # ok 10 # SKIP sigill_SVE AES
11458 05:57:20.949626 # ok 11 cpuinfo_match_SVE2 PMULL
11459 05:57:20.952989 # # SIGILL reported for SVE2 PMULL
11460 05:57:20.953396 # ok 12 # SKIP sigill_SVE2 PMULL
11461 05:57:20.956075 # ok 13 cpuinfo_match_SVE2 BITPERM
11462 05:57:20.959516 # # SIGILL reported for SVE2 BITPERM
11463 05:57:20.962858 # ok 14 # SKIP sigill_SVE2 BITPERM
11464 05:57:20.965931 # ok 15 cpuinfo_match_SVE2 SHA3
11465 05:57:20.969218 # # SIGILL reported for SVE2 SHA3
11466 05:57:20.972383 # ok 16 # SKIP sigill_SVE2 SHA3
11467 05:57:20.975458 # ok 17 cpuinfo_match_SVE2 SM4
11468 05:57:20.978758 # # SIGILL reported for SVE2 SM4
11469 05:57:20.982333 # ok 18 # SKIP sigill_SVE2 SM4
11470 05:57:20.982415 # ok 19 cpuinfo_match_SVE2 I8MM
11471 05:57:20.985341 # # SIGILL reported for SVE2 I8MM
11472 05:57:20.988930 # ok 20 # SKIP sigill_SVE2 I8MM
11473 05:57:20.992495 # ok 21 cpuinfo_match_SVE2 F32MM
11474 05:57:20.995696 # # SIGILL reported for SVE2 F32MM
11475 05:57:20.999354 # ok 22 # SKIP sigill_SVE2 F32MM
11476 05:57:21.002538 # ok 23 cpuinfo_match_SVE2 F64MM
11477 05:57:21.005563 # # SIGILL reported for SVE2 F64MM
11478 05:57:21.009342 # ok 24 # SKIP sigill_SVE2 F64MM
11479 05:57:21.012137 # ok 25 cpuinfo_match_SVE2 BF16
11480 05:57:21.012598 # # SIGILL reported for SVE2 BF16
11481 05:57:21.015722 # ok 26 # SKIP sigill_SVE2 BF16
11482 05:57:21.019001 # ok 27 cpuinfo_match_SVE2 EBF16
11483 05:57:21.022150 # ok 28 # SKIP sigill_SVE2 EBF16
11484 05:57:21.028870 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11485 05:57:21.029334 ok 45 selftests: arm64: hwcap
11486 05:57:21.031955 # selftests: arm64: ptrace
11487 05:57:21.035344 # TAP version 13
11488 05:57:21.035837 # 1..7
11489 05:57:21.038575 # # Parent is 1475, child is 1476
11490 05:57:21.039036 # ok 1 read_tpidr_one
11491 05:57:21.041953 # ok 2 write_tpidr_one
11492 05:57:21.045104 # ok 3 verify_tpidr_one
11493 05:57:21.045607 # ok 4 count_tpidrs
11494 05:57:21.048524 # ok 5 tpidr2_write
11495 05:57:21.049042 # ok 6 tpidr2_read
11496 05:57:21.051543 # ok 7 write_tpidr_only
11497 05:57:21.058225 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11498 05:57:21.058649 ok 46 selftests: arm64: ptrace
11499 05:57:21.061699 # selftests: arm64: syscall-abi
11500 05:57:21.065393 # TAP version 13
11501 05:57:21.065781 # 1..2
11502 05:57:21.068677 # ok 1 getpid() FPSIMD
11503 05:57:21.069172 # ok 2 sched_yield() FPSIMD
11504 05:57:21.075439 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11505 05:57:21.078308 ok 47 selftests: arm64: syscall-abi
11506 05:57:21.081748 # selftests: arm64: tpidr2
11507 05:57:21.085007 # TAP version 13
11508 05:57:21.085452 # 1..5
11509 05:57:21.088117 # # PID: 1512
11510 05:57:21.088776 # # SME support not present
11511 05:57:21.091367 # ok 0 skipped, TPIDR2 not supported
11512 05:57:21.094560 # ok 1 skipped, TPIDR2 not supported
11513 05:57:21.098006 # ok 2 skipped, TPIDR2 not supported
11514 05:57:21.101331 # ok 3 skipped, TPIDR2 not supported
11515 05:57:21.104611 # ok 4 skipped, TPIDR2 not supported
11516 05:57:21.111113 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11517 05:57:21.114401 ok 48 selftests: arm64: tpidr2
11518 05:57:21.736606 arm64_tags_test pass
11519 05:57:21.739956 arm64_run_tags_test_sh pass
11520 05:57:21.743392 arm64_fake_sigreturn_bad_magic pass
11521 05:57:21.746094 arm64_fake_sigreturn_bad_size pass
11522 05:57:21.749846 arm64_fake_sigreturn_bad_size_for_magic0 pass
11523 05:57:21.752585 arm64_fake_sigreturn_duplicated_fpsimd pass
11524 05:57:21.756260 arm64_fake_sigreturn_misaligned_sp pass
11525 05:57:21.759661 arm64_fake_sigreturn_missing_fpsimd pass
11526 05:57:21.762549 arm64_fake_sigreturn_sme_change_vl skip
11527 05:57:21.769309 arm64_fake_sigreturn_sve_change_vl skip
11528 05:57:21.772490 arm64_mangle_pstate_invalid_compat_toggle pass
11529 05:57:21.776205 arm64_mangle_pstate_invalid_daif_bits pass
11530 05:57:21.779118 arm64_mangle_pstate_invalid_mode_el1h pass
11531 05:57:21.782312 arm64_mangle_pstate_invalid_mode_el1t pass
11532 05:57:21.785949 arm64_mangle_pstate_invalid_mode_el2h pass
11533 05:57:21.792334 arm64_mangle_pstate_invalid_mode_el2t pass
11534 05:57:21.795926 arm64_mangle_pstate_invalid_mode_el3h pass
11535 05:57:21.799117 arm64_mangle_pstate_invalid_mode_el3t pass
11536 05:57:21.802624 arm64_sme_trap_no_sm skip
11537 05:57:21.806002 arm64_sme_trap_non_streaming skip
11538 05:57:21.806570 arm64_sme_trap_za pass
11539 05:57:21.809232 arm64_sme_vl skip
11540 05:57:21.809734 arm64_ssve_regs skip
11541 05:57:21.812457 arm64_sve_regs skip
11542 05:57:21.813105 arm64_sve_vl skip
11543 05:57:21.815812 arm64_za_no_regs skip
11544 05:57:21.816393 arm64_za_regs skip
11545 05:57:21.818966 arm64_pac_pauth_not_enabled skip
11546 05:57:21.822213 arm64_pac_pauth_not_enabled skip
11547 05:57:21.825854 arm64_pac_generic_pauth_not_enabled skip
11548 05:57:21.828768 arm64_pac_pauth_not_enabled skip
11549 05:57:21.832205 arm64_pac_pauth_not_enabled skip
11550 05:57:21.835327 arm64_pac_pauth_not_enabled skip
11551 05:57:21.838760 arm64_pac_generic_pauth_not_enabled skip
11552 05:57:21.842066 arm64_pac pass
11553 05:57:21.842524 arm64_fp-stress_FPSIMD-0-0 pass
11554 05:57:21.845330 arm64_fp-stress_FPSIMD-0-1 pass
11555 05:57:21.848347 arm64_fp-stress_FPSIMD-1-0 pass
11556 05:57:21.851953 arm64_fp-stress_FPSIMD-1-1 pass
11557 05:57:21.855177 arm64_fp-stress_FPSIMD-2-0 pass
11558 05:57:21.858648 arm64_fp-stress_FPSIMD-2-1 pass
11559 05:57:21.861882 arm64_fp-stress_FPSIMD-3-0 pass
11560 05:57:21.862458 arm64_fp-stress_FPSIMD-3-1 pass
11561 05:57:21.864992 arm64_fp-stress_FPSIMD-4-0 pass
11562 05:57:21.868206 arm64_fp-stress_FPSIMD-4-1 pass
11563 05:57:21.871779 arm64_fp-stress_FPSIMD-5-0 pass
11564 05:57:21.874724 arm64_fp-stress_FPSIMD-5-1 pass
11565 05:57:21.878336 arm64_fp-stress_FPSIMD-6-0 pass
11566 05:57:21.881696 arm64_fp-stress_FPSIMD-6-1 pass
11567 05:57:21.884828 arm64_fp-stress_FPSIMD-7-0 pass
11568 05:57:21.885293 arm64_fp-stress_FPSIMD-7-1 pass
11569 05:57:21.888394 arm64_fp-stress pass
11570 05:57:21.891280 arm64_sve-ptrace_sve_not_available skip
11571 05:57:21.894547 arm64_sve-ptrace skip
11572 05:57:21.897941 arm64_sve-probe-vls_sve_not_available skip
11573 05:57:21.898405 arm64_sve-probe-vls skip
11574 05:57:21.904611 arm64_vec-syscfg_sve_not_supported skip
11575 05:57:21.907750 arm64_vec-syscfg_sve_not_supported skip
11576 05:57:21.910901 arm64_vec-syscfg_sve_not_supported skip
11577 05:57:21.914419 arm64_vec-syscfg_sve_not_supported skip
11578 05:57:21.917922 arm64_vec-syscfg_sve_not_supported skip
11579 05:57:21.920883 arm64_vec-syscfg_sve_not_supported skip
11580 05:57:21.924408 arm64_vec-syscfg_sve_not_supported skip
11581 05:57:21.927809 arm64_vec-syscfg_sve_not_supported skip
11582 05:57:21.931283 arm64_vec-syscfg_sve_not_supported skip
11583 05:57:21.934557 arm64_vec-syscfg_sve_not_supported skip
11584 05:57:21.937703 arm64_vec-syscfg_sme_not_supported skip
11585 05:57:21.940812 arm64_vec-syscfg_sme_not_supported skip
11586 05:57:21.947909 arm64_vec-syscfg_sme_not_supported skip
11587 05:57:21.950930 arm64_vec-syscfg_sme_not_supported skip
11588 05:57:21.954234 arm64_vec-syscfg_sme_not_supported skip
11589 05:57:21.957360 arm64_vec-syscfg_sme_not_supported skip
11590 05:57:21.960840 arm64_vec-syscfg_sme_not_supported skip
11591 05:57:21.964227 arm64_vec-syscfg_sme_not_supported skip
11592 05:57:21.967299 arm64_vec-syscfg_sme_not_supported skip
11593 05:57:21.970345 arm64_vec-syscfg_sme_not_supported skip
11594 05:57:21.973841 arm64_vec-syscfg pass
11595 05:57:21.974298 arm64_za-fork_skipped pass
11596 05:57:21.977162 arm64_za-fork pass
11597 05:57:21.980991 arm64_za-ptrace_sme_not_available skip
11598 05:57:21.983870 arm64_za-ptrace skip
11599 05:57:21.984329 arm64_check_buffer_fill skip
11600 05:57:21.986919 arm64_check_child_memory skip
11601 05:57:21.990337 arm64_check_gcr_el1_cswitch skip
11602 05:57:21.993860 arm64_check_ksm_options skip
11603 05:57:21.996933 arm64_check_mmap_options skip
11604 05:57:22.000942 arm64_check_prctl_check_basic_read pass
11605 05:57:22.001492 arm64_check_prctl_NONE pass
11606 05:57:22.004282 arm64_check_prctl_sync skip
11607 05:57:22.007089 arm64_check_prctl_async skip
11608 05:57:22.010690 arm64_check_prctl_sync_async skip
11609 05:57:22.013436 arm64_check_prctl pass
11610 05:57:22.013897 arm64_check_tags_inclusion skip
11611 05:57:22.016981 arm64_check_user_mem skip
11612 05:57:22.020305 arm64_btitest_nohint_func_call_using_br_x0 skip
11613 05:57:22.027131 arm64_btitest_nohint_func_call_using_br_x16 skip
11614 05:57:22.029941 arm64_btitest_nohint_func_call_using_blr skip
11615 05:57:22.033344 arm64_btitest_bti_none_func_call_using_br_x0 skip
11616 05:57:22.040210 arm64_btitest_bti_none_func_call_using_br_x16 skip
11617 05:57:22.043160 arm64_btitest_bti_none_func_call_using_blr skip
11618 05:57:22.046678 arm64_btitest_bti_c_func_call_using_br_x0 skip
11619 05:57:22.053335 arm64_btitest_bti_c_func_call_using_br_x16 skip
11620 05:57:22.056562 arm64_btitest_bti_c_func_call_using_blr skip
11621 05:57:22.059652 arm64_btitest_bti_j_func_call_using_br_x0 skip
11622 05:57:22.062747 arm64_btitest_bti_j_func_call_using_br_x16 skip
11623 05:57:22.069586 arm64_btitest_bti_j_func_call_using_blr skip
11624 05:57:22.073009 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11625 05:57:22.076166 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11626 05:57:22.079193 arm64_btitest_bti_jc_func_call_using_blr skip
11627 05:57:22.085963 arm64_btitest_paciasp_func_call_using_br_x0 skip
11628 05:57:22.089138 arm64_btitest_paciasp_func_call_using_br_x16 skip
11629 05:57:22.092636 arm64_btitest_paciasp_func_call_using_blr skip
11630 05:57:22.095983 arm64_btitest pass
11631 05:57:22.099523 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11632 05:57:22.105993 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11633 05:57:22.109011 arm64_nobtitest_nohint_func_call_using_blr skip
11634 05:57:22.112519 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11635 05:57:22.119045 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11636 05:57:22.122578 arm64_nobtitest_bti_none_func_call_using_blr skip
11637 05:57:22.125382 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11638 05:57:22.132005 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11639 05:57:22.135217 arm64_nobtitest_bti_c_func_call_using_blr skip
11640 05:57:22.138907 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11641 05:57:22.145173 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11642 05:57:22.148836 arm64_nobtitest_bti_j_func_call_using_blr skip
11643 05:57:22.151926 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11644 05:57:22.158330 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11645 05:57:22.162312 arm64_nobtitest_bti_jc_func_call_using_blr skip
11646 05:57:22.165170 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11647 05:57:22.172139 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11648 05:57:22.174967 arm64_nobtitest_paciasp_func_call_using_blr skip
11649 05:57:22.175388 arm64_nobtitest pass
11650 05:57:22.178342 arm64_hwcap_cpuinfo_match_RNG pass
11651 05:57:22.181474 arm64_hwcap_sigill_rng skip
11652 05:57:22.184820 arm64_hwcap_cpuinfo_match_SME pass
11653 05:57:22.188117 arm64_hwcap_sigill_SME pass
11654 05:57:22.191660 arm64_hwcap_cpuinfo_match_SVE pass
11655 05:57:22.194752 arm64_hwcap_sigill_SVE pass
11656 05:57:22.197885 arm64_hwcap_cpuinfo_match_SVE_2 pass
11657 05:57:22.198360 arm64_hwcap_sigill_sve_2 skip
11658 05:57:22.201699 arm64_hwcap_cpuinfo_match_SVE_AES pass
11659 05:57:22.204629 arm64_hwcap_sigill_sve_aes skip
11660 05:57:22.208309 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11661 05:57:22.211547 arm64_hwcap_sigill_sve2_pmull skip
11662 05:57:22.217988 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11663 05:57:22.221315 arm64_hwcap_sigill_sve2_bitperm skip
11664 05:57:22.224622 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11665 05:57:22.227608 arm64_hwcap_sigill_sve2_sha3 skip
11666 05:57:22.231493 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11667 05:57:22.234294 arm64_hwcap_sigill_sve2_sm4 skip
11668 05:57:22.237462 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11669 05:57:22.240835 arm64_hwcap_sigill_sve2_i8mm skip
11670 05:57:22.244226 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11671 05:57:22.247414 arm64_hwcap_sigill_sve2_f32mm skip
11672 05:57:22.250645 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11673 05:57:22.254093 arm64_hwcap_sigill_sve2_f64mm skip
11674 05:57:22.257797 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11675 05:57:22.260779 arm64_hwcap_sigill_sve2_bf16 skip
11676 05:57:22.263858 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11677 05:57:22.267212 arm64_hwcap_sigill_sve2_ebf16 skip
11678 05:57:22.267632 arm64_hwcap pass
11679 05:57:22.270688 arm64_ptrace_read_tpidr_one pass
11680 05:57:22.273903 arm64_ptrace_write_tpidr_one pass
11681 05:57:22.277241 arm64_ptrace_verify_tpidr_one pass
11682 05:57:22.280510 arm64_ptrace_count_tpidrs pass
11683 05:57:22.283807 arm64_ptrace_tpidr2_write pass
11684 05:57:22.287267 arm64_ptrace_tpidr2_read pass
11685 05:57:22.290345 arm64_ptrace_write_tpidr_only pass
11686 05:57:22.290778 arm64_ptrace pass
11687 05:57:22.293797 arm64_syscall-abi_getpid_FPSIMD pass
11688 05:57:22.297289 arm64_syscall-abi_sched_yield_FPSIMD pass
11689 05:57:22.300031 arm64_syscall-abi pass
11690 05:57:22.303586 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11691 05:57:22.306693 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11692 05:57:22.313495 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11693 05:57:22.317097 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11694 05:57:22.319986 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11695 05:57:22.323467 arm64_tpidr2 pass
11696 05:57:22.326745 + ../../utils/send-to-lava.sh ./output/result.txt
11697 05:57:22.333079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11698 05:57:22.333872 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11700 05:57:22.336385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11701 05:57:22.337102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11703 05:57:22.343307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11704 05:57:22.343981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11706 05:57:22.349872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11707 05:57:22.350549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11709 05:57:22.379058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11710 05:57:22.379738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11712 05:57:22.425534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11713 05:57:22.425951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11715 05:57:22.467375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11716 05:57:22.467857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11718 05:57:22.519938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11719 05:57:22.520660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11721 05:57:22.570680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11722 05:57:22.571402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11724 05:57:22.622212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11725 05:57:22.622926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11727 05:57:22.671465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11728 05:57:22.672195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11730 05:57:22.720362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11731 05:57:22.721205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11733 05:57:22.770332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11734 05:57:22.771039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
11736 05:57:22.823290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
11737 05:57:22.824033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
11739 05:57:22.876662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
11740 05:57:22.877420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
11742 05:57:22.926970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
11743 05:57:22.927503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
11745 05:57:22.980685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
11746 05:57:22.981414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
11748 05:57:23.033916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
11749 05:57:23.034636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
11751 05:57:23.084255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
11752 05:57:23.085124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
11754 05:57:23.133486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
11755 05:57:23.134241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
11757 05:57:23.187181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
11759 05:57:23.190013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
11760 05:57:23.237823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
11761 05:57:23.238548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
11763 05:57:23.288744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
11764 05:57:23.289470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
11766 05:57:23.338419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
11767 05:57:23.339112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
11769 05:57:23.392012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
11770 05:57:23.392695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
11772 05:57:23.442538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
11773 05:57:23.443221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
11775 05:57:23.492189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
11776 05:57:23.492996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
11778 05:57:23.542461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
11779 05:57:23.543163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
11781 05:57:23.589678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11782 05:57:23.590417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11784 05:57:23.638380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11786 05:57:23.640821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11787 05:57:23.690394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
11788 05:57:23.691082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
11790 05:57:23.741633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11792 05:57:23.744334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11793 05:57:23.791489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11795 05:57:23.794599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11796 05:57:23.841461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11798 05:57:23.844633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11799 05:57:23.894274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
11800 05:57:23.894953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
11802 05:57:23.941552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
11803 05:57:23.942326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
11805 05:57:23.991558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
11806 05:57:23.991815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
11808 05:57:24.038233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
11809 05:57:24.038543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
11811 05:57:24.080727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
11812 05:57:24.080996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
11814 05:57:24.129920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
11815 05:57:24.130457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
11817 05:57:24.189461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
11818 05:57:24.190273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
11820 05:57:24.242585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
11821 05:57:24.243328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
11823 05:57:24.294687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
11824 05:57:24.295383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
11826 05:57:24.346332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
11827 05:57:24.347022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
11829 05:57:24.398308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
11830 05:57:24.399005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
11832 05:57:24.455193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
11833 05:57:24.455893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
11835 05:57:24.507532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
11836 05:57:24.508341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
11838 05:57:24.561528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
11839 05:57:24.562209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
11841 05:57:24.610405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
11842 05:57:24.611089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
11844 05:57:24.653578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
11845 05:57:24.653934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
11847 05:57:24.703363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
11848 05:57:24.704053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
11850 05:57:24.751296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
11851 05:57:24.752007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
11853 05:57:24.801386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
11854 05:57:24.802071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
11856 05:57:24.856646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
11857 05:57:24.857500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
11859 05:57:24.906770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
11860 05:57:24.907491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
11862 05:57:24.959798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
11863 05:57:24.960483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
11865 05:57:25.002352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
11866 05:57:25.003030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
11868 05:57:25.057050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11869 05:57:25.057756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11871 05:57:25.101862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11872 05:57:25.102558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11874 05:57:25.144860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11875 05:57:25.145663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11877 05:57:25.189943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11878 05:57:25.190649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11880 05:57:25.231609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11881 05:57:25.231875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11883 05:57:25.269564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11884 05:57:25.269824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11886 05:57:25.303481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11887 05:57:25.303741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11889 05:57:25.337259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11890 05:57:25.337528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11892 05:57:25.371591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11893 05:57:25.371865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11895 05:57:25.408663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11896 05:57:25.408948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11898 05:57:25.444023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11899 05:57:25.444293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11901 05:57:25.476532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11902 05:57:25.476798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11904 05:57:25.510419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11905 05:57:25.510673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11907 05:57:25.543799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11908 05:57:25.544065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11910 05:57:25.579676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11911 05:57:25.579935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11913 05:57:25.614680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11914 05:57:25.614934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11916 05:57:25.645762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11917 05:57:25.646024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11919 05:57:25.678756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11920 05:57:25.679014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11922 05:57:25.713364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11923 05:57:25.713620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11925 05:57:25.747642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11926 05:57:25.747937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11928 05:57:25.778500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
11929 05:57:25.778755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
11931 05:57:25.812702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
11932 05:57:25.812980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
11934 05:57:25.847524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
11935 05:57:25.847784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
11937 05:57:25.883027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
11938 05:57:25.883285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
11940 05:57:25.917084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
11941 05:57:25.917340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
11943 05:57:25.953715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
11944 05:57:25.953977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
11946 05:57:25.983284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
11947 05:57:25.983540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
11949 05:57:26.018728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
11951 05:57:26.021696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
11952 05:57:26.053753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
11953 05:57:26.054012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
11955 05:57:26.087044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
11956 05:57:26.087302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
11958 05:57:26.132643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
11959 05:57:26.132951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
11961 05:57:26.163279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
11962 05:57:26.163575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
11964 05:57:26.197759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
11965 05:57:26.198015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
11967 05:57:26.231462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
11968 05:57:26.231752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
11970 05:57:26.266748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
11972 05:57:26.270325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
11973 05:57:26.304097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
11974 05:57:26.304378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
11976 05:57:26.340365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
11977 05:57:26.340653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
11979 05:57:26.373964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
11980 05:57:26.374230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
11982 05:57:26.412279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
11983 05:57:26.412577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
11985 05:57:26.445691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
11986 05:57:26.445983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
11988 05:57:26.479205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
11989 05:57:26.479489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
11991 05:57:26.514150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
11992 05:57:26.514403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
11994 05:57:26.549726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
11995 05:57:26.549990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
11997 05:57:26.584207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
11998 05:57:26.584471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12000 05:57:26.618710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12001 05:57:26.618994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12003 05:57:26.651431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12004 05:57:26.651735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12006 05:57:26.687443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12007 05:57:26.687723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12009 05:57:26.723925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12010 05:57:26.724198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12012 05:57:26.761577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12013 05:57:26.761840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12015 05:57:26.797560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12016 05:57:26.797835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12018 05:57:26.830483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12019 05:57:26.830747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12021 05:57:26.865938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12022 05:57:26.866217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12024 05:57:26.898257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12025 05:57:26.898527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12027 05:57:26.929964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12028 05:57:26.930227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12030 05:57:26.964355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12031 05:57:26.964633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12033 05:57:27.003311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12034 05:57:27.003610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12036 05:57:27.039205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12037 05:57:27.039491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12039 05:57:27.073005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12040 05:57:27.073277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12042 05:57:27.111518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12043 05:57:27.111800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12045 05:57:27.147617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12046 05:57:27.147877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12048 05:57:27.184103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12049 05:57:27.184367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12051 05:57:27.221287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12052 05:57:27.221545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12054 05:57:27.255280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12055 05:57:27.255545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12057 05:57:27.291261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12058 05:57:27.291518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12060 05:57:27.327425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12061 05:57:27.327713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12063 05:57:27.363379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12064 05:57:27.363639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12066 05:57:27.400574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12067 05:57:27.400874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12069 05:57:27.432732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12070 05:57:27.433012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12072 05:57:27.467021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12073 05:57:27.467370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12075 05:57:27.506605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12076 05:57:27.506903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12078 05:57:27.545828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12079 05:57:27.546122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12081 05:57:27.585701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12082 05:57:27.585959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12084 05:57:27.624434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12085 05:57:27.624724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12087 05:57:27.663266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12088 05:57:27.663561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12090 05:57:27.695505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12091 05:57:27.695791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12093 05:57:27.730327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12094 05:57:27.730608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12096 05:57:27.765839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12097 05:57:27.766124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12099 05:57:27.806524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12100 05:57:27.806797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12102 05:57:27.846624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12103 05:57:27.846905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12105 05:57:27.883412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12106 05:57:27.883685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12108 05:57:27.926619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12109 05:57:27.926877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12111 05:57:27.959652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12112 05:57:27.959928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12114 05:57:28.003415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12115 05:57:28.003680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12117 05:57:28.031298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12118 05:57:28.031584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12120 05:57:28.071411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12121 05:57:28.071669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12123 05:57:28.107307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12124 05:57:28.107562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12126 05:57:28.151133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12127 05:57:28.151404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12129 05:57:28.186877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12130 05:57:28.187131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12132 05:57:28.223762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12133 05:57:28.224041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12135 05:57:28.263665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12136 05:57:28.263960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12138 05:57:28.297858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12139 05:57:28.298113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12141 05:57:28.328044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12143 05:57:28.331077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12144 05:57:28.366379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12145 05:57:28.366641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12147 05:57:28.402583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12149 05:57:28.405739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12150 05:57:28.440619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12151 05:57:28.440922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12153 05:57:28.476467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12155 05:57:28.479156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12156 05:57:28.512947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12157 05:57:28.513202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12159 05:57:28.548101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12160 05:57:28.548365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12162 05:57:28.586124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12163 05:57:28.586392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12165 05:57:28.623494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12166 05:57:28.623762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12168 05:57:28.660897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12169 05:57:28.661182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12171 05:57:28.692746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12173 05:57:28.695710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12174 05:57:28.730274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12175 05:57:28.730549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12177 05:57:28.764224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12178 05:57:28.764481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12180 05:57:28.798797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12181 05:57:28.799054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12183 05:57:28.836476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12185 05:57:28.839250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12186 05:57:28.875160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12188 05:57:28.878355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12189 05:57:28.910468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12190 05:57:28.910740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12192 05:57:28.944113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12193 05:57:28.944397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12195 05:57:28.975895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12196 05:57:28.976166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12198 05:57:29.009710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12199 05:57:29.009992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12201 05:57:29.050976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12202 05:57:29.051245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12204 05:57:29.078387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12205 05:57:29.078668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12207 05:57:29.117573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12208 05:57:29.117832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12210 05:57:29.152558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12211 05:57:29.152847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12213 05:57:29.186681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12214 05:57:29.186972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12216 05:57:29.221138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12217 05:57:29.221425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12219 05:57:29.257694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12220 05:57:29.257984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12222 05:57:29.292863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12223 05:57:29.293121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12225 05:57:29.328323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12226 05:57:29.328614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12228 05:57:29.360755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12229 05:57:29.361034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12231 05:57:29.390344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12232 05:57:29.390437 + set +x
12233 05:57:29.390675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12235 05:57:29.397263 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 12379428_1.6.2.3.5>
12236 05:57:29.397567 Received signal: <ENDRUN> 1_kselftest-arm64 12379428_1.6.2.3.5
12237 05:57:29.397658 Ending use of test pattern.
12238 05:57:29.397722 Ending test lava.1_kselftest-arm64 (12379428_1.6.2.3.5), duration 29.97
12240 05:57:29.400536 <LAVA_TEST_RUNNER EXIT>
12241 05:57:29.400790 ok: lava_test_shell seems to have completed
12242 05:57:29.401777 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12243 05:57:29.401927 end: 3.1 lava-test-shell (duration 00:00:31) [common]
12244 05:57:29.402015 end: 3 lava-test-retry (duration 00:00:31) [common]
12245 05:57:29.402104 start: 4 finalize (timeout 00:07:24) [common]
12246 05:57:29.402195 start: 4.1 power-off (timeout 00:00:30) [common]
12247 05:57:29.402347 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
12248 05:57:29.477094 >> Command sent successfully.
12249 05:57:29.479424 Returned 0 in 0 seconds
12250 05:57:29.579818 end: 4.1 power-off (duration 00:00:00) [common]
12252 05:57:29.580146 start: 4.2 read-feedback (timeout 00:07:24) [common]
12253 05:57:29.580422 Listened to connection for namespace 'common' for up to 1s
12254 05:57:30.581372 Finalising connection for namespace 'common'
12255 05:57:30.581558 Disconnecting from shell: Finalise
12256 05:57:30.581638 / #
12257 05:57:30.681970 end: 4.2 read-feedback (duration 00:00:01) [common]
12258 05:57:30.682155 end: 4 finalize (duration 00:00:01) [common]
12259 05:57:30.682331 Cleaning after the job
12260 05:57:30.682457 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/ramdisk
12261 05:57:30.685497 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/kernel
12262 05:57:30.699032 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/dtb
12263 05:57:30.699298 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/nfsrootfs
12264 05:57:30.788810 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379428/tftp-deploy-k5yrtuvm/modules
12265 05:57:30.795876 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12379428
12266 05:57:31.458062 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12379428
12267 05:57:31.458248 Job finished correctly