Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 17
- Kernel Errors: 37
- Errors: 0
1 05:55:30.771446 lava-dispatcher, installed at version: 2023.10
2 05:55:30.771655 start: 0 validate
3 05:55:30.771788 Start time: 2023-12-25 05:55:30.771778+00:00 (UTC)
4 05:55:30.771904 Using caching service: 'http://localhost/cache/?uri=%s'
5 05:55:30.772029 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 05:55:31.041949 Using caching service: 'http://localhost/cache/?uri=%s'
7 05:55:31.042874 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 05:55:31.315665 Using caching service: 'http://localhost/cache/?uri=%s'
9 05:55:31.316522 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 05:55:31.586856 Using caching service: 'http://localhost/cache/?uri=%s'
11 05:55:31.587605 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:55:31.857294 Using caching service: 'http://localhost/cache/?uri=%s'
13 05:55:31.858067 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 05:55:32.133178 validate duration: 1.36
16 05:55:32.134351 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:55:32.134904 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:55:32.135421 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:55:32.136145 Not decompressing ramdisk as can be used compressed.
20 05:55:32.136603 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 05:55:32.136937 saving as /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/ramdisk/initrd.cpio.gz
22 05:55:32.137270 total size: 4665395 (4 MB)
23 05:55:32.142179 progress 0 % (0 MB)
24 05:55:32.150321 progress 5 % (0 MB)
25 05:55:32.157054 progress 10 % (0 MB)
26 05:55:32.161934 progress 15 % (0 MB)
27 05:55:32.165439 progress 20 % (0 MB)
28 05:55:32.168703 progress 25 % (1 MB)
29 05:55:32.171587 progress 30 % (1 MB)
30 05:55:32.174008 progress 35 % (1 MB)
31 05:55:32.176275 progress 40 % (1 MB)
32 05:55:32.178656 progress 45 % (2 MB)
33 05:55:32.180588 progress 50 % (2 MB)
34 05:55:32.182553 progress 55 % (2 MB)
35 05:55:32.184263 progress 60 % (2 MB)
36 05:55:32.185982 progress 65 % (2 MB)
37 05:55:32.187665 progress 70 % (3 MB)
38 05:55:32.189181 progress 75 % (3 MB)
39 05:55:32.190732 progress 80 % (3 MB)
40 05:55:32.192452 progress 85 % (3 MB)
41 05:55:32.193842 progress 90 % (4 MB)
42 05:55:32.195212 progress 95 % (4 MB)
43 05:55:32.196602 progress 100 % (4 MB)
44 05:55:32.196776 4 MB downloaded in 0.06 s (74.74 MB/s)
45 05:55:32.196945 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:55:32.197207 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:55:32.197301 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:55:32.197400 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:55:32.197543 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 05:55:32.197613 saving as /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/kernel/Image
52 05:55:32.197673 total size: 50024960 (47 MB)
53 05:55:32.197734 No compression specified
54 05:55:32.198822 progress 0 % (0 MB)
55 05:55:32.211804 progress 5 % (2 MB)
56 05:55:32.224709 progress 10 % (4 MB)
57 05:55:32.237758 progress 15 % (7 MB)
58 05:55:32.250777 progress 20 % (9 MB)
59 05:55:32.263695 progress 25 % (11 MB)
60 05:55:32.276757 progress 30 % (14 MB)
61 05:55:32.289896 progress 35 % (16 MB)
62 05:55:32.302730 progress 40 % (19 MB)
63 05:55:32.315545 progress 45 % (21 MB)
64 05:55:32.328472 progress 50 % (23 MB)
65 05:55:32.341588 progress 55 % (26 MB)
66 05:55:32.354776 progress 60 % (28 MB)
67 05:55:32.367816 progress 65 % (31 MB)
68 05:55:32.380811 progress 70 % (33 MB)
69 05:55:32.394756 progress 75 % (35 MB)
70 05:55:32.408932 progress 80 % (38 MB)
71 05:55:32.422751 progress 85 % (40 MB)
72 05:55:32.437147 progress 90 % (42 MB)
73 05:55:32.450690 progress 95 % (45 MB)
74 05:55:32.463477 progress 100 % (47 MB)
75 05:55:32.463694 47 MB downloaded in 0.27 s (179.34 MB/s)
76 05:55:32.463845 end: 1.2.1 http-download (duration 00:00:00) [common]
78 05:55:32.464081 end: 1.2 download-retry (duration 00:00:00) [common]
79 05:55:32.464167 start: 1.3 download-retry (timeout 00:10:00) [common]
80 05:55:32.464254 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 05:55:32.464393 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 05:55:32.464464 saving as /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/dtb/mt8192-asurada-spherion-r0.dtb
83 05:55:32.464525 total size: 47278 (0 MB)
84 05:55:32.464585 No compression specified
85 05:55:32.465702 progress 69 % (0 MB)
86 05:55:32.465982 progress 100 % (0 MB)
87 05:55:32.466138 0 MB downloaded in 0.00 s (28.00 MB/s)
88 05:55:32.466258 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:55:32.466476 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:55:32.466562 start: 1.4 download-retry (timeout 00:10:00) [common]
92 05:55:32.466643 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 05:55:32.466754 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 05:55:32.466821 saving as /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/nfsrootfs/full.rootfs.tar
95 05:55:32.466881 total size: 200813988 (191 MB)
96 05:55:32.466942 Using unxz to decompress xz
97 05:55:32.471164 progress 0 % (0 MB)
98 05:55:33.002947 progress 5 % (9 MB)
99 05:55:33.514723 progress 10 % (19 MB)
100 05:55:34.092721 progress 15 % (28 MB)
101 05:55:34.462527 progress 20 % (38 MB)
102 05:55:34.781328 progress 25 % (47 MB)
103 05:55:35.364444 progress 30 % (57 MB)
104 05:55:35.910953 progress 35 % (67 MB)
105 05:55:36.500418 progress 40 % (76 MB)
106 05:55:37.054341 progress 45 % (86 MB)
107 05:55:37.637782 progress 50 % (95 MB)
108 05:55:38.265956 progress 55 % (105 MB)
109 05:55:38.931159 progress 60 % (114 MB)
110 05:55:39.052292 progress 65 % (124 MB)
111 05:55:39.190711 progress 70 % (134 MB)
112 05:55:39.286036 progress 75 % (143 MB)
113 05:55:39.356124 progress 80 % (153 MB)
114 05:55:39.423942 progress 85 % (162 MB)
115 05:55:39.523654 progress 90 % (172 MB)
116 05:55:39.798572 progress 95 % (181 MB)
117 05:55:40.365246 progress 100 % (191 MB)
118 05:55:40.370478 191 MB downloaded in 7.90 s (24.23 MB/s)
119 05:55:40.370745 end: 1.4.1 http-download (duration 00:00:08) [common]
121 05:55:40.371009 end: 1.4 download-retry (duration 00:00:08) [common]
122 05:55:40.371098 start: 1.5 download-retry (timeout 00:09:52) [common]
123 05:55:40.371185 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 05:55:40.371346 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 05:55:40.371416 saving as /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/modules/modules.tar
126 05:55:40.371478 total size: 8619328 (8 MB)
127 05:55:40.371542 Using unxz to decompress xz
128 05:55:40.375607 progress 0 % (0 MB)
129 05:55:40.396310 progress 5 % (0 MB)
130 05:55:40.419656 progress 10 % (0 MB)
131 05:55:40.442817 progress 15 % (1 MB)
132 05:55:40.465723 progress 20 % (1 MB)
133 05:55:40.489375 progress 25 % (2 MB)
134 05:55:40.514734 progress 30 % (2 MB)
135 05:55:40.540501 progress 35 % (2 MB)
136 05:55:40.563684 progress 40 % (3 MB)
137 05:55:40.587830 progress 45 % (3 MB)
138 05:55:40.612601 progress 50 % (4 MB)
139 05:55:40.636363 progress 55 % (4 MB)
140 05:55:40.660675 progress 60 % (4 MB)
141 05:55:40.685903 progress 65 % (5 MB)
142 05:55:40.712699 progress 70 % (5 MB)
143 05:55:40.736388 progress 75 % (6 MB)
144 05:55:40.763547 progress 80 % (6 MB)
145 05:55:40.788942 progress 85 % (7 MB)
146 05:55:40.813561 progress 90 % (7 MB)
147 05:55:40.842821 progress 95 % (7 MB)
148 05:55:40.872353 progress 100 % (8 MB)
149 05:55:40.876930 8 MB downloaded in 0.51 s (16.26 MB/s)
150 05:55:40.877186 end: 1.5.1 http-download (duration 00:00:01) [common]
152 05:55:40.877453 end: 1.5 download-retry (duration 00:00:01) [common]
153 05:55:40.877585 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 05:55:40.877686 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 05:55:44.350939 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12379453/extract-nfsrootfs-4j3s6mu7
156 05:55:44.351126 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 05:55:44.351234 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 05:55:44.351403 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud
159 05:55:44.351535 makedir: /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin
160 05:55:44.351635 makedir: /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/tests
161 05:55:44.351732 makedir: /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/results
162 05:55:44.351832 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-add-keys
163 05:55:44.351976 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-add-sources
164 05:55:44.352109 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-background-process-start
165 05:55:44.352253 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-background-process-stop
166 05:55:44.352379 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-common-functions
167 05:55:44.352502 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-echo-ipv4
168 05:55:44.352624 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-install-packages
169 05:55:44.352746 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-installed-packages
170 05:55:44.352866 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-os-build
171 05:55:44.352992 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-probe-channel
172 05:55:44.353116 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-probe-ip
173 05:55:44.353255 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-target-ip
174 05:55:44.353380 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-target-mac
175 05:55:44.353511 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-target-storage
176 05:55:44.353638 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-test-case
177 05:55:44.353763 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-test-event
178 05:55:44.353887 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-test-feedback
179 05:55:44.354010 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-test-raise
180 05:55:44.354132 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-test-reference
181 05:55:44.354255 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-test-runner
182 05:55:44.354376 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-test-set
183 05:55:44.354498 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-test-shell
184 05:55:44.354622 Updating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-add-keys (debian)
185 05:55:44.354767 Updating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-add-sources (debian)
186 05:55:44.354926 Updating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-install-packages (debian)
187 05:55:44.355069 Updating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-installed-packages (debian)
188 05:55:44.355229 Updating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/bin/lava-os-build (debian)
189 05:55:44.355363 Creating /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/environment
190 05:55:44.355485 LAVA metadata
191 05:55:44.355582 - LAVA_JOB_ID=12379453
192 05:55:44.355681 - LAVA_DISPATCHER_IP=192.168.201.1
193 05:55:44.355820 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 05:55:44.355912 skipped lava-vland-overlay
195 05:55:44.356017 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 05:55:44.356098 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 05:55:44.356186 skipped lava-multinode-overlay
198 05:55:44.356287 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 05:55:44.356386 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 05:55:44.356462 Loading test definitions
201 05:55:44.356553 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 05:55:44.356623 Using /lava-12379453 at stage 0
203 05:55:44.356918 uuid=12379453_1.6.2.3.1 testdef=None
204 05:55:44.357012 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 05:55:44.357100 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 05:55:44.357764 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 05:55:44.358002 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 05:55:44.358804 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 05:55:44.359169 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 05:55:44.360148 runner path: /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/0/tests/0_timesync-off test_uuid 12379453_1.6.2.3.1
213 05:55:44.360345 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 05:55:44.360720 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 05:55:44.360814 Using /lava-12379453 at stage 0
217 05:55:44.360964 Fetching tests from https://github.com/kernelci/test-definitions.git
218 05:55:44.361069 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/0/tests/1_kselftest-dt'
219 05:55:48.348842 Running '/usr/bin/git checkout kernelci.org
220 05:55:48.496573 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 05:55:48.497306 uuid=12379453_1.6.2.3.5 testdef=None
222 05:55:48.497467 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 05:55:48.497731 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 05:55:48.498491 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 05:55:48.498724 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 05:55:48.499709 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 05:55:48.499945 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 05:55:48.500872 runner path: /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/0/tests/1_kselftest-dt test_uuid 12379453_1.6.2.3.5
232 05:55:48.500962 BOARD='mt8192-asurada-spherion-r0'
233 05:55:48.501027 BRANCH='cip'
234 05:55:48.501087 SKIPFILE='/dev/null'
235 05:55:48.501145 SKIP_INSTALL='True'
236 05:55:48.501200 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 05:55:48.501260 TST_CASENAME=''
238 05:55:48.501315 TST_CMDFILES='dt'
239 05:55:48.501459 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 05:55:48.501674 Creating lava-test-runner.conf files
242 05:55:48.501738 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379453/lava-overlay-o1wt0oud/lava-12379453/0 for stage 0
243 05:55:48.501831 - 0_timesync-off
244 05:55:48.501901 - 1_kselftest-dt
245 05:55:48.502000 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 05:55:48.502087 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 05:55:56.043652 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 05:55:56.043806 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 05:55:56.043900 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 05:55:56.044000 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 05:55:56.044091 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 05:55:56.166434 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 05:55:56.166807 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 05:55:56.166929 extracting modules file /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379453/extract-nfsrootfs-4j3s6mu7
255 05:55:56.409950 extracting modules file /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379453/extract-overlay-ramdisk-7151qooq/ramdisk
256 05:55:56.646363 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 05:55:56.646525 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 05:55:56.646623 [common] Applying overlay to NFS
259 05:55:56.646697 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379453/compress-overlay-_k_xa9nl/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12379453/extract-nfsrootfs-4j3s6mu7
260 05:55:57.588045 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 05:55:57.588218 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 05:55:57.588322 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 05:55:57.588412 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 05:55:57.588497 Building ramdisk /var/lib/lava/dispatcher/tmp/12379453/extract-overlay-ramdisk-7151qooq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12379453/extract-overlay-ramdisk-7151qooq/ramdisk
265 05:55:57.888462 >> 119415 blocks
266 05:55:59.866140 rename /var/lib/lava/dispatcher/tmp/12379453/extract-overlay-ramdisk-7151qooq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/ramdisk/ramdisk.cpio.gz
267 05:55:59.866621 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 05:55:59.866771 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 05:55:59.866918 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 05:55:59.867071 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/kernel/Image'
271 05:56:12.354622 Returned 0 in 12 seconds
272 05:56:12.455256 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/kernel/image.itb
273 05:56:12.812274 output: FIT description: Kernel Image image with one or more FDT blobs
274 05:56:12.812647 output: Created: Mon Dec 25 05:56:12 2023
275 05:56:12.812724 output: Image 0 (kernel-1)
276 05:56:12.812791 output: Description:
277 05:56:12.812857 output: Created: Mon Dec 25 05:56:12 2023
278 05:56:12.812919 output: Type: Kernel Image
279 05:56:12.812981 output: Compression: lzma compressed
280 05:56:12.813039 output: Data Size: 11481830 Bytes = 11212.72 KiB = 10.95 MiB
281 05:56:12.813097 output: Architecture: AArch64
282 05:56:12.813154 output: OS: Linux
283 05:56:12.813209 output: Load Address: 0x00000000
284 05:56:12.813269 output: Entry Point: 0x00000000
285 05:56:12.813324 output: Hash algo: crc32
286 05:56:12.813377 output: Hash value: a47c00f1
287 05:56:12.813429 output: Image 1 (fdt-1)
288 05:56:12.813497 output: Description: mt8192-asurada-spherion-r0
289 05:56:12.813563 output: Created: Mon Dec 25 05:56:12 2023
290 05:56:12.813618 output: Type: Flat Device Tree
291 05:56:12.813671 output: Compression: uncompressed
292 05:56:12.813723 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 05:56:12.813777 output: Architecture: AArch64
294 05:56:12.813828 output: Hash algo: crc32
295 05:56:12.813880 output: Hash value: cc4352de
296 05:56:12.813932 output: Image 2 (ramdisk-1)
297 05:56:12.813984 output: Description: unavailable
298 05:56:12.814036 output: Created: Mon Dec 25 05:56:12 2023
299 05:56:12.814088 output: Type: RAMDisk Image
300 05:56:12.814141 output: Compression: Unknown Compression
301 05:56:12.814193 output: Data Size: 17798995 Bytes = 17381.83 KiB = 16.97 MiB
302 05:56:12.814245 output: Architecture: AArch64
303 05:56:12.814297 output: OS: Linux
304 05:56:12.814349 output: Load Address: unavailable
305 05:56:12.814400 output: Entry Point: unavailable
306 05:56:12.814452 output: Hash algo: crc32
307 05:56:12.814503 output: Hash value: 796e476a
308 05:56:12.814555 output: Default Configuration: 'conf-1'
309 05:56:12.814606 output: Configuration 0 (conf-1)
310 05:56:12.814658 output: Description: mt8192-asurada-spherion-r0
311 05:56:12.814709 output: Kernel: kernel-1
312 05:56:12.814761 output: Init Ramdisk: ramdisk-1
313 05:56:12.814813 output: FDT: fdt-1
314 05:56:12.814864 output: Loadables: kernel-1
315 05:56:12.814916 output:
316 05:56:12.815121 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 05:56:12.815220 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 05:56:12.815325 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 05:56:12.815415 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 05:56:12.815495 No LXC device requested
321 05:56:12.815572 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 05:56:12.815653 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 05:56:12.815728 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 05:56:12.815794 Checking files for TFTP limit of 4294967296 bytes.
325 05:56:12.816299 end: 1 tftp-deploy (duration 00:00:41) [common]
326 05:56:12.816400 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 05:56:12.816491 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 05:56:12.816625 substitutions:
329 05:56:12.816694 - {DTB}: 12379453/tftp-deploy-ry1yvk2f/dtb/mt8192-asurada-spherion-r0.dtb
330 05:56:12.816757 - {INITRD}: 12379453/tftp-deploy-ry1yvk2f/ramdisk/ramdisk.cpio.gz
331 05:56:12.816816 - {KERNEL}: 12379453/tftp-deploy-ry1yvk2f/kernel/Image
332 05:56:12.816873 - {LAVA_MAC}: None
333 05:56:12.816929 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12379453/extract-nfsrootfs-4j3s6mu7
334 05:56:12.816985 - {NFS_SERVER_IP}: 192.168.201.1
335 05:56:12.817039 - {PRESEED_CONFIG}: None
336 05:56:12.817093 - {PRESEED_LOCAL}: None
337 05:56:12.817147 - {RAMDISK}: 12379453/tftp-deploy-ry1yvk2f/ramdisk/ramdisk.cpio.gz
338 05:56:12.817200 - {ROOT_PART}: None
339 05:56:12.817252 - {ROOT}: None
340 05:56:12.817306 - {SERVER_IP}: 192.168.201.1
341 05:56:12.817358 - {TEE}: None
342 05:56:12.817412 Parsed boot commands:
343 05:56:12.817464 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 05:56:12.817652 Parsed boot commands: tftpboot 192.168.201.1 12379453/tftp-deploy-ry1yvk2f/kernel/image.itb 12379453/tftp-deploy-ry1yvk2f/kernel/cmdline
345 05:56:12.817740 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 05:56:12.817824 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 05:56:12.817914 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 05:56:12.817998 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 05:56:12.818073 Not connected, no need to disconnect.
350 05:56:12.818147 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 05:56:12.818225 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 05:56:12.818291 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 05:56:12.822157 Setting prompt string to ['lava-test: # ']
354 05:56:12.822524 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 05:56:12.822635 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 05:56:12.822739 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 05:56:12.822831 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 05:56:12.823057 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 05:56:17.955787 >> Command sent successfully.
360 05:56:17.958539 Returned 0 in 5 seconds
361 05:56:18.058953 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 05:56:18.059347 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 05:56:18.059478 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 05:56:18.059581 Setting prompt string to 'Starting depthcharge on Spherion...'
366 05:56:18.059659 Changing prompt to 'Starting depthcharge on Spherion...'
367 05:56:18.059747 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 05:56:18.060035 [Enter `^Ec?' for help]
369 05:56:18.229549
370 05:56:18.229716
371 05:56:18.229812 F0: 102B 0000
372 05:56:18.229882
373 05:56:18.229953 F3: 1001 0000 [0200]
374 05:56:18.230020
375 05:56:18.233403 F3: 1001 0000
376 05:56:18.233518
377 05:56:18.233593 F7: 102D 0000
378 05:56:18.233656
379 05:56:18.237282 F1: 0000 0000
380 05:56:18.237359
381 05:56:18.237432 V0: 0000 0000 [0001]
382 05:56:18.237507
383 05:56:18.237567 00: 0007 8000
384 05:56:18.237645
385 05:56:18.240677 01: 0000 0000
386 05:56:18.240754
387 05:56:18.240816 BP: 0C00 0209 [0000]
388 05:56:18.240874
389 05:56:18.243921 G0: 1182 0000
390 05:56:18.244032
391 05:56:18.244125 EC: 0000 0021 [4000]
392 05:56:18.244225
393 05:56:18.248087 S7: 0000 0000 [0000]
394 05:56:18.248198
395 05:56:18.248310 CC: 0000 0000 [0001]
396 05:56:18.248396
397 05:56:18.250964 T0: 0000 0040 [010F]
398 05:56:18.251043
399 05:56:18.251114 Jump to BL
400 05:56:18.251204
401 05:56:18.276791
402 05:56:18.276907
403 05:56:18.276975
404 05:56:18.283833 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 05:56:18.287811 ARM64: Exception handlers installed.
406 05:56:18.291551 ARM64: Testing exception
407 05:56:18.295066 ARM64: Done test exception
408 05:56:18.302311 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 05:56:18.309788 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 05:56:18.316883 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 05:56:18.327437 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 05:56:18.334049 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 05:56:18.344500 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 05:56:18.354622 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 05:56:18.361599 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 05:56:18.379634 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 05:56:18.382616 WDT: Last reset was cold boot
418 05:56:18.386054 SPI1(PAD0) initialized at 2873684 Hz
419 05:56:18.389458 SPI5(PAD0) initialized at 992727 Hz
420 05:56:18.392888 VBOOT: Loading verstage.
421 05:56:18.399163 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 05:56:18.402875 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 05:56:18.406005 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 05:56:18.409359 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 05:56:18.416893 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 05:56:18.423233 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 05:56:18.434468 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
428 05:56:18.434561
429 05:56:18.434658
430 05:56:18.444401 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 05:56:18.447237 ARM64: Exception handlers installed.
432 05:56:18.450804 ARM64: Testing exception
433 05:56:18.450889 ARM64: Done test exception
434 05:56:18.457800 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 05:56:18.461138 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 05:56:18.475558 Probing TPM: . done!
437 05:56:18.475655 TPM ready after 0 ms
438 05:56:18.482063 Connected to device vid:did:rid of 1ae0:0028:00
439 05:56:18.489337 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 05:56:18.529308 Initialized TPM device CR50 revision 0
441 05:56:18.540678 tlcl_send_startup: Startup return code is 0
442 05:56:18.540798 TPM: setup succeeded
443 05:56:18.552054 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 05:56:18.561079 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 05:56:18.572446 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 05:56:18.583835 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 05:56:18.587061 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 05:56:18.590981 in-header: 03 07 00 00 08 00 00 00
449 05:56:18.594409 in-data: aa e4 47 04 13 02 00 00
450 05:56:18.598506 Chrome EC: UHEPI supported
451 05:56:18.604773 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 05:56:18.608845 in-header: 03 9d 00 00 08 00 00 00
453 05:56:18.612952 in-data: 10 20 20 08 00 00 00 00
454 05:56:18.613037 Phase 1
455 05:56:18.616430 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 05:56:18.623363 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 05:56:18.630566 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 05:56:18.634215 Recovery requested (1009000e)
459 05:56:18.639938 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 05:56:18.645383 tlcl_extend: response is 0
461 05:56:18.655719 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 05:56:18.658880 tlcl_extend: response is 0
463 05:56:18.665775 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 05:56:18.686327 read SPI 0x210d4 0x2173b: 15144 us, 9047 KB/s, 72.376 Mbps
465 05:56:18.693745 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 05:56:18.693884
467 05:56:18.693950
468 05:56:18.701032 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 05:56:18.704512 ARM64: Exception handlers installed.
470 05:56:18.708495 ARM64: Testing exception
471 05:56:18.711753 ARM64: Done test exception
472 05:56:18.732013 pmic_efuse_setting: Set efuses in 11 msecs
473 05:56:18.735287 pmwrap_interface_init: Select PMIF_VLD_RDY
474 05:56:18.739162 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 05:56:18.746324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 05:56:18.750212 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 05:56:18.753949 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 05:56:18.761746 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 05:56:18.764994 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 05:56:18.768559 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 05:56:18.772926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 05:56:18.779494 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 05:56:18.782967 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 05:56:18.789257 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 05:56:18.793074 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 05:56:18.795949 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 05:56:18.803232 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 05:56:18.809594 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 05:56:18.816528 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 05:56:18.819509 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 05:56:18.826334 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 05:56:18.833716 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 05:56:18.837459 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 05:56:18.844856 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 05:56:18.848125 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 05:56:18.854915 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 05:56:18.858730 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 05:56:18.865413 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 05:56:18.872559 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 05:56:18.875622 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 05:56:18.882568 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 05:56:18.885496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 05:56:18.889428 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 05:56:18.896785 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 05:56:18.900769 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 05:56:18.904544 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 05:56:18.911695 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 05:56:18.915810 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 05:56:18.919322 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 05:56:18.926645 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 05:56:18.930110 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 05:56:18.933715 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 05:56:18.940030 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 05:56:18.943485 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 05:56:18.946854 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 05:56:18.953460 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 05:56:18.956790 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 05:56:18.959844 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 05:56:18.967072 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 05:56:18.969994 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 05:56:18.973400 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 05:56:18.979972 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 05:56:18.983371 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 05:56:18.986567 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 05:56:18.992939 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 05:56:19.003159 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 05:56:19.006412 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 05:56:19.016409 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 05:56:19.023235 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 05:56:19.030110 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 05:56:19.033003 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 05:56:19.036334 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 05:56:19.044305 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
534 05:56:19.050855 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 05:56:19.054258 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 05:56:19.057425 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 05:56:19.068698 [RTC]rtc_get_frequency_meter,154: input=15, output=794
538 05:56:19.072139 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 05:56:19.078466 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 05:56:19.082005 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 05:56:19.085386 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 05:56:19.088706 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 05:56:19.091880 ADC[4]: Raw value=897780 ID=7
544 05:56:19.095150 ADC[3]: Raw value=212700 ID=1
545 05:56:19.095227 RAM Code: 0x71
546 05:56:19.101728 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 05:56:19.105125 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 05:56:19.115838 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 05:56:19.122705 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 05:56:19.125691 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 05:56:19.129178 in-header: 03 07 00 00 08 00 00 00
552 05:56:19.132579 in-data: aa e4 47 04 13 02 00 00
553 05:56:19.136143 Chrome EC: UHEPI supported
554 05:56:19.139445 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 05:56:19.142987 in-header: 03 d5 00 00 08 00 00 00
556 05:56:19.147026 in-data: 98 20 60 08 00 00 00 00
557 05:56:19.150719 MRC: failed to locate region type 0.
558 05:56:19.157985 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 05:56:19.161282 DRAM-K: Running full calibration
560 05:56:19.168160 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 05:56:19.168260 header.status = 0x0
562 05:56:19.171303 header.version = 0x6 (expected: 0x6)
563 05:56:19.174669 header.size = 0xd00 (expected: 0xd00)
564 05:56:19.178658 header.flags = 0x0
565 05:56:19.182214 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 05:56:19.200876 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
567 05:56:19.207377 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 05:56:19.211113 dram_init: ddr_geometry: 2
569 05:56:19.211200 [EMI] MDL number = 2
570 05:56:19.214130 [EMI] Get MDL freq = 0
571 05:56:19.217546 dram_init: ddr_type: 0
572 05:56:19.217636 is_discrete_lpddr4: 1
573 05:56:19.220720 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 05:56:19.220820
575 05:56:19.220919
576 05:56:19.224174 [Bian_co] ETT version 0.0.0.1
577 05:56:19.230584 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 05:56:19.230661
579 05:56:19.234005 dramc_set_vcore_voltage set vcore to 650000
580 05:56:19.234092 Read voltage for 800, 4
581 05:56:19.237135 Vio18 = 0
582 05:56:19.237211 Vcore = 650000
583 05:56:19.237287 Vdram = 0
584 05:56:19.240804 Vddq = 0
585 05:56:19.240882 Vmddr = 0
586 05:56:19.244251 dram_init: config_dvfs: 1
587 05:56:19.247674 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 05:56:19.254235 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 05:56:19.257551 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 05:56:19.260890 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 05:56:19.264290 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 05:56:19.267544 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 05:56:19.270499 MEM_TYPE=3, freq_sel=18
594 05:56:19.274009 sv_algorithm_assistance_LP4_1600
595 05:56:19.277125 ============ PULL DRAM RESETB DOWN ============
596 05:56:19.280547 ========== PULL DRAM RESETB DOWN end =========
597 05:56:19.287158 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 05:56:19.290693 ===================================
599 05:56:19.294028 LPDDR4 DRAM CONFIGURATION
600 05:56:19.294116 ===================================
601 05:56:19.297184 EX_ROW_EN[0] = 0x0
602 05:56:19.300684 EX_ROW_EN[1] = 0x0
603 05:56:19.300799 LP4Y_EN = 0x0
604 05:56:19.304569 WORK_FSP = 0x0
605 05:56:19.304724 WL = 0x2
606 05:56:19.308030 RL = 0x2
607 05:56:19.308124 BL = 0x2
608 05:56:19.311955 RPST = 0x0
609 05:56:19.312042 RD_PRE = 0x0
610 05:56:19.312109 WR_PRE = 0x1
611 05:56:19.315315 WR_PST = 0x0
612 05:56:19.315399 DBI_WR = 0x0
613 05:56:19.319074 DBI_RD = 0x0
614 05:56:19.319189 OTF = 0x1
615 05:56:19.323217 ===================================
616 05:56:19.326664 ===================================
617 05:56:19.326771 ANA top config
618 05:56:19.330693 ===================================
619 05:56:19.334216 DLL_ASYNC_EN = 0
620 05:56:19.338064 ALL_SLAVE_EN = 1
621 05:56:19.338187 NEW_RANK_MODE = 1
622 05:56:19.341257 DLL_IDLE_MODE = 1
623 05:56:19.345050 LP45_APHY_COMB_EN = 1
624 05:56:19.348808 TX_ODT_DIS = 1
625 05:56:19.348909 NEW_8X_MODE = 1
626 05:56:19.352625 ===================================
627 05:56:19.356038 ===================================
628 05:56:19.359701 data_rate = 1600
629 05:56:19.363661 CKR = 1
630 05:56:19.363791 DQ_P2S_RATIO = 8
631 05:56:19.367493 ===================================
632 05:56:19.370918 CA_P2S_RATIO = 8
633 05:56:19.374894 DQ_CA_OPEN = 0
634 05:56:19.374978 DQ_SEMI_OPEN = 0
635 05:56:19.378801 CA_SEMI_OPEN = 0
636 05:56:19.382349 CA_FULL_RATE = 0
637 05:56:19.385644 DQ_CKDIV4_EN = 1
638 05:56:19.385770 CA_CKDIV4_EN = 1
639 05:56:19.389672 CA_PREDIV_EN = 0
640 05:56:19.392598 PH8_DLY = 0
641 05:56:19.396117 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 05:56:19.399555 DQ_AAMCK_DIV = 4
643 05:56:19.399639 CA_AAMCK_DIV = 4
644 05:56:19.402737 CA_ADMCK_DIV = 4
645 05:56:19.406235 DQ_TRACK_CA_EN = 0
646 05:56:19.409257 CA_PICK = 800
647 05:56:19.412850 CA_MCKIO = 800
648 05:56:19.415813 MCKIO_SEMI = 0
649 05:56:19.419582 PLL_FREQ = 3068
650 05:56:19.422940 DQ_UI_PI_RATIO = 32
651 05:56:19.423023 CA_UI_PI_RATIO = 0
652 05:56:19.426212 ===================================
653 05:56:19.429254 ===================================
654 05:56:19.432847 memory_type:LPDDR4
655 05:56:19.436054 GP_NUM : 10
656 05:56:19.436137 SRAM_EN : 1
657 05:56:19.439506 MD32_EN : 0
658 05:56:19.443065 ===================================
659 05:56:19.445756 [ANA_INIT] >>>>>>>>>>>>>>
660 05:56:19.445839 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 05:56:19.449627 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 05:56:19.452838 ===================================
663 05:56:19.456301 data_rate = 1600,PCW = 0X7600
664 05:56:19.459684 ===================================
665 05:56:19.462659 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 05:56:19.469254 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 05:56:19.476159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 05:56:19.479624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 05:56:19.482863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 05:56:19.486237 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 05:56:19.489704 [ANA_INIT] flow start
672 05:56:19.489803 [ANA_INIT] PLL >>>>>>>>
673 05:56:19.493123 [ANA_INIT] PLL <<<<<<<<
674 05:56:19.496676 [ANA_INIT] MIDPI >>>>>>>>
675 05:56:19.496811 [ANA_INIT] MIDPI <<<<<<<<
676 05:56:19.500729 [ANA_INIT] DLL >>>>>>>>
677 05:56:19.500853 [ANA_INIT] flow end
678 05:56:19.504157 ============ LP4 DIFF to SE enter ============
679 05:56:19.511854 ============ LP4 DIFF to SE exit ============
680 05:56:19.511989 [ANA_INIT] <<<<<<<<<<<<<
681 05:56:19.515819 [Flow] Enable top DCM control >>>>>
682 05:56:19.519293 [Flow] Enable top DCM control <<<<<
683 05:56:19.523175 Enable DLL master slave shuffle
684 05:56:19.526649 ==============================================================
685 05:56:19.529958 Gating Mode config
686 05:56:19.533392 ==============================================================
687 05:56:19.536693 Config description:
688 05:56:19.547134 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 05:56:19.553690 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 05:56:19.557009 SELPH_MODE 0: By rank 1: By Phase
691 05:56:19.563429 ==============================================================
692 05:56:19.566599 GAT_TRACK_EN = 1
693 05:56:19.570112 RX_GATING_MODE = 2
694 05:56:19.573246 RX_GATING_TRACK_MODE = 2
695 05:56:19.576551 SELPH_MODE = 1
696 05:56:19.576667 PICG_EARLY_EN = 1
697 05:56:19.579797 VALID_LAT_VALUE = 1
698 05:56:19.586561 ==============================================================
699 05:56:19.590113 Enter into Gating configuration >>>>
700 05:56:19.593399 Exit from Gating configuration <<<<
701 05:56:19.596620 Enter into DVFS_PRE_config >>>>>
702 05:56:19.606541 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 05:56:19.609808 Exit from DVFS_PRE_config <<<<<
704 05:56:19.613137 Enter into PICG configuration >>>>
705 05:56:19.616534 Exit from PICG configuration <<<<
706 05:56:19.619827 [RX_INPUT] configuration >>>>>
707 05:56:19.623406 [RX_INPUT] configuration <<<<<
708 05:56:19.626748 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 05:56:19.633371 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 05:56:19.639814 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 05:56:19.646458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 05:56:19.653361 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 05:56:19.656542 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 05:56:19.663376 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 05:56:19.666673 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 05:56:19.670154 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 05:56:19.673041 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 05:56:19.676400 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 05:56:19.683172 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 05:56:19.686681 ===================================
721 05:56:19.689807 LPDDR4 DRAM CONFIGURATION
722 05:56:19.692993 ===================================
723 05:56:19.693084 EX_ROW_EN[0] = 0x0
724 05:56:19.696607 EX_ROW_EN[1] = 0x0
725 05:56:19.696694 LP4Y_EN = 0x0
726 05:56:19.699863 WORK_FSP = 0x0
727 05:56:19.699948 WL = 0x2
728 05:56:19.703562 RL = 0x2
729 05:56:19.703648 BL = 0x2
730 05:56:19.706239 RPST = 0x0
731 05:56:19.706324 RD_PRE = 0x0
732 05:56:19.709955 WR_PRE = 0x1
733 05:56:19.710041 WR_PST = 0x0
734 05:56:19.712951 DBI_WR = 0x0
735 05:56:19.713038 DBI_RD = 0x0
736 05:56:19.716199 OTF = 0x1
737 05:56:19.719599 ===================================
738 05:56:19.723415 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 05:56:19.726251 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 05:56:19.732962 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 05:56:19.736191 ===================================
742 05:56:19.736283 LPDDR4 DRAM CONFIGURATION
743 05:56:19.740147 ===================================
744 05:56:19.742898 EX_ROW_EN[0] = 0x10
745 05:56:19.746362 EX_ROW_EN[1] = 0x0
746 05:56:19.746463 LP4Y_EN = 0x0
747 05:56:19.749827 WORK_FSP = 0x0
748 05:56:19.749913 WL = 0x2
749 05:56:19.752989 RL = 0x2
750 05:56:19.753077 BL = 0x2
751 05:56:19.756258 RPST = 0x0
752 05:56:19.756352 RD_PRE = 0x0
753 05:56:19.759753 WR_PRE = 0x1
754 05:56:19.759872 WR_PST = 0x0
755 05:56:19.762827 DBI_WR = 0x0
756 05:56:19.762928 DBI_RD = 0x0
757 05:56:19.766343 OTF = 0x1
758 05:56:19.769654 ===================================
759 05:56:19.776032 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 05:56:19.779420 nWR fixed to 40
761 05:56:19.779515 [ModeRegInit_LP4] CH0 RK0
762 05:56:19.782963 [ModeRegInit_LP4] CH0 RK1
763 05:56:19.786343 [ModeRegInit_LP4] CH1 RK0
764 05:56:19.789714 [ModeRegInit_LP4] CH1 RK1
765 05:56:19.789814 match AC timing 13
766 05:56:19.793071 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 05:56:19.797019 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 05:56:19.803983 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 05:56:19.807452 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 05:56:19.810779 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 05:56:19.814262 [EMI DOE] emi_dcm 0
772 05:56:19.817998 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 05:56:19.818094 ==
774 05:56:19.821754 Dram Type= 6, Freq= 0, CH_0, rank 0
775 05:56:19.825368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 05:56:19.825464 ==
777 05:56:19.832518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 05:56:19.836088 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 05:56:19.847099 [CA 0] Center 38 (7~69) winsize 63
780 05:56:19.850646 [CA 1] Center 37 (7~68) winsize 62
781 05:56:19.854063 [CA 2] Center 35 (5~66) winsize 62
782 05:56:19.858059 [CA 3] Center 35 (5~66) winsize 62
783 05:56:19.861621 [CA 4] Center 34 (4~65) winsize 62
784 05:56:19.864777 [CA 5] Center 34 (3~65) winsize 63
785 05:56:19.864891
786 05:56:19.869056 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 05:56:19.869160
788 05:56:19.872379 [CATrainingPosCal] consider 1 rank data
789 05:56:19.872468 u2DelayCellTimex100 = 270/100 ps
790 05:56:19.876512 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 05:56:19.879887 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 05:56:19.887460 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 05:56:19.887581 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 05:56:19.891426 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 05:56:19.894749 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
796 05:56:19.894876
797 05:56:19.898541 CA PerBit enable=1, Macro0, CA PI delay=34
798 05:56:19.898660
799 05:56:19.902605 [CBTSetCACLKResult] CA Dly = 34
800 05:56:19.905895 CS Dly: 6 (0~37)
801 05:56:19.905994 ==
802 05:56:19.909399 Dram Type= 6, Freq= 0, CH_0, rank 1
803 05:56:19.913547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 05:56:19.913640 ==
805 05:56:19.917488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 05:56:19.924461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 05:56:19.933078 [CA 0] Center 38 (7~69) winsize 63
808 05:56:19.936819 [CA 1] Center 38 (7~69) winsize 63
809 05:56:19.940776 [CA 2] Center 35 (5~66) winsize 62
810 05:56:19.944336 [CA 3] Center 35 (5~66) winsize 62
811 05:56:19.948809 [CA 4] Center 34 (4~65) winsize 62
812 05:56:19.948926 [CA 5] Center 34 (4~65) winsize 62
813 05:56:19.949020
814 05:56:19.952276 [CmdBusTrainingLP45] Vref(ca) range 1: 34
815 05:56:19.952384
816 05:56:19.956184 [CATrainingPosCal] consider 2 rank data
817 05:56:19.959389 u2DelayCellTimex100 = 270/100 ps
818 05:56:19.963274 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 05:56:19.966958 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 05:56:19.970690 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 05:56:19.974718 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 05:56:19.977854 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 05:56:19.982046 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 05:56:19.982173
825 05:56:19.985289 CA PerBit enable=1, Macro0, CA PI delay=34
826 05:56:19.985399
827 05:56:19.989173 [CBTSetCACLKResult] CA Dly = 34
828 05:56:19.992796 CS Dly: 6 (0~38)
829 05:56:19.992893
830 05:56:19.992961 ----->DramcWriteLeveling(PI) begin...
831 05:56:19.996832 ==
832 05:56:19.996946 Dram Type= 6, Freq= 0, CH_0, rank 0
833 05:56:20.000677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 05:56:20.004452 ==
835 05:56:20.004572 Write leveling (Byte 0): 31 => 31
836 05:56:20.007811 Write leveling (Byte 1): 29 => 29
837 05:56:20.011996 DramcWriteLeveling(PI) end<-----
838 05:56:20.012114
839 05:56:20.012210 ==
840 05:56:20.015492 Dram Type= 6, Freq= 0, CH_0, rank 0
841 05:56:20.019442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 05:56:20.019568 ==
843 05:56:20.023089 [Gating] SW mode calibration
844 05:56:20.030625 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 05:56:20.033907 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 05:56:20.037552 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 05:56:20.044999 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 05:56:20.048704 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
849 05:56:20.052171 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 05:56:20.056086 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 05:56:20.060004 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 05:56:20.063249 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 05:56:20.071049 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 05:56:20.074263 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 05:56:20.078268 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 05:56:20.081719 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 05:56:20.085249 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 05:56:20.093142 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 05:56:20.096505 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 05:56:20.100354 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 05:56:20.104393 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 05:56:20.108123 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 05:56:20.115068 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 05:56:20.118525 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
865 05:56:20.122050 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
866 05:56:20.125362 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 05:56:20.132372 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 05:56:20.135297 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 05:56:20.138549 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 05:56:20.145444 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 05:56:20.148915 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 05:56:20.152340 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
873 05:56:20.158524 0 9 12 | B1->B0 | 2525 3131 | 0 1 | (0 0) (0 0)
874 05:56:20.162083 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 05:56:20.165595 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 05:56:20.172404 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 05:56:20.175768 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 05:56:20.178712 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 05:56:20.182032 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 05:56:20.188603 0 10 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
881 05:56:20.192267 0 10 12 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
882 05:56:20.195183 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 05:56:20.201794 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 05:56:20.205462 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 05:56:20.208495 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 05:56:20.215396 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 05:56:20.218271 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 05:56:20.222021 0 11 8 | B1->B0 | 2929 3030 | 0 0 | (0 0) (0 0)
889 05:56:20.228295 0 11 12 | B1->B0 | 3737 4141 | 0 0 | (0 0) (0 0)
890 05:56:20.231799 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 05:56:20.235320 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 05:56:20.241646 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 05:56:20.245057 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 05:56:20.248441 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 05:56:20.255096 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 05:56:20.258253 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
897 05:56:20.261716 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
898 05:56:20.268604 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 05:56:20.272097 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 05:56:20.274917 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 05:56:20.281924 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 05:56:20.285219 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 05:56:20.288280 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 05:56:20.295149 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 05:56:20.298372 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 05:56:20.301825 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 05:56:20.308287 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 05:56:20.311986 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 05:56:20.314759 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 05:56:20.318182 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 05:56:20.324742 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 05:56:20.328295 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 05:56:20.331540 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
914 05:56:20.338394 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
915 05:56:20.341839 Total UI for P1: 0, mck2ui 16
916 05:56:20.344722 best dqsien dly found for B0: ( 0, 14, 12)
917 05:56:20.344846 Total UI for P1: 0, mck2ui 16
918 05:56:20.351613 best dqsien dly found for B1: ( 0, 14, 12)
919 05:56:20.355078 best DQS0 dly(MCK, UI, PI) = (0, 14, 12)
920 05:56:20.358548 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
921 05:56:20.358662
922 05:56:20.361767 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 12)
923 05:56:20.364770 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
924 05:56:20.368207 [Gating] SW calibration Done
925 05:56:20.368323 ==
926 05:56:20.371555 Dram Type= 6, Freq= 0, CH_0, rank 0
927 05:56:20.374974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 05:56:20.375067 ==
929 05:56:20.378206 RX Vref Scan: 0
930 05:56:20.378292
931 05:56:20.378359 RX Vref 0 -> 0, step: 1
932 05:56:20.381813
933 05:56:20.381900 RX Delay -130 -> 252, step: 16
934 05:56:20.388115 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
935 05:56:20.391549 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
936 05:56:20.394942 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
937 05:56:20.398039 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
938 05:56:20.401250 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
939 05:56:20.408040 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
940 05:56:20.411472 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
941 05:56:20.415092 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
942 05:56:20.418263 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
943 05:56:20.421422 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
944 05:56:20.428434 iDelay=222, Bit 10, Center 61 (-66 ~ 189) 256
945 05:56:20.431731 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
946 05:56:20.434720 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
947 05:56:20.437951 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
948 05:56:20.441696 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
949 05:56:20.448267 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
950 05:56:20.448386 ==
951 05:56:20.451483 Dram Type= 6, Freq= 0, CH_0, rank 0
952 05:56:20.454650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 05:56:20.454745 ==
954 05:56:20.454813 DQS Delay:
955 05:56:20.457878 DQS0 = 0, DQS1 = 0
956 05:56:20.457990 DQM Delay:
957 05:56:20.461344 DQM0 = 82, DQM1 = 68
958 05:56:20.461459 DQ Delay:
959 05:56:20.465107 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
960 05:56:20.467792 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
961 05:56:20.471335 DQ8 =61, DQ9 =53, DQ10 =61, DQ11 =61
962 05:56:20.474904 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 05:56:20.474998
964 05:56:20.475065
965 05:56:20.475125 ==
966 05:56:20.478220 Dram Type= 6, Freq= 0, CH_0, rank 0
967 05:56:20.482387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 05:56:20.482488 ==
969 05:56:20.482555
970 05:56:20.482616
971 05:56:20.485064 TX Vref Scan disable
972 05:56:20.488524 == TX Byte 0 ==
973 05:56:20.491988 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
974 05:56:20.495387 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
975 05:56:20.498977 == TX Byte 1 ==
976 05:56:20.502168 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
977 05:56:20.505333 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
978 05:56:20.505421 ==
979 05:56:20.508852 Dram Type= 6, Freq= 0, CH_0, rank 0
980 05:56:20.512229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 05:56:20.512321 ==
982 05:56:20.526318 TX Vref=22, minBit 3, minWin=26, winSum=431
983 05:56:20.529654 TX Vref=24, minBit 5, minWin=26, winSum=438
984 05:56:20.533048 TX Vref=26, minBit 4, minWin=27, winSum=441
985 05:56:20.536491 TX Vref=28, minBit 0, minWin=27, winSum=443
986 05:56:20.539844 TX Vref=30, minBit 2, minWin=27, winSum=444
987 05:56:20.543445 TX Vref=32, minBit 1, minWin=27, winSum=439
988 05:56:20.549621 [TxChooseVref] Worse bit 2, Min win 27, Win sum 444, Final Vref 30
989 05:56:20.549731
990 05:56:20.553189 Final TX Range 1 Vref 30
991 05:56:20.553282
992 05:56:20.553350 ==
993 05:56:20.556365 Dram Type= 6, Freq= 0, CH_0, rank 0
994 05:56:20.559907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 05:56:20.560005 ==
996 05:56:20.560071
997 05:56:20.560139
998 05:56:20.563147 TX Vref Scan disable
999 05:56:20.566345 == TX Byte 0 ==
1000 05:56:20.570041 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1001 05:56:20.573187 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1002 05:56:20.576615 == TX Byte 1 ==
1003 05:56:20.579847 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1004 05:56:20.583253 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1005 05:56:20.583381
1006 05:56:20.586372 [DATLAT]
1007 05:56:20.586459 Freq=800, CH0 RK0
1008 05:56:20.586529
1009 05:56:20.589681 DATLAT Default: 0xa
1010 05:56:20.589780 0, 0xFFFF, sum = 0
1011 05:56:20.593114 1, 0xFFFF, sum = 0
1012 05:56:20.593209 2, 0xFFFF, sum = 0
1013 05:56:20.596582 3, 0xFFFF, sum = 0
1014 05:56:20.596694 4, 0xFFFF, sum = 0
1015 05:56:20.600115 5, 0xFFFF, sum = 0
1016 05:56:20.600226 6, 0xFFFF, sum = 0
1017 05:56:20.602996 7, 0xFFFF, sum = 0
1018 05:56:20.603081 8, 0xFFFF, sum = 0
1019 05:56:20.606387 9, 0x0, sum = 1
1020 05:56:20.606536 10, 0x0, sum = 2
1021 05:56:20.609745 11, 0x0, sum = 3
1022 05:56:20.609834 12, 0x0, sum = 4
1023 05:56:20.613351 best_step = 10
1024 05:56:20.613438
1025 05:56:20.613555 ==
1026 05:56:20.616503 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 05:56:20.619999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 05:56:20.620118 ==
1029 05:56:20.623471 RX Vref Scan: 1
1030 05:56:20.623555
1031 05:56:20.623620 Set Vref Range= 32 -> 127
1032 05:56:20.623681
1033 05:56:20.626870 RX Vref 32 -> 127, step: 1
1034 05:56:20.626953
1035 05:56:20.629497 RX Delay -111 -> 252, step: 8
1036 05:56:20.629593
1037 05:56:20.632959 Set Vref, RX VrefLevel [Byte0]: 32
1038 05:56:20.636467 [Byte1]: 32
1039 05:56:20.636562
1040 05:56:20.640009 Set Vref, RX VrefLevel [Byte0]: 33
1041 05:56:20.643381 [Byte1]: 33
1042 05:56:20.646761
1043 05:56:20.646858 Set Vref, RX VrefLevel [Byte0]: 34
1044 05:56:20.650266 [Byte1]: 34
1045 05:56:20.654255
1046 05:56:20.654343 Set Vref, RX VrefLevel [Byte0]: 35
1047 05:56:20.657731 [Byte1]: 35
1048 05:56:20.662164
1049 05:56:20.662273 Set Vref, RX VrefLevel [Byte0]: 36
1050 05:56:20.665693 [Byte1]: 36
1051 05:56:20.669891
1052 05:56:20.670016 Set Vref, RX VrefLevel [Byte0]: 37
1053 05:56:20.672993 [Byte1]: 37
1054 05:56:20.677288
1055 05:56:20.677413 Set Vref, RX VrefLevel [Byte0]: 38
1056 05:56:20.684071 [Byte1]: 38
1057 05:56:20.684188
1058 05:56:20.687305 Set Vref, RX VrefLevel [Byte0]: 39
1059 05:56:20.690574 [Byte1]: 39
1060 05:56:20.690666
1061 05:56:20.693640 Set Vref, RX VrefLevel [Byte0]: 40
1062 05:56:20.697261 [Byte1]: 40
1063 05:56:20.700529
1064 05:56:20.700659 Set Vref, RX VrefLevel [Byte0]: 41
1065 05:56:20.704065 [Byte1]: 41
1066 05:56:20.708054
1067 05:56:20.708173 Set Vref, RX VrefLevel [Byte0]: 42
1068 05:56:20.715951 [Byte1]: 42
1069 05:56:20.716087
1070 05:56:20.716158 Set Vref, RX VrefLevel [Byte0]: 43
1071 05:56:20.719180 [Byte1]: 43
1072 05:56:20.723314
1073 05:56:20.723433 Set Vref, RX VrefLevel [Byte0]: 44
1074 05:56:20.726770 [Byte1]: 44
1075 05:56:20.731396
1076 05:56:20.731502 Set Vref, RX VrefLevel [Byte0]: 45
1077 05:56:20.734855 [Byte1]: 45
1078 05:56:20.739004
1079 05:56:20.739108 Set Vref, RX VrefLevel [Byte0]: 46
1080 05:56:20.742736 [Byte1]: 46
1081 05:56:20.747052
1082 05:56:20.747201 Set Vref, RX VrefLevel [Byte0]: 47
1083 05:56:20.749975 [Byte1]: 47
1084 05:56:20.754444
1085 05:56:20.754595 Set Vref, RX VrefLevel [Byte0]: 48
1086 05:56:20.757985 [Byte1]: 48
1087 05:56:20.762053
1088 05:56:20.762167 Set Vref, RX VrefLevel [Byte0]: 49
1089 05:56:20.764996 [Byte1]: 49
1090 05:56:20.768997
1091 05:56:20.769098 Set Vref, RX VrefLevel [Byte0]: 50
1092 05:56:20.772400 [Byte1]: 50
1093 05:56:20.776811
1094 05:56:20.776908 Set Vref, RX VrefLevel [Byte0]: 51
1095 05:56:20.779733 [Byte1]: 51
1096 05:56:20.784272
1097 05:56:20.784369 Set Vref, RX VrefLevel [Byte0]: 52
1098 05:56:20.787733 [Byte1]: 52
1099 05:56:20.791902
1100 05:56:20.792002 Set Vref, RX VrefLevel [Byte0]: 53
1101 05:56:20.795543 [Byte1]: 53
1102 05:56:20.799811
1103 05:56:20.799926 Set Vref, RX VrefLevel [Byte0]: 54
1104 05:56:20.803024 [Byte1]: 54
1105 05:56:20.807318
1106 05:56:20.807414 Set Vref, RX VrefLevel [Byte0]: 55
1107 05:56:20.811233 [Byte1]: 55
1108 05:56:20.814841
1109 05:56:20.814938 Set Vref, RX VrefLevel [Byte0]: 56
1110 05:56:20.818125 [Byte1]: 56
1111 05:56:20.822616
1112 05:56:20.822716 Set Vref, RX VrefLevel [Byte0]: 57
1113 05:56:20.825881 [Byte1]: 57
1114 05:56:20.830146
1115 05:56:20.830248 Set Vref, RX VrefLevel [Byte0]: 58
1116 05:56:20.833629 [Byte1]: 58
1117 05:56:20.838168
1118 05:56:20.838268 Set Vref, RX VrefLevel [Byte0]: 59
1119 05:56:20.841094 [Byte1]: 59
1120 05:56:20.845978
1121 05:56:20.846081 Set Vref, RX VrefLevel [Byte0]: 60
1122 05:56:20.848964 [Byte1]: 60
1123 05:56:20.853138
1124 05:56:20.853238 Set Vref, RX VrefLevel [Byte0]: 61
1125 05:56:20.856507 [Byte1]: 61
1126 05:56:20.861124
1127 05:56:20.861223 Set Vref, RX VrefLevel [Byte0]: 62
1128 05:56:20.863992 [Byte1]: 62
1129 05:56:20.868645
1130 05:56:20.868762 Set Vref, RX VrefLevel [Byte0]: 63
1131 05:56:20.872023 [Byte1]: 63
1132 05:56:20.876097
1133 05:56:20.876194 Set Vref, RX VrefLevel [Byte0]: 64
1134 05:56:20.879571 [Byte1]: 64
1135 05:56:20.883570
1136 05:56:20.883664 Set Vref, RX VrefLevel [Byte0]: 65
1137 05:56:20.887009 [Byte1]: 65
1138 05:56:20.891640
1139 05:56:20.891738 Set Vref, RX VrefLevel [Byte0]: 66
1140 05:56:20.894493 [Byte1]: 66
1141 05:56:20.899361
1142 05:56:20.899473 Set Vref, RX VrefLevel [Byte0]: 67
1143 05:56:20.902327 [Byte1]: 67
1144 05:56:20.906665
1145 05:56:20.906763 Set Vref, RX VrefLevel [Byte0]: 68
1146 05:56:20.909818 [Byte1]: 68
1147 05:56:20.914358
1148 05:56:20.914457 Set Vref, RX VrefLevel [Byte0]: 69
1149 05:56:20.917454 [Byte1]: 69
1150 05:56:20.921846
1151 05:56:20.921948 Set Vref, RX VrefLevel [Byte0]: 70
1152 05:56:20.925196 [Byte1]: 70
1153 05:56:20.929444
1154 05:56:20.929576 Set Vref, RX VrefLevel [Byte0]: 71
1155 05:56:20.933020 [Byte1]: 71
1156 05:56:20.937122
1157 05:56:20.937224 Set Vref, RX VrefLevel [Byte0]: 72
1158 05:56:20.940483 [Byte1]: 72
1159 05:56:20.945017
1160 05:56:20.947885 Set Vref, RX VrefLevel [Byte0]: 73
1161 05:56:20.951226 [Byte1]: 73
1162 05:56:20.951321
1163 05:56:20.954997 Set Vref, RX VrefLevel [Byte0]: 74
1164 05:56:20.957997 [Byte1]: 74
1165 05:56:20.958102
1166 05:56:20.961752 Set Vref, RX VrefLevel [Byte0]: 75
1167 05:56:20.964513 [Byte1]: 75
1168 05:56:20.964630
1169 05:56:20.968021 Set Vref, RX VrefLevel [Byte0]: 76
1170 05:56:20.971415 [Byte1]: 76
1171 05:56:20.975511
1172 05:56:20.975664 Set Vref, RX VrefLevel [Byte0]: 77
1173 05:56:20.979075 [Byte1]: 77
1174 05:56:20.983042
1175 05:56:20.983283 Set Vref, RX VrefLevel [Byte0]: 78
1176 05:56:20.986579 [Byte1]: 78
1177 05:56:20.990757
1178 05:56:20.990962 Set Vref, RX VrefLevel [Byte0]: 79
1179 05:56:20.994077 [Byte1]: 79
1180 05:56:20.998627
1181 05:56:20.998791 Final RX Vref Byte 0 = 59 to rank0
1182 05:56:21.001557 Final RX Vref Byte 1 = 62 to rank0
1183 05:56:21.004981 Final RX Vref Byte 0 = 59 to rank1
1184 05:56:21.008599 Final RX Vref Byte 1 = 62 to rank1==
1185 05:56:21.011899 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 05:56:21.018560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 05:56:21.018717 ==
1188 05:56:21.018853 DQS Delay:
1189 05:56:21.018949 DQS0 = 0, DQS1 = 0
1190 05:56:21.021975 DQM Delay:
1191 05:56:21.022090 DQM0 = 82, DQM1 = 68
1192 05:56:21.024917 DQ Delay:
1193 05:56:21.028313 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1194 05:56:21.028455 DQ4 =84, DQ5 =68, DQ6 =88, DQ7 =92
1195 05:56:21.032058 DQ8 =64, DQ9 =56, DQ10 =68, DQ11 =60
1196 05:56:21.035281 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1197 05:56:21.038263
1198 05:56:21.038390
1199 05:56:21.045415 [DQSOSCAuto] RK0, (LSB)MR18= 0x2524, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1200 05:56:21.048600 CH0 RK0: MR19=606, MR18=2524
1201 05:56:21.054927 CH0_RK0: MR19=0x606, MR18=0x2524, DQSOSC=400, MR23=63, INC=92, DEC=61
1202 05:56:21.055079
1203 05:56:21.058335 ----->DramcWriteLeveling(PI) begin...
1204 05:56:21.058461 ==
1205 05:56:21.061538 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 05:56:21.065187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 05:56:21.065323 ==
1208 05:56:21.068313 Write leveling (Byte 0): 31 => 31
1209 05:56:21.071692 Write leveling (Byte 1): 30 => 30
1210 05:56:21.075151 DramcWriteLeveling(PI) end<-----
1211 05:56:21.075285
1212 05:56:21.075387 ==
1213 05:56:21.078634 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 05:56:21.081993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 05:56:21.082117 ==
1216 05:56:21.085269 [Gating] SW mode calibration
1217 05:56:21.091648 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 05:56:21.098683 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 05:56:21.101542 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 05:56:21.104913 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 05:56:21.111974 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1222 05:56:21.115304 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 05:56:21.118913 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 05:56:21.124950 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 05:56:21.128310 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 05:56:21.131787 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 05:56:21.138388 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 05:56:21.141772 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 05:56:21.145063 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 05:56:21.148483 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 05:56:21.195878 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 05:56:21.196023 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 05:56:21.196318 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 05:56:21.196427 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 05:56:21.196540 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 05:56:21.196644 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1237 05:56:21.196763 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1238 05:56:21.196868 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 05:56:21.196973 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 05:56:21.197063 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 05:56:21.238809 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 05:56:21.238990 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 05:56:21.239394 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 05:56:21.239666 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 05:56:21.239735 0 9 8 | B1->B0 | 2323 2e2e | 1 0 | (0 0) (0 0)
1246 05:56:21.239837 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1247 05:56:21.239907 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 05:56:21.240029 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 05:56:21.240119 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 05:56:21.240237 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 05:56:21.243581 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 05:56:21.246732 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1253 05:56:21.250406 0 10 8 | B1->B0 | 2f2f 2828 | 0 0 | (1 0) (0 0)
1254 05:56:21.257077 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1255 05:56:21.259970 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 05:56:21.263840 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 05:56:21.270515 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 05:56:21.273577 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 05:56:21.277306 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 05:56:21.283368 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 05:56:21.287000 0 11 8 | B1->B0 | 3030 3a3a | 0 0 | (1 1) (0 0)
1262 05:56:21.290028 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1263 05:56:21.293921 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 05:56:21.300216 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 05:56:21.303589 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 05:56:21.306980 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 05:56:21.313958 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 05:56:21.317979 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1269 05:56:21.321984 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1270 05:56:21.325355 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1271 05:56:21.328677 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 05:56:21.335324 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 05:56:21.339488 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 05:56:21.343194 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 05:56:21.346103 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 05:56:21.353010 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 05:56:21.356036 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 05:56:21.359692 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 05:56:21.366086 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 05:56:21.369571 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 05:56:21.372889 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 05:56:21.379715 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 05:56:21.382929 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 05:56:21.386067 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1285 05:56:21.393194 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1286 05:56:21.393339 Total UI for P1: 0, mck2ui 16
1287 05:56:21.399659 best dqsien dly found for B0: ( 0, 14, 4)
1288 05:56:21.402524 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1289 05:56:21.405937 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 05:56:21.409176 Total UI for P1: 0, mck2ui 16
1291 05:56:21.412657 best dqsien dly found for B1: ( 0, 14, 10)
1292 05:56:21.416092 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1293 05:56:21.419523 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1294 05:56:21.419637
1295 05:56:21.426309 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1296 05:56:21.429234 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1297 05:56:21.429347 [Gating] SW calibration Done
1298 05:56:21.432563 ==
1299 05:56:21.432650 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 05:56:21.439199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 05:56:21.439330 ==
1302 05:56:21.439430 RX Vref Scan: 0
1303 05:56:21.439518
1304 05:56:21.442644 RX Vref 0 -> 0, step: 1
1305 05:56:21.442762
1306 05:56:21.445843 RX Delay -130 -> 252, step: 16
1307 05:56:21.449161 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1308 05:56:21.452741 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1309 05:56:21.459332 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1310 05:56:21.462353 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1311 05:56:21.466123 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1312 05:56:21.469222 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1313 05:56:21.472690 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1314 05:56:21.475936 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1315 05:56:21.482531 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1316 05:56:21.485940 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1317 05:56:21.489390 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1318 05:56:21.492635 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1319 05:56:21.499332 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1320 05:56:21.502331 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1321 05:56:21.505902 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1322 05:56:21.509411 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1323 05:56:21.509581 ==
1324 05:56:21.512807 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 05:56:21.515738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 05:56:21.519233 ==
1327 05:56:21.519354 DQS Delay:
1328 05:56:21.519424 DQS0 = 0, DQS1 = 0
1329 05:56:21.522511 DQM Delay:
1330 05:56:21.522628 DQM0 = 80, DQM1 = 69
1331 05:56:21.526251 DQ Delay:
1332 05:56:21.526398 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1333 05:56:21.529029 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
1334 05:56:21.532413 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1335 05:56:21.535789 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1336 05:56:21.535884
1337 05:56:21.538962
1338 05:56:21.539048 ==
1339 05:56:21.542386 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 05:56:21.545797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 05:56:21.545900 ==
1342 05:56:21.545969
1343 05:56:21.546057
1344 05:56:21.549178 TX Vref Scan disable
1345 05:56:21.549265 == TX Byte 0 ==
1346 05:56:21.555773 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1347 05:56:21.559175 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1348 05:56:21.559281 == TX Byte 1 ==
1349 05:56:21.565980 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1350 05:56:21.569379 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1351 05:56:21.569520 ==
1352 05:56:21.572638 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 05:56:21.575944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 05:56:21.576036 ==
1355 05:56:21.589036 TX Vref=22, minBit 0, minWin=27, winSum=435
1356 05:56:21.592303 TX Vref=24, minBit 0, minWin=27, winSum=438
1357 05:56:21.595694 TX Vref=26, minBit 1, minWin=27, winSum=442
1358 05:56:21.599071 TX Vref=28, minBit 1, minWin=27, winSum=441
1359 05:56:21.602556 TX Vref=30, minBit 8, minWin=27, winSum=444
1360 05:56:21.609289 TX Vref=32, minBit 14, minWin=26, winSum=442
1361 05:56:21.612320 [TxChooseVref] Worse bit 8, Min win 27, Win sum 444, Final Vref 30
1362 05:56:21.612421
1363 05:56:21.615830 Final TX Range 1 Vref 30
1364 05:56:21.615917
1365 05:56:21.615981 ==
1366 05:56:21.619272 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 05:56:21.622735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 05:56:21.622866 ==
1369 05:56:21.622932
1370 05:56:21.625627
1371 05:56:21.625710 TX Vref Scan disable
1372 05:56:21.628970 == TX Byte 0 ==
1373 05:56:21.632351 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1374 05:56:21.638855 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1375 05:56:21.638963 == TX Byte 1 ==
1376 05:56:21.642545 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1377 05:56:21.649250 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1378 05:56:21.649393
1379 05:56:21.649511 [DATLAT]
1380 05:56:21.649588 Freq=800, CH0 RK1
1381 05:56:21.649646
1382 05:56:21.652620 DATLAT Default: 0xa
1383 05:56:21.652705 0, 0xFFFF, sum = 0
1384 05:56:21.655904 1, 0xFFFF, sum = 0
1385 05:56:21.655989 2, 0xFFFF, sum = 0
1386 05:56:21.659364 3, 0xFFFF, sum = 0
1387 05:56:21.659453 4, 0xFFFF, sum = 0
1388 05:56:21.662251 5, 0xFFFF, sum = 0
1389 05:56:21.666120 6, 0xFFFF, sum = 0
1390 05:56:21.666218 7, 0xFFFF, sum = 0
1391 05:56:21.669394 8, 0xFFFF, sum = 0
1392 05:56:21.669540 9, 0x0, sum = 1
1393 05:56:21.669607 10, 0x0, sum = 2
1394 05:56:21.672261 11, 0x0, sum = 3
1395 05:56:21.672380 12, 0x0, sum = 4
1396 05:56:21.675874 best_step = 10
1397 05:56:21.675990
1398 05:56:21.676085 ==
1399 05:56:21.679340 Dram Type= 6, Freq= 0, CH_0, rank 1
1400 05:56:21.682419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 05:56:21.682534 ==
1402 05:56:21.685738 RX Vref Scan: 0
1403 05:56:21.685847
1404 05:56:21.685947 RX Vref 0 -> 0, step: 1
1405 05:56:21.686046
1406 05:56:21.689077 RX Delay -111 -> 252, step: 8
1407 05:56:21.695733 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1408 05:56:21.699279 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1409 05:56:21.702760 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1410 05:56:21.706007 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1411 05:56:21.709188 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1412 05:56:21.715632 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1413 05:56:21.719121 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1414 05:56:21.722545 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1415 05:56:21.725870 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1416 05:56:21.729446 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1417 05:56:21.736052 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1418 05:56:21.739368 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1419 05:56:21.742447 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1420 05:56:21.746340 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1421 05:56:21.749461 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1422 05:56:21.756118 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1423 05:56:21.756233 ==
1424 05:56:21.759417 Dram Type= 6, Freq= 0, CH_0, rank 1
1425 05:56:21.762457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 05:56:21.762570 ==
1427 05:56:21.762662 DQS Delay:
1428 05:56:21.765865 DQS0 = 0, DQS1 = 0
1429 05:56:21.765967 DQM Delay:
1430 05:56:21.769424 DQM0 = 80, DQM1 = 69
1431 05:56:21.769532 DQ Delay:
1432 05:56:21.772745 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =76
1433 05:56:21.775741 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =88
1434 05:56:21.779055 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1435 05:56:21.782457 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =76
1436 05:56:21.782550
1437 05:56:21.782613
1438 05:56:21.789301 [DQSOSCAuto] RK1, (LSB)MR18= 0x431e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1439 05:56:21.792447 CH0 RK1: MR19=606, MR18=431E
1440 05:56:21.798939 CH0_RK1: MR19=0x606, MR18=0x431E, DQSOSC=393, MR23=63, INC=95, DEC=63
1441 05:56:21.802319 [RxdqsGatingPostProcess] freq 800
1442 05:56:21.808903 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1443 05:56:21.812512 Pre-setting of DQS Precalculation
1444 05:56:21.815862 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1445 05:56:21.815959 ==
1446 05:56:21.819081 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 05:56:21.822685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 05:56:21.822787 ==
1449 05:56:21.829102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1450 05:56:21.835833 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1451 05:56:21.844145 [CA 0] Center 37 (7~67) winsize 61
1452 05:56:21.847874 [CA 1] Center 36 (6~67) winsize 62
1453 05:56:21.850726 [CA 2] Center 34 (5~64) winsize 60
1454 05:56:21.854416 [CA 3] Center 34 (4~64) winsize 61
1455 05:56:21.857350 [CA 4] Center 34 (4~65) winsize 62
1456 05:56:21.860768 [CA 5] Center 34 (4~64) winsize 61
1457 05:56:21.860866
1458 05:56:21.864159 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1459 05:56:21.864255
1460 05:56:21.867339 [CATrainingPosCal] consider 1 rank data
1461 05:56:21.870898 u2DelayCellTimex100 = 270/100 ps
1462 05:56:21.874110 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1463 05:56:21.877512 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 05:56:21.883966 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1465 05:56:21.887289 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1466 05:56:21.890770 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 05:56:21.893990 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1468 05:56:21.894100
1469 05:56:21.897745 CA PerBit enable=1, Macro0, CA PI delay=34
1470 05:56:21.897862
1471 05:56:21.901002 [CBTSetCACLKResult] CA Dly = 34
1472 05:56:21.901106 CS Dly: 5 (0~36)
1473 05:56:21.901200 ==
1474 05:56:21.904509 Dram Type= 6, Freq= 0, CH_1, rank 1
1475 05:56:21.910702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 05:56:21.910852 ==
1477 05:56:21.913898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1478 05:56:21.920426 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1479 05:56:21.930761 [CA 0] Center 37 (7~67) winsize 61
1480 05:56:21.933638 [CA 1] Center 36 (6~67) winsize 62
1481 05:56:21.937127 [CA 2] Center 34 (4~65) winsize 62
1482 05:56:21.940640 [CA 3] Center 33 (3~64) winsize 62
1483 05:56:21.943990 [CA 4] Center 34 (4~65) winsize 62
1484 05:56:21.947192 [CA 5] Center 33 (3~64) winsize 62
1485 05:56:21.947307
1486 05:56:21.950372 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1487 05:56:21.950477
1488 05:56:21.954114 [CATrainingPosCal] consider 2 rank data
1489 05:56:21.957273 u2DelayCellTimex100 = 270/100 ps
1490 05:56:21.960399 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1491 05:56:21.963638 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1492 05:56:21.970652 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1493 05:56:21.970765 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1494 05:56:21.974600 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1495 05:56:21.978640 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1496 05:56:21.978739
1497 05:56:21.985021 CA PerBit enable=1, Macro0, CA PI delay=34
1498 05:56:21.985158
1499 05:56:21.985243 [CBTSetCACLKResult] CA Dly = 34
1500 05:56:21.988873 CS Dly: 6 (0~38)
1501 05:56:21.988961
1502 05:56:21.992741 ----->DramcWriteLeveling(PI) begin...
1503 05:56:21.992831 ==
1504 05:56:21.996683 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 05:56:22.000093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 05:56:22.000225 ==
1507 05:56:22.003671 Write leveling (Byte 0): 28 => 28
1508 05:56:22.007215 Write leveling (Byte 1): 29 => 29
1509 05:56:22.007308 DramcWriteLeveling(PI) end<-----
1510 05:56:22.007375
1511 05:56:22.010693 ==
1512 05:56:22.014140 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 05:56:22.017140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1514 05:56:22.017277 ==
1515 05:56:22.021048 [Gating] SW mode calibration
1516 05:56:22.027252 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1517 05:56:22.030624 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1518 05:56:22.037267 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1519 05:56:22.040801 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1520 05:56:22.044249 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1521 05:56:22.050657 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 05:56:22.053969 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 05:56:22.057142 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 05:56:22.063827 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 05:56:22.067088 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 05:56:22.070460 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 05:56:22.077155 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 05:56:22.080508 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 05:56:22.083810 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 05:56:22.087386 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 05:56:22.094143 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 05:56:22.097008 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 05:56:22.100456 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 05:56:22.107067 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 05:56:22.110549 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1536 05:56:22.114105 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1537 05:56:22.120696 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 05:56:22.123948 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 05:56:22.127331 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 05:56:22.134094 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 05:56:22.137417 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 05:56:22.140546 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 05:56:22.147333 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 05:56:22.150265 0 9 8 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
1545 05:56:22.153627 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1546 05:56:22.160461 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 05:56:22.163556 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 05:56:22.166905 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 05:56:22.173566 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 05:56:22.177085 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 05:56:22.180354 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 05:56:22.187106 0 10 8 | B1->B0 | 2d2d 2626 | 0 0 | (0 1) (0 0)
1553 05:56:22.190371 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 05:56:22.193724 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 05:56:22.200107 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 05:56:22.203426 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 05:56:22.207000 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 05:56:22.210372 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 05:56:22.217137 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1560 05:56:22.220192 0 11 8 | B1->B0 | 3535 3737 | 0 1 | (0 0) (0 0)
1561 05:56:22.223381 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 05:56:22.230134 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 05:56:22.233599 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 05:56:22.236907 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 05:56:22.243531 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 05:56:22.246799 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 05:56:22.250618 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 05:56:22.256832 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1569 05:56:22.260353 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 05:56:22.263720 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 05:56:22.270105 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 05:56:22.273609 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 05:56:22.276966 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 05:56:22.283637 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 05:56:22.286957 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 05:56:22.290273 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 05:56:22.296801 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 05:56:22.300638 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 05:56:22.304136 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 05:56:22.307045 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 05:56:22.313751 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 05:56:22.317131 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 05:56:22.320577 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1584 05:56:22.326774 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1585 05:56:22.330323 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1586 05:56:22.333402 Total UI for P1: 0, mck2ui 16
1587 05:56:22.336662 best dqsien dly found for B0: ( 0, 14, 6)
1588 05:56:22.340490 Total UI for P1: 0, mck2ui 16
1589 05:56:22.343380 best dqsien dly found for B1: ( 0, 14, 6)
1590 05:56:22.347429 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1591 05:56:22.350265 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1592 05:56:22.350387
1593 05:56:22.353637 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1594 05:56:22.356915 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1595 05:56:22.360592 [Gating] SW calibration Done
1596 05:56:22.360696 ==
1597 05:56:22.364097 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 05:56:22.366930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 05:56:22.367020 ==
1600 05:56:22.370416 RX Vref Scan: 0
1601 05:56:22.370532
1602 05:56:22.373824 RX Vref 0 -> 0, step: 1
1603 05:56:22.373938
1604 05:56:22.374034 RX Delay -130 -> 252, step: 16
1605 05:56:22.380290 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1606 05:56:22.383865 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1607 05:56:22.387378 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1608 05:56:22.390625 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1609 05:56:22.393607 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1610 05:56:22.400358 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1611 05:56:22.403972 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1612 05:56:22.407044 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1613 05:56:22.410183 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1614 05:56:22.413560 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1615 05:56:22.420547 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1616 05:56:22.423932 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1617 05:56:22.426775 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1618 05:56:22.430173 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1619 05:56:22.437144 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1620 05:56:22.440187 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1621 05:56:22.440304 ==
1622 05:56:22.443659 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 05:56:22.446921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 05:56:22.447028 ==
1625 05:56:22.447125 DQS Delay:
1626 05:56:22.450462 DQS0 = 0, DQS1 = 0
1627 05:56:22.450565 DQM Delay:
1628 05:56:22.453627 DQM0 = 80, DQM1 = 70
1629 05:56:22.453729 DQ Delay:
1630 05:56:22.457181 DQ0 =85, DQ1 =77, DQ2 =61, DQ3 =77
1631 05:56:22.460237 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1632 05:56:22.463344 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1633 05:56:22.467060 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1634 05:56:22.467155
1635 05:56:22.467220
1636 05:56:22.467280 ==
1637 05:56:22.470506 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 05:56:22.473385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 05:56:22.476942 ==
1640 05:56:22.477028
1641 05:56:22.477093
1642 05:56:22.477152 TX Vref Scan disable
1643 05:56:22.480179 == TX Byte 0 ==
1644 05:56:22.483435 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1645 05:56:22.486672 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1646 05:56:22.489900 == TX Byte 1 ==
1647 05:56:22.493234 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1648 05:56:22.496693 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1649 05:56:22.500203 ==
1650 05:56:22.500309 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 05:56:22.506791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 05:56:22.506909 ==
1653 05:56:22.518777 TX Vref=22, minBit 1, minWin=26, winSum=440
1654 05:56:22.522168 TX Vref=24, minBit 1, minWin=27, winSum=441
1655 05:56:22.525605 TX Vref=26, minBit 1, minWin=27, winSum=444
1656 05:56:22.528984 TX Vref=28, minBit 6, minWin=27, winSum=447
1657 05:56:22.532447 TX Vref=30, minBit 0, minWin=27, winSum=443
1658 05:56:22.535309 TX Vref=32, minBit 0, minWin=27, winSum=443
1659 05:56:22.542444 [TxChooseVref] Worse bit 6, Min win 27, Win sum 447, Final Vref 28
1660 05:56:22.542574
1661 05:56:22.545795 Final TX Range 1 Vref 28
1662 05:56:22.545899
1663 05:56:22.545965 ==
1664 05:56:22.549084 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 05:56:22.552527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 05:56:22.552632 ==
1667 05:56:22.552730
1668 05:56:22.552805
1669 05:56:22.555695 TX Vref Scan disable
1670 05:56:22.559242 == TX Byte 0 ==
1671 05:56:22.562778 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1672 05:56:22.565892 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1673 05:56:22.568832 == TX Byte 1 ==
1674 05:56:22.572144 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1675 05:56:22.575707 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1676 05:56:22.575817
1677 05:56:22.579141 [DATLAT]
1678 05:56:22.579241 Freq=800, CH1 RK0
1679 05:56:22.579337
1680 05:56:22.582593 DATLAT Default: 0xa
1681 05:56:22.582695 0, 0xFFFF, sum = 0
1682 05:56:22.585871 1, 0xFFFF, sum = 0
1683 05:56:22.585972 2, 0xFFFF, sum = 0
1684 05:56:22.589158 3, 0xFFFF, sum = 0
1685 05:56:22.589243 4, 0xFFFF, sum = 0
1686 05:56:22.592585 5, 0xFFFF, sum = 0
1687 05:56:22.592687 6, 0xFFFF, sum = 0
1688 05:56:22.595909 7, 0xFFFF, sum = 0
1689 05:56:22.596010 8, 0xFFFF, sum = 0
1690 05:56:22.599202 9, 0x0, sum = 1
1691 05:56:22.599304 10, 0x0, sum = 2
1692 05:56:22.602075 11, 0x0, sum = 3
1693 05:56:22.602176 12, 0x0, sum = 4
1694 05:56:22.605667 best_step = 10
1695 05:56:22.605768
1696 05:56:22.605863 ==
1697 05:56:22.608990 Dram Type= 6, Freq= 0, CH_1, rank 0
1698 05:56:22.612318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1699 05:56:22.612422 ==
1700 05:56:22.615564 RX Vref Scan: 1
1701 05:56:22.615651
1702 05:56:22.615748 Set Vref Range= 32 -> 127
1703 05:56:22.615839
1704 05:56:22.618730 RX Vref 32 -> 127, step: 1
1705 05:56:22.618830
1706 05:56:22.622586 RX Delay -111 -> 252, step: 8
1707 05:56:22.622690
1708 05:56:22.625620 Set Vref, RX VrefLevel [Byte0]: 32
1709 05:56:22.629136 [Byte1]: 32
1710 05:56:22.629226
1711 05:56:22.632004 Set Vref, RX VrefLevel [Byte0]: 33
1712 05:56:22.635437 [Byte1]: 33
1713 05:56:22.638955
1714 05:56:22.639049 Set Vref, RX VrefLevel [Byte0]: 34
1715 05:56:22.642875 [Byte1]: 34
1716 05:56:22.646738
1717 05:56:22.646832 Set Vref, RX VrefLevel [Byte0]: 35
1718 05:56:22.650207 [Byte1]: 35
1719 05:56:22.654732
1720 05:56:22.654836 Set Vref, RX VrefLevel [Byte0]: 36
1721 05:56:22.657574 [Byte1]: 36
1722 05:56:22.662059
1723 05:56:22.662193 Set Vref, RX VrefLevel [Byte0]: 37
1724 05:56:22.665460 [Byte1]: 37
1725 05:56:22.669670
1726 05:56:22.669809 Set Vref, RX VrefLevel [Byte0]: 38
1727 05:56:22.673202 [Byte1]: 38
1728 05:56:22.677543
1729 05:56:22.677656 Set Vref, RX VrefLevel [Byte0]: 39
1730 05:56:22.681121 [Byte1]: 39
1731 05:56:22.684976
1732 05:56:22.685087 Set Vref, RX VrefLevel [Byte0]: 40
1733 05:56:22.688451 [Byte1]: 40
1734 05:56:22.692752
1735 05:56:22.692849 Set Vref, RX VrefLevel [Byte0]: 41
1736 05:56:22.696096 [Byte1]: 41
1737 05:56:22.700490
1738 05:56:22.700588 Set Vref, RX VrefLevel [Byte0]: 42
1739 05:56:22.703946 [Byte1]: 42
1740 05:56:22.707917
1741 05:56:22.708011 Set Vref, RX VrefLevel [Byte0]: 43
1742 05:56:22.711358 [Byte1]: 43
1743 05:56:22.715862
1744 05:56:22.715956 Set Vref, RX VrefLevel [Byte0]: 44
1745 05:56:22.719198 [Byte1]: 44
1746 05:56:22.723060
1747 05:56:22.726305 Set Vref, RX VrefLevel [Byte0]: 45
1748 05:56:22.726402 [Byte1]: 45
1749 05:56:22.730650
1750 05:56:22.730772 Set Vref, RX VrefLevel [Byte0]: 46
1751 05:56:22.734008 [Byte1]: 46
1752 05:56:22.738635
1753 05:56:22.738744 Set Vref, RX VrefLevel [Byte0]: 47
1754 05:56:22.741985 [Byte1]: 47
1755 05:56:22.746411
1756 05:56:22.746510 Set Vref, RX VrefLevel [Byte0]: 48
1757 05:56:22.749705 [Byte1]: 48
1758 05:56:22.753699
1759 05:56:22.753802 Set Vref, RX VrefLevel [Byte0]: 49
1760 05:56:22.757082 [Byte1]: 49
1761 05:56:22.761572
1762 05:56:22.761667 Set Vref, RX VrefLevel [Byte0]: 50
1763 05:56:22.764710 [Byte1]: 50
1764 05:56:22.769138
1765 05:56:22.769238 Set Vref, RX VrefLevel [Byte0]: 51
1766 05:56:22.772381 [Byte1]: 51
1767 05:56:22.776962
1768 05:56:22.777067 Set Vref, RX VrefLevel [Byte0]: 52
1769 05:56:22.780137 [Byte1]: 52
1770 05:56:22.784363
1771 05:56:22.784458 Set Vref, RX VrefLevel [Byte0]: 53
1772 05:56:22.787876 [Byte1]: 53
1773 05:56:22.792258
1774 05:56:22.792373 Set Vref, RX VrefLevel [Byte0]: 54
1775 05:56:22.795491 [Byte1]: 54
1776 05:56:22.799837
1777 05:56:22.799931 Set Vref, RX VrefLevel [Byte0]: 55
1778 05:56:22.802921 [Byte1]: 55
1779 05:56:22.807540
1780 05:56:22.807636 Set Vref, RX VrefLevel [Byte0]: 56
1781 05:56:22.811032 [Byte1]: 56
1782 05:56:22.815062
1783 05:56:22.815154 Set Vref, RX VrefLevel [Byte0]: 57
1784 05:56:22.818451 [Byte1]: 57
1785 05:56:22.822804
1786 05:56:22.822901 Set Vref, RX VrefLevel [Byte0]: 58
1787 05:56:22.826125 [Byte1]: 58
1788 05:56:22.830057
1789 05:56:22.830147 Set Vref, RX VrefLevel [Byte0]: 59
1790 05:56:22.833442 [Byte1]: 59
1791 05:56:22.838082
1792 05:56:22.838179 Set Vref, RX VrefLevel [Byte0]: 60
1793 05:56:22.841068 [Byte1]: 60
1794 05:56:22.845656
1795 05:56:22.845748 Set Vref, RX VrefLevel [Byte0]: 61
1796 05:56:22.848909 [Byte1]: 61
1797 05:56:22.853348
1798 05:56:22.853442 Set Vref, RX VrefLevel [Byte0]: 62
1799 05:56:22.856694 [Byte1]: 62
1800 05:56:22.860702
1801 05:56:22.860793 Set Vref, RX VrefLevel [Byte0]: 63
1802 05:56:22.864117 [Byte1]: 63
1803 05:56:22.868749
1804 05:56:22.868850 Set Vref, RX VrefLevel [Byte0]: 64
1805 05:56:22.872196 [Byte1]: 64
1806 05:56:22.876109
1807 05:56:22.876200 Set Vref, RX VrefLevel [Byte0]: 65
1808 05:56:22.879400 [Byte1]: 65
1809 05:56:22.883877
1810 05:56:22.883976 Set Vref, RX VrefLevel [Byte0]: 66
1811 05:56:22.887295 [Byte1]: 66
1812 05:56:22.891762
1813 05:56:22.891857 Set Vref, RX VrefLevel [Byte0]: 67
1814 05:56:22.895067 [Byte1]: 67
1815 05:56:22.899241
1816 05:56:22.899335 Set Vref, RX VrefLevel [Byte0]: 68
1817 05:56:22.902267 [Byte1]: 68
1818 05:56:22.906613
1819 05:56:22.906710 Set Vref, RX VrefLevel [Byte0]: 69
1820 05:56:22.910199 [Byte1]: 69
1821 05:56:22.914487
1822 05:56:22.914598 Set Vref, RX VrefLevel [Byte0]: 70
1823 05:56:22.917484 [Byte1]: 70
1824 05:56:22.922198
1825 05:56:22.922303 Set Vref, RX VrefLevel [Byte0]: 71
1826 05:56:22.925440 [Byte1]: 71
1827 05:56:22.929963
1828 05:56:22.930064 Set Vref, RX VrefLevel [Byte0]: 72
1829 05:56:22.933093 [Byte1]: 72
1830 05:56:22.937176
1831 05:56:22.937274 Set Vref, RX VrefLevel [Byte0]: 73
1832 05:56:22.940466 [Byte1]: 73
1833 05:56:22.945289
1834 05:56:22.945390 Final RX Vref Byte 0 = 60 to rank0
1835 05:56:22.948527 Final RX Vref Byte 1 = 59 to rank0
1836 05:56:22.951440 Final RX Vref Byte 0 = 60 to rank1
1837 05:56:22.955133 Final RX Vref Byte 1 = 59 to rank1==
1838 05:56:22.958338 Dram Type= 6, Freq= 0, CH_1, rank 0
1839 05:56:22.965182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 05:56:22.965305 ==
1841 05:56:22.965376 DQS Delay:
1842 05:56:22.965437 DQS0 = 0, DQS1 = 0
1843 05:56:22.968634 DQM Delay:
1844 05:56:22.968728 DQM0 = 81, DQM1 = 70
1845 05:56:22.971998 DQ Delay:
1846 05:56:22.975469 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1847 05:56:22.975565 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1848 05:56:22.978733 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1849 05:56:22.981553 DQ12 =76, DQ13 =76, DQ14 =76, DQ15 =76
1850 05:56:22.984962
1851 05:56:22.985054
1852 05:56:22.991378 [DQSOSCAuto] RK0, (LSB)MR18= 0x131d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1853 05:56:22.995100 CH1 RK0: MR19=606, MR18=131D
1854 05:56:23.001938 CH1_RK0: MR19=0x606, MR18=0x131D, DQSOSC=402, MR23=63, INC=91, DEC=60
1855 05:56:23.002057
1856 05:56:23.004764 ----->DramcWriteLeveling(PI) begin...
1857 05:56:23.004853 ==
1858 05:56:23.008160 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 05:56:23.011491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 05:56:23.011586 ==
1861 05:56:23.015373 Write leveling (Byte 0): 29 => 29
1862 05:56:23.018452 Write leveling (Byte 1): 31 => 31
1863 05:56:23.021613 DramcWriteLeveling(PI) end<-----
1864 05:56:23.021736
1865 05:56:23.021846 ==
1866 05:56:23.024844 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 05:56:23.028448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 05:56:23.028543 ==
1869 05:56:23.031777 [Gating] SW mode calibration
1870 05:56:23.038078 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1871 05:56:23.044924 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1872 05:56:23.048194 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1873 05:56:23.051413 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1874 05:56:23.058260 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 05:56:23.061670 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 05:56:23.064659 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 05:56:23.071497 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 05:56:23.074959 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 05:56:23.078444 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 05:56:23.085027 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 05:56:23.087961 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 05:56:23.091463 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 05:56:23.098190 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 05:56:23.101437 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 05:56:23.104799 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 05:56:23.111046 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 05:56:23.115075 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 05:56:23.117979 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1889 05:56:23.124733 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1890 05:56:23.128216 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1891 05:56:23.131325 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 05:56:23.134716 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 05:56:23.141397 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 05:56:23.144800 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 05:56:23.148216 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 05:56:23.154315 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 05:56:23.157729 0 9 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
1898 05:56:23.161461 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1899 05:56:23.167662 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 05:56:23.171287 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 05:56:23.174273 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 05:56:23.181083 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 05:56:23.184582 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 05:56:23.187465 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1905 05:56:23.194648 0 10 4 | B1->B0 | 3030 2f2f | 0 1 | (0 0) (1 0)
1906 05:56:23.197397 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1907 05:56:23.200928 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 05:56:23.208017 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 05:56:23.210840 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 05:56:23.214084 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 05:56:23.221004 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 05:56:23.224327 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 05:56:23.227757 0 11 4 | B1->B0 | 2e2e 3636 | 0 0 | (0 0) (1 1)
1914 05:56:23.234287 0 11 8 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
1915 05:56:23.237654 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 05:56:23.240671 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 05:56:23.247495 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 05:56:23.250784 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 05:56:23.254008 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 05:56:23.260784 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 05:56:23.264462 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1922 05:56:23.267823 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1923 05:56:23.271050 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 05:56:23.277350 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 05:56:23.280760 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 05:56:23.283992 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 05:56:23.291146 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 05:56:23.293979 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 05:56:23.297215 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 05:56:23.304050 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 05:56:23.307306 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 05:56:23.310342 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 05:56:23.317234 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 05:56:23.320641 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 05:56:23.324063 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 05:56:23.330656 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 05:56:23.333689 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1938 05:56:23.337080 Total UI for P1: 0, mck2ui 16
1939 05:56:23.340297 best dqsien dly found for B0: ( 0, 14, 2)
1940 05:56:23.343723 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1941 05:56:23.350660 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1942 05:56:23.350804 Total UI for P1: 0, mck2ui 16
1943 05:56:23.357330 best dqsien dly found for B1: ( 0, 14, 6)
1944 05:56:23.360299 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1945 05:56:23.363540 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1946 05:56:23.363658
1947 05:56:23.367183 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1948 05:56:23.370534 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1949 05:56:23.373619 [Gating] SW calibration Done
1950 05:56:23.373737 ==
1951 05:56:23.377522 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 05:56:23.380411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 05:56:23.380526 ==
1954 05:56:23.383947 RX Vref Scan: 0
1955 05:56:23.384062
1956 05:56:23.384159 RX Vref 0 -> 0, step: 1
1957 05:56:23.384247
1958 05:56:23.386912 RX Delay -130 -> 252, step: 16
1959 05:56:23.390716 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1960 05:56:23.397018 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1961 05:56:23.400221 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1962 05:56:23.403743 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1963 05:56:23.407206 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1964 05:56:23.410390 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1965 05:56:23.416972 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1966 05:56:23.420322 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1967 05:56:23.423745 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1968 05:56:23.427194 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1969 05:56:23.430592 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1970 05:56:23.437210 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1971 05:56:23.440479 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1972 05:56:23.443857 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1973 05:56:23.446730 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1974 05:56:23.450225 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1975 05:56:23.453511 ==
1976 05:56:23.453646 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 05:56:23.460485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 05:56:23.460637 ==
1979 05:56:23.460731 DQS Delay:
1980 05:56:23.463818 DQS0 = 0, DQS1 = 0
1981 05:56:23.463913 DQM Delay:
1982 05:56:23.467248 DQM0 = 78, DQM1 = 71
1983 05:56:23.467446 DQ Delay:
1984 05:56:23.470042 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1985 05:56:23.473552 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1986 05:56:23.476978 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1987 05:56:23.480338 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1988 05:56:23.480461
1989 05:56:23.480529
1990 05:56:23.480618 ==
1991 05:56:23.483578 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 05:56:23.487327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 05:56:23.487446 ==
1994 05:56:23.487528
1995 05:56:23.487621
1996 05:56:23.490567 TX Vref Scan disable
1997 05:56:23.493807 == TX Byte 0 ==
1998 05:56:23.497062 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1999 05:56:23.500262 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2000 05:56:23.500373 == TX Byte 1 ==
2001 05:56:23.507075 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2002 05:56:23.510176 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2003 05:56:23.510302 ==
2004 05:56:23.513955 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 05:56:23.516979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 05:56:23.517090 ==
2007 05:56:23.531048 TX Vref=22, minBit 3, minWin=27, winSum=448
2008 05:56:23.534575 TX Vref=24, minBit 0, minWin=27, winSum=448
2009 05:56:23.537939 TX Vref=26, minBit 5, minWin=27, winSum=455
2010 05:56:23.541258 TX Vref=28, minBit 1, minWin=27, winSum=456
2011 05:56:23.544487 TX Vref=30, minBit 1, minWin=27, winSum=455
2012 05:56:23.547932 TX Vref=32, minBit 1, minWin=27, winSum=452
2013 05:56:23.554840 [TxChooseVref] Worse bit 1, Min win 27, Win sum 456, Final Vref 28
2014 05:56:23.554974
2015 05:56:23.558222 Final TX Range 1 Vref 28
2016 05:56:23.558316
2017 05:56:23.558383 ==
2018 05:56:23.561093 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 05:56:23.564537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 05:56:23.564643 ==
2021 05:56:23.564725
2022 05:56:23.567974
2023 05:56:23.568092 TX Vref Scan disable
2024 05:56:23.570967 == TX Byte 0 ==
2025 05:56:23.574375 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2026 05:56:23.581298 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2027 05:56:23.581494 == TX Byte 1 ==
2028 05:56:23.584754 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2029 05:56:23.591259 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2030 05:56:23.591482
2031 05:56:23.591557 [DATLAT]
2032 05:56:23.591650 Freq=800, CH1 RK1
2033 05:56:23.591738
2034 05:56:23.594313 DATLAT Default: 0xa
2035 05:56:23.594418 0, 0xFFFF, sum = 0
2036 05:56:23.597960 1, 0xFFFF, sum = 0
2037 05:56:23.598111 2, 0xFFFF, sum = 0
2038 05:56:23.601149 3, 0xFFFF, sum = 0
2039 05:56:23.601288 4, 0xFFFF, sum = 0
2040 05:56:23.604519 5, 0xFFFF, sum = 0
2041 05:56:23.607723 6, 0xFFFF, sum = 0
2042 05:56:23.607845 7, 0xFFFF, sum = 0
2043 05:56:23.611524 8, 0xFFFF, sum = 0
2044 05:56:23.611636 9, 0x0, sum = 1
2045 05:56:23.611718 10, 0x0, sum = 2
2046 05:56:23.614404 11, 0x0, sum = 3
2047 05:56:23.614510 12, 0x0, sum = 4
2048 05:56:23.617698 best_step = 10
2049 05:56:23.617805
2050 05:56:23.617886 ==
2051 05:56:23.621611 Dram Type= 6, Freq= 0, CH_1, rank 1
2052 05:56:23.624494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2053 05:56:23.624615 ==
2054 05:56:23.627998 RX Vref Scan: 0
2055 05:56:23.628117
2056 05:56:23.628199 RX Vref 0 -> 0, step: 1
2057 05:56:23.628290
2058 05:56:23.631145 RX Delay -111 -> 252, step: 8
2059 05:56:23.637954 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2060 05:56:23.641142 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2061 05:56:23.644748 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2062 05:56:23.648029 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2063 05:56:23.651729 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2064 05:56:23.658203 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2065 05:56:23.661688 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2066 05:56:23.664990 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2067 05:56:23.667845 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2068 05:56:23.671378 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2069 05:56:23.677772 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2070 05:56:23.681175 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2071 05:56:23.684444 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2072 05:56:23.687968 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2073 05:56:23.691365 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2074 05:56:23.697960 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2075 05:56:23.698096 ==
2076 05:56:23.701405 Dram Type= 6, Freq= 0, CH_1, rank 1
2077 05:56:23.704620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2078 05:56:23.704733 ==
2079 05:56:23.704831 DQS Delay:
2080 05:56:23.707971 DQS0 = 0, DQS1 = 0
2081 05:56:23.708066 DQM Delay:
2082 05:56:23.711135 DQM0 = 77, DQM1 = 75
2083 05:56:23.711253 DQ Delay:
2084 05:56:23.714654 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2085 05:56:23.718088 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2086 05:56:23.721224 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
2087 05:56:23.724469 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2088 05:56:23.724619
2089 05:56:23.724717
2090 05:56:23.734370 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
2091 05:56:23.734545 CH1 RK1: MR19=606, MR18=1E36
2092 05:56:23.741156 CH1_RK1: MR19=0x606, MR18=0x1E36, DQSOSC=396, MR23=63, INC=94, DEC=62
2093 05:56:23.744361 [RxdqsGatingPostProcess] freq 800
2094 05:56:23.751332 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2095 05:56:23.754496 Pre-setting of DQS Precalculation
2096 05:56:23.757943 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2097 05:56:23.764711 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2098 05:56:23.771254 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2099 05:56:23.771416
2100 05:56:23.774848
2101 05:56:23.774971 [Calibration Summary] 1600 Mbps
2102 05:56:23.777680 CH 0, Rank 0
2103 05:56:23.777790 SW Impedance : PASS
2104 05:56:23.781139 DUTY Scan : NO K
2105 05:56:23.784446 ZQ Calibration : PASS
2106 05:56:23.784568 Jitter Meter : NO K
2107 05:56:23.787991 CBT Training : PASS
2108 05:56:23.791372 Write leveling : PASS
2109 05:56:23.791478 RX DQS gating : PASS
2110 05:56:23.794807 RX DQ/DQS(RDDQC) : PASS
2111 05:56:23.797691 TX DQ/DQS : PASS
2112 05:56:23.797809 RX DATLAT : PASS
2113 05:56:23.801006 RX DQ/DQS(Engine): PASS
2114 05:56:23.801117 TX OE : NO K
2115 05:56:23.804678 All Pass.
2116 05:56:23.804783
2117 05:56:23.804882 CH 0, Rank 1
2118 05:56:23.807849 SW Impedance : PASS
2119 05:56:23.807952 DUTY Scan : NO K
2120 05:56:23.811114 ZQ Calibration : PASS
2121 05:56:23.814420 Jitter Meter : NO K
2122 05:56:23.814527 CBT Training : PASS
2123 05:56:23.817951 Write leveling : PASS
2124 05:56:23.821078 RX DQS gating : PASS
2125 05:56:23.821186 RX DQ/DQS(RDDQC) : PASS
2126 05:56:23.824673 TX DQ/DQS : PASS
2127 05:56:23.827973 RX DATLAT : PASS
2128 05:56:23.828134 RX DQ/DQS(Engine): PASS
2129 05:56:23.831360 TX OE : NO K
2130 05:56:23.831448 All Pass.
2131 05:56:23.831513
2132 05:56:23.834553 CH 1, Rank 0
2133 05:56:23.834638 SW Impedance : PASS
2134 05:56:23.838077 DUTY Scan : NO K
2135 05:56:23.841377 ZQ Calibration : PASS
2136 05:56:23.841497 Jitter Meter : NO K
2137 05:56:23.844361 CBT Training : PASS
2138 05:56:23.847793 Write leveling : PASS
2139 05:56:23.847888 RX DQS gating : PASS
2140 05:56:23.851280 RX DQ/DQS(RDDQC) : PASS
2141 05:56:23.851369 TX DQ/DQS : PASS
2142 05:56:23.854426 RX DATLAT : PASS
2143 05:56:23.857794 RX DQ/DQS(Engine): PASS
2144 05:56:23.857898 TX OE : NO K
2145 05:56:23.861326 All Pass.
2146 05:56:23.861418
2147 05:56:23.861514 CH 1, Rank 1
2148 05:56:23.864222 SW Impedance : PASS
2149 05:56:23.864312 DUTY Scan : NO K
2150 05:56:23.868182 ZQ Calibration : PASS
2151 05:56:23.871430 Jitter Meter : NO K
2152 05:56:23.871537 CBT Training : PASS
2153 05:56:23.874465 Write leveling : PASS
2154 05:56:23.877393 RX DQS gating : PASS
2155 05:56:23.877499 RX DQ/DQS(RDDQC) : PASS
2156 05:56:23.880849 TX DQ/DQS : PASS
2157 05:56:23.884238 RX DATLAT : PASS
2158 05:56:23.884353 RX DQ/DQS(Engine): PASS
2159 05:56:23.887639 TX OE : NO K
2160 05:56:23.887732 All Pass.
2161 05:56:23.887799
2162 05:56:23.891089 DramC Write-DBI off
2163 05:56:23.894485 PER_BANK_REFRESH: Hybrid Mode
2164 05:56:23.894579 TX_TRACKING: ON
2165 05:56:23.897958 [GetDramInforAfterCalByMRR] Vendor 6.
2166 05:56:23.900791 [GetDramInforAfterCalByMRR] Revision 606.
2167 05:56:23.904599 [GetDramInforAfterCalByMRR] Revision 2 0.
2168 05:56:23.907850 MR0 0x3b3b
2169 05:56:23.907955 MR8 0x5151
2170 05:56:23.911104 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2171 05:56:23.911193
2172 05:56:23.911259 MR0 0x3b3b
2173 05:56:23.914480 MR8 0x5151
2174 05:56:23.917486 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2175 05:56:23.917597
2176 05:56:23.927512 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2177 05:56:23.931075 [FAST_K] Save calibration result to emmc
2178 05:56:23.934314 [FAST_K] Save calibration result to emmc
2179 05:56:23.934433 dram_init: config_dvfs: 1
2180 05:56:23.941107 dramc_set_vcore_voltage set vcore to 662500
2181 05:56:23.941239 Read voltage for 1200, 2
2182 05:56:23.944567 Vio18 = 0
2183 05:56:23.944661 Vcore = 662500
2184 05:56:23.944729 Vdram = 0
2185 05:56:23.944790 Vddq = 0
2186 05:56:23.947512 Vmddr = 0
2187 05:56:23.950894 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2188 05:56:23.957685 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2189 05:56:23.960959 MEM_TYPE=3, freq_sel=15
2190 05:56:23.961110 sv_algorithm_assistance_LP4_1600
2191 05:56:23.967303 ============ PULL DRAM RESETB DOWN ============
2192 05:56:23.970566 ========== PULL DRAM RESETB DOWN end =========
2193 05:56:23.974069 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2194 05:56:23.977693 ===================================
2195 05:56:23.980549 LPDDR4 DRAM CONFIGURATION
2196 05:56:23.984388 ===================================
2197 05:56:23.987542 EX_ROW_EN[0] = 0x0
2198 05:56:23.987649 EX_ROW_EN[1] = 0x0
2199 05:56:23.990578 LP4Y_EN = 0x0
2200 05:56:23.990669 WORK_FSP = 0x0
2201 05:56:23.994101 WL = 0x4
2202 05:56:23.994199 RL = 0x4
2203 05:56:23.997380 BL = 0x2
2204 05:56:23.997524 RPST = 0x0
2205 05:56:24.000669 RD_PRE = 0x0
2206 05:56:24.000764 WR_PRE = 0x1
2207 05:56:24.004198 WR_PST = 0x0
2208 05:56:24.004301 DBI_WR = 0x0
2209 05:56:24.007457 DBI_RD = 0x0
2210 05:56:24.007549 OTF = 0x1
2211 05:56:24.010751 ===================================
2212 05:56:24.014275 ===================================
2213 05:56:24.017180 ANA top config
2214 05:56:24.020950 ===================================
2215 05:56:24.024169 DLL_ASYNC_EN = 0
2216 05:56:24.024307 ALL_SLAVE_EN = 0
2217 05:56:24.027536 NEW_RANK_MODE = 1
2218 05:56:24.030777 DLL_IDLE_MODE = 1
2219 05:56:24.033995 LP45_APHY_COMB_EN = 1
2220 05:56:24.034103 TX_ODT_DIS = 1
2221 05:56:24.037451 NEW_8X_MODE = 1
2222 05:56:24.040612 ===================================
2223 05:56:24.044031 ===================================
2224 05:56:24.047441 data_rate = 2400
2225 05:56:24.051009 CKR = 1
2226 05:56:24.053846 DQ_P2S_RATIO = 8
2227 05:56:24.057336 ===================================
2228 05:56:24.060807 CA_P2S_RATIO = 8
2229 05:56:24.060925 DQ_CA_OPEN = 0
2230 05:56:24.064191 DQ_SEMI_OPEN = 0
2231 05:56:24.067670 CA_SEMI_OPEN = 0
2232 05:56:24.071046 CA_FULL_RATE = 0
2233 05:56:24.074025 DQ_CKDIV4_EN = 0
2234 05:56:24.077260 CA_CKDIV4_EN = 0
2235 05:56:24.077395 CA_PREDIV_EN = 0
2236 05:56:24.080729 PH8_DLY = 17
2237 05:56:24.084258 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2238 05:56:24.087737 DQ_AAMCK_DIV = 4
2239 05:56:24.090618 CA_AAMCK_DIV = 4
2240 05:56:24.094125 CA_ADMCK_DIV = 4
2241 05:56:24.094241 DQ_TRACK_CA_EN = 0
2242 05:56:24.097446 CA_PICK = 1200
2243 05:56:24.100833 CA_MCKIO = 1200
2244 05:56:24.104031 MCKIO_SEMI = 0
2245 05:56:24.107497 PLL_FREQ = 2366
2246 05:56:24.111129 DQ_UI_PI_RATIO = 32
2247 05:56:24.113789 CA_UI_PI_RATIO = 0
2248 05:56:24.117268 ===================================
2249 05:56:24.120435 ===================================
2250 05:56:24.120527 memory_type:LPDDR4
2251 05:56:24.123964 GP_NUM : 10
2252 05:56:24.127213 SRAM_EN : 1
2253 05:56:24.127308 MD32_EN : 0
2254 05:56:24.130887 ===================================
2255 05:56:24.133936 [ANA_INIT] >>>>>>>>>>>>>>
2256 05:56:24.137254 <<<<<< [CONFIGURE PHASE]: ANA_TX
2257 05:56:24.140432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2258 05:56:24.143834 ===================================
2259 05:56:24.147086 data_rate = 2400,PCW = 0X5b00
2260 05:56:24.150579 ===================================
2261 05:56:24.153753 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2262 05:56:24.157024 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2263 05:56:24.163999 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2264 05:56:24.167137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2265 05:56:24.170720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2266 05:56:24.174168 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2267 05:56:24.177418 [ANA_INIT] flow start
2268 05:56:24.180823 [ANA_INIT] PLL >>>>>>>>
2269 05:56:24.180940 [ANA_INIT] PLL <<<<<<<<
2270 05:56:24.183787 [ANA_INIT] MIDPI >>>>>>>>
2271 05:56:24.187240 [ANA_INIT] MIDPI <<<<<<<<
2272 05:56:24.187353 [ANA_INIT] DLL >>>>>>>>
2273 05:56:24.190644 [ANA_INIT] DLL <<<<<<<<
2274 05:56:24.194020 [ANA_INIT] flow end
2275 05:56:24.197327 ============ LP4 DIFF to SE enter ============
2276 05:56:24.200745 ============ LP4 DIFF to SE exit ============
2277 05:56:24.203648 [ANA_INIT] <<<<<<<<<<<<<
2278 05:56:24.207199 [Flow] Enable top DCM control >>>>>
2279 05:56:24.210670 [Flow] Enable top DCM control <<<<<
2280 05:56:24.213565 Enable DLL master slave shuffle
2281 05:56:24.216832 ==============================================================
2282 05:56:24.220650 Gating Mode config
2283 05:56:24.227358 ==============================================================
2284 05:56:24.227506 Config description:
2285 05:56:24.236888 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2286 05:56:24.243719 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2287 05:56:24.247039 SELPH_MODE 0: By rank 1: By Phase
2288 05:56:24.253651 ==============================================================
2289 05:56:24.257214 GAT_TRACK_EN = 1
2290 05:56:24.260148 RX_GATING_MODE = 2
2291 05:56:24.263842 RX_GATING_TRACK_MODE = 2
2292 05:56:24.267366 SELPH_MODE = 1
2293 05:56:24.270154 PICG_EARLY_EN = 1
2294 05:56:24.273928 VALID_LAT_VALUE = 1
2295 05:56:24.277323 ==============================================================
2296 05:56:24.280712 Enter into Gating configuration >>>>
2297 05:56:24.283508 Exit from Gating configuration <<<<
2298 05:56:24.286979 Enter into DVFS_PRE_config >>>>>
2299 05:56:24.297291 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2300 05:56:24.300032 Exit from DVFS_PRE_config <<<<<
2301 05:56:24.303413 Enter into PICG configuration >>>>
2302 05:56:24.307397 Exit from PICG configuration <<<<
2303 05:56:24.310129 [RX_INPUT] configuration >>>>>
2304 05:56:24.313689 [RX_INPUT] configuration <<<<<
2305 05:56:24.320519 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2306 05:56:24.323904 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2307 05:56:24.330432 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 05:56:24.337398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 05:56:24.343643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2310 05:56:24.350582 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2311 05:56:24.353643 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2312 05:56:24.357145 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2313 05:56:24.360383 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2314 05:56:24.363520 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2315 05:56:24.370242 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2316 05:56:24.373650 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2317 05:56:24.377173 ===================================
2318 05:56:24.380315 LPDDR4 DRAM CONFIGURATION
2319 05:56:24.383524 ===================================
2320 05:56:24.383640 EX_ROW_EN[0] = 0x0
2321 05:56:24.387071 EX_ROW_EN[1] = 0x0
2322 05:56:24.387161 LP4Y_EN = 0x0
2323 05:56:24.390542 WORK_FSP = 0x0
2324 05:56:24.390629 WL = 0x4
2325 05:56:24.393467 RL = 0x4
2326 05:56:24.393592 BL = 0x2
2327 05:56:24.396935 RPST = 0x0
2328 05:56:24.397020 RD_PRE = 0x0
2329 05:56:24.400330 WR_PRE = 0x1
2330 05:56:24.400417 WR_PST = 0x0
2331 05:56:24.403565 DBI_WR = 0x0
2332 05:56:24.407021 DBI_RD = 0x0
2333 05:56:24.407115 OTF = 0x1
2334 05:56:24.410497 ===================================
2335 05:56:24.413973 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2336 05:56:24.416801 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2337 05:56:24.423706 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2338 05:56:24.427275 ===================================
2339 05:56:24.430618 LPDDR4 DRAM CONFIGURATION
2340 05:56:24.430718 ===================================
2341 05:56:24.433985 EX_ROW_EN[0] = 0x10
2342 05:56:24.436891 EX_ROW_EN[1] = 0x0
2343 05:56:24.436988 LP4Y_EN = 0x0
2344 05:56:24.440301 WORK_FSP = 0x0
2345 05:56:24.440388 WL = 0x4
2346 05:56:24.443785 RL = 0x4
2347 05:56:24.443875 BL = 0x2
2348 05:56:24.447129 RPST = 0x0
2349 05:56:24.447278 RD_PRE = 0x0
2350 05:56:24.450213 WR_PRE = 0x1
2351 05:56:24.450304 WR_PST = 0x0
2352 05:56:24.453870 DBI_WR = 0x0
2353 05:56:24.453964 DBI_RD = 0x0
2354 05:56:24.457092 OTF = 0x1
2355 05:56:24.460447 ===================================
2356 05:56:24.467194 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2357 05:56:24.467311 ==
2358 05:56:24.470462 Dram Type= 6, Freq= 0, CH_0, rank 0
2359 05:56:24.473470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2360 05:56:24.473590 ==
2361 05:56:24.477151 [Duty_Offset_Calibration]
2362 05:56:24.477240 B0:2 B1:0 CA:3
2363 05:56:24.477305
2364 05:56:24.480489 [DutyScan_Calibration_Flow] k_type=0
2365 05:56:24.490655
2366 05:56:24.490785 ==CLK 0==
2367 05:56:24.494132 Final CLK duty delay cell = 0
2368 05:56:24.497232 [0] MAX Duty = 5031%(X100), DQS PI = 12
2369 05:56:24.500659 [0] MIN Duty = 4875%(X100), DQS PI = 58
2370 05:56:24.500765 [0] AVG Duty = 4953%(X100)
2371 05:56:24.503859
2372 05:56:24.507515 CH0 CLK Duty spec in!! Max-Min= 156%
2373 05:56:24.510673 [DutyScan_Calibration_Flow] ====Done====
2374 05:56:24.510770
2375 05:56:24.513656 [DutyScan_Calibration_Flow] k_type=1
2376 05:56:24.530317
2377 05:56:24.530469 ==DQS 0 ==
2378 05:56:24.533602 Final DQS duty delay cell = 0
2379 05:56:24.536873 [0] MAX Duty = 5062%(X100), DQS PI = 16
2380 05:56:24.540281 [0] MIN Duty = 4907%(X100), DQS PI = 2
2381 05:56:24.540388 [0] AVG Duty = 4984%(X100)
2382 05:56:24.543109
2383 05:56:24.543197 ==DQS 1 ==
2384 05:56:24.546603 Final DQS duty delay cell = 0
2385 05:56:24.550021 [0] MAX Duty = 5125%(X100), DQS PI = 34
2386 05:56:24.553369 [0] MIN Duty = 5031%(X100), DQS PI = 0
2387 05:56:24.553542 [0] AVG Duty = 5078%(X100)
2388 05:56:24.556715
2389 05:56:24.559772 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2390 05:56:24.559862
2391 05:56:24.563305 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2392 05:56:24.566683 [DutyScan_Calibration_Flow] ====Done====
2393 05:56:24.566775
2394 05:56:24.570129 [DutyScan_Calibration_Flow] k_type=3
2395 05:56:24.586903
2396 05:56:24.587050 ==DQM 0 ==
2397 05:56:24.590289 Final DQM duty delay cell = 0
2398 05:56:24.593614 [0] MAX Duty = 5124%(X100), DQS PI = 28
2399 05:56:24.597299 [0] MIN Duty = 4876%(X100), DQS PI = 0
2400 05:56:24.597389 [0] AVG Duty = 5000%(X100)
2401 05:56:24.600436
2402 05:56:24.600519 ==DQM 1 ==
2403 05:56:24.603640 Final DQM duty delay cell = 4
2404 05:56:24.607010 [4] MAX Duty = 5124%(X100), DQS PI = 50
2405 05:56:24.610373 [4] MIN Duty = 5031%(X100), DQS PI = 12
2406 05:56:24.610484 [4] AVG Duty = 5077%(X100)
2407 05:56:24.613769
2408 05:56:24.617150 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2409 05:56:24.617252
2410 05:56:24.620336 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2411 05:56:24.623860 [DutyScan_Calibration_Flow] ====Done====
2412 05:56:24.623966
2413 05:56:24.627288 [DutyScan_Calibration_Flow] k_type=2
2414 05:56:24.642163
2415 05:56:24.642317 ==DQ 0 ==
2416 05:56:24.645019 Final DQ duty delay cell = -4
2417 05:56:24.648337 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2418 05:56:24.651837 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2419 05:56:24.655089 [-4] AVG Duty = 4969%(X100)
2420 05:56:24.655197
2421 05:56:24.655263 ==DQ 1 ==
2422 05:56:24.658480 Final DQ duty delay cell = -4
2423 05:56:24.661886 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2424 05:56:24.665305 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2425 05:56:24.668620 [-4] AVG Duty = 4938%(X100)
2426 05:56:24.668719
2427 05:56:24.671543 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2428 05:56:24.671669
2429 05:56:24.675075 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2430 05:56:24.678664 [DutyScan_Calibration_Flow] ====Done====
2431 05:56:24.678781 ==
2432 05:56:24.681429 Dram Type= 6, Freq= 0, CH_1, rank 0
2433 05:56:24.684842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2434 05:56:24.684944 ==
2435 05:56:24.688133 [Duty_Offset_Calibration]
2436 05:56:24.688221 B0:1 B1:-2 CA:0
2437 05:56:24.688286
2438 05:56:24.691366 [DutyScan_Calibration_Flow] k_type=0
2439 05:56:24.702527
2440 05:56:24.702673 ==CLK 0==
2441 05:56:24.705881 Final CLK duty delay cell = 0
2442 05:56:24.708737 [0] MAX Duty = 5062%(X100), DQS PI = 30
2443 05:56:24.712671 [0] MIN Duty = 4875%(X100), DQS PI = 58
2444 05:56:24.712766 [0] AVG Duty = 4968%(X100)
2445 05:56:24.715733
2446 05:56:24.718887 CH1 CLK Duty spec in!! Max-Min= 187%
2447 05:56:24.722656 [DutyScan_Calibration_Flow] ====Done====
2448 05:56:24.722752
2449 05:56:24.725431 [DutyScan_Calibration_Flow] k_type=1
2450 05:56:24.741101
2451 05:56:24.741256 ==DQS 0 ==
2452 05:56:24.744386 Final DQS duty delay cell = -4
2453 05:56:24.747726 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2454 05:56:24.751177 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2455 05:56:24.754460 [-4] AVG Duty = 4953%(X100)
2456 05:56:24.754563
2457 05:56:24.754630 ==DQS 1 ==
2458 05:56:24.757656 Final DQS duty delay cell = 0
2459 05:56:24.761209 [0] MAX Duty = 5093%(X100), DQS PI = 0
2460 05:56:24.764604 [0] MIN Duty = 4875%(X100), DQS PI = 26
2461 05:56:24.764696 [0] AVG Duty = 4984%(X100)
2462 05:56:24.768076
2463 05:56:24.770968 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2464 05:56:24.771064
2465 05:56:24.774419 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2466 05:56:24.777691 [DutyScan_Calibration_Flow] ====Done====
2467 05:56:24.777807
2468 05:56:24.780890 [DutyScan_Calibration_Flow] k_type=3
2469 05:56:24.797816
2470 05:56:24.797968 ==DQM 0 ==
2471 05:56:24.800865 Final DQM duty delay cell = 0
2472 05:56:24.804067 [0] MAX Duty = 5000%(X100), DQS PI = 22
2473 05:56:24.807421 [0] MIN Duty = 4844%(X100), DQS PI = 52
2474 05:56:24.810965 [0] AVG Duty = 4922%(X100)
2475 05:56:24.811058
2476 05:56:24.811124 ==DQM 1 ==
2477 05:56:24.814412 Final DQM duty delay cell = 0
2478 05:56:24.817249 [0] MAX Duty = 5031%(X100), DQS PI = 36
2479 05:56:24.820637 [0] MIN Duty = 4907%(X100), DQS PI = 0
2480 05:56:24.820727 [0] AVG Duty = 4969%(X100)
2481 05:56:24.824262
2482 05:56:24.827650 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2483 05:56:24.827750
2484 05:56:24.831003 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2485 05:56:24.833793 [DutyScan_Calibration_Flow] ====Done====
2486 05:56:24.833883
2487 05:56:24.837193 [DutyScan_Calibration_Flow] k_type=2
2488 05:56:24.854181
2489 05:56:24.854334 ==DQ 0 ==
2490 05:56:24.856958 Final DQ duty delay cell = 0
2491 05:56:24.860368 [0] MAX Duty = 5062%(X100), DQS PI = 18
2492 05:56:24.863889 [0] MIN Duty = 4938%(X100), DQS PI = 54
2493 05:56:24.864054 [0] AVG Duty = 5000%(X100)
2494 05:56:24.866943
2495 05:56:24.867051 ==DQ 1 ==
2496 05:56:24.870362 Final DQ duty delay cell = 0
2497 05:56:24.873915 [0] MAX Duty = 5093%(X100), DQS PI = 20
2498 05:56:24.877261 [0] MIN Duty = 4969%(X100), DQS PI = 26
2499 05:56:24.877373 [0] AVG Duty = 5031%(X100)
2500 05:56:24.877463
2501 05:56:24.880141 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2502 05:56:24.883877
2503 05:56:24.886951 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2504 05:56:24.890235 [DutyScan_Calibration_Flow] ====Done====
2505 05:56:24.893736 nWR fixed to 30
2506 05:56:24.893823 [ModeRegInit_LP4] CH0 RK0
2507 05:56:24.897025 [ModeRegInit_LP4] CH0 RK1
2508 05:56:24.899949 [ModeRegInit_LP4] CH1 RK0
2509 05:56:24.903988 [ModeRegInit_LP4] CH1 RK1
2510 05:56:24.904103 match AC timing 7
2511 05:56:24.906640 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2512 05:56:24.913694 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2513 05:56:24.917066 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2514 05:56:24.923310 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2515 05:56:24.926678 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2516 05:56:24.926767 ==
2517 05:56:24.930525 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 05:56:24.933735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 05:56:24.933827 ==
2520 05:56:24.940060 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2521 05:56:24.946916 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2522 05:56:24.953597 [CA 0] Center 40 (10~71) winsize 62
2523 05:56:24.957036 [CA 1] Center 40 (10~70) winsize 61
2524 05:56:24.960291 [CA 2] Center 36 (6~66) winsize 61
2525 05:56:24.964025 [CA 3] Center 35 (5~66) winsize 62
2526 05:56:24.967000 [CA 4] Center 34 (4~65) winsize 62
2527 05:56:24.970428 [CA 5] Center 33 (3~64) winsize 62
2528 05:56:24.970549
2529 05:56:24.973793 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2530 05:56:24.973912
2531 05:56:24.977212 [CATrainingPosCal] consider 1 rank data
2532 05:56:24.980522 u2DelayCellTimex100 = 270/100 ps
2533 05:56:24.984037 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2534 05:56:24.990299 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2535 05:56:24.994111 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2536 05:56:24.997044 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2537 05:56:25.000612 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2538 05:56:25.004019 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2539 05:56:25.004135
2540 05:56:25.006977 CA PerBit enable=1, Macro0, CA PI delay=33
2541 05:56:25.007068
2542 05:56:25.010338 [CBTSetCACLKResult] CA Dly = 33
2543 05:56:25.014180 CS Dly: 7 (0~38)
2544 05:56:25.014262 ==
2545 05:56:25.017164 Dram Type= 6, Freq= 0, CH_0, rank 1
2546 05:56:25.020467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 05:56:25.020575 ==
2548 05:56:25.027393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2549 05:56:25.030211 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2550 05:56:25.040064 [CA 0] Center 40 (10~70) winsize 61
2551 05:56:25.043521 [CA 1] Center 39 (9~70) winsize 62
2552 05:56:25.046916 [CA 2] Center 35 (5~66) winsize 62
2553 05:56:25.049862 [CA 3] Center 35 (5~66) winsize 62
2554 05:56:25.053381 [CA 4] Center 34 (4~65) winsize 62
2555 05:56:25.056729 [CA 5] Center 33 (3~64) winsize 62
2556 05:56:25.056816
2557 05:56:25.059947 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2558 05:56:25.060054
2559 05:56:25.063720 [CATrainingPosCal] consider 2 rank data
2560 05:56:25.066629 u2DelayCellTimex100 = 270/100 ps
2561 05:56:25.070016 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2562 05:56:25.076627 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2563 05:56:25.080155 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2564 05:56:25.083438 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2565 05:56:25.087224 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2566 05:56:25.090010 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2567 05:56:25.090095
2568 05:56:25.093400 CA PerBit enable=1, Macro0, CA PI delay=33
2569 05:56:25.093521
2570 05:56:25.096985 [CBTSetCACLKResult] CA Dly = 33
2571 05:56:25.097066 CS Dly: 8 (0~40)
2572 05:56:25.097126
2573 05:56:25.100002 ----->DramcWriteLeveling(PI) begin...
2574 05:56:25.103315 ==
2575 05:56:25.106800 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 05:56:25.110487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 05:56:25.110579 ==
2578 05:56:25.113385 Write leveling (Byte 0): 32 => 32
2579 05:56:25.116751 Write leveling (Byte 1): 29 => 29
2580 05:56:25.119981 DramcWriteLeveling(PI) end<-----
2581 05:56:25.120085
2582 05:56:25.120172 ==
2583 05:56:25.123722 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 05:56:25.126703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 05:56:25.126784 ==
2586 05:56:25.130087 [Gating] SW mode calibration
2587 05:56:25.136975 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2588 05:56:25.143587 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2589 05:56:25.146680 0 15 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
2590 05:56:25.150141 0 15 4 | B1->B0 | 2525 3434 | 0 0 | (1 1) (0 0)
2591 05:56:25.153665 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 05:56:25.160305 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 05:56:25.163773 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 05:56:25.167099 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 05:56:25.173787 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 05:56:25.177190 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 05:56:25.180030 1 0 0 | B1->B0 | 3232 2b2b | 1 0 | (1 1) (0 0)
2598 05:56:25.187196 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 05:56:25.190047 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 05:56:25.193484 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 05:56:25.200428 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 05:56:25.203279 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 05:56:25.206507 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 05:56:25.213328 1 0 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2605 05:56:25.216781 1 1 0 | B1->B0 | 2727 3030 | 0 0 | (0 0) (0 0)
2606 05:56:25.219982 1 1 4 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
2607 05:56:25.226958 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 05:56:25.230176 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 05:56:25.233282 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 05:56:25.240120 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 05:56:25.243610 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 05:56:25.246431 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2613 05:56:25.253578 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2614 05:56:25.256397 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2615 05:56:25.259757 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 05:56:25.263203 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 05:56:25.269819 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 05:56:25.273635 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 05:56:25.276599 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 05:56:25.283260 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 05:56:25.286696 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 05:56:25.289916 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 05:56:25.296682 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 05:56:25.299668 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 05:56:25.303138 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 05:56:25.309968 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 05:56:25.313344 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 05:56:25.316638 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2629 05:56:25.323051 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2630 05:56:25.326403 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2631 05:56:25.329725 Total UI for P1: 0, mck2ui 16
2632 05:56:25.333088 best dqsien dly found for B0: ( 1, 3, 30)
2633 05:56:25.336581 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2634 05:56:25.339552 Total UI for P1: 0, mck2ui 16
2635 05:56:25.343393 best dqsien dly found for B1: ( 1, 4, 4)
2636 05:56:25.346695 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2637 05:56:25.349903 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2638 05:56:25.349994
2639 05:56:25.353499 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2640 05:56:25.359896 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2641 05:56:25.360037 [Gating] SW calibration Done
2642 05:56:25.360134 ==
2643 05:56:25.363333 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 05:56:25.369943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 05:56:25.370049 ==
2646 05:56:25.370132 RX Vref Scan: 0
2647 05:56:25.370220
2648 05:56:25.373161 RX Vref 0 -> 0, step: 1
2649 05:56:25.373243
2650 05:56:25.376323 RX Delay -40 -> 252, step: 8
2651 05:56:25.379763 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2652 05:56:25.383231 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2653 05:56:25.386454 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2654 05:56:25.393070 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2655 05:56:25.396311 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2656 05:56:25.399772 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2657 05:56:25.403191 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2658 05:56:25.406725 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2659 05:56:25.409590 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2660 05:56:25.416278 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2661 05:56:25.419943 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2662 05:56:25.422881 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2663 05:56:25.426160 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2664 05:56:25.429693 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2665 05:56:25.436604 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2666 05:56:25.439709 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2667 05:56:25.439799 ==
2668 05:56:25.443137 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 05:56:25.446499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 05:56:25.446607 ==
2671 05:56:25.449951 DQS Delay:
2672 05:56:25.450056 DQS0 = 0, DQS1 = 0
2673 05:56:25.450144 DQM Delay:
2674 05:56:25.453267 DQM0 = 113, DQM1 = 102
2675 05:56:25.453365 DQ Delay:
2676 05:56:25.456540 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =107
2677 05:56:25.459506 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2678 05:56:25.463222 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2679 05:56:25.466511 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2680 05:56:25.469951
2681 05:56:25.470044
2682 05:56:25.470122 ==
2683 05:56:25.473348 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 05:56:25.476295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 05:56:25.476401 ==
2686 05:56:25.476493
2687 05:56:25.476578
2688 05:56:25.480043 TX Vref Scan disable
2689 05:56:25.480145 == TX Byte 0 ==
2690 05:56:25.486727 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2691 05:56:25.490057 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2692 05:56:25.490184 == TX Byte 1 ==
2693 05:56:25.496680 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2694 05:56:25.500041 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2695 05:56:25.500163 ==
2696 05:56:25.502974 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 05:56:25.506380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 05:56:25.506493 ==
2699 05:56:25.518852 TX Vref=22, minBit 5, minWin=25, winSum=419
2700 05:56:25.522624 TX Vref=24, minBit 1, minWin=26, winSum=427
2701 05:56:25.526056 TX Vref=26, minBit 0, minWin=27, winSum=440
2702 05:56:25.528836 TX Vref=28, minBit 0, minWin=27, winSum=441
2703 05:56:25.532412 TX Vref=30, minBit 1, minWin=27, winSum=439
2704 05:56:25.535284 TX Vref=32, minBit 1, minWin=26, winSum=432
2705 05:56:25.541919 [TxChooseVref] Worse bit 0, Min win 27, Win sum 441, Final Vref 28
2706 05:56:25.542034
2707 05:56:25.545588 Final TX Range 1 Vref 28
2708 05:56:25.545694
2709 05:56:25.545773 ==
2710 05:56:25.548879 Dram Type= 6, Freq= 0, CH_0, rank 0
2711 05:56:25.551870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2712 05:56:25.551982 ==
2713 05:56:25.555149
2714 05:56:25.555257
2715 05:56:25.555378 TX Vref Scan disable
2716 05:56:25.558603 == TX Byte 0 ==
2717 05:56:25.561988 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2718 05:56:25.565207 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2719 05:56:25.569014 == TX Byte 1 ==
2720 05:56:25.572341 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2721 05:56:25.575581 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2722 05:56:25.575698
2723 05:56:25.578778 [DATLAT]
2724 05:56:25.578889 Freq=1200, CH0 RK0
2725 05:56:25.579023
2726 05:56:25.581903 DATLAT Default: 0xd
2727 05:56:25.582012 0, 0xFFFF, sum = 0
2728 05:56:25.585425 1, 0xFFFF, sum = 0
2729 05:56:25.585581 2, 0xFFFF, sum = 0
2730 05:56:25.588787 3, 0xFFFF, sum = 0
2731 05:56:25.588897 4, 0xFFFF, sum = 0
2732 05:56:25.592134 5, 0xFFFF, sum = 0
2733 05:56:25.592244 6, 0xFFFF, sum = 0
2734 05:56:25.595443 7, 0xFFFF, sum = 0
2735 05:56:25.598915 8, 0xFFFF, sum = 0
2736 05:56:25.599029 9, 0xFFFF, sum = 0
2737 05:56:25.601983 10, 0xFFFF, sum = 0
2738 05:56:25.602094 11, 0xFFFF, sum = 0
2739 05:56:25.605277 12, 0x0, sum = 1
2740 05:56:25.605390 13, 0x0, sum = 2
2741 05:56:25.608616 14, 0x0, sum = 3
2742 05:56:25.608728 15, 0x0, sum = 4
2743 05:56:25.608824 best_step = 13
2744 05:56:25.608915
2745 05:56:25.612150 ==
2746 05:56:25.615385 Dram Type= 6, Freq= 0, CH_0, rank 0
2747 05:56:25.618912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2748 05:56:25.619026 ==
2749 05:56:25.619123 RX Vref Scan: 1
2750 05:56:25.619215
2751 05:56:25.621736 Set Vref Range= 32 -> 127
2752 05:56:25.621844
2753 05:56:25.625038 RX Vref 32 -> 127, step: 1
2754 05:56:25.625145
2755 05:56:25.628729 RX Delay -37 -> 252, step: 4
2756 05:56:25.628839
2757 05:56:25.632172 Set Vref, RX VrefLevel [Byte0]: 32
2758 05:56:25.635567 [Byte1]: 32
2759 05:56:25.635680
2760 05:56:25.638386 Set Vref, RX VrefLevel [Byte0]: 33
2761 05:56:25.641749 [Byte1]: 33
2762 05:56:25.645238
2763 05:56:25.645349 Set Vref, RX VrefLevel [Byte0]: 34
2764 05:56:25.648341 [Byte1]: 34
2765 05:56:25.653408
2766 05:56:25.653540 Set Vref, RX VrefLevel [Byte0]: 35
2767 05:56:25.656875 [Byte1]: 35
2768 05:56:25.661296
2769 05:56:25.661413 Set Vref, RX VrefLevel [Byte0]: 36
2770 05:56:25.664288 [Byte1]: 36
2771 05:56:25.669395
2772 05:56:25.669554 Set Vref, RX VrefLevel [Byte0]: 37
2773 05:56:25.672636 [Byte1]: 37
2774 05:56:25.677176
2775 05:56:25.677299 Set Vref, RX VrefLevel [Byte0]: 38
2776 05:56:25.680408 [Byte1]: 38
2777 05:56:25.685507
2778 05:56:25.685650 Set Vref, RX VrefLevel [Byte0]: 39
2779 05:56:25.688745 [Byte1]: 39
2780 05:56:25.693362
2781 05:56:25.693487 Set Vref, RX VrefLevel [Byte0]: 40
2782 05:56:25.696306 [Byte1]: 40
2783 05:56:25.701144
2784 05:56:25.701261 Set Vref, RX VrefLevel [Byte0]: 41
2785 05:56:25.704954 [Byte1]: 41
2786 05:56:25.709418
2787 05:56:25.709539 Set Vref, RX VrefLevel [Byte0]: 42
2788 05:56:25.715047 [Byte1]: 42
2789 05:56:25.717043
2790 05:56:25.717137 Set Vref, RX VrefLevel [Byte0]: 43
2791 05:56:25.720858 [Byte1]: 43
2792 05:56:25.725208
2793 05:56:25.725312 Set Vref, RX VrefLevel [Byte0]: 44
2794 05:56:25.728679 [Byte1]: 44
2795 05:56:25.733738
2796 05:56:25.733856 Set Vref, RX VrefLevel [Byte0]: 45
2797 05:56:25.736306 [Byte1]: 45
2798 05:56:25.741301
2799 05:56:25.741391 Set Vref, RX VrefLevel [Byte0]: 46
2800 05:56:25.744758 [Byte1]: 46
2801 05:56:25.749420
2802 05:56:25.749544 Set Vref, RX VrefLevel [Byte0]: 47
2803 05:56:25.752580 [Byte1]: 47
2804 05:56:25.757537
2805 05:56:25.757636 Set Vref, RX VrefLevel [Byte0]: 48
2806 05:56:25.760824 [Byte1]: 48
2807 05:56:25.765347
2808 05:56:25.765449 Set Vref, RX VrefLevel [Byte0]: 49
2809 05:56:25.768817 [Byte1]: 49
2810 05:56:25.773552
2811 05:56:25.773646 Set Vref, RX VrefLevel [Byte0]: 50
2812 05:56:25.776978 [Byte1]: 50
2813 05:56:25.781152
2814 05:56:25.781238 Set Vref, RX VrefLevel [Byte0]: 51
2815 05:56:25.784875 [Byte1]: 51
2816 05:56:25.789601
2817 05:56:25.789693 Set Vref, RX VrefLevel [Byte0]: 52
2818 05:56:25.792662 [Byte1]: 52
2819 05:56:25.797300
2820 05:56:25.797392 Set Vref, RX VrefLevel [Byte0]: 53
2821 05:56:25.800641 [Byte1]: 53
2822 05:56:25.805174
2823 05:56:25.805280 Set Vref, RX VrefLevel [Byte0]: 54
2824 05:56:25.808513 [Byte1]: 54
2825 05:56:25.813061
2826 05:56:25.813148 Set Vref, RX VrefLevel [Byte0]: 55
2827 05:56:25.816719 [Byte1]: 55
2828 05:56:25.821141
2829 05:56:25.821248 Set Vref, RX VrefLevel [Byte0]: 56
2830 05:56:25.824394 [Byte1]: 56
2831 05:56:25.829111
2832 05:56:25.829218 Set Vref, RX VrefLevel [Byte0]: 57
2833 05:56:25.832634 [Byte1]: 57
2834 05:56:25.837316
2835 05:56:25.837406 Set Vref, RX VrefLevel [Byte0]: 58
2836 05:56:25.840685 [Byte1]: 58
2837 05:56:25.845442
2838 05:56:25.845576 Set Vref, RX VrefLevel [Byte0]: 59
2839 05:56:25.848769 [Byte1]: 59
2840 05:56:25.853348
2841 05:56:25.853464 Set Vref, RX VrefLevel [Byte0]: 60
2842 05:56:25.856586 [Byte1]: 60
2843 05:56:25.861279
2844 05:56:25.861395 Set Vref, RX VrefLevel [Byte0]: 61
2845 05:56:25.864581 [Byte1]: 61
2846 05:56:25.869320
2847 05:56:25.869434 Set Vref, RX VrefLevel [Byte0]: 62
2848 05:56:25.872820 [Byte1]: 62
2849 05:56:25.877482
2850 05:56:25.877633 Set Vref, RX VrefLevel [Byte0]: 63
2851 05:56:25.880362 [Byte1]: 63
2852 05:56:25.885431
2853 05:56:25.885588 Set Vref, RX VrefLevel [Byte0]: 64
2854 05:56:25.888693 [Byte1]: 64
2855 05:56:25.893261
2856 05:56:25.893370 Set Vref, RX VrefLevel [Byte0]: 65
2857 05:56:25.896522 [Byte1]: 65
2858 05:56:25.901252
2859 05:56:25.901346 Set Vref, RX VrefLevel [Byte0]: 66
2860 05:56:25.904622 [Byte1]: 66
2861 05:56:25.909247
2862 05:56:25.909336 Set Vref, RX VrefLevel [Byte0]: 67
2863 05:56:25.912623 [Byte1]: 67
2864 05:56:25.917080
2865 05:56:25.917186 Set Vref, RX VrefLevel [Byte0]: 68
2866 05:56:25.920406 [Byte1]: 68
2867 05:56:25.925486
2868 05:56:25.925599 Set Vref, RX VrefLevel [Byte0]: 69
2869 05:56:25.928399 [Byte1]: 69
2870 05:56:25.933439
2871 05:56:25.933538 Set Vref, RX VrefLevel [Byte0]: 70
2872 05:56:25.936870 [Byte1]: 70
2873 05:56:25.941344
2874 05:56:25.941437 Set Vref, RX VrefLevel [Byte0]: 71
2875 05:56:25.944499 [Byte1]: 71
2876 05:56:25.949317
2877 05:56:25.949423 Set Vref, RX VrefLevel [Byte0]: 72
2878 05:56:25.952839 [Byte1]: 72
2879 05:56:25.957431
2880 05:56:25.957546 Set Vref, RX VrefLevel [Byte0]: 73
2881 05:56:25.960707 [Byte1]: 73
2882 05:56:25.965322
2883 05:56:25.965430 Final RX Vref Byte 0 = 63 to rank0
2884 05:56:25.968403 Final RX Vref Byte 1 = 47 to rank0
2885 05:56:25.971810 Final RX Vref Byte 0 = 63 to rank1
2886 05:56:25.975304 Final RX Vref Byte 1 = 47 to rank1==
2887 05:56:25.978745 Dram Type= 6, Freq= 0, CH_0, rank 0
2888 05:56:25.985028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 05:56:25.985129 ==
2890 05:56:25.985230 DQS Delay:
2891 05:56:25.985328 DQS0 = 0, DQS1 = 0
2892 05:56:25.988341 DQM Delay:
2893 05:56:25.988440 DQM0 = 112, DQM1 = 98
2894 05:56:25.991763 DQ Delay:
2895 05:56:25.995129 DQ0 =110, DQ1 =112, DQ2 =114, DQ3 =106
2896 05:56:25.998766 DQ4 =114, DQ5 =104, DQ6 =118, DQ7 =120
2897 05:56:26.001797 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2898 05:56:26.005463 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2899 05:56:26.005586
2900 05:56:26.005671
2901 05:56:26.011908 [DQSOSCAuto] RK0, (LSB)MR18= 0xffff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2902 05:56:26.015375 CH0 RK0: MR19=303, MR18=FFFF
2903 05:56:26.021708 CH0_RK0: MR19=0x303, MR18=0xFFFF, DQSOSC=410, MR23=63, INC=39, DEC=26
2904 05:56:26.021815
2905 05:56:26.025671 ----->DramcWriteLeveling(PI) begin...
2906 05:56:26.025788 ==
2907 05:56:26.028617 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 05:56:26.031735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 05:56:26.031826 ==
2910 05:56:26.035179 Write leveling (Byte 0): 33 => 33
2911 05:56:26.038609 Write leveling (Byte 1): 31 => 31
2912 05:56:26.041841 DramcWriteLeveling(PI) end<-----
2913 05:56:26.041974
2914 05:56:26.042060 ==
2915 05:56:26.045128 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 05:56:26.048440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 05:56:26.052318 ==
2918 05:56:26.052408 [Gating] SW mode calibration
2919 05:56:26.061768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2920 05:56:26.065217 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2921 05:56:26.068497 0 15 0 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
2922 05:56:26.075468 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 05:56:26.078323 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 05:56:26.081970 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 05:56:26.088796 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 05:56:26.091695 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 05:56:26.095578 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2928 05:56:26.101808 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
2929 05:56:26.105198 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2930 05:56:26.108987 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 05:56:26.115260 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 05:56:26.118825 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 05:56:26.121995 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 05:56:26.128385 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 05:56:26.131670 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2936 05:56:26.135365 1 0 28 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
2937 05:56:26.141594 1 1 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2938 05:56:26.144941 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 05:56:26.148558 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 05:56:26.151550 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 05:56:26.158282 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 05:56:26.161697 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 05:56:26.165180 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 05:56:26.171820 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2945 05:56:26.175389 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2946 05:56:26.178854 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 05:56:26.185000 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 05:56:26.188627 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 05:56:26.191526 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 05:56:26.198672 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 05:56:26.201589 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 05:56:26.205057 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 05:56:26.211809 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 05:56:26.215019 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 05:56:26.218425 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 05:56:26.225156 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 05:56:26.228251 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 05:56:26.232068 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 05:56:26.238805 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 05:56:26.241851 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2961 05:56:26.245125 Total UI for P1: 0, mck2ui 16
2962 05:56:26.248504 best dqsien dly found for B0: ( 1, 3, 26)
2963 05:56:26.251708 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2964 05:56:26.255404 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 05:56:26.258466 Total UI for P1: 0, mck2ui 16
2966 05:56:26.261945 best dqsien dly found for B1: ( 1, 3, 30)
2967 05:56:26.265266 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2968 05:56:26.268749 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2969 05:56:26.271436
2970 05:56:26.275197 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2971 05:56:26.278552 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2972 05:56:26.281390 [Gating] SW calibration Done
2973 05:56:26.281543 ==
2974 05:56:26.284797 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 05:56:26.288335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 05:56:26.288449 ==
2977 05:56:26.288543 RX Vref Scan: 0
2978 05:56:26.291668
2979 05:56:26.291777 RX Vref 0 -> 0, step: 1
2980 05:56:26.291871
2981 05:56:26.295148 RX Delay -40 -> 252, step: 8
2982 05:56:26.298396 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2983 05:56:26.301631 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2984 05:56:26.308195 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2985 05:56:26.311963 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2986 05:56:26.315201 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
2987 05:56:26.318496 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2988 05:56:26.321409 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2989 05:56:26.328127 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2990 05:56:26.331481 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2991 05:56:26.334859 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2992 05:56:26.338342 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2993 05:56:26.341415 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2994 05:56:26.344912 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2995 05:56:26.351801 iDelay=200, Bit 13, Center 103 (32 ~ 175) 144
2996 05:56:26.355275 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2997 05:56:26.358443 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2998 05:56:26.358556 ==
2999 05:56:26.361739 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 05:56:26.365213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 05:56:26.368659 ==
3002 05:56:26.368770 DQS Delay:
3003 05:56:26.368862 DQS0 = 0, DQS1 = 0
3004 05:56:26.371570 DQM Delay:
3005 05:56:26.371677 DQM0 = 111, DQM1 = 100
3006 05:56:26.375019 DQ Delay:
3007 05:56:26.378364 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
3008 05:56:26.381710 DQ4 =111, DQ5 =99, DQ6 =119, DQ7 =123
3009 05:56:26.384673 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3010 05:56:26.388111 DQ12 =107, DQ13 =103, DQ14 =111, DQ15 =111
3011 05:56:26.388224
3012 05:56:26.388318
3013 05:56:26.388407 ==
3014 05:56:26.391453 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 05:56:26.394897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 05:56:26.395008 ==
3017 05:56:26.395100
3018 05:56:26.395191
3019 05:56:26.398409 TX Vref Scan disable
3020 05:56:26.401229 == TX Byte 0 ==
3021 05:56:26.404595 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3022 05:56:26.408072 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3023 05:56:26.411426 == TX Byte 1 ==
3024 05:56:26.414609 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3025 05:56:26.417974 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3026 05:56:26.418120 ==
3027 05:56:26.421089 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 05:56:26.424857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 05:56:26.427985 ==
3030 05:56:26.438282 TX Vref=22, minBit 2, minWin=26, winSum=430
3031 05:56:26.441625 TX Vref=24, minBit 0, minWin=27, winSum=433
3032 05:56:26.445215 TX Vref=26, minBit 0, minWin=27, winSum=440
3033 05:56:26.448284 TX Vref=28, minBit 1, minWin=27, winSum=442
3034 05:56:26.451874 TX Vref=30, minBit 1, minWin=27, winSum=446
3035 05:56:26.454902 TX Vref=32, minBit 1, minWin=27, winSum=444
3036 05:56:26.461697 [TxChooseVref] Worse bit 1, Min win 27, Win sum 446, Final Vref 30
3037 05:56:26.461838
3038 05:56:26.464837 Final TX Range 1 Vref 30
3039 05:56:26.464925
3040 05:56:26.464990 ==
3041 05:56:26.468126 Dram Type= 6, Freq= 0, CH_0, rank 1
3042 05:56:26.471665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 05:56:26.471753 ==
3044 05:56:26.471818
3045 05:56:26.471877
3046 05:56:26.475250 TX Vref Scan disable
3047 05:56:26.478152 == TX Byte 0 ==
3048 05:56:26.481468 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3049 05:56:26.484956 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3050 05:56:26.488412 == TX Byte 1 ==
3051 05:56:26.491879 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3052 05:56:26.494859 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3053 05:56:26.494948
3054 05:56:26.498186 [DATLAT]
3055 05:56:26.498271 Freq=1200, CH0 RK1
3056 05:56:26.498337
3057 05:56:26.501665 DATLAT Default: 0xd
3058 05:56:26.501751 0, 0xFFFF, sum = 0
3059 05:56:26.505117 1, 0xFFFF, sum = 0
3060 05:56:26.505202 2, 0xFFFF, sum = 0
3061 05:56:26.508669 3, 0xFFFF, sum = 0
3062 05:56:26.508756 4, 0xFFFF, sum = 0
3063 05:56:26.511561 5, 0xFFFF, sum = 0
3064 05:56:26.511652 6, 0xFFFF, sum = 0
3065 05:56:26.515071 7, 0xFFFF, sum = 0
3066 05:56:26.515161 8, 0xFFFF, sum = 0
3067 05:56:26.518266 9, 0xFFFF, sum = 0
3068 05:56:26.521765 10, 0xFFFF, sum = 0
3069 05:56:26.521854 11, 0xFFFF, sum = 0
3070 05:56:26.525183 12, 0x0, sum = 1
3071 05:56:26.525269 13, 0x0, sum = 2
3072 05:56:26.525335 14, 0x0, sum = 3
3073 05:56:26.528567 15, 0x0, sum = 4
3074 05:56:26.528663 best_step = 13
3075 05:56:26.528729
3076 05:56:26.528789 ==
3077 05:56:26.532061 Dram Type= 6, Freq= 0, CH_0, rank 1
3078 05:56:26.538471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 05:56:26.538584 ==
3080 05:56:26.538654 RX Vref Scan: 0
3081 05:56:26.538715
3082 05:56:26.541556 RX Vref 0 -> 0, step: 1
3083 05:56:26.541683
3084 05:56:26.544836 RX Delay -37 -> 252, step: 4
3085 05:56:26.548473 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3086 05:56:26.551479 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3087 05:56:26.558531 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3088 05:56:26.561963 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3089 05:56:26.565152 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3090 05:56:26.568444 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3091 05:56:26.571763 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3092 05:56:26.578444 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3093 05:56:26.581959 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3094 05:56:26.585362 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3095 05:56:26.588451 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3096 05:56:26.591935 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3097 05:56:26.598171 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3098 05:56:26.601722 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3099 05:56:26.605181 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3100 05:56:26.608561 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3101 05:56:26.608687 ==
3102 05:56:26.611576 Dram Type= 6, Freq= 0, CH_0, rank 1
3103 05:56:26.614919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 05:56:26.618402 ==
3105 05:56:26.618522 DQS Delay:
3106 05:56:26.618588 DQS0 = 0, DQS1 = 0
3107 05:56:26.621543 DQM Delay:
3108 05:56:26.621660 DQM0 = 111, DQM1 = 99
3109 05:56:26.624942 DQ Delay:
3110 05:56:26.628495 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3111 05:56:26.631901 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3112 05:56:26.635444 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3113 05:56:26.638497 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3114 05:56:26.638622
3115 05:56:26.638688
3116 05:56:26.645459 [DQSOSCAuto] RK1, (LSB)MR18= 0x12fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3117 05:56:26.648895 CH0 RK1: MR19=403, MR18=12FB
3118 05:56:26.655748 CH0_RK1: MR19=0x403, MR18=0x12FB, DQSOSC=403, MR23=63, INC=40, DEC=26
3119 05:56:26.658563 [RxdqsGatingPostProcess] freq 1200
3120 05:56:26.661968 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3121 05:56:26.665775 best DQS0 dly(2T, 0.5T) = (0, 11)
3122 05:56:26.668631 best DQS1 dly(2T, 0.5T) = (0, 12)
3123 05:56:26.671818 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3124 05:56:26.675439 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3125 05:56:26.678479 best DQS0 dly(2T, 0.5T) = (0, 11)
3126 05:56:26.681941 best DQS1 dly(2T, 0.5T) = (0, 11)
3127 05:56:26.685419 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3128 05:56:26.688578 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3129 05:56:26.692104 Pre-setting of DQS Precalculation
3130 05:56:26.695417 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3131 05:56:26.698690 ==
3132 05:56:26.698776 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 05:56:26.705452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 05:56:26.705549 ==
3135 05:56:26.708563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3136 05:56:26.715424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3137 05:56:26.724025 [CA 0] Center 37 (7~67) winsize 61
3138 05:56:26.727880 [CA 1] Center 38 (8~68) winsize 61
3139 05:56:26.730797 [CA 2] Center 34 (4~64) winsize 61
3140 05:56:26.734220 [CA 3] Center 34 (4~64) winsize 61
3141 05:56:26.737673 [CA 4] Center 34 (4~64) winsize 61
3142 05:56:26.741184 [CA 5] Center 33 (3~63) winsize 61
3143 05:56:26.741266
3144 05:56:26.744079 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3145 05:56:26.744160
3146 05:56:26.747626 [CATrainingPosCal] consider 1 rank data
3147 05:56:26.751049 u2DelayCellTimex100 = 270/100 ps
3148 05:56:26.754353 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3149 05:56:26.757869 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3150 05:56:26.764704 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 05:56:26.767448 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3152 05:56:26.770747 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3153 05:56:26.774140 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3154 05:56:26.774223
3155 05:56:26.777628 CA PerBit enable=1, Macro0, CA PI delay=33
3156 05:56:26.777710
3157 05:56:26.780489 [CBTSetCACLKResult] CA Dly = 33
3158 05:56:26.780571 CS Dly: 6 (0~37)
3159 05:56:26.784205 ==
3160 05:56:26.784286 Dram Type= 6, Freq= 0, CH_1, rank 1
3161 05:56:26.790866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 05:56:26.790949 ==
3163 05:56:26.794073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3164 05:56:26.800854 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3165 05:56:26.809798 [CA 0] Center 37 (8~67) winsize 60
3166 05:56:26.813139 [CA 1] Center 37 (7~68) winsize 62
3167 05:56:26.816564 [CA 2] Center 34 (4~65) winsize 62
3168 05:56:26.819956 [CA 3] Center 33 (3~64) winsize 62
3169 05:56:26.822915 [CA 4] Center 34 (4~65) winsize 62
3170 05:56:26.826415 [CA 5] Center 32 (2~63) winsize 62
3171 05:56:26.826496
3172 05:56:26.829892 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3173 05:56:26.829974
3174 05:56:26.833225 [CATrainingPosCal] consider 2 rank data
3175 05:56:26.836520 u2DelayCellTimex100 = 270/100 ps
3176 05:56:26.839967 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3177 05:56:26.843424 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3178 05:56:26.849736 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3179 05:56:26.853377 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3180 05:56:26.856761 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3181 05:56:26.860276 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3182 05:56:26.860358
3183 05:56:26.863221 CA PerBit enable=1, Macro0, CA PI delay=33
3184 05:56:26.863302
3185 05:56:26.866479 [CBTSetCACLKResult] CA Dly = 33
3186 05:56:26.866561 CS Dly: 7 (0~40)
3187 05:56:26.866625
3188 05:56:26.869842 ----->DramcWriteLeveling(PI) begin...
3189 05:56:26.873048 ==
3190 05:56:26.873129 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 05:56:26.879767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 05:56:26.879851 ==
3193 05:56:26.883275 Write leveling (Byte 0): 24 => 24
3194 05:56:26.886859 Write leveling (Byte 1): 28 => 28
3195 05:56:26.889632 DramcWriteLeveling(PI) end<-----
3196 05:56:26.889713
3197 05:56:26.889778 ==
3198 05:56:26.893333 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 05:56:26.896531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 05:56:26.896614 ==
3201 05:56:26.899659 [Gating] SW mode calibration
3202 05:56:26.906403 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3203 05:56:26.909774 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3204 05:56:26.916303 0 15 0 | B1->B0 | 2e2e 2a2a | 0 1 | (0 0) (1 1)
3205 05:56:26.919830 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 05:56:26.922901 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 05:56:26.930062 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 05:56:26.932893 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 05:56:26.936368 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 05:56:26.942992 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 05:56:26.946543 0 15 28 | B1->B0 | 3131 3131 | 0 0 | (0 0) (0 1)
3212 05:56:26.949443 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 05:56:26.956134 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 05:56:26.959623 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 05:56:26.963033 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 05:56:26.969540 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 05:56:26.972881 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 05:56:26.976193 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 05:56:26.982846 1 0 28 | B1->B0 | 3e3e 3f3f | 0 0 | (0 0) (0 0)
3220 05:56:26.986310 1 1 0 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
3221 05:56:26.989781 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 05:56:26.996222 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 05:56:26.999454 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 05:56:27.002733 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 05:56:27.009703 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 05:56:27.012622 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 05:56:27.016190 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3228 05:56:27.022772 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3229 05:56:27.026067 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 05:56:27.029797 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 05:56:27.032793 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 05:56:27.039733 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 05:56:27.042587 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 05:56:27.046009 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 05:56:27.052778 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 05:56:27.056424 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 05:56:27.059765 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 05:56:27.066202 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 05:56:27.069535 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 05:56:27.072491 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 05:56:27.079350 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 05:56:27.082868 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 05:56:27.086182 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3244 05:56:27.092778 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3245 05:56:27.092885 Total UI for P1: 0, mck2ui 16
3246 05:56:27.099391 best dqsien dly found for B0: ( 1, 3, 28)
3247 05:56:27.099471 Total UI for P1: 0, mck2ui 16
3248 05:56:27.102697 best dqsien dly found for B1: ( 1, 3, 30)
3249 05:56:27.109367 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3250 05:56:27.112728 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3251 05:56:27.112808
3252 05:56:27.116292 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3253 05:56:27.119631 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3254 05:56:27.122903 [Gating] SW calibration Done
3255 05:56:27.122982 ==
3256 05:56:27.126384 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 05:56:27.129745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 05:56:27.129828 ==
3259 05:56:27.129892 RX Vref Scan: 0
3260 05:56:27.132729
3261 05:56:27.132810 RX Vref 0 -> 0, step: 1
3262 05:56:27.132874
3263 05:56:27.136608 RX Delay -40 -> 252, step: 8
3264 05:56:27.139372 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3265 05:56:27.142979 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3266 05:56:27.149468 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3267 05:56:27.152783 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3268 05:56:27.156244 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3269 05:56:27.159675 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3270 05:56:27.163225 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3271 05:56:27.169468 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3272 05:56:27.172914 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3273 05:56:27.176168 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3274 05:56:27.179698 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3275 05:56:27.183020 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3276 05:56:27.189767 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3277 05:56:27.192601 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3278 05:56:27.196280 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3279 05:56:27.199761 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3280 05:56:27.199843 ==
3281 05:56:27.202634 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 05:56:27.206049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 05:56:27.209410 ==
3284 05:56:27.209518 DQS Delay:
3285 05:56:27.209585 DQS0 = 0, DQS1 = 0
3286 05:56:27.212754 DQM Delay:
3287 05:56:27.212835 DQM0 = 113, DQM1 = 104
3288 05:56:27.216162 DQ Delay:
3289 05:56:27.219528 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =115
3290 05:56:27.222779 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3291 05:56:27.225871 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3292 05:56:27.229648 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3293 05:56:27.229729
3294 05:56:27.229793
3295 05:56:27.229852 ==
3296 05:56:27.232771 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 05:56:27.236153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 05:56:27.236235 ==
3299 05:56:27.236300
3300 05:56:27.236359
3301 05:56:27.239400 TX Vref Scan disable
3302 05:56:27.242908 == TX Byte 0 ==
3303 05:56:27.246323 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3304 05:56:27.249226 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3305 05:56:27.253037 == TX Byte 1 ==
3306 05:56:27.256103 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3307 05:56:27.260998 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3308 05:56:27.261099 ==
3309 05:56:27.262617 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 05:56:27.266022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 05:56:27.269581 ==
3312 05:56:27.279782 TX Vref=22, minBit 8, minWin=24, winSum=402
3313 05:56:27.283256 TX Vref=24, minBit 11, minWin=24, winSum=412
3314 05:56:27.286168 TX Vref=26, minBit 10, minWin=24, winSum=417
3315 05:56:27.289772 TX Vref=28, minBit 9, minWin=25, winSum=416
3316 05:56:27.292968 TX Vref=30, minBit 9, minWin=25, winSum=423
3317 05:56:27.299278 TX Vref=32, minBit 9, minWin=24, winSum=420
3318 05:56:27.303177 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 30
3319 05:56:27.303269
3320 05:56:27.306458 Final TX Range 1 Vref 30
3321 05:56:27.306543
3322 05:56:27.306607 ==
3323 05:56:27.309354 Dram Type= 6, Freq= 0, CH_1, rank 0
3324 05:56:27.312784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3325 05:56:27.316052 ==
3326 05:56:27.316140
3327 05:56:27.316206
3328 05:56:27.316265 TX Vref Scan disable
3329 05:56:27.319619 == TX Byte 0 ==
3330 05:56:27.323036 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3331 05:56:27.326496 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3332 05:56:27.329434 == TX Byte 1 ==
3333 05:56:27.332758 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3334 05:56:27.336177 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3335 05:56:27.339837
3336 05:56:27.339929 [DATLAT]
3337 05:56:27.339996 Freq=1200, CH1 RK0
3338 05:56:27.340061
3339 05:56:27.342816 DATLAT Default: 0xd
3340 05:56:27.342898 0, 0xFFFF, sum = 0
3341 05:56:27.346247 1, 0xFFFF, sum = 0
3342 05:56:27.346330 2, 0xFFFF, sum = 0
3343 05:56:27.349812 3, 0xFFFF, sum = 0
3344 05:56:27.353031 4, 0xFFFF, sum = 0
3345 05:56:27.353114 5, 0xFFFF, sum = 0
3346 05:56:27.355925 6, 0xFFFF, sum = 0
3347 05:56:27.356009 7, 0xFFFF, sum = 0
3348 05:56:27.359440 8, 0xFFFF, sum = 0
3349 05:56:27.359523 9, 0xFFFF, sum = 0
3350 05:56:27.362698 10, 0xFFFF, sum = 0
3351 05:56:27.362781 11, 0xFFFF, sum = 0
3352 05:56:27.366193 12, 0x0, sum = 1
3353 05:56:27.366276 13, 0x0, sum = 2
3354 05:56:27.369699 14, 0x0, sum = 3
3355 05:56:27.369783 15, 0x0, sum = 4
3356 05:56:27.369847 best_step = 13
3357 05:56:27.372502
3358 05:56:27.372583 ==
3359 05:56:27.376412 Dram Type= 6, Freq= 0, CH_1, rank 0
3360 05:56:27.379300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3361 05:56:27.379389 ==
3362 05:56:27.379454 RX Vref Scan: 1
3363 05:56:27.379514
3364 05:56:27.382779 Set Vref Range= 32 -> 127
3365 05:56:27.382861
3366 05:56:27.386129 RX Vref 32 -> 127, step: 1
3367 05:56:27.386210
3368 05:56:27.389615 RX Delay -21 -> 252, step: 4
3369 05:56:27.389697
3370 05:56:27.392493 Set Vref, RX VrefLevel [Byte0]: 32
3371 05:56:27.395982 [Byte1]: 32
3372 05:56:27.396063
3373 05:56:27.399400 Set Vref, RX VrefLevel [Byte0]: 33
3374 05:56:27.402753 [Byte1]: 33
3375 05:56:27.406287
3376 05:56:27.406371 Set Vref, RX VrefLevel [Byte0]: 34
3377 05:56:27.409401 [Byte1]: 34
3378 05:56:27.413962
3379 05:56:27.414130 Set Vref, RX VrefLevel [Byte0]: 35
3380 05:56:27.417335 [Byte1]: 35
3381 05:56:27.421774
3382 05:56:27.421940 Set Vref, RX VrefLevel [Byte0]: 36
3383 05:56:27.425256 [Byte1]: 36
3384 05:56:27.429836
3385 05:56:27.430002 Set Vref, RX VrefLevel [Byte0]: 37
3386 05:56:27.433237 [Byte1]: 37
3387 05:56:27.437632
3388 05:56:27.437778 Set Vref, RX VrefLevel [Byte0]: 38
3389 05:56:27.441011 [Byte1]: 38
3390 05:56:27.445366
3391 05:56:27.445538 Set Vref, RX VrefLevel [Byte0]: 39
3392 05:56:27.449120 [Byte1]: 39
3393 05:56:27.453773
3394 05:56:27.453931 Set Vref, RX VrefLevel [Byte0]: 40
3395 05:56:27.456924 [Byte1]: 40
3396 05:56:27.461349
3397 05:56:27.461518 Set Vref, RX VrefLevel [Byte0]: 41
3398 05:56:27.464899 [Byte1]: 41
3399 05:56:27.469429
3400 05:56:27.469612 Set Vref, RX VrefLevel [Byte0]: 42
3401 05:56:27.472567 [Byte1]: 42
3402 05:56:27.477309
3403 05:56:27.477427 Set Vref, RX VrefLevel [Byte0]: 43
3404 05:56:27.480422 [Byte1]: 43
3405 05:56:27.485340
3406 05:56:27.485449 Set Vref, RX VrefLevel [Byte0]: 44
3407 05:56:27.488281 [Byte1]: 44
3408 05:56:27.492912
3409 05:56:27.493010 Set Vref, RX VrefLevel [Byte0]: 45
3410 05:56:27.496407 [Byte1]: 45
3411 05:56:27.501092
3412 05:56:27.501232 Set Vref, RX VrefLevel [Byte0]: 46
3413 05:56:27.504454 [Byte1]: 46
3414 05:56:27.508978
3415 05:56:27.509077 Set Vref, RX VrefLevel [Byte0]: 47
3416 05:56:27.512414 [Byte1]: 47
3417 05:56:27.517168
3418 05:56:27.517252 Set Vref, RX VrefLevel [Byte0]: 48
3419 05:56:27.520150 [Byte1]: 48
3420 05:56:27.525016
3421 05:56:27.525098 Set Vref, RX VrefLevel [Byte0]: 49
3422 05:56:27.527965 [Byte1]: 49
3423 05:56:27.532594
3424 05:56:27.532686 Set Vref, RX VrefLevel [Byte0]: 50
3425 05:56:27.536078 [Byte1]: 50
3426 05:56:27.540625
3427 05:56:27.540715 Set Vref, RX VrefLevel [Byte0]: 51
3428 05:56:27.543770 [Byte1]: 51
3429 05:56:27.548469
3430 05:56:27.548551 Set Vref, RX VrefLevel [Byte0]: 52
3431 05:56:27.551759 [Byte1]: 52
3432 05:56:27.556284
3433 05:56:27.556377 Set Vref, RX VrefLevel [Byte0]: 53
3434 05:56:27.560110 [Byte1]: 53
3435 05:56:27.564252
3436 05:56:27.564406 Set Vref, RX VrefLevel [Byte0]: 54
3437 05:56:27.567884 [Byte1]: 54
3438 05:56:27.572503
3439 05:56:27.572660 Set Vref, RX VrefLevel [Byte0]: 55
3440 05:56:27.575452 [Byte1]: 55
3441 05:56:27.580268
3442 05:56:27.580401 Set Vref, RX VrefLevel [Byte0]: 56
3443 05:56:27.583588 [Byte1]: 56
3444 05:56:27.588186
3445 05:56:27.588307 Set Vref, RX VrefLevel [Byte0]: 57
3446 05:56:27.591319 [Byte1]: 57
3447 05:56:27.595993
3448 05:56:27.596099 Set Vref, RX VrefLevel [Byte0]: 58
3449 05:56:27.599439 [Byte1]: 58
3450 05:56:27.604020
3451 05:56:27.604148 Set Vref, RX VrefLevel [Byte0]: 59
3452 05:56:27.607404 [Byte1]: 59
3453 05:56:27.612040
3454 05:56:27.612174 Set Vref, RX VrefLevel [Byte0]: 60
3455 05:56:27.615380 [Byte1]: 60
3456 05:56:27.619751
3457 05:56:27.619877 Set Vref, RX VrefLevel [Byte0]: 61
3458 05:56:27.623484 [Byte1]: 61
3459 05:56:27.627897
3460 05:56:27.628003 Set Vref, RX VrefLevel [Byte0]: 62
3461 05:56:27.630834 [Byte1]: 62
3462 05:56:27.635493
3463 05:56:27.635631 Set Vref, RX VrefLevel [Byte0]: 63
3464 05:56:27.638852 [Byte1]: 63
3465 05:56:27.643539
3466 05:56:27.643677 Set Vref, RX VrefLevel [Byte0]: 64
3467 05:56:27.646765 [Byte1]: 64
3468 05:56:27.651492
3469 05:56:27.651590 Set Vref, RX VrefLevel [Byte0]: 65
3470 05:56:27.654854 [Byte1]: 65
3471 05:56:27.659335
3472 05:56:27.659436 Set Vref, RX VrefLevel [Byte0]: 66
3473 05:56:27.662815 [Byte1]: 66
3474 05:56:27.667333
3475 05:56:27.667473 Set Vref, RX VrefLevel [Byte0]: 67
3476 05:56:27.670692 [Byte1]: 67
3477 05:56:27.675448
3478 05:56:27.675702 Final RX Vref Byte 0 = 55 to rank0
3479 05:56:27.678622 Final RX Vref Byte 1 = 51 to rank0
3480 05:56:27.681741 Final RX Vref Byte 0 = 55 to rank1
3481 05:56:27.685127 Final RX Vref Byte 1 = 51 to rank1==
3482 05:56:27.688530 Dram Type= 6, Freq= 0, CH_1, rank 0
3483 05:56:27.695528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 05:56:27.695616 ==
3485 05:56:27.695682 DQS Delay:
3486 05:56:27.695741 DQS0 = 0, DQS1 = 0
3487 05:56:27.698616 DQM Delay:
3488 05:56:27.698698 DQM0 = 114, DQM1 = 105
3489 05:56:27.701814 DQ Delay:
3490 05:56:27.705418 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =112
3491 05:56:27.708951 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3492 05:56:27.711742 DQ8 =92, DQ9 =98, DQ10 =104, DQ11 =100
3493 05:56:27.715221 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =110
3494 05:56:27.715303
3495 05:56:27.715367
3496 05:56:27.724961 [DQSOSCAuto] RK0, (LSB)MR18= 0xeff6, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3497 05:56:27.725053 CH1 RK0: MR19=303, MR18=EFF6
3498 05:56:27.731814 CH1_RK0: MR19=0x303, MR18=0xEFF6, DQSOSC=414, MR23=63, INC=38, DEC=25
3499 05:56:27.731899
3500 05:56:27.735254 ----->DramcWriteLeveling(PI) begin...
3501 05:56:27.735338 ==
3502 05:56:27.738702 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 05:56:27.741463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3504 05:56:27.745067 ==
3505 05:56:27.745148 Write leveling (Byte 0): 25 => 25
3506 05:56:27.748391 Write leveling (Byte 1): 27 => 27
3507 05:56:27.751771 DramcWriteLeveling(PI) end<-----
3508 05:56:27.751853
3509 05:56:27.751916 ==
3510 05:56:27.755097 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 05:56:27.761918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 05:56:27.762004 ==
3513 05:56:27.764711 [Gating] SW mode calibration
3514 05:56:27.771721 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3515 05:56:27.775022 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3516 05:56:27.781744 0 15 0 | B1->B0 | 3434 3535 | 1 1 | (0 0) (0 0)
3517 05:56:27.785148 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 05:56:27.788235 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 05:56:27.791902 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 05:56:27.798874 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 05:56:27.802015 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3522 05:56:27.805098 0 15 24 | B1->B0 | 3333 2424 | 0 0 | (0 1) (1 0)
3523 05:56:27.811783 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3524 05:56:27.815107 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 05:56:27.818605 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 05:56:27.824856 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 05:56:27.828444 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 05:56:27.831786 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 05:56:27.838371 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3530 05:56:27.841457 1 0 24 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
3531 05:56:27.844824 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3532 05:56:27.851597 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 05:56:27.855064 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 05:56:27.858416 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 05:56:27.864782 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 05:56:27.868214 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 05:56:27.871695 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3538 05:56:27.878483 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3539 05:56:27.881833 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3540 05:56:27.885005 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 05:56:27.891377 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 05:56:27.894736 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 05:56:27.897870 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 05:56:27.904463 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 05:56:27.908194 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 05:56:27.911320 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 05:56:27.918044 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 05:56:27.921420 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 05:56:27.924724 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 05:56:27.930929 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 05:56:27.934402 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 05:56:27.937839 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 05:56:27.941330 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3554 05:56:27.947446 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3555 05:56:27.950980 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3556 05:56:27.954504 Total UI for P1: 0, mck2ui 16
3557 05:56:27.957813 best dqsien dly found for B0: ( 1, 3, 22)
3558 05:56:27.961185 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 05:56:27.964052 Total UI for P1: 0, mck2ui 16
3560 05:56:27.967336 best dqsien dly found for B1: ( 1, 3, 26)
3561 05:56:27.970928 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3562 05:56:27.977739 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3563 05:56:27.977889
3564 05:56:27.980523 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3565 05:56:27.984063 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3566 05:56:27.987431 [Gating] SW calibration Done
3567 05:56:27.987530 ==
3568 05:56:27.990692 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 05:56:27.994274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 05:56:27.994373 ==
3571 05:56:27.997080 RX Vref Scan: 0
3572 05:56:27.997179
3573 05:56:27.997259 RX Vref 0 -> 0, step: 1
3574 05:56:27.997336
3575 05:56:28.000443 RX Delay -40 -> 252, step: 8
3576 05:56:28.003650 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3577 05:56:28.010681 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3578 05:56:28.013683 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3579 05:56:28.017098 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3580 05:56:28.020409 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3581 05:56:28.023924 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3582 05:56:28.026853 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3583 05:56:28.033637 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3584 05:56:28.036948 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3585 05:56:28.040417 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3586 05:56:28.043989 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3587 05:56:28.047466 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3588 05:56:28.053454 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3589 05:56:28.057254 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3590 05:56:28.060499 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3591 05:56:28.063433 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3592 05:56:28.063530 ==
3593 05:56:28.066890 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 05:56:28.073462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 05:56:28.073621 ==
3596 05:56:28.073688 DQS Delay:
3597 05:56:28.077088 DQS0 = 0, DQS1 = 0
3598 05:56:28.077211 DQM Delay:
3599 05:56:28.077316 DQM0 = 110, DQM1 = 107
3600 05:56:28.080522 DQ Delay:
3601 05:56:28.083375 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3602 05:56:28.086741 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3603 05:56:28.090075 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3604 05:56:28.093309 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3605 05:56:28.093416
3606 05:56:28.093541
3607 05:56:28.093603 ==
3608 05:56:28.096781 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 05:56:28.099757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 05:56:28.103176 ==
3611 05:56:28.103271
3612 05:56:28.103363
3613 05:56:28.103452 TX Vref Scan disable
3614 05:56:28.106601 == TX Byte 0 ==
3615 05:56:28.109708 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3616 05:56:28.113191 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3617 05:56:28.116469 == TX Byte 1 ==
3618 05:56:28.119842 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3619 05:56:28.123314 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3620 05:56:28.123415 ==
3621 05:56:28.126679 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 05:56:28.133141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 05:56:28.133251 ==
3624 05:56:28.144111 TX Vref=22, minBit 9, minWin=25, winSum=418
3625 05:56:28.147462 TX Vref=24, minBit 9, minWin=25, winSum=428
3626 05:56:28.150765 TX Vref=26, minBit 8, minWin=26, winSum=429
3627 05:56:28.153852 TX Vref=28, minBit 13, minWin=26, winSum=436
3628 05:56:28.157341 TX Vref=30, minBit 10, minWin=26, winSum=433
3629 05:56:28.164060 TX Vref=32, minBit 8, minWin=25, winSum=429
3630 05:56:28.167410 [TxChooseVref] Worse bit 13, Min win 26, Win sum 436, Final Vref 28
3631 05:56:28.167502
3632 05:56:28.170550 Final TX Range 1 Vref 28
3633 05:56:28.170634
3634 05:56:28.170699 ==
3635 05:56:28.173967 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 05:56:28.177311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 05:56:28.180086 ==
3638 05:56:28.180191
3639 05:56:28.180262
3640 05:56:28.180323 TX Vref Scan disable
3641 05:56:28.184234 == TX Byte 0 ==
3642 05:56:28.187205 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3643 05:56:28.194030 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3644 05:56:28.194126 == TX Byte 1 ==
3645 05:56:28.197316 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3646 05:56:28.204196 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3647 05:56:28.204296
3648 05:56:28.204361 [DATLAT]
3649 05:56:28.204421 Freq=1200, CH1 RK1
3650 05:56:28.204479
3651 05:56:28.207145 DATLAT Default: 0xd
3652 05:56:28.207227 0, 0xFFFF, sum = 0
3653 05:56:28.210499 1, 0xFFFF, sum = 0
3654 05:56:28.210583 2, 0xFFFF, sum = 0
3655 05:56:28.214263 3, 0xFFFF, sum = 0
3656 05:56:28.217242 4, 0xFFFF, sum = 0
3657 05:56:28.217326 5, 0xFFFF, sum = 0
3658 05:56:28.220486 6, 0xFFFF, sum = 0
3659 05:56:28.220570 7, 0xFFFF, sum = 0
3660 05:56:28.223848 8, 0xFFFF, sum = 0
3661 05:56:28.223932 9, 0xFFFF, sum = 0
3662 05:56:28.227312 10, 0xFFFF, sum = 0
3663 05:56:28.227397 11, 0xFFFF, sum = 0
3664 05:56:28.230371 12, 0x0, sum = 1
3665 05:56:28.230455 13, 0x0, sum = 2
3666 05:56:28.233825 14, 0x0, sum = 3
3667 05:56:28.233908 15, 0x0, sum = 4
3668 05:56:28.237123 best_step = 13
3669 05:56:28.237205
3670 05:56:28.237268 ==
3671 05:56:28.240623 Dram Type= 6, Freq= 0, CH_1, rank 1
3672 05:56:28.243780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3673 05:56:28.243864 ==
3674 05:56:28.243928 RX Vref Scan: 0
3675 05:56:28.243987
3676 05:56:28.247278 RX Vref 0 -> 0, step: 1
3677 05:56:28.247360
3678 05:56:28.250098 RX Delay -21 -> 252, step: 4
3679 05:56:28.253968 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3680 05:56:28.260538 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3681 05:56:28.263926 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3682 05:56:28.266780 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3683 05:56:28.270101 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3684 05:56:28.273539 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3685 05:56:28.280150 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3686 05:56:28.283661 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3687 05:56:28.286612 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3688 05:56:28.290010 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3689 05:56:28.293358 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3690 05:56:28.300093 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3691 05:56:28.303433 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3692 05:56:28.306878 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3693 05:56:28.309715 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3694 05:56:28.316339 iDelay=195, Bit 15, Center 116 (47 ~ 186) 140
3695 05:56:28.316425 ==
3696 05:56:28.319786 Dram Type= 6, Freq= 0, CH_1, rank 1
3697 05:56:28.323193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3698 05:56:28.323276 ==
3699 05:56:28.323340 DQS Delay:
3700 05:56:28.326566 DQS0 = 0, DQS1 = 0
3701 05:56:28.326649 DQM Delay:
3702 05:56:28.329738 DQM0 = 111, DQM1 = 108
3703 05:56:28.329824 DQ Delay:
3704 05:56:28.333133 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3705 05:56:28.336726 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =110
3706 05:56:28.339610 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =104
3707 05:56:28.342970 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =116
3708 05:56:28.343057
3709 05:56:28.343121
3710 05:56:28.352833 [DQSOSCAuto] RK1, (LSB)MR18= 0xf707, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3711 05:56:28.356410 CH1 RK1: MR19=304, MR18=F707
3712 05:56:28.362649 CH1_RK1: MR19=0x304, MR18=0xF707, DQSOSC=407, MR23=63, INC=39, DEC=26
3713 05:56:28.365994 [RxdqsGatingPostProcess] freq 1200
3714 05:56:28.369327 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3715 05:56:28.372890 best DQS0 dly(2T, 0.5T) = (0, 11)
3716 05:56:28.376336 best DQS1 dly(2T, 0.5T) = (0, 11)
3717 05:56:28.379142 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3718 05:56:28.382554 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3719 05:56:28.385936 best DQS0 dly(2T, 0.5T) = (0, 11)
3720 05:56:28.389245 best DQS1 dly(2T, 0.5T) = (0, 11)
3721 05:56:28.392649 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3722 05:56:28.395736 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3723 05:56:28.398920 Pre-setting of DQS Precalculation
3724 05:56:28.402098 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3725 05:56:28.412250 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3726 05:56:28.419081 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3727 05:56:28.419173
3728 05:56:28.419238
3729 05:56:28.422297 [Calibration Summary] 2400 Mbps
3730 05:56:28.422380 CH 0, Rank 0
3731 05:56:28.425246 SW Impedance : PASS
3732 05:56:28.425328 DUTY Scan : NO K
3733 05:56:28.428708 ZQ Calibration : PASS
3734 05:56:28.432060 Jitter Meter : NO K
3735 05:56:28.432144 CBT Training : PASS
3736 05:56:28.435331 Write leveling : PASS
3737 05:56:28.438574 RX DQS gating : PASS
3738 05:56:28.438671 RX DQ/DQS(RDDQC) : PASS
3739 05:56:28.442113 TX DQ/DQS : PASS
3740 05:56:28.445002 RX DATLAT : PASS
3741 05:56:28.445086 RX DQ/DQS(Engine): PASS
3742 05:56:28.448464 TX OE : NO K
3743 05:56:28.448548 All Pass.
3744 05:56:28.448612
3745 05:56:28.451749 CH 0, Rank 1
3746 05:56:28.451832 SW Impedance : PASS
3747 05:56:28.455349 DUTY Scan : NO K
3748 05:56:28.455431 ZQ Calibration : PASS
3749 05:56:28.458738 Jitter Meter : NO K
3750 05:56:28.461790 CBT Training : PASS
3751 05:56:28.461873 Write leveling : PASS
3752 05:56:28.465244 RX DQS gating : PASS
3753 05:56:28.468517 RX DQ/DQS(RDDQC) : PASS
3754 05:56:28.468619 TX DQ/DQS : PASS
3755 05:56:28.471735 RX DATLAT : PASS
3756 05:56:28.474970 RX DQ/DQS(Engine): PASS
3757 05:56:28.475053 TX OE : NO K
3758 05:56:28.478670 All Pass.
3759 05:56:28.478755
3760 05:56:28.478819 CH 1, Rank 0
3761 05:56:28.481778 SW Impedance : PASS
3762 05:56:28.481860 DUTY Scan : NO K
3763 05:56:28.484934 ZQ Calibration : PASS
3764 05:56:28.488385 Jitter Meter : NO K
3765 05:56:28.488467 CBT Training : PASS
3766 05:56:28.491800 Write leveling : PASS
3767 05:56:28.495108 RX DQS gating : PASS
3768 05:56:28.495190 RX DQ/DQS(RDDQC) : PASS
3769 05:56:28.498517 TX DQ/DQS : PASS
3770 05:56:28.501734 RX DATLAT : PASS
3771 05:56:28.501817 RX DQ/DQS(Engine): PASS
3772 05:56:28.504595 TX OE : NO K
3773 05:56:28.504668 All Pass.
3774 05:56:28.504729
3775 05:56:28.508412 CH 1, Rank 1
3776 05:56:28.508493 SW Impedance : PASS
3777 05:56:28.511570 DUTY Scan : NO K
3778 05:56:28.511651 ZQ Calibration : PASS
3779 05:56:28.514601 Jitter Meter : NO K
3780 05:56:28.517883 CBT Training : PASS
3781 05:56:28.517967 Write leveling : PASS
3782 05:56:28.521280 RX DQS gating : PASS
3783 05:56:28.524622 RX DQ/DQS(RDDQC) : PASS
3784 05:56:28.524704 TX DQ/DQS : PASS
3785 05:56:28.528084 RX DATLAT : PASS
3786 05:56:28.531741 RX DQ/DQS(Engine): PASS
3787 05:56:28.531822 TX OE : NO K
3788 05:56:28.534537 All Pass.
3789 05:56:28.534620
3790 05:56:28.534684 DramC Write-DBI off
3791 05:56:28.538019 PER_BANK_REFRESH: Hybrid Mode
3792 05:56:28.541377 TX_TRACKING: ON
3793 05:56:28.548160 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3794 05:56:28.550875 [FAST_K] Save calibration result to emmc
3795 05:56:28.554302 dramc_set_vcore_voltage set vcore to 650000
3796 05:56:28.557712 Read voltage for 600, 5
3797 05:56:28.557795 Vio18 = 0
3798 05:56:28.561272 Vcore = 650000
3799 05:56:28.561354 Vdram = 0
3800 05:56:28.561418 Vddq = 0
3801 05:56:28.564120 Vmddr = 0
3802 05:56:28.567567 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3803 05:56:28.574413 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3804 05:56:28.574514 MEM_TYPE=3, freq_sel=19
3805 05:56:28.577901 sv_algorithm_assistance_LP4_1600
3806 05:56:28.584448 ============ PULL DRAM RESETB DOWN ============
3807 05:56:28.587794 ========== PULL DRAM RESETB DOWN end =========
3808 05:56:28.590837 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3809 05:56:28.594156 ===================================
3810 05:56:28.597421 LPDDR4 DRAM CONFIGURATION
3811 05:56:28.600777 ===================================
3812 05:56:28.604222 EX_ROW_EN[0] = 0x0
3813 05:56:28.604307 EX_ROW_EN[1] = 0x0
3814 05:56:28.607581 LP4Y_EN = 0x0
3815 05:56:28.607665 WORK_FSP = 0x0
3816 05:56:28.610995 WL = 0x2
3817 05:56:28.611078 RL = 0x2
3818 05:56:28.614014 BL = 0x2
3819 05:56:28.614096 RPST = 0x0
3820 05:56:28.617363 RD_PRE = 0x0
3821 05:56:28.617446 WR_PRE = 0x1
3822 05:56:28.620498 WR_PST = 0x0
3823 05:56:28.620579 DBI_WR = 0x0
3824 05:56:28.624103 DBI_RD = 0x0
3825 05:56:28.624186 OTF = 0x1
3826 05:56:28.627427 ===================================
3827 05:56:28.630726 ===================================
3828 05:56:28.634140 ANA top config
3829 05:56:28.637034 ===================================
3830 05:56:28.640424 DLL_ASYNC_EN = 0
3831 05:56:28.640511 ALL_SLAVE_EN = 1
3832 05:56:28.643982 NEW_RANK_MODE = 1
3833 05:56:28.647446 DLL_IDLE_MODE = 1
3834 05:56:28.650643 LP45_APHY_COMB_EN = 1
3835 05:56:28.650735 TX_ODT_DIS = 1
3836 05:56:28.653885 NEW_8X_MODE = 1
3837 05:56:28.656820 ===================================
3838 05:56:28.660378 ===================================
3839 05:56:28.663759 data_rate = 1200
3840 05:56:28.667180 CKR = 1
3841 05:56:28.670402 DQ_P2S_RATIO = 8
3842 05:56:28.674043 ===================================
3843 05:56:28.677454 CA_P2S_RATIO = 8
3844 05:56:28.677582 DQ_CA_OPEN = 0
3845 05:56:28.680318 DQ_SEMI_OPEN = 0
3846 05:56:28.683665 CA_SEMI_OPEN = 0
3847 05:56:28.686864 CA_FULL_RATE = 0
3848 05:56:28.690427 DQ_CKDIV4_EN = 1
3849 05:56:28.693337 CA_CKDIV4_EN = 1
3850 05:56:28.693420 CA_PREDIV_EN = 0
3851 05:56:28.696707 PH8_DLY = 0
3852 05:56:28.700094 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3853 05:56:28.703633 DQ_AAMCK_DIV = 4
3854 05:56:28.706798 CA_AAMCK_DIV = 4
3855 05:56:28.710402 CA_ADMCK_DIV = 4
3856 05:56:28.710483 DQ_TRACK_CA_EN = 0
3857 05:56:28.713810 CA_PICK = 600
3858 05:56:28.716718 CA_MCKIO = 600
3859 05:56:28.720169 MCKIO_SEMI = 0
3860 05:56:28.723519 PLL_FREQ = 2288
3861 05:56:28.726721 DQ_UI_PI_RATIO = 32
3862 05:56:28.730071 CA_UI_PI_RATIO = 0
3863 05:56:28.733316 ===================================
3864 05:56:28.736270 ===================================
3865 05:56:28.736353 memory_type:LPDDR4
3866 05:56:28.739451 GP_NUM : 10
3867 05:56:28.742998 SRAM_EN : 1
3868 05:56:28.743081 MD32_EN : 0
3869 05:56:28.746533 ===================================
3870 05:56:28.750016 [ANA_INIT] >>>>>>>>>>>>>>
3871 05:56:28.752781 <<<<<< [CONFIGURE PHASE]: ANA_TX
3872 05:56:28.756247 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3873 05:56:28.759539 ===================================
3874 05:56:28.763068 data_rate = 1200,PCW = 0X5800
3875 05:56:28.766505 ===================================
3876 05:56:28.769372 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3877 05:56:28.772673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3878 05:56:28.779562 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3879 05:56:28.782466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3880 05:56:28.785836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3881 05:56:28.792520 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3882 05:56:28.792610 [ANA_INIT] flow start
3883 05:56:28.795983 [ANA_INIT] PLL >>>>>>>>
3884 05:56:28.799358 [ANA_INIT] PLL <<<<<<<<
3885 05:56:28.799441 [ANA_INIT] MIDPI >>>>>>>>
3886 05:56:28.802752 [ANA_INIT] MIDPI <<<<<<<<
3887 05:56:28.806028 [ANA_INIT] DLL >>>>>>>>
3888 05:56:28.806111 [ANA_INIT] flow end
3889 05:56:28.809048 ============ LP4 DIFF to SE enter ============
3890 05:56:28.816098 ============ LP4 DIFF to SE exit ============
3891 05:56:28.816224 [ANA_INIT] <<<<<<<<<<<<<
3892 05:56:28.819037 [Flow] Enable top DCM control >>>>>
3893 05:56:28.822455 [Flow] Enable top DCM control <<<<<
3894 05:56:28.825821 Enable DLL master slave shuffle
3895 05:56:28.832049 ==============================================================
3896 05:56:28.835334 Gating Mode config
3897 05:56:28.838935 ==============================================================
3898 05:56:28.842121 Config description:
3899 05:56:28.852010 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3900 05:56:28.858740 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3901 05:56:28.862218 SELPH_MODE 0: By rank 1: By Phase
3902 05:56:28.868921 ==============================================================
3903 05:56:28.872480 GAT_TRACK_EN = 1
3904 05:56:28.875343 RX_GATING_MODE = 2
3905 05:56:28.875425 RX_GATING_TRACK_MODE = 2
3906 05:56:28.879002 SELPH_MODE = 1
3907 05:56:28.881937 PICG_EARLY_EN = 1
3908 05:56:28.885367 VALID_LAT_VALUE = 1
3909 05:56:28.892141 ==============================================================
3910 05:56:28.895520 Enter into Gating configuration >>>>
3911 05:56:28.898280 Exit from Gating configuration <<<<
3912 05:56:28.901681 Enter into DVFS_PRE_config >>>>>
3913 05:56:28.911813 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3914 05:56:28.915413 Exit from DVFS_PRE_config <<<<<
3915 05:56:28.918308 Enter into PICG configuration >>>>
3916 05:56:28.921692 Exit from PICG configuration <<<<
3917 05:56:28.925066 [RX_INPUT] configuration >>>>>
3918 05:56:28.928409 [RX_INPUT] configuration <<<<<
3919 05:56:28.931481 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3920 05:56:28.938168 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3921 05:56:28.945160 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3922 05:56:28.951182 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3923 05:56:28.958006 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3924 05:56:28.960912 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3925 05:56:28.967768 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3926 05:56:28.970952 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3927 05:56:28.974442 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3928 05:56:28.977997 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3929 05:56:28.984535 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3930 05:56:28.987427 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3931 05:56:28.990354 ===================================
3932 05:56:28.993765 LPDDR4 DRAM CONFIGURATION
3933 05:56:28.997226 ===================================
3934 05:56:28.997311 EX_ROW_EN[0] = 0x0
3935 05:56:29.000744 EX_ROW_EN[1] = 0x0
3936 05:56:29.000831 LP4Y_EN = 0x0
3937 05:56:29.004043 WORK_FSP = 0x0
3938 05:56:29.006939 WL = 0x2
3939 05:56:29.007037 RL = 0x2
3940 05:56:29.010881 BL = 0x2
3941 05:56:29.010990 RPST = 0x0
3942 05:56:29.013748 RD_PRE = 0x0
3943 05:56:29.013833 WR_PRE = 0x1
3944 05:56:29.017263 WR_PST = 0x0
3945 05:56:29.017348 DBI_WR = 0x0
3946 05:56:29.020180 DBI_RD = 0x0
3947 05:56:29.020265 OTF = 0x1
3948 05:56:29.023614 ===================================
3949 05:56:29.027089 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3950 05:56:29.033335 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3951 05:56:29.036678 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3952 05:56:29.040462 ===================================
3953 05:56:29.043576 LPDDR4 DRAM CONFIGURATION
3954 05:56:29.046840 ===================================
3955 05:56:29.046941 EX_ROW_EN[0] = 0x10
3956 05:56:29.050377 EX_ROW_EN[1] = 0x0
3957 05:56:29.053386 LP4Y_EN = 0x0
3958 05:56:29.053469 WORK_FSP = 0x0
3959 05:56:29.056534 WL = 0x2
3960 05:56:29.056617 RL = 0x2
3961 05:56:29.060029 BL = 0x2
3962 05:56:29.060112 RPST = 0x0
3963 05:56:29.063176 RD_PRE = 0x0
3964 05:56:29.063258 WR_PRE = 0x1
3965 05:56:29.066428 WR_PST = 0x0
3966 05:56:29.066510 DBI_WR = 0x0
3967 05:56:29.069928 DBI_RD = 0x0
3968 05:56:29.070010 OTF = 0x1
3969 05:56:29.073356 ===================================
3970 05:56:29.080104 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3971 05:56:29.084022 nWR fixed to 30
3972 05:56:29.087410 [ModeRegInit_LP4] CH0 RK0
3973 05:56:29.087495 [ModeRegInit_LP4] CH0 RK1
3974 05:56:29.090650 [ModeRegInit_LP4] CH1 RK0
3975 05:56:29.094190 [ModeRegInit_LP4] CH1 RK1
3976 05:56:29.094274 match AC timing 17
3977 05:56:29.100849 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3978 05:56:29.103682 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3979 05:56:29.107184 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3980 05:56:29.113766 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3981 05:56:29.117249 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3982 05:56:29.117336 ==
3983 05:56:29.120538 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 05:56:29.123538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 05:56:29.123623 ==
3986 05:56:29.130431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3987 05:56:29.137179 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3988 05:56:29.140215 [CA 0] Center 37 (7~67) winsize 61
3989 05:56:29.143639 [CA 1] Center 37 (7~67) winsize 61
3990 05:56:29.146886 [CA 2] Center 35 (5~65) winsize 61
3991 05:56:29.150163 [CA 3] Center 35 (5~65) winsize 61
3992 05:56:29.153502 [CA 4] Center 34 (4~65) winsize 62
3993 05:56:29.157068 [CA 5] Center 33 (3~64) winsize 62
3994 05:56:29.157193
3995 05:56:29.160190 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3996 05:56:29.160277
3997 05:56:29.163236 [CATrainingPosCal] consider 1 rank data
3998 05:56:29.166978 u2DelayCellTimex100 = 270/100 ps
3999 05:56:29.170151 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
4000 05:56:29.173258 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
4001 05:56:29.176536 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4002 05:56:29.180302 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
4003 05:56:29.187005 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4004 05:56:29.189835 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4005 05:56:29.189982
4006 05:56:29.193104 CA PerBit enable=1, Macro0, CA PI delay=33
4007 05:56:29.193211
4008 05:56:29.196514 [CBTSetCACLKResult] CA Dly = 33
4009 05:56:29.196624 CS Dly: 5 (0~36)
4010 05:56:29.196723 ==
4011 05:56:29.199982 Dram Type= 6, Freq= 0, CH_0, rank 1
4012 05:56:29.206706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 05:56:29.206823 ==
4014 05:56:29.209455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4015 05:56:29.216275 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4016 05:56:29.219778 [CA 0] Center 37 (7~67) winsize 61
4017 05:56:29.222750 [CA 1] Center 37 (7~67) winsize 61
4018 05:56:29.226155 [CA 2] Center 35 (5~65) winsize 61
4019 05:56:29.229462 [CA 3] Center 34 (4~65) winsize 62
4020 05:56:29.232915 [CA 4] Center 34 (4~64) winsize 61
4021 05:56:29.236011 [CA 5] Center 33 (3~64) winsize 62
4022 05:56:29.236113
4023 05:56:29.239214 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4024 05:56:29.239327
4025 05:56:29.242776 [CATrainingPosCal] consider 2 rank data
4026 05:56:29.245847 u2DelayCellTimex100 = 270/100 ps
4027 05:56:29.249132 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
4028 05:56:29.255998 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
4029 05:56:29.259413 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4030 05:56:29.262339 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
4031 05:56:29.265669 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4032 05:56:29.269101 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4033 05:56:29.269186
4034 05:56:29.272566 CA PerBit enable=1, Macro0, CA PI delay=33
4035 05:56:29.272650
4036 05:56:29.275729 [CBTSetCACLKResult] CA Dly = 33
4037 05:56:29.278992 CS Dly: 6 (0~38)
4038 05:56:29.279085
4039 05:56:29.282713 ----->DramcWriteLeveling(PI) begin...
4040 05:56:29.282800 ==
4041 05:56:29.285717 Dram Type= 6, Freq= 0, CH_0, rank 0
4042 05:56:29.289096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4043 05:56:29.289183 ==
4044 05:56:29.292150 Write leveling (Byte 0): 34 => 34
4045 05:56:29.295436 Write leveling (Byte 1): 31 => 31
4046 05:56:29.298957 DramcWriteLeveling(PI) end<-----
4047 05:56:29.299068
4048 05:56:29.299134 ==
4049 05:56:29.302372 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 05:56:29.305230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 05:56:29.305314 ==
4052 05:56:29.309004 [Gating] SW mode calibration
4053 05:56:29.315231 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4054 05:56:29.321972 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4055 05:56:29.325411 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4056 05:56:29.328379 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4057 05:56:29.335245 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4058 05:56:29.338669 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4059 05:56:29.342093 0 9 16 | B1->B0 | 2f2f 2a2a | 1 0 | (1 0) (0 0)
4060 05:56:29.348501 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4061 05:56:29.351550 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 05:56:29.355348 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 05:56:29.361415 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 05:56:29.365001 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 05:56:29.368258 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 05:56:29.375303 0 10 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4067 05:56:29.378163 0 10 16 | B1->B0 | 3131 3939 | 0 0 | (0 0) (1 1)
4068 05:56:29.381461 0 10 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4069 05:56:29.388294 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 05:56:29.391611 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 05:56:29.394947 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 05:56:29.401276 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 05:56:29.404475 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 05:56:29.408169 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4075 05:56:29.414681 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4076 05:56:29.417690 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 05:56:29.421309 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 05:56:29.428007 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 05:56:29.431175 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 05:56:29.434181 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 05:56:29.441107 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 05:56:29.443980 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 05:56:29.447496 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 05:56:29.454304 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 05:56:29.457698 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 05:56:29.461084 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 05:56:29.467414 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 05:56:29.470798 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 05:56:29.474060 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 05:56:29.480690 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4091 05:56:29.484267 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4092 05:56:29.487065 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 05:56:29.490637 Total UI for P1: 0, mck2ui 16
4094 05:56:29.493957 best dqsien dly found for B0: ( 0, 13, 14)
4095 05:56:29.497309 Total UI for P1: 0, mck2ui 16
4096 05:56:29.500485 best dqsien dly found for B1: ( 0, 13, 18)
4097 05:56:29.503812 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4098 05:56:29.507171 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4099 05:56:29.507254
4100 05:56:29.513772 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4101 05:56:29.516985 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4102 05:56:29.517068 [Gating] SW calibration Done
4103 05:56:29.520521 ==
4104 05:56:29.523552 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 05:56:29.527203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 05:56:29.527311 ==
4107 05:56:29.527403 RX Vref Scan: 0
4108 05:56:29.527492
4109 05:56:29.530404 RX Vref 0 -> 0, step: 1
4110 05:56:29.530483
4111 05:56:29.534012 RX Delay -230 -> 252, step: 16
4112 05:56:29.537082 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4113 05:56:29.540586 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4114 05:56:29.546941 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4115 05:56:29.550416 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4116 05:56:29.553355 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4117 05:56:29.556739 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4118 05:56:29.560292 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4119 05:56:29.566605 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4120 05:56:29.570063 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4121 05:56:29.573505 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4122 05:56:29.576964 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4123 05:56:29.582998 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4124 05:56:29.586424 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4125 05:56:29.589890 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4126 05:56:29.592987 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4127 05:56:29.599882 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4128 05:56:29.599964 ==
4129 05:56:29.603299 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 05:56:29.606441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 05:56:29.606524 ==
4132 05:56:29.606588 DQS Delay:
4133 05:56:29.609942 DQS0 = 0, DQS1 = 0
4134 05:56:29.610022 DQM Delay:
4135 05:56:29.613223 DQM0 = 38, DQM1 = 31
4136 05:56:29.613305 DQ Delay:
4137 05:56:29.616690 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4138 05:56:29.619530 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4139 05:56:29.622709 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4140 05:56:29.626349 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4141 05:56:29.626430
4142 05:56:29.626494
4143 05:56:29.626552 ==
4144 05:56:29.629520 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 05:56:29.632727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 05:56:29.635982 ==
4147 05:56:29.636065
4148 05:56:29.636132
4149 05:56:29.636190 TX Vref Scan disable
4150 05:56:29.639285 == TX Byte 0 ==
4151 05:56:29.642919 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4152 05:56:29.649274 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4153 05:56:29.649364 == TX Byte 1 ==
4154 05:56:29.652470 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4155 05:56:29.659365 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4156 05:56:29.659451 ==
4157 05:56:29.662302 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 05:56:29.665845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 05:56:29.665927 ==
4160 05:56:29.665991
4161 05:56:29.666050
4162 05:56:29.669089 TX Vref Scan disable
4163 05:56:29.672412 == TX Byte 0 ==
4164 05:56:29.675777 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4165 05:56:29.679182 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4166 05:56:29.682199 == TX Byte 1 ==
4167 05:56:29.685883 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4168 05:56:29.689166 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4169 05:56:29.689272
4170 05:56:29.689363 [DATLAT]
4171 05:56:29.692624 Freq=600, CH0 RK0
4172 05:56:29.692706
4173 05:56:29.695447 DATLAT Default: 0x9
4174 05:56:29.695527 0, 0xFFFF, sum = 0
4175 05:56:29.699000 1, 0xFFFF, sum = 0
4176 05:56:29.699083 2, 0xFFFF, sum = 0
4177 05:56:29.702376 3, 0xFFFF, sum = 0
4178 05:56:29.702457 4, 0xFFFF, sum = 0
4179 05:56:29.705905 5, 0xFFFF, sum = 0
4180 05:56:29.705987 6, 0xFFFF, sum = 0
4181 05:56:29.708824 7, 0xFFFF, sum = 0
4182 05:56:29.708908 8, 0x0, sum = 1
4183 05:56:29.712323 9, 0x0, sum = 2
4184 05:56:29.712405 10, 0x0, sum = 3
4185 05:56:29.715683 11, 0x0, sum = 4
4186 05:56:29.715764 best_step = 9
4187 05:56:29.715827
4188 05:56:29.715885 ==
4189 05:56:29.718785 Dram Type= 6, Freq= 0, CH_0, rank 0
4190 05:56:29.721925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 05:56:29.722007 ==
4192 05:56:29.725345 RX Vref Scan: 1
4193 05:56:29.725451
4194 05:56:29.728855 RX Vref 0 -> 0, step: 1
4195 05:56:29.728936
4196 05:56:29.728999 RX Delay -195 -> 252, step: 8
4197 05:56:29.729057
4198 05:56:29.732103 Set Vref, RX VrefLevel [Byte0]: 63
4199 05:56:29.735251 [Byte1]: 47
4200 05:56:29.740095
4201 05:56:29.740175 Final RX Vref Byte 0 = 63 to rank0
4202 05:56:29.743286 Final RX Vref Byte 1 = 47 to rank0
4203 05:56:29.746439 Final RX Vref Byte 0 = 63 to rank1
4204 05:56:29.749710 Final RX Vref Byte 1 = 47 to rank1==
4205 05:56:29.752904 Dram Type= 6, Freq= 0, CH_0, rank 0
4206 05:56:29.759502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 05:56:29.759593 ==
4208 05:56:29.759662 DQS Delay:
4209 05:56:29.763043 DQS0 = 0, DQS1 = 0
4210 05:56:29.763123 DQM Delay:
4211 05:56:29.763186 DQM0 = 36, DQM1 = 29
4212 05:56:29.766447 DQ Delay:
4213 05:56:29.769462 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4214 05:56:29.772795 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =44
4215 05:56:29.776543 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4216 05:56:29.779422 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4217 05:56:29.779542
4218 05:56:29.779658
4219 05:56:29.786199 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a39, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4220 05:56:29.789601 CH0 RK0: MR19=808, MR18=3A39
4221 05:56:29.796364 CH0_RK0: MR19=0x808, MR18=0x3A39, DQSOSC=398, MR23=63, INC=165, DEC=110
4222 05:56:29.796445
4223 05:56:29.799338 ----->DramcWriteLeveling(PI) begin...
4224 05:56:29.799420 ==
4225 05:56:29.802716 Dram Type= 6, Freq= 0, CH_0, rank 1
4226 05:56:29.805800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 05:56:29.805880 ==
4228 05:56:29.809049 Write leveling (Byte 0): 31 => 31
4229 05:56:29.812610 Write leveling (Byte 1): 31 => 31
4230 05:56:29.816038 DramcWriteLeveling(PI) end<-----
4231 05:56:29.816118
4232 05:56:29.816180 ==
4233 05:56:29.819597 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 05:56:29.822476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 05:56:29.825991 ==
4236 05:56:29.826070 [Gating] SW mode calibration
4237 05:56:29.832438 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4238 05:56:29.839418 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4239 05:56:29.842751 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4240 05:56:29.848976 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4241 05:56:29.852577 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4242 05:56:29.855684 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 1)
4243 05:56:29.862415 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4244 05:56:29.865454 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 05:56:29.868988 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 05:56:29.875721 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 05:56:29.878671 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 05:56:29.882004 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 05:56:29.888769 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 05:56:29.892310 0 10 12 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
4251 05:56:29.895476 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4252 05:56:29.901930 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 05:56:29.905421 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 05:56:29.908413 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 05:56:29.915337 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 05:56:29.918295 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 05:56:29.922159 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 05:56:29.928535 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4259 05:56:29.931870 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4260 05:56:29.935285 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 05:56:29.941764 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 05:56:29.945226 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 05:56:29.948220 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 05:56:29.951581 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 05:56:29.958251 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 05:56:29.961768 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 05:56:29.965000 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 05:56:29.971803 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 05:56:29.975010 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 05:56:29.978138 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 05:56:29.984912 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 05:56:29.987895 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 05:56:29.991391 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 05:56:29.998103 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4275 05:56:30.001307 Total UI for P1: 0, mck2ui 16
4276 05:56:30.004704 best dqsien dly found for B0: ( 0, 13, 10)
4277 05:56:30.007732 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 05:56:30.011172 Total UI for P1: 0, mck2ui 16
4279 05:56:30.014751 best dqsien dly found for B1: ( 0, 13, 14)
4280 05:56:30.017654 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4281 05:56:30.021116 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4282 05:56:30.021196
4283 05:56:30.024599 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4284 05:56:30.031008 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4285 05:56:30.031088 [Gating] SW calibration Done
4286 05:56:30.031152 ==
4287 05:56:30.034589 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 05:56:30.040874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 05:56:30.040956 ==
4290 05:56:30.041019 RX Vref Scan: 0
4291 05:56:30.041078
4292 05:56:30.044641 RX Vref 0 -> 0, step: 1
4293 05:56:30.044747
4294 05:56:30.047944 RX Delay -230 -> 252, step: 16
4295 05:56:30.051027 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4296 05:56:30.054609 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4297 05:56:30.060983 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4298 05:56:30.064393 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4299 05:56:30.067738 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4300 05:56:30.071122 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4301 05:56:30.074098 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4302 05:56:30.080558 iDelay=218, Bit 7, Center 41 (-134 ~ 217) 352
4303 05:56:30.083987 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4304 05:56:30.087265 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4305 05:56:30.090689 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4306 05:56:30.097396 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4307 05:56:30.100447 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4308 05:56:30.103840 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4309 05:56:30.107389 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4310 05:56:30.110876 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4311 05:56:30.113821 ==
4312 05:56:30.117203 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 05:56:30.120650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 05:56:30.120732 ==
4315 05:56:30.120796 DQS Delay:
4316 05:56:30.124222 DQS0 = 0, DQS1 = 0
4317 05:56:30.124301 DQM Delay:
4318 05:56:30.127210 DQM0 = 34, DQM1 = 28
4319 05:56:30.127290 DQ Delay:
4320 05:56:30.130629 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4321 05:56:30.134073 DQ4 =33, DQ5 =25, DQ6 =41, DQ7 =41
4322 05:56:30.136993 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4323 05:56:30.140513 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4324 05:56:30.140592
4325 05:56:30.140655
4326 05:56:30.140713 ==
4327 05:56:30.143816 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 05:56:30.147070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 05:56:30.147151 ==
4330 05:56:30.147214
4331 05:56:30.147272
4332 05:56:30.150497 TX Vref Scan disable
4333 05:56:30.153930 == TX Byte 0 ==
4334 05:56:30.156879 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4335 05:56:30.160389 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4336 05:56:30.163626 == TX Byte 1 ==
4337 05:56:30.166840 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4338 05:56:30.170319 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4339 05:56:30.170400 ==
4340 05:56:30.173677 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 05:56:30.180271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 05:56:30.180404 ==
4343 05:56:30.180521
4344 05:56:30.180583
4345 05:56:30.180641 TX Vref Scan disable
4346 05:56:30.184489 == TX Byte 0 ==
4347 05:56:30.188018 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4348 05:56:30.194217 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4349 05:56:30.194298 == TX Byte 1 ==
4350 05:56:30.197598 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4351 05:56:30.204474 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4352 05:56:30.204554
4353 05:56:30.204617 [DATLAT]
4354 05:56:30.204676 Freq=600, CH0 RK1
4355 05:56:30.204732
4356 05:56:30.207811 DATLAT Default: 0x9
4357 05:56:30.207895 0, 0xFFFF, sum = 0
4358 05:56:30.211361 1, 0xFFFF, sum = 0
4359 05:56:30.211443 2, 0xFFFF, sum = 0
4360 05:56:30.214577 3, 0xFFFF, sum = 0
4361 05:56:30.214658 4, 0xFFFF, sum = 0
4362 05:56:30.217839 5, 0xFFFF, sum = 0
4363 05:56:30.217925 6, 0xFFFF, sum = 0
4364 05:56:30.221224 7, 0xFFFF, sum = 0
4365 05:56:30.221304 8, 0x0, sum = 1
4366 05:56:30.224498 9, 0x0, sum = 2
4367 05:56:30.224580 10, 0x0, sum = 3
4368 05:56:30.227912 11, 0x0, sum = 4
4369 05:56:30.228020 best_step = 9
4370 05:56:30.228110
4371 05:56:30.228195 ==
4372 05:56:30.231032 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 05:56:30.237724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 05:56:30.237810 ==
4375 05:56:30.237873 RX Vref Scan: 0
4376 05:56:30.237931
4377 05:56:30.241202 RX Vref 0 -> 0, step: 1
4378 05:56:30.241281
4379 05:56:30.243938 RX Delay -195 -> 252, step: 8
4380 05:56:30.247761 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4381 05:56:30.254518 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4382 05:56:30.257336 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4383 05:56:30.260711 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4384 05:56:30.264073 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4385 05:56:30.267505 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4386 05:56:30.274220 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4387 05:56:30.277202 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4388 05:56:30.280506 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4389 05:56:30.284064 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4390 05:56:30.290681 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4391 05:56:30.293724 iDelay=205, Bit 11, Center 16 (-139 ~ 172) 312
4392 05:56:30.297156 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4393 05:56:30.300195 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4394 05:56:30.307054 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4395 05:56:30.310425 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4396 05:56:30.310506 ==
4397 05:56:30.314028 Dram Type= 6, Freq= 0, CH_0, rank 1
4398 05:56:30.316835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 05:56:30.316916 ==
4400 05:56:30.320325 DQS Delay:
4401 05:56:30.320404 DQS0 = 0, DQS1 = 0
4402 05:56:30.323729 DQM Delay:
4403 05:56:30.323808 DQM0 = 33, DQM1 = 27
4404 05:56:30.323871 DQ Delay:
4405 05:56:30.326781 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4406 05:56:30.330129 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4407 05:56:30.333362 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =16
4408 05:56:30.336596 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4409 05:56:30.336676
4410 05:56:30.336738
4411 05:56:30.346545 [DQSOSCAuto] RK1, (LSB)MR18= 0x6937, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4412 05:56:30.349761 CH0 RK1: MR19=808, MR18=6937
4413 05:56:30.356276 CH0_RK1: MR19=0x808, MR18=0x6937, DQSOSC=390, MR23=63, INC=172, DEC=114
4414 05:56:30.356358 [RxdqsGatingPostProcess] freq 600
4415 05:56:30.363163 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4416 05:56:30.366337 Pre-setting of DQS Precalculation
4417 05:56:30.372771 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4418 05:56:30.372854 ==
4419 05:56:30.376014 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 05:56:30.379571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 05:56:30.379653 ==
4422 05:56:30.386042 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4423 05:56:30.388998 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4424 05:56:30.393429 [CA 0] Center 36 (6~66) winsize 61
4425 05:56:30.396849 [CA 1] Center 36 (6~66) winsize 61
4426 05:56:30.400057 [CA 2] Center 34 (4~65) winsize 62
4427 05:56:30.403125 [CA 3] Center 34 (4~65) winsize 62
4428 05:56:30.406575 [CA 4] Center 34 (4~65) winsize 62
4429 05:56:30.409994 [CA 5] Center 33 (3~64) winsize 62
4430 05:56:30.410074
4431 05:56:30.413371 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4432 05:56:30.413484
4433 05:56:30.416339 [CATrainingPosCal] consider 1 rank data
4434 05:56:30.419818 u2DelayCellTimex100 = 270/100 ps
4435 05:56:30.422895 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4436 05:56:30.429643 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4437 05:56:30.433096 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4438 05:56:30.436355 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4439 05:56:30.439791 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4440 05:56:30.442655 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4441 05:56:30.442735
4442 05:56:30.446073 CA PerBit enable=1, Macro0, CA PI delay=33
4443 05:56:30.446179
4444 05:56:30.449442 [CBTSetCACLKResult] CA Dly = 33
4445 05:56:30.452671 CS Dly: 4 (0~35)
4446 05:56:30.452751 ==
4447 05:56:30.456216 Dram Type= 6, Freq= 0, CH_1, rank 1
4448 05:56:30.459620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 05:56:30.459702 ==
4450 05:56:30.466137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4451 05:56:30.469825 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4452 05:56:30.473522 [CA 0] Center 36 (6~66) winsize 61
4453 05:56:30.476980 [CA 1] Center 35 (5~66) winsize 62
4454 05:56:30.480336 [CA 2] Center 34 (4~65) winsize 62
4455 05:56:30.483727 [CA 3] Center 34 (3~65) winsize 63
4456 05:56:30.486663 [CA 4] Center 34 (4~65) winsize 62
4457 05:56:30.490140 [CA 5] Center 33 (3~64) winsize 62
4458 05:56:30.490220
4459 05:56:30.493515 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4460 05:56:30.493597
4461 05:56:30.496546 [CATrainingPosCal] consider 2 rank data
4462 05:56:30.500033 u2DelayCellTimex100 = 270/100 ps
4463 05:56:30.503508 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4464 05:56:30.506796 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4465 05:56:30.513461 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4466 05:56:30.516478 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4467 05:56:30.520038 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4468 05:56:30.523510 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4469 05:56:30.523592
4470 05:56:30.527066 CA PerBit enable=1, Macro0, CA PI delay=33
4471 05:56:30.527147
4472 05:56:30.529825 [CBTSetCACLKResult] CA Dly = 33
4473 05:56:30.529906 CS Dly: 4 (0~36)
4474 05:56:30.529969
4475 05:56:30.536809 ----->DramcWriteLeveling(PI) begin...
4476 05:56:30.536892 ==
4477 05:56:30.540077 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 05:56:30.543053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 05:56:30.543135 ==
4480 05:56:30.546533 Write leveling (Byte 0): 29 => 29
4481 05:56:30.550023 Write leveling (Byte 1): 30 => 30
4482 05:56:30.553391 DramcWriteLeveling(PI) end<-----
4483 05:56:30.553538
4484 05:56:30.553635 ==
4485 05:56:30.556235 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 05:56:30.559801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 05:56:30.559883 ==
4488 05:56:30.562988 [Gating] SW mode calibration
4489 05:56:30.569642 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4490 05:56:30.576402 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4491 05:56:30.579687 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4492 05:56:30.582987 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4493 05:56:30.589426 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4494 05:56:30.592569 0 9 12 | B1->B0 | 3030 3131 | 0 0 | (0 0) (0 0)
4495 05:56:30.596340 0 9 16 | B1->B0 | 2828 2a2a | 0 0 | (1 0) (0 0)
4496 05:56:30.602632 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 05:56:30.605742 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 05:56:30.609204 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 05:56:30.616180 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 05:56:30.619077 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 05:56:30.622291 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 05:56:30.629077 0 10 12 | B1->B0 | 2a2a 3030 | 0 0 | (0 0) (0 0)
4503 05:56:30.632370 0 10 16 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
4504 05:56:30.635453 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 05:56:30.642122 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 05:56:30.645443 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 05:56:30.649079 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 05:56:30.655453 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 05:56:30.658851 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 05:56:30.662325 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4511 05:56:30.668489 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 05:56:30.672091 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 05:56:30.675513 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 05:56:30.681745 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 05:56:30.685071 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 05:56:30.688861 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 05:56:30.692086 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 05:56:30.698893 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 05:56:30.701747 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 05:56:30.705335 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 05:56:30.711902 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 05:56:30.714960 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 05:56:30.718203 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 05:56:30.725085 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 05:56:30.728119 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 05:56:30.731623 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4527 05:56:30.738040 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 05:56:30.742047 Total UI for P1: 0, mck2ui 16
4529 05:56:30.744747 best dqsien dly found for B0: ( 0, 13, 12)
4530 05:56:30.748138 Total UI for P1: 0, mck2ui 16
4531 05:56:30.751584 best dqsien dly found for B1: ( 0, 13, 12)
4532 05:56:30.754564 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4533 05:56:30.758026 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4534 05:56:30.758108
4535 05:56:30.761420 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4536 05:56:30.764805 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4537 05:56:30.768302 [Gating] SW calibration Done
4538 05:56:30.768384 ==
4539 05:56:30.771484 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 05:56:30.774647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 05:56:30.774730 ==
4542 05:56:30.778110 RX Vref Scan: 0
4543 05:56:30.778191
4544 05:56:30.781641 RX Vref 0 -> 0, step: 1
4545 05:56:30.781732
4546 05:56:30.781797 RX Delay -230 -> 252, step: 16
4547 05:56:30.787818 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4548 05:56:30.791178 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4549 05:56:30.794344 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4550 05:56:30.797743 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4551 05:56:30.804579 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4552 05:56:30.807718 iDelay=218, Bit 5, Center 41 (-134 ~ 217) 352
4553 05:56:30.811052 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4554 05:56:30.814377 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4555 05:56:30.820939 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4556 05:56:30.824308 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4557 05:56:30.827756 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4558 05:56:30.831171 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4559 05:56:30.834063 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4560 05:56:30.840579 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4561 05:56:30.844519 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4562 05:56:30.847304 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4563 05:56:30.847384 ==
4564 05:56:30.850576 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 05:56:30.857444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 05:56:30.857542 ==
4567 05:56:30.857606 DQS Delay:
4568 05:56:30.857665 DQS0 = 0, DQS1 = 0
4569 05:56:30.860543 DQM Delay:
4570 05:56:30.860623 DQM0 = 36, DQM1 = 30
4571 05:56:30.863908 DQ Delay:
4572 05:56:30.867338 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4573 05:56:30.870720 DQ4 =33, DQ5 =41, DQ6 =49, DQ7 =33
4574 05:56:30.870801 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4575 05:56:30.877422 DQ12 =41, DQ13 =41, DQ14 =33, DQ15 =33
4576 05:56:30.877542
4577 05:56:30.877606
4578 05:56:30.877664 ==
4579 05:56:30.880866 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 05:56:30.883874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 05:56:30.883956 ==
4582 05:56:30.884019
4583 05:56:30.884077
4584 05:56:30.887368 TX Vref Scan disable
4585 05:56:30.887448 == TX Byte 0 ==
4586 05:56:30.894236 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4587 05:56:30.897073 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4588 05:56:30.897153 == TX Byte 1 ==
4589 05:56:30.903930 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4590 05:56:30.907508 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4591 05:56:30.907588 ==
4592 05:56:30.910445 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 05:56:30.913423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 05:56:30.913516 ==
4595 05:56:30.913608
4596 05:56:30.916899
4597 05:56:30.916982 TX Vref Scan disable
4598 05:56:30.920528 == TX Byte 0 ==
4599 05:56:30.923506 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4600 05:56:30.930153 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4601 05:56:30.930233 == TX Byte 1 ==
4602 05:56:30.933963 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4603 05:56:30.940328 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4604 05:56:30.940410
4605 05:56:30.940473 [DATLAT]
4606 05:56:30.940532 Freq=600, CH1 RK0
4607 05:56:30.940588
4608 05:56:30.943697 DATLAT Default: 0x9
4609 05:56:30.946575 0, 0xFFFF, sum = 0
4610 05:56:30.946657 1, 0xFFFF, sum = 0
4611 05:56:30.949771 2, 0xFFFF, sum = 0
4612 05:56:30.949852 3, 0xFFFF, sum = 0
4613 05:56:30.953394 4, 0xFFFF, sum = 0
4614 05:56:30.953523 5, 0xFFFF, sum = 0
4615 05:56:30.956633 6, 0xFFFF, sum = 0
4616 05:56:30.956714 7, 0xFFFF, sum = 0
4617 05:56:30.959912 8, 0x0, sum = 1
4618 05:56:30.959994 9, 0x0, sum = 2
4619 05:56:30.963443 10, 0x0, sum = 3
4620 05:56:30.963528 11, 0x0, sum = 4
4621 05:56:30.963592 best_step = 9
4622 05:56:30.963649
4623 05:56:30.966343 ==
4624 05:56:30.969846 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 05:56:30.973290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 05:56:30.973396 ==
4627 05:56:30.973493 RX Vref Scan: 1
4628 05:56:30.973556
4629 05:56:30.976604 RX Vref 0 -> 0, step: 1
4630 05:56:30.976684
4631 05:56:30.980058 RX Delay -195 -> 252, step: 8
4632 05:56:30.980138
4633 05:56:30.982789 Set Vref, RX VrefLevel [Byte0]: 55
4634 05:56:30.986350 [Byte1]: 51
4635 05:56:30.986430
4636 05:56:30.989848 Final RX Vref Byte 0 = 55 to rank0
4637 05:56:30.993322 Final RX Vref Byte 1 = 51 to rank0
4638 05:56:30.996198 Final RX Vref Byte 0 = 55 to rank1
4639 05:56:30.999653 Final RX Vref Byte 1 = 51 to rank1==
4640 05:56:31.003116 Dram Type= 6, Freq= 0, CH_1, rank 0
4641 05:56:31.006476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 05:56:31.009719 ==
4643 05:56:31.009801 DQS Delay:
4644 05:56:31.009864 DQS0 = 0, DQS1 = 0
4645 05:56:31.013034 DQM Delay:
4646 05:56:31.013114 DQM0 = 39, DQM1 = 28
4647 05:56:31.016548 DQ Delay:
4648 05:56:31.016629 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4649 05:56:31.019488 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4650 05:56:31.022966 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4651 05:56:31.026323 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4652 05:56:31.026403
4653 05:56:31.029228
4654 05:56:31.035698 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b28, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
4655 05:56:31.039453 CH1 RK0: MR19=808, MR18=1B28
4656 05:56:31.045991 CH1_RK0: MR19=0x808, MR18=0x1B28, DQSOSC=402, MR23=63, INC=162, DEC=108
4657 05:56:31.046076
4658 05:56:31.048958 ----->DramcWriteLeveling(PI) begin...
4659 05:56:31.049041 ==
4660 05:56:31.052594 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 05:56:31.056069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 05:56:31.056151 ==
4663 05:56:31.059002 Write leveling (Byte 0): 32 => 32
4664 05:56:31.062658 Write leveling (Byte 1): 32 => 32
4665 05:56:31.065697 DramcWriteLeveling(PI) end<-----
4666 05:56:31.065778
4667 05:56:31.065841 ==
4668 05:56:31.068907 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 05:56:31.072350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 05:56:31.072432 ==
4671 05:56:31.075867 [Gating] SW mode calibration
4672 05:56:31.082278 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4673 05:56:31.089076 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4674 05:56:31.091956 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4675 05:56:31.098697 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4676 05:56:31.102130 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4677 05:56:31.105068 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 1)
4678 05:56:31.111780 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4679 05:56:31.115147 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 05:56:31.118591 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 05:56:31.125043 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 05:56:31.128541 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 05:56:31.131428 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 05:56:31.138052 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4685 05:56:31.141300 0 10 12 | B1->B0 | 3030 3b3b | 0 0 | (0 0) (0 0)
4686 05:56:31.144627 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4687 05:56:31.151593 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 05:56:31.154917 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 05:56:31.158092 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 05:56:31.164607 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 05:56:31.167805 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 05:56:31.171111 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4693 05:56:31.178082 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4694 05:56:31.181169 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4695 05:56:31.184600 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 05:56:31.187877 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 05:56:31.194164 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 05:56:31.197692 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 05:56:31.204172 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 05:56:31.207510 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 05:56:31.211035 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 05:56:31.213924 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 05:56:31.220713 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 05:56:31.224157 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 05:56:31.227698 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 05:56:31.234083 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 05:56:31.237067 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 05:56:31.243538 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 05:56:31.247267 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4710 05:56:31.250198 Total UI for P1: 0, mck2ui 16
4711 05:56:31.253878 best dqsien dly found for B0: ( 0, 13, 10)
4712 05:56:31.256736 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 05:56:31.260136 Total UI for P1: 0, mck2ui 16
4714 05:56:31.263490 best dqsien dly found for B1: ( 0, 13, 12)
4715 05:56:31.266964 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4716 05:56:31.269853 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4717 05:56:31.269963
4718 05:56:31.276650 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4719 05:56:31.279796 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4720 05:56:31.279876 [Gating] SW calibration Done
4721 05:56:31.283396 ==
4722 05:56:31.286659 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 05:56:31.289650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 05:56:31.289731 ==
4725 05:56:31.289795 RX Vref Scan: 0
4726 05:56:31.289854
4727 05:56:31.293329 RX Vref 0 -> 0, step: 1
4728 05:56:31.293439
4729 05:56:31.296181 RX Delay -230 -> 252, step: 16
4730 05:56:31.299806 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4731 05:56:31.303219 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4732 05:56:31.310050 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4733 05:56:31.313178 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4734 05:56:31.316702 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4735 05:56:31.319642 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4736 05:56:31.326393 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4737 05:56:31.329730 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4738 05:56:31.332625 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4739 05:56:31.336071 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4740 05:56:31.339503 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4741 05:56:31.346308 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4742 05:56:31.349184 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4743 05:56:31.352357 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4744 05:56:31.355692 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4745 05:56:31.362380 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4746 05:56:31.362463 ==
4747 05:56:31.365800 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 05:56:31.369141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 05:56:31.369223 ==
4750 05:56:31.369287 DQS Delay:
4751 05:56:31.372524 DQS0 = 0, DQS1 = 0
4752 05:56:31.372605 DQM Delay:
4753 05:56:31.375558 DQM0 = 36, DQM1 = 31
4754 05:56:31.375638 DQ Delay:
4755 05:56:31.378788 DQ0 =33, DQ1 =33, DQ2 =25, DQ3 =33
4756 05:56:31.382096 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4757 05:56:31.385382 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =33
4758 05:56:31.389161 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4759 05:56:31.389267
4760 05:56:31.389358
4761 05:56:31.389444 ==
4762 05:56:31.392191 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 05:56:31.398737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 05:56:31.398823 ==
4765 05:56:31.398887
4766 05:56:31.398946
4767 05:56:31.399002 TX Vref Scan disable
4768 05:56:31.402405 == TX Byte 0 ==
4769 05:56:31.405708 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4770 05:56:31.412076 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4771 05:56:31.412157 == TX Byte 1 ==
4772 05:56:31.415562 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4773 05:56:31.421768 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4774 05:56:31.421851 ==
4775 05:56:31.425052 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 05:56:31.428536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 05:56:31.428618 ==
4778 05:56:31.428681
4779 05:56:31.428740
4780 05:56:31.431999 TX Vref Scan disable
4781 05:56:31.434839 == TX Byte 0 ==
4782 05:56:31.438184 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4783 05:56:31.441583 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4784 05:56:31.445168 == TX Byte 1 ==
4785 05:56:31.448388 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4786 05:56:31.451469 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4787 05:56:31.451548
4788 05:56:31.451611 [DATLAT]
4789 05:56:31.454800 Freq=600, CH1 RK1
4790 05:56:31.454881
4791 05:56:31.458018 DATLAT Default: 0x9
4792 05:56:31.458099 0, 0xFFFF, sum = 0
4793 05:56:31.461454 1, 0xFFFF, sum = 0
4794 05:56:31.461562 2, 0xFFFF, sum = 0
4795 05:56:31.465013 3, 0xFFFF, sum = 0
4796 05:56:31.465094 4, 0xFFFF, sum = 0
4797 05:56:31.467828 5, 0xFFFF, sum = 0
4798 05:56:31.467910 6, 0xFFFF, sum = 0
4799 05:56:31.471263 7, 0xFFFF, sum = 0
4800 05:56:31.471344 8, 0x0, sum = 1
4801 05:56:31.474672 9, 0x0, sum = 2
4802 05:56:31.474753 10, 0x0, sum = 3
4803 05:56:31.478116 11, 0x0, sum = 4
4804 05:56:31.478196 best_step = 9
4805 05:56:31.478259
4806 05:56:31.478317 ==
4807 05:56:31.481015 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 05:56:31.484453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 05:56:31.484536 ==
4810 05:56:31.487695 RX Vref Scan: 0
4811 05:56:31.487775
4812 05:56:31.491168 RX Vref 0 -> 0, step: 1
4813 05:56:31.491248
4814 05:56:31.491312 RX Delay -195 -> 252, step: 8
4815 05:56:31.499641 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4816 05:56:31.502686 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4817 05:56:31.505917 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4818 05:56:31.509183 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4819 05:56:31.516040 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4820 05:56:31.519271 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4821 05:56:31.522537 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4822 05:56:31.525886 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4823 05:56:31.532628 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4824 05:56:31.535678 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4825 05:56:31.538676 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4826 05:56:31.542114 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4827 05:56:31.545606 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4828 05:56:31.552207 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4829 05:56:31.555796 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4830 05:56:31.558638 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4831 05:56:31.558721 ==
4832 05:56:31.562000 Dram Type= 6, Freq= 0, CH_1, rank 1
4833 05:56:31.568663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4834 05:56:31.568778 ==
4835 05:56:31.568847 DQS Delay:
4836 05:56:31.568937 DQS0 = 0, DQS1 = 0
4837 05:56:31.572014 DQM Delay:
4838 05:56:31.572100 DQM0 = 35, DQM1 = 29
4839 05:56:31.575378 DQ Delay:
4840 05:56:31.578342 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4841 05:56:31.581963 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4842 05:56:31.585415 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =20
4843 05:56:31.588854 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4844 05:56:31.588935
4845 05:56:31.588999
4846 05:56:31.595165 [DQSOSCAuto] RK1, (LSB)MR18= 0x3051, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
4847 05:56:31.598597 CH1 RK1: MR19=808, MR18=3051
4848 05:56:31.605029 CH1_RK1: MR19=0x808, MR18=0x3051, DQSOSC=394, MR23=63, INC=168, DEC=112
4849 05:56:31.608449 [RxdqsGatingPostProcess] freq 600
4850 05:56:31.611922 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4851 05:56:31.614959 Pre-setting of DQS Precalculation
4852 05:56:31.621936 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4853 05:56:31.628028 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4854 05:56:31.634935 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4855 05:56:31.635024
4856 05:56:31.635087
4857 05:56:31.637755 [Calibration Summary] 1200 Mbps
4858 05:56:31.637836 CH 0, Rank 0
4859 05:56:31.641362 SW Impedance : PASS
4860 05:56:31.644870 DUTY Scan : NO K
4861 05:56:31.644952 ZQ Calibration : PASS
4862 05:56:31.648337 Jitter Meter : NO K
4863 05:56:31.651253 CBT Training : PASS
4864 05:56:31.651334 Write leveling : PASS
4865 05:56:31.654648 RX DQS gating : PASS
4866 05:56:31.657999 RX DQ/DQS(RDDQC) : PASS
4867 05:56:31.658082 TX DQ/DQS : PASS
4868 05:56:31.661538 RX DATLAT : PASS
4869 05:56:31.664481 RX DQ/DQS(Engine): PASS
4870 05:56:31.664563 TX OE : NO K
4871 05:56:31.668315 All Pass.
4872 05:56:31.668396
4873 05:56:31.668459 CH 0, Rank 1
4874 05:56:31.671433 SW Impedance : PASS
4875 05:56:31.671516 DUTY Scan : NO K
4876 05:56:31.674666 ZQ Calibration : PASS
4877 05:56:31.677996 Jitter Meter : NO K
4878 05:56:31.678077 CBT Training : PASS
4879 05:56:31.681009 Write leveling : PASS
4880 05:56:31.681089 RX DQS gating : PASS
4881 05:56:31.684470 RX DQ/DQS(RDDQC) : PASS
4882 05:56:31.687952 TX DQ/DQS : PASS
4883 05:56:31.688035 RX DATLAT : PASS
4884 05:56:31.691498 RX DQ/DQS(Engine): PASS
4885 05:56:31.694745 TX OE : NO K
4886 05:56:31.694827 All Pass.
4887 05:56:31.694890
4888 05:56:31.694950 CH 1, Rank 0
4889 05:56:31.697672 SW Impedance : PASS
4890 05:56:31.701137 DUTY Scan : NO K
4891 05:56:31.701219 ZQ Calibration : PASS
4892 05:56:31.704802 Jitter Meter : NO K
4893 05:56:31.707505 CBT Training : PASS
4894 05:56:31.707587 Write leveling : PASS
4895 05:56:31.711077 RX DQS gating : PASS
4896 05:56:31.714421 RX DQ/DQS(RDDQC) : PASS
4897 05:56:31.714503 TX DQ/DQS : PASS
4898 05:56:31.718023 RX DATLAT : PASS
4899 05:56:31.720876 RX DQ/DQS(Engine): PASS
4900 05:56:31.720957 TX OE : NO K
4901 05:56:31.721022 All Pass.
4902 05:56:31.724340
4903 05:56:31.724420 CH 1, Rank 1
4904 05:56:31.727744 SW Impedance : PASS
4905 05:56:31.727825 DUTY Scan : NO K
4906 05:56:31.731221 ZQ Calibration : PASS
4907 05:56:31.731302 Jitter Meter : NO K
4908 05:56:31.734541 CBT Training : PASS
4909 05:56:31.737784 Write leveling : PASS
4910 05:56:31.737865 RX DQS gating : PASS
4911 05:56:31.741251 RX DQ/DQS(RDDQC) : PASS
4912 05:56:31.744522 TX DQ/DQS : PASS
4913 05:56:31.744605 RX DATLAT : PASS
4914 05:56:31.747670 RX DQ/DQS(Engine): PASS
4915 05:56:31.751114 TX OE : NO K
4916 05:56:31.751196 All Pass.
4917 05:56:31.751260
4918 05:56:31.754206 DramC Write-DBI off
4919 05:56:31.754289 PER_BANK_REFRESH: Hybrid Mode
4920 05:56:31.757653 TX_TRACKING: ON
4921 05:56:31.764419 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4922 05:56:31.770797 [FAST_K] Save calibration result to emmc
4923 05:56:31.774091 dramc_set_vcore_voltage set vcore to 662500
4924 05:56:31.774175 Read voltage for 933, 3
4925 05:56:31.777709 Vio18 = 0
4926 05:56:31.777791 Vcore = 662500
4927 05:56:31.777855 Vdram = 0
4928 05:56:31.780824 Vddq = 0
4929 05:56:31.780906 Vmddr = 0
4930 05:56:31.784110 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4931 05:56:31.790471 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4932 05:56:31.793831 MEM_TYPE=3, freq_sel=17
4933 05:56:31.797324 sv_algorithm_assistance_LP4_1600
4934 05:56:31.800722 ============ PULL DRAM RESETB DOWN ============
4935 05:56:31.803783 ========== PULL DRAM RESETB DOWN end =========
4936 05:56:31.810456 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4937 05:56:31.814053 ===================================
4938 05:56:31.814138 LPDDR4 DRAM CONFIGURATION
4939 05:56:31.817292 ===================================
4940 05:56:31.820344 EX_ROW_EN[0] = 0x0
4941 05:56:31.820426 EX_ROW_EN[1] = 0x0
4942 05:56:31.823897 LP4Y_EN = 0x0
4943 05:56:31.823979 WORK_FSP = 0x0
4944 05:56:31.827398 WL = 0x3
4945 05:56:31.830302 RL = 0x3
4946 05:56:31.830384 BL = 0x2
4947 05:56:31.833647 RPST = 0x0
4948 05:56:31.833729 RD_PRE = 0x0
4949 05:56:31.837055 WR_PRE = 0x1
4950 05:56:31.837136 WR_PST = 0x0
4951 05:56:31.840434 DBI_WR = 0x0
4952 05:56:31.840515 DBI_RD = 0x0
4953 05:56:31.843600 OTF = 0x1
4954 05:56:31.846667 ===================================
4955 05:56:31.850122 ===================================
4956 05:56:31.850204 ANA top config
4957 05:56:31.853551 ===================================
4958 05:56:31.856944 DLL_ASYNC_EN = 0
4959 05:56:31.860045 ALL_SLAVE_EN = 1
4960 05:56:31.860135 NEW_RANK_MODE = 1
4961 05:56:31.863572 DLL_IDLE_MODE = 1
4962 05:56:31.866813 LP45_APHY_COMB_EN = 1
4963 05:56:31.870190 TX_ODT_DIS = 1
4964 05:56:31.870272 NEW_8X_MODE = 1
4965 05:56:31.873973 ===================================
4966 05:56:31.876858 ===================================
4967 05:56:31.880074 data_rate = 1866
4968 05:56:31.883502 CKR = 1
4969 05:56:31.886524 DQ_P2S_RATIO = 8
4970 05:56:31.890535 ===================================
4971 05:56:31.893458 CA_P2S_RATIO = 8
4972 05:56:31.896875 DQ_CA_OPEN = 0
4973 05:56:31.899745 DQ_SEMI_OPEN = 0
4974 05:56:31.899826 CA_SEMI_OPEN = 0
4975 05:56:31.903127 CA_FULL_RATE = 0
4976 05:56:31.906641 DQ_CKDIV4_EN = 1
4977 05:56:31.910171 CA_CKDIV4_EN = 1
4978 05:56:31.912942 CA_PREDIV_EN = 0
4979 05:56:31.916559 PH8_DLY = 0
4980 05:56:31.916640 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4981 05:56:31.919988 DQ_AAMCK_DIV = 4
4982 05:56:31.922838 CA_AAMCK_DIV = 4
4983 05:56:31.926195 CA_ADMCK_DIV = 4
4984 05:56:31.929761 DQ_TRACK_CA_EN = 0
4985 05:56:31.933147 CA_PICK = 933
4986 05:56:31.936196 CA_MCKIO = 933
4987 05:56:31.936301 MCKIO_SEMI = 0
4988 05:56:31.939403 PLL_FREQ = 3732
4989 05:56:31.942918 DQ_UI_PI_RATIO = 32
4990 05:56:31.946262 CA_UI_PI_RATIO = 0
4991 05:56:31.949445 ===================================
4992 05:56:31.953034 ===================================
4993 05:56:31.956487 memory_type:LPDDR4
4994 05:56:31.956567 GP_NUM : 10
4995 05:56:31.959349 SRAM_EN : 1
4996 05:56:31.962844 MD32_EN : 0
4997 05:56:31.966086 ===================================
4998 05:56:31.966177 [ANA_INIT] >>>>>>>>>>>>>>
4999 05:56:31.969615 <<<<<< [CONFIGURE PHASE]: ANA_TX
5000 05:56:31.972807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5001 05:56:31.976139 ===================================
5002 05:56:31.979755 data_rate = 1866,PCW = 0X8f00
5003 05:56:31.982859 ===================================
5004 05:56:31.985853 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5005 05:56:31.992653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5006 05:56:31.995610 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5007 05:56:32.002505 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5008 05:56:32.005783 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5009 05:56:32.009089 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5010 05:56:32.009170 [ANA_INIT] flow start
5011 05:56:32.012636 [ANA_INIT] PLL >>>>>>>>
5012 05:56:32.015555 [ANA_INIT] PLL <<<<<<<<
5013 05:56:32.018912 [ANA_INIT] MIDPI >>>>>>>>
5014 05:56:32.018993 [ANA_INIT] MIDPI <<<<<<<<
5015 05:56:32.022428 [ANA_INIT] DLL >>>>>>>>
5016 05:56:32.022508 [ANA_INIT] flow end
5017 05:56:32.028757 ============ LP4 DIFF to SE enter ============
5018 05:56:32.032208 ============ LP4 DIFF to SE exit ============
5019 05:56:32.035585 [ANA_INIT] <<<<<<<<<<<<<
5020 05:56:32.038512 [Flow] Enable top DCM control >>>>>
5021 05:56:32.042088 [Flow] Enable top DCM control <<<<<
5022 05:56:32.045375 Enable DLL master slave shuffle
5023 05:56:32.048758 ==============================================================
5024 05:56:32.051640 Gating Mode config
5025 05:56:32.055699 ==============================================================
5026 05:56:32.058446 Config description:
5027 05:56:32.068249 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5028 05:56:32.075077 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5029 05:56:32.078443 SELPH_MODE 0: By rank 1: By Phase
5030 05:56:32.084779 ==============================================================
5031 05:56:32.088135 GAT_TRACK_EN = 1
5032 05:56:32.091747 RX_GATING_MODE = 2
5033 05:56:32.095026 RX_GATING_TRACK_MODE = 2
5034 05:56:32.098045 SELPH_MODE = 1
5035 05:56:32.101383 PICG_EARLY_EN = 1
5036 05:56:32.104520 VALID_LAT_VALUE = 1
5037 05:56:32.108280 ==============================================================
5038 05:56:32.111676 Enter into Gating configuration >>>>
5039 05:56:32.114509 Exit from Gating configuration <<<<
5040 05:56:32.118093 Enter into DVFS_PRE_config >>>>>
5041 05:56:32.131296 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5042 05:56:32.131379 Exit from DVFS_PRE_config <<<<<
5043 05:56:32.134788 Enter into PICG configuration >>>>
5044 05:56:32.137586 Exit from PICG configuration <<<<
5045 05:56:32.141061 [RX_INPUT] configuration >>>>>
5046 05:56:32.144075 [RX_INPUT] configuration <<<<<
5047 05:56:32.150710 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5048 05:56:32.154337 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5049 05:56:32.161328 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5050 05:56:32.167683 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5051 05:56:32.174005 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5052 05:56:32.180592 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5053 05:56:32.184013 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5054 05:56:32.187443 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5055 05:56:32.193833 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5056 05:56:32.197342 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5057 05:56:32.200240 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5058 05:56:32.204041 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5059 05:56:32.207053 ===================================
5060 05:56:32.210388 LPDDR4 DRAM CONFIGURATION
5061 05:56:32.213764 ===================================
5062 05:56:32.216810 EX_ROW_EN[0] = 0x0
5063 05:56:32.216890 EX_ROW_EN[1] = 0x0
5064 05:56:32.220246 LP4Y_EN = 0x0
5065 05:56:32.220327 WORK_FSP = 0x0
5066 05:56:32.223499 WL = 0x3
5067 05:56:32.223580 RL = 0x3
5068 05:56:32.227089 BL = 0x2
5069 05:56:32.227169 RPST = 0x0
5070 05:56:32.230077 RD_PRE = 0x0
5071 05:56:32.230157 WR_PRE = 0x1
5072 05:56:32.233388 WR_PST = 0x0
5073 05:56:32.233468 DBI_WR = 0x0
5074 05:56:32.236926 DBI_RD = 0x0
5075 05:56:32.239834 OTF = 0x1
5076 05:56:32.243434 ===================================
5077 05:56:32.246430 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5078 05:56:32.250383 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5079 05:56:32.253306 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5080 05:56:32.256717 ===================================
5081 05:56:32.259645 LPDDR4 DRAM CONFIGURATION
5082 05:56:32.263125 ===================================
5083 05:56:32.266132 EX_ROW_EN[0] = 0x10
5084 05:56:32.266212 EX_ROW_EN[1] = 0x0
5085 05:56:32.269904 LP4Y_EN = 0x0
5086 05:56:32.269984 WORK_FSP = 0x0
5087 05:56:32.272900 WL = 0x3
5088 05:56:32.272979 RL = 0x3
5089 05:56:32.276411 BL = 0x2
5090 05:56:32.276490 RPST = 0x0
5091 05:56:32.279926 RD_PRE = 0x0
5092 05:56:32.280006 WR_PRE = 0x1
5093 05:56:32.283227 WR_PST = 0x0
5094 05:56:32.283333 DBI_WR = 0x0
5095 05:56:32.286410 DBI_RD = 0x0
5096 05:56:32.289436 OTF = 0x1
5097 05:56:32.293035 ===================================
5098 05:56:32.296424 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5099 05:56:32.301371 nWR fixed to 30
5100 05:56:32.304898 [ModeRegInit_LP4] CH0 RK0
5101 05:56:32.304978 [ModeRegInit_LP4] CH0 RK1
5102 05:56:32.307782 [ModeRegInit_LP4] CH1 RK0
5103 05:56:32.311440 [ModeRegInit_LP4] CH1 RK1
5104 05:56:32.311520 match AC timing 9
5105 05:56:32.318032 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5106 05:56:32.321198 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5107 05:56:32.324410 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5108 05:56:32.331036 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5109 05:56:32.334406 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5110 05:56:32.334486 ==
5111 05:56:32.337701 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 05:56:32.340965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 05:56:32.341045 ==
5114 05:56:32.347877 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5115 05:56:32.354256 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5116 05:56:32.357638 [CA 0] Center 38 (8~69) winsize 62
5117 05:56:32.360929 [CA 1] Center 38 (8~69) winsize 62
5118 05:56:32.364401 [CA 2] Center 35 (5~65) winsize 61
5119 05:56:32.368162 [CA 3] Center 35 (5~65) winsize 61
5120 05:56:32.370989 [CA 4] Center 34 (4~65) winsize 62
5121 05:56:32.374691 [CA 5] Center 33 (3~64) winsize 62
5122 05:56:32.374851
5123 05:56:32.377639 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5124 05:56:32.377774
5125 05:56:32.380740 [CATrainingPosCal] consider 1 rank data
5126 05:56:32.384148 u2DelayCellTimex100 = 270/100 ps
5127 05:56:32.387791 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5128 05:56:32.391112 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5129 05:56:32.393939 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5130 05:56:32.397840 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5131 05:56:32.400872 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5132 05:56:32.407876 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5133 05:56:32.408045
5134 05:56:32.411446 CA PerBit enable=1, Macro0, CA PI delay=33
5135 05:56:32.411614
5136 05:56:32.414006 [CBTSetCACLKResult] CA Dly = 33
5137 05:56:32.414139 CS Dly: 7 (0~38)
5138 05:56:32.414227 ==
5139 05:56:32.417507 Dram Type= 6, Freq= 0, CH_0, rank 1
5140 05:56:32.421170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 05:56:32.424257 ==
5142 05:56:32.427479 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5143 05:56:32.433828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5144 05:56:32.437562 [CA 0] Center 38 (8~69) winsize 62
5145 05:56:32.440569 [CA 1] Center 38 (8~69) winsize 62
5146 05:56:32.443916 [CA 2] Center 35 (5~66) winsize 62
5147 05:56:32.447813 [CA 3] Center 35 (5~66) winsize 62
5148 05:56:32.450578 [CA 4] Center 34 (3~65) winsize 63
5149 05:56:32.454194 [CA 5] Center 33 (3~64) winsize 62
5150 05:56:32.454523
5151 05:56:32.457503 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5152 05:56:32.457826
5153 05:56:32.460693 [CATrainingPosCal] consider 2 rank data
5154 05:56:32.463977 u2DelayCellTimex100 = 270/100 ps
5155 05:56:32.467437 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5156 05:56:32.471044 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5157 05:56:32.473600 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5158 05:56:32.480338 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5159 05:56:32.483725 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5160 05:56:32.487311 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5161 05:56:32.487430
5162 05:56:32.490111 CA PerBit enable=1, Macro0, CA PI delay=33
5163 05:56:32.490201
5164 05:56:32.493449 [CBTSetCACLKResult] CA Dly = 33
5165 05:56:32.493583 CS Dly: 7 (0~39)
5166 05:56:32.493649
5167 05:56:32.497035 ----->DramcWriteLeveling(PI) begin...
5168 05:56:32.497131 ==
5169 05:56:32.500223 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 05:56:32.506902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 05:56:32.506999 ==
5172 05:56:32.510484 Write leveling (Byte 0): 33 => 33
5173 05:56:32.513164 Write leveling (Byte 1): 31 => 31
5174 05:56:32.516630 DramcWriteLeveling(PI) end<-----
5175 05:56:32.516723
5176 05:56:32.516788 ==
5177 05:56:32.520131 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 05:56:32.523615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 05:56:32.523710 ==
5180 05:56:32.526509 [Gating] SW mode calibration
5181 05:56:32.533344 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5182 05:56:32.536787 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5183 05:56:32.543203 0 14 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
5184 05:56:32.546673 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5185 05:56:32.549734 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 05:56:32.556471 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 05:56:32.559599 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 05:56:32.563073 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 05:56:32.569830 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 05:56:32.572727 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5191 05:56:32.576031 0 15 0 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (1 0)
5192 05:56:32.583115 0 15 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
5193 05:56:32.586506 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 05:56:32.589698 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 05:56:32.595975 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 05:56:32.599333 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 05:56:32.602824 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 05:56:32.609386 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 05:56:32.612529 1 0 0 | B1->B0 | 2a2a 3c3c | 0 0 | (1 1) (1 1)
5200 05:56:32.615574 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5201 05:56:32.622549 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 05:56:32.625541 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 05:56:32.629178 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 05:56:32.636006 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 05:56:32.638809 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 05:56:32.642307 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5207 05:56:32.649207 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5208 05:56:32.652003 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5209 05:56:32.655231 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 05:56:32.662211 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 05:56:32.665547 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 05:56:32.668915 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 05:56:32.674979 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 05:56:32.678698 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 05:56:32.681859 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 05:56:32.688605 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 05:56:32.691897 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 05:56:32.695278 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 05:56:32.701391 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 05:56:32.704877 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 05:56:32.708434 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 05:56:32.714861 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 05:56:32.718136 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5224 05:56:32.721228 Total UI for P1: 0, mck2ui 16
5225 05:56:32.724656 best dqsien dly found for B0: ( 1, 2, 30)
5226 05:56:32.727920 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5227 05:56:32.734440 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 05:56:32.734521 Total UI for P1: 0, mck2ui 16
5229 05:56:32.741213 best dqsien dly found for B1: ( 1, 3, 4)
5230 05:56:32.744645 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5231 05:56:32.748229 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5232 05:56:32.748310
5233 05:56:32.751259 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5234 05:56:32.754741 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5235 05:56:32.757457 [Gating] SW calibration Done
5236 05:56:32.757580 ==
5237 05:56:32.760838 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 05:56:32.764747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 05:56:32.764828 ==
5240 05:56:32.767683 RX Vref Scan: 0
5241 05:56:32.767764
5242 05:56:32.767828 RX Vref 0 -> 0, step: 1
5243 05:56:32.767887
5244 05:56:32.771260 RX Delay -80 -> 252, step: 8
5245 05:56:32.774576 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5246 05:56:32.781192 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5247 05:56:32.784482 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5248 05:56:32.787994 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5249 05:56:32.790802 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5250 05:56:32.794584 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5251 05:56:32.797623 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5252 05:56:32.804274 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5253 05:56:32.807432 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5254 05:56:32.810804 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5255 05:56:32.814273 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5256 05:56:32.817744 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5257 05:56:32.824132 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5258 05:56:32.827473 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5259 05:56:32.830918 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5260 05:56:32.833947 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5261 05:56:32.834111 ==
5262 05:56:32.837230 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 05:56:32.843948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 05:56:32.844056 ==
5265 05:56:32.844148 DQS Delay:
5266 05:56:32.844235 DQS0 = 0, DQS1 = 0
5267 05:56:32.847438 DQM Delay:
5268 05:56:32.847549 DQM0 = 95, DQM1 = 83
5269 05:56:32.850977 DQ Delay:
5270 05:56:32.853658 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5271 05:56:32.857295 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5272 05:56:32.860211 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5273 05:56:32.863696 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5274 05:56:32.863787
5275 05:56:32.863852
5276 05:56:32.863911 ==
5277 05:56:32.867214 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 05:56:32.870608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 05:56:32.870713 ==
5280 05:56:32.870789
5281 05:56:32.870849
5282 05:56:32.873645 TX Vref Scan disable
5283 05:56:32.873734 == TX Byte 0 ==
5284 05:56:32.880433 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5285 05:56:32.883468 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5286 05:56:32.886836 == TX Byte 1 ==
5287 05:56:32.890468 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5288 05:56:32.893356 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5289 05:56:32.893519 ==
5290 05:56:32.897036 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 05:56:32.900406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 05:56:32.900763 ==
5293 05:56:32.903312
5294 05:56:32.903686
5295 05:56:32.903983 TX Vref Scan disable
5296 05:56:32.907194 == TX Byte 0 ==
5297 05:56:32.910562 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5298 05:56:32.917224 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5299 05:56:32.917622 == TX Byte 1 ==
5300 05:56:32.920754 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5301 05:56:32.927477 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5302 05:56:32.927941
5303 05:56:32.928244 [DATLAT]
5304 05:56:32.928524 Freq=933, CH0 RK0
5305 05:56:32.928796
5306 05:56:32.930351 DATLAT Default: 0xd
5307 05:56:32.930730 0, 0xFFFF, sum = 0
5308 05:56:32.933977 1, 0xFFFF, sum = 0
5309 05:56:32.934365 2, 0xFFFF, sum = 0
5310 05:56:32.937262 3, 0xFFFF, sum = 0
5311 05:56:32.940437 4, 0xFFFF, sum = 0
5312 05:56:32.940863 5, 0xFFFF, sum = 0
5313 05:56:32.944260 6, 0xFFFF, sum = 0
5314 05:56:32.944811 7, 0xFFFF, sum = 0
5315 05:56:32.947302 8, 0xFFFF, sum = 0
5316 05:56:32.947685 9, 0xFFFF, sum = 0
5317 05:56:32.950072 10, 0x0, sum = 1
5318 05:56:32.950453 11, 0x0, sum = 2
5319 05:56:32.953671 12, 0x0, sum = 3
5320 05:56:32.954152 13, 0x0, sum = 4
5321 05:56:32.954460 best_step = 11
5322 05:56:32.954740
5323 05:56:32.957009 ==
5324 05:56:32.960147 Dram Type= 6, Freq= 0, CH_0, rank 0
5325 05:56:32.963623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 05:56:32.964047 ==
5327 05:56:32.964347 RX Vref Scan: 1
5328 05:56:32.964626
5329 05:56:32.967495 RX Vref 0 -> 0, step: 1
5330 05:56:32.967974
5331 05:56:32.970223 RX Delay -69 -> 252, step: 4
5332 05:56:32.970733
5333 05:56:32.973753 Set Vref, RX VrefLevel [Byte0]: 63
5334 05:56:32.977145 [Byte1]: 47
5335 05:56:32.977699
5336 05:56:32.979999 Final RX Vref Byte 0 = 63 to rank0
5337 05:56:32.983817 Final RX Vref Byte 1 = 47 to rank0
5338 05:56:32.986649 Final RX Vref Byte 0 = 63 to rank1
5339 05:56:32.990112 Final RX Vref Byte 1 = 47 to rank1==
5340 05:56:32.993594 Dram Type= 6, Freq= 0, CH_0, rank 0
5341 05:56:32.997439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 05:56:33.000068 ==
5343 05:56:33.000481 DQS Delay:
5344 05:56:33.000810 DQS0 = 0, DQS1 = 0
5345 05:56:33.003139 DQM Delay:
5346 05:56:33.003522 DQM0 = 95, DQM1 = 82
5347 05:56:33.006837 DQ Delay:
5348 05:56:33.007232 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5349 05:56:33.009688 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5350 05:56:33.013546 DQ8 =74, DQ9 =70, DQ10 =82, DQ11 =76
5351 05:56:33.016542 DQ12 =86, DQ13 =86, DQ14 =96, DQ15 =90
5352 05:56:33.020131
5353 05:56:33.020609
5354 05:56:33.026369 [DQSOSCAuto] RK0, (LSB)MR18= 0xe0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 417 ps
5355 05:56:33.029936 CH0 RK0: MR19=505, MR18=E0E
5356 05:56:33.036721 CH0_RK0: MR19=0x505, MR18=0xE0E, DQSOSC=417, MR23=63, INC=62, DEC=41
5357 05:56:33.037196
5358 05:56:33.039956 ----->DramcWriteLeveling(PI) begin...
5359 05:56:33.040355 ==
5360 05:56:33.042788 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 05:56:33.046583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 05:56:33.046963 ==
5363 05:56:33.049712 Write leveling (Byte 0): 30 => 30
5364 05:56:33.053310 Write leveling (Byte 1): 30 => 30
5365 05:56:33.056092 DramcWriteLeveling(PI) end<-----
5366 05:56:33.056467
5367 05:56:33.056759 ==
5368 05:56:33.059380 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 05:56:33.063018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 05:56:33.063399 ==
5371 05:56:33.066118 [Gating] SW mode calibration
5372 05:56:33.073375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5373 05:56:33.079686 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5374 05:56:33.083308 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
5375 05:56:33.085998 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5376 05:56:33.092694 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 05:56:33.096093 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 05:56:33.099581 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 05:56:33.105994 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 05:56:33.109579 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 05:56:33.112640 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
5382 05:56:33.119773 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5383 05:56:33.122612 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 05:56:33.125926 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 05:56:33.132756 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 05:56:33.136226 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 05:56:33.139102 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 05:56:33.145638 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 05:56:33.149188 0 15 28 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
5390 05:56:33.152651 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5391 05:56:33.158930 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 05:56:33.162085 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 05:56:33.165700 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 05:56:33.172308 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 05:56:33.176134 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 05:56:33.178807 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 05:56:33.185674 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5398 05:56:33.189114 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5399 05:56:33.192307 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 05:56:33.198965 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 05:56:33.202214 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 05:56:33.205866 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 05:56:33.212416 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 05:56:33.215726 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 05:56:33.218974 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 05:56:33.225744 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 05:56:33.228674 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 05:56:33.232497 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 05:56:33.238699 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 05:56:33.242023 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 05:56:33.245570 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 05:56:33.248530 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 05:56:33.255422 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5414 05:56:33.258230 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5415 05:56:33.261865 Total UI for P1: 0, mck2ui 16
5416 05:56:33.265238 best dqsien dly found for B0: ( 1, 2, 28)
5417 05:56:33.268805 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 05:56:33.271867 Total UI for P1: 0, mck2ui 16
5419 05:56:33.275225 best dqsien dly found for B1: ( 1, 3, 0)
5420 05:56:33.278789 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5421 05:56:33.281530 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5422 05:56:33.285106
5423 05:56:33.288036 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5424 05:56:33.292021 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5425 05:56:33.295199 [Gating] SW calibration Done
5426 05:56:33.295679 ==
5427 05:56:33.298162 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 05:56:33.301422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 05:56:33.301857 ==
5430 05:56:33.302157 RX Vref Scan: 0
5431 05:56:33.302437
5432 05:56:33.305272 RX Vref 0 -> 0, step: 1
5433 05:56:33.305856
5434 05:56:33.308318 RX Delay -80 -> 252, step: 8
5435 05:56:33.311405 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5436 05:56:33.314906 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5437 05:56:33.321383 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5438 05:56:33.324831 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5439 05:56:33.328456 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5440 05:56:33.331188 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5441 05:56:33.334649 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5442 05:56:33.338355 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5443 05:56:33.344560 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5444 05:56:33.348474 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5445 05:56:33.351095 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5446 05:56:33.355117 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5447 05:56:33.357782 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5448 05:56:33.364278 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5449 05:56:33.367630 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5450 05:56:33.371822 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5451 05:56:33.372287 ==
5452 05:56:33.374519 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 05:56:33.378082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 05:56:33.378472 ==
5455 05:56:33.381525 DQS Delay:
5456 05:56:33.381877 DQS0 = 0, DQS1 = 0
5457 05:56:33.384742 DQM Delay:
5458 05:56:33.385194 DQM0 = 91, DQM1 = 80
5459 05:56:33.385513 DQ Delay:
5460 05:56:33.388046 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5461 05:56:33.391839 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =107
5462 05:56:33.394916 DQ8 =71, DQ9 =63, DQ10 =83, DQ11 =71
5463 05:56:33.398284 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5464 05:56:33.398711
5465 05:56:33.399042
5466 05:56:33.401234 ==
5467 05:56:33.405012 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 05:56:33.407763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 05:56:33.408187 ==
5470 05:56:33.408519
5471 05:56:33.408824
5472 05:56:33.410974 TX Vref Scan disable
5473 05:56:33.411392 == TX Byte 0 ==
5474 05:56:33.414599 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5475 05:56:33.420878 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5476 05:56:33.421388 == TX Byte 1 ==
5477 05:56:33.424850 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5478 05:56:33.431000 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5479 05:56:33.431505 ==
5480 05:56:33.434275 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 05:56:33.437683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 05:56:33.438098 ==
5483 05:56:33.438425
5484 05:56:33.438723
5485 05:56:33.441005 TX Vref Scan disable
5486 05:56:33.444464 == TX Byte 0 ==
5487 05:56:33.447663 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5488 05:56:33.450925 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5489 05:56:33.454162 == TX Byte 1 ==
5490 05:56:33.457943 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5491 05:56:33.460799 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5492 05:56:33.461312
5493 05:56:33.464080 [DATLAT]
5494 05:56:33.464490 Freq=933, CH0 RK1
5495 05:56:33.464884
5496 05:56:33.468059 DATLAT Default: 0xb
5497 05:56:33.468571 0, 0xFFFF, sum = 0
5498 05:56:33.470907 1, 0xFFFF, sum = 0
5499 05:56:33.471426 2, 0xFFFF, sum = 0
5500 05:56:33.474345 3, 0xFFFF, sum = 0
5501 05:56:33.474865 4, 0xFFFF, sum = 0
5502 05:56:33.477373 5, 0xFFFF, sum = 0
5503 05:56:33.477836 6, 0xFFFF, sum = 0
5504 05:56:33.481117 7, 0xFFFF, sum = 0
5505 05:56:33.481699 8, 0xFFFF, sum = 0
5506 05:56:33.484451 9, 0xFFFF, sum = 0
5507 05:56:33.484992 10, 0x0, sum = 1
5508 05:56:33.487553 11, 0x0, sum = 2
5509 05:56:33.487979 12, 0x0, sum = 3
5510 05:56:33.490861 13, 0x0, sum = 4
5511 05:56:33.491299 best_step = 11
5512 05:56:33.491631
5513 05:56:33.491935 ==
5514 05:56:33.494176 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 05:56:33.500717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 05:56:33.501245 ==
5517 05:56:33.501840 RX Vref Scan: 0
5518 05:56:33.502189
5519 05:56:33.504245 RX Vref 0 -> 0, step: 1
5520 05:56:33.504757
5521 05:56:33.507559 RX Delay -77 -> 252, step: 4
5522 05:56:33.510311 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5523 05:56:33.514029 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5524 05:56:33.520726 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5525 05:56:33.523402 iDelay=199, Bit 3, Center 86 (-9 ~ 182) 192
5526 05:56:33.527114 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5527 05:56:33.530119 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5528 05:56:33.533523 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5529 05:56:33.540005 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5530 05:56:33.543311 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5531 05:56:33.547329 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5532 05:56:33.550122 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5533 05:56:33.553582 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5534 05:56:33.560212 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5535 05:56:33.563242 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5536 05:56:33.567055 iDelay=199, Bit 14, Center 94 (7 ~ 182) 176
5537 05:56:33.570015 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5538 05:56:33.570526 ==
5539 05:56:33.573804 Dram Type= 6, Freq= 0, CH_0, rank 1
5540 05:56:33.577313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 05:56:33.577885 ==
5542 05:56:33.580273 DQS Delay:
5543 05:56:33.580841 DQS0 = 0, DQS1 = 0
5544 05:56:33.583924 DQM Delay:
5545 05:56:33.584433 DQM0 = 91, DQM1 = 83
5546 05:56:33.584759 DQ Delay:
5547 05:56:33.586877 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =86
5548 05:56:33.589843 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104
5549 05:56:33.593547 DQ8 =76, DQ9 =66, DQ10 =84, DQ11 =76
5550 05:56:33.596936 DQ12 =88, DQ13 =90, DQ14 =94, DQ15 =92
5551 05:56:33.597514
5552 05:56:33.600584
5553 05:56:33.606765 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5554 05:56:33.609498 CH0 RK1: MR19=505, MR18=2D0F
5555 05:56:33.616666 CH0_RK1: MR19=0x505, MR18=0x2D0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5556 05:56:33.620014 [RxdqsGatingPostProcess] freq 933
5557 05:56:33.623210 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5558 05:56:33.626570 best DQS0 dly(2T, 0.5T) = (0, 10)
5559 05:56:33.629568 best DQS1 dly(2T, 0.5T) = (0, 11)
5560 05:56:33.632900 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5561 05:56:33.636256 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5562 05:56:33.639642 best DQS0 dly(2T, 0.5T) = (0, 10)
5563 05:56:33.642611 best DQS1 dly(2T, 0.5T) = (0, 11)
5564 05:56:33.646154 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5565 05:56:33.649737 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5566 05:56:33.652490 Pre-setting of DQS Precalculation
5567 05:56:33.656626 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5568 05:56:33.657149 ==
5569 05:56:33.659251 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 05:56:33.665935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 05:56:33.666357 ==
5572 05:56:33.669733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5573 05:56:33.676219 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5574 05:56:33.679170 [CA 0] Center 37 (7~67) winsize 61
5575 05:56:33.682481 [CA 1] Center 38 (8~68) winsize 61
5576 05:56:33.686460 [CA 2] Center 34 (5~64) winsize 60
5577 05:56:33.689384 [CA 3] Center 34 (5~64) winsize 60
5578 05:56:33.692907 [CA 4] Center 34 (5~64) winsize 60
5579 05:56:33.696011 [CA 5] Center 34 (4~64) winsize 61
5580 05:56:33.696529
5581 05:56:33.699118 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5582 05:56:33.699633
5583 05:56:33.702624 [CATrainingPosCal] consider 1 rank data
5584 05:56:33.705878 u2DelayCellTimex100 = 270/100 ps
5585 05:56:33.709630 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5586 05:56:33.712388 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5587 05:56:33.718959 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5588 05:56:33.722646 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5589 05:56:33.725271 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5590 05:56:33.728756 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5591 05:56:33.729277
5592 05:56:33.732091 CA PerBit enable=1, Macro0, CA PI delay=34
5593 05:56:33.732614
5594 05:56:33.735551 [CBTSetCACLKResult] CA Dly = 34
5595 05:56:33.735921 CS Dly: 6 (0~37)
5596 05:56:33.736296 ==
5597 05:56:33.739183 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 05:56:33.745134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 05:56:33.745682 ==
5600 05:56:33.748753 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5601 05:56:33.755457 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5602 05:56:33.758899 [CA 0] Center 37 (7~68) winsize 62
5603 05:56:33.762401 [CA 1] Center 37 (7~68) winsize 62
5604 05:56:33.765445 [CA 2] Center 35 (5~65) winsize 61
5605 05:56:33.768719 [CA 3] Center 34 (4~64) winsize 61
5606 05:56:33.771976 [CA 4] Center 35 (5~65) winsize 61
5607 05:56:33.775473 [CA 5] Center 33 (3~64) winsize 62
5608 05:56:33.775981
5609 05:56:33.779091 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5610 05:56:33.779601
5611 05:56:33.782223 [CATrainingPosCal] consider 2 rank data
5612 05:56:33.785171 u2DelayCellTimex100 = 270/100 ps
5613 05:56:33.788821 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5614 05:56:33.795383 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5615 05:56:33.798166 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5616 05:56:33.801880 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5617 05:56:33.805401 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5618 05:56:33.808184 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5619 05:56:33.808685
5620 05:56:33.812210 CA PerBit enable=1, Macro0, CA PI delay=34
5621 05:56:33.812741
5622 05:56:33.814968 [CBTSetCACLKResult] CA Dly = 34
5623 05:56:33.818471 CS Dly: 7 (0~39)
5624 05:56:33.818979
5625 05:56:33.821724 ----->DramcWriteLeveling(PI) begin...
5626 05:56:33.822239 ==
5627 05:56:33.825148 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 05:56:33.828739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 05:56:33.829246 ==
5630 05:56:33.831669 Write leveling (Byte 0): 27 => 27
5631 05:56:33.835341 Write leveling (Byte 1): 29 => 29
5632 05:56:33.838062 DramcWriteLeveling(PI) end<-----
5633 05:56:33.838474
5634 05:56:33.838798 ==
5635 05:56:33.841959 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 05:56:33.844584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 05:56:33.845092 ==
5638 05:56:33.848171 [Gating] SW mode calibration
5639 05:56:33.854962 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5640 05:56:33.861701 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5641 05:56:33.864665 0 14 0 | B1->B0 | 3030 3333 | 0 1 | (0 0) (0 0)
5642 05:56:33.868178 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 05:56:33.874541 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 05:56:33.877589 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 05:56:33.881621 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 05:56:33.888562 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 05:56:33.890946 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 05:56:33.894800 0 14 28 | B1->B0 | 3131 2e2e | 1 1 | (0 1) (1 0)
5649 05:56:33.901295 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5650 05:56:33.904627 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 05:56:33.907742 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 05:56:33.914132 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 05:56:33.917672 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 05:56:33.920980 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 05:56:33.927757 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 05:56:33.930558 0 15 28 | B1->B0 | 302f 2c2c | 1 0 | (0 0) (0 0)
5657 05:56:33.934119 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 05:56:33.940691 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 05:56:33.944022 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 05:56:33.947122 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 05:56:33.953968 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 05:56:33.956805 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 05:56:33.960289 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 05:56:33.966840 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5665 05:56:33.970264 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 05:56:33.973847 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 05:56:33.980473 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 05:56:33.983320 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 05:56:33.986632 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 05:56:33.993519 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 05:56:33.997069 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 05:56:34.000008 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 05:56:34.007049 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 05:56:34.010048 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 05:56:34.013695 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 05:56:34.020103 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 05:56:34.023138 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 05:56:34.026993 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 05:56:34.032986 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5680 05:56:34.036794 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5681 05:56:34.039940 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 05:56:34.042797 Total UI for P1: 0, mck2ui 16
5683 05:56:34.046311 best dqsien dly found for B0: ( 1, 2, 26)
5684 05:56:34.049835 Total UI for P1: 0, mck2ui 16
5685 05:56:34.053532 best dqsien dly found for B1: ( 1, 2, 28)
5686 05:56:34.056280 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5687 05:56:34.059866 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5688 05:56:34.060283
5689 05:56:34.062808 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5690 05:56:34.069952 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5691 05:56:34.070381 [Gating] SW calibration Done
5692 05:56:34.070731 ==
5693 05:56:34.073034 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 05:56:34.079669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 05:56:34.080118 ==
5696 05:56:34.080460 RX Vref Scan: 0
5697 05:56:34.080865
5698 05:56:34.082865 RX Vref 0 -> 0, step: 1
5699 05:56:34.083276
5700 05:56:34.086304 RX Delay -80 -> 252, step: 8
5701 05:56:34.089437 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5702 05:56:34.093058 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5703 05:56:34.096167 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5704 05:56:34.099217 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5705 05:56:34.106114 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5706 05:56:34.109257 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5707 05:56:34.112588 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5708 05:56:34.116244 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5709 05:56:34.119421 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5710 05:56:34.126220 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5711 05:56:34.129272 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5712 05:56:34.132958 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5713 05:56:34.135926 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5714 05:56:34.139186 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5715 05:56:34.146016 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5716 05:56:34.149350 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5717 05:56:34.149949 ==
5718 05:56:34.152564 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 05:56:34.155824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 05:56:34.156338 ==
5721 05:56:34.156670 DQS Delay:
5722 05:56:34.158977 DQS0 = 0, DQS1 = 0
5723 05:56:34.159391 DQM Delay:
5724 05:56:34.162949 DQM0 = 94, DQM1 = 86
5725 05:56:34.163461 DQ Delay:
5726 05:56:34.165549 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5727 05:56:34.169514 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5728 05:56:34.173152 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5729 05:56:34.176102 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5730 05:56:34.176615
5731 05:56:34.176944
5732 05:56:34.177251 ==
5733 05:56:34.179616 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 05:56:34.186062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 05:56:34.186574 ==
5736 05:56:34.186905
5737 05:56:34.187207
5738 05:56:34.187496 TX Vref Scan disable
5739 05:56:34.189331 == TX Byte 0 ==
5740 05:56:34.192489 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5741 05:56:34.199051 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5742 05:56:34.199559 == TX Byte 1 ==
5743 05:56:34.201997 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5744 05:56:34.208762 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5745 05:56:34.209271 ==
5746 05:56:34.211911 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 05:56:34.215231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 05:56:34.215654 ==
5749 05:56:34.215985
5750 05:56:34.216292
5751 05:56:34.218435 TX Vref Scan disable
5752 05:56:34.218852 == TX Byte 0 ==
5753 05:56:34.225720 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5754 05:56:34.228844 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5755 05:56:34.232181 == TX Byte 1 ==
5756 05:56:34.234958 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5757 05:56:34.238707 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5758 05:56:34.239124
5759 05:56:34.239452 [DATLAT]
5760 05:56:34.242192 Freq=933, CH1 RK0
5761 05:56:34.242702
5762 05:56:34.243031 DATLAT Default: 0xd
5763 05:56:34.245668 0, 0xFFFF, sum = 0
5764 05:56:34.246182 1, 0xFFFF, sum = 0
5765 05:56:34.248418 2, 0xFFFF, sum = 0
5766 05:56:34.252043 3, 0xFFFF, sum = 0
5767 05:56:34.252570 4, 0xFFFF, sum = 0
5768 05:56:34.255123 5, 0xFFFF, sum = 0
5769 05:56:34.255639 6, 0xFFFF, sum = 0
5770 05:56:34.258556 7, 0xFFFF, sum = 0
5771 05:56:34.259074 8, 0xFFFF, sum = 0
5772 05:56:34.261973 9, 0xFFFF, sum = 0
5773 05:56:34.262491 10, 0x0, sum = 1
5774 05:56:34.264952 11, 0x0, sum = 2
5775 05:56:34.265372 12, 0x0, sum = 3
5776 05:56:34.268900 13, 0x0, sum = 4
5777 05:56:34.269417 best_step = 11
5778 05:56:34.269805
5779 05:56:34.270114 ==
5780 05:56:34.271696 Dram Type= 6, Freq= 0, CH_1, rank 0
5781 05:56:34.275240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 05:56:34.275757 ==
5783 05:56:34.278835 RX Vref Scan: 1
5784 05:56:34.279343
5785 05:56:34.281734 RX Vref 0 -> 0, step: 1
5786 05:56:34.282243
5787 05:56:34.282569 RX Delay -69 -> 252, step: 4
5788 05:56:34.282901
5789 05:56:34.285275 Set Vref, RX VrefLevel [Byte0]: 55
5790 05:56:34.288320 [Byte1]: 51
5791 05:56:34.293221
5792 05:56:34.294025 Final RX Vref Byte 0 = 55 to rank0
5793 05:56:34.296561 Final RX Vref Byte 1 = 51 to rank0
5794 05:56:34.299314 Final RX Vref Byte 0 = 55 to rank1
5795 05:56:34.302703 Final RX Vref Byte 1 = 51 to rank1==
5796 05:56:34.306153 Dram Type= 6, Freq= 0, CH_1, rank 0
5797 05:56:34.312962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 05:56:34.313508 ==
5799 05:56:34.313852 DQS Delay:
5800 05:56:34.316135 DQS0 = 0, DQS1 = 0
5801 05:56:34.316645 DQM Delay:
5802 05:56:34.316976 DQM0 = 96, DQM1 = 89
5803 05:56:34.319200 DQ Delay:
5804 05:56:34.322863 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =94
5805 05:56:34.325568 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =94
5806 05:56:34.329304 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =82
5807 05:56:34.332633 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5808 05:56:34.333053
5809 05:56:34.333383
5810 05:56:34.339167 [DQSOSCAuto] RK0, (LSB)MR18= 0xfc05, (MSB)MR19= 0x405, tDQSOscB0 = 420 ps tDQSOscB1 = 423 ps
5811 05:56:34.343051 CH1 RK0: MR19=405, MR18=FC05
5812 05:56:34.349118 CH1_RK0: MR19=0x405, MR18=0xFC05, DQSOSC=420, MR23=63, INC=61, DEC=40
5813 05:56:34.349704
5814 05:56:34.351892 ----->DramcWriteLeveling(PI) begin...
5815 05:56:34.352314 ==
5816 05:56:34.355843 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 05:56:34.358720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 05:56:34.359140 ==
5819 05:56:34.362173 Write leveling (Byte 0): 26 => 26
5820 05:56:34.365693 Write leveling (Byte 1): 27 => 27
5821 05:56:34.368781 DramcWriteLeveling(PI) end<-----
5822 05:56:34.369290
5823 05:56:34.369664 ==
5824 05:56:34.372451 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 05:56:34.375837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 05:56:34.378929 ==
5827 05:56:34.379441 [Gating] SW mode calibration
5828 05:56:34.388722 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5829 05:56:34.392393 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5830 05:56:34.394994 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 05:56:34.401925 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 05:56:34.405353 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 05:56:34.408378 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 05:56:34.415625 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 05:56:34.418142 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5836 05:56:34.421846 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5837 05:56:34.429870 0 14 28 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
5838 05:56:34.431970 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 05:56:34.435016 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 05:56:34.441759 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 05:56:34.444552 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 05:56:34.448402 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 05:56:34.455330 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 05:56:34.458203 0 15 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
5845 05:56:34.461678 0 15 28 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
5846 05:56:34.468157 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5847 05:56:34.471740 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 05:56:34.474762 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 05:56:34.481391 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 05:56:34.484980 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 05:56:34.488161 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 05:56:34.494503 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5853 05:56:34.498264 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 05:56:34.501030 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 05:56:34.507969 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 05:56:34.511169 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 05:56:34.514577 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 05:56:34.521294 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 05:56:34.524222 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 05:56:34.528013 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 05:56:34.534342 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 05:56:34.537567 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 05:56:34.540855 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 05:56:34.547262 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 05:56:34.550919 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 05:56:34.553593 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 05:56:34.560177 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 05:56:34.563600 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 05:56:34.567003 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5870 05:56:34.570345 Total UI for P1: 0, mck2ui 16
5871 05:56:34.573452 best dqsien dly found for B0: ( 1, 2, 26)
5872 05:56:34.580470 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5873 05:56:34.580928 Total UI for P1: 0, mck2ui 16
5874 05:56:34.587000 best dqsien dly found for B1: ( 1, 2, 28)
5875 05:56:34.590051 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5876 05:56:34.593783 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5877 05:56:34.594217
5878 05:56:34.596718 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5879 05:56:34.600575 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5880 05:56:34.603267 [Gating] SW calibration Done
5881 05:56:34.603701 ==
5882 05:56:34.607243 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 05:56:34.609886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 05:56:34.610326 ==
5885 05:56:34.613744 RX Vref Scan: 0
5886 05:56:34.614271
5887 05:56:34.614713 RX Vref 0 -> 0, step: 1
5888 05:56:34.615130
5889 05:56:34.616904 RX Delay -80 -> 252, step: 8
5890 05:56:34.620137 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5891 05:56:34.626467 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5892 05:56:34.630102 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5893 05:56:34.633848 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5894 05:56:34.636751 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5895 05:56:34.640184 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5896 05:56:34.643306 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5897 05:56:34.650409 iDelay=208, Bit 7, Center 87 (-16 ~ 191) 208
5898 05:56:34.653137 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5899 05:56:34.656560 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5900 05:56:34.659950 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5901 05:56:34.663426 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5902 05:56:34.669842 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5903 05:56:34.673181 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5904 05:56:34.676718 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5905 05:56:34.680008 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5906 05:56:34.680526 ==
5907 05:56:34.682675 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 05:56:34.689158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 05:56:34.689717 ==
5910 05:56:34.690161 DQS Delay:
5911 05:56:34.690712 DQS0 = 0, DQS1 = 0
5912 05:56:34.692935 DQM Delay:
5913 05:56:34.693464 DQM0 = 92, DQM1 = 87
5914 05:56:34.696039 DQ Delay:
5915 05:56:34.699797 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =87
5916 05:56:34.702541 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5917 05:56:34.706248 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5918 05:56:34.709051 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5919 05:56:34.709577
5920 05:56:34.709840
5921 05:56:34.710054 ==
5922 05:56:34.712556 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 05:56:34.715812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 05:56:34.716038 ==
5925 05:56:34.716216
5926 05:56:34.716381
5927 05:56:34.719414 TX Vref Scan disable
5928 05:56:34.719690 == TX Byte 0 ==
5929 05:56:34.725637 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5930 05:56:34.729302 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5931 05:56:34.729457 == TX Byte 1 ==
5932 05:56:34.735541 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5933 05:56:34.738609 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5934 05:56:34.738769 ==
5935 05:56:34.742382 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 05:56:34.745332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 05:56:34.745469 ==
5938 05:56:34.745606
5939 05:56:34.748698
5940 05:56:34.748833 TX Vref Scan disable
5941 05:56:34.751688 == TX Byte 0 ==
5942 05:56:34.755257 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5943 05:56:34.758267 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5944 05:56:34.761721 == TX Byte 1 ==
5945 05:56:34.765089 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5946 05:56:34.768518 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5947 05:56:34.772248
5948 05:56:34.772570 [DATLAT]
5949 05:56:34.772827 Freq=933, CH1 RK1
5950 05:56:34.773066
5951 05:56:34.775519 DATLAT Default: 0xb
5952 05:56:34.775760 0, 0xFFFF, sum = 0
5953 05:56:34.778627 1, 0xFFFF, sum = 0
5954 05:56:34.778870 2, 0xFFFF, sum = 0
5955 05:56:34.781868 3, 0xFFFF, sum = 0
5956 05:56:34.782112 4, 0xFFFF, sum = 0
5957 05:56:34.785076 5, 0xFFFF, sum = 0
5958 05:56:34.788518 6, 0xFFFF, sum = 0
5959 05:56:34.788760 7, 0xFFFF, sum = 0
5960 05:56:34.791841 8, 0xFFFF, sum = 0
5961 05:56:34.792082 9, 0xFFFF, sum = 0
5962 05:56:34.795051 10, 0x0, sum = 1
5963 05:56:34.795297 11, 0x0, sum = 2
5964 05:56:34.795492 12, 0x0, sum = 3
5965 05:56:34.798834 13, 0x0, sum = 4
5966 05:56:34.799158 best_step = 11
5967 05:56:34.799358
5968 05:56:34.801783 ==
5969 05:56:34.802021 Dram Type= 6, Freq= 0, CH_1, rank 1
5970 05:56:34.808680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5971 05:56:34.809002 ==
5972 05:56:34.809205 RX Vref Scan: 0
5973 05:56:34.809387
5974 05:56:34.812149 RX Vref 0 -> 0, step: 1
5975 05:56:34.812536
5976 05:56:34.815881 RX Delay -69 -> 252, step: 4
5977 05:56:34.818650 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5978 05:56:34.825339 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5979 05:56:34.829131 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5980 05:56:34.832210 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5981 05:56:34.835589 iDelay=203, Bit 4, Center 92 (-5 ~ 190) 196
5982 05:56:34.838847 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5983 05:56:34.844996 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5984 05:56:34.848924 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5985 05:56:34.851502 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5986 05:56:34.854887 iDelay=203, Bit 9, Center 84 (-9 ~ 178) 188
5987 05:56:34.858461 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5988 05:56:34.861380 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5989 05:56:34.868280 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5990 05:56:34.871573 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5991 05:56:34.874977 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5992 05:56:34.878547 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5993 05:56:34.878958 ==
5994 05:56:34.881238 Dram Type= 6, Freq= 0, CH_1, rank 1
5995 05:56:34.888370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5996 05:56:34.888886 ==
5997 05:56:34.889268 DQS Delay:
5998 05:56:34.891073 DQS0 = 0, DQS1 = 0
5999 05:56:34.891491 DQM Delay:
6000 05:56:34.891814 DQM0 = 92, DQM1 = 91
6001 05:56:34.894726 DQ Delay:
6002 05:56:34.897967 DQ0 =96, DQ1 =86, DQ2 =80, DQ3 =88
6003 05:56:34.901138 DQ4 =92, DQ5 =102, DQ6 =104, DQ7 =88
6004 05:56:34.905022 DQ8 =78, DQ9 =84, DQ10 =92, DQ11 =84
6005 05:56:34.908109 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =98
6006 05:56:34.908620
6007 05:56:34.908943
6008 05:56:34.914609 [DQSOSCAuto] RK1, (LSB)MR18= 0xe21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
6009 05:56:34.918010 CH1 RK1: MR19=505, MR18=E21
6010 05:56:34.924842 CH1_RK1: MR19=0x505, MR18=0xE21, DQSOSC=411, MR23=63, INC=64, DEC=42
6011 05:56:34.927675 [RxdqsGatingPostProcess] freq 933
6012 05:56:34.931567 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6013 05:56:34.934682 best DQS0 dly(2T, 0.5T) = (0, 10)
6014 05:56:34.937987 best DQS1 dly(2T, 0.5T) = (0, 10)
6015 05:56:34.941562 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6016 05:56:34.944669 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6017 05:56:34.947800 best DQS0 dly(2T, 0.5T) = (0, 10)
6018 05:56:34.951390 best DQS1 dly(2T, 0.5T) = (0, 10)
6019 05:56:34.954428 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6020 05:56:34.958283 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6021 05:56:34.961220 Pre-setting of DQS Precalculation
6022 05:56:34.964309 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6023 05:56:34.973935 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6024 05:56:34.980926 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6025 05:56:34.981338
6026 05:56:34.981702
6027 05:56:34.984167 [Calibration Summary] 1866 Mbps
6028 05:56:34.984690 CH 0, Rank 0
6029 05:56:34.987766 SW Impedance : PASS
6030 05:56:34.988282 DUTY Scan : NO K
6031 05:56:34.990406 ZQ Calibration : PASS
6032 05:56:34.993943 Jitter Meter : NO K
6033 05:56:34.994358 CBT Training : PASS
6034 05:56:34.996805 Write leveling : PASS
6035 05:56:35.000485 RX DQS gating : PASS
6036 05:56:35.000903 RX DQ/DQS(RDDQC) : PASS
6037 05:56:35.003942 TX DQ/DQS : PASS
6038 05:56:35.007060 RX DATLAT : PASS
6039 05:56:35.007484 RX DQ/DQS(Engine): PASS
6040 05:56:35.010521 TX OE : NO K
6041 05:56:35.010943 All Pass.
6042 05:56:35.011273
6043 05:56:35.013847 CH 0, Rank 1
6044 05:56:35.014279 SW Impedance : PASS
6045 05:56:35.016918 DUTY Scan : NO K
6046 05:56:35.020200 ZQ Calibration : PASS
6047 05:56:35.020497 Jitter Meter : NO K
6048 05:56:35.023812 CBT Training : PASS
6049 05:56:35.026889 Write leveling : PASS
6050 05:56:35.027195 RX DQS gating : PASS
6051 05:56:35.030260 RX DQ/DQS(RDDQC) : PASS
6052 05:56:35.033653 TX DQ/DQS : PASS
6053 05:56:35.034035 RX DATLAT : PASS
6054 05:56:35.036760 RX DQ/DQS(Engine): PASS
6055 05:56:35.037276 TX OE : NO K
6056 05:56:35.039950 All Pass.
6057 05:56:35.040382
6058 05:56:35.040765 CH 1, Rank 0
6059 05:56:35.043417 SW Impedance : PASS
6060 05:56:35.046325 DUTY Scan : NO K
6061 05:56:35.046628 ZQ Calibration : PASS
6062 05:56:35.049931 Jitter Meter : NO K
6063 05:56:35.050228 CBT Training : PASS
6064 05:56:35.052952 Write leveling : PASS
6065 05:56:35.056719 RX DQS gating : PASS
6066 05:56:35.057107 RX DQ/DQS(RDDQC) : PASS
6067 05:56:35.060036 TX DQ/DQS : PASS
6068 05:56:35.062992 RX DATLAT : PASS
6069 05:56:35.063291 RX DQ/DQS(Engine): PASS
6070 05:56:35.066579 TX OE : NO K
6071 05:56:35.066878 All Pass.
6072 05:56:35.067115
6073 05:56:35.069662 CH 1, Rank 1
6074 05:56:35.069958 SW Impedance : PASS
6075 05:56:35.073505 DUTY Scan : NO K
6076 05:56:35.076564 ZQ Calibration : PASS
6077 05:56:35.076953 Jitter Meter : NO K
6078 05:56:35.079651 CBT Training : PASS
6079 05:56:35.083553 Write leveling : PASS
6080 05:56:35.084030 RX DQS gating : PASS
6081 05:56:35.086239 RX DQ/DQS(RDDQC) : PASS
6082 05:56:35.090062 TX DQ/DQS : PASS
6083 05:56:35.090576 RX DATLAT : PASS
6084 05:56:35.093633 RX DQ/DQS(Engine): PASS
6085 05:56:35.096606 TX OE : NO K
6086 05:56:35.097290 All Pass.
6087 05:56:35.097791
6088 05:56:35.098113 DramC Write-DBI off
6089 05:56:35.099819 PER_BANK_REFRESH: Hybrid Mode
6090 05:56:35.102941 TX_TRACKING: ON
6091 05:56:35.109251 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6092 05:56:35.112618 [FAST_K] Save calibration result to emmc
6093 05:56:35.119757 dramc_set_vcore_voltage set vcore to 650000
6094 05:56:35.120270 Read voltage for 400, 6
6095 05:56:35.122623 Vio18 = 0
6096 05:56:35.123035 Vcore = 650000
6097 05:56:35.123360 Vdram = 0
6098 05:56:35.125841 Vddq = 0
6099 05:56:35.126255 Vmddr = 0
6100 05:56:35.129559 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6101 05:56:35.136083 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6102 05:56:35.139236 MEM_TYPE=3, freq_sel=20
6103 05:56:35.142618 sv_algorithm_assistance_LP4_800
6104 05:56:35.145980 ============ PULL DRAM RESETB DOWN ============
6105 05:56:35.148792 ========== PULL DRAM RESETB DOWN end =========
6106 05:56:35.155475 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6107 05:56:35.156025 ===================================
6108 05:56:35.158956 LPDDR4 DRAM CONFIGURATION
6109 05:56:35.162065 ===================================
6110 05:56:35.165552 EX_ROW_EN[0] = 0x0
6111 05:56:35.165975 EX_ROW_EN[1] = 0x0
6112 05:56:35.168771 LP4Y_EN = 0x0
6113 05:56:35.169185 WORK_FSP = 0x0
6114 05:56:35.171812 WL = 0x2
6115 05:56:35.172247 RL = 0x2
6116 05:56:35.175699 BL = 0x2
6117 05:56:35.178956 RPST = 0x0
6118 05:56:35.179372 RD_PRE = 0x0
6119 05:56:35.181879 WR_PRE = 0x1
6120 05:56:35.182294 WR_PST = 0x0
6121 05:56:35.185102 DBI_WR = 0x0
6122 05:56:35.185610 DBI_RD = 0x0
6123 05:56:35.188943 OTF = 0x1
6124 05:56:35.191578 ===================================
6125 05:56:35.194996 ===================================
6126 05:56:35.195413 ANA top config
6127 05:56:35.198141 ===================================
6128 05:56:35.201546 DLL_ASYNC_EN = 0
6129 05:56:35.205187 ALL_SLAVE_EN = 1
6130 05:56:35.205655 NEW_RANK_MODE = 1
6131 05:56:35.208749 DLL_IDLE_MODE = 1
6132 05:56:35.211913 LP45_APHY_COMB_EN = 1
6133 05:56:35.215300 TX_ODT_DIS = 1
6134 05:56:35.218924 NEW_8X_MODE = 1
6135 05:56:35.221426 ===================================
6136 05:56:35.221888 ===================================
6137 05:56:35.225071 data_rate = 800
6138 05:56:35.228356 CKR = 1
6139 05:56:35.231546 DQ_P2S_RATIO = 4
6140 05:56:35.235022 ===================================
6141 05:56:35.237953 CA_P2S_RATIO = 4
6142 05:56:35.241874 DQ_CA_OPEN = 0
6143 05:56:35.244880 DQ_SEMI_OPEN = 1
6144 05:56:35.245391 CA_SEMI_OPEN = 1
6145 05:56:35.248351 CA_FULL_RATE = 0
6146 05:56:35.251479 DQ_CKDIV4_EN = 0
6147 05:56:35.254805 CA_CKDIV4_EN = 1
6148 05:56:35.258393 CA_PREDIV_EN = 0
6149 05:56:35.261504 PH8_DLY = 0
6150 05:56:35.262031 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6151 05:56:35.264818 DQ_AAMCK_DIV = 0
6152 05:56:35.267675 CA_AAMCK_DIV = 0
6153 05:56:35.271277 CA_ADMCK_DIV = 4
6154 05:56:35.274632 DQ_TRACK_CA_EN = 0
6155 05:56:35.278300 CA_PICK = 800
6156 05:56:35.279112 CA_MCKIO = 400
6157 05:56:35.281128 MCKIO_SEMI = 400
6158 05:56:35.284593 PLL_FREQ = 3016
6159 05:56:35.287642 DQ_UI_PI_RATIO = 32
6160 05:56:35.290922 CA_UI_PI_RATIO = 32
6161 05:56:35.294611 ===================================
6162 05:56:35.297410 ===================================
6163 05:56:35.300792 memory_type:LPDDR4
6164 05:56:35.301203 GP_NUM : 10
6165 05:56:35.304683 SRAM_EN : 1
6166 05:56:35.307787 MD32_EN : 0
6167 05:56:35.311402 ===================================
6168 05:56:35.311914 [ANA_INIT] >>>>>>>>>>>>>>
6169 05:56:35.314177 <<<<<< [CONFIGURE PHASE]: ANA_TX
6170 05:56:35.317582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6171 05:56:35.321137 ===================================
6172 05:56:35.324060 data_rate = 800,PCW = 0X7400
6173 05:56:35.327764 ===================================
6174 05:56:35.331123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6175 05:56:35.337754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6176 05:56:35.347393 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6177 05:56:35.354113 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6178 05:56:35.357548 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6179 05:56:35.360911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6180 05:56:35.361425 [ANA_INIT] flow start
6181 05:56:35.364139 [ANA_INIT] PLL >>>>>>>>
6182 05:56:35.366958 [ANA_INIT] PLL <<<<<<<<
6183 05:56:35.367425 [ANA_INIT] MIDPI >>>>>>>>
6184 05:56:35.370465 [ANA_INIT] MIDPI <<<<<<<<
6185 05:56:35.373980 [ANA_INIT] DLL >>>>>>>>
6186 05:56:35.374491 [ANA_INIT] flow end
6187 05:56:35.380504 ============ LP4 DIFF to SE enter ============
6188 05:56:35.383684 ============ LP4 DIFF to SE exit ============
6189 05:56:35.387019 [ANA_INIT] <<<<<<<<<<<<<
6190 05:56:35.390252 [Flow] Enable top DCM control >>>>>
6191 05:56:35.393765 [Flow] Enable top DCM control <<<<<
6192 05:56:35.394315 Enable DLL master slave shuffle
6193 05:56:35.400244 ==============================================================
6194 05:56:35.403350 Gating Mode config
6195 05:56:35.407121 ==============================================================
6196 05:56:35.410084 Config description:
6197 05:56:35.420288 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6198 05:56:35.426928 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6199 05:56:35.430115 SELPH_MODE 0: By rank 1: By Phase
6200 05:56:35.436924 ==============================================================
6201 05:56:35.439700 GAT_TRACK_EN = 0
6202 05:56:35.443273 RX_GATING_MODE = 2
6203 05:56:35.446532 RX_GATING_TRACK_MODE = 2
6204 05:56:35.449961 SELPH_MODE = 1
6205 05:56:35.453173 PICG_EARLY_EN = 1
6206 05:56:35.453630 VALID_LAT_VALUE = 1
6207 05:56:35.460033 ==============================================================
6208 05:56:35.462706 Enter into Gating configuration >>>>
6209 05:56:35.466427 Exit from Gating configuration <<<<
6210 05:56:35.469747 Enter into DVFS_PRE_config >>>>>
6211 05:56:35.479650 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6212 05:56:35.482704 Exit from DVFS_PRE_config <<<<<
6213 05:56:35.486285 Enter into PICG configuration >>>>
6214 05:56:35.489646 Exit from PICG configuration <<<<
6215 05:56:35.492827 [RX_INPUT] configuration >>>>>
6216 05:56:35.495938 [RX_INPUT] configuration <<<<<
6217 05:56:35.502699 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6218 05:56:35.506161 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6219 05:56:35.512723 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6220 05:56:35.519480 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6221 05:56:35.525574 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6222 05:56:35.532692 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6223 05:56:35.536009 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6224 05:56:35.539066 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6225 05:56:35.542428 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6226 05:56:35.549351 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6227 05:56:35.552849 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6228 05:56:35.555370 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6229 05:56:35.558985 ===================================
6230 05:56:35.562524 LPDDR4 DRAM CONFIGURATION
6231 05:56:35.565897 ===================================
6232 05:56:35.566411 EX_ROW_EN[0] = 0x0
6233 05:56:35.569075 EX_ROW_EN[1] = 0x0
6234 05:56:35.569518 LP4Y_EN = 0x0
6235 05:56:35.572651 WORK_FSP = 0x0
6236 05:56:35.575705 WL = 0x2
6237 05:56:35.576213 RL = 0x2
6238 05:56:35.579086 BL = 0x2
6239 05:56:35.579499 RPST = 0x0
6240 05:56:35.581982 RD_PRE = 0x0
6241 05:56:35.582395 WR_PRE = 0x1
6242 05:56:35.585604 WR_PST = 0x0
6243 05:56:35.586114 DBI_WR = 0x0
6244 05:56:35.589204 DBI_RD = 0x0
6245 05:56:35.589815 OTF = 0x1
6246 05:56:35.592224 ===================================
6247 05:56:35.595904 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6248 05:56:35.601956 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6249 05:56:35.605758 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6250 05:56:35.608439 ===================================
6251 05:56:35.611756 LPDDR4 DRAM CONFIGURATION
6252 05:56:35.615256 ===================================
6253 05:56:35.615671 EX_ROW_EN[0] = 0x10
6254 05:56:35.618242 EX_ROW_EN[1] = 0x0
6255 05:56:35.618654 LP4Y_EN = 0x0
6256 05:56:35.621603 WORK_FSP = 0x0
6257 05:56:35.625042 WL = 0x2
6258 05:56:35.625597 RL = 0x2
6259 05:56:35.628631 BL = 0x2
6260 05:56:35.629141 RPST = 0x0
6261 05:56:35.631808 RD_PRE = 0x0
6262 05:56:35.632325 WR_PRE = 0x1
6263 05:56:35.635230 WR_PST = 0x0
6264 05:56:35.635896 DBI_WR = 0x0
6265 05:56:35.638058 DBI_RD = 0x0
6266 05:56:35.638473 OTF = 0x1
6267 05:56:35.641381 ===================================
6268 05:56:35.647940 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6269 05:56:35.652376 nWR fixed to 30
6270 05:56:35.655658 [ModeRegInit_LP4] CH0 RK0
6271 05:56:35.656070 [ModeRegInit_LP4] CH0 RK1
6272 05:56:35.658997 [ModeRegInit_LP4] CH1 RK0
6273 05:56:35.662411 [ModeRegInit_LP4] CH1 RK1
6274 05:56:35.662915 match AC timing 19
6275 05:56:35.668688 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6276 05:56:35.672549 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6277 05:56:35.675505 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6278 05:56:35.682139 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6279 05:56:35.685541 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6280 05:56:35.686087 ==
6281 05:56:35.688444 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 05:56:35.692166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 05:56:35.692682 ==
6284 05:56:35.698745 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6285 05:56:35.705022 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6286 05:56:35.709084 [CA 0] Center 36 (8~64) winsize 57
6287 05:56:35.712073 [CA 1] Center 36 (8~64) winsize 57
6288 05:56:35.715667 [CA 2] Center 36 (8~64) winsize 57
6289 05:56:35.718781 [CA 3] Center 36 (8~64) winsize 57
6290 05:56:35.721652 [CA 4] Center 36 (8~64) winsize 57
6291 05:56:35.722071 [CA 5] Center 36 (8~64) winsize 57
6292 05:56:35.725352
6293 05:56:35.728556 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6294 05:56:35.729069
6295 05:56:35.731693 [CATrainingPosCal] consider 1 rank data
6296 05:56:35.735013 u2DelayCellTimex100 = 270/100 ps
6297 05:56:35.738076 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 05:56:35.741872 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 05:56:35.744784 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 05:56:35.748234 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 05:56:35.751656 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 05:56:35.754741 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 05:56:35.755154
6304 05:56:35.758027 CA PerBit enable=1, Macro0, CA PI delay=36
6305 05:56:35.758440
6306 05:56:35.761470 [CBTSetCACLKResult] CA Dly = 36
6307 05:56:35.764850 CS Dly: 1 (0~32)
6308 05:56:35.765264 ==
6309 05:56:35.768025 Dram Type= 6, Freq= 0, CH_0, rank 1
6310 05:56:35.770932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 05:56:35.771351 ==
6312 05:56:35.778151 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6313 05:56:35.784763 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6314 05:56:35.787361 [CA 0] Center 36 (8~64) winsize 57
6315 05:56:35.790893 [CA 1] Center 36 (8~64) winsize 57
6316 05:56:35.791424 [CA 2] Center 36 (8~64) winsize 57
6317 05:56:35.794223 [CA 3] Center 36 (8~64) winsize 57
6318 05:56:35.797555 [CA 4] Center 36 (8~64) winsize 57
6319 05:56:35.801083 [CA 5] Center 36 (8~64) winsize 57
6320 05:56:35.801682
6321 05:56:35.804427 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6322 05:56:35.804839
6323 05:56:35.811318 [CATrainingPosCal] consider 2 rank data
6324 05:56:35.811732 u2DelayCellTimex100 = 270/100 ps
6325 05:56:35.817591 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 05:56:35.820927 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 05:56:35.823890 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 05:56:35.827329 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 05:56:35.830842 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 05:56:35.833803 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 05:56:35.833953
6332 05:56:35.837349 CA PerBit enable=1, Macro0, CA PI delay=36
6333 05:56:35.837485
6334 05:56:35.840433 [CBTSetCACLKResult] CA Dly = 36
6335 05:56:35.844158 CS Dly: 1 (0~32)
6336 05:56:35.844579
6337 05:56:35.847126 ----->DramcWriteLeveling(PI) begin...
6338 05:56:35.847366 ==
6339 05:56:35.850738 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 05:56:35.854099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 05:56:35.854430 ==
6342 05:56:35.857776 Write leveling (Byte 0): 40 => 8
6343 05:56:35.860675 Write leveling (Byte 1): 32 => 0
6344 05:56:35.863766 DramcWriteLeveling(PI) end<-----
6345 05:56:35.864018
6346 05:56:35.864206 ==
6347 05:56:35.866918 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 05:56:35.870462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 05:56:35.870718 ==
6350 05:56:35.874304 [Gating] SW mode calibration
6351 05:56:35.880448 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6352 05:56:35.887281 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6353 05:56:35.891075 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6354 05:56:35.893922 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6355 05:56:35.900461 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6356 05:56:35.904176 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 05:56:35.907499 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6358 05:56:35.913875 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6359 05:56:35.917214 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 05:56:35.920749 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6361 05:56:35.927081 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6362 05:56:35.927493 Total UI for P1: 0, mck2ui 16
6363 05:56:35.933580 best dqsien dly found for B0: ( 0, 14, 24)
6364 05:56:35.933994 Total UI for P1: 0, mck2ui 16
6365 05:56:35.936982 best dqsien dly found for B1: ( 0, 14, 24)
6366 05:56:35.943686 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6367 05:56:35.947232 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6368 05:56:35.947753
6369 05:56:35.950381 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6370 05:56:35.953665 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6371 05:56:35.956851 [Gating] SW calibration Done
6372 05:56:35.957264 ==
6373 05:56:35.960388 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 05:56:35.963946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 05:56:35.964465 ==
6376 05:56:35.966489 RX Vref Scan: 0
6377 05:56:35.966899
6378 05:56:35.967221 RX Vref 0 -> 0, step: 1
6379 05:56:35.967524
6380 05:56:35.969889 RX Delay -410 -> 252, step: 16
6381 05:56:35.976748 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6382 05:56:35.980279 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6383 05:56:35.983941 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6384 05:56:35.986414 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6385 05:56:35.993632 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6386 05:56:35.996930 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6387 05:56:36.000250 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6388 05:56:36.003408 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6389 05:56:36.009849 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6390 05:56:36.013465 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6391 05:56:36.016252 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6392 05:56:36.019537 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6393 05:56:36.026402 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6394 05:56:36.029964 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6395 05:56:36.032746 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6396 05:56:36.036807 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6397 05:56:36.039553 ==
6398 05:56:36.043407 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 05:56:36.046106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 05:56:36.046522 ==
6401 05:56:36.046847 DQS Delay:
6402 05:56:36.049567 DQS0 = 59, DQS1 = 59
6403 05:56:36.050007 DQM Delay:
6404 05:56:36.052617 DQM0 = 18, DQM1 = 10
6405 05:56:36.053132 DQ Delay:
6406 05:56:36.056125 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6407 05:56:36.059572 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6408 05:56:36.063129 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6409 05:56:36.065881 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6410 05:56:36.066295
6411 05:56:36.066619
6412 05:56:36.066918 ==
6413 05:56:36.069389 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 05:56:36.072716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 05:56:36.073237 ==
6416 05:56:36.073619
6417 05:56:36.073929
6418 05:56:36.076347 TX Vref Scan disable
6419 05:56:36.076855 == TX Byte 0 ==
6420 05:56:36.082572 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6421 05:56:36.086282 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6422 05:56:36.086805 == TX Byte 1 ==
6423 05:56:36.092736 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6424 05:56:36.095789 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6425 05:56:36.096205 ==
6426 05:56:36.099497 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 05:56:36.102203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 05:56:36.102628 ==
6429 05:56:36.102960
6430 05:56:36.106104
6431 05:56:36.106610 TX Vref Scan disable
6432 05:56:36.109469 == TX Byte 0 ==
6433 05:56:36.112477 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6434 05:56:36.115679 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6435 05:56:36.118860 == TX Byte 1 ==
6436 05:56:36.122442 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6437 05:56:36.125654 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6438 05:56:36.126198
6439 05:56:36.126572 [DATLAT]
6440 05:56:36.128593 Freq=400, CH0 RK0
6441 05:56:36.129001
6442 05:56:36.131973 DATLAT Default: 0xf
6443 05:56:36.132412 0, 0xFFFF, sum = 0
6444 05:56:36.135946 1, 0xFFFF, sum = 0
6445 05:56:36.136498 2, 0xFFFF, sum = 0
6446 05:56:36.138514 3, 0xFFFF, sum = 0
6447 05:56:36.138983 4, 0xFFFF, sum = 0
6448 05:56:36.141902 5, 0xFFFF, sum = 0
6449 05:56:36.142319 6, 0xFFFF, sum = 0
6450 05:56:36.145417 7, 0xFFFF, sum = 0
6451 05:56:36.145888 8, 0xFFFF, sum = 0
6452 05:56:36.148940 9, 0xFFFF, sum = 0
6453 05:56:36.149352 10, 0xFFFF, sum = 0
6454 05:56:36.152102 11, 0xFFFF, sum = 0
6455 05:56:36.152626 12, 0xFFFF, sum = 0
6456 05:56:36.155356 13, 0x0, sum = 1
6457 05:56:36.155769 14, 0x0, sum = 2
6458 05:56:36.158116 15, 0x0, sum = 3
6459 05:56:36.158556 16, 0x0, sum = 4
6460 05:56:36.161861 best_step = 14
6461 05:56:36.162363
6462 05:56:36.162690 ==
6463 05:56:36.165509 Dram Type= 6, Freq= 0, CH_0, rank 0
6464 05:56:36.168182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 05:56:36.168680 ==
6466 05:56:36.171936 RX Vref Scan: 1
6467 05:56:36.172452
6468 05:56:36.172782 RX Vref 0 -> 0, step: 1
6469 05:56:36.173087
6470 05:56:36.174987 RX Delay -359 -> 252, step: 8
6471 05:56:36.175503
6472 05:56:36.178401 Set Vref, RX VrefLevel [Byte0]: 63
6473 05:56:36.182077 [Byte1]: 47
6474 05:56:36.186386
6475 05:56:36.186907 Final RX Vref Byte 0 = 63 to rank0
6476 05:56:36.190070 Final RX Vref Byte 1 = 47 to rank0
6477 05:56:36.193592 Final RX Vref Byte 0 = 63 to rank1
6478 05:56:36.196159 Final RX Vref Byte 1 = 47 to rank1==
6479 05:56:36.199756 Dram Type= 6, Freq= 0, CH_0, rank 0
6480 05:56:36.206033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 05:56:36.206456 ==
6482 05:56:36.206786 DQS Delay:
6483 05:56:36.209792 DQS0 = 60, DQS1 = 68
6484 05:56:36.210212 DQM Delay:
6485 05:56:36.210545 DQM0 = 14, DQM1 = 12
6486 05:56:36.213462 DQ Delay:
6487 05:56:36.216040 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =8
6488 05:56:36.220045 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6489 05:56:36.220563 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6490 05:56:36.223041 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6491 05:56:36.226303
6492 05:56:36.226873
6493 05:56:36.232900 [DQSOSCAuto] RK0, (LSB)MR18= 0x8382, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6494 05:56:36.235917 CH0 RK0: MR19=C0C, MR18=8382
6495 05:56:36.243005 CH0_RK0: MR19=0xC0C, MR18=0x8382, DQSOSC=393, MR23=63, INC=382, DEC=254
6496 05:56:36.243527 ==
6497 05:56:36.245934 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 05:56:36.249379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 05:56:36.249845 ==
6500 05:56:36.252815 [Gating] SW mode calibration
6501 05:56:36.259572 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6502 05:56:36.266306 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6503 05:56:36.269231 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6504 05:56:36.272637 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6505 05:56:36.279539 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 05:56:36.282285 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 05:56:36.285990 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 05:56:36.292514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 05:56:36.295628 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 05:56:36.299171 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 05:56:36.306026 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6512 05:56:36.306543 Total UI for P1: 0, mck2ui 16
6513 05:56:36.312586 best dqsien dly found for B0: ( 0, 14, 24)
6514 05:56:36.313114 Total UI for P1: 0, mck2ui 16
6515 05:56:36.315468 best dqsien dly found for B1: ( 0, 14, 24)
6516 05:56:36.322577 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6517 05:56:36.325519 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6518 05:56:36.325941
6519 05:56:36.329117 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6520 05:56:36.332014 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6521 05:56:36.335822 [Gating] SW calibration Done
6522 05:56:36.336369 ==
6523 05:56:36.338563 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 05:56:36.341906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 05:56:36.342324 ==
6526 05:56:36.345523 RX Vref Scan: 0
6527 05:56:36.346040
6528 05:56:36.346369 RX Vref 0 -> 0, step: 1
6529 05:56:36.346675
6530 05:56:36.348698 RX Delay -410 -> 252, step: 16
6531 05:56:36.355509 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6532 05:56:36.359086 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6533 05:56:36.361973 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6534 05:56:36.365351 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6535 05:56:36.372303 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6536 05:56:36.375893 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6537 05:56:36.378563 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6538 05:56:36.382114 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6539 05:56:36.388827 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6540 05:56:36.392038 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6541 05:56:36.395552 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6542 05:56:36.398943 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6543 05:56:36.404724 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6544 05:56:36.408592 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6545 05:56:36.411947 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6546 05:56:36.415388 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6547 05:56:36.418122 ==
6548 05:56:36.421958 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 05:56:36.425040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 05:56:36.425620 ==
6551 05:56:36.425968 DQS Delay:
6552 05:56:36.428340 DQS0 = 59, DQS1 = 59
6553 05:56:36.428862 DQM Delay:
6554 05:56:36.432020 DQM0 = 16, DQM1 = 10
6555 05:56:36.432543 DQ Delay:
6556 05:56:36.434723 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6557 05:56:36.438443 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6558 05:56:36.441704 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6559 05:56:36.444893 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6560 05:56:36.445315
6561 05:56:36.445685
6562 05:56:36.445995 ==
6563 05:56:36.448765 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 05:56:36.451323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 05:56:36.451747 ==
6566 05:56:36.452080
6567 05:56:36.452383
6568 05:56:36.454765 TX Vref Scan disable
6569 05:56:36.455188 == TX Byte 0 ==
6570 05:56:36.461629 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6571 05:56:36.464964 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6572 05:56:36.465536 == TX Byte 1 ==
6573 05:56:36.471796 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6574 05:56:36.475331 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6575 05:56:36.475853 ==
6576 05:56:36.477880 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 05:56:36.481802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 05:56:36.482330 ==
6579 05:56:36.482667
6580 05:56:36.482976
6581 05:56:36.485115 TX Vref Scan disable
6582 05:56:36.485713 == TX Byte 0 ==
6583 05:56:36.491631 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6584 05:56:36.494738 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6585 05:56:36.495160 == TX Byte 1 ==
6586 05:56:36.501898 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6587 05:56:36.504826 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6588 05:56:36.505451
6589 05:56:36.505871 [DATLAT]
6590 05:56:36.507743 Freq=400, CH0 RK1
6591 05:56:36.508160
6592 05:56:36.508487 DATLAT Default: 0xe
6593 05:56:36.511265 0, 0xFFFF, sum = 0
6594 05:56:36.511690 1, 0xFFFF, sum = 0
6595 05:56:36.514266 2, 0xFFFF, sum = 0
6596 05:56:36.514691 3, 0xFFFF, sum = 0
6597 05:56:36.517791 4, 0xFFFF, sum = 0
6598 05:56:36.518215 5, 0xFFFF, sum = 0
6599 05:56:36.521150 6, 0xFFFF, sum = 0
6600 05:56:36.521710 7, 0xFFFF, sum = 0
6601 05:56:36.524353 8, 0xFFFF, sum = 0
6602 05:56:36.527341 9, 0xFFFF, sum = 0
6603 05:56:36.527762 10, 0xFFFF, sum = 0
6604 05:56:36.530780 11, 0xFFFF, sum = 0
6605 05:56:36.531200 12, 0xFFFF, sum = 0
6606 05:56:36.534580 13, 0x0, sum = 1
6607 05:56:36.535315 14, 0x0, sum = 2
6608 05:56:36.537389 15, 0x0, sum = 3
6609 05:56:36.537814 16, 0x0, sum = 4
6610 05:56:36.538129 best_step = 14
6611 05:56:36.540939
6612 05:56:36.541347 ==
6613 05:56:36.544212 Dram Type= 6, Freq= 0, CH_0, rank 1
6614 05:56:36.547829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 05:56:36.548346 ==
6616 05:56:36.548677 RX Vref Scan: 0
6617 05:56:36.548983
6618 05:56:36.550362 RX Vref 0 -> 0, step: 1
6619 05:56:36.550777
6620 05:56:36.553946 RX Delay -359 -> 252, step: 8
6621 05:56:36.560875 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6622 05:56:36.564682 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6623 05:56:36.568255 iDelay=217, Bit 2, Center -56 (-303 ~ 192) 496
6624 05:56:36.574384 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6625 05:56:36.578111 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6626 05:56:36.581070 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6627 05:56:36.584704 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6628 05:56:36.591519 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6629 05:56:36.594115 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6630 05:56:36.597593 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6631 05:56:36.601107 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6632 05:56:36.607345 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6633 05:56:36.610882 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6634 05:56:36.614035 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6635 05:56:36.617421 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6636 05:56:36.623954 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6637 05:56:36.624468 ==
6638 05:56:36.627576 Dram Type= 6, Freq= 0, CH_0, rank 1
6639 05:56:36.630891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 05:56:36.631315 ==
6641 05:56:36.631644 DQS Delay:
6642 05:56:36.634109 DQS0 = 60, DQS1 = 72
6643 05:56:36.634643 DQM Delay:
6644 05:56:36.637642 DQM0 = 11, DQM1 = 16
6645 05:56:36.638150 DQ Delay:
6646 05:56:36.640923 DQ0 =8, DQ1 =16, DQ2 =4, DQ3 =8
6647 05:56:36.644124 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6648 05:56:36.647595 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6649 05:56:36.651092 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6650 05:56:36.651600
6651 05:56:36.651927
6652 05:56:36.657736 [DQSOSCAuto] RK1, (LSB)MR18= 0xc57a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6653 05:56:36.660781 CH0 RK1: MR19=C0C, MR18=C57A
6654 05:56:36.667263 CH0_RK1: MR19=0xC0C, MR18=0xC57A, DQSOSC=385, MR23=63, INC=398, DEC=265
6655 05:56:36.670600 [RxdqsGatingPostProcess] freq 400
6656 05:56:36.677377 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6657 05:56:36.680505 best DQS0 dly(2T, 0.5T) = (0, 10)
6658 05:56:36.684160 best DQS1 dly(2T, 0.5T) = (0, 10)
6659 05:56:36.684675 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6660 05:56:36.687083 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6661 05:56:36.690337 best DQS0 dly(2T, 0.5T) = (0, 10)
6662 05:56:36.693599 best DQS1 dly(2T, 0.5T) = (0, 10)
6663 05:56:36.697121 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6664 05:56:36.700141 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6665 05:56:36.703466 Pre-setting of DQS Precalculation
6666 05:56:36.710139 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6667 05:56:36.710645 ==
6668 05:56:36.713663 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 05:56:36.716482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 05:56:36.717001 ==
6671 05:56:36.723566 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6672 05:56:36.730109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6673 05:56:36.733181 [CA 0] Center 36 (8~64) winsize 57
6674 05:56:36.733743 [CA 1] Center 36 (8~64) winsize 57
6675 05:56:36.736606 [CA 2] Center 36 (8~64) winsize 57
6676 05:56:36.739832 [CA 3] Center 36 (8~64) winsize 57
6677 05:56:36.743310 [CA 4] Center 36 (8~64) winsize 57
6678 05:56:36.746491 [CA 5] Center 36 (8~64) winsize 57
6679 05:56:36.746914
6680 05:56:36.749408 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6681 05:56:36.749894
6682 05:56:36.752951 [CATrainingPosCal] consider 1 rank data
6683 05:56:36.756454 u2DelayCellTimex100 = 270/100 ps
6684 05:56:36.759298 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 05:56:36.766292 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 05:56:36.769428 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 05:56:36.772402 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 05:56:36.776113 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 05:56:36.779520 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 05:56:36.780034
6691 05:56:36.782706 CA PerBit enable=1, Macro0, CA PI delay=36
6692 05:56:36.783126
6693 05:56:36.786449 [CBTSetCACLKResult] CA Dly = 36
6694 05:56:36.788998 CS Dly: 1 (0~32)
6695 05:56:36.789420 ==
6696 05:56:36.792839 Dram Type= 6, Freq= 0, CH_1, rank 1
6697 05:56:36.795614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 05:56:36.796041 ==
6699 05:56:36.803010 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6700 05:56:36.805740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6701 05:56:36.809323 [CA 0] Center 36 (8~64) winsize 57
6702 05:56:36.812899 [CA 1] Center 36 (8~64) winsize 57
6703 05:56:36.816031 [CA 2] Center 36 (8~64) winsize 57
6704 05:56:36.819362 [CA 3] Center 36 (8~64) winsize 57
6705 05:56:36.822183 [CA 4] Center 36 (8~64) winsize 57
6706 05:56:36.826006 [CA 5] Center 36 (8~64) winsize 57
6707 05:56:36.826538
6708 05:56:36.829282 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6709 05:56:36.829737
6710 05:56:36.832477 [CATrainingPosCal] consider 2 rank data
6711 05:56:36.835869 u2DelayCellTimex100 = 270/100 ps
6712 05:56:36.838863 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 05:56:36.842489 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 05:56:36.845639 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 05:56:36.852408 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 05:56:36.855310 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 05:56:36.858800 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 05:56:36.859221
6719 05:56:36.862094 CA PerBit enable=1, Macro0, CA PI delay=36
6720 05:56:36.862618
6721 05:56:36.865842 [CBTSetCACLKResult] CA Dly = 36
6722 05:56:36.866394 CS Dly: 1 (0~32)
6723 05:56:36.866737
6724 05:56:36.869054 ----->DramcWriteLeveling(PI) begin...
6725 05:56:36.869553 ==
6726 05:56:36.871876 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 05:56:36.879113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 05:56:36.879637 ==
6729 05:56:36.882365 Write leveling (Byte 0): 40 => 8
6730 05:56:36.885853 Write leveling (Byte 1): 40 => 8
6731 05:56:36.886379 DramcWriteLeveling(PI) end<-----
6732 05:56:36.888871
6733 05:56:36.889292 ==
6734 05:56:36.891733 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 05:56:36.895222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 05:56:36.895645 ==
6737 05:56:36.898711 [Gating] SW mode calibration
6738 05:56:36.905085 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6739 05:56:36.908652 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6740 05:56:36.914902 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
6741 05:56:36.918350 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6742 05:56:36.921421 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6743 05:56:36.927883 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 05:56:36.931244 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6745 05:56:36.934356 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6746 05:56:36.941108 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 05:56:36.944577 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6748 05:56:36.947773 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6749 05:56:36.951197 Total UI for P1: 0, mck2ui 16
6750 05:56:36.954505 best dqsien dly found for B0: ( 0, 14, 24)
6751 05:56:36.957393 Total UI for P1: 0, mck2ui 16
6752 05:56:36.960772 best dqsien dly found for B1: ( 0, 14, 24)
6753 05:56:36.964216 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6754 05:56:36.967773 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6755 05:56:36.970530
6756 05:56:36.973724 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6757 05:56:36.977541 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6758 05:56:36.980544 [Gating] SW calibration Done
6759 05:56:36.980628 ==
6760 05:56:36.983921 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 05:56:36.987289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 05:56:36.987373 ==
6763 05:56:36.987438 RX Vref Scan: 0
6764 05:56:36.990433
6765 05:56:36.990515 RX Vref 0 -> 0, step: 1
6766 05:56:36.990580
6767 05:56:36.994180 RX Delay -410 -> 252, step: 16
6768 05:56:36.997452 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6769 05:56:37.004008 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6770 05:56:37.006963 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6771 05:56:37.010564 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6772 05:56:37.013762 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6773 05:56:37.020303 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6774 05:56:37.023656 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6775 05:56:37.026923 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6776 05:56:37.030414 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6777 05:56:37.036761 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6778 05:56:37.040225 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6779 05:56:37.043528 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6780 05:56:37.046614 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6781 05:56:37.053317 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6782 05:56:37.057015 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6783 05:56:37.060199 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6784 05:56:37.060282 ==
6785 05:56:37.063734 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 05:56:37.070135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 05:56:37.070219 ==
6788 05:56:37.070284 DQS Delay:
6789 05:56:37.073666 DQS0 = 51, DQS1 = 67
6790 05:56:37.073750 DQM Delay:
6791 05:56:37.073814 DQM0 = 13, DQM1 = 20
6792 05:56:37.076557 DQ Delay:
6793 05:56:37.080048 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6794 05:56:37.083539 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6795 05:56:37.083621 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6796 05:56:37.086847 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6797 05:56:37.090155
6798 05:56:37.090237
6799 05:56:37.090301 ==
6800 05:56:37.093493 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 05:56:37.096674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 05:56:37.096757 ==
6803 05:56:37.096821
6804 05:56:37.096880
6805 05:56:37.099893 TX Vref Scan disable
6806 05:56:37.099975 == TX Byte 0 ==
6807 05:56:37.103241 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6808 05:56:37.109646 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6809 05:56:37.109732 == TX Byte 1 ==
6810 05:56:37.113061 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 05:56:37.119462 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 05:56:37.119544 ==
6813 05:56:37.122990 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 05:56:37.126513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 05:56:37.126596 ==
6816 05:56:37.126660
6817 05:56:37.126719
6818 05:56:37.129308 TX Vref Scan disable
6819 05:56:37.129415 == TX Byte 0 ==
6820 05:56:37.136070 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6821 05:56:37.139634 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6822 05:56:37.139716 == TX Byte 1 ==
6823 05:56:37.146053 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6824 05:56:37.149594 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6825 05:56:37.149675
6826 05:56:37.149739 [DATLAT]
6827 05:56:37.152651 Freq=400, CH1 RK0
6828 05:56:37.152733
6829 05:56:37.152797 DATLAT Default: 0xf
6830 05:56:37.156019 0, 0xFFFF, sum = 0
6831 05:56:37.156102 1, 0xFFFF, sum = 0
6832 05:56:37.159332 2, 0xFFFF, sum = 0
6833 05:56:37.159414 3, 0xFFFF, sum = 0
6834 05:56:37.162392 4, 0xFFFF, sum = 0
6835 05:56:37.162475 5, 0xFFFF, sum = 0
6836 05:56:37.166391 6, 0xFFFF, sum = 0
6837 05:56:37.166479 7, 0xFFFF, sum = 0
6838 05:56:37.169365 8, 0xFFFF, sum = 0
6839 05:56:37.169448 9, 0xFFFF, sum = 0
6840 05:56:37.172757 10, 0xFFFF, sum = 0
6841 05:56:37.172839 11, 0xFFFF, sum = 0
6842 05:56:37.176010 12, 0xFFFF, sum = 0
6843 05:56:37.179076 13, 0x0, sum = 1
6844 05:56:37.179158 14, 0x0, sum = 2
6845 05:56:37.179223 15, 0x0, sum = 3
6846 05:56:37.182480 16, 0x0, sum = 4
6847 05:56:37.182562 best_step = 14
6848 05:56:37.182625
6849 05:56:37.182684 ==
6850 05:56:37.185971 Dram Type= 6, Freq= 0, CH_1, rank 0
6851 05:56:37.192402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 05:56:37.192485 ==
6853 05:56:37.192549 RX Vref Scan: 1
6854 05:56:37.192608
6855 05:56:37.195976 RX Vref 0 -> 0, step: 1
6856 05:56:37.196057
6857 05:56:37.198948 RX Delay -375 -> 252, step: 8
6858 05:56:37.199029
6859 05:56:37.202423 Set Vref, RX VrefLevel [Byte0]: 55
6860 05:56:37.205600 [Byte1]: 51
6861 05:56:37.209237
6862 05:56:37.209319 Final RX Vref Byte 0 = 55 to rank0
6863 05:56:37.212590 Final RX Vref Byte 1 = 51 to rank0
6864 05:56:37.215735 Final RX Vref Byte 0 = 55 to rank1
6865 05:56:37.219183 Final RX Vref Byte 1 = 51 to rank1==
6866 05:56:37.222364 Dram Type= 6, Freq= 0, CH_1, rank 0
6867 05:56:37.229313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 05:56:37.229397 ==
6869 05:56:37.229463 DQS Delay:
6870 05:56:37.232638 DQS0 = 56, DQS1 = 64
6871 05:56:37.232719 DQM Delay:
6872 05:56:37.232784 DQM0 = 13, DQM1 = 10
6873 05:56:37.236108 DQ Delay:
6874 05:56:37.239055 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6875 05:56:37.239137 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =12
6876 05:56:37.242473 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6877 05:56:37.245588 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6878 05:56:37.249132
6879 05:56:37.249213
6880 05:56:37.255490 [DQSOSCAuto] RK0, (LSB)MR18= 0x5164, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 399 ps
6881 05:56:37.258918 CH1 RK0: MR19=C0C, MR18=5164
6882 05:56:37.265253 CH1_RK0: MR19=0xC0C, MR18=0x5164, DQSOSC=397, MR23=63, INC=374, DEC=249
6883 05:56:37.265336 ==
6884 05:56:37.268538 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 05:56:37.271944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 05:56:37.272027 ==
6887 05:56:37.275450 [Gating] SW mode calibration
6888 05:56:37.281844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6889 05:56:37.288468 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6890 05:56:37.291745 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6891 05:56:37.295109 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6892 05:56:37.302008 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6893 05:56:37.304920 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 05:56:37.308390 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6895 05:56:37.315240 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6896 05:56:37.318044 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 05:56:37.321697 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6898 05:56:37.328162 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6899 05:56:37.328265 Total UI for P1: 0, mck2ui 16
6900 05:56:37.334914 best dqsien dly found for B0: ( 0, 14, 24)
6901 05:56:37.335100 Total UI for P1: 0, mck2ui 16
6902 05:56:37.341256 best dqsien dly found for B1: ( 0, 14, 24)
6903 05:56:37.344667 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6904 05:56:37.348038 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6905 05:56:37.348121
6906 05:56:37.351535 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6907 05:56:37.354528 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6908 05:56:37.358024 [Gating] SW calibration Done
6909 05:56:37.358107 ==
6910 05:56:37.361087 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 05:56:37.364547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 05:56:37.364630 ==
6913 05:56:37.368044 RX Vref Scan: 0
6914 05:56:37.368126
6915 05:56:37.368190 RX Vref 0 -> 0, step: 1
6916 05:56:37.368249
6917 05:56:37.370962 RX Delay -410 -> 252, step: 16
6918 05:56:37.377598 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6919 05:56:37.380985 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6920 05:56:37.384419 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6921 05:56:37.387981 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6922 05:56:37.394598 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6923 05:56:37.397618 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6924 05:56:37.401176 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6925 05:56:37.405201 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6926 05:56:37.411473 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6927 05:56:37.414573 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6928 05:56:37.418114 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6929 05:56:37.420953 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6930 05:56:37.427590 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6931 05:56:37.431024 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6932 05:56:37.434377 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6933 05:56:37.440940 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6934 05:56:37.441176 ==
6935 05:56:37.444354 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 05:56:37.447712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 05:56:37.447948 ==
6938 05:56:37.448133 DQS Delay:
6939 05:56:37.451209 DQS0 = 59, DQS1 = 59
6940 05:56:37.451446 DQM Delay:
6941 05:56:37.454394 DQM0 = 19, DQM1 = 14
6942 05:56:37.454745 DQ Delay:
6943 05:56:37.457614 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6944 05:56:37.461320 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6945 05:56:37.464824 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6946 05:56:37.467667 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6947 05:56:37.467971
6948 05:56:37.468201
6949 05:56:37.468414 ==
6950 05:56:37.471188 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 05:56:37.474147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 05:56:37.474441 ==
6953 05:56:37.474670
6954 05:56:37.474922
6955 05:56:37.477558 TX Vref Scan disable
6956 05:56:37.481343 == TX Byte 0 ==
6957 05:56:37.484040 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6958 05:56:37.487375 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6959 05:56:37.487762 == TX Byte 1 ==
6960 05:56:37.494407 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6961 05:56:37.497924 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6962 05:56:37.498307 ==
6963 05:56:37.501052 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 05:56:37.504194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 05:56:37.504674 ==
6966 05:56:37.504975
6967 05:56:37.505280
6968 05:56:37.507657 TX Vref Scan disable
6969 05:56:37.510965 == TX Byte 0 ==
6970 05:56:37.514098 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6971 05:56:37.517447 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6972 05:56:37.520418 == TX Byte 1 ==
6973 05:56:37.524193 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6974 05:56:37.527836 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6975 05:56:37.528311
6976 05:56:37.528611 [DATLAT]
6977 05:56:37.530463 Freq=400, CH1 RK1
6978 05:56:37.530839
6979 05:56:37.531136 DATLAT Default: 0xe
6980 05:56:37.533828 0, 0xFFFF, sum = 0
6981 05:56:37.537223 1, 0xFFFF, sum = 0
6982 05:56:37.537769 2, 0xFFFF, sum = 0
6983 05:56:37.540578 3, 0xFFFF, sum = 0
6984 05:56:37.541059 4, 0xFFFF, sum = 0
6985 05:56:37.543958 5, 0xFFFF, sum = 0
6986 05:56:37.544340 6, 0xFFFF, sum = 0
6987 05:56:37.547423 7, 0xFFFF, sum = 0
6988 05:56:37.547806 8, 0xFFFF, sum = 0
6989 05:56:37.550397 9, 0xFFFF, sum = 0
6990 05:56:37.550780 10, 0xFFFF, sum = 0
6991 05:56:37.553689 11, 0xFFFF, sum = 0
6992 05:56:37.554078 12, 0xFFFF, sum = 0
6993 05:56:37.556531 13, 0x0, sum = 1
6994 05:56:37.556949 14, 0x0, sum = 2
6995 05:56:37.559951 15, 0x0, sum = 3
6996 05:56:37.560335 16, 0x0, sum = 4
6997 05:56:37.563580 best_step = 14
6998 05:56:37.563985
6999 05:56:37.564283 ==
7000 05:56:37.566932 Dram Type= 6, Freq= 0, CH_1, rank 1
7001 05:56:37.569960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7002 05:56:37.570339 ==
7003 05:56:37.573786 RX Vref Scan: 0
7004 05:56:37.574162
7005 05:56:37.574456 RX Vref 0 -> 0, step: 1
7006 05:56:37.574734
7007 05:56:37.576600 RX Delay -359 -> 252, step: 8
7008 05:56:37.584323 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7009 05:56:37.588154 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7010 05:56:37.591081 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7011 05:56:37.594803 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7012 05:56:37.601030 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7013 05:56:37.604450 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7014 05:56:37.607406 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7015 05:56:37.614074 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7016 05:56:37.617529 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7017 05:56:37.621029 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7018 05:56:37.623844 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7019 05:56:37.630403 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7020 05:56:37.634055 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7021 05:56:37.637005 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7022 05:56:37.640596 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7023 05:56:37.647084 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7024 05:56:37.647411 ==
7025 05:56:37.650358 Dram Type= 6, Freq= 0, CH_1, rank 1
7026 05:56:37.653536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7027 05:56:37.653788 ==
7028 05:56:37.653977 DQS Delay:
7029 05:56:37.656794 DQS0 = 60, DQS1 = 64
7030 05:56:37.656991 DQM Delay:
7031 05:56:37.660212 DQM0 = 12, DQM1 = 10
7032 05:56:37.660380 DQ Delay:
7033 05:56:37.663242 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7034 05:56:37.666610 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7035 05:56:37.669989 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7036 05:56:37.673617 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7037 05:56:37.673702
7038 05:56:37.673767
7039 05:56:37.680502 [DQSOSCAuto] RK1, (LSB)MR18= 0x72a3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
7040 05:56:37.683623 CH1 RK1: MR19=C0C, MR18=72A3
7041 05:56:37.690207 CH1_RK1: MR19=0xC0C, MR18=0x72A3, DQSOSC=389, MR23=63, INC=390, DEC=260
7042 05:56:37.693760 [RxdqsGatingPostProcess] freq 400
7043 05:56:37.700404 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7044 05:56:37.703787 best DQS0 dly(2T, 0.5T) = (0, 10)
7045 05:56:37.703945 best DQS1 dly(2T, 0.5T) = (0, 10)
7046 05:56:37.706840 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7047 05:56:37.710184 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7048 05:56:37.713263 best DQS0 dly(2T, 0.5T) = (0, 10)
7049 05:56:37.716657 best DQS1 dly(2T, 0.5T) = (0, 10)
7050 05:56:37.719707 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7051 05:56:37.723359 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7052 05:56:37.726926 Pre-setting of DQS Precalculation
7053 05:56:37.733079 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7054 05:56:37.740248 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7055 05:56:37.746853 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7056 05:56:37.747102
7057 05:56:37.747252
7058 05:56:37.749697 [Calibration Summary] 800 Mbps
7059 05:56:37.749897 CH 0, Rank 0
7060 05:56:37.753099 SW Impedance : PASS
7061 05:56:37.756789 DUTY Scan : NO K
7062 05:56:37.757108 ZQ Calibration : PASS
7063 05:56:37.759384 Jitter Meter : NO K
7064 05:56:37.763004 CBT Training : PASS
7065 05:56:37.763479 Write leveling : PASS
7066 05:56:37.766643 RX DQS gating : PASS
7067 05:56:37.769837 RX DQ/DQS(RDDQC) : PASS
7068 05:56:37.770429 TX DQ/DQS : PASS
7069 05:56:37.772823 RX DATLAT : PASS
7070 05:56:37.776425 RX DQ/DQS(Engine): PASS
7071 05:56:37.776837 TX OE : NO K
7072 05:56:37.777165 All Pass.
7073 05:56:37.779705
7074 05:56:37.780215 CH 0, Rank 1
7075 05:56:37.782792 SW Impedance : PASS
7076 05:56:37.783202 DUTY Scan : NO K
7077 05:56:37.786377 ZQ Calibration : PASS
7078 05:56:37.790025 Jitter Meter : NO K
7079 05:56:37.790539 CBT Training : PASS
7080 05:56:37.792749 Write leveling : NO K
7081 05:56:37.793119 RX DQS gating : PASS
7082 05:56:37.796608 RX DQ/DQS(RDDQC) : PASS
7083 05:56:37.799220 TX DQ/DQS : PASS
7084 05:56:37.799638 RX DATLAT : PASS
7085 05:56:37.803195 RX DQ/DQS(Engine): PASS
7086 05:56:37.805966 TX OE : NO K
7087 05:56:37.806382 All Pass.
7088 05:56:37.806707
7089 05:56:37.807007 CH 1, Rank 0
7090 05:56:37.809168 SW Impedance : PASS
7091 05:56:37.812548 DUTY Scan : NO K
7092 05:56:37.813111 ZQ Calibration : PASS
7093 05:56:37.816493 Jitter Meter : NO K
7094 05:56:37.819414 CBT Training : PASS
7095 05:56:37.819927 Write leveling : PASS
7096 05:56:37.822430 RX DQS gating : PASS
7097 05:56:37.826294 RX DQ/DQS(RDDQC) : PASS
7098 05:56:37.826800 TX DQ/DQS : PASS
7099 05:56:37.829538 RX DATLAT : PASS
7100 05:56:37.832647 RX DQ/DQS(Engine): PASS
7101 05:56:37.833154 TX OE : NO K
7102 05:56:37.836080 All Pass.
7103 05:56:37.836582
7104 05:56:37.836908 CH 1, Rank 1
7105 05:56:37.839513 SW Impedance : PASS
7106 05:56:37.840017 DUTY Scan : NO K
7107 05:56:37.842124 ZQ Calibration : PASS
7108 05:56:37.846057 Jitter Meter : NO K
7109 05:56:37.846560 CBT Training : PASS
7110 05:56:37.849464 Write leveling : NO K
7111 05:56:37.850021 RX DQS gating : PASS
7112 05:56:37.852718 RX DQ/DQS(RDDQC) : PASS
7113 05:56:37.855286 TX DQ/DQS : PASS
7114 05:56:37.855831 RX DATLAT : PASS
7115 05:56:37.858667 RX DQ/DQS(Engine): PASS
7116 05:56:37.862758 TX OE : NO K
7117 05:56:37.863283 All Pass.
7118 05:56:37.863613
7119 05:56:37.865456 DramC Write-DBI off
7120 05:56:37.865911 PER_BANK_REFRESH: Hybrid Mode
7121 05:56:37.868672 TX_TRACKING: ON
7122 05:56:37.879032 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7123 05:56:37.882131 [FAST_K] Save calibration result to emmc
7124 05:56:37.885632 dramc_set_vcore_voltage set vcore to 725000
7125 05:56:37.886098 Read voltage for 1600, 0
7126 05:56:37.889227 Vio18 = 0
7127 05:56:37.889854 Vcore = 725000
7128 05:56:37.890285 Vdram = 0
7129 05:56:37.892209 Vddq = 0
7130 05:56:37.892790 Vmddr = 0
7131 05:56:37.898536 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7132 05:56:37.901976 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7133 05:56:37.905263 MEM_TYPE=3, freq_sel=13
7134 05:56:37.908750 sv_algorithm_assistance_LP4_3733
7135 05:56:37.912078 ============ PULL DRAM RESETB DOWN ============
7136 05:56:37.915422 ========== PULL DRAM RESETB DOWN end =========
7137 05:56:37.921971 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7138 05:56:37.925253 ===================================
7139 05:56:37.925729 LPDDR4 DRAM CONFIGURATION
7140 05:56:37.928859 ===================================
7141 05:56:37.931815 EX_ROW_EN[0] = 0x0
7142 05:56:37.935276 EX_ROW_EN[1] = 0x0
7143 05:56:37.935690 LP4Y_EN = 0x0
7144 05:56:37.938450 WORK_FSP = 0x1
7145 05:56:37.938863 WL = 0x5
7146 05:56:37.941894 RL = 0x5
7147 05:56:37.942210 BL = 0x2
7148 05:56:37.945334 RPST = 0x0
7149 05:56:37.945660 RD_PRE = 0x0
7150 05:56:37.948161 WR_PRE = 0x1
7151 05:56:37.948382 WR_PST = 0x1
7152 05:56:37.951515 DBI_WR = 0x0
7153 05:56:37.951751 DBI_RD = 0x0
7154 05:56:37.955108 OTF = 0x1
7155 05:56:37.957786 ===================================
7156 05:56:37.961453 ===================================
7157 05:56:37.961559 ANA top config
7158 05:56:37.964941 ===================================
7159 05:56:37.967866 DLL_ASYNC_EN = 0
7160 05:56:37.971080 ALL_SLAVE_EN = 0
7161 05:56:37.971154 NEW_RANK_MODE = 1
7162 05:56:37.974490 DLL_IDLE_MODE = 1
7163 05:56:37.978273 LP45_APHY_COMB_EN = 1
7164 05:56:37.981782 TX_ODT_DIS = 0
7165 05:56:37.985137 NEW_8X_MODE = 1
7166 05:56:37.988337 ===================================
7167 05:56:37.991191 ===================================
7168 05:56:37.991671 data_rate = 3200
7169 05:56:37.995029 CKR = 1
7170 05:56:37.997714 DQ_P2S_RATIO = 8
7171 05:56:38.001385 ===================================
7172 05:56:38.004790 CA_P2S_RATIO = 8
7173 05:56:38.007656 DQ_CA_OPEN = 0
7174 05:56:38.011234 DQ_SEMI_OPEN = 0
7175 05:56:38.011790 CA_SEMI_OPEN = 0
7176 05:56:38.014684 CA_FULL_RATE = 0
7177 05:56:38.017582 DQ_CKDIV4_EN = 0
7178 05:56:38.020868 CA_CKDIV4_EN = 0
7179 05:56:38.024555 CA_PREDIV_EN = 0
7180 05:56:38.027801 PH8_DLY = 12
7181 05:56:38.030980 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7182 05:56:38.031388 DQ_AAMCK_DIV = 4
7183 05:56:38.034394 CA_AAMCK_DIV = 4
7184 05:56:38.037446 CA_ADMCK_DIV = 4
7185 05:56:38.040854 DQ_TRACK_CA_EN = 0
7186 05:56:38.044217 CA_PICK = 1600
7187 05:56:38.047620 CA_MCKIO = 1600
7188 05:56:38.050743 MCKIO_SEMI = 0
7189 05:56:38.051163 PLL_FREQ = 3068
7190 05:56:38.054393 DQ_UI_PI_RATIO = 32
7191 05:56:38.057816 CA_UI_PI_RATIO = 0
7192 05:56:38.060660 ===================================
7193 05:56:38.064110 ===================================
7194 05:56:38.067633 memory_type:LPDDR4
7195 05:56:38.068054 GP_NUM : 10
7196 05:56:38.070497 SRAM_EN : 1
7197 05:56:38.074147 MD32_EN : 0
7198 05:56:38.077759 ===================================
7199 05:56:38.078273 [ANA_INIT] >>>>>>>>>>>>>>
7200 05:56:38.080858 <<<<<< [CONFIGURE PHASE]: ANA_TX
7201 05:56:38.084401 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7202 05:56:38.087723 ===================================
7203 05:56:38.090639 data_rate = 3200,PCW = 0X7600
7204 05:56:38.094023 ===================================
7205 05:56:38.097064 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7206 05:56:38.103857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7207 05:56:38.110607 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7208 05:56:38.113807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7209 05:56:38.116690 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7210 05:56:38.120320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7211 05:56:38.123750 [ANA_INIT] flow start
7212 05:56:38.124296 [ANA_INIT] PLL >>>>>>>>
7213 05:56:38.127102 [ANA_INIT] PLL <<<<<<<<
7214 05:56:38.130574 [ANA_INIT] MIDPI >>>>>>>>
7215 05:56:38.131019 [ANA_INIT] MIDPI <<<<<<<<
7216 05:56:38.133456 [ANA_INIT] DLL >>>>>>>>
7217 05:56:38.136950 [ANA_INIT] DLL <<<<<<<<
7218 05:56:38.137360 [ANA_INIT] flow end
7219 05:56:38.143316 ============ LP4 DIFF to SE enter ============
7220 05:56:38.146896 ============ LP4 DIFF to SE exit ============
7221 05:56:38.150105 [ANA_INIT] <<<<<<<<<<<<<
7222 05:56:38.153371 [Flow] Enable top DCM control >>>>>
7223 05:56:38.157168 [Flow] Enable top DCM control <<<<<
7224 05:56:38.157758 Enable DLL master slave shuffle
7225 05:56:38.163473 ==============================================================
7226 05:56:38.166646 Gating Mode config
7227 05:56:38.170185 ==============================================================
7228 05:56:38.172942 Config description:
7229 05:56:38.183112 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7230 05:56:38.189980 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7231 05:56:38.193439 SELPH_MODE 0: By rank 1: By Phase
7232 05:56:38.199455 ==============================================================
7233 05:56:38.203272 GAT_TRACK_EN = 1
7234 05:56:38.206128 RX_GATING_MODE = 2
7235 05:56:38.209541 RX_GATING_TRACK_MODE = 2
7236 05:56:38.212694 SELPH_MODE = 1
7237 05:56:38.213180 PICG_EARLY_EN = 1
7238 05:56:38.216352 VALID_LAT_VALUE = 1
7239 05:56:38.222771 ==============================================================
7240 05:56:38.226235 Enter into Gating configuration >>>>
7241 05:56:38.228975 Exit from Gating configuration <<<<
7242 05:56:38.232382 Enter into DVFS_PRE_config >>>>>
7243 05:56:38.242770 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7244 05:56:38.245785 Exit from DVFS_PRE_config <<<<<
7245 05:56:38.249255 Enter into PICG configuration >>>>
7246 05:56:38.252551 Exit from PICG configuration <<<<
7247 05:56:38.255636 [RX_INPUT] configuration >>>>>
7248 05:56:38.259077 [RX_INPUT] configuration <<<<<
7249 05:56:38.266213 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7250 05:56:38.269002 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7251 05:56:38.275917 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7252 05:56:38.282538 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7253 05:56:38.288830 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7254 05:56:38.295715 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7255 05:56:38.299149 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7256 05:56:38.302105 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7257 05:56:38.305469 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7258 05:56:38.312361 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7259 05:56:38.315696 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7260 05:56:38.318566 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7261 05:56:38.321946 ===================================
7262 05:56:38.325358 LPDDR4 DRAM CONFIGURATION
7263 05:56:38.328529 ===================================
7264 05:56:38.329034 EX_ROW_EN[0] = 0x0
7265 05:56:38.331871 EX_ROW_EN[1] = 0x0
7266 05:56:38.334864 LP4Y_EN = 0x0
7267 05:56:38.335274 WORK_FSP = 0x1
7268 05:56:38.338435 WL = 0x5
7269 05:56:38.338843 RL = 0x5
7270 05:56:38.341989 BL = 0x2
7271 05:56:38.342547 RPST = 0x0
7272 05:56:38.344856 RD_PRE = 0x0
7273 05:56:38.345266 WR_PRE = 0x1
7274 05:56:38.348451 WR_PST = 0x1
7275 05:56:38.348863 DBI_WR = 0x0
7276 05:56:38.352018 DBI_RD = 0x0
7277 05:56:38.352427 OTF = 0x1
7278 05:56:38.354974 ===================================
7279 05:56:38.358775 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7280 05:56:38.364505 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7281 05:56:38.368458 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7282 05:56:38.371600 ===================================
7283 05:56:38.374888 LPDDR4 DRAM CONFIGURATION
7284 05:56:38.378140 ===================================
7285 05:56:38.378582 EX_ROW_EN[0] = 0x10
7286 05:56:38.381112 EX_ROW_EN[1] = 0x0
7287 05:56:38.384724 LP4Y_EN = 0x0
7288 05:56:38.385282 WORK_FSP = 0x1
7289 05:56:38.387560 WL = 0x5
7290 05:56:38.388011 RL = 0x5
7291 05:56:38.391002 BL = 0x2
7292 05:56:38.391443 RPST = 0x0
7293 05:56:38.394806 RD_PRE = 0x0
7294 05:56:38.395443 WR_PRE = 0x1
7295 05:56:38.398172 WR_PST = 0x1
7296 05:56:38.398750 DBI_WR = 0x0
7297 05:56:38.401220 DBI_RD = 0x0
7298 05:56:38.401906 OTF = 0x1
7299 05:56:38.404457 ===================================
7300 05:56:38.410882 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7301 05:56:38.411296 ==
7302 05:56:38.414459 Dram Type= 6, Freq= 0, CH_0, rank 0
7303 05:56:38.417603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7304 05:56:38.421061 ==
7305 05:56:38.421470 [Duty_Offset_Calibration]
7306 05:56:38.423876 B0:2 B1:0 CA:3
7307 05:56:38.424303
7308 05:56:38.427653 [DutyScan_Calibration_Flow] k_type=0
7309 05:56:38.436403
7310 05:56:38.436814 ==CLK 0==
7311 05:56:38.439640 Final CLK duty delay cell = 0
7312 05:56:38.443141 [0] MAX Duty = 5031%(X100), DQS PI = 12
7313 05:56:38.446063 [0] MIN Duty = 4907%(X100), DQS PI = 6
7314 05:56:38.446939 [0] AVG Duty = 4969%(X100)
7315 05:56:38.449812
7316 05:56:38.453033 CH0 CLK Duty spec in!! Max-Min= 124%
7317 05:56:38.456192 [DutyScan_Calibration_Flow] ====Done====
7318 05:56:38.456700
7319 05:56:38.459713 [DutyScan_Calibration_Flow] k_type=1
7320 05:56:38.475909
7321 05:56:38.476373 ==DQS 0 ==
7322 05:56:38.479466 Final DQS duty delay cell = 0
7323 05:56:38.482898 [0] MAX Duty = 5125%(X100), DQS PI = 30
7324 05:56:38.486402 [0] MIN Duty = 4875%(X100), DQS PI = 48
7325 05:56:38.489404 [0] AVG Duty = 5000%(X100)
7326 05:56:38.489867
7327 05:56:38.490195 ==DQS 1 ==
7328 05:56:38.492688 Final DQS duty delay cell = 0
7329 05:56:38.496082 [0] MAX Duty = 5156%(X100), DQS PI = 30
7330 05:56:38.499517 [0] MIN Duty = 5031%(X100), DQS PI = 12
7331 05:56:38.502666 [0] AVG Duty = 5093%(X100)
7332 05:56:38.503120
7333 05:56:38.506169 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7334 05:56:38.506582
7335 05:56:38.509081 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7336 05:56:38.512709 [DutyScan_Calibration_Flow] ====Done====
7337 05:56:38.513120
7338 05:56:38.515652 [DutyScan_Calibration_Flow] k_type=3
7339 05:56:38.533892
7340 05:56:38.534312 ==DQM 0 ==
7341 05:56:38.537374 Final DQM duty delay cell = 0
7342 05:56:38.540533 [0] MAX Duty = 5156%(X100), DQS PI = 30
7343 05:56:38.544196 [0] MIN Duty = 4844%(X100), DQS PI = 52
7344 05:56:38.547344 [0] AVG Duty = 5000%(X100)
7345 05:56:38.547890
7346 05:56:38.548398 ==DQM 1 ==
7347 05:56:38.550322 Final DQM duty delay cell = 4
7348 05:56:38.554113 [4] MAX Duty = 5187%(X100), DQS PI = 62
7349 05:56:38.557529 [4] MIN Duty = 5000%(X100), DQS PI = 38
7350 05:56:38.560309 [4] AVG Duty = 5093%(X100)
7351 05:56:38.560729
7352 05:56:38.563512 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7353 05:56:38.564193
7354 05:56:38.567214 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7355 05:56:38.570295 [DutyScan_Calibration_Flow] ====Done====
7356 05:56:38.570888
7357 05:56:38.573908 [DutyScan_Calibration_Flow] k_type=2
7358 05:56:38.590630
7359 05:56:38.591042 ==DQ 0 ==
7360 05:56:38.593388 Final DQ duty delay cell = -4
7361 05:56:38.597002 [-4] MAX Duty = 5000%(X100), DQS PI = 12
7362 05:56:38.600204 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7363 05:56:38.603494 [-4] AVG Duty = 4938%(X100)
7364 05:56:38.603951
7365 05:56:38.604471 ==DQ 1 ==
7366 05:56:38.606809 Final DQ duty delay cell = 0
7367 05:56:38.610433 [0] MAX Duty = 5156%(X100), DQS PI = 58
7368 05:56:38.613420 [0] MIN Duty = 5000%(X100), DQS PI = 16
7369 05:56:38.616425 [0] AVG Duty = 5078%(X100)
7370 05:56:38.616651
7371 05:56:38.619791 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7372 05:56:38.619968
7373 05:56:38.622848 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7374 05:56:38.626278 [DutyScan_Calibration_Flow] ====Done====
7375 05:56:38.626426 ==
7376 05:56:38.629899 Dram Type= 6, Freq= 0, CH_1, rank 0
7377 05:56:38.632780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7378 05:56:38.632930 ==
7379 05:56:38.636495 [Duty_Offset_Calibration]
7380 05:56:38.636641 B0:1 B1:-2 CA:0
7381 05:56:38.636759
7382 05:56:38.639463 [DutyScan_Calibration_Flow] k_type=0
7383 05:56:38.650679
7384 05:56:38.651170 ==CLK 0==
7385 05:56:38.654104 Final CLK duty delay cell = 0
7386 05:56:38.657594 [0] MAX Duty = 5093%(X100), DQS PI = 22
7387 05:56:38.660996 [0] MIN Duty = 4844%(X100), DQS PI = 2
7388 05:56:38.661405 [0] AVG Duty = 4968%(X100)
7389 05:56:38.664213
7390 05:56:38.664665 CH1 CLK Duty spec in!! Max-Min= 249%
7391 05:56:38.670726 [DutyScan_Calibration_Flow] ====Done====
7392 05:56:38.671134
7393 05:56:38.673805 [DutyScan_Calibration_Flow] k_type=1
7394 05:56:38.690300
7395 05:56:38.690803 ==DQS 0 ==
7396 05:56:38.693862 Final DQS duty delay cell = 0
7397 05:56:38.696756 [0] MAX Duty = 5187%(X100), DQS PI = 24
7398 05:56:38.700061 [0] MIN Duty = 5062%(X100), DQS PI = 0
7399 05:56:38.703692 [0] AVG Duty = 5124%(X100)
7400 05:56:38.704164
7401 05:56:38.704515 ==DQS 1 ==
7402 05:56:38.706846 Final DQS duty delay cell = 0
7403 05:56:38.710195 [0] MAX Duty = 5093%(X100), DQS PI = 60
7404 05:56:38.713514 [0] MIN Duty = 4844%(X100), DQS PI = 24
7405 05:56:38.716934 [0] AVG Duty = 4968%(X100)
7406 05:56:38.717350
7407 05:56:38.720120 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7408 05:56:38.720627
7409 05:56:38.723285 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7410 05:56:38.726796 [DutyScan_Calibration_Flow] ====Done====
7411 05:56:38.727214
7412 05:56:38.730158 [DutyScan_Calibration_Flow] k_type=3
7413 05:56:38.747319
7414 05:56:38.747826 ==DQM 0 ==
7415 05:56:38.750639 Final DQM duty delay cell = 0
7416 05:56:38.753469 [0] MAX Duty = 5031%(X100), DQS PI = 24
7417 05:56:38.757120 [0] MIN Duty = 4813%(X100), DQS PI = 54
7418 05:56:38.760106 [0] AVG Duty = 4922%(X100)
7419 05:56:38.760614
7420 05:56:38.760940 ==DQM 1 ==
7421 05:56:38.763611 Final DQM duty delay cell = 0
7422 05:56:38.766643 [0] MAX Duty = 5062%(X100), DQS PI = 34
7423 05:56:38.770100 [0] MIN Duty = 4875%(X100), DQS PI = 24
7424 05:56:38.773619 [0] AVG Duty = 4968%(X100)
7425 05:56:38.774042
7426 05:56:38.776540 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7427 05:56:38.777226
7428 05:56:38.779508 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7429 05:56:38.783002 [DutyScan_Calibration_Flow] ====Done====
7430 05:56:38.783424
7431 05:56:38.786698 [DutyScan_Calibration_Flow] k_type=2
7432 05:56:38.804237
7433 05:56:38.804655 ==DQ 0 ==
7434 05:56:38.807220 Final DQ duty delay cell = 0
7435 05:56:38.810412 [0] MAX Duty = 5093%(X100), DQS PI = 22
7436 05:56:38.813582 [0] MIN Duty = 4907%(X100), DQS PI = 48
7437 05:56:38.814078 [0] AVG Duty = 5000%(X100)
7438 05:56:38.817104
7439 05:56:38.817705 ==DQ 1 ==
7440 05:56:38.820351 Final DQ duty delay cell = 0
7441 05:56:38.823949 [0] MAX Duty = 5125%(X100), DQS PI = 34
7442 05:56:38.827107 [0] MIN Duty = 4938%(X100), DQS PI = 24
7443 05:56:38.827534 [0] AVG Duty = 5031%(X100)
7444 05:56:38.830632
7445 05:56:38.833540 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7446 05:56:38.834082
7447 05:56:38.836813 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7448 05:56:38.840326 [DutyScan_Calibration_Flow] ====Done====
7449 05:56:38.843835 nWR fixed to 30
7450 05:56:38.844383 [ModeRegInit_LP4] CH0 RK0
7451 05:56:38.847474 [ModeRegInit_LP4] CH0 RK1
7452 05:56:38.850243 [ModeRegInit_LP4] CH1 RK0
7453 05:56:38.853618 [ModeRegInit_LP4] CH1 RK1
7454 05:56:38.854139 match AC timing 5
7455 05:56:38.860244 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7456 05:56:38.863812 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7457 05:56:38.866533 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7458 05:56:38.873643 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7459 05:56:38.876943 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7460 05:56:38.877360 [MiockJmeterHQA]
7461 05:56:38.877744
7462 05:56:38.879854 [DramcMiockJmeter] u1RxGatingPI = 0
7463 05:56:38.883285 0 : 4258, 4029
7464 05:56:38.883708 4 : 4255, 4029
7465 05:56:38.886950 8 : 4371, 4143
7466 05:56:38.887368 12 : 4257, 4029
7467 05:56:38.887702 16 : 4260, 4032
7468 05:56:38.889900 20 : 4257, 4029
7469 05:56:38.890321 24 : 4257, 4030
7470 05:56:38.893437 28 : 4255, 4029
7471 05:56:38.893882 32 : 4255, 4029
7472 05:56:38.897026 36 : 4258, 4032
7473 05:56:38.897442 40 : 4366, 4140
7474 05:56:38.900295 44 : 4366, 4139
7475 05:56:38.900715 48 : 4255, 4029
7476 05:56:38.901049 52 : 4253, 4029
7477 05:56:38.903804 56 : 4252, 4029
7478 05:56:38.904319 60 : 4255, 4029
7479 05:56:38.907115 64 : 4252, 4030
7480 05:56:38.907535 68 : 4368, 4143
7481 05:56:38.910142 72 : 4252, 4029
7482 05:56:38.910576 76 : 4257, 4032
7483 05:56:38.910912 80 : 4255, 4029
7484 05:56:38.913552 84 : 4250, 4027
7485 05:56:38.913974 88 : 4257, 4032
7486 05:56:38.916701 92 : 4255, 4029
7487 05:56:38.917123 96 : 4253, 4029
7488 05:56:38.919748 100 : 4255, 4029
7489 05:56:38.920172 104 : 4366, 3781
7490 05:56:38.923295 108 : 4363, 3
7491 05:56:38.923715 112 : 4255, 0
7492 05:56:38.924051 116 : 4255, 0
7493 05:56:38.926698 120 : 4252, 0
7494 05:56:38.927120 124 : 4255, 0
7495 05:56:38.929924 128 : 4258, 0
7496 05:56:38.930349 132 : 4363, 0
7497 05:56:38.930700 136 : 4363, 0
7498 05:56:38.933424 140 : 4253, 0
7499 05:56:38.933874 144 : 4363, 0
7500 05:56:38.934207 148 : 4363, 0
7501 05:56:38.936833 152 : 4368, 0
7502 05:56:38.937253 156 : 4255, 0
7503 05:56:38.940042 160 : 4252, 0
7504 05:56:38.940562 164 : 4253, 0
7505 05:56:38.940899 168 : 4257, 0
7506 05:56:38.943161 172 : 4252, 0
7507 05:56:38.943584 176 : 4252, 0
7508 05:56:38.946406 180 : 4257, 0
7509 05:56:38.946828 184 : 4252, 0
7510 05:56:38.947160 188 : 4252, 0
7511 05:56:38.950070 192 : 4253, 0
7512 05:56:38.950489 196 : 4365, 0
7513 05:56:38.952853 200 : 4253, 0
7514 05:56:38.953272 204 : 4253, 0
7515 05:56:38.953642 208 : 4255, 0
7516 05:56:38.956378 212 : 4363, 0
7517 05:56:38.956810 216 : 4252, 0
7518 05:56:38.959480 220 : 4250, 0
7519 05:56:38.960000 224 : 4360, 0
7520 05:56:38.960337 228 : 4252, 0
7521 05:56:38.962724 232 : 4255, 1
7522 05:56:38.963146 236 : 4252, 1230
7523 05:56:38.966146 240 : 4257, 4031
7524 05:56:38.966567 244 : 4366, 4140
7525 05:56:38.969470 248 : 4253, 4029
7526 05:56:38.969933 252 : 4252, 4030
7527 05:56:38.970263 256 : 4250, 4026
7528 05:56:38.972887 260 : 4258, 4032
7529 05:56:38.973309 264 : 4366, 4140
7530 05:56:38.976436 268 : 4252, 4030
7531 05:56:38.976861 272 : 4252, 4029
7532 05:56:38.979222 276 : 4368, 4143
7533 05:56:38.979648 280 : 4255, 4029
7534 05:56:38.982796 284 : 4365, 4140
7535 05:56:38.983270 288 : 4253, 4029
7536 05:56:38.985964 292 : 4255, 4029
7537 05:56:38.986386 296 : 4255, 4029
7538 05:56:38.989070 300 : 4255, 4029
7539 05:56:38.989669 304 : 4252, 4029
7540 05:56:38.992613 308 : 4255, 4029
7541 05:56:38.993035 312 : 4363, 4140
7542 05:56:38.996152 316 : 4255, 4029
7543 05:56:38.996578 320 : 4252, 4030
7544 05:56:38.999296 324 : 4252, 4029
7545 05:56:38.999824 328 : 4257, 4032
7546 05:56:39.000217 332 : 4255, 4029
7547 05:56:39.002930 336 : 4365, 4140
7548 05:56:39.003445 340 : 4252, 4029
7549 05:56:39.005534 344 : 4252, 4029
7550 05:56:39.005955 348 : 4252, 4029
7551 05:56:39.009354 352 : 4253, 4020
7552 05:56:39.009918 356 : 4252, 2863
7553 05:56:39.012755 360 : 4252, 0
7554 05:56:39.013178
7555 05:56:39.013567 MIOCK jitter meter ch=0
7556 05:56:39.013884
7557 05:56:39.016018 1T = (360-108) = 252 dly cells
7558 05:56:39.022360 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7559 05:56:39.022777 ==
7560 05:56:39.025653 Dram Type= 6, Freq= 0, CH_0, rank 0
7561 05:56:39.028517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7562 05:56:39.028937 ==
7563 05:56:39.035681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7564 05:56:39.038942 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7565 05:56:39.045573 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7566 05:56:39.048287 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7567 05:56:39.058627 [CA 0] Center 44 (14~75) winsize 62
7568 05:56:39.062131 [CA 1] Center 43 (13~74) winsize 62
7569 05:56:39.065667 [CA 2] Center 40 (11~69) winsize 59
7570 05:56:39.069079 [CA 3] Center 39 (10~68) winsize 59
7571 05:56:39.071665 [CA 4] Center 37 (8~67) winsize 60
7572 05:56:39.074920 [CA 5] Center 37 (7~67) winsize 61
7573 05:56:39.075001
7574 05:56:39.078563 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7575 05:56:39.078644
7576 05:56:39.085060 [CATrainingPosCal] consider 1 rank data
7577 05:56:39.085141 u2DelayCellTimex100 = 258/100 ps
7578 05:56:39.091592 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7579 05:56:39.095016 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7580 05:56:39.097724 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7581 05:56:39.101685 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7582 05:56:39.104948 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7583 05:56:39.108190 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7584 05:56:39.108270
7585 05:56:39.111143 CA PerBit enable=1, Macro0, CA PI delay=37
7586 05:56:39.111305
7587 05:56:39.114701 [CBTSetCACLKResult] CA Dly = 37
7588 05:56:39.117655 CS Dly: 11 (0~42)
7589 05:56:39.120997 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7590 05:56:39.124651 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7591 05:56:39.124733 ==
7592 05:56:39.128172 Dram Type= 6, Freq= 0, CH_0, rank 1
7593 05:56:39.134603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 05:56:39.134714 ==
7595 05:56:39.138274 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7596 05:56:39.144359 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7597 05:56:39.147851 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7598 05:56:39.154507 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7599 05:56:39.162533 [CA 0] Center 43 (13~74) winsize 62
7600 05:56:39.166077 [CA 1] Center 43 (13~74) winsize 62
7601 05:56:39.168980 [CA 2] Center 39 (10~68) winsize 59
7602 05:56:39.172548 [CA 3] Center 39 (10~68) winsize 59
7603 05:56:39.175623 [CA 4] Center 36 (7~66) winsize 60
7604 05:56:39.178677 [CA 5] Center 36 (6~66) winsize 61
7605 05:56:39.178782
7606 05:56:39.182048 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7607 05:56:39.182153
7608 05:56:39.188710 [CATrainingPosCal] consider 2 rank data
7609 05:56:39.188817 u2DelayCellTimex100 = 258/100 ps
7610 05:56:39.195672 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7611 05:56:39.198533 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7612 05:56:39.201856 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7613 05:56:39.205063 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7614 05:56:39.208456 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7615 05:56:39.212078 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7616 05:56:39.212159
7617 05:56:39.215439 CA PerBit enable=1, Macro0, CA PI delay=36
7618 05:56:39.215519
7619 05:56:39.218348 [CBTSetCACLKResult] CA Dly = 36
7620 05:56:39.222022 CS Dly: 11 (0~43)
7621 05:56:39.225060 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7622 05:56:39.228511 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7623 05:56:39.228593
7624 05:56:39.231645 ----->DramcWriteLeveling(PI) begin...
7625 05:56:39.235078 ==
7626 05:56:39.235160 Dram Type= 6, Freq= 0, CH_0, rank 0
7627 05:56:39.241664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 05:56:39.241748 ==
7629 05:56:39.244996 Write leveling (Byte 0): 35 => 35
7630 05:56:39.248533 Write leveling (Byte 1): 26 => 26
7631 05:56:39.251483 DramcWriteLeveling(PI) end<-----
7632 05:56:39.251566
7633 05:56:39.251630 ==
7634 05:56:39.254994 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 05:56:39.258599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 05:56:39.258682 ==
7637 05:56:39.261933 [Gating] SW mode calibration
7638 05:56:39.268350 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7639 05:56:39.271832 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7640 05:56:39.278530 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 05:56:39.281347 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 05:56:39.284725 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 05:56:39.291319 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 05:56:39.294833 1 4 16 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7645 05:56:39.298475 1 4 20 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7646 05:56:39.304630 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7647 05:56:39.307907 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7648 05:56:39.311155 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7649 05:56:39.318254 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7650 05:56:39.321726 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7651 05:56:39.324766 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7652 05:56:39.331111 1 5 16 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
7653 05:56:39.334608 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7654 05:56:39.338150 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7655 05:56:39.344828 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7656 05:56:39.348119 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 05:56:39.351178 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 05:56:39.357892 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 05:56:39.361402 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7660 05:56:39.364382 1 6 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7661 05:56:39.371291 1 6 20 | B1->B0 | 2b2b 4646 | 0 0 | (1 1) (0 0)
7662 05:56:39.374520 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7663 05:56:39.377457 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 05:56:39.384764 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7665 05:56:39.387631 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 05:56:39.390975 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7667 05:56:39.397576 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7668 05:56:39.400648 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7669 05:56:39.404315 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7670 05:56:39.410921 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7671 05:56:39.413902 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 05:56:39.417404 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 05:56:39.424287 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 05:56:39.427692 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 05:56:39.430579 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 05:56:39.437338 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 05:56:39.440557 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 05:56:39.444116 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 05:56:39.450967 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 05:56:39.453667 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 05:56:39.456951 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 05:56:39.463510 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 05:56:39.467071 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 05:56:39.470633 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7685 05:56:39.474049 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7686 05:56:39.476917 Total UI for P1: 0, mck2ui 16
7687 05:56:39.480310 best dqsien dly found for B0: ( 1, 9, 16)
7688 05:56:39.486805 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7689 05:56:39.490036 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7690 05:56:39.493725 Total UI for P1: 0, mck2ui 16
7691 05:56:39.496683 best dqsien dly found for B1: ( 1, 9, 22)
7692 05:56:39.500134 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7693 05:56:39.503682 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7694 05:56:39.503758
7695 05:56:39.506644 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7696 05:56:39.513947 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7697 05:56:39.514322 [Gating] SW calibration Done
7698 05:56:39.514651 ==
7699 05:56:39.517271 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 05:56:39.523780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 05:56:39.524226 ==
7702 05:56:39.524558 RX Vref Scan: 0
7703 05:56:39.524863
7704 05:56:39.527075 RX Vref 0 -> 0, step: 1
7705 05:56:39.527490
7706 05:56:39.530062 RX Delay 0 -> 252, step: 8
7707 05:56:39.533694 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7708 05:56:39.536575 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7709 05:56:39.540314 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7710 05:56:39.546883 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7711 05:56:39.550339 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7712 05:56:39.553162 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7713 05:56:39.556507 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7714 05:56:39.559975 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7715 05:56:39.567050 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7716 05:56:39.570013 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7717 05:56:39.573383 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7718 05:56:39.576215 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7719 05:56:39.579798 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7720 05:56:39.586548 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7721 05:56:39.589423 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7722 05:56:39.593511 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7723 05:56:39.593999 ==
7724 05:56:39.596060 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 05:56:39.599608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 05:56:39.602759 ==
7727 05:56:39.603161 DQS Delay:
7728 05:56:39.603481 DQS0 = 0, DQS1 = 0
7729 05:56:39.606249 DQM Delay:
7730 05:56:39.606663 DQM0 = 128, DQM1 = 123
7731 05:56:39.609392 DQ Delay:
7732 05:56:39.613115 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7733 05:56:39.616483 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =143
7734 05:56:39.619341 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7735 05:56:39.622688 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7736 05:56:39.623104
7737 05:56:39.623428
7738 05:56:39.623730 ==
7739 05:56:39.626258 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 05:56:39.629242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 05:56:39.629711 ==
7742 05:56:39.632533
7743 05:56:39.632943
7744 05:56:39.633286 TX Vref Scan disable
7745 05:56:39.635880 == TX Byte 0 ==
7746 05:56:39.639096 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7747 05:56:39.642630 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7748 05:56:39.645692 == TX Byte 1 ==
7749 05:56:39.648950 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7750 05:56:39.652604 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7751 05:56:39.655608 ==
7752 05:56:39.656023 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 05:56:39.662184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 05:56:39.662608 ==
7755 05:56:39.675396
7756 05:56:39.678810 TX Vref early break, caculate TX vref
7757 05:56:39.681908 TX Vref=16, minBit 11, minWin=21, winSum=359
7758 05:56:39.685571 TX Vref=18, minBit 8, minWin=21, winSum=365
7759 05:56:39.688325 TX Vref=20, minBit 8, minWin=21, winSum=378
7760 05:56:39.691648 TX Vref=22, minBit 4, minWin=23, winSum=388
7761 05:56:39.698472 TX Vref=24, minBit 8, minWin=23, winSum=394
7762 05:56:39.701802 TX Vref=26, minBit 4, minWin=24, winSum=400
7763 05:56:39.705276 TX Vref=28, minBit 2, minWin=24, winSum=403
7764 05:56:39.707998 TX Vref=30, minBit 8, minWin=23, winSum=397
7765 05:56:39.711238 TX Vref=32, minBit 8, minWin=23, winSum=386
7766 05:56:39.714662 TX Vref=34, minBit 8, minWin=21, winSum=376
7767 05:56:39.721510 [TxChooseVref] Worse bit 2, Min win 24, Win sum 403, Final Vref 28
7768 05:56:39.722021
7769 05:56:39.725042 Final TX Range 0 Vref 28
7770 05:56:39.725578
7771 05:56:39.725945 ==
7772 05:56:39.727986 Dram Type= 6, Freq= 0, CH_0, rank 0
7773 05:56:39.731365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7774 05:56:39.731785 ==
7775 05:56:39.732114
7776 05:56:39.732416
7777 05:56:39.734775 TX Vref Scan disable
7778 05:56:39.741425 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7779 05:56:39.741972 == TX Byte 0 ==
7780 05:56:39.744664 u2DelayCellOfst[0]=18 cells (5 PI)
7781 05:56:39.748056 u2DelayCellOfst[1]=22 cells (6 PI)
7782 05:56:39.750959 u2DelayCellOfst[2]=15 cells (4 PI)
7783 05:56:39.754334 u2DelayCellOfst[3]=15 cells (4 PI)
7784 05:56:39.757645 u2DelayCellOfst[4]=11 cells (3 PI)
7785 05:56:39.761250 u2DelayCellOfst[5]=0 cells (0 PI)
7786 05:56:39.764202 u2DelayCellOfst[6]=22 cells (6 PI)
7787 05:56:39.767723 u2DelayCellOfst[7]=18 cells (5 PI)
7788 05:56:39.770814 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7789 05:56:39.774392 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7790 05:56:39.777902 == TX Byte 1 ==
7791 05:56:39.780999 u2DelayCellOfst[8]=0 cells (0 PI)
7792 05:56:39.783898 u2DelayCellOfst[9]=0 cells (0 PI)
7793 05:56:39.787540 u2DelayCellOfst[10]=7 cells (2 PI)
7794 05:56:39.788009 u2DelayCellOfst[11]=3 cells (1 PI)
7795 05:56:39.790533 u2DelayCellOfst[12]=15 cells (4 PI)
7796 05:56:39.794109 u2DelayCellOfst[13]=11 cells (3 PI)
7797 05:56:39.797355 u2DelayCellOfst[14]=15 cells (4 PI)
7798 05:56:39.800495 u2DelayCellOfst[15]=11 cells (3 PI)
7799 05:56:39.807389 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7800 05:56:39.810567 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7801 05:56:39.811114 DramC Write-DBI on
7802 05:56:39.813584 ==
7803 05:56:39.816890 Dram Type= 6, Freq= 0, CH_0, rank 0
7804 05:56:39.820451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7805 05:56:39.821079 ==
7806 05:56:39.821547
7807 05:56:39.821898
7808 05:56:39.823876 TX Vref Scan disable
7809 05:56:39.824462 == TX Byte 0 ==
7810 05:56:39.830115 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7811 05:56:39.830532 == TX Byte 1 ==
7812 05:56:39.833858 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7813 05:56:39.837067 DramC Write-DBI off
7814 05:56:39.837527
7815 05:56:39.837880 [DATLAT]
7816 05:56:39.840432 Freq=1600, CH0 RK0
7817 05:56:39.840848
7818 05:56:39.841172 DATLAT Default: 0xf
7819 05:56:39.843406 0, 0xFFFF, sum = 0
7820 05:56:39.843828 1, 0xFFFF, sum = 0
7821 05:56:39.846766 2, 0xFFFF, sum = 0
7822 05:56:39.847190 3, 0xFFFF, sum = 0
7823 05:56:39.850498 4, 0xFFFF, sum = 0
7824 05:56:39.850918 5, 0xFFFF, sum = 0
7825 05:56:39.853584 6, 0xFFFF, sum = 0
7826 05:56:39.856546 7, 0xFFFF, sum = 0
7827 05:56:39.856844 8, 0xFFFF, sum = 0
7828 05:56:39.860120 9, 0xFFFF, sum = 0
7829 05:56:39.860420 10, 0xFFFF, sum = 0
7830 05:56:39.863102 11, 0xFFFF, sum = 0
7831 05:56:39.863402 12, 0xFFFF, sum = 0
7832 05:56:39.866537 13, 0xEFFF, sum = 0
7833 05:56:39.866837 14, 0x0, sum = 1
7834 05:56:39.869723 15, 0x0, sum = 2
7835 05:56:39.870022 16, 0x0, sum = 3
7836 05:56:39.873034 17, 0x0, sum = 4
7837 05:56:39.873332 best_step = 15
7838 05:56:39.873605
7839 05:56:39.873832 ==
7840 05:56:39.876836 Dram Type= 6, Freq= 0, CH_0, rank 0
7841 05:56:39.880285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7842 05:56:39.880586 ==
7843 05:56:39.883332 RX Vref Scan: 1
7844 05:56:39.883625
7845 05:56:39.886300 Set Vref Range= 24 -> 127
7846 05:56:39.886594
7847 05:56:39.886824 RX Vref 24 -> 127, step: 1
7848 05:56:39.889876
7849 05:56:39.890169 RX Delay 11 -> 252, step: 4
7850 05:56:39.890401
7851 05:56:39.893443 Set Vref, RX VrefLevel [Byte0]: 24
7852 05:56:39.896452 [Byte1]: 24
7853 05:56:39.899922
7854 05:56:39.900215 Set Vref, RX VrefLevel [Byte0]: 25
7855 05:56:39.903452 [Byte1]: 25
7856 05:56:39.907504
7857 05:56:39.910965 Set Vref, RX VrefLevel [Byte0]: 26
7858 05:56:39.913896 [Byte1]: 26
7859 05:56:39.914259
7860 05:56:39.917538 Set Vref, RX VrefLevel [Byte0]: 27
7861 05:56:39.920875 [Byte1]: 27
7862 05:56:39.921173
7863 05:56:39.924367 Set Vref, RX VrefLevel [Byte0]: 28
7864 05:56:39.927276 [Byte1]: 28
7865 05:56:39.930605
7866 05:56:39.930948 Set Vref, RX VrefLevel [Byte0]: 29
7867 05:56:39.933541 [Byte1]: 29
7868 05:56:39.938121
7869 05:56:39.938502 Set Vref, RX VrefLevel [Byte0]: 30
7870 05:56:39.941226 [Byte1]: 30
7871 05:56:39.945419
7872 05:56:39.945743 Set Vref, RX VrefLevel [Byte0]: 31
7873 05:56:39.948966 [Byte1]: 31
7874 05:56:39.953143
7875 05:56:39.953550 Set Vref, RX VrefLevel [Byte0]: 32
7876 05:56:39.956489 [Byte1]: 32
7877 05:56:39.961165
7878 05:56:39.961459 Set Vref, RX VrefLevel [Byte0]: 33
7879 05:56:39.964138 [Byte1]: 33
7880 05:56:39.968276
7881 05:56:39.968605 Set Vref, RX VrefLevel [Byte0]: 34
7882 05:56:39.971751 [Byte1]: 34
7883 05:56:39.976452
7884 05:56:39.976746 Set Vref, RX VrefLevel [Byte0]: 35
7885 05:56:39.979450 [Byte1]: 35
7886 05:56:39.983522
7887 05:56:39.983812 Set Vref, RX VrefLevel [Byte0]: 36
7888 05:56:39.987157 [Byte1]: 36
7889 05:56:39.991612
7890 05:56:39.991909 Set Vref, RX VrefLevel [Byte0]: 37
7891 05:56:39.995015 [Byte1]: 37
7892 05:56:39.999218
7893 05:56:39.999510 Set Vref, RX VrefLevel [Byte0]: 38
7894 05:56:40.002346 [Byte1]: 38
7895 05:56:40.006544
7896 05:56:40.006837 Set Vref, RX VrefLevel [Byte0]: 39
7897 05:56:40.010068 [Byte1]: 39
7898 05:56:40.014143
7899 05:56:40.014438 Set Vref, RX VrefLevel [Byte0]: 40
7900 05:56:40.017818 [Byte1]: 40
7901 05:56:40.022065
7902 05:56:40.022360 Set Vref, RX VrefLevel [Byte0]: 41
7903 05:56:40.024936 [Byte1]: 41
7904 05:56:40.029471
7905 05:56:40.029889 Set Vref, RX VrefLevel [Byte0]: 42
7906 05:56:40.032898 [Byte1]: 42
7907 05:56:40.037132
7908 05:56:40.037425 Set Vref, RX VrefLevel [Byte0]: 43
7909 05:56:40.040137 [Byte1]: 43
7910 05:56:40.044971
7911 05:56:40.045266 Set Vref, RX VrefLevel [Byte0]: 44
7912 05:56:40.047947 [Byte1]: 44
7913 05:56:40.052137
7914 05:56:40.052545 Set Vref, RX VrefLevel [Byte0]: 45
7915 05:56:40.055801 [Byte1]: 45
7916 05:56:40.059953
7917 05:56:40.060368 Set Vref, RX VrefLevel [Byte0]: 46
7918 05:56:40.063383 [Byte1]: 46
7919 05:56:40.067323
7920 05:56:40.067617 Set Vref, RX VrefLevel [Byte0]: 47
7921 05:56:40.071067 [Byte1]: 47
7922 05:56:40.074879
7923 05:56:40.075232 Set Vref, RX VrefLevel [Byte0]: 48
7924 05:56:40.078259 [Byte1]: 48
7925 05:56:40.083016
7926 05:56:40.083310 Set Vref, RX VrefLevel [Byte0]: 49
7927 05:56:40.085956 [Byte1]: 49
7928 05:56:40.089999
7929 05:56:40.090081 Set Vref, RX VrefLevel [Byte0]: 50
7930 05:56:40.093140 [Byte1]: 50
7931 05:56:40.097868
7932 05:56:40.097952 Set Vref, RX VrefLevel [Byte0]: 51
7933 05:56:40.101096 [Byte1]: 51
7934 05:56:40.105579
7935 05:56:40.105660 Set Vref, RX VrefLevel [Byte0]: 52
7936 05:56:40.108534 [Byte1]: 52
7937 05:56:40.113043
7938 05:56:40.113123 Set Vref, RX VrefLevel [Byte0]: 53
7939 05:56:40.116216 [Byte1]: 53
7940 05:56:40.120430
7941 05:56:40.120550 Set Vref, RX VrefLevel [Byte0]: 54
7942 05:56:40.124421 [Byte1]: 54
7943 05:56:40.128590
7944 05:56:40.128764 Set Vref, RX VrefLevel [Byte0]: 55
7945 05:56:40.131979 [Byte1]: 55
7946 05:56:40.135906
7947 05:56:40.136084 Set Vref, RX VrefLevel [Byte0]: 56
7948 05:56:40.139289 [Byte1]: 56
7949 05:56:40.144223
7950 05:56:40.144423 Set Vref, RX VrefLevel [Byte0]: 57
7951 05:56:40.147167 [Byte1]: 57
7952 05:56:40.151704
7953 05:56:40.151910 Set Vref, RX VrefLevel [Byte0]: 58
7954 05:56:40.154601 [Byte1]: 58
7955 05:56:40.158818
7956 05:56:40.158992 Set Vref, RX VrefLevel [Byte0]: 59
7957 05:56:40.161856 [Byte1]: 59
7958 05:56:40.166192
7959 05:56:40.166391 Set Vref, RX VrefLevel [Byte0]: 60
7960 05:56:40.169965 [Byte1]: 60
7961 05:56:40.174329
7962 05:56:40.174625 Set Vref, RX VrefLevel [Byte0]: 61
7963 05:56:40.177591 [Byte1]: 61
7964 05:56:40.181472
7965 05:56:40.181890 Set Vref, RX VrefLevel [Byte0]: 62
7966 05:56:40.184847 [Byte1]: 62
7967 05:56:40.189189
7968 05:56:40.189607 Set Vref, RX VrefLevel [Byte0]: 63
7969 05:56:40.192760 [Byte1]: 63
7970 05:56:40.197254
7971 05:56:40.197661 Set Vref, RX VrefLevel [Byte0]: 64
7972 05:56:40.200398 [Byte1]: 64
7973 05:56:40.204746
7974 05:56:40.208361 Set Vref, RX VrefLevel [Byte0]: 65
7975 05:56:40.211498 [Byte1]: 65
7976 05:56:40.211883
7977 05:56:40.214182 Set Vref, RX VrefLevel [Byte0]: 66
7978 05:56:40.217546 [Byte1]: 66
7979 05:56:40.217930
7980 05:56:40.221213 Set Vref, RX VrefLevel [Byte0]: 67
7981 05:56:40.224279 [Byte1]: 67
7982 05:56:40.227671
7983 05:56:40.228052 Set Vref, RX VrefLevel [Byte0]: 68
7984 05:56:40.230760 [Byte1]: 68
7985 05:56:40.234660
7986 05:56:40.234740 Set Vref, RX VrefLevel [Byte0]: 69
7987 05:56:40.238030 [Byte1]: 69
7988 05:56:40.242512
7989 05:56:40.242594 Set Vref, RX VrefLevel [Byte0]: 70
7990 05:56:40.245387 [Byte1]: 70
7991 05:56:40.250171
7992 05:56:40.250250 Set Vref, RX VrefLevel [Byte0]: 71
7993 05:56:40.253449 [Byte1]: 71
7994 05:56:40.257374
7995 05:56:40.257459 Set Vref, RX VrefLevel [Byte0]: 72
7996 05:56:40.260695 [Byte1]: 72
7997 05:56:40.265489
7998 05:56:40.265593 Set Vref, RX VrefLevel [Byte0]: 73
7999 05:56:40.268406 [Byte1]: 73
8000 05:56:40.273206
8001 05:56:40.273325 Set Vref, RX VrefLevel [Byte0]: 74
8002 05:56:40.276008 [Byte1]: 74
8003 05:56:40.280587
8004 05:56:40.280794 Set Vref, RX VrefLevel [Byte0]: 75
8005 05:56:40.283723 [Byte1]: 75
8006 05:56:40.288420
8007 05:56:40.288598 Final RX Vref Byte 0 = 60 to rank0
8008 05:56:40.291735 Final RX Vref Byte 1 = 60 to rank0
8009 05:56:40.294614 Final RX Vref Byte 0 = 60 to rank1
8010 05:56:40.297759 Final RX Vref Byte 1 = 60 to rank1==
8011 05:56:40.301253 Dram Type= 6, Freq= 0, CH_0, rank 0
8012 05:56:40.307949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8013 05:56:40.308446 ==
8014 05:56:40.308782 DQS Delay:
8015 05:56:40.311405 DQS0 = 0, DQS1 = 0
8016 05:56:40.311915 DQM Delay:
8017 05:56:40.312252 DQM0 = 126, DQM1 = 119
8018 05:56:40.314610 DQ Delay:
8019 05:56:40.317967 DQ0 =126, DQ1 =128, DQ2 =124, DQ3 =122
8020 05:56:40.321573 DQ4 =126, DQ5 =114, DQ6 =132, DQ7 =138
8021 05:56:40.324613 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8022 05:56:40.328314 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8023 05:56:40.328728
8024 05:56:40.329053
8025 05:56:40.329358
8026 05:56:40.331311 [DramC_TX_OE_Calibration] TA2
8027 05:56:40.335083 Original DQ_B0 (3 6) =30, OEN = 27
8028 05:56:40.338240 Original DQ_B1 (3 6) =30, OEN = 27
8029 05:56:40.341398 24, 0x0, End_B0=24 End_B1=24
8030 05:56:40.341865 25, 0x0, End_B0=25 End_B1=25
8031 05:56:40.344676 26, 0x0, End_B0=26 End_B1=26
8032 05:56:40.347760 27, 0x0, End_B0=27 End_B1=27
8033 05:56:40.351557 28, 0x0, End_B0=28 End_B1=28
8034 05:56:40.354323 29, 0x0, End_B0=29 End_B1=29
8035 05:56:40.354752 30, 0x0, End_B0=30 End_B1=30
8036 05:56:40.357793 31, 0x4141, End_B0=30 End_B1=30
8037 05:56:40.361246 Byte0 end_step=30 best_step=27
8038 05:56:40.364536 Byte1 end_step=30 best_step=27
8039 05:56:40.367828 Byte0 TX OE(2T, 0.5T) = (3, 3)
8040 05:56:40.371249 Byte1 TX OE(2T, 0.5T) = (3, 3)
8041 05:56:40.371667
8042 05:56:40.371995
8043 05:56:40.377750 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
8044 05:56:40.381458 CH0 RK0: MR19=303, MR18=1111
8045 05:56:40.388156 CH0_RK0: MR19=0x303, MR18=0x1111, DQSOSC=401, MR23=63, INC=22, DEC=15
8046 05:56:40.388679
8047 05:56:40.391176 ----->DramcWriteLeveling(PI) begin...
8048 05:56:40.391595 ==
8049 05:56:40.394443 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 05:56:40.397303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 05:56:40.397768 ==
8052 05:56:40.401012 Write leveling (Byte 0): 34 => 34
8053 05:56:40.404288 Write leveling (Byte 1): 29 => 29
8054 05:56:40.408292 DramcWriteLeveling(PI) end<-----
8055 05:56:40.408808
8056 05:56:40.409140 ==
8057 05:56:40.411027 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 05:56:40.414363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 05:56:40.414890 ==
8060 05:56:40.417978 [Gating] SW mode calibration
8061 05:56:40.424063 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8062 05:56:40.430531 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8063 05:56:40.434090 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 05:56:40.440946 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 05:56:40.444277 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 05:56:40.447657 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8067 05:56:40.453860 1 4 16 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
8068 05:56:40.456966 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 05:56:40.460668 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 05:56:40.467562 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 05:56:40.470623 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 05:56:40.473581 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 05:56:40.480312 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 05:56:40.483657 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
8075 05:56:40.487060 1 5 16 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8076 05:56:40.493749 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8077 05:56:40.496789 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 05:56:40.500404 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 05:56:40.507325 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 05:56:40.510413 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 05:56:40.513384 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8082 05:56:40.520141 1 6 12 | B1->B0 | 2323 4040 | 0 1 | (0 0) (0 0)
8083 05:56:40.523677 1 6 16 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8084 05:56:40.526882 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 05:56:40.533233 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 05:56:40.536633 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 05:56:40.539971 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 05:56:40.542996 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 05:56:40.549916 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8090 05:56:40.553061 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8091 05:56:40.556464 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8092 05:56:40.563026 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8093 05:56:40.566768 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8094 05:56:40.569923 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 05:56:40.576281 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 05:56:40.579635 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 05:56:40.583150 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 05:56:40.589340 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 05:56:40.592998 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 05:56:40.596124 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 05:56:40.602943 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 05:56:40.606137 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 05:56:40.609408 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 05:56:40.616130 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 05:56:40.619259 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8106 05:56:40.622427 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8107 05:56:40.629428 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8108 05:56:40.632542 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8109 05:56:40.635859 Total UI for P1: 0, mck2ui 16
8110 05:56:40.639018 best dqsien dly found for B0: ( 1, 9, 12)
8111 05:56:40.642440 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8112 05:56:40.645913 Total UI for P1: 0, mck2ui 16
8113 05:56:40.648884 best dqsien dly found for B1: ( 1, 9, 20)
8114 05:56:40.652353 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8115 05:56:40.655904 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8116 05:56:40.656418
8117 05:56:40.662686 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8118 05:56:40.666182 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8119 05:56:40.669405 [Gating] SW calibration Done
8120 05:56:40.669882 ==
8121 05:56:40.672867 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 05:56:40.675760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 05:56:40.676494 ==
8124 05:56:40.677032 RX Vref Scan: 0
8125 05:56:40.677561
8126 05:56:40.679333 RX Vref 0 -> 0, step: 1
8127 05:56:40.679753
8128 05:56:40.682758 RX Delay 0 -> 252, step: 8
8129 05:56:40.685580 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8130 05:56:40.689035 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8131 05:56:40.695864 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8132 05:56:40.699232 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8133 05:56:40.701912 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8134 05:56:40.706080 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8135 05:56:40.709235 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8136 05:56:40.715654 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8137 05:56:40.718810 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8138 05:56:40.721917 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8139 05:56:40.725140 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8140 05:56:40.728429 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8141 05:56:40.734947 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8142 05:56:40.738550 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8143 05:56:40.741560 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8144 05:56:40.745391 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8145 05:56:40.745959 ==
8146 05:56:40.748209 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 05:56:40.755042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 05:56:40.755465 ==
8149 05:56:40.755796 DQS Delay:
8150 05:56:40.757861 DQS0 = 0, DQS1 = 0
8151 05:56:40.758404 DQM Delay:
8152 05:56:40.761381 DQM0 = 128, DQM1 = 122
8153 05:56:40.761850 DQ Delay:
8154 05:56:40.765095 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8155 05:56:40.768495 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8156 05:56:40.771399 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8157 05:56:40.774751 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8158 05:56:40.775176
8159 05:56:40.775505
8160 05:56:40.775808 ==
8161 05:56:40.778002 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 05:56:40.784855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 05:56:40.785276 ==
8164 05:56:40.785651
8165 05:56:40.785964
8166 05:56:40.786257 TX Vref Scan disable
8167 05:56:40.788278 == TX Byte 0 ==
8168 05:56:40.791201 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8169 05:56:40.794752 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8170 05:56:40.798232 == TX Byte 1 ==
8171 05:56:40.801694 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8172 05:56:40.808387 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8173 05:56:40.808912 ==
8174 05:56:40.811410 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 05:56:40.814714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 05:56:40.815138 ==
8177 05:56:40.828695
8178 05:56:40.832094 TX Vref early break, caculate TX vref
8179 05:56:40.834963 TX Vref=16, minBit 0, minWin=22, winSum=370
8180 05:56:40.838681 TX Vref=18, minBit 8, minWin=22, winSum=372
8181 05:56:40.842153 TX Vref=20, minBit 0, minWin=23, winSum=387
8182 05:56:40.844963 TX Vref=22, minBit 4, minWin=23, winSum=392
8183 05:56:40.848316 TX Vref=24, minBit 8, minWin=24, winSum=403
8184 05:56:40.854907 TX Vref=26, minBit 0, minWin=25, winSum=404
8185 05:56:40.858326 TX Vref=28, minBit 4, minWin=25, winSum=413
8186 05:56:40.862250 TX Vref=30, minBit 8, minWin=24, winSum=411
8187 05:56:40.864871 TX Vref=32, minBit 8, minWin=23, winSum=398
8188 05:56:40.868587 TX Vref=34, minBit 8, minWin=23, winSum=392
8189 05:56:40.871615 TX Vref=36, minBit 8, minWin=23, winSum=384
8190 05:56:40.878247 [TxChooseVref] Worse bit 4, Min win 25, Win sum 413, Final Vref 28
8191 05:56:40.878750
8192 05:56:40.881348 Final TX Range 0 Vref 28
8193 05:56:40.881801
8194 05:56:40.882132 ==
8195 05:56:40.884749 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 05:56:40.888327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 05:56:40.888851 ==
8198 05:56:40.890998
8199 05:56:40.891413
8200 05:56:40.891737 TX Vref Scan disable
8201 05:56:40.898073 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8202 05:56:40.898491 == TX Byte 0 ==
8203 05:56:40.900989 u2DelayCellOfst[0]=11 cells (3 PI)
8204 05:56:40.904561 u2DelayCellOfst[1]=18 cells (5 PI)
8205 05:56:40.907688 u2DelayCellOfst[2]=11 cells (3 PI)
8206 05:56:40.911183 u2DelayCellOfst[3]=11 cells (3 PI)
8207 05:56:40.914433 u2DelayCellOfst[4]=7 cells (2 PI)
8208 05:56:40.917929 u2DelayCellOfst[5]=0 cells (0 PI)
8209 05:56:40.921167 u2DelayCellOfst[6]=18 cells (5 PI)
8210 05:56:40.924225 u2DelayCellOfst[7]=18 cells (5 PI)
8211 05:56:40.928061 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8212 05:56:40.931371 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8213 05:56:40.934471 == TX Byte 1 ==
8214 05:56:40.937995 u2DelayCellOfst[8]=0 cells (0 PI)
8215 05:56:40.940960 u2DelayCellOfst[9]=0 cells (0 PI)
8216 05:56:40.944410 u2DelayCellOfst[10]=7 cells (2 PI)
8217 05:56:40.947179 u2DelayCellOfst[11]=3 cells (1 PI)
8218 05:56:40.947593 u2DelayCellOfst[12]=11 cells (3 PI)
8219 05:56:40.951065 u2DelayCellOfst[13]=11 cells (3 PI)
8220 05:56:40.954450 u2DelayCellOfst[14]=15 cells (4 PI)
8221 05:56:40.957527 u2DelayCellOfst[15]=7 cells (2 PI)
8222 05:56:40.963797 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8223 05:56:40.967799 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8224 05:56:40.968314 DramC Write-DBI on
8225 05:56:40.971038 ==
8226 05:56:40.973645 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 05:56:40.977062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 05:56:40.977522 ==
8229 05:56:40.977866
8230 05:56:40.978174
8231 05:56:40.981109 TX Vref Scan disable
8232 05:56:40.981750 == TX Byte 0 ==
8233 05:56:40.986950 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8234 05:56:40.987431 == TX Byte 1 ==
8235 05:56:40.990290 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8236 05:56:40.994042 DramC Write-DBI off
8237 05:56:40.994549
8238 05:56:40.994884 [DATLAT]
8239 05:56:40.997207 Freq=1600, CH0 RK1
8240 05:56:40.997767
8241 05:56:40.998103 DATLAT Default: 0xf
8242 05:56:41.000852 0, 0xFFFF, sum = 0
8243 05:56:41.001370 1, 0xFFFF, sum = 0
8244 05:56:41.003500 2, 0xFFFF, sum = 0
8245 05:56:41.003924 3, 0xFFFF, sum = 0
8246 05:56:41.007059 4, 0xFFFF, sum = 0
8247 05:56:41.007479 5, 0xFFFF, sum = 0
8248 05:56:41.010877 6, 0xFFFF, sum = 0
8249 05:56:41.013672 7, 0xFFFF, sum = 0
8250 05:56:41.014204 8, 0xFFFF, sum = 0
8251 05:56:41.017246 9, 0xFFFF, sum = 0
8252 05:56:41.017822 10, 0xFFFF, sum = 0
8253 05:56:41.020382 11, 0xFFFF, sum = 0
8254 05:56:41.020801 12, 0xFFFF, sum = 0
8255 05:56:41.023427 13, 0xCFFF, sum = 0
8256 05:56:41.023846 14, 0x0, sum = 1
8257 05:56:41.026902 15, 0x0, sum = 2
8258 05:56:41.027323 16, 0x0, sum = 3
8259 05:56:41.029778 17, 0x0, sum = 4
8260 05:56:41.030200 best_step = 15
8261 05:56:41.030528
8262 05:56:41.030832 ==
8263 05:56:41.033975 Dram Type= 6, Freq= 0, CH_0, rank 1
8264 05:56:41.036732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 05:56:41.040084 ==
8266 05:56:41.040497 RX Vref Scan: 0
8267 05:56:41.040822
8268 05:56:41.043074 RX Vref 0 -> 0, step: 1
8269 05:56:41.043488
8270 05:56:41.043813 RX Delay 3 -> 252, step: 4
8271 05:56:41.050399 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8272 05:56:41.054083 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8273 05:56:41.057125 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8274 05:56:41.060672 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8275 05:56:41.064189 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8276 05:56:41.070364 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8277 05:56:41.073975 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8278 05:56:41.076773 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8279 05:56:41.080186 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8280 05:56:41.084071 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8281 05:56:41.090428 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8282 05:56:41.093809 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8283 05:56:41.096994 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8284 05:56:41.100130 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8285 05:56:41.106690 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8286 05:56:41.109998 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8287 05:56:41.110416 ==
8288 05:56:41.113339 Dram Type= 6, Freq= 0, CH_0, rank 1
8289 05:56:41.116807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 05:56:41.117224 ==
8291 05:56:41.120439 DQS Delay:
8292 05:56:41.120960 DQS0 = 0, DQS1 = 0
8293 05:56:41.121290 DQM Delay:
8294 05:56:41.123295 DQM0 = 124, DQM1 = 117
8295 05:56:41.123709 DQ Delay:
8296 05:56:41.127166 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =122
8297 05:56:41.130026 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8298 05:56:41.133774 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8299 05:56:41.140228 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8300 05:56:41.140745
8301 05:56:41.141077
8302 05:56:41.141381
8303 05:56:41.143752 [DramC_TX_OE_Calibration] TA2
8304 05:56:41.146532 Original DQ_B0 (3 6) =30, OEN = 27
8305 05:56:41.147053 Original DQ_B1 (3 6) =30, OEN = 27
8306 05:56:41.149872 24, 0x0, End_B0=24 End_B1=24
8307 05:56:41.153759 25, 0x0, End_B0=25 End_B1=25
8308 05:56:41.156533 26, 0x0, End_B0=26 End_B1=26
8309 05:56:41.160008 27, 0x0, End_B0=27 End_B1=27
8310 05:56:41.160533 28, 0x0, End_B0=28 End_B1=28
8311 05:56:41.163321 29, 0x0, End_B0=29 End_B1=29
8312 05:56:41.166374 30, 0x0, End_B0=30 End_B1=30
8313 05:56:41.169345 31, 0x4141, End_B0=30 End_B1=30
8314 05:56:41.173555 Byte0 end_step=30 best_step=27
8315 05:56:41.176112 Byte1 end_step=30 best_step=27
8316 05:56:41.176540 Byte0 TX OE(2T, 0.5T) = (3, 3)
8317 05:56:41.179545 Byte1 TX OE(2T, 0.5T) = (3, 3)
8318 05:56:41.179959
8319 05:56:41.180284
8320 05:56:41.189539 [DQSOSCAuto] RK1, (LSB)MR18= 0x2512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8321 05:56:41.189965 CH0 RK1: MR19=303, MR18=2512
8322 05:56:41.196065 CH0_RK1: MR19=0x303, MR18=0x2512, DQSOSC=391, MR23=63, INC=24, DEC=16
8323 05:56:41.199663 [RxdqsGatingPostProcess] freq 1600
8324 05:56:41.206183 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8325 05:56:41.209344 best DQS0 dly(2T, 0.5T) = (1, 1)
8326 05:56:41.213084 best DQS1 dly(2T, 0.5T) = (1, 1)
8327 05:56:41.216297 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8328 05:56:41.219423 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8329 05:56:41.222787 best DQS0 dly(2T, 0.5T) = (1, 1)
8330 05:56:41.223305 best DQS1 dly(2T, 0.5T) = (1, 1)
8331 05:56:41.226048 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8332 05:56:41.228988 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8333 05:56:41.232508 Pre-setting of DQS Precalculation
8334 05:56:41.239522 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8335 05:56:41.240044 ==
8336 05:56:41.242837 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 05:56:41.245802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 05:56:41.246221 ==
8339 05:56:41.252925 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8340 05:56:41.255875 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8341 05:56:41.259230 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8342 05:56:41.265854 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8343 05:56:41.275097 [CA 0] Center 41 (12~71) winsize 60
8344 05:56:41.278352 [CA 1] Center 42 (12~72) winsize 61
8345 05:56:41.281806 [CA 2] Center 37 (9~66) winsize 58
8346 05:56:41.285038 [CA 3] Center 36 (7~66) winsize 60
8347 05:56:41.288146 [CA 4] Center 37 (8~66) winsize 59
8348 05:56:41.290947 [CA 5] Center 36 (7~66) winsize 60
8349 05:56:41.291389
8350 05:56:41.294357 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8351 05:56:41.294870
8352 05:56:41.297780 [CATrainingPosCal] consider 1 rank data
8353 05:56:41.301581 u2DelayCellTimex100 = 258/100 ps
8354 05:56:41.307952 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8355 05:56:41.311582 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8356 05:56:41.314798 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8357 05:56:41.317691 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8358 05:56:41.321416 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8359 05:56:41.324740 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8360 05:56:41.325171
8361 05:56:41.327914 CA PerBit enable=1, Macro0, CA PI delay=36
8362 05:56:41.328325
8363 05:56:41.331180 [CBTSetCACLKResult] CA Dly = 36
8364 05:56:41.334270 CS Dly: 9 (0~40)
8365 05:56:41.338046 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8366 05:56:41.341020 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8367 05:56:41.341312 ==
8368 05:56:41.344508 Dram Type= 6, Freq= 0, CH_1, rank 1
8369 05:56:41.347717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 05:56:41.350680 ==
8371 05:56:41.354036 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8372 05:56:41.357630 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8373 05:56:41.364294 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8374 05:56:41.370514 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8375 05:56:41.378217 [CA 0] Center 42 (13~71) winsize 59
8376 05:56:41.381556 [CA 1] Center 42 (13~72) winsize 60
8377 05:56:41.385002 [CA 2] Center 38 (9~68) winsize 60
8378 05:56:41.388315 [CA 3] Center 36 (7~66) winsize 60
8379 05:56:41.391047 [CA 4] Center 38 (9~68) winsize 60
8380 05:56:41.394837 [CA 5] Center 36 (6~67) winsize 62
8381 05:56:41.395354
8382 05:56:41.397593 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8383 05:56:41.398007
8384 05:56:41.401430 [CATrainingPosCal] consider 2 rank data
8385 05:56:41.404414 u2DelayCellTimex100 = 258/100 ps
8386 05:56:41.411779 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8387 05:56:41.414404 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8388 05:56:41.417649 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8389 05:56:41.421301 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8390 05:56:41.424468 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8391 05:56:41.427277 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8392 05:56:41.427697
8393 05:56:41.430880 CA PerBit enable=1, Macro0, CA PI delay=36
8394 05:56:41.431297
8395 05:56:41.434172 [CBTSetCACLKResult] CA Dly = 36
8396 05:56:41.437650 CS Dly: 10 (0~43)
8397 05:56:41.441049 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8398 05:56:41.444275 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8399 05:56:41.444698
8400 05:56:41.447859 ----->DramcWriteLeveling(PI) begin...
8401 05:56:41.448282 ==
8402 05:56:41.451484 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 05:56:41.457669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 05:56:41.458091 ==
8405 05:56:41.460762 Write leveling (Byte 0): 25 => 25
8406 05:56:41.461176 Write leveling (Byte 1): 30 => 30
8407 05:56:41.464145 DramcWriteLeveling(PI) end<-----
8408 05:56:41.464553
8409 05:56:41.464874 ==
8410 05:56:41.467715 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 05:56:41.474088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 05:56:41.474592 ==
8413 05:56:41.477692 [Gating] SW mode calibration
8414 05:56:41.484225 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8415 05:56:41.487640 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8416 05:56:41.493871 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 05:56:41.497011 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 05:56:41.500930 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 05:56:41.507018 1 4 12 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
8420 05:56:41.510637 1 4 16 | B1->B0 | 3232 3333 | 1 0 | (1 1) (0 0)
8421 05:56:41.513948 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 05:56:41.520828 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 05:56:41.524142 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 05:56:41.526886 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 05:56:41.534298 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 05:56:41.536795 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 05:56:41.540563 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8428 05:56:41.546980 1 5 16 | B1->B0 | 2727 2626 | 0 0 | (1 0) (1 0)
8429 05:56:41.550099 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 05:56:41.553561 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 05:56:41.559932 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 05:56:41.563769 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 05:56:41.566508 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 05:56:41.573416 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 05:56:41.576471 1 6 12 | B1->B0 | 2727 2323 | 0 1 | (0 0) (0 0)
8436 05:56:41.580114 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8437 05:56:41.586397 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 05:56:41.589575 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 05:56:41.592879 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 05:56:41.599763 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 05:56:41.603385 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 05:56:41.606508 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 05:56:41.613400 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8444 05:56:41.616557 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8445 05:56:41.620249 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8446 05:56:41.623462 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 05:56:41.629830 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 05:56:41.633106 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 05:56:41.636297 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 05:56:41.643293 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 05:56:41.646449 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 05:56:41.649374 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 05:56:41.656550 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 05:56:41.659431 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 05:56:41.662550 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 05:56:41.669263 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 05:56:41.672778 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 05:56:41.676277 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 05:56:41.682704 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8460 05:56:41.686157 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8461 05:56:41.689120 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8462 05:56:41.692489 Total UI for P1: 0, mck2ui 16
8463 05:56:41.695912 best dqsien dly found for B0: ( 1, 9, 14)
8464 05:56:41.702829 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8465 05:56:41.703387 Total UI for P1: 0, mck2ui 16
8466 05:56:41.708917 best dqsien dly found for B1: ( 1, 9, 16)
8467 05:56:41.712304 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8468 05:56:41.715382 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8469 05:56:41.715979
8470 05:56:41.719027 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8471 05:56:41.722322 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8472 05:56:41.725579 [Gating] SW calibration Done
8473 05:56:41.726118 ==
8474 05:56:41.728903 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 05:56:41.732308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 05:56:41.732730 ==
8477 05:56:41.735694 RX Vref Scan: 0
8478 05:56:41.736219
8479 05:56:41.736558 RX Vref 0 -> 0, step: 1
8480 05:56:41.738918
8481 05:56:41.739333 RX Delay 0 -> 252, step: 8
8482 05:56:41.742311 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8483 05:56:41.748873 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8484 05:56:41.752086 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8485 05:56:41.755278 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8486 05:56:41.759064 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8487 05:56:41.765594 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8488 05:56:41.768482 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8489 05:56:41.772173 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8490 05:56:41.775116 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8491 05:56:41.778581 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8492 05:56:41.781953 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8493 05:56:41.788713 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8494 05:56:41.792002 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8495 05:56:41.795540 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8496 05:56:41.798345 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8497 05:56:41.805537 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8498 05:56:41.806040 ==
8499 05:56:41.808402 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 05:56:41.811937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 05:56:41.812453 ==
8502 05:56:41.812786 DQS Delay:
8503 05:56:41.814873 DQS0 = 0, DQS1 = 0
8504 05:56:41.815289 DQM Delay:
8505 05:56:41.818284 DQM0 = 132, DQM1 = 126
8506 05:56:41.818700 DQ Delay:
8507 05:56:41.821860 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8508 05:56:41.824654 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8509 05:56:41.828046 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8510 05:56:41.831583 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8511 05:56:41.832000
8512 05:56:41.834795
8513 05:56:41.835208 ==
8514 05:56:41.838174 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 05:56:41.841291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 05:56:41.841803 ==
8517 05:56:41.842137
8518 05:56:41.842441
8519 05:56:41.844660 TX Vref Scan disable
8520 05:56:41.845073 == TX Byte 0 ==
8521 05:56:41.851309 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8522 05:56:41.854396 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8523 05:56:41.854813 == TX Byte 1 ==
8524 05:56:41.861352 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8525 05:56:41.864831 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8526 05:56:41.865321 ==
8527 05:56:41.867995 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 05:56:41.871122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 05:56:41.871542 ==
8530 05:56:41.884639
8531 05:56:41.888106 TX Vref early break, caculate TX vref
8532 05:56:41.891589 TX Vref=16, minBit 8, minWin=21, winSum=363
8533 05:56:41.894579 TX Vref=18, minBit 8, minWin=21, winSum=371
8534 05:56:41.897875 TX Vref=20, minBit 11, minWin=21, winSum=378
8535 05:56:41.901272 TX Vref=22, minBit 8, minWin=22, winSum=390
8536 05:56:41.904899 TX Vref=24, minBit 11, minWin=23, winSum=400
8537 05:56:41.911340 TX Vref=26, minBit 8, minWin=24, winSum=409
8538 05:56:41.914842 TX Vref=28, minBit 8, minWin=24, winSum=412
8539 05:56:41.918211 TX Vref=30, minBit 8, minWin=24, winSum=409
8540 05:56:41.921242 TX Vref=32, minBit 9, minWin=23, winSum=401
8541 05:56:41.924850 TX Vref=34, minBit 9, minWin=22, winSum=390
8542 05:56:41.931120 [TxChooseVref] Worse bit 8, Min win 24, Win sum 412, Final Vref 28
8543 05:56:41.931540
8544 05:56:41.934434 Final TX Range 0 Vref 28
8545 05:56:41.934850
8546 05:56:41.935175 ==
8547 05:56:41.937998 Dram Type= 6, Freq= 0, CH_1, rank 0
8548 05:56:41.940957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8549 05:56:41.941376 ==
8550 05:56:41.941775
8551 05:56:41.942088
8552 05:56:41.944475 TX Vref Scan disable
8553 05:56:41.950997 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8554 05:56:41.951464 == TX Byte 0 ==
8555 05:56:41.954666 u2DelayCellOfst[0]=22 cells (6 PI)
8556 05:56:41.957592 u2DelayCellOfst[1]=15 cells (4 PI)
8557 05:56:41.960876 u2DelayCellOfst[2]=0 cells (0 PI)
8558 05:56:41.964059 u2DelayCellOfst[3]=7 cells (2 PI)
8559 05:56:41.967230 u2DelayCellOfst[4]=7 cells (2 PI)
8560 05:56:41.970659 u2DelayCellOfst[5]=22 cells (6 PI)
8561 05:56:41.973993 u2DelayCellOfst[6]=18 cells (5 PI)
8562 05:56:41.977405 u2DelayCellOfst[7]=7 cells (2 PI)
8563 05:56:41.980920 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8564 05:56:41.983800 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8565 05:56:41.987073 == TX Byte 1 ==
8566 05:56:41.990605 u2DelayCellOfst[8]=0 cells (0 PI)
8567 05:56:41.991030 u2DelayCellOfst[9]=7 cells (2 PI)
8568 05:56:41.993903 u2DelayCellOfst[10]=15 cells (4 PI)
8569 05:56:41.997079 u2DelayCellOfst[11]=11 cells (3 PI)
8570 05:56:42.000638 u2DelayCellOfst[12]=15 cells (4 PI)
8571 05:56:42.003825 u2DelayCellOfst[13]=18 cells (5 PI)
8572 05:56:42.007424 u2DelayCellOfst[14]=18 cells (5 PI)
8573 05:56:42.010369 u2DelayCellOfst[15]=18 cells (5 PI)
8574 05:56:42.016941 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8575 05:56:42.020341 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8576 05:56:42.020829 DramC Write-DBI on
8577 05:56:42.021295 ==
8578 05:56:42.023641 Dram Type= 6, Freq= 0, CH_1, rank 0
8579 05:56:42.030130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8580 05:56:42.030817 ==
8581 05:56:42.031184
8582 05:56:42.031632
8583 05:56:42.032080 TX Vref Scan disable
8584 05:56:42.034484 == TX Byte 0 ==
8585 05:56:42.037429 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8586 05:56:42.041122 == TX Byte 1 ==
8587 05:56:42.044155 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8588 05:56:42.047216 DramC Write-DBI off
8589 05:56:42.047742
8590 05:56:42.048115 [DATLAT]
8591 05:56:42.048677 Freq=1600, CH1 RK0
8592 05:56:42.049125
8593 05:56:42.050817 DATLAT Default: 0xf
8594 05:56:42.051344 0, 0xFFFF, sum = 0
8595 05:56:42.054444 1, 0xFFFF, sum = 0
8596 05:56:42.057436 2, 0xFFFF, sum = 0
8597 05:56:42.057963 3, 0xFFFF, sum = 0
8598 05:56:42.060987 4, 0xFFFF, sum = 0
8599 05:56:42.061523 5, 0xFFFF, sum = 0
8600 05:56:42.063989 6, 0xFFFF, sum = 0
8601 05:56:42.064541 7, 0xFFFF, sum = 0
8602 05:56:42.067340 8, 0xFFFF, sum = 0
8603 05:56:42.067873 9, 0xFFFF, sum = 0
8604 05:56:42.070705 10, 0xFFFF, sum = 0
8605 05:56:42.071311 11, 0xFFFF, sum = 0
8606 05:56:42.073754 12, 0xFFFF, sum = 0
8607 05:56:42.074409 13, 0x8FFF, sum = 0
8608 05:56:42.077048 14, 0x0, sum = 1
8609 05:56:42.077426 15, 0x0, sum = 2
8610 05:56:42.080819 16, 0x0, sum = 3
8611 05:56:42.081123 17, 0x0, sum = 4
8612 05:56:42.083571 best_step = 15
8613 05:56:42.083869
8614 05:56:42.084104 ==
8615 05:56:42.087369 Dram Type= 6, Freq= 0, CH_1, rank 0
8616 05:56:42.090458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8617 05:56:42.090771 ==
8618 05:56:42.093591 RX Vref Scan: 1
8619 05:56:42.093892
8620 05:56:42.094128 Set Vref Range= 24 -> 127
8621 05:56:42.094351
8622 05:56:42.097020 RX Vref 24 -> 127, step: 1
8623 05:56:42.097319
8624 05:56:42.100185 RX Delay 11 -> 252, step: 4
8625 05:56:42.100482
8626 05:56:42.103663 Set Vref, RX VrefLevel [Byte0]: 24
8627 05:56:42.106757 [Byte1]: 24
8628 05:56:42.107056
8629 05:56:42.110424 Set Vref, RX VrefLevel [Byte0]: 25
8630 05:56:42.113274 [Byte1]: 25
8631 05:56:42.116834
8632 05:56:42.117132 Set Vref, RX VrefLevel [Byte0]: 26
8633 05:56:42.120241 [Byte1]: 26
8634 05:56:42.124545
8635 05:56:42.124626 Set Vref, RX VrefLevel [Byte0]: 27
8636 05:56:42.127444 [Byte1]: 27
8637 05:56:42.132292
8638 05:56:42.132389 Set Vref, RX VrefLevel [Byte0]: 28
8639 05:56:42.135393 [Byte1]: 28
8640 05:56:42.139663
8641 05:56:42.139793 Set Vref, RX VrefLevel [Byte0]: 29
8642 05:56:42.142973 [Byte1]: 29
8643 05:56:42.147335
8644 05:56:42.147425 Set Vref, RX VrefLevel [Byte0]: 30
8645 05:56:42.150311 [Byte1]: 30
8646 05:56:42.154822
8647 05:56:42.154904 Set Vref, RX VrefLevel [Byte0]: 31
8648 05:56:42.158146 [Byte1]: 31
8649 05:56:42.162418
8650 05:56:42.162523 Set Vref, RX VrefLevel [Byte0]: 32
8651 05:56:42.165967 [Byte1]: 32
8652 05:56:42.170248
8653 05:56:42.170352 Set Vref, RX VrefLevel [Byte0]: 33
8654 05:56:42.173074 [Byte1]: 33
8655 05:56:42.177809
8656 05:56:42.177954 Set Vref, RX VrefLevel [Byte0]: 34
8657 05:56:42.181279 [Byte1]: 34
8658 05:56:42.185086
8659 05:56:42.185221 Set Vref, RX VrefLevel [Byte0]: 35
8660 05:56:42.188616 [Byte1]: 35
8661 05:56:42.192627
8662 05:56:42.192815 Set Vref, RX VrefLevel [Byte0]: 36
8663 05:56:42.196287 [Byte1]: 36
8664 05:56:42.200454
8665 05:56:42.200679 Set Vref, RX VrefLevel [Byte0]: 37
8666 05:56:42.203776 [Byte1]: 37
8667 05:56:42.208334
8668 05:56:42.208576 Set Vref, RX VrefLevel [Byte0]: 38
8669 05:56:42.211587 [Byte1]: 38
8670 05:56:42.215885
8671 05:56:42.216276 Set Vref, RX VrefLevel [Byte0]: 39
8672 05:56:42.219274 [Byte1]: 39
8673 05:56:42.223905
8674 05:56:42.224312 Set Vref, RX VrefLevel [Byte0]: 40
8675 05:56:42.226938 [Byte1]: 40
8676 05:56:42.231003
8677 05:56:42.231615 Set Vref, RX VrefLevel [Byte0]: 41
8678 05:56:42.234445 [Byte1]: 41
8679 05:56:42.238651
8680 05:56:42.239089 Set Vref, RX VrefLevel [Byte0]: 42
8681 05:56:42.242174 [Byte1]: 42
8682 05:56:42.246334
8683 05:56:42.246734 Set Vref, RX VrefLevel [Byte0]: 43
8684 05:56:42.250000 [Byte1]: 43
8685 05:56:42.253973
8686 05:56:42.254453 Set Vref, RX VrefLevel [Byte0]: 44
8687 05:56:42.257553 [Byte1]: 44
8688 05:56:42.261461
8689 05:56:42.261904 Set Vref, RX VrefLevel [Byte0]: 45
8690 05:56:42.265007 [Byte1]: 45
8691 05:56:42.269322
8692 05:56:42.269765 Set Vref, RX VrefLevel [Byte0]: 46
8693 05:56:42.272818 [Byte1]: 46
8694 05:56:42.276786
8695 05:56:42.277361 Set Vref, RX VrefLevel [Byte0]: 47
8696 05:56:42.280390 [Byte1]: 47
8697 05:56:42.284413
8698 05:56:42.284813 Set Vref, RX VrefLevel [Byte0]: 48
8699 05:56:42.287727 [Byte1]: 48
8700 05:56:42.292301
8701 05:56:42.292704 Set Vref, RX VrefLevel [Byte0]: 49
8702 05:56:42.295338 [Byte1]: 49
8703 05:56:42.299772
8704 05:56:42.300261 Set Vref, RX VrefLevel [Byte0]: 50
8705 05:56:42.303001 [Byte1]: 50
8706 05:56:42.307356
8707 05:56:42.307756 Set Vref, RX VrefLevel [Byte0]: 51
8708 05:56:42.310351 [Byte1]: 51
8709 05:56:42.315260
8710 05:56:42.315660 Set Vref, RX VrefLevel [Byte0]: 52
8711 05:56:42.318679 [Byte1]: 52
8712 05:56:42.322832
8713 05:56:42.323233 Set Vref, RX VrefLevel [Byte0]: 53
8714 05:56:42.325782 [Byte1]: 53
8715 05:56:42.330434
8716 05:56:42.330847 Set Vref, RX VrefLevel [Byte0]: 54
8717 05:56:42.333410 [Byte1]: 54
8718 05:56:42.337804
8719 05:56:42.338290 Set Vref, RX VrefLevel [Byte0]: 55
8720 05:56:42.341008 [Byte1]: 55
8721 05:56:42.344963
8722 05:56:42.345515 Set Vref, RX VrefLevel [Byte0]: 56
8723 05:56:42.348522 [Byte1]: 56
8724 05:56:42.352808
8725 05:56:42.353333 Set Vref, RX VrefLevel [Byte0]: 57
8726 05:56:42.356266 [Byte1]: 57
8727 05:56:42.360586
8728 05:56:42.361088 Set Vref, RX VrefLevel [Byte0]: 58
8729 05:56:42.363547 [Byte1]: 58
8730 05:56:42.368286
8731 05:56:42.368786 Set Vref, RX VrefLevel [Byte0]: 59
8732 05:56:42.371492 [Byte1]: 59
8733 05:56:42.375583
8734 05:56:42.375983 Set Vref, RX VrefLevel [Byte0]: 60
8735 05:56:42.378993 [Byte1]: 60
8736 05:56:42.383397
8737 05:56:42.383788 Set Vref, RX VrefLevel [Byte0]: 61
8738 05:56:42.386919 [Byte1]: 61
8739 05:56:42.390974
8740 05:56:42.391356 Set Vref, RX VrefLevel [Byte0]: 62
8741 05:56:42.394030 [Byte1]: 62
8742 05:56:42.398610
8743 05:56:42.398992 Set Vref, RX VrefLevel [Byte0]: 63
8744 05:56:42.401957 [Byte1]: 63
8745 05:56:42.406316
8746 05:56:42.406814 Set Vref, RX VrefLevel [Byte0]: 64
8747 05:56:42.409161 [Byte1]: 64
8748 05:56:42.413845
8749 05:56:42.414334 Set Vref, RX VrefLevel [Byte0]: 65
8750 05:56:42.417066 [Byte1]: 65
8751 05:56:42.421207
8752 05:56:42.421309 Set Vref, RX VrefLevel [Byte0]: 66
8753 05:56:42.424401 [Byte1]: 66
8754 05:56:42.428804
8755 05:56:42.428905 Set Vref, RX VrefLevel [Byte0]: 67
8756 05:56:42.432153 [Byte1]: 67
8757 05:56:42.436182
8758 05:56:42.436293 Set Vref, RX VrefLevel [Byte0]: 68
8759 05:56:42.439773 [Byte1]: 68
8760 05:56:42.444226
8761 05:56:42.444337 Set Vref, RX VrefLevel [Byte0]: 69
8762 05:56:42.450669 [Byte1]: 69
8763 05:56:42.450779
8764 05:56:42.453446 Set Vref, RX VrefLevel [Byte0]: 70
8765 05:56:42.456973 [Byte1]: 70
8766 05:56:42.457056
8767 05:56:42.460036 Set Vref, RX VrefLevel [Byte0]: 71
8768 05:56:42.463725 [Byte1]: 71
8769 05:56:42.466653
8770 05:56:42.466737 Set Vref, RX VrefLevel [Byte0]: 72
8771 05:56:42.470073 [Byte1]: 72
8772 05:56:42.474384
8773 05:56:42.474460 Final RX Vref Byte 0 = 58 to rank0
8774 05:56:42.477631 Final RX Vref Byte 1 = 55 to rank0
8775 05:56:42.481342 Final RX Vref Byte 0 = 58 to rank1
8776 05:56:42.484268 Final RX Vref Byte 1 = 55 to rank1==
8777 05:56:42.487651 Dram Type= 6, Freq= 0, CH_1, rank 0
8778 05:56:42.494226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 05:56:42.494307 ==
8780 05:56:42.494372 DQS Delay:
8781 05:56:42.494438 DQS0 = 0, DQS1 = 0
8782 05:56:42.497727 DQM Delay:
8783 05:56:42.497798 DQM0 = 131, DQM1 = 123
8784 05:56:42.500722 DQ Delay:
8785 05:56:42.504316 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =130
8786 05:56:42.507584 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8787 05:56:42.510754 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8788 05:56:42.514362 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8789 05:56:42.514445
8790 05:56:42.514553
8791 05:56:42.514643
8792 05:56:42.517806 [DramC_TX_OE_Calibration] TA2
8793 05:56:42.520751 Original DQ_B0 (3 6) =30, OEN = 27
8794 05:56:42.524305 Original DQ_B1 (3 6) =30, OEN = 27
8795 05:56:42.527659 24, 0x0, End_B0=24 End_B1=24
8796 05:56:42.527736 25, 0x0, End_B0=25 End_B1=25
8797 05:56:42.530534 26, 0x0, End_B0=26 End_B1=26
8798 05:56:42.533964 27, 0x0, End_B0=27 End_B1=27
8799 05:56:42.537532 28, 0x0, End_B0=28 End_B1=28
8800 05:56:42.541090 29, 0x0, End_B0=29 End_B1=29
8801 05:56:42.541165 30, 0x0, End_B0=30 End_B1=30
8802 05:56:42.544069 31, 0x4141, End_B0=30 End_B1=30
8803 05:56:42.547521 Byte0 end_step=30 best_step=27
8804 05:56:42.550516 Byte1 end_step=30 best_step=27
8805 05:56:42.553765 Byte0 TX OE(2T, 0.5T) = (3, 3)
8806 05:56:42.557114 Byte1 TX OE(2T, 0.5T) = (3, 3)
8807 05:56:42.557192
8808 05:56:42.557255
8809 05:56:42.564206 [DQSOSCAuto] RK0, (LSB)MR18= 0x80d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8810 05:56:42.567021 CH1 RK0: MR19=303, MR18=80D
8811 05:56:42.573796 CH1_RK0: MR19=0x303, MR18=0x80D, DQSOSC=403, MR23=63, INC=22, DEC=15
8812 05:56:42.573874
8813 05:56:42.576873 ----->DramcWriteLeveling(PI) begin...
8814 05:56:42.576951 ==
8815 05:56:42.580349 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 05:56:42.583936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 05:56:42.584013 ==
8818 05:56:42.587272 Write leveling (Byte 0): 24 => 24
8819 05:56:42.590222 Write leveling (Byte 1): 27 => 27
8820 05:56:42.593698 DramcWriteLeveling(PI) end<-----
8821 05:56:42.593804
8822 05:56:42.593869 ==
8823 05:56:42.597286 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 05:56:42.600107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 05:56:42.600186 ==
8826 05:56:42.603664 [Gating] SW mode calibration
8827 05:56:42.610094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8828 05:56:42.616523 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8829 05:56:42.620145 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 05:56:42.626768 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 05:56:42.630324 1 4 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8832 05:56:42.633284 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
8833 05:56:42.636805 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 05:56:42.643086 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 05:56:42.646453 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 05:56:42.649782 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 05:56:42.656397 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 05:56:42.659745 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8839 05:56:42.663017 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
8840 05:56:42.669596 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8841 05:56:42.672855 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 05:56:42.676197 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 05:56:42.683064 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 05:56:42.686080 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 05:56:42.689771 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 05:56:42.696151 1 6 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8847 05:56:42.699079 1 6 8 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
8848 05:56:42.702480 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8849 05:56:42.709032 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 05:56:42.712509 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 05:56:42.716160 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 05:56:42.722269 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 05:56:42.725792 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 05:56:42.728883 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 05:56:42.735562 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8856 05:56:42.739123 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8857 05:56:42.742057 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 05:56:42.748680 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 05:56:42.752172 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 05:56:42.755356 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 05:56:42.762454 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 05:56:42.765731 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 05:56:42.768744 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 05:56:42.775421 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 05:56:42.779137 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 05:56:42.781861 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 05:56:42.788897 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 05:56:42.791779 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 05:56:42.795248 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 05:56:42.802107 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 05:56:42.804929 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8872 05:56:42.808490 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8873 05:56:42.814917 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8874 05:56:42.814997 Total UI for P1: 0, mck2ui 16
8875 05:56:42.821961 best dqsien dly found for B0: ( 1, 9, 10)
8876 05:56:42.822044 Total UI for P1: 0, mck2ui 16
8877 05:56:42.828752 best dqsien dly found for B1: ( 1, 9, 10)
8878 05:56:42.831679 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8879 05:56:42.834995 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8880 05:56:42.835078
8881 05:56:42.838618 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8882 05:56:42.841547 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8883 05:56:42.845124 [Gating] SW calibration Done
8884 05:56:42.845202 ==
8885 05:56:42.848552 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 05:56:42.851559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 05:56:42.851636 ==
8888 05:56:42.855102 RX Vref Scan: 0
8889 05:56:42.855180
8890 05:56:42.855241 RX Vref 0 -> 0, step: 1
8891 05:56:42.855299
8892 05:56:42.858495 RX Delay 0 -> 252, step: 8
8893 05:56:42.861851 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8894 05:56:42.868608 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8895 05:56:42.871984 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8896 05:56:42.874917 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8897 05:56:42.878337 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8898 05:56:42.881744 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8899 05:56:42.888481 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8900 05:56:42.891555 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8901 05:56:42.895085 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8902 05:56:42.898281 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8903 05:56:42.901326 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8904 05:56:42.908449 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8905 05:56:42.911513 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8906 05:56:42.915109 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8907 05:56:42.918342 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8908 05:56:42.921328 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8909 05:56:42.924662 ==
8910 05:56:42.927988 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 05:56:42.931450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 05:56:42.931525 ==
8913 05:56:42.931590 DQS Delay:
8914 05:56:42.934394 DQS0 = 0, DQS1 = 0
8915 05:56:42.934492 DQM Delay:
8916 05:56:42.938030 DQM0 = 132, DQM1 = 129
8917 05:56:42.938100 DQ Delay:
8918 05:56:42.941388 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8919 05:56:42.944489 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8920 05:56:42.948188 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8921 05:56:42.951103 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8922 05:56:42.951176
8923 05:56:42.951241
8924 05:56:42.951300 ==
8925 05:56:42.954632 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 05:56:42.961076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 05:56:42.961154 ==
8928 05:56:42.961217
8929 05:56:42.961280
8930 05:56:42.964382 TX Vref Scan disable
8931 05:56:42.964459 == TX Byte 0 ==
8932 05:56:42.967827 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8933 05:56:42.974017 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8934 05:56:42.974109 == TX Byte 1 ==
8935 05:56:42.977305 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8936 05:56:42.984187 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8937 05:56:42.984269 ==
8938 05:56:42.987763 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 05:56:42.990560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 05:56:42.990638 ==
8941 05:56:43.004204
8942 05:56:43.007397 TX Vref early break, caculate TX vref
8943 05:56:43.010380 TX Vref=16, minBit 0, minWin=23, winSum=385
8944 05:56:43.013655 TX Vref=18, minBit 0, minWin=23, winSum=391
8945 05:56:43.016943 TX Vref=20, minBit 5, minWin=24, winSum=403
8946 05:56:43.020725 TX Vref=22, minBit 0, minWin=24, winSum=411
8947 05:56:43.023763 TX Vref=24, minBit 0, minWin=24, winSum=418
8948 05:56:43.030448 TX Vref=26, minBit 6, minWin=25, winSum=425
8949 05:56:43.033727 TX Vref=28, minBit 1, minWin=25, winSum=426
8950 05:56:43.037197 TX Vref=30, minBit 5, minWin=25, winSum=425
8951 05:56:43.040162 TX Vref=32, minBit 1, minWin=24, winSum=414
8952 05:56:43.043714 TX Vref=34, minBit 1, minWin=23, winSum=403
8953 05:56:43.050478 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 28
8954 05:56:43.050560
8955 05:56:43.053435 Final TX Range 0 Vref 28
8956 05:56:43.053560
8957 05:56:43.053623 ==
8958 05:56:43.056653 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 05:56:43.060076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 05:56:43.060151 ==
8961 05:56:43.060213
8962 05:56:43.060277
8963 05:56:43.063590 TX Vref Scan disable
8964 05:56:43.069774 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8965 05:56:43.069858 == TX Byte 0 ==
8966 05:56:43.073266 u2DelayCellOfst[0]=18 cells (5 PI)
8967 05:56:43.076750 u2DelayCellOfst[1]=11 cells (3 PI)
8968 05:56:43.079567 u2DelayCellOfst[2]=0 cells (0 PI)
8969 05:56:43.082897 u2DelayCellOfst[3]=3 cells (1 PI)
8970 05:56:43.086261 u2DelayCellOfst[4]=7 cells (2 PI)
8971 05:56:43.089602 u2DelayCellOfst[5]=22 cells (6 PI)
8972 05:56:43.093042 u2DelayCellOfst[6]=18 cells (5 PI)
8973 05:56:43.096630 u2DelayCellOfst[7]=7 cells (2 PI)
8974 05:56:43.100006 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8975 05:56:43.103056 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8976 05:56:43.106217 == TX Byte 1 ==
8977 05:56:43.109918 u2DelayCellOfst[8]=0 cells (0 PI)
8978 05:56:43.109994 u2DelayCellOfst[9]=7 cells (2 PI)
8979 05:56:43.112732 u2DelayCellOfst[10]=11 cells (3 PI)
8980 05:56:43.116399 u2DelayCellOfst[11]=7 cells (2 PI)
8981 05:56:43.119370 u2DelayCellOfst[12]=15 cells (4 PI)
8982 05:56:43.122747 u2DelayCellOfst[13]=18 cells (5 PI)
8983 05:56:43.126515 u2DelayCellOfst[14]=18 cells (5 PI)
8984 05:56:43.129445 u2DelayCellOfst[15]=22 cells (6 PI)
8985 05:56:43.132868 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8986 05:56:43.139585 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8987 05:56:43.139667 DramC Write-DBI on
8988 05:56:43.139735 ==
8989 05:56:43.142730 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 05:56:43.149453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 05:56:43.149578 ==
8992 05:56:43.149643
8993 05:56:43.149716
8994 05:56:43.149787 TX Vref Scan disable
8995 05:56:43.153019 == TX Byte 0 ==
8996 05:56:43.156404 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8997 05:56:43.159859 == TX Byte 1 ==
8998 05:56:43.163034 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8999 05:56:43.166179 DramC Write-DBI off
9000 05:56:43.166262
9001 05:56:43.166361 [DATLAT]
9002 05:56:43.166458 Freq=1600, CH1 RK1
9003 05:56:43.166554
9004 05:56:43.169583 DATLAT Default: 0xf
9005 05:56:43.169680 0, 0xFFFF, sum = 0
9006 05:56:43.172866 1, 0xFFFF, sum = 0
9007 05:56:43.172950 2, 0xFFFF, sum = 0
9008 05:56:43.176377 3, 0xFFFF, sum = 0
9009 05:56:43.179411 4, 0xFFFF, sum = 0
9010 05:56:43.179518 5, 0xFFFF, sum = 0
9011 05:56:43.183090 6, 0xFFFF, sum = 0
9012 05:56:43.183168 7, 0xFFFF, sum = 0
9013 05:56:43.186124 8, 0xFFFF, sum = 0
9014 05:56:43.186204 9, 0xFFFF, sum = 0
9015 05:56:43.189712 10, 0xFFFF, sum = 0
9016 05:56:43.189795 11, 0xFFFF, sum = 0
9017 05:56:43.193001 12, 0xFFFF, sum = 0
9018 05:56:43.193077 13, 0x8FFF, sum = 0
9019 05:56:43.196322 14, 0x0, sum = 1
9020 05:56:43.196399 15, 0x0, sum = 2
9021 05:56:43.199243 16, 0x0, sum = 3
9022 05:56:43.199316 17, 0x0, sum = 4
9023 05:56:43.202860 best_step = 15
9024 05:56:43.202941
9025 05:56:43.203003 ==
9026 05:56:43.206372 Dram Type= 6, Freq= 0, CH_1, rank 1
9027 05:56:43.209215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9028 05:56:43.209336 ==
9029 05:56:43.212983 RX Vref Scan: 0
9030 05:56:43.213065
9031 05:56:43.213171 RX Vref 0 -> 0, step: 1
9032 05:56:43.213262
9033 05:56:43.215927 RX Delay 11 -> 252, step: 4
9034 05:56:43.219495 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9035 05:56:43.226496 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9036 05:56:43.229335 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9037 05:56:43.232886 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
9038 05:56:43.235860 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9039 05:56:43.239201 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9040 05:56:43.245696 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9041 05:56:43.249097 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
9042 05:56:43.252249 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
9043 05:56:43.255869 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9044 05:56:43.259031 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9045 05:56:43.265432 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9046 05:56:43.268858 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9047 05:56:43.272079 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9048 05:56:43.275841 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9049 05:56:43.282337 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9050 05:56:43.282420 ==
9051 05:56:43.285866 Dram Type= 6, Freq= 0, CH_1, rank 1
9052 05:56:43.288754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9053 05:56:43.288835 ==
9054 05:56:43.288899 DQS Delay:
9055 05:56:43.292347 DQS0 = 0, DQS1 = 0
9056 05:56:43.292427 DQM Delay:
9057 05:56:43.295765 DQM0 = 130, DQM1 = 125
9058 05:56:43.295846 DQ Delay:
9059 05:56:43.299298 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =128
9060 05:56:43.301918 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =126
9061 05:56:43.305790 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =120
9062 05:56:43.308806 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =136
9063 05:56:43.308886
9064 05:56:43.308950
9065 05:56:43.312153
9066 05:56:43.312233 [DramC_TX_OE_Calibration] TA2
9067 05:56:43.315572 Original DQ_B0 (3 6) =30, OEN = 27
9068 05:56:43.318794 Original DQ_B1 (3 6) =30, OEN = 27
9069 05:56:43.322342 24, 0x0, End_B0=24 End_B1=24
9070 05:56:43.325201 25, 0x0, End_B0=25 End_B1=25
9071 05:56:43.328575 26, 0x0, End_B0=26 End_B1=26
9072 05:56:43.328657 27, 0x0, End_B0=27 End_B1=27
9073 05:56:43.331654 28, 0x0, End_B0=28 End_B1=28
9074 05:56:43.335400 29, 0x0, End_B0=29 End_B1=29
9075 05:56:43.338642 30, 0x0, End_B0=30 End_B1=30
9076 05:56:43.342119 31, 0x4545, End_B0=30 End_B1=30
9077 05:56:43.342203 Byte0 end_step=30 best_step=27
9078 05:56:43.345017 Byte1 end_step=30 best_step=27
9079 05:56:43.348401 Byte0 TX OE(2T, 0.5T) = (3, 3)
9080 05:56:43.351991 Byte1 TX OE(2T, 0.5T) = (3, 3)
9081 05:56:43.352080
9082 05:56:43.352145
9083 05:56:43.358458 [DQSOSCAuto] RK1, (LSB)MR18= 0x101c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9084 05:56:43.361742 CH1 RK1: MR19=303, MR18=101C
9085 05:56:43.368267 CH1_RK1: MR19=0x303, MR18=0x101C, DQSOSC=395, MR23=63, INC=23, DEC=15
9086 05:56:43.371766 [RxdqsGatingPostProcess] freq 1600
9087 05:56:43.378440 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9088 05:56:43.381640 best DQS0 dly(2T, 0.5T) = (1, 1)
9089 05:56:43.384966 best DQS1 dly(2T, 0.5T) = (1, 1)
9090 05:56:43.385049 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9091 05:56:43.388127 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9092 05:56:43.391660 best DQS0 dly(2T, 0.5T) = (1, 1)
9093 05:56:43.394794 best DQS1 dly(2T, 0.5T) = (1, 1)
9094 05:56:43.398269 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9095 05:56:43.401772 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9096 05:56:43.404775 Pre-setting of DQS Precalculation
9097 05:56:43.411234 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9098 05:56:43.418179 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9099 05:56:43.424377 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9100 05:56:43.424460
9101 05:56:43.424525
9102 05:56:43.427952 [Calibration Summary] 3200 Mbps
9103 05:56:43.428034 CH 0, Rank 0
9104 05:56:43.431440 SW Impedance : PASS
9105 05:56:43.434326 DUTY Scan : NO K
9106 05:56:43.434468 ZQ Calibration : PASS
9107 05:56:43.437674 Jitter Meter : NO K
9108 05:56:43.441233 CBT Training : PASS
9109 05:56:43.441344 Write leveling : PASS
9110 05:56:43.444524 RX DQS gating : PASS
9111 05:56:43.444605 RX DQ/DQS(RDDQC) : PASS
9112 05:56:43.447755 TX DQ/DQS : PASS
9113 05:56:43.451181 RX DATLAT : PASS
9114 05:56:43.451261 RX DQ/DQS(Engine): PASS
9115 05:56:43.454681 TX OE : PASS
9116 05:56:43.454762 All Pass.
9117 05:56:43.454826
9118 05:56:43.457594 CH 0, Rank 1
9119 05:56:43.457675 SW Impedance : PASS
9120 05:56:43.461162 DUTY Scan : NO K
9121 05:56:43.464303 ZQ Calibration : PASS
9122 05:56:43.464399 Jitter Meter : NO K
9123 05:56:43.467833 CBT Training : PASS
9124 05:56:43.470673 Write leveling : PASS
9125 05:56:43.470753 RX DQS gating : PASS
9126 05:56:43.474138 RX DQ/DQS(RDDQC) : PASS
9127 05:56:43.477546 TX DQ/DQS : PASS
9128 05:56:43.477627 RX DATLAT : PASS
9129 05:56:43.480951 RX DQ/DQS(Engine): PASS
9130 05:56:43.484208 TX OE : PASS
9131 05:56:43.484289 All Pass.
9132 05:56:43.484353
9133 05:56:43.484412 CH 1, Rank 0
9134 05:56:43.487246 SW Impedance : PASS
9135 05:56:43.490713 DUTY Scan : NO K
9136 05:56:43.490807 ZQ Calibration : PASS
9137 05:56:43.494015 Jitter Meter : NO K
9138 05:56:43.497218 CBT Training : PASS
9139 05:56:43.497335 Write leveling : PASS
9140 05:56:43.500272 RX DQS gating : PASS
9141 05:56:43.503740 RX DQ/DQS(RDDQC) : PASS
9142 05:56:43.503812 TX DQ/DQS : PASS
9143 05:56:43.507200 RX DATLAT : PASS
9144 05:56:43.507283 RX DQ/DQS(Engine): PASS
9145 05:56:43.510623 TX OE : PASS
9146 05:56:43.510729 All Pass.
9147 05:56:43.510819
9148 05:56:43.513589 CH 1, Rank 1
9149 05:56:43.513669 SW Impedance : PASS
9150 05:56:43.516957 DUTY Scan : NO K
9151 05:56:43.520318 ZQ Calibration : PASS
9152 05:56:43.520399 Jitter Meter : NO K
9153 05:56:43.523725 CBT Training : PASS
9154 05:56:43.526958 Write leveling : PASS
9155 05:56:43.527038 RX DQS gating : PASS
9156 05:56:43.530324 RX DQ/DQS(RDDQC) : PASS
9157 05:56:43.533304 TX DQ/DQS : PASS
9158 05:56:43.533387 RX DATLAT : PASS
9159 05:56:43.536815 RX DQ/DQS(Engine): PASS
9160 05:56:43.540512 TX OE : PASS
9161 05:56:43.540594 All Pass.
9162 05:56:43.540658
9163 05:56:43.543471 DramC Write-DBI on
9164 05:56:43.543552 PER_BANK_REFRESH: Hybrid Mode
9165 05:56:43.547269 TX_TRACKING: ON
9166 05:56:43.556606 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9167 05:56:43.563883 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9168 05:56:43.569995 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9169 05:56:43.573625 [FAST_K] Save calibration result to emmc
9170 05:56:43.576473 sync common calibartion params.
9171 05:56:43.580104 sync cbt_mode0:1, 1:1
9172 05:56:43.580213 dram_init: ddr_geometry: 2
9173 05:56:43.583075 dram_init: ddr_geometry: 2
9174 05:56:43.586582 dram_init: ddr_geometry: 2
9175 05:56:43.590091 0:dram_rank_size:100000000
9176 05:56:43.590184 1:dram_rank_size:100000000
9177 05:56:43.596533 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9178 05:56:43.600053 DFS_SHUFFLE_HW_MODE: ON
9179 05:56:43.603346 dramc_set_vcore_voltage set vcore to 725000
9180 05:56:43.603449 Read voltage for 1600, 0
9181 05:56:43.606212 Vio18 = 0
9182 05:56:43.606363 Vcore = 725000
9183 05:56:43.606460 Vdram = 0
9184 05:56:43.609692 Vddq = 0
9185 05:56:43.609783 Vmddr = 0
9186 05:56:43.612978 switch to 3200 Mbps bootup
9187 05:56:43.613053 [DramcRunTimeConfig]
9188 05:56:43.616458 PHYPLL
9189 05:56:43.616559 DPM_CONTROL_AFTERK: ON
9190 05:56:43.619840 PER_BANK_REFRESH: ON
9191 05:56:43.623014 REFRESH_OVERHEAD_REDUCTION: ON
9192 05:56:43.623089 CMD_PICG_NEW_MODE: OFF
9193 05:56:43.626200 XRTWTW_NEW_MODE: ON
9194 05:56:43.626274 XRTRTR_NEW_MODE: ON
9195 05:56:43.629670 TX_TRACKING: ON
9196 05:56:43.629744 RDSEL_TRACKING: OFF
9197 05:56:43.633023 DQS Precalculation for DVFS: ON
9198 05:56:43.635912 RX_TRACKING: OFF
9199 05:56:43.635992 HW_GATING DBG: ON
9200 05:56:43.639556 ZQCS_ENABLE_LP4: ON
9201 05:56:43.639643 RX_PICG_NEW_MODE: ON
9202 05:56:43.642612 TX_PICG_NEW_MODE: ON
9203 05:56:43.642688 ENABLE_RX_DCM_DPHY: ON
9204 05:56:43.646123 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9205 05:56:43.649117 DUMMY_READ_FOR_TRACKING: OFF
9206 05:56:43.652528 !!! SPM_CONTROL_AFTERK: OFF
9207 05:56:43.656195 !!! SPM could not control APHY
9208 05:56:43.656274 IMPEDANCE_TRACKING: ON
9209 05:56:43.659435 TEMP_SENSOR: ON
9210 05:56:43.659545 HW_SAVE_FOR_SR: OFF
9211 05:56:43.662922 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9212 05:56:43.665680 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9213 05:56:43.669285 Read ODT Tracking: ON
9214 05:56:43.672715 Refresh Rate DeBounce: ON
9215 05:56:43.672793 DFS_NO_QUEUE_FLUSH: ON
9216 05:56:43.675533 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9217 05:56:43.679102 ENABLE_DFS_RUNTIME_MRW: OFF
9218 05:56:43.682237 DDR_RESERVE_NEW_MODE: ON
9219 05:56:43.682317 MR_CBT_SWITCH_FREQ: ON
9220 05:56:43.685820 =========================
9221 05:56:43.704415 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9222 05:56:43.707998 dram_init: ddr_geometry: 2
9223 05:56:43.726035 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9224 05:56:43.729336 dram_init: dram init end (result: 0)
9225 05:56:43.736521 DRAM-K: Full calibration passed in 24563 msecs
9226 05:56:43.739307 MRC: failed to locate region type 0.
9227 05:56:43.739414 DRAM rank0 size:0x100000000,
9228 05:56:43.742879 DRAM rank1 size=0x100000000
9229 05:56:43.752522 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9230 05:56:43.759646 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9231 05:56:43.765842 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9232 05:56:43.772652 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9233 05:56:43.775467 DRAM rank0 size:0x100000000,
9234 05:56:43.778902 DRAM rank1 size=0x100000000
9235 05:56:43.778976 CBMEM:
9236 05:56:43.782458 IMD: root @ 0xfffff000 254 entries.
9237 05:56:43.786195 IMD: root @ 0xffffec00 62 entries.
9238 05:56:43.789086 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9239 05:56:43.795423 WARNING: RO_VPD is uninitialized or empty.
9240 05:56:43.799027 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9241 05:56:43.806018 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9242 05:56:43.819005 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9243 05:56:43.830132 BS: romstage times (exec / console): total (unknown) / 24031 ms
9244 05:56:43.830217
9245 05:56:43.830323
9246 05:56:43.840041 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9247 05:56:43.843487 ARM64: Exception handlers installed.
9248 05:56:43.846862 ARM64: Testing exception
9249 05:56:43.849927 ARM64: Done test exception
9250 05:56:43.850056 Enumerating buses...
9251 05:56:43.853361 Show all devs... Before device enumeration.
9252 05:56:43.856759 Root Device: enabled 1
9253 05:56:43.859827 CPU_CLUSTER: 0: enabled 1
9254 05:56:43.859935 CPU: 00: enabled 1
9255 05:56:43.863427 Compare with tree...
9256 05:56:43.863526 Root Device: enabled 1
9257 05:56:43.867123 CPU_CLUSTER: 0: enabled 1
9258 05:56:43.870012 CPU: 00: enabled 1
9259 05:56:43.870094 Root Device scanning...
9260 05:56:43.873377 scan_static_bus for Root Device
9261 05:56:43.876535 CPU_CLUSTER: 0 enabled
9262 05:56:43.880053 scan_static_bus for Root Device done
9263 05:56:43.883152 scan_bus: bus Root Device finished in 8 msecs
9264 05:56:43.883235 done
9265 05:56:43.889953 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9266 05:56:43.893113 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9267 05:56:43.899931 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9268 05:56:43.903382 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9269 05:56:43.906357 Allocating resources...
9270 05:56:43.909687 Reading resources...
9271 05:56:43.913168 Root Device read_resources bus 0 link: 0
9272 05:56:43.916642 DRAM rank0 size:0x100000000,
9273 05:56:43.916724 DRAM rank1 size=0x100000000
9274 05:56:43.919568 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9275 05:56:43.922960 CPU: 00 missing read_resources
9276 05:56:43.929366 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9277 05:56:43.932829 Root Device read_resources bus 0 link: 0 done
9278 05:56:43.932912 Done reading resources.
9279 05:56:43.939165 Show resources in subtree (Root Device)...After reading.
9280 05:56:43.942594 Root Device child on link 0 CPU_CLUSTER: 0
9281 05:56:43.946010 CPU_CLUSTER: 0 child on link 0 CPU: 00
9282 05:56:43.955994 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9283 05:56:43.956077 CPU: 00
9284 05:56:43.959397 Root Device assign_resources, bus 0 link: 0
9285 05:56:43.962744 CPU_CLUSTER: 0 missing set_resources
9286 05:56:43.969313 Root Device assign_resources, bus 0 link: 0 done
9287 05:56:43.969396 Done setting resources.
9288 05:56:43.975729 Show resources in subtree (Root Device)...After assigning values.
9289 05:56:43.979027 Root Device child on link 0 CPU_CLUSTER: 0
9290 05:56:43.982293 CPU_CLUSTER: 0 child on link 0 CPU: 00
9291 05:56:43.992335 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9292 05:56:43.992512 CPU: 00
9293 05:56:43.995715 Done allocating resources.
9294 05:56:44.002203 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9295 05:56:44.002286 Enabling resources...
9296 05:56:44.002351 done.
9297 05:56:44.008488 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9298 05:56:44.012239 Initializing devices...
9299 05:56:44.012340 Root Device init
9300 05:56:44.015132 init hardware done!
9301 05:56:44.015209 0x00000018: ctrlr->caps
9302 05:56:44.018642 52.000 MHz: ctrlr->f_max
9303 05:56:44.021978 0.400 MHz: ctrlr->f_min
9304 05:56:44.022097 0x40ff8080: ctrlr->voltages
9305 05:56:44.025411 sclk: 390625
9306 05:56:44.025530 Bus Width = 1
9307 05:56:44.025598 sclk: 390625
9308 05:56:44.028475 Bus Width = 1
9309 05:56:44.031983 Early init status = 3
9310 05:56:44.034923 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9311 05:56:44.038695 in-header: 03 fc 00 00 01 00 00 00
9312 05:56:44.042190 in-data: 00
9313 05:56:44.045534 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9314 05:56:44.050904 in-header: 03 fd 00 00 00 00 00 00
9315 05:56:44.054459 in-data:
9316 05:56:44.057448 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9317 05:56:44.062389 in-header: 03 fc 00 00 01 00 00 00
9318 05:56:44.065187 in-data: 00
9319 05:56:44.068675 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9320 05:56:44.074531 in-header: 03 fd 00 00 00 00 00 00
9321 05:56:44.077412 in-data:
9322 05:56:44.080983 [SSUSB] Setting up USB HOST controller...
9323 05:56:44.084016 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9324 05:56:44.087639 [SSUSB] phy power-on done.
9325 05:56:44.090538 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9326 05:56:44.097528 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9327 05:56:44.101172 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9328 05:56:44.107598 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9329 05:56:44.113768 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9330 05:56:44.120468 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9331 05:56:44.126925 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9332 05:56:44.133874 read SPI 0x705bc 0x1f6a: 926 us, 8684 KB/s, 69.472 Mbps
9333 05:56:44.136999 SPM: binary array size = 0x9dc
9334 05:56:44.140527 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9335 05:56:44.146814 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9336 05:56:44.153775 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9337 05:56:44.160353 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9338 05:56:44.163912 configure_display: Starting display init
9339 05:56:44.197738 anx7625_power_on_init: Init interface.
9340 05:56:44.200612 anx7625_disable_pd_protocol: Disabled PD feature.
9341 05:56:44.204282 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9342 05:56:44.232060 anx7625_start_dp_work: Secure OCM version=00
9343 05:56:44.235347 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9344 05:56:44.250228 sp_tx_get_edid_block: EDID Block = 1
9345 05:56:44.352463 Extracted contents:
9346 05:56:44.355934 header: 00 ff ff ff ff ff ff 00
9347 05:56:44.359130 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9348 05:56:44.362448 version: 01 04
9349 05:56:44.365969 basic params: 95 1f 11 78 0a
9350 05:56:44.368942 chroma info: 76 90 94 55 54 90 27 21 50 54
9351 05:56:44.372616 established: 00 00 00
9352 05:56:44.378890 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9353 05:56:44.382225 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9354 05:56:44.389097 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9355 05:56:44.395505 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9356 05:56:44.402031 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9357 05:56:44.405604 extensions: 00
9358 05:56:44.405686 checksum: fb
9359 05:56:44.405752
9360 05:56:44.409045 Manufacturer: IVO Model 57d Serial Number 0
9361 05:56:44.412030 Made week 0 of 2020
9362 05:56:44.412111 EDID version: 1.4
9363 05:56:44.415481 Digital display
9364 05:56:44.418937 6 bits per primary color channel
9365 05:56:44.419020 DisplayPort interface
9366 05:56:44.422395 Maximum image size: 31 cm x 17 cm
9367 05:56:44.425598 Gamma: 220%
9368 05:56:44.425679 Check DPMS levels
9369 05:56:44.429028 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9370 05:56:44.435326 First detailed timing is preferred timing
9371 05:56:44.435481 Established timings supported:
9372 05:56:44.438877 Standard timings supported:
9373 05:56:44.441747 Detailed timings
9374 05:56:44.444902 Hex of detail: 383680a07038204018303c0035ae10000019
9375 05:56:44.451622 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9376 05:56:44.455279 0780 0798 07c8 0820 hborder 0
9377 05:56:44.458198 0438 043b 0447 0458 vborder 0
9378 05:56:44.461703 -hsync -vsync
9379 05:56:44.461805 Did detailed timing
9380 05:56:44.468145 Hex of detail: 000000000000000000000000000000000000
9381 05:56:44.471479 Manufacturer-specified data, tag 0
9382 05:56:44.474655 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9383 05:56:44.478312 ASCII string: InfoVision
9384 05:56:44.481381 Hex of detail: 000000fe00523134304e574635205248200a
9385 05:56:44.484904 ASCII string: R140NWF5 RH
9386 05:56:44.484986 Checksum
9387 05:56:44.488154 Checksum: 0xfb (valid)
9388 05:56:44.491376 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9389 05:56:44.494480 DSI data_rate: 832800000 bps
9390 05:56:44.500978 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9391 05:56:44.504432 anx7625_parse_edid: pixelclock(138800).
9392 05:56:44.508082 hactive(1920), hsync(48), hfp(24), hbp(88)
9393 05:56:44.510958 vactive(1080), vsync(12), vfp(3), vbp(17)
9394 05:56:44.514580 anx7625_dsi_config: config dsi.
9395 05:56:44.520956 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9396 05:56:44.534990 anx7625_dsi_config: success to config DSI
9397 05:56:44.537622 anx7625_dp_start: MIPI phy setup OK.
9398 05:56:44.541172 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9399 05:56:44.544289 mtk_ddp_mode_set invalid vrefresh 60
9400 05:56:44.547709 main_disp_path_setup
9401 05:56:44.547792 ovl_layer_smi_id_en
9402 05:56:44.551119 ovl_layer_smi_id_en
9403 05:56:44.551202 ccorr_config
9404 05:56:44.551267 aal_config
9405 05:56:44.554324 gamma_config
9406 05:56:44.554406 postmask_config
9407 05:56:44.557922 dither_config
9408 05:56:44.560862 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9409 05:56:44.567516 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9410 05:56:44.571105 Root Device init finished in 555 msecs
9411 05:56:44.574521 CPU_CLUSTER: 0 init
9412 05:56:44.580931 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9413 05:56:44.587218 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9414 05:56:44.587330 APU_MBOX 0x190000b0 = 0x10001
9415 05:56:44.590758 APU_MBOX 0x190001b0 = 0x10001
9416 05:56:44.593992 APU_MBOX 0x190005b0 = 0x10001
9417 05:56:44.597203 APU_MBOX 0x190006b0 = 0x10001
9418 05:56:44.604101 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9419 05:56:44.613384 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9420 05:56:44.626353 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9421 05:56:44.632806 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9422 05:56:44.644028 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9423 05:56:44.653597 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9424 05:56:44.656905 CPU_CLUSTER: 0 init finished in 81 msecs
9425 05:56:44.659940 Devices initialized
9426 05:56:44.663105 Show all devs... After init.
9427 05:56:44.663213 Root Device: enabled 1
9428 05:56:44.666773 CPU_CLUSTER: 0: enabled 1
9429 05:56:44.669834 CPU: 00: enabled 1
9430 05:56:44.673284 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9431 05:56:44.676289 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9432 05:56:44.679637 ELOG: NV offset 0x57f000 size 0x1000
9433 05:56:44.686831 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9434 05:56:44.693230 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9435 05:56:44.696177 ELOG: Event(17) added with size 13 at 2023-12-25 05:56:44 UTC
9436 05:56:44.702799 out: cmd=0x121: 03 db 21 01 00 00 00 00
9437 05:56:44.706294 in-header: 03 61 00 00 2c 00 00 00
9438 05:56:44.716165 in-data: fe 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9439 05:56:44.722743 ELOG: Event(A1) added with size 10 at 2023-12-25 05:56:45 UTC
9440 05:56:44.729226 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9441 05:56:44.735792 ELOG: Event(A0) added with size 9 at 2023-12-25 05:56:45 UTC
9442 05:56:44.739122 elog_add_boot_reason: Logged dev mode boot
9443 05:56:44.745604 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9444 05:56:44.745718 Finalize devices...
9445 05:56:44.749192 Devices finalized
9446 05:56:44.752621 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9447 05:56:44.755575 Writing coreboot table at 0xffe64000
9448 05:56:44.759060 0. 000000000010a000-0000000000113fff: RAMSTAGE
9449 05:56:44.765767 1. 0000000040000000-00000000400fffff: RAM
9450 05:56:44.769050 2. 0000000040100000-000000004032afff: RAMSTAGE
9451 05:56:44.772570 3. 000000004032b000-00000000545fffff: RAM
9452 05:56:44.775701 4. 0000000054600000-000000005465ffff: BL31
9453 05:56:44.778816 5. 0000000054660000-00000000ffe63fff: RAM
9454 05:56:44.785826 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9455 05:56:44.788821 7. 0000000100000000-000000023fffffff: RAM
9456 05:56:44.792266 Passing 5 GPIOs to payload:
9457 05:56:44.795814 NAME | PORT | POLARITY | VALUE
9458 05:56:44.802440 EC in RW | 0x000000aa | low | undefined
9459 05:56:44.805387 EC interrupt | 0x00000005 | low | undefined
9460 05:56:44.809071 TPM interrupt | 0x000000ab | high | undefined
9461 05:56:44.815561 SD card detect | 0x00000011 | high | undefined
9462 05:56:44.818605 speaker enable | 0x00000093 | high | undefined
9463 05:56:44.822130 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9464 05:56:44.825402 in-header: 03 f9 00 00 02 00 00 00
9465 05:56:44.828531 in-data: 02 00
9466 05:56:44.832008 ADC[4]: Raw value=894081 ID=7
9467 05:56:44.832107 ADC[3]: Raw value=213070 ID=1
9468 05:56:44.834926 RAM Code: 0x71
9469 05:56:44.838449 ADC[6]: Raw value=74722 ID=0
9470 05:56:44.838541 ADC[5]: Raw value=211960 ID=1
9471 05:56:44.841876 SKU Code: 0x1
9472 05:56:44.848674 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4d57
9473 05:56:44.848790 coreboot table: 964 bytes.
9474 05:56:44.851385 IMD ROOT 0. 0xfffff000 0x00001000
9475 05:56:44.855031 IMD SMALL 1. 0xffffe000 0x00001000
9476 05:56:44.858445 RO MCACHE 2. 0xffffc000 0x00001104
9477 05:56:44.861493 CONSOLE 3. 0xfff7c000 0x00080000
9478 05:56:44.865090 FMAP 4. 0xfff7b000 0x00000452
9479 05:56:44.868074 TIME STAMP 5. 0xfff7a000 0x00000910
9480 05:56:44.871603 VBOOT WORK 6. 0xfff66000 0x00014000
9481 05:56:44.874694 RAMOOPS 7. 0xffe66000 0x00100000
9482 05:56:44.878029 COREBOOT 8. 0xffe64000 0x00002000
9483 05:56:44.881412 IMD small region:
9484 05:56:44.884489 IMD ROOT 0. 0xffffec00 0x00000400
9485 05:56:44.888257 VPD 1. 0xffffeb80 0x0000006c
9486 05:56:44.891190 MMC STATUS 2. 0xffffeb60 0x00000004
9487 05:56:44.894871 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9488 05:56:44.897666 Probing TPM: done!
9489 05:56:44.901373 Connected to device vid:did:rid of 1ae0:0028:00
9490 05:56:44.912480 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9491 05:56:44.916004 Initialized TPM device CR50 revision 0
9492 05:56:44.919452 Checking cr50 for pending updates
9493 05:56:44.923087 Reading cr50 TPM mode
9494 05:56:44.932038 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9495 05:56:44.938392 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9496 05:56:44.978683 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9497 05:56:44.982065 Checking segment from ROM address 0x40100000
9498 05:56:44.985619 Checking segment from ROM address 0x4010001c
9499 05:56:44.992280 Loading segment from ROM address 0x40100000
9500 05:56:44.992398 code (compression=0)
9501 05:56:45.001735 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9502 05:56:45.008711 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9503 05:56:45.008822 it's not compressed!
9504 05:56:45.015571 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9505 05:56:45.018353 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9506 05:56:45.038867 Loading segment from ROM address 0x4010001c
9507 05:56:45.038978 Entry Point 0x80000000
9508 05:56:45.042500 Loaded segments
9509 05:56:45.045413 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9510 05:56:45.052241 Jumping to boot code at 0x80000000(0xffe64000)
9511 05:56:45.058940 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9512 05:56:45.065483 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9513 05:56:45.073269 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9514 05:56:45.076771 Checking segment from ROM address 0x40100000
9515 05:56:45.080206 Checking segment from ROM address 0x4010001c
9516 05:56:45.086962 Loading segment from ROM address 0x40100000
9517 05:56:45.087068 code (compression=1)
9518 05:56:45.093956 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9519 05:56:45.103366 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9520 05:56:45.103453 using LZMA
9521 05:56:45.112092 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9522 05:56:45.118171 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9523 05:56:45.121962 Loading segment from ROM address 0x4010001c
9524 05:56:45.122074 Entry Point 0x54601000
9525 05:56:45.124907 Loaded segments
9526 05:56:45.128601 NOTICE: MT8192 bl31_setup
9527 05:56:45.135432 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9528 05:56:45.138532 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9529 05:56:45.142098 WARNING: region 0:
9530 05:56:45.145556 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9531 05:56:45.145672 WARNING: region 1:
9532 05:56:45.152103 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9533 05:56:45.155524 WARNING: region 2:
9534 05:56:45.158916 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9535 05:56:45.161954 WARNING: region 3:
9536 05:56:45.165105 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9537 05:56:45.168414 WARNING: region 4:
9538 05:56:45.175061 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9539 05:56:45.175171 WARNING: region 5:
9540 05:56:45.178472 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 05:56:45.182091 WARNING: region 6:
9542 05:56:45.185595 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 05:56:45.188383 WARNING: region 7:
9544 05:56:45.191843 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9545 05:56:45.198443 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9546 05:56:45.201843 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9547 05:56:45.205054 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9548 05:56:45.211694 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9549 05:56:45.215404 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9550 05:56:45.218317 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9551 05:56:45.225143 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9552 05:56:45.228390 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9553 05:56:45.235118 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9554 05:56:45.238559 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9555 05:56:45.242169 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9556 05:56:45.248382 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9557 05:56:45.251983 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9558 05:56:45.254999 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9559 05:56:45.262247 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9560 05:56:45.265136 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9561 05:56:45.271693 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9562 05:56:45.274976 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9563 05:56:45.278501 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9564 05:56:45.285541 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9565 05:56:45.288234 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9566 05:56:45.291859 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9567 05:56:45.298808 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9568 05:56:45.301816 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9569 05:56:45.308316 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9570 05:56:45.311824 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9571 05:56:45.314889 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9572 05:56:45.321874 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9573 05:56:45.325207 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9574 05:56:45.331958 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9575 05:56:45.335053 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9576 05:56:45.338690 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9577 05:56:45.345323 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9578 05:56:45.348404 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9579 05:56:45.351844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9580 05:56:45.354810 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9581 05:56:45.361888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9582 05:56:45.364954 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9583 05:56:45.368358 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9584 05:56:45.371932 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9585 05:56:45.378599 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9586 05:56:45.381967 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9587 05:56:45.385142 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9588 05:56:45.388692 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9589 05:56:45.395217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9590 05:56:45.398338 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9591 05:56:45.401897 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9592 05:56:45.404941 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9593 05:56:45.411949 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9594 05:56:45.415033 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9595 05:56:45.421938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9596 05:56:45.425250 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9597 05:56:45.428471 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9598 05:56:45.435401 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9599 05:56:45.438804 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9600 05:56:45.445156 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9601 05:56:45.448374 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9602 05:56:45.455111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9603 05:56:45.458415 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9604 05:56:45.461958 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9605 05:56:45.468405 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9606 05:56:45.471908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9607 05:56:45.478361 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9608 05:56:45.481883 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9609 05:56:45.488514 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9610 05:56:45.491825 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9611 05:56:45.498342 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9612 05:56:45.501950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9613 05:56:45.505451 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9614 05:56:45.512018 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9615 05:56:45.515010 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9616 05:56:45.522086 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9617 05:56:45.525075 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9618 05:56:45.528497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9619 05:56:45.535312 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9620 05:56:45.538481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9621 05:56:45.545060 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9622 05:56:45.548437 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9623 05:56:45.555335 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9624 05:56:45.558473 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9625 05:56:45.565096 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9626 05:56:45.568582 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9627 05:56:45.571810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9628 05:56:45.578328 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9629 05:56:45.581935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9630 05:56:45.588725 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9631 05:56:45.592138 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9632 05:56:45.598448 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9633 05:56:45.601902 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9634 05:56:45.605039 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9635 05:56:45.611951 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9636 05:56:45.614928 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9637 05:56:45.622078 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9638 05:56:45.625037 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9639 05:56:45.632068 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9640 05:56:45.635011 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9641 05:56:45.638520 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9642 05:56:45.645047 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9643 05:56:45.648529 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9644 05:56:45.652151 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9645 05:56:45.655214 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9646 05:56:45.661924 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9647 05:56:45.665242 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9648 05:56:45.671615 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9649 05:56:45.675118 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9650 05:56:45.678133 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9651 05:56:45.685124 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9652 05:56:45.688033 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9653 05:56:45.695099 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9654 05:56:45.698394 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9655 05:56:45.701940 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9656 05:56:45.708315 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9657 05:56:45.711579 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9658 05:56:45.718059 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9659 05:56:45.721580 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9660 05:56:45.725183 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9661 05:56:45.728089 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9662 05:56:45.735246 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9663 05:56:45.738299 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9664 05:56:45.741389 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9665 05:56:45.748251 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9666 05:56:45.751496 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9667 05:56:45.755254 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9668 05:56:45.758278 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9669 05:56:45.764625 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9670 05:56:45.768180 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9671 05:56:45.774951 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9672 05:56:45.778424 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9673 05:56:45.781265 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9674 05:56:45.787853 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9675 05:56:45.791492 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9676 05:56:45.798072 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9677 05:56:45.801417 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9678 05:56:45.805028 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9679 05:56:45.810938 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9680 05:56:45.814436 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9681 05:56:45.821214 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9682 05:56:45.824526 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9683 05:56:45.827976 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9684 05:56:45.834463 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9685 05:56:45.837879 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9686 05:56:45.844637 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9687 05:56:45.847556 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9688 05:56:45.851126 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9689 05:56:45.857582 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9690 05:56:45.860779 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9691 05:56:45.864242 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9692 05:56:45.870836 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9693 05:56:45.874335 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9694 05:56:45.880624 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9695 05:56:45.884252 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9696 05:56:45.887136 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9697 05:56:45.894066 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9698 05:56:45.897366 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9699 05:56:45.904250 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9700 05:56:45.907366 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9701 05:56:45.910896 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9702 05:56:45.917433 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9703 05:56:45.920511 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9704 05:56:45.927492 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9705 05:56:45.930904 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9706 05:56:45.933717 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9707 05:56:45.940413 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9708 05:56:45.944033 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9709 05:56:45.950625 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9710 05:56:45.953717 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9711 05:56:45.957158 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9712 05:56:45.963869 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9713 05:56:45.967046 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9714 05:56:45.970209 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9715 05:56:45.976991 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9716 05:56:45.980477 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9717 05:56:45.986684 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9718 05:56:45.990339 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9719 05:56:45.993776 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9720 05:56:46.000299 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9721 05:56:46.003839 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9722 05:56:46.010361 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9723 05:56:46.013467 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9724 05:56:46.017065 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9725 05:56:46.023546 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9726 05:56:46.026589 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9727 05:56:46.033374 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9728 05:56:46.036887 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9729 05:56:46.039869 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9730 05:56:46.046598 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9731 05:56:46.050021 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9732 05:56:46.056759 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9733 05:56:46.059758 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9734 05:56:46.063299 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9735 05:56:46.069840 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9736 05:56:46.073162 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9737 05:56:46.079547 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9738 05:56:46.083036 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9739 05:56:46.086598 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9740 05:56:46.093366 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9741 05:56:46.096372 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9742 05:56:46.103329 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9743 05:56:46.106256 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9744 05:56:46.113344 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9745 05:56:46.116222 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9746 05:56:46.119408 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9747 05:56:46.126340 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9748 05:56:46.129659 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9749 05:56:46.136254 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9750 05:56:46.139261 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9751 05:56:46.145966 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9752 05:56:46.149253 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9753 05:56:46.152526 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9754 05:56:46.159614 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9755 05:56:46.162522 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9756 05:56:46.169130 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9757 05:56:46.172701 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9758 05:56:46.179091 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9759 05:56:46.182719 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9760 05:56:46.185881 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9761 05:56:46.192694 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9762 05:56:46.195521 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9763 05:56:46.202065 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9764 05:56:46.205489 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9765 05:56:46.208541 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9766 05:56:46.215231 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9767 05:56:46.218887 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9768 05:56:46.225621 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9769 05:56:46.228456 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9770 05:56:46.235497 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9771 05:56:46.238404 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9772 05:56:46.241959 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9773 05:56:46.248333 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9774 05:56:46.252013 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9775 05:56:46.255143 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9776 05:56:46.258167 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9777 05:56:46.265140 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9778 05:56:46.268397 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9779 05:56:46.272059 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9780 05:56:46.278560 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9781 05:56:46.281520 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9782 05:56:46.287950 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9783 05:56:46.291303 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9784 05:56:46.294905 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9785 05:56:46.301260 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9786 05:56:46.304725 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9787 05:56:46.307944 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9788 05:56:46.314971 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9789 05:56:46.317922 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9790 05:56:46.321496 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9791 05:56:46.328001 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9792 05:56:46.331341 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9793 05:56:46.334312 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9794 05:56:46.341297 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9795 05:56:46.344322 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9796 05:56:46.350945 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9797 05:56:46.354496 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9798 05:56:46.357796 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9799 05:56:46.364310 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9800 05:56:46.367861 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9801 05:56:46.374312 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9802 05:56:46.377552 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9803 05:56:46.381235 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9804 05:56:46.387287 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9805 05:56:46.390981 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9806 05:56:46.393843 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9807 05:56:46.400934 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9808 05:56:46.403948 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9809 05:56:46.407383 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9810 05:56:46.413669 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9811 05:56:46.417198 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9812 05:56:46.423892 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9813 05:56:46.426921 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9814 05:56:46.430465 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9815 05:56:46.433898 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9816 05:56:46.440301 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9817 05:56:46.443704 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9818 05:56:46.447209 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9819 05:56:46.450202 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9820 05:56:46.457131 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9821 05:56:46.460094 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9822 05:56:46.463596 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9823 05:56:46.467120 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9824 05:56:46.470137 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9825 05:56:46.477219 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9826 05:56:46.480010 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9827 05:56:46.486852 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9828 05:56:46.490122 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9829 05:56:46.493906 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9830 05:56:46.499986 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9831 05:56:46.503670 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9832 05:56:46.509914 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9833 05:56:46.513368 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9834 05:56:46.516669 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9835 05:56:46.523521 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9836 05:56:46.526513 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9837 05:56:46.532968 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9838 05:56:46.536484 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9839 05:56:46.539941 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9840 05:56:46.546808 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9841 05:56:46.550235 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9842 05:56:46.556801 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9843 05:56:46.559921 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9844 05:56:46.563299 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9845 05:56:46.570157 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9846 05:56:46.573005 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9847 05:56:46.579907 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9848 05:56:46.583102 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9849 05:56:46.589414 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9850 05:56:46.592906 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9851 05:56:46.596255 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9852 05:56:46.603025 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9853 05:56:46.606448 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9854 05:56:46.613096 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9855 05:56:46.615965 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9856 05:56:46.622887 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9857 05:56:46.626086 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9858 05:56:46.629407 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9859 05:56:46.636012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9860 05:56:46.639645 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9861 05:56:46.646148 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9862 05:56:46.649564 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9863 05:56:46.652988 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9864 05:56:46.659596 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9865 05:56:46.662491 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9866 05:56:46.669106 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9867 05:56:46.672448 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9868 05:56:46.675935 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9869 05:56:46.682545 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9870 05:56:46.685387 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9871 05:56:46.692404 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9872 05:56:46.696051 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9873 05:56:46.702426 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9874 05:56:46.705654 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9875 05:56:46.708973 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9876 05:56:46.715415 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9877 05:56:46.718930 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9878 05:56:46.725439 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9879 05:56:46.728678 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9880 05:56:46.731960 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9881 05:56:46.738498 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9882 05:56:46.742075 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9883 05:56:46.748362 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9884 05:56:46.751672 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9885 05:56:46.755175 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9886 05:56:46.761584 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9887 05:56:46.765040 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9888 05:56:46.771624 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9889 05:56:46.775044 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9890 05:56:46.778452 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9891 05:56:46.784888 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9892 05:56:46.787852 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9893 05:56:46.794811 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9894 05:56:46.798050 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9895 05:56:46.804394 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9896 05:56:46.807814 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9897 05:56:46.814810 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9898 05:56:46.818157 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9899 05:56:46.821035 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9900 05:56:46.827643 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9901 05:56:46.831027 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9902 05:56:46.837204 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9903 05:56:46.840550 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9904 05:56:46.847477 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9905 05:56:46.850858 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9906 05:56:46.853854 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9907 05:56:46.860825 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9908 05:56:46.864356 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9909 05:56:46.870919 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9910 05:56:46.873866 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9911 05:56:46.880541 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9912 05:56:46.883984 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9913 05:56:46.890454 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9914 05:56:46.894082 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9915 05:56:46.896900 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9916 05:56:46.903820 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9917 05:56:46.906827 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9918 05:56:46.913278 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9919 05:56:46.916819 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9920 05:56:46.923372 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9921 05:56:46.926950 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9922 05:56:46.929895 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9923 05:56:46.936718 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9924 05:56:46.939951 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9925 05:56:46.946348 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9926 05:56:46.949774 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9927 05:56:46.956451 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9928 05:56:46.959931 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9929 05:56:46.966122 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9930 05:56:46.969689 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9931 05:56:46.972816 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9932 05:56:46.979836 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9933 05:56:46.982806 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9934 05:56:46.989404 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9935 05:56:46.992982 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9936 05:56:46.999416 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9937 05:56:47.002827 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9938 05:56:47.009151 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9939 05:56:47.012664 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9940 05:56:47.016191 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9941 05:56:47.022466 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9942 05:56:47.025852 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9943 05:56:47.032695 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9944 05:56:47.035426 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9945 05:56:47.042459 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9946 05:56:47.045730 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9947 05:56:47.048947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9948 05:56:47.055320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9949 05:56:47.058561 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9950 05:56:47.065374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9951 05:56:47.068845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9952 05:56:47.075356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9953 05:56:47.078856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9954 05:56:47.085242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9955 05:56:47.088855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9956 05:56:47.095083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9957 05:56:47.098584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9958 05:56:47.104876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9959 05:56:47.108388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9960 05:56:47.114873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9961 05:56:47.118386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9962 05:56:47.124980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9963 05:56:47.128109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9964 05:56:47.134923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9965 05:56:47.138350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9966 05:56:47.141719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9967 05:56:47.148449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9968 05:56:47.151917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9969 05:56:47.158125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9970 05:56:47.164995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9971 05:56:47.167973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9972 05:56:47.174799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9973 05:56:47.177770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9974 05:56:47.184277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9975 05:56:47.187609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9976 05:56:47.194684 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9977 05:56:47.197627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9978 05:56:47.204108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9979 05:56:47.207705 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9980 05:56:47.211165 INFO: [APUAPC] vio 0
9981 05:56:47.214170 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9982 05:56:47.217673 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9983 05:56:47.221230 INFO: [APUAPC] D0_APC_0: 0x400510
9984 05:56:47.224172 INFO: [APUAPC] D0_APC_1: 0x0
9985 05:56:47.227250 INFO: [APUAPC] D0_APC_2: 0x1540
9986 05:56:47.230792 INFO: [APUAPC] D0_APC_3: 0x0
9987 05:56:47.233826 INFO: [APUAPC] D1_APC_0: 0xffffffff
9988 05:56:47.237424 INFO: [APUAPC] D1_APC_1: 0xffffffff
9989 05:56:47.240788 INFO: [APUAPC] D1_APC_2: 0x3fffff
9990 05:56:47.244132 INFO: [APUAPC] D1_APC_3: 0x0
9991 05:56:47.247447 INFO: [APUAPC] D2_APC_0: 0xffffffff
9992 05:56:47.250840 INFO: [APUAPC] D2_APC_1: 0xffffffff
9993 05:56:47.254089 INFO: [APUAPC] D2_APC_2: 0x3fffff
9994 05:56:47.257413 INFO: [APUAPC] D2_APC_3: 0x0
9995 05:56:47.260935 INFO: [APUAPC] D3_APC_0: 0xffffffff
9996 05:56:47.263991 INFO: [APUAPC] D3_APC_1: 0xffffffff
9997 05:56:47.267136 INFO: [APUAPC] D3_APC_2: 0x3fffff
9998 05:56:47.270609 INFO: [APUAPC] D3_APC_3: 0x0
9999 05:56:47.273910 INFO: [APUAPC] D4_APC_0: 0xffffffff
10000 05:56:47.277052 INFO: [APUAPC] D4_APC_1: 0xffffffff
10001 05:56:47.280661 INFO: [APUAPC] D4_APC_2: 0x3fffff
10002 05:56:47.283639 INFO: [APUAPC] D4_APC_3: 0x0
10003 05:56:47.287222 INFO: [APUAPC] D5_APC_0: 0xffffffff
10004 05:56:47.290664 INFO: [APUAPC] D5_APC_1: 0xffffffff
10005 05:56:47.294288 INFO: [APUAPC] D5_APC_2: 0x3fffff
10006 05:56:47.297360 INFO: [APUAPC] D5_APC_3: 0x0
10007 05:56:47.300598 INFO: [APUAPC] D6_APC_0: 0xffffffff
10008 05:56:47.303565 INFO: [APUAPC] D6_APC_1: 0xffffffff
10009 05:56:47.307256 INFO: [APUAPC] D6_APC_2: 0x3fffff
10010 05:56:47.310123 INFO: [APUAPC] D6_APC_3: 0x0
10011 05:56:47.313554 INFO: [APUAPC] D7_APC_0: 0xffffffff
10012 05:56:47.317001 INFO: [APUAPC] D7_APC_1: 0xffffffff
10013 05:56:47.320568 INFO: [APUAPC] D7_APC_2: 0x3fffff
10014 05:56:47.323459 INFO: [APUAPC] D7_APC_3: 0x0
10015 05:56:47.326956 INFO: [APUAPC] D8_APC_0: 0xffffffff
10016 05:56:47.330574 INFO: [APUAPC] D8_APC_1: 0xffffffff
10017 05:56:47.333503 INFO: [APUAPC] D8_APC_2: 0x3fffff
10018 05:56:47.336972 INFO: [APUAPC] D8_APC_3: 0x0
10019 05:56:47.340044 INFO: [APUAPC] D9_APC_0: 0xffffffff
10020 05:56:47.343430 INFO: [APUAPC] D9_APC_1: 0xffffffff
10021 05:56:47.346909 INFO: [APUAPC] D9_APC_2: 0x3fffff
10022 05:56:47.347022 INFO: [APUAPC] D9_APC_3: 0x0
10023 05:56:47.350426 INFO: [APUAPC] D10_APC_0: 0xffffffff
10024 05:56:47.356637 INFO: [APUAPC] D10_APC_1: 0xffffffff
10025 05:56:47.360181 INFO: [APUAPC] D10_APC_2: 0x3fffff
10026 05:56:47.360264 INFO: [APUAPC] D10_APC_3: 0x0
10027 05:56:47.366875 INFO: [APUAPC] D11_APC_0: 0xffffffff
10028 05:56:47.370383 INFO: [APUAPC] D11_APC_1: 0xffffffff
10029 05:56:47.373639 INFO: [APUAPC] D11_APC_2: 0x3fffff
10030 05:56:47.373722 INFO: [APUAPC] D11_APC_3: 0x0
10031 05:56:47.379936 INFO: [APUAPC] D12_APC_0: 0xffffffff
10032 05:56:47.383126 INFO: [APUAPC] D12_APC_1: 0xffffffff
10033 05:56:47.386498 INFO: [APUAPC] D12_APC_2: 0x3fffff
10034 05:56:47.389816 INFO: [APUAPC] D12_APC_3: 0x0
10035 05:56:47.393121 INFO: [APUAPC] D13_APC_0: 0xffffffff
10036 05:56:47.396730 INFO: [APUAPC] D13_APC_1: 0xffffffff
10037 05:56:47.399601 INFO: [APUAPC] D13_APC_2: 0x3fffff
10038 05:56:47.402979 INFO: [APUAPC] D13_APC_3: 0x0
10039 05:56:47.406439 INFO: [APUAPC] D14_APC_0: 0xffffffff
10040 05:56:47.409590 INFO: [APUAPC] D14_APC_1: 0xffffffff
10041 05:56:47.412984 INFO: [APUAPC] D14_APC_2: 0x3fffff
10042 05:56:47.416548 INFO: [APUAPC] D14_APC_3: 0x0
10043 05:56:47.419687 INFO: [APUAPC] D15_APC_0: 0xffffffff
10044 05:56:47.422673 INFO: [APUAPC] D15_APC_1: 0xffffffff
10045 05:56:47.426269 INFO: [APUAPC] D15_APC_2: 0x3fffff
10046 05:56:47.429228 INFO: [APUAPC] D15_APC_3: 0x0
10047 05:56:47.429308 INFO: [APUAPC] APC_CON: 0x4
10048 05:56:47.432847 INFO: [NOCDAPC] D0_APC_0: 0x0
10049 05:56:47.436336 INFO: [NOCDAPC] D0_APC_1: 0x0
10050 05:56:47.439157 INFO: [NOCDAPC] D1_APC_0: 0x0
10051 05:56:47.442678 INFO: [NOCDAPC] D1_APC_1: 0xfff
10052 05:56:47.446193 INFO: [NOCDAPC] D2_APC_0: 0x0
10053 05:56:47.449090 INFO: [NOCDAPC] D2_APC_1: 0xfff
10054 05:56:47.452514 INFO: [NOCDAPC] D3_APC_0: 0x0
10055 05:56:47.456063 INFO: [NOCDAPC] D3_APC_1: 0xfff
10056 05:56:47.459490 INFO: [NOCDAPC] D4_APC_0: 0x0
10057 05:56:47.462776 INFO: [NOCDAPC] D4_APC_1: 0xfff
10058 05:56:47.462854 INFO: [NOCDAPC] D5_APC_0: 0x0
10059 05:56:47.465770 INFO: [NOCDAPC] D5_APC_1: 0xfff
10060 05:56:47.469079 INFO: [NOCDAPC] D6_APC_0: 0x0
10061 05:56:47.472497 INFO: [NOCDAPC] D6_APC_1: 0xfff
10062 05:56:47.476051 INFO: [NOCDAPC] D7_APC_0: 0x0
10063 05:56:47.479021 INFO: [NOCDAPC] D7_APC_1: 0xfff
10064 05:56:47.482858 INFO: [NOCDAPC] D8_APC_0: 0x0
10065 05:56:47.485708 INFO: [NOCDAPC] D8_APC_1: 0xfff
10066 05:56:47.489324 INFO: [NOCDAPC] D9_APC_0: 0x0
10067 05:56:47.492670 INFO: [NOCDAPC] D9_APC_1: 0xfff
10068 05:56:47.495862 INFO: [NOCDAPC] D10_APC_0: 0x0
10069 05:56:47.499064 INFO: [NOCDAPC] D10_APC_1: 0xfff
10070 05:56:47.499176 INFO: [NOCDAPC] D11_APC_0: 0x0
10071 05:56:47.502203 INFO: [NOCDAPC] D11_APC_1: 0xfff
10072 05:56:47.505876 INFO: [NOCDAPC] D12_APC_0: 0x0
10073 05:56:47.508961 INFO: [NOCDAPC] D12_APC_1: 0xfff
10074 05:56:47.512103 INFO: [NOCDAPC] D13_APC_0: 0x0
10075 05:56:47.515942 INFO: [NOCDAPC] D13_APC_1: 0xfff
10076 05:56:47.518832 INFO: [NOCDAPC] D14_APC_0: 0x0
10077 05:56:47.522130 INFO: [NOCDAPC] D14_APC_1: 0xfff
10078 05:56:47.525432 INFO: [NOCDAPC] D15_APC_0: 0x0
10079 05:56:47.528998 INFO: [NOCDAPC] D15_APC_1: 0xfff
10080 05:56:47.531968 INFO: [NOCDAPC] APC_CON: 0x4
10081 05:56:47.535501 INFO: [APUAPC] set_apusys_apc done
10082 05:56:47.538983 INFO: [DEVAPC] devapc_init done
10083 05:56:47.541965 INFO: GICv3 without legacy support detected.
10084 05:56:47.545575 INFO: ARM GICv3 driver initialized in EL3
10085 05:56:47.548551 INFO: Maximum SPI INTID supported: 639
10086 05:56:47.555441 INFO: BL31: Initializing runtime services
10087 05:56:47.558404 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10088 05:56:47.561966 INFO: SPM: enable CPC mode
10089 05:56:47.568248 INFO: mcdi ready for mcusys-off-idle and system suspend
10090 05:56:47.571866 INFO: BL31: Preparing for EL3 exit to normal world
10091 05:56:47.574745 INFO: Entry point address = 0x80000000
10092 05:56:47.577982 INFO: SPSR = 0x8
10093 05:56:47.583784
10094 05:56:47.583867
10095 05:56:47.583931
10096 05:56:47.586679 Starting depthcharge on Spherion...
10097 05:56:47.586761
10098 05:56:47.586826 Wipe memory regions:
10099 05:56:47.586887
10100 05:56:47.587572 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10101 05:56:47.587671 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10102 05:56:47.587752 Setting prompt string to ['asurada:']
10103 05:56:47.587836 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10104 05:56:47.590373 [0x00000040000000, 0x00000054600000)
10105 05:56:47.712601
10106 05:56:47.712719 [0x00000054660000, 0x00000080000000)
10107 05:56:47.973073
10108 05:56:47.973209 [0x000000821a7280, 0x000000ffe64000)
10109 05:56:48.717944
10110 05:56:48.718078 [0x00000100000000, 0x00000240000000)
10111 05:56:50.608584
10112 05:56:50.611483 Initializing XHCI USB controller at 0x11200000.
10113 05:56:51.650864
10114 05:56:51.653854 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10115 05:56:51.653970
10116 05:56:51.654064
10117 05:56:51.654153
10118 05:56:51.654470 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10120 05:56:51.754814 asurada: tftpboot 192.168.201.1 12379453/tftp-deploy-ry1yvk2f/kernel/image.itb 12379453/tftp-deploy-ry1yvk2f/kernel/cmdline
10121 05:56:51.755003 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10122 05:56:51.755129 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10123 05:56:51.759156 tftpboot 192.168.201.1 12379453/tftp-deploy-ry1yvk2f/kernel/image.ittp-deploy-ry1yvk2f/kernel/cmdline
10124 05:56:51.759266
10125 05:56:51.759363 Waiting for link
10126 05:56:51.919494
10127 05:56:51.919624 R8152: Initializing
10128 05:56:51.919701
10129 05:56:51.922787 Version 6 (ocp_data = 5c30)
10130 05:56:51.922860
10131 05:56:51.925915 R8152: Done initializing
10132 05:56:51.926011
10133 05:56:51.926107 Adding net device
10134 05:56:53.924051
10135 05:56:53.924222 done.
10136 05:56:53.924323
10137 05:56:53.924418 MAC: 00:24:32:30:78:ff
10138 05:56:53.924514
10139 05:56:53.927574 Sending DHCP discover... done.
10140 05:56:53.927678
10141 05:56:57.272154 Waiting for reply... done.
10142 05:56:57.272313
10143 05:56:57.272423 Sending DHCP request... done.
10144 05:56:57.274878
10145 05:56:57.281108 Waiting for reply... done.
10146 05:56:57.281234
10147 05:56:57.281326 My ip is 192.168.201.21
10148 05:56:57.281424
10149 05:56:57.284796 The DHCP server ip is 192.168.201.1
10150 05:56:57.284897
10151 05:56:57.291290 TFTP server IP predefined by user: 192.168.201.1
10152 05:56:57.291400
10153 05:56:57.297804 Bootfile predefined by user: 12379453/tftp-deploy-ry1yvk2f/kernel/image.itb
10154 05:56:57.297912
10155 05:56:57.298009 Sending tftp read request... done.
10156 05:56:57.301280
10157 05:56:57.305341 Waiting for the transfer...
10158 05:56:57.305443
10159 05:56:57.849931 00000000 ################################################################
10160 05:56:57.850096
10161 05:56:58.381420 00080000 ################################################################
10162 05:56:58.381577
10163 05:56:58.902908 00100000 ################################################################
10164 05:56:58.903042
10165 05:56:59.424832 00180000 ################################################################
10166 05:56:59.424979
10167 05:56:59.948069 00200000 ################################################################
10168 05:56:59.948208
10169 05:57:00.493720 00280000 ################################################################
10170 05:57:00.493853
10171 05:57:01.032443 00300000 ################################################################
10172 05:57:01.032603
10173 05:57:01.565288 00380000 ################################################################
10174 05:57:01.565423
10175 05:57:02.102266 00400000 ################################################################
10176 05:57:02.102407
10177 05:57:02.645849 00480000 ################################################################
10178 05:57:02.645982
10179 05:57:03.200294 00500000 ################################################################
10180 05:57:03.200429
10181 05:57:03.759859 00580000 ################################################################
10182 05:57:03.759995
10183 05:57:04.295058 00600000 ################################################################
10184 05:57:04.295192
10185 05:57:04.849436 00680000 ################################################################
10186 05:57:04.849600
10187 05:57:05.402819 00700000 ################################################################
10188 05:57:05.402955
10189 05:57:05.946151 00780000 ################################################################
10190 05:57:05.946285
10191 05:57:06.487925 00800000 ################################################################
10192 05:57:06.488055
10193 05:57:07.019132 00880000 ################################################################
10194 05:57:07.019268
10195 05:57:07.568680 00900000 ################################################################
10196 05:57:07.568816
10197 05:57:08.137012 00980000 ################################################################
10198 05:57:08.137151
10199 05:57:08.698153 00a00000 ################################################################
10200 05:57:08.698313
10201 05:57:09.258628 00a80000 ################################################################
10202 05:57:09.258816
10203 05:57:09.795046 00b00000 ################################################################
10204 05:57:09.795221
10205 05:57:10.335111 00b80000 ################################################################
10206 05:57:10.335240
10207 05:57:10.890451 00c00000 ################################################################
10208 05:57:10.890595
10209 05:57:11.447882 00c80000 ################################################################
10210 05:57:11.448040
10211 05:57:11.977375 00d00000 ################################################################
10212 05:57:11.977586
10213 05:57:12.495241 00d80000 ################################################################
10214 05:57:12.495460
10215 05:57:13.026046 00e00000 ################################################################
10216 05:57:13.026211
10217 05:57:13.557830 00e80000 ################################################################
10218 05:57:13.557991
10219 05:57:14.090215 00f00000 ################################################################
10220 05:57:14.090348
10221 05:57:14.625036 00f80000 ################################################################
10222 05:57:14.625184
10223 05:57:15.159177 01000000 ################################################################
10224 05:57:15.159353
10225 05:57:15.713086 01080000 ################################################################
10226 05:57:15.713230
10227 05:57:16.274463 01100000 ################################################################
10228 05:57:16.274599
10229 05:57:16.838847 01180000 ################################################################
10230 05:57:16.838998
10231 05:57:17.410582 01200000 ################################################################
10232 05:57:17.410759
10233 05:57:17.957559 01280000 ################################################################
10234 05:57:17.957717
10235 05:57:18.516528 01300000 ################################################################
10236 05:57:18.516672
10237 05:57:19.074709 01380000 ################################################################
10238 05:57:19.074870
10239 05:57:19.619000 01400000 ################################################################
10240 05:57:19.619140
10241 05:57:20.160782 01480000 ################################################################
10242 05:57:20.160938
10243 05:57:20.686897 01500000 ################################################################
10244 05:57:20.687036
10245 05:57:21.220086 01580000 ################################################################
10246 05:57:21.220248
10247 05:57:21.758775 01600000 ################################################################
10248 05:57:21.758905
10249 05:57:22.308948 01680000 ################################################################
10250 05:57:22.309098
10251 05:57:22.846135 01700000 ################################################################
10252 05:57:22.846288
10253 05:57:23.376470 01780000 ################################################################
10254 05:57:23.376643
10255 05:57:23.913373 01800000 ################################################################
10256 05:57:23.913563
10257 05:57:24.458738 01880000 ################################################################
10258 05:57:24.458885
10259 05:57:25.044231 01900000 ################################################################
10260 05:57:25.044368
10261 05:57:25.615067 01980000 ################################################################
10262 05:57:25.615212
10263 05:57:26.171726 01a00000 ################################################################
10264 05:57:26.171899
10265 05:57:26.743283 01a80000 ################################################################
10266 05:57:26.743430
10267 05:57:27.318683 01b00000 ################################################################
10268 05:57:27.318824
10269 05:57:27.872069 01b80000 ############################################################# done.
10270 05:57:27.872223
10271 05:57:27.875188 The bootfile was 29330138 bytes long.
10272 05:57:27.875271
10273 05:57:27.875337 Sending tftp read request... done.
10274 05:57:27.878636
10275 05:57:27.878708 Waiting for the transfer...
10276 05:57:27.878769
10277 05:57:27.882026 00000000 # done.
10278 05:57:27.882103
10279 05:57:27.888465 Command line loaded dynamically from TFTP file: 12379453/tftp-deploy-ry1yvk2f/kernel/cmdline
10280 05:57:27.888541
10281 05:57:27.911784 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12379453/extract-nfsrootfs-4j3s6mu7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10282 05:57:27.911872
10283 05:57:27.911936 Loading FIT.
10284 05:57:27.911995
10285 05:57:27.915227 Image ramdisk-1 has 17798995 bytes.
10286 05:57:27.915302
10287 05:57:27.918390 Image fdt-1 has 47278 bytes.
10288 05:57:27.918476
10289 05:57:27.922011 Image kernel-1 has 11481830 bytes.
10290 05:57:27.922449
10291 05:57:27.932322 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10292 05:57:27.932838
10293 05:57:27.949322 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10294 05:57:27.949908
10295 05:57:27.951910 Choosing best match conf-1 for compat google,spherion-rev2.
10296 05:57:27.958010
10297 05:57:27.962225 Connected to device vid:did:rid of 1ae0:0028:00
10298 05:57:27.969178
10299 05:57:27.972765 tpm_get_response: command 0x17b, return code 0x0
10300 05:57:27.973278
10301 05:57:27.975881 ec_init: CrosEC protocol v3 supported (256, 248)
10302 05:57:27.979998
10303 05:57:27.982769 tpm_cleanup: add release locality here.
10304 05:57:27.983181
10305 05:57:27.983507 Shutting down all USB controllers.
10306 05:57:27.986837
10307 05:57:27.987352 Removing current net device
10308 05:57:27.987684
10309 05:57:27.993178 Exiting depthcharge with code 4 at timestamp: 69712181
10310 05:57:27.993728
10311 05:57:27.996529 LZMA decompressing kernel-1 to 0x821a6718
10312 05:57:27.997151
10313 05:57:27.999460 LZMA decompressing kernel-1 to 0x40000000
10314 05:57:29.436467
10315 05:57:29.436945 jumping to kernel
10316 05:57:29.438518 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10317 05:57:29.438996 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10318 05:57:29.439364 Setting prompt string to ['Linux version [0-9]']
10319 05:57:29.439714 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10320 05:57:29.440129 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10321 05:57:29.519636
10322 05:57:29.523024 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10323 05:57:29.526363 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10324 05:57:29.526827 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10325 05:57:29.527201 Setting prompt string to []
10326 05:57:29.527573 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10327 05:57:29.527925 Using line separator: #'\n'#
10328 05:57:29.528221 No login prompt set.
10329 05:57:29.528585 Parsing kernel messages
10330 05:57:29.528863 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10331 05:57:29.529354 [login-action] Waiting for messages, (timeout 00:03:43)
10332 05:57:29.545710 [ 0.000000] Linux version 6.1.67-cip12 (KernelCI@build-j59664-arm64-gcc-10-defconfig-arm64-chromebook-fgc24) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023
10333 05:57:29.549712 [ 0.000000] random: crng init done
10334 05:57:29.556071 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10335 05:57:29.558902 [ 0.000000] efi: UEFI not found.
10336 05:57:29.565435 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10337 05:57:29.572217 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10338 05:57:29.582141 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10339 05:57:29.592115 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10340 05:57:29.598827 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10341 05:57:29.605064 [ 0.000000] printk: bootconsole [mtk8250] enabled
10342 05:57:29.612320 [ 0.000000] NUMA: No NUMA configuration found
10343 05:57:29.618636 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10344 05:57:29.621735 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10345 05:57:29.625555 [ 0.000000] Zone ranges:
10346 05:57:29.631900 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10347 05:57:29.635301 [ 0.000000] DMA32 empty
10348 05:57:29.641551 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10349 05:57:29.645165 [ 0.000000] Movable zone start for each node
10350 05:57:29.648526 [ 0.000000] Early memory node ranges
10351 05:57:29.654968 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10352 05:57:29.661727 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10353 05:57:29.668391 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10354 05:57:29.674637 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10355 05:57:29.678067 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10356 05:57:29.687998 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10357 05:57:29.744009 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10358 05:57:29.750401 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10359 05:57:29.756875 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10360 05:57:29.760465 [ 0.000000] psci: probing for conduit method from DT.
10361 05:57:29.766963 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10362 05:57:29.770061 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10363 05:57:29.777169 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10364 05:57:29.779820 [ 0.000000] psci: SMC Calling Convention v1.2
10365 05:57:29.786770 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10366 05:57:29.789801 [ 0.000000] Detected VIPT I-cache on CPU0
10367 05:57:29.796766 [ 0.000000] CPU features: detected: GIC system register CPU interface
10368 05:57:29.803024 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10369 05:57:29.809787 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10370 05:57:29.816236 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10371 05:57:29.825962 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10372 05:57:29.832579 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10373 05:57:29.835831 [ 0.000000] alternatives: applying boot alternatives
10374 05:57:29.842120 [ 0.000000] Fallback order for Node 0: 0
10375 05:57:29.849697 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10376 05:57:29.852459 [ 0.000000] Policy zone: Normal
10377 05:57:29.875611 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12379453/extract-nfsrootfs-4j3s6mu7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10378 05:57:29.885815 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10379 05:57:29.896460 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10380 05:57:29.906355 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10381 05:57:29.912786 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10382 05:57:29.916349 <6>[ 0.000000] software IO TLB: area num 8.
10383 05:57:29.973129 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10384 05:57:30.122284 <6>[ 0.000000] Memory: 7951336K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 401432K reserved, 32768K cma-reserved)
10385 05:57:30.129227 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10386 05:57:30.135563 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10387 05:57:30.138881 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10388 05:57:30.145503 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10389 05:57:30.152050 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10390 05:57:30.155260 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10391 05:57:30.165247 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10392 05:57:30.172082 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10393 05:57:30.178773 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10394 05:57:30.185162 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10395 05:57:30.188693 <6>[ 0.000000] GICv3: 608 SPIs implemented
10396 05:57:30.191720 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10397 05:57:30.198859 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10398 05:57:30.202265 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10399 05:57:30.208736 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10400 05:57:30.222269 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10401 05:57:30.231895 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10402 05:57:30.241834 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10403 05:57:30.248581 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10404 05:57:30.261997 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10405 05:57:30.268326 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10406 05:57:30.275346 <6>[ 0.009234] Console: colour dummy device 80x25
10407 05:57:30.285053 <6>[ 0.013948] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10408 05:57:30.292272 <6>[ 0.024390] pid_max: default: 32768 minimum: 301
10409 05:57:30.295525 <6>[ 0.029291] LSM: Security Framework initializing
10410 05:57:30.301846 <6>[ 0.034228] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10411 05:57:30.311966 <6>[ 0.042090] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10412 05:57:30.318553 <6>[ 0.051512] cblist_init_generic: Setting adjustable number of callback queues.
10413 05:57:30.325001 <6>[ 0.058954] cblist_init_generic: Setting shift to 3 and lim to 1.
10414 05:57:30.335340 <6>[ 0.065293] cblist_init_generic: Setting adjustable number of callback queues.
10415 05:57:30.341878 <6>[ 0.072765] cblist_init_generic: Setting shift to 3 and lim to 1.
10416 05:57:30.345414 <6>[ 0.079165] rcu: Hierarchical SRCU implementation.
10417 05:57:30.351908 <6>[ 0.084181] rcu: Max phase no-delay instances is 1000.
10418 05:57:30.358170 <6>[ 0.091203] EFI services will not be available.
10419 05:57:30.361646 <6>[ 0.096161] smp: Bringing up secondary CPUs ...
10420 05:57:30.370103 <6>[ 0.101210] Detected VIPT I-cache on CPU1
10421 05:57:30.376544 <6>[ 0.101280] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10422 05:57:30.382805 <6>[ 0.101312] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10423 05:57:30.386263 <6>[ 0.101641] Detected VIPT I-cache on CPU2
10424 05:57:30.392981 <6>[ 0.101687] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10425 05:57:30.402922 <6>[ 0.101703] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10426 05:57:30.405869 <6>[ 0.101957] Detected VIPT I-cache on CPU3
10427 05:57:30.412988 <6>[ 0.102003] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10428 05:57:30.419451 <6>[ 0.102017] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10429 05:57:30.422799 <6>[ 0.102319] CPU features: detected: Spectre-v4
10430 05:57:30.429268 <6>[ 0.102325] CPU features: detected: Spectre-BHB
10431 05:57:30.432458 <6>[ 0.102330] Detected PIPT I-cache on CPU4
10432 05:57:30.439080 <6>[ 0.102387] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10433 05:57:30.445529 <6>[ 0.102404] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10434 05:57:30.452168 <6>[ 0.102694] Detected PIPT I-cache on CPU5
10435 05:57:30.459165 <6>[ 0.102756] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10436 05:57:30.465782 <6>[ 0.102772] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10437 05:57:30.469132 <6>[ 0.103055] Detected PIPT I-cache on CPU6
10438 05:57:30.475999 <6>[ 0.103119] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10439 05:57:30.482000 <6>[ 0.103135] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10440 05:57:30.489304 <6>[ 0.103430] Detected PIPT I-cache on CPU7
10441 05:57:30.495783 <6>[ 0.103497] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10442 05:57:30.502235 <6>[ 0.103512] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10443 05:57:30.505116 <6>[ 0.103560] smp: Brought up 1 node, 8 CPUs
10444 05:57:30.511642 <6>[ 0.244815] SMP: Total of 8 processors activated.
10445 05:57:30.514972 <6>[ 0.249736] CPU features: detected: 32-bit EL0 Support
10446 05:57:30.524725 <6>[ 0.255099] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10447 05:57:30.531278 <6>[ 0.263899] CPU features: detected: Common not Private translations
10448 05:57:30.537714 <6>[ 0.270375] CPU features: detected: CRC32 instructions
10449 05:57:30.541282 <6>[ 0.275726] CPU features: detected: RCpc load-acquire (LDAPR)
10450 05:57:30.547979 <6>[ 0.281686] CPU features: detected: LSE atomic instructions
10451 05:57:30.554528 <6>[ 0.287468] CPU features: detected: Privileged Access Never
10452 05:57:30.560950 <6>[ 0.293284] CPU features: detected: RAS Extension Support
10453 05:57:30.568479 <6>[ 0.298893] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10454 05:57:30.571185 <6>[ 0.306114] CPU: All CPU(s) started at EL2
10455 05:57:30.577764 <6>[ 0.310430] alternatives: applying system-wide alternatives
10456 05:57:30.587427 <6>[ 0.321140] devtmpfs: initialized
10457 05:57:30.603247 <6>[ 0.330024] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10458 05:57:30.609237 <6>[ 0.339985] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10459 05:57:30.616274 <6>[ 0.348174] pinctrl core: initialized pinctrl subsystem
10460 05:57:30.619349 <6>[ 0.354839] DMI not present or invalid.
10461 05:57:30.625713 <6>[ 0.359249] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10462 05:57:30.636156 <6>[ 0.366069] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10463 05:57:30.642575 <6>[ 0.373654] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10464 05:57:30.652114 <6>[ 0.381882] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10465 05:57:30.655638 <6>[ 0.390124] audit: initializing netlink subsys (disabled)
10466 05:57:30.665854 <5>[ 0.395817] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10467 05:57:30.672019 <6>[ 0.396519] thermal_sys: Registered thermal governor 'step_wise'
10468 05:57:30.678628 <6>[ 0.403783] thermal_sys: Registered thermal governor 'power_allocator'
10469 05:57:30.682149 <6>[ 0.410034] cpuidle: using governor menu
10470 05:57:30.688510 <6>[ 0.420989] NET: Registered PF_QIPCRTR protocol family
10471 05:57:30.695516 <6>[ 0.426471] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10472 05:57:30.698448 <6>[ 0.433576] ASID allocator initialised with 32768 entries
10473 05:57:30.705904 <6>[ 0.440152] Serial: AMBA PL011 UART driver
10474 05:57:30.714979 <4>[ 0.448952] Trying to register duplicate clock ID: 134
10475 05:57:30.768741 <6>[ 0.506361] KASLR enabled
10476 05:57:30.783273 <6>[ 0.514076] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10477 05:57:30.789840 <6>[ 0.521091] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10478 05:57:30.796378 <6>[ 0.527582] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10479 05:57:30.802805 <6>[ 0.534585] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10480 05:57:30.809979 <6>[ 0.541070] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10481 05:57:30.816309 <6>[ 0.548071] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10482 05:57:30.822962 <6>[ 0.554559] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10483 05:57:30.829264 <6>[ 0.561560] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10484 05:57:30.832708 <6>[ 0.569050] ACPI: Interpreter disabled.
10485 05:57:30.840984 <6>[ 0.575454] iommu: Default domain type: Translated
10486 05:57:30.847586 <6>[ 0.580564] iommu: DMA domain TLB invalidation policy: strict mode
10487 05:57:30.851117 <5>[ 0.587223] SCSI subsystem initialized
10488 05:57:30.857389 <6>[ 0.591387] usbcore: registered new interface driver usbfs
10489 05:57:30.864147 <6>[ 0.597120] usbcore: registered new interface driver hub
10490 05:57:30.867648 <6>[ 0.602670] usbcore: registered new device driver usb
10491 05:57:30.874407 <6>[ 0.608767] pps_core: LinuxPPS API ver. 1 registered
10492 05:57:30.884214 <6>[ 0.613958] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10493 05:57:30.887656 <6>[ 0.623305] PTP clock support registered
10494 05:57:30.890810 <6>[ 0.627545] EDAC MC: Ver: 3.0.0
10495 05:57:30.898716 <6>[ 0.632684] FPGA manager framework
10496 05:57:30.905046 <6>[ 0.636362] Advanced Linux Sound Architecture Driver Initialized.
10497 05:57:30.908332 <6>[ 0.643136] vgaarb: loaded
10498 05:57:30.914906 <6>[ 0.646295] clocksource: Switched to clocksource arch_sys_counter
10499 05:57:30.918246 <5>[ 0.652733] VFS: Disk quotas dquot_6.6.0
10500 05:57:30.924701 <6>[ 0.656924] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10501 05:57:30.928168 <6>[ 0.664107] pnp: PnP ACPI: disabled
10502 05:57:30.936320 <6>[ 0.670775] NET: Registered PF_INET protocol family
10503 05:57:30.946262 <6>[ 0.676358] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10504 05:57:30.957638 <6>[ 0.688694] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10505 05:57:30.967712 <6>[ 0.697508] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10506 05:57:30.974673 <6>[ 0.705477] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10507 05:57:30.984270 <6>[ 0.714181] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10508 05:57:30.990592 <6>[ 0.723935] TCP: Hash tables configured (established 65536 bind 65536)
10509 05:57:30.997618 <6>[ 0.730800] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10510 05:57:31.007070 <6>[ 0.737995] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10511 05:57:31.013810 <6>[ 0.745693] NET: Registered PF_UNIX/PF_LOCAL protocol family
10512 05:57:31.017396 <6>[ 0.751809] RPC: Registered named UNIX socket transport module.
10513 05:57:31.023965 <6>[ 0.757961] RPC: Registered udp transport module.
10514 05:57:31.027408 <6>[ 0.762893] RPC: Registered tcp transport module.
10515 05:57:31.033845 <6>[ 0.767825] RPC: Registered tcp NFSv4.1 backchannel transport module.
10516 05:57:31.040431 <6>[ 0.774493] PCI: CLS 0 bytes, default 64
10517 05:57:31.043853 <6>[ 0.778902] Unpacking initramfs...
10518 05:57:31.050494 <6>[ 0.782629] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10519 05:57:31.060437 <6>[ 0.791264] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10520 05:57:31.064106 <6>[ 0.800113] kvm [1]: IPA Size Limit: 40 bits
10521 05:57:31.070617 <6>[ 0.804641] kvm [1]: GICv3: no GICV resource entry
10522 05:57:31.073788 <6>[ 0.809660] kvm [1]: disabling GICv2 emulation
10523 05:57:31.080342 <6>[ 0.814347] kvm [1]: GIC system register CPU interface enabled
10524 05:57:31.087270 <6>[ 0.820522] kvm [1]: vgic interrupt IRQ18
10525 05:57:31.094010 <6>[ 0.826352] kvm [1]: VHE mode initialized successfully
10526 05:57:31.096933 <5>[ 0.832765] Initialise system trusted keyrings
10527 05:57:31.103633 <6>[ 0.837562] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10528 05:57:31.113776 <6>[ 0.847496] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10529 05:57:31.120478 <5>[ 0.853875] NFS: Registering the id_resolver key type
10530 05:57:31.123473 <5>[ 0.859174] Key type id_resolver registered
10531 05:57:31.130026 <5>[ 0.863590] Key type id_legacy registered
10532 05:57:31.136604 <6>[ 0.867873] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10533 05:57:31.143393 <6>[ 0.874799] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10534 05:57:31.149789 <6>[ 0.882507] 9p: Installing v9fs 9p2000 file system support
10535 05:57:31.186983 <5>[ 0.920671] Key type asymmetric registered
10536 05:57:31.190371 <5>[ 0.925001] Asymmetric key parser 'x509' registered
10537 05:57:31.199874 <6>[ 0.930150] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10538 05:57:31.203607 <6>[ 0.937760] io scheduler mq-deadline registered
10539 05:57:31.206480 <6>[ 0.942553] io scheduler kyber registered
10540 05:57:31.225210 <6>[ 0.959503] EINJ: ACPI disabled.
10541 05:57:31.257155 <4>[ 0.984630] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10542 05:57:31.267177 <4>[ 0.995263] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10543 05:57:31.281550 <6>[ 1.015644] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10544 05:57:31.289913 <6>[ 1.023546] printk: console [ttyS0] disabled
10545 05:57:31.317936 <6>[ 1.048194] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10546 05:57:31.324253 <6>[ 1.057675] printk: console [ttyS0] enabled
10547 05:57:31.327769 <6>[ 1.057675] printk: console [ttyS0] enabled
10548 05:57:31.334253 <6>[ 1.066573] printk: bootconsole [mtk8250] disabled
10549 05:57:31.337749 <6>[ 1.066573] printk: bootconsole [mtk8250] disabled
10550 05:57:31.344105 <6>[ 1.077614] SuperH (H)SCI(F) driver initialized
10551 05:57:31.347795 <6>[ 1.082915] msm_serial: driver initialized
10552 05:57:31.361100 <6>[ 1.091862] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10553 05:57:31.370963 <6>[ 1.100411] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10554 05:57:31.378121 <6>[ 1.108954] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10555 05:57:31.388228 <6>[ 1.117582] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10556 05:57:31.398112 <6>[ 1.126292] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10557 05:57:31.404701 <6>[ 1.135004] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10558 05:57:31.414577 <6>[ 1.143543] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10559 05:57:31.421077 <6>[ 1.152344] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10560 05:57:31.430663 <6>[ 1.160887] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10561 05:57:31.443259 <6>[ 1.176496] loop: module loaded
10562 05:57:31.449031 <6>[ 1.182462] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10563 05:57:31.472043 <4>[ 1.205633] mtk-pmic-keys: Failed to locate of_node [id: -1]
10564 05:57:31.478560 <6>[ 1.212440] megasas: 07.719.03.00-rc1
10565 05:57:31.487749 <6>[ 1.221941] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10566 05:57:31.499657 <6>[ 1.233695] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10567 05:57:31.516161 <6>[ 1.250298] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10568 05:57:31.571963 <6>[ 1.299662] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10569 05:57:31.784474 <6>[ 1.518129] Freeing initrd memory: 17380K
10570 05:57:31.794369 <6>[ 1.528380] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10571 05:57:31.805548 <6>[ 1.539209] tun: Universal TUN/TAP device driver, 1.6
10572 05:57:31.808373 <6>[ 1.545256] thunder_xcv, ver 1.0
10573 05:57:31.811696 <6>[ 1.548762] thunder_bgx, ver 1.0
10574 05:57:31.815345 <6>[ 1.552255] nicpf, ver 1.0
10575 05:57:31.826011 <6>[ 1.556260] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10576 05:57:31.829136 <6>[ 1.563736] hns3: Copyright (c) 2017 Huawei Corporation.
10577 05:57:31.832376 <6>[ 1.569322] hclge is initializing
10578 05:57:31.839221 <6>[ 1.572895] e1000: Intel(R) PRO/1000 Network Driver
10579 05:57:31.845446 <6>[ 1.578026] e1000: Copyright (c) 1999-2006 Intel Corporation.
10580 05:57:31.849225 <6>[ 1.584038] e1000e: Intel(R) PRO/1000 Network Driver
10581 05:57:31.855793 <6>[ 1.589254] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10582 05:57:31.862055 <6>[ 1.595438] igb: Intel(R) Gigabit Ethernet Network Driver
10583 05:57:31.868807 <6>[ 1.601088] igb: Copyright (c) 2007-2014 Intel Corporation.
10584 05:57:31.875662 <6>[ 1.606927] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10585 05:57:31.882130 <6>[ 1.613445] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10586 05:57:31.885297 <6>[ 1.619906] sky2: driver version 1.30
10587 05:57:31.892377 <6>[ 1.624897] VFIO - User Level meta-driver version: 0.3
10588 05:57:31.899382 <6>[ 1.633098] usbcore: registered new interface driver usb-storage
10589 05:57:31.905796 <6>[ 1.639557] usbcore: registered new device driver onboard-usb-hub
10590 05:57:31.914854 <6>[ 1.648697] mt6397-rtc mt6359-rtc: registered as rtc0
10591 05:57:31.924676 <6>[ 1.654162] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-25T05:57:32 UTC (1703483852)
10592 05:57:31.928300 <6>[ 1.663720] i2c_dev: i2c /dev entries driver
10593 05:57:31.944980 <6>[ 1.675388] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10594 05:57:31.965588 <6>[ 1.699396] cpu cpu0: EM: created perf domain
10595 05:57:31.968467 <6>[ 1.704324] cpu cpu4: EM: created perf domain
10596 05:57:31.976212 <6>[ 1.709880] sdhci: Secure Digital Host Controller Interface driver
10597 05:57:31.982738 <6>[ 1.716314] sdhci: Copyright(c) Pierre Ossman
10598 05:57:31.989205 <6>[ 1.721274] Synopsys Designware Multimedia Card Interface Driver
10599 05:57:31.995703 <6>[ 1.727913] sdhci-pltfm: SDHCI platform and OF driver helper
10600 05:57:31.999290 <6>[ 1.728036] mmc0: CQHCI version 5.10
10601 05:57:32.006314 <6>[ 1.737906] ledtrig-cpu: registered to indicate activity on CPUs
10602 05:57:32.012560 <6>[ 1.744858] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10603 05:57:32.019336 <6>[ 1.751906] usbcore: registered new interface driver usbhid
10604 05:57:32.022810 <6>[ 1.757727] usbhid: USB HID core driver
10605 05:57:32.029164 <6>[ 1.761923] spi_master spi0: will run message pump with realtime priority
10606 05:57:32.072443 <6>[ 1.800043] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10607 05:57:32.092105 <6>[ 1.816020] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10608 05:57:32.095755 <6>[ 1.829919] mmc0: Command Queue Engine enabled
10609 05:57:32.102465 <6>[ 1.834683] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10610 05:57:32.109090 <6>[ 1.841459] cros-ec-spi spi0.0: Chrome EC device registered
10611 05:57:32.111712 <6>[ 1.841898] mmcblk0: mmc0:0001 DA4128 116 GiB
10612 05:57:32.123383 <6>[ 1.857612] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10613 05:57:32.131194 <6>[ 1.864801] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10614 05:57:32.137685 <6>[ 1.870847] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10615 05:57:32.147461 <6>[ 1.876279] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10616 05:57:32.154155 <6>[ 1.876784] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10617 05:57:32.157615 <6>[ 1.886630] NET: Registered PF_PACKET protocol family
10618 05:57:32.164263 <6>[ 1.897529] 9pnet: Installing 9P2000 support
10619 05:57:32.167532 <5>[ 1.902111] Key type dns_resolver registered
10620 05:57:32.174016 <6>[ 1.907103] registered taskstats version 1
10621 05:57:32.177442 <5>[ 1.911509] Loading compiled-in X.509 certificates
10622 05:57:32.206030 <4>[ 1.933484] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10623 05:57:32.215826 <4>[ 1.944254] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10624 05:57:32.222633 <3>[ 1.954869] debugfs: File 'uA_load' in directory '/' already present!
10625 05:57:32.229460 <3>[ 1.961582] debugfs: File 'min_uV' in directory '/' already present!
10626 05:57:32.235915 <3>[ 1.968192] debugfs: File 'max_uV' in directory '/' already present!
10627 05:57:32.242514 <3>[ 1.974799] debugfs: File 'constraint_flags' in directory '/' already present!
10628 05:57:32.253411 <3>[ 1.984294] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10629 05:57:32.262687 <6>[ 1.996538] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10630 05:57:32.269814 <6>[ 2.003371] xhci-mtk 11200000.usb: xHCI Host Controller
10631 05:57:32.276234 <6>[ 2.008867] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10632 05:57:32.286468 <6>[ 2.016836] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10633 05:57:32.292809 <6>[ 2.026279] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10634 05:57:32.299633 <6>[ 2.032373] xhci-mtk 11200000.usb: xHCI Host Controller
10635 05:57:32.306134 <6>[ 2.037858] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10636 05:57:32.312734 <6>[ 2.045515] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10637 05:57:32.319592 <6>[ 2.053405] hub 1-0:1.0: USB hub found
10638 05:57:32.323171 <6>[ 2.057449] hub 1-0:1.0: 1 port detected
10639 05:57:32.332476 <6>[ 2.061740] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10640 05:57:32.336066 <6>[ 2.070575] hub 2-0:1.0: USB hub found
10641 05:57:32.338740 <6>[ 2.074596] hub 2-0:1.0: 1 port detected
10642 05:57:32.348845 <6>[ 2.082761] mtk-msdc 11f70000.mmc: Got CD GPIO
10643 05:57:32.359720 <6>[ 2.090434] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10644 05:57:32.366244 <6>[ 2.098457] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10645 05:57:32.376211 <4>[ 2.106375] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10646 05:57:32.385735 <6>[ 2.115919] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10647 05:57:32.392522 <6>[ 2.123996] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10648 05:57:32.399479 <6>[ 2.132013] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10649 05:57:32.409455 <6>[ 2.139934] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10650 05:57:32.415843 <6>[ 2.147754] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10651 05:57:32.426115 <6>[ 2.155575] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10652 05:57:32.435831 <6>[ 2.165925] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10653 05:57:32.442259 <6>[ 2.174307] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10654 05:57:32.452173 <6>[ 2.182654] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10655 05:57:32.459211 <6>[ 2.190993] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10656 05:57:32.468976 <6>[ 2.199331] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10657 05:57:32.475457 <6>[ 2.207671] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10658 05:57:32.485624 <6>[ 2.216010] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10659 05:57:32.492617 <6>[ 2.224348] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10660 05:57:32.502568 <6>[ 2.232687] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10661 05:57:32.508812 <6>[ 2.241025] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10662 05:57:32.518626 <6>[ 2.249364] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10663 05:57:32.525321 <6>[ 2.257709] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10664 05:57:32.535083 <6>[ 2.266050] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10665 05:57:32.545014 <6>[ 2.274402] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10666 05:57:32.551932 <6>[ 2.282742] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10667 05:57:32.558493 <6>[ 2.291466] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10668 05:57:32.564797 <6>[ 2.298601] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10669 05:57:32.571585 <6>[ 2.305352] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10670 05:57:32.578415 <6>[ 2.312112] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10671 05:57:32.588326 <6>[ 2.319046] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10672 05:57:32.595125 <6>[ 2.325898] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10673 05:57:32.604982 <6>[ 2.335025] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10674 05:57:32.614788 <6>[ 2.344143] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10675 05:57:32.624709 <6>[ 2.353437] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10676 05:57:32.634760 <6>[ 2.362909] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10677 05:57:32.641042 <6>[ 2.372377] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10678 05:57:32.651114 <6>[ 2.381496] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10679 05:57:32.660924 <6>[ 2.390963] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10680 05:57:32.670866 <6>[ 2.400080] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10681 05:57:32.680787 <6>[ 2.409373] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10682 05:57:32.690786 <6>[ 2.419534] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10683 05:57:32.700204 <6>[ 2.431066] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10684 05:57:32.707175 <6>[ 2.440836] Trying to probe devices needed for running init ...
10685 05:57:32.751402 <6>[ 2.482573] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10686 05:57:32.906523 <6>[ 2.640391] hub 1-1:1.0: USB hub found
10687 05:57:32.909774 <6>[ 2.644925] hub 1-1:1.0: 4 ports detected
10688 05:57:32.919281 <6>[ 2.653396] hub 1-1:1.0: USB hub found
10689 05:57:32.922641 <6>[ 2.657872] hub 1-1:1.0: 4 ports detected
10690 05:57:33.031846 <6>[ 2.762702] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10691 05:57:33.057115 <6>[ 2.791286] hub 2-1:1.0: USB hub found
10692 05:57:33.060539 <6>[ 2.795737] hub 2-1:1.0: 3 ports detected
10693 05:57:33.069533 <6>[ 2.803567] hub 2-1:1.0: USB hub found
10694 05:57:33.072709 <6>[ 2.808068] hub 2-1:1.0: 3 ports detected
10695 05:57:33.247545 <6>[ 2.978592] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10696 05:57:33.380164 <6>[ 3.114405] hub 1-1.4:1.0: USB hub found
10697 05:57:33.383451 <6>[ 3.119062] hub 1-1.4:1.0: 2 ports detected
10698 05:57:33.392975 <6>[ 3.127291] hub 1-1.4:1.0: USB hub found
10699 05:57:33.396354 <6>[ 3.131896] hub 1-1.4:1.0: 2 ports detected
10700 05:57:33.459668 <6>[ 3.190729] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10701 05:57:33.691229 <6>[ 3.422620] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10702 05:57:33.883422 <6>[ 3.614588] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10703 05:57:44.996699 <6>[ 14.735596] ALSA device list:
10704 05:57:45.003171 <6>[ 14.738892] No soundcards found.
10705 05:57:45.010859 <6>[ 14.746851] Freeing unused kernel memory: 8448K
10706 05:57:45.014344 <6>[ 14.751938] Run /init as init process
10707 05:57:45.026046 Loading, please wait...
10708 05:57:45.046398 Starting version 247.3-7+deb11u2
10709 05:57:45.257336 <3>[ 14.989650] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 05:57:45.264155 <3>[ 14.997982] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 05:57:45.273736 <3>[ 15.006122] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 05:57:45.280498 <6>[ 15.015232] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10713 05:57:45.290565 <6>[ 15.016416] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10714 05:57:45.297001 <6>[ 15.022953] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10715 05:57:45.306615 <6>[ 15.024094] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10716 05:57:45.313750 <3>[ 15.026539] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 05:57:45.323334 <3>[ 15.026573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 05:57:45.329764 <3>[ 15.026586] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 05:57:45.336604 <3>[ 15.026597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 05:57:45.346854 <3>[ 15.026605] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 05:57:45.356383 <3>[ 15.040823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 05:57:45.362773 <4>[ 15.048732] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10723 05:57:45.369756 <4>[ 15.048732] Fallback method does not support PEC.
10724 05:57:45.376313 <6>[ 15.054872] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10725 05:57:45.383245 <6>[ 15.071656] remoteproc remoteproc0: scp is available
10726 05:57:45.390372 <3>[ 15.072939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 05:57:45.399984 <3>[ 15.072956] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 05:57:45.406490 <3>[ 15.072964] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 05:57:45.416864 <3>[ 15.073480] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 05:57:45.423158 <3>[ 15.073487] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 05:57:45.430004 <3>[ 15.073491] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 05:57:45.439462 <3>[ 15.073497] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 05:57:45.445995 <3>[ 15.073500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 05:57:45.456193 <3>[ 15.073531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 05:57:45.459619 <6>[ 15.077053] mc: Linux media interface: v0.10
10736 05:57:45.466348 <4>[ 15.080229] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10737 05:57:45.472661 <6>[ 15.088177] remoteproc remoteproc0: powering up scp
10738 05:57:45.479287 <4>[ 15.096034] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10739 05:57:45.489697 <6>[ 15.109326] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10740 05:57:45.492380 <6>[ 15.109363] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10741 05:57:45.499335 <6>[ 15.109842] usbcore: registered new interface driver r8152
10742 05:57:45.506107 <6>[ 15.117408] videodev: Linux video capture interface: v2.00
10743 05:57:45.515938 <3>[ 15.132063] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10744 05:57:45.522765 <6>[ 15.187182] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10745 05:57:45.530009 <6>[ 15.199811] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10746 05:57:45.539359 <6>[ 15.201438] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10747 05:57:45.546082 <6>[ 15.208427] pci_bus 0000:00: root bus resource [bus 00-ff]
10748 05:57:45.552964 <6>[ 15.234906] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10749 05:57:45.559697 <6>[ 15.240653] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10750 05:57:45.569652 <6>[ 15.240721] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10751 05:57:45.576034 <6>[ 15.240731] remoteproc remoteproc0: remote processor scp is now up
10752 05:57:45.582837 <6>[ 15.242352] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10753 05:57:45.592772 <6>[ 15.242359] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10754 05:57:45.599388 <6>[ 15.242394] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10755 05:57:45.605573 <6>[ 15.242413] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10756 05:57:45.609283 <6>[ 15.242490] pci 0000:00:00.0: supports D1 D2
10757 05:57:45.619086 <6>[ 15.242494] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10758 05:57:45.625485 <6>[ 15.244179] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10759 05:57:45.632294 <6>[ 15.244287] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10760 05:57:45.639121 <6>[ 15.244318] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10761 05:57:45.645553 <6>[ 15.244338] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10762 05:57:45.655296 <6>[ 15.244357] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10763 05:57:45.658665 <6>[ 15.244472] pci 0000:01:00.0: supports D1 D2
10764 05:57:45.665659 <6>[ 15.244475] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10765 05:57:45.671799 <6>[ 15.254449] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10766 05:57:45.682154 <6>[ 15.258160] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10767 05:57:45.688314 <6>[ 15.265232] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10768 05:57:45.698300 <4>[ 15.270514] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10769 05:57:45.708090 <4>[ 15.270529] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10770 05:57:45.714842 <3>[ 15.275357] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10771 05:57:45.724801 <6>[ 15.281117] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10772 05:57:45.731748 <6>[ 15.281138] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10773 05:57:45.737750 <6>[ 15.287349] usbcore: registered new interface driver cdc_ether
10774 05:57:45.744713 <6>[ 15.288636] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10775 05:57:45.754552 <6>[ 15.290729] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10776 05:57:45.761363 <6>[ 15.294013] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10777 05:57:45.767487 <6>[ 15.309767] usbcore: registered new interface driver r8153_ecm
10778 05:57:45.777766 <6>[ 15.316024] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10779 05:57:45.780725 <6>[ 15.316047] pci 0000:00:00.0: PCI bridge to [bus 01]
10780 05:57:45.787835 <6>[ 15.324581] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10781 05:57:45.797392 <6>[ 15.333071] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10782 05:57:45.803830 <6>[ 15.333280] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10783 05:57:45.807186 <6>[ 15.333291] r8152 2-1.3:1.0 eth0: v1.12.13
10784 05:57:45.810507 <6>[ 15.334397] Bluetooth: Core ver 2.22
10785 05:57:45.817436 <6>[ 15.334502] NET: Registered PF_BLUETOOTH protocol family
10786 05:57:45.824192 <6>[ 15.334508] Bluetooth: HCI device and connection manager initialized
10787 05:57:45.827045 <6>[ 15.334537] Bluetooth: HCI socket layer initialized
10788 05:57:45.833614 <6>[ 15.334557] Bluetooth: L2CAP socket layer initialized
10789 05:57:45.840105 <6>[ 15.334577] Bluetooth: SCO socket layer initialized
10790 05:57:45.843460 <6>[ 15.340675] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10791 05:57:45.857062 <6>[ 15.340949] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10792 05:57:45.863264 <6>[ 15.341048] usbcore: registered new interface driver uvcvideo
10793 05:57:45.870167 <6>[ 15.349490] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10794 05:57:45.876977 <6>[ 15.367039] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10795 05:57:45.883286 <6>[ 15.373166] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10796 05:57:45.886823 <6>[ 15.380855] usbcore: registered new interface driver btusb
10797 05:57:45.899530 <4>[ 15.381495] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10798 05:57:45.902878 <3>[ 15.381501] Bluetooth: hci0: Failed to load firmware file (-2)
10799 05:57:45.909755 <3>[ 15.381503] Bluetooth: hci0: Failed to set up firmware (-2)
10800 05:57:45.919337 <4>[ 15.381505] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10801 05:57:45.936379 <5>[ 15.669061] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10802 05:57:45.957696 <5>[ 15.690370] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10803 05:57:45.964693 <4>[ 15.697392] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10804 05:57:45.971196 <6>[ 15.706329] cfg80211: failed to load regulatory.db
10805 05:57:46.028121 <6>[ 15.760921] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10806 05:57:46.034579 <6>[ 15.768577] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10807 05:57:46.058668 <6>[ 15.794543] mt7921e 0000:01:00.0: ASIC revision: 79610010
10808 05:57:46.162061 <6>[ 15.894945] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10809 05:57:46.165431 <6>[ 15.894945]
10810 05:57:46.173450 Begin: Loading essential drivers ... done.
10811 05:57:46.176644 Begin: Running /scripts/init-premount ... done.
10812 05:57:46.183215 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10813 05:57:46.193408 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10814 05:57:46.196638 Device /sys/class/net/enx0024323078ff found
10815 05:57:46.196720 done.
10816 05:57:46.258395 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10817 05:57:46.431012 <6>[ 16.163325] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10818 05:57:47.248150 <6>[ 16.984386] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10819 05:57:47.281181 <6>[ 17.017409] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10820 05:57:47.418264 IP-Config: no response after 2 secs - giving up
10821 05:57:47.466605 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10822 05:57:48.181547 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10823 05:57:48.190333 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10824 05:57:48.197404 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10825 05:57:48.203959 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10826 05:57:48.210485 host : mt8192-asurada-spherion-r0-cbg-8
10827 05:57:48.216792 domain : lava-rack
10828 05:57:48.223518 rootserver: 192.168.201.1 rootpath:
10829 05:57:48.223601 filename :
10830 05:57:48.356009 done.
10831 05:57:48.363390 Begin: Running /scripts/nfs-bottom ... done.
10832 05:57:48.379550 Begin: Running /scripts/init-bottom ... done.
10833 05:57:49.604576 <6>[ 19.340865] NET: Registered PF_INET6 protocol family
10834 05:57:49.612080 <6>[ 19.348635] Segment Routing with IPv6
10835 05:57:49.615390 <6>[ 19.352623] In-situ OAM (IOAM) with IPv6
10836 05:57:49.749081 <30>[ 19.465806] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10837 05:57:49.755895 <30>[ 19.490230] systemd[1]: Detected architecture arm64.
10838 05:57:49.774993
10839 05:57:49.778542 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10840 05:57:49.778657
10841 05:57:49.800750 <30>[ 19.537153] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10842 05:57:50.654628 <30>[ 20.387957] systemd[1]: Queued start job for default target Graphical Interface.
10843 05:57:50.688112 <30>[ 20.424878] systemd[1]: Created slice system-getty.slice.
10844 05:57:50.694740 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10845 05:57:50.711531 <30>[ 20.447960] systemd[1]: Created slice system-modprobe.slice.
10846 05:57:50.718071 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10847 05:57:50.735132 <30>[ 20.471816] systemd[1]: Created slice system-serial\x2dgetty.slice.
10848 05:57:50.745621 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10849 05:57:50.759293 <30>[ 20.495672] systemd[1]: Created slice User and Session Slice.
10850 05:57:50.765441 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10851 05:57:50.786072 <30>[ 20.519432] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10852 05:57:50.796083 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10853 05:57:50.814431 <30>[ 20.547348] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10854 05:57:50.820842 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10855 05:57:50.844930 <30>[ 20.574736] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10856 05:57:50.851331 <30>[ 20.586900] systemd[1]: Reached target Local Encrypted Volumes.
10857 05:57:50.858204 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10858 05:57:50.874183 <30>[ 20.610726] systemd[1]: Reached target Paths.
10859 05:57:50.877400 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10860 05:57:50.893999 <30>[ 20.630586] systemd[1]: Reached target Remote File Systems.
10861 05:57:50.900499 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10862 05:57:50.918322 <30>[ 20.654544] systemd[1]: Reached target Slices.
10863 05:57:50.924527 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10864 05:57:50.938018 <30>[ 20.674610] systemd[1]: Reached target Swap.
10865 05:57:50.941174 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10866 05:57:50.962029 <30>[ 20.695019] systemd[1]: Listening on initctl Compatibility Named Pipe.
10867 05:57:50.968383 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10868 05:57:50.975136 <30>[ 20.711138] systemd[1]: Listening on Journal Audit Socket.
10869 05:57:50.981744 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10870 05:57:50.999150 <30>[ 20.735920] systemd[1]: Listening on Journal Socket (/dev/log).
10871 05:57:51.006239 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10872 05:57:51.022726 <30>[ 20.759160] systemd[1]: Listening on Journal Socket.
10873 05:57:51.029281 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10874 05:57:51.047029 <30>[ 20.780097] systemd[1]: Listening on Network Service Netlink Socket.
10875 05:57:51.053761 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10876 05:57:51.069295 <30>[ 20.805610] systemd[1]: Listening on udev Control Socket.
10877 05:57:51.075759 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10878 05:57:51.090530 <30>[ 20.827017] systemd[1]: Listening on udev Kernel Socket.
10879 05:57:51.096830 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10880 05:57:51.154314 <30>[ 20.890734] systemd[1]: Mounting Huge Pages File System...
10881 05:57:51.160573 Mounting [0;1;39mHuge Pages File System[0m...
10882 05:57:51.177881 <30>[ 20.914597] systemd[1]: Mounting POSIX Message Queue File System...
10883 05:57:51.185001 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10884 05:57:51.230663 <30>[ 20.967014] systemd[1]: Mounting Kernel Debug File System...
10885 05:57:51.236943 Mounting [0;1;39mKernel Debug File System[0m...
10886 05:57:51.253827 <30>[ 20.986884] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10887 05:57:51.298017 <30>[ 21.031361] systemd[1]: Starting Create list of static device nodes for the current kernel...
10888 05:57:51.304663 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10889 05:57:51.327027 <30>[ 21.063467] systemd[1]: Starting Load Kernel Module configfs...
10890 05:57:51.333387 Starting [0;1;39mLoad Kernel Module configfs[0m...
10891 05:57:51.350295 <30>[ 21.086972] systemd[1]: Starting Load Kernel Module drm...
10892 05:57:51.357051 Starting [0;1;39mLoad Kernel Module drm[0m...
10893 05:57:51.374843 <30>[ 21.111237] systemd[1]: Starting Load Kernel Module fuse...
10894 05:57:51.381228 Starting [0;1;39mLoad Kernel Module fuse[0m...
10895 05:57:51.416726 <6>[ 21.153439] fuse: init (API version 7.37)
10896 05:57:51.426973 <30>[ 21.154311] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10897 05:57:51.466841 <30>[ 21.203474] systemd[1]: Starting Journal Service...
10898 05:57:51.470608 Starting [0;1;39mJournal Service[0m...
10899 05:57:51.497233 <30>[ 21.233674] systemd[1]: Starting Load Kernel Modules...
10900 05:57:51.503713 Starting [0;1;39mLoad Kernel Modules[0m...
10901 05:57:51.525056 <30>[ 21.258280] systemd[1]: Starting Remount Root and Kernel File Systems...
10902 05:57:51.531382 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10903 05:57:51.554918 <30>[ 21.291377] systemd[1]: Starting Coldplug All udev Devices...
10904 05:57:51.561674 Starting [0;1;39mColdplug All udev Devices[0m...
10905 05:57:51.581237 <30>[ 21.317769] systemd[1]: Mounted Huge Pages File System.
10906 05:57:51.587591 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10907 05:57:51.609095 <3>[ 21.342604] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 05:57:51.615818 <30>[ 21.343090] systemd[1]: Mounted POSIX Message Queue File System.
10909 05:57:51.622815 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10910 05:57:51.639028 <30>[ 21.374905] systemd[1]: Mounted Kernel Debug File System.
10911 05:57:51.648762 <3>[ 21.380101] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 05:57:51.655132 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10913 05:57:51.687531 <3>[ 21.420578] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 05:57:51.697449 <30>[ 21.430635] systemd[1]: Finished Create list of static device nodes for the current kernel.
10915 05:57:51.708096 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10916 05:57:51.718407 <3>[ 21.450036] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 05:57:51.724985 <30>[ 21.459904] systemd[1]: modprobe@configfs.service: Succeeded.
10918 05:57:51.731400 <30>[ 21.466886] systemd[1]: Finished Load Kernel Module configfs.
10919 05:57:51.738639 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10920 05:57:51.745730 <3>[ 21.479836] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 05:57:51.755225 <30>[ 21.491862] systemd[1]: modprobe@drm.service: Succeeded.
10922 05:57:51.761941 <30>[ 21.498191] systemd[1]: Finished Load Kernel Module drm.
10923 05:57:51.775989 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m<3>[ 21.509396] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 05:57:51.776079 .
10925 05:57:51.784130 <30>[ 21.520706] systemd[1]: modprobe@fuse.service: Succeeded.
10926 05:57:51.791091 <30>[ 21.527524] systemd[1]: Finished Load Kernel Module fuse.
10927 05:57:51.797900 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10928 05:57:51.809942 <3>[ 21.543377] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 05:57:51.818725 <30>[ 21.554980] systemd[1]: Finished Load Kernel Modules.
10930 05:57:51.824899 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10931 05:57:51.840914 <3>[ 21.574123] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 05:57:51.854227 <30>[ 21.587656] systemd[1]: Finished Remount Root and Kernel File Systems.
10933 05:57:51.861495 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10934 05:57:51.871640 <3>[ 21.604091] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 05:57:51.902799 <3>[ 21.636293] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 05:57:51.909776 <30>[ 21.641366] systemd[1]: Mounting FUSE Control File System...
10937 05:57:51.916056 Mounting [0;1;39mFUSE Control File System[0m...
10938 05:57:51.936634 <30>[ 21.669741] systemd[1]: Mounting Kernel Configuration File System...
10939 05:57:51.939621 Mounting [0;1;39mKernel Configuration File System[0m...
10940 05:57:51.962106 <30>[ 21.695045] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10941 05:57:51.971505 <30>[ 21.704222] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10942 05:57:52.026953 <30>[ 21.763431] systemd[1]: Starting Load/Save Random Seed...
10943 05:57:52.033554 Starting [0;1;39mLoad/Save Random Seed[0m...
10944 05:57:52.055171 <4>[ 21.782173] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10945 05:57:52.065450 <3>[ 21.797877] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10946 05:57:52.068607 <30>[ 21.801290] systemd[1]: Starting Apply Kernel Variables...
10947 05:57:52.075152 Starting [0;1;39mApply Kernel Variables[0m...
10948 05:57:52.139310 <30>[ 21.875498] systemd[1]: Starting Create System Users...
10949 05:57:52.145437 Starting [0;1;39mCreate System Users[0m...
10950 05:57:52.160385 <30>[ 21.896966] systemd[1]: Started Journal Service.
10951 05:57:52.166811 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10952 05:57:52.189389 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10953 05:57:52.201774 See 'systemctl status systemd-udev-trigger.service' for details.
10954 05:57:52.218785 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10955 05:57:52.234017 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10956 05:57:52.250979 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10957 05:57:52.266906 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10958 05:57:52.284086 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10959 05:57:52.330581 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10960 05:57:52.348080 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10961 05:57:52.388910 <46>[ 22.122584] systemd-journald[291]: Received client request to flush runtime journal.
10962 05:57:52.445670 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10963 05:57:52.458601 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10964 05:57:52.473925 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10965 05:57:52.526687 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10966 05:57:53.792986 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10967 05:57:53.834888 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10968 05:57:53.892262 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10969 05:57:53.947162 Starting [0;1;39mNetwork Service[0m...
10970 05:57:54.229185 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10971 05:57:54.251163 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10972 05:57:54.311671 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10973 05:57:54.653260 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10974 05:57:54.669492 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10975 05:57:54.690038 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10976 05:57:54.706150 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10977 05:57:54.778768 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10978 05:57:54.799994 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10979 05:57:54.825218 Starting [0;1;39mNetwork Name Resolution[0m...
10980 05:57:54.849133 Starting [0;1;39mNetwork Time Synchronization[0m...
10981 05:57:54.871109 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10982 05:57:54.887210 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10983 05:57:54.930928 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10984 05:57:55.047825 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10985 05:57:55.066214 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10986 05:57:55.089424 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10987 05:57:55.105875 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10988 05:57:55.121432 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10989 05:57:55.153742 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10990 05:57:55.224621 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10991 05:57:55.319106 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10992 05:57:55.369405 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10993 05:57:55.382118 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10994 05:57:55.403241 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10995 05:57:55.417982 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10996 05:57:55.433760 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10997 05:57:55.478594 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10998 05:57:56.198044 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10999 05:57:56.579657 Starting [0;1;39mUser Login Management[0m...
11000 05:57:56.600532 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11001 05:57:56.621744 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11002 05:57:56.634202 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11003 05:57:56.680334 Starting [0;1;39mPermit User Sessions[0m...
11004 05:57:56.793139 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11005 05:57:56.808942 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11006 05:57:56.845940 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11007 05:57:56.888705 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11008 05:57:56.906165 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11009 05:57:56.924416 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11010 05:57:56.943865 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11011 05:57:56.962242 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11012 05:57:57.014721 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11013 05:57:57.061146 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11014 05:57:57.155723
11015 05:57:57.155887
11016 05:57:57.159168 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11017 05:57:57.159287
11018 05:57:57.162074 debian-bullseye-arm64 login: root (automatic login)
11019 05:57:57.162157
11020 05:57:57.162220
11021 05:57:57.522039 Linux debian-bullseye-arm64 6.1.67-cip12 #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023 aarch64
11022 05:57:57.522165
11023 05:57:57.528387 The programs included with the Debian GNU/Linux system are free software;
11024 05:57:57.535049 the exact distribution terms for each program are described in the
11025 05:57:57.538263 individual files in /usr/share/doc/*/copyright.
11026 05:57:57.538342
11027 05:57:57.545309 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11028 05:57:57.548177 permitted by applicable law.
11029 05:57:58.386130 Matched prompt #10: / #
11031 05:57:58.386410 Setting prompt string to ['/ #']
11032 05:57:58.386506 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11034 05:57:58.386702 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11035 05:57:58.386793 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
11036 05:57:58.386866 Setting prompt string to ['/ #']
11037 05:57:58.386927 Forcing a shell prompt, looking for ['/ #']
11039 05:57:58.437150 / #
11040 05:57:58.437289 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11041 05:57:58.437426 Waiting using forced prompt support (timeout 00:02:30)
11042 05:57:58.442871
11043 05:57:58.443180 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11044 05:57:58.443275 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
11046 05:57:58.543624 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12379453/extract-nfsrootfs-4j3s6mu7'
11047 05:57:58.549078 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12379453/extract-nfsrootfs-4j3s6mu7'
11049 05:57:58.649647 / # export NFS_SERVER_IP='192.168.201.1'
11050 05:57:58.655121 export NFS_SERVER_IP='192.168.201.1'
11051 05:57:58.655414 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11052 05:57:58.655513 end: 2.2 depthcharge-retry (duration 00:01:46) [common]
11053 05:57:58.655606 end: 2 depthcharge-action (duration 00:01:46) [common]
11054 05:57:58.655695 start: 3 lava-test-retry (timeout 00:07:33) [common]
11055 05:57:58.655781 start: 3.1 lava-test-shell (timeout 00:07:33) [common]
11056 05:57:58.655852 Using namespace: common
11058 05:57:58.756208 / # #
11059 05:57:58.756371 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11060 05:57:58.761863 #
11061 05:57:58.762169 Using /lava-12379453
11063 05:57:58.862502 / # export SHELL=/bin/bash
11064 05:57:58.868000 export SHELL=/bin/bash
11066 05:57:58.968560 / # . /lava-12379453/environment
11067 05:57:58.974066 . /lava-12379453/environment
11069 05:57:59.080322 / # /lava-12379453/bin/lava-test-runner /lava-12379453/0
11070 05:57:59.080477 Test shell timeout: 10s (minimum of the action and connection timeout)
11071 05:57:59.085309 /lava-12379453/bin/lava-test-runner /lava-12379453/0
11072 05:57:59.382050 + export TESTRUN_ID=0_timesync-off
11073 05:57:59.384876 + TESTRUN_ID=0_timesync-off
11074 05:57:59.388634 + cd /lava-12379453/0/tests/0_timesync-off
11075 05:57:59.391517 ++ cat uuid
11076 05:57:59.397707 + UUID=12379453_1.6.2.3.1
11077 05:57:59.397817 + set +x
11078 05:57:59.404354 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12379453_1.6.2.3.1>
11079 05:57:59.404670 Received signal: <STARTRUN> 0_timesync-off 12379453_1.6.2.3.1
11080 05:57:59.404793 Starting test lava.0_timesync-off (12379453_1.6.2.3.1)
11081 05:57:59.404946 Skipping test definition patterns.
11082 05:57:59.407572 + systemctl stop systemd-timesyncd
11083 05:57:59.463017 + set +x
11084 05:57:59.466471 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12379453_1.6.2.3.1>
11085 05:57:59.466782 Received signal: <ENDRUN> 0_timesync-off 12379453_1.6.2.3.1
11086 05:57:59.466898 Ending use of test pattern.
11087 05:57:59.466990 Ending test lava.0_timesync-off (12379453_1.6.2.3.1), duration 0.06
11089 05:57:59.548233 + export TESTRUN_ID=1_kselftest-dt
11090 05:57:59.551012 + TESTRUN_ID=1_kselftest-dt
11091 05:57:59.554203 + cd /lava-12379453/0/tests/1_kselftest-dt
11092 05:57:59.557616 ++ cat uuid
11093 05:57:59.562127 + UUID=12379453_1.6.2.3.5
11094 05:57:59.562206 + set +x
11095 05:57:59.569128 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 12379453_1.6.2.3.5>
11096 05:57:59.569439 Received signal: <STARTRUN> 1_kselftest-dt 12379453_1.6.2.3.5
11097 05:57:59.569595 Starting test lava.1_kselftest-dt (12379453_1.6.2.3.5)
11098 05:57:59.569683 Skipping test definition patterns.
11099 05:57:59.572457 + cd ./automated/linux/kselftest/
11100 05:57:59.595359 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11101 05:57:59.638369 INFO: install_deps skipped
11102 05:57:59.757643 --2023-12-25 05:57:59-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11103 05:57:59.769891 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11104 05:57:59.902857 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11105 05:58:00.036765 HTTP request sent, awaiting response... 200 OK
11106 05:58:00.040381 Length: 2966180 (2.8M) [application/octet-stream]
11107 05:58:00.043297 Saving to: 'kselftest.tar.xz'
11108 05:58:00.043371
11109 05:58:00.043433
11110 05:58:00.303739 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11111 05:58:00.570614 kselftest.tar.xz 1%[ ] 47.81K 180KB/s
11112 05:58:00.840996 kselftest.tar.xz 7%[> ] 219.84K 413KB/s
11113 05:58:01.040637 kselftest.tar.xz 30%[=====> ] 897.66K 1.09MB/s
11114 05:58:01.307512 kselftest.tar.xz 51%[=========> ] 1.45M 1.45MB/s
11115 05:58:01.444984 kselftest.tar.xz 93%[=================> ] 2.65M 2.09MB/s
11116 05:58:01.451351 kselftest.tar.xz 100%[===================>] 2.83M 2.01MB/s in 1.4s
11117 05:58:01.451498
11118 05:58:01.710288 2023-12-25 05:58:01 (2.01 MB/s) - 'kselftest.tar.xz' saved [2966180/2966180]
11119 05:58:01.710430
11120 05:58:08.005672 skiplist:
11121 05:58:08.009117 ========================================
11122 05:58:08.012530 ========================================
11123 05:58:08.086189 ============== Tests to run ===============
11124 05:58:08.089119 ===========End Tests to run ===============
11125 05:58:08.094757 shardfile-dt fail
11126 05:58:08.121265 ./kselftest.sh: 131: cannot open /lava-12379453/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11127 05:58:08.124470 + ../../utils/send-to-lava.sh ./output/result.txt
11128 05:58:08.195982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11129 05:58:08.196118 + set +x
11130 05:58:08.196397 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11132 05:58:08.202657 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 12379453_1.6.2.3.5>
11133 05:58:08.202921 Received signal: <ENDRUN> 1_kselftest-dt 12379453_1.6.2.3.5
11134 05:58:08.203029 Ending use of test pattern.
11135 05:58:08.203108 Ending test lava.1_kselftest-dt (12379453_1.6.2.3.5), duration 8.63
11137 05:58:08.203514 ok: lava_test_shell seems to have completed
11138 05:58:08.203629 shardfile-dt: fail
11139 05:58:08.203756 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11140 05:58:08.203878 end: 3 lava-test-retry (duration 00:00:10) [common]
11141 05:58:08.204005 start: 4 finalize (timeout 00:07:24) [common]
11142 05:58:08.204137 start: 4.1 power-off (timeout 00:00:30) [common]
11143 05:58:08.204429 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11144 05:58:08.280706 >> Command sent successfully.
11145 05:58:08.283350 Returned 0 in 0 seconds
11146 05:58:08.383806 end: 4.1 power-off (duration 00:00:00) [common]
11148 05:58:08.384323 start: 4.2 read-feedback (timeout 00:07:24) [common]
11150 05:58:08.385052 Listened to connection for namespace 'common' for up to 1s
11151 05:58:09.385551 Finalising connection for namespace 'common'
11152 05:58:09.385780 Disconnecting from shell: Finalise
11153 05:58:09.385896 / #
11154 05:58:09.486255 end: 4.2 read-feedback (duration 00:00:01) [common]
11155 05:58:09.486505 end: 4 finalize (duration 00:00:01) [common]
11156 05:58:09.486666 Cleaning after the job
11157 05:58:09.486812 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/ramdisk
11158 05:58:09.490436 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/kernel
11159 05:58:09.507196 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/dtb
11160 05:58:09.507426 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/nfsrootfs
11161 05:58:09.606432 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379453/tftp-deploy-ry1yvk2f/modules
11162 05:58:09.613905 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12379453
11163 05:58:10.290416 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12379453
11164 05:58:10.290599 Job finished correctly