Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 17
- Kernel Errors: 38
- Errors: 0
1 05:51:31.203842 lava-dispatcher, installed at version: 2023.10
2 05:51:31.204060 start: 0 validate
3 05:51:31.204199 Start time: 2023-12-25 05:51:31.204191+00:00 (UTC)
4 05:51:31.204325 Using caching service: 'http://localhost/cache/?uri=%s'
5 05:51:31.204463 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 05:51:31.466832 Using caching service: 'http://localhost/cache/?uri=%s'
7 05:51:31.467019 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 05:51:31.468078 Using caching service: 'http://localhost/cache/?uri=%s'
9 05:51:31.468205 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 05:51:31.739760 Using caching service: 'http://localhost/cache/?uri=%s'
11 05:51:31.739945 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 05:51:32.261695 Using caching service: 'http://localhost/cache/?uri=%s'
13 05:51:32.261879 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 05:51:32.264183 validate duration: 1.06
16 05:51:32.264405 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:51:32.264504 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:51:32.264593 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:51:32.264717 Not decompressing ramdisk as can be used compressed.
20 05:51:32.264802 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 05:51:32.264870 saving as /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/ramdisk/initrd.cpio.gz
22 05:51:32.264935 total size: 4665395 (4 MB)
23 05:51:32.265970 progress 0 % (0 MB)
24 05:51:32.267509 progress 5 % (0 MB)
25 05:51:32.268809 progress 10 % (0 MB)
26 05:51:32.270122 progress 15 % (0 MB)
27 05:51:32.271378 progress 20 % (0 MB)
28 05:51:32.272615 progress 25 % (1 MB)
29 05:51:32.273901 progress 30 % (1 MB)
30 05:51:32.275186 progress 35 % (1 MB)
31 05:51:32.276538 progress 40 % (1 MB)
32 05:51:32.278148 progress 45 % (2 MB)
33 05:51:32.279531 progress 50 % (2 MB)
34 05:51:32.280862 progress 55 % (2 MB)
35 05:51:32.282146 progress 60 % (2 MB)
36 05:51:32.283427 progress 65 % (2 MB)
37 05:51:32.284699 progress 70 % (3 MB)
38 05:51:32.286074 progress 75 % (3 MB)
39 05:51:32.287359 progress 80 % (3 MB)
40 05:51:32.288805 progress 85 % (3 MB)
41 05:51:32.290196 progress 90 % (4 MB)
42 05:51:32.291504 progress 95 % (4 MB)
43 05:51:32.292960 progress 100 % (4 MB)
44 05:51:32.293124 4 MB downloaded in 0.03 s (157.85 MB/s)
45 05:51:32.293287 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:51:32.293578 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:51:32.293682 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:51:32.293797 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:51:32.293951 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 05:51:32.294031 saving as /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/kernel/Image
52 05:51:32.294192 total size: 50024960 (47 MB)
53 05:51:32.294288 No compression specified
54 05:51:32.295508 progress 0 % (0 MB)
55 05:51:32.309028 progress 5 % (2 MB)
56 05:51:32.322504 progress 10 % (4 MB)
57 05:51:32.335710 progress 15 % (7 MB)
58 05:51:32.349845 progress 20 % (9 MB)
59 05:51:32.363891 progress 25 % (11 MB)
60 05:51:32.377451 progress 30 % (14 MB)
61 05:51:32.391199 progress 35 % (16 MB)
62 05:51:32.404949 progress 40 % (19 MB)
63 05:51:32.418672 progress 45 % (21 MB)
64 05:51:32.432556 progress 50 % (23 MB)
65 05:51:32.445865 progress 55 % (26 MB)
66 05:51:32.459516 progress 60 % (28 MB)
67 05:51:32.473158 progress 65 % (31 MB)
68 05:51:32.486539 progress 70 % (33 MB)
69 05:51:32.499919 progress 75 % (35 MB)
70 05:51:32.513522 progress 80 % (38 MB)
71 05:51:32.527068 progress 85 % (40 MB)
72 05:51:32.540603 progress 90 % (42 MB)
73 05:51:32.554909 progress 95 % (45 MB)
74 05:51:32.568150 progress 100 % (47 MB)
75 05:51:32.568402 47 MB downloaded in 0.27 s (173.98 MB/s)
76 05:51:32.568557 end: 1.2.1 http-download (duration 00:00:00) [common]
78 05:51:32.568829 end: 1.2 download-retry (duration 00:00:00) [common]
79 05:51:32.568916 start: 1.3 download-retry (timeout 00:10:00) [common]
80 05:51:32.569006 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 05:51:32.569144 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 05:51:32.569234 saving as /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/dtb/mt8192-asurada-spherion-r0.dtb
83 05:51:32.569310 total size: 47278 (0 MB)
84 05:51:32.569372 No compression specified
85 05:51:32.570721 progress 69 % (0 MB)
86 05:51:32.571028 progress 100 % (0 MB)
87 05:51:32.571186 0 MB downloaded in 0.00 s (24.07 MB/s)
88 05:51:32.571310 end: 1.3.1 http-download (duration 00:00:00) [common]
90 05:51:32.571535 end: 1.3 download-retry (duration 00:00:00) [common]
91 05:51:32.571624 start: 1.4 download-retry (timeout 00:10:00) [common]
92 05:51:32.571708 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 05:51:32.571825 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 05:51:32.571924 saving as /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/nfsrootfs/full.rootfs.tar
95 05:51:32.571985 total size: 200813988 (191 MB)
96 05:51:32.572046 Using unxz to decompress xz
97 05:51:32.576585 progress 0 % (0 MB)
98 05:51:33.121646 progress 5 % (9 MB)
99 05:51:33.650591 progress 10 % (19 MB)
100 05:51:34.248091 progress 15 % (28 MB)
101 05:51:34.633559 progress 20 % (38 MB)
102 05:51:34.977872 progress 25 % (47 MB)
103 05:51:35.603001 progress 30 % (57 MB)
104 05:51:36.171974 progress 35 % (67 MB)
105 05:51:36.794658 progress 40 % (76 MB)
106 05:51:37.369093 progress 45 % (86 MB)
107 05:51:37.976450 progress 50 % (95 MB)
108 05:51:38.628891 progress 55 % (105 MB)
109 05:51:39.315373 progress 60 % (114 MB)
110 05:51:39.436916 progress 65 % (124 MB)
111 05:51:39.582053 progress 70 % (134 MB)
112 05:51:39.690894 progress 75 % (143 MB)
113 05:51:39.767046 progress 80 % (153 MB)
114 05:51:39.842813 progress 85 % (162 MB)
115 05:51:39.957043 progress 90 % (172 MB)
116 05:51:40.254655 progress 95 % (181 MB)
117 05:51:40.861351 progress 100 % (191 MB)
118 05:51:40.866914 191 MB downloaded in 8.29 s (23.09 MB/s)
119 05:51:40.867270 end: 1.4.1 http-download (duration 00:00:08) [common]
121 05:51:40.867694 end: 1.4 download-retry (duration 00:00:08) [common]
122 05:51:40.867817 start: 1.5 download-retry (timeout 00:09:51) [common]
123 05:51:40.867938 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 05:51:40.868136 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 05:51:40.868240 saving as /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/modules/modules.tar
126 05:51:40.868336 total size: 8619328 (8 MB)
127 05:51:40.868436 Using unxz to decompress xz
128 05:51:41.139842 progress 0 % (0 MB)
129 05:51:41.162555 progress 5 % (0 MB)
130 05:51:41.188283 progress 10 % (0 MB)
131 05:51:41.213216 progress 15 % (1 MB)
132 05:51:41.238515 progress 20 % (1 MB)
133 05:51:41.264020 progress 25 % (2 MB)
134 05:51:41.291151 progress 30 % (2 MB)
135 05:51:41.318772 progress 35 % (2 MB)
136 05:51:41.343905 progress 40 % (3 MB)
137 05:51:41.369706 progress 45 % (3 MB)
138 05:51:41.396190 progress 50 % (4 MB)
139 05:51:41.422125 progress 55 % (4 MB)
140 05:51:41.448280 progress 60 % (4 MB)
141 05:51:41.475208 progress 65 % (5 MB)
142 05:51:41.503396 progress 70 % (5 MB)
143 05:51:41.528206 progress 75 % (6 MB)
144 05:51:41.556067 progress 80 % (6 MB)
145 05:51:41.582856 progress 85 % (7 MB)
146 05:51:41.609038 progress 90 % (7 MB)
147 05:51:41.639930 progress 95 % (7 MB)
148 05:51:41.670920 progress 100 % (8 MB)
149 05:51:41.675771 8 MB downloaded in 0.81 s (10.18 MB/s)
150 05:51:41.676152 end: 1.5.1 http-download (duration 00:00:01) [common]
152 05:51:41.676564 end: 1.5 download-retry (duration 00:00:01) [common]
153 05:51:41.676697 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 05:51:41.676836 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 05:51:45.401818 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12379416/extract-nfsrootfs-69r2xshf
156 05:51:45.402031 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 05:51:45.402146 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 05:51:45.402342 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2
159 05:51:45.402486 makedir: /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin
160 05:51:45.402594 makedir: /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/tests
161 05:51:45.402698 makedir: /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/results
162 05:51:45.402805 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-add-keys
163 05:51:45.402960 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-add-sources
164 05:51:45.403097 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-background-process-start
165 05:51:45.403227 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-background-process-stop
166 05:51:45.403357 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-common-functions
167 05:51:45.403484 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-echo-ipv4
168 05:51:45.403611 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-install-packages
169 05:51:45.403737 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-installed-packages
170 05:51:45.403887 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-os-build
171 05:51:45.404016 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-probe-channel
172 05:51:45.404146 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-probe-ip
173 05:51:45.404273 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-target-ip
174 05:51:45.404402 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-target-mac
175 05:51:45.404528 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-target-storage
176 05:51:45.404659 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-test-case
177 05:51:45.404787 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-test-event
178 05:51:45.404916 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-test-feedback
179 05:51:45.405043 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-test-raise
180 05:51:45.405169 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-test-reference
181 05:51:45.405299 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-test-runner
182 05:51:45.405428 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-test-set
183 05:51:45.405570 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-test-shell
184 05:51:45.405700 Updating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-add-keys (debian)
185 05:51:45.405858 Updating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-add-sources (debian)
186 05:51:45.406001 Updating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-install-packages (debian)
187 05:51:45.406143 Updating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-installed-packages (debian)
188 05:51:45.406284 Updating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/bin/lava-os-build (debian)
189 05:51:45.406407 Creating /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/environment
190 05:51:45.406505 LAVA metadata
191 05:51:45.406579 - LAVA_JOB_ID=12379416
192 05:51:45.406643 - LAVA_DISPATCHER_IP=192.168.201.1
193 05:51:45.406770 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 05:51:45.406841 skipped lava-vland-overlay
195 05:51:45.406921 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 05:51:45.407004 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 05:51:45.407066 skipped lava-multinode-overlay
198 05:51:45.407154 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 05:51:45.407233 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 05:51:45.407314 Loading test definitions
201 05:51:45.407408 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 05:51:45.407480 Using /lava-12379416 at stage 0
203 05:51:45.407791 uuid=12379416_1.6.2.3.1 testdef=None
204 05:51:45.407881 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 05:51:45.407968 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 05:51:45.408437 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 05:51:45.408660 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 05:51:45.409234 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 05:51:45.409467 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 05:51:45.410243 runner path: /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/0/tests/0_timesync-off test_uuid 12379416_1.6.2.3.1
213 05:51:45.410405 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 05:51:45.410634 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 05:51:45.410710 Using /lava-12379416 at stage 0
217 05:51:45.410810 Fetching tests from https://github.com/kernelci/test-definitions.git
218 05:51:45.410889 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/0/tests/1_kselftest-rtc'
219 05:51:52.867243 Running '/usr/bin/git checkout kernelci.org
220 05:51:53.021658 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 05:51:53.022641 uuid=12379416_1.6.2.3.5 testdef=None
222 05:51:53.022844 end: 1.6.2.3.5 git-repo-action (duration 00:00:08) [common]
224 05:51:53.023240 start: 1.6.2.3.6 test-overlay (timeout 00:09:39) [common]
225 05:51:53.024297 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 05:51:53.024670 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:39) [common]
228 05:51:53.025964 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 05:51:53.026220 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:39) [common]
231 05:51:53.027663 runner path: /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/0/tests/1_kselftest-rtc test_uuid 12379416_1.6.2.3.5
232 05:51:53.027795 BOARD='mt8192-asurada-spherion-r0'
233 05:51:53.027890 BRANCH='cip'
234 05:51:53.027987 SKIPFILE='/dev/null'
235 05:51:53.028078 SKIP_INSTALL='True'
236 05:51:53.028165 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 05:51:53.028265 TST_CASENAME=''
238 05:51:53.028353 TST_CMDFILES='rtc'
239 05:51:53.028548 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 05:51:53.028851 Creating lava-test-runner.conf files
242 05:51:53.028924 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379416/lava-overlay-4wm1tbd2/lava-12379416/0 for stage 0
243 05:51:53.029027 - 0_timesync-off
244 05:51:53.029096 - 1_kselftest-rtc
245 05:51:53.029206 end: 1.6.2.3 test-definition (duration 00:00:08) [common]
246 05:51:53.029327 start: 1.6.2.4 compress-overlay (timeout 00:09:39) [common]
247 05:52:00.963794 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 05:52:00.963988 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:31) [common]
249 05:52:00.964116 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 05:52:00.964261 end: 1.6.2 lava-overlay (duration 00:00:16) [common]
251 05:52:00.964393 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:31) [common]
252 05:52:01.095730 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 05:52:01.096181 start: 1.6.4 extract-modules (timeout 00:09:31) [common]
254 05:52:01.096329 extracting modules file /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379416/extract-nfsrootfs-69r2xshf
255 05:52:01.324901 extracting modules file /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379416/extract-overlay-ramdisk-kz7bmpwk/ramdisk
256 05:52:01.567474 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 05:52:01.567672 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
258 05:52:01.567767 [common] Applying overlay to NFS
259 05:52:01.567838 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379416/compress-overlay-zu072w7z/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12379416/extract-nfsrootfs-69r2xshf
260 05:52:02.531903 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 05:52:02.532070 start: 1.6.6 configure-preseed-file (timeout 00:09:30) [common]
262 05:52:02.532173 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 05:52:02.532265 start: 1.6.7 compress-ramdisk (timeout 00:09:30) [common]
264 05:52:02.532346 Building ramdisk /var/lib/lava/dispatcher/tmp/12379416/extract-overlay-ramdisk-kz7bmpwk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12379416/extract-overlay-ramdisk-kz7bmpwk/ramdisk
265 05:52:02.874018 >> 119415 blocks
266 05:52:04.855331 rename /var/lib/lava/dispatcher/tmp/12379416/extract-overlay-ramdisk-kz7bmpwk/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/ramdisk/ramdisk.cpio.gz
267 05:52:04.855780 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 05:52:04.855905 start: 1.6.8 prepare-kernel (timeout 00:09:27) [common]
269 05:52:04.856026 start: 1.6.8.1 prepare-fit (timeout 00:09:27) [common]
270 05:52:04.856138 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/kernel/Image'
271 05:52:18.633756 Returned 0 in 13 seconds
272 05:52:18.734376 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/kernel/image.itb
273 05:52:19.110208 output: FIT description: Kernel Image image with one or more FDT blobs
274 05:52:19.110623 output: Created: Mon Dec 25 05:52:19 2023
275 05:52:19.110702 output: Image 0 (kernel-1)
276 05:52:19.110772 output: Description:
277 05:52:19.110839 output: Created: Mon Dec 25 05:52:19 2023
278 05:52:19.110903 output: Type: Kernel Image
279 05:52:19.110963 output: Compression: lzma compressed
280 05:52:19.111021 output: Data Size: 11481830 Bytes = 11212.72 KiB = 10.95 MiB
281 05:52:19.111081 output: Architecture: AArch64
282 05:52:19.111141 output: OS: Linux
283 05:52:19.111196 output: Load Address: 0x00000000
284 05:52:19.111253 output: Entry Point: 0x00000000
285 05:52:19.111309 output: Hash algo: crc32
286 05:52:19.111377 output: Hash value: a47c00f1
287 05:52:19.111447 output: Image 1 (fdt-1)
288 05:52:19.111500 output: Description: mt8192-asurada-spherion-r0
289 05:52:19.111553 output: Created: Mon Dec 25 05:52:19 2023
290 05:52:19.111607 output: Type: Flat Device Tree
291 05:52:19.111660 output: Compression: uncompressed
292 05:52:19.111713 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 05:52:19.111767 output: Architecture: AArch64
294 05:52:19.111820 output: Hash algo: crc32
295 05:52:19.111873 output: Hash value: cc4352de
296 05:52:19.111926 output: Image 2 (ramdisk-1)
297 05:52:19.111979 output: Description: unavailable
298 05:52:19.112031 output: Created: Mon Dec 25 05:52:19 2023
299 05:52:19.112083 output: Type: RAMDisk Image
300 05:52:19.112136 output: Compression: Unknown Compression
301 05:52:19.112189 output: Data Size: 17799094 Bytes = 17381.93 KiB = 16.97 MiB
302 05:52:19.112242 output: Architecture: AArch64
303 05:52:19.112295 output: OS: Linux
304 05:52:19.112348 output: Load Address: unavailable
305 05:52:19.112401 output: Entry Point: unavailable
306 05:52:19.112453 output: Hash algo: crc32
307 05:52:19.112506 output: Hash value: c07171dc
308 05:52:19.112558 output: Default Configuration: 'conf-1'
309 05:52:19.112610 output: Configuration 0 (conf-1)
310 05:52:19.112662 output: Description: mt8192-asurada-spherion-r0
311 05:52:19.112714 output: Kernel: kernel-1
312 05:52:19.112767 output: Init Ramdisk: ramdisk-1
313 05:52:19.112820 output: FDT: fdt-1
314 05:52:19.112872 output: Loadables: kernel-1
315 05:52:19.112924 output:
316 05:52:19.113162 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 05:52:19.113298 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 05:52:19.113453 end: 1.6 prepare-tftp-overlay (duration 00:00:37) [common]
319 05:52:19.113592 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:13) [common]
320 05:52:19.113676 No LXC device requested
321 05:52:19.113756 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 05:52:19.113859 start: 1.8 deploy-device-env (timeout 00:09:13) [common]
323 05:52:19.113979 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 05:52:19.114057 Checking files for TFTP limit of 4294967296 bytes.
325 05:52:19.114566 end: 1 tftp-deploy (duration 00:00:47) [common]
326 05:52:19.114669 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 05:52:19.114763 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 05:52:19.114913 substitutions:
329 05:52:19.114995 - {DTB}: 12379416/tftp-deploy-v3ap0rf0/dtb/mt8192-asurada-spherion-r0.dtb
330 05:52:19.115058 - {INITRD}: 12379416/tftp-deploy-v3ap0rf0/ramdisk/ramdisk.cpio.gz
331 05:52:19.115118 - {KERNEL}: 12379416/tftp-deploy-v3ap0rf0/kernel/Image
332 05:52:19.115177 - {LAVA_MAC}: None
333 05:52:19.115234 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12379416/extract-nfsrootfs-69r2xshf
334 05:52:19.115291 - {NFS_SERVER_IP}: 192.168.201.1
335 05:52:19.115347 - {PRESEED_CONFIG}: None
336 05:52:19.115402 - {PRESEED_LOCAL}: None
337 05:52:19.115457 - {RAMDISK}: 12379416/tftp-deploy-v3ap0rf0/ramdisk/ramdisk.cpio.gz
338 05:52:19.115512 - {ROOT_PART}: None
339 05:52:19.115566 - {ROOT}: None
340 05:52:19.115623 - {SERVER_IP}: 192.168.201.1
341 05:52:19.115677 - {TEE}: None
342 05:52:19.115734 Parsed boot commands:
343 05:52:19.115788 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 05:52:19.115971 Parsed boot commands: tftpboot 192.168.201.1 12379416/tftp-deploy-v3ap0rf0/kernel/image.itb 12379416/tftp-deploy-v3ap0rf0/kernel/cmdline
345 05:52:19.116061 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 05:52:19.116147 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 05:52:19.116238 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 05:52:19.116328 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 05:52:19.116406 Not connected, no need to disconnect.
350 05:52:19.116481 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 05:52:19.116560 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 05:52:19.116628 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 05:52:19.120833 Setting prompt string to ['lava-test: # ']
354 05:52:19.121258 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 05:52:19.121390 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 05:52:19.121520 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 05:52:19.121648 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 05:52:19.121843 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 05:52:24.255923 >> Command sent successfully.
360 05:52:24.258749 Returned 0 in 5 seconds
361 05:52:24.359149 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 05:52:24.359486 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 05:52:24.359603 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 05:52:24.359700 Setting prompt string to 'Starting depthcharge on Spherion...'
366 05:52:24.359771 Changing prompt to 'Starting depthcharge on Spherion...'
367 05:52:24.359843 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 05:52:24.360142 [Enter `^Ec?' for help]
369 05:52:24.530805
370 05:52:24.530951
371 05:52:24.531025 F0: 102B 0000
372 05:52:24.531096
373 05:52:24.531157 F3: 1001 0000 [0200]
374 05:52:24.531218
375 05:52:24.534410 F3: 1001 0000
376 05:52:24.534515
377 05:52:24.534619 F7: 102D 0000
378 05:52:24.534720
379 05:52:24.534814 F1: 0000 0000
380 05:52:24.538010
381 05:52:24.538095 V0: 0000 0000 [0001]
382 05:52:24.538191
383 05:52:24.538292 00: 0007 8000
384 05:52:24.538392
385 05:52:24.541749 01: 0000 0000
386 05:52:24.541836
387 05:52:24.541904 BP: 0C00 0209 [0000]
388 05:52:24.541967
389 05:52:24.545231 G0: 1182 0000
390 05:52:24.545316
391 05:52:24.545384 EC: 0000 0021 [4000]
392 05:52:24.545448
393 05:52:24.549021 S7: 0000 0000 [0000]
394 05:52:24.549107
395 05:52:24.549175 CC: 0000 0000 [0001]
396 05:52:24.549237
397 05:52:24.551868 T0: 0000 0040 [010F]
398 05:52:24.551954
399 05:52:24.552022 Jump to BL
400 05:52:24.552085
401 05:52:24.577972
402 05:52:24.578109
403 05:52:24.578178
404 05:52:24.585609 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 05:52:24.588774 ARM64: Exception handlers installed.
406 05:52:24.592920 ARM64: Testing exception
407 05:52:24.596320 ARM64: Done test exception
408 05:52:24.603392 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 05:52:24.610134 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 05:52:24.617319 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 05:52:24.628128 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 05:52:24.635210 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 05:52:24.645052 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 05:52:24.656014 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 05:52:24.662277 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 05:52:24.680602 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 05:52:24.683732 WDT: Last reset was cold boot
418 05:52:24.686906 SPI1(PAD0) initialized at 2873684 Hz
419 05:52:24.690595 SPI5(PAD0) initialized at 992727 Hz
420 05:52:24.693465 VBOOT: Loading verstage.
421 05:52:24.700115 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 05:52:24.703651 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 05:52:24.706874 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 05:52:24.710265 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 05:52:24.718129 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 05:52:24.724627 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 05:52:24.735383 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 05:52:24.735511
429 05:52:24.735583
430 05:52:24.819492 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 05:52:24.819696 ARM64: Exception handlers installed.
432 05:52:24.819798 ARM64: Testing exception
433 05:52:24.819935 ARM64: Done test exception
434 05:52:24.820041 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 05:52:24.820145 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 05:52:24.820296 Probing TPM: . done!
437 05:52:24.820405 TPM ready after 0 ms
438 05:52:24.820507 Connected to device vid:did:rid of 1ae0:0028:00
439 05:52:24.820587 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 05:52:24.830860 Initialized TPM device CR50 revision 0
441 05:52:24.843053 tlcl_send_startup: Startup return code is 0
442 05:52:24.843242 TPM: setup succeeded
443 05:52:24.854614 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 05:52:24.863268 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 05:52:24.875503 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 05:52:24.885160 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 05:52:24.888139 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 05:52:24.891751 in-header: 03 07 00 00 08 00 00 00
449 05:52:24.895643 in-data: aa e4 47 04 13 02 00 00
450 05:52:24.899285 Chrome EC: UHEPI supported
451 05:52:24.906656 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 05:52:24.910308 in-header: 03 9d 00 00 08 00 00 00
453 05:52:24.914075 in-data: 10 20 20 08 00 00 00 00
454 05:52:24.914162 Phase 1
455 05:52:24.917259 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 05:52:24.925121 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 05:52:24.928560 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 05:52:24.932283 Recovery requested (1009000e)
459 05:52:24.936872 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 05:52:24.944874 tlcl_extend: response is 0
461 05:52:24.953019 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 05:52:24.958944 tlcl_extend: response is 0
463 05:52:24.965472 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 05:52:24.986433 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 05:52:24.993571 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 05:52:24.993692
467 05:52:24.993763
468 05:52:25.004421 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 05:52:25.004539 ARM64: Exception handlers installed.
470 05:52:25.008181 ARM64: Testing exception
471 05:52:25.011246 ARM64: Done test exception
472 05:52:25.031640 pmic_efuse_setting: Set efuses in 11 msecs
473 05:52:25.035223 pmwrap_interface_init: Select PMIF_VLD_RDY
474 05:52:25.042326 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 05:52:25.045809 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 05:52:25.049718 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 05:52:25.057021 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 05:52:25.060425 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 05:52:25.064138 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 05:52:25.067907 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 05:52:25.074979 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 05:52:25.077963 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 05:52:25.084812 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 05:52:25.087892 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 05:52:25.091579 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 05:52:25.098118 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 05:52:25.104543 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 05:52:25.108292 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 05:52:25.114979 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 05:52:25.121653 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 05:52:25.127726 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 05:52:25.131522 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 05:52:25.139027 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 05:52:25.142448 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 05:52:25.149893 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 05:52:25.153543 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 05:52:25.160112 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 05:52:25.163779 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 05:52:25.170468 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 05:52:25.176868 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 05:52:25.180593 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 05:52:25.183880 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 05:52:25.190934 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 05:52:25.195358 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 05:52:25.201999 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 05:52:25.205417 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 05:52:25.209034 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 05:52:25.216884 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 05:52:25.219988 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 05:52:25.223769 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 05:52:25.230463 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 05:52:25.233672 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 05:52:25.240268 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 05:52:25.244005 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 05:52:25.247009 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 05:52:25.253708 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 05:52:25.257133 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 05:52:25.260616 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 05:52:25.264243 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 05:52:25.270532 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 05:52:25.274192 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 05:52:25.277138 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 05:52:25.280482 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 05:52:25.287028 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 05:52:25.293815 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 05:52:25.303755 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 05:52:25.307398 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 05:52:25.314009 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 05:52:25.323877 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 05:52:25.327485 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 05:52:25.333569 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 05:52:25.337190 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 05:52:25.344065 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xb
534 05:52:25.350762 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 05:52:25.354115 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 05:52:25.357083 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 05:52:25.368722 [RTC]rtc_get_frequency_meter,154: input=15, output=793
538 05:52:25.371775 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 05:52:25.378533 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 05:52:25.382208 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 05:52:25.385191 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 05:52:25.388492 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 05:52:25.392047 ADC[4]: Raw value=900000 ID=7
544 05:52:25.394987 ADC[3]: Raw value=213070 ID=1
545 05:52:25.398423 RAM Code: 0x71
546 05:52:25.401856 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 05:52:25.405374 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 05:52:25.416017 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 05:52:25.422196 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 05:52:25.425766 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 05:52:25.428881 in-header: 03 07 00 00 08 00 00 00
552 05:52:25.432341 in-data: aa e4 47 04 13 02 00 00
553 05:52:25.435492 Chrome EC: UHEPI supported
554 05:52:25.439214 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 05:52:25.443466 in-header: 03 d5 00 00 08 00 00 00
556 05:52:25.447244 in-data: 98 20 60 08 00 00 00 00
557 05:52:25.450358 MRC: failed to locate region type 0.
558 05:52:25.457730 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 05:52:25.460936 DRAM-K: Running full calibration
560 05:52:25.467615 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 05:52:25.467728 header.status = 0x0
562 05:52:25.471651 header.version = 0x6 (expected: 0x6)
563 05:52:25.475370 header.size = 0xd00 (expected: 0xd00)
564 05:52:25.475478 header.flags = 0x0
565 05:52:25.482089 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 05:52:25.500609 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
567 05:52:25.507430 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 05:52:25.510395 dram_init: ddr_geometry: 2
569 05:52:25.513743 [EMI] MDL number = 2
570 05:52:25.513840 [EMI] Get MDL freq = 0
571 05:52:25.517153 dram_init: ddr_type: 0
572 05:52:25.517269 is_discrete_lpddr4: 1
573 05:52:25.520655 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 05:52:25.520763
575 05:52:25.520872
576 05:52:25.523979 [Bian_co] ETT version 0.0.0.1
577 05:52:25.530446 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 05:52:25.530527
579 05:52:25.534049 dramc_set_vcore_voltage set vcore to 650000
580 05:52:25.534123 Read voltage for 800, 4
581 05:52:25.537105 Vio18 = 0
582 05:52:25.537214 Vcore = 650000
583 05:52:25.537308 Vdram = 0
584 05:52:25.540880 Vddq = 0
585 05:52:25.540986 Vmddr = 0
586 05:52:25.543854 dram_init: config_dvfs: 1
587 05:52:25.547636 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 05:52:25.554385 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 05:52:25.557406 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 05:52:25.560902 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 05:52:25.564484 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 05:52:25.567858 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 05:52:25.570990 MEM_TYPE=3, freq_sel=18
594 05:52:25.574598 sv_algorithm_assistance_LP4_1600
595 05:52:25.577560 ============ PULL DRAM RESETB DOWN ============
596 05:52:25.581208 ========== PULL DRAM RESETB DOWN end =========
597 05:52:25.589074 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 05:52:25.589194 ===================================
599 05:52:25.592177 LPDDR4 DRAM CONFIGURATION
600 05:52:25.595957 ===================================
601 05:52:25.596067 EX_ROW_EN[0] = 0x0
602 05:52:25.599938 EX_ROW_EN[1] = 0x0
603 05:52:25.600044 LP4Y_EN = 0x0
604 05:52:25.603162 WORK_FSP = 0x0
605 05:52:25.603268 WL = 0x2
606 05:52:25.607262 RL = 0x2
607 05:52:25.607382 BL = 0x2
608 05:52:25.610696 RPST = 0x0
609 05:52:25.610806 RD_PRE = 0x0
610 05:52:25.614819 WR_PRE = 0x1
611 05:52:25.614899 WR_PST = 0x0
612 05:52:25.618391 DBI_WR = 0x0
613 05:52:25.618496 DBI_RD = 0x0
614 05:52:25.622013 OTF = 0x1
615 05:52:25.625222 ===================================
616 05:52:25.628948 ===================================
617 05:52:25.629032 ANA top config
618 05:52:25.632513 ===================================
619 05:52:25.632597 DLL_ASYNC_EN = 0
620 05:52:25.636150 ALL_SLAVE_EN = 1
621 05:52:25.639883 NEW_RANK_MODE = 1
622 05:52:25.643433 DLL_IDLE_MODE = 1
623 05:52:25.643512 LP45_APHY_COMB_EN = 1
624 05:52:25.647727 TX_ODT_DIS = 1
625 05:52:25.651409 NEW_8X_MODE = 1
626 05:52:25.651515 ===================================
627 05:52:25.655142 ===================================
628 05:52:25.658897 data_rate = 1600
629 05:52:25.662371 CKR = 1
630 05:52:25.666159 DQ_P2S_RATIO = 8
631 05:52:25.669707 ===================================
632 05:52:25.669788 CA_P2S_RATIO = 8
633 05:52:25.672743 DQ_CA_OPEN = 0
634 05:52:25.676146 DQ_SEMI_OPEN = 0
635 05:52:25.679776 CA_SEMI_OPEN = 0
636 05:52:25.682623 CA_FULL_RATE = 0
637 05:52:25.686334 DQ_CKDIV4_EN = 1
638 05:52:25.686407 CA_CKDIV4_EN = 1
639 05:52:25.689387 CA_PREDIV_EN = 0
640 05:52:25.692977 PH8_DLY = 0
641 05:52:25.696002 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 05:52:25.699741 DQ_AAMCK_DIV = 4
643 05:52:25.699835 CA_AAMCK_DIV = 4
644 05:52:25.702777 CA_ADMCK_DIV = 4
645 05:52:25.705855 DQ_TRACK_CA_EN = 0
646 05:52:25.709775 CA_PICK = 800
647 05:52:25.712700 CA_MCKIO = 800
648 05:52:25.716083 MCKIO_SEMI = 0
649 05:52:25.719560 PLL_FREQ = 3068
650 05:52:25.719642 DQ_UI_PI_RATIO = 32
651 05:52:25.722763 CA_UI_PI_RATIO = 0
652 05:52:25.726138 ===================================
653 05:52:25.729263 ===================================
654 05:52:25.732879 memory_type:LPDDR4
655 05:52:25.736325 GP_NUM : 10
656 05:52:25.736428 SRAM_EN : 1
657 05:52:25.739328 MD32_EN : 0
658 05:52:25.743017 ===================================
659 05:52:25.745832 [ANA_INIT] >>>>>>>>>>>>>>
660 05:52:25.745930 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 05:52:25.749611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 05:52:25.752762 ===================================
663 05:52:25.755851 data_rate = 1600,PCW = 0X7600
664 05:52:25.759401 ===================================
665 05:52:25.762534 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 05:52:25.769861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 05:52:25.775918 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 05:52:25.779354 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 05:52:25.782968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 05:52:25.786419 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 05:52:25.790113 [ANA_INIT] flow start
672 05:52:25.790195 [ANA_INIT] PLL >>>>>>>>
673 05:52:25.793666 [ANA_INIT] PLL <<<<<<<<
674 05:52:25.793744 [ANA_INIT] MIDPI >>>>>>>>
675 05:52:25.797328 [ANA_INIT] MIDPI <<<<<<<<
676 05:52:25.800968 [ANA_INIT] DLL >>>>>>>>
677 05:52:25.801082 [ANA_INIT] flow end
678 05:52:25.804588 ============ LP4 DIFF to SE enter ============
679 05:52:25.808523 ============ LP4 DIFF to SE exit ============
680 05:52:25.812284 [ANA_INIT] <<<<<<<<<<<<<
681 05:52:25.815972 [Flow] Enable top DCM control >>>>>
682 05:52:25.819866 [Flow] Enable top DCM control <<<<<
683 05:52:25.823472 Enable DLL master slave shuffle
684 05:52:25.827638 ==============================================================
685 05:52:25.827753 Gating Mode config
686 05:52:25.834821 ==============================================================
687 05:52:25.838098 Config description:
688 05:52:25.844427 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 05:52:25.851406 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 05:52:25.857964 SELPH_MODE 0: By rank 1: By Phase
691 05:52:25.864537 ==============================================================
692 05:52:25.864617 GAT_TRACK_EN = 1
693 05:52:25.868372 RX_GATING_MODE = 2
694 05:52:25.871360 RX_GATING_TRACK_MODE = 2
695 05:52:25.874346 SELPH_MODE = 1
696 05:52:25.877961 PICG_EARLY_EN = 1
697 05:52:25.881446 VALID_LAT_VALUE = 1
698 05:52:25.887822 ==============================================================
699 05:52:25.891276 Enter into Gating configuration >>>>
700 05:52:25.894741 Exit from Gating configuration <<<<
701 05:52:25.897638 Enter into DVFS_PRE_config >>>>>
702 05:52:25.907610 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 05:52:25.911307 Exit from DVFS_PRE_config <<<<<
704 05:52:25.914328 Enter into PICG configuration >>>>
705 05:52:25.918077 Exit from PICG configuration <<<<
706 05:52:25.921122 [RX_INPUT] configuration >>>>>
707 05:52:25.921197 [RX_INPUT] configuration <<<<<
708 05:52:25.927627 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 05:52:25.934485 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 05:52:25.938036 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 05:52:25.944191 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 05:52:25.951156 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 05:52:25.958112 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 05:52:25.960895 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 05:52:25.964312 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 05:52:25.971355 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 05:52:25.974228 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 05:52:25.978006 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 05:52:25.981222 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 05:52:25.984416 ===================================
721 05:52:25.988261 LPDDR4 DRAM CONFIGURATION
722 05:52:25.991243 ===================================
723 05:52:25.994272 EX_ROW_EN[0] = 0x0
724 05:52:25.994386 EX_ROW_EN[1] = 0x0
725 05:52:25.997859 LP4Y_EN = 0x0
726 05:52:25.997962 WORK_FSP = 0x0
727 05:52:26.001294 WL = 0x2
728 05:52:26.001395 RL = 0x2
729 05:52:26.004733 BL = 0x2
730 05:52:26.004836 RPST = 0x0
731 05:52:26.007896 RD_PRE = 0x0
732 05:52:26.007998 WR_PRE = 0x1
733 05:52:26.011085 WR_PST = 0x0
734 05:52:26.011185 DBI_WR = 0x0
735 05:52:26.014731 DBI_RD = 0x0
736 05:52:26.014830 OTF = 0x1
737 05:52:26.017838 ===================================
738 05:52:26.024642 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 05:52:26.028421 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 05:52:26.031245 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 05:52:26.034828 ===================================
742 05:52:26.037757 LPDDR4 DRAM CONFIGURATION
743 05:52:26.041325 ===================================
744 05:52:26.044444 EX_ROW_EN[0] = 0x10
745 05:52:26.044551 EX_ROW_EN[1] = 0x0
746 05:52:26.048087 LP4Y_EN = 0x0
747 05:52:26.048197 WORK_FSP = 0x0
748 05:52:26.051613 WL = 0x2
749 05:52:26.051720 RL = 0x2
750 05:52:26.055078 BL = 0x2
751 05:52:26.055188 RPST = 0x0
752 05:52:26.058831 RD_PRE = 0x0
753 05:52:26.058911 WR_PRE = 0x1
754 05:52:26.058981 WR_PST = 0x0
755 05:52:26.062771 DBI_WR = 0x0
756 05:52:26.062878 DBI_RD = 0x0
757 05:52:26.066357 OTF = 0x1
758 05:52:26.070051 ===================================
759 05:52:26.073572 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 05:52:26.079308 nWR fixed to 40
761 05:52:26.083013 [ModeRegInit_LP4] CH0 RK0
762 05:52:26.083097 [ModeRegInit_LP4] CH0 RK1
763 05:52:26.086716 [ModeRegInit_LP4] CH1 RK0
764 05:52:26.086821 [ModeRegInit_LP4] CH1 RK1
765 05:52:26.090485 match AC timing 13
766 05:52:26.094191 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 05:52:26.097340 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 05:52:26.104601 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 05:52:26.108189 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 05:52:26.112627 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 05:52:26.112714 [EMI DOE] emi_dcm 0
772 05:52:26.120071 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 05:52:26.120164 ==
774 05:52:26.123747 Dram Type= 6, Freq= 0, CH_0, rank 0
775 05:52:26.127465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 05:52:26.127553 ==
777 05:52:26.131128 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 05:52:26.137805 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 05:52:26.147093 [CA 0] Center 38 (7~69) winsize 63
780 05:52:26.150759 [CA 1] Center 37 (7~68) winsize 62
781 05:52:26.154110 [CA 2] Center 35 (5~66) winsize 62
782 05:52:26.158247 [CA 3] Center 35 (5~66) winsize 62
783 05:52:26.161784 [CA 4] Center 34 (4~65) winsize 62
784 05:52:26.165188 [CA 5] Center 34 (4~65) winsize 62
785 05:52:26.165275
786 05:52:26.169051 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 05:52:26.169134
788 05:52:26.172926 [CATrainingPosCal] consider 1 rank data
789 05:52:26.173027 u2DelayCellTimex100 = 270/100 ps
790 05:52:26.176267 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 05:52:26.180450 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 05:52:26.183954 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 05:52:26.187608 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 05:52:26.191478 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 05:52:26.195209 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
796 05:52:26.195293
797 05:52:26.199367 CA PerBit enable=1, Macro0, CA PI delay=34
798 05:52:26.199451
799 05:52:26.203054 [CBTSetCACLKResult] CA Dly = 34
800 05:52:26.206180 CS Dly: 6 (0~37)
801 05:52:26.206279 ==
802 05:52:26.206359 Dram Type= 6, Freq= 0, CH_0, rank 1
803 05:52:26.214160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 05:52:26.214247 ==
805 05:52:26.217619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 05:52:26.224529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 05:52:26.233223 [CA 0] Center 38 (7~69) winsize 63
808 05:52:26.237010 [CA 1] Center 37 (7~68) winsize 62
809 05:52:26.240444 [CA 2] Center 35 (5~66) winsize 62
810 05:52:26.244037 [CA 3] Center 35 (5~66) winsize 62
811 05:52:26.247490 [CA 4] Center 34 (4~65) winsize 62
812 05:52:26.251146 [CA 5] Center 34 (4~65) winsize 62
813 05:52:26.251230
814 05:52:26.255064 [CmdBusTrainingLP45] Vref(ca) range 1: 28
815 05:52:26.255148
816 05:52:26.258693 [CATrainingPosCal] consider 2 rank data
817 05:52:26.258777 u2DelayCellTimex100 = 270/100 ps
818 05:52:26.262306 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 05:52:26.269599 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 05:52:26.269686 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 05:52:26.273424 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 05:52:26.276883 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 05:52:26.280703 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 05:52:26.280817
825 05:52:26.284657 CA PerBit enable=1, Macro0, CA PI delay=34
826 05:52:26.288143
827 05:52:26.288227 [CBTSetCACLKResult] CA Dly = 34
828 05:52:26.291964 CS Dly: 6 (0~38)
829 05:52:26.292049
830 05:52:26.295521 ----->DramcWriteLeveling(PI) begin...
831 05:52:26.295606 ==
832 05:52:26.299112 Dram Type= 6, Freq= 0, CH_0, rank 0
833 05:52:26.303100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 05:52:26.303184 ==
835 05:52:26.306279 Write leveling (Byte 0): 33 => 33
836 05:52:26.309823 Write leveling (Byte 1): 30 => 30
837 05:52:26.309920 DramcWriteLeveling(PI) end<-----
838 05:52:26.310004
839 05:52:26.313604 ==
840 05:52:26.313723 Dram Type= 6, Freq= 0, CH_0, rank 0
841 05:52:26.321525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 05:52:26.321611 ==
843 05:52:26.321692 [Gating] SW mode calibration
844 05:52:26.328427 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 05:52:26.336268 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 05:52:26.339338 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 05:52:26.343539 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 05:52:26.346922 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
849 05:52:26.350022 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 05:52:26.357291 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 05:52:26.360692 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 05:52:26.363746 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 05:52:26.370354 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 05:52:26.373979 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 05:52:26.377622 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 05:52:26.381802 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 05:52:26.385524 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 05:52:26.392133 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 05:52:26.395517 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 05:52:26.399323 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 05:52:26.406015 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 05:52:26.409427 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 05:52:26.413060 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 05:52:26.416142 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
865 05:52:26.423024 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
866 05:52:26.426220 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 05:52:26.429735 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 05:52:26.436020 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 05:52:26.439899 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 05:52:26.443081 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 05:52:26.449469 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 05:52:26.452647 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 05:52:26.456373 0 9 12 | B1->B0 | 2424 2f2f | 1 1 | (1 1) (1 1)
874 05:52:26.463022 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 05:52:26.466158 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 05:52:26.469605 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 05:52:26.476160 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 05:52:26.479234 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 05:52:26.482883 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 05:52:26.489740 0 10 8 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 1)
881 05:52:26.492912 0 10 12 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
882 05:52:26.495913 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 05:52:26.502618 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 05:52:26.506264 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 05:52:26.509346 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 05:52:26.515855 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 05:52:26.519353 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 05:52:26.522784 0 11 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
889 05:52:26.525630 0 11 12 | B1->B0 | 3737 4444 | 1 0 | (0 0) (0 0)
890 05:52:26.532433 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 05:52:26.536016 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 05:52:26.539117 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 05:52:26.546107 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 05:52:26.549025 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 05:52:26.552465 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
896 05:52:26.559384 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 05:52:26.562899 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
898 05:52:26.565956 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 05:52:26.572636 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 05:52:26.576297 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 05:52:26.579218 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 05:52:26.585885 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 05:52:26.589559 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 05:52:26.592475 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 05:52:26.599294 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 05:52:26.602314 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 05:52:26.605814 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 05:52:26.612686 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 05:52:26.615685 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 05:52:26.619265 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 05:52:26.625809 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 05:52:26.629362 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
913 05:52:26.632798 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
914 05:52:26.635688 Total UI for P1: 0, mck2ui 16
915 05:52:26.639337 best dqsien dly found for B0: ( 0, 14, 8)
916 05:52:26.642386 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 05:52:26.646035 Total UI for P1: 0, mck2ui 16
918 05:52:26.648955 best dqsien dly found for B1: ( 0, 14, 12)
919 05:52:26.652496 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
920 05:52:26.659130 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
921 05:52:26.659219
922 05:52:26.662695 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
923 05:52:26.665702 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
924 05:52:26.668827 [Gating] SW calibration Done
925 05:52:26.668919 ==
926 05:52:26.672591 Dram Type= 6, Freq= 0, CH_0, rank 0
927 05:52:26.675674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 05:52:26.675756 ==
929 05:52:26.675855 RX Vref Scan: 0
930 05:52:26.679254
931 05:52:26.679329 RX Vref 0 -> 0, step: 1
932 05:52:26.679392
933 05:52:26.682275 RX Delay -130 -> 252, step: 16
934 05:52:26.685604 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
935 05:52:26.689156 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
936 05:52:26.695963 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
937 05:52:26.699041 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
938 05:52:26.702005 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
939 05:52:26.705697 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
940 05:52:26.708872 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
941 05:52:26.715556 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
942 05:52:26.718940 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
943 05:52:26.722204 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
944 05:52:26.725716 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
945 05:52:26.728723 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
946 05:52:26.735317 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
947 05:52:26.739017 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
948 05:52:26.742414 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
949 05:52:26.745542 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
950 05:52:26.745646 ==
951 05:52:26.748971 Dram Type= 6, Freq= 0, CH_0, rank 0
952 05:52:26.755733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 05:52:26.755814 ==
954 05:52:26.755880 DQS Delay:
955 05:52:26.758756 DQS0 = 0, DQS1 = 0
956 05:52:26.758833 DQM Delay:
957 05:52:26.758911 DQM0 = 80, DQM1 = 70
958 05:52:26.762551 DQ Delay:
959 05:52:26.766003 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
960 05:52:26.768812 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
961 05:52:26.768949 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
962 05:52:26.775411 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 05:52:26.775498
964 05:52:26.775566
965 05:52:26.775630 ==
966 05:52:26.779110 Dram Type= 6, Freq= 0, CH_0, rank 0
967 05:52:26.783509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 05:52:26.783612 ==
969 05:52:26.783741
970 05:52:26.783835
971 05:52:26.783958 TX Vref Scan disable
972 05:52:26.787131 == TX Byte 0 ==
973 05:52:26.790670 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
974 05:52:26.793727 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
975 05:52:26.796801 == TX Byte 1 ==
976 05:52:26.800505 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
977 05:52:26.803450 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
978 05:52:26.807317 ==
979 05:52:26.810277 Dram Type= 6, Freq= 0, CH_0, rank 0
980 05:52:26.813334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 05:52:26.813436 ==
982 05:52:26.826450 TX Vref=22, minBit 9, minWin=26, winSum=431
983 05:52:26.829796 TX Vref=24, minBit 11, minWin=26, winSum=435
984 05:52:26.833096 TX Vref=26, minBit 14, minWin=26, winSum=440
985 05:52:26.836238 TX Vref=28, minBit 5, minWin=27, winSum=442
986 05:52:26.839373 TX Vref=30, minBit 12, minWin=26, winSum=442
987 05:52:26.846461 TX Vref=32, minBit 1, minWin=27, winSum=439
988 05:52:26.849418 [TxChooseVref] Worse bit 5, Min win 27, Win sum 442, Final Vref 28
989 05:52:26.849535
990 05:52:26.852982 Final TX Range 1 Vref 28
991 05:52:26.853067
992 05:52:26.853139 ==
993 05:52:26.856442 Dram Type= 6, Freq= 0, CH_0, rank 0
994 05:52:26.859807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 05:52:26.859893 ==
996 05:52:26.862736
997 05:52:26.862821
998 05:52:26.862888 TX Vref Scan disable
999 05:52:26.866316 == TX Byte 0 ==
1000 05:52:26.870000 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1001 05:52:26.872942 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1002 05:52:26.876516 == TX Byte 1 ==
1003 05:52:26.879969 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1004 05:52:26.886539 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1005 05:52:26.886627
1006 05:52:26.886694 [DATLAT]
1007 05:52:26.886757 Freq=800, CH0 RK0
1008 05:52:26.886818
1009 05:52:26.889518 DATLAT Default: 0xa
1010 05:52:26.889629 0, 0xFFFF, sum = 0
1011 05:52:26.893137 1, 0xFFFF, sum = 0
1012 05:52:26.893242 2, 0xFFFF, sum = 0
1013 05:52:26.896341 3, 0xFFFF, sum = 0
1014 05:52:26.896445 4, 0xFFFF, sum = 0
1015 05:52:26.899407 5, 0xFFFF, sum = 0
1016 05:52:26.903016 6, 0xFFFF, sum = 0
1017 05:52:26.903104 7, 0xFFFF, sum = 0
1018 05:52:26.906666 8, 0xFFFF, sum = 0
1019 05:52:26.906781 9, 0x0, sum = 1
1020 05:52:26.906888 10, 0x0, sum = 2
1021 05:52:26.909672 11, 0x0, sum = 3
1022 05:52:26.909758 12, 0x0, sum = 4
1023 05:52:26.912884 best_step = 10
1024 05:52:26.912969
1025 05:52:26.913041 ==
1026 05:52:26.916529 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 05:52:26.919610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 05:52:26.919704 ==
1029 05:52:26.923374 RX Vref Scan: 1
1030 05:52:26.923461
1031 05:52:26.923565 Set Vref Range= 32 -> 127
1032 05:52:26.926307
1033 05:52:26.926391 RX Vref 32 -> 127, step: 1
1034 05:52:26.926459
1035 05:52:26.929942 RX Delay -111 -> 252, step: 8
1036 05:52:26.930015
1037 05:52:26.933089 Set Vref, RX VrefLevel [Byte0]: 32
1038 05:52:26.936433 [Byte1]: 32
1039 05:52:26.936540
1040 05:52:26.939654 Set Vref, RX VrefLevel [Byte0]: 33
1041 05:52:26.943059 [Byte1]: 33
1042 05:52:26.946800
1043 05:52:26.946875 Set Vref, RX VrefLevel [Byte0]: 34
1044 05:52:26.950372 [Byte1]: 34
1045 05:52:26.954621
1046 05:52:26.954694 Set Vref, RX VrefLevel [Byte0]: 35
1047 05:52:26.958365 [Byte1]: 35
1048 05:52:26.962061
1049 05:52:26.962141 Set Vref, RX VrefLevel [Byte0]: 36
1050 05:52:26.965672 [Byte1]: 36
1051 05:52:26.969702
1052 05:52:26.969772 Set Vref, RX VrefLevel [Byte0]: 37
1053 05:52:26.973186 [Byte1]: 37
1054 05:52:26.977547
1055 05:52:26.977622 Set Vref, RX VrefLevel [Byte0]: 38
1056 05:52:26.980986 [Byte1]: 38
1057 05:52:26.985165
1058 05:52:26.985270 Set Vref, RX VrefLevel [Byte0]: 39
1059 05:52:26.988546 [Byte1]: 39
1060 05:52:26.993165
1061 05:52:26.993239 Set Vref, RX VrefLevel [Byte0]: 40
1062 05:52:26.996238 [Byte1]: 40
1063 05:52:27.000767
1064 05:52:27.000839 Set Vref, RX VrefLevel [Byte0]: 41
1065 05:52:27.003669 [Byte1]: 41
1066 05:52:27.007909
1067 05:52:27.008007 Set Vref, RX VrefLevel [Byte0]: 42
1068 05:52:27.011562 [Byte1]: 42
1069 05:52:27.015879
1070 05:52:27.015954 Set Vref, RX VrefLevel [Byte0]: 43
1071 05:52:27.018909 [Byte1]: 43
1072 05:52:27.023292
1073 05:52:27.023367 Set Vref, RX VrefLevel [Byte0]: 44
1074 05:52:27.026977 [Byte1]: 44
1075 05:52:27.031253
1076 05:52:27.031352 Set Vref, RX VrefLevel [Byte0]: 45
1077 05:52:27.034323 [Byte1]: 45
1078 05:52:27.039272
1079 05:52:27.039349 Set Vref, RX VrefLevel [Byte0]: 46
1080 05:52:27.042326 [Byte1]: 46
1081 05:52:27.047303
1082 05:52:27.047386 Set Vref, RX VrefLevel [Byte0]: 47
1083 05:52:27.050632 [Byte1]: 47
1084 05:52:27.054220
1085 05:52:27.054315 Set Vref, RX VrefLevel [Byte0]: 48
1086 05:52:27.057839 [Byte1]: 48
1087 05:52:27.061643
1088 05:52:27.061744 Set Vref, RX VrefLevel [Byte0]: 49
1089 05:52:27.065345 [Byte1]: 49
1090 05:52:27.069606
1091 05:52:27.069679 Set Vref, RX VrefLevel [Byte0]: 50
1092 05:52:27.073353 [Byte1]: 50
1093 05:52:27.076987
1094 05:52:27.077060 Set Vref, RX VrefLevel [Byte0]: 51
1095 05:52:27.079914 [Byte1]: 51
1096 05:52:27.084467
1097 05:52:27.084548 Set Vref, RX VrefLevel [Byte0]: 52
1098 05:52:27.087863 [Byte1]: 52
1099 05:52:27.092030
1100 05:52:27.092110 Set Vref, RX VrefLevel [Byte0]: 53
1101 05:52:27.095663 [Byte1]: 53
1102 05:52:27.099860
1103 05:52:27.100006 Set Vref, RX VrefLevel [Byte0]: 54
1104 05:52:27.102988 [Byte1]: 54
1105 05:52:27.107235
1106 05:52:27.107309 Set Vref, RX VrefLevel [Byte0]: 55
1107 05:52:27.110908 [Byte1]: 55
1108 05:52:27.114918
1109 05:52:27.114993 Set Vref, RX VrefLevel [Byte0]: 56
1110 05:52:27.118511 [Byte1]: 56
1111 05:52:27.122683
1112 05:52:27.122756 Set Vref, RX VrefLevel [Byte0]: 57
1113 05:52:27.126391 [Byte1]: 57
1114 05:52:27.130746
1115 05:52:27.130846 Set Vref, RX VrefLevel [Byte0]: 58
1116 05:52:27.133815 [Byte1]: 58
1117 05:52:27.138037
1118 05:52:27.138137 Set Vref, RX VrefLevel [Byte0]: 59
1119 05:52:27.141759 [Byte1]: 59
1120 05:52:27.145996
1121 05:52:27.146071 Set Vref, RX VrefLevel [Byte0]: 60
1122 05:52:27.149066 [Byte1]: 60
1123 05:52:27.153119
1124 05:52:27.153225 Set Vref, RX VrefLevel [Byte0]: 61
1125 05:52:27.156528 [Byte1]: 61
1126 05:52:27.160767
1127 05:52:27.160912 Set Vref, RX VrefLevel [Byte0]: 62
1128 05:52:27.164292 [Byte1]: 62
1129 05:52:27.168637
1130 05:52:27.168735 Set Vref, RX VrefLevel [Byte0]: 63
1131 05:52:27.172357 [Byte1]: 63
1132 05:52:27.176607
1133 05:52:27.176711 Set Vref, RX VrefLevel [Byte0]: 64
1134 05:52:27.179623 [Byte1]: 64
1135 05:52:27.183886
1136 05:52:27.184002 Set Vref, RX VrefLevel [Byte0]: 65
1137 05:52:27.187448 [Byte1]: 65
1138 05:52:27.191666
1139 05:52:27.191774 Set Vref, RX VrefLevel [Byte0]: 66
1140 05:52:27.194649 [Byte1]: 66
1141 05:52:27.199399
1142 05:52:27.199470 Set Vref, RX VrefLevel [Byte0]: 67
1143 05:52:27.202253 [Byte1]: 67
1144 05:52:27.206663
1145 05:52:27.206760 Set Vref, RX VrefLevel [Byte0]: 68
1146 05:52:27.210050 [Byte1]: 68
1147 05:52:27.214562
1148 05:52:27.214676 Set Vref, RX VrefLevel [Byte0]: 69
1149 05:52:27.217968 [Byte1]: 69
1150 05:52:27.222245
1151 05:52:27.222319 Set Vref, RX VrefLevel [Byte0]: 70
1152 05:52:27.225444 [Byte1]: 70
1153 05:52:27.229812
1154 05:52:27.229900 Set Vref, RX VrefLevel [Byte0]: 71
1155 05:52:27.233316 [Byte1]: 71
1156 05:52:27.237447
1157 05:52:27.237568 Set Vref, RX VrefLevel [Byte0]: 72
1158 05:52:27.241036 [Byte1]: 72
1159 05:52:27.245330
1160 05:52:27.245431 Set Vref, RX VrefLevel [Byte0]: 73
1161 05:52:27.248393 [Byte1]: 73
1162 05:52:27.252722
1163 05:52:27.252822 Set Vref, RX VrefLevel [Byte0]: 74
1164 05:52:27.256459 [Byte1]: 74
1165 05:52:27.260186
1166 05:52:27.260291 Set Vref, RX VrefLevel [Byte0]: 75
1167 05:52:27.263704 [Byte1]: 75
1168 05:52:27.268230
1169 05:52:27.268329 Set Vref, RX VrefLevel [Byte0]: 76
1170 05:52:27.271545 [Byte1]: 76
1171 05:52:27.275915
1172 05:52:27.276013 Set Vref, RX VrefLevel [Byte0]: 77
1173 05:52:27.279068 [Byte1]: 77
1174 05:52:27.283252
1175 05:52:27.283355 Set Vref, RX VrefLevel [Byte0]: 78
1176 05:52:27.286831 [Byte1]: 78
1177 05:52:27.290974
1178 05:52:27.291056 Set Vref, RX VrefLevel [Byte0]: 79
1179 05:52:27.294539 [Byte1]: 79
1180 05:52:27.298780
1181 05:52:27.298879 Set Vref, RX VrefLevel [Byte0]: 80
1182 05:52:27.301935 [Byte1]: 80
1183 05:52:27.306442
1184 05:52:27.306544 Set Vref, RX VrefLevel [Byte0]: 81
1185 05:52:27.309428 [Byte1]: 81
1186 05:52:27.314173
1187 05:52:27.314270 Final RX Vref Byte 0 = 59 to rank0
1188 05:52:27.317093 Final RX Vref Byte 1 = 57 to rank0
1189 05:52:27.320429 Final RX Vref Byte 0 = 59 to rank1
1190 05:52:27.324113 Final RX Vref Byte 1 = 57 to rank1==
1191 05:52:27.327174 Dram Type= 6, Freq= 0, CH_0, rank 0
1192 05:52:27.330782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1193 05:52:27.334243 ==
1194 05:52:27.334328 DQS Delay:
1195 05:52:27.334395 DQS0 = 0, DQS1 = 0
1196 05:52:27.337687 DQM Delay:
1197 05:52:27.337771 DQM0 = 82, DQM1 = 68
1198 05:52:27.340554 DQ Delay:
1199 05:52:27.340637 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1200 05:52:27.343809 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1201 05:52:27.347027 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1202 05:52:27.350655 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1203 05:52:27.353793
1204 05:52:27.353876
1205 05:52:27.360384 [DQSOSCAuto] RK0, (LSB)MR18= 0x2222, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1206 05:52:27.363976 CH0 RK0: MR19=606, MR18=2222
1207 05:52:27.370732 CH0_RK0: MR19=0x606, MR18=0x2222, DQSOSC=401, MR23=63, INC=91, DEC=61
1208 05:52:27.370817
1209 05:52:27.374163 ----->DramcWriteLeveling(PI) begin...
1210 05:52:27.374247 ==
1211 05:52:27.377609 Dram Type= 6, Freq= 0, CH_0, rank 1
1212 05:52:27.380977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1213 05:52:27.381062 ==
1214 05:52:27.384337 Write leveling (Byte 0): 31 => 31
1215 05:52:27.387614 Write leveling (Byte 1): 31 => 31
1216 05:52:27.390678 DramcWriteLeveling(PI) end<-----
1217 05:52:27.390761
1218 05:52:27.390827 ==
1219 05:52:27.394400 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 05:52:27.397357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1221 05:52:27.397441 ==
1222 05:52:27.401042 [Gating] SW mode calibration
1223 05:52:27.407246 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1224 05:52:27.414445 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1225 05:52:27.417428 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1226 05:52:27.420941 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1227 05:52:27.427483 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1228 05:52:27.430602 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1229 05:52:27.434285 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 05:52:27.440857 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 05:52:27.443991 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 05:52:27.447567 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 05:52:27.450627 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 05:52:27.494968 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 05:52:27.495576 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 05:52:27.495847 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 05:52:27.496105 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 05:52:27.496174 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 05:52:27.496237 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 05:52:27.496308 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 05:52:27.496369 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 05:52:27.496438 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1243 05:52:27.496499 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1244 05:52:27.538584 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 05:52:27.539195 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 05:52:27.539283 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 05:52:27.539550 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 05:52:27.539632 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 05:52:27.539700 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 05:52:27.539776 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 05:52:27.539840 0 9 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
1252 05:52:27.540474 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1253 05:52:27.540571 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 05:52:27.543558 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 05:52:27.550028 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 05:52:27.553142 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 05:52:27.556756 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 05:52:27.562936 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
1259 05:52:27.566555 0 10 8 | B1->B0 | 2f2f 2525 | 1 0 | (1 1) (0 0)
1260 05:52:27.569929 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 05:52:27.576804 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 05:52:27.579665 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 05:52:27.583108 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 05:52:27.590228 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 05:52:27.593299 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 05:52:27.596815 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1267 05:52:27.603257 0 11 8 | B1->B0 | 2929 3636 | 0 0 | (0 0) (0 0)
1268 05:52:27.606374 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1269 05:52:27.609885 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 05:52:27.613617 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 05:52:27.621203 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 05:52:27.624836 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 05:52:27.628555 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 05:52:27.631942 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 05:52:27.635639 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1276 05:52:27.642698 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 05:52:27.646335 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 05:52:27.649430 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 05:52:27.652943 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 05:52:27.659269 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 05:52:27.662691 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 05:52:27.666401 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 05:52:27.672620 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 05:52:27.676070 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 05:52:27.679710 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 05:52:27.686263 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 05:52:27.689744 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 05:52:27.692536 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 05:52:27.699735 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 05:52:27.702817 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1291 05:52:27.706182 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1292 05:52:27.712837 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1293 05:52:27.712946 Total UI for P1: 0, mck2ui 16
1294 05:52:27.719570 best dqsien dly found for B0: ( 0, 14, 6)
1295 05:52:27.719667 Total UI for P1: 0, mck2ui 16
1296 05:52:27.726097 best dqsien dly found for B1: ( 0, 14, 10)
1297 05:52:27.729197 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1298 05:52:27.732709 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1299 05:52:27.732809
1300 05:52:27.736356 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1301 05:52:27.739319 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1302 05:52:27.742476 [Gating] SW calibration Done
1303 05:52:27.742553 ==
1304 05:52:27.746201 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 05:52:27.749097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 05:52:27.749196 ==
1307 05:52:27.752608 RX Vref Scan: 0
1308 05:52:27.752751
1309 05:52:27.752856 RX Vref 0 -> 0, step: 1
1310 05:52:27.753006
1311 05:52:27.756052 RX Delay -130 -> 252, step: 16
1312 05:52:27.759447 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1313 05:52:27.765912 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1314 05:52:27.769031 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1315 05:52:27.772509 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1316 05:52:27.775978 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1317 05:52:27.779463 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1318 05:52:27.786282 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1319 05:52:27.789294 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1320 05:52:27.792797 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1321 05:52:27.795835 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1322 05:52:27.799731 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1323 05:52:27.806308 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1324 05:52:27.809161 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1325 05:52:27.812730 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1326 05:52:27.816177 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1327 05:52:27.819399 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1328 05:52:27.822918 ==
1329 05:52:27.823021 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 05:52:27.829646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 05:52:27.829731 ==
1332 05:52:27.829817 DQS Delay:
1333 05:52:27.832759 DQS0 = 0, DQS1 = 0
1334 05:52:27.832842 DQM Delay:
1335 05:52:27.836306 DQM0 = 78, DQM1 = 69
1336 05:52:27.836413 DQ Delay:
1337 05:52:27.839152 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =77
1338 05:52:27.842708 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1339 05:52:27.845755 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1340 05:52:27.849442 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1341 05:52:27.849580
1342 05:52:27.849671
1343 05:52:27.849734 ==
1344 05:52:27.852480 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 05:52:27.856187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 05:52:27.856310 ==
1347 05:52:27.856418
1348 05:52:27.856519
1349 05:52:27.859166 TX Vref Scan disable
1350 05:52:27.862184 == TX Byte 0 ==
1351 05:52:27.865706 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1352 05:52:27.868921 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1353 05:52:27.872227 == TX Byte 1 ==
1354 05:52:27.875543 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1355 05:52:27.879059 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1356 05:52:27.879154 ==
1357 05:52:27.882539 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 05:52:27.886005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 05:52:27.888902 ==
1360 05:52:27.899791 TX Vref=22, minBit 11, minWin=26, winSum=436
1361 05:52:27.903395 TX Vref=24, minBit 1, minWin=27, winSum=438
1362 05:52:27.906854 TX Vref=26, minBit 1, minWin=27, winSum=441
1363 05:52:27.909694 TX Vref=28, minBit 1, minWin=27, winSum=443
1364 05:52:27.913674 TX Vref=30, minBit 11, minWin=26, winSum=440
1365 05:52:27.919990 TX Vref=32, minBit 10, minWin=27, winSum=444
1366 05:52:27.923456 [TxChooseVref] Worse bit 10, Min win 27, Win sum 444, Final Vref 32
1367 05:52:27.923597
1368 05:52:27.926359 Final TX Range 1 Vref 32
1369 05:52:27.926487
1370 05:52:27.926603 ==
1371 05:52:27.929564 Dram Type= 6, Freq= 0, CH_0, rank 1
1372 05:52:27.936484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 05:52:27.936623 ==
1374 05:52:27.936742
1375 05:52:27.936858
1376 05:52:27.936971 TX Vref Scan disable
1377 05:52:27.940129 == TX Byte 0 ==
1378 05:52:27.943615 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1379 05:52:27.950168 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1380 05:52:27.950317 == TX Byte 1 ==
1381 05:52:27.953359 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1382 05:52:27.960380 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1383 05:52:27.960526
1384 05:52:27.960652 [DATLAT]
1385 05:52:27.960770 Freq=800, CH0 RK1
1386 05:52:27.960891
1387 05:52:27.963409 DATLAT Default: 0xa
1388 05:52:27.963545 0, 0xFFFF, sum = 0
1389 05:52:27.966561 1, 0xFFFF, sum = 0
1390 05:52:27.966699 2, 0xFFFF, sum = 0
1391 05:52:27.970192 3, 0xFFFF, sum = 0
1392 05:52:27.973741 4, 0xFFFF, sum = 0
1393 05:52:27.973884 5, 0xFFFF, sum = 0
1394 05:52:27.976883 6, 0xFFFF, sum = 0
1395 05:52:27.977022 7, 0xFFFF, sum = 0
1396 05:52:27.980256 8, 0xFFFF, sum = 0
1397 05:52:27.980393 9, 0x0, sum = 1
1398 05:52:27.980515 10, 0x0, sum = 2
1399 05:52:27.983251 11, 0x0, sum = 3
1400 05:52:27.983388 12, 0x0, sum = 4
1401 05:52:27.986647 best_step = 10
1402 05:52:27.986780
1403 05:52:27.986902 ==
1404 05:52:27.989944 Dram Type= 6, Freq= 0, CH_0, rank 1
1405 05:52:27.993460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 05:52:27.993602 ==
1407 05:52:27.997096 RX Vref Scan: 0
1408 05:52:27.997231
1409 05:52:27.997353 RX Vref 0 -> 0, step: 1
1410 05:52:27.997471
1411 05:52:27.999993 RX Delay -111 -> 252, step: 8
1412 05:52:28.007253 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1413 05:52:28.010301 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1414 05:52:28.013973 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1415 05:52:28.016894 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1416 05:52:28.020238 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1417 05:52:28.026818 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1418 05:52:28.030261 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1419 05:52:28.033912 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1420 05:52:28.037266 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1421 05:52:28.040589 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1422 05:52:28.047138 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1423 05:52:28.050626 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1424 05:52:28.053627 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1425 05:52:28.057289 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1426 05:52:28.060217 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1427 05:52:28.066915 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1428 05:52:28.067055 ==
1429 05:52:28.070422 Dram Type= 6, Freq= 0, CH_0, rank 1
1430 05:52:28.073427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1431 05:52:28.073571 ==
1432 05:52:28.073696 DQS Delay:
1433 05:52:28.076935 DQS0 = 0, DQS1 = 0
1434 05:52:28.077068 DQM Delay:
1435 05:52:28.080508 DQM0 = 79, DQM1 = 69
1436 05:52:28.080643 DQ Delay:
1437 05:52:28.083483 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1438 05:52:28.087044 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =88
1439 05:52:28.090385 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =60
1440 05:52:28.093713 DQ12 =80, DQ13 =72, DQ14 =80, DQ15 =76
1441 05:52:28.093847
1442 05:52:28.093972
1443 05:52:28.100249 [DQSOSCAuto] RK1, (LSB)MR18= 0x411c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1444 05:52:28.103496 CH0 RK1: MR19=606, MR18=411C
1445 05:52:28.110503 CH0_RK1: MR19=0x606, MR18=0x411C, DQSOSC=393, MR23=63, INC=95, DEC=63
1446 05:52:28.113584 [RxdqsGatingPostProcess] freq 800
1447 05:52:28.120172 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1448 05:52:28.123744 Pre-setting of DQS Precalculation
1449 05:52:28.127162 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1450 05:52:28.127300 ==
1451 05:52:28.130446 Dram Type= 6, Freq= 0, CH_1, rank 0
1452 05:52:28.133743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1453 05:52:28.133880 ==
1454 05:52:28.140481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1455 05:52:28.146902 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1456 05:52:28.154996 [CA 0] Center 36 (6~66) winsize 61
1457 05:52:28.158585 [CA 1] Center 36 (6~67) winsize 62
1458 05:52:28.162342 [CA 2] Center 34 (4~65) winsize 62
1459 05:52:28.165368 [CA 3] Center 34 (4~64) winsize 61
1460 05:52:28.168888 [CA 4] Center 34 (4~65) winsize 62
1461 05:52:28.171765 [CA 5] Center 34 (4~64) winsize 61
1462 05:52:28.171902
1463 05:52:28.175414 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1464 05:52:28.175563
1465 05:52:28.178849 [CATrainingPosCal] consider 1 rank data
1466 05:52:28.181753 u2DelayCellTimex100 = 270/100 ps
1467 05:52:28.185366 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1468 05:52:28.188416 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1469 05:52:28.194973 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1470 05:52:28.198566 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1471 05:52:28.202056 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1472 05:52:28.204906 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1473 05:52:28.205038
1474 05:52:28.208315 CA PerBit enable=1, Macro0, CA PI delay=34
1475 05:52:28.208462
1476 05:52:28.211897 [CBTSetCACLKResult] CA Dly = 34
1477 05:52:28.212049 CS Dly: 5 (0~36)
1478 05:52:28.215302 ==
1479 05:52:28.215435 Dram Type= 6, Freq= 0, CH_1, rank 1
1480 05:52:28.221923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1481 05:52:28.222061 ==
1482 05:52:28.224943 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1483 05:52:28.231575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1484 05:52:28.241481 [CA 0] Center 37 (7~67) winsize 61
1485 05:52:28.244633 [CA 1] Center 36 (6~67) winsize 62
1486 05:52:28.248149 [CA 2] Center 35 (5~65) winsize 61
1487 05:52:28.251472 [CA 3] Center 34 (4~64) winsize 61
1488 05:52:28.254874 [CA 4] Center 34 (4~65) winsize 62
1489 05:52:28.258045 [CA 5] Center 33 (3~64) winsize 62
1490 05:52:28.258185
1491 05:52:28.261110 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1492 05:52:28.261248
1493 05:52:28.264665 [CATrainingPosCal] consider 2 rank data
1494 05:52:28.268158 u2DelayCellTimex100 = 270/100 ps
1495 05:52:28.271247 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1496 05:52:28.274861 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1497 05:52:28.278505 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1498 05:52:28.282615 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1499 05:52:28.286253 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1500 05:52:28.289855 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1501 05:52:28.290000
1502 05:52:28.292912 CA PerBit enable=1, Macro0, CA PI delay=34
1503 05:52:28.296657
1504 05:52:28.296743 [CBTSetCACLKResult] CA Dly = 34
1505 05:52:28.300313 CS Dly: 6 (0~38)
1506 05:52:28.300418
1507 05:52:28.303998 ----->DramcWriteLeveling(PI) begin...
1508 05:52:28.304105 ==
1509 05:52:28.307740 Dram Type= 6, Freq= 0, CH_1, rank 0
1510 05:52:28.311238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1511 05:52:28.311335 ==
1512 05:52:28.314840 Write leveling (Byte 0): 29 => 29
1513 05:52:28.318039 Write leveling (Byte 1): 30 => 30
1514 05:52:28.321432 DramcWriteLeveling(PI) end<-----
1515 05:52:28.321555
1516 05:52:28.321641 ==
1517 05:52:28.324521 Dram Type= 6, Freq= 0, CH_1, rank 0
1518 05:52:28.328114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1519 05:52:28.328199 ==
1520 05:52:28.331242 [Gating] SW mode calibration
1521 05:52:28.338262 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1522 05:52:28.341283 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1523 05:52:28.347960 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1524 05:52:28.351307 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1525 05:52:28.354813 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1526 05:52:28.361406 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 05:52:28.364493 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 05:52:28.367804 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 05:52:28.374693 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 05:52:28.378163 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 05:52:28.381517 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 05:52:28.387957 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 05:52:28.391532 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 05:52:28.394598 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 05:52:28.401192 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 05:52:28.404678 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 05:52:28.408243 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 05:52:28.414789 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 05:52:28.418259 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 05:52:28.421149 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1541 05:52:28.428079 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1542 05:52:28.431098 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 05:52:28.434701 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 05:52:28.437613 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 05:52:28.444289 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 05:52:28.448002 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 05:52:28.451501 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 05:52:28.457371 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 05:52:28.460897 0 9 8 | B1->B0 | 2525 2626 | 1 1 | (1 1) (1 1)
1550 05:52:28.464533 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 05:52:28.471249 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 05:52:28.474268 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 05:52:28.477899 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 05:52:28.484225 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 05:52:28.487948 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 05:52:28.490957 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 05:52:28.497510 0 10 8 | B1->B0 | 2e2e 2f2f | 1 0 | (1 0) (1 0)
1558 05:52:28.500687 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 05:52:28.504254 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 05:52:28.510859 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 05:52:28.514452 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 05:52:28.517441 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 05:52:28.524248 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 05:52:28.527742 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 05:52:28.531287 0 11 8 | B1->B0 | 3434 3737 | 0 0 | (0 0) (0 0)
1566 05:52:28.537624 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 05:52:28.541145 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 05:52:28.544606 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 05:52:28.547670 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 05:52:28.554304 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 05:52:28.558020 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 05:52:28.561010 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 05:52:28.568006 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1574 05:52:28.571144 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 05:52:28.574151 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 05:52:28.580686 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 05:52:28.584468 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 05:52:28.587478 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 05:52:28.594485 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 05:52:28.597729 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 05:52:28.601239 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 05:52:28.607817 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 05:52:28.610914 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 05:52:28.614080 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 05:52:28.620959 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 05:52:28.624383 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 05:52:28.627361 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 05:52:28.634367 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1589 05:52:28.637463 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1590 05:52:28.640874 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1591 05:52:28.644540 Total UI for P1: 0, mck2ui 16
1592 05:52:28.647501 best dqsien dly found for B1: ( 0, 14, 8)
1593 05:52:28.651168 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1594 05:52:28.654079 Total UI for P1: 0, mck2ui 16
1595 05:52:28.657600 best dqsien dly found for B0: ( 0, 14, 8)
1596 05:52:28.660753 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1597 05:52:28.667464 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1598 05:52:28.667653
1599 05:52:28.670779 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1600 05:52:28.674266 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1601 05:52:28.677728 [Gating] SW calibration Done
1602 05:52:28.677907 ==
1603 05:52:28.680762 Dram Type= 6, Freq= 0, CH_1, rank 0
1604 05:52:28.684301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1605 05:52:28.684467 ==
1606 05:52:28.684546 RX Vref Scan: 0
1607 05:52:28.684623
1608 05:52:28.687887 RX Vref 0 -> 0, step: 1
1609 05:52:28.688066
1610 05:52:28.690985 RX Delay -130 -> 252, step: 16
1611 05:52:28.694000 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1612 05:52:28.697621 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1613 05:52:28.703901 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1614 05:52:28.707248 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1615 05:52:28.710785 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1616 05:52:28.714229 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1617 05:52:28.717584 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1618 05:52:28.724438 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1619 05:52:28.727175 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1620 05:52:28.730541 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1621 05:52:28.733877 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1622 05:52:28.737360 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1623 05:52:28.743980 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1624 05:52:28.747392 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1625 05:52:28.750997 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1626 05:52:28.754148 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1627 05:52:28.754256 ==
1628 05:52:28.757607 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 05:52:28.764396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 05:52:28.764505 ==
1631 05:52:28.764601 DQS Delay:
1632 05:52:28.764691 DQS0 = 0, DQS1 = 0
1633 05:52:28.767328 DQM Delay:
1634 05:52:28.767440 DQM0 = 81, DQM1 = 71
1635 05:52:28.770492 DQ Delay:
1636 05:52:28.774022 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1637 05:52:28.777641 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1638 05:52:28.777737 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1639 05:52:28.784055 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1640 05:52:28.784168
1641 05:52:28.784263
1642 05:52:28.784356 ==
1643 05:52:28.787736 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 05:52:28.790863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 05:52:28.790975 ==
1646 05:52:28.791070
1647 05:52:28.791159
1648 05:52:28.794268 TX Vref Scan disable
1649 05:52:28.794377 == TX Byte 0 ==
1650 05:52:28.800815 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1651 05:52:28.804022 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1652 05:52:28.804107 == TX Byte 1 ==
1653 05:52:28.810970 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1654 05:52:28.814554 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1655 05:52:28.814639 ==
1656 05:52:28.817505 Dram Type= 6, Freq= 0, CH_1, rank 0
1657 05:52:28.820812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1658 05:52:28.820928 ==
1659 05:52:28.834256 TX Vref=22, minBit 1, minWin=26, winSum=438
1660 05:52:28.837661 TX Vref=24, minBit 1, minWin=26, winSum=439
1661 05:52:28.840979 TX Vref=26, minBit 0, minWin=27, winSum=442
1662 05:52:28.844319 TX Vref=28, minBit 1, minWin=26, winSum=446
1663 05:52:28.847791 TX Vref=30, minBit 4, minWin=27, winSum=444
1664 05:52:28.851180 TX Vref=32, minBit 0, minWin=27, winSum=446
1665 05:52:28.858356 [TxChooseVref] Worse bit 0, Min win 27, Win sum 446, Final Vref 32
1666 05:52:28.858464
1667 05:52:28.861912 Final TX Range 1 Vref 32
1668 05:52:28.862022
1669 05:52:28.862114 ==
1670 05:52:28.864809 Dram Type= 6, Freq= 0, CH_1, rank 0
1671 05:52:28.868434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1672 05:52:28.868537 ==
1673 05:52:28.868631
1674 05:52:28.868720
1675 05:52:28.871372 TX Vref Scan disable
1676 05:52:28.874925 == TX Byte 0 ==
1677 05:52:28.878073 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1678 05:52:28.881665 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1679 05:52:28.885121 == TX Byte 1 ==
1680 05:52:28.888133 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1681 05:52:28.891528 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1682 05:52:28.891644
1683 05:52:28.895167 [DATLAT]
1684 05:52:28.895328 Freq=800, CH1 RK0
1685 05:52:28.895424
1686 05:52:28.898151 DATLAT Default: 0xa
1687 05:52:28.898267 0, 0xFFFF, sum = 0
1688 05:52:28.901757 1, 0xFFFF, sum = 0
1689 05:52:28.901865 2, 0xFFFF, sum = 0
1690 05:52:28.904707 3, 0xFFFF, sum = 0
1691 05:52:28.904825 4, 0xFFFF, sum = 0
1692 05:52:28.908318 5, 0xFFFF, sum = 0
1693 05:52:28.908420 6, 0xFFFF, sum = 0
1694 05:52:28.911846 7, 0xFFFF, sum = 0
1695 05:52:28.911931 8, 0xFFFF, sum = 0
1696 05:52:28.914735 9, 0x0, sum = 1
1697 05:52:28.914827 10, 0x0, sum = 2
1698 05:52:28.918253 11, 0x0, sum = 3
1699 05:52:28.918335 12, 0x0, sum = 4
1700 05:52:28.921972 best_step = 10
1701 05:52:28.922053
1702 05:52:28.922117 ==
1703 05:52:28.924858 Dram Type= 6, Freq= 0, CH_1, rank 0
1704 05:52:28.928275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1705 05:52:28.928388 ==
1706 05:52:28.928479 RX Vref Scan: 1
1707 05:52:28.928566
1708 05:52:28.931864 Set Vref Range= 32 -> 127
1709 05:52:28.931945
1710 05:52:28.934913 RX Vref 32 -> 127, step: 1
1711 05:52:28.934994
1712 05:52:28.938552 RX Delay -111 -> 252, step: 8
1713 05:52:28.938659
1714 05:52:28.941497 Set Vref, RX VrefLevel [Byte0]: 32
1715 05:52:28.945146 [Byte1]: 32
1716 05:52:28.945254
1717 05:52:28.948506 Set Vref, RX VrefLevel [Byte0]: 33
1718 05:52:28.951946 [Byte1]: 33
1719 05:52:28.952051
1720 05:52:28.955330 Set Vref, RX VrefLevel [Byte0]: 34
1721 05:52:28.958363 [Byte1]: 34
1722 05:52:28.962373
1723 05:52:28.962468 Set Vref, RX VrefLevel [Byte0]: 35
1724 05:52:28.965605 [Byte1]: 35
1725 05:52:28.970437
1726 05:52:28.970521 Set Vref, RX VrefLevel [Byte0]: 36
1727 05:52:28.973393 [Byte1]: 36
1728 05:52:28.977601
1729 05:52:28.977685 Set Vref, RX VrefLevel [Byte0]: 37
1730 05:52:28.981256 [Byte1]: 37
1731 05:52:28.985564
1732 05:52:28.985646 Set Vref, RX VrefLevel [Byte0]: 38
1733 05:52:28.988544 [Byte1]: 38
1734 05:52:28.993281
1735 05:52:28.993393 Set Vref, RX VrefLevel [Byte0]: 39
1736 05:52:28.996247 [Byte1]: 39
1737 05:52:29.000732
1738 05:52:29.000813 Set Vref, RX VrefLevel [Byte0]: 40
1739 05:52:29.003986 [Byte1]: 40
1740 05:52:29.008089
1741 05:52:29.008168 Set Vref, RX VrefLevel [Byte0]: 41
1742 05:52:29.011737 [Byte1]: 41
1743 05:52:29.015828
1744 05:52:29.015906 Set Vref, RX VrefLevel [Byte0]: 42
1745 05:52:29.019400 [Byte1]: 42
1746 05:52:29.023555
1747 05:52:29.023631 Set Vref, RX VrefLevel [Byte0]: 43
1748 05:52:29.026633 [Byte1]: 43
1749 05:52:29.031100
1750 05:52:29.031201 Set Vref, RX VrefLevel [Byte0]: 44
1751 05:52:29.034417 [Byte1]: 44
1752 05:52:29.038940
1753 05:52:29.039049 Set Vref, RX VrefLevel [Byte0]: 45
1754 05:52:29.042123 [Byte1]: 45
1755 05:52:29.046737
1756 05:52:29.046815 Set Vref, RX VrefLevel [Byte0]: 46
1757 05:52:29.049881 [Byte1]: 46
1758 05:52:29.054007
1759 05:52:29.054081 Set Vref, RX VrefLevel [Byte0]: 47
1760 05:52:29.057360 [Byte1]: 47
1761 05:52:29.062067
1762 05:52:29.062141 Set Vref, RX VrefLevel [Byte0]: 48
1763 05:52:29.065097 [Byte1]: 48
1764 05:52:29.069180
1765 05:52:29.069272 Set Vref, RX VrefLevel [Byte0]: 49
1766 05:52:29.072618 [Byte1]: 49
1767 05:52:29.076778
1768 05:52:29.076859 Set Vref, RX VrefLevel [Byte0]: 50
1769 05:52:29.080501 [Byte1]: 50
1770 05:52:29.084634
1771 05:52:29.088182 Set Vref, RX VrefLevel [Byte0]: 51
1772 05:52:29.088260 [Byte1]: 51
1773 05:52:29.092371
1774 05:52:29.092474 Set Vref, RX VrefLevel [Byte0]: 52
1775 05:52:29.095833 [Byte1]: 52
1776 05:52:29.100021
1777 05:52:29.100129 Set Vref, RX VrefLevel [Byte0]: 53
1778 05:52:29.103512 [Byte1]: 53
1779 05:52:29.107567
1780 05:52:29.107658 Set Vref, RX VrefLevel [Byte0]: 54
1781 05:52:29.111134 [Byte1]: 54
1782 05:52:29.115398
1783 05:52:29.115492 Set Vref, RX VrefLevel [Byte0]: 55
1784 05:52:29.118822 [Byte1]: 55
1785 05:52:29.123056
1786 05:52:29.123141 Set Vref, RX VrefLevel [Byte0]: 56
1787 05:52:29.126426 [Byte1]: 56
1788 05:52:29.130874
1789 05:52:29.130983 Set Vref, RX VrefLevel [Byte0]: 57
1790 05:52:29.133805 [Byte1]: 57
1791 05:52:29.138439
1792 05:52:29.138513 Set Vref, RX VrefLevel [Byte0]: 58
1793 05:52:29.141371 [Byte1]: 58
1794 05:52:29.145877
1795 05:52:29.145965 Set Vref, RX VrefLevel [Byte0]: 59
1796 05:52:29.149355 [Byte1]: 59
1797 05:52:29.153529
1798 05:52:29.153629 Set Vref, RX VrefLevel [Byte0]: 60
1799 05:52:29.156522 [Byte1]: 60
1800 05:52:29.161035
1801 05:52:29.161115 Set Vref, RX VrefLevel [Byte0]: 61
1802 05:52:29.164591 [Byte1]: 61
1803 05:52:29.168561
1804 05:52:29.168665 Set Vref, RX VrefLevel [Byte0]: 62
1805 05:52:29.171845 [Byte1]: 62
1806 05:52:29.176521
1807 05:52:29.176631 Set Vref, RX VrefLevel [Byte0]: 63
1808 05:52:29.179647 [Byte1]: 63
1809 05:52:29.183938
1810 05:52:29.184046 Set Vref, RX VrefLevel [Byte0]: 64
1811 05:52:29.187589 [Byte1]: 64
1812 05:52:29.191873
1813 05:52:29.191952 Set Vref, RX VrefLevel [Byte0]: 65
1814 05:52:29.195414 [Byte1]: 65
1815 05:52:29.199613
1816 05:52:29.199699 Set Vref, RX VrefLevel [Byte0]: 66
1817 05:52:29.202626 [Byte1]: 66
1818 05:52:29.206849
1819 05:52:29.206933 Set Vref, RX VrefLevel [Byte0]: 67
1820 05:52:29.210396 [Byte1]: 67
1821 05:52:29.214708
1822 05:52:29.214786 Set Vref, RX VrefLevel [Byte0]: 68
1823 05:52:29.218136 [Byte1]: 68
1824 05:52:29.222182
1825 05:52:29.222285 Set Vref, RX VrefLevel [Byte0]: 69
1826 05:52:29.225511 [Byte1]: 69
1827 05:52:29.229980
1828 05:52:29.230066 Set Vref, RX VrefLevel [Byte0]: 70
1829 05:52:29.233362 [Byte1]: 70
1830 05:52:29.237587
1831 05:52:29.237667 Set Vref, RX VrefLevel [Byte0]: 71
1832 05:52:29.240995 [Byte1]: 71
1833 05:52:29.245132
1834 05:52:29.245243 Set Vref, RX VrefLevel [Byte0]: 72
1835 05:52:29.249139 [Byte1]: 72
1836 05:52:29.253174
1837 05:52:29.253257 Set Vref, RX VrefLevel [Byte0]: 73
1838 05:52:29.256086 [Byte1]: 73
1839 05:52:29.260909
1840 05:52:29.260993 Set Vref, RX VrefLevel [Byte0]: 74
1841 05:52:29.263760 [Byte1]: 74
1842 05:52:29.268034
1843 05:52:29.268142 Final RX Vref Byte 0 = 64 to rank0
1844 05:52:29.271516 Final RX Vref Byte 1 = 56 to rank0
1845 05:52:29.275114 Final RX Vref Byte 0 = 64 to rank1
1846 05:52:29.278070 Final RX Vref Byte 1 = 56 to rank1==
1847 05:52:29.281551 Dram Type= 6, Freq= 0, CH_1, rank 0
1848 05:52:29.288296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 05:52:29.288406 ==
1850 05:52:29.288500 DQS Delay:
1851 05:52:29.288609 DQS0 = 0, DQS1 = 0
1852 05:52:29.291438 DQM Delay:
1853 05:52:29.291543 DQM0 = 80, DQM1 = 71
1854 05:52:29.294596 DQ Delay:
1855 05:52:29.298182 DQ0 =88, DQ1 =72, DQ2 =68, DQ3 =76
1856 05:52:29.298259 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1857 05:52:29.301752 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1858 05:52:29.304642 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1859 05:52:29.308222
1860 05:52:29.308297
1861 05:52:29.314875 [DQSOSCAuto] RK0, (LSB)MR18= 0x131d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1862 05:52:29.318366 CH1 RK0: MR19=606, MR18=131D
1863 05:52:29.324805 CH1_RK0: MR19=0x606, MR18=0x131D, DQSOSC=402, MR23=63, INC=91, DEC=60
1864 05:52:29.324889
1865 05:52:29.328448 ----->DramcWriteLeveling(PI) begin...
1866 05:52:29.328525 ==
1867 05:52:29.331961 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 05:52:29.334871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 05:52:29.334945 ==
1870 05:52:29.338111 Write leveling (Byte 0): 26 => 26
1871 05:52:29.341591 Write leveling (Byte 1): 30 => 30
1872 05:52:29.345042 DramcWriteLeveling(PI) end<-----
1873 05:52:29.345121
1874 05:52:29.345202 ==
1875 05:52:29.348178 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 05:52:29.351663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 05:52:29.351740 ==
1878 05:52:29.354644 [Gating] SW mode calibration
1879 05:52:29.361215 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1880 05:52:29.368279 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1881 05:52:29.371187 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1882 05:52:29.374739 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1883 05:52:29.381330 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 05:52:29.384948 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 05:52:29.388408 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 05:52:29.394567 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 05:52:29.398467 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 05:52:29.401390 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 05:52:29.408049 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 05:52:29.411556 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 05:52:29.414563 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 05:52:29.421714 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 05:52:29.424602 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 05:52:29.428345 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 05:52:29.431245 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 05:52:29.438280 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 05:52:29.441235 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 05:52:29.444601 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1899 05:52:29.451645 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 05:52:29.455099 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 05:52:29.457898 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 05:52:29.464835 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 05:52:29.467859 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 05:52:29.471420 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 05:52:29.477747 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 05:52:29.481281 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
1907 05:52:29.484898 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1908 05:52:29.491418 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 05:52:29.494385 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 05:52:29.497859 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 05:52:29.504658 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 05:52:29.507985 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 05:52:29.511197 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 05:52:29.517944 0 10 4 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
1915 05:52:29.521059 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1916 05:52:29.524611 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 05:52:29.531141 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 05:52:29.534514 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 05:52:29.537470 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 05:52:29.544132 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 05:52:29.547566 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1922 05:52:29.551032 0 11 4 | B1->B0 | 2929 3636 | 1 1 | (0 0) (0 0)
1923 05:52:29.557953 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1924 05:52:29.561213 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 05:52:29.564521 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 05:52:29.567446 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 05:52:29.574604 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 05:52:29.577497 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 05:52:29.581071 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 05:52:29.587463 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1931 05:52:29.590934 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 05:52:29.593946 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 05:52:29.600992 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 05:52:29.604064 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 05:52:29.607621 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 05:52:29.614118 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 05:52:29.617691 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 05:52:29.621177 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 05:52:29.627334 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 05:52:29.630863 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 05:52:29.634463 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 05:52:29.640763 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 05:52:29.644298 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 05:52:29.647928 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 05:52:29.654403 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 05:52:29.657687 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1947 05:52:29.661077 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1948 05:52:29.664515 Total UI for P1: 0, mck2ui 16
1949 05:52:29.667974 best dqsien dly found for B0: ( 0, 14, 4)
1950 05:52:29.671333 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1951 05:52:29.674683 Total UI for P1: 0, mck2ui 16
1952 05:52:29.678139 best dqsien dly found for B1: ( 0, 14, 8)
1953 05:52:29.681200 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1954 05:52:29.684583 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1955 05:52:29.684663
1956 05:52:29.690877 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1957 05:52:29.694451 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1958 05:52:29.694530 [Gating] SW calibration Done
1959 05:52:29.697899 ==
1960 05:52:29.700945 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 05:52:29.704511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 05:52:29.704586 ==
1963 05:52:29.704666 RX Vref Scan: 0
1964 05:52:29.704744
1965 05:52:29.708035 RX Vref 0 -> 0, step: 1
1966 05:52:29.708121
1967 05:52:29.711189 RX Delay -130 -> 252, step: 16
1968 05:52:29.714666 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1969 05:52:29.717707 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1970 05:52:29.724879 iDelay=206, Bit 2, Center 61 (-66 ~ 189) 256
1971 05:52:29.727765 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1972 05:52:29.731257 iDelay=206, Bit 4, Center 69 (-50 ~ 189) 240
1973 05:52:29.734286 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1974 05:52:29.738093 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1975 05:52:29.741303 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1976 05:52:29.747652 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1977 05:52:29.751208 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1978 05:52:29.754710 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1979 05:52:29.757768 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1980 05:52:29.761308 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1981 05:52:29.767952 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1982 05:52:29.771190 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1983 05:52:29.774355 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1984 05:52:29.774457 ==
1985 05:52:29.777664 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 05:52:29.781452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 05:52:29.781559 ==
1988 05:52:29.784485 DQS Delay:
1989 05:52:29.784572 DQS0 = 0, DQS1 = 0
1990 05:52:29.788060 DQM Delay:
1991 05:52:29.788135 DQM0 = 75, DQM1 = 71
1992 05:52:29.788215 DQ Delay:
1993 05:52:29.791047 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =69
1994 05:52:29.794690 DQ4 =69, DQ5 =85, DQ6 =85, DQ7 =77
1995 05:52:29.798215 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1996 05:52:29.801076 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1997 05:52:29.801181
1998 05:52:29.801299
1999 05:52:29.804700 ==
2000 05:52:29.807705 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 05:52:29.811301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 05:52:29.811376 ==
2003 05:52:29.811460
2004 05:52:29.811535
2005 05:52:29.814375 TX Vref Scan disable
2006 05:52:29.814458 == TX Byte 0 ==
2007 05:52:29.817844 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2008 05:52:29.824972 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2009 05:52:29.825054 == TX Byte 1 ==
2010 05:52:29.827932 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2011 05:52:29.834476 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2012 05:52:29.834558 ==
2013 05:52:29.838011 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 05:52:29.841377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 05:52:29.841493 ==
2016 05:52:29.854644 TX Vref=22, minBit 0, minWin=28, winSum=452
2017 05:52:29.857905 TX Vref=24, minBit 1, minWin=28, winSum=457
2018 05:52:29.861408 TX Vref=26, minBit 1, minWin=28, winSum=459
2019 05:52:29.865033 TX Vref=28, minBit 1, minWin=28, winSum=461
2020 05:52:29.867986 TX Vref=30, minBit 1, minWin=28, winSum=465
2021 05:52:29.871398 TX Vref=32, minBit 1, minWin=27, winSum=459
2022 05:52:29.878108 [TxChooseVref] Worse bit 1, Min win 28, Win sum 465, Final Vref 30
2023 05:52:29.878214
2024 05:52:29.881391 Final TX Range 1 Vref 30
2025 05:52:29.881516
2026 05:52:29.881598 ==
2027 05:52:29.884749 Dram Type= 6, Freq= 0, CH_1, rank 1
2028 05:52:29.888074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2029 05:52:29.888174 ==
2030 05:52:29.891305
2031 05:52:29.891384
2032 05:52:29.891482 TX Vref Scan disable
2033 05:52:29.894664 == TX Byte 0 ==
2034 05:52:29.898325 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2035 05:52:29.901157 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2036 05:52:29.904643 == TX Byte 1 ==
2037 05:52:29.908307 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2038 05:52:29.911400 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2039 05:52:29.915108
2040 05:52:29.915201 [DATLAT]
2041 05:52:29.915287 Freq=800, CH1 RK1
2042 05:52:29.915385
2043 05:52:29.917962 DATLAT Default: 0xa
2044 05:52:29.918037 0, 0xFFFF, sum = 0
2045 05:52:29.921563 1, 0xFFFF, sum = 0
2046 05:52:29.921637 2, 0xFFFF, sum = 0
2047 05:52:29.924515 3, 0xFFFF, sum = 0
2048 05:52:29.924590 4, 0xFFFF, sum = 0
2049 05:52:29.928164 5, 0xFFFF, sum = 0
2050 05:52:29.931209 6, 0xFFFF, sum = 0
2051 05:52:29.931284 7, 0xFFFF, sum = 0
2052 05:52:29.934720 8, 0xFFFF, sum = 0
2053 05:52:29.934793 9, 0x0, sum = 1
2054 05:52:29.934878 10, 0x0, sum = 2
2055 05:52:29.937799 11, 0x0, sum = 3
2056 05:52:29.937871 12, 0x0, sum = 4
2057 05:52:29.941287 best_step = 10
2058 05:52:29.941365
2059 05:52:29.941491 ==
2060 05:52:29.944367 Dram Type= 6, Freq= 0, CH_1, rank 1
2061 05:52:29.948182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2062 05:52:29.948258 ==
2063 05:52:29.951160 RX Vref Scan: 0
2064 05:52:29.951232
2065 05:52:29.951313 RX Vref 0 -> 0, step: 1
2066 05:52:29.951390
2067 05:52:29.954769 RX Delay -111 -> 252, step: 8
2068 05:52:29.961602 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2069 05:52:29.964889 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2070 05:52:29.968115 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2071 05:52:29.971704 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2072 05:52:29.974457 iDelay=209, Bit 4, Center 72 (-47 ~ 192) 240
2073 05:52:29.981057 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2074 05:52:29.984920 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2075 05:52:29.988138 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2076 05:52:29.991442 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2077 05:52:29.994526 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2078 05:52:30.001342 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2079 05:52:30.004490 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2080 05:52:30.007919 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2081 05:52:30.010906 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2082 05:52:30.017486 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2083 05:52:30.021150 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2084 05:52:30.021229 ==
2085 05:52:30.024087 Dram Type= 6, Freq= 0, CH_1, rank 1
2086 05:52:30.027746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2087 05:52:30.027820 ==
2088 05:52:30.030703 DQS Delay:
2089 05:52:30.030776 DQS0 = 0, DQS1 = 0
2090 05:52:30.030855 DQM Delay:
2091 05:52:30.034124 DQM0 = 77, DQM1 = 74
2092 05:52:30.034195 DQ Delay:
2093 05:52:30.037885 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2094 05:52:30.040978 DQ4 =72, DQ5 =88, DQ6 =88, DQ7 =76
2095 05:52:30.043953 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =68
2096 05:52:30.047520 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2097 05:52:30.047599
2098 05:52:30.047679
2099 05:52:30.057463 [DQSOSCAuto] RK1, (LSB)MR18= 0x223a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2100 05:52:30.057571 CH1 RK1: MR19=606, MR18=223A
2101 05:52:30.064078 CH1_RK1: MR19=0x606, MR18=0x223A, DQSOSC=395, MR23=63, INC=94, DEC=63
2102 05:52:30.067040 [RxdqsGatingPostProcess] freq 800
2103 05:52:30.074021 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2104 05:52:30.077435 Pre-setting of DQS Precalculation
2105 05:52:30.080477 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2106 05:52:30.087326 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2107 05:52:30.097134 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2108 05:52:30.097243
2109 05:52:30.097343
2110 05:52:30.100407 [Calibration Summary] 1600 Mbps
2111 05:52:30.100506 CH 0, Rank 0
2112 05:52:30.103826 SW Impedance : PASS
2113 05:52:30.103925 DUTY Scan : NO K
2114 05:52:30.107419 ZQ Calibration : PASS
2115 05:52:30.110484 Jitter Meter : NO K
2116 05:52:30.110562 CBT Training : PASS
2117 05:52:30.113957 Write leveling : PASS
2118 05:52:30.114031 RX DQS gating : PASS
2119 05:52:30.117067 RX DQ/DQS(RDDQC) : PASS
2120 05:52:30.120497 TX DQ/DQS : PASS
2121 05:52:30.120576 RX DATLAT : PASS
2122 05:52:30.123945 RX DQ/DQS(Engine): PASS
2123 05:52:30.127518 TX OE : NO K
2124 05:52:30.127593 All Pass.
2125 05:52:30.127672
2126 05:52:30.127752 CH 0, Rank 1
2127 05:52:30.130561 SW Impedance : PASS
2128 05:52:30.134083 DUTY Scan : NO K
2129 05:52:30.134157 ZQ Calibration : PASS
2130 05:52:30.137143 Jitter Meter : NO K
2131 05:52:30.140750 CBT Training : PASS
2132 05:52:30.140847 Write leveling : PASS
2133 05:52:30.143805 RX DQS gating : PASS
2134 05:52:30.147290 RX DQ/DQS(RDDQC) : PASS
2135 05:52:30.147372 TX DQ/DQS : PASS
2136 05:52:30.151000 RX DATLAT : PASS
2137 05:52:30.153926 RX DQ/DQS(Engine): PASS
2138 05:52:30.153999 TX OE : NO K
2139 05:52:30.154081 All Pass.
2140 05:52:30.157535
2141 05:52:30.157606 CH 1, Rank 0
2142 05:52:30.160497 SW Impedance : PASS
2143 05:52:30.160568 DUTY Scan : NO K
2144 05:52:30.164103 ZQ Calibration : PASS
2145 05:52:30.164179 Jitter Meter : NO K
2146 05:52:30.167072 CBT Training : PASS
2147 05:52:30.170703 Write leveling : PASS
2148 05:52:30.170781 RX DQS gating : PASS
2149 05:52:30.173821 RX DQ/DQS(RDDQC) : PASS
2150 05:52:30.177398 TX DQ/DQS : PASS
2151 05:52:30.177544 RX DATLAT : PASS
2152 05:52:30.180903 RX DQ/DQS(Engine): PASS
2153 05:52:30.183988 TX OE : NO K
2154 05:52:30.184060 All Pass.
2155 05:52:30.184142
2156 05:52:30.184216 CH 1, Rank 1
2157 05:52:30.187604 SW Impedance : PASS
2158 05:52:30.190537 DUTY Scan : NO K
2159 05:52:30.190644 ZQ Calibration : PASS
2160 05:52:30.194116 Jitter Meter : NO K
2161 05:52:30.197285 CBT Training : PASS
2162 05:52:30.197368 Write leveling : PASS
2163 05:52:30.200633 RX DQS gating : PASS
2164 05:52:30.200712 RX DQ/DQS(RDDQC) : PASS
2165 05:52:30.204177 TX DQ/DQS : PASS
2166 05:52:30.207219 RX DATLAT : PASS
2167 05:52:30.207296 RX DQ/DQS(Engine): PASS
2168 05:52:30.210949 TX OE : NO K
2169 05:52:30.211034 All Pass.
2170 05:52:30.211157
2171 05:52:30.213933 DramC Write-DBI off
2172 05:52:30.217385 PER_BANK_REFRESH: Hybrid Mode
2173 05:52:30.217461 TX_TRACKING: ON
2174 05:52:30.221063 [GetDramInforAfterCalByMRR] Vendor 6.
2175 05:52:30.223858 [GetDramInforAfterCalByMRR] Revision 606.
2176 05:52:30.227172 [GetDramInforAfterCalByMRR] Revision 2 0.
2177 05:52:30.230777 MR0 0x3b3b
2178 05:52:30.230850 MR8 0x5151
2179 05:52:30.234083 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2180 05:52:30.234159
2181 05:52:30.237258 MR0 0x3b3b
2182 05:52:30.237337 MR8 0x5151
2183 05:52:30.240841 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2184 05:52:30.240915
2185 05:52:30.250920 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2186 05:52:30.253961 [FAST_K] Save calibration result to emmc
2187 05:52:30.257630 [FAST_K] Save calibration result to emmc
2188 05:52:30.257706 dram_init: config_dvfs: 1
2189 05:52:30.264128 dramc_set_vcore_voltage set vcore to 662500
2190 05:52:30.264208 Read voltage for 1200, 2
2191 05:52:30.267080 Vio18 = 0
2192 05:52:30.267153 Vcore = 662500
2193 05:52:30.267250 Vdram = 0
2194 05:52:30.270747 Vddq = 0
2195 05:52:30.270820 Vmddr = 0
2196 05:52:30.273672 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2197 05:52:30.280330 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2198 05:52:30.283860 MEM_TYPE=3, freq_sel=15
2199 05:52:30.287357 sv_algorithm_assistance_LP4_1600
2200 05:52:30.290492 ============ PULL DRAM RESETB DOWN ============
2201 05:52:30.294040 ========== PULL DRAM RESETB DOWN end =========
2202 05:52:30.297642 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2203 05:52:30.300505 ===================================
2204 05:52:30.304209 LPDDR4 DRAM CONFIGURATION
2205 05:52:30.307084 ===================================
2206 05:52:30.310528 EX_ROW_EN[0] = 0x0
2207 05:52:30.310609 EX_ROW_EN[1] = 0x0
2208 05:52:30.313982 LP4Y_EN = 0x0
2209 05:52:30.314063 WORK_FSP = 0x0
2210 05:52:30.317247 WL = 0x4
2211 05:52:30.317367 RL = 0x4
2212 05:52:30.320640 BL = 0x2
2213 05:52:30.320713 RPST = 0x0
2214 05:52:30.323872 RD_PRE = 0x0
2215 05:52:30.323954 WR_PRE = 0x1
2216 05:52:30.327327 WR_PST = 0x0
2217 05:52:30.327410 DBI_WR = 0x0
2218 05:52:30.330423 DBI_RD = 0x0
2219 05:52:30.333819 OTF = 0x1
2220 05:52:30.333900 ===================================
2221 05:52:30.337147 ===================================
2222 05:52:30.340505 ANA top config
2223 05:52:30.343809 ===================================
2224 05:52:30.347502 DLL_ASYNC_EN = 0
2225 05:52:30.347584 ALL_SLAVE_EN = 0
2226 05:52:30.350909 NEW_RANK_MODE = 1
2227 05:52:30.353805 DLL_IDLE_MODE = 1
2228 05:52:30.357353 LP45_APHY_COMB_EN = 1
2229 05:52:30.360370 TX_ODT_DIS = 1
2230 05:52:30.360469 NEW_8X_MODE = 1
2231 05:52:30.363952 ===================================
2232 05:52:30.367106 ===================================
2233 05:52:30.370759 data_rate = 2400
2234 05:52:30.373667 CKR = 1
2235 05:52:30.377297 DQ_P2S_RATIO = 8
2236 05:52:30.380222 ===================================
2237 05:52:30.383983 CA_P2S_RATIO = 8
2238 05:52:30.384062 DQ_CA_OPEN = 0
2239 05:52:30.386862 DQ_SEMI_OPEN = 0
2240 05:52:30.390433 CA_SEMI_OPEN = 0
2241 05:52:30.394077 CA_FULL_RATE = 0
2242 05:52:30.397017 DQ_CKDIV4_EN = 0
2243 05:52:30.400729 CA_CKDIV4_EN = 0
2244 05:52:30.400804 CA_PREDIV_EN = 0
2245 05:52:30.403697 PH8_DLY = 17
2246 05:52:30.407217 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2247 05:52:30.410613 DQ_AAMCK_DIV = 4
2248 05:52:30.413492 CA_AAMCK_DIV = 4
2249 05:52:30.417120 CA_ADMCK_DIV = 4
2250 05:52:30.417195 DQ_TRACK_CA_EN = 0
2251 05:52:30.420507 CA_PICK = 1200
2252 05:52:30.423484 CA_MCKIO = 1200
2253 05:52:30.426919 MCKIO_SEMI = 0
2254 05:52:30.430263 PLL_FREQ = 2366
2255 05:52:30.433791 DQ_UI_PI_RATIO = 32
2256 05:52:30.436649 CA_UI_PI_RATIO = 0
2257 05:52:30.440302 ===================================
2258 05:52:30.443255 ===================================
2259 05:52:30.443362 memory_type:LPDDR4
2260 05:52:30.446902 GP_NUM : 10
2261 05:52:30.450347 SRAM_EN : 1
2262 05:52:30.450428 MD32_EN : 0
2263 05:52:30.453604 ===================================
2264 05:52:30.456893 [ANA_INIT] >>>>>>>>>>>>>>
2265 05:52:30.460094 <<<<<< [CONFIGURE PHASE]: ANA_TX
2266 05:52:30.463242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2267 05:52:30.466953 ===================================
2268 05:52:30.469852 data_rate = 2400,PCW = 0X5b00
2269 05:52:30.473591 ===================================
2270 05:52:30.476534 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2271 05:52:30.480264 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2272 05:52:30.486821 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2273 05:52:30.489871 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2274 05:52:30.493351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2275 05:52:30.497014 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2276 05:52:30.499855 [ANA_INIT] flow start
2277 05:52:30.503560 [ANA_INIT] PLL >>>>>>>>
2278 05:52:30.503640 [ANA_INIT] PLL <<<<<<<<
2279 05:52:30.506529 [ANA_INIT] MIDPI >>>>>>>>
2280 05:52:30.510100 [ANA_INIT] MIDPI <<<<<<<<
2281 05:52:30.513686 [ANA_INIT] DLL >>>>>>>>
2282 05:52:30.513797 [ANA_INIT] DLL <<<<<<<<
2283 05:52:30.516601 [ANA_INIT] flow end
2284 05:52:30.520369 ============ LP4 DIFF to SE enter ============
2285 05:52:30.523280 ============ LP4 DIFF to SE exit ============
2286 05:52:30.526678 [ANA_INIT] <<<<<<<<<<<<<
2287 05:52:30.530406 [Flow] Enable top DCM control >>>>>
2288 05:52:30.533386 [Flow] Enable top DCM control <<<<<
2289 05:52:30.536909 Enable DLL master slave shuffle
2290 05:52:30.543231 ==============================================================
2291 05:52:30.543315 Gating Mode config
2292 05:52:30.550327 ==============================================================
2293 05:52:30.550412 Config description:
2294 05:52:30.560399 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2295 05:52:30.566899 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2296 05:52:30.573520 SELPH_MODE 0: By rank 1: By Phase
2297 05:52:30.577033 ==============================================================
2298 05:52:30.579948 GAT_TRACK_EN = 1
2299 05:52:30.583513 RX_GATING_MODE = 2
2300 05:52:30.586498 RX_GATING_TRACK_MODE = 2
2301 05:52:30.590075 SELPH_MODE = 1
2302 05:52:30.593723 PICG_EARLY_EN = 1
2303 05:52:30.596533 VALID_LAT_VALUE = 1
2304 05:52:30.600195 ==============================================================
2305 05:52:30.603208 Enter into Gating configuration >>>>
2306 05:52:30.606884 Exit from Gating configuration <<<<
2307 05:52:30.609895 Enter into DVFS_PRE_config >>>>>
2308 05:52:30.623454 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2309 05:52:30.623539 Exit from DVFS_PRE_config <<<<<
2310 05:52:30.626918 Enter into PICG configuration >>>>
2311 05:52:30.630221 Exit from PICG configuration <<<<
2312 05:52:30.633170 [RX_INPUT] configuration >>>>>
2313 05:52:30.636723 [RX_INPUT] configuration <<<<<
2314 05:52:30.643177 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2315 05:52:30.646824 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2316 05:52:30.653314 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2317 05:52:30.659945 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2318 05:52:30.666897 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2319 05:52:30.672929 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2320 05:52:30.676348 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2321 05:52:30.679732 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2322 05:52:30.683146 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2323 05:52:30.690037 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2324 05:52:30.693420 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2325 05:52:30.696599 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2326 05:52:30.700253 ===================================
2327 05:52:30.703467 LPDDR4 DRAM CONFIGURATION
2328 05:52:30.706561 ===================================
2329 05:52:30.706641 EX_ROW_EN[0] = 0x0
2330 05:52:30.710252 EX_ROW_EN[1] = 0x0
2331 05:52:30.713148 LP4Y_EN = 0x0
2332 05:52:30.713222 WORK_FSP = 0x0
2333 05:52:30.716665 WL = 0x4
2334 05:52:30.716740 RL = 0x4
2335 05:52:30.720243 BL = 0x2
2336 05:52:30.720342 RPST = 0x0
2337 05:52:30.723346 RD_PRE = 0x0
2338 05:52:30.723427 WR_PRE = 0x1
2339 05:52:30.726905 WR_PST = 0x0
2340 05:52:30.726986 DBI_WR = 0x0
2341 05:52:30.730412 DBI_RD = 0x0
2342 05:52:30.730527 OTF = 0x1
2343 05:52:30.733654 ===================================
2344 05:52:30.736997 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2345 05:52:30.743358 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2346 05:52:30.746841 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2347 05:52:30.749918 ===================================
2348 05:52:30.753507 LPDDR4 DRAM CONFIGURATION
2349 05:52:30.756477 ===================================
2350 05:52:30.756552 EX_ROW_EN[0] = 0x10
2351 05:52:30.759901 EX_ROW_EN[1] = 0x0
2352 05:52:30.759978 LP4Y_EN = 0x0
2353 05:52:30.763471 WORK_FSP = 0x0
2354 05:52:30.763547 WL = 0x4
2355 05:52:30.766436 RL = 0x4
2356 05:52:30.769989 BL = 0x2
2357 05:52:30.770094 RPST = 0x0
2358 05:52:30.773270 RD_PRE = 0x0
2359 05:52:30.773344 WR_PRE = 0x1
2360 05:52:30.776332 WR_PST = 0x0
2361 05:52:30.776435 DBI_WR = 0x0
2362 05:52:30.780013 DBI_RD = 0x0
2363 05:52:30.780118 OTF = 0x1
2364 05:52:30.783036 ===================================
2365 05:52:30.789607 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2366 05:52:30.789714 ==
2367 05:52:30.792979 Dram Type= 6, Freq= 0, CH_0, rank 0
2368 05:52:30.796225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2369 05:52:30.796301 ==
2370 05:52:30.799415 [Duty_Offset_Calibration]
2371 05:52:30.803064 B0:2 B1:0 CA:3
2372 05:52:30.803142
2373 05:52:30.805951 [DutyScan_Calibration_Flow] k_type=0
2374 05:52:30.814283
2375 05:52:30.814378 ==CLK 0==
2376 05:52:30.817387 Final CLK duty delay cell = 0
2377 05:52:30.820883 [0] MAX Duty = 5031%(X100), DQS PI = 12
2378 05:52:30.824557 [0] MIN Duty = 4875%(X100), DQS PI = 58
2379 05:52:30.824635 [0] AVG Duty = 4953%(X100)
2380 05:52:30.827503
2381 05:52:30.831082 CH0 CLK Duty spec in!! Max-Min= 156%
2382 05:52:30.834119 [DutyScan_Calibration_Flow] ====Done====
2383 05:52:30.834201
2384 05:52:30.837741 [DutyScan_Calibration_Flow] k_type=1
2385 05:52:30.852845
2386 05:52:30.852932 ==DQS 0 ==
2387 05:52:30.856149 Final DQS duty delay cell = 0
2388 05:52:30.859092 [0] MAX Duty = 5062%(X100), DQS PI = 12
2389 05:52:30.862632 [0] MIN Duty = 4907%(X100), DQS PI = 44
2390 05:52:30.862735 [0] AVG Duty = 4984%(X100)
2391 05:52:30.866054
2392 05:52:30.866130 ==DQS 1 ==
2393 05:52:30.869619 Final DQS duty delay cell = -4
2394 05:52:30.872485 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2395 05:52:30.875891 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2396 05:52:30.879340 [-4] AVG Duty = 4922%(X100)
2397 05:52:30.879441
2398 05:52:30.882825 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2399 05:52:30.882899
2400 05:52:30.886289 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2401 05:52:30.889122 [DutyScan_Calibration_Flow] ====Done====
2402 05:52:30.889193
2403 05:52:30.892790 [DutyScan_Calibration_Flow] k_type=3
2404 05:52:30.910263
2405 05:52:30.910345 ==DQM 0 ==
2406 05:52:30.913381 Final DQM duty delay cell = 0
2407 05:52:30.916989 [0] MAX Duty = 5124%(X100), DQS PI = 28
2408 05:52:30.919993 [0] MIN Duty = 4876%(X100), DQS PI = 48
2409 05:52:30.923525 [0] AVG Duty = 5000%(X100)
2410 05:52:30.923641
2411 05:52:30.923729 ==DQM 1 ==
2412 05:52:30.927219 Final DQM duty delay cell = 4
2413 05:52:30.930147 [4] MAX Duty = 5124%(X100), DQS PI = 50
2414 05:52:30.933731 [4] MIN Duty = 5000%(X100), DQS PI = 14
2415 05:52:30.933801 [4] AVG Duty = 5062%(X100)
2416 05:52:30.936700
2417 05:52:30.940351 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2418 05:52:30.940421
2419 05:52:30.943978 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2420 05:52:30.946953 [DutyScan_Calibration_Flow] ====Done====
2421 05:52:30.947024
2422 05:52:30.950405 [DutyScan_Calibration_Flow] k_type=2
2423 05:52:30.965163
2424 05:52:30.965248 ==DQ 0 ==
2425 05:52:30.968664 Final DQ duty delay cell = -4
2426 05:52:30.972114 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2427 05:52:30.975365 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2428 05:52:30.978780 [-4] AVG Duty = 4969%(X100)
2429 05:52:30.978859
2430 05:52:30.978945 ==DQ 1 ==
2431 05:52:30.981743 Final DQ duty delay cell = -4
2432 05:52:30.985364 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2433 05:52:30.988369 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2434 05:52:30.991887 [-4] AVG Duty = 4938%(X100)
2435 05:52:30.991997
2436 05:52:30.995419 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2437 05:52:30.995518
2438 05:52:30.998428 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2439 05:52:31.002020 [DutyScan_Calibration_Flow] ====Done====
2440 05:52:31.002096 ==
2441 05:52:31.004911 Dram Type= 6, Freq= 0, CH_1, rank 0
2442 05:52:31.008473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2443 05:52:31.008551 ==
2444 05:52:31.011575 [Duty_Offset_Calibration]
2445 05:52:31.011651 B0:1 B1:-2 CA:0
2446 05:52:31.011760
2447 05:52:31.015060 [DutyScan_Calibration_Flow] k_type=0
2448 05:52:31.025550
2449 05:52:31.025634 ==CLK 0==
2450 05:52:31.029145 Final CLK duty delay cell = 0
2451 05:52:31.032125 [0] MAX Duty = 5031%(X100), DQS PI = 16
2452 05:52:31.035790 [0] MIN Duty = 4844%(X100), DQS PI = 58
2453 05:52:31.035870 [0] AVG Duty = 4937%(X100)
2454 05:52:31.039296
2455 05:52:31.042259 CH1 CLK Duty spec in!! Max-Min= 187%
2456 05:52:31.045796 [DutyScan_Calibration_Flow] ====Done====
2457 05:52:31.045873
2458 05:52:31.048673 [DutyScan_Calibration_Flow] k_type=1
2459 05:52:31.064175
2460 05:52:31.064283 ==DQS 0 ==
2461 05:52:31.067568 Final DQS duty delay cell = -4
2462 05:52:31.070895 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2463 05:52:31.074425 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2464 05:52:31.077638 [-4] AVG Duty = 4953%(X100)
2465 05:52:31.077717
2466 05:52:31.077783 ==DQS 1 ==
2467 05:52:31.080855 Final DQS duty delay cell = 0
2468 05:52:31.084230 [0] MAX Duty = 5093%(X100), DQS PI = 0
2469 05:52:31.087528 [0] MIN Duty = 4875%(X100), DQS PI = 28
2470 05:52:31.090915 [0] AVG Duty = 4984%(X100)
2471 05:52:31.090992
2472 05:52:31.094450 CH1 DQS 0 Duty spec in!! Max-Min= 155%
2473 05:52:31.094536
2474 05:52:31.097357 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2475 05:52:31.101058 [DutyScan_Calibration_Flow] ====Done====
2476 05:52:31.101133
2477 05:52:31.103971 [DutyScan_Calibration_Flow] k_type=3
2478 05:52:31.120863
2479 05:52:31.120950 ==DQM 0 ==
2480 05:52:31.124342 Final DQM duty delay cell = 0
2481 05:52:31.127519 [0] MAX Duty = 5000%(X100), DQS PI = 22
2482 05:52:31.130989 [0] MIN Duty = 4844%(X100), DQS PI = 56
2483 05:52:31.131075 [0] AVG Duty = 4922%(X100)
2484 05:52:31.134535
2485 05:52:31.134612 ==DQM 1 ==
2486 05:52:31.137785 Final DQM duty delay cell = 0
2487 05:52:31.141276 [0] MAX Duty = 5031%(X100), DQS PI = 36
2488 05:52:31.144173 [0] MIN Duty = 4907%(X100), DQS PI = 0
2489 05:52:31.144250 [0] AVG Duty = 4969%(X100)
2490 05:52:31.147708
2491 05:52:31.151311 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2492 05:52:31.151391
2493 05:52:31.154260 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2494 05:52:31.158086 [DutyScan_Calibration_Flow] ====Done====
2495 05:52:31.158160
2496 05:52:31.161024 [DutyScan_Calibration_Flow] k_type=2
2497 05:52:31.177318
2498 05:52:31.177415 ==DQ 0 ==
2499 05:52:31.180903 Final DQ duty delay cell = 0
2500 05:52:31.184449 [0] MAX Duty = 5093%(X100), DQS PI = 20
2501 05:52:31.187331 [0] MIN Duty = 4938%(X100), DQS PI = 54
2502 05:52:31.187415 [0] AVG Duty = 5015%(X100)
2503 05:52:31.190553
2504 05:52:31.190650 ==DQ 1 ==
2505 05:52:31.194259 Final DQ duty delay cell = 0
2506 05:52:31.197442 [0] MAX Duty = 5125%(X100), DQS PI = 36
2507 05:52:31.200788 [0] MIN Duty = 4969%(X100), DQS PI = 26
2508 05:52:31.200868 [0] AVG Duty = 5047%(X100)
2509 05:52:31.200953
2510 05:52:31.204175 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2511 05:52:31.204274
2512 05:52:31.207577 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2513 05:52:31.214053 [DutyScan_Calibration_Flow] ====Done====
2514 05:52:31.217669 nWR fixed to 30
2515 05:52:31.217801 [ModeRegInit_LP4] CH0 RK0
2516 05:52:31.220707 [ModeRegInit_LP4] CH0 RK1
2517 05:52:31.224173 [ModeRegInit_LP4] CH1 RK0
2518 05:52:31.224248 [ModeRegInit_LP4] CH1 RK1
2519 05:52:31.227245 match AC timing 7
2520 05:52:31.230792 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2521 05:52:31.234210 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2522 05:52:31.240793 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2523 05:52:31.243877 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2524 05:52:31.250904 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2525 05:52:31.251025 ==
2526 05:52:31.253974 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 05:52:31.257600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 05:52:31.257673 ==
2529 05:52:31.264320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2530 05:52:31.267283 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2531 05:52:31.277492 [CA 0] Center 40 (10~71) winsize 62
2532 05:52:31.280841 [CA 1] Center 39 (9~70) winsize 62
2533 05:52:31.284209 [CA 2] Center 36 (6~66) winsize 61
2534 05:52:31.287879 [CA 3] Center 35 (5~66) winsize 62
2535 05:52:31.290812 [CA 4] Center 34 (4~65) winsize 62
2536 05:52:31.293843 [CA 5] Center 33 (3~63) winsize 61
2537 05:52:31.293920
2538 05:52:31.297335 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2539 05:52:31.297420
2540 05:52:31.300800 [CATrainingPosCal] consider 1 rank data
2541 05:52:31.304142 u2DelayCellTimex100 = 270/100 ps
2542 05:52:31.307423 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2543 05:52:31.314354 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2544 05:52:31.317381 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2545 05:52:31.320768 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2546 05:52:31.324356 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2547 05:52:31.327293 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2548 05:52:31.327424
2549 05:52:31.330961 CA PerBit enable=1, Macro0, CA PI delay=33
2550 05:52:31.331097
2551 05:52:31.334023 [CBTSetCACLKResult] CA Dly = 33
2552 05:52:31.334105 CS Dly: 7 (0~38)
2553 05:52:31.337334 ==
2554 05:52:31.340715 Dram Type= 6, Freq= 0, CH_0, rank 1
2555 05:52:31.343765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2556 05:52:31.343849 ==
2557 05:52:31.347419 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2558 05:52:31.353780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=23, u1VrefScanEnd=33
2559 05:52:31.363799 [CA 0] Center 40 (10~71) winsize 62
2560 05:52:31.366740 [CA 1] Center 39 (9~70) winsize 62
2561 05:52:31.370375 [CA 2] Center 36 (6~66) winsize 61
2562 05:52:31.373601 [CA 3] Center 35 (5~66) winsize 62
2563 05:52:31.377169 [CA 4] Center 34 (4~65) winsize 62
2564 05:52:31.380226 [CA 5] Center 33 (3~63) winsize 61
2565 05:52:31.380334
2566 05:52:31.383735 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2567 05:52:31.383814
2568 05:52:31.386651 [CATrainingPosCal] consider 2 rank data
2569 05:52:31.389976 u2DelayCellTimex100 = 270/100 ps
2570 05:52:31.393269 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2571 05:52:31.400105 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2572 05:52:31.403190 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2573 05:52:31.406724 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2574 05:52:31.409933 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2575 05:52:31.413380 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2576 05:52:31.413495
2577 05:52:31.416716 CA PerBit enable=1, Macro0, CA PI delay=33
2578 05:52:31.416817
2579 05:52:31.420095 [CBTSetCACLKResult] CA Dly = 33
2580 05:52:31.420199 CS Dly: 7 (0~39)
2581 05:52:31.423277
2582 05:52:31.426860 ----->DramcWriteLeveling(PI) begin...
2583 05:52:31.426967 ==
2584 05:52:31.429973 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 05:52:31.433545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 05:52:31.433621 ==
2587 05:52:31.436590 Write leveling (Byte 0): 31 => 31
2588 05:52:31.440234 Write leveling (Byte 1): 30 => 30
2589 05:52:31.443631 DramcWriteLeveling(PI) end<-----
2590 05:52:31.443731
2591 05:52:31.443825 ==
2592 05:52:31.447085 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 05:52:31.450149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 05:52:31.450228 ==
2595 05:52:31.453635 [Gating] SW mode calibration
2596 05:52:31.460042 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2597 05:52:31.466528 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2598 05:52:31.469954 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 05:52:31.473461 0 15 4 | B1->B0 | 2525 3333 | 0 1 | (0 0) (1 1)
2600 05:52:31.479948 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 05:52:31.483545 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 05:52:31.486427 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 05:52:31.490018 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 05:52:31.496937 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 05:52:31.500407 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2606 05:52:31.503220 1 0 0 | B1->B0 | 3232 2626 | 1 0 | (1 1) (1 0)
2607 05:52:31.509862 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 05:52:31.513440 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 05:52:31.516950 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 05:52:31.523135 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 05:52:31.526632 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 05:52:31.530046 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 05:52:31.536518 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 05:52:31.540143 1 1 0 | B1->B0 | 2424 2a2a | 0 1 | (0 0) (0 0)
2615 05:52:31.543142 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2616 05:52:31.550371 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 05:52:31.553289 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 05:52:31.556804 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 05:52:31.563261 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 05:52:31.566715 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 05:52:31.570192 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2622 05:52:31.576770 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2623 05:52:31.580071 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2624 05:52:31.582996 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 05:52:31.590154 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 05:52:31.593133 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 05:52:31.596644 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 05:52:31.599681 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 05:52:31.606656 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 05:52:31.609869 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 05:52:31.613675 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 05:52:31.620028 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 05:52:31.623025 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 05:52:31.626446 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 05:52:31.633037 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 05:52:31.636668 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 05:52:31.639654 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2638 05:52:31.646631 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2639 05:52:31.649470 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2640 05:52:31.652894 Total UI for P1: 0, mck2ui 16
2641 05:52:31.656564 best dqsien dly found for B0: ( 1, 3, 30)
2642 05:52:31.659689 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2643 05:52:31.663262 Total UI for P1: 0, mck2ui 16
2644 05:52:31.666738 best dqsien dly found for B1: ( 1, 4, 2)
2645 05:52:31.669634 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2646 05:52:31.673121 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2647 05:52:31.673203
2648 05:52:31.679524 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2649 05:52:31.683011 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2650 05:52:31.683093 [Gating] SW calibration Done
2651 05:52:31.686438 ==
2652 05:52:31.686519 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 05:52:31.692939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 05:52:31.693021 ==
2655 05:52:31.693086 RX Vref Scan: 0
2656 05:52:31.693173
2657 05:52:31.696612 RX Vref 0 -> 0, step: 1
2658 05:52:31.696692
2659 05:52:31.699535 RX Delay -40 -> 252, step: 8
2660 05:52:31.702934 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2661 05:52:31.706502 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2662 05:52:31.709432 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2663 05:52:31.716447 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2664 05:52:31.719732 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2665 05:52:31.723267 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2666 05:52:31.726258 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2667 05:52:31.729362 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2668 05:52:31.736348 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2669 05:52:31.739946 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2670 05:52:31.743279 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2671 05:52:31.746103 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2672 05:52:31.749517 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2673 05:52:31.755924 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2674 05:52:31.759394 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2675 05:52:31.763071 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2676 05:52:31.763151 ==
2677 05:52:31.765994 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 05:52:31.769605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 05:52:31.769686 ==
2680 05:52:31.772512 DQS Delay:
2681 05:52:31.772593 DQS0 = 0, DQS1 = 0
2682 05:52:31.776119 DQM Delay:
2683 05:52:31.776199 DQM0 = 113, DQM1 = 103
2684 05:52:31.776263 DQ Delay:
2685 05:52:31.779078 DQ0 =115, DQ1 =111, DQ2 =115, DQ3 =107
2686 05:52:31.782785 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2687 05:52:31.786323 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2688 05:52:31.792724 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2689 05:52:31.792848
2690 05:52:31.792912
2691 05:52:31.792972 ==
2692 05:52:31.796023 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 05:52:31.798943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 05:52:31.799040 ==
2695 05:52:31.799121
2696 05:52:31.799181
2697 05:52:31.802388 TX Vref Scan disable
2698 05:52:31.802484 == TX Byte 0 ==
2699 05:52:31.809070 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2700 05:52:31.812540 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2701 05:52:31.812622 == TX Byte 1 ==
2702 05:52:31.819106 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2703 05:52:31.822114 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2704 05:52:31.822196 ==
2705 05:52:31.825403 Dram Type= 6, Freq= 0, CH_0, rank 0
2706 05:52:31.828793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2707 05:52:31.828874 ==
2708 05:52:31.842242 TX Vref=22, minBit 12, minWin=25, winSum=418
2709 05:52:31.845778 TX Vref=24, minBit 14, minWin=25, winSum=423
2710 05:52:31.848733 TX Vref=26, minBit 10, minWin=26, winSum=432
2711 05:52:31.852233 TX Vref=28, minBit 1, minWin=27, winSum=435
2712 05:52:31.855611 TX Vref=30, minBit 10, minWin=26, winSum=435
2713 05:52:31.862289 TX Vref=32, minBit 11, minWin=26, winSum=431
2714 05:52:31.865378 [TxChooseVref] Worse bit 1, Min win 27, Win sum 435, Final Vref 28
2715 05:52:31.865512
2716 05:52:31.868927 Final TX Range 1 Vref 28
2717 05:52:31.869008
2718 05:52:31.869079 ==
2719 05:52:31.872414 Dram Type= 6, Freq= 0, CH_0, rank 0
2720 05:52:31.875357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2721 05:52:31.878860 ==
2722 05:52:31.878941
2723 05:52:31.879005
2724 05:52:31.879063 TX Vref Scan disable
2725 05:52:31.882477 == TX Byte 0 ==
2726 05:52:31.885455 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2727 05:52:31.888998 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2728 05:52:31.892498 == TX Byte 1 ==
2729 05:52:31.895593 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2730 05:52:31.899127 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2731 05:52:31.902565
2732 05:52:31.902646 [DATLAT]
2733 05:52:31.902710 Freq=1200, CH0 RK0
2734 05:52:31.902771
2735 05:52:31.905693 DATLAT Default: 0xd
2736 05:52:31.905774 0, 0xFFFF, sum = 0
2737 05:52:31.909008 1, 0xFFFF, sum = 0
2738 05:52:31.909109 2, 0xFFFF, sum = 0
2739 05:52:31.912031 3, 0xFFFF, sum = 0
2740 05:52:31.915691 4, 0xFFFF, sum = 0
2741 05:52:31.915791 5, 0xFFFF, sum = 0
2742 05:52:31.918665 6, 0xFFFF, sum = 0
2743 05:52:31.918747 7, 0xFFFF, sum = 0
2744 05:52:31.922345 8, 0xFFFF, sum = 0
2745 05:52:31.922444 9, 0xFFFF, sum = 0
2746 05:52:31.925813 10, 0xFFFF, sum = 0
2747 05:52:31.925895 11, 0xFFFF, sum = 0
2748 05:52:31.928907 12, 0x0, sum = 1
2749 05:52:31.928988 13, 0x0, sum = 2
2750 05:52:31.932319 14, 0x0, sum = 3
2751 05:52:31.932433 15, 0x0, sum = 4
2752 05:52:31.932531 best_step = 13
2753 05:52:31.935248
2754 05:52:31.935328 ==
2755 05:52:31.938578 Dram Type= 6, Freq= 0, CH_0, rank 0
2756 05:52:31.942072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2757 05:52:31.942154 ==
2758 05:52:31.942219 RX Vref Scan: 1
2759 05:52:31.942279
2760 05:52:31.945366 Set Vref Range= 32 -> 127
2761 05:52:31.945447
2762 05:52:31.948805 RX Vref 32 -> 127, step: 1
2763 05:52:31.948887
2764 05:52:31.951776 RX Delay -37 -> 252, step: 4
2765 05:52:31.951857
2766 05:52:31.955298 Set Vref, RX VrefLevel [Byte0]: 32
2767 05:52:31.958872 [Byte1]: 32
2768 05:52:31.958953
2769 05:52:31.962377 Set Vref, RX VrefLevel [Byte0]: 33
2770 05:52:31.965358 [Byte1]: 33
2771 05:52:31.968934
2772 05:52:31.969014 Set Vref, RX VrefLevel [Byte0]: 34
2773 05:52:31.972308 [Byte1]: 34
2774 05:52:31.977103
2775 05:52:31.977184 Set Vref, RX VrefLevel [Byte0]: 35
2776 05:52:31.980566 [Byte1]: 35
2777 05:52:31.984877
2778 05:52:31.984958 Set Vref, RX VrefLevel [Byte0]: 36
2779 05:52:31.988408 [Byte1]: 36
2780 05:52:31.993176
2781 05:52:31.993258 Set Vref, RX VrefLevel [Byte0]: 37
2782 05:52:31.996161 [Byte1]: 37
2783 05:52:32.001052
2784 05:52:32.001132 Set Vref, RX VrefLevel [Byte0]: 38
2785 05:52:32.004205 [Byte1]: 38
2786 05:52:32.008944
2787 05:52:32.009017 Set Vref, RX VrefLevel [Byte0]: 39
2788 05:52:32.012446 [Byte1]: 39
2789 05:52:32.017241
2790 05:52:32.017323 Set Vref, RX VrefLevel [Byte0]: 40
2791 05:52:32.020141 [Byte1]: 40
2792 05:52:32.024915
2793 05:52:32.024996 Set Vref, RX VrefLevel [Byte0]: 41
2794 05:52:32.027916 [Byte1]: 41
2795 05:52:32.032668
2796 05:52:32.032750 Set Vref, RX VrefLevel [Byte0]: 42
2797 05:52:32.036220 [Byte1]: 42
2798 05:52:32.041077
2799 05:52:32.041170 Set Vref, RX VrefLevel [Byte0]: 43
2800 05:52:32.044153 [Byte1]: 43
2801 05:52:32.049216
2802 05:52:32.049340 Set Vref, RX VrefLevel [Byte0]: 44
2803 05:52:32.052002 [Byte1]: 44
2804 05:52:32.057203
2805 05:52:32.057310 Set Vref, RX VrefLevel [Byte0]: 45
2806 05:52:32.060121 [Byte1]: 45
2807 05:52:32.064788
2808 05:52:32.064869 Set Vref, RX VrefLevel [Byte0]: 46
2809 05:52:32.068452 [Byte1]: 46
2810 05:52:32.073180
2811 05:52:32.073262 Set Vref, RX VrefLevel [Byte0]: 47
2812 05:52:32.076034 [Byte1]: 47
2813 05:52:32.080644
2814 05:52:32.080739 Set Vref, RX VrefLevel [Byte0]: 48
2815 05:52:32.084218 [Byte1]: 48
2816 05:52:32.088785
2817 05:52:32.088866 Set Vref, RX VrefLevel [Byte0]: 49
2818 05:52:32.092300 [Byte1]: 49
2819 05:52:32.097119
2820 05:52:32.097199 Set Vref, RX VrefLevel [Byte0]: 50
2821 05:52:32.100118 [Byte1]: 50
2822 05:52:32.104836
2823 05:52:32.104917 Set Vref, RX VrefLevel [Byte0]: 51
2824 05:52:32.108406 [Byte1]: 51
2825 05:52:32.113223
2826 05:52:32.113303 Set Vref, RX VrefLevel [Byte0]: 52
2827 05:52:32.116143 [Byte1]: 52
2828 05:52:32.120901
2829 05:52:32.120981 Set Vref, RX VrefLevel [Byte0]: 53
2830 05:52:32.124352 [Byte1]: 53
2831 05:52:32.129243
2832 05:52:32.129323 Set Vref, RX VrefLevel [Byte0]: 54
2833 05:52:32.132169 [Byte1]: 54
2834 05:52:32.136948
2835 05:52:32.137028 Set Vref, RX VrefLevel [Byte0]: 55
2836 05:52:32.140394 [Byte1]: 55
2837 05:52:32.144666
2838 05:52:32.144746 Set Vref, RX VrefLevel [Byte0]: 56
2839 05:52:32.148244 [Byte1]: 56
2840 05:52:32.152688
2841 05:52:32.152770 Set Vref, RX VrefLevel [Byte0]: 57
2842 05:52:32.156454 [Byte1]: 57
2843 05:52:32.160856
2844 05:52:32.160937 Set Vref, RX VrefLevel [Byte0]: 58
2845 05:52:32.164100 [Byte1]: 58
2846 05:52:32.168707
2847 05:52:32.168789 Set Vref, RX VrefLevel [Byte0]: 59
2848 05:52:32.172436 [Byte1]: 59
2849 05:52:32.176882
2850 05:52:32.176963 Set Vref, RX VrefLevel [Byte0]: 60
2851 05:52:32.180505 [Byte1]: 60
2852 05:52:32.184659
2853 05:52:32.184740 Set Vref, RX VrefLevel [Byte0]: 61
2854 05:52:32.188123 [Byte1]: 61
2855 05:52:32.193135
2856 05:52:32.193216 Set Vref, RX VrefLevel [Byte0]: 62
2857 05:52:32.196006 [Byte1]: 62
2858 05:52:32.200656
2859 05:52:32.200738 Set Vref, RX VrefLevel [Byte0]: 63
2860 05:52:32.204354 [Byte1]: 63
2861 05:52:32.209209
2862 05:52:32.209332 Set Vref, RX VrefLevel [Byte0]: 64
2863 05:52:32.212283 [Byte1]: 64
2864 05:52:32.217066
2865 05:52:32.217148 Set Vref, RX VrefLevel [Byte0]: 65
2866 05:52:32.220199 [Byte1]: 65
2867 05:52:32.224899
2868 05:52:32.224980 Set Vref, RX VrefLevel [Byte0]: 66
2869 05:52:32.228519 [Byte1]: 66
2870 05:52:32.233180
2871 05:52:32.233276 Set Vref, RX VrefLevel [Byte0]: 67
2872 05:52:32.236534 [Byte1]: 67
2873 05:52:32.241257
2874 05:52:32.241338 Set Vref, RX VrefLevel [Byte0]: 68
2875 05:52:32.244152 [Byte1]: 68
2876 05:52:32.248918
2877 05:52:32.249000 Set Vref, RX VrefLevel [Byte0]: 69
2878 05:52:32.252115 [Byte1]: 69
2879 05:52:32.256830
2880 05:52:32.256911 Set Vref, RX VrefLevel [Byte0]: 70
2881 05:52:32.260276 [Byte1]: 70
2882 05:52:32.265292
2883 05:52:32.265400 Set Vref, RX VrefLevel [Byte0]: 71
2884 05:52:32.268203 [Byte1]: 71
2885 05:52:32.272805
2886 05:52:32.272888 Set Vref, RX VrefLevel [Byte0]: 72
2887 05:52:32.276473 [Byte1]: 72
2888 05:52:32.281193
2889 05:52:32.281302 Set Vref, RX VrefLevel [Byte0]: 73
2890 05:52:32.287173 [Byte1]: 73
2891 05:52:32.287255
2892 05:52:32.290675 Final RX Vref Byte 0 = 64 to rank0
2893 05:52:32.293968 Final RX Vref Byte 1 = 52 to rank0
2894 05:52:32.297470 Final RX Vref Byte 0 = 64 to rank1
2895 05:52:32.301050 Final RX Vref Byte 1 = 52 to rank1==
2896 05:52:32.304381 Dram Type= 6, Freq= 0, CH_0, rank 0
2897 05:52:32.307414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 05:52:32.307497 ==
2899 05:52:32.307562 DQS Delay:
2900 05:52:32.311030 DQS0 = 0, DQS1 = 0
2901 05:52:32.311112 DQM Delay:
2902 05:52:32.313918 DQM0 = 112, DQM1 = 101
2903 05:52:32.314000 DQ Delay:
2904 05:52:32.317486 DQ0 =110, DQ1 =112, DQ2 =114, DQ3 =108
2905 05:52:32.320505 DQ4 =114, DQ5 =104, DQ6 =120, DQ7 =120
2906 05:52:32.324089 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2907 05:52:32.327045 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2908 05:52:32.327127
2909 05:52:32.327191
2910 05:52:32.337453 [DQSOSCAuto] RK0, (LSB)MR18= 0xf9f8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
2911 05:52:32.340368 CH0 RK0: MR19=303, MR18=F9F8
2912 05:52:32.347389 CH0_RK0: MR19=0x303, MR18=0xF9F8, DQSOSC=412, MR23=63, INC=38, DEC=25
2913 05:52:32.347474
2914 05:52:32.350502 ----->DramcWriteLeveling(PI) begin...
2915 05:52:32.350588 ==
2916 05:52:32.354140 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 05:52:32.357035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 05:52:32.357119 ==
2919 05:52:32.360398 Write leveling (Byte 0): 33 => 33
2920 05:52:32.364074 Write leveling (Byte 1): 31 => 31
2921 05:52:32.366952 DramcWriteLeveling(PI) end<-----
2922 05:52:32.367035
2923 05:52:32.367102 ==
2924 05:52:32.370740 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 05:52:32.373767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 05:52:32.373851 ==
2927 05:52:32.377238 [Gating] SW mode calibration
2928 05:52:32.383960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2929 05:52:32.390591 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2930 05:52:32.393967 0 15 0 | B1->B0 | 2a29 3434 | 1 1 | (0 0) (1 1)
2931 05:52:32.397365 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 05:52:32.403715 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2933 05:52:32.407210 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2934 05:52:32.410140 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2935 05:52:32.417393 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2936 05:52:32.420305 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2937 05:52:32.423777 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
2938 05:52:32.430380 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
2939 05:52:32.433399 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 05:52:32.436950 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2941 05:52:32.440605 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2942 05:52:32.447152 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2943 05:52:32.450450 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2944 05:52:32.453430 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2945 05:52:32.460694 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (1 1)
2946 05:52:32.463716 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2947 05:52:32.467333 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 05:52:32.473953 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 05:52:32.476680 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 05:52:32.480155 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 05:52:32.487073 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 05:52:32.490452 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2953 05:52:32.493308 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2954 05:52:32.500317 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2955 05:52:32.503757 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 05:52:32.507032 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 05:52:32.513746 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 05:52:32.517211 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 05:52:32.520102 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 05:52:32.526720 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 05:52:32.530413 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 05:52:32.533366 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 05:52:32.540055 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 05:52:32.543487 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 05:52:32.547155 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 05:52:32.550201 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 05:52:32.556919 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 05:52:32.559971 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 05:52:32.563611 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2970 05:52:32.570215 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2971 05:52:32.573114 Total UI for P1: 0, mck2ui 16
2972 05:52:32.576680 best dqsien dly found for B0: ( 1, 3, 28)
2973 05:52:32.580249 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 05:52:32.583135 Total UI for P1: 0, mck2ui 16
2975 05:52:32.586509 best dqsien dly found for B1: ( 1, 4, 0)
2976 05:52:32.590155 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2977 05:52:32.593549 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2978 05:52:32.593631
2979 05:52:32.596534 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2980 05:52:32.600145 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2981 05:52:32.603196 [Gating] SW calibration Done
2982 05:52:32.603299 ==
2983 05:52:32.606592 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 05:52:32.609987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 05:52:32.613326 ==
2986 05:52:32.613410 RX Vref Scan: 0
2987 05:52:32.613485
2988 05:52:32.616569 RX Vref 0 -> 0, step: 1
2989 05:52:32.616653
2990 05:52:32.620036 RX Delay -40 -> 252, step: 8
2991 05:52:32.623612 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2992 05:52:32.626835 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2993 05:52:32.629757 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2994 05:52:32.633326 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2995 05:52:32.639942 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
2996 05:52:32.643430 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2997 05:52:32.646593 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2998 05:52:32.650315 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2999 05:52:32.653299 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3000 05:52:32.656884 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
3001 05:52:32.663322 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3002 05:52:32.666302 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3003 05:52:32.669784 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
3004 05:52:32.673484 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3005 05:52:32.676578 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3006 05:52:32.683543 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
3007 05:52:32.683627 ==
3008 05:52:32.687002 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 05:52:32.689881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 05:52:32.690008 ==
3011 05:52:32.690088 DQS Delay:
3012 05:52:32.693665 DQS0 = 0, DQS1 = 0
3013 05:52:32.693762 DQM Delay:
3014 05:52:32.697084 DQM0 = 111, DQM1 = 101
3015 05:52:32.697166 DQ Delay:
3016 05:52:32.700068 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
3017 05:52:32.703652 DQ4 =111, DQ5 =99, DQ6 =119, DQ7 =123
3018 05:52:32.706532 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3019 05:52:32.710177 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
3020 05:52:32.710276
3021 05:52:32.710371
3022 05:52:32.710446 ==
3023 05:52:32.713167 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 05:52:32.719849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 05:52:32.719946 ==
3026 05:52:32.720042
3027 05:52:32.720117
3028 05:52:32.722960 TX Vref Scan disable
3029 05:52:32.723044 == TX Byte 0 ==
3030 05:52:32.726588 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3031 05:52:32.732952 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3032 05:52:32.733037 == TX Byte 1 ==
3033 05:52:32.736843 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3034 05:52:32.743034 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3035 05:52:32.743119 ==
3036 05:52:32.746597 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 05:52:32.749677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 05:52:32.749762 ==
3039 05:52:32.761467 TX Vref=22, minBit 0, minWin=26, winSum=426
3040 05:52:32.765002 TX Vref=24, minBit 12, minWin=26, winSum=432
3041 05:52:32.768463 TX Vref=26, minBit 1, minWin=26, winSum=438
3042 05:52:32.771791 TX Vref=28, minBit 1, minWin=27, winSum=441
3043 05:52:32.774778 TX Vref=30, minBit 1, minWin=27, winSum=439
3044 05:52:32.781920 TX Vref=32, minBit 0, minWin=27, winSum=442
3045 05:52:32.784907 [TxChooseVref] Worse bit 0, Min win 27, Win sum 442, Final Vref 32
3046 05:52:32.784991
3047 05:52:32.788293 Final TX Range 1 Vref 32
3048 05:52:32.788377
3049 05:52:32.788443 ==
3050 05:52:32.791715 Dram Type= 6, Freq= 0, CH_0, rank 1
3051 05:52:32.795158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3052 05:52:32.795242 ==
3053 05:52:32.798056
3054 05:52:32.798138
3055 05:52:32.798204 TX Vref Scan disable
3056 05:52:32.801438 == TX Byte 0 ==
3057 05:52:32.804548 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3058 05:52:32.811568 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3059 05:52:32.811652 == TX Byte 1 ==
3060 05:52:32.814625 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3061 05:52:32.818393 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3062 05:52:32.821707
3063 05:52:32.821790 [DATLAT]
3064 05:52:32.821856 Freq=1200, CH0 RK1
3065 05:52:32.821918
3066 05:52:32.824692 DATLAT Default: 0xd
3067 05:52:32.824775 0, 0xFFFF, sum = 0
3068 05:52:32.828143 1, 0xFFFF, sum = 0
3069 05:52:32.828228 2, 0xFFFF, sum = 0
3070 05:52:32.831394 3, 0xFFFF, sum = 0
3071 05:52:32.834626 4, 0xFFFF, sum = 0
3072 05:52:32.834714 5, 0xFFFF, sum = 0
3073 05:52:32.838183 6, 0xFFFF, sum = 0
3074 05:52:32.838295 7, 0xFFFF, sum = 0
3075 05:52:32.841293 8, 0xFFFF, sum = 0
3076 05:52:32.841370 9, 0xFFFF, sum = 0
3077 05:52:32.844731 10, 0xFFFF, sum = 0
3078 05:52:32.844820 11, 0xFFFF, sum = 0
3079 05:52:32.848001 12, 0x0, sum = 1
3080 05:52:32.848088 13, 0x0, sum = 2
3081 05:52:32.851761 14, 0x0, sum = 3
3082 05:52:32.851840 15, 0x0, sum = 4
3083 05:52:32.851906 best_step = 13
3084 05:52:32.854878
3085 05:52:32.854953 ==
3086 05:52:32.858440 Dram Type= 6, Freq= 0, CH_0, rank 1
3087 05:52:32.861546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 05:52:32.861632 ==
3089 05:52:32.861696 RX Vref Scan: 0
3090 05:52:32.861757
3091 05:52:32.865134 RX Vref 0 -> 0, step: 1
3092 05:52:32.865202
3093 05:52:32.867950 RX Delay -37 -> 252, step: 4
3094 05:52:32.871478 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3095 05:52:32.878362 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3096 05:52:32.881402 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3097 05:52:32.884468 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3098 05:52:32.887988 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3099 05:52:32.891453 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3100 05:52:32.897884 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3101 05:52:32.901372 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3102 05:52:32.904726 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3103 05:52:32.908125 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3104 05:52:32.911109 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3105 05:52:32.917709 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3106 05:52:32.921485 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3107 05:52:32.924357 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3108 05:52:32.927954 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3109 05:52:32.931101 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3110 05:52:32.934532 ==
3111 05:52:32.934609 Dram Type= 6, Freq= 0, CH_0, rank 1
3112 05:52:32.941115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 05:52:32.941200 ==
3114 05:52:32.941267 DQS Delay:
3115 05:52:32.944431 DQS0 = 0, DQS1 = 0
3116 05:52:32.944514 DQM Delay:
3117 05:52:32.948030 DQM0 = 110, DQM1 = 101
3118 05:52:32.948115 DQ Delay:
3119 05:52:32.950997 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3120 05:52:32.954543 DQ4 =110, DQ5 =100, DQ6 =120, DQ7 =120
3121 05:52:32.957893 DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =92
3122 05:52:32.960923 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3123 05:52:32.961032
3124 05:52:32.961129
3125 05:52:32.971000 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3126 05:52:32.971115 CH0 RK1: MR19=403, MR18=11F9
3127 05:52:32.977957 CH0_RK1: MR19=0x403, MR18=0x11F9, DQSOSC=403, MR23=63, INC=40, DEC=26
3128 05:52:32.980842 [RxdqsGatingPostProcess] freq 1200
3129 05:52:32.988097 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3130 05:52:32.991021 best DQS0 dly(2T, 0.5T) = (0, 11)
3131 05:52:32.994631 best DQS1 dly(2T, 0.5T) = (0, 12)
3132 05:52:32.997685 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3133 05:52:33.001209 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3134 05:52:33.001312 best DQS0 dly(2T, 0.5T) = (0, 11)
3135 05:52:33.004191 best DQS1 dly(2T, 0.5T) = (0, 12)
3136 05:52:33.007677 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3137 05:52:33.011056 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3138 05:52:33.014644 Pre-setting of DQS Precalculation
3139 05:52:33.021338 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3140 05:52:33.021422 ==
3141 05:52:33.024195 Dram Type= 6, Freq= 0, CH_1, rank 0
3142 05:52:33.027760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 05:52:33.027843 ==
3144 05:52:33.034386 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3145 05:52:33.040791 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3146 05:52:33.047544 [CA 0] Center 37 (7~67) winsize 61
3147 05:52:33.050958 [CA 1] Center 37 (7~68) winsize 62
3148 05:52:33.054534 [CA 2] Center 34 (4~64) winsize 61
3149 05:52:33.057496 [CA 3] Center 34 (4~64) winsize 61
3150 05:52:33.060924 [CA 4] Center 34 (4~64) winsize 61
3151 05:52:33.064429 [CA 5] Center 33 (3~63) winsize 61
3152 05:52:33.064509
3153 05:52:33.067432 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3154 05:52:33.067522
3155 05:52:33.070994 [CATrainingPosCal] consider 1 rank data
3156 05:52:33.074303 u2DelayCellTimex100 = 270/100 ps
3157 05:52:33.077686 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3158 05:52:33.081011 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3159 05:52:33.087901 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3160 05:52:33.091200 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3161 05:52:33.094157 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3162 05:52:33.097598 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3163 05:52:33.097682
3164 05:52:33.101254 CA PerBit enable=1, Macro0, CA PI delay=33
3165 05:52:33.101337
3166 05:52:33.104237 [CBTSetCACLKResult] CA Dly = 33
3167 05:52:33.104320 CS Dly: 6 (0~37)
3168 05:52:33.107715 ==
3169 05:52:33.107797 Dram Type= 6, Freq= 0, CH_1, rank 1
3170 05:52:33.114081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 05:52:33.114165 ==
3172 05:52:33.117372 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3173 05:52:33.124021 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3174 05:52:33.133047 [CA 0] Center 38 (8~68) winsize 61
3175 05:52:33.136665 [CA 1] Center 37 (7~68) winsize 62
3176 05:52:33.139713 [CA 2] Center 35 (5~65) winsize 61
3177 05:52:33.143267 [CA 3] Center 33 (3~64) winsize 62
3178 05:52:33.146287 [CA 4] Center 34 (4~65) winsize 62
3179 05:52:33.149857 [CA 5] Center 33 (3~63) winsize 61
3180 05:52:33.149938
3181 05:52:33.153243 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3182 05:52:33.153344
3183 05:52:33.156742 [CATrainingPosCal] consider 2 rank data
3184 05:52:33.159845 u2DelayCellTimex100 = 270/100 ps
3185 05:52:33.163379 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3186 05:52:33.166926 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3187 05:52:33.173275 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3188 05:52:33.176294 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3189 05:52:33.179985 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3190 05:52:33.182919 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3191 05:52:33.183000
3192 05:52:33.186395 CA PerBit enable=1, Macro0, CA PI delay=33
3193 05:52:33.186521
3194 05:52:33.189936 [CBTSetCACLKResult] CA Dly = 33
3195 05:52:33.190016 CS Dly: 7 (0~40)
3196 05:52:33.190081
3197 05:52:33.193244 ----->DramcWriteLeveling(PI) begin...
3198 05:52:33.196433 ==
3199 05:52:33.199925 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 05:52:33.203538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 05:52:33.203651 ==
3202 05:52:33.206686 Write leveling (Byte 0): 26 => 26
3203 05:52:33.210022 Write leveling (Byte 1): 30 => 30
3204 05:52:33.213235 DramcWriteLeveling(PI) end<-----
3205 05:52:33.213315
3206 05:52:33.213379 ==
3207 05:52:33.216691 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 05:52:33.220201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 05:52:33.220311 ==
3210 05:52:33.223459 [Gating] SW mode calibration
3211 05:52:33.230039 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3212 05:52:33.233455 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3213 05:52:33.240180 0 15 0 | B1->B0 | 2e2e 2828 | 0 0 | (0 0) (0 0)
3214 05:52:33.243275 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3215 05:52:33.246855 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3216 05:52:33.253371 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3217 05:52:33.256948 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3218 05:52:33.260185 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3219 05:52:33.266563 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3220 05:52:33.270210 0 15 28 | B1->B0 | 2d2d 2e2e | 0 0 | (0 0) (0 1)
3221 05:52:33.273276 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 05:52:33.279961 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3223 05:52:33.283436 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3224 05:52:33.286439 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3225 05:52:33.293056 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3226 05:52:33.296730 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3227 05:52:33.299706 1 0 24 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
3228 05:52:33.306844 1 0 28 | B1->B0 | 3b3b 3333 | 1 0 | (1 1) (1 1)
3229 05:52:33.309911 1 1 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3230 05:52:33.313415 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 05:52:33.319970 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 05:52:33.323237 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 05:52:33.326394 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 05:52:33.329945 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3235 05:52:33.336351 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3236 05:52:33.339454 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3237 05:52:33.346067 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3238 05:52:33.349700 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 05:52:33.352732 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 05:52:33.356301 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 05:52:33.362947 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 05:52:33.366385 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 05:52:33.369866 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 05:52:33.376382 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 05:52:33.379609 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 05:52:33.383209 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 05:52:33.389408 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 05:52:33.393060 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 05:52:33.396582 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 05:52:33.402807 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 05:52:33.406603 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 05:52:33.409611 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3253 05:52:33.416535 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3254 05:52:33.416637 Total UI for P1: 0, mck2ui 16
3255 05:52:33.422809 best dqsien dly found for B0: ( 1, 3, 28)
3256 05:52:33.426503 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3257 05:52:33.429430 Total UI for P1: 0, mck2ui 16
3258 05:52:33.433077 best dqsien dly found for B1: ( 1, 3, 30)
3259 05:52:33.436209 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3260 05:52:33.439795 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3261 05:52:33.439913
3262 05:52:33.442792 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3263 05:52:33.446421 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3264 05:52:33.449886 [Gating] SW calibration Done
3265 05:52:33.449992 ==
3266 05:52:33.453061 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 05:52:33.456041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 05:52:33.456119 ==
3269 05:52:33.459483 RX Vref Scan: 0
3270 05:52:33.459586
3271 05:52:33.462726 RX Vref 0 -> 0, step: 1
3272 05:52:33.462828
3273 05:52:33.462920 RX Delay -40 -> 252, step: 8
3274 05:52:33.469705 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3275 05:52:33.472931 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3276 05:52:33.476103 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3277 05:52:33.479394 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3278 05:52:33.482831 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3279 05:52:33.489249 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3280 05:52:33.492840 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3281 05:52:33.495846 iDelay=208, Bit 7, Center 111 (40 ~ 183) 144
3282 05:52:33.499441 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3283 05:52:33.502598 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3284 05:52:33.509170 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
3285 05:52:33.512715 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3286 05:52:33.516330 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3287 05:52:33.519412 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3288 05:52:33.522479 iDelay=208, Bit 14, Center 111 (40 ~ 183) 144
3289 05:52:33.529463 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3290 05:52:33.529559 ==
3291 05:52:33.532461 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 05:52:33.536042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 05:52:33.536123 ==
3294 05:52:33.536187 DQS Delay:
3295 05:52:33.539111 DQS0 = 0, DQS1 = 0
3296 05:52:33.539181 DQM Delay:
3297 05:52:33.542664 DQM0 = 115, DQM1 = 107
3298 05:52:33.542746 DQ Delay:
3299 05:52:33.546142 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3300 05:52:33.548928 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3301 05:52:33.552513 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =103
3302 05:52:33.555999 DQ12 =115, DQ13 =119, DQ14 =111, DQ15 =111
3303 05:52:33.556096
3304 05:52:33.556161
3305 05:52:33.559002 ==
3306 05:52:33.562573 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 05:52:33.566089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 05:52:33.566180 ==
3309 05:52:33.566272
3310 05:52:33.566359
3311 05:52:33.569398 TX Vref Scan disable
3312 05:52:33.569504 == TX Byte 0 ==
3313 05:52:33.572525 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3314 05:52:33.579136 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3315 05:52:33.579215 == TX Byte 1 ==
3316 05:52:33.582832 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3317 05:52:33.589488 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3318 05:52:33.589569 ==
3319 05:52:33.592925 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 05:52:33.595714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 05:52:33.595790 ==
3322 05:52:33.608096 TX Vref=22, minBit 3, minWin=25, winSum=414
3323 05:52:33.611658 TX Vref=24, minBit 8, minWin=25, winSum=416
3324 05:52:33.614621 TX Vref=26, minBit 8, minWin=24, winSum=427
3325 05:52:33.618159 TX Vref=28, minBit 1, minWin=26, winSum=427
3326 05:52:33.621308 TX Vref=30, minBit 1, minWin=26, winSum=428
3327 05:52:33.628002 TX Vref=32, minBit 1, minWin=26, winSum=428
3328 05:52:33.630874 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
3329 05:52:33.630983
3330 05:52:33.634469 Final TX Range 1 Vref 30
3331 05:52:33.634551
3332 05:52:33.634615 ==
3333 05:52:33.637994 Dram Type= 6, Freq= 0, CH_1, rank 0
3334 05:52:33.641015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3335 05:52:33.641096 ==
3336 05:52:33.644588
3337 05:52:33.644667
3338 05:52:33.644731 TX Vref Scan disable
3339 05:52:33.647581 == TX Byte 0 ==
3340 05:52:33.651378 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3341 05:52:33.654654 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3342 05:52:33.657697 == TX Byte 1 ==
3343 05:52:33.661334 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3344 05:52:33.664188 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3345 05:52:33.667739
3346 05:52:33.667839 [DATLAT]
3347 05:52:33.667930 Freq=1200, CH1 RK0
3348 05:52:33.668017
3349 05:52:33.671333 DATLAT Default: 0xd
3350 05:52:33.671427 0, 0xFFFF, sum = 0
3351 05:52:33.674252 1, 0xFFFF, sum = 0
3352 05:52:33.674329 2, 0xFFFF, sum = 0
3353 05:52:33.677680 3, 0xFFFF, sum = 0
3354 05:52:33.680838 4, 0xFFFF, sum = 0
3355 05:52:33.680909 5, 0xFFFF, sum = 0
3356 05:52:33.684127 6, 0xFFFF, sum = 0
3357 05:52:33.684202 7, 0xFFFF, sum = 0
3358 05:52:33.687700 8, 0xFFFF, sum = 0
3359 05:52:33.687789 9, 0xFFFF, sum = 0
3360 05:52:33.691175 10, 0xFFFF, sum = 0
3361 05:52:33.691246 11, 0xFFFF, sum = 0
3362 05:52:33.694129 12, 0x0, sum = 1
3363 05:52:33.694232 13, 0x0, sum = 2
3364 05:52:33.697734 14, 0x0, sum = 3
3365 05:52:33.697806 15, 0x0, sum = 4
3366 05:52:33.697868 best_step = 13
3367 05:52:33.700650
3368 05:52:33.700722 ==
3369 05:52:33.704164 Dram Type= 6, Freq= 0, CH_1, rank 0
3370 05:52:33.707623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3371 05:52:33.707699 ==
3372 05:52:33.707766 RX Vref Scan: 1
3373 05:52:33.707852
3374 05:52:33.710927 Set Vref Range= 32 -> 127
3375 05:52:33.711000
3376 05:52:33.714446 RX Vref 32 -> 127, step: 1
3377 05:52:33.714544
3378 05:52:33.717591 RX Delay -21 -> 252, step: 4
3379 05:52:33.717689
3380 05:52:33.721155 Set Vref, RX VrefLevel [Byte0]: 32
3381 05:52:33.724482 [Byte1]: 32
3382 05:52:33.724582
3383 05:52:33.727376 Set Vref, RX VrefLevel [Byte0]: 33
3384 05:52:33.730929 [Byte1]: 33
3385 05:52:33.731007
3386 05:52:33.734559 Set Vref, RX VrefLevel [Byte0]: 34
3387 05:52:33.737456 [Byte1]: 34
3388 05:52:33.742210
3389 05:52:33.742308 Set Vref, RX VrefLevel [Byte0]: 35
3390 05:52:33.745277 [Byte1]: 35
3391 05:52:33.750119
3392 05:52:33.750197 Set Vref, RX VrefLevel [Byte0]: 36
3393 05:52:33.753210 [Byte1]: 36
3394 05:52:33.758023
3395 05:52:33.758124 Set Vref, RX VrefLevel [Byte0]: 37
3396 05:52:33.761005 [Byte1]: 37
3397 05:52:33.765829
3398 05:52:33.765905 Set Vref, RX VrefLevel [Byte0]: 38
3399 05:52:33.769263 [Byte1]: 38
3400 05:52:33.774006
3401 05:52:33.774091 Set Vref, RX VrefLevel [Byte0]: 39
3402 05:52:33.776999 [Byte1]: 39
3403 05:52:33.781778
3404 05:52:33.781851 Set Vref, RX VrefLevel [Byte0]: 40
3405 05:52:33.784733 [Byte1]: 40
3406 05:52:33.789453
3407 05:52:33.789587 Set Vref, RX VrefLevel [Byte0]: 41
3408 05:52:33.792945 [Byte1]: 41
3409 05:52:33.797545
3410 05:52:33.797647 Set Vref, RX VrefLevel [Byte0]: 42
3411 05:52:33.801097 [Byte1]: 42
3412 05:52:33.805272
3413 05:52:33.805373 Set Vref, RX VrefLevel [Byte0]: 43
3414 05:52:33.808979 [Byte1]: 43
3415 05:52:33.813070
3416 05:52:33.813145 Set Vref, RX VrefLevel [Byte0]: 44
3417 05:52:33.816655 [Byte1]: 44
3418 05:52:33.821480
3419 05:52:33.821583 Set Vref, RX VrefLevel [Byte0]: 45
3420 05:52:33.824441 [Byte1]: 45
3421 05:52:33.829136
3422 05:52:33.829245 Set Vref, RX VrefLevel [Byte0]: 46
3423 05:52:33.832441 [Byte1]: 46
3424 05:52:33.837424
3425 05:52:33.837556 Set Vref, RX VrefLevel [Byte0]: 47
3426 05:52:33.840506 [Byte1]: 47
3427 05:52:33.844919
3428 05:52:33.845018 Set Vref, RX VrefLevel [Byte0]: 48
3429 05:52:33.848385 [Byte1]: 48
3430 05:52:33.852936
3431 05:52:33.853054 Set Vref, RX VrefLevel [Byte0]: 49
3432 05:52:33.856574 [Byte1]: 49
3433 05:52:33.860707
3434 05:52:33.860808 Set Vref, RX VrefLevel [Byte0]: 50
3435 05:52:33.864121 [Byte1]: 50
3436 05:52:33.868906
3437 05:52:33.868978 Set Vref, RX VrefLevel [Byte0]: 51
3438 05:52:33.871900 [Byte1]: 51
3439 05:52:33.876778
3440 05:52:33.879788 Set Vref, RX VrefLevel [Byte0]: 52
3441 05:52:33.879860 [Byte1]: 52
3442 05:52:33.884464
3443 05:52:33.884537 Set Vref, RX VrefLevel [Byte0]: 53
3444 05:52:33.888167 [Byte1]: 53
3445 05:52:33.892868
3446 05:52:33.892964 Set Vref, RX VrefLevel [Byte0]: 54
3447 05:52:33.895581 [Byte1]: 54
3448 05:52:33.900394
3449 05:52:33.900490 Set Vref, RX VrefLevel [Byte0]: 55
3450 05:52:33.903700 [Byte1]: 55
3451 05:52:33.908299
3452 05:52:33.908402 Set Vref, RX VrefLevel [Byte0]: 56
3453 05:52:33.912025 [Byte1]: 56
3454 05:52:33.916056
3455 05:52:33.916153 Set Vref, RX VrefLevel [Byte0]: 57
3456 05:52:33.919705 [Byte1]: 57
3457 05:52:33.924396
3458 05:52:33.924469 Set Vref, RX VrefLevel [Byte0]: 58
3459 05:52:33.927350 [Byte1]: 58
3460 05:52:33.932022
3461 05:52:33.932092 Set Vref, RX VrefLevel [Byte0]: 59
3462 05:52:33.935519 [Byte1]: 59
3463 05:52:33.939813
3464 05:52:33.939884 Set Vref, RX VrefLevel [Byte0]: 60
3465 05:52:33.943390 [Byte1]: 60
3466 05:52:33.948264
3467 05:52:33.948361 Set Vref, RX VrefLevel [Byte0]: 61
3468 05:52:33.951198 [Byte1]: 61
3469 05:52:33.955971
3470 05:52:33.956069 Set Vref, RX VrefLevel [Byte0]: 62
3471 05:52:33.959189 [Byte1]: 62
3472 05:52:33.964037
3473 05:52:33.964135 Set Vref, RX VrefLevel [Byte0]: 63
3474 05:52:33.967196 [Byte1]: 63
3475 05:52:33.971529
3476 05:52:33.971630 Set Vref, RX VrefLevel [Byte0]: 64
3477 05:52:33.975305 [Byte1]: 64
3478 05:52:33.979915
3479 05:52:33.979991 Set Vref, RX VrefLevel [Byte0]: 65
3480 05:52:33.982965 [Byte1]: 65
3481 05:52:33.987608
3482 05:52:33.987680 Set Vref, RX VrefLevel [Byte0]: 66
3483 05:52:33.990630 [Byte1]: 66
3484 05:52:33.995358
3485 05:52:33.995430 Set Vref, RX VrefLevel [Byte0]: 67
3486 05:52:33.998937 [Byte1]: 67
3487 05:52:34.003328
3488 05:52:34.003402 Set Vref, RX VrefLevel [Byte0]: 68
3489 05:52:34.006575 [Byte1]: 68
3490 05:52:34.011177
3491 05:52:34.011277 Set Vref, RX VrefLevel [Byte0]: 69
3492 05:52:34.015019 [Byte1]: 69
3493 05:52:34.019146
3494 05:52:34.019251 Set Vref, RX VrefLevel [Byte0]: 70
3495 05:52:34.022623 [Byte1]: 70
3496 05:52:34.026943
3497 05:52:34.027042 Set Vref, RX VrefLevel [Byte0]: 71
3498 05:52:34.030476 [Byte1]: 71
3499 05:52:34.035348
3500 05:52:34.035449 Final RX Vref Byte 0 = 54 to rank0
3501 05:52:34.038218 Final RX Vref Byte 1 = 55 to rank0
3502 05:52:34.041644 Final RX Vref Byte 0 = 54 to rank1
3503 05:52:34.045271 Final RX Vref Byte 1 = 55 to rank1==
3504 05:52:34.048223 Dram Type= 6, Freq= 0, CH_1, rank 0
3505 05:52:34.054797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 05:52:34.054906 ==
3507 05:52:34.054999 DQS Delay:
3508 05:52:34.055087 DQS0 = 0, DQS1 = 0
3509 05:52:34.058278 DQM Delay:
3510 05:52:34.058379 DQM0 = 114, DQM1 = 106
3511 05:52:34.061838 DQ Delay:
3512 05:52:34.064976 DQ0 =118, DQ1 =112, DQ2 =104, DQ3 =112
3513 05:52:34.068566 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3514 05:52:34.071322 DQ8 =94, DQ9 =98, DQ10 =106, DQ11 =102
3515 05:52:34.075035 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =112
3516 05:52:34.075173
3517 05:52:34.075325
3518 05:52:34.084806 [DQSOSCAuto] RK0, (LSB)MR18= 0xeaf1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 419 ps
3519 05:52:34.084912 CH1 RK0: MR19=303, MR18=EAF1
3520 05:52:34.091383 CH1_RK0: MR19=0x303, MR18=0xEAF1, DQSOSC=416, MR23=63, INC=37, DEC=25
3521 05:52:34.091533
3522 05:52:34.094587 ----->DramcWriteLeveling(PI) begin...
3523 05:52:34.094725 ==
3524 05:52:34.098167 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 05:52:34.101718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 05:52:34.104693 ==
3527 05:52:34.104845 Write leveling (Byte 0): 25 => 25
3528 05:52:34.108302 Write leveling (Byte 1): 28 => 28
3529 05:52:34.111776 DramcWriteLeveling(PI) end<-----
3530 05:52:34.111873
3531 05:52:34.111961 ==
3532 05:52:34.114761 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 05:52:34.121342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 05:52:34.121452 ==
3535 05:52:34.124616 [Gating] SW mode calibration
3536 05:52:34.131456 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3537 05:52:34.134946 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3538 05:52:34.141356 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3539 05:52:34.144948 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3540 05:52:34.147934 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3541 05:52:34.154401 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3542 05:52:34.158107 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3543 05:52:34.161621 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3544 05:52:34.164552 0 15 24 | B1->B0 | 3333 2727 | 1 0 | (1 0) (0 0)
3545 05:52:34.171497 0 15 28 | B1->B0 | 2929 2323 | 1 0 | (1 1) (0 0)
3546 05:52:34.175077 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3547 05:52:34.178090 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3548 05:52:34.184767 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3549 05:52:34.187688 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3550 05:52:34.191148 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3551 05:52:34.197759 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3552 05:52:34.201081 1 0 24 | B1->B0 | 2b2b 4343 | 0 0 | (0 0) (0 0)
3553 05:52:34.204364 1 0 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3554 05:52:34.210971 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 05:52:34.214689 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3556 05:52:34.217592 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 05:52:34.224234 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 05:52:34.227666 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 05:52:34.230924 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 05:52:34.237746 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3561 05:52:34.240664 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3562 05:52:34.244301 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 05:52:34.250932 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 05:52:34.254392 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 05:52:34.257342 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 05:52:34.264003 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 05:52:34.267047 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 05:52:34.270584 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 05:52:34.277083 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 05:52:34.280642 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 05:52:34.283771 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 05:52:34.290688 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 05:52:34.293687 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 05:52:34.297309 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 05:52:34.303896 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3576 05:52:34.307048 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3577 05:52:34.310708 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3578 05:52:34.313645 Total UI for P1: 0, mck2ui 16
3579 05:52:34.317030 best dqsien dly found for B0: ( 1, 3, 22)
3580 05:52:34.323513 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3581 05:52:34.323591 Total UI for P1: 0, mck2ui 16
3582 05:52:34.326874 best dqsien dly found for B1: ( 1, 3, 26)
3583 05:52:34.333482 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3584 05:52:34.337147 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3585 05:52:34.337247
3586 05:52:34.340039 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3587 05:52:34.343284 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3588 05:52:34.347045 [Gating] SW calibration Done
3589 05:52:34.347114 ==
3590 05:52:34.349825 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 05:52:34.353379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 05:52:34.353506 ==
3593 05:52:34.356918 RX Vref Scan: 0
3594 05:52:34.356989
3595 05:52:34.357055 RX Vref 0 -> 0, step: 1
3596 05:52:34.357145
3597 05:52:34.359856 RX Delay -40 -> 252, step: 8
3598 05:52:34.363428 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3599 05:52:34.370040 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3600 05:52:34.373687 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3601 05:52:34.376652 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3602 05:52:34.380100 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3603 05:52:34.383112 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3604 05:52:34.389754 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3605 05:52:34.393455 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3606 05:52:34.396867 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3607 05:52:34.399793 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3608 05:52:34.403397 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3609 05:52:34.406857 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3610 05:52:34.413156 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3611 05:52:34.416807 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3612 05:52:34.419786 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3613 05:52:34.422911 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3614 05:52:34.426414 ==
3615 05:52:34.426514 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 05:52:34.432990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 05:52:34.433105 ==
3618 05:52:34.433177 DQS Delay:
3619 05:52:34.436134 DQS0 = 0, DQS1 = 0
3620 05:52:34.436204 DQM Delay:
3621 05:52:34.439470 DQM0 = 110, DQM1 = 109
3622 05:52:34.439551 DQ Delay:
3623 05:52:34.443067 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3624 05:52:34.446114 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3625 05:52:34.449718 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3626 05:52:34.452718 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3627 05:52:34.452812
3628 05:52:34.452881
3629 05:52:34.452969 ==
3630 05:52:34.455892 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 05:52:34.462498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 05:52:34.462601 ==
3633 05:52:34.462692
3634 05:52:34.462778
3635 05:52:34.462867 TX Vref Scan disable
3636 05:52:34.466223 == TX Byte 0 ==
3637 05:52:34.469699 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3638 05:52:34.476322 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3639 05:52:34.476401 == TX Byte 1 ==
3640 05:52:34.479458 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3641 05:52:34.486065 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3642 05:52:34.486148 ==
3643 05:52:34.489654 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 05:52:34.492544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 05:52:34.492620 ==
3646 05:52:34.504302 TX Vref=22, minBit 9, minWin=25, winSum=423
3647 05:52:34.507404 TX Vref=24, minBit 9, minWin=25, winSum=423
3648 05:52:34.510825 TX Vref=26, minBit 9, minWin=25, winSum=432
3649 05:52:34.514213 TX Vref=28, minBit 8, minWin=26, winSum=434
3650 05:52:34.517325 TX Vref=30, minBit 1, minWin=26, winSum=430
3651 05:52:34.523910 TX Vref=32, minBit 1, minWin=26, winSum=434
3652 05:52:34.527444 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
3653 05:52:34.527545
3654 05:52:34.530538 Final TX Range 1 Vref 28
3655 05:52:34.530616
3656 05:52:34.530679 ==
3657 05:52:34.533581 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 05:52:34.537293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 05:52:34.537408 ==
3660 05:52:34.540787
3661 05:52:34.540859
3662 05:52:34.540919 TX Vref Scan disable
3663 05:52:34.543681 == TX Byte 0 ==
3664 05:52:34.547040 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3665 05:52:34.550205 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3666 05:52:34.553873 == TX Byte 1 ==
3667 05:52:34.557343 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3668 05:52:34.563944 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3669 05:52:34.564050
3670 05:52:34.564141 [DATLAT]
3671 05:52:34.564233 Freq=1200, CH1 RK1
3672 05:52:34.564322
3673 05:52:34.566850 DATLAT Default: 0xd
3674 05:52:34.566920 0, 0xFFFF, sum = 0
3675 05:52:34.570301 1, 0xFFFF, sum = 0
3676 05:52:34.573416 2, 0xFFFF, sum = 0
3677 05:52:34.573552 3, 0xFFFF, sum = 0
3678 05:52:34.577130 4, 0xFFFF, sum = 0
3679 05:52:34.577248 5, 0xFFFF, sum = 0
3680 05:52:34.580601 6, 0xFFFF, sum = 0
3681 05:52:34.580703 7, 0xFFFF, sum = 0
3682 05:52:34.583552 8, 0xFFFF, sum = 0
3683 05:52:34.583660 9, 0xFFFF, sum = 0
3684 05:52:34.587086 10, 0xFFFF, sum = 0
3685 05:52:34.587164 11, 0xFFFF, sum = 0
3686 05:52:34.590068 12, 0x0, sum = 1
3687 05:52:34.590176 13, 0x0, sum = 2
3688 05:52:34.593731 14, 0x0, sum = 3
3689 05:52:34.593809 15, 0x0, sum = 4
3690 05:52:34.593873 best_step = 13
3691 05:52:34.597367
3692 05:52:34.597464 ==
3693 05:52:34.600331 Dram Type= 6, Freq= 0, CH_1, rank 1
3694 05:52:34.603741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3695 05:52:34.603815 ==
3696 05:52:34.603877 RX Vref Scan: 0
3697 05:52:34.603936
3698 05:52:34.606655 RX Vref 0 -> 0, step: 1
3699 05:52:34.606743
3700 05:52:34.610293 RX Delay -21 -> 252, step: 4
3701 05:52:34.613375 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3702 05:52:34.620202 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3703 05:52:34.623814 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3704 05:52:34.627017 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3705 05:52:34.629924 iDelay=195, Bit 4, Center 108 (35 ~ 182) 148
3706 05:52:34.633565 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3707 05:52:34.640148 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3708 05:52:34.643100 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3709 05:52:34.646611 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3710 05:52:34.650108 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3711 05:52:34.653013 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3712 05:52:34.659773 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3713 05:52:34.663312 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3714 05:52:34.666393 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3715 05:52:34.669837 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3716 05:52:34.676405 iDelay=195, Bit 15, Center 120 (59 ~ 182) 124
3717 05:52:34.676480 ==
3718 05:52:34.679772 Dram Type= 6, Freq= 0, CH_1, rank 1
3719 05:52:34.682869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3720 05:52:34.682960 ==
3721 05:52:34.683024 DQS Delay:
3722 05:52:34.686506 DQS0 = 0, DQS1 = 0
3723 05:52:34.686588 DQM Delay:
3724 05:52:34.689749 DQM0 = 111, DQM1 = 110
3725 05:52:34.689825 DQ Delay:
3726 05:52:34.693215 DQ0 =114, DQ1 =108, DQ2 =102, DQ3 =108
3727 05:52:34.696097 DQ4 =108, DQ5 =120, DQ6 =120, DQ7 =108
3728 05:52:34.699669 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =102
3729 05:52:34.702674 DQ12 =120, DQ13 =116, DQ14 =120, DQ15 =120
3730 05:52:34.702777
3731 05:52:34.702853
3732 05:52:34.712625 [DQSOSCAuto] RK1, (LSB)MR18= 0xf807, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3733 05:52:34.716105 CH1 RK1: MR19=304, MR18=F807
3734 05:52:34.722500 CH1_RK1: MR19=0x304, MR18=0xF807, DQSOSC=407, MR23=63, INC=39, DEC=26
3735 05:52:34.722575 [RxdqsGatingPostProcess] freq 1200
3736 05:52:34.729563 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3737 05:52:34.732537 best DQS0 dly(2T, 0.5T) = (0, 11)
3738 05:52:34.736220 best DQS1 dly(2T, 0.5T) = (0, 11)
3739 05:52:34.739300 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3740 05:52:34.742369 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3741 05:52:34.745943 best DQS0 dly(2T, 0.5T) = (0, 11)
3742 05:52:34.748935 best DQS1 dly(2T, 0.5T) = (0, 11)
3743 05:52:34.752525 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3744 05:52:34.755536 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3745 05:52:34.759118 Pre-setting of DQS Precalculation
3746 05:52:34.762415 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3747 05:52:34.768831 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3748 05:52:34.778964 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3749 05:52:34.779043
3750 05:52:34.779109
3751 05:52:34.779173 [Calibration Summary] 2400 Mbps
3752 05:52:34.782118 CH 0, Rank 0
3753 05:52:34.785736 SW Impedance : PASS
3754 05:52:34.785834 DUTY Scan : NO K
3755 05:52:34.788560 ZQ Calibration : PASS
3756 05:52:34.788660 Jitter Meter : NO K
3757 05:52:34.792011 CBT Training : PASS
3758 05:52:34.795282 Write leveling : PASS
3759 05:52:34.795372 RX DQS gating : PASS
3760 05:52:34.798933 RX DQ/DQS(RDDQC) : PASS
3761 05:52:34.802154 TX DQ/DQS : PASS
3762 05:52:34.802232 RX DATLAT : PASS
3763 05:52:34.805579 RX DQ/DQS(Engine): PASS
3764 05:52:34.808968 TX OE : NO K
3765 05:52:34.809041 All Pass.
3766 05:52:34.809102
3767 05:52:34.809168 CH 0, Rank 1
3768 05:52:34.811824 SW Impedance : PASS
3769 05:52:34.815277 DUTY Scan : NO K
3770 05:52:34.815348 ZQ Calibration : PASS
3771 05:52:34.818869 Jitter Meter : NO K
3772 05:52:34.821759 CBT Training : PASS
3773 05:52:34.821856 Write leveling : PASS
3774 05:52:34.825300 RX DQS gating : PASS
3775 05:52:34.828689 RX DQ/DQS(RDDQC) : PASS
3776 05:52:34.828788 TX DQ/DQS : PASS
3777 05:52:34.831587 RX DATLAT : PASS
3778 05:52:34.835164 RX DQ/DQS(Engine): PASS
3779 05:52:34.835240 TX OE : NO K
3780 05:52:34.838170 All Pass.
3781 05:52:34.838265
3782 05:52:34.838353 CH 1, Rank 0
3783 05:52:34.841732 SW Impedance : PASS
3784 05:52:34.841800 DUTY Scan : NO K
3785 05:52:34.845263 ZQ Calibration : PASS
3786 05:52:34.848241 Jitter Meter : NO K
3787 05:52:34.848341 CBT Training : PASS
3788 05:52:34.851731 Write leveling : PASS
3789 05:52:34.851832 RX DQS gating : PASS
3790 05:52:34.855144 RX DQ/DQS(RDDQC) : PASS
3791 05:52:34.858119 TX DQ/DQS : PASS
3792 05:52:34.858222 RX DATLAT : PASS
3793 05:52:34.861738 RX DQ/DQS(Engine): PASS
3794 05:52:34.864654 TX OE : NO K
3795 05:52:34.864729 All Pass.
3796 05:52:34.864790
3797 05:52:34.864847 CH 1, Rank 1
3798 05:52:34.868129 SW Impedance : PASS
3799 05:52:34.871539 DUTY Scan : NO K
3800 05:52:34.871638 ZQ Calibration : PASS
3801 05:52:34.875095 Jitter Meter : NO K
3802 05:52:34.878153 CBT Training : PASS
3803 05:52:34.878255 Write leveling : PASS
3804 05:52:34.881145 RX DQS gating : PASS
3805 05:52:34.884731 RX DQ/DQS(RDDQC) : PASS
3806 05:52:34.884804 TX DQ/DQS : PASS
3807 05:52:34.887810 RX DATLAT : PASS
3808 05:52:34.891435 RX DQ/DQS(Engine): PASS
3809 05:52:34.891512 TX OE : NO K
3810 05:52:34.894369 All Pass.
3811 05:52:34.894468
3812 05:52:34.894559 DramC Write-DBI off
3813 05:52:34.897959 PER_BANK_REFRESH: Hybrid Mode
3814 05:52:34.898031 TX_TRACKING: ON
3815 05:52:34.907931 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3816 05:52:34.911137 [FAST_K] Save calibration result to emmc
3817 05:52:34.914401 dramc_set_vcore_voltage set vcore to 650000
3818 05:52:34.917815 Read voltage for 600, 5
3819 05:52:34.917889 Vio18 = 0
3820 05:52:34.920980 Vcore = 650000
3821 05:52:34.921052 Vdram = 0
3822 05:52:34.921114 Vddq = 0
3823 05:52:34.924089 Vmddr = 0
3824 05:52:34.927840 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3825 05:52:34.934182 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3826 05:52:34.934289 MEM_TYPE=3, freq_sel=19
3827 05:52:34.937702 sv_algorithm_assistance_LP4_1600
3828 05:52:34.944346 ============ PULL DRAM RESETB DOWN ============
3829 05:52:34.947356 ========== PULL DRAM RESETB DOWN end =========
3830 05:52:34.950872 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3831 05:52:34.953682 ===================================
3832 05:52:34.957205 LPDDR4 DRAM CONFIGURATION
3833 05:52:34.960338 ===================================
3834 05:52:34.963901 EX_ROW_EN[0] = 0x0
3835 05:52:34.963999 EX_ROW_EN[1] = 0x0
3836 05:52:34.967522 LP4Y_EN = 0x0
3837 05:52:34.967592 WORK_FSP = 0x0
3838 05:52:34.970432 WL = 0x2
3839 05:52:34.970505 RL = 0x2
3840 05:52:34.973869 BL = 0x2
3841 05:52:34.973964 RPST = 0x0
3842 05:52:34.977135 RD_PRE = 0x0
3843 05:52:34.977231 WR_PRE = 0x1
3844 05:52:34.980527 WR_PST = 0x0
3845 05:52:34.980599 DBI_WR = 0x0
3846 05:52:34.983470 DBI_RD = 0x0
3847 05:52:34.983546 OTF = 0x1
3848 05:52:34.986951 ===================================
3849 05:52:34.990403 ===================================
3850 05:52:34.993505 ANA top config
3851 05:52:34.997212 ===================================
3852 05:52:35.000061 DLL_ASYNC_EN = 0
3853 05:52:35.000156 ALL_SLAVE_EN = 1
3854 05:52:35.003514 NEW_RANK_MODE = 1
3855 05:52:35.006595 DLL_IDLE_MODE = 1
3856 05:52:35.009965 LP45_APHY_COMB_EN = 1
3857 05:52:35.010053 TX_ODT_DIS = 1
3858 05:52:35.013367 NEW_8X_MODE = 1
3859 05:52:35.016908 ===================================
3860 05:52:35.020268 ===================================
3861 05:52:35.023227 data_rate = 1200
3862 05:52:35.026678 CKR = 1
3863 05:52:35.030176 DQ_P2S_RATIO = 8
3864 05:52:35.033507 ===================================
3865 05:52:35.036778 CA_P2S_RATIO = 8
3866 05:52:35.036851 DQ_CA_OPEN = 0
3867 05:52:35.039756 DQ_SEMI_OPEN = 0
3868 05:52:35.043373 CA_SEMI_OPEN = 0
3869 05:52:35.046538 CA_FULL_RATE = 0
3870 05:52:35.049636 DQ_CKDIV4_EN = 1
3871 05:52:35.053087 CA_CKDIV4_EN = 1
3872 05:52:35.053191 CA_PREDIV_EN = 0
3873 05:52:35.056711 PH8_DLY = 0
3874 05:52:35.059708 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3875 05:52:35.063135 DQ_AAMCK_DIV = 4
3876 05:52:35.066314 CA_AAMCK_DIV = 4
3877 05:52:35.069931 CA_ADMCK_DIV = 4
3878 05:52:35.070008 DQ_TRACK_CA_EN = 0
3879 05:52:35.072894 CA_PICK = 600
3880 05:52:35.076417 CA_MCKIO = 600
3881 05:52:35.079498 MCKIO_SEMI = 0
3882 05:52:35.082802 PLL_FREQ = 2288
3883 05:52:35.086325 DQ_UI_PI_RATIO = 32
3884 05:52:35.089803 CA_UI_PI_RATIO = 0
3885 05:52:35.092906 ===================================
3886 05:52:35.096460 ===================================
3887 05:52:35.096533 memory_type:LPDDR4
3888 05:52:35.099334 GP_NUM : 10
3889 05:52:35.102880 SRAM_EN : 1
3890 05:52:35.102976 MD32_EN : 0
3891 05:52:35.105904 ===================================
3892 05:52:35.109567 [ANA_INIT] >>>>>>>>>>>>>>
3893 05:52:35.112453 <<<<<< [CONFIGURE PHASE]: ANA_TX
3894 05:52:35.116107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3895 05:52:35.119046 ===================================
3896 05:52:35.122564 data_rate = 1200,PCW = 0X5800
3897 05:52:35.126002 ===================================
3898 05:52:35.128959 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3899 05:52:35.132574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3900 05:52:35.139187 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3901 05:52:35.142579 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3902 05:52:35.146200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3903 05:52:35.148980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3904 05:52:35.152327 [ANA_INIT] flow start
3905 05:52:35.155744 [ANA_INIT] PLL >>>>>>>>
3906 05:52:35.155859 [ANA_INIT] PLL <<<<<<<<
3907 05:52:35.159094 [ANA_INIT] MIDPI >>>>>>>>
3908 05:52:35.162735 [ANA_INIT] MIDPI <<<<<<<<
3909 05:52:35.165945 [ANA_INIT] DLL >>>>>>>>
3910 05:52:35.166044 [ANA_INIT] flow end
3911 05:52:35.169257 ============ LP4 DIFF to SE enter ============
3912 05:52:35.175728 ============ LP4 DIFF to SE exit ============
3913 05:52:35.175806 [ANA_INIT] <<<<<<<<<<<<<
3914 05:52:35.178696 [Flow] Enable top DCM control >>>>>
3915 05:52:35.182493 [Flow] Enable top DCM control <<<<<
3916 05:52:35.185404 Enable DLL master slave shuffle
3917 05:52:35.192316 ==============================================================
3918 05:52:35.192398 Gating Mode config
3919 05:52:35.198586 ==============================================================
3920 05:52:35.201892 Config description:
3921 05:52:35.211825 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3922 05:52:35.218430 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3923 05:52:35.221874 SELPH_MODE 0: By rank 1: By Phase
3924 05:52:35.228933 ==============================================================
3925 05:52:35.231795 GAT_TRACK_EN = 1
3926 05:52:35.235410 RX_GATING_MODE = 2
3927 05:52:35.235509 RX_GATING_TRACK_MODE = 2
3928 05:52:35.238314 SELPH_MODE = 1
3929 05:52:35.241924 PICG_EARLY_EN = 1
3930 05:52:35.245040 VALID_LAT_VALUE = 1
3931 05:52:35.252034 ==============================================================
3932 05:52:35.254925 Enter into Gating configuration >>>>
3933 05:52:35.258306 Exit from Gating configuration <<<<
3934 05:52:35.261874 Enter into DVFS_PRE_config >>>>>
3935 05:52:35.271538 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3936 05:52:35.275010 Exit from DVFS_PRE_config <<<<<
3937 05:52:35.278495 Enter into PICG configuration >>>>
3938 05:52:35.281428 Exit from PICG configuration <<<<
3939 05:52:35.284855 [RX_INPUT] configuration >>>>>
3940 05:52:35.288342 [RX_INPUT] configuration <<<<<
3941 05:52:35.291760 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3942 05:52:35.298608 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3943 05:52:35.305068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3944 05:52:35.311711 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3945 05:52:35.314759 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3946 05:52:35.321983 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3947 05:52:35.324917 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3948 05:52:35.331395 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3949 05:52:35.334816 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3950 05:52:35.337880 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3951 05:52:35.341505 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3952 05:52:35.348148 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3953 05:52:35.351164 ===================================
3954 05:52:35.351245 LPDDR4 DRAM CONFIGURATION
3955 05:52:35.354754 ===================================
3956 05:52:35.357660 EX_ROW_EN[0] = 0x0
3957 05:52:35.361116 EX_ROW_EN[1] = 0x0
3958 05:52:35.361196 LP4Y_EN = 0x0
3959 05:52:35.364628 WORK_FSP = 0x0
3960 05:52:35.364708 WL = 0x2
3961 05:52:35.367544 RL = 0x2
3962 05:52:35.367624 BL = 0x2
3963 05:52:35.371203 RPST = 0x0
3964 05:52:35.371282 RD_PRE = 0x0
3965 05:52:35.374521 WR_PRE = 0x1
3966 05:52:35.374601 WR_PST = 0x0
3967 05:52:35.377472 DBI_WR = 0x0
3968 05:52:35.377591 DBI_RD = 0x0
3969 05:52:35.380874 OTF = 0x1
3970 05:52:35.384391 ===================================
3971 05:52:35.387969 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3972 05:52:35.390928 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3973 05:52:35.397241 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3974 05:52:35.400726 ===================================
3975 05:52:35.400801 LPDDR4 DRAM CONFIGURATION
3976 05:52:35.404262 ===================================
3977 05:52:35.407483 EX_ROW_EN[0] = 0x10
3978 05:52:35.410972 EX_ROW_EN[1] = 0x0
3979 05:52:35.411049 LP4Y_EN = 0x0
3980 05:52:35.414045 WORK_FSP = 0x0
3981 05:52:35.414117 WL = 0x2
3982 05:52:35.417088 RL = 0x2
3983 05:52:35.417184 BL = 0x2
3984 05:52:35.420548 RPST = 0x0
3985 05:52:35.420621 RD_PRE = 0x0
3986 05:52:35.424125 WR_PRE = 0x1
3987 05:52:35.424232 WR_PST = 0x0
3988 05:52:35.427114 DBI_WR = 0x0
3989 05:52:35.427186 DBI_RD = 0x0
3990 05:52:35.430574 OTF = 0x1
3991 05:52:35.433622 ===================================
3992 05:52:35.440082 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3993 05:52:35.443598 nWR fixed to 30
3994 05:52:35.447176 [ModeRegInit_LP4] CH0 RK0
3995 05:52:35.447274 [ModeRegInit_LP4] CH0 RK1
3996 05:52:35.450138 [ModeRegInit_LP4] CH1 RK0
3997 05:52:35.453779 [ModeRegInit_LP4] CH1 RK1
3998 05:52:35.453859 match AC timing 17
3999 05:52:35.460326 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4000 05:52:35.463241 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4001 05:52:35.466840 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4002 05:52:35.473238 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4003 05:52:35.476868 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4004 05:52:35.476982 ==
4005 05:52:35.479767 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 05:52:35.483277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 05:52:35.483382 ==
4008 05:52:35.489681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4009 05:52:35.496554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4010 05:52:35.499517 [CA 0] Center 37 (7~67) winsize 61
4011 05:52:35.502926 [CA 1] Center 36 (6~67) winsize 62
4012 05:52:35.506312 [CA 2] Center 35 (5~65) winsize 61
4013 05:52:35.509278 [CA 3] Center 35 (5~65) winsize 61
4014 05:52:35.512864 [CA 4] Center 34 (4~65) winsize 62
4015 05:52:35.515873 [CA 5] Center 34 (4~64) winsize 61
4016 05:52:35.515951
4017 05:52:35.519552 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4018 05:52:35.519665
4019 05:52:35.522658 [CATrainingPosCal] consider 1 rank data
4020 05:52:35.525860 u2DelayCellTimex100 = 270/100 ps
4021 05:52:35.529460 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4022 05:52:35.532451 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4023 05:52:35.536076 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4024 05:52:35.539299 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4025 05:52:35.545881 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4026 05:52:35.549058 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4027 05:52:35.549163
4028 05:52:35.552651 CA PerBit enable=1, Macro0, CA PI delay=34
4029 05:52:35.552738
4030 05:52:35.555957 [CBTSetCACLKResult] CA Dly = 34
4031 05:52:35.556085 CS Dly: 4 (0~35)
4032 05:52:35.556207 ==
4033 05:52:35.559211 Dram Type= 6, Freq= 0, CH_0, rank 1
4034 05:52:35.565931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 05:52:35.566037 ==
4036 05:52:35.569076 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4037 05:52:35.575542 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4038 05:52:35.579165 [CA 0] Center 37 (7~67) winsize 61
4039 05:52:35.582216 [CA 1] Center 37 (7~67) winsize 61
4040 05:52:35.585293 [CA 2] Center 35 (5~65) winsize 61
4041 05:52:35.588919 [CA 3] Center 35 (5~65) winsize 61
4042 05:52:35.591991 [CA 4] Center 34 (4~65) winsize 62
4043 05:52:35.595093 [CA 5] Center 34 (3~65) winsize 63
4044 05:52:35.595193
4045 05:52:35.598702 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4046 05:52:35.598802
4047 05:52:35.601811 [CATrainingPosCal] consider 2 rank data
4048 05:52:35.605335 u2DelayCellTimex100 = 270/100 ps
4049 05:52:35.608363 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4050 05:52:35.615368 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4051 05:52:35.618539 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4052 05:52:35.621678 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4053 05:52:35.625373 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4054 05:52:35.628400 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4055 05:52:35.628502
4056 05:52:35.631674 CA PerBit enable=1, Macro0, CA PI delay=34
4057 05:52:35.631775
4058 05:52:35.634835 [CBTSetCACLKResult] CA Dly = 34
4059 05:52:35.638467 CS Dly: 5 (0~37)
4060 05:52:35.638541
4061 05:52:35.641451 ----->DramcWriteLeveling(PI) begin...
4062 05:52:35.641541 ==
4063 05:52:35.644934 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 05:52:35.647832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 05:52:35.647935 ==
4066 05:52:35.651432 Write leveling (Byte 0): 33 => 33
4067 05:52:35.654956 Write leveling (Byte 1): 30 => 30
4068 05:52:35.658049 DramcWriteLeveling(PI) end<-----
4069 05:52:35.658151
4070 05:52:35.658243 ==
4071 05:52:35.661393 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 05:52:35.664668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 05:52:35.664742 ==
4074 05:52:35.667758 [Gating] SW mode calibration
4075 05:52:35.674710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4076 05:52:35.681316 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4077 05:52:35.684474 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4078 05:52:35.687600 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4079 05:52:35.694311 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4080 05:52:35.698009 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4081 05:52:35.701093 0 9 16 | B1->B0 | 3232 2d2d | 1 1 | (0 0) (1 0)
4082 05:52:35.707528 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4083 05:52:35.710565 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4084 05:52:35.714400 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 05:52:35.720497 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4086 05:52:35.723933 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4087 05:52:35.727242 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4088 05:52:35.733598 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4089 05:52:35.737179 0 10 16 | B1->B0 | 2f2f 3939 | 0 1 | (0 0) (0 0)
4090 05:52:35.740311 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4091 05:52:35.747016 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 05:52:35.750076 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 05:52:35.753634 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 05:52:35.760211 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 05:52:35.763988 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 05:52:35.767148 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4097 05:52:35.773253 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4098 05:52:35.777057 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 05:52:35.780042 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 05:52:35.786811 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 05:52:35.789970 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 05:52:35.793562 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 05:52:35.800106 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 05:52:35.803635 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 05:52:35.806700 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 05:52:35.813308 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 05:52:35.816285 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 05:52:35.819795 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 05:52:35.826567 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 05:52:35.829406 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 05:52:35.832999 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 05:52:35.839875 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4113 05:52:35.843131 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4114 05:52:35.846466 Total UI for P1: 0, mck2ui 16
4115 05:52:35.849631 best dqsien dly found for B0: ( 0, 13, 12)
4116 05:52:35.853124 Total UI for P1: 0, mck2ui 16
4117 05:52:35.856271 best dqsien dly found for B1: ( 0, 13, 14)
4118 05:52:35.859656 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4119 05:52:35.862657 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4120 05:52:35.862758
4121 05:52:35.866077 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4122 05:52:35.869086 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4123 05:52:35.872761 [Gating] SW calibration Done
4124 05:52:35.872841 ==
4125 05:52:35.875812 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 05:52:35.882515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 05:52:35.882620 ==
4128 05:52:35.882723 RX Vref Scan: 0
4129 05:52:35.882826
4130 05:52:35.886168 RX Vref 0 -> 0, step: 1
4131 05:52:35.886245
4132 05:52:35.889223 RX Delay -230 -> 252, step: 16
4133 05:52:35.892326 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4134 05:52:35.895908 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4135 05:52:35.898938 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4136 05:52:35.905680 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4137 05:52:35.909346 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4138 05:52:35.912471 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4139 05:52:35.915413 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4140 05:52:35.922305 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4141 05:52:35.925516 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4142 05:52:35.929065 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4143 05:52:35.932209 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4144 05:52:35.935346 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4145 05:52:35.942000 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4146 05:52:35.945084 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4147 05:52:35.948853 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4148 05:52:35.955390 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4149 05:52:35.955498 ==
4150 05:52:35.958825 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 05:52:35.961812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 05:52:35.961887 ==
4153 05:52:35.961951 DQS Delay:
4154 05:52:35.965018 DQS0 = 0, DQS1 = 0
4155 05:52:35.965121 DQM Delay:
4156 05:52:35.968319 DQM0 = 37, DQM1 = 28
4157 05:52:35.968420 DQ Delay:
4158 05:52:35.971658 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =41
4159 05:52:35.975177 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4160 05:52:35.978879 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4161 05:52:35.981864 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4162 05:52:35.981936
4163 05:52:35.981999
4164 05:52:35.982058 ==
4165 05:52:35.984805 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 05:52:35.988331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 05:52:35.988430 ==
4168 05:52:35.988519
4169 05:52:35.988605
4170 05:52:35.992081 TX Vref Scan disable
4171 05:52:35.995245 == TX Byte 0 ==
4172 05:52:35.998385 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4173 05:52:36.001427 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4174 05:52:36.005269 == TX Byte 1 ==
4175 05:52:36.008354 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4176 05:52:36.011891 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4177 05:52:36.011973 ==
4178 05:52:36.015040 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 05:52:36.021810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 05:52:36.021893 ==
4181 05:52:36.021958
4182 05:52:36.022018
4183 05:52:36.022076 TX Vref Scan disable
4184 05:52:36.026137 == TX Byte 0 ==
4185 05:52:36.029149 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4186 05:52:36.035903 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4187 05:52:36.035986 == TX Byte 1 ==
4188 05:52:36.039034 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4189 05:52:36.045766 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4190 05:52:36.045906
4191 05:52:36.046000 [DATLAT]
4192 05:52:36.046093 Freq=600, CH0 RK0
4193 05:52:36.046188
4194 05:52:36.049588 DATLAT Default: 0x9
4195 05:52:36.049670 0, 0xFFFF, sum = 0
4196 05:52:36.052667 1, 0xFFFF, sum = 0
4197 05:52:36.055677 2, 0xFFFF, sum = 0
4198 05:52:36.055785 3, 0xFFFF, sum = 0
4199 05:52:36.059419 4, 0xFFFF, sum = 0
4200 05:52:36.059531 5, 0xFFFF, sum = 0
4201 05:52:36.062555 6, 0xFFFF, sum = 0
4202 05:52:36.062634 7, 0xFFFF, sum = 0
4203 05:52:36.065524 8, 0x0, sum = 1
4204 05:52:36.065619 9, 0x0, sum = 2
4205 05:52:36.065685 10, 0x0, sum = 3
4206 05:52:36.069327 11, 0x0, sum = 4
4207 05:52:36.069410 best_step = 9
4208 05:52:36.069502
4209 05:52:36.069611 ==
4210 05:52:36.072367 Dram Type= 6, Freq= 0, CH_0, rank 0
4211 05:52:36.078995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 05:52:36.079077 ==
4213 05:52:36.079143 RX Vref Scan: 1
4214 05:52:36.079210
4215 05:52:36.082107 RX Vref 0 -> 0, step: 1
4216 05:52:36.082196
4217 05:52:36.085443 RX Delay -195 -> 252, step: 8
4218 05:52:36.085583
4219 05:52:36.088683 Set Vref, RX VrefLevel [Byte0]: 64
4220 05:52:36.092597 [Byte1]: 52
4221 05:52:36.092681
4222 05:52:36.095496 Final RX Vref Byte 0 = 64 to rank0
4223 05:52:36.099147 Final RX Vref Byte 1 = 52 to rank0
4224 05:52:36.102299 Final RX Vref Byte 0 = 64 to rank1
4225 05:52:36.105277 Final RX Vref Byte 1 = 52 to rank1==
4226 05:52:36.108906 Dram Type= 6, Freq= 0, CH_0, rank 0
4227 05:52:36.111934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 05:52:36.112035 ==
4229 05:52:36.115495 DQS Delay:
4230 05:52:36.115618 DQS0 = 0, DQS1 = 0
4231 05:52:36.118631 DQM Delay:
4232 05:52:36.118699 DQM0 = 36, DQM1 = 29
4233 05:52:36.118760 DQ Delay:
4234 05:52:36.121701 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4235 05:52:36.125437 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =44
4236 05:52:36.128459 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =24
4237 05:52:36.132257 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4238 05:52:36.132342
4239 05:52:36.132408
4240 05:52:36.142061 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4241 05:52:36.145036 CH0 RK0: MR19=808, MR18=3F3D
4242 05:52:36.151904 CH0_RK0: MR19=0x808, MR18=0x3F3D, DQSOSC=397, MR23=63, INC=166, DEC=110
4243 05:52:36.152013
4244 05:52:36.155055 ----->DramcWriteLeveling(PI) begin...
4245 05:52:36.155142 ==
4246 05:52:36.158181 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 05:52:36.162004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 05:52:36.162102 ==
4249 05:52:36.165273 Write leveling (Byte 0): 34 => 34
4250 05:52:36.168090 Write leveling (Byte 1): 30 => 30
4251 05:52:36.171985 DramcWriteLeveling(PI) end<-----
4252 05:52:36.172090
4253 05:52:36.172185 ==
4254 05:52:36.174578 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 05:52:36.178292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 05:52:36.178378 ==
4257 05:52:36.181341 [Gating] SW mode calibration
4258 05:52:36.187874 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4259 05:52:36.194426 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4260 05:52:36.197796 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4261 05:52:36.201114 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4262 05:52:36.208119 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4263 05:52:36.211200 0 9 12 | B1->B0 | 3434 2f2f | 0 1 | (0 1) (0 0)
4264 05:52:36.214671 0 9 16 | B1->B0 | 2a2a 2424 | 1 1 | (0 0) (1 0)
4265 05:52:36.221297 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4266 05:52:36.224317 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4267 05:52:36.227826 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 05:52:36.234175 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 05:52:36.237967 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 05:52:36.241095 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 05:52:36.247469 0 10 12 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 0)
4272 05:52:36.250653 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4273 05:52:36.254212 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 05:52:36.260927 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 05:52:36.263942 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 05:52:36.267515 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 05:52:36.274362 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 05:52:36.277526 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 05:52:36.280471 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4280 05:52:36.287443 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4281 05:52:36.290368 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 05:52:36.293860 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 05:52:36.300635 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 05:52:36.303705 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 05:52:36.307440 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 05:52:36.313548 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 05:52:36.317138 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 05:52:36.320013 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 05:52:36.326906 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 05:52:36.330044 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 05:52:36.333113 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 05:52:36.339799 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 05:52:36.343706 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 05:52:36.346335 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 05:52:36.353074 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4296 05:52:36.356613 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4297 05:52:36.359682 Total UI for P1: 0, mck2ui 16
4298 05:52:36.363541 best dqsien dly found for B0: ( 0, 13, 12)
4299 05:52:36.366571 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 05:52:36.369692 Total UI for P1: 0, mck2ui 16
4301 05:52:36.373048 best dqsien dly found for B1: ( 0, 13, 16)
4302 05:52:36.376762 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4303 05:52:36.379902 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4304 05:52:36.379980
4305 05:52:36.386486 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4306 05:52:36.390085 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4307 05:52:36.390170 [Gating] SW calibration Done
4308 05:52:36.393020 ==
4309 05:52:36.396565 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 05:52:36.400248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 05:52:36.400332 ==
4312 05:52:36.400399 RX Vref Scan: 0
4313 05:52:36.400462
4314 05:52:36.403175 RX Vref 0 -> 0, step: 1
4315 05:52:36.403258
4316 05:52:36.406747 RX Delay -230 -> 252, step: 16
4317 05:52:36.409878 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4318 05:52:36.412979 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4319 05:52:36.419411 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4320 05:52:36.423062 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4321 05:52:36.426723 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4322 05:52:36.429935 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4323 05:52:36.436536 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4324 05:52:36.439496 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4325 05:52:36.443033 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4326 05:52:36.446018 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4327 05:52:36.449768 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4328 05:52:36.455800 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4329 05:52:36.459040 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4330 05:52:36.462370 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4331 05:52:36.469282 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4332 05:52:36.472447 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4333 05:52:36.472556 ==
4334 05:52:36.475987 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 05:52:36.479003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 05:52:36.479087 ==
4337 05:52:36.479154 DQS Delay:
4338 05:52:36.482191 DQS0 = 0, DQS1 = 0
4339 05:52:36.482305 DQM Delay:
4340 05:52:36.485931 DQM0 = 39, DQM1 = 30
4341 05:52:36.486048 DQ Delay:
4342 05:52:36.488948 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4343 05:52:36.492635 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4344 05:52:36.495593 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4345 05:52:36.499141 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4346 05:52:36.499255
4347 05:52:36.499356
4348 05:52:36.499454 ==
4349 05:52:36.502202 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 05:52:36.508834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 05:52:36.508946 ==
4352 05:52:36.509042
4353 05:52:36.509139
4354 05:52:36.509228 TX Vref Scan disable
4355 05:52:36.512051 == TX Byte 0 ==
4356 05:52:36.515801 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4357 05:52:36.521946 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4358 05:52:36.522031 == TX Byte 1 ==
4359 05:52:36.525550 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4360 05:52:36.532387 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4361 05:52:36.532500 ==
4362 05:52:36.535481 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 05:52:36.538536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 05:52:36.538649 ==
4365 05:52:36.538745
4366 05:52:36.538837
4367 05:52:36.541696 TX Vref Scan disable
4368 05:52:36.545401 == TX Byte 0 ==
4369 05:52:36.548492 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4370 05:52:36.551559 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4371 05:52:36.555206 == TX Byte 1 ==
4372 05:52:36.558334 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4373 05:52:36.561495 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4374 05:52:36.561574
4375 05:52:36.565138 [DATLAT]
4376 05:52:36.565244 Freq=600, CH0 RK1
4377 05:52:36.565341
4378 05:52:36.568134 DATLAT Default: 0x9
4379 05:52:36.568248 0, 0xFFFF, sum = 0
4380 05:52:36.571927 1, 0xFFFF, sum = 0
4381 05:52:36.572041 2, 0xFFFF, sum = 0
4382 05:52:36.574640 3, 0xFFFF, sum = 0
4383 05:52:36.574755 4, 0xFFFF, sum = 0
4384 05:52:36.578055 5, 0xFFFF, sum = 0
4385 05:52:36.578154 6, 0xFFFF, sum = 0
4386 05:52:36.581763 7, 0xFFFF, sum = 0
4387 05:52:36.581854 8, 0x0, sum = 1
4388 05:52:36.584588 9, 0x0, sum = 2
4389 05:52:36.584703 10, 0x0, sum = 3
4390 05:52:36.587850 11, 0x0, sum = 4
4391 05:52:36.587964 best_step = 9
4392 05:52:36.588060
4393 05:52:36.588152 ==
4394 05:52:36.591643 Dram Type= 6, Freq= 0, CH_0, rank 1
4395 05:52:36.594798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 05:52:36.594905 ==
4397 05:52:36.597966 RX Vref Scan: 0
4398 05:52:36.598048
4399 05:52:36.601376 RX Vref 0 -> 0, step: 1
4400 05:52:36.601459
4401 05:52:36.601537 RX Delay -195 -> 252, step: 8
4402 05:52:36.609567 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4403 05:52:36.612625 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4404 05:52:36.616300 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4405 05:52:36.619477 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4406 05:52:36.625952 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4407 05:52:36.629134 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4408 05:52:36.632582 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4409 05:52:36.635758 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4410 05:52:36.642545 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4411 05:52:36.645530 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4412 05:52:36.649363 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4413 05:52:36.652315 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4414 05:52:36.659132 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4415 05:52:36.662137 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4416 05:52:36.665367 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4417 05:52:36.669074 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4418 05:52:36.669157 ==
4419 05:52:36.672032 Dram Type= 6, Freq= 0, CH_0, rank 1
4420 05:52:36.679084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 05:52:36.679168 ==
4422 05:52:36.679234 DQS Delay:
4423 05:52:36.682270 DQS0 = 0, DQS1 = 0
4424 05:52:36.682353 DQM Delay:
4425 05:52:36.682418 DQM0 = 33, DQM1 = 28
4426 05:52:36.685339 DQ Delay:
4427 05:52:36.688724 DQ0 =32, DQ1 =32, DQ2 =32, DQ3 =28
4428 05:52:36.691833 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4429 05:52:36.695500 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4430 05:52:36.698638 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4431 05:52:36.698723
4432 05:52:36.698789
4433 05:52:36.705468 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b39, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
4434 05:52:36.708757 CH0 RK1: MR19=808, MR18=6B39
4435 05:52:36.715112 CH0_RK1: MR19=0x808, MR18=0x6B39, DQSOSC=389, MR23=63, INC=173, DEC=115
4436 05:52:36.718461 [RxdqsGatingPostProcess] freq 600
4437 05:52:36.722087 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4438 05:52:36.725015 Pre-setting of DQS Precalculation
4439 05:52:36.731704 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4440 05:52:36.731816 ==
4441 05:52:36.735210 Dram Type= 6, Freq= 0, CH_1, rank 0
4442 05:52:36.738373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 05:52:36.738458 ==
4444 05:52:36.744946 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4445 05:52:36.751532 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4446 05:52:36.754752 [CA 0] Center 35 (5~66) winsize 62
4447 05:52:36.758160 [CA 1] Center 36 (6~66) winsize 61
4448 05:52:36.761705 [CA 2] Center 34 (4~65) winsize 62
4449 05:52:36.764834 [CA 3] Center 34 (4~65) winsize 62
4450 05:52:36.768060 [CA 4] Center 34 (4~65) winsize 62
4451 05:52:36.771690 [CA 5] Center 33 (3~64) winsize 62
4452 05:52:36.771773
4453 05:52:36.774814 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4454 05:52:36.774898
4455 05:52:36.778023 [CATrainingPosCal] consider 1 rank data
4456 05:52:36.781627 u2DelayCellTimex100 = 270/100 ps
4457 05:52:36.784841 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4458 05:52:36.788014 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4459 05:52:36.791304 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4460 05:52:36.794402 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4461 05:52:36.797958 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4462 05:52:36.801347 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4463 05:52:36.801431
4464 05:52:36.807727 CA PerBit enable=1, Macro0, CA PI delay=33
4465 05:52:36.807812
4466 05:52:36.807879 [CBTSetCACLKResult] CA Dly = 33
4467 05:52:36.811320 CS Dly: 5 (0~36)
4468 05:52:36.811404 ==
4469 05:52:36.814733 Dram Type= 6, Freq= 0, CH_1, rank 1
4470 05:52:36.817806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 05:52:36.817890 ==
4472 05:52:36.824383 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4473 05:52:36.830745 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4474 05:52:36.834166 [CA 0] Center 36 (6~66) winsize 61
4475 05:52:36.837419 [CA 1] Center 36 (6~66) winsize 61
4476 05:52:36.840689 [CA 2] Center 34 (4~65) winsize 62
4477 05:52:36.844412 [CA 3] Center 34 (3~65) winsize 63
4478 05:52:36.847322 [CA 4] Center 34 (4~65) winsize 62
4479 05:52:36.850443 [CA 5] Center 33 (3~64) winsize 62
4480 05:52:36.850553
4481 05:52:36.853955 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4482 05:52:36.854039
4483 05:52:36.856987 [CATrainingPosCal] consider 2 rank data
4484 05:52:36.860455 u2DelayCellTimex100 = 270/100 ps
4485 05:52:36.863968 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4486 05:52:36.867137 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4487 05:52:36.870592 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4488 05:52:36.873763 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4489 05:52:36.880321 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4490 05:52:36.883929 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4491 05:52:36.884010
4492 05:52:36.886925 CA PerBit enable=1, Macro0, CA PI delay=33
4493 05:52:36.887007
4494 05:52:36.890181 [CBTSetCACLKResult] CA Dly = 33
4495 05:52:36.890276 CS Dly: 5 (0~36)
4496 05:52:36.890371
4497 05:52:36.893758 ----->DramcWriteLeveling(PI) begin...
4498 05:52:36.893856 ==
4499 05:52:36.896661 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 05:52:36.903467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 05:52:36.903583 ==
4502 05:52:36.906926 Write leveling (Byte 0): 30 => 30
4503 05:52:36.909918 Write leveling (Byte 1): 31 => 31
4504 05:52:36.910030 DramcWriteLeveling(PI) end<-----
4505 05:52:36.913195
4506 05:52:36.913300 ==
4507 05:52:36.916644 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 05:52:36.920199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 05:52:36.920280 ==
4510 05:52:36.923273 [Gating] SW mode calibration
4511 05:52:36.930112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4512 05:52:36.933095 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4513 05:52:36.939916 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4514 05:52:36.943417 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4515 05:52:36.946472 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4516 05:52:36.953151 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
4517 05:52:36.956506 0 9 16 | B1->B0 | 2626 2929 | 0 0 | (1 1) (0 0)
4518 05:52:36.959936 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4519 05:52:36.966421 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4520 05:52:36.969979 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 05:52:36.973086 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4522 05:52:36.979501 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4523 05:52:36.982743 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4524 05:52:36.986418 0 10 12 | B1->B0 | 2828 2a2a | 1 0 | (0 0) (0 0)
4525 05:52:36.993188 0 10 16 | B1->B0 | 4040 4141 | 0 0 | (0 0) (0 0)
4526 05:52:36.996275 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 05:52:36.999293 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 05:52:37.005991 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 05:52:37.009465 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 05:52:37.012560 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 05:52:37.019758 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 05:52:37.022673 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4533 05:52:37.025961 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 05:52:37.032728 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 05:52:37.035875 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 05:52:37.039589 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 05:52:37.045751 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 05:52:37.049377 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 05:52:37.052504 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 05:52:37.059306 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 05:52:37.062183 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 05:52:37.065801 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 05:52:37.072579 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 05:52:37.075768 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 05:52:37.078945 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 05:52:37.082223 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 05:52:37.088952 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 05:52:37.092398 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 05:52:37.095945 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4550 05:52:37.098923 Total UI for P1: 0, mck2ui 16
4551 05:52:37.102707 best dqsien dly found for B0: ( 0, 13, 14)
4552 05:52:37.105642 Total UI for P1: 0, mck2ui 16
4553 05:52:37.109385 best dqsien dly found for B1: ( 0, 13, 14)
4554 05:52:37.112393 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4555 05:52:37.119204 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4556 05:52:37.119289
4557 05:52:37.122143 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4558 05:52:37.125818 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4559 05:52:37.128801 [Gating] SW calibration Done
4560 05:52:37.128885 ==
4561 05:52:37.132318 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 05:52:37.135377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 05:52:37.135462 ==
4564 05:52:37.135528 RX Vref Scan: 0
4565 05:52:37.138651
4566 05:52:37.138734 RX Vref 0 -> 0, step: 1
4567 05:52:37.138801
4568 05:52:37.142374 RX Delay -230 -> 252, step: 16
4569 05:52:37.145702 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4570 05:52:37.152057 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4571 05:52:37.155563 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4572 05:52:37.158558 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4573 05:52:37.162236 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4574 05:52:37.168581 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4575 05:52:37.171592 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4576 05:52:37.175082 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4577 05:52:37.178205 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4578 05:52:37.182215 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4579 05:52:37.188320 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4580 05:52:37.191737 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4581 05:52:37.195157 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4582 05:52:37.198339 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4583 05:52:37.204741 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4584 05:52:37.207875 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4585 05:52:37.207960 ==
4586 05:52:37.211416 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 05:52:37.214444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 05:52:37.214528 ==
4589 05:52:37.218097 DQS Delay:
4590 05:52:37.218180 DQS0 = 0, DQS1 = 0
4591 05:52:37.221087 DQM Delay:
4592 05:52:37.221170 DQM0 = 39, DQM1 = 32
4593 05:52:37.221237 DQ Delay:
4594 05:52:37.224632 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4595 05:52:37.227611 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4596 05:52:37.231391 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4597 05:52:37.234825 DQ12 =41, DQ13 =33, DQ14 =33, DQ15 =33
4598 05:52:37.234907
4599 05:52:37.234973
4600 05:52:37.235032 ==
4601 05:52:37.237664 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 05:52:37.244386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 05:52:37.244471 ==
4604 05:52:37.244558
4605 05:52:37.244640
4606 05:52:37.244719 TX Vref Scan disable
4607 05:52:37.248594 == TX Byte 0 ==
4608 05:52:37.252021 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4609 05:52:37.258532 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4610 05:52:37.258615 == TX Byte 1 ==
4611 05:52:37.261566 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4612 05:52:37.268122 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4613 05:52:37.268204 ==
4614 05:52:37.271499 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 05:52:37.274606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 05:52:37.274688 ==
4617 05:52:37.274753
4618 05:52:37.274813
4619 05:52:37.278308 TX Vref Scan disable
4620 05:52:37.281248 == TX Byte 0 ==
4621 05:52:37.284786 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4622 05:52:37.288227 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4623 05:52:37.291341 == TX Byte 1 ==
4624 05:52:37.294901 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4625 05:52:37.298002 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4626 05:52:37.298085
4627 05:52:37.298149 [DATLAT]
4628 05:52:37.300884 Freq=600, CH1 RK0
4629 05:52:37.300966
4630 05:52:37.304459 DATLAT Default: 0x9
4631 05:52:37.304540 0, 0xFFFF, sum = 0
4632 05:52:37.307839 1, 0xFFFF, sum = 0
4633 05:52:37.307923 2, 0xFFFF, sum = 0
4634 05:52:37.311171 3, 0xFFFF, sum = 0
4635 05:52:37.311254 4, 0xFFFF, sum = 0
4636 05:52:37.314317 5, 0xFFFF, sum = 0
4637 05:52:37.314401 6, 0xFFFF, sum = 0
4638 05:52:37.317644 7, 0xFFFF, sum = 0
4639 05:52:37.317727 8, 0x0, sum = 1
4640 05:52:37.320878 9, 0x0, sum = 2
4641 05:52:37.320964 10, 0x0, sum = 3
4642 05:52:37.324672 11, 0x0, sum = 4
4643 05:52:37.324758 best_step = 9
4644 05:52:37.324845
4645 05:52:37.324926 ==
4646 05:52:37.327769 Dram Type= 6, Freq= 0, CH_1, rank 0
4647 05:52:37.331416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 05:52:37.331501 ==
4649 05:52:37.334439 RX Vref Scan: 1
4650 05:52:37.334531
4651 05:52:37.337867 RX Vref 0 -> 0, step: 1
4652 05:52:37.337977
4653 05:52:37.338065 RX Delay -179 -> 252, step: 8
4654 05:52:37.338147
4655 05:52:37.340970 Set Vref, RX VrefLevel [Byte0]: 54
4656 05:52:37.344187 [Byte1]: 55
4657 05:52:37.349002
4658 05:52:37.349086 Final RX Vref Byte 0 = 54 to rank0
4659 05:52:37.352076 Final RX Vref Byte 1 = 55 to rank0
4660 05:52:37.355632 Final RX Vref Byte 0 = 54 to rank1
4661 05:52:37.358627 Final RX Vref Byte 1 = 55 to rank1==
4662 05:52:37.362236 Dram Type= 6, Freq= 0, CH_1, rank 0
4663 05:52:37.368468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 05:52:37.368566 ==
4665 05:52:37.368646 DQS Delay:
4666 05:52:37.371953 DQS0 = 0, DQS1 = 0
4667 05:52:37.372036 DQM Delay:
4668 05:52:37.372129 DQM0 = 39, DQM1 = 28
4669 05:52:37.375115 DQ Delay:
4670 05:52:37.378280 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4671 05:52:37.381456 DQ4 =36, DQ5 =52, DQ6 =52, DQ7 =36
4672 05:52:37.385013 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4673 05:52:37.388613 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4674 05:52:37.388709
4675 05:52:37.388774
4676 05:52:37.395210 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c2a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
4677 05:52:37.398298 CH1 RK0: MR19=808, MR18=1C2A
4678 05:52:37.405043 CH1_RK0: MR19=0x808, MR18=0x1C2A, DQSOSC=401, MR23=63, INC=163, DEC=108
4679 05:52:37.405126
4680 05:52:37.408088 ----->DramcWriteLeveling(PI) begin...
4681 05:52:37.408171 ==
4682 05:52:37.411733 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 05:52:37.414712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 05:52:37.414795 ==
4685 05:52:37.418345 Write leveling (Byte 0): 27 => 27
4686 05:52:37.421751 Write leveling (Byte 1): 31 => 31
4687 05:52:37.424735 DramcWriteLeveling(PI) end<-----
4688 05:52:37.424814
4689 05:52:37.424877 ==
4690 05:52:37.428154 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 05:52:37.431423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 05:52:37.431500 ==
4693 05:52:37.434670 [Gating] SW mode calibration
4694 05:52:37.441647 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4695 05:52:37.448286 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4696 05:52:37.451144 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4697 05:52:37.458272 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4698 05:52:37.461286 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4699 05:52:37.464922 0 9 12 | B1->B0 | 3333 3030 | 0 0 | (0 1) (0 1)
4700 05:52:37.471483 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
4701 05:52:37.474421 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4702 05:52:37.478011 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4703 05:52:37.484895 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4704 05:52:37.487967 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4705 05:52:37.491260 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4706 05:52:37.497542 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4707 05:52:37.501058 0 10 12 | B1->B0 | 2f2f 3939 | 1 0 | (0 0) (0 0)
4708 05:52:37.504279 0 10 16 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
4709 05:52:37.511225 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 05:52:37.514315 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 05:52:37.517854 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 05:52:37.521029 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 05:52:37.527905 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 05:52:37.530847 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 05:52:37.534496 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4716 05:52:37.540959 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 05:52:37.544221 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 05:52:37.547308 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 05:52:37.554473 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 05:52:37.557330 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 05:52:37.560915 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 05:52:37.567609 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 05:52:37.570567 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 05:52:37.574116 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 05:52:37.580602 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 05:52:37.584219 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 05:52:37.587203 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 05:52:37.593695 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 05:52:37.597052 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 05:52:37.600526 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4731 05:52:37.607359 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4732 05:52:37.610670 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4733 05:52:37.613770 Total UI for P1: 0, mck2ui 16
4734 05:52:37.616912 best dqsien dly found for B0: ( 0, 13, 10)
4735 05:52:37.620569 Total UI for P1: 0, mck2ui 16
4736 05:52:37.623423 best dqsien dly found for B1: ( 0, 13, 12)
4737 05:52:37.627129 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4738 05:52:37.630534 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4739 05:52:37.630609
4740 05:52:37.633563 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4741 05:52:37.637142 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4742 05:52:37.640074 [Gating] SW calibration Done
4743 05:52:37.640149 ==
4744 05:52:37.643730 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 05:52:37.650262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 05:52:37.650342 ==
4747 05:52:37.650405 RX Vref Scan: 0
4748 05:52:37.650465
4749 05:52:37.653260 RX Vref 0 -> 0, step: 1
4750 05:52:37.653358
4751 05:52:37.657068 RX Delay -230 -> 252, step: 16
4752 05:52:37.659888 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4753 05:52:37.663484 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4754 05:52:37.666891 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4755 05:52:37.673406 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4756 05:52:37.676516 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4757 05:52:37.680155 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4758 05:52:37.683136 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4759 05:52:37.690171 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4760 05:52:37.693237 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4761 05:52:37.696244 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4762 05:52:37.699688 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4763 05:52:37.706483 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4764 05:52:37.709378 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4765 05:52:37.713069 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4766 05:52:37.716123 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4767 05:52:37.719595 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4768 05:52:37.722775 ==
4769 05:52:37.726065 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 05:52:37.729311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 05:52:37.729396 ==
4772 05:52:37.729522 DQS Delay:
4773 05:52:37.732481 DQS0 = 0, DQS1 = 0
4774 05:52:37.732565 DQM Delay:
4775 05:52:37.736182 DQM0 = 35, DQM1 = 30
4776 05:52:37.736267 DQ Delay:
4777 05:52:37.739109 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4778 05:52:37.742635 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4779 05:52:37.745653 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4780 05:52:37.749457 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =41
4781 05:52:37.749564
4782 05:52:37.749658
4783 05:52:37.749746 ==
4784 05:52:37.752465 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 05:52:37.755574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 05:52:37.755671 ==
4787 05:52:37.755751
4788 05:52:37.759164
4789 05:52:37.759244 TX Vref Scan disable
4790 05:52:37.762275 == TX Byte 0 ==
4791 05:52:37.765662 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4792 05:52:37.769174 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4793 05:52:37.771971 == TX Byte 1 ==
4794 05:52:37.775858 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4795 05:52:37.779125 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4796 05:52:37.782344 ==
4797 05:52:37.782451 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 05:52:37.788985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 05:52:37.789099 ==
4800 05:52:37.789190
4801 05:52:37.789275
4802 05:52:37.791906 TX Vref Scan disable
4803 05:52:37.792035 == TX Byte 0 ==
4804 05:52:37.798479 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4805 05:52:37.802201 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4806 05:52:37.802282 == TX Byte 1 ==
4807 05:52:37.808538 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4808 05:52:37.811801 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4809 05:52:37.811883
4810 05:52:37.811948 [DATLAT]
4811 05:52:37.815357 Freq=600, CH1 RK1
4812 05:52:37.815467
4813 05:52:37.815531 DATLAT Default: 0x9
4814 05:52:37.818744 0, 0xFFFF, sum = 0
4815 05:52:37.818872 1, 0xFFFF, sum = 0
4816 05:52:37.821777 2, 0xFFFF, sum = 0
4817 05:52:37.821859 3, 0xFFFF, sum = 0
4818 05:52:37.825310 4, 0xFFFF, sum = 0
4819 05:52:37.828383 5, 0xFFFF, sum = 0
4820 05:52:37.828466 6, 0xFFFF, sum = 0
4821 05:52:37.831906 7, 0xFFFF, sum = 0
4822 05:52:37.831989 8, 0x0, sum = 1
4823 05:52:37.832056 9, 0x0, sum = 2
4824 05:52:37.834894 10, 0x0, sum = 3
4825 05:52:37.834977 11, 0x0, sum = 4
4826 05:52:37.838276 best_step = 9
4827 05:52:37.838358
4828 05:52:37.838423 ==
4829 05:52:37.841743 Dram Type= 6, Freq= 0, CH_1, rank 1
4830 05:52:37.845050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4831 05:52:37.845132 ==
4832 05:52:37.848255 RX Vref Scan: 0
4833 05:52:37.848336
4834 05:52:37.848401 RX Vref 0 -> 0, step: 1
4835 05:52:37.848462
4836 05:52:37.851785 RX Delay -195 -> 252, step: 8
4837 05:52:37.858940 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4838 05:52:37.862009 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4839 05:52:37.865642 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4840 05:52:37.868740 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4841 05:52:37.875463 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4842 05:52:37.878843 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4843 05:52:37.882436 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4844 05:52:37.885582 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4845 05:52:37.888829 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4846 05:52:37.895345 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4847 05:52:37.898891 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4848 05:52:37.902361 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4849 05:52:37.905384 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4850 05:52:37.912047 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4851 05:52:37.915570 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4852 05:52:37.919221 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4853 05:52:37.919302 ==
4854 05:52:37.922247 Dram Type= 6, Freq= 0, CH_1, rank 1
4855 05:52:37.928696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4856 05:52:37.928778 ==
4857 05:52:37.928844 DQS Delay:
4858 05:52:37.928903 DQS0 = 0, DQS1 = 0
4859 05:52:37.931664 DQM Delay:
4860 05:52:37.931764 DQM0 = 36, DQM1 = 29
4861 05:52:37.935162 DQ Delay:
4862 05:52:37.938725 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4863 05:52:37.941795 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =32
4864 05:52:37.945321 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =24
4865 05:52:37.948686 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4866 05:52:37.948767
4867 05:52:37.948830
4868 05:52:37.955036 [DQSOSCAuto] RK1, (LSB)MR18= 0x3453, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
4869 05:52:37.958337 CH1 RK1: MR19=808, MR18=3453
4870 05:52:37.965302 CH1_RK1: MR19=0x808, MR18=0x3453, DQSOSC=394, MR23=63, INC=168, DEC=112
4871 05:52:37.968429 [RxdqsGatingPostProcess] freq 600
4872 05:52:37.971602 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4873 05:52:37.975222 Pre-setting of DQS Precalculation
4874 05:52:37.981487 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4875 05:52:37.988167 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4876 05:52:37.994885 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4877 05:52:37.994966
4878 05:52:37.995030
4879 05:52:37.998468 [Calibration Summary] 1200 Mbps
4880 05:52:37.998547 CH 0, Rank 0
4881 05:52:38.001286 SW Impedance : PASS
4882 05:52:38.004603 DUTY Scan : NO K
4883 05:52:38.004682 ZQ Calibration : PASS
4884 05:52:38.008093 Jitter Meter : NO K
4885 05:52:38.011335 CBT Training : PASS
4886 05:52:38.011414 Write leveling : PASS
4887 05:52:38.014526 RX DQS gating : PASS
4888 05:52:38.018177 RX DQ/DQS(RDDQC) : PASS
4889 05:52:38.018258 TX DQ/DQS : PASS
4890 05:52:38.021208 RX DATLAT : PASS
4891 05:52:38.024688 RX DQ/DQS(Engine): PASS
4892 05:52:38.024768 TX OE : NO K
4893 05:52:38.024833 All Pass.
4894 05:52:38.024893
4895 05:52:38.027727 CH 0, Rank 1
4896 05:52:38.031107 SW Impedance : PASS
4897 05:52:38.031188 DUTY Scan : NO K
4898 05:52:38.034408 ZQ Calibration : PASS
4899 05:52:38.034488 Jitter Meter : NO K
4900 05:52:38.038052 CBT Training : PASS
4901 05:52:38.040999 Write leveling : PASS
4902 05:52:38.041079 RX DQS gating : PASS
4903 05:52:38.044496 RX DQ/DQS(RDDQC) : PASS
4904 05:52:38.047572 TX DQ/DQS : PASS
4905 05:52:38.047652 RX DATLAT : PASS
4906 05:52:38.051072 RX DQ/DQS(Engine): PASS
4907 05:52:38.054629 TX OE : NO K
4908 05:52:38.054710 All Pass.
4909 05:52:38.054774
4910 05:52:38.054833 CH 1, Rank 0
4911 05:52:38.057781 SW Impedance : PASS
4912 05:52:38.061315 DUTY Scan : NO K
4913 05:52:38.061424 ZQ Calibration : PASS
4914 05:52:38.064166 Jitter Meter : NO K
4915 05:52:38.067648 CBT Training : PASS
4916 05:52:38.067728 Write leveling : PASS
4917 05:52:38.071036 RX DQS gating : PASS
4918 05:52:38.074648 RX DQ/DQS(RDDQC) : PASS
4919 05:52:38.074724 TX DQ/DQS : PASS
4920 05:52:38.077645 RX DATLAT : PASS
4921 05:52:38.077720 RX DQ/DQS(Engine): PASS
4922 05:52:38.081276 TX OE : NO K
4923 05:52:38.081350 All Pass.
4924 05:52:38.081413
4925 05:52:38.084207 CH 1, Rank 1
4926 05:52:38.084280 SW Impedance : PASS
4927 05:52:38.087711 DUTY Scan : NO K
4928 05:52:38.091331 ZQ Calibration : PASS
4929 05:52:38.091412 Jitter Meter : NO K
4930 05:52:38.094311 CBT Training : PASS
4931 05:52:38.097359 Write leveling : PASS
4932 05:52:38.097431 RX DQS gating : PASS
4933 05:52:38.100962 RX DQ/DQS(RDDQC) : PASS
4934 05:52:38.104030 TX DQ/DQS : PASS
4935 05:52:38.104106 RX DATLAT : PASS
4936 05:52:38.107476 RX DQ/DQS(Engine): PASS
4937 05:52:38.110539 TX OE : NO K
4938 05:52:38.110614 All Pass.
4939 05:52:38.110676
4940 05:52:38.114209 DramC Write-DBI off
4941 05:52:38.114285 PER_BANK_REFRESH: Hybrid Mode
4942 05:52:38.117613 TX_TRACKING: ON
4943 05:52:38.124112 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4944 05:52:38.130664 [FAST_K] Save calibration result to emmc
4945 05:52:38.133730 dramc_set_vcore_voltage set vcore to 662500
4946 05:52:38.133854 Read voltage for 933, 3
4947 05:52:38.137340 Vio18 = 0
4948 05:52:38.137419 Vcore = 662500
4949 05:52:38.137508 Vdram = 0
4950 05:52:38.140251 Vddq = 0
4951 05:52:38.140324 Vmddr = 0
4952 05:52:38.143698 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4953 05:52:38.150285 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4954 05:52:38.153507 MEM_TYPE=3, freq_sel=17
4955 05:52:38.157180 sv_algorithm_assistance_LP4_1600
4956 05:52:38.160446 ============ PULL DRAM RESETB DOWN ============
4957 05:52:38.163889 ========== PULL DRAM RESETB DOWN end =========
4958 05:52:38.170344 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4959 05:52:38.173344 ===================================
4960 05:52:38.173452 LPDDR4 DRAM CONFIGURATION
4961 05:52:38.176850 ===================================
4962 05:52:38.180141 EX_ROW_EN[0] = 0x0
4963 05:52:38.180241 EX_ROW_EN[1] = 0x0
4964 05:52:38.183683 LP4Y_EN = 0x0
4965 05:52:38.186924 WORK_FSP = 0x0
4966 05:52:38.186998 WL = 0x3
4967 05:52:38.189867 RL = 0x3
4968 05:52:38.189946 BL = 0x2
4969 05:52:38.193361 RPST = 0x0
4970 05:52:38.193460 RD_PRE = 0x0
4971 05:52:38.196363 WR_PRE = 0x1
4972 05:52:38.196461 WR_PST = 0x0
4973 05:52:38.199966 DBI_WR = 0x0
4974 05:52:38.200043 DBI_RD = 0x0
4975 05:52:38.202964 OTF = 0x1
4976 05:52:38.206730 ===================================
4977 05:52:38.209614 ===================================
4978 05:52:38.209720 ANA top config
4979 05:52:38.213290 ===================================
4980 05:52:38.216346 DLL_ASYNC_EN = 0
4981 05:52:38.219582 ALL_SLAVE_EN = 1
4982 05:52:38.219689 NEW_RANK_MODE = 1
4983 05:52:38.222823 DLL_IDLE_MODE = 1
4984 05:52:38.226607 LP45_APHY_COMB_EN = 1
4985 05:52:38.229657 TX_ODT_DIS = 1
4986 05:52:38.232625 NEW_8X_MODE = 1
4987 05:52:38.236196 ===================================
4988 05:52:38.239665 ===================================
4989 05:52:38.239775 data_rate = 1866
4990 05:52:38.243090 CKR = 1
4991 05:52:38.246484 DQ_P2S_RATIO = 8
4992 05:52:38.249611 ===================================
4993 05:52:38.252765 CA_P2S_RATIO = 8
4994 05:52:38.256336 DQ_CA_OPEN = 0
4995 05:52:38.259845 DQ_SEMI_OPEN = 0
4996 05:52:38.259951 CA_SEMI_OPEN = 0
4997 05:52:38.262972 CA_FULL_RATE = 0
4998 05:52:38.266415 DQ_CKDIV4_EN = 1
4999 05:52:38.269453 CA_CKDIV4_EN = 1
5000 05:52:38.272796 CA_PREDIV_EN = 0
5001 05:52:38.276211 PH8_DLY = 0
5002 05:52:38.276315 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5003 05:52:38.279386 DQ_AAMCK_DIV = 4
5004 05:52:38.282475 CA_AAMCK_DIV = 4
5005 05:52:38.286200 CA_ADMCK_DIV = 4
5006 05:52:38.289211 DQ_TRACK_CA_EN = 0
5007 05:52:38.292724 CA_PICK = 933
5008 05:52:38.295821 CA_MCKIO = 933
5009 05:52:38.295924 MCKIO_SEMI = 0
5010 05:52:38.299482 PLL_FREQ = 3732
5011 05:52:38.302807 DQ_UI_PI_RATIO = 32
5012 05:52:38.305914 CA_UI_PI_RATIO = 0
5013 05:52:38.309016 ===================================
5014 05:52:38.312122 ===================================
5015 05:52:38.315978 memory_type:LPDDR4
5016 05:52:38.316078 GP_NUM : 10
5017 05:52:38.319155 SRAM_EN : 1
5018 05:52:38.322249 MD32_EN : 0
5019 05:52:38.325354 ===================================
5020 05:52:38.325472 [ANA_INIT] >>>>>>>>>>>>>>
5021 05:52:38.329049 <<<<<< [CONFIGURE PHASE]: ANA_TX
5022 05:52:38.332082 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5023 05:52:38.335341 ===================================
5024 05:52:38.338823 data_rate = 1866,PCW = 0X8f00
5025 05:52:38.342109 ===================================
5026 05:52:38.345242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5027 05:52:38.352359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5028 05:52:38.355262 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5029 05:52:38.361973 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5030 05:52:38.365676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5031 05:52:38.368657 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5032 05:52:38.368744 [ANA_INIT] flow start
5033 05:52:38.372314 [ANA_INIT] PLL >>>>>>>>
5034 05:52:38.375367 [ANA_INIT] PLL <<<<<<<<
5035 05:52:38.375479 [ANA_INIT] MIDPI >>>>>>>>
5036 05:52:38.378777 [ANA_INIT] MIDPI <<<<<<<<
5037 05:52:38.382161 [ANA_INIT] DLL >>>>>>>>
5038 05:52:38.382272 [ANA_INIT] flow end
5039 05:52:38.388708 ============ LP4 DIFF to SE enter ============
5040 05:52:38.392081 ============ LP4 DIFF to SE exit ============
5041 05:52:38.395443 [ANA_INIT] <<<<<<<<<<<<<
5042 05:52:38.398643 [Flow] Enable top DCM control >>>>>
5043 05:52:38.402113 [Flow] Enable top DCM control <<<<<
5044 05:52:38.405226 Enable DLL master slave shuffle
5045 05:52:38.408420 ==============================================================
5046 05:52:38.411889 Gating Mode config
5047 05:52:38.414940 ==============================================================
5048 05:52:38.418397 Config description:
5049 05:52:38.428064 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5050 05:52:38.435124 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5051 05:52:38.438093 SELPH_MODE 0: By rank 1: By Phase
5052 05:52:38.444931 ==============================================================
5053 05:52:38.448542 GAT_TRACK_EN = 1
5054 05:52:38.451532 RX_GATING_MODE = 2
5055 05:52:38.455219 RX_GATING_TRACK_MODE = 2
5056 05:52:38.458169 SELPH_MODE = 1
5057 05:52:38.461733 PICG_EARLY_EN = 1
5058 05:52:38.461816 VALID_LAT_VALUE = 1
5059 05:52:38.468532 ==============================================================
5060 05:52:38.471179 Enter into Gating configuration >>>>
5061 05:52:38.474537 Exit from Gating configuration <<<<
5062 05:52:38.477813 Enter into DVFS_PRE_config >>>>>
5063 05:52:38.487904 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5064 05:52:38.490987 Exit from DVFS_PRE_config <<<<<
5065 05:52:38.494437 Enter into PICG configuration >>>>
5066 05:52:38.497740 Exit from PICG configuration <<<<
5067 05:52:38.500934 [RX_INPUT] configuration >>>>>
5068 05:52:38.504353 [RX_INPUT] configuration <<<<<
5069 05:52:38.510853 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5070 05:52:38.514548 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5071 05:52:38.520908 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5072 05:52:38.527727 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5073 05:52:38.534155 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5074 05:52:38.541000 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5075 05:52:38.544620 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5076 05:52:38.547675 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5077 05:52:38.550950 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5078 05:52:38.557273 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5079 05:52:38.561090 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5080 05:52:38.564346 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5081 05:52:38.567360 ===================================
5082 05:52:38.570472 LPDDR4 DRAM CONFIGURATION
5083 05:52:38.574148 ===================================
5084 05:52:38.574255 EX_ROW_EN[0] = 0x0
5085 05:52:38.577169 EX_ROW_EN[1] = 0x0
5086 05:52:38.580840 LP4Y_EN = 0x0
5087 05:52:38.580923 WORK_FSP = 0x0
5088 05:52:38.583512 WL = 0x3
5089 05:52:38.583590 RL = 0x3
5090 05:52:38.586825 BL = 0x2
5091 05:52:38.586931 RPST = 0x0
5092 05:52:38.590168 RD_PRE = 0x0
5093 05:52:38.590254 WR_PRE = 0x1
5094 05:52:38.593383 WR_PST = 0x0
5095 05:52:38.593491 DBI_WR = 0x0
5096 05:52:38.597063 DBI_RD = 0x0
5097 05:52:38.597168 OTF = 0x1
5098 05:52:38.600079 ===================================
5099 05:52:38.603602 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5100 05:52:38.610189 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5101 05:52:38.613395 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5102 05:52:38.616734 ===================================
5103 05:52:38.619773 LPDDR4 DRAM CONFIGURATION
5104 05:52:38.623567 ===================================
5105 05:52:38.623687 EX_ROW_EN[0] = 0x10
5106 05:52:38.626616 EX_ROW_EN[1] = 0x0
5107 05:52:38.630102 LP4Y_EN = 0x0
5108 05:52:38.630179 WORK_FSP = 0x0
5109 05:52:38.633324 WL = 0x3
5110 05:52:38.633396 RL = 0x3
5111 05:52:38.636884 BL = 0x2
5112 05:52:38.636959 RPST = 0x0
5113 05:52:38.639903 RD_PRE = 0x0
5114 05:52:38.639975 WR_PRE = 0x1
5115 05:52:38.643408 WR_PST = 0x0
5116 05:52:38.643518 DBI_WR = 0x0
5117 05:52:38.646472 DBI_RD = 0x0
5118 05:52:38.646572 OTF = 0x1
5119 05:52:38.649705 ===================================
5120 05:52:38.656408 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5121 05:52:38.661289 nWR fixed to 30
5122 05:52:38.664379 [ModeRegInit_LP4] CH0 RK0
5123 05:52:38.664499 [ModeRegInit_LP4] CH0 RK1
5124 05:52:38.667933 [ModeRegInit_LP4] CH1 RK0
5125 05:52:38.670913 [ModeRegInit_LP4] CH1 RK1
5126 05:52:38.671017 match AC timing 9
5127 05:52:38.677580 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5128 05:52:38.680671 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5129 05:52:38.684263 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5130 05:52:38.690834 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5131 05:52:38.694374 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5132 05:52:38.694476 ==
5133 05:52:38.697238 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 05:52:38.700762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 05:52:38.700839 ==
5136 05:52:38.707044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5137 05:52:38.714258 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5138 05:52:38.717063 [CA 0] Center 38 (8~69) winsize 62
5139 05:52:38.720490 [CA 1] Center 38 (7~69) winsize 63
5140 05:52:38.723780 [CA 2] Center 35 (5~66) winsize 62
5141 05:52:38.727007 [CA 3] Center 35 (5~66) winsize 62
5142 05:52:38.730651 [CA 4] Center 34 (4~65) winsize 62
5143 05:52:38.733909 [CA 5] Center 33 (3~64) winsize 62
5144 05:52:38.733987
5145 05:52:38.737268 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5146 05:52:38.737367
5147 05:52:38.740208 [CATrainingPosCal] consider 1 rank data
5148 05:52:38.743884 u2DelayCellTimex100 = 270/100 ps
5149 05:52:38.746861 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5150 05:52:38.750580 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5151 05:52:38.753581 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5152 05:52:38.756684 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5153 05:52:38.763640 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5154 05:52:38.766709 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5155 05:52:38.766820
5156 05:52:38.770448 CA PerBit enable=1, Macro0, CA PI delay=33
5157 05:52:38.770561
5158 05:52:38.773567 [CBTSetCACLKResult] CA Dly = 33
5159 05:52:38.773668 CS Dly: 6 (0~37)
5160 05:52:38.773760 ==
5161 05:52:38.776827 Dram Type= 6, Freq= 0, CH_0, rank 1
5162 05:52:38.783427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 05:52:38.783530 ==
5164 05:52:38.786553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5165 05:52:38.793301 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5166 05:52:38.796322 [CA 0] Center 38 (8~69) winsize 62
5167 05:52:38.800022 [CA 1] Center 38 (8~69) winsize 62
5168 05:52:38.803044 [CA 2] Center 35 (5~66) winsize 62
5169 05:52:38.806329 [CA 3] Center 35 (5~66) winsize 62
5170 05:52:38.810008 [CA 4] Center 34 (3~65) winsize 63
5171 05:52:38.813128 [CA 5] Center 33 (3~64) winsize 62
5172 05:52:38.813226
5173 05:52:38.816500 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5174 05:52:38.816602
5175 05:52:38.819984 [CATrainingPosCal] consider 2 rank data
5176 05:52:38.823369 u2DelayCellTimex100 = 270/100 ps
5177 05:52:38.826367 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5178 05:52:38.829615 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5179 05:52:38.836164 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5180 05:52:38.839170 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5181 05:52:38.842605 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5182 05:52:38.845976 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5183 05:52:38.846081
5184 05:52:38.849351 CA PerBit enable=1, Macro0, CA PI delay=33
5185 05:52:38.849465
5186 05:52:38.852930 [CBTSetCACLKResult] CA Dly = 33
5187 05:52:38.853040 CS Dly: 7 (0~39)
5188 05:52:38.856098
5189 05:52:38.859137 ----->DramcWriteLeveling(PI) begin...
5190 05:52:38.859250 ==
5191 05:52:38.862821 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 05:52:38.865874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 05:52:38.865951 ==
5194 05:52:38.868889 Write leveling (Byte 0): 34 => 34
5195 05:52:38.872693 Write leveling (Byte 1): 32 => 32
5196 05:52:38.875843 DramcWriteLeveling(PI) end<-----
5197 05:52:38.875944
5198 05:52:38.876036 ==
5199 05:52:38.878918 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 05:52:38.882524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 05:52:38.882604 ==
5202 05:52:38.886109 [Gating] SW mode calibration
5203 05:52:38.892687 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5204 05:52:38.899127 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5205 05:52:38.902669 0 14 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
5206 05:52:38.905552 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5207 05:52:38.912374 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5208 05:52:38.916061 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5209 05:52:38.918990 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5210 05:52:38.925210 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5211 05:52:38.928718 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5212 05:52:38.932304 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5213 05:52:38.938478 0 15 0 | B1->B0 | 3333 2d2d | 0 0 | (0 0) (1 1)
5214 05:52:38.941898 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5215 05:52:38.945269 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5216 05:52:38.951972 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 05:52:38.955483 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5218 05:52:38.958718 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5219 05:52:38.965242 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5220 05:52:38.968362 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5221 05:52:38.971737 1 0 0 | B1->B0 | 2525 3838 | 0 1 | (0 0) (0 0)
5222 05:52:38.978291 1 0 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5223 05:52:38.982027 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 05:52:38.985045 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 05:52:38.991557 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 05:52:38.995162 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 05:52:38.998127 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 05:52:39.001451 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5229 05:52:39.008125 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5230 05:52:39.011712 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5231 05:52:39.018311 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 05:52:39.021444 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 05:52:39.025050 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 05:52:39.031357 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 05:52:39.034528 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 05:52:39.037903 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 05:52:39.041340 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 05:52:39.047818 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 05:52:39.051231 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 05:52:39.054627 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 05:52:39.061162 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 05:52:39.064808 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 05:52:39.067790 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 05:52:39.074560 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5245 05:52:39.078134 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5246 05:52:39.081095 Total UI for P1: 0, mck2ui 16
5247 05:52:39.084393 best dqsien dly found for B0: ( 1, 2, 28)
5248 05:52:39.087727 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5249 05:52:39.094949 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5250 05:52:39.095031 Total UI for P1: 0, mck2ui 16
5251 05:52:39.101632 best dqsien dly found for B1: ( 1, 3, 4)
5252 05:52:39.104514 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5253 05:52:39.107946 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5254 05:52:39.108094
5255 05:52:39.111010 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5256 05:52:39.114736 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5257 05:52:39.117855 [Gating] SW calibration Done
5258 05:52:39.117931 ==
5259 05:52:39.121048 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 05:52:39.124210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 05:52:39.124313 ==
5262 05:52:39.127873 RX Vref Scan: 0
5263 05:52:39.127987
5264 05:52:39.128079 RX Vref 0 -> 0, step: 1
5265 05:52:39.128169
5266 05:52:39.131023 RX Delay -80 -> 252, step: 8
5267 05:52:39.134145 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5268 05:52:39.140920 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5269 05:52:39.144465 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5270 05:52:39.147257 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5271 05:52:39.150699 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5272 05:52:39.154236 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5273 05:52:39.157163 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5274 05:52:39.164121 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5275 05:52:39.167091 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5276 05:52:39.170807 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5277 05:52:39.173916 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5278 05:52:39.177060 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5279 05:52:39.183919 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5280 05:52:39.187425 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5281 05:52:39.190434 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5282 05:52:39.193664 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5283 05:52:39.193738 ==
5284 05:52:39.196745 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 05:52:39.204026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 05:52:39.204190 ==
5287 05:52:39.204308 DQS Delay:
5288 05:52:39.206552 DQS0 = 0, DQS1 = 0
5289 05:52:39.206624 DQM Delay:
5290 05:52:39.206706 DQM0 = 94, DQM1 = 82
5291 05:52:39.210263 DQ Delay:
5292 05:52:39.213353 DQ0 =95, DQ1 =95, DQ2 =91, DQ3 =91
5293 05:52:39.216560 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5294 05:52:39.220295 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5295 05:52:39.223577 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =91
5296 05:52:39.223660
5297 05:52:39.223740
5298 05:52:39.223815 ==
5299 05:52:39.226752 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 05:52:39.229931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 05:52:39.230015 ==
5302 05:52:39.230082
5303 05:52:39.230144
5304 05:52:39.233171 TX Vref Scan disable
5305 05:52:39.236162 == TX Byte 0 ==
5306 05:52:39.239937 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5307 05:52:39.243139 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5308 05:52:39.246281 == TX Byte 1 ==
5309 05:52:39.249748 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5310 05:52:39.252721 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5311 05:52:39.252805 ==
5312 05:52:39.256286 Dram Type= 6, Freq= 0, CH_0, rank 0
5313 05:52:39.262896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 05:52:39.263016 ==
5315 05:52:39.263111
5316 05:52:39.263200
5317 05:52:39.263289 TX Vref Scan disable
5318 05:52:39.266506 == TX Byte 0 ==
5319 05:52:39.270023 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5320 05:52:39.276611 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5321 05:52:39.276730 == TX Byte 1 ==
5322 05:52:39.279788 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5323 05:52:39.286288 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5324 05:52:39.286373
5325 05:52:39.286439 [DATLAT]
5326 05:52:39.286502 Freq=933, CH0 RK0
5327 05:52:39.286562
5328 05:52:39.290135 DATLAT Default: 0xd
5329 05:52:39.290224 0, 0xFFFF, sum = 0
5330 05:52:39.293243 1, 0xFFFF, sum = 0
5331 05:52:39.293356 2, 0xFFFF, sum = 0
5332 05:52:39.296434 3, 0xFFFF, sum = 0
5333 05:52:39.300096 4, 0xFFFF, sum = 0
5334 05:52:39.300190 5, 0xFFFF, sum = 0
5335 05:52:39.303095 6, 0xFFFF, sum = 0
5336 05:52:39.303216 7, 0xFFFF, sum = 0
5337 05:52:39.306470 8, 0xFFFF, sum = 0
5338 05:52:39.306582 9, 0xFFFF, sum = 0
5339 05:52:39.309635 10, 0x0, sum = 1
5340 05:52:39.309749 11, 0x0, sum = 2
5341 05:52:39.312928 12, 0x0, sum = 3
5342 05:52:39.313043 13, 0x0, sum = 4
5343 05:52:39.313138 best_step = 11
5344 05:52:39.313227
5345 05:52:39.316314 ==
5346 05:52:39.319931 Dram Type= 6, Freq= 0, CH_0, rank 0
5347 05:52:39.323029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 05:52:39.323114 ==
5349 05:52:39.323181 RX Vref Scan: 1
5350 05:52:39.323243
5351 05:52:39.326150 RX Vref 0 -> 0, step: 1
5352 05:52:39.326261
5353 05:52:39.329378 RX Delay -69 -> 252, step: 4
5354 05:52:39.329501
5355 05:52:39.332496 Set Vref, RX VrefLevel [Byte0]: 64
5356 05:52:39.336122 [Byte1]: 52
5357 05:52:39.339412
5358 05:52:39.339495 Final RX Vref Byte 0 = 64 to rank0
5359 05:52:39.342566 Final RX Vref Byte 1 = 52 to rank0
5360 05:52:39.345800 Final RX Vref Byte 0 = 64 to rank1
5361 05:52:39.349018 Final RX Vref Byte 1 = 52 to rank1==
5362 05:52:39.352644 Dram Type= 6, Freq= 0, CH_0, rank 0
5363 05:52:39.359242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 05:52:39.359329 ==
5365 05:52:39.359396 DQS Delay:
5366 05:52:39.359457 DQS0 = 0, DQS1 = 0
5367 05:52:39.362423 DQM Delay:
5368 05:52:39.362505 DQM0 = 96, DQM1 = 84
5369 05:52:39.365849 DQ Delay:
5370 05:52:39.369408 DQ0 =92, DQ1 =98, DQ2 =92, DQ3 =92
5371 05:52:39.372365 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =110
5372 05:52:39.376093 DQ8 =78, DQ9 =70, DQ10 =84, DQ11 =78
5373 05:52:39.378968 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =90
5374 05:52:39.379052
5375 05:52:39.379117
5376 05:52:39.385695 [DQSOSCAuto] RK0, (LSB)MR18= 0x1514, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5377 05:52:39.388835 CH0 RK0: MR19=505, MR18=1514
5378 05:52:39.395668 CH0_RK0: MR19=0x505, MR18=0x1514, DQSOSC=415, MR23=63, INC=62, DEC=41
5379 05:52:39.395782
5380 05:52:39.398884 ----->DramcWriteLeveling(PI) begin...
5381 05:52:39.398995 ==
5382 05:52:39.401973 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 05:52:39.405153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 05:52:39.405237 ==
5385 05:52:39.408817 Write leveling (Byte 0): 29 => 29
5386 05:52:39.411787 Write leveling (Byte 1): 28 => 28
5387 05:52:39.415358 DramcWriteLeveling(PI) end<-----
5388 05:52:39.415449
5389 05:52:39.415516 ==
5390 05:52:39.418797 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 05:52:39.422361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 05:52:39.422451 ==
5393 05:52:39.425470 [Gating] SW mode calibration
5394 05:52:39.431867 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5395 05:52:39.438409 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5396 05:52:39.442226 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
5397 05:52:39.448885 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 05:52:39.451915 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 05:52:39.454999 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 05:52:39.462039 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5401 05:52:39.464867 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5402 05:52:39.468195 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5403 05:52:39.474966 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
5404 05:52:39.478432 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5405 05:52:39.481964 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5406 05:52:39.488716 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 05:52:39.491527 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 05:52:39.495213 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5409 05:52:39.501468 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5410 05:52:39.504934 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5411 05:52:39.508148 0 15 28 | B1->B0 | 2424 3636 | 0 1 | (0 0) (0 0)
5412 05:52:39.514961 1 0 0 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
5413 05:52:39.517953 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 05:52:39.521383 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 05:52:39.524478 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 05:52:39.531344 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 05:52:39.534723 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 05:52:39.537974 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5419 05:52:39.544729 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5420 05:52:39.547829 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5421 05:52:39.551020 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 05:52:39.557821 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 05:52:39.560891 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 05:52:39.563982 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 05:52:39.570951 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 05:52:39.573879 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 05:52:39.577613 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 05:52:39.583898 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 05:52:39.587342 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 05:52:39.590494 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 05:52:39.597366 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 05:52:39.600417 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 05:52:39.604011 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 05:52:39.610381 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 05:52:39.613953 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5436 05:52:39.617019 Total UI for P1: 0, mck2ui 16
5437 05:52:39.620764 best dqsien dly found for B0: ( 1, 2, 26)
5438 05:52:39.623682 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 05:52:39.627090 Total UI for P1: 0, mck2ui 16
5440 05:52:39.630576 best dqsien dly found for B1: ( 1, 2, 28)
5441 05:52:39.633739 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5442 05:52:39.637454 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5443 05:52:39.637570
5444 05:52:39.643975 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5445 05:52:39.647350 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5446 05:52:39.650268 [Gating] SW calibration Done
5447 05:52:39.650351 ==
5448 05:52:39.654069 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 05:52:39.657099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 05:52:39.657202 ==
5451 05:52:39.657267 RX Vref Scan: 0
5452 05:52:39.657328
5453 05:52:39.660726 RX Vref 0 -> 0, step: 1
5454 05:52:39.660830
5455 05:52:39.663941 RX Delay -80 -> 252, step: 8
5456 05:52:39.666986 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5457 05:52:39.670023 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5458 05:52:39.676733 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5459 05:52:39.680593 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5460 05:52:39.683674 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5461 05:52:39.686812 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5462 05:52:39.690124 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5463 05:52:39.693367 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5464 05:52:39.700085 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5465 05:52:39.703679 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5466 05:52:39.706654 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5467 05:52:39.710427 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5468 05:52:39.713492 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5469 05:52:39.719871 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5470 05:52:39.723234 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5471 05:52:39.726955 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5472 05:52:39.727063 ==
5473 05:52:39.730421 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 05:52:39.733331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 05:52:39.733438 ==
5476 05:52:39.736561 DQS Delay:
5477 05:52:39.736641 DQS0 = 0, DQS1 = 0
5478 05:52:39.739896 DQM Delay:
5479 05:52:39.739989 DQM0 = 93, DQM1 = 83
5480 05:52:39.740059 DQ Delay:
5481 05:52:39.743413 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =91
5482 05:52:39.746444 DQ4 =91, DQ5 =79, DQ6 =107, DQ7 =107
5483 05:52:39.750015 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5484 05:52:39.752874 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =87
5485 05:52:39.752947
5486 05:52:39.753007
5487 05:52:39.756281 ==
5488 05:52:39.759791 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 05:52:39.763265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 05:52:39.763349 ==
5491 05:52:39.763445
5492 05:52:39.763508
5493 05:52:39.766356 TX Vref Scan disable
5494 05:52:39.766427 == TX Byte 0 ==
5495 05:52:39.772723 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5496 05:52:39.776572 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5497 05:52:39.776645 == TX Byte 1 ==
5498 05:52:39.782791 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5499 05:52:39.785800 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5500 05:52:39.785902 ==
5501 05:52:39.789443 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 05:52:39.792634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 05:52:39.792741 ==
5504 05:52:39.792833
5505 05:52:39.792919
5506 05:52:39.795623 TX Vref Scan disable
5507 05:52:39.799524 == TX Byte 0 ==
5508 05:52:39.802561 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5509 05:52:39.805765 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5510 05:52:39.809345 == TX Byte 1 ==
5511 05:52:39.812374 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5512 05:52:39.815921 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5513 05:52:39.815997
5514 05:52:39.819074 [DATLAT]
5515 05:52:39.819148 Freq=933, CH0 RK1
5516 05:52:39.819210
5517 05:52:39.822707 DATLAT Default: 0xb
5518 05:52:39.822788 0, 0xFFFF, sum = 0
5519 05:52:39.825582 1, 0xFFFF, sum = 0
5520 05:52:39.825666 2, 0xFFFF, sum = 0
5521 05:52:39.828986 3, 0xFFFF, sum = 0
5522 05:52:39.829070 4, 0xFFFF, sum = 0
5523 05:52:39.832522 5, 0xFFFF, sum = 0
5524 05:52:39.832632 6, 0xFFFF, sum = 0
5525 05:52:39.835428 7, 0xFFFF, sum = 0
5526 05:52:39.835510 8, 0xFFFF, sum = 0
5527 05:52:39.839072 9, 0xFFFF, sum = 0
5528 05:52:39.839154 10, 0x0, sum = 1
5529 05:52:39.842079 11, 0x0, sum = 2
5530 05:52:39.842162 12, 0x0, sum = 3
5531 05:52:39.845623 13, 0x0, sum = 4
5532 05:52:39.845701 best_step = 11
5533 05:52:39.845770
5534 05:52:39.845830 ==
5535 05:52:39.849027 Dram Type= 6, Freq= 0, CH_0, rank 1
5536 05:52:39.855368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 05:52:39.855467 ==
5538 05:52:39.855563 RX Vref Scan: 0
5539 05:52:39.855626
5540 05:52:39.858929 RX Vref 0 -> 0, step: 1
5541 05:52:39.859014
5542 05:52:39.861884 RX Delay -77 -> 252, step: 4
5543 05:52:39.865256 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5544 05:52:39.868607 iDelay=199, Bit 1, Center 96 (7 ~ 186) 180
5545 05:52:39.875307 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5546 05:52:39.878881 iDelay=199, Bit 3, Center 86 (-9 ~ 182) 192
5547 05:52:39.881893 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5548 05:52:39.885356 iDelay=199, Bit 5, Center 78 (-13 ~ 170) 184
5549 05:52:39.888842 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5550 05:52:39.894935 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5551 05:52:39.898624 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5552 05:52:39.901805 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5553 05:52:39.904916 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5554 05:52:39.908463 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5555 05:52:39.915010 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5556 05:52:39.918265 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5557 05:52:39.921974 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5558 05:52:39.925054 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5559 05:52:39.925135 ==
5560 05:52:39.928043 Dram Type= 6, Freq= 0, CH_0, rank 1
5561 05:52:39.931755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 05:52:39.934600 ==
5563 05:52:39.934681 DQS Delay:
5564 05:52:39.934746 DQS0 = 0, DQS1 = 0
5565 05:52:39.938016 DQM Delay:
5566 05:52:39.938096 DQM0 = 91, DQM1 = 83
5567 05:52:39.941588 DQ Delay:
5568 05:52:39.944534 DQ0 =88, DQ1 =96, DQ2 =86, DQ3 =86
5569 05:52:39.948009 DQ4 =90, DQ5 =78, DQ6 =106, DQ7 =104
5570 05:52:39.951184 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5571 05:52:39.954565 DQ12 =88, DQ13 =88, DQ14 =94, DQ15 =90
5572 05:52:39.954646
5573 05:52:39.954710
5574 05:52:39.960939 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5575 05:52:39.964458 CH0 RK1: MR19=505, MR18=2D0F
5576 05:52:39.970850 CH0_RK1: MR19=0x505, MR18=0x2D0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5577 05:52:39.974250 [RxdqsGatingPostProcess] freq 933
5578 05:52:39.977668 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5579 05:52:39.981160 best DQS0 dly(2T, 0.5T) = (0, 10)
5580 05:52:39.984558 best DQS1 dly(2T, 0.5T) = (0, 11)
5581 05:52:39.987566 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5582 05:52:39.990892 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5583 05:52:39.994282 best DQS0 dly(2T, 0.5T) = (0, 10)
5584 05:52:39.997865 best DQS1 dly(2T, 0.5T) = (0, 10)
5585 05:52:40.000802 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5586 05:52:40.004360 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5587 05:52:40.007362 Pre-setting of DQS Precalculation
5588 05:52:40.010952 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5589 05:52:40.011033 ==
5590 05:52:40.014028 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 05:52:40.020694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 05:52:40.020815 ==
5593 05:52:40.024044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5594 05:52:40.030579 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5595 05:52:40.033808 [CA 0] Center 37 (8~67) winsize 60
5596 05:52:40.037423 [CA 1] Center 37 (7~68) winsize 62
5597 05:52:40.040974 [CA 2] Center 35 (5~65) winsize 61
5598 05:52:40.044032 [CA 3] Center 35 (5~65) winsize 61
5599 05:52:40.047553 [CA 4] Center 35 (5~65) winsize 61
5600 05:52:40.050442 [CA 5] Center 34 (4~64) winsize 61
5601 05:52:40.050517
5602 05:52:40.054054 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5603 05:52:40.054133
5604 05:52:40.057081 [CATrainingPosCal] consider 1 rank data
5605 05:52:40.060527 u2DelayCellTimex100 = 270/100 ps
5606 05:52:40.064149 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5607 05:52:40.070505 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5608 05:52:40.073678 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5609 05:52:40.076908 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5610 05:52:40.080259 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5611 05:52:40.083731 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5612 05:52:40.083806
5613 05:52:40.086646 CA PerBit enable=1, Macro0, CA PI delay=34
5614 05:52:40.086745
5615 05:52:40.090391 [CBTSetCACLKResult] CA Dly = 34
5616 05:52:40.093735 CS Dly: 6 (0~37)
5617 05:52:40.093809 ==
5618 05:52:40.097209 Dram Type= 6, Freq= 0, CH_1, rank 1
5619 05:52:40.100134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 05:52:40.100215 ==
5621 05:52:40.106720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5622 05:52:40.109680 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5623 05:52:40.114382 [CA 0] Center 37 (8~67) winsize 60
5624 05:52:40.117360 [CA 1] Center 37 (7~68) winsize 62
5625 05:52:40.121001 [CA 2] Center 35 (5~65) winsize 61
5626 05:52:40.123775 [CA 3] Center 34 (4~64) winsize 61
5627 05:52:40.127428 [CA 4] Center 35 (5~65) winsize 61
5628 05:52:40.130994 [CA 5] Center 34 (4~64) winsize 61
5629 05:52:40.131067
5630 05:52:40.134023 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5631 05:52:40.134101
5632 05:52:40.137583 [CATrainingPosCal] consider 2 rank data
5633 05:52:40.140529 u2DelayCellTimex100 = 270/100 ps
5634 05:52:40.144011 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5635 05:52:40.150484 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5636 05:52:40.153944 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5637 05:52:40.156767 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5638 05:52:40.160507 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5639 05:52:40.163441 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5640 05:52:40.163522
5641 05:52:40.167091 CA PerBit enable=1, Macro0, CA PI delay=34
5642 05:52:40.167170
5643 05:52:40.170076 [CBTSetCACLKResult] CA Dly = 34
5644 05:52:40.170149 CS Dly: 7 (0~39)
5645 05:52:40.173672
5646 05:52:40.177203 ----->DramcWriteLeveling(PI) begin...
5647 05:52:40.177284 ==
5648 05:52:40.180208 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 05:52:40.183381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 05:52:40.183456 ==
5651 05:52:40.187270 Write leveling (Byte 0): 28 => 28
5652 05:52:40.190500 Write leveling (Byte 1): 30 => 30
5653 05:52:40.193874 DramcWriteLeveling(PI) end<-----
5654 05:52:40.193949
5655 05:52:40.194010 ==
5656 05:52:40.196649 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 05:52:40.200188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 05:52:40.200292 ==
5659 05:52:40.203696 [Gating] SW mode calibration
5660 05:52:40.210236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5661 05:52:40.216834 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5662 05:52:40.220208 0 14 0 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
5663 05:52:40.223176 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 05:52:40.230318 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 05:52:40.233246 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 05:52:40.236745 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5667 05:52:40.243503 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5668 05:52:40.246485 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5669 05:52:40.250002 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
5670 05:52:40.256465 0 15 0 | B1->B0 | 2828 2a2a | 1 1 | (1 1) (1 1)
5671 05:52:40.259442 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 05:52:40.262947 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 05:52:40.269592 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 05:52:40.273197 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5675 05:52:40.276168 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5676 05:52:40.283070 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5677 05:52:40.286087 0 15 28 | B1->B0 | 3232 3333 | 0 1 | (0 0) (0 0)
5678 05:52:40.289648 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 05:52:40.295878 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 05:52:40.299245 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 05:52:40.302446 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 05:52:40.309320 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 05:52:40.312494 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 05:52:40.315714 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5685 05:52:40.322534 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5686 05:52:40.325991 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 05:52:40.328970 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 05:52:40.335741 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 05:52:40.339280 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 05:52:40.342375 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 05:52:40.345866 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 05:52:40.352562 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 05:52:40.355615 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 05:52:40.359262 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 05:52:40.365825 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 05:52:40.369275 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 05:52:40.372253 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 05:52:40.378751 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 05:52:40.382301 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 05:52:40.385704 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 05:52:40.392276 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5702 05:52:40.395287 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5703 05:52:40.398740 Total UI for P1: 0, mck2ui 16
5704 05:52:40.401693 best dqsien dly found for B0: ( 1, 2, 28)
5705 05:52:40.405311 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5706 05:52:40.408860 Total UI for P1: 0, mck2ui 16
5707 05:52:40.411757 best dqsien dly found for B1: ( 1, 2, 30)
5708 05:52:40.415360 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5709 05:52:40.418952 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5710 05:52:40.422122
5711 05:52:40.425400 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5712 05:52:40.428598 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5713 05:52:40.432268 [Gating] SW calibration Done
5714 05:52:40.432343 ==
5715 05:52:40.435035 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 05:52:40.438716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 05:52:40.438788 ==
5718 05:52:40.438850 RX Vref Scan: 0
5719 05:52:40.438909
5720 05:52:40.441791 RX Vref 0 -> 0, step: 1
5721 05:52:40.441861
5722 05:52:40.444970 RX Delay -80 -> 252, step: 8
5723 05:52:40.448650 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5724 05:52:40.451601 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5725 05:52:40.458216 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5726 05:52:40.461501 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5727 05:52:40.464704 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5728 05:52:40.468338 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5729 05:52:40.471251 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5730 05:52:40.474660 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5731 05:52:40.481422 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5732 05:52:40.484531 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5733 05:52:40.487970 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5734 05:52:40.491551 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5735 05:52:40.495035 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5736 05:52:40.501089 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5737 05:52:40.504453 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5738 05:52:40.507921 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5739 05:52:40.508001 ==
5740 05:52:40.510967 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 05:52:40.514317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 05:52:40.514398 ==
5743 05:52:40.517737 DQS Delay:
5744 05:52:40.517830 DQS0 = 0, DQS1 = 0
5745 05:52:40.521767 DQM Delay:
5746 05:52:40.521841 DQM0 = 95, DQM1 = 85
5747 05:52:40.521909 DQ Delay:
5748 05:52:40.524681 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5749 05:52:40.527755 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5750 05:52:40.531187 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5751 05:52:40.534041 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5752 05:52:40.537909
5753 05:52:40.537986
5754 05:52:40.538049 ==
5755 05:52:40.540756 Dram Type= 6, Freq= 0, CH_1, rank 0
5756 05:52:40.544225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 05:52:40.544299 ==
5758 05:52:40.544361
5759 05:52:40.544418
5760 05:52:40.547324 TX Vref Scan disable
5761 05:52:40.547398 == TX Byte 0 ==
5762 05:52:40.554031 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5763 05:52:40.557458 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5764 05:52:40.557582 == TX Byte 1 ==
5765 05:52:40.563937 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5766 05:52:40.567494 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5767 05:52:40.567573 ==
5768 05:52:40.570981 Dram Type= 6, Freq= 0, CH_1, rank 0
5769 05:52:40.573884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 05:52:40.573982 ==
5771 05:52:40.574072
5772 05:52:40.574165
5773 05:52:40.577768 TX Vref Scan disable
5774 05:52:40.580462 == TX Byte 0 ==
5775 05:52:40.583924 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5776 05:52:40.587460 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5777 05:52:40.590432 == TX Byte 1 ==
5778 05:52:40.593899 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5779 05:52:40.596838 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5780 05:52:40.596936
5781 05:52:40.600345 [DATLAT]
5782 05:52:40.600426 Freq=933, CH1 RK0
5783 05:52:40.600491
5784 05:52:40.603822 DATLAT Default: 0xd
5785 05:52:40.603902 0, 0xFFFF, sum = 0
5786 05:52:40.606748 1, 0xFFFF, sum = 0
5787 05:52:40.606830 2, 0xFFFF, sum = 0
5788 05:52:40.610266 3, 0xFFFF, sum = 0
5789 05:52:40.610349 4, 0xFFFF, sum = 0
5790 05:52:40.613849 5, 0xFFFF, sum = 0
5791 05:52:40.613932 6, 0xFFFF, sum = 0
5792 05:52:40.616859 7, 0xFFFF, sum = 0
5793 05:52:40.620301 8, 0xFFFF, sum = 0
5794 05:52:40.620383 9, 0xFFFF, sum = 0
5795 05:52:40.623174 10, 0x0, sum = 1
5796 05:52:40.623258 11, 0x0, sum = 2
5797 05:52:40.623324 12, 0x0, sum = 3
5798 05:52:40.626561 13, 0x0, sum = 4
5799 05:52:40.626642 best_step = 11
5800 05:52:40.626706
5801 05:52:40.630099 ==
5802 05:52:40.630179 Dram Type= 6, Freq= 0, CH_1, rank 0
5803 05:52:40.636778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 05:52:40.636863 ==
5805 05:52:40.636928 RX Vref Scan: 1
5806 05:52:40.636997
5807 05:52:40.640336 RX Vref 0 -> 0, step: 1
5808 05:52:40.640416
5809 05:52:40.643297 RX Delay -69 -> 252, step: 4
5810 05:52:40.643378
5811 05:52:40.646591 Set Vref, RX VrefLevel [Byte0]: 54
5812 05:52:40.650010 [Byte1]: 55
5813 05:52:40.650091
5814 05:52:40.653615 Final RX Vref Byte 0 = 54 to rank0
5815 05:52:40.656666 Final RX Vref Byte 1 = 55 to rank0
5816 05:52:40.660281 Final RX Vref Byte 0 = 54 to rank1
5817 05:52:40.663118 Final RX Vref Byte 1 = 55 to rank1==
5818 05:52:40.666433 Dram Type= 6, Freq= 0, CH_1, rank 0
5819 05:52:40.669979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 05:52:40.670060 ==
5821 05:52:40.673118 DQS Delay:
5822 05:52:40.673224 DQS0 = 0, DQS1 = 0
5823 05:52:40.676540 DQM Delay:
5824 05:52:40.676612 DQM0 = 95, DQM1 = 88
5825 05:52:40.676672 DQ Delay:
5826 05:52:40.679971 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =94
5827 05:52:40.683287 DQ4 =92, DQ5 =106, DQ6 =108, DQ7 =92
5828 05:52:40.686728 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =82
5829 05:52:40.689851 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =94
5830 05:52:40.689932
5831 05:52:40.693464
5832 05:52:40.700024 [DQSOSCAuto] RK0, (LSB)MR18= 0xfc05, (MSB)MR19= 0x405, tDQSOscB0 = 420 ps tDQSOscB1 = 423 ps
5833 05:52:40.703107 CH1 RK0: MR19=405, MR18=FC05
5834 05:52:40.709681 CH1_RK0: MR19=0x405, MR18=0xFC05, DQSOSC=420, MR23=63, INC=61, DEC=40
5835 05:52:40.709763
5836 05:52:40.713147 ----->DramcWriteLeveling(PI) begin...
5837 05:52:40.713230 ==
5838 05:52:40.716630 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 05:52:40.719596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 05:52:40.719678 ==
5841 05:52:40.723120 Write leveling (Byte 0): 25 => 25
5842 05:52:40.726646 Write leveling (Byte 1): 25 => 25
5843 05:52:40.729407 DramcWriteLeveling(PI) end<-----
5844 05:52:40.729496
5845 05:52:40.729563 ==
5846 05:52:40.732657 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 05:52:40.736099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 05:52:40.736180 ==
5849 05:52:40.739721 [Gating] SW mode calibration
5850 05:52:40.746204 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5851 05:52:40.752567 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5852 05:52:40.755983 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5853 05:52:40.759455 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 05:52:40.766088 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 05:52:40.769648 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 05:52:40.772459 0 14 16 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
5857 05:52:40.779026 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5858 05:52:40.782618 0 14 24 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
5859 05:52:40.786000 0 14 28 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5860 05:52:40.792194 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5861 05:52:40.795761 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5862 05:52:40.798748 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 05:52:40.805329 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5864 05:52:40.808719 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5865 05:52:40.811869 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5866 05:52:40.818925 0 15 24 | B1->B0 | 2424 2d2d | 0 1 | (1 1) (0 0)
5867 05:52:40.821931 0 15 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5868 05:52:40.824895 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 05:52:40.831528 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 05:52:40.834815 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 05:52:40.838333 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5872 05:52:40.845400 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5873 05:52:40.848519 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 05:52:40.851629 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5875 05:52:40.858136 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5876 05:52:40.861140 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 05:52:40.864960 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 05:52:40.871410 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 05:52:40.874857 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 05:52:40.877885 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 05:52:40.884914 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 05:52:40.888037 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 05:52:40.891541 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 05:52:40.897733 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 05:52:40.901350 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 05:52:40.904812 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 05:52:40.911334 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 05:52:40.914903 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 05:52:40.917917 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 05:52:40.924280 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5891 05:52:40.927708 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5892 05:52:40.931341 Total UI for P1: 0, mck2ui 16
5893 05:52:40.934364 best dqsien dly found for B0: ( 1, 2, 24)
5894 05:52:40.937969 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5895 05:52:40.940898 Total UI for P1: 0, mck2ui 16
5896 05:52:40.944524 best dqsien dly found for B1: ( 1, 2, 28)
5897 05:52:40.947375 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5898 05:52:40.950666 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5899 05:52:40.950747
5900 05:52:40.957369 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5901 05:52:40.960466 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5902 05:52:40.964000 [Gating] SW calibration Done
5903 05:52:40.964081 ==
5904 05:52:40.967483 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 05:52:40.970538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 05:52:40.970619 ==
5907 05:52:40.970684 RX Vref Scan: 0
5908 05:52:40.970743
5909 05:52:40.974042 RX Vref 0 -> 0, step: 1
5910 05:52:40.974127
5911 05:52:40.977543 RX Delay -80 -> 252, step: 8
5912 05:52:40.980847 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5913 05:52:40.983845 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5914 05:52:40.990562 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5915 05:52:40.993465 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5916 05:52:40.997162 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5917 05:52:41.000573 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5918 05:52:41.003292 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5919 05:52:41.006955 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5920 05:52:41.013312 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5921 05:52:41.016883 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5922 05:52:41.019885 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5923 05:52:41.023446 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5924 05:52:41.026378 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5925 05:52:41.033104 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5926 05:52:41.036529 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5927 05:52:41.040042 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5928 05:52:41.040124 ==
5929 05:52:41.043538 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 05:52:41.046573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 05:52:41.046655 ==
5932 05:52:41.049566 DQS Delay:
5933 05:52:41.049648 DQS0 = 0, DQS1 = 0
5934 05:52:41.053244 DQM Delay:
5935 05:52:41.053325 DQM0 = 94, DQM1 = 89
5936 05:52:41.053390 DQ Delay:
5937 05:52:41.056466 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5938 05:52:41.059822 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5939 05:52:41.062865 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5940 05:52:41.066239 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =99
5941 05:52:41.066322
5942 05:52:41.066388
5943 05:52:41.069729 ==
5944 05:52:41.073246 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 05:52:41.076195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 05:52:41.076277 ==
5947 05:52:41.076343
5948 05:52:41.076402
5949 05:52:41.079751 TX Vref Scan disable
5950 05:52:41.079832 == TX Byte 0 ==
5951 05:52:41.086529 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5952 05:52:41.089414 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5953 05:52:41.089554 == TX Byte 1 ==
5954 05:52:41.096050 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5955 05:52:41.099520 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5956 05:52:41.099604 ==
5957 05:52:41.102539 Dram Type= 6, Freq= 0, CH_1, rank 1
5958 05:52:41.106003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5959 05:52:41.106085 ==
5960 05:52:41.106150
5961 05:52:41.106210
5962 05:52:41.109605 TX Vref Scan disable
5963 05:52:41.112423 == TX Byte 0 ==
5964 05:52:41.115810 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5965 05:52:41.119077 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5966 05:52:41.122707 == TX Byte 1 ==
5967 05:52:41.126017 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5968 05:52:41.129305 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5969 05:52:41.129406
5970 05:52:41.132241 [DATLAT]
5971 05:52:41.132323 Freq=933, CH1 RK1
5972 05:52:41.132388
5973 05:52:41.135914 DATLAT Default: 0xb
5974 05:52:41.135994 0, 0xFFFF, sum = 0
5975 05:52:41.139024 1, 0xFFFF, sum = 0
5976 05:52:41.139108 2, 0xFFFF, sum = 0
5977 05:52:41.142587 3, 0xFFFF, sum = 0
5978 05:52:41.142686 4, 0xFFFF, sum = 0
5979 05:52:41.145652 5, 0xFFFF, sum = 0
5980 05:52:41.145735 6, 0xFFFF, sum = 0
5981 05:52:41.149198 7, 0xFFFF, sum = 0
5982 05:52:41.149281 8, 0xFFFF, sum = 0
5983 05:52:41.152214 9, 0xFFFF, sum = 0
5984 05:52:41.152297 10, 0x0, sum = 1
5985 05:52:41.155789 11, 0x0, sum = 2
5986 05:52:41.155872 12, 0x0, sum = 3
5987 05:52:41.158795 13, 0x0, sum = 4
5988 05:52:41.158878 best_step = 11
5989 05:52:41.158943
5990 05:52:41.159003 ==
5991 05:52:41.162415 Dram Type= 6, Freq= 0, CH_1, rank 1
5992 05:52:41.168760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5993 05:52:41.168844 ==
5994 05:52:41.168924 RX Vref Scan: 0
5995 05:52:41.168998
5996 05:52:41.172092 RX Vref 0 -> 0, step: 1
5997 05:52:41.172173
5998 05:52:41.175771 RX Delay -69 -> 252, step: 4
5999 05:52:41.178719 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
6000 05:52:41.182160 iDelay=203, Bit 1, Center 88 (-9 ~ 186) 196
6001 05:52:41.188861 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
6002 05:52:41.191902 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
6003 05:52:41.195535 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
6004 05:52:41.199062 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
6005 05:52:41.202016 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
6006 05:52:41.205644 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
6007 05:52:41.211931 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
6008 05:52:41.215578 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
6009 05:52:41.218484 iDelay=203, Bit 10, Center 96 (3 ~ 190) 188
6010 05:52:41.222097 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
6011 05:52:41.225454 iDelay=203, Bit 12, Center 100 (7 ~ 194) 188
6012 05:52:41.231955 iDelay=203, Bit 13, Center 100 (7 ~ 194) 188
6013 05:52:41.235109 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
6014 05:52:41.238312 iDelay=203, Bit 15, Center 100 (7 ~ 194) 188
6015 05:52:41.238393 ==
6016 05:52:41.242146 Dram Type= 6, Freq= 0, CH_1, rank 1
6017 05:52:41.245059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6018 05:52:41.245141 ==
6019 05:52:41.248616 DQS Delay:
6020 05:52:41.248697 DQS0 = 0, DQS1 = 0
6021 05:52:41.251627 DQM Delay:
6022 05:52:41.251709 DQM0 = 92, DQM1 = 92
6023 05:52:41.251774 DQ Delay:
6024 05:52:41.254928 DQ0 =96, DQ1 =88, DQ2 =82, DQ3 =88
6025 05:52:41.258491 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
6026 05:52:41.261467 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
6027 05:52:41.265109 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =100
6028 05:52:41.268143
6029 05:52:41.268224
6030 05:52:41.274763 [DQSOSCAuto] RK1, (LSB)MR18= 0xb1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
6031 05:52:41.278346 CH1 RK1: MR19=505, MR18=B1F
6032 05:52:41.284696 CH1_RK1: MR19=0x505, MR18=0xB1F, DQSOSC=412, MR23=63, INC=63, DEC=42
6033 05:52:41.284778 [RxdqsGatingPostProcess] freq 933
6034 05:52:41.291664 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6035 05:52:41.294444 best DQS0 dly(2T, 0.5T) = (0, 10)
6036 05:52:41.298288 best DQS1 dly(2T, 0.5T) = (0, 10)
6037 05:52:41.301331 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6038 05:52:41.305009 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6039 05:52:41.307925 best DQS0 dly(2T, 0.5T) = (0, 10)
6040 05:52:41.310965 best DQS1 dly(2T, 0.5T) = (0, 10)
6041 05:52:41.314575 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6042 05:52:41.317798 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6043 05:52:41.321461 Pre-setting of DQS Precalculation
6044 05:52:41.324485 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6045 05:52:41.330927 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6046 05:52:41.341168 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6047 05:52:41.341250
6048 05:52:41.341314
6049 05:52:41.344512 [Calibration Summary] 1866 Mbps
6050 05:52:41.344592 CH 0, Rank 0
6051 05:52:41.347841 SW Impedance : PASS
6052 05:52:41.347921 DUTY Scan : NO K
6053 05:52:41.351057 ZQ Calibration : PASS
6054 05:52:41.351218 Jitter Meter : NO K
6055 05:52:41.354326 CBT Training : PASS
6056 05:52:41.357374 Write leveling : PASS
6057 05:52:41.357456 RX DQS gating : PASS
6058 05:52:41.360967 RX DQ/DQS(RDDQC) : PASS
6059 05:52:41.364031 TX DQ/DQS : PASS
6060 05:52:41.364112 RX DATLAT : PASS
6061 05:52:41.367608 RX DQ/DQS(Engine): PASS
6062 05:52:41.370607 TX OE : NO K
6063 05:52:41.370688 All Pass.
6064 05:52:41.370753
6065 05:52:41.370811 CH 0, Rank 1
6066 05:52:41.374154 SW Impedance : PASS
6067 05:52:41.377722 DUTY Scan : NO K
6068 05:52:41.377803 ZQ Calibration : PASS
6069 05:52:41.380702 Jitter Meter : NO K
6070 05:52:41.383856 CBT Training : PASS
6071 05:52:41.383937 Write leveling : PASS
6072 05:52:41.387250 RX DQS gating : PASS
6073 05:52:41.390702 RX DQ/DQS(RDDQC) : PASS
6074 05:52:41.390782 TX DQ/DQS : PASS
6075 05:52:41.394023 RX DATLAT : PASS
6076 05:52:41.397280 RX DQ/DQS(Engine): PASS
6077 05:52:41.397402 TX OE : NO K
6078 05:52:41.397528 All Pass.
6079 05:52:41.400545
6080 05:52:41.400625 CH 1, Rank 0
6081 05:52:41.403806 SW Impedance : PASS
6082 05:52:41.403887 DUTY Scan : NO K
6083 05:52:41.406987 ZQ Calibration : PASS
6084 05:52:41.410455 Jitter Meter : NO K
6085 05:52:41.410536 CBT Training : PASS
6086 05:52:41.414149 Write leveling : PASS
6087 05:52:41.414229 RX DQS gating : PASS
6088 05:52:41.417138 RX DQ/DQS(RDDQC) : PASS
6089 05:52:41.420586 TX DQ/DQS : PASS
6090 05:52:41.420667 RX DATLAT : PASS
6091 05:52:41.423610 RX DQ/DQS(Engine): PASS
6092 05:52:41.427307 TX OE : NO K
6093 05:52:41.427395 All Pass.
6094 05:52:41.427461
6095 05:52:41.427521 CH 1, Rank 1
6096 05:52:41.430204 SW Impedance : PASS
6097 05:52:41.433931 DUTY Scan : NO K
6098 05:52:41.434012 ZQ Calibration : PASS
6099 05:52:41.436864 Jitter Meter : NO K
6100 05:52:41.440339 CBT Training : PASS
6101 05:52:41.440446 Write leveling : PASS
6102 05:52:41.443966 RX DQS gating : PASS
6103 05:52:41.446768 RX DQ/DQS(RDDQC) : PASS
6104 05:52:41.446848 TX DQ/DQS : PASS
6105 05:52:41.450387 RX DATLAT : PASS
6106 05:52:41.453963 RX DQ/DQS(Engine): PASS
6107 05:52:41.454044 TX OE : NO K
6108 05:52:41.454109 All Pass.
6109 05:52:41.456772
6110 05:52:41.456862 DramC Write-DBI off
6111 05:52:41.460186 PER_BANK_REFRESH: Hybrid Mode
6112 05:52:41.460269 TX_TRACKING: ON
6113 05:52:41.470278 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6114 05:52:41.473262 [FAST_K] Save calibration result to emmc
6115 05:52:41.476923 dramc_set_vcore_voltage set vcore to 650000
6116 05:52:41.480024 Read voltage for 400, 6
6117 05:52:41.480106 Vio18 = 0
6118 05:52:41.483506 Vcore = 650000
6119 05:52:41.483587 Vdram = 0
6120 05:52:41.483652 Vddq = 0
6121 05:52:41.483748 Vmddr = 0
6122 05:52:41.489890 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6123 05:52:41.496430 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6124 05:52:41.496513 MEM_TYPE=3, freq_sel=20
6125 05:52:41.500023 sv_algorithm_assistance_LP4_800
6126 05:52:41.503363 ============ PULL DRAM RESETB DOWN ============
6127 05:52:41.510028 ========== PULL DRAM RESETB DOWN end =========
6128 05:52:41.513353 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6129 05:52:41.516758 ===================================
6130 05:52:41.519539 LPDDR4 DRAM CONFIGURATION
6131 05:52:41.523138 ===================================
6132 05:52:41.523223 EX_ROW_EN[0] = 0x0
6133 05:52:41.526593 EX_ROW_EN[1] = 0x0
6134 05:52:41.526675 LP4Y_EN = 0x0
6135 05:52:41.529623 WORK_FSP = 0x0
6136 05:52:41.533074 WL = 0x2
6137 05:52:41.533156 RL = 0x2
6138 05:52:41.536105 BL = 0x2
6139 05:52:41.536187 RPST = 0x0
6140 05:52:41.539557 RD_PRE = 0x0
6141 05:52:41.539639 WR_PRE = 0x1
6142 05:52:41.543292 WR_PST = 0x0
6143 05:52:41.543374 DBI_WR = 0x0
6144 05:52:41.546089 DBI_RD = 0x0
6145 05:52:41.546171 OTF = 0x1
6146 05:52:41.549568 ===================================
6147 05:52:41.553209 ===================================
6148 05:52:41.556139 ANA top config
6149 05:52:41.559664 ===================================
6150 05:52:41.559747 DLL_ASYNC_EN = 0
6151 05:52:41.562684 ALL_SLAVE_EN = 1
6152 05:52:41.566161 NEW_RANK_MODE = 1
6153 05:52:41.569502 DLL_IDLE_MODE = 1
6154 05:52:41.569598 LP45_APHY_COMB_EN = 1
6155 05:52:41.572864 TX_ODT_DIS = 1
6156 05:52:41.576415 NEW_8X_MODE = 1
6157 05:52:41.579508 ===================================
6158 05:52:41.582538 ===================================
6159 05:52:41.586193 data_rate = 800
6160 05:52:41.589690 CKR = 1
6161 05:52:41.592624 DQ_P2S_RATIO = 4
6162 05:52:41.596077 ===================================
6163 05:52:41.596160 CA_P2S_RATIO = 4
6164 05:52:41.599636 DQ_CA_OPEN = 0
6165 05:52:41.602684 DQ_SEMI_OPEN = 1
6166 05:52:41.606163 CA_SEMI_OPEN = 1
6167 05:52:41.609630 CA_FULL_RATE = 0
6168 05:52:41.612707 DQ_CKDIV4_EN = 0
6169 05:52:41.612789 CA_CKDIV4_EN = 1
6170 05:52:41.615873 CA_PREDIV_EN = 0
6171 05:52:41.619315 PH8_DLY = 0
6172 05:52:41.622634 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6173 05:52:41.626130 DQ_AAMCK_DIV = 0
6174 05:52:41.629077 CA_AAMCK_DIV = 0
6175 05:52:41.629160 CA_ADMCK_DIV = 4
6176 05:52:41.632429 DQ_TRACK_CA_EN = 0
6177 05:52:41.636076 CA_PICK = 800
6178 05:52:41.639487 CA_MCKIO = 400
6179 05:52:41.642522 MCKIO_SEMI = 400
6180 05:52:41.645621 PLL_FREQ = 3016
6181 05:52:41.649099 DQ_UI_PI_RATIO = 32
6182 05:52:41.649180 CA_UI_PI_RATIO = 32
6183 05:52:41.652659 ===================================
6184 05:52:41.656174 ===================================
6185 05:52:41.659237 memory_type:LPDDR4
6186 05:52:41.662155 GP_NUM : 10
6187 05:52:41.662237 SRAM_EN : 1
6188 05:52:41.665842 MD32_EN : 0
6189 05:52:41.669296 ===================================
6190 05:52:41.672439 [ANA_INIT] >>>>>>>>>>>>>>
6191 05:52:41.675870 <<<<<< [CONFIGURE PHASE]: ANA_TX
6192 05:52:41.679347 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6193 05:52:41.682361 ===================================
6194 05:52:41.682443 data_rate = 800,PCW = 0X7400
6195 05:52:41.685900 ===================================
6196 05:52:41.689434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6197 05:52:41.695543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6198 05:52:41.709285 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6199 05:52:41.712086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6200 05:52:41.715517 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6201 05:52:41.719161 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6202 05:52:41.722410 [ANA_INIT] flow start
6203 05:52:41.722492 [ANA_INIT] PLL >>>>>>>>
6204 05:52:41.725806 [ANA_INIT] PLL <<<<<<<<
6205 05:52:41.729154 [ANA_INIT] MIDPI >>>>>>>>
6206 05:52:41.729235 [ANA_INIT] MIDPI <<<<<<<<
6207 05:52:41.731965 [ANA_INIT] DLL >>>>>>>>
6208 05:52:41.735397 [ANA_INIT] flow end
6209 05:52:41.738659 ============ LP4 DIFF to SE enter ============
6210 05:52:41.742170 ============ LP4 DIFF to SE exit ============
6211 05:52:41.745674 [ANA_INIT] <<<<<<<<<<<<<
6212 05:52:41.748688 [Flow] Enable top DCM control >>>>>
6213 05:52:41.752319 [Flow] Enable top DCM control <<<<<
6214 05:52:41.755276 Enable DLL master slave shuffle
6215 05:52:41.758821 ==============================================================
6216 05:52:41.761907 Gating Mode config
6217 05:52:41.768347 ==============================================================
6218 05:52:41.768429 Config description:
6219 05:52:41.778540 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6220 05:52:41.784762 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6221 05:52:41.791762 SELPH_MODE 0: By rank 1: By Phase
6222 05:52:41.794792 ==============================================================
6223 05:52:41.798395 GAT_TRACK_EN = 0
6224 05:52:41.801280 RX_GATING_MODE = 2
6225 05:52:41.804961 RX_GATING_TRACK_MODE = 2
6226 05:52:41.808008 SELPH_MODE = 1
6227 05:52:41.811378 PICG_EARLY_EN = 1
6228 05:52:41.814903 VALID_LAT_VALUE = 1
6229 05:52:41.817773 ==============================================================
6230 05:52:41.821343 Enter into Gating configuration >>>>
6231 05:52:41.824898 Exit from Gating configuration <<<<
6232 05:52:41.828178 Enter into DVFS_PRE_config >>>>>
6233 05:52:41.841165 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6234 05:52:41.844579 Exit from DVFS_PRE_config <<<<<
6235 05:52:41.847811 Enter into PICG configuration >>>>
6236 05:52:41.851069 Exit from PICG configuration <<<<
6237 05:52:41.851166 [RX_INPUT] configuration >>>>>
6238 05:52:41.854754 [RX_INPUT] configuration <<<<<
6239 05:52:41.861270 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6240 05:52:41.864358 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6241 05:52:41.871015 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6242 05:52:41.877713 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6243 05:52:41.884229 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6244 05:52:41.890718 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6245 05:52:41.894191 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6246 05:52:41.897266 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6247 05:52:41.904048 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6248 05:52:41.907544 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6249 05:52:41.910539 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6250 05:52:41.916954 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6251 05:52:41.920329 ===================================
6252 05:52:41.920403 LPDDR4 DRAM CONFIGURATION
6253 05:52:41.923380 ===================================
6254 05:52:41.927134 EX_ROW_EN[0] = 0x0
6255 05:52:41.927215 EX_ROW_EN[1] = 0x0
6256 05:52:41.930113 LP4Y_EN = 0x0
6257 05:52:41.930193 WORK_FSP = 0x0
6258 05:52:41.933459 WL = 0x2
6259 05:52:41.936759 RL = 0x2
6260 05:52:41.936864 BL = 0x2
6261 05:52:41.940081 RPST = 0x0
6262 05:52:41.940182 RD_PRE = 0x0
6263 05:52:41.943678 WR_PRE = 0x1
6264 05:52:41.943777 WR_PST = 0x0
6265 05:52:41.946570 DBI_WR = 0x0
6266 05:52:41.946644 DBI_RD = 0x0
6267 05:52:41.949959 OTF = 0x1
6268 05:52:41.953358 ===================================
6269 05:52:41.956588 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6270 05:52:41.960094 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6271 05:52:41.966583 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6272 05:52:41.970043 ===================================
6273 05:52:41.970125 LPDDR4 DRAM CONFIGURATION
6274 05:52:41.973003 ===================================
6275 05:52:41.976582 EX_ROW_EN[0] = 0x10
6276 05:52:41.976663 EX_ROW_EN[1] = 0x0
6277 05:52:41.979632 LP4Y_EN = 0x0
6278 05:52:41.983155 WORK_FSP = 0x0
6279 05:52:41.983235 WL = 0x2
6280 05:52:41.986086 RL = 0x2
6281 05:52:41.986167 BL = 0x2
6282 05:52:41.989404 RPST = 0x0
6283 05:52:41.989540 RD_PRE = 0x0
6284 05:52:41.992664 WR_PRE = 0x1
6285 05:52:41.992745 WR_PST = 0x0
6286 05:52:41.996186 DBI_WR = 0x0
6287 05:52:41.996266 DBI_RD = 0x0
6288 05:52:41.999581 OTF = 0x1
6289 05:52:42.002691 ===================================
6290 05:52:42.009575 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6291 05:52:42.012588 nWR fixed to 30
6292 05:52:42.012683 [ModeRegInit_LP4] CH0 RK0
6293 05:52:42.016237 [ModeRegInit_LP4] CH0 RK1
6294 05:52:42.018999 [ModeRegInit_LP4] CH1 RK0
6295 05:52:42.022509 [ModeRegInit_LP4] CH1 RK1
6296 05:52:42.022609 match AC timing 19
6297 05:52:42.026048 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6298 05:52:42.032765 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6299 05:52:42.035526 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6300 05:52:42.039235 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6301 05:52:42.045311 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6302 05:52:42.045409 ==
6303 05:52:42.048786 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 05:52:42.052134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 05:52:42.052210 ==
6306 05:52:42.058827 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6307 05:52:42.065170 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6308 05:52:42.068466 [CA 0] Center 36 (8~64) winsize 57
6309 05:52:42.071754 [CA 1] Center 36 (8~64) winsize 57
6310 05:52:42.071857 [CA 2] Center 36 (8~64) winsize 57
6311 05:52:42.074975 [CA 3] Center 36 (8~64) winsize 57
6312 05:52:42.078506 [CA 4] Center 36 (8~64) winsize 57
6313 05:52:42.081659 [CA 5] Center 36 (8~64) winsize 57
6314 05:52:42.081730
6315 05:52:42.085317 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6316 05:52:42.088742
6317 05:52:42.091618 [CATrainingPosCal] consider 1 rank data
6318 05:52:42.091691 u2DelayCellTimex100 = 270/100 ps
6319 05:52:42.098657 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 05:52:42.101516 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 05:52:42.105100 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 05:52:42.108206 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 05:52:42.111689 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 05:52:42.114714 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 05:52:42.114811
6326 05:52:42.118451 CA PerBit enable=1, Macro0, CA PI delay=36
6327 05:52:42.118522
6328 05:52:42.121341 [CBTSetCACLKResult] CA Dly = 36
6329 05:52:42.125002 CS Dly: 1 (0~32)
6330 05:52:42.125100 ==
6331 05:52:42.127942 Dram Type= 6, Freq= 0, CH_0, rank 1
6332 05:52:42.131601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 05:52:42.131679 ==
6334 05:52:42.138326 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6335 05:52:42.141271 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6336 05:52:42.144842 [CA 0] Center 36 (8~64) winsize 57
6337 05:52:42.147927 [CA 1] Center 36 (8~64) winsize 57
6338 05:52:42.151236 [CA 2] Center 36 (8~64) winsize 57
6339 05:52:42.154466 [CA 3] Center 36 (8~64) winsize 57
6340 05:52:42.157691 [CA 4] Center 36 (8~64) winsize 57
6341 05:52:42.160727 [CA 5] Center 36 (8~64) winsize 57
6342 05:52:42.160823
6343 05:52:42.164405 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6344 05:52:42.164506
6345 05:52:42.167429 [CATrainingPosCal] consider 2 rank data
6346 05:52:42.170805 u2DelayCellTimex100 = 270/100 ps
6347 05:52:42.174275 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 05:52:42.180509 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 05:52:42.183949 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 05:52:42.187348 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6351 05:52:42.190880 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6352 05:52:42.193992 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6353 05:52:42.194065
6354 05:52:42.197430 CA PerBit enable=1, Macro0, CA PI delay=36
6355 05:52:42.197553
6356 05:52:42.200749 [CBTSetCACLKResult] CA Dly = 36
6357 05:52:42.200849 CS Dly: 1 (0~32)
6358 05:52:42.203819
6359 05:52:42.207362 ----->DramcWriteLeveling(PI) begin...
6360 05:52:42.207437 ==
6361 05:52:42.210186 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 05:52:42.213708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 05:52:42.213810 ==
6364 05:52:42.217219 Write leveling (Byte 0): 40 => 8
6365 05:52:42.220291 Write leveling (Byte 1): 40 => 8
6366 05:52:42.223830 DramcWriteLeveling(PI) end<-----
6367 05:52:42.223934
6368 05:52:42.224026 ==
6369 05:52:42.226874 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 05:52:42.230394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 05:52:42.230493 ==
6372 05:52:42.233305 [Gating] SW mode calibration
6373 05:52:42.240413 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6374 05:52:42.246423 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6375 05:52:42.249951 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6376 05:52:42.253369 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6377 05:52:42.259743 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6378 05:52:42.263122 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6379 05:52:42.266403 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6380 05:52:42.273177 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6381 05:52:42.276389 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6382 05:52:42.279910 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6383 05:52:42.286179 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6384 05:52:42.286262 Total UI for P1: 0, mck2ui 16
6385 05:52:42.292846 best dqsien dly found for B0: ( 0, 14, 24)
6386 05:52:42.292923 Total UI for P1: 0, mck2ui 16
6387 05:52:42.299656 best dqsien dly found for B1: ( 0, 14, 24)
6388 05:52:42.302916 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6389 05:52:42.306080 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6390 05:52:42.306187
6391 05:52:42.309404 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6392 05:52:42.313104 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6393 05:52:42.316093 [Gating] SW calibration Done
6394 05:52:42.316164 ==
6395 05:52:42.319452 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 05:52:42.322587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 05:52:42.322658 ==
6398 05:52:42.325892 RX Vref Scan: 0
6399 05:52:42.325961
6400 05:52:42.326019 RX Vref 0 -> 0, step: 1
6401 05:52:42.329442
6402 05:52:42.329549 RX Delay -410 -> 252, step: 16
6403 05:52:42.335827 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6404 05:52:42.339299 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6405 05:52:42.342236 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6406 05:52:42.345880 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6407 05:52:42.352489 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6408 05:52:42.355392 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6409 05:52:42.359065 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6410 05:52:42.365148 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6411 05:52:42.368822 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6412 05:52:42.372079 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6413 05:52:42.375414 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6414 05:52:42.381893 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6415 05:52:42.385323 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6416 05:52:42.388878 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6417 05:52:42.391888 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6418 05:52:42.398420 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6419 05:52:42.398503 ==
6420 05:52:42.401928 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 05:52:42.404905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 05:52:42.404978 ==
6423 05:52:42.405039 DQS Delay:
6424 05:52:42.408174 DQS0 = 59, DQS1 = 59
6425 05:52:42.408268 DQM Delay:
6426 05:52:42.411485 DQM0 = 18, DQM1 = 10
6427 05:52:42.411559 DQ Delay:
6428 05:52:42.415298 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6429 05:52:42.418555 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6430 05:52:42.421499 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6431 05:52:42.424996 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6432 05:52:42.425065
6433 05:52:42.425125
6434 05:52:42.425180 ==
6435 05:52:42.428491 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 05:52:42.431715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 05:52:42.431785 ==
6438 05:52:42.431846
6439 05:52:42.435135
6440 05:52:42.435204 TX Vref Scan disable
6441 05:52:42.438110 == TX Byte 0 ==
6442 05:52:42.441585 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6443 05:52:42.445173 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6444 05:52:42.448259 == TX Byte 1 ==
6445 05:52:42.451754 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6446 05:52:42.454740 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6447 05:52:42.454810 ==
6448 05:52:42.458339 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 05:52:42.461273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 05:52:42.464881 ==
6451 05:52:42.464955
6452 05:52:42.465015
6453 05:52:42.465072 TX Vref Scan disable
6454 05:52:42.467964 == TX Byte 0 ==
6455 05:52:42.471471 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6456 05:52:42.474515 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6457 05:52:42.478116 == TX Byte 1 ==
6458 05:52:42.481484 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6459 05:52:42.484999 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6460 05:52:42.485071
6461 05:52:42.485147 [DATLAT]
6462 05:52:42.487750 Freq=400, CH0 RK0
6463 05:52:42.487822
6464 05:52:42.491170 DATLAT Default: 0xf
6465 05:52:42.491251 0, 0xFFFF, sum = 0
6466 05:52:42.494700 1, 0xFFFF, sum = 0
6467 05:52:42.494773 2, 0xFFFF, sum = 0
6468 05:52:42.497693 3, 0xFFFF, sum = 0
6469 05:52:42.497763 4, 0xFFFF, sum = 0
6470 05:52:42.501125 5, 0xFFFF, sum = 0
6471 05:52:42.501195 6, 0xFFFF, sum = 0
6472 05:52:42.504794 7, 0xFFFF, sum = 0
6473 05:52:42.504864 8, 0xFFFF, sum = 0
6474 05:52:42.507624 9, 0xFFFF, sum = 0
6475 05:52:42.507724 10, 0xFFFF, sum = 0
6476 05:52:42.511320 11, 0xFFFF, sum = 0
6477 05:52:42.511407 12, 0xFFFF, sum = 0
6478 05:52:42.514445 13, 0x0, sum = 1
6479 05:52:42.514515 14, 0x0, sum = 2
6480 05:52:42.517924 15, 0x0, sum = 3
6481 05:52:42.518011 16, 0x0, sum = 4
6482 05:52:42.521162 best_step = 14
6483 05:52:42.521232
6484 05:52:42.521291 ==
6485 05:52:42.524347 Dram Type= 6, Freq= 0, CH_0, rank 0
6486 05:52:42.527643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 05:52:42.527717 ==
6488 05:52:42.530916 RX Vref Scan: 1
6489 05:52:42.531020
6490 05:52:42.531110 RX Vref 0 -> 0, step: 1
6491 05:52:42.531202
6492 05:52:42.534119 RX Delay -359 -> 252, step: 8
6493 05:52:42.534192
6494 05:52:42.537371 Set Vref, RX VrefLevel [Byte0]: 64
6495 05:52:42.540855 [Byte1]: 52
6496 05:52:42.545736
6497 05:52:42.545809 Final RX Vref Byte 0 = 64 to rank0
6498 05:52:42.548941 Final RX Vref Byte 1 = 52 to rank0
6499 05:52:42.552467 Final RX Vref Byte 0 = 64 to rank1
6500 05:52:42.555594 Final RX Vref Byte 1 = 52 to rank1==
6501 05:52:42.558668 Dram Type= 6, Freq= 0, CH_0, rank 0
6502 05:52:42.565650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 05:52:42.565734 ==
6504 05:52:42.565799 DQS Delay:
6505 05:52:42.568755 DQS0 = 60, DQS1 = 68
6506 05:52:42.568837 DQM Delay:
6507 05:52:42.568901 DQM0 = 14, DQM1 = 14
6508 05:52:42.572178 DQ Delay:
6509 05:52:42.575231 DQ0 =12, DQ1 =16, DQ2 =16, DQ3 =8
6510 05:52:42.578986 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6511 05:52:42.579067 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6512 05:52:42.585623 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6513 05:52:42.585704
6514 05:52:42.585768
6515 05:52:42.591757 [DQSOSCAuto] RK0, (LSB)MR18= 0x7f7e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6516 05:52:42.595111 CH0 RK0: MR19=C0C, MR18=7F7E
6517 05:52:42.602217 CH0_RK0: MR19=0xC0C, MR18=0x7F7E, DQSOSC=393, MR23=63, INC=382, DEC=254
6518 05:52:42.602343 ==
6519 05:52:42.605092 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 05:52:42.608699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 05:52:42.608781 ==
6522 05:52:42.611660 [Gating] SW mode calibration
6523 05:52:42.618674 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6524 05:52:42.625134 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6525 05:52:42.628468 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6526 05:52:42.631403 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6527 05:52:42.638316 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6528 05:52:42.641438 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6529 05:52:42.644881 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6530 05:52:42.651211 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6531 05:52:42.654561 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6532 05:52:42.658294 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6533 05:52:42.664821 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6534 05:52:42.664904 Total UI for P1: 0, mck2ui 16
6535 05:52:42.671358 best dqsien dly found for B0: ( 0, 14, 24)
6536 05:52:42.671440 Total UI for P1: 0, mck2ui 16
6537 05:52:42.677922 best dqsien dly found for B1: ( 0, 14, 24)
6538 05:52:42.681436 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6539 05:52:42.684447 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6540 05:52:42.684528
6541 05:52:42.687976 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6542 05:52:42.690953 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6543 05:52:42.694566 [Gating] SW calibration Done
6544 05:52:42.694675 ==
6545 05:52:42.698113 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 05:52:42.701306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 05:52:42.701388 ==
6548 05:52:42.704496 RX Vref Scan: 0
6549 05:52:42.704577
6550 05:52:42.704642 RX Vref 0 -> 0, step: 1
6551 05:52:42.704701
6552 05:52:42.707782 RX Delay -410 -> 252, step: 16
6553 05:52:42.714346 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6554 05:52:42.718017 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6555 05:52:42.720937 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6556 05:52:42.724544 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6557 05:52:42.731124 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6558 05:52:42.734727 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6559 05:52:42.737673 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6560 05:52:42.741049 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6561 05:52:42.747575 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6562 05:52:42.750778 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6563 05:52:42.754379 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6564 05:52:42.757932 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6565 05:52:42.764461 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6566 05:52:42.767691 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6567 05:52:42.770523 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6568 05:52:42.777041 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6569 05:52:42.777123 ==
6570 05:52:42.780744 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 05:52:42.783670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 05:52:42.783752 ==
6573 05:52:42.783818 DQS Delay:
6574 05:52:42.787110 DQS0 = 59, DQS1 = 59
6575 05:52:42.787192 DQM Delay:
6576 05:52:42.790729 DQM0 = 17, DQM1 = 10
6577 05:52:42.790811 DQ Delay:
6578 05:52:42.793838 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6579 05:52:42.797393 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6580 05:52:42.800391 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6581 05:52:42.803906 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6582 05:52:42.803988
6583 05:52:42.804053
6584 05:52:42.804112 ==
6585 05:52:42.806761 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 05:52:42.810035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 05:52:42.810146 ==
6588 05:52:42.810237
6589 05:52:42.810322
6590 05:52:42.813354 TX Vref Scan disable
6591 05:52:42.816670 == TX Byte 0 ==
6592 05:52:42.820270 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6593 05:52:42.823791 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6594 05:52:42.826723 == TX Byte 1 ==
6595 05:52:42.830356 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6596 05:52:42.833828 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6597 05:52:42.833912 ==
6598 05:52:42.836741 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 05:52:42.839939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 05:52:42.840021 ==
6601 05:52:42.840086
6602 05:52:42.843469
6603 05:52:42.843580 TX Vref Scan disable
6604 05:52:42.846453 == TX Byte 0 ==
6605 05:52:42.850138 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6606 05:52:42.853472 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6607 05:52:42.856410 == TX Byte 1 ==
6608 05:52:42.859804 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6609 05:52:42.863080 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6610 05:52:42.863162
6611 05:52:42.863227 [DATLAT]
6612 05:52:42.866562 Freq=400, CH0 RK1
6613 05:52:42.866675
6614 05:52:42.866767 DATLAT Default: 0xe
6615 05:52:42.869664 0, 0xFFFF, sum = 0
6616 05:52:42.872961 1, 0xFFFF, sum = 0
6617 05:52:42.873044 2, 0xFFFF, sum = 0
6618 05:52:42.876131 3, 0xFFFF, sum = 0
6619 05:52:42.876214 4, 0xFFFF, sum = 0
6620 05:52:42.879478 5, 0xFFFF, sum = 0
6621 05:52:42.879561 6, 0xFFFF, sum = 0
6622 05:52:42.883122 7, 0xFFFF, sum = 0
6623 05:52:42.883234 8, 0xFFFF, sum = 0
6624 05:52:42.886159 9, 0xFFFF, sum = 0
6625 05:52:42.886241 10, 0xFFFF, sum = 0
6626 05:52:42.889375 11, 0xFFFF, sum = 0
6627 05:52:42.889481 12, 0xFFFF, sum = 0
6628 05:52:42.893045 13, 0x0, sum = 1
6629 05:52:42.893127 14, 0x0, sum = 2
6630 05:52:42.895983 15, 0x0, sum = 3
6631 05:52:42.896066 16, 0x0, sum = 4
6632 05:52:42.899533 best_step = 14
6633 05:52:42.899614
6634 05:52:42.899678 ==
6635 05:52:42.902659 Dram Type= 6, Freq= 0, CH_0, rank 1
6636 05:52:42.906152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 05:52:42.906234 ==
6638 05:52:42.909726 RX Vref Scan: 0
6639 05:52:42.909807
6640 05:52:42.909871 RX Vref 0 -> 0, step: 1
6641 05:52:42.909932
6642 05:52:42.912614 RX Delay -359 -> 252, step: 8
6643 05:52:42.920778 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6644 05:52:42.924022 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6645 05:52:42.926980 iDelay=217, Bit 2, Center -56 (-303 ~ 192) 496
6646 05:52:42.930594 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6647 05:52:42.937227 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6648 05:52:42.940121 iDelay=217, Bit 5, Center -64 (-311 ~ 184) 496
6649 05:52:42.943805 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6650 05:52:42.950096 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6651 05:52:42.953640 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6652 05:52:42.956596 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6653 05:52:42.960202 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6654 05:52:42.966874 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6655 05:52:42.969875 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6656 05:52:42.973358 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6657 05:52:42.976692 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6658 05:52:42.983330 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6659 05:52:42.983412 ==
6660 05:52:42.986753 Dram Type= 6, Freq= 0, CH_0, rank 1
6661 05:52:42.989955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 05:52:42.990038 ==
6663 05:52:42.990103 DQS Delay:
6664 05:52:42.993326 DQS0 = 64, DQS1 = 72
6665 05:52:42.993407 DQM Delay:
6666 05:52:42.996354 DQM0 = 15, DQM1 = 17
6667 05:52:42.996435 DQ Delay:
6668 05:52:42.999957 DQ0 =12, DQ1 =20, DQ2 =8, DQ3 =12
6669 05:52:43.003167 DQ4 =12, DQ5 =0, DQ6 =28, DQ7 =28
6670 05:52:43.006751 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6671 05:52:43.009725 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6672 05:52:43.009806
6673 05:52:43.009871
6674 05:52:43.016684 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc72, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6675 05:52:43.020207 CH0 RK1: MR19=C0C, MR18=BC72
6676 05:52:43.026643 CH0_RK1: MR19=0xC0C, MR18=0xBC72, DQSOSC=386, MR23=63, INC=396, DEC=264
6677 05:52:43.030022 [RxdqsGatingPostProcess] freq 400
6678 05:52:43.036602 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6679 05:52:43.039628 best DQS0 dly(2T, 0.5T) = (0, 10)
6680 05:52:43.039709 best DQS1 dly(2T, 0.5T) = (0, 10)
6681 05:52:43.043206 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6682 05:52:43.046747 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6683 05:52:43.049749 best DQS0 dly(2T, 0.5T) = (0, 10)
6684 05:52:43.053264 best DQS1 dly(2T, 0.5T) = (0, 10)
6685 05:52:43.056179 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6686 05:52:43.059772 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6687 05:52:43.062675 Pre-setting of DQS Precalculation
6688 05:52:43.069351 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6689 05:52:43.069430 ==
6690 05:52:43.072798 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 05:52:43.076446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 05:52:43.076528 ==
6693 05:52:43.082964 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6694 05:52:43.089356 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6695 05:52:43.089453 [CA 0] Center 36 (8~64) winsize 57
6696 05:52:43.092796 [CA 1] Center 36 (8~64) winsize 57
6697 05:52:43.096027 [CA 2] Center 36 (8~64) winsize 57
6698 05:52:43.099079 [CA 3] Center 36 (8~64) winsize 57
6699 05:52:43.102689 [CA 4] Center 36 (8~64) winsize 57
6700 05:52:43.105845 [CA 5] Center 36 (8~64) winsize 57
6701 05:52:43.105940
6702 05:52:43.109243 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6703 05:52:43.109314
6704 05:52:43.112613 [CATrainingPosCal] consider 1 rank data
6705 05:52:43.115571 u2DelayCellTimex100 = 270/100 ps
6706 05:52:43.119356 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 05:52:43.125966 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 05:52:43.129189 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 05:52:43.132355 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 05:52:43.135461 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 05:52:43.139251 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 05:52:43.139332
6713 05:52:43.142156 CA PerBit enable=1, Macro0, CA PI delay=36
6714 05:52:43.142237
6715 05:52:43.145603 [CBTSetCACLKResult] CA Dly = 36
6716 05:52:43.145685 CS Dly: 1 (0~32)
6717 05:52:43.149139 ==
6718 05:52:43.152131 Dram Type= 6, Freq= 0, CH_1, rank 1
6719 05:52:43.155657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 05:52:43.155740 ==
6721 05:52:43.159119 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6722 05:52:43.165822 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6723 05:52:43.168690 [CA 0] Center 36 (8~64) winsize 57
6724 05:52:43.172308 [CA 1] Center 36 (8~64) winsize 57
6725 05:52:43.175348 [CA 2] Center 36 (8~64) winsize 57
6726 05:52:43.178862 [CA 3] Center 36 (8~64) winsize 57
6727 05:52:43.182411 [CA 4] Center 36 (8~64) winsize 57
6728 05:52:43.185443 [CA 5] Center 36 (8~64) winsize 57
6729 05:52:43.185559
6730 05:52:43.188497 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6731 05:52:43.188579
6732 05:52:43.192099 [CATrainingPosCal] consider 2 rank data
6733 05:52:43.195187 u2DelayCellTimex100 = 270/100 ps
6734 05:52:43.198828 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 05:52:43.201737 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 05:52:43.205075 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 05:52:43.208638 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6738 05:52:43.215373 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6739 05:52:43.218285 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6740 05:52:43.218396
6741 05:52:43.221864 CA PerBit enable=1, Macro0, CA PI delay=36
6742 05:52:43.221971
6743 05:52:43.225197 [CBTSetCACLKResult] CA Dly = 36
6744 05:52:43.225278 CS Dly: 1 (0~32)
6745 05:52:43.225343
6746 05:52:43.228512 ----->DramcWriteLeveling(PI) begin...
6747 05:52:43.228595 ==
6748 05:52:43.231817 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 05:52:43.238443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 05:52:43.238526 ==
6751 05:52:43.241815 Write leveling (Byte 0): 40 => 8
6752 05:52:43.244993 Write leveling (Byte 1): 40 => 8
6753 05:52:43.245074 DramcWriteLeveling(PI) end<-----
6754 05:52:43.245139
6755 05:52:43.248056 ==
6756 05:52:43.251565 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 05:52:43.254967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 05:52:43.255074 ==
6759 05:52:43.257956 [Gating] SW mode calibration
6760 05:52:43.265069 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6761 05:52:43.267879 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6762 05:52:43.274563 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6763 05:52:43.278225 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6764 05:52:43.281186 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6765 05:52:43.287754 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6766 05:52:43.291348 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6767 05:52:43.294304 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6768 05:52:43.300892 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6769 05:52:43.304520 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6770 05:52:43.307572 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6771 05:52:43.311010 Total UI for P1: 0, mck2ui 16
6772 05:52:43.314507 best dqsien dly found for B0: ( 0, 14, 24)
6773 05:52:43.317489 Total UI for P1: 0, mck2ui 16
6774 05:52:43.320732 best dqsien dly found for B1: ( 0, 14, 24)
6775 05:52:43.324275 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6776 05:52:43.327622 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6777 05:52:43.331156
6778 05:52:43.334455 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6779 05:52:43.337524 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6780 05:52:43.340925 [Gating] SW calibration Done
6781 05:52:43.341007 ==
6782 05:52:43.344349 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 05:52:43.347797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 05:52:43.347905 ==
6785 05:52:43.347998 RX Vref Scan: 0
6786 05:52:43.348061
6787 05:52:43.350659 RX Vref 0 -> 0, step: 1
6788 05:52:43.350741
6789 05:52:43.354050 RX Delay -410 -> 252, step: 16
6790 05:52:43.357396 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6791 05:52:43.364102 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6792 05:52:43.367288 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6793 05:52:43.370769 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6794 05:52:43.373768 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6795 05:52:43.380327 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6796 05:52:43.384047 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6797 05:52:43.386983 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6798 05:52:43.390689 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6799 05:52:43.397280 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6800 05:52:43.400261 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6801 05:52:43.403967 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6802 05:52:43.406951 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6803 05:52:43.413455 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6804 05:52:43.416961 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6805 05:52:43.420463 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6806 05:52:43.420540 ==
6807 05:52:43.423960 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 05:52:43.430340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 05:52:43.430423 ==
6810 05:52:43.430489 DQS Delay:
6811 05:52:43.433751 DQS0 = 51, DQS1 = 67
6812 05:52:43.433833 DQM Delay:
6813 05:52:43.433898 DQM0 = 12, DQM1 = 17
6814 05:52:43.436414 DQ Delay:
6815 05:52:43.440004 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6816 05:52:43.440102 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6817 05:52:43.443320 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6818 05:52:43.446673 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6819 05:52:43.449999
6820 05:52:43.450080
6821 05:52:43.450145 ==
6822 05:52:43.452971 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 05:52:43.456714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 05:52:43.456796 ==
6825 05:52:43.456862
6826 05:52:43.456923
6827 05:52:43.459699 TX Vref Scan disable
6828 05:52:43.459780 == TX Byte 0 ==
6829 05:52:43.463288 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6830 05:52:43.469422 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6831 05:52:43.469527 == TX Byte 1 ==
6832 05:52:43.473086 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6833 05:52:43.479627 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6834 05:52:43.479709 ==
6835 05:52:43.483093 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 05:52:43.486117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 05:52:43.486199 ==
6838 05:52:43.486265
6839 05:52:43.486327
6840 05:52:43.489666 TX Vref Scan disable
6841 05:52:43.489747 == TX Byte 0 ==
6842 05:52:43.496355 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6843 05:52:43.499363 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6844 05:52:43.499445 == TX Byte 1 ==
6845 05:52:43.505938 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6846 05:52:43.509445 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6847 05:52:43.509576
6848 05:52:43.509669 [DATLAT]
6849 05:52:43.512546 Freq=400, CH1 RK0
6850 05:52:43.512628
6851 05:52:43.512692 DATLAT Default: 0xf
6852 05:52:43.515502 0, 0xFFFF, sum = 0
6853 05:52:43.515585 1, 0xFFFF, sum = 0
6854 05:52:43.518895 2, 0xFFFF, sum = 0
6855 05:52:43.518978 3, 0xFFFF, sum = 0
6856 05:52:43.522478 4, 0xFFFF, sum = 0
6857 05:52:43.522561 5, 0xFFFF, sum = 0
6858 05:52:43.526071 6, 0xFFFF, sum = 0
6859 05:52:43.526154 7, 0xFFFF, sum = 0
6860 05:52:43.529016 8, 0xFFFF, sum = 0
6861 05:52:43.529099 9, 0xFFFF, sum = 0
6862 05:52:43.532122 10, 0xFFFF, sum = 0
6863 05:52:43.535616 11, 0xFFFF, sum = 0
6864 05:52:43.535699 12, 0xFFFF, sum = 0
6865 05:52:43.538885 13, 0x0, sum = 1
6866 05:52:43.538967 14, 0x0, sum = 2
6867 05:52:43.542329 15, 0x0, sum = 3
6868 05:52:43.542412 16, 0x0, sum = 4
6869 05:52:43.542478 best_step = 14
6870 05:52:43.542537
6871 05:52:43.545307 ==
6872 05:52:43.548812 Dram Type= 6, Freq= 0, CH_1, rank 0
6873 05:52:43.552237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 05:52:43.552320 ==
6875 05:52:43.552385 RX Vref Scan: 1
6876 05:52:43.552445
6877 05:52:43.555590 RX Vref 0 -> 0, step: 1
6878 05:52:43.555689
6879 05:52:43.558853 RX Delay -375 -> 252, step: 8
6880 05:52:43.558934
6881 05:52:43.561989 Set Vref, RX VrefLevel [Byte0]: 54
6882 05:52:43.565359 [Byte1]: 55
6883 05:52:43.568981
6884 05:52:43.569062 Final RX Vref Byte 0 = 54 to rank0
6885 05:52:43.572639 Final RX Vref Byte 1 = 55 to rank0
6886 05:52:43.575674 Final RX Vref Byte 0 = 54 to rank1
6887 05:52:43.578965 Final RX Vref Byte 1 = 55 to rank1==
6888 05:52:43.582602 Dram Type= 6, Freq= 0, CH_1, rank 0
6889 05:52:43.589224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 05:52:43.589346 ==
6891 05:52:43.589440 DQS Delay:
6892 05:52:43.592156 DQS0 = 52, DQS1 = 68
6893 05:52:43.592253 DQM Delay:
6894 05:52:43.592341 DQM0 = 9, DQM1 = 13
6895 05:52:43.595197 DQ Delay:
6896 05:52:43.598784 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6897 05:52:43.598866 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6898 05:52:43.601878 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6899 05:52:43.605442 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6900 05:52:43.605580
6901 05:52:43.608911
6902 05:52:43.615485 [DQSOSCAuto] RK0, (LSB)MR18= 0x5569, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6903 05:52:43.618550 CH1 RK0: MR19=C0C, MR18=5569
6904 05:52:43.624928 CH1_RK0: MR19=0xC0C, MR18=0x5569, DQSOSC=396, MR23=63, INC=376, DEC=251
6905 05:52:43.625012 ==
6906 05:52:43.628467 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 05:52:43.631850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 05:52:43.631930 ==
6909 05:52:43.634818 [Gating] SW mode calibration
6910 05:52:43.641345 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6911 05:52:43.648194 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6912 05:52:43.651731 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6913 05:52:43.654699 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6914 05:52:43.661603 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6915 05:52:43.664594 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6916 05:52:43.667883 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6917 05:52:43.674537 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6918 05:52:43.678099 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6919 05:52:43.681131 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6920 05:52:43.687642 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6921 05:52:43.687717 Total UI for P1: 0, mck2ui 16
6922 05:52:43.694179 best dqsien dly found for B0: ( 0, 14, 24)
6923 05:52:43.694255 Total UI for P1: 0, mck2ui 16
6924 05:52:43.701243 best dqsien dly found for B1: ( 0, 14, 24)
6925 05:52:43.704180 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6926 05:52:43.707703 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6927 05:52:43.707800
6928 05:52:43.710708 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6929 05:52:43.714406 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6930 05:52:43.717466 [Gating] SW calibration Done
6931 05:52:43.717579 ==
6932 05:52:43.720972 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 05:52:43.724529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 05:52:43.724613 ==
6935 05:52:43.727397 RX Vref Scan: 0
6936 05:52:43.727467
6937 05:52:43.727528 RX Vref 0 -> 0, step: 1
6938 05:52:43.727591
6939 05:52:43.730710 RX Delay -410 -> 252, step: 16
6940 05:52:43.737266 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6941 05:52:43.740807 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6942 05:52:43.744363 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6943 05:52:43.747456 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6944 05:52:43.753942 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6945 05:52:43.757429 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6946 05:52:43.760473 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6947 05:52:43.763962 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6948 05:52:43.770304 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6949 05:52:43.773785 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6950 05:52:43.777168 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6951 05:52:43.780259 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6952 05:52:43.787159 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6953 05:52:43.790222 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6954 05:52:43.793668 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6955 05:52:43.800571 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6956 05:52:43.800650 ==
6957 05:52:43.803544 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 05:52:43.807221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 05:52:43.807320 ==
6960 05:52:43.807418 DQS Delay:
6961 05:52:43.810101 DQS0 = 59, DQS1 = 59
6962 05:52:43.810171 DQM Delay:
6963 05:52:43.813629 DQM0 = 19, DQM1 = 16
6964 05:52:43.813729 DQ Delay:
6965 05:52:43.816736 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6966 05:52:43.820382 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6967 05:52:43.823332 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6968 05:52:43.826861 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6969 05:52:43.826932
6970 05:52:43.826993
6971 05:52:43.827050 ==
6972 05:52:43.829784 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 05:52:43.833407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 05:52:43.833546 ==
6975 05:52:43.833637
6976 05:52:43.833722
6977 05:52:43.836785 TX Vref Scan disable
6978 05:52:43.839874 == TX Byte 0 ==
6979 05:52:43.843263 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6980 05:52:43.846320 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6981 05:52:43.849981 == TX Byte 1 ==
6982 05:52:43.853447 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6983 05:52:43.856458 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6984 05:52:43.856555 ==
6985 05:52:43.860012 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 05:52:43.862853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 05:52:43.862924 ==
6988 05:52:43.866460
6989 05:52:43.866548
6990 05:52:43.866618 TX Vref Scan disable
6991 05:52:43.869428 == TX Byte 0 ==
6992 05:52:43.872780 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6993 05:52:43.876121 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6994 05:52:43.879627 == TX Byte 1 ==
6995 05:52:43.882683 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6996 05:52:43.886039 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6997 05:52:43.886114
6998 05:52:43.886186 [DATLAT]
6999 05:52:43.889274 Freq=400, CH1 RK1
7000 05:52:43.889377
7001 05:52:43.893015 DATLAT Default: 0xe
7002 05:52:43.893102 0, 0xFFFF, sum = 0
7003 05:52:43.896034 1, 0xFFFF, sum = 0
7004 05:52:43.896111 2, 0xFFFF, sum = 0
7005 05:52:43.899660 3, 0xFFFF, sum = 0
7006 05:52:43.899736 4, 0xFFFF, sum = 0
7007 05:52:43.903044 5, 0xFFFF, sum = 0
7008 05:52:43.903138 6, 0xFFFF, sum = 0
7009 05:52:43.906514 7, 0xFFFF, sum = 0
7010 05:52:43.906603 8, 0xFFFF, sum = 0
7011 05:52:43.909374 9, 0xFFFF, sum = 0
7012 05:52:43.909491 10, 0xFFFF, sum = 0
7013 05:52:43.913027 11, 0xFFFF, sum = 0
7014 05:52:43.913102 12, 0xFFFF, sum = 0
7015 05:52:43.915979 13, 0x0, sum = 1
7016 05:52:43.916048 14, 0x0, sum = 2
7017 05:52:43.919124 15, 0x0, sum = 3
7018 05:52:43.919197 16, 0x0, sum = 4
7019 05:52:43.922817 best_step = 14
7020 05:52:43.922906
7021 05:52:43.922993 ==
7022 05:52:43.925916 Dram Type= 6, Freq= 0, CH_1, rank 1
7023 05:52:43.928975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7024 05:52:43.929061 ==
7025 05:52:43.932600 RX Vref Scan: 0
7026 05:52:43.932666
7027 05:52:43.932725 RX Vref 0 -> 0, step: 1
7028 05:52:43.932788
7029 05:52:43.935711 RX Delay -359 -> 252, step: 8
7030 05:52:43.943819 iDelay=217, Bit 0, Center -40 (-287 ~ 208) 496
7031 05:52:43.946842 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7032 05:52:43.950380 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7033 05:52:43.953353 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7034 05:52:43.960075 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7035 05:52:43.963883 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7036 05:52:43.966785 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7037 05:52:43.970285 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7038 05:52:43.976964 iDelay=217, Bit 8, Center -68 (-327 ~ 192) 520
7039 05:52:43.980392 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7040 05:52:43.983318 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7041 05:52:43.986916 iDelay=217, Bit 11, Center -60 (-319 ~ 200) 520
7042 05:52:43.993641 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7043 05:52:43.996667 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7044 05:52:43.999987 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7045 05:52:44.006913 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7046 05:52:44.006994 ==
7047 05:52:44.010120 Dram Type= 6, Freq= 0, CH_1, rank 1
7048 05:52:44.013321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7049 05:52:44.013397 ==
7050 05:52:44.013467 DQS Delay:
7051 05:52:44.016835 DQS0 = 60, DQS1 = 68
7052 05:52:44.016913 DQM Delay:
7053 05:52:44.020241 DQM0 = 13, DQM1 = 14
7054 05:52:44.020315 DQ Delay:
7055 05:52:44.023242 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
7056 05:52:44.026961 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7057 05:52:44.029852 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
7058 05:52:44.033413 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
7059 05:52:44.033521
7060 05:52:44.033589
7061 05:52:44.040007 [DQSOSCAuto] RK1, (LSB)MR18= 0x72a2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
7062 05:52:44.043321 CH1 RK1: MR19=C0C, MR18=72A2
7063 05:52:44.049937 CH1_RK1: MR19=0xC0C, MR18=0x72A2, DQSOSC=389, MR23=63, INC=390, DEC=260
7064 05:52:44.052891 [RxdqsGatingPostProcess] freq 400
7065 05:52:44.059915 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7066 05:52:44.060020 best DQS0 dly(2T, 0.5T) = (0, 10)
7067 05:52:44.062940 best DQS1 dly(2T, 0.5T) = (0, 10)
7068 05:52:44.066427 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7069 05:52:44.070071 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7070 05:52:44.073001 best DQS0 dly(2T, 0.5T) = (0, 10)
7071 05:52:44.076506 best DQS1 dly(2T, 0.5T) = (0, 10)
7072 05:52:44.079935 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7073 05:52:44.082943 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7074 05:52:44.086413 Pre-setting of DQS Precalculation
7075 05:52:44.092825 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7076 05:52:44.099363 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7077 05:52:44.106385 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7078 05:52:44.106470
7079 05:52:44.106536
7080 05:52:44.109361 [Calibration Summary] 800 Mbps
7081 05:52:44.109463 CH 0, Rank 0
7082 05:52:44.113165 SW Impedance : PASS
7083 05:52:44.113266 DUTY Scan : NO K
7084 05:52:44.116359 ZQ Calibration : PASS
7085 05:52:44.119783 Jitter Meter : NO K
7086 05:52:44.119858 CBT Training : PASS
7087 05:52:44.122419 Write leveling : PASS
7088 05:52:44.125918 RX DQS gating : PASS
7089 05:52:44.125992 RX DQ/DQS(RDDQC) : PASS
7090 05:52:44.129494 TX DQ/DQS : PASS
7091 05:52:44.132491 RX DATLAT : PASS
7092 05:52:44.132563 RX DQ/DQS(Engine): PASS
7093 05:52:44.136132 TX OE : NO K
7094 05:52:44.136210 All Pass.
7095 05:52:44.136273
7096 05:52:44.139229 CH 0, Rank 1
7097 05:52:44.139299 SW Impedance : PASS
7098 05:52:44.142759 DUTY Scan : NO K
7099 05:52:44.145655 ZQ Calibration : PASS
7100 05:52:44.145723 Jitter Meter : NO K
7101 05:52:44.149197 CBT Training : PASS
7102 05:52:44.152206 Write leveling : NO K
7103 05:52:44.152284 RX DQS gating : PASS
7104 05:52:44.155789 RX DQ/DQS(RDDQC) : PASS
7105 05:52:44.159192 TX DQ/DQS : PASS
7106 05:52:44.159267 RX DATLAT : PASS
7107 05:52:44.162106 RX DQ/DQS(Engine): PASS
7108 05:52:44.165685 TX OE : NO K
7109 05:52:44.165761 All Pass.
7110 05:52:44.165823
7111 05:52:44.165881 CH 1, Rank 0
7112 05:52:44.168605 SW Impedance : PASS
7113 05:52:44.172143 DUTY Scan : NO K
7114 05:52:44.172248 ZQ Calibration : PASS
7115 05:52:44.175743 Jitter Meter : NO K
7116 05:52:44.178563 CBT Training : PASS
7117 05:52:44.178638 Write leveling : PASS
7118 05:52:44.181991 RX DQS gating : PASS
7119 05:52:44.185391 RX DQ/DQS(RDDQC) : PASS
7120 05:52:44.185484 TX DQ/DQS : PASS
7121 05:52:44.188990 RX DATLAT : PASS
7122 05:52:44.191878 RX DQ/DQS(Engine): PASS
7123 05:52:44.191956 TX OE : NO K
7124 05:52:44.192017 All Pass.
7125 05:52:44.195134
7126 05:52:44.195213 CH 1, Rank 1
7127 05:52:44.198727 SW Impedance : PASS
7128 05:52:44.198795 DUTY Scan : NO K
7129 05:52:44.201765 ZQ Calibration : PASS
7130 05:52:44.201830 Jitter Meter : NO K
7131 05:52:44.205159 CBT Training : PASS
7132 05:52:44.208756 Write leveling : NO K
7133 05:52:44.208834 RX DQS gating : PASS
7134 05:52:44.211686 RX DQ/DQS(RDDQC) : PASS
7135 05:52:44.215206 TX DQ/DQS : PASS
7136 05:52:44.215287 RX DATLAT : PASS
7137 05:52:44.218480 RX DQ/DQS(Engine): PASS
7138 05:52:44.221355 TX OE : NO K
7139 05:52:44.221447 All Pass.
7140 05:52:44.221531
7141 05:52:44.224705 DramC Write-DBI off
7142 05:52:44.224771 PER_BANK_REFRESH: Hybrid Mode
7143 05:52:44.228021 TX_TRACKING: ON
7144 05:52:44.238250 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7145 05:52:44.241256 [FAST_K] Save calibration result to emmc
7146 05:52:44.244780 dramc_set_vcore_voltage set vcore to 725000
7147 05:52:44.244857 Read voltage for 1600, 0
7148 05:52:44.247801 Vio18 = 0
7149 05:52:44.247870 Vcore = 725000
7150 05:52:44.247935 Vdram = 0
7151 05:52:44.251190 Vddq = 0
7152 05:52:44.251263 Vmddr = 0
7153 05:52:44.257837 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7154 05:52:44.261107 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7155 05:52:44.264659 MEM_TYPE=3, freq_sel=13
7156 05:52:44.267554 sv_algorithm_assistance_LP4_3733
7157 05:52:44.271027 ============ PULL DRAM RESETB DOWN ============
7158 05:52:44.274615 ========== PULL DRAM RESETB DOWN end =========
7159 05:52:44.281228 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7160 05:52:44.284232 ===================================
7161 05:52:44.284308 LPDDR4 DRAM CONFIGURATION
7162 05:52:44.287818 ===================================
7163 05:52:44.291281 EX_ROW_EN[0] = 0x0
7164 05:52:44.294070 EX_ROW_EN[1] = 0x0
7165 05:52:44.294149 LP4Y_EN = 0x0
7166 05:52:44.297421 WORK_FSP = 0x1
7167 05:52:44.297517 WL = 0x5
7168 05:52:44.300774 RL = 0x5
7169 05:52:44.300843 BL = 0x2
7170 05:52:44.304274 RPST = 0x0
7171 05:52:44.304347 RD_PRE = 0x0
7172 05:52:44.307680 WR_PRE = 0x1
7173 05:52:44.307748 WR_PST = 0x1
7174 05:52:44.310636 DBI_WR = 0x0
7175 05:52:44.310751 DBI_RD = 0x0
7176 05:52:44.314195 OTF = 0x1
7177 05:52:44.317775 ===================================
7178 05:52:44.321122 ===================================
7179 05:52:44.321195 ANA top config
7180 05:52:44.324514 ===================================
7181 05:52:44.327416 DLL_ASYNC_EN = 0
7182 05:52:44.331002 ALL_SLAVE_EN = 0
7183 05:52:44.331077 NEW_RANK_MODE = 1
7184 05:52:44.334265 DLL_IDLE_MODE = 1
7185 05:52:44.337593 LP45_APHY_COMB_EN = 1
7186 05:52:44.340889 TX_ODT_DIS = 0
7187 05:52:44.343800 NEW_8X_MODE = 1
7188 05:52:44.347421 ===================================
7189 05:52:44.351068 ===================================
7190 05:52:44.351138 data_rate = 3200
7191 05:52:44.354033 CKR = 1
7192 05:52:44.357418 DQ_P2S_RATIO = 8
7193 05:52:44.360536 ===================================
7194 05:52:44.364058 CA_P2S_RATIO = 8
7195 05:52:44.367595 DQ_CA_OPEN = 0
7196 05:52:44.370501 DQ_SEMI_OPEN = 0
7197 05:52:44.370581 CA_SEMI_OPEN = 0
7198 05:52:44.373994 CA_FULL_RATE = 0
7199 05:52:44.376991 DQ_CKDIV4_EN = 0
7200 05:52:44.380527 CA_CKDIV4_EN = 0
7201 05:52:44.383645 CA_PREDIV_EN = 0
7202 05:52:44.387210 PH8_DLY = 12
7203 05:52:44.387278 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7204 05:52:44.390295 DQ_AAMCK_DIV = 4
7205 05:52:44.393862 CA_AAMCK_DIV = 4
7206 05:52:44.396881 CA_ADMCK_DIV = 4
7207 05:52:44.400353 DQ_TRACK_CA_EN = 0
7208 05:52:44.403862 CA_PICK = 1600
7209 05:52:44.407124 CA_MCKIO = 1600
7210 05:52:44.407200 MCKIO_SEMI = 0
7211 05:52:44.410429 PLL_FREQ = 3068
7212 05:52:44.413736 DQ_UI_PI_RATIO = 32
7213 05:52:44.416663 CA_UI_PI_RATIO = 0
7214 05:52:44.420381 ===================================
7215 05:52:44.423811 ===================================
7216 05:52:44.426775 memory_type:LPDDR4
7217 05:52:44.426851 GP_NUM : 10
7218 05:52:44.430340 SRAM_EN : 1
7219 05:52:44.433321 MD32_EN : 0
7220 05:52:44.436886 ===================================
7221 05:52:44.436964 [ANA_INIT] >>>>>>>>>>>>>>
7222 05:52:44.440348 <<<<<< [CONFIGURE PHASE]: ANA_TX
7223 05:52:44.443218 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7224 05:52:44.446592 ===================================
7225 05:52:44.449817 data_rate = 3200,PCW = 0X7600
7226 05:52:44.453708 ===================================
7227 05:52:44.456568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7228 05:52:44.463311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7229 05:52:44.467016 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7230 05:52:44.473491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7231 05:52:44.476454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7232 05:52:44.480062 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7233 05:52:44.480144 [ANA_INIT] flow start
7234 05:52:44.483667 [ANA_INIT] PLL >>>>>>>>
7235 05:52:44.486627 [ANA_INIT] PLL <<<<<<<<
7236 05:52:44.490186 [ANA_INIT] MIDPI >>>>>>>>
7237 05:52:44.490259 [ANA_INIT] MIDPI <<<<<<<<
7238 05:52:44.493243 [ANA_INIT] DLL >>>>>>>>
7239 05:52:44.496735 [ANA_INIT] DLL <<<<<<<<
7240 05:52:44.496811 [ANA_INIT] flow end
7241 05:52:44.499686 ============ LP4 DIFF to SE enter ============
7242 05:52:44.506779 ============ LP4 DIFF to SE exit ============
7243 05:52:44.506858 [ANA_INIT] <<<<<<<<<<<<<
7244 05:52:44.509810 [Flow] Enable top DCM control >>>>>
7245 05:52:44.513170 [Flow] Enable top DCM control <<<<<
7246 05:52:44.516573 Enable DLL master slave shuffle
7247 05:52:44.523270 ==============================================================
7248 05:52:44.523348 Gating Mode config
7249 05:52:44.529541 ==============================================================
7250 05:52:44.532996 Config description:
7251 05:52:44.543022 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7252 05:52:44.549640 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7253 05:52:44.552609 SELPH_MODE 0: By rank 1: By Phase
7254 05:52:44.559485 ==============================================================
7255 05:52:44.562740 GAT_TRACK_EN = 1
7256 05:52:44.566183 RX_GATING_MODE = 2
7257 05:52:44.569273 RX_GATING_TRACK_MODE = 2
7258 05:52:44.569352 SELPH_MODE = 1
7259 05:52:44.572742 PICG_EARLY_EN = 1
7260 05:52:44.576257 VALID_LAT_VALUE = 1
7261 05:52:44.582663 ==============================================================
7262 05:52:44.586190 Enter into Gating configuration >>>>
7263 05:52:44.589191 Exit from Gating configuration <<<<
7264 05:52:44.592287 Enter into DVFS_PRE_config >>>>>
7265 05:52:44.602465 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7266 05:52:44.606033 Exit from DVFS_PRE_config <<<<<
7267 05:52:44.608964 Enter into PICG configuration >>>>
7268 05:52:44.612606 Exit from PICG configuration <<<<
7269 05:52:44.615540 [RX_INPUT] configuration >>>>>
7270 05:52:44.619002 [RX_INPUT] configuration <<<<<
7271 05:52:44.622465 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7272 05:52:44.628705 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7273 05:52:44.635837 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7274 05:52:44.642484 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7275 05:52:44.648747 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7276 05:52:44.652298 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7277 05:52:44.658858 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7278 05:52:44.662448 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7279 05:52:44.665278 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7280 05:52:44.668573 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7281 05:52:44.675200 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7282 05:52:44.678421 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7283 05:52:44.682182 ===================================
7284 05:52:44.685027 LPDDR4 DRAM CONFIGURATION
7285 05:52:44.688581 ===================================
7286 05:52:44.688703 EX_ROW_EN[0] = 0x0
7287 05:52:44.691537 EX_ROW_EN[1] = 0x0
7288 05:52:44.691617 LP4Y_EN = 0x0
7289 05:52:44.695080 WORK_FSP = 0x1
7290 05:52:44.695155 WL = 0x5
7291 05:52:44.698673 RL = 0x5
7292 05:52:44.698752 BL = 0x2
7293 05:52:44.701649 RPST = 0x0
7294 05:52:44.701723 RD_PRE = 0x0
7295 05:52:44.705165 WR_PRE = 0x1
7296 05:52:44.705265 WR_PST = 0x1
7297 05:52:44.708074 DBI_WR = 0x0
7298 05:52:44.711651 DBI_RD = 0x0
7299 05:52:44.711726 OTF = 0x1
7300 05:52:44.715231 ===================================
7301 05:52:44.718219 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7302 05:52:44.721892 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7303 05:52:44.727875 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7304 05:52:44.731187 ===================================
7305 05:52:44.734767 LPDDR4 DRAM CONFIGURATION
7306 05:52:44.738174 ===================================
7307 05:52:44.738253 EX_ROW_EN[0] = 0x10
7308 05:52:44.741675 EX_ROW_EN[1] = 0x0
7309 05:52:44.741744 LP4Y_EN = 0x0
7310 05:52:44.744898 WORK_FSP = 0x1
7311 05:52:44.744971 WL = 0x5
7312 05:52:44.748318 RL = 0x5
7313 05:52:44.748390 BL = 0x2
7314 05:52:44.751240 RPST = 0x0
7315 05:52:44.751313 RD_PRE = 0x0
7316 05:52:44.754623 WR_PRE = 0x1
7317 05:52:44.754696 WR_PST = 0x1
7318 05:52:44.758117 DBI_WR = 0x0
7319 05:52:44.761091 DBI_RD = 0x0
7320 05:52:44.761186 OTF = 0x1
7321 05:52:44.764726 ===================================
7322 05:52:44.771088 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7323 05:52:44.771169 ==
7324 05:52:44.774449 Dram Type= 6, Freq= 0, CH_0, rank 0
7325 05:52:44.778056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7326 05:52:44.778129 ==
7327 05:52:44.780991 [Duty_Offset_Calibration]
7328 05:52:44.781060 B0:2 B1:0 CA:3
7329 05:52:44.784448
7330 05:52:44.787706 [DutyScan_Calibration_Flow] k_type=0
7331 05:52:44.795882
7332 05:52:44.796024 ==CLK 0==
7333 05:52:44.798899 Final CLK duty delay cell = 0
7334 05:52:44.802497 [0] MAX Duty = 5031%(X100), DQS PI = 12
7335 05:52:44.806043 [0] MIN Duty = 4907%(X100), DQS PI = 4
7336 05:52:44.806115 [0] AVG Duty = 4969%(X100)
7337 05:52:44.809025
7338 05:52:44.812089 CH0 CLK Duty spec in!! Max-Min= 124%
7339 05:52:44.815613 [DutyScan_Calibration_Flow] ====Done====
7340 05:52:44.815685
7341 05:52:44.818574 [DutyScan_Calibration_Flow] k_type=1
7342 05:52:44.835959
7343 05:52:44.836043 ==DQS 0 ==
7344 05:52:44.839328 Final DQS duty delay cell = 0
7345 05:52:44.842377 [0] MAX Duty = 5094%(X100), DQS PI = 28
7346 05:52:44.845849 [0] MIN Duty = 4875%(X100), DQS PI = 50
7347 05:52:44.845921 [0] AVG Duty = 4984%(X100)
7348 05:52:44.848791
7349 05:52:44.848864 ==DQS 1 ==
7350 05:52:44.852121 Final DQS duty delay cell = 0
7351 05:52:44.855305 [0] MAX Duty = 5156%(X100), DQS PI = 32
7352 05:52:44.859027 [0] MIN Duty = 5062%(X100), DQS PI = 0
7353 05:52:44.862056 [0] AVG Duty = 5109%(X100)
7354 05:52:44.862131
7355 05:52:44.865691 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7356 05:52:44.865801
7357 05:52:44.868669 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7358 05:52:44.872177 [DutyScan_Calibration_Flow] ====Done====
7359 05:52:44.872248
7360 05:52:44.875419 [DutyScan_Calibration_Flow] k_type=3
7361 05:52:44.893810
7362 05:52:44.893892 ==DQM 0 ==
7363 05:52:44.896834 Final DQM duty delay cell = 0
7364 05:52:44.900337 [0] MAX Duty = 5156%(X100), DQS PI = 30
7365 05:52:44.903581 [0] MIN Duty = 4875%(X100), DQS PI = 0
7366 05:52:44.906911 [0] AVG Duty = 5015%(X100)
7367 05:52:44.906986
7368 05:52:44.907047 ==DQM 1 ==
7369 05:52:44.910446 Final DQM duty delay cell = 4
7370 05:52:44.913348 [4] MAX Duty = 5187%(X100), DQS PI = 60
7371 05:52:44.916952 [4] MIN Duty = 5031%(X100), DQS PI = 16
7372 05:52:44.920003 [4] AVG Duty = 5109%(X100)
7373 05:52:44.920076
7374 05:52:44.923525 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7375 05:52:44.923598
7376 05:52:44.926461 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7377 05:52:44.930127 [DutyScan_Calibration_Flow] ====Done====
7378 05:52:44.930198
7379 05:52:44.933032 [DutyScan_Calibration_Flow] k_type=2
7380 05:52:44.950104
7381 05:52:44.950184 ==DQ 0 ==
7382 05:52:44.953611 Final DQ duty delay cell = -4
7383 05:52:44.956510 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7384 05:52:44.960071 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7385 05:52:44.963338 [-4] AVG Duty = 4938%(X100)
7386 05:52:44.963408
7387 05:52:44.963468 ==DQ 1 ==
7388 05:52:44.966611 Final DQ duty delay cell = 0
7389 05:52:44.969566 [0] MAX Duty = 5156%(X100), DQS PI = 58
7390 05:52:44.972828 [0] MIN Duty = 5000%(X100), DQS PI = 16
7391 05:52:44.976321 [0] AVG Duty = 5078%(X100)
7392 05:52:44.976394
7393 05:52:44.979773 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7394 05:52:44.979843
7395 05:52:44.982808 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7396 05:52:44.986328 [DutyScan_Calibration_Flow] ====Done====
7397 05:52:44.986399 ==
7398 05:52:44.989363 Dram Type= 6, Freq= 0, CH_1, rank 0
7399 05:52:44.993064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7400 05:52:44.993137 ==
7401 05:52:44.996020 [Duty_Offset_Calibration]
7402 05:52:44.996093 B0:1 B1:-2 CA:1
7403 05:52:44.996159
7404 05:52:44.999555 [DutyScan_Calibration_Flow] k_type=0
7405 05:52:45.010507
7406 05:52:45.010585 ==CLK 0==
7407 05:52:45.013978 Final CLK duty delay cell = 0
7408 05:52:45.017458 [0] MAX Duty = 5062%(X100), DQS PI = 22
7409 05:52:45.020494 [0] MIN Duty = 4813%(X100), DQS PI = 60
7410 05:52:45.024097 [0] AVG Duty = 4937%(X100)
7411 05:52:45.024202
7412 05:52:45.027069 CH1 CLK Duty spec in!! Max-Min= 249%
7413 05:52:45.030578 [DutyScan_Calibration_Flow] ====Done====
7414 05:52:45.030652
7415 05:52:45.033594 [DutyScan_Calibration_Flow] k_type=1
7416 05:52:45.050535
7417 05:52:45.050612 ==DQS 0 ==
7418 05:52:45.053434 Final DQS duty delay cell = 0
7419 05:52:45.057254 [0] MAX Duty = 5187%(X100), DQS PI = 22
7420 05:52:45.060286 [0] MIN Duty = 5031%(X100), DQS PI = 54
7421 05:52:45.063904 [0] AVG Duty = 5109%(X100)
7422 05:52:45.063980
7423 05:52:45.064043 ==DQS 1 ==
7424 05:52:45.066905 Final DQS duty delay cell = 0
7425 05:52:45.070411 [0] MAX Duty = 5093%(X100), DQS PI = 62
7426 05:52:45.073399 [0] MIN Duty = 4844%(X100), DQS PI = 24
7427 05:52:45.076594 [0] AVG Duty = 4968%(X100)
7428 05:52:45.076668
7429 05:52:45.080198 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7430 05:52:45.080269
7431 05:52:45.083179 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7432 05:52:45.086747 [DutyScan_Calibration_Flow] ====Done====
7433 05:52:45.086816
7434 05:52:45.089859 [DutyScan_Calibration_Flow] k_type=3
7435 05:52:45.107389
7436 05:52:45.107468 ==DQM 0 ==
7437 05:52:45.110428 Final DQM duty delay cell = 0
7438 05:52:45.114044 [0] MAX Duty = 5031%(X100), DQS PI = 24
7439 05:52:45.116930 [0] MIN Duty = 4813%(X100), DQS PI = 54
7440 05:52:45.120334 [0] AVG Duty = 4922%(X100)
7441 05:52:45.120408
7442 05:52:45.120476 ==DQM 1 ==
7443 05:52:45.123772 Final DQM duty delay cell = 0
7444 05:52:45.127218 [0] MAX Duty = 5062%(X100), DQS PI = 34
7445 05:52:45.130195 [0] MIN Duty = 4875%(X100), DQS PI = 26
7446 05:52:45.133700 [0] AVG Duty = 4968%(X100)
7447 05:52:45.133794
7448 05:52:45.137186 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7449 05:52:45.137256
7450 05:52:45.140120 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7451 05:52:45.143602 [DutyScan_Calibration_Flow] ====Done====
7452 05:52:45.143670
7453 05:52:45.146661 [DutyScan_Calibration_Flow] k_type=2
7454 05:52:45.164061
7455 05:52:45.164133 ==DQ 0 ==
7456 05:52:45.167384 Final DQ duty delay cell = 0
7457 05:52:45.170811 [0] MAX Duty = 5093%(X100), DQS PI = 22
7458 05:52:45.174331 [0] MIN Duty = 4907%(X100), DQS PI = 60
7459 05:52:45.174402 [0] AVG Duty = 5000%(X100)
7460 05:52:45.177306
7461 05:52:45.177398 ==DQ 1 ==
7462 05:52:45.180949 Final DQ duty delay cell = 0
7463 05:52:45.183980 [0] MAX Duty = 5125%(X100), DQS PI = 34
7464 05:52:45.187355 [0] MIN Duty = 4969%(X100), DQS PI = 24
7465 05:52:45.187449 [0] AVG Duty = 5047%(X100)
7466 05:52:45.190554
7467 05:52:45.193786 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7468 05:52:45.193863
7469 05:52:45.197467 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7470 05:52:45.200614 [DutyScan_Calibration_Flow] ====Done====
7471 05:52:45.204071 nWR fixed to 30
7472 05:52:45.204146 [ModeRegInit_LP4] CH0 RK0
7473 05:52:45.207146 [ModeRegInit_LP4] CH0 RK1
7474 05:52:45.210457 [ModeRegInit_LP4] CH1 RK0
7475 05:52:45.213949 [ModeRegInit_LP4] CH1 RK1
7476 05:52:45.214021 match AC timing 5
7477 05:52:45.220606 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7478 05:52:45.223979 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7479 05:52:45.226938 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7480 05:52:45.233705 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7481 05:52:45.237275 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7482 05:52:45.237354 [MiockJmeterHQA]
7483 05:52:45.237432
7484 05:52:45.240302 [DramcMiockJmeter] u1RxGatingPI = 0
7485 05:52:45.243294 0 : 4258, 4029
7486 05:52:45.243362 4 : 4252, 4027
7487 05:52:45.247025 8 : 4253, 4026
7488 05:52:45.247097 12 : 4252, 4027
7489 05:52:45.247158 16 : 4363, 4137
7490 05:52:45.249987 20 : 4255, 4029
7491 05:52:45.250053 24 : 4253, 4026
7492 05:52:45.253485 28 : 4253, 4026
7493 05:52:45.253557 32 : 4252, 4027
7494 05:52:45.256492 36 : 4361, 4137
7495 05:52:45.256564 40 : 4252, 4027
7496 05:52:45.260154 44 : 4360, 4137
7497 05:52:45.260220 48 : 4250, 4027
7498 05:52:45.260284 52 : 4250, 4027
7499 05:52:45.263158 56 : 4250, 4026
7500 05:52:45.263226 60 : 4360, 4138
7501 05:52:45.266681 64 : 4250, 4027
7502 05:52:45.266762 68 : 4361, 4137
7503 05:52:45.269600 72 : 4253, 4027
7504 05:52:45.269673 76 : 4250, 4026
7505 05:52:45.273070 80 : 4250, 4027
7506 05:52:45.273174 84 : 4255, 4031
7507 05:52:45.273268 88 : 4361, 4137
7508 05:52:45.276952 92 : 4250, 4027
7509 05:52:45.277053 96 : 4360, 4137
7510 05:52:45.279772 100 : 4250, 4027
7511 05:52:45.279851 104 : 4250, 3745
7512 05:52:45.283292 108 : 4250, 4
7513 05:52:45.283361 112 : 4360, 0
7514 05:52:45.283420 116 : 4250, 0
7515 05:52:45.286830 120 : 4250, 0
7516 05:52:45.286897 124 : 4250, 0
7517 05:52:45.289782 128 : 4361, 0
7518 05:52:45.289879 132 : 4360, 0
7519 05:52:45.289975 136 : 4250, 0
7520 05:52:45.293288 140 : 4250, 0
7521 05:52:45.293387 144 : 4250, 0
7522 05:52:45.296653 148 : 4250, 0
7523 05:52:45.296762 152 : 4249, 0
7524 05:52:45.296831 156 : 4250, 0
7525 05:52:45.299583 160 : 4250, 0
7526 05:52:45.299664 164 : 4360, 0
7527 05:52:45.303186 168 : 4361, 0
7528 05:52:45.303255 172 : 4247, 0
7529 05:52:45.303314 176 : 4250, 0
7530 05:52:45.306570 180 : 4361, 0
7531 05:52:45.306637 184 : 4360, 0
7532 05:52:45.306696 188 : 4250, 0
7533 05:52:45.309546 192 : 4250, 0
7534 05:52:45.309645 196 : 4250, 0
7535 05:52:45.312690 200 : 4250, 0
7536 05:52:45.312771 204 : 4250, 0
7537 05:52:45.312840 208 : 4250, 0
7538 05:52:45.316381 212 : 4250, 0
7539 05:52:45.316456 216 : 4360, 0
7540 05:52:45.319723 220 : 4361, 0
7541 05:52:45.319795 224 : 4247, 0
7542 05:52:45.319856 228 : 4250, 0
7543 05:52:45.322886 232 : 4360, 1
7544 05:52:45.322962 236 : 4360, 1173
7545 05:52:45.326213 240 : 4361, 4137
7546 05:52:45.326292 244 : 4250, 4026
7547 05:52:45.329736 248 : 4250, 4027
7548 05:52:45.329844 252 : 4252, 4030
7549 05:52:45.332668 256 : 4250, 4026
7550 05:52:45.332739 260 : 4250, 4027
7551 05:52:45.336066 264 : 4250, 4027
7552 05:52:45.336139 268 : 4250, 4027
7553 05:52:45.336201 272 : 4250, 4027
7554 05:52:45.339290 276 : 4361, 4137
7555 05:52:45.339370 280 : 4360, 4138
7556 05:52:45.342752 284 : 4247, 4024
7557 05:52:45.342827 288 : 4360, 4137
7558 05:52:45.346336 292 : 4361, 4137
7559 05:52:45.346427 296 : 4250, 4027
7560 05:52:45.349275 300 : 4249, 4027
7561 05:52:45.349347 304 : 4249, 4027
7562 05:52:45.352802 308 : 4250, 4026
7563 05:52:45.352876 312 : 4250, 4027
7564 05:52:45.355823 316 : 4249, 4027
7565 05:52:45.355901 320 : 4250, 4027
7566 05:52:45.359429 324 : 4250, 4026
7567 05:52:45.359529 328 : 4361, 4137
7568 05:52:45.362503 332 : 4360, 4138
7569 05:52:45.362574 336 : 4247, 4024
7570 05:52:45.362638 340 : 4360, 4138
7571 05:52:45.366048 344 : 4361, 4137
7572 05:52:45.366126 348 : 4250, 4027
7573 05:52:45.368984 352 : 4250, 4015
7574 05:52:45.369087 356 : 4250, 3038
7575 05:52:45.372520 360 : 4250, 2
7576 05:52:45.372595
7577 05:52:45.372659 MIOCK jitter meter ch=0
7578 05:52:45.372717
7579 05:52:45.375500 1T = (360-108) = 252 dly cells
7580 05:52:45.382415 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7581 05:52:45.382494 ==
7582 05:52:45.385284 Dram Type= 6, Freq= 0, CH_0, rank 0
7583 05:52:45.389079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 05:52:45.392385 ==
7585 05:52:45.395357 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7586 05:52:45.398918 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7587 05:52:45.405075 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7588 05:52:45.408665 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7589 05:52:45.419466 [CA 0] Center 43 (13~74) winsize 62
7590 05:52:45.422386 [CA 1] Center 43 (13~74) winsize 62
7591 05:52:45.425835 [CA 2] Center 39 (10~68) winsize 59
7592 05:52:45.428872 [CA 3] Center 39 (10~68) winsize 59
7593 05:52:45.432337 [CA 4] Center 37 (8~66) winsize 59
7594 05:52:45.435702 [CA 5] Center 36 (7~66) winsize 60
7595 05:52:45.435771
7596 05:52:45.439202 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7597 05:52:45.439277
7598 05:52:45.445893 [CATrainingPosCal] consider 1 rank data
7599 05:52:45.445975 u2DelayCellTimex100 = 258/100 ps
7600 05:52:45.452297 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7601 05:52:45.455803 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7602 05:52:45.458790 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7603 05:52:45.462434 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7604 05:52:45.465537 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7605 05:52:45.469054 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7606 05:52:45.469155
7607 05:52:45.472060 CA PerBit enable=1, Macro0, CA PI delay=36
7608 05:52:45.472129
7609 05:52:45.475774 [CBTSetCACLKResult] CA Dly = 36
7610 05:52:45.478771 CS Dly: 11 (0~42)
7611 05:52:45.481928 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7612 05:52:45.485024 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7613 05:52:45.485096 ==
7614 05:52:45.488781 Dram Type= 6, Freq= 0, CH_0, rank 1
7615 05:52:45.495231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 05:52:45.495320 ==
7617 05:52:45.498706 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7618 05:52:45.505427 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7619 05:52:45.508378 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7620 05:52:45.514848 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7621 05:52:45.523090 [CA 0] Center 44 (14~75) winsize 62
7622 05:52:45.526548 [CA 1] Center 44 (13~75) winsize 63
7623 05:52:45.529726 [CA 2] Center 39 (10~69) winsize 60
7624 05:52:45.533196 [CA 3] Center 39 (10~69) winsize 60
7625 05:52:45.536197 [CA 4] Center 37 (8~67) winsize 60
7626 05:52:45.539543 [CA 5] Center 37 (7~67) winsize 61
7627 05:52:45.539639
7628 05:52:45.542934 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7629 05:52:45.543006
7630 05:52:45.549776 [CATrainingPosCal] consider 2 rank data
7631 05:52:45.549850 u2DelayCellTimex100 = 258/100 ps
7632 05:52:45.556216 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7633 05:52:45.559600 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7634 05:52:45.562627 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7635 05:52:45.565948 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7636 05:52:45.569437 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7637 05:52:45.573029 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7638 05:52:45.573110
7639 05:52:45.575965 CA PerBit enable=1, Macro0, CA PI delay=36
7640 05:52:45.576035
7641 05:52:45.579560 [CBTSetCACLKResult] CA Dly = 36
7642 05:52:45.582601 CS Dly: 11 (0~42)
7643 05:52:45.586159 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7644 05:52:45.589079 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7645 05:52:45.589149
7646 05:52:45.592574 ----->DramcWriteLeveling(PI) begin...
7647 05:52:45.592650 ==
7648 05:52:45.596247 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 05:52:45.602823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 05:52:45.602897 ==
7651 05:52:45.605847 Write leveling (Byte 0): 35 => 35
7652 05:52:45.609127 Write leveling (Byte 1): 28 => 28
7653 05:52:45.612565 DramcWriteLeveling(PI) end<-----
7654 05:52:45.612634
7655 05:52:45.612695 ==
7656 05:52:45.615705 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 05:52:45.618954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 05:52:45.619026 ==
7659 05:52:45.622228 [Gating] SW mode calibration
7660 05:52:45.629047 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7661 05:52:45.635682 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7662 05:52:45.638705 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7663 05:52:45.642266 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7664 05:52:45.649184 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 05:52:45.652108 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 05:52:45.655671 1 4 16 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7667 05:52:45.659085 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7668 05:52:45.665439 1 4 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7669 05:52:45.668569 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7670 05:52:45.672160 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7671 05:52:45.678584 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7672 05:52:45.681814 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7673 05:52:45.685603 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7674 05:52:45.692082 1 5 16 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
7675 05:52:45.694984 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7676 05:52:45.698517 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7677 05:52:45.705314 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7678 05:52:45.708325 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7679 05:52:45.711916 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7680 05:52:45.718461 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7681 05:52:45.721914 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7682 05:52:45.725147 1 6 16 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7683 05:52:45.731616 1 6 20 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7684 05:52:45.735038 1 6 24 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
7685 05:52:45.738171 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7686 05:52:45.745230 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7687 05:52:45.748112 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7688 05:52:45.751822 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7689 05:52:45.758226 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7690 05:52:45.761303 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7691 05:52:45.764923 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7692 05:52:45.771302 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7693 05:52:45.774305 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7694 05:52:45.777849 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 05:52:45.784386 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 05:52:45.787607 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 05:52:45.790668 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 05:52:45.797636 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 05:52:45.800689 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 05:52:45.804374 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 05:52:45.810862 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 05:52:45.814310 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 05:52:45.817341 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 05:52:45.824435 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 05:52:45.827500 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 05:52:45.830546 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7707 05:52:45.837448 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7708 05:52:45.837539 Total UI for P1: 0, mck2ui 16
7709 05:52:45.843562 best dqsien dly found for B0: ( 1, 9, 16)
7710 05:52:45.847326 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7711 05:52:45.850396 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7712 05:52:45.853814 Total UI for P1: 0, mck2ui 16
7713 05:52:45.857333 best dqsien dly found for B1: ( 1, 9, 26)
7714 05:52:45.860347 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7715 05:52:45.863998 best DQS1 dly(MCK, UI, PI) = (1, 9, 26)
7716 05:52:45.864079
7717 05:52:45.870008 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7718 05:52:45.873534 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 26)
7719 05:52:45.876455 [Gating] SW calibration Done
7720 05:52:45.876535 ==
7721 05:52:45.880136 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 05:52:45.883155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 05:52:45.883237 ==
7724 05:52:45.883301 RX Vref Scan: 0
7725 05:52:45.886720
7726 05:52:45.886801 RX Vref 0 -> 0, step: 1
7727 05:52:45.886865
7728 05:52:45.890238 RX Delay 0 -> 252, step: 8
7729 05:52:45.893111 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7730 05:52:45.896395 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7731 05:52:45.903279 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7732 05:52:45.906433 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7733 05:52:45.909779 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7734 05:52:45.913258 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7735 05:52:45.916453 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7736 05:52:45.922700 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7737 05:52:45.926295 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7738 05:52:45.929768 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7739 05:52:45.932799 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7740 05:52:45.935827 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7741 05:52:45.942812 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7742 05:52:45.946136 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7743 05:52:45.949095 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7744 05:52:45.952503 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7745 05:52:45.952615 ==
7746 05:52:45.955848 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 05:52:45.962439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 05:52:45.962521 ==
7749 05:52:45.962585 DQS Delay:
7750 05:52:45.966039 DQS0 = 0, DQS1 = 0
7751 05:52:45.966119 DQM Delay:
7752 05:52:45.969082 DQM0 = 127, DQM1 = 124
7753 05:52:45.969164 DQ Delay:
7754 05:52:45.972675 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7755 05:52:45.975567 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7756 05:52:45.979157 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7757 05:52:45.982149 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7758 05:52:45.982230
7759 05:52:45.982333
7760 05:52:45.982392 ==
7761 05:52:45.985691 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 05:52:45.992167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 05:52:45.992248 ==
7764 05:52:45.992312
7765 05:52:45.992372
7766 05:52:45.992462 TX Vref Scan disable
7767 05:52:45.995697 == TX Byte 0 ==
7768 05:52:45.999185 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7769 05:52:46.005637 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7770 05:52:46.005718 == TX Byte 1 ==
7771 05:52:46.009276 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7772 05:52:46.015614 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7773 05:52:46.015695 ==
7774 05:52:46.019199 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 05:52:46.022145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 05:52:46.022226 ==
7777 05:52:46.035667
7778 05:52:46.038556 TX Vref early break, caculate TX vref
7779 05:52:46.042150 TX Vref=16, minBit 8, minWin=21, winSum=356
7780 05:52:46.045207 TX Vref=18, minBit 8, minWin=22, winSum=369
7781 05:52:46.048580 TX Vref=20, minBit 0, minWin=23, winSum=379
7782 05:52:46.052049 TX Vref=22, minBit 0, minWin=23, winSum=386
7783 05:52:46.055623 TX Vref=24, minBit 4, minWin=24, winSum=392
7784 05:52:46.061974 TX Vref=26, minBit 4, minWin=24, winSum=405
7785 05:52:46.065535 TX Vref=28, minBit 4, minWin=24, winSum=405
7786 05:52:46.068670 TX Vref=30, minBit 8, minWin=24, winSum=398
7787 05:52:46.071739 TX Vref=32, minBit 0, minWin=24, winSum=389
7788 05:52:46.075286 TX Vref=34, minBit 8, minWin=22, winSum=380
7789 05:52:46.081752 [TxChooseVref] Worse bit 4, Min win 24, Win sum 405, Final Vref 26
7790 05:52:46.081834
7791 05:52:46.085189 Final TX Range 0 Vref 26
7792 05:52:46.085270
7793 05:52:46.085334 ==
7794 05:52:46.088082 Dram Type= 6, Freq= 0, CH_0, rank 0
7795 05:52:46.091620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7796 05:52:46.091701 ==
7797 05:52:46.091765
7798 05:52:46.091824
7799 05:52:46.095129 TX Vref Scan disable
7800 05:52:46.101538 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7801 05:52:46.101632 == TX Byte 0 ==
7802 05:52:46.104890 u2DelayCellOfst[0]=15 cells (4 PI)
7803 05:52:46.107969 u2DelayCellOfst[1]=18 cells (5 PI)
7804 05:52:46.111576 u2DelayCellOfst[2]=11 cells (3 PI)
7805 05:52:46.114695 u2DelayCellOfst[3]=11 cells (3 PI)
7806 05:52:46.118055 u2DelayCellOfst[4]=11 cells (3 PI)
7807 05:52:46.121632 u2DelayCellOfst[5]=0 cells (0 PI)
7808 05:52:46.124496 u2DelayCellOfst[6]=22 cells (6 PI)
7809 05:52:46.128020 u2DelayCellOfst[7]=22 cells (6 PI)
7810 05:52:46.131640 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7811 05:52:46.134934 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7812 05:52:46.137926 == TX Byte 1 ==
7813 05:52:46.141306 u2DelayCellOfst[8]=0 cells (0 PI)
7814 05:52:46.141387 u2DelayCellOfst[9]=0 cells (0 PI)
7815 05:52:46.144585 u2DelayCellOfst[10]=7 cells (2 PI)
7816 05:52:46.147858 u2DelayCellOfst[11]=7 cells (2 PI)
7817 05:52:46.150866 u2DelayCellOfst[12]=11 cells (3 PI)
7818 05:52:46.154306 u2DelayCellOfst[13]=11 cells (3 PI)
7819 05:52:46.157896 u2DelayCellOfst[14]=15 cells (4 PI)
7820 05:52:46.161329 u2DelayCellOfst[15]=11 cells (3 PI)
7821 05:52:46.167870 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7822 05:52:46.170846 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7823 05:52:46.170928 DramC Write-DBI on
7824 05:52:46.170993 ==
7825 05:52:46.174334 Dram Type= 6, Freq= 0, CH_0, rank 0
7826 05:52:46.180893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7827 05:52:46.180974 ==
7828 05:52:46.181041
7829 05:52:46.181131
7830 05:52:46.181218 TX Vref Scan disable
7831 05:52:46.184943 == TX Byte 0 ==
7832 05:52:46.188311 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7833 05:52:46.191723 == TX Byte 1 ==
7834 05:52:46.194799 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7835 05:52:46.198435 DramC Write-DBI off
7836 05:52:46.198515
7837 05:52:46.198578 [DATLAT]
7838 05:52:46.198638 Freq=1600, CH0 RK0
7839 05:52:46.198695
7840 05:52:46.201505 DATLAT Default: 0xf
7841 05:52:46.201600 0, 0xFFFF, sum = 0
7842 05:52:46.205071 1, 0xFFFF, sum = 0
7843 05:52:46.208371 2, 0xFFFF, sum = 0
7844 05:52:46.208455 3, 0xFFFF, sum = 0
7845 05:52:46.211192 4, 0xFFFF, sum = 0
7846 05:52:46.211275 5, 0xFFFF, sum = 0
7847 05:52:46.214691 6, 0xFFFF, sum = 0
7848 05:52:46.214772 7, 0xFFFF, sum = 0
7849 05:52:46.218273 8, 0xFFFF, sum = 0
7850 05:52:46.218354 9, 0xFFFF, sum = 0
7851 05:52:46.221801 10, 0xFFFF, sum = 0
7852 05:52:46.221883 11, 0xFFFF, sum = 0
7853 05:52:46.224586 12, 0xFFFF, sum = 0
7854 05:52:46.224672 13, 0xEFFF, sum = 0
7855 05:52:46.228182 14, 0x0, sum = 1
7856 05:52:46.228264 15, 0x0, sum = 2
7857 05:52:46.231205 16, 0x0, sum = 3
7858 05:52:46.231287 17, 0x0, sum = 4
7859 05:52:46.234841 best_step = 15
7860 05:52:46.234921
7861 05:52:46.234986 ==
7862 05:52:46.237701 Dram Type= 6, Freq= 0, CH_0, rank 0
7863 05:52:46.241351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7864 05:52:46.241464 ==
7865 05:52:46.244637 RX Vref Scan: 1
7866 05:52:46.244717
7867 05:52:46.244780 Set Vref Range= 24 -> 127
7868 05:52:46.244847
7869 05:52:46.247624 RX Vref 24 -> 127, step: 1
7870 05:52:46.247730
7871 05:52:46.251218 RX Delay 11 -> 252, step: 4
7872 05:52:46.251299
7873 05:52:46.254646 Set Vref, RX VrefLevel [Byte0]: 24
7874 05:52:46.258029 [Byte1]: 24
7875 05:52:46.258109
7876 05:52:46.261326 Set Vref, RX VrefLevel [Byte0]: 25
7877 05:52:46.264445 [Byte1]: 25
7878 05:52:46.267941
7879 05:52:46.268048 Set Vref, RX VrefLevel [Byte0]: 26
7880 05:52:46.270867 [Byte1]: 26
7881 05:52:46.275317
7882 05:52:46.275459 Set Vref, RX VrefLevel [Byte0]: 27
7883 05:52:46.278946 [Byte1]: 27
7884 05:52:46.283034
7885 05:52:46.283114 Set Vref, RX VrefLevel [Byte0]: 28
7886 05:52:46.286527 [Byte1]: 28
7887 05:52:46.290585
7888 05:52:46.290682 Set Vref, RX VrefLevel [Byte0]: 29
7889 05:52:46.293988 [Byte1]: 29
7890 05:52:46.298204
7891 05:52:46.298301 Set Vref, RX VrefLevel [Byte0]: 30
7892 05:52:46.301279 [Byte1]: 30
7893 05:52:46.306048
7894 05:52:46.306145 Set Vref, RX VrefLevel [Byte0]: 31
7895 05:52:46.309062 [Byte1]: 31
7896 05:52:46.313604
7897 05:52:46.313679 Set Vref, RX VrefLevel [Byte0]: 32
7898 05:52:46.316547 [Byte1]: 32
7899 05:52:46.321257
7900 05:52:46.321330 Set Vref, RX VrefLevel [Byte0]: 33
7901 05:52:46.324199 [Byte1]: 33
7902 05:52:46.328808
7903 05:52:46.328880 Set Vref, RX VrefLevel [Byte0]: 34
7904 05:52:46.331835 [Byte1]: 34
7905 05:52:46.336493
7906 05:52:46.336594 Set Vref, RX VrefLevel [Byte0]: 35
7907 05:52:46.339442 [Byte1]: 35
7908 05:52:46.343684
7909 05:52:46.343756 Set Vref, RX VrefLevel [Byte0]: 36
7910 05:52:46.347301 [Byte1]: 36
7911 05:52:46.351192
7912 05:52:46.351294 Set Vref, RX VrefLevel [Byte0]: 37
7913 05:52:46.354845 [Byte1]: 37
7914 05:52:46.359180
7915 05:52:46.359278 Set Vref, RX VrefLevel [Byte0]: 38
7916 05:52:46.362264 [Byte1]: 38
7917 05:52:46.366839
7918 05:52:46.366970 Set Vref, RX VrefLevel [Byte0]: 39
7919 05:52:46.370375 [Byte1]: 39
7920 05:52:46.374309
7921 05:52:46.374411 Set Vref, RX VrefLevel [Byte0]: 40
7922 05:52:46.377878 [Byte1]: 40
7923 05:52:46.381751
7924 05:52:46.381856 Set Vref, RX VrefLevel [Byte0]: 41
7925 05:52:46.385222 [Byte1]: 41
7926 05:52:46.389533
7927 05:52:46.389627 Set Vref, RX VrefLevel [Byte0]: 42
7928 05:52:46.392628 [Byte1]: 42
7929 05:52:46.396998
7930 05:52:46.397097 Set Vref, RX VrefLevel [Byte0]: 43
7931 05:52:46.400393 [Byte1]: 43
7932 05:52:46.404588
7933 05:52:46.404667 Set Vref, RX VrefLevel [Byte0]: 44
7934 05:52:46.407729 [Byte1]: 44
7935 05:52:46.412540
7936 05:52:46.412617 Set Vref, RX VrefLevel [Byte0]: 45
7937 05:52:46.415552 [Byte1]: 45
7938 05:52:46.419813
7939 05:52:46.419912 Set Vref, RX VrefLevel [Byte0]: 46
7940 05:52:46.423459 [Byte1]: 46
7941 05:52:46.427926
7942 05:52:46.428048 Set Vref, RX VrefLevel [Byte0]: 47
7943 05:52:46.433726 [Byte1]: 47
7944 05:52:46.433808
7945 05:52:46.437505 Set Vref, RX VrefLevel [Byte0]: 48
7946 05:52:46.440487 [Byte1]: 48
7947 05:52:46.440566
7948 05:52:46.444223 Set Vref, RX VrefLevel [Byte0]: 49
7949 05:52:46.447389 [Byte1]: 49
7950 05:52:46.450390
7951 05:52:46.450491 Set Vref, RX VrefLevel [Byte0]: 50
7952 05:52:46.454069 [Byte1]: 50
7953 05:52:46.458182
7954 05:52:46.458255 Set Vref, RX VrefLevel [Byte0]: 51
7955 05:52:46.461454 [Byte1]: 51
7956 05:52:46.465511
7957 05:52:46.465595 Set Vref, RX VrefLevel [Byte0]: 52
7958 05:52:46.469132 [Byte1]: 52
7959 05:52:46.473156
7960 05:52:46.473260 Set Vref, RX VrefLevel [Byte0]: 53
7961 05:52:46.476556 [Byte1]: 53
7962 05:52:46.480584
7963 05:52:46.480664 Set Vref, RX VrefLevel [Byte0]: 54
7964 05:52:46.484111 [Byte1]: 54
7965 05:52:46.488363
7966 05:52:46.488472 Set Vref, RX VrefLevel [Byte0]: 55
7967 05:52:46.491878 [Byte1]: 55
7968 05:52:46.496272
7969 05:52:46.496357 Set Vref, RX VrefLevel [Byte0]: 56
7970 05:52:46.499160 [Byte1]: 56
7971 05:52:46.503575
7972 05:52:46.503700 Set Vref, RX VrefLevel [Byte0]: 57
7973 05:52:46.507172 [Byte1]: 57
7974 05:52:46.511520
7975 05:52:46.511623 Set Vref, RX VrefLevel [Byte0]: 58
7976 05:52:46.514578 [Byte1]: 58
7977 05:52:46.518884
7978 05:52:46.518971 Set Vref, RX VrefLevel [Byte0]: 59
7979 05:52:46.522369 [Byte1]: 59
7980 05:52:46.526546
7981 05:52:46.526624 Set Vref, RX VrefLevel [Byte0]: 60
7982 05:52:46.529634 [Byte1]: 60
7983 05:52:46.534036
7984 05:52:46.534117 Set Vref, RX VrefLevel [Byte0]: 61
7985 05:52:46.537618 [Byte1]: 61
7986 05:52:46.541998
7987 05:52:46.542080 Set Vref, RX VrefLevel [Byte0]: 62
7988 05:52:46.545216 [Byte1]: 62
7989 05:52:46.549586
7990 05:52:46.549698 Set Vref, RX VrefLevel [Byte0]: 63
7991 05:52:46.552784 [Byte1]: 63
7992 05:52:46.556823
7993 05:52:46.556905 Set Vref, RX VrefLevel [Byte0]: 64
7994 05:52:46.560536 [Byte1]: 64
7995 05:52:46.564877
7996 05:52:46.564962 Set Vref, RX VrefLevel [Byte0]: 65
7997 05:52:46.567828 [Byte1]: 65
7998 05:52:46.572048
7999 05:52:46.572169 Set Vref, RX VrefLevel [Byte0]: 66
8000 05:52:46.575839 [Byte1]: 66
8001 05:52:46.580073
8002 05:52:46.580181 Set Vref, RX VrefLevel [Byte0]: 67
8003 05:52:46.582889 [Byte1]: 67
8004 05:52:46.587816
8005 05:52:46.587915 Set Vref, RX VrefLevel [Byte0]: 68
8006 05:52:46.590798 [Byte1]: 68
8007 05:52:46.595102
8008 05:52:46.595178 Set Vref, RX VrefLevel [Byte0]: 69
8009 05:52:46.598603 [Byte1]: 69
8010 05:52:46.602514
8011 05:52:46.602604 Set Vref, RX VrefLevel [Byte0]: 70
8012 05:52:46.606142 [Byte1]: 70
8013 05:52:46.610539
8014 05:52:46.610641 Set Vref, RX VrefLevel [Byte0]: 71
8015 05:52:46.613393 [Byte1]: 71
8016 05:52:46.617778
8017 05:52:46.617875 Set Vref, RX VrefLevel [Byte0]: 72
8018 05:52:46.621384 [Byte1]: 72
8019 05:52:46.625410
8020 05:52:46.625523 Set Vref, RX VrefLevel [Byte0]: 73
8021 05:52:46.629038 [Byte1]: 73
8022 05:52:46.633271
8023 05:52:46.633353 Set Vref, RX VrefLevel [Byte0]: 74
8024 05:52:46.636275 [Byte1]: 74
8025 05:52:46.641047
8026 05:52:46.641130 Set Vref, RX VrefLevel [Byte0]: 75
8027 05:52:46.643851 [Byte1]: 75
8028 05:52:46.648160
8029 05:52:46.648243 Final RX Vref Byte 0 = 63 to rank0
8030 05:52:46.651599 Final RX Vref Byte 1 = 58 to rank0
8031 05:52:46.655224 Final RX Vref Byte 0 = 63 to rank1
8032 05:52:46.658163 Final RX Vref Byte 1 = 58 to rank1==
8033 05:52:46.661804 Dram Type= 6, Freq= 0, CH_0, rank 0
8034 05:52:46.668512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8035 05:52:46.668596 ==
8036 05:52:46.668672 DQS Delay:
8037 05:52:46.668735 DQS0 = 0, DQS1 = 0
8038 05:52:46.671402 DQM Delay:
8039 05:52:46.671506 DQM0 = 126, DQM1 = 119
8040 05:52:46.674969 DQ Delay:
8041 05:52:46.678409 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8042 05:52:46.681735 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8043 05:52:46.685311 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8044 05:52:46.687979 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8045 05:52:46.688087
8046 05:52:46.688180
8047 05:52:46.688271
8048 05:52:46.691470 [DramC_TX_OE_Calibration] TA2
8049 05:52:46.694979 Original DQ_B0 (3 6) =30, OEN = 27
8050 05:52:46.698228 Original DQ_B1 (3 6) =30, OEN = 27
8051 05:52:46.701840 24, 0x0, End_B0=24 End_B1=24
8052 05:52:46.701918 25, 0x0, End_B0=25 End_B1=25
8053 05:52:46.704702 26, 0x0, End_B0=26 End_B1=26
8054 05:52:46.708215 27, 0x0, End_B0=27 End_B1=27
8055 05:52:46.711303 28, 0x0, End_B0=28 End_B1=28
8056 05:52:46.714895 29, 0x0, End_B0=29 End_B1=29
8057 05:52:46.714981 30, 0x0, End_B0=30 End_B1=30
8058 05:52:46.717860 31, 0x5151, End_B0=30 End_B1=30
8059 05:52:46.721272 Byte0 end_step=30 best_step=27
8060 05:52:46.724590 Byte1 end_step=30 best_step=27
8061 05:52:46.728074 Byte0 TX OE(2T, 0.5T) = (3, 3)
8062 05:52:46.731288 Byte1 TX OE(2T, 0.5T) = (3, 3)
8063 05:52:46.731387
8064 05:52:46.731483
8065 05:52:46.738035 [DQSOSCAuto] RK0, (LSB)MR18= 0x1010, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
8066 05:52:46.741124 CH0 RK0: MR19=303, MR18=1010
8067 05:52:46.747620 CH0_RK0: MR19=0x303, MR18=0x1010, DQSOSC=401, MR23=63, INC=22, DEC=15
8068 05:52:46.747720
8069 05:52:46.751331 ----->DramcWriteLeveling(PI) begin...
8070 05:52:46.751461 ==
8071 05:52:46.754295 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 05:52:46.758050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 05:52:46.758131 ==
8074 05:52:46.760840 Write leveling (Byte 0): 35 => 35
8075 05:52:46.764351 Write leveling (Byte 1): 27 => 27
8076 05:52:46.767376 DramcWriteLeveling(PI) end<-----
8077 05:52:46.767485
8078 05:52:46.767554 ==
8079 05:52:46.771020 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 05:52:46.774041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 05:52:46.774147 ==
8082 05:52:46.777181 [Gating] SW mode calibration
8083 05:52:46.784219 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8084 05:52:46.790549 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8085 05:52:46.793634 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 05:52:46.800332 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 05:52:46.803853 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 05:52:46.806929 1 4 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8089 05:52:46.813902 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8090 05:52:46.816938 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8091 05:52:46.820496 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8092 05:52:46.827235 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8093 05:52:46.830145 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8094 05:52:46.833577 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8095 05:52:46.840481 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8096 05:52:46.844008 1 5 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
8097 05:52:46.847105 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8098 05:52:46.853524 1 5 20 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
8099 05:52:46.857060 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8100 05:52:46.860157 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8101 05:52:46.866896 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8102 05:52:46.869893 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8103 05:52:46.873432 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8104 05:52:46.880066 1 6 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
8105 05:52:46.883546 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8106 05:52:46.886463 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8107 05:52:46.890051 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8108 05:52:46.896375 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 05:52:46.899824 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8110 05:52:46.903236 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8111 05:52:46.909684 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8112 05:52:46.913085 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8113 05:52:46.916707 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8114 05:52:46.923257 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 05:52:46.926169 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 05:52:46.929604 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 05:52:46.936074 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 05:52:46.939713 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 05:52:46.942736 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 05:52:46.949612 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 05:52:46.952975 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 05:52:46.956218 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 05:52:46.962972 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 05:52:46.965994 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 05:52:46.969072 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 05:52:46.975579 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 05:52:46.979222 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8128 05:52:46.982344 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8129 05:52:46.989015 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8130 05:52:46.992130 Total UI for P1: 0, mck2ui 16
8131 05:52:46.995831 best dqsien dly found for B0: ( 1, 9, 10)
8132 05:52:46.998885 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8133 05:52:47.002389 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8134 05:52:47.005809 Total UI for P1: 0, mck2ui 16
8135 05:52:47.009044 best dqsien dly found for B1: ( 1, 9, 18)
8136 05:52:47.012198 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8137 05:52:47.015463 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8138 05:52:47.015544
8139 05:52:47.022035 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8140 05:52:47.025383 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8141 05:52:47.028963 [Gating] SW calibration Done
8142 05:52:47.029076 ==
8143 05:52:47.032035 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 05:52:47.035514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 05:52:47.035628 ==
8146 05:52:47.035727 RX Vref Scan: 0
8147 05:52:47.038957
8148 05:52:47.039055 RX Vref 0 -> 0, step: 1
8149 05:52:47.039154
8150 05:52:47.041839 RX Delay 0 -> 252, step: 8
8151 05:52:47.045692 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8152 05:52:47.048696 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8153 05:52:47.055151 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8154 05:52:47.058731 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8155 05:52:47.062034 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8156 05:52:47.065385 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8157 05:52:47.068446 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8158 05:52:47.075074 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8159 05:52:47.078698 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8160 05:52:47.081906 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8161 05:52:47.084899 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8162 05:52:47.088582 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8163 05:52:47.094726 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8164 05:52:47.098262 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8165 05:52:47.101946 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8166 05:52:47.104892 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8167 05:52:47.104973 ==
8168 05:52:47.107876 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 05:52:47.114989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 05:52:47.115072 ==
8171 05:52:47.115137 DQS Delay:
8172 05:52:47.117878 DQS0 = 0, DQS1 = 0
8173 05:52:47.117959 DQM Delay:
8174 05:52:47.121433 DQM0 = 127, DQM1 = 122
8175 05:52:47.121564 DQ Delay:
8176 05:52:47.124418 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8177 05:52:47.127922 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8178 05:52:47.131375 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8179 05:52:47.134714 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8180 05:52:47.134806
8181 05:52:47.134901
8182 05:52:47.134976 ==
8183 05:52:47.138160 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 05:52:47.144684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 05:52:47.144767 ==
8186 05:52:47.144832
8187 05:52:47.144891
8188 05:52:47.144948 TX Vref Scan disable
8189 05:52:47.147654 == TX Byte 0 ==
8190 05:52:47.151280 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8191 05:52:47.157515 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8192 05:52:47.157600 == TX Byte 1 ==
8193 05:52:47.161078 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8194 05:52:47.167770 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8195 05:52:47.167890 ==
8196 05:52:47.171105 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 05:52:47.174364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 05:52:47.174473 ==
8199 05:52:47.189026
8200 05:52:47.192159 TX Vref early break, caculate TX vref
8201 05:52:47.195685 TX Vref=16, minBit 8, minWin=21, winSum=368
8202 05:52:47.198727 TX Vref=18, minBit 8, minWin=22, winSum=376
8203 05:52:47.202343 TX Vref=20, minBit 8, minWin=22, winSum=382
8204 05:52:47.205318 TX Vref=22, minBit 8, minWin=23, winSum=390
8205 05:52:47.209006 TX Vref=24, minBit 0, minWin=24, winSum=399
8206 05:52:47.215108 TX Vref=26, minBit 0, minWin=25, winSum=407
8207 05:52:47.218783 TX Vref=28, minBit 8, minWin=24, winSum=412
8208 05:52:47.221579 TX Vref=30, minBit 8, minWin=24, winSum=412
8209 05:52:47.225048 TX Vref=32, minBit 13, minWin=23, winSum=400
8210 05:52:47.228534 TX Vref=34, minBit 8, minWin=22, winSum=391
8211 05:52:47.235203 TX Vref=36, minBit 8, minWin=22, winSum=384
8212 05:52:47.238611 [TxChooseVref] Worse bit 0, Min win 25, Win sum 407, Final Vref 26
8213 05:52:47.238721
8214 05:52:47.241460 Final TX Range 0 Vref 26
8215 05:52:47.241546
8216 05:52:47.241610 ==
8217 05:52:47.244997 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 05:52:47.248011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 05:52:47.251121 ==
8220 05:52:47.251198
8221 05:52:47.251262
8222 05:52:47.251322 TX Vref Scan disable
8223 05:52:47.258138 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8224 05:52:47.258218 == TX Byte 0 ==
8225 05:52:47.261794 u2DelayCellOfst[0]=15 cells (4 PI)
8226 05:52:47.264654 u2DelayCellOfst[1]=18 cells (5 PI)
8227 05:52:47.268558 u2DelayCellOfst[2]=15 cells (4 PI)
8228 05:52:47.271737 u2DelayCellOfst[3]=15 cells (4 PI)
8229 05:52:47.274776 u2DelayCellOfst[4]=11 cells (3 PI)
8230 05:52:47.278156 u2DelayCellOfst[5]=0 cells (0 PI)
8231 05:52:47.281742 u2DelayCellOfst[6]=22 cells (6 PI)
8232 05:52:47.284640 u2DelayCellOfst[7]=18 cells (5 PI)
8233 05:52:47.288260 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8234 05:52:47.291272 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8235 05:52:47.294917 == TX Byte 1 ==
8236 05:52:47.297964 u2DelayCellOfst[8]=0 cells (0 PI)
8237 05:52:47.301438 u2DelayCellOfst[9]=3 cells (1 PI)
8238 05:52:47.304482 u2DelayCellOfst[10]=11 cells (3 PI)
8239 05:52:47.308068 u2DelayCellOfst[11]=7 cells (2 PI)
8240 05:52:47.311206 u2DelayCellOfst[12]=15 cells (4 PI)
8241 05:52:47.314273 u2DelayCellOfst[13]=15 cells (4 PI)
8242 05:52:47.314389 u2DelayCellOfst[14]=15 cells (4 PI)
8243 05:52:47.318092 u2DelayCellOfst[15]=11 cells (3 PI)
8244 05:52:47.324662 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8245 05:52:47.327600 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8246 05:52:47.331241 DramC Write-DBI on
8247 05:52:47.331349 ==
8248 05:52:47.334694 Dram Type= 6, Freq= 0, CH_0, rank 1
8249 05:52:47.337565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8250 05:52:47.337670 ==
8251 05:52:47.337771
8252 05:52:47.337866
8253 05:52:47.341041 TX Vref Scan disable
8254 05:52:47.341112 == TX Byte 0 ==
8255 05:52:47.347491 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8256 05:52:47.347569 == TX Byte 1 ==
8257 05:52:47.350817 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8258 05:52:47.353870 DramC Write-DBI off
8259 05:52:47.353949
8260 05:52:47.354012 [DATLAT]
8261 05:52:47.357189 Freq=1600, CH0 RK1
8262 05:52:47.357293
8263 05:52:47.357389 DATLAT Default: 0xf
8264 05:52:47.360653 0, 0xFFFF, sum = 0
8265 05:52:47.363809 1, 0xFFFF, sum = 0
8266 05:52:47.363915 2, 0xFFFF, sum = 0
8267 05:52:47.366920 3, 0xFFFF, sum = 0
8268 05:52:47.367014 4, 0xFFFF, sum = 0
8269 05:52:47.370588 5, 0xFFFF, sum = 0
8270 05:52:47.370703 6, 0xFFFF, sum = 0
8271 05:52:47.373927 7, 0xFFFF, sum = 0
8272 05:52:47.374039 8, 0xFFFF, sum = 0
8273 05:52:47.376822 9, 0xFFFF, sum = 0
8274 05:52:47.376932 10, 0xFFFF, sum = 0
8275 05:52:47.380237 11, 0xFFFF, sum = 0
8276 05:52:47.380360 12, 0xFFFF, sum = 0
8277 05:52:47.383830 13, 0xCFFF, sum = 0
8278 05:52:47.383953 14, 0x0, sum = 1
8279 05:52:47.386979 15, 0x0, sum = 2
8280 05:52:47.387096 16, 0x0, sum = 3
8281 05:52:47.390613 17, 0x0, sum = 4
8282 05:52:47.390704 best_step = 15
8283 05:52:47.390771
8284 05:52:47.390832 ==
8285 05:52:47.393952 Dram Type= 6, Freq= 0, CH_0, rank 1
8286 05:52:47.400683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 05:52:47.400795 ==
8288 05:52:47.400891 RX Vref Scan: 0
8289 05:52:47.400982
8290 05:52:47.403546 RX Vref 0 -> 0, step: 1
8291 05:52:47.403628
8292 05:52:47.407314 RX Delay 3 -> 252, step: 4
8293 05:52:47.410240 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8294 05:52:47.413221 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8295 05:52:47.416911 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8296 05:52:47.423138 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8297 05:52:47.426744 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8298 05:52:47.429835 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8299 05:52:47.432969 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8300 05:52:47.436558 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8301 05:52:47.443408 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8302 05:52:47.446637 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8303 05:52:47.449795 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8304 05:52:47.453279 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8305 05:52:47.459774 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8306 05:52:47.463151 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8307 05:52:47.465986 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8308 05:52:47.469464 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8309 05:52:47.469575 ==
8310 05:52:47.472737 Dram Type= 6, Freq= 0, CH_0, rank 1
8311 05:52:47.479290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 05:52:47.479392 ==
8313 05:52:47.479460 DQS Delay:
8314 05:52:47.479528 DQS0 = 0, DQS1 = 0
8315 05:52:47.482579 DQM Delay:
8316 05:52:47.482697 DQM0 = 124, DQM1 = 118
8317 05:52:47.486221 DQ Delay:
8318 05:52:47.489500 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8319 05:52:47.492396 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8320 05:52:47.496078 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
8321 05:52:47.499641 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8322 05:52:47.499753
8323 05:52:47.499849
8324 05:52:47.499944
8325 05:52:47.502496 [DramC_TX_OE_Calibration] TA2
8326 05:52:47.506062 Original DQ_B0 (3 6) =30, OEN = 27
8327 05:52:47.509036 Original DQ_B1 (3 6) =30, OEN = 27
8328 05:52:47.512687 24, 0x0, End_B0=24 End_B1=24
8329 05:52:47.512797 25, 0x0, End_B0=25 End_B1=25
8330 05:52:47.515553 26, 0x0, End_B0=26 End_B1=26
8331 05:52:47.519246 27, 0x0, End_B0=27 End_B1=27
8332 05:52:47.522301 28, 0x0, End_B0=28 End_B1=28
8333 05:52:47.525883 29, 0x0, End_B0=29 End_B1=29
8334 05:52:47.525995 30, 0x0, End_B0=30 End_B1=30
8335 05:52:47.529047 31, 0x4141, End_B0=30 End_B1=30
8336 05:52:47.532243 Byte0 end_step=30 best_step=27
8337 05:52:47.535273 Byte1 end_step=30 best_step=27
8338 05:52:47.538839 Byte0 TX OE(2T, 0.5T) = (3, 3)
8339 05:52:47.542383 Byte1 TX OE(2T, 0.5T) = (3, 3)
8340 05:52:47.542493
8341 05:52:47.542590
8342 05:52:47.548915 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8343 05:52:47.552008 CH0 RK1: MR19=303, MR18=210F
8344 05:52:47.558824 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8345 05:52:47.561740 [RxdqsGatingPostProcess] freq 1600
8346 05:52:47.565173 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8347 05:52:47.568295 best DQS0 dly(2T, 0.5T) = (1, 1)
8348 05:52:47.571676 best DQS1 dly(2T, 0.5T) = (1, 1)
8349 05:52:47.575270 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8350 05:52:47.578357 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8351 05:52:47.582033 best DQS0 dly(2T, 0.5T) = (1, 1)
8352 05:52:47.584924 best DQS1 dly(2T, 0.5T) = (1, 1)
8353 05:52:47.588096 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8354 05:52:47.591631 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8355 05:52:47.594984 Pre-setting of DQS Precalculation
8356 05:52:47.598319 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8357 05:52:47.598403 ==
8358 05:52:47.601575 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 05:52:47.607965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 05:52:47.608053 ==
8361 05:52:47.611650 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8362 05:52:47.618139 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8363 05:52:47.621267 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8364 05:52:47.627845 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8365 05:52:47.635608 [CA 0] Center 42 (13~71) winsize 59
8366 05:52:47.638693 [CA 1] Center 42 (12~72) winsize 61
8367 05:52:47.642213 [CA 2] Center 38 (9~67) winsize 59
8368 05:52:47.645255 [CA 3] Center 37 (8~67) winsize 60
8369 05:52:47.648891 [CA 4] Center 38 (9~67) winsize 59
8370 05:52:47.651971 [CA 5] Center 37 (8~66) winsize 59
8371 05:52:47.652040
8372 05:52:47.655496 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8373 05:52:47.655568
8374 05:52:47.658507 [CATrainingPosCal] consider 1 rank data
8375 05:52:47.661943 u2DelayCellTimex100 = 258/100 ps
8376 05:52:47.668787 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8377 05:52:47.671929 CA1 delay=42 (12~72),Diff = 5 PI (18 cell)
8378 05:52:47.675241 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8379 05:52:47.678657 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8380 05:52:47.682020 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8381 05:52:47.685019 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8382 05:52:47.685119
8383 05:52:47.688441 CA PerBit enable=1, Macro0, CA PI delay=37
8384 05:52:47.688524
8385 05:52:47.691971 [CBTSetCACLKResult] CA Dly = 37
8386 05:52:47.695019 CS Dly: 9 (0~40)
8387 05:52:47.698551 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8388 05:52:47.701592 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8389 05:52:47.701699 ==
8390 05:52:47.705123 Dram Type= 6, Freq= 0, CH_1, rank 1
8391 05:52:47.711409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8392 05:52:47.711487 ==
8393 05:52:47.714873 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8394 05:52:47.718399 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8395 05:52:47.724959 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8396 05:52:47.731162 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8397 05:52:47.739142 [CA 0] Center 42 (12~72) winsize 61
8398 05:52:47.742089 [CA 1] Center 42 (12~72) winsize 61
8399 05:52:47.745306 [CA 2] Center 38 (9~67) winsize 59
8400 05:52:47.748978 [CA 3] Center 36 (7~66) winsize 60
8401 05:52:47.752089 [CA 4] Center 38 (8~68) winsize 61
8402 05:52:47.755156 [CA 5] Center 36 (7~66) winsize 60
8403 05:52:47.755264
8404 05:52:47.758843 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8405 05:52:47.758950
8406 05:52:47.761886 [CATrainingPosCal] consider 2 rank data
8407 05:52:47.765491 u2DelayCellTimex100 = 258/100 ps
8408 05:52:47.768570 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8409 05:52:47.775370 CA1 delay=42 (12~72),Diff = 5 PI (18 cell)
8410 05:52:47.778887 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8411 05:52:47.781958 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8412 05:52:47.784910 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8413 05:52:47.788185 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8414 05:52:47.788263
8415 05:52:47.791504 CA PerBit enable=1, Macro0, CA PI delay=37
8416 05:52:47.791579
8417 05:52:47.795215 [CBTSetCACLKResult] CA Dly = 37
8418 05:52:47.798200 CS Dly: 10 (0~43)
8419 05:52:47.801590 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8420 05:52:47.804609 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8421 05:52:47.804717
8422 05:52:47.808226 ----->DramcWriteLeveling(PI) begin...
8423 05:52:47.808339 ==
8424 05:52:47.811186 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 05:52:47.817870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 05:52:47.817976 ==
8427 05:52:47.821431 Write leveling (Byte 0): 24 => 24
8428 05:52:47.824872 Write leveling (Byte 1): 27 => 27
8429 05:52:47.824983 DramcWriteLeveling(PI) end<-----
8430 05:52:47.825075
8431 05:52:47.827812 ==
8432 05:52:47.831286 Dram Type= 6, Freq= 0, CH_1, rank 0
8433 05:52:47.834764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8434 05:52:47.834878 ==
8435 05:52:47.838392 [Gating] SW mode calibration
8436 05:52:47.844395 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8437 05:52:47.848062 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8438 05:52:47.854223 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 05:52:47.857997 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 05:52:47.861026 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 05:52:47.867772 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 05:52:47.870856 1 4 16 | B1->B0 | 3333 3232 | 1 0 | (1 1) (1 1)
8443 05:52:47.874333 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8444 05:52:47.881010 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8445 05:52:47.884096 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8446 05:52:47.887817 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8447 05:52:47.894404 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8448 05:52:47.897703 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8449 05:52:47.901060 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8450 05:52:47.907320 1 5 16 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
8451 05:52:47.911076 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 05:52:47.914289 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 05:52:47.920920 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8454 05:52:47.924571 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8455 05:52:47.927508 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8456 05:52:47.934227 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8457 05:52:47.937277 1 6 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8458 05:52:47.940726 1 6 16 | B1->B0 | 4141 3e3d | 1 1 | (0 0) (0 0)
8459 05:52:47.946921 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 05:52:47.950592 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 05:52:47.953707 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 05:52:47.960234 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8463 05:52:47.963791 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8464 05:52:47.966857 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8465 05:52:47.973446 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8466 05:52:47.977096 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8467 05:52:47.980675 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 05:52:47.983732 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 05:52:47.990454 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 05:52:47.993473 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 05:52:47.996580 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 05:52:48.003252 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 05:52:48.006615 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 05:52:48.010311 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 05:52:48.016756 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 05:52:48.020126 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 05:52:48.023248 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 05:52:48.029889 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 05:52:48.033087 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 05:52:48.036710 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 05:52:48.043319 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8482 05:52:48.046325 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8483 05:52:48.049791 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8484 05:52:48.056245 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8485 05:52:48.060169 Total UI for P1: 0, mck2ui 16
8486 05:52:48.063154 best dqsien dly found for B0: ( 1, 9, 16)
8487 05:52:48.066283 Total UI for P1: 0, mck2ui 16
8488 05:52:48.070084 best dqsien dly found for B1: ( 1, 9, 16)
8489 05:52:48.073069 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8490 05:52:48.076017 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8491 05:52:48.076123
8492 05:52:48.079830 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8493 05:52:48.082797 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8494 05:52:48.086538 [Gating] SW calibration Done
8495 05:52:48.086618 ==
8496 05:52:48.089510 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 05:52:48.092512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 05:52:48.092593 ==
8499 05:52:48.096193 RX Vref Scan: 0
8500 05:52:48.096274
8501 05:52:48.099281 RX Vref 0 -> 0, step: 1
8502 05:52:48.099361
8503 05:52:48.099426 RX Delay 0 -> 252, step: 8
8504 05:52:48.105924 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8505 05:52:48.109280 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8506 05:52:48.112527 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8507 05:52:48.115955 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8508 05:52:48.118879 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8509 05:52:48.125464 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8510 05:52:48.128967 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8511 05:52:48.132350 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8512 05:52:48.135695 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8513 05:52:48.138697 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8514 05:52:48.145905 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8515 05:52:48.148913 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8516 05:52:48.152513 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8517 05:52:48.155422 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8518 05:52:48.161985 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8519 05:52:48.165393 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8520 05:52:48.165532 ==
8521 05:52:48.168675 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 05:52:48.171818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 05:52:48.171937 ==
8524 05:52:48.172030 DQS Delay:
8525 05:52:48.175564 DQS0 = 0, DQS1 = 0
8526 05:52:48.175637 DQM Delay:
8527 05:52:48.178466 DQM0 = 132, DQM1 = 126
8528 05:52:48.178562 DQ Delay:
8529 05:52:48.182193 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8530 05:52:48.185183 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8531 05:52:48.188910 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8532 05:52:48.195438 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8533 05:52:48.195547
8534 05:52:48.195630
8535 05:52:48.195694 ==
8536 05:52:48.198405 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 05:52:48.201999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 05:52:48.202104 ==
8539 05:52:48.202205
8540 05:52:48.202292
8541 05:52:48.205018 TX Vref Scan disable
8542 05:52:48.205087 == TX Byte 0 ==
8543 05:52:48.211478 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8544 05:52:48.215072 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8545 05:52:48.215140 == TX Byte 1 ==
8546 05:52:48.221831 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8547 05:52:48.224918 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8548 05:52:48.224987 ==
8549 05:52:48.227980 Dram Type= 6, Freq= 0, CH_1, rank 0
8550 05:52:48.231615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8551 05:52:48.231723 ==
8552 05:52:48.245020
8553 05:52:48.248652 TX Vref early break, caculate TX vref
8554 05:52:48.251825 TX Vref=16, minBit 1, minWin=22, winSum=365
8555 05:52:48.254796 TX Vref=18, minBit 11, minWin=22, winSum=371
8556 05:52:48.258645 TX Vref=20, minBit 1, minWin=23, winSum=383
8557 05:52:48.262032 TX Vref=22, minBit 1, minWin=24, winSum=396
8558 05:52:48.268156 TX Vref=24, minBit 10, minWin=24, winSum=403
8559 05:52:48.271895 TX Vref=26, minBit 1, minWin=25, winSum=414
8560 05:52:48.274866 TX Vref=28, minBit 8, minWin=25, winSum=419
8561 05:52:48.278371 TX Vref=30, minBit 1, minWin=25, winSum=417
8562 05:52:48.281213 TX Vref=32, minBit 1, minWin=24, winSum=407
8563 05:52:48.284535 TX Vref=34, minBit 6, minWin=23, winSum=397
8564 05:52:48.291294 [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 28
8565 05:52:48.291404
8566 05:52:48.294549 Final TX Range 0 Vref 28
8567 05:52:48.294628
8568 05:52:48.294690 ==
8569 05:52:48.298115 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 05:52:48.300992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 05:52:48.301063 ==
8572 05:52:48.301123
8573 05:52:48.301180
8574 05:52:48.304437 TX Vref Scan disable
8575 05:52:48.311029 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8576 05:52:48.311099 == TX Byte 0 ==
8577 05:52:48.314639 u2DelayCellOfst[0]=22 cells (6 PI)
8578 05:52:48.317760 u2DelayCellOfst[1]=15 cells (4 PI)
8579 05:52:48.320819 u2DelayCellOfst[2]=0 cells (0 PI)
8580 05:52:48.324438 u2DelayCellOfst[3]=3 cells (1 PI)
8581 05:52:48.327983 u2DelayCellOfst[4]=7 cells (2 PI)
8582 05:52:48.331024 u2DelayCellOfst[5]=22 cells (6 PI)
8583 05:52:48.334364 u2DelayCellOfst[6]=18 cells (5 PI)
8584 05:52:48.337812 u2DelayCellOfst[7]=7 cells (2 PI)
8585 05:52:48.341186 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8586 05:52:48.344269 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8587 05:52:48.347401 == TX Byte 1 ==
8588 05:52:48.350948 u2DelayCellOfst[8]=0 cells (0 PI)
8589 05:52:48.354018 u2DelayCellOfst[9]=7 cells (2 PI)
8590 05:52:48.357496 u2DelayCellOfst[10]=15 cells (4 PI)
8591 05:52:48.360640 u2DelayCellOfst[11]=11 cells (3 PI)
8592 05:52:48.360740 u2DelayCellOfst[12]=18 cells (5 PI)
8593 05:52:48.364035 u2DelayCellOfst[13]=22 cells (6 PI)
8594 05:52:48.367073 u2DelayCellOfst[14]=22 cells (6 PI)
8595 05:52:48.370250 u2DelayCellOfst[15]=22 cells (6 PI)
8596 05:52:48.377011 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8597 05:52:48.380080 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8598 05:52:48.383628 DramC Write-DBI on
8599 05:52:48.383704 ==
8600 05:52:48.387179 Dram Type= 6, Freq= 0, CH_1, rank 0
8601 05:52:48.390077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8602 05:52:48.390180 ==
8603 05:52:48.390260
8604 05:52:48.390355
8605 05:52:48.393553 TX Vref Scan disable
8606 05:52:48.393633 == TX Byte 0 ==
8607 05:52:48.400244 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8608 05:52:48.400328 == TX Byte 1 ==
8609 05:52:48.403183 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8610 05:52:48.407639 DramC Write-DBI off
8611 05:52:48.407715
8612 05:52:48.407778 [DATLAT]
8613 05:52:48.409934 Freq=1600, CH1 RK0
8614 05:52:48.410004
8615 05:52:48.410062 DATLAT Default: 0xf
8616 05:52:48.412980 0, 0xFFFF, sum = 0
8617 05:52:48.413046 1, 0xFFFF, sum = 0
8618 05:52:48.416620 2, 0xFFFF, sum = 0
8619 05:52:48.416701 3, 0xFFFF, sum = 0
8620 05:52:48.419644 4, 0xFFFF, sum = 0
8621 05:52:48.423256 5, 0xFFFF, sum = 0
8622 05:52:48.423338 6, 0xFFFF, sum = 0
8623 05:52:48.426309 7, 0xFFFF, sum = 0
8624 05:52:48.426391 8, 0xFFFF, sum = 0
8625 05:52:48.429915 9, 0xFFFF, sum = 0
8626 05:52:48.429998 10, 0xFFFF, sum = 0
8627 05:52:48.432934 11, 0xFFFF, sum = 0
8628 05:52:48.433016 12, 0xFFFF, sum = 0
8629 05:52:48.436466 13, 0x8FFF, sum = 0
8630 05:52:48.436547 14, 0x0, sum = 1
8631 05:52:48.439919 15, 0x0, sum = 2
8632 05:52:48.440001 16, 0x0, sum = 3
8633 05:52:48.442631 17, 0x0, sum = 4
8634 05:52:48.442713 best_step = 15
8635 05:52:48.442777
8636 05:52:48.442837 ==
8637 05:52:48.446004 Dram Type= 6, Freq= 0, CH_1, rank 0
8638 05:52:48.449299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8639 05:52:48.452876 ==
8640 05:52:48.452956 RX Vref Scan: 1
8641 05:52:48.453021
8642 05:52:48.455873 Set Vref Range= 24 -> 127
8643 05:52:48.455953
8644 05:52:48.459531 RX Vref 24 -> 127, step: 1
8645 05:52:48.459612
8646 05:52:48.459676 RX Delay 11 -> 252, step: 4
8647 05:52:48.459737
8648 05:52:48.462436 Set Vref, RX VrefLevel [Byte0]: 24
8649 05:52:48.466019 [Byte1]: 24
8650 05:52:48.470156
8651 05:52:48.470236 Set Vref, RX VrefLevel [Byte0]: 25
8652 05:52:48.473073 [Byte1]: 25
8653 05:52:48.477343
8654 05:52:48.477423 Set Vref, RX VrefLevel [Byte0]: 26
8655 05:52:48.480902 [Byte1]: 26
8656 05:52:48.485413
8657 05:52:48.485515 Set Vref, RX VrefLevel [Byte0]: 27
8658 05:52:48.488662 [Byte1]: 27
8659 05:52:48.492611
8660 05:52:48.492691 Set Vref, RX VrefLevel [Byte0]: 28
8661 05:52:48.496275 [Byte1]: 28
8662 05:52:48.500401
8663 05:52:48.500481 Set Vref, RX VrefLevel [Byte0]: 29
8664 05:52:48.504063 [Byte1]: 29
8665 05:52:48.508011
8666 05:52:48.508091 Set Vref, RX VrefLevel [Byte0]: 30
8667 05:52:48.511159 [Byte1]: 30
8668 05:52:48.515597
8669 05:52:48.515676 Set Vref, RX VrefLevel [Byte0]: 31
8670 05:52:48.519035 [Byte1]: 31
8671 05:52:48.523124
8672 05:52:48.523204 Set Vref, RX VrefLevel [Byte0]: 32
8673 05:52:48.526682 [Byte1]: 32
8674 05:52:48.530799
8675 05:52:48.530879 Set Vref, RX VrefLevel [Byte0]: 33
8676 05:52:48.534267 [Byte1]: 33
8677 05:52:48.538463
8678 05:52:48.538544 Set Vref, RX VrefLevel [Byte0]: 34
8679 05:52:48.541501 [Byte1]: 34
8680 05:52:48.546045
8681 05:52:48.546125 Set Vref, RX VrefLevel [Byte0]: 35
8682 05:52:48.549473 [Byte1]: 35
8683 05:52:48.553723
8684 05:52:48.553803 Set Vref, RX VrefLevel [Byte0]: 36
8685 05:52:48.557188 [Byte1]: 36
8686 05:52:48.561384
8687 05:52:48.561464 Set Vref, RX VrefLevel [Byte0]: 37
8688 05:52:48.564400 [Byte1]: 37
8689 05:52:48.569265
8690 05:52:48.569345 Set Vref, RX VrefLevel [Byte0]: 38
8691 05:52:48.572187 [Byte1]: 38
8692 05:52:48.576429
8693 05:52:48.576509 Set Vref, RX VrefLevel [Byte0]: 39
8694 05:52:48.579896 [Byte1]: 39
8695 05:52:48.584105
8696 05:52:48.584185 Set Vref, RX VrefLevel [Byte0]: 40
8697 05:52:48.587348 [Byte1]: 40
8698 05:52:48.591528
8699 05:52:48.591608 Set Vref, RX VrefLevel [Byte0]: 41
8700 05:52:48.594927 [Byte1]: 41
8701 05:52:48.599568
8702 05:52:48.599651 Set Vref, RX VrefLevel [Byte0]: 42
8703 05:52:48.602651 [Byte1]: 42
8704 05:52:48.607343
8705 05:52:48.607423 Set Vref, RX VrefLevel [Byte0]: 43
8706 05:52:48.610335 [Byte1]: 43
8707 05:52:48.614351
8708 05:52:48.614432 Set Vref, RX VrefLevel [Byte0]: 44
8709 05:52:48.617935 [Byte1]: 44
8710 05:52:48.622207
8711 05:52:48.622287 Set Vref, RX VrefLevel [Byte0]: 45
8712 05:52:48.625513 [Byte1]: 45
8713 05:52:48.629851
8714 05:52:48.629931 Set Vref, RX VrefLevel [Byte0]: 46
8715 05:52:48.632858 [Byte1]: 46
8716 05:52:48.637681
8717 05:52:48.637761 Set Vref, RX VrefLevel [Byte0]: 47
8718 05:52:48.640685 [Byte1]: 47
8719 05:52:48.644835
8720 05:52:48.644915 Set Vref, RX VrefLevel [Byte0]: 48
8721 05:52:48.648248 [Byte1]: 48
8722 05:52:48.652420
8723 05:52:48.652500 Set Vref, RX VrefLevel [Byte0]: 49
8724 05:52:48.656036 [Byte1]: 49
8725 05:52:48.660025
8726 05:52:48.660106 Set Vref, RX VrefLevel [Byte0]: 50
8727 05:52:48.663797 [Byte1]: 50
8728 05:52:48.667694
8729 05:52:48.667773 Set Vref, RX VrefLevel [Byte0]: 51
8730 05:52:48.671326 [Byte1]: 51
8731 05:52:48.675571
8732 05:52:48.675651 Set Vref, RX VrefLevel [Byte0]: 52
8733 05:52:48.678564 [Byte1]: 52
8734 05:52:48.683298
8735 05:52:48.683378 Set Vref, RX VrefLevel [Byte0]: 53
8736 05:52:48.686217 [Byte1]: 53
8737 05:52:48.690786
8738 05:52:48.690867 Set Vref, RX VrefLevel [Byte0]: 54
8739 05:52:48.694194 [Byte1]: 54
8740 05:52:48.698072
8741 05:52:48.698152 Set Vref, RX VrefLevel [Byte0]: 55
8742 05:52:48.701383 [Byte1]: 55
8743 05:52:48.706132
8744 05:52:48.706212 Set Vref, RX VrefLevel [Byte0]: 56
8745 05:52:48.709112 [Byte1]: 56
8746 05:52:48.713864
8747 05:52:48.713950 Set Vref, RX VrefLevel [Byte0]: 57
8748 05:52:48.716920 [Byte1]: 57
8749 05:52:48.721136
8750 05:52:48.721206 Set Vref, RX VrefLevel [Byte0]: 58
8751 05:52:48.724153 [Byte1]: 58
8752 05:52:48.728908
8753 05:52:48.729008 Set Vref, RX VrefLevel [Byte0]: 59
8754 05:52:48.731906 [Byte1]: 59
8755 05:52:48.736372
8756 05:52:48.736441 Set Vref, RX VrefLevel [Byte0]: 60
8757 05:52:48.739875 [Byte1]: 60
8758 05:52:48.744137
8759 05:52:48.744207 Set Vref, RX VrefLevel [Byte0]: 61
8760 05:52:48.747270 [Byte1]: 61
8761 05:52:48.751411
8762 05:52:48.751483 Set Vref, RX VrefLevel [Byte0]: 62
8763 05:52:48.754928 [Byte1]: 62
8764 05:52:48.759069
8765 05:52:48.759146 Set Vref, RX VrefLevel [Byte0]: 63
8766 05:52:48.762630 [Byte1]: 63
8767 05:52:48.766827
8768 05:52:48.766900 Set Vref, RX VrefLevel [Byte0]: 64
8769 05:52:48.770042 [Byte1]: 64
8770 05:52:48.774809
8771 05:52:48.774889 Set Vref, RX VrefLevel [Byte0]: 65
8772 05:52:48.777793 [Byte1]: 65
8773 05:52:48.781969
8774 05:52:48.782053 Set Vref, RX VrefLevel [Byte0]: 66
8775 05:52:48.785448 [Byte1]: 66
8776 05:52:48.789661
8777 05:52:48.789735 Set Vref, RX VrefLevel [Byte0]: 67
8778 05:52:48.793032 [Byte1]: 67
8779 05:52:48.797402
8780 05:52:48.797537 Set Vref, RX VrefLevel [Byte0]: 68
8781 05:52:48.800901 [Byte1]: 68
8782 05:52:48.805036
8783 05:52:48.805110 Set Vref, RX VrefLevel [Byte0]: 69
8784 05:52:48.808366 [Byte1]: 69
8785 05:52:48.812634
8786 05:52:48.812711 Set Vref, RX VrefLevel [Byte0]: 70
8787 05:52:48.815933 [Byte1]: 70
8788 05:52:48.820095
8789 05:52:48.820171 Final RX Vref Byte 0 = 58 to rank0
8790 05:52:48.823681 Final RX Vref Byte 1 = 55 to rank0
8791 05:52:48.826759 Final RX Vref Byte 0 = 58 to rank1
8792 05:52:48.830216 Final RX Vref Byte 1 = 55 to rank1==
8793 05:52:48.833266 Dram Type= 6, Freq= 0, CH_1, rank 0
8794 05:52:48.839871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 05:52:48.839948 ==
8796 05:52:48.840029 DQS Delay:
8797 05:52:48.840109 DQS0 = 0, DQS1 = 0
8798 05:52:48.843442 DQM Delay:
8799 05:52:48.843515 DQM0 = 131, DQM1 = 123
8800 05:52:48.846555 DQ Delay:
8801 05:52:48.849889 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =128
8802 05:52:48.853096 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8803 05:52:48.856439 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8804 05:52:48.859521 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8805 05:52:48.859597
8806 05:52:48.859680
8807 05:52:48.859776
8808 05:52:48.863116 [DramC_TX_OE_Calibration] TA2
8809 05:52:48.866157 Original DQ_B0 (3 6) =30, OEN = 27
8810 05:52:48.869687 Original DQ_B1 (3 6) =30, OEN = 27
8811 05:52:48.873290 24, 0x0, End_B0=24 End_B1=24
8812 05:52:48.873393 25, 0x0, End_B0=25 End_B1=25
8813 05:52:48.876126 26, 0x0, End_B0=26 End_B1=26
8814 05:52:48.879823 27, 0x0, End_B0=27 End_B1=27
8815 05:52:48.883094 28, 0x0, End_B0=28 End_B1=28
8816 05:52:48.886434 29, 0x0, End_B0=29 End_B1=29
8817 05:52:48.886517 30, 0x0, End_B0=30 End_B1=30
8818 05:52:48.889406 31, 0x4141, End_B0=30 End_B1=30
8819 05:52:48.892950 Byte0 end_step=30 best_step=27
8820 05:52:48.895900 Byte1 end_step=30 best_step=27
8821 05:52:48.899384 Byte0 TX OE(2T, 0.5T) = (3, 3)
8822 05:52:48.902657 Byte1 TX OE(2T, 0.5T) = (3, 3)
8823 05:52:48.902734
8824 05:52:48.902819
8825 05:52:48.909282 [DQSOSCAuto] RK0, (LSB)MR18= 0x60b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
8826 05:52:48.912917 CH1 RK0: MR19=303, MR18=60B
8827 05:52:48.919283 CH1_RK0: MR19=0x303, MR18=0x60B, DQSOSC=404, MR23=63, INC=22, DEC=15
8828 05:52:48.919381
8829 05:52:48.922605 ----->DramcWriteLeveling(PI) begin...
8830 05:52:48.922687 ==
8831 05:52:48.925841 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 05:52:48.929421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 05:52:48.929556 ==
8834 05:52:48.932416 Write leveling (Byte 0): 24 => 24
8835 05:52:48.935475 Write leveling (Byte 1): 26 => 26
8836 05:52:48.938851 DramcWriteLeveling(PI) end<-----
8837 05:52:48.938925
8838 05:52:48.939006 ==
8839 05:52:48.942465 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 05:52:48.945396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 05:52:48.945529 ==
8842 05:52:48.949182 [Gating] SW mode calibration
8843 05:52:48.955760 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8844 05:52:48.962280 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8845 05:52:48.965518 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 05:52:48.972278 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 05:52:48.975589 1 4 8 | B1->B0 | 2323 2f2f | 0 0 | (1 1) (0 0)
8848 05:52:48.978786 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8849 05:52:48.985215 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8850 05:52:48.988697 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 05:52:48.991963 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 05:52:48.998396 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8853 05:52:49.002034 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8854 05:52:49.004966 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8855 05:52:49.011562 1 5 8 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 0)
8856 05:52:49.014849 1 5 12 | B1->B0 | 2a2a 2323 | 1 0 | (0 1) (0 0)
8857 05:52:49.018351 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8858 05:52:49.024879 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 05:52:49.028371 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 05:52:49.031606 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 05:52:49.037953 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 05:52:49.041440 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8863 05:52:49.045061 1 6 8 | B1->B0 | 2323 4443 | 0 1 | (0 0) (0 0)
8864 05:52:49.051773 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8865 05:52:49.054606 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 05:52:49.058370 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 05:52:49.061218 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 05:52:49.067819 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 05:52:49.071242 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 05:52:49.074801 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 05:52:49.081117 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8872 05:52:49.084535 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8873 05:52:49.087857 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8874 05:52:49.094686 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 05:52:49.097514 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 05:52:49.100783 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 05:52:49.107650 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 05:52:49.110715 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 05:52:49.114148 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 05:52:49.120888 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 05:52:49.123815 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 05:52:49.127187 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 05:52:49.134072 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 05:52:49.137462 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 05:52:49.140749 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 05:52:49.147168 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 05:52:49.150926 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8888 05:52:49.153806 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8889 05:52:49.157540 Total UI for P1: 0, mck2ui 16
8890 05:52:49.160597 best dqsien dly found for B0: ( 1, 9, 8)
8891 05:52:49.167303 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8892 05:52:49.167386 Total UI for P1: 0, mck2ui 16
8893 05:52:49.173817 best dqsien dly found for B1: ( 1, 9, 10)
8894 05:52:49.176853 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8895 05:52:49.180387 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8896 05:52:49.180469
8897 05:52:49.183437 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8898 05:52:49.187093 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8899 05:52:49.190027 [Gating] SW calibration Done
8900 05:52:49.190108 ==
8901 05:52:49.193511 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 05:52:49.196781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 05:52:49.196862 ==
8904 05:52:49.200078 RX Vref Scan: 0
8905 05:52:49.200159
8906 05:52:49.203219 RX Vref 0 -> 0, step: 1
8907 05:52:49.203300
8908 05:52:49.203364 RX Delay 0 -> 252, step: 8
8909 05:52:49.209951 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8910 05:52:49.213637 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8911 05:52:49.216602 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8912 05:52:49.220206 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8913 05:52:49.223567 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8914 05:52:49.230039 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8915 05:52:49.233511 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8916 05:52:49.236468 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8917 05:52:49.240069 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8918 05:52:49.243026 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8919 05:52:49.249697 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8920 05:52:49.253029 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8921 05:52:49.256517 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8922 05:52:49.260101 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8923 05:52:49.263130 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8924 05:52:49.269663 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8925 05:52:49.269744 ==
8926 05:52:49.273143 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 05:52:49.276182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 05:52:49.276263 ==
8929 05:52:49.276327 DQS Delay:
8930 05:52:49.279632 DQS0 = 0, DQS1 = 0
8931 05:52:49.279712 DQM Delay:
8932 05:52:49.283259 DQM0 = 132, DQM1 = 127
8933 05:52:49.283340 DQ Delay:
8934 05:52:49.286323 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8935 05:52:49.289326 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8936 05:52:49.292809 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =123
8937 05:52:49.296371 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8938 05:52:49.296452
8939 05:52:49.299296
8940 05:52:49.299376 ==
8941 05:52:49.302902 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 05:52:49.306003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 05:52:49.306085 ==
8944 05:52:49.306149
8945 05:52:49.306208
8946 05:52:49.309429 TX Vref Scan disable
8947 05:52:49.309516 == TX Byte 0 ==
8948 05:52:49.315644 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8949 05:52:49.319141 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8950 05:52:49.319226 == TX Byte 1 ==
8951 05:52:49.325897 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8952 05:52:49.329104 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8953 05:52:49.329185 ==
8954 05:52:49.332374 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 05:52:49.335560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 05:52:49.335642 ==
8957 05:52:49.349012
8958 05:52:49.352467 TX Vref early break, caculate TX vref
8959 05:52:49.355837 TX Vref=16, minBit 0, minWin=23, winSum=383
8960 05:52:49.359263 TX Vref=18, minBit 0, minWin=23, winSum=397
8961 05:52:49.362421 TX Vref=20, minBit 0, minWin=23, winSum=398
8962 05:52:49.365594 TX Vref=22, minBit 0, minWin=25, winSum=412
8963 05:52:49.369180 TX Vref=24, minBit 0, minWin=25, winSum=421
8964 05:52:49.375715 TX Vref=26, minBit 0, minWin=25, winSum=423
8965 05:52:49.378568 TX Vref=28, minBit 5, minWin=25, winSum=429
8966 05:52:49.382162 TX Vref=30, minBit 5, minWin=25, winSum=424
8967 05:52:49.385717 TX Vref=32, minBit 5, minWin=24, winSum=416
8968 05:52:49.388632 TX Vref=34, minBit 5, minWin=23, winSum=404
8969 05:52:49.395650 [TxChooseVref] Worse bit 5, Min win 25, Win sum 429, Final Vref 28
8970 05:52:49.395731
8971 05:52:49.398674 Final TX Range 0 Vref 28
8972 05:52:49.398754
8973 05:52:49.398818 ==
8974 05:52:49.401727 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 05:52:49.405197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 05:52:49.405279 ==
8977 05:52:49.405343
8978 05:52:49.405401
8979 05:52:49.408256 TX Vref Scan disable
8980 05:52:49.414921 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8981 05:52:49.415002 == TX Byte 0 ==
8982 05:52:49.418375 u2DelayCellOfst[0]=18 cells (5 PI)
8983 05:52:49.421741 u2DelayCellOfst[1]=15 cells (4 PI)
8984 05:52:49.424744 u2DelayCellOfst[2]=0 cells (0 PI)
8985 05:52:49.428413 u2DelayCellOfst[3]=3 cells (1 PI)
8986 05:52:49.431188 u2DelayCellOfst[4]=7 cells (2 PI)
8987 05:52:49.434516 u2DelayCellOfst[5]=22 cells (6 PI)
8988 05:52:49.437832 u2DelayCellOfst[6]=18 cells (5 PI)
8989 05:52:49.441142 u2DelayCellOfst[7]=3 cells (1 PI)
8990 05:52:49.444947 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8991 05:52:49.447980 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8992 05:52:49.450986 == TX Byte 1 ==
8993 05:52:49.454351 u2DelayCellOfst[8]=0 cells (0 PI)
8994 05:52:49.457953 u2DelayCellOfst[9]=7 cells (2 PI)
8995 05:52:49.460869 u2DelayCellOfst[10]=11 cells (3 PI)
8996 05:52:49.460949 u2DelayCellOfst[11]=7 cells (2 PI)
8997 05:52:49.464541 u2DelayCellOfst[12]=18 cells (5 PI)
8998 05:52:49.467526 u2DelayCellOfst[13]=22 cells (6 PI)
8999 05:52:49.470802 u2DelayCellOfst[14]=18 cells (5 PI)
9000 05:52:49.474479 u2DelayCellOfst[15]=18 cells (5 PI)
9001 05:52:49.480716 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9002 05:52:49.484360 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9003 05:52:49.484441 DramC Write-DBI on
9004 05:52:49.487646 ==
9005 05:52:49.487727 Dram Type= 6, Freq= 0, CH_1, rank 1
9006 05:52:49.494228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9007 05:52:49.494309 ==
9008 05:52:49.494373
9009 05:52:49.494432
9010 05:52:49.497657 TX Vref Scan disable
9011 05:52:49.497738 == TX Byte 0 ==
9012 05:52:49.504386 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9013 05:52:49.504466 == TX Byte 1 ==
9014 05:52:49.507355 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9015 05:52:49.510947 DramC Write-DBI off
9016 05:52:49.511027
9017 05:52:49.511091 [DATLAT]
9018 05:52:49.514023 Freq=1600, CH1 RK1
9019 05:52:49.514103
9020 05:52:49.514167 DATLAT Default: 0xf
9021 05:52:49.517435 0, 0xFFFF, sum = 0
9022 05:52:49.517553 1, 0xFFFF, sum = 0
9023 05:52:49.520441 2, 0xFFFF, sum = 0
9024 05:52:49.520521 3, 0xFFFF, sum = 0
9025 05:52:49.523932 4, 0xFFFF, sum = 0
9026 05:52:49.524014 5, 0xFFFF, sum = 0
9027 05:52:49.527382 6, 0xFFFF, sum = 0
9028 05:52:49.527464 7, 0xFFFF, sum = 0
9029 05:52:49.530931 8, 0xFFFF, sum = 0
9030 05:52:49.531013 9, 0xFFFF, sum = 0
9031 05:52:49.533870 10, 0xFFFF, sum = 0
9032 05:52:49.537420 11, 0xFFFF, sum = 0
9033 05:52:49.537539 12, 0xFFFF, sum = 0
9034 05:52:49.540505 13, 0x8FFF, sum = 0
9035 05:52:49.540587 14, 0x0, sum = 1
9036 05:52:49.543977 15, 0x0, sum = 2
9037 05:52:49.544059 16, 0x0, sum = 3
9038 05:52:49.547127 17, 0x0, sum = 4
9039 05:52:49.547210 best_step = 15
9040 05:52:49.547313
9041 05:52:49.547373 ==
9042 05:52:49.550439 Dram Type= 6, Freq= 0, CH_1, rank 1
9043 05:52:49.553938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9044 05:52:49.554020 ==
9045 05:52:49.557171 RX Vref Scan: 0
9046 05:52:49.557252
9047 05:52:49.560429 RX Vref 0 -> 0, step: 1
9048 05:52:49.560510
9049 05:52:49.560574 RX Delay 3 -> 252, step: 4
9050 05:52:49.567415 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9051 05:52:49.570435 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9052 05:52:49.574077 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9053 05:52:49.576988 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
9054 05:52:49.583909 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9055 05:52:49.587107 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9056 05:52:49.590419 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9057 05:52:49.593584 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
9058 05:52:49.597201 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9059 05:52:49.600102 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9060 05:52:49.607206 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9061 05:52:49.610186 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9062 05:52:49.613913 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9063 05:52:49.616815 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9064 05:52:49.623417 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9065 05:52:49.626968 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9066 05:52:49.627048 ==
9067 05:52:49.629917 Dram Type= 6, Freq= 0, CH_1, rank 1
9068 05:52:49.633455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9069 05:52:49.633574 ==
9070 05:52:49.636843 DQS Delay:
9071 05:52:49.636923 DQS0 = 0, DQS1 = 0
9072 05:52:49.636987 DQM Delay:
9073 05:52:49.640423 DQM0 = 130, DQM1 = 125
9074 05:52:49.640504 DQ Delay:
9075 05:52:49.643264 DQ0 =134, DQ1 =128, DQ2 =116, DQ3 =128
9076 05:52:49.646994 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =126
9077 05:52:49.649976 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
9078 05:52:49.656526 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =136
9079 05:52:49.656606
9080 05:52:49.656669
9081 05:52:49.656728
9082 05:52:49.659705 [DramC_TX_OE_Calibration] TA2
9083 05:52:49.663347 Original DQ_B0 (3 6) =30, OEN = 27
9084 05:52:49.663428 Original DQ_B1 (3 6) =30, OEN = 27
9085 05:52:49.666715 24, 0x0, End_B0=24 End_B1=24
9086 05:52:49.670047 25, 0x0, End_B0=25 End_B1=25
9087 05:52:49.673426 26, 0x0, End_B0=26 End_B1=26
9088 05:52:49.676221 27, 0x0, End_B0=27 End_B1=27
9089 05:52:49.676303 28, 0x0, End_B0=28 End_B1=28
9090 05:52:49.679488 29, 0x0, End_B0=29 End_B1=29
9091 05:52:49.683054 30, 0x0, End_B0=30 End_B1=30
9092 05:52:49.686620 31, 0x4545, End_B0=30 End_B1=30
9093 05:52:49.689715 Byte0 end_step=30 best_step=27
9094 05:52:49.689797 Byte1 end_step=30 best_step=27
9095 05:52:49.693124 Byte0 TX OE(2T, 0.5T) = (3, 3)
9096 05:52:49.696401 Byte1 TX OE(2T, 0.5T) = (3, 3)
9097 05:52:49.696482
9098 05:52:49.696546
9099 05:52:49.706391 [DQSOSCAuto] RK1, (LSB)MR18= 0x111d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9100 05:52:49.706474 CH1 RK1: MR19=303, MR18=111D
9101 05:52:49.712702 CH1_RK1: MR19=0x303, MR18=0x111D, DQSOSC=395, MR23=63, INC=23, DEC=15
9102 05:52:49.716215 [RxdqsGatingPostProcess] freq 1600
9103 05:52:49.722878 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9104 05:52:49.725983 best DQS0 dly(2T, 0.5T) = (1, 1)
9105 05:52:49.729657 best DQS1 dly(2T, 0.5T) = (1, 1)
9106 05:52:49.732602 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9107 05:52:49.736227 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9108 05:52:49.739633 best DQS0 dly(2T, 0.5T) = (1, 1)
9109 05:52:49.739713 best DQS1 dly(2T, 0.5T) = (1, 1)
9110 05:52:49.742405 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9111 05:52:49.745951 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9112 05:52:49.749593 Pre-setting of DQS Precalculation
9113 05:52:49.755709 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9114 05:52:49.762834 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9115 05:52:49.769240 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9116 05:52:49.769322
9117 05:52:49.769386
9118 05:52:49.772714 [Calibration Summary] 3200 Mbps
9119 05:52:49.772795 CH 0, Rank 0
9120 05:52:49.775617 SW Impedance : PASS
9121 05:52:49.779176 DUTY Scan : NO K
9122 05:52:49.779256 ZQ Calibration : PASS
9123 05:52:49.782601 Jitter Meter : NO K
9124 05:52:49.785870 CBT Training : PASS
9125 05:52:49.785980 Write leveling : PASS
9126 05:52:49.788855 RX DQS gating : PASS
9127 05:52:49.792445 RX DQ/DQS(RDDQC) : PASS
9128 05:52:49.792526 TX DQ/DQS : PASS
9129 05:52:49.795427 RX DATLAT : PASS
9130 05:52:49.799042 RX DQ/DQS(Engine): PASS
9131 05:52:49.799122 TX OE : PASS
9132 05:52:49.802089 All Pass.
9133 05:52:49.802170
9134 05:52:49.802234 CH 0, Rank 1
9135 05:52:49.805732 SW Impedance : PASS
9136 05:52:49.805812 DUTY Scan : NO K
9137 05:52:49.809117 ZQ Calibration : PASS
9138 05:52:49.812536 Jitter Meter : NO K
9139 05:52:49.812616 CBT Training : PASS
9140 05:52:49.815807 Write leveling : PASS
9141 05:52:49.819113 RX DQS gating : PASS
9142 05:52:49.819194 RX DQ/DQS(RDDQC) : PASS
9143 05:52:49.822257 TX DQ/DQS : PASS
9144 05:52:49.822337 RX DATLAT : PASS
9145 05:52:49.825617 RX DQ/DQS(Engine): PASS
9146 05:52:49.829101 TX OE : PASS
9147 05:52:49.829219 All Pass.
9148 05:52:49.829284
9149 05:52:49.829344 CH 1, Rank 0
9150 05:52:49.832016 SW Impedance : PASS
9151 05:52:49.835554 DUTY Scan : NO K
9152 05:52:49.835634 ZQ Calibration : PASS
9153 05:52:49.838571 Jitter Meter : NO K
9154 05:52:49.842021 CBT Training : PASS
9155 05:52:49.842101 Write leveling : PASS
9156 05:52:49.845553 RX DQS gating : PASS
9157 05:52:49.848960 RX DQ/DQS(RDDQC) : PASS
9158 05:52:49.849041 TX DQ/DQS : PASS
9159 05:52:49.851974 RX DATLAT : PASS
9160 05:52:49.855549 RX DQ/DQS(Engine): PASS
9161 05:52:49.855630 TX OE : PASS
9162 05:52:49.858543 All Pass.
9163 05:52:49.858623
9164 05:52:49.858687 CH 1, Rank 1
9165 05:52:49.861937 SW Impedance : PASS
9166 05:52:49.862043 DUTY Scan : NO K
9167 05:52:49.865050 ZQ Calibration : PASS
9168 05:52:49.868717 Jitter Meter : NO K
9169 05:52:49.868813 CBT Training : PASS
9170 05:52:49.871563 Write leveling : PASS
9171 05:52:49.874956 RX DQS gating : PASS
9172 05:52:49.875037 RX DQ/DQS(RDDQC) : PASS
9173 05:52:49.878284 TX DQ/DQS : PASS
9174 05:52:49.878366 RX DATLAT : PASS
9175 05:52:49.881757 RX DQ/DQS(Engine): PASS
9176 05:52:49.885286 TX OE : PASS
9177 05:52:49.885384 All Pass.
9178 05:52:49.885450
9179 05:52:49.888355 DramC Write-DBI on
9180 05:52:49.888510 PER_BANK_REFRESH: Hybrid Mode
9181 05:52:49.891661 TX_TRACKING: ON
9182 05:52:49.901456 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9183 05:52:49.908238 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9184 05:52:49.914590 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9185 05:52:49.918106 [FAST_K] Save calibration result to emmc
9186 05:52:49.921177 sync common calibartion params.
9187 05:52:49.924693 sync cbt_mode0:1, 1:1
9188 05:52:49.927664 dram_init: ddr_geometry: 2
9189 05:52:49.927745 dram_init: ddr_geometry: 2
9190 05:52:49.931023 dram_init: ddr_geometry: 2
9191 05:52:49.934814 0:dram_rank_size:100000000
9192 05:52:49.934897 1:dram_rank_size:100000000
9193 05:52:49.941144 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9194 05:52:49.944274 DFS_SHUFFLE_HW_MODE: ON
9195 05:52:49.947811 dramc_set_vcore_voltage set vcore to 725000
9196 05:52:49.950952 Read voltage for 1600, 0
9197 05:52:49.951034 Vio18 = 0
9198 05:52:49.951128 Vcore = 725000
9199 05:52:49.954393 Vdram = 0
9200 05:52:49.954473 Vddq = 0
9201 05:52:49.954538 Vmddr = 0
9202 05:52:49.957869 switch to 3200 Mbps bootup
9203 05:52:49.957950 [DramcRunTimeConfig]
9204 05:52:49.960880 PHYPLL
9205 05:52:49.960960 DPM_CONTROL_AFTERK: ON
9206 05:52:49.964474 PER_BANK_REFRESH: ON
9207 05:52:49.967517 REFRESH_OVERHEAD_REDUCTION: ON
9208 05:52:49.967613 CMD_PICG_NEW_MODE: OFF
9209 05:52:49.971089 XRTWTW_NEW_MODE: ON
9210 05:52:49.971173 XRTRTR_NEW_MODE: ON
9211 05:52:49.974096 TX_TRACKING: ON
9212 05:52:49.974206 RDSEL_TRACKING: OFF
9213 05:52:49.977657 DQS Precalculation for DVFS: ON
9214 05:52:49.981006 RX_TRACKING: OFF
9215 05:52:49.981087 HW_GATING DBG: ON
9216 05:52:49.984388 ZQCS_ENABLE_LP4: ON
9217 05:52:49.984468 RX_PICG_NEW_MODE: ON
9218 05:52:49.987498 TX_PICG_NEW_MODE: ON
9219 05:52:49.990840 ENABLE_RX_DCM_DPHY: ON
9220 05:52:49.990921 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9221 05:52:49.994415 DUMMY_READ_FOR_TRACKING: OFF
9222 05:52:49.997293 !!! SPM_CONTROL_AFTERK: OFF
9223 05:52:50.000801 !!! SPM could not control APHY
9224 05:52:50.000882 IMPEDANCE_TRACKING: ON
9225 05:52:50.004154 TEMP_SENSOR: ON
9226 05:52:50.004270 HW_SAVE_FOR_SR: OFF
9227 05:52:50.007213 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9228 05:52:50.010810 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9229 05:52:50.014423 Read ODT Tracking: ON
9230 05:52:50.017322 Refresh Rate DeBounce: ON
9231 05:52:50.017403 DFS_NO_QUEUE_FLUSH: ON
9232 05:52:50.020811 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9233 05:52:50.023629 ENABLE_DFS_RUNTIME_MRW: OFF
9234 05:52:50.027359 DDR_RESERVE_NEW_MODE: ON
9235 05:52:50.027440 MR_CBT_SWITCH_FREQ: ON
9236 05:52:50.030268 =========================
9237 05:52:50.049682 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9238 05:52:50.053438 dram_init: ddr_geometry: 2
9239 05:52:50.071310 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9240 05:52:50.074511 dram_init: dram init end (result: 0)
9241 05:52:50.081355 DRAM-K: Full calibration passed in 24609 msecs
9242 05:52:50.085081 MRC: failed to locate region type 0.
9243 05:52:50.085162 DRAM rank0 size:0x100000000,
9244 05:52:50.088064 DRAM rank1 size=0x100000000
9245 05:52:50.097868 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9246 05:52:50.104801 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9247 05:52:50.111545 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9248 05:52:50.117643 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9249 05:52:50.121369 DRAM rank0 size:0x100000000,
9250 05:52:50.124354 DRAM rank1 size=0x100000000
9251 05:52:50.124453 CBMEM:
9252 05:52:50.127859 IMD: root @ 0xfffff000 254 entries.
9253 05:52:50.130869 IMD: root @ 0xffffec00 62 entries.
9254 05:52:50.134608 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9255 05:52:50.140700 WARNING: RO_VPD is uninitialized or empty.
9256 05:52:50.144242 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9257 05:52:50.151332 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9258 05:52:50.164229 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9259 05:52:50.175630 BS: romstage times (exec / console): total (unknown) / 24069 ms
9260 05:52:50.175722
9261 05:52:50.175788
9262 05:52:50.185607 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9263 05:52:50.188666 ARM64: Exception handlers installed.
9264 05:52:50.192414 ARM64: Testing exception
9265 05:52:50.195354 ARM64: Done test exception
9266 05:52:50.195453 Enumerating buses...
9267 05:52:50.198940 Show all devs... Before device enumeration.
9268 05:52:50.202037 Root Device: enabled 1
9269 05:52:50.205803 CPU_CLUSTER: 0: enabled 1
9270 05:52:50.205881 CPU: 00: enabled 1
9271 05:52:50.208606 Compare with tree...
9272 05:52:50.208700 Root Device: enabled 1
9273 05:52:50.212030 CPU_CLUSTER: 0: enabled 1
9274 05:52:50.215306 CPU: 00: enabled 1
9275 05:52:50.215411 Root Device scanning...
9276 05:52:50.218888 scan_static_bus for Root Device
9277 05:52:50.221928 CPU_CLUSTER: 0 enabled
9278 05:52:50.225587 scan_static_bus for Root Device done
9279 05:52:50.228622 scan_bus: bus Root Device finished in 8 msecs
9280 05:52:50.228734 done
9281 05:52:50.235046 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9282 05:52:50.238798 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9283 05:52:50.245499 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9284 05:52:50.248463 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9285 05:52:50.251555 Allocating resources...
9286 05:52:50.255297 Reading resources...
9287 05:52:50.258319 Root Device read_resources bus 0 link: 0
9288 05:52:50.258395 DRAM rank0 size:0x100000000,
9289 05:52:50.261840 DRAM rank1 size=0x100000000
9290 05:52:50.264600 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9291 05:52:50.268422 CPU: 00 missing read_resources
9292 05:52:50.275070 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9293 05:52:50.278016 Root Device read_resources bus 0 link: 0 done
9294 05:52:50.278130 Done reading resources.
9295 05:52:50.284790 Show resources in subtree (Root Device)...After reading.
9296 05:52:50.288464 Root Device child on link 0 CPU_CLUSTER: 0
9297 05:52:50.291557 CPU_CLUSTER: 0 child on link 0 CPU: 00
9298 05:52:50.301451 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9299 05:52:50.301573 CPU: 00
9300 05:52:50.304478 Root Device assign_resources, bus 0 link: 0
9301 05:52:50.308245 CPU_CLUSTER: 0 missing set_resources
9302 05:52:50.314384 Root Device assign_resources, bus 0 link: 0 done
9303 05:52:50.314485 Done setting resources.
9304 05:52:50.321552 Show resources in subtree (Root Device)...After assigning values.
9305 05:52:50.324576 Root Device child on link 0 CPU_CLUSTER: 0
9306 05:52:50.327886 CPU_CLUSTER: 0 child on link 0 CPU: 00
9307 05:52:50.338160 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9308 05:52:50.338241 CPU: 00
9309 05:52:50.341230 Done allocating resources.
9310 05:52:50.347866 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9311 05:52:50.347952 Enabling resources...
9312 05:52:50.348065 done.
9313 05:52:50.354577 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9314 05:52:50.354654 Initializing devices...
9315 05:52:50.357574 Root Device init
9316 05:52:50.357648 init hardware done!
9317 05:52:50.361313 0x00000018: ctrlr->caps
9318 05:52:50.364326 52.000 MHz: ctrlr->f_max
9319 05:52:50.364405 0.400 MHz: ctrlr->f_min
9320 05:52:50.367392 0x40ff8080: ctrlr->voltages
9321 05:52:50.370659 sclk: 390625
9322 05:52:50.370733 Bus Width = 1
9323 05:52:50.370794 sclk: 390625
9324 05:52:50.374128 Bus Width = 1
9325 05:52:50.374206 Early init status = 3
9326 05:52:50.380924 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9327 05:52:50.383899 in-header: 03 fc 00 00 01 00 00 00
9328 05:52:50.387522 in-data: 00
9329 05:52:50.390634 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9330 05:52:50.396692 in-header: 03 fd 00 00 00 00 00 00
9331 05:52:50.399824 in-data:
9332 05:52:50.402886 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9333 05:52:50.407811 in-header: 03 fc 00 00 01 00 00 00
9334 05:52:50.410916 in-data: 00
9335 05:52:50.414000 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9336 05:52:50.420054 in-header: 03 fd 00 00 00 00 00 00
9337 05:52:50.423133 in-data:
9338 05:52:50.426315 [SSUSB] Setting up USB HOST controller...
9339 05:52:50.429481 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9340 05:52:50.433197 [SSUSB] phy power-on done.
9341 05:52:50.436161 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9342 05:52:50.443151 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9343 05:52:50.446068 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9344 05:52:50.452960 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9345 05:52:50.459285 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9346 05:52:50.465922 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9347 05:52:50.472755 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9348 05:52:50.479133 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9349 05:52:50.482717 SPM: binary array size = 0x9dc
9350 05:52:50.485661 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9351 05:52:50.492334 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9352 05:52:50.499124 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9353 05:52:50.505960 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9354 05:52:50.508908 configure_display: Starting display init
9355 05:52:50.543153 anx7625_power_on_init: Init interface.
9356 05:52:50.546110 anx7625_disable_pd_protocol: Disabled PD feature.
9357 05:52:50.549605 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9358 05:52:50.577487 anx7625_start_dp_work: Secure OCM version=00
9359 05:52:50.580503 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9360 05:52:50.595281 sp_tx_get_edid_block: EDID Block = 1
9361 05:52:50.698288 Extracted contents:
9362 05:52:50.701249 header: 00 ff ff ff ff ff ff 00
9363 05:52:50.704605 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9364 05:52:50.707931 version: 01 04
9365 05:52:50.711263 basic params: 95 1f 11 78 0a
9366 05:52:50.714939 chroma info: 76 90 94 55 54 90 27 21 50 54
9367 05:52:50.717955 established: 00 00 00
9368 05:52:50.724640 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9369 05:52:50.730803 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9370 05:52:50.734380 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9371 05:52:50.740666 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9372 05:52:50.747256 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9373 05:52:50.750918 extensions: 00
9374 05:52:50.750994 checksum: fb
9375 05:52:50.751060
9376 05:52:50.757356 Manufacturer: IVO Model 57d Serial Number 0
9377 05:52:50.757481 Made week 0 of 2020
9378 05:52:50.760327 EDID version: 1.4
9379 05:52:50.760433 Digital display
9380 05:52:50.764064 6 bits per primary color channel
9381 05:52:50.764165 DisplayPort interface
9382 05:52:50.767075 Maximum image size: 31 cm x 17 cm
9383 05:52:50.770796 Gamma: 220%
9384 05:52:50.770894 Check DPMS levels
9385 05:52:50.777069 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9386 05:52:50.780241 First detailed timing is preferred timing
9387 05:52:50.780342 Established timings supported:
9388 05:52:50.783967 Standard timings supported:
9389 05:52:50.787308 Detailed timings
9390 05:52:50.790428 Hex of detail: 383680a07038204018303c0035ae10000019
9391 05:52:50.796873 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9392 05:52:50.800463 0780 0798 07c8 0820 hborder 0
9393 05:52:50.803471 0438 043b 0447 0458 vborder 0
9394 05:52:50.807187 -hsync -vsync
9395 05:52:50.807306 Did detailed timing
9396 05:52:50.813751 Hex of detail: 000000000000000000000000000000000000
9397 05:52:50.817091 Manufacturer-specified data, tag 0
9398 05:52:50.820391 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9399 05:52:50.823304 ASCII string: InfoVision
9400 05:52:50.826608 Hex of detail: 000000fe00523134304e574635205248200a
9401 05:52:50.830063 ASCII string: R140NWF5 RH
9402 05:52:50.830146 Checksum
9403 05:52:50.833595 Checksum: 0xfb (valid)
9404 05:52:50.836477 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9405 05:52:50.840040 DSI data_rate: 832800000 bps
9406 05:52:50.846928 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9407 05:52:50.850012 anx7625_parse_edid: pixelclock(138800).
9408 05:52:50.853040 hactive(1920), hsync(48), hfp(24), hbp(88)
9409 05:52:50.856608 vactive(1080), vsync(12), vfp(3), vbp(17)
9410 05:52:50.860122 anx7625_dsi_config: config dsi.
9411 05:52:50.866208 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9412 05:52:50.880107 anx7625_dsi_config: success to config DSI
9413 05:52:50.883417 anx7625_dp_start: MIPI phy setup OK.
9414 05:52:50.886614 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9415 05:52:50.889969 mtk_ddp_mode_set invalid vrefresh 60
9416 05:52:50.893495 main_disp_path_setup
9417 05:52:50.893590 ovl_layer_smi_id_en
9418 05:52:50.896470 ovl_layer_smi_id_en
9419 05:52:50.896551 ccorr_config
9420 05:52:50.896646 aal_config
9421 05:52:50.900015 gamma_config
9422 05:52:50.900096 postmask_config
9423 05:52:50.903060 dither_config
9424 05:52:50.906734 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9425 05:52:50.913282 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9426 05:52:50.916393 Root Device init finished in 555 msecs
9427 05:52:50.919955 CPU_CLUSTER: 0 init
9428 05:52:50.926589 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9429 05:52:50.929726 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9430 05:52:50.933168 APU_MBOX 0x190000b0 = 0x10001
9431 05:52:50.936106 APU_MBOX 0x190001b0 = 0x10001
9432 05:52:50.939810 APU_MBOX 0x190005b0 = 0x10001
9433 05:52:50.942656 APU_MBOX 0x190006b0 = 0x10001
9434 05:52:50.949243 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9435 05:52:50.958912 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9436 05:52:50.971613 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9437 05:52:50.977800 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9438 05:52:50.989804 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9439 05:52:50.998879 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9440 05:52:51.002203 CPU_CLUSTER: 0 init finished in 81 msecs
9441 05:52:51.005328 Devices initialized
9442 05:52:51.008826 Show all devs... After init.
9443 05:52:51.008943 Root Device: enabled 1
9444 05:52:51.011744 CPU_CLUSTER: 0: enabled 1
9445 05:52:51.016159 CPU: 00: enabled 1
9446 05:52:51.018468 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9447 05:52:51.021864 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9448 05:52:51.025075 ELOG: NV offset 0x57f000 size 0x1000
9449 05:52:51.031678 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9450 05:52:51.038963 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9451 05:52:51.041953 ELOG: Event(17) added with size 13 at 2023-12-25 05:52:50 UTC
9452 05:52:51.048444 out: cmd=0x121: 03 db 21 01 00 00 00 00
9453 05:52:51.051605 in-header: 03 32 00 00 2c 00 00 00
9454 05:52:51.061906 in-data: 2c 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9455 05:52:51.067996 ELOG: Event(A1) added with size 10 at 2023-12-25 05:52:50 UTC
9456 05:52:51.074736 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9457 05:52:51.081232 ELOG: Event(A0) added with size 9 at 2023-12-25 05:52:50 UTC
9458 05:52:51.084831 elog_add_boot_reason: Logged dev mode boot
9459 05:52:51.091445 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9460 05:52:51.091528 Finalize devices...
9461 05:52:51.094482 Devices finalized
9462 05:52:51.098199 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9463 05:52:51.100962 Writing coreboot table at 0xffe64000
9464 05:52:51.104267 0. 000000000010a000-0000000000113fff: RAMSTAGE
9465 05:52:51.111370 1. 0000000040000000-00000000400fffff: RAM
9466 05:52:51.114369 2. 0000000040100000-000000004032afff: RAMSTAGE
9467 05:52:51.117960 3. 000000004032b000-00000000545fffff: RAM
9468 05:52:51.120879 4. 0000000054600000-000000005465ffff: BL31
9469 05:52:51.124556 5. 0000000054660000-00000000ffe63fff: RAM
9470 05:52:51.131128 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9471 05:52:51.134404 7. 0000000100000000-000000023fffffff: RAM
9472 05:52:51.137211 Passing 5 GPIOs to payload:
9473 05:52:51.140691 NAME | PORT | POLARITY | VALUE
9474 05:52:51.147460 EC in RW | 0x000000aa | low | undefined
9475 05:52:51.150898 EC interrupt | 0x00000005 | low | undefined
9476 05:52:51.154029 TPM interrupt | 0x000000ab | high | undefined
9477 05:52:51.161126 SD card detect | 0x00000011 | high | undefined
9478 05:52:51.164110 speaker enable | 0x00000093 | high | undefined
9479 05:52:51.167693 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9480 05:52:51.170463 in-header: 03 f9 00 00 02 00 00 00
9481 05:52:51.174017 in-data: 02 00
9482 05:52:51.177682 ADC[4]: Raw value=896300 ID=7
9483 05:52:51.177764 ADC[3]: Raw value=213070 ID=1
9484 05:52:51.180639 RAM Code: 0x71
9485 05:52:51.183688 ADC[6]: Raw value=74722 ID=0
9486 05:52:51.183769 ADC[5]: Raw value=212330 ID=1
9487 05:52:51.187280 SKU Code: 0x1
9488 05:52:51.190890 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4d57
9489 05:52:51.193998 coreboot table: 964 bytes.
9490 05:52:51.196984 IMD ROOT 0. 0xfffff000 0x00001000
9491 05:52:51.200557 IMD SMALL 1. 0xffffe000 0x00001000
9492 05:52:51.204112 RO MCACHE 2. 0xffffc000 0x00001104
9493 05:52:51.207143 CONSOLE 3. 0xfff7c000 0x00080000
9494 05:52:51.210528 FMAP 4. 0xfff7b000 0x00000452
9495 05:52:51.213703 TIME STAMP 5. 0xfff7a000 0x00000910
9496 05:52:51.216946 VBOOT WORK 6. 0xfff66000 0x00014000
9497 05:52:51.220430 RAMOOPS 7. 0xffe66000 0x00100000
9498 05:52:51.223819 COREBOOT 8. 0xffe64000 0x00002000
9499 05:52:51.226740 IMD small region:
9500 05:52:51.230425 IMD ROOT 0. 0xffffec00 0x00000400
9501 05:52:51.233366 VPD 1. 0xffffeb80 0x0000006c
9502 05:52:51.236928 MMC STATUS 2. 0xffffeb60 0x00000004
9503 05:52:51.240426 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9504 05:52:51.243647 Probing TPM: done!
9505 05:52:51.247118 Connected to device vid:did:rid of 1ae0:0028:00
9506 05:52:51.258085 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9507 05:52:51.260888 Initialized TPM device CR50 revision 0
9508 05:52:51.264787 Checking cr50 for pending updates
9509 05:52:51.268658 Reading cr50 TPM mode
9510 05:52:51.276806 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9511 05:52:51.283216 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9512 05:52:51.324055 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9513 05:52:51.327313 Checking segment from ROM address 0x40100000
9514 05:52:51.330453 Checking segment from ROM address 0x4010001c
9515 05:52:51.337108 Loading segment from ROM address 0x40100000
9516 05:52:51.337193 code (compression=0)
9517 05:52:51.347301 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9518 05:52:51.353724 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9519 05:52:51.353830 it's not compressed!
9520 05:52:51.360240 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9521 05:52:51.363773 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9522 05:52:51.384324 Loading segment from ROM address 0x4010001c
9523 05:52:51.384410 Entry Point 0x80000000
9524 05:52:51.387572 Loaded segments
9525 05:52:51.391200 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9526 05:52:51.397228 Jumping to boot code at 0x80000000(0xffe64000)
9527 05:52:51.404300 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9528 05:52:51.410928 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9529 05:52:51.418691 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9530 05:52:51.422215 Checking segment from ROM address 0x40100000
9531 05:52:51.425168 Checking segment from ROM address 0x4010001c
9532 05:52:51.431849 Loading segment from ROM address 0x40100000
9533 05:52:51.431931 code (compression=1)
9534 05:52:51.439148 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9535 05:52:51.449263 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9536 05:52:51.449917 using LZMA
9537 05:52:51.457604 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9538 05:52:51.464197 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9539 05:52:51.467670 Loading segment from ROM address 0x4010001c
9540 05:52:51.468132 Entry Point 0x54601000
9541 05:52:51.471020 Loaded segments
9542 05:52:51.474084 NOTICE: MT8192 bl31_setup
9543 05:52:51.481267 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9544 05:52:51.484634 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9545 05:52:51.488093 WARNING: region 0:
9546 05:52:51.491627 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9547 05:52:51.492158 WARNING: region 1:
9548 05:52:51.497606 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9549 05:52:51.501124 WARNING: region 2:
9550 05:52:51.504107 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9551 05:52:51.507759 WARNING: region 3:
9552 05:52:51.510855 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9553 05:52:51.514433 WARNING: region 4:
9554 05:52:51.520882 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9555 05:52:51.521338 WARNING: region 5:
9556 05:52:51.524563 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9557 05:52:51.527584 WARNING: region 6:
9558 05:52:51.530925 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9559 05:52:51.534586 WARNING: region 7:
9560 05:52:51.537560 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9561 05:52:51.544182 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9562 05:52:51.547909 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9563 05:52:51.551066 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9564 05:52:51.557840 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9565 05:52:51.560682 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9566 05:52:51.564849 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9567 05:52:51.571210 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9568 05:52:51.574040 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9569 05:52:51.580547 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9570 05:52:51.583887 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9571 05:52:51.587306 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9572 05:52:51.594082 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9573 05:52:51.597418 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9574 05:52:51.600805 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9575 05:52:51.607103 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9576 05:52:51.610848 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9577 05:52:51.617649 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9578 05:52:51.620785 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9579 05:52:51.624364 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9580 05:52:51.630783 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9581 05:52:51.633744 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9582 05:52:51.640926 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9583 05:52:51.643780 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9584 05:52:51.647527 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9585 05:52:51.654036 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9586 05:52:51.657278 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9587 05:52:51.663884 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9588 05:52:51.667234 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9589 05:52:51.670428 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9590 05:52:51.677089 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9591 05:52:51.680359 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9592 05:52:51.686847 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9593 05:52:51.690539 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9594 05:52:51.694062 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9595 05:52:51.697128 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9596 05:52:51.700104 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9597 05:52:51.706832 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9598 05:52:51.710495 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9599 05:52:51.713574 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9600 05:52:51.717042 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9601 05:52:51.723965 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9602 05:52:51.726930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9603 05:52:51.730616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9604 05:52:51.733604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9605 05:52:51.740584 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9606 05:52:51.743775 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9607 05:52:51.746878 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9608 05:52:51.754055 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9609 05:52:51.756905 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9610 05:52:51.760587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9611 05:52:51.767129 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9612 05:52:51.770416 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9613 05:52:51.777109 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9614 05:52:51.780969 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9615 05:52:51.784064 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9616 05:52:51.791057 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9617 05:52:51.793738 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9618 05:52:51.800444 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9619 05:52:51.803993 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9620 05:52:51.811074 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9621 05:52:51.813831 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9622 05:52:51.817829 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9623 05:52:51.824155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9624 05:52:51.827496 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9625 05:52:51.833901 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9626 05:52:51.837194 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9627 05:52:51.843984 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9628 05:52:51.847321 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9629 05:52:51.854071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9630 05:52:51.857295 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9631 05:52:51.860696 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9632 05:52:51.867370 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9633 05:52:51.870466 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9634 05:52:51.877289 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9635 05:52:51.880529 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9636 05:52:51.887781 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9637 05:52:51.890682 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9638 05:52:51.894262 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9639 05:52:51.900816 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9640 05:52:51.904362 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9641 05:52:51.910470 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9642 05:52:51.914020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9643 05:52:51.920579 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9644 05:52:51.923982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9645 05:52:51.927390 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9646 05:52:51.934067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9647 05:52:51.937699 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9648 05:52:51.943935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9649 05:52:51.947377 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9650 05:52:51.953695 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9651 05:52:51.957111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9652 05:52:51.960840 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9653 05:52:51.967101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9654 05:52:51.970333 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9655 05:52:51.977214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9656 05:52:51.980346 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9657 05:52:51.983961 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9658 05:52:51.990455 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9659 05:52:51.993770 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9660 05:52:51.996778 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9661 05:52:52.000002 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9662 05:52:52.006621 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9663 05:52:52.010324 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9664 05:52:52.016854 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9665 05:52:52.020456 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9666 05:52:52.023508 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9667 05:52:52.030267 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9668 05:52:52.033881 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9669 05:52:52.040432 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9670 05:52:52.043872 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9671 05:52:52.047425 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9672 05:52:52.054103 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9673 05:52:52.057089 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9674 05:52:52.063860 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9675 05:52:52.066861 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9676 05:52:52.070723 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9677 05:52:52.076981 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9678 05:52:52.080342 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9679 05:52:52.083491 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9680 05:52:52.090784 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9681 05:52:52.093689 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9682 05:52:52.097126 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9683 05:52:52.100323 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9684 05:52:52.103788 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9685 05:52:52.110195 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9686 05:52:52.113643 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9687 05:52:52.120178 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9688 05:52:52.124146 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9689 05:52:52.126812 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9690 05:52:52.133393 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9691 05:52:52.137680 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9692 05:52:52.143895 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9693 05:52:52.146934 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9694 05:52:52.150303 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9695 05:52:52.156925 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9696 05:52:52.160519 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9697 05:52:52.166746 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9698 05:52:52.170273 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9699 05:52:52.173417 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9700 05:52:52.180138 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9701 05:52:52.183744 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9702 05:52:52.190143 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9703 05:52:52.193148 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9704 05:52:52.196908 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9705 05:52:52.203318 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9706 05:52:52.206850 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9707 05:52:52.210126 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9708 05:52:52.216776 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9709 05:52:52.219965 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9710 05:52:52.226767 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9711 05:52:52.230351 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9712 05:52:52.233301 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9713 05:52:52.240023 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9714 05:52:52.243478 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9715 05:52:52.250407 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9716 05:52:52.253516 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9717 05:52:52.256785 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9718 05:52:52.263593 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9719 05:52:52.266856 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9720 05:52:52.269980 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9721 05:52:52.277069 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9722 05:52:52.279953 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9723 05:52:52.286534 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9724 05:52:52.290085 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9725 05:52:52.292838 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9726 05:52:52.299658 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9727 05:52:52.303232 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9728 05:52:52.309935 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9729 05:52:52.312920 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9730 05:52:52.316362 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9731 05:52:52.323277 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9732 05:52:52.326178 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9733 05:52:52.332810 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9734 05:52:52.336321 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9735 05:52:52.339436 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9736 05:52:52.346038 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9737 05:52:52.349506 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9738 05:52:52.356222 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9739 05:52:52.359016 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9740 05:52:52.362868 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9741 05:52:52.369800 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9742 05:52:52.372590 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9743 05:52:52.379141 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9744 05:52:52.382146 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9745 05:52:52.385823 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9746 05:52:52.392234 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9747 05:52:52.395649 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9748 05:52:52.402102 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9749 05:52:52.405402 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9750 05:52:52.408954 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9751 05:52:52.415604 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9752 05:52:52.418971 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9753 05:52:52.425764 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9754 05:52:52.428621 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9755 05:52:52.435037 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9756 05:52:52.438492 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9757 05:52:52.441634 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9758 05:52:52.448325 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9759 05:52:52.451614 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9760 05:52:52.458099 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9761 05:52:52.461836 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9762 05:52:52.468898 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9763 05:52:52.471683 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9764 05:52:52.474683 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9765 05:52:52.481272 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9766 05:52:52.484852 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9767 05:52:52.491367 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9768 05:52:52.495314 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9769 05:52:52.498107 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9770 05:52:52.504504 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9771 05:52:52.508106 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9772 05:52:52.514765 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9773 05:52:52.517802 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9774 05:52:52.524638 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9775 05:52:52.528321 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9776 05:52:52.531050 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9777 05:52:52.537717 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9778 05:52:52.540963 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9779 05:52:52.547624 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9780 05:52:52.551363 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9781 05:52:52.557937 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9782 05:52:52.561030 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9783 05:52:52.563840 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9784 05:52:52.570501 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9785 05:52:52.574091 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9786 05:52:52.580597 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9787 05:52:52.584506 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9788 05:52:52.590683 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9789 05:52:52.593973 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9790 05:52:52.597670 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9791 05:52:52.600716 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9792 05:52:52.606999 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9793 05:52:52.610375 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9794 05:52:52.614249 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9795 05:52:52.617310 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9796 05:52:52.624058 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9797 05:52:52.627144 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9798 05:52:52.633545 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9799 05:52:52.637191 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9800 05:52:52.640499 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9801 05:52:52.646925 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9802 05:52:52.650420 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9803 05:52:52.653894 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9804 05:52:52.659989 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9805 05:52:52.663440 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9806 05:52:52.669743 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9807 05:52:52.673169 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9808 05:52:52.676160 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9809 05:52:52.683030 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9810 05:52:52.686389 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9811 05:52:52.689578 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9812 05:52:52.696529 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9813 05:52:52.699796 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9814 05:52:52.702628 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9815 05:52:52.710319 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9816 05:52:52.713058 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9817 05:52:52.719622 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9818 05:52:52.723012 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9819 05:52:52.726083 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9820 05:52:52.732588 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9821 05:52:52.736297 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9822 05:52:52.742764 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9823 05:52:52.745793 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9824 05:52:52.749357 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9825 05:52:52.756265 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9826 05:52:52.759833 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9827 05:52:52.763050 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9828 05:52:52.769551 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9829 05:52:52.772255 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9830 05:52:52.775843 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9831 05:52:52.779359 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9832 05:52:52.785674 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9833 05:52:52.789398 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9834 05:52:52.792715 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9835 05:52:52.795676 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9836 05:52:52.802466 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9837 05:52:52.805961 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9838 05:52:52.809318 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9839 05:52:52.812285 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9840 05:52:52.819010 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9841 05:52:52.821997 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9842 05:52:52.825521 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9843 05:52:52.832386 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9844 05:52:52.835138 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9845 05:52:52.842003 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9846 05:52:52.844779 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9847 05:52:52.848500 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9848 05:52:52.855117 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9849 05:52:52.858243 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9850 05:52:52.864834 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9851 05:52:52.868509 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9852 05:52:52.871574 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9853 05:52:52.878021 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9854 05:52:52.881535 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9855 05:52:52.888008 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9856 05:52:52.891648 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9857 05:52:52.898068 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9858 05:52:52.901510 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9859 05:52:52.905014 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9860 05:52:52.911485 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9861 05:52:52.914437 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9862 05:52:52.921749 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9863 05:52:52.924760 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9864 05:52:52.928102 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9865 05:52:52.934997 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9866 05:52:52.937943 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9867 05:52:52.944737 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9868 05:52:52.947830 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9869 05:52:52.951141 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9870 05:52:52.958385 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9871 05:52:52.961054 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9872 05:52:52.967677 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9873 05:52:52.971417 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9874 05:52:52.974346 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9875 05:52:52.981060 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9876 05:52:52.984354 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9877 05:52:52.990957 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9878 05:52:52.994061 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9879 05:52:53.000778 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9880 05:52:53.004046 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9881 05:52:53.007564 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9882 05:52:53.014016 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9883 05:52:53.017468 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9884 05:52:53.024056 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9885 05:52:53.026973 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9886 05:52:53.034072 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9887 05:52:53.036909 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9888 05:52:53.040608 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9889 05:52:53.046986 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9890 05:52:53.050717 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9891 05:52:53.053921 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9892 05:52:53.060317 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9893 05:52:53.063693 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9894 05:52:53.070276 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9895 05:52:53.073806 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9896 05:52:53.080302 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9897 05:52:53.083257 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9898 05:52:53.086844 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9899 05:52:53.093338 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9900 05:52:53.096804 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9901 05:52:53.103616 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9902 05:52:53.107036 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9903 05:52:53.110059 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9904 05:52:53.117117 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9905 05:52:53.119947 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9906 05:52:53.126692 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9907 05:52:53.130000 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9908 05:52:53.133429 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9909 05:52:53.139693 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9910 05:52:53.143330 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9911 05:52:53.149880 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9912 05:52:53.153462 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9913 05:52:53.159945 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9914 05:52:53.163371 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9915 05:52:53.166579 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9916 05:52:53.172682 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9917 05:52:53.176679 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9918 05:52:53.182644 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9919 05:52:53.186247 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9920 05:52:53.192987 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9921 05:52:53.196452 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9922 05:52:53.199857 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9923 05:52:53.205964 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9924 05:52:53.209764 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9925 05:52:53.215979 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9926 05:52:53.219471 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9927 05:52:53.226066 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9928 05:52:53.229095 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9929 05:52:53.235862 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9930 05:52:53.239112 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9931 05:52:53.242206 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9932 05:52:53.249420 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9933 05:52:53.252477 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9934 05:52:53.259223 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9935 05:52:53.262295 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9936 05:52:53.269323 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9937 05:52:53.272374 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9938 05:52:53.275981 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9939 05:52:53.282126 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9940 05:52:53.285714 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9941 05:52:53.292695 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9942 05:52:53.296056 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9943 05:52:53.302198 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9944 05:52:53.305893 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9945 05:52:53.312096 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9946 05:52:53.315939 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9947 05:52:53.318763 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9948 05:52:53.325744 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9949 05:52:53.328566 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9950 05:52:53.335572 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9951 05:52:53.339049 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9952 05:52:53.345573 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9953 05:52:53.348963 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9954 05:52:53.351849 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9955 05:52:53.358473 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9956 05:52:53.362052 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9957 05:52:53.368408 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9958 05:52:53.371998 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9959 05:52:53.378519 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9960 05:52:53.382134 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9961 05:52:53.388316 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9962 05:52:53.391793 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9963 05:52:53.395109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9964 05:52:53.401162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9965 05:52:53.405250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9966 05:52:53.411594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9967 05:52:53.414532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9968 05:52:53.421804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9969 05:52:53.424623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9970 05:52:53.431411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9971 05:52:53.434840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9972 05:52:53.441449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9973 05:52:53.444360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9974 05:52:53.451232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9975 05:52:53.454796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9976 05:52:53.457650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9977 05:52:53.464316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9978 05:52:53.467819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9979 05:52:53.474579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9980 05:52:53.477368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9981 05:52:53.483817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9982 05:52:53.487356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9983 05:52:53.493942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9984 05:52:53.497073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9985 05:52:53.503652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9986 05:52:53.507388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9987 05:52:53.513896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9988 05:52:53.517263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9989 05:52:53.523611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9990 05:52:53.526986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9991 05:52:53.533947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9992 05:52:53.537262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9993 05:52:53.543671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9994 05:52:53.547245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9995 05:52:53.553634 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9996 05:52:53.553729 INFO: [APUAPC] vio 0
9997 05:52:53.560683 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9998 05:52:53.564100 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9999 05:52:53.567093 INFO: [APUAPC] D0_APC_0: 0x400510
10000 05:52:53.570717 INFO: [APUAPC] D0_APC_1: 0x0
10001 05:52:53.573691 INFO: [APUAPC] D0_APC_2: 0x1540
10002 05:52:53.577201 INFO: [APUAPC] D0_APC_3: 0x0
10003 05:52:53.580619 INFO: [APUAPC] D1_APC_0: 0xffffffff
10004 05:52:53.583622 INFO: [APUAPC] D1_APC_1: 0xffffffff
10005 05:52:53.587147 INFO: [APUAPC] D1_APC_2: 0x3fffff
10006 05:52:53.590159 INFO: [APUAPC] D1_APC_3: 0x0
10007 05:52:53.593681 INFO: [APUAPC] D2_APC_0: 0xffffffff
10008 05:52:53.596757 INFO: [APUAPC] D2_APC_1: 0xffffffff
10009 05:52:53.600422 INFO: [APUAPC] D2_APC_2: 0x3fffff
10010 05:52:53.603427 INFO: [APUAPC] D2_APC_3: 0x0
10011 05:52:53.607034 INFO: [APUAPC] D3_APC_0: 0xffffffff
10012 05:52:53.610587 INFO: [APUAPC] D3_APC_1: 0xffffffff
10013 05:52:53.613558 INFO: [APUAPC] D3_APC_2: 0x3fffff
10014 05:52:53.616691 INFO: [APUAPC] D3_APC_3: 0x0
10015 05:52:53.620122 INFO: [APUAPC] D4_APC_0: 0xffffffff
10016 05:52:53.623528 INFO: [APUAPC] D4_APC_1: 0xffffffff
10017 05:52:53.626540 INFO: [APUAPC] D4_APC_2: 0x3fffff
10018 05:52:53.626623 INFO: [APUAPC] D4_APC_3: 0x0
10019 05:52:53.633619 INFO: [APUAPC] D5_APC_0: 0xffffffff
10020 05:52:53.636664 INFO: [APUAPC] D5_APC_1: 0xffffffff
10021 05:52:53.640191 INFO: [APUAPC] D5_APC_2: 0x3fffff
10022 05:52:53.640278 INFO: [APUAPC] D5_APC_3: 0x0
10023 05:52:53.643124 INFO: [APUAPC] D6_APC_0: 0xffffffff
10024 05:52:53.646652 INFO: [APUAPC] D6_APC_1: 0xffffffff
10025 05:52:53.649954 INFO: [APUAPC] D6_APC_2: 0x3fffff
10026 05:52:53.653596 INFO: [APUAPC] D6_APC_3: 0x0
10027 05:52:53.657025 INFO: [APUAPC] D7_APC_0: 0xffffffff
10028 05:52:53.660084 INFO: [APUAPC] D7_APC_1: 0xffffffff
10029 05:52:53.663484 INFO: [APUAPC] D7_APC_2: 0x3fffff
10030 05:52:53.666864 INFO: [APUAPC] D7_APC_3: 0x0
10031 05:52:53.669917 INFO: [APUAPC] D8_APC_0: 0xffffffff
10032 05:52:53.673626 INFO: [APUAPC] D8_APC_1: 0xffffffff
10033 05:52:53.676667 INFO: [APUAPC] D8_APC_2: 0x3fffff
10034 05:52:53.680413 INFO: [APUAPC] D8_APC_3: 0x0
10035 05:52:53.683341 INFO: [APUAPC] D9_APC_0: 0xffffffff
10036 05:52:53.686816 INFO: [APUAPC] D9_APC_1: 0xffffffff
10037 05:52:53.689779 INFO: [APUAPC] D9_APC_2: 0x3fffff
10038 05:52:53.693263 INFO: [APUAPC] D9_APC_3: 0x0
10039 05:52:53.696393 INFO: [APUAPC] D10_APC_0: 0xffffffff
10040 05:52:53.700048 INFO: [APUAPC] D10_APC_1: 0xffffffff
10041 05:52:53.703080 INFO: [APUAPC] D10_APC_2: 0x3fffff
10042 05:52:53.706668 INFO: [APUAPC] D10_APC_3: 0x0
10043 05:52:53.709815 INFO: [APUAPC] D11_APC_0: 0xffffffff
10044 05:52:53.713230 INFO: [APUAPC] D11_APC_1: 0xffffffff
10045 05:52:53.716306 INFO: [APUAPC] D11_APC_2: 0x3fffff
10046 05:52:53.719845 INFO: [APUAPC] D11_APC_3: 0x0
10047 05:52:53.722959 INFO: [APUAPC] D12_APC_0: 0xffffffff
10048 05:52:53.726408 INFO: [APUAPC] D12_APC_1: 0xffffffff
10049 05:52:53.729371 INFO: [APUAPC] D12_APC_2: 0x3fffff
10050 05:52:53.733002 INFO: [APUAPC] D12_APC_3: 0x0
10051 05:52:53.735946 INFO: [APUAPC] D13_APC_0: 0xffffffff
10052 05:52:53.739301 INFO: [APUAPC] D13_APC_1: 0xffffffff
10053 05:52:53.742788 INFO: [APUAPC] D13_APC_2: 0x3fffff
10054 05:52:53.745846 INFO: [APUAPC] D13_APC_3: 0x0
10055 05:52:53.749444 INFO: [APUAPC] D14_APC_0: 0xffffffff
10056 05:52:53.752503 INFO: [APUAPC] D14_APC_1: 0xffffffff
10057 05:52:53.755906 INFO: [APUAPC] D14_APC_2: 0x3fffff
10058 05:52:53.759373 INFO: [APUAPC] D14_APC_3: 0x0
10059 05:52:53.762317 INFO: [APUAPC] D15_APC_0: 0xffffffff
10060 05:52:53.765868 INFO: [APUAPC] D15_APC_1: 0xffffffff
10061 05:52:53.769259 INFO: [APUAPC] D15_APC_2: 0x3fffff
10062 05:52:53.772506 INFO: [APUAPC] D15_APC_3: 0x0
10063 05:52:53.776075 INFO: [APUAPC] APC_CON: 0x4
10064 05:52:53.779042 INFO: [NOCDAPC] D0_APC_0: 0x0
10065 05:52:53.782415 INFO: [NOCDAPC] D0_APC_1: 0x0
10066 05:52:53.786123 INFO: [NOCDAPC] D1_APC_0: 0x0
10067 05:52:53.789127 INFO: [NOCDAPC] D1_APC_1: 0xfff
10068 05:52:53.792415 INFO: [NOCDAPC] D2_APC_0: 0x0
10069 05:52:53.795431 INFO: [NOCDAPC] D2_APC_1: 0xfff
10070 05:52:53.795516 INFO: [NOCDAPC] D3_APC_0: 0x0
10071 05:52:53.799158 INFO: [NOCDAPC] D3_APC_1: 0xfff
10072 05:52:53.802103 INFO: [NOCDAPC] D4_APC_0: 0x0
10073 05:52:53.805713 INFO: [NOCDAPC] D4_APC_1: 0xfff
10074 05:52:53.808828 INFO: [NOCDAPC] D5_APC_0: 0x0
10075 05:52:53.811908 INFO: [NOCDAPC] D5_APC_1: 0xfff
10076 05:52:53.815483 INFO: [NOCDAPC] D6_APC_0: 0x0
10077 05:52:53.819148 INFO: [NOCDAPC] D6_APC_1: 0xfff
10078 05:52:53.822233 INFO: [NOCDAPC] D7_APC_0: 0x0
10079 05:52:53.825177 INFO: [NOCDAPC] D7_APC_1: 0xfff
10080 05:52:53.828600 INFO: [NOCDAPC] D8_APC_0: 0x0
10081 05:52:53.832118 INFO: [NOCDAPC] D8_APC_1: 0xfff
10082 05:52:53.832203 INFO: [NOCDAPC] D9_APC_0: 0x0
10083 05:52:53.835098 INFO: [NOCDAPC] D9_APC_1: 0xfff
10084 05:52:53.838681 INFO: [NOCDAPC] D10_APC_0: 0x0
10085 05:52:53.842279 INFO: [NOCDAPC] D10_APC_1: 0xfff
10086 05:52:53.845344 INFO: [NOCDAPC] D11_APC_0: 0x0
10087 05:52:53.848904 INFO: [NOCDAPC] D11_APC_1: 0xfff
10088 05:52:53.851806 INFO: [NOCDAPC] D12_APC_0: 0x0
10089 05:52:53.855429 INFO: [NOCDAPC] D12_APC_1: 0xfff
10090 05:52:53.858575 INFO: [NOCDAPC] D13_APC_0: 0x0
10091 05:52:53.861596 INFO: [NOCDAPC] D13_APC_1: 0xfff
10092 05:52:53.864965 INFO: [NOCDAPC] D14_APC_0: 0x0
10093 05:52:53.868390 INFO: [NOCDAPC] D14_APC_1: 0xfff
10094 05:52:53.871937 INFO: [NOCDAPC] D15_APC_0: 0x0
10095 05:52:53.874952 INFO: [NOCDAPC] D15_APC_1: 0xfff
10096 05:52:53.875036 INFO: [NOCDAPC] APC_CON: 0x4
10097 05:52:53.878041 INFO: [APUAPC] set_apusys_apc done
10098 05:52:53.881662 INFO: [DEVAPC] devapc_init done
10099 05:52:53.888264 INFO: GICv3 without legacy support detected.
10100 05:52:53.891571 INFO: ARM GICv3 driver initialized in EL3
10101 05:52:53.894935 INFO: Maximum SPI INTID supported: 639
10102 05:52:53.898333 INFO: BL31: Initializing runtime services
10103 05:52:53.905094 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10104 05:52:53.908217 INFO: SPM: enable CPC mode
10105 05:52:53.911211 INFO: mcdi ready for mcusys-off-idle and system suspend
10106 05:52:53.917855 INFO: BL31: Preparing for EL3 exit to normal world
10107 05:52:53.921357 INFO: Entry point address = 0x80000000
10108 05:52:53.921442 INFO: SPSR = 0x8
10109 05:52:53.928482
10110 05:52:53.928565
10111 05:52:53.928635
10112 05:52:53.932193 Starting depthcharge on Spherion...
10113 05:52:53.932276
10114 05:52:53.932341 Wipe memory regions:
10115 05:52:53.932413
10116 05:52:53.933189 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10117 05:52:53.933290 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10118 05:52:53.933382 Setting prompt string to ['asurada:']
10119 05:52:53.933521 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10120 05:52:53.935112 [0x00000040000000, 0x00000054600000)
10121 05:52:54.057430
10122 05:52:54.057602 [0x00000054660000, 0x00000080000000)
10123 05:52:54.318443
10124 05:52:54.318582 [0x000000821a7280, 0x000000ffe64000)
10125 05:52:55.063007
10126 05:52:55.063139 [0x00000100000000, 0x00000240000000)
10127 05:52:56.953042
10128 05:52:56.956604 Initializing XHCI USB controller at 0x11200000.
10129 05:52:57.994215
10130 05:52:57.997382 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10131 05:52:57.997470
10132 05:52:57.997576
10133 05:52:57.997638
10134 05:52:57.997920 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10136 05:52:58.098284 asurada: tftpboot 192.168.201.1 12379416/tftp-deploy-v3ap0rf0/kernel/image.itb 12379416/tftp-deploy-v3ap0rf0/kernel/cmdline
10137 05:52:58.098441 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10138 05:52:58.098530 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10139 05:52:58.103262 tftpboot 192.168.201.1 12379416/tftp-deploy-v3ap0rf0/kernel/image.itp-deploy-v3ap0rf0/kernel/cmdline
10140 05:52:58.103348
10141 05:52:58.103414 Waiting for link
10142 05:52:58.263675
10143 05:52:58.263840 R8152: Initializing
10144 05:52:58.263936
10145 05:52:58.266786 Version 6 (ocp_data = 5c30)
10146 05:52:58.266896
10147 05:52:58.270474 R8152: Done initializing
10148 05:52:58.270547
10149 05:52:58.270609 Adding net device
10150 05:53:00.173640
10151 05:53:00.173837 done.
10152 05:53:00.173981
10153 05:53:00.174086 MAC: 00:24:32:30:78:ff
10154 05:53:00.174192
10155 05:53:00.176768 Sending DHCP discover... done.
10156 05:53:00.176885
10157 05:53:00.180302 Waiting for reply... done.
10158 05:53:00.180423
10159 05:53:00.183256 Sending DHCP request... done.
10160 05:53:00.183365
10161 05:53:00.188159 Waiting for reply... done.
10162 05:53:00.188277
10163 05:53:00.188385 My ip is 192.168.201.21
10164 05:53:00.188489
10165 05:53:00.191248 The DHCP server ip is 192.168.201.1
10166 05:53:00.191335
10167 05:53:00.198187 TFTP server IP predefined by user: 192.168.201.1
10168 05:53:00.198313
10169 05:53:00.205086 Bootfile predefined by user: 12379416/tftp-deploy-v3ap0rf0/kernel/image.itb
10170 05:53:00.205200
10171 05:53:00.205347 Sending tftp read request... done.
10172 05:53:00.207787
10173 05:53:00.212209 Waiting for the transfer...
10174 05:53:00.212365
10175 05:53:00.767542 00000000 ################################################################
10176 05:53:00.767687
10177 05:53:01.346294 00080000 ################################################################
10178 05:53:01.346440
10179 05:53:01.923351 00100000 ################################################################
10180 05:53:01.923494
10181 05:53:02.533971 00180000 ################################################################
10182 05:53:02.534157
10183 05:53:03.064717 00200000 ################################################################
10184 05:53:03.064879
10185 05:53:03.635282 00280000 ################################################################
10186 05:53:03.635429
10187 05:53:04.209796 00300000 ################################################################
10188 05:53:04.209954
10189 05:53:04.796725 00380000 ################################################################
10190 05:53:04.796902
10191 05:53:05.381331 00400000 ################################################################
10192 05:53:05.381525
10193 05:53:05.974063 00480000 ################################################################
10194 05:53:05.974210
10195 05:53:06.559076 00500000 ################################################################
10196 05:53:06.559498
10197 05:53:07.210744 00580000 ################################################################
10198 05:53:07.210901
10199 05:53:07.871667 00600000 ################################################################
10200 05:53:07.872154
10201 05:53:08.528853 00680000 ################################################################
10202 05:53:08.530093
10203 05:53:09.094802 00700000 ################################################################
10204 05:53:09.094952
10205 05:53:09.650304 00780000 ################################################################
10206 05:53:09.650518
10207 05:53:10.291623 00800000 ################################################################
10208 05:53:10.292172
10209 05:53:10.954457 00880000 ################################################################
10210 05:53:10.954989
10211 05:53:11.630560 00900000 ################################################################
10212 05:53:11.631086
10213 05:53:12.310427 00980000 ################################################################
10214 05:53:12.311013
10215 05:53:12.998336 00a00000 ################################################################
10216 05:53:12.998853
10217 05:53:13.688833 00a80000 ################################################################
10218 05:53:13.689032
10219 05:53:14.417175 00b00000 ################################################################
10220 05:53:14.417747
10221 05:53:15.070872 00b80000 ################################################################
10222 05:53:15.071426
10223 05:53:15.781578 00c00000 ################################################################
10224 05:53:15.782067
10225 05:53:16.487552 00c80000 ################################################################
10226 05:53:16.487778
10227 05:53:17.151764 00d00000 ################################################################
10228 05:53:17.152142
10229 05:53:17.695051 00d80000 ################################################################
10230 05:53:17.695182
10231 05:53:18.385421 00e00000 ################################################################
10232 05:53:18.385951
10233 05:53:19.084753 00e80000 ################################################################
10234 05:53:19.085251
10235 05:53:19.755171 00f00000 ################################################################
10236 05:53:19.755683
10237 05:53:20.346420 00f80000 ################################################################
10238 05:53:20.346956
10239 05:53:21.049504 01000000 ################################################################
10240 05:53:21.049875
10241 05:53:21.776075 01080000 ################################################################
10242 05:53:21.776588
10243 05:53:22.432559 01100000 ################################################################
10244 05:53:22.432749
10245 05:53:23.102887 01180000 ################################################################
10246 05:53:23.103401
10247 05:53:23.714793 01200000 ################################################################
10248 05:53:23.714932
10249 05:53:24.380041 01280000 ################################################################
10250 05:53:24.380552
10251 05:53:25.113804 01300000 ################################################################
10252 05:53:25.114306
10253 05:53:25.853353 01380000 ################################################################
10254 05:53:25.853963
10255 05:53:26.587596 01400000 ################################################################
10256 05:53:26.588136
10257 05:53:27.307134 01480000 ################################################################
10258 05:53:27.307646
10259 05:53:28.005156 01500000 ################################################################
10260 05:53:28.005742
10261 05:53:28.696528 01580000 ################################################################
10262 05:53:28.696747
10263 05:53:29.399052 01600000 ################################################################
10264 05:53:29.399862
10265 05:53:30.097190 01680000 ################################################################
10266 05:53:30.097794
10267 05:53:30.794457 01700000 ################################################################
10268 05:53:30.794683
10269 05:53:31.441561 01780000 ################################################################
10270 05:53:31.442063
10271 05:53:32.147067 01800000 ################################################################
10272 05:53:32.147564
10273 05:53:32.763314 01880000 ################################################################
10274 05:53:32.763474
10275 05:53:33.336464 01900000 ################################################################
10276 05:53:33.336613
10277 05:53:33.902120 01980000 ################################################################
10278 05:53:33.902275
10279 05:53:34.465894 01a00000 ################################################################
10280 05:53:34.466040
10281 05:53:35.040440 01a80000 ################################################################
10282 05:53:35.040605
10283 05:53:35.616255 01b00000 ################################################################
10284 05:53:35.616392
10285 05:53:36.147053 01b80000 ############################################################# done.
10286 05:53:36.147189
10287 05:53:36.150522 The bootfile was 29330238 bytes long.
10288 05:53:36.150607
10289 05:53:36.150672 Sending tftp read request... done.
10290 05:53:36.153899
10291 05:53:36.153982 Waiting for the transfer...
10292 05:53:36.154047
10293 05:53:36.157260 00000000 # done.
10294 05:53:36.157342
10295 05:53:36.164033 Command line loaded dynamically from TFTP file: 12379416/tftp-deploy-v3ap0rf0/kernel/cmdline
10296 05:53:36.164118
10297 05:53:36.186848 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12379416/extract-nfsrootfs-69r2xshf,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10298 05:53:36.186959
10299 05:53:36.187025 Loading FIT.
10300 05:53:36.187085
10301 05:53:36.190464 Image ramdisk-1 has 17799094 bytes.
10302 05:53:36.190546
10303 05:53:36.193578 Image fdt-1 has 47278 bytes.
10304 05:53:36.193659
10305 05:53:36.197027 Image kernel-1 has 11481830 bytes.
10306 05:53:36.197108
10307 05:53:36.206476 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10308 05:53:36.206559
10309 05:53:36.223130 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10310 05:53:36.223226
10311 05:53:36.226940 Choosing best match conf-1 for compat google,spherion-rev2.
10312 05:53:36.232018
10313 05:53:36.236703 Connected to device vid:did:rid of 1ae0:0028:00
10314 05:53:36.245377
10315 05:53:36.248241 tpm_get_response: command 0x17b, return code 0x0
10316 05:53:36.248323
10317 05:53:36.251755 ec_init: CrosEC protocol v3 supported (256, 248)
10318 05:53:36.255724
10319 05:53:36.258746 tpm_cleanup: add release locality here.
10320 05:53:36.258828
10321 05:53:36.258893 Shutting down all USB controllers.
10322 05:53:36.261973
10323 05:53:36.262054 Removing current net device
10324 05:53:36.262119
10325 05:53:36.268820 Exiting depthcharge with code 4 at timestamp: 71687485
10326 05:53:36.268902
10327 05:53:36.272359 LZMA decompressing kernel-1 to 0x821a6718
10328 05:53:36.272466
10329 05:53:36.275516 LZMA decompressing kernel-1 to 0x40000000
10330 05:53:37.712063
10331 05:53:37.712217 jumping to kernel
10332 05:53:37.712672 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10333 05:53:37.712775 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10334 05:53:37.712854 Setting prompt string to ['Linux version [0-9]']
10335 05:53:37.712922 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10336 05:53:37.712991 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10337 05:53:37.794254
10338 05:53:37.797472 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10339 05:53:37.800667 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10340 05:53:37.800758 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10341 05:53:37.800830 Setting prompt string to []
10342 05:53:37.800907 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10343 05:53:37.800979 Using line separator: #'\n'#
10344 05:53:37.801040 No login prompt set.
10345 05:53:37.801102 Parsing kernel messages
10346 05:53:37.801161 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10347 05:53:37.801263 [login-action] Waiting for messages, (timeout 00:03:41)
10348 05:53:37.820275 [ 0.000000] Linux version 6.1.67-cip12 (KernelCI@build-j59664-arm64-gcc-10-defconfig-arm64-chromebook-fgc24) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023
10349 05:53:37.823605 [ 0.000000] random: crng init done
10350 05:53:37.830336 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10351 05:53:37.833967 [ 0.000000] efi: UEFI not found.
10352 05:53:37.840018 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10353 05:53:37.846748 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10354 05:53:37.856695 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10355 05:53:37.866468 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10356 05:53:37.873308 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10357 05:53:37.880199 [ 0.000000] printk: bootconsole [mtk8250] enabled
10358 05:53:37.886327 [ 0.000000] NUMA: No NUMA configuration found
10359 05:53:37.893115 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10360 05:53:37.896432 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10361 05:53:37.899295 [ 0.000000] Zone ranges:
10362 05:53:37.906083 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10363 05:53:37.909641 [ 0.000000] DMA32 empty
10364 05:53:37.915879 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10365 05:53:37.919157 [ 0.000000] Movable zone start for each node
10366 05:53:37.922496 [ 0.000000] Early memory node ranges
10367 05:53:37.929216 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10368 05:53:37.935734 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10369 05:53:37.942257 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10370 05:53:37.949180 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10371 05:53:37.955668 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10372 05:53:37.961893 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10373 05:53:38.018569 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10374 05:53:38.024820 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10375 05:53:38.031474 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10376 05:53:38.035066 [ 0.000000] psci: probing for conduit method from DT.
10377 05:53:38.041673 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10378 05:53:38.044429 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10379 05:53:38.051575 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10380 05:53:38.054387 [ 0.000000] psci: SMC Calling Convention v1.2
10381 05:53:38.060948 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10382 05:53:38.064426 [ 0.000000] Detected VIPT I-cache on CPU0
10383 05:53:38.071124 [ 0.000000] CPU features: detected: GIC system register CPU interface
10384 05:53:38.077445 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10385 05:53:38.084390 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10386 05:53:38.090711 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10387 05:53:38.097544 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10388 05:53:38.107738 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10389 05:53:38.110871 [ 0.000000] alternatives: applying boot alternatives
10390 05:53:38.117229 [ 0.000000] Fallback order for Node 0: 0
10391 05:53:38.124137 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10392 05:53:38.127529 [ 0.000000] Policy zone: Normal
10393 05:53:38.150444 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12379416/extract-nfsrootfs-69r2xshf,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10394 05:53:38.160403 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10395 05:53:38.170543 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10396 05:53:38.180477 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10397 05:53:38.187130 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10398 05:53:38.190093 <6>[ 0.000000] software IO TLB: area num 8.
10399 05:53:38.246908 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10400 05:53:38.395784 <6>[ 0.000000] Memory: 7951336K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 401432K reserved, 32768K cma-reserved)
10401 05:53:38.402620 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10402 05:53:38.409164 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10403 05:53:38.412671 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10404 05:53:38.419320 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10405 05:53:38.425533 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10406 05:53:38.429040 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10407 05:53:38.438783 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10408 05:53:38.445652 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10409 05:53:38.451977 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10410 05:53:38.458513 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10411 05:53:38.462104 <6>[ 0.000000] GICv3: 608 SPIs implemented
10412 05:53:38.465452 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10413 05:53:38.471696 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10414 05:53:38.475084 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10415 05:53:38.481763 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10416 05:53:38.495352 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10417 05:53:38.504905 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10418 05:53:38.515398 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10419 05:53:38.522346 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10420 05:53:38.536104 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10421 05:53:38.542249 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10422 05:53:38.549360 <6>[ 0.009184] Console: colour dummy device 80x25
10423 05:53:38.559074 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10424 05:53:38.565795 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10425 05:53:38.569250 <6>[ 0.029222] LSM: Security Framework initializing
10426 05:53:38.575638 <6>[ 0.034160] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10427 05:53:38.585390 <6>[ 0.042022] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10428 05:53:38.592315 <6>[ 0.051431] cblist_init_generic: Setting adjustable number of callback queues.
10429 05:53:38.598597 <6>[ 0.058920] cblist_init_generic: Setting shift to 3 and lim to 1.
10430 05:53:38.608847 <6>[ 0.065256] cblist_init_generic: Setting adjustable number of callback queues.
10431 05:53:38.615120 <6>[ 0.072685] cblist_init_generic: Setting shift to 3 and lim to 1.
10432 05:53:38.618532 <6>[ 0.079085] rcu: Hierarchical SRCU implementation.
10433 05:53:38.624916 <6>[ 0.084132] rcu: Max phase no-delay instances is 1000.
10434 05:53:38.631399 <6>[ 0.091156] EFI services will not be available.
10435 05:53:38.634923 <6>[ 0.096113] smp: Bringing up secondary CPUs ...
10436 05:53:38.643654 <6>[ 0.101159] Detected VIPT I-cache on CPU1
10437 05:53:38.649758 <6>[ 0.101230] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10438 05:53:38.656566 <6>[ 0.101260] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10439 05:53:38.659576 <6>[ 0.101596] Detected VIPT I-cache on CPU2
10440 05:53:38.669428 <6>[ 0.101647] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10441 05:53:38.675888 <6>[ 0.101663] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10442 05:53:38.679803 <6>[ 0.101918] Detected VIPT I-cache on CPU3
10443 05:53:38.685892 <6>[ 0.101964] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10444 05:53:38.692676 <6>[ 0.101978] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10445 05:53:38.699094 <6>[ 0.102281] CPU features: detected: Spectre-v4
10446 05:53:38.702460 <6>[ 0.102287] CPU features: detected: Spectre-BHB
10447 05:53:38.705873 <6>[ 0.102292] Detected PIPT I-cache on CPU4
10448 05:53:38.712256 <6>[ 0.102349] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10449 05:53:38.718988 <6>[ 0.102365] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10450 05:53:38.725838 <6>[ 0.102659] Detected PIPT I-cache on CPU5
10451 05:53:38.732233 <6>[ 0.102720] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10452 05:53:38.738862 <6>[ 0.102736] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10453 05:53:38.742335 <6>[ 0.103016] Detected PIPT I-cache on CPU6
10454 05:53:38.751739 <6>[ 0.103079] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10455 05:53:38.758594 <6>[ 0.103096] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10456 05:53:38.761641 <6>[ 0.103391] Detected PIPT I-cache on CPU7
10457 05:53:38.768529 <6>[ 0.103456] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10458 05:53:38.774789 <6>[ 0.103472] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10459 05:53:38.778234 <6>[ 0.103520] smp: Brought up 1 node, 8 CPUs
10460 05:53:38.785150 <6>[ 0.244922] SMP: Total of 8 processors activated.
10461 05:53:38.791329 <6>[ 0.249873] CPU features: detected: 32-bit EL0 Support
10462 05:53:38.798119 <6>[ 0.255236] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10463 05:53:38.804803 <6>[ 0.264037] CPU features: detected: Common not Private translations
10464 05:53:38.811057 <6>[ 0.270553] CPU features: detected: CRC32 instructions
10465 05:53:38.817737 <6>[ 0.275905] CPU features: detected: RCpc load-acquire (LDAPR)
10466 05:53:38.821169 <6>[ 0.281902] CPU features: detected: LSE atomic instructions
10467 05:53:38.827696 <6>[ 0.287683] CPU features: detected: Privileged Access Never
10468 05:53:38.834372 <6>[ 0.293463] CPU features: detected: RAS Extension Support
10469 05:53:38.840865 <6>[ 0.299072] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10470 05:53:38.844304 <6>[ 0.306291] CPU: All CPU(s) started at EL2
10471 05:53:38.850691 <6>[ 0.310608] alternatives: applying system-wide alternatives
10472 05:53:38.861044 <6>[ 0.321325] devtmpfs: initialized
10473 05:53:38.873053 <6>[ 0.330260] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10474 05:53:38.883014 <6>[ 0.340223] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10475 05:53:38.886429 <6>[ 0.348024] pinctrl core: initialized pinctrl subsystem
10476 05:53:38.894244 <6>[ 0.354692] DMI not present or invalid.
10477 05:53:38.901303 <6>[ 0.359100] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10478 05:53:38.907446 <6>[ 0.365972] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10479 05:53:38.917457 <6>[ 0.373561] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10480 05:53:38.923799 <6>[ 0.381778] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10481 05:53:38.930482 <6>[ 0.390021] audit: initializing netlink subsys (disabled)
10482 05:53:38.937327 <5>[ 0.395716] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10483 05:53:38.944066 <6>[ 0.396418] thermal_sys: Registered thermal governor 'step_wise'
10484 05:53:38.950406 <6>[ 0.403680] thermal_sys: Registered thermal governor 'power_allocator'
10485 05:53:38.954012 <6>[ 0.409929] cpuidle: using governor menu
10486 05:53:38.960818 <6>[ 0.420886] NET: Registered PF_QIPCRTR protocol family
10487 05:53:38.967237 <6>[ 0.426365] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10488 05:53:38.973988 <6>[ 0.433467] ASID allocator initialised with 32768 entries
10489 05:53:38.980463 <6>[ 0.440035] Serial: AMBA PL011 UART driver
10490 05:53:38.988454 <4>[ 0.448825] Trying to register duplicate clock ID: 134
10491 05:53:39.042366 <6>[ 0.506261] KASLR enabled
10492 05:53:39.056780 <6>[ 0.513979] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10493 05:53:39.063709 <6>[ 0.520994] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10494 05:53:39.070150 <6>[ 0.527486] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10495 05:53:39.076894 <6>[ 0.534493] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10496 05:53:39.083222 <6>[ 0.540981] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10497 05:53:39.090105 <6>[ 0.547983] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10498 05:53:39.096698 <6>[ 0.554468] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10499 05:53:39.103605 <6>[ 0.561475] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10500 05:53:39.106475 <6>[ 0.568979] ACPI: Interpreter disabled.
10501 05:53:39.114843 <6>[ 0.575386] iommu: Default domain type: Translated
10502 05:53:39.121629 <6>[ 0.580499] iommu: DMA domain TLB invalidation policy: strict mode
10503 05:53:39.124857 <5>[ 0.587161] SCSI subsystem initialized
10504 05:53:39.131746 <6>[ 0.591323] usbcore: registered new interface driver usbfs
10505 05:53:39.137980 <6>[ 0.597058] usbcore: registered new interface driver hub
10506 05:53:39.141759 <6>[ 0.602611] usbcore: registered new device driver usb
10507 05:53:39.148123 <6>[ 0.608711] pps_core: LinuxPPS API ver. 1 registered
10508 05:53:39.158094 <6>[ 0.613906] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10509 05:53:39.161469 <6>[ 0.623248] PTP clock support registered
10510 05:53:39.165004 <6>[ 0.627489] EDAC MC: Ver: 3.0.0
10511 05:53:39.172060 <6>[ 0.632645] FPGA manager framework
10512 05:53:39.178797 <6>[ 0.636323] Advanced Linux Sound Architecture Driver Initialized.
10513 05:53:39.182229 <6>[ 0.643094] vgaarb: loaded
10514 05:53:39.188488 <6>[ 0.646263] clocksource: Switched to clocksource arch_sys_counter
10515 05:53:39.191939 <5>[ 0.652701] VFS: Disk quotas dquot_6.6.0
10516 05:53:39.198743 <6>[ 0.656888] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10517 05:53:39.202241 <6>[ 0.664072] pnp: PnP ACPI: disabled
10518 05:53:39.210092 <6>[ 0.670759] NET: Registered PF_INET protocol family
10519 05:53:39.220589 <6>[ 0.676337] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10520 05:53:39.231350 <6>[ 0.688647] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10521 05:53:39.241301 <6>[ 0.697458] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10522 05:53:39.248375 <6>[ 0.705427] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10523 05:53:39.257928 <6>[ 0.714128] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10524 05:53:39.264537 <6>[ 0.723873] TCP: Hash tables configured (established 65536 bind 65536)
10525 05:53:39.271067 <6>[ 0.730727] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10526 05:53:39.281039 <6>[ 0.737929] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10527 05:53:39.287760 <6>[ 0.745627] NET: Registered PF_UNIX/PF_LOCAL protocol family
10528 05:53:39.291247 <6>[ 0.751795] RPC: Registered named UNIX socket transport module.
10529 05:53:39.297277 <6>[ 0.757949] RPC: Registered udp transport module.
10530 05:53:39.300608 <6>[ 0.762883] RPC: Registered tcp transport module.
10531 05:53:39.310512 <6>[ 0.767812] RPC: Registered tcp NFSv4.1 backchannel transport module.
10532 05:53:39.313994 <6>[ 0.774478] PCI: CLS 0 bytes, default 64
10533 05:53:39.317535 <6>[ 0.778909] Unpacking initramfs...
10534 05:53:39.327269 <6>[ 0.783111] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10535 05:53:39.334091 <6>[ 0.791764] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10536 05:53:39.340604 <6>[ 0.800536] kvm [1]: IPA Size Limit: 40 bits
10537 05:53:39.343774 <6>[ 0.805063] kvm [1]: GICv3: no GICV resource entry
10538 05:53:39.350609 <6>[ 0.810082] kvm [1]: disabling GICv2 emulation
10539 05:53:39.356903 <6>[ 0.814763] kvm [1]: GIC system register CPU interface enabled
10540 05:53:39.360458 <6>[ 0.820936] kvm [1]: vgic interrupt IRQ18
10541 05:53:39.366640 <6>[ 0.826329] kvm [1]: VHE mode initialized successfully
10542 05:53:39.373703 <5>[ 0.832794] Initialise system trusted keyrings
10543 05:53:39.379745 <6>[ 0.837578] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10544 05:53:39.387141 <6>[ 0.847558] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10545 05:53:39.393633 <5>[ 0.853931] NFS: Registering the id_resolver key type
10546 05:53:39.396858 <5>[ 0.859232] Key type id_resolver registered
10547 05:53:39.403663 <5>[ 0.863649] Key type id_legacy registered
10548 05:53:39.410195 <6>[ 0.867926] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10549 05:53:39.417060 <6>[ 0.874847] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10550 05:53:39.423364 <6>[ 0.882569] 9p: Installing v9fs 9p2000 file system support
10551 05:53:39.459875 <5>[ 0.920299] Key type asymmetric registered
10552 05:53:39.463403 <5>[ 0.924631] Asymmetric key parser 'x509' registered
10553 05:53:39.473229 <6>[ 0.929767] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10554 05:53:39.476511 <6>[ 0.937385] io scheduler mq-deadline registered
10555 05:53:39.479446 <6>[ 0.942147] io scheduler kyber registered
10556 05:53:39.498673 <6>[ 0.959235] EINJ: ACPI disabled.
10557 05:53:39.530719 <4>[ 0.984293] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10558 05:53:39.540436 <4>[ 0.994930] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10559 05:53:39.554917 <6>[ 1.015446] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10560 05:53:39.562794 <6>[ 1.023274] printk: console [ttyS0] disabled
10561 05:53:39.590973 <6>[ 1.047916] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10562 05:53:39.597388 <6>[ 1.057388] printk: console [ttyS0] enabled
10563 05:53:39.600815 <6>[ 1.057388] printk: console [ttyS0] enabled
10564 05:53:39.607167 <6>[ 1.066284] printk: bootconsole [mtk8250] disabled
10565 05:53:39.610663 <6>[ 1.066284] printk: bootconsole [mtk8250] disabled
10566 05:53:39.617436 <6>[ 1.077315] SuperH (H)SCI(F) driver initialized
10567 05:53:39.620378 <6>[ 1.082598] msm_serial: driver initialized
10568 05:53:39.634877 <6>[ 1.091502] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10569 05:53:39.644395 <6>[ 1.100047] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10570 05:53:39.651333 <6>[ 1.108590] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10571 05:53:39.661181 <6>[ 1.117218] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10572 05:53:39.670833 <6>[ 1.125924] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10573 05:53:39.677453 <6>[ 1.134638] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10574 05:53:39.687460 <6>[ 1.143177] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10575 05:53:39.694018 <6>[ 1.151975] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10576 05:53:39.703760 <6>[ 1.160517] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10577 05:53:39.715685 <6>[ 1.175975] loop: module loaded
10578 05:53:39.721957 <6>[ 1.181985] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10579 05:53:39.744689 <4>[ 1.205301] mtk-pmic-keys: Failed to locate of_node [id: -1]
10580 05:53:39.751659 <6>[ 1.212127] megasas: 07.719.03.00-rc1
10581 05:53:39.761312 <6>[ 1.221588] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10582 05:53:39.769541 <6>[ 1.229640] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10583 05:53:39.786331 <6>[ 1.246360] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10584 05:53:39.842673 <6>[ 1.296331] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10585 05:53:40.057030 <6>[ 1.517158] Freeing initrd memory: 17380K
10586 05:53:40.067125 <6>[ 1.527564] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10587 05:53:40.078056 <6>[ 1.538483] tun: Universal TUN/TAP device driver, 1.6
10588 05:53:40.081587 <6>[ 1.544538] thunder_xcv, ver 1.0
10589 05:53:40.084876 <6>[ 1.548043] thunder_bgx, ver 1.0
10590 05:53:40.087789 <6>[ 1.551537] nicpf, ver 1.0
10591 05:53:40.098227 <6>[ 1.555546] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10592 05:53:40.101623 <6>[ 1.563023] hns3: Copyright (c) 2017 Huawei Corporation.
10593 05:53:40.108385 <6>[ 1.568610] hclge is initializing
10594 05:53:40.111604 <6>[ 1.572190] e1000: Intel(R) PRO/1000 Network Driver
10595 05:53:40.118524 <6>[ 1.577319] e1000: Copyright (c) 1999-2006 Intel Corporation.
10596 05:53:40.121990 <6>[ 1.583331] e1000e: Intel(R) PRO/1000 Network Driver
10597 05:53:40.128114 <6>[ 1.588548] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10598 05:53:40.135001 <6>[ 1.594737] igb: Intel(R) Gigabit Ethernet Network Driver
10599 05:53:40.141383 <6>[ 1.600388] igb: Copyright (c) 2007-2014 Intel Corporation.
10600 05:53:40.148171 <6>[ 1.606225] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10601 05:53:40.154723 <6>[ 1.612744] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10602 05:53:40.157935 <6>[ 1.619209] sky2: driver version 1.30
10603 05:53:40.164431 <6>[ 1.624195] VFIO - User Level meta-driver version: 0.3
10604 05:53:40.172043 <6>[ 1.632430] usbcore: registered new interface driver usb-storage
10605 05:53:40.178907 <6>[ 1.638872] usbcore: registered new device driver onboard-usb-hub
10606 05:53:40.187685 <6>[ 1.647997] mt6397-rtc mt6359-rtc: registered as rtc0
10607 05:53:40.197472 <6>[ 1.653459] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-25T05:53:40 UTC (1703483620)
10608 05:53:40.200727 <6>[ 1.663040] i2c_dev: i2c /dev entries driver
10609 05:53:40.217539 <6>[ 1.674738] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10610 05:53:40.237342 <6>[ 1.697753] cpu cpu0: EM: created perf domain
10611 05:53:40.240927 <6>[ 1.702658] cpu cpu4: EM: created perf domain
10612 05:53:40.247786 <6>[ 1.708229] sdhci: Secure Digital Host Controller Interface driver
10613 05:53:40.254553 <6>[ 1.714662] sdhci: Copyright(c) Pierre Ossman
10614 05:53:40.261169 <6>[ 1.719613] Synopsys Designware Multimedia Card Interface Driver
10615 05:53:40.267515 <6>[ 1.726252] sdhci-pltfm: SDHCI platform and OF driver helper
10616 05:53:40.270799 <6>[ 1.726397] mmc0: CQHCI version 5.10
10617 05:53:40.277818 <6>[ 1.736630] ledtrig-cpu: registered to indicate activity on CPUs
10618 05:53:40.284282 <6>[ 1.743607] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10619 05:53:40.291220 <6>[ 1.750671] usbcore: registered new interface driver usbhid
10620 05:53:40.294001 <6>[ 1.756493] usbhid: USB HID core driver
10621 05:53:40.300777 <6>[ 1.760694] spi_master spi0: will run message pump with realtime priority
10622 05:53:40.344585 <6>[ 1.798485] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10623 05:53:40.364092 <6>[ 1.814466] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10624 05:53:40.367495 <6>[ 1.828099] mmc0: Command Queue Engine enabled
10625 05:53:40.374336 <6>[ 1.832896] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10626 05:53:40.381091 <6>[ 1.839823] cros-ec-spi spi0.0: Chrome EC device registered
10627 05:53:40.384138 <6>[ 1.840131] mmcblk0: mmc0:0001 DA4128 116 GiB
10628 05:53:40.393995 <6>[ 1.854547] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10629 05:53:40.401567 <6>[ 1.862010] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10630 05:53:40.408399 <6>[ 1.867928] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10631 05:53:40.414582 <6>[ 1.873780] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10632 05:53:40.430302 <6>[ 1.887481] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10633 05:53:40.437758 <6>[ 1.897814] NET: Registered PF_PACKET protocol family
10634 05:53:40.440449 <6>[ 1.903265] 9pnet: Installing 9P2000 support
10635 05:53:40.447449 <5>[ 1.907828] Key type dns_resolver registered
10636 05:53:40.450955 <6>[ 1.912810] registered taskstats version 1
10637 05:53:40.457233 <5>[ 1.917199] Loading compiled-in X.509 certificates
10638 05:53:40.484032 <4>[ 1.937874] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10639 05:53:40.494386 <4>[ 1.948626] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10640 05:53:40.500769 <3>[ 1.959212] debugfs: File 'uA_load' in directory '/' already present!
10641 05:53:40.507037 <3>[ 1.965925] debugfs: File 'min_uV' in directory '/' already present!
10642 05:53:40.513948 <3>[ 1.972538] debugfs: File 'max_uV' in directory '/' already present!
10643 05:53:40.520507 <3>[ 1.979145] debugfs: File 'constraint_flags' in directory '/' already present!
10644 05:53:40.531735 <3>[ 1.988789] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10645 05:53:40.544299 <6>[ 2.004619] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10646 05:53:40.551064 <6>[ 2.011408] xhci-mtk 11200000.usb: xHCI Host Controller
10647 05:53:40.557315 <6>[ 2.016911] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10648 05:53:40.567733 <6>[ 2.024770] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10649 05:53:40.574699 <6>[ 2.034226] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10650 05:53:40.581064 <6>[ 2.040430] xhci-mtk 11200000.usb: xHCI Host Controller
10651 05:53:40.587560 <6>[ 2.045930] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10652 05:53:40.594466 <6>[ 2.053589] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10653 05:53:40.600741 <6>[ 2.061506] hub 1-0:1.0: USB hub found
10654 05:53:40.604258 <6>[ 2.065545] hub 1-0:1.0: 1 port detected
10655 05:53:40.614130 <6>[ 2.069842] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10656 05:53:40.617450 <6>[ 2.078659] hub 2-0:1.0: USB hub found
10657 05:53:40.620955 <6>[ 2.082693] hub 2-0:1.0: 1 port detected
10658 05:53:40.630055 <6>[ 2.090594] mtk-msdc 11f70000.mmc: Got CD GPIO
10659 05:53:40.643736 <6>[ 2.100508] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10660 05:53:40.649923 <6>[ 2.108570] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10661 05:53:40.659905 <4>[ 2.116504] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10662 05:53:40.669915 <6>[ 2.126075] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10663 05:53:40.676785 <6>[ 2.134158] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10664 05:53:40.683164 <6>[ 2.142185] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10665 05:53:40.692847 <6>[ 2.150101] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10666 05:53:40.699645 <6>[ 2.157919] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10667 05:53:40.709730 <6>[ 2.165737] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10668 05:53:40.719431 <6>[ 2.176041] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10669 05:53:40.726233 <6>[ 2.184401] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10670 05:53:40.736341 <6>[ 2.192748] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10671 05:53:40.742732 <6>[ 2.201087] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10672 05:53:40.752463 <6>[ 2.209426] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10673 05:53:40.759130 <6>[ 2.217765] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10674 05:53:40.769362 <6>[ 2.226104] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10675 05:53:40.775968 <6>[ 2.234442] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10676 05:53:40.785751 <6>[ 2.242780] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10677 05:53:40.795649 <6>[ 2.251120] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10678 05:53:40.802059 <6>[ 2.259460] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10679 05:53:40.812082 <6>[ 2.267799] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10680 05:53:40.819209 <6>[ 2.276139] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10681 05:53:40.828929 <6>[ 2.284478] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10682 05:53:40.835106 <6>[ 2.292816] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10683 05:53:40.841903 <6>[ 2.301527] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10684 05:53:40.848783 <6>[ 2.308619] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10685 05:53:40.855204 <6>[ 2.315379] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10686 05:53:40.861894 <6>[ 2.322133] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10687 05:53:40.868822 <6>[ 2.329067] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10688 05:53:40.878700 <6>[ 2.335922] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10689 05:53:40.888615 <6>[ 2.345058] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10690 05:53:40.898778 <6>[ 2.354177] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10691 05:53:40.908511 <6>[ 2.363471] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10692 05:53:40.918447 <6>[ 2.372943] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10693 05:53:40.925308 <6>[ 2.382411] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10694 05:53:40.934651 <6>[ 2.391531] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10695 05:53:40.944817 <6>[ 2.400998] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10696 05:53:40.954815 <6>[ 2.410116] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10697 05:53:40.964642 <6>[ 2.419409] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10698 05:53:40.974779 <6>[ 2.429570] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10699 05:53:40.984295 <6>[ 2.441075] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10700 05:53:40.991086 <6>[ 2.450974] Trying to probe devices needed for running init ...
10701 05:53:41.033342 <6>[ 2.490532] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10702 05:53:41.187748 <6>[ 2.648356] hub 1-1:1.0: USB hub found
10703 05:53:41.191224 <6>[ 2.652869] hub 1-1:1.0: 4 ports detected
10704 05:53:41.201118 <6>[ 2.661405] hub 1-1:1.0: USB hub found
10705 05:53:41.204009 <6>[ 2.665870] hub 1-1:1.0: 4 ports detected
10706 05:53:41.313385 <6>[ 2.770862] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10707 05:53:41.339609 <6>[ 2.800161] hub 2-1:1.0: USB hub found
10708 05:53:41.343090 <6>[ 2.804656] hub 2-1:1.0: 3 ports detected
10709 05:53:41.352180 <6>[ 2.812681] hub 2-1:1.0: USB hub found
10710 05:53:41.355729 <6>[ 2.817170] hub 2-1:1.0: 3 ports detected
10711 05:53:41.529085 <6>[ 2.986535] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10712 05:53:41.661278 <6>[ 3.122074] hub 1-1.4:1.0: USB hub found
10713 05:53:41.664775 <6>[ 3.126712] hub 1-1.4:1.0: 2 ports detected
10714 05:53:41.674118 <6>[ 3.134765] hub 1-1.4:1.0: USB hub found
10715 05:53:41.677676 <6>[ 3.139371] hub 1-1.4:1.0: 2 ports detected
10716 05:53:41.741603 <6>[ 3.198753] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10717 05:53:41.972999 <6>[ 3.430571] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10718 05:53:42.165369 <6>[ 3.622553] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10719 05:53:53.270034 <6>[ 14.735537] ALSA device list:
10720 05:53:53.276774 <6>[ 14.738831] No soundcards found.
10721 05:53:53.284994 <6>[ 14.746784] Freeing unused kernel memory: 8448K
10722 05:53:53.287875 <6>[ 14.751872] Run /init as init process
10723 05:53:53.299802 Loading, please wait...
10724 05:53:53.320256 Starting version 247.3-7+deb11u2
10725 05:53:53.513975 <6>[ 14.972493] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10726 05:53:53.522663 <6>[ 14.984730] remoteproc remoteproc0: scp is available
10727 05:53:53.529270 <6>[ 14.990285] remoteproc remoteproc0: powering up scp
10728 05:53:53.536240 <6>[ 14.995463] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10729 05:53:53.545503 <6>[ 15.007261] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10730 05:53:53.563890 <6>[ 15.022569] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10731 05:53:53.570481 <6>[ 15.030415] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10732 05:53:53.580277 <6>[ 15.039130] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10733 05:53:53.590245 <3>[ 15.048969] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 05:53:53.596853 <3>[ 15.057121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 05:53:53.603321 <6>[ 15.064051] mc: Linux media interface: v0.10
10736 05:53:53.610370 <3>[ 15.065267] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 05:53:53.620185 <6>[ 15.073697] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10738 05:53:53.626472 <3>[ 15.077915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 05:53:53.633102 <4>[ 15.086349] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10740 05:53:53.642909 <3>[ 15.093592] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 05:53:53.646310 <6>[ 15.101827] videodev: Linux video capture interface: v2.00
10742 05:53:53.656259 <3>[ 15.108991] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10743 05:53:53.663097 <4>[ 15.114245] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10744 05:53:53.669998 <6>[ 15.115985] usbcore: registered new interface driver r8152
10745 05:53:53.676466 <4>[ 15.120490] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10746 05:53:53.683421 <4>[ 15.120490] Fallback method does not support PEC.
10747 05:53:53.689832 <3>[ 15.122784] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 05:53:53.700371 <3>[ 15.122799] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 05:53:53.706991 <3>[ 15.124623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 05:53:53.717135 <3>[ 15.135682] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10751 05:53:53.723876 <3>[ 15.136209] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10752 05:53:53.733262 <6>[ 15.138409] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10753 05:53:53.739876 <6>[ 15.138423] remoteproc remoteproc0: remote processor scp is now up
10754 05:53:53.746594 <6>[ 15.138424] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10755 05:53:53.753204 <3>[ 15.170272] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10756 05:53:53.760152 <6>[ 15.171437] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10757 05:53:53.766335 <6>[ 15.171447] pci_bus 0000:00: root bus resource [bus 00-ff]
10758 05:53:53.772920 <6>[ 15.171458] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10759 05:53:53.783150 <6>[ 15.171464] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10760 05:53:53.789432 <6>[ 15.171512] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10761 05:53:53.799936 <6>[ 15.171534] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10762 05:53:53.802723 <6>[ 15.171625] pci 0000:00:00.0: supports D1 D2
10763 05:53:53.809358 <6>[ 15.171630] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10764 05:53:53.816488 <6>[ 15.173417] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10765 05:53:53.822700 <6>[ 15.173542] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10766 05:53:53.832977 <6>[ 15.173575] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10767 05:53:53.839568 <6>[ 15.173595] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10768 05:53:53.846348 <6>[ 15.173613] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10769 05:53:53.849126 <6>[ 15.173729] pci 0000:01:00.0: supports D1 D2
10770 05:53:53.859120 <6>[ 15.173732] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10771 05:53:53.866001 <3>[ 15.174023] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 05:53:53.872863 <6>[ 15.186327] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10773 05:53:53.882788 <3>[ 15.190757] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 05:53:53.889154 <3>[ 15.190839] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10775 05:53:53.895622 <3>[ 15.190846] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 05:53:53.905202 <3>[ 15.190849] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 05:53:53.912032 <3>[ 15.190857] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 05:53:53.921730 <3>[ 15.190862] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 05:53:53.928737 <3>[ 15.190889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 05:53:53.938454 <6>[ 15.192373] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10781 05:53:53.945100 <6>[ 15.199542] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10782 05:53:53.951571 <6>[ 15.206898] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10783 05:53:53.961573 <6>[ 15.213028] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10784 05:53:53.967868 <6>[ 15.222307] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10785 05:53:53.977660 <6>[ 15.226060] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10786 05:53:53.988157 <6>[ 15.228592] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10787 05:53:53.997931 <6>[ 15.230757] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10788 05:53:54.004152 <6>[ 15.230997] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10789 05:53:54.014622 <4>[ 15.245262] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10790 05:53:54.020622 <6>[ 15.251361] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10791 05:53:54.030954 <6>[ 15.251376] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10792 05:53:54.037390 <6>[ 15.251677] usbcore: registered new interface driver cdc_ether
10793 05:53:54.043724 <4>[ 15.258332] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10794 05:53:54.050635 <6>[ 15.265132] pci 0000:00:00.0: PCI bridge to [bus 01]
10795 05:53:54.057176 <6>[ 15.265438] usbcore: registered new interface driver r8153_ecm
10796 05:53:54.060379 <6>[ 15.270337] Bluetooth: Core ver 2.22
10797 05:53:54.066810 <6>[ 15.276519] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10798 05:53:54.073739 <6>[ 15.284850] NET: Registered PF_BLUETOOTH protocol family
10799 05:53:54.080226 <6>[ 15.291204] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10800 05:53:54.086622 <6>[ 15.292367] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10801 05:53:54.099894 <6>[ 15.293499] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10802 05:53:54.106398 <6>[ 15.293600] usbcore: registered new interface driver uvcvideo
10803 05:53:54.113108 <6>[ 15.298510] Bluetooth: HCI device and connection manager initialized
10804 05:53:54.116205 <6>[ 15.306787] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10805 05:53:54.123004 <6>[ 15.313549] Bluetooth: HCI socket layer initialized
10806 05:53:54.126528 <6>[ 15.314325] r8152 2-1.3:1.0 eth0: v1.12.13
10807 05:53:54.133125 <6>[ 15.318469] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10808 05:53:54.139646 <6>[ 15.318921] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10809 05:53:54.145971 <6>[ 15.320791] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10810 05:53:54.149511 <6>[ 15.324899] Bluetooth: L2CAP socket layer initialized
10811 05:53:54.155670 <6>[ 15.617956] Bluetooth: SCO socket layer initialized
10812 05:53:54.164755 <6>[ 15.626667] usbcore: registered new interface driver btusb
10813 05:53:54.174771 <4>[ 15.627914] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10814 05:53:54.184590 <5>[ 15.636880] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10815 05:53:54.191057 <3>[ 15.642997] Bluetooth: hci0: Failed to load firmware file (-2)
10816 05:53:54.194311 <3>[ 15.657114] Bluetooth: hci0: Failed to set up firmware (-2)
10817 05:53:54.201373 <5>[ 15.661931] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10818 05:53:54.214750 <4>[ 15.662965] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10819 05:53:54.221282 <4>[ 15.669846] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10820 05:53:54.227649 <6>[ 15.689118] cfg80211: failed to load regulatory.db
10821 05:53:54.286771 <6>[ 15.745250] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10822 05:53:54.293003 <6>[ 15.752804] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10823 05:53:54.317624 <6>[ 15.779590] mt7921e 0000:01:00.0: ASIC revision: 79610010
10824 05:53:54.419446 <6>[ 15.878230] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10825 05:53:54.422781 <6>[ 15.878230]
10826 05:53:54.430198 Begin: Loading essential drivers ... done.
10827 05:53:54.433179 Begin: Running /scripts/init-premount ... done.
10828 05:53:54.440050 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10829 05:53:54.450128 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10830 05:53:54.453247 Device /sys/class/net/enx0024323078ff found
10831 05:53:54.453332 done.
10832 05:53:54.500030 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10833 05:53:54.687779 <6>[ 16.146609] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10834 05:53:55.514771 <6>[ 16.976840] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10835 05:53:55.538072 <6>[ 17.000600] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10836 05:53:55.691156 IP-Config: no response after 2 secs - giving up
10837 05:53:55.720020 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10838 05:53:56.443140 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10839 05:53:56.450001 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10840 05:53:56.456707 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10841 05:53:56.463523 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10842 05:53:56.469890 host : mt8192-asurada-spherion-r0-cbg-8
10843 05:53:56.476887 domain : lava-rack
10844 05:53:56.479846 rootserver: 192.168.201.1 rootpath:
10845 05:53:56.479955 filename :
10846 05:53:56.580099 done.
10847 05:53:56.587073 Begin: Running /scripts/nfs-bottom ... done.
10848 05:53:56.608326 Begin: Running /scripts/init-bottom ... done.
10849 05:53:57.818092 <6>[ 19.280616] NET: Registered PF_INET6 protocol family
10850 05:53:57.826257 <6>[ 19.288478] Segment Routing with IPv6
10851 05:53:57.829034 <6>[ 19.292432] In-situ OAM (IOAM) with IPv6
10852 05:53:57.963657 <30>[ 19.406014] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10853 05:53:57.966852 <30>[ 19.430497] systemd[1]: Detected architecture arm64.
10854 05:53:57.989078
10855 05:53:57.992488 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10856 05:53:57.992600
10857 05:53:58.010933 <30>[ 19.473110] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10858 05:53:58.882973 <30>[ 20.342523] systemd[1]: Queued start job for default target Graphical Interface.
10859 05:53:58.918256 <30>[ 20.380926] systemd[1]: Created slice system-getty.slice.
10860 05:53:58.924785 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10861 05:53:58.941520 <30>[ 20.403938] systemd[1]: Created slice system-modprobe.slice.
10862 05:53:58.947740 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10863 05:53:58.965088 <30>[ 20.427776] systemd[1]: Created slice system-serial\x2dgetty.slice.
10864 05:53:58.975256 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10865 05:53:58.988993 <30>[ 20.451619] systemd[1]: Created slice User and Session Slice.
10866 05:53:58.995883 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10867 05:53:59.015876 <30>[ 20.475388] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10868 05:53:59.025747 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10869 05:53:59.043588 <30>[ 20.502753] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10870 05:53:59.049833 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10871 05:53:59.070746 <30>[ 20.526663] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10872 05:53:59.077242 <30>[ 20.538805] systemd[1]: Reached target Local Encrypted Volumes.
10873 05:53:59.084282 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10874 05:53:59.100803 <30>[ 20.563003] systemd[1]: Reached target Paths.
10875 05:53:59.103776 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10876 05:53:59.119981 <30>[ 20.582525] systemd[1]: Reached target Remote File Systems.
10877 05:53:59.126303 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10878 05:53:59.139939 <30>[ 20.602519] systemd[1]: Reached target Slices.
10879 05:53:59.146405 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10880 05:53:59.159885 <30>[ 20.622554] systemd[1]: Reached target Swap.
10881 05:53:59.163358 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10882 05:53:59.183968 <30>[ 20.643059] systemd[1]: Listening on initctl Compatibility Named Pipe.
10883 05:53:59.190662 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10884 05:53:59.196883 <30>[ 20.659160] systemd[1]: Listening on Journal Audit Socket.
10885 05:53:59.203259 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10886 05:53:59.221455 <30>[ 20.683830] systemd[1]: Listening on Journal Socket (/dev/log).
10887 05:53:59.227670 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10888 05:53:59.244520 <30>[ 20.707089] systemd[1]: Listening on Journal Socket.
10889 05:53:59.251159 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10890 05:53:59.268953 <30>[ 20.728086] systemd[1]: Listening on Network Service Netlink Socket.
10891 05:53:59.275307 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10892 05:53:59.290890 <30>[ 20.753275] systemd[1]: Listening on udev Control Socket.
10893 05:53:59.297282 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10894 05:53:59.312281 <30>[ 20.774967] systemd[1]: Listening on udev Kernel Socket.
10895 05:53:59.318861 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10896 05:53:59.368216 <30>[ 20.831044] systemd[1]: Mounting Huge Pages File System...
10897 05:53:59.374912 Mounting [0;1;39mHuge Pages File System[0m...
10898 05:53:59.390381 <30>[ 20.852944] systemd[1]: Mounting POSIX Message Queue File System...
10899 05:53:59.397052 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10900 05:53:59.415370 <30>[ 20.877879] systemd[1]: Mounting Kernel Debug File System...
10901 05:53:59.421942 Mounting [0;1;39mKernel Debug File System[0m...
10902 05:53:59.439507 <30>[ 20.899040] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10903 05:53:59.456235 <30>[ 20.915472] systemd[1]: Starting Create list of static device nodes for the current kernel...
10904 05:53:59.466090 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10905 05:53:59.484643 <30>[ 20.947063] systemd[1]: Starting Load Kernel Module configfs...
10906 05:53:59.491143 Starting [0;1;39mLoad Kernel Module configfs[0m...
10907 05:53:59.508807 <30>[ 20.971529] systemd[1]: Starting Load Kernel Module drm...
10908 05:53:59.515592 Starting [0;1;39mLoad Kernel Module drm[0m...
10909 05:53:59.532939 <30>[ 20.995419] systemd[1]: Starting Load Kernel Module fuse...
10910 05:53:59.539104 Starting [0;1;39mLoad Kernel Module fuse[0m...
10911 05:53:59.575388 <30>[ 21.034616] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10912 05:53:59.581951 <6>[ 21.035010] fuse: init (API version 7.37)
10913 05:53:59.590398 <30>[ 21.052802] systemd[1]: Starting Journal Service...
10914 05:53:59.596898 Starting [0;1;39mJournal Service[0m...
10915 05:53:59.625382 <30>[ 21.087780] systemd[1]: Starting Load Kernel Modules...
10916 05:53:59.631826 Starting [0;1;39mLoad Kernel Modules[0m...
10917 05:53:59.652455 <30>[ 21.111575] systemd[1]: Starting Remount Root and Kernel File Systems...
10918 05:53:59.658471 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10919 05:53:59.677737 <30>[ 21.140259] systemd[1]: Starting Coldplug All udev Devices...
10920 05:53:59.684063 Starting [0;1;39mColdplug All udev Devices[0m...
10921 05:53:59.706458 <30>[ 21.168948] systemd[1]: Mounted Huge Pages File System.
10922 05:53:59.712914 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10923 05:53:59.728458 <3>[ 21.187800] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 05:53:59.735132 <30>[ 21.197280] systemd[1]: Mounted POSIX Message Queue File System.
10925 05:53:59.741424 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10926 05:53:59.755855 <30>[ 21.218797] systemd[1]: Mounted Kernel Debug File System.
10927 05:53:59.765815 <3>[ 21.219305] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 05:53:59.772552 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10929 05:53:59.792960 <30>[ 21.252388] systemd[1]: Finished Create list of static device nodes for the current kernel.
10930 05:53:59.803028 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10931 05:53:59.815197 <3>[ 21.274216] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 05:53:59.821748 <30>[ 21.284041] systemd[1]: modprobe@configfs.service: Succeeded.
10933 05:53:59.828543 <30>[ 21.291076] systemd[1]: Finished Load Kernel Module configfs.
10934 05:53:59.835397 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10935 05:53:59.845739 <3>[ 21.303739] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 05:53:59.852552 <30>[ 21.315348] systemd[1]: modprobe@drm.service: Succeeded.
10937 05:53:59.859146 <30>[ 21.321692] systemd[1]: Finished Load Kernel Module drm.
10938 05:53:59.866482 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10939 05:53:59.876473 <3>[ 21.333793] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 05:53:59.883059 <30>[ 21.343991] systemd[1]: modprobe@fuse.service: Succeeded.
10941 05:53:59.890252 <30>[ 21.350929] systemd[1]: Finished Load Kernel Module fuse.
10942 05:53:59.896781 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10943 05:53:59.903238 <3>[ 21.363702] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 05:53:59.913790 <30>[ 21.376380] systemd[1]: Finished Load Kernel Modules.
10945 05:53:59.920233 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10946 05:53:59.933673 <3>[ 21.392996] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 05:53:59.944487 <30>[ 21.403967] systemd[1]: Finished Remount Root and Kernel File Systems.
10948 05:53:59.951278 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10949 05:53:59.964371 <3>[ 21.423509] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 05:53:59.995922 <3>[ 21.455333] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 05:54:00.022730 <30>[ 21.485167] systemd[1]: Mounting FUSE Control File System...
10952 05:54:00.032593 <3>[ 21.486427] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 05:54:00.039257 Mounting [0;1;39mFUSE Control File System[0m...
10954 05:54:00.061491 <30>[ 21.521088] systemd[1]: Mounting Kernel Configuration File System...
10955 05:54:00.065163 Mounting [0;1;39mKernel Configuration File System[0m...
10956 05:54:00.089524 <30>[ 21.548704] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10957 05:54:00.099079 <30>[ 21.558019] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10958 05:54:00.109575 <30>[ 21.572239] systemd[1]: Starting Load/Save Random Seed...
10959 05:54:00.116134 Starting [0;1;39mLoad/Save Random Seed[0m...
10960 05:54:00.136641 <30>[ 21.599426] systemd[1]: Starting Apply Kernel Variables...
10961 05:54:00.143494 Starting [0;1;39mApply Kernel Variables[0m...
10962 05:54:00.160418 <30>[ 21.622930] systemd[1]: Starting Create System Users...
10963 05:54:00.166812 Starting [0;1;39mCreate System Users[0m...
10964 05:54:00.182632 <30>[ 21.645248] systemd[1]: Started Journal Service.
10965 05:54:00.189185 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10966 05:54:00.206512 <4>[ 21.659460] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10967 05:54:00.216372 <3>[ 21.675158] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10968 05:54:00.219830 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10969 05:54:00.236627 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10970 05:54:00.257068 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10971 05:54:00.267663 See 'systemctl status systemd-udev-trigger.service' for details.
10972 05:54:00.284973 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10973 05:54:00.301973 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10974 05:54:00.321453 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10975 05:54:00.372945 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10976 05:54:00.389726 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10977 05:54:00.430818 <46>[ 21.890365] systemd-journald[293]: Received client request to flush runtime journal.
10978 05:54:00.489795 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10979 05:54:00.504440 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10980 05:54:00.520209 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10981 05:54:00.580671 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10982 05:54:01.887489 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10983 05:54:01.933127 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10984 05:54:01.976744 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10985 05:54:02.048516 Starting [0;1;39mNetwork Service[0m...
10986 05:54:02.406731 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10987 05:54:02.727577 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10988 05:54:02.743739 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10989 05:54:02.763632 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10990 05:54:02.800020 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10991 05:54:02.817047 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10992 05:54:02.888889 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10993 05:54:02.908742 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10994 05:54:02.928743 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10995 05:54:02.948137 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10996 05:54:03.008295 Starting [0;1;39mNetwork Name Resolution[0m...
10997 05:54:03.031691 Starting [0;1;39mNetwork Time Synchronization[0m...
10998 05:54:03.054983 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10999 05:54:03.106829 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11000 05:54:03.240543 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11001 05:54:03.261847 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11002 05:54:03.288018 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11003 05:54:03.307783 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11004 05:54:03.327769 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11005 05:54:03.480773 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11006 05:54:03.511779 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11007 05:54:03.548820 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11008 05:54:03.601860 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11009 05:54:03.619579 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11010 05:54:03.648422 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11011 05:54:03.659763 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11012 05:54:03.679387 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11013 05:54:03.742821 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11014 05:54:03.821677 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11015 05:54:03.925372 Starting [0;1;39mUser Login Management[0m...
11016 05:54:03.947296 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11017 05:54:03.963743 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11018 05:54:03.987167 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11019 05:54:04.030229 Starting [0;1;39mPermit User Sessions[0m...
11020 05:54:04.094781 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11021 05:54:04.118065 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11022 05:54:04.159201 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11023 05:54:04.184635 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11024 05:54:04.200576 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11025 05:54:04.224048 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11026 05:54:04.243629 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11027 05:54:04.258982 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11028 05:54:04.310314 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11029 05:54:04.355737 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11030 05:54:04.417957
11031 05:54:04.418129
11032 05:54:04.421345 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11033 05:54:04.421458
11034 05:54:04.424555 debian-bullseye-arm64 login: root (automatic login)
11035 05:54:04.424667
11036 05:54:04.424762
11037 05:54:04.822348 Linux debian-bullseye-arm64 6.1.67-cip12 #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023 aarch64
11038 05:54:04.830756
11039 05:54:04.837524 The programs included with the Debian GNU/Linux system are free software;
11040 05:54:04.840536 the exact distribution terms for each program are described in the
11041 05:54:04.847328 individual files in /usr/share/doc/*/copyright.
11042 05:54:04.847483
11043 05:54:04.850277 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11044 05:54:04.853993 permitted by applicable law.
11045 05:54:05.753822 Matched prompt #10: / #
11047 05:54:05.754220 Setting prompt string to ['/ #']
11048 05:54:05.754357 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11050 05:54:05.754659 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11051 05:54:05.754790 start: 2.2.6 expect-shell-connection (timeout 00:03:13) [common]
11052 05:54:05.754897 Setting prompt string to ['/ #']
11053 05:54:05.754991 Forcing a shell prompt, looking for ['/ #']
11055 05:54:05.805266 / #
11056 05:54:05.805486 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11057 05:54:05.805643 Waiting using forced prompt support (timeout 00:02:30)
11058 05:54:05.810557
11059 05:54:05.810886 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11060 05:54:05.811021 start: 2.2.7 export-device-env (timeout 00:03:13) [common]
11062 05:54:05.911431 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12379416/extract-nfsrootfs-69r2xshf'
11063 05:54:05.917195 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12379416/extract-nfsrootfs-69r2xshf'
11065 05:54:06.017841 / # export NFS_SERVER_IP='192.168.201.1'
11066 05:54:06.022773 export NFS_SERVER_IP='192.168.201.1'
11067 05:54:06.023110 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11068 05:54:06.023254 end: 2.2 depthcharge-retry (duration 00:01:47) [common]
11069 05:54:06.023386 end: 2 depthcharge-action (duration 00:01:47) [common]
11070 05:54:06.023516 start: 3 lava-test-retry (timeout 00:07:26) [common]
11071 05:54:06.023642 start: 3.1 lava-test-shell (timeout 00:07:26) [common]
11072 05:54:06.023752 Using namespace: common
11074 05:54:06.124148 / # #
11075 05:54:06.124363 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11076 05:54:06.129634 #
11077 05:54:06.129943 Using /lava-12379416
11079 05:54:06.230326 / # export SHELL=/bin/bash
11080 05:54:06.235683 export SHELL=/bin/bash
11082 05:54:06.336240 / # . /lava-12379416/environment
11083 05:54:06.341610 . /lava-12379416/environment
11085 05:54:06.447364 / # /lava-12379416/bin/lava-test-runner /lava-12379416/0
11086 05:54:06.447570 Test shell timeout: 10s (minimum of the action and connection timeout)
11087 05:54:06.452676 /lava-12379416/bin/lava-test-runner /lava-12379416/0
11088 05:54:06.783632 + export TESTRUN_ID=0_timesync-off
11089 05:54:06.786908 + TESTRUN_ID=0_timesync-off
11090 05:54:06.790055 + cd /lava-12379416/0/tests/0_timesync-off
11091 05:54:06.793295 ++ cat uuid
11092 05:54:06.799032 + UUID=12379416_1.6.2.3.1
11093 05:54:06.799149 + set +x
11094 05:54:06.806119 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12379416_1.6.2.3.1>
11095 05:54:06.806420 Received signal: <STARTRUN> 0_timesync-off 12379416_1.6.2.3.1
11096 05:54:06.806534 Starting test lava.0_timesync-off (12379416_1.6.2.3.1)
11097 05:54:06.806659 Skipping test definition patterns.
11098 05:54:06.809152 + systemctl stop systemd-timesyncd
11099 05:54:06.876535 + set +x
11100 05:54:06.879507 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12379416_1.6.2.3.1>
11101 05:54:06.879803 Received signal: <ENDRUN> 0_timesync-off 12379416_1.6.2.3.1
11102 05:54:06.879923 Ending use of test pattern.
11103 05:54:06.880017 Ending test lava.0_timesync-off (12379416_1.6.2.3.1), duration 0.07
11105 05:54:06.962263 + export TESTRUN_ID=1_kselftest-rtc
11106 05:54:06.965779 + TESTRUN_ID=1_kselftest-rtc
11107 05:54:06.969159 + cd /lava-12379416/0/tests/1_kselftest-rtc
11108 05:54:06.972527 ++ cat uuid
11109 05:54:06.977665 + UUID=12379416_1.6.2.3.5
11110 05:54:06.977776 + set +x
11111 05:54:06.984960 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 12379416_1.6.2.3.5>
11112 05:54:06.985273 Received signal: <STARTRUN> 1_kselftest-rtc 12379416_1.6.2.3.5
11113 05:54:06.985381 Starting test lava.1_kselftest-rtc (12379416_1.6.2.3.5)
11114 05:54:06.985510 Skipping test definition patterns.
11115 05:54:06.987760 + cd ./automated/linux/kselftest/
11116 05:54:07.014314 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11117 05:54:07.058847 INFO: install_deps skipped
11118 05:54:07.179109 --2023-12-25 05:54:07-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11119 05:54:07.204129 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11120 05:54:07.334895 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11121 05:54:07.464762 HTTP request sent, awaiting response... 200 OK
11122 05:54:07.467598 Length: 2966180 (2.8M) [application/octet-stream]
11123 05:54:07.471066 Saving to: 'kselftest.tar.xz'
11124 05:54:07.471169
11125 05:54:07.471260
11126 05:54:07.723183 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11127 05:54:07.982386 kselftest.tar.xz 1%[ ] 47.81K 191KB/s
11128 05:54:08.263311 kselftest.tar.xz 7%[> ] 219.84K 437KB/s
11129 05:54:08.500479 kselftest.tar.xz 12%[=> ] 349.00K 449KB/s
11130 05:54:08.758389 kselftest.tar.xz 39%[======> ] 1.11M 1.10MB/s
11131 05:54:09.017321 kselftest.tar.xz 57%[==========> ] 1.64M 1.30MB/s
11132 05:54:09.244730 kselftest.tar.xz 77%[==============> ] 2.18M 1.44MB/s
11133 05:54:09.283249 kselftest.tar.xz 97%[==================> ] 2.75M 1.58MB/s
11134 05:54:09.289726 kselftest.tar.xz 100%[===================>] 2.83M 1.59MB/s in 1.8s
11135 05:54:09.289841
11136 05:54:09.548447 2023-12-25 05:54:09 (1.59 MB/s) - 'kselftest.tar.xz' saved [2966180/2966180]
11137 05:54:09.548579
11138 05:54:16.200219 skiplist:
11139 05:54:16.203953 ========================================
11140 05:54:16.206846 ========================================
11141 05:54:16.261786 rtc:rtctest
11142 05:54:16.283186 ============== Tests to run ===============
11143 05:54:16.286164 rtc:rtctest
11144 05:54:16.289302 ===========End Tests to run ===============
11145 05:54:16.293574 shardfile-rtc pass
11146 05:54:16.416090 <12>[ 37.880549] kselftest: Running tests in rtc
11147 05:54:16.427851 TAP version 13
11148 05:54:16.441913 1..1
11149 05:54:16.477913 # selftests: rtc: rtctest
11150 05:54:16.975905 # TAP version 13
11151 05:54:16.976064 # 1..8
11152 05:54:16.979198 # # Starting 8 tests from 2 test cases.
11153 05:54:16.982668 # # RUN rtc.date_read ...
11154 05:54:16.989542 # # rtctest.c:49:date_read:Current RTC date/time is 25/12/2023 05:54:16.
11155 05:54:16.992720 # # OK rtc.date_read
11156 05:54:16.995903 # ok 1 rtc.date_read
11157 05:54:16.999014 # # RUN rtc.date_read_loop ...
11158 05:54:17.009113 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11159 05:54:25.001779 <6>[ 46.470626] vpu: disabling
11160 05:54:25.005232 <6>[ 46.473729] vproc2: disabling
11161 05:54:25.008281 <6>[ 46.477050] vproc1: disabling
11162 05:54:25.011689 <6>[ 46.480420] vaud18: disabling
11163 05:54:25.018448 <6>[ 46.483931] vsram_others: disabling
11164 05:54:25.021766 <6>[ 46.487929] va09: disabling
11165 05:54:25.024860 <6>[ 46.491097] vsram_md: disabling
11166 05:54:25.028079 <6>[ 46.494696] Vgpu: disabling
11167 05:54:46.743459 # # rtctest.c:115:date_read_loop:Performed 2599 RTC time reads.
11168 05:54:46.746416 # # OK rtc.date_read_loop
11169 05:54:46.750117 # ok 2 rtc.date_read_loop
11170 05:54:46.752997 # # RUN rtc.uie_read ...
11171 05:54:49.724796 # # OK rtc.uie_read
11172 05:54:49.725364 # ok 3 rtc.uie_read
11173 05:54:49.728285 # # RUN rtc.uie_select ...
11174 05:54:52.721096 # # OK rtc.uie_select
11175 05:54:52.724344 # ok 4 rtc.uie_select
11176 05:54:52.727984 # # RUN rtc.alarm_alm_set ...
11177 05:54:52.734367 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 05:54:56.
11178 05:54:52.737392 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11179 05:54:52.744063 # # alarm_alm_set: Test terminated by assertion
11180 05:54:52.747442 # # FAIL rtc.alarm_alm_set
11181 05:54:52.747865 # not ok 5 rtc.alarm_alm_set
11182 05:54:52.754105 # # RUN rtc.alarm_wkalm_set ...
11183 05:54:52.760563 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 25/12/2023 05:54:56.
11184 05:54:55.723655 # # OK rtc.alarm_wkalm_set
11185 05:54:55.724140 # ok 6 rtc.alarm_wkalm_set
11186 05:54:55.730471 # # RUN rtc.alarm_alm_set_minute ...
11187 05:54:55.733892 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 05:55:00.
11188 05:54:55.740244 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11189 05:54:55.747314 # # alarm_alm_set_minute: Test terminated by assertion
11190 05:54:55.750438 # # FAIL rtc.alarm_alm_set_minute
11191 05:54:55.753888 # not ok 7 rtc.alarm_alm_set_minute
11192 05:54:55.756973 # # RUN rtc.alarm_wkalm_set_minute ...
11193 05:54:55.763495 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 25/12/2023 05:55:00.
11194 05:54:59.723359 # # OK rtc.alarm_wkalm_set_minute
11195 05:54:59.726746 # ok 8 rtc.alarm_wkalm_set_minute
11196 05:54:59.729862 # # FAILED: 6 / 8 tests passed.
11197 05:54:59.733248 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11198 05:54:59.736084 not ok 1 selftests: rtc: rtctest # exit=1
11199 05:55:00.411068 rtc_rtctest_rtc_date_read pass
11200 05:55:00.414019 rtc_rtctest_rtc_date_read_loop pass
11201 05:55:00.417454 rtc_rtctest_rtc_uie_read pass
11202 05:55:00.421085 rtc_rtctest_rtc_uie_select pass
11203 05:55:00.424168 rtc_rtctest_rtc_alarm_alm_set fail
11204 05:55:00.427669 rtc_rtctest_rtc_alarm_wkalm_set pass
11205 05:55:00.430588 rtc_rtctest_rtc_alarm_alm_set_minute fail
11206 05:55:00.434092 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11207 05:55:00.437104 rtc_rtctest fail
11208 05:55:00.445984 + ../../utils/send-to-lava.sh ./output/result.txt
11209 05:55:00.552093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11210 05:55:00.552865 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11212 05:55:00.628218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11213 05:55:00.628946 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11215 05:55:00.708952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11216 05:55:00.709905 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11218 05:55:00.778455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11219 05:55:00.778883 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11221 05:55:00.854938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11222 05:55:00.855641 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11224 05:55:00.938300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11225 05:55:00.939010 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11227 05:55:01.017178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11228 05:55:01.017912 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11230 05:55:01.092163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11231 05:55:01.092869 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11233 05:55:01.168171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11234 05:55:01.168907 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11236 05:55:01.241521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11237 05:55:01.242105 + set +x
11238 05:55:01.242828 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11240 05:55:01.247516 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 12379416_1.6.2.3.5>
11241 05:55:01.248213 Received signal: <ENDRUN> 1_kselftest-rtc 12379416_1.6.2.3.5
11242 05:55:01.248636 Ending use of test pattern.
11243 05:55:01.249045 Ending test lava.1_kselftest-rtc (12379416_1.6.2.3.5), duration 54.26
11245 05:55:01.250949 <LAVA_TEST_RUNNER EXIT>
11246 05:55:01.251643 ok: lava_test_shell seems to have completed
11247 05:55:01.252458 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11248 05:55:01.252952 end: 3.1 lava-test-shell (duration 00:00:55) [common]
11249 05:55:01.253471 end: 3 lava-test-retry (duration 00:00:55) [common]
11250 05:55:01.254029 start: 4 finalize (timeout 00:06:31) [common]
11251 05:55:01.254574 start: 4.1 power-off (timeout 00:00:30) [common]
11252 05:55:01.255402 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11253 05:55:01.369276 >> Command sent successfully.
11254 05:55:01.380144 Returned 0 in 0 seconds
11255 05:55:01.481414 end: 4.1 power-off (duration 00:00:00) [common]
11257 05:55:01.482995 start: 4.2 read-feedback (timeout 00:06:31) [common]
11258 05:55:01.484267 Listened to connection for namespace 'common' for up to 1s
11259 05:55:02.484795 Finalising connection for namespace 'common'
11260 05:55:02.485037 Disconnecting from shell: Finalise
11261 05:55:02.485174 / #
11262 05:55:02.585837 end: 4.2 read-feedback (duration 00:00:01) [common]
11263 05:55:02.586541 end: 4 finalize (duration 00:00:01) [common]
11264 05:55:02.587189 Cleaning after the job
11265 05:55:02.587730 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/ramdisk
11266 05:55:02.600734 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/kernel
11267 05:55:02.630753 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/dtb
11268 05:55:02.631115 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/nfsrootfs
11269 05:55:02.723868 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379416/tftp-deploy-v3ap0rf0/modules
11270 05:55:02.731495 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12379416
11271 05:55:03.377863 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12379416
11272 05:55:03.378047 Job finished correctly