Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 37
- Kernel Errors: 29
- Errors: 0
1 05:58:06.238523 lava-dispatcher, installed at version: 2023.10
2 05:58:06.238731 start: 0 validate
3 05:58:06.238860 Start time: 2023-12-25 05:58:06.238853+00:00 (UTC)
4 05:58:06.238986 Using caching service: 'http://localhost/cache/?uri=%s'
5 05:58:06.239111 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 05:58:06.506063 Using caching service: 'http://localhost/cache/?uri=%s'
7 05:58:06.506234 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 05:58:06.772089 Using caching service: 'http://localhost/cache/?uri=%s'
9 05:58:06.772261 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 05:58:07.029628 Using caching service: 'http://localhost/cache/?uri=%s'
11 05:58:07.029880 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 05:58:07.296154 validate duration: 1.06
14 05:58:07.296489 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 05:58:07.296590 start: 1.1 download-retry (timeout 00:10:00) [common]
16 05:58:07.296682 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 05:58:07.296853 Not decompressing ramdisk as can be used compressed.
18 05:58:07.296941 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 05:58:07.297004 saving as /var/lib/lava/dispatcher/tmp/12379448/tftp-deploy-81t6ocb1/ramdisk/rootfs.cpio.gz
20 05:58:07.297073 total size: 84918747 (80 MB)
21 05:58:07.298142 progress 0 % (0 MB)
22 05:58:07.321252 progress 5 % (4 MB)
23 05:58:07.343752 progress 10 % (8 MB)
24 05:58:07.366431 progress 15 % (12 MB)
25 05:58:07.389546 progress 20 % (16 MB)
26 05:58:07.412156 progress 25 % (20 MB)
27 05:58:07.435340 progress 30 % (24 MB)
28 05:58:07.457870 progress 35 % (28 MB)
29 05:58:07.480379 progress 40 % (32 MB)
30 05:58:07.503643 progress 45 % (36 MB)
31 05:58:07.527332 progress 50 % (40 MB)
32 05:58:07.551207 progress 55 % (44 MB)
33 05:58:07.576249 progress 60 % (48 MB)
34 05:58:07.600495 progress 65 % (52 MB)
35 05:58:07.624659 progress 70 % (56 MB)
36 05:58:07.647800 progress 75 % (60 MB)
37 05:58:07.670924 progress 80 % (64 MB)
38 05:58:07.694160 progress 85 % (68 MB)
39 05:58:07.718278 progress 90 % (72 MB)
40 05:58:07.740510 progress 95 % (76 MB)
41 05:58:07.762178 progress 100 % (80 MB)
42 05:58:07.762397 80 MB downloaded in 0.47 s (174.04 MB/s)
43 05:58:07.762566 end: 1.1.1 http-download (duration 00:00:00) [common]
45 05:58:07.762815 end: 1.1 download-retry (duration 00:00:00) [common]
46 05:58:07.762900 start: 1.2 download-retry (timeout 00:10:00) [common]
47 05:58:07.762982 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 05:58:07.763119 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 05:58:07.763185 saving as /var/lib/lava/dispatcher/tmp/12379448/tftp-deploy-81t6ocb1/kernel/Image
50 05:58:07.763246 total size: 50024960 (47 MB)
51 05:58:07.763307 No compression specified
52 05:58:07.764383 progress 0 % (0 MB)
53 05:58:07.777514 progress 5 % (2 MB)
54 05:58:07.790612 progress 10 % (4 MB)
55 05:58:07.803685 progress 15 % (7 MB)
56 05:58:07.816755 progress 20 % (9 MB)
57 05:58:07.829871 progress 25 % (11 MB)
58 05:58:07.843408 progress 30 % (14 MB)
59 05:58:07.856664 progress 35 % (16 MB)
60 05:58:07.869847 progress 40 % (19 MB)
61 05:58:07.883086 progress 45 % (21 MB)
62 05:58:07.897085 progress 50 % (23 MB)
63 05:58:07.910381 progress 55 % (26 MB)
64 05:58:07.923641 progress 60 % (28 MB)
65 05:58:07.937012 progress 65 % (31 MB)
66 05:58:07.950556 progress 70 % (33 MB)
67 05:58:07.963663 progress 75 % (35 MB)
68 05:58:07.976801 progress 80 % (38 MB)
69 05:58:07.989765 progress 85 % (40 MB)
70 05:58:08.003071 progress 90 % (42 MB)
71 05:58:08.016125 progress 95 % (45 MB)
72 05:58:08.029304 progress 100 % (47 MB)
73 05:58:08.029547 47 MB downloaded in 0.27 s (179.15 MB/s)
74 05:58:08.029696 end: 1.2.1 http-download (duration 00:00:00) [common]
76 05:58:08.029922 end: 1.2 download-retry (duration 00:00:00) [common]
77 05:58:08.030005 start: 1.3 download-retry (timeout 00:09:59) [common]
78 05:58:08.030092 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 05:58:08.030227 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 05:58:08.030297 saving as /var/lib/lava/dispatcher/tmp/12379448/tftp-deploy-81t6ocb1/dtb/mt8192-asurada-spherion-r0.dtb
81 05:58:08.030356 total size: 47278 (0 MB)
82 05:58:08.030416 No compression specified
83 05:58:08.031470 progress 69 % (0 MB)
84 05:58:08.031739 progress 100 % (0 MB)
85 05:58:08.031916 0 MB downloaded in 0.00 s (28.96 MB/s)
86 05:58:08.032035 end: 1.3.1 http-download (duration 00:00:00) [common]
88 05:58:08.032276 end: 1.3 download-retry (duration 00:00:00) [common]
89 05:58:08.032385 start: 1.4 download-retry (timeout 00:09:59) [common]
90 05:58:08.032469 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 05:58:08.032582 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 05:58:08.032648 saving as /var/lib/lava/dispatcher/tmp/12379448/tftp-deploy-81t6ocb1/modules/modules.tar
93 05:58:08.032707 total size: 8619328 (8 MB)
94 05:58:08.032766 Using unxz to decompress xz
95 05:58:08.037087 progress 0 % (0 MB)
96 05:58:08.058816 progress 5 % (0 MB)
97 05:58:08.082562 progress 10 % (0 MB)
98 05:58:08.106836 progress 15 % (1 MB)
99 05:58:08.130465 progress 20 % (1 MB)
100 05:58:08.154860 progress 25 % (2 MB)
101 05:58:08.180857 progress 30 % (2 MB)
102 05:58:08.207540 progress 35 % (2 MB)
103 05:58:08.231577 progress 40 % (3 MB)
104 05:58:08.256315 progress 45 % (3 MB)
105 05:58:08.282753 progress 50 % (4 MB)
106 05:58:08.307304 progress 55 % (4 MB)
107 05:58:08.333125 progress 60 % (4 MB)
108 05:58:08.359106 progress 65 % (5 MB)
109 05:58:08.386619 progress 70 % (5 MB)
110 05:58:08.410414 progress 75 % (6 MB)
111 05:58:08.437723 progress 80 % (6 MB)
112 05:58:08.463934 progress 85 % (7 MB)
113 05:58:08.489188 progress 90 % (7 MB)
114 05:58:08.519283 progress 95 % (7 MB)
115 05:58:08.549611 progress 100 % (8 MB)
116 05:58:08.554408 8 MB downloaded in 0.52 s (15.76 MB/s)
117 05:58:08.554668 end: 1.4.1 http-download (duration 00:00:01) [common]
119 05:58:08.554934 end: 1.4 download-retry (duration 00:00:01) [common]
120 05:58:08.555028 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 05:58:08.555124 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 05:58:08.555205 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 05:58:08.555293 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 05:58:08.555514 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_
125 05:58:08.555646 makedir: /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin
126 05:58:08.555750 makedir: /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/tests
127 05:58:08.555852 makedir: /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/results
128 05:58:08.555966 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-add-keys
129 05:58:08.556114 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-add-sources
130 05:58:08.556245 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-background-process-start
131 05:58:08.556414 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-background-process-stop
132 05:58:08.556544 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-common-functions
133 05:58:08.556668 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-echo-ipv4
134 05:58:08.556792 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-install-packages
135 05:58:08.556914 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-installed-packages
136 05:58:08.557039 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-os-build
137 05:58:08.557163 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-probe-channel
138 05:58:08.557286 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-probe-ip
139 05:58:08.557409 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-target-ip
140 05:58:08.557532 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-target-mac
141 05:58:08.557654 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-target-storage
142 05:58:08.557782 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-test-case
143 05:58:08.557942 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-test-event
144 05:58:08.558065 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-test-feedback
145 05:58:08.558188 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-test-raise
146 05:58:08.558312 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-test-reference
147 05:58:08.558433 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-test-runner
148 05:58:08.558554 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-test-set
149 05:58:08.558678 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-test-shell
150 05:58:08.558804 Updating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-install-packages (oe)
151 05:58:08.558953 Updating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/bin/lava-installed-packages (oe)
152 05:58:08.559074 Creating /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/environment
153 05:58:08.559171 LAVA metadata
154 05:58:08.559242 - LAVA_JOB_ID=12379448
155 05:58:08.559305 - LAVA_DISPATCHER_IP=192.168.201.1
156 05:58:08.559404 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 05:58:08.559471 skipped lava-vland-overlay
158 05:58:08.559542 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 05:58:08.559621 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 05:58:08.559684 skipped lava-multinode-overlay
161 05:58:08.559756 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 05:58:08.559908 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 05:58:08.559995 Loading test definitions
164 05:58:08.560083 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 05:58:08.560156 Using /lava-12379448 at stage 0
166 05:58:08.560248 Fetching tests from https://github.com/kernelci/kernelci-core
167 05:58:08.560366 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/0/tests/0_sleep'
168 05:58:09.178556 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/0/tests/0_sleep
169 05:58:09.179968 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 05:58:09.180454 uuid=12379448_1.5.2.3.1 testdef=None
171 05:58:09.180602 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 05:58:09.180865 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 05:58:09.181474 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 05:58:09.181747 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 05:58:09.182696 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 05:58:09.183098 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 05:58:09.184118 runner path: /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/0/tests/0_sleep test_uuid 12379448_1.5.2.3.1
181 05:58:09.184231 sleep_params='mem'
182 05:58:09.184438 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 05:58:09.184675 Creating lava-test-runner.conf files
185 05:58:09.184753 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379448/lava-overlay-tkv9fh6_/lava-12379448/0 for stage 0
186 05:58:09.184864 - 0_sleep
187 05:58:09.184990 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 05:58:09.185082 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 05:58:09.333282 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 05:58:09.333431 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 05:58:09.333525 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 05:58:09.333684 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 05:58:09.333788 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 05:58:11.977265 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 05:58:11.977669 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 05:58:11.977793 extracting modules file /var/lib/lava/dispatcher/tmp/12379448/tftp-deploy-81t6ocb1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379448/extract-overlay-ramdisk-9oai_tno/ramdisk
197 05:58:12.215206 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 05:58:12.215377 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 05:58:12.215479 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379448/compress-overlay-446y5rjh/overlay-1.5.2.4.tar.gz to ramdisk
200 05:58:12.215560 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379448/compress-overlay-446y5rjh/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12379448/extract-overlay-ramdisk-9oai_tno/ramdisk
201 05:58:12.317605 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 05:58:12.317770 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 05:58:12.317875 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 05:58:12.317970 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 05:58:12.318057 Building ramdisk /var/lib/lava/dispatcher/tmp/12379448/extract-overlay-ramdisk-9oai_tno/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12379448/extract-overlay-ramdisk-9oai_tno/ramdisk
206 05:58:13.982635 >> 563595 blocks
207 05:58:24.310882 rename /var/lib/lava/dispatcher/tmp/12379448/extract-overlay-ramdisk-9oai_tno/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12379448/tftp-deploy-81t6ocb1/ramdisk/ramdisk.cpio.gz
208 05:58:24.311336 end: 1.5.7 compress-ramdisk (duration 00:00:12) [common]
209 05:58:24.311463 start: 1.5.8 prepare-kernel (timeout 00:09:43) [common]
210 05:58:24.311564 start: 1.5.8.1 prepare-fit (timeout 00:09:43) [common]
211 05:58:24.311675 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12379448/tftp-deploy-81t6ocb1/kernel/Image'
212 05:58:37.489986 Returned 0 in 13 seconds
213 05:58:37.590620 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12379448/tftp-deploy-81t6ocb1/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12379448/tftp-deploy-81t6ocb1/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12379448/tftp-deploy-81t6ocb1/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12379448/tftp-deploy-81t6ocb1/kernel/image.itb
214 05:58:38.933865 output: FIT description: Kernel Image image with one or more FDT blobs
215 05:58:38.934280 output: Created: Mon Dec 25 05:58:38 2023
216 05:58:38.934378 output: Image 0 (kernel-1)
217 05:58:38.934447 output: Description:
218 05:58:38.934530 output: Created: Mon Dec 25 05:58:38 2023
219 05:58:38.934594 output: Type: Kernel Image
220 05:58:38.934656 output: Compression: lzma compressed
221 05:58:38.934729 output: Data Size: 11481830 Bytes = 11212.72 KiB = 10.95 MiB
222 05:58:38.934789 output: Architecture: AArch64
223 05:58:38.934848 output: OS: Linux
224 05:58:38.934915 output: Load Address: 0x00000000
225 05:58:38.934973 output: Entry Point: 0x00000000
226 05:58:38.935032 output: Hash algo: crc32
227 05:58:38.935102 output: Hash value: a47c00f1
228 05:58:38.935168 output: Image 1 (fdt-1)
229 05:58:38.935230 output: Description: mt8192-asurada-spherion-r0
230 05:58:38.935290 output: Created: Mon Dec 25 05:58:38 2023
231 05:58:38.935353 output: Type: Flat Device Tree
232 05:58:38.935412 output: Compression: uncompressed
233 05:58:38.935469 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 05:58:38.935523 output: Architecture: AArch64
235 05:58:38.935586 output: Hash algo: crc32
236 05:58:38.935644 output: Hash value: cc4352de
237 05:58:38.935719 output: Image 2 (ramdisk-1)
238 05:58:38.935812 output: Description: unavailable
239 05:58:38.935870 output: Created: Mon Dec 25 05:58:38 2023
240 05:58:38.935925 output: Type: RAMDisk Image
241 05:58:38.935996 output: Compression: Unknown Compression
242 05:58:38.936058 output: Data Size: 98348206 Bytes = 96043.17 KiB = 93.79 MiB
243 05:58:38.936112 output: Architecture: AArch64
244 05:58:38.936166 output: OS: Linux
245 05:58:38.936230 output: Load Address: unavailable
246 05:58:38.936294 output: Entry Point: unavailable
247 05:58:38.936351 output: Hash algo: crc32
248 05:58:38.936416 output: Hash value: 033a19b6
249 05:58:38.936477 output: Default Configuration: 'conf-1'
250 05:58:38.936544 output: Configuration 0 (conf-1)
251 05:58:38.936603 output: Description: mt8192-asurada-spherion-r0
252 05:58:38.936667 output: Kernel: kernel-1
253 05:58:38.936733 output: Init Ramdisk: ramdisk-1
254 05:58:38.936798 output: FDT: fdt-1
255 05:58:38.936881 output: Loadables: kernel-1
256 05:58:38.936936 output:
257 05:58:38.937146 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
258 05:58:38.937270 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
259 05:58:38.937389 end: 1.5 prepare-tftp-overlay (duration 00:00:30) [common]
260 05:58:38.937487 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:28) [common]
261 05:58:38.937588 No LXC device requested
262 05:58:38.937682 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 05:58:38.937784 start: 1.7 deploy-device-env (timeout 00:09:28) [common]
264 05:58:38.937867 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 05:58:38.937952 Checking files for TFTP limit of 4294967296 bytes.
266 05:58:38.938536 end: 1 tftp-deploy (duration 00:00:32) [common]
267 05:58:38.938647 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 05:58:38.938759 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 05:58:38.938891 substitutions:
270 05:58:38.938970 - {DTB}: 12379448/tftp-deploy-81t6ocb1/dtb/mt8192-asurada-spherion-r0.dtb
271 05:58:38.939038 - {INITRD}: 12379448/tftp-deploy-81t6ocb1/ramdisk/ramdisk.cpio.gz
272 05:58:38.939101 - {KERNEL}: 12379448/tftp-deploy-81t6ocb1/kernel/Image
273 05:58:38.939160 - {LAVA_MAC}: None
274 05:58:38.939218 - {PRESEED_CONFIG}: None
275 05:58:38.939288 - {PRESEED_LOCAL}: None
276 05:58:38.939348 - {RAMDISK}: 12379448/tftp-deploy-81t6ocb1/ramdisk/ramdisk.cpio.gz
277 05:58:38.939406 - {ROOT_PART}: None
278 05:58:38.939472 - {ROOT}: None
279 05:58:38.939542 - {SERVER_IP}: 192.168.201.1
280 05:58:38.939602 - {TEE}: None
281 05:58:38.939657 Parsed boot commands:
282 05:58:38.939721 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 05:58:38.939920 Parsed boot commands: tftpboot 192.168.201.1 12379448/tftp-deploy-81t6ocb1/kernel/image.itb 12379448/tftp-deploy-81t6ocb1/kernel/cmdline
284 05:58:38.940062 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 05:58:38.940160 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 05:58:38.940276 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 05:58:38.940395 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 05:58:38.940483 Not connected, no need to disconnect.
289 05:58:38.940564 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 05:58:38.940659 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 05:58:38.940731 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
292 05:58:38.945073 Setting prompt string to ['lava-test: # ']
293 05:58:38.945521 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 05:58:38.945657 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 05:58:38.945760 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 05:58:38.945867 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 05:58:38.946088 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
298 05:58:44.088663 >> Command sent successfully.
299 05:58:44.091103 Returned 0 in 5 seconds
300 05:58:44.191479 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 05:58:44.191895 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 05:58:44.192022 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 05:58:44.192136 Setting prompt string to 'Starting depthcharge on Spherion...'
305 05:58:44.192233 Changing prompt to 'Starting depthcharge on Spherion...'
306 05:58:44.192371 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 05:58:44.192848 [Enter `^Ec?' for help]
308 05:58:44.365584
309 05:58:44.365737
310 05:58:44.365808 F0: 102B 0000
311 05:58:44.365875
312 05:58:44.365934 F3: 1001 0000 [0200]
313 05:58:44.365992
314 05:58:44.369345 F3: 1001 0000
315 05:58:44.369432
316 05:58:44.369499 F7: 102D 0000
317 05:58:44.369559
318 05:58:44.369618 F1: 0000 0000
319 05:58:44.369674
320 05:58:44.372025 V0: 0000 0000 [0001]
321 05:58:44.372111
322 05:58:44.372176 00: 0007 8000
323 05:58:44.372240
324 05:58:44.375838 01: 0000 0000
325 05:58:44.375945
326 05:58:44.376043 BP: 0C00 0209 [0000]
327 05:58:44.376104
328 05:58:44.379623 G0: 1182 0000
329 05:58:44.379732
330 05:58:44.379833 EC: 0000 0021 [4000]
331 05:58:44.379972
332 05:58:44.383490 S7: 0000 0000 [0000]
333 05:58:44.383601
334 05:58:44.383718 CC: 0000 0000 [0001]
335 05:58:44.383820
336 05:58:44.386602 T0: 0000 0040 [010F]
337 05:58:44.386688
338 05:58:44.386768 Jump to BL
339 05:58:44.386829
340 05:58:44.411957
341 05:58:44.412089
342 05:58:44.412157
343 05:58:44.419354 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 05:58:44.422947 ARM64: Exception handlers installed.
345 05:58:44.426670 ARM64: Testing exception
346 05:58:44.430904 ARM64: Done test exception
347 05:58:44.434932 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 05:58:44.445909 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 05:58:44.452807 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 05:58:44.462983 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 05:58:44.469849 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 05:58:44.476750 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 05:58:44.488569 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 05:58:44.495460 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 05:58:44.514455 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 05:58:44.518163 WDT: Last reset was cold boot
357 05:58:44.521844 SPI1(PAD0) initialized at 2873684 Hz
358 05:58:44.524807 SPI5(PAD0) initialized at 992727 Hz
359 05:58:44.527884 VBOOT: Loading verstage.
360 05:58:44.534955 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 05:58:44.539453 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 05:58:44.542508 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 05:58:44.545394 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 05:58:44.552224 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 05:58:44.558677 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 05:58:44.569551 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 05:58:44.569688
368 05:58:44.569756
369 05:58:44.580500 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 05:58:44.583702 ARM64: Exception handlers installed.
371 05:58:44.583792 ARM64: Testing exception
372 05:58:44.587454 ARM64: Done test exception
373 05:58:44.590550 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 05:58:44.597146 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 05:58:44.610459 Probing TPM: . done!
376 05:58:44.610592 TPM ready after 0 ms
377 05:58:44.618888 Connected to device vid:did:rid of 1ae0:0028:00
378 05:58:44.625635 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 05:58:44.685258 Initialized TPM device CR50 revision 0
380 05:58:44.695533 tlcl_send_startup: Startup return code is 0
381 05:58:44.695627 TPM: setup succeeded
382 05:58:44.707091 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 05:58:44.716096 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 05:58:44.730010 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 05:58:44.736820 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 05:58:44.740172 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 05:58:44.744980 in-header: 03 07 00 00 08 00 00 00
388 05:58:44.748476 in-data: aa e4 47 04 13 02 00 00
389 05:58:44.752510 Chrome EC: UHEPI supported
390 05:58:44.759909 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 05:58:44.763306 in-header: 03 95 00 00 08 00 00 00
392 05:58:44.767421 in-data: 18 20 20 08 00 00 00 00
393 05:58:44.767505 Phase 1
394 05:58:44.770888 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 05:58:44.774416 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 05:58:44.782005 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 05:58:44.785615 Recovery requested (1009000e)
398 05:58:44.795397 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 05:58:44.798676 tlcl_extend: response is 0
400 05:58:44.808101 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 05:58:44.814038 tlcl_extend: response is 0
402 05:58:44.820541 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 05:58:44.840783 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
404 05:58:44.847491 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 05:58:44.847587
406 05:58:44.847652
407 05:58:44.857322 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 05:58:44.860247 ARM64: Exception handlers installed.
409 05:58:44.863952 ARM64: Testing exception
410 05:58:44.864035 ARM64: Done test exception
411 05:58:44.885988 pmic_efuse_setting: Set efuses in 11 msecs
412 05:58:44.889475 pmwrap_interface_init: Select PMIF_VLD_RDY
413 05:58:44.896087 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 05:58:44.899563 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 05:58:44.906562 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 05:58:44.910596 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 05:58:44.914140 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 05:58:44.920792 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 05:58:44.925250 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 05:58:44.928241 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 05:58:44.931713 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 05:58:44.939610 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 05:58:44.943433 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 05:58:44.946834 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 05:58:44.950505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 05:58:44.958007 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 05:58:44.965153 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 05:58:44.969081 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 05:58:44.976784 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 05:58:44.980279 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 05:58:44.987001 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 05:58:44.990807 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 05:58:44.998367 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 05:58:45.002209 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 05:58:45.009510 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 05:58:45.013489 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 05:58:45.021436 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 05:58:45.024861 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 05:58:45.032052 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 05:58:45.035565 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 05:58:45.039224 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 05:58:45.042988 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 05:58:45.050987 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 05:58:45.054794 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 05:58:45.061790 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 05:58:45.065306 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 05:58:45.068936 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 05:58:45.076728 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 05:58:45.080105 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 05:58:45.084442 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 05:58:45.087912 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 05:58:45.095363 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 05:58:45.098955 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 05:58:45.102497 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 05:58:45.106120 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 05:58:45.113083 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 05:58:45.116587 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 05:58:45.120265 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 05:58:45.124638 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 05:58:45.128160 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 05:58:45.131947 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 05:58:45.135075 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 05:58:45.139204 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 05:58:45.150309 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 05:58:45.157469 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 05:58:45.160972 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 05:58:45.172399 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 05:58:45.179068 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 05:58:45.183363 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 05:58:45.186874 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 05:58:45.190871 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 05:58:45.199560 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2e
473 05:58:45.203270 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 05:58:45.211721 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 05:58:45.214597 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 05:58:45.223929 [RTC]rtc_get_frequency_meter,154: input=15, output=759
477 05:58:45.233629 [RTC]rtc_get_frequency_meter,154: input=23, output=943
478 05:58:45.242995 [RTC]rtc_get_frequency_meter,154: input=19, output=850
479 05:58:45.252779 [RTC]rtc_get_frequency_meter,154: input=17, output=805
480 05:58:45.262234 [RTC]rtc_get_frequency_meter,154: input=16, output=782
481 05:58:45.271410 [RTC]rtc_get_frequency_meter,154: input=16, output=783
482 05:58:45.281369 [RTC]rtc_get_frequency_meter,154: input=17, output=805
483 05:58:45.284702 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
484 05:58:45.288365 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
485 05:58:45.292575 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 05:58:45.299854 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
487 05:58:45.303374 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 05:58:45.307141 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
489 05:58:45.310737 ADC[4]: Raw value=906573 ID=7
490 05:58:45.310848 ADC[3]: Raw value=213810 ID=1
491 05:58:45.314378 RAM Code: 0x71
492 05:58:45.318670 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 05:58:45.322226 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 05:58:45.333767 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 05:58:45.337223 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 05:58:45.341464 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 05:58:45.345470 in-header: 03 07 00 00 08 00 00 00
498 05:58:45.349410 in-data: aa e4 47 04 13 02 00 00
499 05:58:45.349495 Chrome EC: UHEPI supported
500 05:58:45.356550 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 05:58:45.360163 in-header: 03 95 00 00 08 00 00 00
502 05:58:45.364298 in-data: 18 20 20 08 00 00 00 00
503 05:58:45.367907 MRC: failed to locate region type 0.
504 05:58:45.375611 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 05:58:45.375698 DRAM-K: Running full calibration
506 05:58:45.382985 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 05:58:45.386496 header.status = 0x0
508 05:58:45.386671 header.version = 0x6 (expected: 0x6)
509 05:58:45.390503 header.size = 0xd00 (expected: 0xd00)
510 05:58:45.393676 header.flags = 0x0
511 05:58:45.401312 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 05:58:45.417911 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
513 05:58:45.425010 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 05:58:45.429007 dram_init: ddr_geometry: 2
515 05:58:45.429133 [EMI] MDL number = 2
516 05:58:45.432700 [EMI] Get MDL freq = 0
517 05:58:45.432879 dram_init: ddr_type: 0
518 05:58:45.436143 is_discrete_lpddr4: 1
519 05:58:45.440577 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 05:58:45.440677
521 05:58:45.440810
522 05:58:45.440957 [Bian_co] ETT version 0.0.0.1
523 05:58:45.447861 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 05:58:45.447959
525 05:58:45.451449 dramc_set_vcore_voltage set vcore to 650000
526 05:58:45.451591 Read voltage for 800, 4
527 05:58:45.451688 Vio18 = 0
528 05:58:45.455374 Vcore = 650000
529 05:58:45.455484 Vdram = 0
530 05:58:45.455567 Vddq = 0
531 05:58:45.459264 Vmddr = 0
532 05:58:45.459408 dram_init: config_dvfs: 1
533 05:58:45.462741 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 05:58:45.470098 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 05:58:45.473610 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
536 05:58:45.477746 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
537 05:58:45.481363 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
538 05:58:45.484307 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
539 05:58:45.487806 MEM_TYPE=3, freq_sel=18
540 05:58:45.491419 sv_algorithm_assistance_LP4_1600
541 05:58:45.494248 ============ PULL DRAM RESETB DOWN ============
542 05:58:45.497953 ========== PULL DRAM RESETB DOWN end =========
543 05:58:45.505245 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 05:58:45.505374 ===================================
545 05:58:45.508793 LPDDR4 DRAM CONFIGURATION
546 05:58:45.512976 ===================================
547 05:58:45.513146 EX_ROW_EN[0] = 0x0
548 05:58:45.516580 EX_ROW_EN[1] = 0x0
549 05:58:45.516689 LP4Y_EN = 0x0
550 05:58:45.520123 WORK_FSP = 0x0
551 05:58:45.520215 WL = 0x2
552 05:58:45.523567 RL = 0x2
553 05:58:45.523737 BL = 0x2
554 05:58:45.527043 RPST = 0x0
555 05:58:45.527157 RD_PRE = 0x0
556 05:58:45.530577 WR_PRE = 0x1
557 05:58:45.530709 WR_PST = 0x0
558 05:58:45.534301 DBI_WR = 0x0
559 05:58:45.534402 DBI_RD = 0x0
560 05:58:45.537274 OTF = 0x1
561 05:58:45.540723 ===================================
562 05:58:45.544139 ===================================
563 05:58:45.544308 ANA top config
564 05:58:45.548028 ===================================
565 05:58:45.551591 DLL_ASYNC_EN = 0
566 05:58:45.551770 ALL_SLAVE_EN = 1
567 05:58:45.554883 NEW_RANK_MODE = 1
568 05:58:45.558334 DLL_IDLE_MODE = 1
569 05:58:45.561654 LP45_APHY_COMB_EN = 1
570 05:58:45.565079 TX_ODT_DIS = 1
571 05:58:45.565244 NEW_8X_MODE = 1
572 05:58:45.568614 ===================================
573 05:58:45.572789 ===================================
574 05:58:45.575363 data_rate = 1600
575 05:58:45.579287 CKR = 1
576 05:58:45.582572 DQ_P2S_RATIO = 8
577 05:58:45.585941 ===================================
578 05:58:45.586105 CA_P2S_RATIO = 8
579 05:58:45.589597 DQ_CA_OPEN = 0
580 05:58:45.592508 DQ_SEMI_OPEN = 0
581 05:58:45.596077 CA_SEMI_OPEN = 0
582 05:58:45.599079 CA_FULL_RATE = 0
583 05:58:45.602654 DQ_CKDIV4_EN = 1
584 05:58:45.602743 CA_CKDIV4_EN = 1
585 05:58:45.606128 CA_PREDIV_EN = 0
586 05:58:45.609054 PH8_DLY = 0
587 05:58:45.612612 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 05:58:45.616258 DQ_AAMCK_DIV = 4
589 05:58:45.619056 CA_AAMCK_DIV = 4
590 05:58:45.619142 CA_ADMCK_DIV = 4
591 05:58:45.622659 DQ_TRACK_CA_EN = 0
592 05:58:45.626199 CA_PICK = 800
593 05:58:45.629064 CA_MCKIO = 800
594 05:58:45.633251 MCKIO_SEMI = 0
595 05:58:45.633336 PLL_FREQ = 3068
596 05:58:45.636858 DQ_UI_PI_RATIO = 32
597 05:58:45.640443 CA_UI_PI_RATIO = 0
598 05:58:45.644158 ===================================
599 05:58:45.648315 ===================================
600 05:58:45.648420 memory_type:LPDDR4
601 05:58:45.652607 GP_NUM : 10
602 05:58:45.652700 SRAM_EN : 1
603 05:58:45.656132 MD32_EN : 0
604 05:58:45.660230 ===================================
605 05:58:45.660339 [ANA_INIT] >>>>>>>>>>>>>>
606 05:58:45.663477 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 05:58:45.667464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 05:58:45.670615 ===================================
609 05:58:45.674369 data_rate = 1600,PCW = 0X7600
610 05:58:45.677347 ===================================
611 05:58:45.680853 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 05:58:45.684271 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 05:58:45.691322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 05:58:45.694303 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 05:58:45.697954 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 05:58:45.701480 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 05:58:45.704780 [ANA_INIT] flow start
618 05:58:45.707582 [ANA_INIT] PLL >>>>>>>>
619 05:58:45.707668 [ANA_INIT] PLL <<<<<<<<
620 05:58:45.711078 [ANA_INIT] MIDPI >>>>>>>>
621 05:58:45.714510 [ANA_INIT] MIDPI <<<<<<<<
622 05:58:45.717591 [ANA_INIT] DLL >>>>>>>>
623 05:58:45.717701 [ANA_INIT] flow end
624 05:58:45.721647 ============ LP4 DIFF to SE enter ============
625 05:58:45.727651 ============ LP4 DIFF to SE exit ============
626 05:58:45.727751 [ANA_INIT] <<<<<<<<<<<<<
627 05:58:45.731357 [Flow] Enable top DCM control >>>>>
628 05:58:45.734800 [Flow] Enable top DCM control <<<<<
629 05:58:45.737670 Enable DLL master slave shuffle
630 05:58:45.744763 ==============================================================
631 05:58:45.744853 Gating Mode config
632 05:58:45.751351 ==============================================================
633 05:58:45.751440 Config description:
634 05:58:45.761520 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 05:58:45.768159 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 05:58:45.774591 SELPH_MODE 0: By rank 1: By Phase
637 05:58:45.777958 ==============================================================
638 05:58:45.781378 GAT_TRACK_EN = 1
639 05:58:45.784905 RX_GATING_MODE = 2
640 05:58:45.788226 RX_GATING_TRACK_MODE = 2
641 05:58:45.791554 SELPH_MODE = 1
642 05:58:45.794976 PICG_EARLY_EN = 1
643 05:58:45.797718 VALID_LAT_VALUE = 1
644 05:58:45.804897 ==============================================================
645 05:58:45.807716 Enter into Gating configuration >>>>
646 05:58:45.811431 Exit from Gating configuration <<<<
647 05:58:45.811517 Enter into DVFS_PRE_config >>>>>
648 05:58:45.824714 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 05:58:45.828126 Exit from DVFS_PRE_config <<<<<
650 05:58:45.831444 Enter into PICG configuration >>>>
651 05:58:45.834540 Exit from PICG configuration <<<<
652 05:58:45.834651 [RX_INPUT] configuration >>>>>
653 05:58:45.838223 [RX_INPUT] configuration <<<<<
654 05:58:45.844649 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 05:58:45.847713 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 05:58:45.854629 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 05:58:45.861448 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 05:58:45.867937 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 05:58:45.874524 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 05:58:45.878201 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 05:58:45.881125 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 05:58:45.887776 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 05:58:45.891196 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 05:58:45.894705 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 05:58:45.898163 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 05:58:45.901481 ===================================
667 05:58:45.904765 LPDDR4 DRAM CONFIGURATION
668 05:58:45.907903 ===================================
669 05:58:45.911525 EX_ROW_EN[0] = 0x0
670 05:58:45.911610 EX_ROW_EN[1] = 0x0
671 05:58:45.914458 LP4Y_EN = 0x0
672 05:58:45.914542 WORK_FSP = 0x0
673 05:58:45.918105 WL = 0x2
674 05:58:45.918188 RL = 0x2
675 05:58:45.921122 BL = 0x2
676 05:58:45.921205 RPST = 0x0
677 05:58:45.924660 RD_PRE = 0x0
678 05:58:45.924745 WR_PRE = 0x1
679 05:58:45.928432 WR_PST = 0x0
680 05:58:45.928515 DBI_WR = 0x0
681 05:58:45.931327 DBI_RD = 0x0
682 05:58:45.931410 OTF = 0x1
683 05:58:45.934928 ===================================
684 05:58:45.941460 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 05:58:45.944404 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 05:58:45.947905 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 05:58:45.951315 ===================================
688 05:58:45.954651 LPDDR4 DRAM CONFIGURATION
689 05:58:45.957955 ===================================
690 05:58:45.958041 EX_ROW_EN[0] = 0x10
691 05:58:45.961297 EX_ROW_EN[1] = 0x0
692 05:58:45.964552 LP4Y_EN = 0x0
693 05:58:45.964660 WORK_FSP = 0x0
694 05:58:45.968628 WL = 0x2
695 05:58:45.968711 RL = 0x2
696 05:58:45.971714 BL = 0x2
697 05:58:45.971817 RPST = 0x0
698 05:58:45.974751 RD_PRE = 0x0
699 05:58:45.974833 WR_PRE = 0x1
700 05:58:45.978027 WR_PST = 0x0
701 05:58:45.978110 DBI_WR = 0x0
702 05:58:45.981707 DBI_RD = 0x0
703 05:58:45.981793 OTF = 0x1
704 05:58:45.985080 ===================================
705 05:58:45.991952 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 05:58:45.995594 nWR fixed to 40
707 05:58:45.999018 [ModeRegInit_LP4] CH0 RK0
708 05:58:45.999154 [ModeRegInit_LP4] CH0 RK1
709 05:58:46.002440 [ModeRegInit_LP4] CH1 RK0
710 05:58:46.005439 [ModeRegInit_LP4] CH1 RK1
711 05:58:46.005526 match AC timing 13
712 05:58:46.012275 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 05:58:46.015660 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 05:58:46.018768 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 05:58:46.025268 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 05:58:46.028929 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 05:58:46.029031 [EMI DOE] emi_dcm 0
718 05:58:46.035778 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 05:58:46.035872 ==
720 05:58:46.039344 Dram Type= 6, Freq= 0, CH_0, rank 0
721 05:58:46.042206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 05:58:46.042294 ==
723 05:58:46.049231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 05:58:46.055622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 05:58:46.062763 [CA 0] Center 36 (6~67) winsize 62
726 05:58:46.066181 [CA 1] Center 37 (7~67) winsize 61
727 05:58:46.069477 [CA 2] Center 34 (4~65) winsize 62
728 05:58:46.072877 [CA 3] Center 33 (3~64) winsize 62
729 05:58:46.076397 [CA 4] Center 33 (3~63) winsize 61
730 05:58:46.079941 [CA 5] Center 32 (2~62) winsize 61
731 05:58:46.080060
732 05:58:46.082834 [CmdBusTrainingLP45] Vref(ca) range 1: 32
733 05:58:46.082917
734 05:58:46.086379 [CATrainingPosCal] consider 1 rank data
735 05:58:46.089935 u2DelayCellTimex100 = 270/100 ps
736 05:58:46.093513 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
737 05:58:46.096158 CA1 delay=37 (7~67),Diff = 5 PI (36 cell)
738 05:58:46.103051 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
739 05:58:46.106232 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
740 05:58:46.109448 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
741 05:58:46.113081 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
742 05:58:46.113236
743 05:58:46.116033 CA PerBit enable=1, Macro0, CA PI delay=32
744 05:58:46.116174
745 05:58:46.119587 [CBTSetCACLKResult] CA Dly = 32
746 05:58:46.119727 CS Dly: 5 (0~36)
747 05:58:46.122910 ==
748 05:58:46.123074 Dram Type= 6, Freq= 0, CH_0, rank 1
749 05:58:46.129286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 05:58:46.129438 ==
751 05:58:46.132747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 05:58:46.139509 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 05:58:46.149226 [CA 0] Center 36 (6~67) winsize 62
754 05:58:46.152079 [CA 1] Center 36 (6~67) winsize 62
755 05:58:46.155719 [CA 2] Center 34 (3~65) winsize 63
756 05:58:46.159225 [CA 3] Center 33 (3~64) winsize 62
757 05:58:46.162269 [CA 4] Center 32 (2~63) winsize 62
758 05:58:46.165844 [CA 5] Center 32 (2~63) winsize 62
759 05:58:46.165965
760 05:58:46.168725 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 05:58:46.168838
762 05:58:46.172311 [CATrainingPosCal] consider 2 rank data
763 05:58:46.175651 u2DelayCellTimex100 = 270/100 ps
764 05:58:46.178853 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
765 05:58:46.182533 CA1 delay=37 (7~67),Diff = 5 PI (36 cell)
766 05:58:46.188951 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
767 05:58:46.192453 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
768 05:58:46.195912 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
769 05:58:46.199456 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
770 05:58:46.199621
771 05:58:46.202318 CA PerBit enable=1, Macro0, CA PI delay=32
772 05:58:46.202424
773 05:58:46.205931 [CBTSetCACLKResult] CA Dly = 32
774 05:58:46.206035 CS Dly: 5 (0~37)
775 05:58:46.206104
776 05:58:46.209436 ----->DramcWriteLeveling(PI) begin...
777 05:58:46.213122 ==
778 05:58:46.213209 Dram Type= 6, Freq= 0, CH_0, rank 0
779 05:58:46.220199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 05:58:46.220305 ==
781 05:58:46.220376 Write leveling (Byte 0): 34 => 34
782 05:58:46.224473 Write leveling (Byte 1): 29 => 29
783 05:58:46.228029 DramcWriteLeveling(PI) end<-----
784 05:58:46.228118
785 05:58:46.228227 ==
786 05:58:46.230835 Dram Type= 6, Freq= 0, CH_0, rank 0
787 05:58:46.234306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 05:58:46.234422 ==
789 05:58:46.237863 [Gating] SW mode calibration
790 05:58:46.245245 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 05:58:46.252059 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 05:58:46.255320 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 05:58:46.258395 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
794 05:58:46.265599 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
795 05:58:46.268891 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 05:58:46.272075 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 05:58:46.275118 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 05:58:46.282169 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 05:58:46.285583 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 05:58:46.289001 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 05:58:46.295645 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 05:58:46.299155 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 05:58:46.301927 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 05:58:46.309171 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 05:58:46.311963 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 05:58:46.315558 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 05:58:46.321892 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 05:58:46.325362 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 05:58:46.328819 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
810 05:58:46.335263 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 05:58:46.338837 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
812 05:58:46.342398 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 05:58:46.348756 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 05:58:46.352140 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 05:58:46.355775 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 05:58:46.361954 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 05:58:46.365606 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 05:58:46.368488 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
819 05:58:46.371952 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
820 05:58:46.378528 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 05:58:46.381948 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 05:58:46.385302 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 05:58:46.392425 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 05:58:46.395405 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 05:58:46.398858 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
826 05:58:46.405812 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
827 05:58:46.409176 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
828 05:58:46.412419 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 05:58:46.418890 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 05:58:46.422390 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 05:58:46.425868 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 05:58:46.429133 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 05:58:46.435655 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
834 05:58:46.439043 0 11 8 | B1->B0 | 2d2d 4343 | 0 1 | (0 0) (0 0)
835 05:58:46.442600 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
836 05:58:46.449072 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 05:58:46.452596 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 05:58:46.456224 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 05:58:46.462518 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 05:58:46.466176 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 05:58:46.469081 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 05:58:46.475706 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
843 05:58:46.479304 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
844 05:58:46.482275 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 05:58:46.489427 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 05:58:46.492247 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 05:58:46.495809 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 05:58:46.502283 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 05:58:46.506096 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 05:58:46.508969 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 05:58:46.515478 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 05:58:46.518976 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 05:58:46.522312 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 05:58:46.525996 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 05:58:46.532517 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 05:58:46.535840 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 05:58:46.539211 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
858 05:58:46.545740 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
859 05:58:46.549210 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 05:58:46.552563 Total UI for P1: 0, mck2ui 16
861 05:58:46.555971 best dqsien dly found for B0: ( 0, 14, 6)
862 05:58:46.559296 Total UI for P1: 0, mck2ui 16
863 05:58:46.562863 best dqsien dly found for B1: ( 0, 14, 10)
864 05:58:46.566369 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
865 05:58:46.569945 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
866 05:58:46.570029
867 05:58:46.573524 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
868 05:58:46.576627 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
869 05:58:46.579893 [Gating] SW calibration Done
870 05:58:46.579978 ==
871 05:58:46.583418 Dram Type= 6, Freq= 0, CH_0, rank 0
872 05:58:46.586780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 05:58:46.586898 ==
874 05:58:46.589914 RX Vref Scan: 0
875 05:58:46.589995
876 05:58:46.590059 RX Vref 0 -> 0, step: 1
877 05:58:46.590121
878 05:58:46.593582 RX Delay -130 -> 252, step: 16
879 05:58:46.596619 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
880 05:58:46.603797 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
881 05:58:46.606645 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
882 05:58:46.610230 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
883 05:58:46.613678 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
884 05:58:46.617251 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
885 05:58:46.623528 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
886 05:58:46.626909 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
887 05:58:46.630098 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
888 05:58:46.634125 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
889 05:58:46.636883 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
890 05:58:46.643555 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
891 05:58:46.647259 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
892 05:58:46.650302 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
893 05:58:46.653988 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
894 05:58:46.656922 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
895 05:58:46.660584 ==
896 05:58:46.660668 Dram Type= 6, Freq= 0, CH_0, rank 0
897 05:58:46.666981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 05:58:46.667065 ==
899 05:58:46.667131 DQS Delay:
900 05:58:46.670530 DQS0 = 0, DQS1 = 0
901 05:58:46.670613 DQM Delay:
902 05:58:46.673527 DQM0 = 88, DQM1 = 80
903 05:58:46.673609 DQ Delay:
904 05:58:46.676797 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
905 05:58:46.680797 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
906 05:58:46.684035 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
907 05:58:46.687257 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
908 05:58:46.687441
909 05:58:46.687543
910 05:58:46.687682 ==
911 05:58:46.690493 Dram Type= 6, Freq= 0, CH_0, rank 0
912 05:58:46.694096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 05:58:46.694197 ==
914 05:58:46.694265
915 05:58:46.694334
916 05:58:46.697080 TX Vref Scan disable
917 05:58:46.700150 == TX Byte 0 ==
918 05:58:46.703781 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
919 05:58:46.706902 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
920 05:58:46.710515 == TX Byte 1 ==
921 05:58:46.714010 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
922 05:58:46.716821 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
923 05:58:46.716930 ==
924 05:58:46.720426 Dram Type= 6, Freq= 0, CH_0, rank 0
925 05:58:46.723617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 05:58:46.723709 ==
927 05:58:46.738449 TX Vref=22, minBit 8, minWin=27, winSum=448
928 05:58:46.741831 TX Vref=24, minBit 8, minWin=27, winSum=451
929 05:58:46.745153 TX Vref=26, minBit 0, minWin=28, winSum=456
930 05:58:46.748645 TX Vref=28, minBit 5, minWin=28, winSum=457
931 05:58:46.752229 TX Vref=30, minBit 0, minWin=28, winSum=456
932 05:58:46.758753 TX Vref=32, minBit 10, minWin=27, winSum=454
933 05:58:46.762203 [TxChooseVref] Worse bit 5, Min win 28, Win sum 457, Final Vref 28
934 05:58:46.762294
935 05:58:46.764999 Final TX Range 1 Vref 28
936 05:58:46.765084
937 05:58:46.765150 ==
938 05:58:46.768523 Dram Type= 6, Freq= 0, CH_0, rank 0
939 05:58:46.772063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 05:58:46.772148 ==
941 05:58:46.774823
942 05:58:46.774930
943 05:58:46.775043 TX Vref Scan disable
944 05:58:46.778524 == TX Byte 0 ==
945 05:58:46.782207 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
946 05:58:46.785041 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
947 05:58:46.788656 == TX Byte 1 ==
948 05:58:46.792093 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
949 05:58:46.795223 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
950 05:58:46.798873
951 05:58:46.798964 [DATLAT]
952 05:58:46.799044 Freq=800, CH0 RK0
953 05:58:46.799108
954 05:58:46.802347 DATLAT Default: 0xa
955 05:58:46.802429 0, 0xFFFF, sum = 0
956 05:58:46.805082 1, 0xFFFF, sum = 0
957 05:58:46.805174 2, 0xFFFF, sum = 0
958 05:58:46.808545 3, 0xFFFF, sum = 0
959 05:58:46.808630 4, 0xFFFF, sum = 0
960 05:58:46.812202 5, 0xFFFF, sum = 0
961 05:58:46.812356 6, 0xFFFF, sum = 0
962 05:58:46.815808 7, 0xFFFF, sum = 0
963 05:58:46.818864 8, 0xFFFF, sum = 0
964 05:58:46.818966 9, 0x0, sum = 1
965 05:58:46.819038 10, 0x0, sum = 2
966 05:58:46.822330 11, 0x0, sum = 3
967 05:58:46.822413 12, 0x0, sum = 4
968 05:58:46.825229 best_step = 10
969 05:58:46.825311
970 05:58:46.825412 ==
971 05:58:46.828624 Dram Type= 6, Freq= 0, CH_0, rank 0
972 05:58:46.832149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 05:58:46.832293 ==
974 05:58:46.835393 RX Vref Scan: 1
975 05:58:46.835527
976 05:58:46.835626 Set Vref Range= 32 -> 127
977 05:58:46.835718
978 05:58:46.838536 RX Vref 32 -> 127, step: 1
979 05:58:46.838688
980 05:58:46.842090 RX Delay -95 -> 252, step: 8
981 05:58:46.842174
982 05:58:46.844973 Set Vref, RX VrefLevel [Byte0]: 32
983 05:58:46.849100 [Byte1]: 32
984 05:58:46.849221
985 05:58:46.852330 Set Vref, RX VrefLevel [Byte0]: 33
986 05:58:46.855762 [Byte1]: 33
987 05:58:46.858962
988 05:58:46.859047 Set Vref, RX VrefLevel [Byte0]: 34
989 05:58:46.862334 [Byte1]: 34
990 05:58:46.866456
991 05:58:46.866539 Set Vref, RX VrefLevel [Byte0]: 35
992 05:58:46.870212 [Byte1]: 35
993 05:58:46.874017
994 05:58:46.874165 Set Vref, RX VrefLevel [Byte0]: 36
995 05:58:46.877745 [Byte1]: 36
996 05:58:46.882053
997 05:58:46.882221 Set Vref, RX VrefLevel [Byte0]: 37
998 05:58:46.885491 [Byte1]: 37
999 05:58:46.889674
1000 05:58:46.889800 Set Vref, RX VrefLevel [Byte0]: 38
1001 05:58:46.893147 [Byte1]: 38
1002 05:58:46.897412
1003 05:58:46.897571 Set Vref, RX VrefLevel [Byte0]: 39
1004 05:58:46.900849 [Byte1]: 39
1005 05:58:46.905237
1006 05:58:46.905430 Set Vref, RX VrefLevel [Byte0]: 40
1007 05:58:46.908685 [Byte1]: 40
1008 05:58:46.911937
1009 05:58:46.912059 Set Vref, RX VrefLevel [Byte0]: 41
1010 05:58:46.915568 [Byte1]: 41
1011 05:58:46.919912
1012 05:58:46.920041 Set Vref, RX VrefLevel [Byte0]: 42
1013 05:58:46.922786 [Byte1]: 42
1014 05:58:46.926998
1015 05:58:46.927083 Set Vref, RX VrefLevel [Byte0]: 43
1016 05:58:46.930704 [Byte1]: 43
1017 05:58:46.934870
1018 05:58:46.934967 Set Vref, RX VrefLevel [Byte0]: 44
1019 05:58:46.938438 [Byte1]: 44
1020 05:58:46.942652
1021 05:58:46.942739 Set Vref, RX VrefLevel [Byte0]: 45
1022 05:58:46.945552 [Byte1]: 45
1023 05:58:46.950462
1024 05:58:46.950574 Set Vref, RX VrefLevel [Byte0]: 46
1025 05:58:46.953278 [Byte1]: 46
1026 05:58:46.957473
1027 05:58:46.957556 Set Vref, RX VrefLevel [Byte0]: 47
1028 05:58:46.960914 [Byte1]: 47
1029 05:58:46.965181
1030 05:58:46.965265 Set Vref, RX VrefLevel [Byte0]: 48
1031 05:58:46.968676 [Byte1]: 48
1032 05:58:46.972754
1033 05:58:46.972838 Set Vref, RX VrefLevel [Byte0]: 49
1034 05:58:46.976046 [Byte1]: 49
1035 05:58:46.980544
1036 05:58:46.980630 Set Vref, RX VrefLevel [Byte0]: 50
1037 05:58:46.984026 [Byte1]: 50
1038 05:58:46.987985
1039 05:58:46.988070 Set Vref, RX VrefLevel [Byte0]: 51
1040 05:58:46.991246 [Byte1]: 51
1041 05:58:46.995898
1042 05:58:46.995988 Set Vref, RX VrefLevel [Byte0]: 52
1043 05:58:46.999149 [Byte1]: 52
1044 05:58:47.003097
1045 05:58:47.003194 Set Vref, RX VrefLevel [Byte0]: 53
1046 05:58:47.006739 [Byte1]: 53
1047 05:58:47.010698
1048 05:58:47.010784 Set Vref, RX VrefLevel [Byte0]: 54
1049 05:58:47.014020 [Byte1]: 54
1050 05:58:47.018581
1051 05:58:47.018667 Set Vref, RX VrefLevel [Byte0]: 55
1052 05:58:47.021634 [Byte1]: 55
1053 05:58:47.026036
1054 05:58:47.026118 Set Vref, RX VrefLevel [Byte0]: 56
1055 05:58:47.029594 [Byte1]: 56
1056 05:58:47.033864
1057 05:58:47.033947 Set Vref, RX VrefLevel [Byte0]: 57
1058 05:58:47.036915 [Byte1]: 57
1059 05:58:47.041146
1060 05:58:47.041251 Set Vref, RX VrefLevel [Byte0]: 58
1061 05:58:47.044810 [Byte1]: 58
1062 05:58:47.048935
1063 05:58:47.049050 Set Vref, RX VrefLevel [Byte0]: 59
1064 05:58:47.052619 [Byte1]: 59
1065 05:58:47.056137
1066 05:58:47.056217 Set Vref, RX VrefLevel [Byte0]: 60
1067 05:58:47.059631 [Byte1]: 60
1068 05:58:47.063996
1069 05:58:47.064077 Set Vref, RX VrefLevel [Byte0]: 61
1070 05:58:47.067592 [Byte1]: 61
1071 05:58:47.071954
1072 05:58:47.072035 Set Vref, RX VrefLevel [Byte0]: 62
1073 05:58:47.074827 [Byte1]: 62
1074 05:58:47.079202
1075 05:58:47.079282 Set Vref, RX VrefLevel [Byte0]: 63
1076 05:58:47.082646 [Byte1]: 63
1077 05:58:47.086864
1078 05:58:47.086945 Set Vref, RX VrefLevel [Byte0]: 64
1079 05:58:47.090497 [Byte1]: 64
1080 05:58:47.094623
1081 05:58:47.094703 Set Vref, RX VrefLevel [Byte0]: 65
1082 05:58:47.098167 [Byte1]: 65
1083 05:58:47.102468
1084 05:58:47.102549 Set Vref, RX VrefLevel [Byte0]: 66
1085 05:58:47.105138 [Byte1]: 66
1086 05:58:47.109509
1087 05:58:47.109589 Set Vref, RX VrefLevel [Byte0]: 67
1088 05:58:47.113149 [Byte1]: 67
1089 05:58:47.117366
1090 05:58:47.117446 Set Vref, RX VrefLevel [Byte0]: 68
1091 05:58:47.120764 [Byte1]: 68
1092 05:58:47.124651
1093 05:58:47.124731 Set Vref, RX VrefLevel [Byte0]: 69
1094 05:58:47.128374 [Byte1]: 69
1095 05:58:47.132552
1096 05:58:47.132632 Set Vref, RX VrefLevel [Byte0]: 70
1097 05:58:47.135896 [Byte1]: 70
1098 05:58:47.140272
1099 05:58:47.140406 Set Vref, RX VrefLevel [Byte0]: 71
1100 05:58:47.143426 [Byte1]: 71
1101 05:58:47.147612
1102 05:58:47.147771 Set Vref, RX VrefLevel [Byte0]: 72
1103 05:58:47.150807 [Byte1]: 72
1104 05:58:47.155600
1105 05:58:47.155781 Set Vref, RX VrefLevel [Byte0]: 73
1106 05:58:47.158526 [Byte1]: 73
1107 05:58:47.162725
1108 05:58:47.162935 Set Vref, RX VrefLevel [Byte0]: 74
1109 05:58:47.165814 [Byte1]: 74
1110 05:58:47.170279
1111 05:58:47.170464 Set Vref, RX VrefLevel [Byte0]: 75
1112 05:58:47.173711 [Byte1]: 75
1113 05:58:47.178117
1114 05:58:47.178265 Set Vref, RX VrefLevel [Byte0]: 76
1115 05:58:47.181229 [Byte1]: 76
1116 05:58:47.185376
1117 05:58:47.185467 Set Vref, RX VrefLevel [Byte0]: 77
1118 05:58:47.189130 [Byte1]: 77
1119 05:58:47.193218
1120 05:58:47.193302 Final RX Vref Byte 0 = 56 to rank0
1121 05:58:47.196871 Final RX Vref Byte 1 = 57 to rank0
1122 05:58:47.199808 Final RX Vref Byte 0 = 56 to rank1
1123 05:58:47.203364 Final RX Vref Byte 1 = 57 to rank1==
1124 05:58:47.206762 Dram Type= 6, Freq= 0, CH_0, rank 0
1125 05:58:47.213219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 05:58:47.213302 ==
1127 05:58:47.213367 DQS Delay:
1128 05:58:47.213426 DQS0 = 0, DQS1 = 0
1129 05:58:47.216790 DQM Delay:
1130 05:58:47.216870 DQM0 = 92, DQM1 = 84
1131 05:58:47.220436 DQ Delay:
1132 05:58:47.223300 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1133 05:58:47.223380 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1134 05:58:47.226903 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1135 05:58:47.233290 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1136 05:58:47.233372
1137 05:58:47.233436
1138 05:58:47.240408 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a40, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1139 05:58:47.243314 CH0 RK0: MR19=606, MR18=4A40
1140 05:58:47.250175 CH0_RK0: MR19=0x606, MR18=0x4A40, DQSOSC=391, MR23=63, INC=96, DEC=64
1141 05:58:47.250304
1142 05:58:47.253734 ----->DramcWriteLeveling(PI) begin...
1143 05:58:47.253818 ==
1144 05:58:47.256617 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 05:58:47.260170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 05:58:47.260253 ==
1147 05:58:47.263570 Write leveling (Byte 0): 34 => 34
1148 05:58:47.266940 Write leveling (Byte 1): 29 => 29
1149 05:58:47.270395 DramcWriteLeveling(PI) end<-----
1150 05:58:47.270478
1151 05:58:47.270543 ==
1152 05:58:47.273634 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 05:58:47.276790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 05:58:47.276883 ==
1155 05:58:47.279855 [Gating] SW mode calibration
1156 05:58:47.327269 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1157 05:58:47.327908 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1158 05:58:47.328736 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 05:58:47.328818 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1160 05:58:47.329125 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1161 05:58:47.329206 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 05:58:47.329282 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 05:58:47.329396 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 05:58:47.329490 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 05:58:47.329563 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 05:58:47.350860 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 05:58:47.351535 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 05:58:47.351805 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 05:58:47.351873 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 05:58:47.351935 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 05:58:47.355192 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 05:58:47.358894 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 05:58:47.361637 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 05:58:47.369193 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 05:58:47.372084 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 05:58:47.375502 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1177 05:58:47.378460 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 05:58:47.385443 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 05:58:47.389040 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 05:58:47.391848 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 05:58:47.398774 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 05:58:47.401625 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 05:58:47.405238 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 05:58:47.411750 0 9 8 | B1->B0 | 2d2d 2c2c | 1 1 | (1 1) (0 0)
1185 05:58:47.415149 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 05:58:47.418937 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 05:58:47.425426 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 05:58:47.428458 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 05:58:47.431980 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 05:58:47.438854 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 05:58:47.441824 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 05:58:47.445349 0 10 8 | B1->B0 | 2929 2828 | 0 0 | (1 0) (0 0)
1193 05:58:47.452074 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 05:58:47.455801 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 05:58:47.459667 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 05:58:47.463164 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 05:58:47.466813 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 05:58:47.473941 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 05:58:47.477670 0 11 4 | B1->B0 | 2929 2727 | 0 0 | (0 0) (0 0)
1200 05:58:47.481228 0 11 8 | B1->B0 | 3c3c 3c3c | 0 0 | (0 0) (0 0)
1201 05:58:47.484408 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 05:58:47.491510 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 05:58:47.495129 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 05:58:47.498662 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 05:58:47.505119 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 05:58:47.508718 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 05:58:47.511610 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 05:58:47.514941 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1209 05:58:47.521262 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1210 05:58:47.524799 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 05:58:47.528419 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 05:58:47.534998 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 05:58:47.538535 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 05:58:47.550842 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 05:58:47.551024 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 05:58:47.551577 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 05:58:47.554723 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 05:58:47.561678 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 05:58:47.565294 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 05:58:47.568449 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 05:58:47.575255 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 05:58:47.578427 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 05:58:47.581440 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 05:58:47.588633 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1225 05:58:47.592089 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 05:58:47.595278 Total UI for P1: 0, mck2ui 16
1227 05:58:47.598195 best dqsien dly found for B0: ( 0, 14, 8)
1228 05:58:47.601937 Total UI for P1: 0, mck2ui 16
1229 05:58:47.605387 best dqsien dly found for B1: ( 0, 14, 8)
1230 05:58:47.608913 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1231 05:58:47.611806 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1232 05:58:47.612163
1233 05:58:47.615455 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1234 05:58:47.618380 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1235 05:58:47.621781 [Gating] SW calibration Done
1236 05:58:47.622135 ==
1237 05:58:47.625366 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 05:58:47.628369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 05:58:47.628895 ==
1240 05:58:47.631907 RX Vref Scan: 0
1241 05:58:47.632244
1242 05:58:47.632562 RX Vref 0 -> 0, step: 1
1243 05:58:47.635391
1244 05:58:47.635882 RX Delay -130 -> 252, step: 16
1245 05:58:47.641911 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1246 05:58:47.645440 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1247 05:58:47.648659 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1248 05:58:47.652361 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1249 05:58:47.655174 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1250 05:58:47.659145 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1251 05:58:47.665089 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1252 05:58:47.668583 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1253 05:58:47.671879 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1254 05:58:47.675338 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1255 05:58:47.678469 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1256 05:58:47.685221 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1257 05:58:47.688508 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1258 05:58:47.691656 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1259 05:58:47.695060 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1260 05:58:47.698803 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1261 05:58:47.701825 ==
1262 05:58:47.705478 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 05:58:47.708705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 05:58:47.708863 ==
1265 05:58:47.708967 DQS Delay:
1266 05:58:47.712028 DQS0 = 0, DQS1 = 0
1267 05:58:47.712160 DQM Delay:
1268 05:58:47.715146 DQM0 = 91, DQM1 = 81
1269 05:58:47.715265 DQ Delay:
1270 05:58:47.718611 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1271 05:58:47.722137 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1272 05:58:47.725764 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1273 05:58:47.728273 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1274 05:58:47.728375
1275 05:58:47.728457
1276 05:58:47.728526 ==
1277 05:58:47.731986 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 05:58:47.735478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 05:58:47.735595 ==
1280 05:58:47.735663
1281 05:58:47.735764
1282 05:58:47.739031 TX Vref Scan disable
1283 05:58:47.742020 == TX Byte 0 ==
1284 05:58:47.745450 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1285 05:58:47.749008 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1286 05:58:47.751879 == TX Byte 1 ==
1287 05:58:47.755291 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1288 05:58:47.758734 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1289 05:58:47.758868 ==
1290 05:58:47.762218 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 05:58:47.765215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 05:58:47.768772 ==
1293 05:58:47.780957 TX Vref=22, minBit 8, minWin=27, winSum=446
1294 05:58:47.783721 TX Vref=24, minBit 8, minWin=27, winSum=453
1295 05:58:47.786986 TX Vref=26, minBit 1, minWin=28, winSum=456
1296 05:58:47.790955 TX Vref=28, minBit 1, minWin=28, winSum=456
1297 05:58:47.794213 TX Vref=30, minBit 7, minWin=28, winSum=458
1298 05:58:47.797045 TX Vref=32, minBit 4, minWin=28, winSum=456
1299 05:58:47.804182 [TxChooseVref] Worse bit 7, Min win 28, Win sum 458, Final Vref 30
1300 05:58:47.804315
1301 05:58:47.807116 Final TX Range 1 Vref 30
1302 05:58:47.807200
1303 05:58:47.807264 ==
1304 05:58:47.810609 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 05:58:47.814077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 05:58:47.814163 ==
1307 05:58:47.814231
1308 05:58:47.814304
1309 05:58:47.817245 TX Vref Scan disable
1310 05:58:47.820399 == TX Byte 0 ==
1311 05:58:47.824243 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1312 05:58:47.827395 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1313 05:58:47.830689 == TX Byte 1 ==
1314 05:58:47.833766 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1315 05:58:47.837187 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1316 05:58:47.837270
1317 05:58:47.840930 [DATLAT]
1318 05:58:47.841034 Freq=800, CH0 RK1
1319 05:58:47.841100
1320 05:58:47.843806 DATLAT Default: 0xa
1321 05:58:47.843901 0, 0xFFFF, sum = 0
1322 05:58:47.847421 1, 0xFFFF, sum = 0
1323 05:58:47.847519 2, 0xFFFF, sum = 0
1324 05:58:47.851097 3, 0xFFFF, sum = 0
1325 05:58:47.851212 4, 0xFFFF, sum = 0
1326 05:58:47.853967 5, 0xFFFF, sum = 0
1327 05:58:47.854049 6, 0xFFFF, sum = 0
1328 05:58:47.857459 7, 0xFFFF, sum = 0
1329 05:58:47.857541 8, 0xFFFF, sum = 0
1330 05:58:47.861004 9, 0x0, sum = 1
1331 05:58:47.861085 10, 0x0, sum = 2
1332 05:58:47.864399 11, 0x0, sum = 3
1333 05:58:47.864480 12, 0x0, sum = 4
1334 05:58:47.867268 best_step = 10
1335 05:58:47.867347
1336 05:58:47.867410 ==
1337 05:58:47.870869 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 05:58:47.873758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 05:58:47.873839 ==
1340 05:58:47.877459 RX Vref Scan: 0
1341 05:58:47.877540
1342 05:58:47.877604 RX Vref 0 -> 0, step: 1
1343 05:58:47.877665
1344 05:58:47.880953 RX Delay -95 -> 252, step: 8
1345 05:58:47.887542 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1346 05:58:47.891039 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1347 05:58:47.893816 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1348 05:58:47.897216 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1349 05:58:47.900665 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1350 05:58:47.907361 iDelay=209, Bit 5, Center 84 (-31 ~ 200) 232
1351 05:58:47.910625 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1352 05:58:47.913978 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1353 05:58:47.917539 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1354 05:58:47.921108 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1355 05:58:47.924027 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1356 05:58:47.931018 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1357 05:58:47.934045 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1358 05:58:47.937771 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1359 05:58:47.941360 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1360 05:58:47.944179 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1361 05:58:47.947606 ==
1362 05:58:47.950576 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 05:58:47.954217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 05:58:47.954301 ==
1365 05:58:47.954366 DQS Delay:
1366 05:58:47.957906 DQS0 = 0, DQS1 = 0
1367 05:58:47.957987 DQM Delay:
1368 05:58:47.960864 DQM0 = 93, DQM1 = 82
1369 05:58:47.960945 DQ Delay:
1370 05:58:47.964119 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1371 05:58:47.967909 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1372 05:58:47.970729 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1373 05:58:47.974159 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1374 05:58:47.974242
1375 05:58:47.974307
1376 05:58:47.981225 [DQSOSCAuto] RK1, (LSB)MR18= 0x4011, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1377 05:58:47.983936 CH0 RK1: MR19=606, MR18=4011
1378 05:58:47.991170 CH0_RK1: MR19=0x606, MR18=0x4011, DQSOSC=393, MR23=63, INC=95, DEC=63
1379 05:58:47.994236 [RxdqsGatingPostProcess] freq 800
1380 05:58:48.000638 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1381 05:58:48.000722 Pre-setting of DQS Precalculation
1382 05:58:48.007620 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1383 05:58:48.007703 ==
1384 05:58:48.010985 Dram Type= 6, Freq= 0, CH_1, rank 0
1385 05:58:48.014254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 05:58:48.014337 ==
1387 05:58:48.020974 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1388 05:58:48.027210 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1389 05:58:48.035374 [CA 0] Center 36 (6~67) winsize 62
1390 05:58:48.038929 [CA 1] Center 36 (6~67) winsize 62
1391 05:58:48.041762 [CA 2] Center 35 (5~66) winsize 62
1392 05:58:48.045599 [CA 3] Center 34 (4~65) winsize 62
1393 05:58:48.048403 [CA 4] Center 35 (5~65) winsize 61
1394 05:58:48.052128 [CA 5] Center 34 (4~64) winsize 61
1395 05:58:48.052206
1396 05:58:48.055558 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1397 05:58:48.055653
1398 05:58:48.059004 [CATrainingPosCal] consider 1 rank data
1399 05:58:48.062518 u2DelayCellTimex100 = 270/100 ps
1400 05:58:48.065237 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1401 05:58:48.069234 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1402 05:58:48.075413 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1403 05:58:48.079121 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1404 05:58:48.082032 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1405 05:58:48.085836 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1406 05:58:48.085918
1407 05:58:48.089105 CA PerBit enable=1, Macro0, CA PI delay=34
1408 05:58:48.089217
1409 05:58:48.092155 [CBTSetCACLKResult] CA Dly = 34
1410 05:58:48.092231 CS Dly: 6 (0~37)
1411 05:58:48.092370 ==
1412 05:58:48.095691 Dram Type= 6, Freq= 0, CH_1, rank 1
1413 05:58:48.102569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 05:58:48.102673 ==
1415 05:58:48.105346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 05:58:48.112519 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 05:58:48.122240 [CA 0] Center 36 (6~67) winsize 62
1418 05:58:48.125600 [CA 1] Center 37 (6~68) winsize 63
1419 05:58:48.129083 [CA 2] Center 35 (5~66) winsize 62
1420 05:58:48.133129 [CA 3] Center 34 (4~65) winsize 62
1421 05:58:48.136533 [CA 4] Center 35 (5~66) winsize 62
1422 05:58:48.140431 [CA 5] Center 34 (4~65) winsize 62
1423 05:58:48.140528
1424 05:58:48.144741 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1425 05:58:48.144814
1426 05:58:48.144875 [CATrainingPosCal] consider 2 rank data
1427 05:58:48.148260 u2DelayCellTimex100 = 270/100 ps
1428 05:58:48.151904 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1429 05:58:48.155672 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1430 05:58:48.159132 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1431 05:58:48.162560 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1432 05:58:48.166110 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1433 05:58:48.172582 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1434 05:58:48.172657
1435 05:58:48.176141 CA PerBit enable=1, Macro0, CA PI delay=34
1436 05:58:48.176236
1437 05:58:48.178866 [CBTSetCACLKResult] CA Dly = 34
1438 05:58:48.178944 CS Dly: 6 (0~38)
1439 05:58:48.179041
1440 05:58:48.182439 ----->DramcWriteLeveling(PI) begin...
1441 05:58:48.182525 ==
1442 05:58:48.185813 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 05:58:48.189222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 05:58:48.192521 ==
1445 05:58:48.192600 Write leveling (Byte 0): 24 => 24
1446 05:58:48.195772 Write leveling (Byte 1): 25 => 25
1447 05:58:48.199092 DramcWriteLeveling(PI) end<-----
1448 05:58:48.199173
1449 05:58:48.199254 ==
1450 05:58:48.202357 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 05:58:48.208799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 05:58:48.208889 ==
1453 05:58:48.208992 [Gating] SW mode calibration
1454 05:58:48.219180 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1455 05:58:48.222637 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1456 05:58:48.225702 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1457 05:58:48.232556 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1458 05:58:48.235908 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 05:58:48.239323 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 05:58:48.245565 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 05:58:48.249483 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 05:58:48.252812 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 05:58:48.259277 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 05:58:48.262872 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 05:58:48.265807 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 05:58:48.272804 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 05:58:48.275799 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 05:58:48.279314 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 05:58:48.285862 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 05:58:48.289461 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 05:58:48.292947 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 05:58:48.299221 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1473 05:58:48.302587 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1474 05:58:48.306110 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1475 05:58:48.309568 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 05:58:48.315911 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 05:58:48.319388 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 05:58:48.322886 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 05:58:48.329566 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 05:58:48.332861 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 05:58:48.336063 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1482 05:58:48.342721 0 9 8 | B1->B0 | 3131 3333 | 0 0 | (0 0) (0 0)
1483 05:58:48.346015 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 05:58:48.349290 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 05:58:48.356813 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 05:58:48.359990 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 05:58:48.363649 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 05:58:48.370010 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1489 05:58:48.372842 0 10 4 | B1->B0 | 3434 2929 | 0 1 | (0 1) (1 1)
1490 05:58:48.376647 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 05:58:48.383315 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 05:58:48.386298 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 05:58:48.389838 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 05:58:48.393620 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 05:58:48.400094 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 05:58:48.403620 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 05:58:48.406384 0 11 4 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
1498 05:58:48.413413 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1499 05:58:48.416906 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 05:58:48.419869 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 05:58:48.426750 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 05:58:48.429613 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 05:58:48.433034 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 05:58:48.439921 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1505 05:58:48.443475 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1506 05:58:48.447031 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1507 05:58:48.453001 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 05:58:48.456278 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 05:58:48.460029 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 05:58:48.466328 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 05:58:48.469581 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 05:58:48.472656 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 05:58:48.476107 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 05:58:48.482857 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 05:58:48.486469 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 05:58:48.489531 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 05:58:48.496828 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 05:58:48.499563 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 05:58:48.503174 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 05:58:48.509553 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 05:58:48.513251 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1522 05:58:48.516802 Total UI for P1: 0, mck2ui 16
1523 05:58:48.519639 best dqsien dly found for B1: ( 0, 14, 2)
1524 05:58:48.523073 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 05:58:48.526478 Total UI for P1: 0, mck2ui 16
1526 05:58:48.530170 best dqsien dly found for B0: ( 0, 14, 4)
1527 05:58:48.533199 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1528 05:58:48.536651 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1529 05:58:48.536732
1530 05:58:48.540112 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1531 05:58:48.546285 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1532 05:58:48.546435 [Gating] SW calibration Done
1533 05:58:48.546510 ==
1534 05:58:48.549825 Dram Type= 6, Freq= 0, CH_1, rank 0
1535 05:58:48.556256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1536 05:58:48.556417 ==
1537 05:58:48.556499 RX Vref Scan: 0
1538 05:58:48.556568
1539 05:58:48.560157 RX Vref 0 -> 0, step: 1
1540 05:58:48.560353
1541 05:58:48.563383 RX Delay -130 -> 252, step: 16
1542 05:58:48.566212 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1543 05:58:48.569750 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1544 05:58:48.573250 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1545 05:58:48.579463 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1546 05:58:48.583186 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1547 05:58:48.586232 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1548 05:58:48.589525 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1549 05:58:48.593283 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1550 05:58:48.599978 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1551 05:58:48.603388 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1552 05:58:48.607072 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1553 05:58:48.609990 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1554 05:58:48.613639 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1555 05:58:48.616669 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1556 05:58:48.624472 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1557 05:58:48.626929 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1558 05:58:48.627307 ==
1559 05:58:48.630401 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 05:58:48.633680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 05:58:48.634053 ==
1562 05:58:48.637086 DQS Delay:
1563 05:58:48.637454 DQS0 = 0, DQS1 = 0
1564 05:58:48.637854 DQM Delay:
1565 05:58:48.640831 DQM0 = 92, DQM1 = 87
1566 05:58:48.641232 DQ Delay:
1567 05:58:48.643677 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1568 05:58:48.647476 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1569 05:58:48.651049 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1570 05:58:48.654236 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1571 05:58:48.654612
1572 05:58:48.654927
1573 05:58:48.655207 ==
1574 05:58:48.657309 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 05:58:48.663941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 05:58:48.664368 ==
1577 05:58:48.664687
1578 05:58:48.665161
1579 05:58:48.665439 TX Vref Scan disable
1580 05:58:48.667492 == TX Byte 0 ==
1581 05:58:48.670254 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1582 05:58:48.677080 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1583 05:58:48.677571 == TX Byte 1 ==
1584 05:58:48.680683 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1585 05:58:48.684349 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1586 05:58:48.687084 ==
1587 05:58:48.690560 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 05:58:48.694193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 05:58:48.694695 ==
1590 05:58:48.706526 TX Vref=22, minBit 0, minWin=27, winSum=436
1591 05:58:48.709765 TX Vref=24, minBit 0, minWin=27, winSum=440
1592 05:58:48.713241 TX Vref=26, minBit 3, minWin=27, winSum=444
1593 05:58:48.716579 TX Vref=28, minBit 0, minWin=27, winSum=449
1594 05:58:48.719825 TX Vref=30, minBit 0, minWin=27, winSum=451
1595 05:58:48.723475 TX Vref=32, minBit 1, minWin=27, winSum=445
1596 05:58:48.730155 [TxChooseVref] Worse bit 0, Min win 27, Win sum 451, Final Vref 30
1597 05:58:48.730657
1598 05:58:48.733523 Final TX Range 1 Vref 30
1599 05:58:48.733921
1600 05:58:48.734223 ==
1601 05:58:48.736414 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 05:58:48.739975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 05:58:48.740408 ==
1604 05:58:48.740719
1605 05:58:48.740997
1606 05:58:48.743466 TX Vref Scan disable
1607 05:58:48.746993 == TX Byte 0 ==
1608 05:58:48.749898 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1609 05:58:48.753371 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1610 05:58:48.757054 == TX Byte 1 ==
1611 05:58:48.759861 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1612 05:58:48.763353 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1613 05:58:48.764331
1614 05:58:48.766720 [DATLAT]
1615 05:58:48.767382 Freq=800, CH1 RK0
1616 05:58:48.767855
1617 05:58:48.769964 DATLAT Default: 0xa
1618 05:58:48.770389 0, 0xFFFF, sum = 0
1619 05:58:48.773350 1, 0xFFFF, sum = 0
1620 05:58:48.773737 2, 0xFFFF, sum = 0
1621 05:58:48.776926 3, 0xFFFF, sum = 0
1622 05:58:48.777632 4, 0xFFFF, sum = 0
1623 05:58:48.780362 5, 0xFFFF, sum = 0
1624 05:58:48.780753 6, 0xFFFF, sum = 0
1625 05:58:48.783127 7, 0xFFFF, sum = 0
1626 05:58:48.783514 8, 0xFFFF, sum = 0
1627 05:58:48.786921 9, 0x0, sum = 1
1628 05:58:48.787306 10, 0x0, sum = 2
1629 05:58:48.790526 11, 0x0, sum = 3
1630 05:58:48.790974 12, 0x0, sum = 4
1631 05:58:48.793290 best_step = 10
1632 05:58:48.793672
1633 05:58:48.793971 ==
1634 05:58:48.796760 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 05:58:48.800254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 05:58:48.800801 ==
1637 05:58:48.801254 RX Vref Scan: 1
1638 05:58:48.801668
1639 05:58:48.803550 Set Vref Range= 32 -> 127
1640 05:58:48.803993
1641 05:58:48.807204 RX Vref 32 -> 127, step: 1
1642 05:58:48.807582
1643 05:58:48.810738 RX Delay -79 -> 252, step: 8
1644 05:58:48.811118
1645 05:58:48.813580 Set Vref, RX VrefLevel [Byte0]: 32
1646 05:58:48.817020 [Byte1]: 32
1647 05:58:48.817403
1648 05:58:48.820458 Set Vref, RX VrefLevel [Byte0]: 33
1649 05:58:48.823912 [Byte1]: 33
1650 05:58:48.824335
1651 05:58:48.827208 Set Vref, RX VrefLevel [Byte0]: 34
1652 05:58:48.830293 [Byte1]: 34
1653 05:58:48.833851
1654 05:58:48.834330 Set Vref, RX VrefLevel [Byte0]: 35
1655 05:58:48.837204 [Byte1]: 35
1656 05:58:48.841403
1657 05:58:48.841824 Set Vref, RX VrefLevel [Byte0]: 36
1658 05:58:48.845136 [Byte1]: 36
1659 05:58:48.848501
1660 05:58:48.849007 Set Vref, RX VrefLevel [Byte0]: 37
1661 05:58:48.852580 [Byte1]: 37
1662 05:58:48.856312
1663 05:58:48.856870 Set Vref, RX VrefLevel [Byte0]: 38
1664 05:58:48.859938 [Byte1]: 38
1665 05:58:48.864394
1666 05:58:48.864776 Set Vref, RX VrefLevel [Byte0]: 39
1667 05:58:48.867582 [Byte1]: 39
1668 05:58:48.871952
1669 05:58:48.872385 Set Vref, RX VrefLevel [Byte0]: 40
1670 05:58:48.874736 [Byte1]: 40
1671 05:58:48.878973
1672 05:58:48.879380 Set Vref, RX VrefLevel [Byte0]: 41
1673 05:58:48.882293 [Byte1]: 41
1674 05:58:48.886813
1675 05:58:48.887323 Set Vref, RX VrefLevel [Byte0]: 42
1676 05:58:48.890197 [Byte1]: 42
1677 05:58:48.893978
1678 05:58:48.894347 Set Vref, RX VrefLevel [Byte0]: 43
1679 05:58:48.897685 [Byte1]: 43
1680 05:58:48.901849
1681 05:58:48.902236 Set Vref, RX VrefLevel [Byte0]: 44
1682 05:58:48.905299 [Byte1]: 44
1683 05:58:48.909424
1684 05:58:48.909795 Set Vref, RX VrefLevel [Byte0]: 45
1685 05:58:48.912870 [Byte1]: 45
1686 05:58:48.916974
1687 05:58:48.917340 Set Vref, RX VrefLevel [Byte0]: 46
1688 05:58:48.919933 [Byte1]: 46
1689 05:58:48.924019
1690 05:58:48.924426 Set Vref, RX VrefLevel [Byte0]: 47
1691 05:58:48.927421 [Byte1]: 47
1692 05:58:48.931892
1693 05:58:48.932261 Set Vref, RX VrefLevel [Byte0]: 48
1694 05:58:48.935286 [Byte1]: 48
1695 05:58:48.939237
1696 05:58:48.939659 Set Vref, RX VrefLevel [Byte0]: 49
1697 05:58:48.942477 [Byte1]: 49
1698 05:58:48.947323
1699 05:58:48.947730 Set Vref, RX VrefLevel [Byte0]: 50
1700 05:58:48.950655 [Byte1]: 50
1701 05:58:48.954504
1702 05:58:48.954910 Set Vref, RX VrefLevel [Byte0]: 51
1703 05:58:48.958080 [Byte1]: 51
1704 05:58:48.962050
1705 05:58:48.962589 Set Vref, RX VrefLevel [Byte0]: 52
1706 05:58:48.965180 [Byte1]: 52
1707 05:58:48.970116
1708 05:58:48.970556 Set Vref, RX VrefLevel [Byte0]: 53
1709 05:58:48.972965 [Byte1]: 53
1710 05:58:48.977461
1711 05:58:48.977865 Set Vref, RX VrefLevel [Byte0]: 54
1712 05:58:48.980270 [Byte1]: 54
1713 05:58:48.984558
1714 05:58:48.984977 Set Vref, RX VrefLevel [Byte0]: 55
1715 05:58:48.987985 [Byte1]: 55
1716 05:58:48.992222
1717 05:58:48.992794 Set Vref, RX VrefLevel [Byte0]: 56
1718 05:58:48.995520 [Byte1]: 56
1719 05:58:48.999930
1720 05:58:49.000223 Set Vref, RX VrefLevel [Byte0]: 57
1721 05:58:49.003382 [Byte1]: 57
1722 05:58:49.007313
1723 05:58:49.007502 Set Vref, RX VrefLevel [Byte0]: 58
1724 05:58:49.010548 [Byte1]: 58
1725 05:58:49.014821
1726 05:58:49.014979 Set Vref, RX VrefLevel [Byte0]: 59
1727 05:58:49.018226 [Byte1]: 59
1728 05:58:49.022356
1729 05:58:49.022467 Set Vref, RX VrefLevel [Byte0]: 60
1730 05:58:49.025328 [Byte1]: 60
1731 05:58:49.029629
1732 05:58:49.029727 Set Vref, RX VrefLevel [Byte0]: 61
1733 05:58:49.032919 [Byte1]: 61
1734 05:58:49.037376
1735 05:58:49.037456 Set Vref, RX VrefLevel [Byte0]: 62
1736 05:58:49.043870 [Byte1]: 62
1737 05:58:49.043975
1738 05:58:49.046752 Set Vref, RX VrefLevel [Byte0]: 63
1739 05:58:49.050284 [Byte1]: 63
1740 05:58:49.050374
1741 05:58:49.053569 Set Vref, RX VrefLevel [Byte0]: 64
1742 05:58:49.056931 [Byte1]: 64
1743 05:58:49.057020
1744 05:58:49.060548 Set Vref, RX VrefLevel [Byte0]: 65
1745 05:58:49.063405 [Byte1]: 65
1746 05:58:49.067175
1747 05:58:49.067295 Set Vref, RX VrefLevel [Byte0]: 66
1748 05:58:49.070360 [Byte1]: 66
1749 05:58:49.075179
1750 05:58:49.075285 Set Vref, RX VrefLevel [Byte0]: 67
1751 05:58:49.078711 [Byte1]: 67
1752 05:58:49.082410
1753 05:58:49.082489 Set Vref, RX VrefLevel [Byte0]: 68
1754 05:58:49.086066 [Byte1]: 68
1755 05:58:49.090379
1756 05:58:49.090459 Set Vref, RX VrefLevel [Byte0]: 69
1757 05:58:49.093063 [Byte1]: 69
1758 05:58:49.097452
1759 05:58:49.097566 Set Vref, RX VrefLevel [Byte0]: 70
1760 05:58:49.100809 [Byte1]: 70
1761 05:58:49.105672
1762 05:58:49.105752 Set Vref, RX VrefLevel [Byte0]: 71
1763 05:58:49.108163 [Byte1]: 71
1764 05:58:49.112888
1765 05:58:49.112968 Set Vref, RX VrefLevel [Byte0]: 72
1766 05:58:49.115978 [Byte1]: 72
1767 05:58:49.119946
1768 05:58:49.120026 Set Vref, RX VrefLevel [Byte0]: 73
1769 05:58:49.123315 [Byte1]: 73
1770 05:58:49.128002
1771 05:58:49.128086 Set Vref, RX VrefLevel [Byte0]: 74
1772 05:58:49.131022 [Byte1]: 74
1773 05:58:49.135519
1774 05:58:49.135699 Final RX Vref Byte 0 = 58 to rank0
1775 05:58:49.138887 Final RX Vref Byte 1 = 55 to rank0
1776 05:58:49.142115 Final RX Vref Byte 0 = 58 to rank1
1777 05:58:49.145281 Final RX Vref Byte 1 = 55 to rank1==
1778 05:58:49.148928 Dram Type= 6, Freq= 0, CH_1, rank 0
1779 05:58:49.152626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1780 05:58:49.155524 ==
1781 05:58:49.155662 DQS Delay:
1782 05:58:49.155825 DQS0 = 0, DQS1 = 0
1783 05:58:49.159094 DQM Delay:
1784 05:58:49.159340 DQM0 = 94, DQM1 = 89
1785 05:58:49.162643 DQ Delay:
1786 05:58:49.162822 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1787 05:58:49.165226 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1788 05:58:49.169045 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1789 05:58:49.171942 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1790 05:58:49.175637
1791 05:58:49.175723
1792 05:58:49.182260 [DQSOSCAuto] RK0, (LSB)MR18= 0x2844, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1793 05:58:49.185533 CH1 RK0: MR19=606, MR18=2844
1794 05:58:49.192258 CH1_RK0: MR19=0x606, MR18=0x2844, DQSOSC=392, MR23=63, INC=96, DEC=64
1795 05:58:49.192386
1796 05:58:49.195301 ----->DramcWriteLeveling(PI) begin...
1797 05:58:49.195440 ==
1798 05:58:49.198943 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 05:58:49.202245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 05:58:49.202422 ==
1801 05:58:49.205982 Write leveling (Byte 0): 28 => 28
1802 05:58:49.208929 Write leveling (Byte 1): 29 => 29
1803 05:58:49.212424 DramcWriteLeveling(PI) end<-----
1804 05:58:49.212586
1805 05:58:49.212734 ==
1806 05:58:49.215904 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 05:58:49.219365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 05:58:49.219533 ==
1809 05:58:49.223013 [Gating] SW mode calibration
1810 05:58:49.229243 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1811 05:58:49.235592 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1812 05:58:49.238954 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1813 05:58:49.242284 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1814 05:58:49.249190 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 05:58:49.252474 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 05:58:49.255928 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 05:58:49.259584 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 05:58:49.266250 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 05:58:49.269355 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 05:58:49.272801 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 05:58:49.278936 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 05:58:49.282770 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 05:58:49.286162 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 05:58:49.292471 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 05:58:49.295487 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 05:58:49.298885 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 05:58:49.306280 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 05:58:49.309135 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1829 05:58:49.312756 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1830 05:58:49.319503 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 05:58:49.323060 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 05:58:49.325898 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 05:58:49.332438 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 05:58:49.335911 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 05:58:49.339598 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 05:58:49.342561 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 05:58:49.349109 0 9 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1838 05:58:49.352578 0 9 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 0)
1839 05:58:49.355968 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 05:58:49.362767 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 05:58:49.366274 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 05:58:49.369753 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 05:58:49.376186 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 05:58:49.379393 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1845 05:58:49.382998 0 10 4 | B1->B0 | 2a2a 2f2f | 0 1 | (0 0) (1 0)
1846 05:58:49.389512 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 05:58:49.392868 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 05:58:49.395900 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 05:58:49.402754 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 05:58:49.406361 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 05:58:49.409304 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 05:58:49.416043 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1853 05:58:49.419580 0 11 4 | B1->B0 | 3737 2d2d | 0 0 | (1 1) (0 0)
1854 05:58:49.422538 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1855 05:58:49.429389 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 05:58:49.432341 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 05:58:49.436126 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 05:58:49.439739 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 05:58:49.446434 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 05:58:49.449288 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1861 05:58:49.453076 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1862 05:58:49.459566 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 05:58:49.463130 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 05:58:49.465809 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 05:58:49.472731 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 05:58:49.476278 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 05:58:49.479669 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 05:58:49.486361 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 05:58:49.489763 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 05:58:49.493202 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 05:58:49.496820 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 05:58:49.503207 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 05:58:49.506642 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 05:58:49.509931 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 05:58:49.516280 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 05:58:49.519715 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1877 05:58:49.523373 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1878 05:58:49.530167 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 05:58:49.533315 Total UI for P1: 0, mck2ui 16
1880 05:58:49.536864 best dqsien dly found for B0: ( 0, 14, 2)
1881 05:58:49.537157 Total UI for P1: 0, mck2ui 16
1882 05:58:49.543431 best dqsien dly found for B1: ( 0, 14, 2)
1883 05:58:49.547090 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1884 05:58:49.550112 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1885 05:58:49.550517
1886 05:58:49.553541 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1887 05:58:49.556688 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1888 05:58:49.560496 [Gating] SW calibration Done
1889 05:58:49.560916 ==
1890 05:58:49.563411 Dram Type= 6, Freq= 0, CH_1, rank 1
1891 05:58:49.567018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1892 05:58:49.567581 ==
1893 05:58:49.570068 RX Vref Scan: 0
1894 05:58:49.570479
1895 05:58:49.570803 RX Vref 0 -> 0, step: 1
1896 05:58:49.571107
1897 05:58:49.573765 RX Delay -130 -> 252, step: 16
1898 05:58:49.577073 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1899 05:58:49.583827 iDelay=222, Bit 1, Center 93 (-2 ~ 189) 192
1900 05:58:49.586782 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1901 05:58:49.589681 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1902 05:58:49.593206 iDelay=222, Bit 4, Center 93 (-2 ~ 189) 192
1903 05:58:49.596676 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1904 05:58:49.600150 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1905 05:58:49.606524 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1906 05:58:49.610067 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1907 05:58:49.613868 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1908 05:58:49.617335 iDelay=222, Bit 10, Center 101 (-2 ~ 205) 208
1909 05:58:49.620266 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1910 05:58:49.626830 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1911 05:58:49.630309 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1912 05:58:49.633711 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1913 05:58:49.637225 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1914 05:58:49.637639 ==
1915 05:58:49.640219 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 05:58:49.646732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 05:58:49.647229 ==
1918 05:58:49.647559 DQS Delay:
1919 05:58:49.650774 DQS0 = 0, DQS1 = 0
1920 05:58:49.651322 DQM Delay:
1921 05:58:49.651739 DQM0 = 96, DQM1 = 92
1922 05:58:49.653231 DQ Delay:
1923 05:58:49.657140 DQ0 =101, DQ1 =93, DQ2 =77, DQ3 =93
1924 05:58:49.660158 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =101
1925 05:58:49.663798 DQ8 =77, DQ9 =77, DQ10 =101, DQ11 =77
1926 05:58:49.667396 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1927 05:58:49.667960
1928 05:58:49.668444
1929 05:58:49.668854 ==
1930 05:58:49.670375 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 05:58:49.674050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 05:58:49.674472 ==
1933 05:58:49.674799
1934 05:58:49.675102
1935 05:58:49.677098 TX Vref Scan disable
1936 05:58:49.680649 == TX Byte 0 ==
1937 05:58:49.684024 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1938 05:58:49.687239 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1939 05:58:49.690102 == TX Byte 1 ==
1940 05:58:49.693751 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1941 05:58:49.696816 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1942 05:58:49.697231 ==
1943 05:58:49.700556 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 05:58:49.703570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 05:58:49.707167 ==
1946 05:58:49.718757 TX Vref=22, minBit 5, minWin=26, winSum=442
1947 05:58:49.721701 TX Vref=24, minBit 1, minWin=26, winSum=446
1948 05:58:49.724570 TX Vref=26, minBit 1, minWin=27, winSum=449
1949 05:58:49.728358 TX Vref=28, minBit 1, minWin=27, winSum=451
1950 05:58:49.731273 TX Vref=30, minBit 2, minWin=27, winSum=451
1951 05:58:49.734928 TX Vref=32, minBit 2, minWin=27, winSum=449
1952 05:58:49.741608 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 28
1953 05:58:49.742024
1954 05:58:49.745212 Final TX Range 1 Vref 28
1955 05:58:49.745629
1956 05:58:49.745976 ==
1957 05:58:49.748019 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 05:58:49.751799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 05:58:49.752391 ==
1960 05:58:49.752736
1961 05:58:49.753043
1962 05:58:49.755119 TX Vref Scan disable
1963 05:58:49.758606 == TX Byte 0 ==
1964 05:58:49.761888 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1965 05:58:49.765199 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1966 05:58:49.768218 == TX Byte 1 ==
1967 05:58:49.771392 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1968 05:58:49.774897 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1969 05:58:49.775401
1970 05:58:49.778786 [DATLAT]
1971 05:58:49.779317 Freq=800, CH1 RK1
1972 05:58:49.779660
1973 05:58:49.781345 DATLAT Default: 0xa
1974 05:58:49.781761 0, 0xFFFF, sum = 0
1975 05:58:49.784863 1, 0xFFFF, sum = 0
1976 05:58:49.785331 2, 0xFFFF, sum = 0
1977 05:58:49.788560 3, 0xFFFF, sum = 0
1978 05:58:49.788993 4, 0xFFFF, sum = 0
1979 05:58:49.791389 5, 0xFFFF, sum = 0
1980 05:58:49.791900 6, 0xFFFF, sum = 0
1981 05:58:49.794874 7, 0xFFFF, sum = 0
1982 05:58:49.795316 8, 0xFFFF, sum = 0
1983 05:58:49.798320 9, 0x0, sum = 1
1984 05:58:49.798894 10, 0x0, sum = 2
1985 05:58:49.801907 11, 0x0, sum = 3
1986 05:58:49.802637 12, 0x0, sum = 4
1987 05:58:49.804824 best_step = 10
1988 05:58:49.805331
1989 05:58:49.805786 ==
1990 05:58:49.808683 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 05:58:49.811521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 05:58:49.811938 ==
1993 05:58:49.815089 RX Vref Scan: 0
1994 05:58:49.815500
1995 05:58:49.815825 RX Vref 0 -> 0, step: 1
1996 05:58:49.816132
1997 05:58:49.818338 RX Delay -79 -> 252, step: 8
1998 05:58:49.825094 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1999 05:58:49.828653 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2000 05:58:49.831796 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2001 05:58:49.834875 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2002 05:58:49.838523 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2003 05:58:49.841871 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2004 05:58:49.848173 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2005 05:58:49.851314 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2006 05:58:49.854777 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2007 05:58:49.858205 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2008 05:58:49.862003 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2009 05:58:49.868640 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2010 05:58:49.871643 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2011 05:58:49.875023 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2012 05:58:49.878515 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2013 05:58:49.881929 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2014 05:58:49.882344 ==
2015 05:58:49.885061 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 05:58:49.891580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 05:58:49.892082 ==
2018 05:58:49.892470 DQS Delay:
2019 05:58:49.894934 DQS0 = 0, DQS1 = 0
2020 05:58:49.895346 DQM Delay:
2021 05:58:49.895671 DQM0 = 97, DQM1 = 91
2022 05:58:49.898589 DQ Delay:
2023 05:58:49.902203 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2024 05:58:49.905541 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2025 05:58:49.908385 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2026 05:58:49.912113 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2027 05:58:49.912624
2028 05:58:49.912955
2029 05:58:49.918734 [DQSOSCAuto] RK1, (LSB)MR18= 0x420c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
2030 05:58:49.921516 CH1 RK1: MR19=606, MR18=420C
2031 05:58:49.928604 CH1_RK1: MR19=0x606, MR18=0x420C, DQSOSC=393, MR23=63, INC=95, DEC=63
2032 05:58:49.931532 [RxdqsGatingPostProcess] freq 800
2033 05:58:49.935294 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2034 05:58:49.938061 Pre-setting of DQS Precalculation
2035 05:58:49.944822 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2036 05:58:49.952135 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2037 05:58:49.958792 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2038 05:58:49.959214
2039 05:58:49.959634
2040 05:58:49.961680 [Calibration Summary] 1600 Mbps
2041 05:58:49.962102 CH 0, Rank 0
2042 05:58:49.965000 SW Impedance : PASS
2043 05:58:49.968342 DUTY Scan : NO K
2044 05:58:49.968770 ZQ Calibration : PASS
2045 05:58:49.972079 Jitter Meter : NO K
2046 05:58:49.975007 CBT Training : PASS
2047 05:58:49.975428 Write leveling : PASS
2048 05:58:49.978720 RX DQS gating : PASS
2049 05:58:49.981616 RX DQ/DQS(RDDQC) : PASS
2050 05:58:49.982040 TX DQ/DQS : PASS
2051 05:58:49.985141 RX DATLAT : PASS
2052 05:58:49.985562 RX DQ/DQS(Engine): PASS
2053 05:58:49.988250 TX OE : NO K
2054 05:58:49.988730 All Pass.
2055 05:58:49.989159
2056 05:58:49.991652 CH 0, Rank 1
2057 05:58:49.992206 SW Impedance : PASS
2058 05:58:49.995277 DUTY Scan : NO K
2059 05:58:49.998465 ZQ Calibration : PASS
2060 05:58:49.999021 Jitter Meter : NO K
2061 05:58:50.002148 CBT Training : PASS
2062 05:58:50.005425 Write leveling : PASS
2063 05:58:50.005852 RX DQS gating : PASS
2064 05:58:50.008701 RX DQ/DQS(RDDQC) : PASS
2065 05:58:50.011955 TX DQ/DQS : PASS
2066 05:58:50.012412 RX DATLAT : PASS
2067 05:58:50.015151 RX DQ/DQS(Engine): PASS
2068 05:58:50.018522 TX OE : NO K
2069 05:58:50.018949 All Pass.
2070 05:58:50.019285
2071 05:58:50.019585 CH 1, Rank 0
2072 05:58:50.022219 SW Impedance : PASS
2073 05:58:50.024902 DUTY Scan : NO K
2074 05:58:50.025304 ZQ Calibration : PASS
2075 05:58:50.028665 Jitter Meter : NO K
2076 05:58:50.032057 CBT Training : PASS
2077 05:58:50.032505 Write leveling : PASS
2078 05:58:50.035723 RX DQS gating : PASS
2079 05:58:50.036245 RX DQ/DQS(RDDQC) : PASS
2080 05:58:50.038320 TX DQ/DQS : PASS
2081 05:58:50.042023 RX DATLAT : PASS
2082 05:58:50.042438 RX DQ/DQS(Engine): PASS
2083 05:58:50.045430 TX OE : NO K
2084 05:58:50.046002 All Pass.
2085 05:58:50.046470
2086 05:58:50.048843 CH 1, Rank 1
2087 05:58:50.049357 SW Impedance : PASS
2088 05:58:50.051717 DUTY Scan : NO K
2089 05:58:50.055311 ZQ Calibration : PASS
2090 05:58:50.055752 Jitter Meter : NO K
2091 05:58:50.058897 CBT Training : PASS
2092 05:58:50.061896 Write leveling : PASS
2093 05:58:50.062339 RX DQS gating : PASS
2094 05:58:50.065451 RX DQ/DQS(RDDQC) : PASS
2095 05:58:50.069057 TX DQ/DQS : PASS
2096 05:58:50.069693 RX DATLAT : PASS
2097 05:58:50.071692 RX DQ/DQS(Engine): PASS
2098 05:58:50.072187 TX OE : NO K
2099 05:58:50.075289 All Pass.
2100 05:58:50.075733
2101 05:58:50.076069 DramC Write-DBI off
2102 05:58:50.078349 PER_BANK_REFRESH: Hybrid Mode
2103 05:58:50.081644 TX_TRACKING: ON
2104 05:58:50.085502 [GetDramInforAfterCalByMRR] Vendor 6.
2105 05:58:50.088453 [GetDramInforAfterCalByMRR] Revision 606.
2106 05:58:50.091933 [GetDramInforAfterCalByMRR] Revision 2 0.
2107 05:58:50.092256 MR0 0x3b3b
2108 05:58:50.092528 MR8 0x5151
2109 05:58:50.098693 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 05:58:50.098927
2111 05:58:50.099100 MR0 0x3b3b
2112 05:58:50.099273 MR8 0x5151
2113 05:58:50.102094 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 05:58:50.102270
2115 05:58:50.111747 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2116 05:58:50.115217 [FAST_K] Save calibration result to emmc
2117 05:58:50.118665 [FAST_K] Save calibration result to emmc
2118 05:58:50.122068 dram_init: config_dvfs: 1
2119 05:58:50.124830 dramc_set_vcore_voltage set vcore to 662500
2120 05:58:50.128080 Read voltage for 1200, 2
2121 05:58:50.128169 Vio18 = 0
2122 05:58:50.128241 Vcore = 662500
2123 05:58:50.132018 Vdram = 0
2124 05:58:50.132101 Vddq = 0
2125 05:58:50.132165 Vmddr = 0
2126 05:58:50.138416 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2127 05:58:50.141319 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2128 05:58:50.144838 MEM_TYPE=3, freq_sel=15
2129 05:58:50.148219 sv_algorithm_assistance_LP4_1600
2130 05:58:50.151880 ============ PULL DRAM RESETB DOWN ============
2131 05:58:50.155414 ========== PULL DRAM RESETB DOWN end =========
2132 05:58:50.162324 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2133 05:58:50.165677 ===================================
2134 05:58:50.165761 LPDDR4 DRAM CONFIGURATION
2135 05:58:50.168294 ===================================
2136 05:58:50.172039 EX_ROW_EN[0] = 0x0
2137 05:58:50.175438 EX_ROW_EN[1] = 0x0
2138 05:58:50.175519 LP4Y_EN = 0x0
2139 05:58:50.178989 WORK_FSP = 0x0
2140 05:58:50.179071 WL = 0x4
2141 05:58:50.182489 RL = 0x4
2142 05:58:50.182570 BL = 0x2
2143 05:58:50.185314 RPST = 0x0
2144 05:58:50.185394 RD_PRE = 0x0
2145 05:58:50.188816 WR_PRE = 0x1
2146 05:58:50.188938 WR_PST = 0x0
2147 05:58:50.192186 DBI_WR = 0x0
2148 05:58:50.192268 DBI_RD = 0x0
2149 05:58:50.195367 OTF = 0x1
2150 05:58:50.199058 ===================================
2151 05:58:50.202030 ===================================
2152 05:58:50.202123 ANA top config
2153 05:58:50.205043 ===================================
2154 05:58:50.208628 DLL_ASYNC_EN = 0
2155 05:58:50.212157 ALL_SLAVE_EN = 0
2156 05:58:50.212240 NEW_RANK_MODE = 1
2157 05:58:50.215618 DLL_IDLE_MODE = 1
2158 05:58:50.218489 LP45_APHY_COMB_EN = 1
2159 05:58:50.222084 TX_ODT_DIS = 1
2160 05:58:50.225483 NEW_8X_MODE = 1
2161 05:58:50.228400 ===================================
2162 05:58:50.231918 ===================================
2163 05:58:50.231999 data_rate = 2400
2164 05:58:50.235751 CKR = 1
2165 05:58:50.239067 DQ_P2S_RATIO = 8
2166 05:58:50.242143 ===================================
2167 05:58:50.245336 CA_P2S_RATIO = 8
2168 05:58:50.248506 DQ_CA_OPEN = 0
2169 05:58:50.252562 DQ_SEMI_OPEN = 0
2170 05:58:50.252645 CA_SEMI_OPEN = 0
2171 05:58:50.255381 CA_FULL_RATE = 0
2172 05:58:50.258689 DQ_CKDIV4_EN = 0
2173 05:58:50.262462 CA_CKDIV4_EN = 0
2174 05:58:50.265437 CA_PREDIV_EN = 0
2175 05:58:50.268976 PH8_DLY = 17
2176 05:58:50.269057 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2177 05:58:50.272533 DQ_AAMCK_DIV = 4
2178 05:58:50.275310 CA_AAMCK_DIV = 4
2179 05:58:50.278720 CA_ADMCK_DIV = 4
2180 05:58:50.282017 DQ_TRACK_CA_EN = 0
2181 05:58:50.286013 CA_PICK = 1200
2182 05:58:50.286123 CA_MCKIO = 1200
2183 05:58:50.288916 MCKIO_SEMI = 0
2184 05:58:50.292568 PLL_FREQ = 2366
2185 05:58:50.304207 DQ_UI_PI_RATIO = 32
2186 05:58:50.304386 CA_UI_PI_RATIO = 0
2187 05:58:50.304453 ===================================
2188 05:58:50.305643 ===================================
2189 05:58:50.308736 memory_type:LPDDR4
2190 05:58:50.308818 GP_NUM : 10
2191 05:58:50.312531 SRAM_EN : 1
2192 05:58:50.312614 MD32_EN : 0
2193 05:58:50.315614 ===================================
2194 05:58:50.319025 [ANA_INIT] >>>>>>>>>>>>>>
2195 05:58:50.322387 <<<<<< [CONFIGURE PHASE]: ANA_TX
2196 05:58:50.326011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2197 05:58:50.328979 ===================================
2198 05:58:50.332559 data_rate = 2400,PCW = 0X5b00
2199 05:58:50.336112 ===================================
2200 05:58:50.339697 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2201 05:58:50.342562 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 05:58:50.349510 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 05:58:50.353181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2204 05:58:50.356431 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2205 05:58:50.359143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2206 05:58:50.362555 [ANA_INIT] flow start
2207 05:58:50.366245 [ANA_INIT] PLL >>>>>>>>
2208 05:58:50.366327 [ANA_INIT] PLL <<<<<<<<
2209 05:58:50.369213 [ANA_INIT] MIDPI >>>>>>>>
2210 05:58:50.372635 [ANA_INIT] MIDPI <<<<<<<<
2211 05:58:50.372742 [ANA_INIT] DLL >>>>>>>>
2212 05:58:50.375654 [ANA_INIT] DLL <<<<<<<<
2213 05:58:50.379282 [ANA_INIT] flow end
2214 05:58:50.382232 ============ LP4 DIFF to SE enter ============
2215 05:58:50.385683 ============ LP4 DIFF to SE exit ============
2216 05:58:50.389291 [ANA_INIT] <<<<<<<<<<<<<
2217 05:58:50.392808 [Flow] Enable top DCM control >>>>>
2218 05:58:50.396195 [Flow] Enable top DCM control <<<<<
2219 05:58:50.398962 Enable DLL master slave shuffle
2220 05:58:50.402960 ==============================================================
2221 05:58:50.405879 Gating Mode config
2222 05:58:50.413028 ==============================================================
2223 05:58:50.413129 Config description:
2224 05:58:50.422636 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2225 05:58:50.429467 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2226 05:58:50.432833 SELPH_MODE 0: By rank 1: By Phase
2227 05:58:50.439478 ==============================================================
2228 05:58:50.442496 GAT_TRACK_EN = 1
2229 05:58:50.446140 RX_GATING_MODE = 2
2230 05:58:50.449565 RX_GATING_TRACK_MODE = 2
2231 05:58:50.452330 SELPH_MODE = 1
2232 05:58:50.455753 PICG_EARLY_EN = 1
2233 05:58:50.459261 VALID_LAT_VALUE = 1
2234 05:58:50.462662 ==============================================================
2235 05:58:50.465894 Enter into Gating configuration >>>>
2236 05:58:50.469312 Exit from Gating configuration <<<<
2237 05:58:50.472915 Enter into DVFS_PRE_config >>>>>
2238 05:58:50.482955 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2239 05:58:50.485969 Exit from DVFS_PRE_config <<<<<
2240 05:58:50.489308 Enter into PICG configuration >>>>
2241 05:58:50.492860 Exit from PICG configuration <<<<
2242 05:58:50.496484 [RX_INPUT] configuration >>>>>
2243 05:58:50.499314 [RX_INPUT] configuration <<<<<
2244 05:58:50.502958 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2245 05:58:50.509711 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2246 05:58:50.516613 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 05:58:50.523181 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 05:58:50.529503 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 05:58:50.533034 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 05:58:50.539420 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2251 05:58:50.542913 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2252 05:58:50.546369 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2253 05:58:50.549528 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2254 05:58:50.556233 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2255 05:58:50.559874 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2256 05:58:50.562914 ===================================
2257 05:58:50.566353 LPDDR4 DRAM CONFIGURATION
2258 05:58:50.570003 ===================================
2259 05:58:50.570086 EX_ROW_EN[0] = 0x0
2260 05:58:50.573395 EX_ROW_EN[1] = 0x0
2261 05:58:50.573476 LP4Y_EN = 0x0
2262 05:58:50.576231 WORK_FSP = 0x0
2263 05:58:50.576351 WL = 0x4
2264 05:58:50.580168 RL = 0x4
2265 05:58:50.580249 BL = 0x2
2266 05:58:50.583471 RPST = 0x0
2267 05:58:50.583799 RD_PRE = 0x0
2268 05:58:50.586584 WR_PRE = 0x1
2269 05:58:50.586835 WR_PST = 0x0
2270 05:58:50.590135 DBI_WR = 0x0
2271 05:58:50.590375 DBI_RD = 0x0
2272 05:58:50.593051 OTF = 0x1
2273 05:58:50.596644 ===================================
2274 05:58:50.600035 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2275 05:58:50.603646 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2276 05:58:50.610032 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2277 05:58:50.613529 ===================================
2278 05:58:50.613768 LPDDR4 DRAM CONFIGURATION
2279 05:58:50.617017 ===================================
2280 05:58:50.620313 EX_ROW_EN[0] = 0x10
2281 05:58:50.623966 EX_ROW_EN[1] = 0x0
2282 05:58:50.624264 LP4Y_EN = 0x0
2283 05:58:50.626909 WORK_FSP = 0x0
2284 05:58:50.627292 WL = 0x4
2285 05:58:50.630584 RL = 0x4
2286 05:58:50.630963 BL = 0x2
2287 05:58:50.633527 RPST = 0x0
2288 05:58:50.633941 RD_PRE = 0x0
2289 05:58:50.637188 WR_PRE = 0x1
2290 05:58:50.637601 WR_PST = 0x0
2291 05:58:50.640801 DBI_WR = 0x0
2292 05:58:50.641300 DBI_RD = 0x0
2293 05:58:50.643496 OTF = 0x1
2294 05:58:50.647155 ===================================
2295 05:58:50.653559 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2296 05:58:50.653974 ==
2297 05:58:50.657002 Dram Type= 6, Freq= 0, CH_0, rank 0
2298 05:58:50.660561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2299 05:58:50.661021 ==
2300 05:58:50.663249 [Duty_Offset_Calibration]
2301 05:58:50.663659 B0:2 B1:1 CA:1
2302 05:58:50.664126
2303 05:58:50.666850 [DutyScan_Calibration_Flow] k_type=0
2304 05:58:50.676699
2305 05:58:50.677105 ==CLK 0==
2306 05:58:50.680235 Final CLK duty delay cell = 0
2307 05:58:50.683752 [0] MAX Duty = 5187%(X100), DQS PI = 24
2308 05:58:50.686999 [0] MIN Duty = 4844%(X100), DQS PI = 48
2309 05:58:50.687410 [0] AVG Duty = 5015%(X100)
2310 05:58:50.690347
2311 05:58:50.693331 CH0 CLK Duty spec in!! Max-Min= 343%
2312 05:58:50.697018 [DutyScan_Calibration_Flow] ====Done====
2313 05:58:50.697472
2314 05:58:50.700361 [DutyScan_Calibration_Flow] k_type=1
2315 05:58:50.715273
2316 05:58:50.715633 ==DQS 0 ==
2317 05:58:50.718820 Final DQS duty delay cell = -4
2318 05:58:50.722189 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2319 05:58:50.725246 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2320 05:58:50.729006 [-4] AVG Duty = 4953%(X100)
2321 05:58:50.729326
2322 05:58:50.729563 ==DQS 1 ==
2323 05:58:50.731803 Final DQS duty delay cell = 0
2324 05:58:50.735065 [0] MAX Duty = 5156%(X100), DQS PI = 62
2325 05:58:50.738662 [0] MIN Duty = 5000%(X100), DQS PI = 36
2326 05:58:50.742189 [0] AVG Duty = 5078%(X100)
2327 05:58:50.742350
2328 05:58:50.745647 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2329 05:58:50.745807
2330 05:58:50.748503 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2331 05:58:50.752172 [DutyScan_Calibration_Flow] ====Done====
2332 05:58:50.752345
2333 05:58:50.755020 [DutyScan_Calibration_Flow] k_type=3
2334 05:58:50.772330
2335 05:58:50.772479 ==DQM 0 ==
2336 05:58:50.775800 Final DQM duty delay cell = 0
2337 05:58:50.778627 [0] MAX Duty = 5156%(X100), DQS PI = 30
2338 05:58:50.782229 [0] MIN Duty = 4906%(X100), DQS PI = 58
2339 05:58:50.782311 [0] AVG Duty = 5031%(X100)
2340 05:58:50.785277
2341 05:58:50.785388 ==DQM 1 ==
2342 05:58:50.788743 Final DQM duty delay cell = 0
2343 05:58:50.792869 [0] MAX Duty = 5093%(X100), DQS PI = 0
2344 05:58:50.795276 [0] MIN Duty = 5031%(X100), DQS PI = 18
2345 05:58:50.795369 [0] AVG Duty = 5062%(X100)
2346 05:58:50.798914
2347 05:58:50.802440 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2348 05:58:50.802576
2349 05:58:50.805196 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2350 05:58:50.808778 [DutyScan_Calibration_Flow] ====Done====
2351 05:58:50.808973
2352 05:58:50.811602 [DutyScan_Calibration_Flow] k_type=2
2353 05:58:50.828529
2354 05:58:50.828785 ==DQ 0 ==
2355 05:58:50.831551 Final DQ duty delay cell = 0
2356 05:58:50.835413 [0] MAX Duty = 5031%(X100), DQS PI = 24
2357 05:58:50.838465 [0] MIN Duty = 4906%(X100), DQS PI = 0
2358 05:58:50.838648 [0] AVG Duty = 4968%(X100)
2359 05:58:50.838761
2360 05:58:50.841564 ==DQ 1 ==
2361 05:58:50.845182 Final DQ duty delay cell = 0
2362 05:58:50.848548 [0] MAX Duty = 5093%(X100), DQS PI = 8
2363 05:58:50.851842 [0] MIN Duty = 4938%(X100), DQS PI = 36
2364 05:58:50.852059 [0] AVG Duty = 5015%(X100)
2365 05:58:50.852220
2366 05:58:50.854982 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2367 05:58:50.855153
2368 05:58:50.858507 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2369 05:58:50.865410 [DutyScan_Calibration_Flow] ====Done====
2370 05:58:50.865556 ==
2371 05:58:50.868600 Dram Type= 6, Freq= 0, CH_1, rank 0
2372 05:58:50.871496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2373 05:58:50.871653 ==
2374 05:58:50.875090 [Duty_Offset_Calibration]
2375 05:58:50.875246 B0:1 B1:0 CA:0
2376 05:58:50.875371
2377 05:58:50.878581 [DutyScan_Calibration_Flow] k_type=0
2378 05:58:50.887872
2379 05:58:50.888126 ==CLK 0==
2380 05:58:50.891348 Final CLK duty delay cell = -4
2381 05:58:50.894271 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2382 05:58:50.897981 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2383 05:58:50.901561 [-4] AVG Duty = 4937%(X100)
2384 05:58:50.902010
2385 05:58:50.904397 CH1 CLK Duty spec in!! Max-Min= 125%
2386 05:58:50.907679 [DutyScan_Calibration_Flow] ====Done====
2387 05:58:50.908088
2388 05:58:50.911182 [DutyScan_Calibration_Flow] k_type=1
2389 05:58:50.927587
2390 05:58:50.928123 ==DQS 0 ==
2391 05:58:50.931100 Final DQS duty delay cell = 0
2392 05:58:50.934445 [0] MAX Duty = 5094%(X100), DQS PI = 26
2393 05:58:50.937957 [0] MIN Duty = 4875%(X100), DQS PI = 0
2394 05:58:50.938365 [0] AVG Duty = 4984%(X100)
2395 05:58:50.940871
2396 05:58:50.941282 ==DQS 1 ==
2397 05:58:50.944201 Final DQS duty delay cell = 0
2398 05:58:50.947470 [0] MAX Duty = 5187%(X100), DQS PI = 18
2399 05:58:50.951095 [0] MIN Duty = 4969%(X100), DQS PI = 8
2400 05:58:50.951507 [0] AVG Duty = 5078%(X100)
2401 05:58:50.951831
2402 05:58:50.957576 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2403 05:58:50.958059
2404 05:58:50.961337 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2405 05:58:50.964536 [DutyScan_Calibration_Flow] ====Done====
2406 05:58:50.964943
2407 05:58:50.967624 [DutyScan_Calibration_Flow] k_type=3
2408 05:58:50.984466
2409 05:58:50.984987 ==DQM 0 ==
2410 05:58:50.987165 Final DQM duty delay cell = 0
2411 05:58:50.990994 [0] MAX Duty = 5156%(X100), DQS PI = 6
2412 05:58:50.994018 [0] MIN Duty = 5031%(X100), DQS PI = 0
2413 05:58:50.994426 [0] AVG Duty = 5093%(X100)
2414 05:58:50.997249
2415 05:58:50.997658 ==DQM 1 ==
2416 05:58:51.000844 Final DQM duty delay cell = 0
2417 05:58:51.004343 [0] MAX Duty = 5031%(X100), DQS PI = 26
2418 05:58:51.007619 [0] MIN Duty = 4907%(X100), DQS PI = 36
2419 05:58:51.008132 [0] AVG Duty = 4969%(X100)
2420 05:58:51.008523
2421 05:58:51.014379 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2422 05:58:51.014797
2423 05:58:51.017698 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2424 05:58:51.020790 [DutyScan_Calibration_Flow] ====Done====
2425 05:58:51.021205
2426 05:58:51.023794 [DutyScan_Calibration_Flow] k_type=2
2427 05:58:51.040003
2428 05:58:51.040622 ==DQ 0 ==
2429 05:58:51.042854 Final DQ duty delay cell = -4
2430 05:58:51.046567 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2431 05:58:51.050267 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2432 05:58:51.050781 [-4] AVG Duty = 5000%(X100)
2433 05:58:51.053482
2434 05:58:51.053894 ==DQ 1 ==
2435 05:58:51.056871 Final DQ duty delay cell = 0
2436 05:58:51.059757 [0] MAX Duty = 5125%(X100), DQS PI = 20
2437 05:58:51.063505 [0] MIN Duty = 4969%(X100), DQS PI = 12
2438 05:58:51.064040 [0] AVG Duty = 5047%(X100)
2439 05:58:51.066862
2440 05:58:51.067280 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2441 05:58:51.069644
2442 05:58:51.073236 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2443 05:58:51.077068 [DutyScan_Calibration_Flow] ====Done====
2444 05:58:51.079690 nWR fixed to 30
2445 05:58:51.080111 [ModeRegInit_LP4] CH0 RK0
2446 05:58:51.083066 [ModeRegInit_LP4] CH0 RK1
2447 05:58:51.086711 [ModeRegInit_LP4] CH1 RK0
2448 05:58:51.087126 [ModeRegInit_LP4] CH1 RK1
2449 05:58:51.090182 match AC timing 7
2450 05:58:51.093003 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2451 05:58:51.096673 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2452 05:58:51.103560 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2453 05:58:51.106794 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2454 05:58:51.113258 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2455 05:58:51.113684 ==
2456 05:58:51.116270 Dram Type= 6, Freq= 0, CH_0, rank 0
2457 05:58:51.119998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2458 05:58:51.120457 ==
2459 05:58:51.126883 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2460 05:58:51.129556 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2461 05:58:51.140076 [CA 0] Center 39 (8~70) winsize 63
2462 05:58:51.143210 [CA 1] Center 39 (8~70) winsize 63
2463 05:58:51.146546 [CA 2] Center 35 (5~66) winsize 62
2464 05:58:51.149973 [CA 3] Center 34 (4~65) winsize 62
2465 05:58:51.153240 [CA 4] Center 33 (3~64) winsize 62
2466 05:58:51.157055 [CA 5] Center 32 (3~62) winsize 60
2467 05:58:51.157470
2468 05:58:51.159731 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2469 05:58:51.160398
2470 05:58:51.162994 [CATrainingPosCal] consider 1 rank data
2471 05:58:51.166776 u2DelayCellTimex100 = 270/100 ps
2472 05:58:51.170249 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2473 05:58:51.173177 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2474 05:58:51.180260 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2475 05:58:51.183170 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2476 05:58:51.186586 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2477 05:58:51.190093 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2478 05:58:51.190508
2479 05:58:51.193617 CA PerBit enable=1, Macro0, CA PI delay=32
2480 05:58:51.194030
2481 05:58:51.196577 [CBTSetCACLKResult] CA Dly = 32
2482 05:58:51.196992 CS Dly: 6 (0~37)
2483 05:58:51.197318 ==
2484 05:58:51.200084 Dram Type= 6, Freq= 0, CH_0, rank 1
2485 05:58:51.206712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2486 05:58:51.207131 ==
2487 05:58:51.210193 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2488 05:58:51.216559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2489 05:58:51.225622 [CA 0] Center 38 (8~69) winsize 62
2490 05:58:51.229206 [CA 1] Center 38 (8~69) winsize 62
2491 05:58:51.232589 [CA 2] Center 35 (5~66) winsize 62
2492 05:58:51.236039 [CA 3] Center 34 (4~65) winsize 62
2493 05:58:51.239334 [CA 4] Center 33 (3~64) winsize 62
2494 05:58:51.242501 [CA 5] Center 32 (3~62) winsize 60
2495 05:58:51.243083
2496 05:58:51.245903 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2497 05:58:51.246511
2498 05:58:51.249182 [CATrainingPosCal] consider 2 rank data
2499 05:58:51.252629 u2DelayCellTimex100 = 270/100 ps
2500 05:58:51.255636 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2501 05:58:51.258973 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2502 05:58:51.265526 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2503 05:58:51.268911 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2504 05:58:51.272509 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2505 05:58:51.275793 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2506 05:58:51.276202
2507 05:58:51.279033 CA PerBit enable=1, Macro0, CA PI delay=32
2508 05:58:51.279445
2509 05:58:51.282044 [CBTSetCACLKResult] CA Dly = 32
2510 05:58:51.282490 CS Dly: 6 (0~38)
2511 05:58:51.282861
2512 05:58:51.285949 ----->DramcWriteLeveling(PI) begin...
2513 05:58:51.288709 ==
2514 05:58:51.292095 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 05:58:51.295549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 05:58:51.296147 ==
2517 05:58:51.299154 Write leveling (Byte 0): 32 => 32
2518 05:58:51.302314 Write leveling (Byte 1): 28 => 28
2519 05:58:51.305586 DramcWriteLeveling(PI) end<-----
2520 05:58:51.306004
2521 05:58:51.306332 ==
2522 05:58:51.309088 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 05:58:51.312526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 05:58:51.312945 ==
2525 05:58:51.316201 [Gating] SW mode calibration
2526 05:58:51.322707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2527 05:58:51.325468 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2528 05:58:51.332840 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2529 05:58:51.335603 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2530 05:58:51.339237 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 05:58:51.345885 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 05:58:51.349171 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 05:58:51.352804 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 05:58:51.359112 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
2535 05:58:51.362888 0 15 28 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
2536 05:58:51.366358 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2537 05:58:51.372547 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 05:58:51.376060 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 05:58:51.379350 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 05:58:51.385493 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 05:58:51.388888 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 05:58:51.392415 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
2543 05:58:51.399392 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2544 05:58:51.403057 1 1 0 | B1->B0 | 3b3a 4646 | 1 0 | (0 0) (0 0)
2545 05:58:51.406042 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 05:58:51.409030 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 05:58:51.415831 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 05:58:51.419179 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 05:58:51.422997 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 05:58:51.429012 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 05:58:51.432548 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2552 05:58:51.435423 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2553 05:58:51.442532 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 05:58:51.446184 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 05:58:51.449459 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 05:58:51.455556 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 05:58:51.459285 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 05:58:51.462144 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 05:58:51.469291 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 05:58:51.472332 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 05:58:51.475680 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 05:58:51.482807 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 05:58:51.486398 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 05:58:51.488953 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 05:58:51.496055 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 05:58:51.499497 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2567 05:58:51.502124 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2568 05:58:51.506186 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2569 05:58:51.512619 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 05:58:51.515496 Total UI for P1: 0, mck2ui 16
2571 05:58:51.519246 best dqsien dly found for B0: ( 1, 3, 28)
2572 05:58:51.522810 Total UI for P1: 0, mck2ui 16
2573 05:58:51.525947 best dqsien dly found for B1: ( 1, 4, 0)
2574 05:58:51.529117 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2575 05:58:51.532623 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2576 05:58:51.533053
2577 05:58:51.535614 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2578 05:58:51.539376 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2579 05:58:51.542407 [Gating] SW calibration Done
2580 05:58:51.542856 ==
2581 05:58:51.545980 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 05:58:51.549145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 05:58:51.549643 ==
2584 05:58:51.552552 RX Vref Scan: 0
2585 05:58:51.552980
2586 05:58:51.553413 RX Vref 0 -> 0, step: 1
2587 05:58:51.553827
2588 05:58:51.556057 RX Delay -40 -> 252, step: 8
2589 05:58:51.558888 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2590 05:58:51.565757 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2591 05:58:51.569613 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2592 05:58:51.572909 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2593 05:58:51.575900 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2594 05:58:51.579421 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2595 05:58:51.585913 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2596 05:58:51.589357 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2597 05:58:51.592816 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2598 05:58:51.595600 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2599 05:58:51.599797 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2600 05:58:51.605868 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2601 05:58:51.609274 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2602 05:58:51.612816 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2603 05:58:51.615603 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2604 05:58:51.619332 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2605 05:58:51.622718 ==
2606 05:58:51.623146 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 05:58:51.629365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 05:58:51.629796 ==
2609 05:58:51.630234 DQS Delay:
2610 05:58:51.632944 DQS0 = 0, DQS1 = 0
2611 05:58:51.633357 DQM Delay:
2612 05:58:51.635687 DQM0 = 121, DQM1 = 113
2613 05:58:51.636098 DQ Delay:
2614 05:58:51.638997 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2615 05:58:51.642669 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2616 05:58:51.646208 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2617 05:58:51.649131 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2618 05:58:51.649612
2619 05:58:51.650109
2620 05:58:51.650519 ==
2621 05:58:51.652581 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 05:58:51.656391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 05:58:51.659283 ==
2624 05:58:51.659713
2625 05:58:51.660143
2626 05:58:51.660634 TX Vref Scan disable
2627 05:58:51.662326 == TX Byte 0 ==
2628 05:58:51.665772 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2629 05:58:51.669333 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2630 05:58:51.672985 == TX Byte 1 ==
2631 05:58:51.676346 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2632 05:58:51.679144 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2633 05:58:51.679573 ==
2634 05:58:51.683159 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 05:58:51.689230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 05:58:51.689723 ==
2637 05:58:51.700575 TX Vref=22, minBit 0, minWin=25, winSum=409
2638 05:58:51.703950 TX Vref=24, minBit 0, minWin=25, winSum=414
2639 05:58:51.707188 TX Vref=26, minBit 3, minWin=25, winSum=419
2640 05:58:51.710482 TX Vref=28, minBit 7, minWin=25, winSum=423
2641 05:58:51.713846 TX Vref=30, minBit 3, minWin=26, winSum=426
2642 05:58:51.717247 TX Vref=32, minBit 0, minWin=26, winSum=425
2643 05:58:51.723753 [TxChooseVref] Worse bit 3, Min win 26, Win sum 426, Final Vref 30
2644 05:58:51.724266
2645 05:58:51.727404 Final TX Range 1 Vref 30
2646 05:58:51.727934
2647 05:58:51.728265 ==
2648 05:58:51.730836 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 05:58:51.734414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 05:58:51.734962 ==
2651 05:58:51.735356
2652 05:58:51.735716
2653 05:58:51.737115 TX Vref Scan disable
2654 05:58:51.740647 == TX Byte 0 ==
2655 05:58:51.744106 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2656 05:58:51.748025 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2657 05:58:51.750718 == TX Byte 1 ==
2658 05:58:51.754605 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2659 05:58:51.757922 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2660 05:58:51.758497
2661 05:58:51.760765 [DATLAT]
2662 05:58:51.761179 Freq=1200, CH0 RK0
2663 05:58:51.761509
2664 05:58:51.764321 DATLAT Default: 0xd
2665 05:58:51.764743 0, 0xFFFF, sum = 0
2666 05:58:51.768118 1, 0xFFFF, sum = 0
2667 05:58:51.768749 2, 0xFFFF, sum = 0
2668 05:58:51.770931 3, 0xFFFF, sum = 0
2669 05:58:51.771453 4, 0xFFFF, sum = 0
2670 05:58:51.774610 5, 0xFFFF, sum = 0
2671 05:58:51.775168 6, 0xFFFF, sum = 0
2672 05:58:51.778183 7, 0xFFFF, sum = 0
2673 05:58:51.778705 8, 0xFFFF, sum = 0
2674 05:58:51.781462 9, 0xFFFF, sum = 0
2675 05:58:51.781982 10, 0xFFFF, sum = 0
2676 05:58:51.783993 11, 0xFFFF, sum = 0
2677 05:58:51.784663 12, 0x0, sum = 1
2678 05:58:51.787541 13, 0x0, sum = 2
2679 05:58:51.787963 14, 0x0, sum = 3
2680 05:58:51.791278 15, 0x0, sum = 4
2681 05:58:51.791802 best_step = 13
2682 05:58:51.792138
2683 05:58:51.792506 ==
2684 05:58:51.794450 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 05:58:51.801154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 05:58:51.801591 ==
2687 05:58:51.801922 RX Vref Scan: 1
2688 05:58:51.802226
2689 05:58:51.804108 Set Vref Range= 32 -> 127
2690 05:58:51.804567
2691 05:58:51.807496 RX Vref 32 -> 127, step: 1
2692 05:58:51.807958
2693 05:58:51.808582 RX Delay -13 -> 252, step: 4
2694 05:58:51.809091
2695 05:58:51.810697 Set Vref, RX VrefLevel [Byte0]: 32
2696 05:58:51.813958 [Byte1]: 32
2697 05:58:51.818707
2698 05:58:51.819114 Set Vref, RX VrefLevel [Byte0]: 33
2699 05:58:51.821742 [Byte1]: 33
2700 05:58:51.826389
2701 05:58:51.826799 Set Vref, RX VrefLevel [Byte0]: 34
2702 05:58:51.829862 [Byte1]: 34
2703 05:58:51.834676
2704 05:58:51.835427 Set Vref, RX VrefLevel [Byte0]: 35
2705 05:58:51.837853 [Byte1]: 35
2706 05:58:51.842258
2707 05:58:51.842666 Set Vref, RX VrefLevel [Byte0]: 36
2708 05:58:51.845542 [Byte1]: 36
2709 05:58:51.850482
2710 05:58:51.850897 Set Vref, RX VrefLevel [Byte0]: 37
2711 05:58:51.853439 [Byte1]: 37
2712 05:58:51.858445
2713 05:58:51.858855 Set Vref, RX VrefLevel [Byte0]: 38
2714 05:58:51.861267 [Byte1]: 38
2715 05:58:51.866273
2716 05:58:51.866695 Set Vref, RX VrefLevel [Byte0]: 39
2717 05:58:51.869078 [Byte1]: 39
2718 05:58:51.874451
2719 05:58:51.874963 Set Vref, RX VrefLevel [Byte0]: 40
2720 05:58:51.876961 [Byte1]: 40
2721 05:58:51.882045
2722 05:58:51.882459 Set Vref, RX VrefLevel [Byte0]: 41
2723 05:58:51.884831 [Byte1]: 41
2724 05:58:51.889802
2725 05:58:51.890320 Set Vref, RX VrefLevel [Byte0]: 42
2726 05:58:51.893025 [Byte1]: 42
2727 05:58:51.897385
2728 05:58:51.897810 Set Vref, RX VrefLevel [Byte0]: 43
2729 05:58:51.901303 [Byte1]: 43
2730 05:58:51.905712
2731 05:58:51.906246 Set Vref, RX VrefLevel [Byte0]: 44
2732 05:58:51.909079 [Byte1]: 44
2733 05:58:51.913182
2734 05:58:51.913610 Set Vref, RX VrefLevel [Byte0]: 45
2735 05:58:51.916593 [Byte1]: 45
2736 05:58:51.921458
2737 05:58:51.922090 Set Vref, RX VrefLevel [Byte0]: 46
2738 05:58:51.924234 [Byte1]: 46
2739 05:58:51.929100
2740 05:58:51.929526 Set Vref, RX VrefLevel [Byte0]: 47
2741 05:58:51.935613 [Byte1]: 47
2742 05:58:51.936046
2743 05:58:51.939145 Set Vref, RX VrefLevel [Byte0]: 48
2744 05:58:51.942363 [Byte1]: 48
2745 05:58:51.942894
2746 05:58:51.945280 Set Vref, RX VrefLevel [Byte0]: 49
2747 05:58:51.949144 [Byte1]: 49
2748 05:58:51.952969
2749 05:58:51.953488 Set Vref, RX VrefLevel [Byte0]: 50
2750 05:58:51.956596 [Byte1]: 50
2751 05:58:51.960582
2752 05:58:51.961033 Set Vref, RX VrefLevel [Byte0]: 51
2753 05:58:51.964061 [Byte1]: 51
2754 05:58:51.968699
2755 05:58:51.969131 Set Vref, RX VrefLevel [Byte0]: 52
2756 05:58:51.972120 [Byte1]: 52
2757 05:58:51.976403
2758 05:58:51.976818 Set Vref, RX VrefLevel [Byte0]: 53
2759 05:58:51.979623 [Byte1]: 53
2760 05:58:51.984665
2761 05:58:51.985153 Set Vref, RX VrefLevel [Byte0]: 54
2762 05:58:51.987605 [Byte1]: 54
2763 05:58:51.992611
2764 05:58:51.993278 Set Vref, RX VrefLevel [Byte0]: 55
2765 05:58:51.995050 [Byte1]: 55
2766 05:58:51.999970
2767 05:58:52.000554 Set Vref, RX VrefLevel [Byte0]: 56
2768 05:58:52.003578 [Byte1]: 56
2769 05:58:52.008021
2770 05:58:52.008473 Set Vref, RX VrefLevel [Byte0]: 57
2771 05:58:52.011612 [Byte1]: 57
2772 05:58:52.015774
2773 05:58:52.016424 Set Vref, RX VrefLevel [Byte0]: 58
2774 05:58:52.018822 [Byte1]: 58
2775 05:58:52.023828
2776 05:58:52.024239 Set Vref, RX VrefLevel [Byte0]: 59
2777 05:58:52.027668 [Byte1]: 59
2778 05:58:52.031841
2779 05:58:52.032404 Set Vref, RX VrefLevel [Byte0]: 60
2780 05:58:52.035399 [Byte1]: 60
2781 05:58:52.039806
2782 05:58:52.040368 Set Vref, RX VrefLevel [Byte0]: 61
2783 05:58:52.043120 [Byte1]: 61
2784 05:58:52.047467
2785 05:58:52.047986 Set Vref, RX VrefLevel [Byte0]: 62
2786 05:58:52.051879 [Byte1]: 62
2787 05:58:52.055400
2788 05:58:52.055814 Set Vref, RX VrefLevel [Byte0]: 63
2789 05:58:52.058725 [Byte1]: 63
2790 05:58:52.062907
2791 05:58:52.063320 Set Vref, RX VrefLevel [Byte0]: 64
2792 05:58:52.067059 [Byte1]: 64
2793 05:58:52.071245
2794 05:58:52.071835 Set Vref, RX VrefLevel [Byte0]: 65
2795 05:58:52.074018 [Byte1]: 65
2796 05:58:52.078883
2797 05:58:52.079465 Set Vref, RX VrefLevel [Byte0]: 66
2798 05:58:52.082278 [Byte1]: 66
2799 05:58:52.087034
2800 05:58:52.087451 Set Vref, RX VrefLevel [Byte0]: 67
2801 05:58:52.090014 [Byte1]: 67
2802 05:58:52.094930
2803 05:58:52.095360 Set Vref, RX VrefLevel [Byte0]: 68
2804 05:58:52.097950 [Byte1]: 68
2805 05:58:52.102822
2806 05:58:52.103384 Set Vref, RX VrefLevel [Byte0]: 69
2807 05:58:52.106039 [Byte1]: 69
2808 05:58:52.110842
2809 05:58:52.111409 Final RX Vref Byte 0 = 58 to rank0
2810 05:58:52.113624 Final RX Vref Byte 1 = 49 to rank0
2811 05:58:52.117503 Final RX Vref Byte 0 = 58 to rank1
2812 05:58:52.120414 Final RX Vref Byte 1 = 49 to rank1==
2813 05:58:52.124008 Dram Type= 6, Freq= 0, CH_0, rank 0
2814 05:58:52.130754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2815 05:58:52.131288 ==
2816 05:58:52.131735 DQS Delay:
2817 05:58:52.132146 DQS0 = 0, DQS1 = 0
2818 05:58:52.134189 DQM Delay:
2819 05:58:52.134615 DQM0 = 121, DQM1 = 112
2820 05:58:52.137316 DQ Delay:
2821 05:58:52.141054 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =120
2822 05:58:52.143848 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2823 05:58:52.147753 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106
2824 05:58:52.150528 DQ12 =118, DQ13 =116, DQ14 =124, DQ15 =120
2825 05:58:52.151024
2826 05:58:52.151459
2827 05:58:52.157045 [DQSOSCAuto] RK0, (LSB)MR18= 0x150f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2828 05:58:52.160722 CH0 RK0: MR19=404, MR18=150F
2829 05:58:52.167403 CH0_RK0: MR19=0x404, MR18=0x150F, DQSOSC=401, MR23=63, INC=40, DEC=27
2830 05:58:52.167831
2831 05:58:52.170665 ----->DramcWriteLeveling(PI) begin...
2832 05:58:52.171101 ==
2833 05:58:52.173993 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 05:58:52.177583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2835 05:58:52.181056 ==
2836 05:58:52.181532 Write leveling (Byte 0): 33 => 33
2837 05:58:52.184462 Write leveling (Byte 1): 27 => 27
2838 05:58:52.187230 DramcWriteLeveling(PI) end<-----
2839 05:58:52.187721
2840 05:58:52.188057 ==
2841 05:58:52.190925 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 05:58:52.197536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 05:58:52.197954 ==
2844 05:58:52.198290 [Gating] SW mode calibration
2845 05:58:52.207358 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2846 05:58:52.210903 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2847 05:58:52.213809 0 15 0 | B1->B0 | 3131 302f | 1 1 | (1 1) (0 0)
2848 05:58:52.220930 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 05:58:52.224150 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 05:58:52.227350 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 05:58:52.234381 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 05:58:52.237367 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 05:58:52.241165 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 05:58:52.247707 0 15 28 | B1->B0 | 2e2e 2b2b | 0 0 | (1 0) (0 1)
2855 05:58:52.250751 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 05:58:52.254353 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 05:58:52.261119 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 05:58:52.264279 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 05:58:52.267205 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 05:58:52.274052 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 05:58:52.277743 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 05:58:52.280813 1 0 28 | B1->B0 | 3e3e 3e3e | 0 1 | (0 0) (0 0)
2863 05:58:52.287657 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 05:58:52.290826 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 05:58:52.294159 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 05:58:52.297235 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 05:58:52.304147 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 05:58:52.307555 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 05:58:52.311215 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 05:58:52.317686 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2871 05:58:52.320602 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2872 05:58:52.324148 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 05:58:52.330904 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 05:58:52.334228 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 05:58:52.337685 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 05:58:52.344480 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 05:58:52.347628 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 05:58:52.350846 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 05:58:52.357818 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 05:58:52.360784 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 05:58:52.364502 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 05:58:52.371077 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 05:58:52.374196 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 05:58:52.377903 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 05:58:52.380720 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 05:58:52.387501 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2887 05:58:52.391174 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2888 05:58:52.394718 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 05:58:52.397441 Total UI for P1: 0, mck2ui 16
2890 05:58:52.400849 best dqsien dly found for B0: ( 1, 3, 30)
2891 05:58:52.404393 Total UI for P1: 0, mck2ui 16
2892 05:58:52.407760 best dqsien dly found for B1: ( 1, 3, 30)
2893 05:58:52.411413 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2894 05:58:52.414474 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2895 05:58:52.414890
2896 05:58:52.421659 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2897 05:58:52.424365 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2898 05:58:52.424791 [Gating] SW calibration Done
2899 05:58:52.427587 ==
2900 05:58:52.427998 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 05:58:52.434827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 05:58:52.435236 ==
2903 05:58:52.435560 RX Vref Scan: 0
2904 05:58:52.435864
2905 05:58:52.438313 RX Vref 0 -> 0, step: 1
2906 05:58:52.438729
2907 05:58:52.441141 RX Delay -40 -> 252, step: 8
2908 05:58:52.444397 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2909 05:58:52.448427 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2910 05:58:52.451317 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2911 05:58:52.458190 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2912 05:58:52.461369 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2913 05:58:52.464872 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2914 05:58:52.468112 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2915 05:58:52.471430 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2916 05:58:52.478040 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2917 05:58:52.481811 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2918 05:58:52.484592 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2919 05:58:52.488249 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2920 05:58:52.491269 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2921 05:58:52.494836 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2922 05:58:52.501538 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2923 05:58:52.505313 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2924 05:58:52.505728 ==
2925 05:58:52.508103 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 05:58:52.511722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 05:58:52.512133 ==
2928 05:58:52.514703 DQS Delay:
2929 05:58:52.515110 DQS0 = 0, DQS1 = 0
2930 05:58:52.515434 DQM Delay:
2931 05:58:52.518277 DQM0 = 122, DQM1 = 111
2932 05:58:52.518686 DQ Delay:
2933 05:58:52.521842 DQ0 =119, DQ1 =123, DQ2 =123, DQ3 =119
2934 05:58:52.525080 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2935 05:58:52.528489 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =103
2936 05:58:52.534851 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2937 05:58:52.535401
2938 05:58:52.535777
2939 05:58:52.536086 ==
2940 05:58:52.538669 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 05:58:52.541377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 05:58:52.541791 ==
2943 05:58:52.542113
2944 05:58:52.542412
2945 05:58:52.544998 TX Vref Scan disable
2946 05:58:52.545406 == TX Byte 0 ==
2947 05:58:52.551420 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2948 05:58:52.554780 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2949 05:58:52.555199 == TX Byte 1 ==
2950 05:58:52.562087 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2951 05:58:52.565149 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2952 05:58:52.565844 ==
2953 05:58:52.568470 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 05:58:52.571403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 05:58:52.571938 ==
2956 05:58:52.584844 TX Vref=22, minBit 2, minWin=25, winSum=413
2957 05:58:52.588168 TX Vref=24, minBit 3, minWin=25, winSum=418
2958 05:58:52.591685 TX Vref=26, minBit 4, minWin=25, winSum=422
2959 05:58:52.594834 TX Vref=28, minBit 1, minWin=26, winSum=427
2960 05:58:52.598424 TX Vref=30, minBit 1, minWin=26, winSum=430
2961 05:58:52.601491 TX Vref=32, minBit 0, minWin=26, winSum=429
2962 05:58:52.608951 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
2963 05:58:52.609512
2964 05:58:52.611811 Final TX Range 1 Vref 30
2965 05:58:52.612433
2966 05:58:52.612979 ==
2967 05:58:52.614674 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 05:58:52.618435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 05:58:52.618871 ==
2970 05:58:52.619200
2971 05:58:52.619501
2972 05:58:52.622152 TX Vref Scan disable
2973 05:58:52.625140 == TX Byte 0 ==
2974 05:58:52.628705 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2975 05:58:52.631514 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2976 05:58:52.635237 == TX Byte 1 ==
2977 05:58:52.638639 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2978 05:58:52.641459 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2979 05:58:52.641890
2980 05:58:52.644842 [DATLAT]
2981 05:58:52.645286 Freq=1200, CH0 RK1
2982 05:58:52.645619
2983 05:58:52.648161 DATLAT Default: 0xd
2984 05:58:52.648606 0, 0xFFFF, sum = 0
2985 05:58:52.651426 1, 0xFFFF, sum = 0
2986 05:58:52.651848 2, 0xFFFF, sum = 0
2987 05:58:52.655267 3, 0xFFFF, sum = 0
2988 05:58:52.655868 4, 0xFFFF, sum = 0
2989 05:58:52.658509 5, 0xFFFF, sum = 0
2990 05:58:52.658940 6, 0xFFFF, sum = 0
2991 05:58:52.662003 7, 0xFFFF, sum = 0
2992 05:58:52.662469 8, 0xFFFF, sum = 0
2993 05:58:52.665450 9, 0xFFFF, sum = 0
2994 05:58:52.665873 10, 0xFFFF, sum = 0
2995 05:58:52.668176 11, 0xFFFF, sum = 0
2996 05:58:52.668631 12, 0x0, sum = 1
2997 05:58:52.671736 13, 0x0, sum = 2
2998 05:58:52.672155 14, 0x0, sum = 3
2999 05:58:52.675427 15, 0x0, sum = 4
3000 05:58:52.675845 best_step = 13
3001 05:58:52.676173
3002 05:58:52.676531 ==
3003 05:58:52.678751 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 05:58:52.685189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 05:58:52.685605 ==
3006 05:58:52.685932 RX Vref Scan: 0
3007 05:58:52.686238
3008 05:58:52.689064 RX Vref 0 -> 0, step: 1
3009 05:58:52.689479
3010 05:58:52.691825 RX Delay -13 -> 252, step: 4
3011 05:58:52.695126 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3012 05:58:52.698446 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3013 05:58:52.705340 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3014 05:58:52.708146 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3015 05:58:52.711929 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3016 05:58:52.714872 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3017 05:58:52.718526 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3018 05:58:52.725086 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3019 05:58:52.729190 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3020 05:58:52.731854 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3021 05:58:52.735508 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3022 05:58:52.738272 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3023 05:58:52.744929 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3024 05:58:52.748632 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3025 05:58:52.751671 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3026 05:58:52.755758 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3027 05:58:52.756248 ==
3028 05:58:52.758490 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 05:58:52.761958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 05:58:52.765417 ==
3031 05:58:52.766068 DQS Delay:
3032 05:58:52.766441 DQS0 = 0, DQS1 = 0
3033 05:58:52.768714 DQM Delay:
3034 05:58:52.769129 DQM0 = 120, DQM1 = 110
3035 05:58:52.772022 DQ Delay:
3036 05:58:52.775307 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3037 05:58:52.778576 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3038 05:58:52.781723 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3039 05:58:52.785533 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118
3040 05:58:52.785946
3041 05:58:52.786273
3042 05:58:52.791830 [DQSOSCAuto] RK1, (LSB)MR18= 0xbed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3043 05:58:52.795254 CH0 RK1: MR19=403, MR18=BED
3044 05:58:52.801888 CH0_RK1: MR19=0x403, MR18=0xBED, DQSOSC=405, MR23=63, INC=39, DEC=26
3045 05:58:52.805526 [RxdqsGatingPostProcess] freq 1200
3046 05:58:52.812066 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3047 05:58:52.812541 best DQS0 dly(2T, 0.5T) = (0, 11)
3048 05:58:52.815381 best DQS1 dly(2T, 0.5T) = (0, 12)
3049 05:58:52.818363 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3050 05:58:52.822021 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3051 05:58:52.825284 best DQS0 dly(2T, 0.5T) = (0, 11)
3052 05:58:52.828762 best DQS1 dly(2T, 0.5T) = (0, 11)
3053 05:58:52.832217 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3054 05:58:52.835208 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3055 05:58:52.838775 Pre-setting of DQS Precalculation
3056 05:58:52.841273 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3057 05:58:52.844837 ==
3058 05:58:52.844919 Dram Type= 6, Freq= 0, CH_1, rank 0
3059 05:58:52.851505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 05:58:52.851606 ==
3061 05:58:52.855136 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3062 05:58:52.861703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3063 05:58:52.870861 [CA 0] Center 37 (7~68) winsize 62
3064 05:58:52.873757 [CA 1] Center 37 (7~68) winsize 62
3065 05:58:52.877310 [CA 2] Center 35 (5~65) winsize 61
3066 05:58:52.880218 [CA 3] Center 34 (5~64) winsize 60
3067 05:58:52.883826 [CA 4] Center 34 (4~64) winsize 61
3068 05:58:52.887258 [CA 5] Center 33 (3~63) winsize 61
3069 05:58:52.887375
3070 05:58:52.890632 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3071 05:58:52.890749
3072 05:58:52.893911 [CATrainingPosCal] consider 1 rank data
3073 05:58:52.897252 u2DelayCellTimex100 = 270/100 ps
3074 05:58:52.900604 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3075 05:58:52.904175 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3076 05:58:52.910597 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3077 05:58:52.914331 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3078 05:58:52.917265 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3079 05:58:52.920627 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3080 05:58:52.920717
3081 05:58:52.924093 CA PerBit enable=1, Macro0, CA PI delay=33
3082 05:58:52.924175
3083 05:58:52.927647 [CBTSetCACLKResult] CA Dly = 33
3084 05:58:52.927734 CS Dly: 7 (0~38)
3085 05:58:52.927798 ==
3086 05:58:52.930834 Dram Type= 6, Freq= 0, CH_1, rank 1
3087 05:58:52.937241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 05:58:52.937320 ==
3089 05:58:52.941059 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3090 05:58:52.947410 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3091 05:58:52.956733 [CA 0] Center 37 (7~68) winsize 62
3092 05:58:52.959646 [CA 1] Center 37 (7~68) winsize 62
3093 05:58:52.963196 [CA 2] Center 35 (5~65) winsize 61
3094 05:58:52.966176 [CA 3] Center 35 (5~65) winsize 61
3095 05:58:52.969654 [CA 4] Center 34 (4~65) winsize 62
3096 05:58:52.972668 [CA 5] Center 34 (4~64) winsize 61
3097 05:58:52.972748
3098 05:58:52.976373 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3099 05:58:52.976453
3100 05:58:52.979391 [CATrainingPosCal] consider 2 rank data
3101 05:58:52.983133 u2DelayCellTimex100 = 270/100 ps
3102 05:58:52.986080 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3103 05:58:52.989866 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3104 05:58:52.996317 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3105 05:58:52.999340 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3106 05:58:53.002752 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3107 05:58:53.005955 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3108 05:58:53.006086
3109 05:58:53.009537 CA PerBit enable=1, Macro0, CA PI delay=33
3110 05:58:53.009685
3111 05:58:53.013065 [CBTSetCACLKResult] CA Dly = 33
3112 05:58:53.013233 CS Dly: 8 (0~41)
3113 05:58:53.013365
3114 05:58:53.016520 ----->DramcWriteLeveling(PI) begin...
3115 05:58:53.019367 ==
3116 05:58:53.022727 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 05:58:53.026344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 05:58:53.026514 ==
3119 05:58:53.029213 Write leveling (Byte 0): 25 => 25
3120 05:58:53.032844 Write leveling (Byte 1): 26 => 26
3121 05:58:53.036620 DramcWriteLeveling(PI) end<-----
3122 05:58:53.036813
3123 05:58:53.036948 ==
3124 05:58:53.039201 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 05:58:53.042724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 05:58:53.042893 ==
3127 05:58:53.046604 [Gating] SW mode calibration
3128 05:58:53.053128 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3129 05:58:53.056024 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3130 05:58:53.063054 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 05:58:53.066623 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 05:58:53.069787 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 05:58:53.076744 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 05:58:53.079826 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 05:58:53.083546 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 05:58:53.089769 0 15 24 | B1->B0 | 3232 2a2a | 1 0 | (1 1) (0 0)
3137 05:58:53.093538 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3138 05:58:53.096595 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 05:58:53.103227 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 05:58:53.107094 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 05:58:53.109883 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 05:58:53.116830 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 05:58:53.120251 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 05:58:53.123219 1 0 24 | B1->B0 | 3030 3c3b | 1 1 | (0 0) (0 0)
3145 05:58:53.126666 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3146 05:58:53.133264 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 05:58:53.136814 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 05:58:53.140455 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 05:58:53.146349 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 05:58:53.149926 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 05:58:53.153263 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 05:58:53.159792 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3153 05:58:53.163329 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3154 05:58:53.166522 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 05:58:53.173080 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 05:58:53.176759 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 05:58:53.180436 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 05:58:53.187191 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 05:58:53.190143 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 05:58:53.193082 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 05:58:53.200185 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 05:58:53.203285 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 05:58:53.206560 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 05:58:53.210251 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 05:58:53.216891 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 05:58:53.220469 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 05:58:53.224054 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 05:58:53.230163 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3169 05:58:53.233944 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 05:58:53.237042 Total UI for P1: 0, mck2ui 16
3171 05:58:53.240763 best dqsien dly found for B0: ( 1, 3, 24)
3172 05:58:53.243578 Total UI for P1: 0, mck2ui 16
3173 05:58:53.247206 best dqsien dly found for B1: ( 1, 3, 24)
3174 05:58:53.250597 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3175 05:58:53.253547 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3176 05:58:53.253980
3177 05:58:53.257167 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3178 05:58:53.260127 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3179 05:58:53.263802 [Gating] SW calibration Done
3180 05:58:53.264170 ==
3181 05:58:53.267316 Dram Type= 6, Freq= 0, CH_1, rank 0
3182 05:58:53.270657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3183 05:58:53.271034 ==
3184 05:58:53.273963 RX Vref Scan: 0
3185 05:58:53.274348
3186 05:58:53.277294 RX Vref 0 -> 0, step: 1
3187 05:58:53.277777
3188 05:58:53.278255 RX Delay -40 -> 252, step: 8
3189 05:58:53.283715 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3190 05:58:53.287212 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3191 05:58:53.290383 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3192 05:58:53.294187 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3193 05:58:53.296982 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3194 05:58:53.304070 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3195 05:58:53.306780 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3196 05:58:53.310474 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3197 05:58:53.313536 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3198 05:58:53.317406 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3199 05:58:53.324090 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3200 05:58:53.326905 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3201 05:58:53.330694 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3202 05:58:53.334286 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3203 05:58:53.337064 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3204 05:58:53.343941 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3205 05:58:53.344500 ==
3206 05:58:53.347612 Dram Type= 6, Freq= 0, CH_1, rank 0
3207 05:58:53.350564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3208 05:58:53.351052 ==
3209 05:58:53.351355 DQS Delay:
3210 05:58:53.354168 DQS0 = 0, DQS1 = 0
3211 05:58:53.354578 DQM Delay:
3212 05:58:53.357792 DQM0 = 121, DQM1 = 116
3213 05:58:53.358161 DQ Delay:
3214 05:58:53.360651 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3215 05:58:53.363918 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3216 05:58:53.367520 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3217 05:58:53.371220 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3218 05:58:53.371568
3219 05:58:53.371854
3220 05:58:53.372120 ==
3221 05:58:53.374215 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 05:58:53.380851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 05:58:53.381356 ==
3224 05:58:53.381867
3225 05:58:53.382216
3226 05:58:53.382586 TX Vref Scan disable
3227 05:58:53.384589 == TX Byte 0 ==
3228 05:58:53.388126 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3229 05:58:53.391647 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3230 05:58:53.394664 == TX Byte 1 ==
3231 05:58:53.397848 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3232 05:58:53.400983 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3233 05:58:53.404589 ==
3234 05:58:53.407976 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 05:58:53.411219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 05:58:53.411319 ==
3237 05:58:53.421549 TX Vref=22, minBit 12, minWin=24, winSum=412
3238 05:58:53.425477 TX Vref=24, minBit 1, minWin=25, winSum=417
3239 05:58:53.428776 TX Vref=26, minBit 9, minWin=25, winSum=420
3240 05:58:53.431860 TX Vref=28, minBit 1, minWin=26, winSum=428
3241 05:58:53.435693 TX Vref=30, minBit 10, minWin=25, winSum=429
3242 05:58:53.442253 TX Vref=32, minBit 10, minWin=25, winSum=430
3243 05:58:53.445239 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
3244 05:58:53.445364
3245 05:58:53.448984 Final TX Range 1 Vref 28
3246 05:58:53.449072
3247 05:58:53.449144 ==
3248 05:58:53.451764 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 05:58:53.455741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 05:58:53.455825 ==
3251 05:58:53.455890
3252 05:58:53.458731
3253 05:58:53.458845 TX Vref Scan disable
3254 05:58:53.461764 == TX Byte 0 ==
3255 05:58:53.465537 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3256 05:58:53.469313 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3257 05:58:53.472197 == TX Byte 1 ==
3258 05:58:53.475887 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3259 05:58:53.479073 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3260 05:58:53.479156
3261 05:58:53.482610 [DATLAT]
3262 05:58:53.482692 Freq=1200, CH1 RK0
3263 05:58:53.482758
3264 05:58:53.485840 DATLAT Default: 0xd
3265 05:58:53.485921 0, 0xFFFF, sum = 0
3266 05:58:53.488578 1, 0xFFFF, sum = 0
3267 05:58:53.488679 2, 0xFFFF, sum = 0
3268 05:58:53.492772 3, 0xFFFF, sum = 0
3269 05:58:53.493227 4, 0xFFFF, sum = 0
3270 05:58:53.495722 5, 0xFFFF, sum = 0
3271 05:58:53.496140 6, 0xFFFF, sum = 0
3272 05:58:53.499478 7, 0xFFFF, sum = 0
3273 05:58:53.499893 8, 0xFFFF, sum = 0
3274 05:58:53.502522 9, 0xFFFF, sum = 0
3275 05:58:53.506128 10, 0xFFFF, sum = 0
3276 05:58:53.506545 11, 0xFFFF, sum = 0
3277 05:58:53.509494 12, 0x0, sum = 1
3278 05:58:53.509909 13, 0x0, sum = 2
3279 05:58:53.510245 14, 0x0, sum = 3
3280 05:58:53.512727 15, 0x0, sum = 4
3281 05:58:53.513146 best_step = 13
3282 05:58:53.513477
3283 05:58:53.513778 ==
3284 05:58:53.515723 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 05:58:53.522870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 05:58:53.523296 ==
3287 05:58:53.523626 RX Vref Scan: 1
3288 05:58:53.523931
3289 05:58:53.526345 Set Vref Range= 32 -> 127
3290 05:58:53.526861
3291 05:58:53.529188 RX Vref 32 -> 127, step: 1
3292 05:58:53.529639
3293 05:58:53.532932 RX Delay -5 -> 252, step: 4
3294 05:58:53.533388
3295 05:58:53.535775 Set Vref, RX VrefLevel [Byte0]: 32
3296 05:58:53.536283 [Byte1]: 32
3297 05:58:53.540197
3298 05:58:53.540727 Set Vref, RX VrefLevel [Byte0]: 33
3299 05:58:53.544138 [Byte1]: 33
3300 05:58:53.548253
3301 05:58:53.548739 Set Vref, RX VrefLevel [Byte0]: 34
3302 05:58:53.551881 [Byte1]: 34
3303 05:58:53.555904
3304 05:58:53.556552 Set Vref, RX VrefLevel [Byte0]: 35
3305 05:58:53.559521 [Byte1]: 35
3306 05:58:53.564281
3307 05:58:53.564719 Set Vref, RX VrefLevel [Byte0]: 36
3308 05:58:53.567269 [Byte1]: 36
3309 05:58:53.571769
3310 05:58:53.572026 Set Vref, RX VrefLevel [Byte0]: 37
3311 05:58:53.575545 [Byte1]: 37
3312 05:58:53.579810
3313 05:58:53.582518 Set Vref, RX VrefLevel [Byte0]: 38
3314 05:58:53.586243 [Byte1]: 38
3315 05:58:53.586570
3316 05:58:53.589895 Set Vref, RX VrefLevel [Byte0]: 39
3317 05:58:53.592706 [Byte1]: 39
3318 05:58:53.592923
3319 05:58:53.596363 Set Vref, RX VrefLevel [Byte0]: 40
3320 05:58:53.599230 [Byte1]: 40
3321 05:58:53.603136
3322 05:58:53.603354 Set Vref, RX VrefLevel [Byte0]: 41
3323 05:58:53.606397 [Byte1]: 41
3324 05:58:53.610910
3325 05:58:53.611129 Set Vref, RX VrefLevel [Byte0]: 42
3326 05:58:53.614777 [Byte1]: 42
3327 05:58:53.619049
3328 05:58:53.619267 Set Vref, RX VrefLevel [Byte0]: 43
3329 05:58:53.622095 [Byte1]: 43
3330 05:58:53.626743
3331 05:58:53.626958 Set Vref, RX VrefLevel [Byte0]: 44
3332 05:58:53.630296 [Byte1]: 44
3333 05:58:53.634978
3334 05:58:53.635223 Set Vref, RX VrefLevel [Byte0]: 45
3335 05:58:53.638053 [Byte1]: 45
3336 05:58:53.642592
3337 05:58:53.642861 Set Vref, RX VrefLevel [Byte0]: 46
3338 05:58:53.645810 [Byte1]: 46
3339 05:58:53.650274
3340 05:58:53.650625 Set Vref, RX VrefLevel [Byte0]: 47
3341 05:58:53.653809 [Byte1]: 47
3342 05:58:53.658014
3343 05:58:53.658276 Set Vref, RX VrefLevel [Byte0]: 48
3344 05:58:53.661713 [Byte1]: 48
3345 05:58:53.666025
3346 05:58:53.666314 Set Vref, RX VrefLevel [Byte0]: 49
3347 05:58:53.669586 [Byte1]: 49
3348 05:58:53.673884
3349 05:58:53.674154 Set Vref, RX VrefLevel [Byte0]: 50
3350 05:58:53.677433 [Byte1]: 50
3351 05:58:53.681961
3352 05:58:53.682312 Set Vref, RX VrefLevel [Byte0]: 51
3353 05:58:53.684877 [Byte1]: 51
3354 05:58:53.689860
3355 05:58:53.690418 Set Vref, RX VrefLevel [Byte0]: 52
3356 05:58:53.693605 [Byte1]: 52
3357 05:58:53.697879
3358 05:58:53.698286 Set Vref, RX VrefLevel [Byte0]: 53
3359 05:58:53.700809 [Byte1]: 53
3360 05:58:53.705143
3361 05:58:53.705544 Set Vref, RX VrefLevel [Byte0]: 54
3362 05:58:53.709052 [Byte1]: 54
3363 05:58:53.713727
3364 05:58:53.714259 Set Vref, RX VrefLevel [Byte0]: 55
3365 05:58:53.716638 [Byte1]: 55
3366 05:58:53.721553
3367 05:58:53.721974 Set Vref, RX VrefLevel [Byte0]: 56
3368 05:58:53.724507 [Byte1]: 56
3369 05:58:53.728776
3370 05:58:53.729218 Set Vref, RX VrefLevel [Byte0]: 57
3371 05:58:53.732444 [Byte1]: 57
3372 05:58:53.736814
3373 05:58:53.737263 Set Vref, RX VrefLevel [Byte0]: 58
3374 05:58:53.739763 [Byte1]: 58
3375 05:58:53.744903
3376 05:58:53.748013 Set Vref, RX VrefLevel [Byte0]: 59
3377 05:58:53.751493 [Byte1]: 59
3378 05:58:53.751923
3379 05:58:53.754557 Set Vref, RX VrefLevel [Byte0]: 60
3380 05:58:53.757407 [Byte1]: 60
3381 05:58:53.757835
3382 05:58:53.761362 Set Vref, RX VrefLevel [Byte0]: 61
3383 05:58:53.764545 [Byte1]: 61
3384 05:58:53.768111
3385 05:58:53.768758 Set Vref, RX VrefLevel [Byte0]: 62
3386 05:58:53.771212 [Byte1]: 62
3387 05:58:53.775825
3388 05:58:53.776234 Set Vref, RX VrefLevel [Byte0]: 63
3389 05:58:53.779397 [Byte1]: 63
3390 05:58:53.784235
3391 05:58:53.784691 Set Vref, RX VrefLevel [Byte0]: 64
3392 05:58:53.787374 [Byte1]: 64
3393 05:58:53.791666
3394 05:58:53.792227 Set Vref, RX VrefLevel [Byte0]: 65
3395 05:58:53.795453 [Byte1]: 65
3396 05:58:53.799902
3397 05:58:53.800491 Set Vref, RX VrefLevel [Byte0]: 66
3398 05:58:53.802862 [Byte1]: 66
3399 05:58:53.807209
3400 05:58:53.807771 Set Vref, RX VrefLevel [Byte0]: 67
3401 05:58:53.811117 [Byte1]: 67
3402 05:58:53.815608
3403 05:58:53.816275 Final RX Vref Byte 0 = 56 to rank0
3404 05:58:53.818769 Final RX Vref Byte 1 = 49 to rank0
3405 05:58:53.822191 Final RX Vref Byte 0 = 56 to rank1
3406 05:58:53.825318 Final RX Vref Byte 1 = 49 to rank1==
3407 05:58:53.829007 Dram Type= 6, Freq= 0, CH_1, rank 0
3408 05:58:53.835073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3409 05:58:53.835656 ==
3410 05:58:53.836062 DQS Delay:
3411 05:58:53.836583 DQS0 = 0, DQS1 = 0
3412 05:58:53.838782 DQM Delay:
3413 05:58:53.839445 DQM0 = 120, DQM1 = 116
3414 05:58:53.841804 DQ Delay:
3415 05:58:53.845294 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3416 05:58:53.848499 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3417 05:58:53.852252 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3418 05:58:53.855354 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3419 05:58:53.855741
3420 05:58:53.856113
3421 05:58:53.861899 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe10, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3422 05:58:53.865028 CH1 RK0: MR19=304, MR18=FE10
3423 05:58:53.871785 CH1_RK0: MR19=0x304, MR18=0xFE10, DQSOSC=403, MR23=63, INC=40, DEC=26
3424 05:58:53.872087
3425 05:58:53.875406 ----->DramcWriteLeveling(PI) begin...
3426 05:58:53.875805 ==
3427 05:58:53.878934 Dram Type= 6, Freq= 0, CH_1, rank 1
3428 05:58:53.882015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 05:58:53.882382 ==
3430 05:58:53.885229 Write leveling (Byte 0): 26 => 26
3431 05:58:53.889006 Write leveling (Byte 1): 28 => 28
3432 05:58:53.893124 DramcWriteLeveling(PI) end<-----
3433 05:58:53.893553
3434 05:58:53.893907 ==
3435 05:58:53.895715 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 05:58:53.899077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 05:58:53.902476 ==
3438 05:58:53.902864 [Gating] SW mode calibration
3439 05:58:53.912885 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3440 05:58:53.915590 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3441 05:58:53.918564 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 05:58:53.925359 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 05:58:53.929120 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 05:58:53.932085 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 05:58:53.938937 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 05:58:53.942415 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3447 05:58:53.945324 0 15 24 | B1->B0 | 2b2b 3434 | 0 1 | (0 1) (1 0)
3448 05:58:53.952247 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3449 05:58:53.955874 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 05:58:53.959120 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 05:58:53.965669 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 05:58:53.968851 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 05:58:53.972346 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 05:58:53.978869 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3455 05:58:53.982157 1 0 24 | B1->B0 | 4545 2525 | 0 0 | (0 0) (0 0)
3456 05:58:53.985905 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3457 05:58:53.988930 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 05:58:53.995306 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 05:58:53.998794 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 05:58:54.002535 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 05:58:54.009211 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 05:58:54.012278 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 05:58:54.015769 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3464 05:58:54.022223 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3465 05:58:54.025579 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 05:58:54.028860 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 05:58:54.035888 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 05:58:54.038661 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 05:58:54.042003 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 05:58:54.049014 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 05:58:54.052009 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 05:58:54.055636 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 05:58:54.062096 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 05:58:54.065706 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 05:58:54.068735 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 05:58:54.075365 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 05:58:54.078874 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 05:58:54.082287 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3479 05:58:54.088996 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3480 05:58:54.091815 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 05:58:54.095320 Total UI for P1: 0, mck2ui 16
3482 05:58:54.098952 best dqsien dly found for B0: ( 1, 3, 24)
3483 05:58:54.101843 Total UI for P1: 0, mck2ui 16
3484 05:58:54.105347 best dqsien dly found for B1: ( 1, 3, 22)
3485 05:58:54.108891 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3486 05:58:54.111653 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3487 05:58:54.112100
3488 05:58:54.115214 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3489 05:58:54.118143 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3490 05:58:54.121934 [Gating] SW calibration Done
3491 05:58:54.122458 ==
3492 05:58:54.125312 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 05:58:54.128561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 05:58:54.129087 ==
3495 05:58:54.131445 RX Vref Scan: 0
3496 05:58:54.131947
3497 05:58:54.135249 RX Vref 0 -> 0, step: 1
3498 05:58:54.135673
3499 05:58:54.136113 RX Delay -40 -> 252, step: 8
3500 05:58:54.142148 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3501 05:58:54.144946 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3502 05:58:54.148507 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3503 05:58:54.151707 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3504 05:58:54.155239 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3505 05:58:54.161584 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3506 05:58:54.164867 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3507 05:58:54.167878 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3508 05:58:54.171707 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3509 05:58:54.174669 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3510 05:58:54.181454 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3511 05:58:54.184453 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3512 05:58:54.188035 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3513 05:58:54.190918 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3514 05:58:54.197670 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3515 05:58:54.201681 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3516 05:58:54.201796 ==
3517 05:58:54.204763 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 05:58:54.208015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 05:58:54.208112 ==
3520 05:58:54.208178 DQS Delay:
3521 05:58:54.210840 DQS0 = 0, DQS1 = 0
3522 05:58:54.210952 DQM Delay:
3523 05:58:54.214792 DQM0 = 120, DQM1 = 118
3524 05:58:54.214905 DQ Delay:
3525 05:58:54.217818 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3526 05:58:54.221401 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3527 05:58:54.225051 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3528 05:58:54.227906 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3529 05:58:54.228004
3530 05:58:54.231514
3531 05:58:54.231615 ==
3532 05:58:54.234399 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 05:58:54.238240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 05:58:54.238341 ==
3535 05:58:54.238431
3536 05:58:54.238517
3537 05:58:54.241130 TX Vref Scan disable
3538 05:58:54.241197 == TX Byte 0 ==
3539 05:58:54.247582 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3540 05:58:54.250892 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3541 05:58:54.250980 == TX Byte 1 ==
3542 05:58:54.257506 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3543 05:58:54.261254 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3544 05:58:54.261387 ==
3545 05:58:54.264112 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 05:58:54.267908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 05:58:54.268075 ==
3548 05:58:54.280269 TX Vref=22, minBit 10, minWin=25, winSum=421
3549 05:58:54.283572 TX Vref=24, minBit 1, minWin=26, winSum=423
3550 05:58:54.286625 TX Vref=26, minBit 8, minWin=26, winSum=430
3551 05:58:54.290296 TX Vref=28, minBit 9, minWin=26, winSum=435
3552 05:58:54.293111 TX Vref=30, minBit 9, minWin=26, winSum=434
3553 05:58:54.299680 TX Vref=32, minBit 9, minWin=26, winSum=435
3554 05:58:54.303528 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 28
3555 05:58:54.303631
3556 05:58:54.306249 Final TX Range 1 Vref 28
3557 05:58:54.306354
3558 05:58:54.306435 ==
3559 05:58:54.310057 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 05:58:54.313146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 05:58:54.313271 ==
3562 05:58:54.316613
3563 05:58:54.316734
3564 05:58:54.316831 TX Vref Scan disable
3565 05:58:54.319539 == TX Byte 0 ==
3566 05:58:54.323230 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3567 05:58:54.329868 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3568 05:58:54.330300 == TX Byte 1 ==
3569 05:58:54.333379 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3570 05:58:54.339662 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3571 05:58:54.340168
3572 05:58:54.340538 [DATLAT]
3573 05:58:54.340843 Freq=1200, CH1 RK1
3574 05:58:54.341140
3575 05:58:54.343058 DATLAT Default: 0xd
3576 05:58:54.343494 0, 0xFFFF, sum = 0
3577 05:58:54.346629 1, 0xFFFF, sum = 0
3578 05:58:54.349791 2, 0xFFFF, sum = 0
3579 05:58:54.350211 3, 0xFFFF, sum = 0
3580 05:58:54.353375 4, 0xFFFF, sum = 0
3581 05:58:54.353882 5, 0xFFFF, sum = 0
3582 05:58:54.356353 6, 0xFFFF, sum = 0
3583 05:58:54.356770 7, 0xFFFF, sum = 0
3584 05:58:54.359959 8, 0xFFFF, sum = 0
3585 05:58:54.360598 9, 0xFFFF, sum = 0
3586 05:58:54.362852 10, 0xFFFF, sum = 0
3587 05:58:54.363409 11, 0xFFFF, sum = 0
3588 05:58:54.366768 12, 0x0, sum = 1
3589 05:58:54.367221 13, 0x0, sum = 2
3590 05:58:54.369858 14, 0x0, sum = 3
3591 05:58:54.370292 15, 0x0, sum = 4
3592 05:58:54.373378 best_step = 13
3593 05:58:54.373785
3594 05:58:54.374107 ==
3595 05:58:54.376421 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 05:58:54.379770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 05:58:54.380379 ==
3598 05:58:54.380740 RX Vref Scan: 0
3599 05:58:54.381087
3600 05:58:54.383362 RX Vref 0 -> 0, step: 1
3601 05:58:54.383768
3602 05:58:54.386235 RX Delay -5 -> 252, step: 4
3603 05:58:54.389976 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3604 05:58:54.396791 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3605 05:58:54.399513 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3606 05:58:54.402936 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3607 05:58:54.406492 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3608 05:58:54.410121 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3609 05:58:54.416032 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3610 05:58:54.419702 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3611 05:58:54.422659 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3612 05:58:54.426476 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3613 05:58:54.429680 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3614 05:58:54.436550 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3615 05:58:54.439603 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3616 05:58:54.442688 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3617 05:58:54.445876 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3618 05:58:54.449437 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3619 05:58:54.453214 ==
3620 05:58:54.456016 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 05:58:54.459605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 05:58:54.460220 ==
3623 05:58:54.460663 DQS Delay:
3624 05:58:54.463052 DQS0 = 0, DQS1 = 0
3625 05:58:54.463490 DQM Delay:
3626 05:58:54.466117 DQM0 = 120, DQM1 = 116
3627 05:58:54.466550 DQ Delay:
3628 05:58:54.469722 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3629 05:58:54.472545 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3630 05:58:54.476179 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3631 05:58:54.479059 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3632 05:58:54.479478
3633 05:58:54.479895
3634 05:58:54.489016 [DQSOSCAuto] RK1, (LSB)MR18= 0xfec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3635 05:58:54.492409 CH1 RK1: MR19=403, MR18=FEC
3636 05:58:54.495883 CH1_RK1: MR19=0x403, MR18=0xFEC, DQSOSC=404, MR23=63, INC=40, DEC=26
3637 05:58:54.498885 [RxdqsGatingPostProcess] freq 1200
3638 05:58:54.505447 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3639 05:58:54.508848 best DQS0 dly(2T, 0.5T) = (0, 11)
3640 05:58:54.512207 best DQS1 dly(2T, 0.5T) = (0, 11)
3641 05:58:54.515634 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3642 05:58:54.519025 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3643 05:58:54.522352 best DQS0 dly(2T, 0.5T) = (0, 11)
3644 05:58:54.525534 best DQS1 dly(2T, 0.5T) = (0, 11)
3645 05:58:54.529136 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3646 05:58:54.532093 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3647 05:58:54.532600 Pre-setting of DQS Precalculation
3648 05:58:54.538915 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3649 05:58:54.545478 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3650 05:58:54.551849 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3651 05:58:54.552422
3652 05:58:54.555346
3653 05:58:54.555756 [Calibration Summary] 2400 Mbps
3654 05:58:54.558377 CH 0, Rank 0
3655 05:58:54.558489 SW Impedance : PASS
3656 05:58:54.561875 DUTY Scan : NO K
3657 05:58:54.564665 ZQ Calibration : PASS
3658 05:58:54.564745 Jitter Meter : NO K
3659 05:58:54.568281 CBT Training : PASS
3660 05:58:54.571787 Write leveling : PASS
3661 05:58:54.571892 RX DQS gating : PASS
3662 05:58:54.574785 RX DQ/DQS(RDDQC) : PASS
3663 05:58:54.578213 TX DQ/DQS : PASS
3664 05:58:54.578303 RX DATLAT : PASS
3665 05:58:54.581862 RX DQ/DQS(Engine): PASS
3666 05:58:54.585044 TX OE : NO K
3667 05:58:54.585166 All Pass.
3668 05:58:54.585270
3669 05:58:54.585370 CH 0, Rank 1
3670 05:58:54.588701 SW Impedance : PASS
3671 05:58:54.591791 DUTY Scan : NO K
3672 05:58:54.591870 ZQ Calibration : PASS
3673 05:58:54.594756 Jitter Meter : NO K
3674 05:58:54.594839 CBT Training : PASS
3675 05:58:54.598356 Write leveling : PASS
3676 05:58:54.601262 RX DQS gating : PASS
3677 05:58:54.601360 RX DQ/DQS(RDDQC) : PASS
3678 05:58:54.604769 TX DQ/DQS : PASS
3679 05:58:54.608384 RX DATLAT : PASS
3680 05:58:54.608502 RX DQ/DQS(Engine): PASS
3681 05:58:54.611811 TX OE : NO K
3682 05:58:54.611930 All Pass.
3683 05:58:54.612044
3684 05:58:54.614778 CH 1, Rank 0
3685 05:58:54.614910 SW Impedance : PASS
3686 05:58:54.618568 DUTY Scan : NO K
3687 05:58:54.621786 ZQ Calibration : PASS
3688 05:58:54.621933 Jitter Meter : NO K
3689 05:58:54.624831 CBT Training : PASS
3690 05:58:54.628496 Write leveling : PASS
3691 05:58:54.628692 RX DQS gating : PASS
3692 05:58:54.631399 RX DQ/DQS(RDDQC) : PASS
3693 05:58:54.634834 TX DQ/DQS : PASS
3694 05:58:54.635070 RX DATLAT : PASS
3695 05:58:54.638013 RX DQ/DQS(Engine): PASS
3696 05:58:54.641399 TX OE : NO K
3697 05:58:54.641690 All Pass.
3698 05:58:54.641918
3699 05:58:54.642183 CH 1, Rank 1
3700 05:58:54.645020 SW Impedance : PASS
3701 05:58:54.648582 DUTY Scan : NO K
3702 05:58:54.649143 ZQ Calibration : PASS
3703 05:58:54.651537 Jitter Meter : NO K
3704 05:58:54.652105 CBT Training : PASS
3705 05:58:54.655041 Write leveling : PASS
3706 05:58:54.658653 RX DQS gating : PASS
3707 05:58:54.659130 RX DQ/DQS(RDDQC) : PASS
3708 05:58:54.661467 TX DQ/DQS : PASS
3709 05:58:54.664812 RX DATLAT : PASS
3710 05:58:54.665262 RX DQ/DQS(Engine): PASS
3711 05:58:54.668054 TX OE : NO K
3712 05:58:54.668563 All Pass.
3713 05:58:54.668901
3714 05:58:54.671236 DramC Write-DBI off
3715 05:58:54.674587 PER_BANK_REFRESH: Hybrid Mode
3716 05:58:54.675233 TX_TRACKING: ON
3717 05:58:54.684561 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3718 05:58:54.687970 [FAST_K] Save calibration result to emmc
3719 05:58:54.691470 dramc_set_vcore_voltage set vcore to 650000
3720 05:58:54.694861 Read voltage for 600, 5
3721 05:58:54.695275 Vio18 = 0
3722 05:58:54.695607 Vcore = 650000
3723 05:58:54.697808 Vdram = 0
3724 05:58:54.698220 Vddq = 0
3725 05:58:54.698547 Vmddr = 0
3726 05:58:54.704432 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3727 05:58:54.707903 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3728 05:58:54.711474 MEM_TYPE=3, freq_sel=19
3729 05:58:54.714356 sv_algorithm_assistance_LP4_1600
3730 05:58:54.717824 ============ PULL DRAM RESETB DOWN ============
3731 05:58:54.721417 ========== PULL DRAM RESETB DOWN end =========
3732 05:58:54.728140 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3733 05:58:54.730831 ===================================
3734 05:58:54.734340 LPDDR4 DRAM CONFIGURATION
3735 05:58:54.737827 ===================================
3736 05:58:54.737943 EX_ROW_EN[0] = 0x0
3737 05:58:54.740684 EX_ROW_EN[1] = 0x0
3738 05:58:54.740798 LP4Y_EN = 0x0
3739 05:58:54.744139 WORK_FSP = 0x0
3740 05:58:54.744259 WL = 0x2
3741 05:58:54.747415 RL = 0x2
3742 05:58:54.747506 BL = 0x2
3743 05:58:54.750876 RPST = 0x0
3744 05:58:54.750968 RD_PRE = 0x0
3745 05:58:54.754024 WR_PRE = 0x1
3746 05:58:54.754107 WR_PST = 0x0
3747 05:58:54.757492 DBI_WR = 0x0
3748 05:58:54.757573 DBI_RD = 0x0
3749 05:58:54.760529 OTF = 0x1
3750 05:58:54.764203 ===================================
3751 05:58:54.767731 ===================================
3752 05:58:54.767813 ANA top config
3753 05:58:54.770509 ===================================
3754 05:58:54.774213 DLL_ASYNC_EN = 0
3755 05:58:54.777535 ALL_SLAVE_EN = 1
3756 05:58:54.780529 NEW_RANK_MODE = 1
3757 05:58:54.780604 DLL_IDLE_MODE = 1
3758 05:58:54.783981 LP45_APHY_COMB_EN = 1
3759 05:58:54.787403 TX_ODT_DIS = 1
3760 05:58:54.790705 NEW_8X_MODE = 1
3761 05:58:54.793904 ===================================
3762 05:58:54.797041 ===================================
3763 05:58:54.800621 data_rate = 1200
3764 05:58:54.803916 CKR = 1
3765 05:58:54.804036 DQ_P2S_RATIO = 8
3766 05:58:54.807326 ===================================
3767 05:58:54.810361 CA_P2S_RATIO = 8
3768 05:58:54.813797 DQ_CA_OPEN = 0
3769 05:58:54.817410 DQ_SEMI_OPEN = 0
3770 05:58:54.820469 CA_SEMI_OPEN = 0
3771 05:58:54.820551 CA_FULL_RATE = 0
3772 05:58:54.824021 DQ_CKDIV4_EN = 1
3773 05:58:54.827495 CA_CKDIV4_EN = 1
3774 05:58:54.830200 CA_PREDIV_EN = 0
3775 05:58:54.833788 PH8_DLY = 0
3776 05:58:54.837150 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3777 05:58:54.837252 DQ_AAMCK_DIV = 4
3778 05:58:54.840790 CA_AAMCK_DIV = 4
3779 05:58:54.843601 CA_ADMCK_DIV = 4
3780 05:58:54.846977 DQ_TRACK_CA_EN = 0
3781 05:58:54.850430 CA_PICK = 600
3782 05:58:54.854218 CA_MCKIO = 600
3783 05:58:54.856880 MCKIO_SEMI = 0
3784 05:58:54.856955 PLL_FREQ = 2288
3785 05:58:54.860505 DQ_UI_PI_RATIO = 32
3786 05:58:54.863587 CA_UI_PI_RATIO = 0
3787 05:58:54.866889 ===================================
3788 05:58:54.870268 ===================================
3789 05:58:54.873687 memory_type:LPDDR4
3790 05:58:54.873794 GP_NUM : 10
3791 05:58:54.877248 SRAM_EN : 1
3792 05:58:54.880061 MD32_EN : 0
3793 05:58:54.883406 ===================================
3794 05:58:54.883508 [ANA_INIT] >>>>>>>>>>>>>>
3795 05:58:54.886935 <<<<<< [CONFIGURE PHASE]: ANA_TX
3796 05:58:54.890388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3797 05:58:54.893078 ===================================
3798 05:58:54.896773 data_rate = 1200,PCW = 0X5800
3799 05:58:54.900498 ===================================
3800 05:58:54.903278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3801 05:58:54.910502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3802 05:58:54.913209 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3803 05:58:54.919743 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3804 05:58:54.923374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3805 05:58:54.926705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3806 05:58:54.930076 [ANA_INIT] flow start
3807 05:58:54.930301 [ANA_INIT] PLL >>>>>>>>
3808 05:58:54.933444 [ANA_INIT] PLL <<<<<<<<
3809 05:58:54.936790 [ANA_INIT] MIDPI >>>>>>>>
3810 05:58:54.937069 [ANA_INIT] MIDPI <<<<<<<<
3811 05:58:54.940062 [ANA_INIT] DLL >>>>>>>>
3812 05:58:54.943545 [ANA_INIT] flow end
3813 05:58:54.947002 ============ LP4 DIFF to SE enter ============
3814 05:58:54.950632 ============ LP4 DIFF to SE exit ============
3815 05:58:54.954046 [ANA_INIT] <<<<<<<<<<<<<
3816 05:58:54.956811 [Flow] Enable top DCM control >>>>>
3817 05:58:54.960354 [Flow] Enable top DCM control <<<<<
3818 05:58:54.963181 Enable DLL master slave shuffle
3819 05:58:54.967085 ==============================================================
3820 05:58:54.970438 Gating Mode config
3821 05:58:54.976864 ==============================================================
3822 05:58:54.977292 Config description:
3823 05:58:54.986619 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3824 05:58:54.993494 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3825 05:58:54.996963 SELPH_MODE 0: By rank 1: By Phase
3826 05:58:55.003341 ==============================================================
3827 05:58:55.006884 GAT_TRACK_EN = 1
3828 05:58:55.010175 RX_GATING_MODE = 2
3829 05:58:55.013604 RX_GATING_TRACK_MODE = 2
3830 05:58:55.016429 SELPH_MODE = 1
3831 05:58:55.019837 PICG_EARLY_EN = 1
3832 05:58:55.023565 VALID_LAT_VALUE = 1
3833 05:58:55.027144 ==============================================================
3834 05:58:55.029662 Enter into Gating configuration >>>>
3835 05:58:55.033085 Exit from Gating configuration <<<<
3836 05:58:55.036521 Enter into DVFS_PRE_config >>>>>
3837 05:58:55.046695 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3838 05:58:55.049640 Exit from DVFS_PRE_config <<<<<
3839 05:58:55.052787 Enter into PICG configuration >>>>
3840 05:58:55.056635 Exit from PICG configuration <<<<
3841 05:58:55.059686 [RX_INPUT] configuration >>>>>
3842 05:58:55.062757 [RX_INPUT] configuration <<<<<
3843 05:58:55.069280 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3844 05:58:55.073148 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3845 05:58:55.079373 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3846 05:58:55.086077 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3847 05:58:55.092966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 05:58:55.099615 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 05:58:55.103244 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3850 05:58:55.106124 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3851 05:58:55.109619 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3852 05:58:55.116494 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3853 05:58:55.119256 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3854 05:58:55.122881 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3855 05:58:55.126473 ===================================
3856 05:58:55.129408 LPDDR4 DRAM CONFIGURATION
3857 05:58:55.132925 ===================================
3858 05:58:55.133044 EX_ROW_EN[0] = 0x0
3859 05:58:55.136421 EX_ROW_EN[1] = 0x0
3860 05:58:55.136540 LP4Y_EN = 0x0
3861 05:58:55.139293 WORK_FSP = 0x0
3862 05:58:55.139454 WL = 0x2
3863 05:58:55.142645 RL = 0x2
3864 05:58:55.146256 BL = 0x2
3865 05:58:55.146403 RPST = 0x0
3866 05:58:55.149884 RD_PRE = 0x0
3867 05:58:55.150051 WR_PRE = 0x1
3868 05:58:55.152801 WR_PST = 0x0
3869 05:58:55.152995 DBI_WR = 0x0
3870 05:58:55.156142 DBI_RD = 0x0
3871 05:58:55.156350 OTF = 0x1
3872 05:58:55.159727 ===================================
3873 05:58:55.162904 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3874 05:58:55.169772 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3875 05:58:55.173037 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3876 05:58:55.176417 ===================================
3877 05:58:55.179899 LPDDR4 DRAM CONFIGURATION
3878 05:58:55.183024 ===================================
3879 05:58:55.183587 EX_ROW_EN[0] = 0x10
3880 05:58:55.186217 EX_ROW_EN[1] = 0x0
3881 05:58:55.186804 LP4Y_EN = 0x0
3882 05:58:55.189779 WORK_FSP = 0x0
3883 05:58:55.190308 WL = 0x2
3884 05:58:55.193175 RL = 0x2
3885 05:58:55.193764 BL = 0x2
3886 05:58:55.196498 RPST = 0x0
3887 05:58:55.197082 RD_PRE = 0x0
3888 05:58:55.199549 WR_PRE = 0x1
3889 05:58:55.200054 WR_PST = 0x0
3890 05:58:55.202676 DBI_WR = 0x0
3891 05:58:55.203255 DBI_RD = 0x0
3892 05:58:55.206630 OTF = 0x1
3893 05:58:55.209895 ===================================
3894 05:58:55.216093 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3895 05:58:55.219683 nWR fixed to 30
3896 05:58:55.223238 [ModeRegInit_LP4] CH0 RK0
3897 05:58:55.223787 [ModeRegInit_LP4] CH0 RK1
3898 05:58:55.226261 [ModeRegInit_LP4] CH1 RK0
3899 05:58:55.229990 [ModeRegInit_LP4] CH1 RK1
3900 05:58:55.230409 match AC timing 17
3901 05:58:55.236450 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3902 05:58:55.239357 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3903 05:58:55.243100 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3904 05:58:55.249584 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3905 05:58:55.252605 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3906 05:58:55.253025 ==
3907 05:58:55.256392 Dram Type= 6, Freq= 0, CH_0, rank 0
3908 05:58:55.259275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3909 05:58:55.259710 ==
3910 05:58:55.266501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3911 05:58:55.272659 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3912 05:58:55.276035 [CA 0] Center 36 (5~67) winsize 63
3913 05:58:55.279444 [CA 1] Center 36 (5~67) winsize 63
3914 05:58:55.283125 [CA 2] Center 33 (3~64) winsize 62
3915 05:58:55.286035 [CA 3] Center 33 (2~64) winsize 63
3916 05:58:55.289726 [CA 4] Center 33 (2~64) winsize 63
3917 05:58:55.292412 [CA 5] Center 32 (2~63) winsize 62
3918 05:58:55.292833
3919 05:58:55.296163 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3920 05:58:55.296631
3921 05:58:55.299646 [CATrainingPosCal] consider 1 rank data
3922 05:58:55.302987 u2DelayCellTimex100 = 270/100 ps
3923 05:58:55.305914 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3924 05:58:55.309226 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3925 05:58:55.312498 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3926 05:58:55.315754 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3927 05:58:55.319638 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3928 05:58:55.322746 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3929 05:58:55.325696
3930 05:58:55.329092 CA PerBit enable=1, Macro0, CA PI delay=32
3931 05:58:55.329635
3932 05:58:55.332778 [CBTSetCACLKResult] CA Dly = 32
3933 05:58:55.333193 CS Dly: 4 (0~35)
3934 05:58:55.333527 ==
3935 05:58:55.336057 Dram Type= 6, Freq= 0, CH_0, rank 1
3936 05:58:55.339573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3937 05:58:55.340002 ==
3938 05:58:55.346189 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3939 05:58:55.352819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3940 05:58:55.355697 [CA 0] Center 35 (5~66) winsize 62
3941 05:58:55.359348 [CA 1] Center 35 (5~66) winsize 62
3942 05:58:55.362926 [CA 2] Center 34 (3~65) winsize 63
3943 05:58:55.365657 [CA 3] Center 33 (3~64) winsize 62
3944 05:58:55.369218 [CA 4] Center 33 (2~64) winsize 63
3945 05:58:55.372890 [CA 5] Center 32 (2~63) winsize 62
3946 05:58:55.373305
3947 05:58:55.375590 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3948 05:58:55.376005
3949 05:58:55.378840 [CATrainingPosCal] consider 2 rank data
3950 05:58:55.382245 u2DelayCellTimex100 = 270/100 ps
3951 05:58:55.385569 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3952 05:58:55.388971 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3953 05:58:55.392278 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3954 05:58:55.395753 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3955 05:58:55.402154 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3956 05:58:55.405622 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3957 05:58:55.406038
3958 05:58:55.409217 CA PerBit enable=1, Macro0, CA PI delay=32
3959 05:58:55.409633
3960 05:58:55.412521 [CBTSetCACLKResult] CA Dly = 32
3961 05:58:55.413117 CS Dly: 4 (0~36)
3962 05:58:55.413712
3963 05:58:55.415167 ----->DramcWriteLeveling(PI) begin...
3964 05:58:55.415770 ==
3965 05:58:55.418935 Dram Type= 6, Freq= 0, CH_0, rank 0
3966 05:58:55.426089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 05:58:55.426536 ==
3968 05:58:55.429132 Write leveling (Byte 0): 37 => 37
3969 05:58:55.429550 Write leveling (Byte 1): 30 => 30
3970 05:58:55.432657 DramcWriteLeveling(PI) end<-----
3971 05:58:55.433071
3972 05:58:55.433397 ==
3973 05:58:55.435508 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 05:58:55.442355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 05:58:55.442751 ==
3976 05:58:55.445807 [Gating] SW mode calibration
3977 05:58:55.451893 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3978 05:58:55.455410 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3979 05:58:55.461477 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 05:58:55.465117 0 9 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
3981 05:58:55.468214 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 05:58:55.475290 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
3983 05:58:55.478714 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
3984 05:58:55.481920 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 05:58:55.488658 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 05:58:55.491528 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 05:58:55.495200 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 05:58:55.501496 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 05:58:55.504991 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 05:58:55.507943 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
3991 05:58:55.514943 0 10 16 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
3992 05:58:55.518520 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 05:58:55.521242 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 05:58:55.525019 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 05:58:55.531513 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 05:58:55.534504 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 05:58:55.538073 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 05:58:55.544871 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3999 05:58:55.548262 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4000 05:58:55.551368 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 05:58:55.557884 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 05:58:55.561583 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 05:58:55.564500 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 05:58:55.571210 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 05:58:55.574875 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 05:58:55.577623 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 05:58:55.584406 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 05:58:55.587661 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 05:58:55.591377 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 05:58:55.597736 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 05:58:55.601141 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 05:58:55.604788 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 05:58:55.611192 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 05:58:55.614203 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4015 05:58:55.617679 Total UI for P1: 0, mck2ui 16
4016 05:58:55.621142 best dqsien dly found for B0: ( 0, 13, 10)
4017 05:58:55.624161 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4018 05:58:55.630889 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 05:58:55.631016 Total UI for P1: 0, mck2ui 16
4020 05:58:55.637664 best dqsien dly found for B1: ( 0, 13, 16)
4021 05:58:55.641207 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4022 05:58:55.644215 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4023 05:58:55.644328
4024 05:58:55.647886 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4025 05:58:55.650833 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4026 05:58:55.654433 [Gating] SW calibration Done
4027 05:58:55.654520 ==
4028 05:58:55.657757 Dram Type= 6, Freq= 0, CH_0, rank 0
4029 05:58:55.661247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4030 05:58:55.661348 ==
4031 05:58:55.664159 RX Vref Scan: 0
4032 05:58:55.664337
4033 05:58:55.664430 RX Vref 0 -> 0, step: 1
4034 05:58:55.664509
4035 05:58:55.667638 RX Delay -230 -> 252, step: 16
4036 05:58:55.671446 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4037 05:58:55.678015 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4038 05:58:55.680958 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4039 05:58:55.684562 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4040 05:58:55.687395 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4041 05:58:55.694060 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4042 05:58:55.697699 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4043 05:58:55.700653 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4044 05:58:55.703974 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4045 05:58:55.707453 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4046 05:58:55.714515 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4047 05:58:55.717939 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4048 05:58:55.721381 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4049 05:58:55.724273 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4050 05:58:55.731415 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4051 05:58:55.734668 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4052 05:58:55.735085 ==
4053 05:58:55.737908 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 05:58:55.741072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 05:58:55.741602 ==
4056 05:58:55.744032 DQS Delay:
4057 05:58:55.744601 DQS0 = 0, DQS1 = 0
4058 05:58:55.745076 DQM Delay:
4059 05:58:55.747543 DQM0 = 52, DQM1 = 45
4060 05:58:55.747952 DQ Delay:
4061 05:58:55.750902 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4062 05:58:55.754487 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =65
4063 05:58:55.757337 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4064 05:58:55.761025 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4065 05:58:55.761535
4066 05:58:55.761909
4067 05:58:55.762257 ==
4068 05:58:55.764470 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 05:58:55.770958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 05:58:55.771539 ==
4071 05:58:55.771962
4072 05:58:55.772336
4073 05:58:55.772657 TX Vref Scan disable
4074 05:58:55.774447 == TX Byte 0 ==
4075 05:58:55.777947 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4076 05:58:55.784359 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4077 05:58:55.784774 == TX Byte 1 ==
4078 05:58:55.788110 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4079 05:58:55.794627 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4080 05:58:55.795042 ==
4081 05:58:55.798348 Dram Type= 6, Freq= 0, CH_0, rank 0
4082 05:58:55.801103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4083 05:58:55.801523 ==
4084 05:58:55.801852
4085 05:58:55.802159
4086 05:58:55.804638 TX Vref Scan disable
4087 05:58:55.808326 == TX Byte 0 ==
4088 05:58:55.811057 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4089 05:58:55.814583 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4090 05:58:55.818163 == TX Byte 1 ==
4091 05:58:55.821609 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4092 05:58:55.824369 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4093 05:58:55.824781
4094 05:58:55.825103 [DATLAT]
4095 05:58:55.827628 Freq=600, CH0 RK0
4096 05:58:55.828070
4097 05:58:55.831034 DATLAT Default: 0x9
4098 05:58:55.831441 0, 0xFFFF, sum = 0
4099 05:58:55.834670 1, 0xFFFF, sum = 0
4100 05:58:55.835084 2, 0xFFFF, sum = 0
4101 05:58:55.837587 3, 0xFFFF, sum = 0
4102 05:58:55.838001 4, 0xFFFF, sum = 0
4103 05:58:55.841395 5, 0xFFFF, sum = 0
4104 05:58:55.841811 6, 0xFFFF, sum = 0
4105 05:58:55.844252 7, 0xFFFF, sum = 0
4106 05:58:55.844712 8, 0x0, sum = 1
4107 05:58:55.847891 9, 0x0, sum = 2
4108 05:58:55.848346 10, 0x0, sum = 3
4109 05:58:55.848857 11, 0x0, sum = 4
4110 05:58:55.850719 best_step = 9
4111 05:58:55.851130
4112 05:58:55.851458 ==
4113 05:58:55.854259 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 05:58:55.857779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 05:58:55.858196 ==
4116 05:58:55.860681 RX Vref Scan: 1
4117 05:58:55.861107
4118 05:58:55.864212 RX Vref 0 -> 0, step: 1
4119 05:58:55.864665
4120 05:58:55.864992 RX Delay -163 -> 252, step: 8
4121 05:58:55.865293
4122 05:58:55.867437 Set Vref, RX VrefLevel [Byte0]: 58
4123 05:58:55.870970 [Byte1]: 49
4124 05:58:55.875539
4125 05:58:55.875958 Final RX Vref Byte 0 = 58 to rank0
4126 05:58:55.878605 Final RX Vref Byte 1 = 49 to rank0
4127 05:58:55.881783 Final RX Vref Byte 0 = 58 to rank1
4128 05:58:55.885217 Final RX Vref Byte 1 = 49 to rank1==
4129 05:58:55.888362 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 05:58:55.894802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 05:58:55.895214 ==
4132 05:58:55.895539 DQS Delay:
4133 05:58:55.898148 DQS0 = 0, DQS1 = 0
4134 05:58:55.898558 DQM Delay:
4135 05:58:55.898883 DQM0 = 54, DQM1 = 46
4136 05:58:55.901758 DQ Delay:
4137 05:58:55.904763 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4138 05:58:55.908556 DQ4 =56, DQ5 =44, DQ6 =64, DQ7 =60
4139 05:58:55.911499 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4140 05:58:55.914920 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4141 05:58:55.915331
4142 05:58:55.915655
4143 05:58:55.921960 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f63, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4144 05:58:55.925548 CH0 RK0: MR19=808, MR18=6F63
4145 05:58:55.932065 CH0_RK0: MR19=0x808, MR18=0x6F63, DQSOSC=389, MR23=63, INC=173, DEC=115
4146 05:58:55.932642
4147 05:58:55.934781 ----->DramcWriteLeveling(PI) begin...
4148 05:58:55.935292 ==
4149 05:58:55.938147 Dram Type= 6, Freq= 0, CH_0, rank 1
4150 05:58:55.941975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 05:58:55.942619 ==
4152 05:58:55.944831 Write leveling (Byte 0): 35 => 35
4153 05:58:55.948402 Write leveling (Byte 1): 31 => 31
4154 05:58:55.952019 DramcWriteLeveling(PI) end<-----
4155 05:58:55.952469
4156 05:58:55.952717 ==
4157 05:58:55.954609 Dram Type= 6, Freq= 0, CH_0, rank 1
4158 05:58:55.958053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 05:58:55.958393 ==
4160 05:58:55.961583 [Gating] SW mode calibration
4161 05:58:55.967919 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4162 05:58:55.974502 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4163 05:58:55.977986 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4164 05:58:55.981561 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 05:58:55.987987 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 05:58:55.990840 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4167 05:58:55.994259 0 9 16 | B1->B0 | 2a2a 2727 | 0 0 | (1 1) (0 0)
4168 05:58:56.001132 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 05:58:56.004572 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 05:58:56.007902 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 05:58:56.014870 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 05:58:56.017987 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 05:58:56.021290 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 05:58:56.028028 0 10 12 | B1->B0 | 2626 2828 | 0 0 | (0 0) (0 0)
4175 05:58:56.031417 0 10 16 | B1->B0 | 3e3e 3a3a | 0 0 | (1 1) (0 0)
4176 05:58:56.034524 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 05:58:56.041328 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 05:58:56.044695 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 05:58:56.048241 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 05:58:56.054993 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 05:58:56.057775 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 05:58:56.061422 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4183 05:58:56.067669 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 05:58:56.071303 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 05:58:56.074807 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 05:58:56.081238 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 05:58:56.084047 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 05:58:56.087666 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 05:58:56.094138 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 05:58:56.097692 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 05:58:56.101146 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 05:58:56.104444 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 05:58:56.110981 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 05:58:56.114653 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 05:58:56.117500 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 05:58:56.124357 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 05:58:56.127921 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 05:58:56.131396 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4199 05:58:56.137950 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 05:58:56.141531 Total UI for P1: 0, mck2ui 16
4201 05:58:56.144521 best dqsien dly found for B0: ( 0, 13, 14)
4202 05:58:56.144939 Total UI for P1: 0, mck2ui 16
4203 05:58:56.151050 best dqsien dly found for B1: ( 0, 13, 12)
4204 05:58:56.154595 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4205 05:58:56.157496 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4206 05:58:56.158061
4207 05:58:56.161221 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4208 05:58:56.164390 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4209 05:58:56.167551 [Gating] SW calibration Done
4210 05:58:56.167915 ==
4211 05:58:56.170629 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 05:58:56.173877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 05:58:56.174149 ==
4214 05:58:56.177417 RX Vref Scan: 0
4215 05:58:56.177683
4216 05:58:56.177938 RX Vref 0 -> 0, step: 1
4217 05:58:56.180919
4218 05:58:56.181108 RX Delay -230 -> 252, step: 16
4219 05:58:56.187256 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4220 05:58:56.190767 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4221 05:58:56.193850 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4222 05:58:56.197219 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4223 05:58:56.203814 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4224 05:58:56.207245 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4225 05:58:56.210775 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4226 05:58:56.213935 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4227 05:58:56.217390 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4228 05:58:56.223685 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4229 05:58:56.227017 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4230 05:58:56.230451 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4231 05:58:56.234006 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4232 05:58:56.240481 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4233 05:58:56.244088 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4234 05:58:56.247629 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4235 05:58:56.247773 ==
4236 05:58:56.250455 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 05:58:56.253926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 05:58:56.254061 ==
4239 05:58:56.257449 DQS Delay:
4240 05:58:56.257558 DQS0 = 0, DQS1 = 0
4241 05:58:56.260060 DQM Delay:
4242 05:58:56.260173 DQM0 = 51, DQM1 = 43
4243 05:58:56.260261 DQ Delay:
4244 05:58:56.263594 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4245 05:58:56.267041 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4246 05:58:56.270371 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4247 05:58:56.273551 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4248 05:58:56.273648
4249 05:58:56.273720
4250 05:58:56.277242 ==
4251 05:58:56.280304 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 05:58:56.284000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 05:58:56.284148 ==
4254 05:58:56.284223
4255 05:58:56.284300
4256 05:58:56.286778 TX Vref Scan disable
4257 05:58:56.286874 == TX Byte 0 ==
4258 05:58:56.293594 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4259 05:58:56.297328 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4260 05:58:56.297426 == TX Byte 1 ==
4261 05:58:56.303304 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4262 05:58:56.306658 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4263 05:58:56.306759 ==
4264 05:58:56.310414 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 05:58:56.314046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 05:58:56.314139 ==
4267 05:58:56.314210
4268 05:58:56.314274
4269 05:58:56.316863 TX Vref Scan disable
4270 05:58:56.320196 == TX Byte 0 ==
4271 05:58:56.323536 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4272 05:58:56.327533 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4273 05:58:56.330407 == TX Byte 1 ==
4274 05:58:56.334075 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4275 05:58:56.337371 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4276 05:58:56.337790
4277 05:58:56.340753 [DATLAT]
4278 05:58:56.341165 Freq=600, CH0 RK1
4279 05:58:56.341496
4280 05:58:56.344146 DATLAT Default: 0x9
4281 05:58:56.344708 0, 0xFFFF, sum = 0
4282 05:58:56.347190 1, 0xFFFF, sum = 0
4283 05:58:56.347608 2, 0xFFFF, sum = 0
4284 05:58:56.350621 3, 0xFFFF, sum = 0
4285 05:58:56.351041 4, 0xFFFF, sum = 0
4286 05:58:56.353482 5, 0xFFFF, sum = 0
4287 05:58:56.353905 6, 0xFFFF, sum = 0
4288 05:58:56.356972 7, 0xFFFF, sum = 0
4289 05:58:56.357408 8, 0x0, sum = 1
4290 05:58:56.360730 9, 0x0, sum = 2
4291 05:58:56.361187 10, 0x0, sum = 3
4292 05:58:56.363530 11, 0x0, sum = 4
4293 05:58:56.363948 best_step = 9
4294 05:58:56.364277
4295 05:58:56.364647 ==
4296 05:58:56.366771 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 05:58:56.373849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 05:58:56.374266 ==
4299 05:58:56.374594 RX Vref Scan: 0
4300 05:58:56.374896
4301 05:58:56.376627 RX Vref 0 -> 0, step: 1
4302 05:58:56.377198
4303 05:58:56.380368 RX Delay -163 -> 252, step: 8
4304 05:58:56.383366 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4305 05:58:56.386714 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4306 05:58:56.393463 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4307 05:58:56.396915 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4308 05:58:56.400364 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4309 05:58:56.403730 iDelay=205, Bit 5, Center 48 (-91 ~ 188) 280
4310 05:58:56.406877 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4311 05:58:56.413453 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4312 05:58:56.416431 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4313 05:58:56.420029 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4314 05:58:56.423225 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4315 05:58:56.426882 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4316 05:58:56.433372 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4317 05:58:56.436791 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4318 05:58:56.439628 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4319 05:58:56.443279 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4320 05:58:56.443694 ==
4321 05:58:56.446761 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 05:58:56.453141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 05:58:56.453669 ==
4324 05:58:56.454029 DQS Delay:
4325 05:58:56.456098 DQS0 = 0, DQS1 = 0
4326 05:58:56.456647 DQM Delay:
4327 05:58:56.459993 DQM0 = 54, DQM1 = 46
4328 05:58:56.460556 DQ Delay:
4329 05:58:56.462956 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4330 05:58:56.466692 DQ4 =52, DQ5 =48, DQ6 =56, DQ7 =64
4331 05:58:56.469657 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =36
4332 05:58:56.473424 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4333 05:58:56.473842
4334 05:58:56.474168
4335 05:58:56.479338 [DQSOSCAuto] RK1, (LSB)MR18= 0x6526, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4336 05:58:56.482770 CH0 RK1: MR19=808, MR18=6526
4337 05:58:56.489587 CH0_RK1: MR19=0x808, MR18=0x6526, DQSOSC=390, MR23=63, INC=172, DEC=114
4338 05:58:56.493295 [RxdqsGatingPostProcess] freq 600
4339 05:58:56.496024 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4340 05:58:56.499663 Pre-setting of DQS Precalculation
4341 05:58:56.506235 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4342 05:58:56.506917 ==
4343 05:58:56.509807 Dram Type= 6, Freq= 0, CH_1, rank 0
4344 05:58:56.513066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 05:58:56.513645 ==
4346 05:58:56.519564 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4347 05:58:56.526167 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4348 05:58:56.528970 [CA 0] Center 36 (5~67) winsize 63
4349 05:58:56.532256 [CA 1] Center 36 (5~67) winsize 63
4350 05:58:56.535730 [CA 2] Center 34 (4~65) winsize 62
4351 05:58:56.539072 [CA 3] Center 34 (4~65) winsize 62
4352 05:58:56.542343 [CA 4] Center 34 (4~65) winsize 62
4353 05:58:56.546082 [CA 5] Center 33 (3~64) winsize 62
4354 05:58:56.546197
4355 05:58:56.549051 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4356 05:58:56.549182
4357 05:58:56.552662 [CATrainingPosCal] consider 1 rank data
4358 05:58:56.555647 u2DelayCellTimex100 = 270/100 ps
4359 05:58:56.558989 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4360 05:58:56.562301 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4361 05:58:56.565952 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4362 05:58:56.568851 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4363 05:58:56.572370 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4364 05:58:56.575807 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4365 05:58:56.575888
4366 05:58:56.579220 CA PerBit enable=1, Macro0, CA PI delay=33
4367 05:58:56.582748
4368 05:58:56.582828 [CBTSetCACLKResult] CA Dly = 33
4369 05:58:56.585535 CS Dly: 5 (0~36)
4370 05:58:56.585652 ==
4371 05:58:56.588709 Dram Type= 6, Freq= 0, CH_1, rank 1
4372 05:58:56.592181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 05:58:56.592263 ==
4374 05:58:56.599462 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4375 05:58:56.605948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4376 05:58:56.608891 [CA 0] Center 36 (5~67) winsize 63
4377 05:58:56.612130 [CA 1] Center 36 (5~67) winsize 63
4378 05:58:56.615792 [CA 2] Center 34 (4~65) winsize 62
4379 05:58:56.619270 [CA 3] Center 34 (4~65) winsize 62
4380 05:58:56.622860 [CA 4] Center 35 (4~66) winsize 63
4381 05:58:56.625560 [CA 5] Center 34 (4~65) winsize 62
4382 05:58:56.625642
4383 05:58:56.629154 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4384 05:58:56.629264
4385 05:58:56.632670 [CATrainingPosCal] consider 2 rank data
4386 05:58:56.635312 u2DelayCellTimex100 = 270/100 ps
4387 05:58:56.638626 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4388 05:58:56.642089 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4389 05:58:56.645627 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 05:58:56.649141 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4391 05:58:56.652416 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4392 05:58:56.655784 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4393 05:58:56.655886
4394 05:58:56.662334 CA PerBit enable=1, Macro0, CA PI delay=34
4395 05:58:56.662519
4396 05:58:56.662609 [CBTSetCACLKResult] CA Dly = 34
4397 05:58:56.665440 CS Dly: 6 (0~38)
4398 05:58:56.665586
4399 05:58:56.669511 ----->DramcWriteLeveling(PI) begin...
4400 05:58:56.669703 ==
4401 05:58:56.672506 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 05:58:56.676113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 05:58:56.676333 ==
4404 05:58:56.678859 Write leveling (Byte 0): 29 => 29
4405 05:58:56.682139 Write leveling (Byte 1): 33 => 33
4406 05:58:56.685917 DramcWriteLeveling(PI) end<-----
4407 05:58:56.686161
4408 05:58:56.686345 ==
4409 05:58:56.689185 Dram Type= 6, Freq= 0, CH_1, rank 0
4410 05:58:56.695833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 05:58:56.696123 ==
4412 05:58:56.696396 [Gating] SW mode calibration
4413 05:58:56.705815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4414 05:58:56.709076 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4415 05:58:56.712585 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4416 05:58:56.719442 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 05:58:56.722168 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4418 05:58:56.725782 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 1)
4419 05:58:56.732658 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4420 05:58:56.736035 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 05:58:56.739083 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 05:58:56.745858 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 05:58:56.749025 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 05:58:56.752498 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 05:58:56.758927 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4426 05:58:56.761986 0 10 12 | B1->B0 | 3535 3737 | 0 0 | (1 1) (0 0)
4427 05:58:56.765776 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 05:58:56.772482 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 05:58:56.775671 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 05:58:56.778683 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 05:58:56.785697 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 05:58:56.789193 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 05:58:56.791992 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4434 05:58:56.798329 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4435 05:58:56.802049 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 05:58:56.805092 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 05:58:56.812447 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 05:58:56.815289 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 05:58:56.818650 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 05:58:56.821823 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 05:58:56.828872 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 05:58:56.831901 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 05:58:56.835022 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 05:58:56.841981 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 05:58:56.845499 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 05:58:56.848258 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 05:58:56.855467 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 05:58:56.858622 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 05:58:56.862069 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 05:58:56.868088 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4451 05:58:56.868334 Total UI for P1: 0, mck2ui 16
4452 05:58:56.874987 best dqsien dly found for B0: ( 0, 13, 10)
4453 05:58:56.878426 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4454 05:58:56.881838 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 05:58:56.884691 Total UI for P1: 0, mck2ui 16
4456 05:58:56.888101 best dqsien dly found for B1: ( 0, 13, 14)
4457 05:58:56.891507 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4458 05:58:56.895180 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4459 05:58:56.895283
4460 05:58:56.901337 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4461 05:58:56.904845 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4462 05:58:56.904930 [Gating] SW calibration Done
4463 05:58:56.908239 ==
4464 05:58:56.911779 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 05:58:56.914559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 05:58:56.914718 ==
4467 05:58:56.914800 RX Vref Scan: 0
4468 05:58:56.914860
4469 05:58:56.918027 RX Vref 0 -> 0, step: 1
4470 05:58:56.918218
4471 05:58:56.921351 RX Delay -230 -> 252, step: 16
4472 05:58:56.924712 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4473 05:58:56.928150 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4474 05:58:56.934905 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4475 05:58:56.938076 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4476 05:58:56.941233 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4477 05:58:56.944519 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4478 05:58:56.951382 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4479 05:58:56.955151 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4480 05:58:56.958092 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4481 05:58:56.961277 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4482 05:58:56.964535 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4483 05:58:56.971103 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4484 05:58:56.974746 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4485 05:58:56.977581 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4486 05:58:56.981019 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4487 05:58:56.987684 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4488 05:58:56.987834 ==
4489 05:58:56.991326 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 05:58:56.994215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 05:58:56.994324 ==
4492 05:58:56.994411 DQS Delay:
4493 05:58:56.997625 DQS0 = 0, DQS1 = 0
4494 05:58:56.997745 DQM Delay:
4495 05:58:57.001187 DQM0 = 50, DQM1 = 46
4496 05:58:57.001383 DQ Delay:
4497 05:58:57.004874 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4498 05:58:57.008180 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4499 05:58:57.011161 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4500 05:58:57.014412 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4501 05:58:57.014618
4502 05:58:57.014753
4503 05:58:57.014878 ==
4504 05:58:57.017932 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 05:58:57.021373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 05:58:57.021602 ==
4507 05:58:57.024082
4508 05:58:57.024327
4509 05:58:57.024562 TX Vref Scan disable
4510 05:58:57.027469 == TX Byte 0 ==
4511 05:58:57.031402 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4512 05:58:57.034071 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4513 05:58:57.037730 == TX Byte 1 ==
4514 05:58:57.041024 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4515 05:58:57.044524 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4516 05:58:57.044745 ==
4517 05:58:57.047985 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 05:58:57.054340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 05:58:57.054542 ==
4520 05:58:57.054702
4521 05:58:57.054849
4522 05:58:57.057800 TX Vref Scan disable
4523 05:58:57.057998 == TX Byte 0 ==
4524 05:58:57.064130 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4525 05:58:57.067770 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4526 05:58:57.068185 == TX Byte 1 ==
4527 05:58:57.074725 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4528 05:58:57.077923 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4529 05:58:57.078342
4530 05:58:57.078669 [DATLAT]
4531 05:58:57.080919 Freq=600, CH1 RK0
4532 05:58:57.081440
4533 05:58:57.081929 DATLAT Default: 0x9
4534 05:58:57.084013 0, 0xFFFF, sum = 0
4535 05:58:57.084477 1, 0xFFFF, sum = 0
4536 05:58:57.087535 2, 0xFFFF, sum = 0
4537 05:58:57.087954 3, 0xFFFF, sum = 0
4538 05:58:57.091061 4, 0xFFFF, sum = 0
4539 05:58:57.091483 5, 0xFFFF, sum = 0
4540 05:58:57.094734 6, 0xFFFF, sum = 0
4541 05:58:57.097913 7, 0xFFFF, sum = 0
4542 05:58:57.098327 8, 0x0, sum = 1
4543 05:58:57.098655 9, 0x0, sum = 2
4544 05:58:57.100959 10, 0x0, sum = 3
4545 05:58:57.101374 11, 0x0, sum = 4
4546 05:58:57.104201 best_step = 9
4547 05:58:57.104647
4548 05:58:57.104967 ==
4549 05:58:57.107764 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 05:58:57.110862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 05:58:57.111472 ==
4552 05:58:57.114438 RX Vref Scan: 1
4553 05:58:57.115018
4554 05:58:57.115548 RX Vref 0 -> 0, step: 1
4555 05:58:57.116057
4556 05:58:57.117648 RX Delay -163 -> 252, step: 8
4557 05:58:57.118206
4558 05:58:57.121303 Set Vref, RX VrefLevel [Byte0]: 56
4559 05:58:57.124030 [Byte1]: 49
4560 05:58:57.127825
4561 05:58:57.128423 Final RX Vref Byte 0 = 56 to rank0
4562 05:58:57.131468 Final RX Vref Byte 1 = 49 to rank0
4563 05:58:57.134656 Final RX Vref Byte 0 = 56 to rank1
4564 05:58:57.137462 Final RX Vref Byte 1 = 49 to rank1==
4565 05:58:57.140950 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 05:58:57.147692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 05:58:57.147987 ==
4568 05:58:57.148243 DQS Delay:
4569 05:58:57.148490 DQS0 = 0, DQS1 = 0
4570 05:58:57.150633 DQM Delay:
4571 05:58:57.150780 DQM0 = 48, DQM1 = 46
4572 05:58:57.154133 DQ Delay:
4573 05:58:57.157679 DQ0 =48, DQ1 =40, DQ2 =40, DQ3 =48
4574 05:58:57.157791 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4575 05:58:57.160544 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =40
4576 05:58:57.167261 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =60
4577 05:58:57.167351
4578 05:58:57.167422
4579 05:58:57.174174 [DQSOSCAuto] RK0, (LSB)MR18= 0x446a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4580 05:58:57.177764 CH1 RK0: MR19=808, MR18=446A
4581 05:58:57.184106 CH1_RK0: MR19=0x808, MR18=0x446A, DQSOSC=389, MR23=63, INC=173, DEC=115
4582 05:58:57.184216
4583 05:58:57.187136 ----->DramcWriteLeveling(PI) begin...
4584 05:58:57.187231 ==
4585 05:58:57.190677 Dram Type= 6, Freq= 0, CH_1, rank 1
4586 05:58:57.194021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 05:58:57.194103 ==
4588 05:58:57.197630 Write leveling (Byte 0): 29 => 29
4589 05:58:57.200999 Write leveling (Byte 1): 30 => 30
4590 05:58:57.204475 DramcWriteLeveling(PI) end<-----
4591 05:58:57.204556
4592 05:58:57.204619 ==
4593 05:58:57.207152 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 05:58:57.210649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 05:58:57.210775 ==
4596 05:58:57.214199 [Gating] SW mode calibration
4597 05:58:57.220746 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4598 05:58:57.227646 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4599 05:58:57.230613 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4600 05:58:57.234312 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 05:58:57.240973 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4602 05:58:57.244797 0 9 12 | B1->B0 | 2e2e 3131 | 0 1 | (0 0) (0 0)
4603 05:58:57.247719 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 05:58:57.254676 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 05:58:57.257972 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 05:58:57.260903 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 05:58:57.268117 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 05:58:57.270771 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 05:58:57.274671 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4610 05:58:57.281211 0 10 12 | B1->B0 | 3939 3636 | 0 0 | (0 0) (0 0)
4611 05:58:57.284767 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 05:58:57.287433 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 05:58:57.294124 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 05:58:57.297528 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 05:58:57.300875 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 05:58:57.307119 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 05:58:57.310594 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 05:58:57.314327 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4619 05:58:57.320748 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 05:58:57.324065 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 05:58:57.327405 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 05:58:57.333846 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 05:58:57.337186 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 05:58:57.340687 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 05:58:57.347399 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 05:58:57.350520 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 05:58:57.353918 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 05:58:57.360745 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 05:58:57.363641 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 05:58:57.367226 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 05:58:57.370521 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 05:58:57.377164 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 05:58:57.380592 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 05:58:57.383810 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4635 05:58:57.390031 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 05:58:57.393788 Total UI for P1: 0, mck2ui 16
4637 05:58:57.396834 best dqsien dly found for B0: ( 0, 13, 12)
4638 05:58:57.400196 Total UI for P1: 0, mck2ui 16
4639 05:58:57.403646 best dqsien dly found for B1: ( 0, 13, 12)
4640 05:58:57.406893 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4641 05:58:57.410403 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4642 05:58:57.410637
4643 05:58:57.412989 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4644 05:58:57.416415 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4645 05:58:57.419373 [Gating] SW calibration Done
4646 05:58:57.419541 ==
4647 05:58:57.422829 Dram Type= 6, Freq= 0, CH_1, rank 1
4648 05:58:57.426703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 05:58:57.426817 ==
4650 05:58:57.429377 RX Vref Scan: 0
4651 05:58:57.429513
4652 05:58:57.432890 RX Vref 0 -> 0, step: 1
4653 05:58:57.432980
4654 05:58:57.433052 RX Delay -230 -> 252, step: 16
4655 05:58:57.440004 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4656 05:58:57.442761 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4657 05:58:57.446156 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4658 05:58:57.449602 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4659 05:58:57.456033 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4660 05:58:57.459367 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4661 05:58:57.462807 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4662 05:58:57.466474 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4663 05:58:57.469522 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4664 05:58:57.476496 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4665 05:58:57.479535 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4666 05:58:57.482953 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4667 05:58:57.486065 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4668 05:58:57.493140 iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304
4669 05:58:57.496390 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4670 05:58:57.499984 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4671 05:58:57.500565 ==
4672 05:58:57.503092 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 05:58:57.506614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 05:58:57.507192 ==
4675 05:58:57.509677 DQS Delay:
4676 05:58:57.510223 DQS0 = 0, DQS1 = 0
4677 05:58:57.512990 DQM Delay:
4678 05:58:57.513491 DQM0 = 48, DQM1 = 50
4679 05:58:57.513947 DQ Delay:
4680 05:58:57.516381 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4681 05:58:57.519871 DQ4 =41, DQ5 =65, DQ6 =65, DQ7 =41
4682 05:58:57.523361 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4683 05:58:57.526258 DQ12 =65, DQ13 =65, DQ14 =57, DQ15 =65
4684 05:58:57.526781
4685 05:58:57.527113
4686 05:58:57.529630 ==
4687 05:58:57.530111 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 05:58:57.536277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 05:58:57.536825 ==
4690 05:58:57.537162
4691 05:58:57.537476
4692 05:58:57.539705 TX Vref Scan disable
4693 05:58:57.540117 == TX Byte 0 ==
4694 05:58:57.543194 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4695 05:58:57.549530 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4696 05:58:57.549945 == TX Byte 1 ==
4697 05:58:57.552825 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4698 05:58:57.559656 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4699 05:58:57.560178 ==
4700 05:58:57.563261 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 05:58:57.566788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 05:58:57.567313 ==
4703 05:58:57.567647
4704 05:58:57.567950
4705 05:58:57.569305 TX Vref Scan disable
4706 05:58:57.573026 == TX Byte 0 ==
4707 05:58:57.576576 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4708 05:58:57.579788 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4709 05:58:57.582559 == TX Byte 1 ==
4710 05:58:57.586020 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4711 05:58:57.589253 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4712 05:58:57.589671
4713 05:58:57.592736 [DATLAT]
4714 05:58:57.593145 Freq=600, CH1 RK1
4715 05:58:57.593476
4716 05:58:57.596460 DATLAT Default: 0x9
4717 05:58:57.596978 0, 0xFFFF, sum = 0
4718 05:58:57.599689 1, 0xFFFF, sum = 0
4719 05:58:57.600112 2, 0xFFFF, sum = 0
4720 05:58:57.602620 3, 0xFFFF, sum = 0
4721 05:58:57.603038 4, 0xFFFF, sum = 0
4722 05:58:57.605796 5, 0xFFFF, sum = 0
4723 05:58:57.606215 6, 0xFFFF, sum = 0
4724 05:58:57.609192 7, 0xFFFF, sum = 0
4725 05:58:57.609606 8, 0x0, sum = 1
4726 05:58:57.612571 9, 0x0, sum = 2
4727 05:58:57.612996 10, 0x0, sum = 3
4728 05:58:57.615707 11, 0x0, sum = 4
4729 05:58:57.616128 best_step = 9
4730 05:58:57.616516
4731 05:58:57.616827 ==
4732 05:58:57.619227 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 05:58:57.622619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 05:58:57.623098 ==
4735 05:58:57.625899 RX Vref Scan: 0
4736 05:58:57.626309
4737 05:58:57.629193 RX Vref 0 -> 0, step: 1
4738 05:58:57.629608
4739 05:58:57.629937 RX Delay -163 -> 252, step: 8
4740 05:58:57.637489 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4741 05:58:57.641038 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4742 05:58:57.643511 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4743 05:58:57.647064 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4744 05:58:57.653932 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4745 05:58:57.657521 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4746 05:58:57.660108 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4747 05:58:57.663306 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4748 05:58:57.666689 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4749 05:58:57.673636 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4750 05:58:57.677063 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4751 05:58:57.679822 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4752 05:58:57.683174 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4753 05:58:57.686735 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4754 05:58:57.693860 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4755 05:58:57.697397 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4756 05:58:57.697655 ==
4757 05:58:57.700267 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 05:58:57.703699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 05:58:57.703960 ==
4760 05:58:57.706487 DQS Delay:
4761 05:58:57.706748 DQS0 = 0, DQS1 = 0
4762 05:58:57.706899 DQM Delay:
4763 05:58:57.710721 DQM0 = 48, DQM1 = 45
4764 05:58:57.710985 DQ Delay:
4765 05:58:57.713524 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4766 05:58:57.716808 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4767 05:58:57.720605 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4768 05:58:57.723790 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4769 05:58:57.724163
4770 05:58:57.724468
4771 05:58:57.733926 [DQSOSCAuto] RK1, (LSB)MR18= 0x641a, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4772 05:58:57.734449 CH1 RK1: MR19=808, MR18=641A
4773 05:58:57.740524 CH1_RK1: MR19=0x808, MR18=0x641A, DQSOSC=391, MR23=63, INC=171, DEC=114
4774 05:58:57.743628 [RxdqsGatingPostProcess] freq 600
4775 05:58:57.750012 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4776 05:58:57.753675 Pre-setting of DQS Precalculation
4777 05:58:57.756893 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4778 05:58:57.763430 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4779 05:58:57.773369 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4780 05:58:57.773828
4781 05:58:57.774296
4782 05:58:57.776674 [Calibration Summary] 1200 Mbps
4783 05:58:57.777131 CH 0, Rank 0
4784 05:58:57.779966 SW Impedance : PASS
4785 05:58:57.780642 DUTY Scan : NO K
4786 05:58:57.783582 ZQ Calibration : PASS
4787 05:58:57.784076 Jitter Meter : NO K
4788 05:58:57.786856 CBT Training : PASS
4789 05:58:57.790337 Write leveling : PASS
4790 05:58:57.790748 RX DQS gating : PASS
4791 05:58:57.793636 RX DQ/DQS(RDDQC) : PASS
4792 05:58:57.796398 TX DQ/DQS : PASS
4793 05:58:57.796827 RX DATLAT : PASS
4794 05:58:57.799920 RX DQ/DQS(Engine): PASS
4795 05:58:57.803205 TX OE : NO K
4796 05:58:57.803510 All Pass.
4797 05:58:57.803818
4798 05:58:57.804107 CH 0, Rank 1
4799 05:58:57.806671 SW Impedance : PASS
4800 05:58:57.809867 DUTY Scan : NO K
4801 05:58:57.810095 ZQ Calibration : PASS
4802 05:58:57.813274 Jitter Meter : NO K
4803 05:58:57.816728 CBT Training : PASS
4804 05:58:57.816913 Write leveling : PASS
4805 05:58:57.820062 RX DQS gating : PASS
4806 05:58:57.823584 RX DQ/DQS(RDDQC) : PASS
4807 05:58:57.823715 TX DQ/DQS : PASS
4808 05:58:57.826402 RX DATLAT : PASS
4809 05:58:57.826533 RX DQ/DQS(Engine): PASS
4810 05:58:57.829793 TX OE : NO K
4811 05:58:57.829908 All Pass.
4812 05:58:57.830026
4813 05:58:57.833348 CH 1, Rank 0
4814 05:58:57.833451 SW Impedance : PASS
4815 05:58:57.836200 DUTY Scan : NO K
4816 05:58:57.839675 ZQ Calibration : PASS
4817 05:58:57.839767 Jitter Meter : NO K
4818 05:58:57.843052 CBT Training : PASS
4819 05:58:57.846430 Write leveling : PASS
4820 05:58:57.846514 RX DQS gating : PASS
4821 05:58:57.849889 RX DQ/DQS(RDDQC) : PASS
4822 05:58:57.853157 TX DQ/DQS : PASS
4823 05:58:57.853240 RX DATLAT : PASS
4824 05:58:57.856435 RX DQ/DQS(Engine): PASS
4825 05:58:57.859676 TX OE : NO K
4826 05:58:57.859757 All Pass.
4827 05:58:57.859820
4828 05:58:57.859878 CH 1, Rank 1
4829 05:58:57.863162 SW Impedance : PASS
4830 05:58:57.866593 DUTY Scan : NO K
4831 05:58:57.866673 ZQ Calibration : PASS
4832 05:58:57.869387 Jitter Meter : NO K
4833 05:58:57.869492 CBT Training : PASS
4834 05:58:57.873139 Write leveling : PASS
4835 05:58:57.876506 RX DQS gating : PASS
4836 05:58:57.876585 RX DQ/DQS(RDDQC) : PASS
4837 05:58:57.879893 TX DQ/DQS : PASS
4838 05:58:57.883613 RX DATLAT : PASS
4839 05:58:57.883951 RX DQ/DQS(Engine): PASS
4840 05:58:57.887231 TX OE : NO K
4841 05:58:57.887639 All Pass.
4842 05:58:57.887932
4843 05:58:57.890140 DramC Write-DBI off
4844 05:58:57.893163 PER_BANK_REFRESH: Hybrid Mode
4845 05:58:57.893490 TX_TRACKING: ON
4846 05:58:57.902878 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4847 05:58:57.906424 [FAST_K] Save calibration result to emmc
4848 05:58:57.910644 dramc_set_vcore_voltage set vcore to 662500
4849 05:58:57.913618 Read voltage for 933, 3
4850 05:58:57.914039 Vio18 = 0
4851 05:58:57.914370 Vcore = 662500
4852 05:58:57.916900 Vdram = 0
4853 05:58:57.917316 Vddq = 0
4854 05:58:57.917644 Vmddr = 0
4855 05:58:57.923139 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4856 05:58:57.926700 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4857 05:58:57.930422 MEM_TYPE=3, freq_sel=17
4858 05:58:57.933228 sv_algorithm_assistance_LP4_1600
4859 05:58:57.936807 ============ PULL DRAM RESETB DOWN ============
4860 05:58:57.939778 ========== PULL DRAM RESETB DOWN end =========
4861 05:58:57.946789 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4862 05:58:57.950064 ===================================
4863 05:58:57.953280 LPDDR4 DRAM CONFIGURATION
4864 05:58:57.956789 ===================================
4865 05:58:57.957322 EX_ROW_EN[0] = 0x0
4866 05:58:57.959976 EX_ROW_EN[1] = 0x0
4867 05:58:57.960445 LP4Y_EN = 0x0
4868 05:58:57.963556 WORK_FSP = 0x0
4869 05:58:57.964091 WL = 0x3
4870 05:58:57.966294 RL = 0x3
4871 05:58:57.966718 BL = 0x2
4872 05:58:57.969886 RPST = 0x0
4873 05:58:57.970468 RD_PRE = 0x0
4874 05:58:57.973277 WR_PRE = 0x1
4875 05:58:57.973715 WR_PST = 0x0
4876 05:58:57.976057 DBI_WR = 0x0
4877 05:58:57.976677 DBI_RD = 0x0
4878 05:58:57.979655 OTF = 0x1
4879 05:58:57.983127 ===================================
4880 05:58:57.986679 ===================================
4881 05:58:57.987294 ANA top config
4882 05:58:57.989282 ===================================
4883 05:58:57.992810 DLL_ASYNC_EN = 0
4884 05:58:57.996267 ALL_SLAVE_EN = 1
4885 05:58:57.999749 NEW_RANK_MODE = 1
4886 05:58:58.000405 DLL_IDLE_MODE = 1
4887 05:58:58.002696 LP45_APHY_COMB_EN = 1
4888 05:58:58.005925 TX_ODT_DIS = 1
4889 05:58:58.009544 NEW_8X_MODE = 1
4890 05:58:58.012932 ===================================
4891 05:58:58.016281 ===================================
4892 05:58:58.019470 data_rate = 1866
4893 05:58:58.022603 CKR = 1
4894 05:58:58.022988 DQ_P2S_RATIO = 8
4895 05:58:58.026231 ===================================
4896 05:58:58.029295 CA_P2S_RATIO = 8
4897 05:58:58.032831 DQ_CA_OPEN = 0
4898 05:58:58.036201 DQ_SEMI_OPEN = 0
4899 05:58:58.038932 CA_SEMI_OPEN = 0
4900 05:58:58.039320 CA_FULL_RATE = 0
4901 05:58:58.042656 DQ_CKDIV4_EN = 1
4902 05:58:58.045636 CA_CKDIV4_EN = 1
4903 05:58:58.049055 CA_PREDIV_EN = 0
4904 05:58:58.052465 PH8_DLY = 0
4905 05:58:58.056004 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4906 05:58:58.056434 DQ_AAMCK_DIV = 4
4907 05:58:58.059304 CA_AAMCK_DIV = 4
4908 05:58:58.062244 CA_ADMCK_DIV = 4
4909 05:58:58.065617 DQ_TRACK_CA_EN = 0
4910 05:58:58.069197 CA_PICK = 933
4911 05:58:58.072356 CA_MCKIO = 933
4912 05:58:58.075440 MCKIO_SEMI = 0
4913 05:58:58.075812 PLL_FREQ = 3732
4914 05:58:58.078722 DQ_UI_PI_RATIO = 32
4915 05:58:58.082471 CA_UI_PI_RATIO = 0
4916 05:58:58.085497 ===================================
4917 05:58:58.089205 ===================================
4918 05:58:58.092377 memory_type:LPDDR4
4919 05:58:58.095882 GP_NUM : 10
4920 05:58:58.096275 SRAM_EN : 1
4921 05:58:58.098735 MD32_EN : 0
4922 05:58:58.102214 ===================================
4923 05:58:58.102503 [ANA_INIT] >>>>>>>>>>>>>>
4924 05:58:58.105638 <<<<<< [CONFIGURE PHASE]: ANA_TX
4925 05:58:58.109012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4926 05:58:58.112364 ===================================
4927 05:58:58.115300 data_rate = 1866,PCW = 0X8f00
4928 05:58:58.118748 ===================================
4929 05:58:58.122239 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4930 05:58:58.128833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4931 05:58:58.131651 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 05:58:58.138337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4933 05:58:58.141889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4934 05:58:58.145390 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4935 05:58:58.148106 [ANA_INIT] flow start
4936 05:58:58.148211 [ANA_INIT] PLL >>>>>>>>
4937 05:58:58.151497 [ANA_INIT] PLL <<<<<<<<
4938 05:58:58.155389 [ANA_INIT] MIDPI >>>>>>>>
4939 05:58:58.155470 [ANA_INIT] MIDPI <<<<<<<<
4940 05:58:58.158481 [ANA_INIT] DLL >>>>>>>>
4941 05:58:58.161532 [ANA_INIT] flow end
4942 05:58:58.165019 ============ LP4 DIFF to SE enter ============
4943 05:58:58.168492 ============ LP4 DIFF to SE exit ============
4944 05:58:58.171550 [ANA_INIT] <<<<<<<<<<<<<
4945 05:58:58.175164 [Flow] Enable top DCM control >>>>>
4946 05:58:58.178484 [Flow] Enable top DCM control <<<<<
4947 05:58:58.181545 Enable DLL master slave shuffle
4948 05:58:58.185043 ==============================================================
4949 05:58:58.188459 Gating Mode config
4950 05:58:58.191834 ==============================================================
4951 05:58:58.194895 Config description:
4952 05:58:58.204752 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4953 05:58:58.211666 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4954 05:58:58.215046 SELPH_MODE 0: By rank 1: By Phase
4955 05:58:58.221479 ==============================================================
4956 05:58:58.225074 GAT_TRACK_EN = 1
4957 05:58:58.228529 RX_GATING_MODE = 2
4958 05:58:58.231962 RX_GATING_TRACK_MODE = 2
4959 05:58:58.234696 SELPH_MODE = 1
4960 05:58:58.238123 PICG_EARLY_EN = 1
4961 05:58:58.241510 VALID_LAT_VALUE = 1
4962 05:58:58.244928 ==============================================================
4963 05:58:58.248527 Enter into Gating configuration >>>>
4964 05:58:58.251327 Exit from Gating configuration <<<<
4965 05:58:58.254962 Enter into DVFS_PRE_config >>>>>
4966 05:58:58.264791 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4967 05:58:58.268103 Exit from DVFS_PRE_config <<<<<
4968 05:58:58.271691 Enter into PICG configuration >>>>
4969 05:58:58.275127 Exit from PICG configuration <<<<
4970 05:58:58.277907 [RX_INPUT] configuration >>>>>
4971 05:58:58.281145 [RX_INPUT] configuration <<<<<
4972 05:58:58.287694 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4973 05:58:58.291185 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4974 05:58:58.297650 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 05:58:58.304666 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 05:58:58.311144 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4977 05:58:58.317832 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4978 05:58:58.320924 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4979 05:58:58.324628 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4980 05:58:58.327679 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4981 05:58:58.334600 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4982 05:58:58.338080 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4983 05:58:58.340917 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4984 05:58:58.344376 ===================================
4985 05:58:58.347635 LPDDR4 DRAM CONFIGURATION
4986 05:58:58.351199 ===================================
4987 05:58:58.351296 EX_ROW_EN[0] = 0x0
4988 05:58:58.354722 EX_ROW_EN[1] = 0x0
4989 05:58:58.354818 LP4Y_EN = 0x0
4990 05:58:58.357508 WORK_FSP = 0x0
4991 05:58:58.357583 WL = 0x3
4992 05:58:58.361224 RL = 0x3
4993 05:58:58.364767 BL = 0x2
4994 05:58:58.364869 RPST = 0x0
4995 05:58:58.367749 RD_PRE = 0x0
4996 05:58:58.367819 WR_PRE = 0x1
4997 05:58:58.371231 WR_PST = 0x0
4998 05:58:58.371325 DBI_WR = 0x0
4999 05:58:58.374708 DBI_RD = 0x0
5000 05:58:58.374800 OTF = 0x1
5001 05:58:58.377502 ===================================
5002 05:58:58.381077 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5003 05:58:58.387938 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5004 05:58:58.390755 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5005 05:58:58.394124 ===================================
5006 05:58:58.397469 LPDDR4 DRAM CONFIGURATION
5007 05:58:58.400787 ===================================
5008 05:58:58.400878 EX_ROW_EN[0] = 0x10
5009 05:58:58.404230 EX_ROW_EN[1] = 0x0
5010 05:58:58.404336 LP4Y_EN = 0x0
5011 05:58:58.407784 WORK_FSP = 0x0
5012 05:58:58.407891 WL = 0x3
5013 05:58:58.411164 RL = 0x3
5014 05:58:58.411260 BL = 0x2
5015 05:58:58.414620 RPST = 0x0
5016 05:58:58.414719 RD_PRE = 0x0
5017 05:58:58.417386 WR_PRE = 0x1
5018 05:58:58.420932 WR_PST = 0x0
5019 05:58:58.421034 DBI_WR = 0x0
5020 05:58:58.424257 DBI_RD = 0x0
5021 05:58:58.424386 OTF = 0x1
5022 05:58:58.427695 ===================================
5023 05:58:58.434029 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5024 05:58:58.437935 nWR fixed to 30
5025 05:58:58.441168 [ModeRegInit_LP4] CH0 RK0
5026 05:58:58.441243 [ModeRegInit_LP4] CH0 RK1
5027 05:58:58.444601 [ModeRegInit_LP4] CH1 RK0
5028 05:58:58.447556 [ModeRegInit_LP4] CH1 RK1
5029 05:58:58.447658 match AC timing 9
5030 05:58:58.454212 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5031 05:58:58.457682 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5032 05:58:58.460972 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5033 05:58:58.467934 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5034 05:58:58.470754 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5035 05:58:58.470833 ==
5036 05:58:58.474215 Dram Type= 6, Freq= 0, CH_0, rank 0
5037 05:58:58.477776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5038 05:58:58.477873 ==
5039 05:58:58.484201 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5040 05:58:58.490454 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5041 05:58:58.494078 [CA 0] Center 37 (6~68) winsize 63
5042 05:58:58.497381 [CA 1] Center 37 (6~68) winsize 63
5043 05:58:58.500847 [CA 2] Center 34 (4~65) winsize 62
5044 05:58:58.504160 [CA 3] Center 33 (3~64) winsize 62
5045 05:58:58.507425 [CA 4] Center 33 (3~64) winsize 62
5046 05:58:58.511033 [CA 5] Center 32 (2~62) winsize 61
5047 05:58:58.511140
5048 05:58:58.513841 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5049 05:58:58.514018
5050 05:58:58.517253 [CATrainingPosCal] consider 1 rank data
5051 05:58:58.520809 u2DelayCellTimex100 = 270/100 ps
5052 05:58:58.523723 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5053 05:58:58.527193 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5054 05:58:58.530682 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5055 05:58:58.534104 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5056 05:58:58.537688 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5057 05:58:58.541037 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5058 05:58:58.543802
5059 05:58:58.547356 CA PerBit enable=1, Macro0, CA PI delay=32
5060 05:58:58.547441
5061 05:58:58.550887 [CBTSetCACLKResult] CA Dly = 32
5062 05:58:58.550968 CS Dly: 5 (0~36)
5063 05:58:58.551031 ==
5064 05:58:58.554366 Dram Type= 6, Freq= 0, CH_0, rank 1
5065 05:58:58.557804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5066 05:58:58.557885 ==
5067 05:58:58.564135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5068 05:58:58.570951 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5069 05:58:58.574152 [CA 0] Center 37 (6~68) winsize 63
5070 05:58:58.577327 [CA 1] Center 37 (7~68) winsize 62
5071 05:58:58.581037 [CA 2] Center 34 (4~65) winsize 62
5072 05:58:58.584063 [CA 3] Center 33 (3~64) winsize 62
5073 05:58:58.587614 [CA 4] Center 33 (3~63) winsize 61
5074 05:58:58.591060 [CA 5] Center 32 (2~62) winsize 61
5075 05:58:58.591141
5076 05:58:58.594367 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5077 05:58:58.594489
5078 05:58:58.597561 [CATrainingPosCal] consider 2 rank data
5079 05:58:58.600906 u2DelayCellTimex100 = 270/100 ps
5080 05:58:58.604223 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5081 05:58:58.607279 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5082 05:58:58.610516 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5083 05:58:58.614262 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5084 05:58:58.617142 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5085 05:58:58.623575 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5086 05:58:58.623658
5087 05:58:58.627082 CA PerBit enable=1, Macro0, CA PI delay=32
5088 05:58:58.627162
5089 05:58:58.630518 [CBTSetCACLKResult] CA Dly = 32
5090 05:58:58.630599 CS Dly: 5 (0~37)
5091 05:58:58.630663
5092 05:58:58.633988 ----->DramcWriteLeveling(PI) begin...
5093 05:58:58.634070 ==
5094 05:58:58.637422 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 05:58:58.640777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 05:58:58.643969 ==
5097 05:58:58.647288 Write leveling (Byte 0): 32 => 32
5098 05:58:58.647369 Write leveling (Byte 1): 32 => 32
5099 05:58:58.650692 DramcWriteLeveling(PI) end<-----
5100 05:58:58.650788
5101 05:58:58.650851 ==
5102 05:58:58.653585 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 05:58:58.660509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 05:58:58.660590 ==
5105 05:58:58.663412 [Gating] SW mode calibration
5106 05:58:58.670394 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5107 05:58:58.673264 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5108 05:58:58.680192 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
5109 05:58:58.683694 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 05:58:58.687085 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 05:58:58.693471 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 05:58:58.696723 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 05:58:58.700086 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 05:58:58.703689 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5115 05:58:58.709927 0 14 28 | B1->B0 | 3333 2a2a | 1 0 | (1 1) (1 0)
5116 05:58:58.713553 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
5117 05:58:58.717202 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 05:58:58.723369 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 05:58:58.726865 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 05:58:58.730005 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 05:58:58.737022 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 05:58:58.740523 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
5123 05:58:58.743180 0 15 28 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
5124 05:58:58.750375 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5125 05:58:58.753381 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 05:58:58.757207 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 05:58:58.763082 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 05:58:58.766280 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 05:58:58.769799 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 05:58:58.776267 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5131 05:58:58.780085 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5132 05:58:58.783548 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5133 05:58:58.790076 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 05:58:58.792933 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 05:58:58.796680 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 05:58:58.802927 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 05:58:58.806065 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 05:58:58.814218 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 05:58:58.816588 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 05:58:58.819922 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 05:58:58.822985 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 05:58:58.829435 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 05:58:58.832941 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 05:58:58.836448 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 05:58:58.842722 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 05:58:58.846304 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5147 05:58:58.849866 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5148 05:58:58.856412 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5149 05:58:58.856502 Total UI for P1: 0, mck2ui 16
5150 05:58:58.859132 best dqsien dly found for B0: ( 1, 2, 26)
5151 05:58:58.866346 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 05:58:58.869765 Total UI for P1: 0, mck2ui 16
5153 05:58:58.873151 best dqsien dly found for B1: ( 1, 3, 0)
5154 05:58:58.876208 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5155 05:58:58.879485 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5156 05:58:58.879566
5157 05:58:58.882754 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5158 05:58:58.885852 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5159 05:58:58.889120 [Gating] SW calibration Done
5160 05:58:58.889227 ==
5161 05:58:58.892426 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 05:58:58.895972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 05:58:58.896053 ==
5164 05:58:58.899202 RX Vref Scan: 0
5165 05:58:58.899282
5166 05:58:58.899346 RX Vref 0 -> 0, step: 1
5167 05:58:58.902544
5168 05:58:58.902624 RX Delay -80 -> 252, step: 8
5169 05:58:58.909413 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5170 05:58:58.912352 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5171 05:58:58.916068 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5172 05:58:58.919074 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5173 05:58:58.922239 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5174 05:58:58.925921 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5175 05:58:58.932534 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5176 05:58:58.935748 iDelay=208, Bit 7, Center 111 (24 ~ 199) 176
5177 05:58:58.939504 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5178 05:58:58.942229 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5179 05:58:58.945722 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5180 05:58:58.949341 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5181 05:58:58.955663 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5182 05:58:58.959213 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5183 05:58:58.962544 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5184 05:58:58.966159 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5185 05:58:58.966241 ==
5186 05:58:58.969571 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 05:58:58.972427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 05:58:58.972535 ==
5189 05:58:58.975867 DQS Delay:
5190 05:58:58.975948 DQS0 = 0, DQS1 = 0
5191 05:58:58.979341 DQM Delay:
5192 05:58:58.979422 DQM0 = 104, DQM1 = 94
5193 05:58:58.979534 DQ Delay:
5194 05:58:58.982573 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5195 05:58:58.986056 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5196 05:58:58.989638 DQ8 =87, DQ9 =87, DQ10 =91, DQ11 =87
5197 05:58:58.992426 DQ12 =99, DQ13 =103, DQ14 =99, DQ15 =99
5198 05:58:58.996028
5199 05:58:58.996135
5200 05:58:58.996230 ==
5201 05:58:58.999564 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 05:58:59.002417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 05:58:59.002505 ==
5204 05:58:59.002611
5205 05:58:59.002700
5206 05:58:59.005882 TX Vref Scan disable
5207 05:58:59.005962 == TX Byte 0 ==
5208 05:58:59.012588 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5209 05:58:59.015928 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5210 05:58:59.016010 == TX Byte 1 ==
5211 05:58:59.022871 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5212 05:58:59.026123 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5213 05:58:59.026209 ==
5214 05:58:59.029279 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 05:58:59.032576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 05:58:59.032679 ==
5217 05:58:59.032769
5218 05:58:59.032851
5219 05:58:59.036216 TX Vref Scan disable
5220 05:58:59.039463 == TX Byte 0 ==
5221 05:58:59.042467 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5222 05:58:59.045914 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5223 05:58:59.048887 == TX Byte 1 ==
5224 05:58:59.052390 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5225 05:58:59.055511 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5226 05:58:59.055613
5227 05:58:59.058998 [DATLAT]
5228 05:58:59.059082 Freq=933, CH0 RK0
5229 05:58:59.059167
5230 05:58:59.062097 DATLAT Default: 0xd
5231 05:58:59.062177 0, 0xFFFF, sum = 0
5232 05:58:59.065580 1, 0xFFFF, sum = 0
5233 05:58:59.065663 2, 0xFFFF, sum = 0
5234 05:58:59.068896 3, 0xFFFF, sum = 0
5235 05:58:59.068978 4, 0xFFFF, sum = 0
5236 05:58:59.071778 5, 0xFFFF, sum = 0
5237 05:58:59.071856 6, 0xFFFF, sum = 0
5238 05:58:59.075373 7, 0xFFFF, sum = 0
5239 05:58:59.075461 8, 0xFFFF, sum = 0
5240 05:58:59.078639 9, 0xFFFF, sum = 0
5241 05:58:59.078722 10, 0x0, sum = 1
5242 05:58:59.082134 11, 0x0, sum = 2
5243 05:58:59.082209 12, 0x0, sum = 3
5244 05:58:59.085566 13, 0x0, sum = 4
5245 05:58:59.085651 best_step = 11
5246 05:58:59.085716
5247 05:58:59.085777 ==
5248 05:58:59.088167 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 05:58:59.094964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 05:58:59.095050 ==
5251 05:58:59.095115 RX Vref Scan: 1
5252 05:58:59.095176
5253 05:58:59.098488 RX Vref 0 -> 0, step: 1
5254 05:58:59.098570
5255 05:58:59.101911 RX Delay -45 -> 252, step: 4
5256 05:58:59.102000
5257 05:58:59.104856 Set Vref, RX VrefLevel [Byte0]: 58
5258 05:58:59.108265 [Byte1]: 49
5259 05:58:59.108365
5260 05:58:59.111806 Final RX Vref Byte 0 = 58 to rank0
5261 05:58:59.115337 Final RX Vref Byte 1 = 49 to rank0
5262 05:58:59.118228 Final RX Vref Byte 0 = 58 to rank1
5263 05:58:59.121749 Final RX Vref Byte 1 = 49 to rank1==
5264 05:58:59.125228 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 05:58:59.128891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 05:58:59.128978 ==
5267 05:58:59.131904 DQS Delay:
5268 05:58:59.131987 DQS0 = 0, DQS1 = 0
5269 05:58:59.135370 DQM Delay:
5270 05:58:59.135452 DQM0 = 104, DQM1 = 95
5271 05:58:59.135519 DQ Delay:
5272 05:58:59.138522 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5273 05:58:59.141943 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112
5274 05:58:59.144799 DQ8 =86, DQ9 =86, DQ10 =96, DQ11 =90
5275 05:58:59.151811 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5276 05:58:59.151896
5277 05:58:59.151962
5278 05:58:59.158536 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5279 05:58:59.161755 CH0 RK0: MR19=505, MR18=3129
5280 05:58:59.167965 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5281 05:58:59.168050
5282 05:58:59.171437 ----->DramcWriteLeveling(PI) begin...
5283 05:58:59.171521 ==
5284 05:58:59.174842 Dram Type= 6, Freq= 0, CH_0, rank 1
5285 05:58:59.178170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 05:58:59.178255 ==
5287 05:58:59.181289 Write leveling (Byte 0): 33 => 33
5288 05:58:59.184901 Write leveling (Byte 1): 28 => 28
5289 05:58:59.187779 DramcWriteLeveling(PI) end<-----
5290 05:58:59.187861
5291 05:58:59.187926 ==
5292 05:58:59.191097 Dram Type= 6, Freq= 0, CH_0, rank 1
5293 05:58:59.194343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 05:58:59.194426 ==
5295 05:58:59.198018 [Gating] SW mode calibration
5296 05:58:59.204643 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5297 05:58:59.210876 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5298 05:58:59.214486 0 14 0 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 1)
5299 05:58:59.221340 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 05:58:59.224555 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 05:58:59.227797 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 05:58:59.234692 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 05:58:59.238154 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 05:58:59.241321 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5305 05:58:59.244750 0 14 28 | B1->B0 | 2727 2e2e | 0 0 | (0 1) (0 0)
5306 05:58:59.250896 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5307 05:58:59.254399 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 05:58:59.257950 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 05:58:59.264138 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 05:58:59.267986 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 05:58:59.271288 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 05:58:59.277435 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5313 05:58:59.280836 0 15 28 | B1->B0 | 3535 2f2f | 1 0 | (0 0) (0 0)
5314 05:58:59.284155 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5315 05:58:59.291128 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 05:58:59.293971 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 05:58:59.297432 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 05:58:59.304084 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 05:58:59.307419 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 05:58:59.310800 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 05:58:59.317575 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5322 05:58:59.321057 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 05:58:59.324578 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 05:58:59.330675 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 05:58:59.333968 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 05:58:59.337584 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 05:58:59.344023 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 05:58:59.347648 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 05:58:59.350921 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 05:58:59.357350 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 05:58:59.361069 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 05:58:59.364572 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 05:58:59.367785 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 05:58:59.373966 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 05:58:59.377740 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 05:58:59.381237 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5337 05:58:59.387515 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5338 05:58:59.391007 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 05:58:59.394435 Total UI for P1: 0, mck2ui 16
5340 05:58:59.397316 best dqsien dly found for B0: ( 1, 2, 26)
5341 05:58:59.400903 Total UI for P1: 0, mck2ui 16
5342 05:58:59.404261 best dqsien dly found for B1: ( 1, 2, 28)
5343 05:58:59.407483 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5344 05:58:59.410743 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5345 05:58:59.410824
5346 05:58:59.413907 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5347 05:58:59.417244 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5348 05:58:59.420748 [Gating] SW calibration Done
5349 05:58:59.420828 ==
5350 05:58:59.424318 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 05:58:59.430614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 05:58:59.430697 ==
5353 05:58:59.430762 RX Vref Scan: 0
5354 05:58:59.430822
5355 05:58:59.434066 RX Vref 0 -> 0, step: 1
5356 05:58:59.434146
5357 05:58:59.437531 RX Delay -80 -> 252, step: 8
5358 05:58:59.441075 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5359 05:58:59.443904 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5360 05:58:59.447284 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5361 05:58:59.450903 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5362 05:58:59.457604 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5363 05:58:59.460987 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5364 05:58:59.464275 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5365 05:58:59.467536 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5366 05:58:59.470807 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5367 05:58:59.473955 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5368 05:58:59.477139 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5369 05:58:59.483907 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5370 05:58:59.487758 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5371 05:58:59.490733 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5372 05:58:59.494173 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5373 05:58:59.497363 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5374 05:58:59.497444 ==
5375 05:58:59.500833 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 05:58:59.507418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 05:58:59.507499 ==
5378 05:58:59.507563 DQS Delay:
5379 05:58:59.510778 DQS0 = 0, DQS1 = 0
5380 05:58:59.510858 DQM Delay:
5381 05:58:59.510921 DQM0 = 106, DQM1 = 93
5382 05:58:59.514024 DQ Delay:
5383 05:58:59.517392 DQ0 =103, DQ1 =111, DQ2 =103, DQ3 =103
5384 05:58:59.521004 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5385 05:58:59.524240 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5386 05:58:59.527194 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5387 05:58:59.527273
5388 05:58:59.527336
5389 05:58:59.527395 ==
5390 05:58:59.530703 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 05:58:59.534054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 05:58:59.534162 ==
5393 05:58:59.534259
5394 05:58:59.534336
5395 05:58:59.537637 TX Vref Scan disable
5396 05:58:59.540987 == TX Byte 0 ==
5397 05:58:59.543767 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5398 05:58:59.547142 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5399 05:58:59.550603 == TX Byte 1 ==
5400 05:58:59.554030 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5401 05:58:59.557380 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5402 05:58:59.557461 ==
5403 05:58:59.560820 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 05:58:59.567091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 05:58:59.567176 ==
5406 05:58:59.567260
5407 05:58:59.567336
5408 05:58:59.567392 TX Vref Scan disable
5409 05:58:59.571164 == TX Byte 0 ==
5410 05:58:59.574416 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5411 05:58:59.581077 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5412 05:58:59.581178 == TX Byte 1 ==
5413 05:58:59.584557 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5414 05:58:59.587496 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5415 05:58:59.590789
5416 05:58:59.590946 [DATLAT]
5417 05:58:59.591072 Freq=933, CH0 RK1
5418 05:58:59.591135
5419 05:58:59.594232 DATLAT Default: 0xb
5420 05:58:59.594356 0, 0xFFFF, sum = 0
5421 05:58:59.597804 1, 0xFFFF, sum = 0
5422 05:58:59.597920 2, 0xFFFF, sum = 0
5423 05:58:59.601325 3, 0xFFFF, sum = 0
5424 05:58:59.601429 4, 0xFFFF, sum = 0
5425 05:58:59.604568 5, 0xFFFF, sum = 0
5426 05:58:59.607921 6, 0xFFFF, sum = 0
5427 05:58:59.608028 7, 0xFFFF, sum = 0
5428 05:58:59.611149 8, 0xFFFF, sum = 0
5429 05:58:59.611262 9, 0xFFFF, sum = 0
5430 05:58:59.614130 10, 0x0, sum = 1
5431 05:58:59.614213 11, 0x0, sum = 2
5432 05:58:59.614279 12, 0x0, sum = 3
5433 05:58:59.618018 13, 0x0, sum = 4
5434 05:58:59.618100 best_step = 11
5435 05:58:59.618165
5436 05:58:59.621015 ==
5437 05:58:59.621095 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 05:58:59.627607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 05:58:59.627690 ==
5440 05:58:59.627753 RX Vref Scan: 0
5441 05:58:59.627813
5442 05:58:59.631265 RX Vref 0 -> 0, step: 1
5443 05:58:59.631345
5444 05:58:59.634206 RX Delay -45 -> 252, step: 4
5445 05:58:59.637563 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5446 05:58:59.644139 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5447 05:58:59.647603 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5448 05:58:59.650575 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5449 05:58:59.654085 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5450 05:58:59.657419 iDelay=199, Bit 5, Center 100 (11 ~ 190) 180
5451 05:58:59.664201 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5452 05:58:59.667702 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5453 05:58:59.670556 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5454 05:58:59.674028 iDelay=199, Bit 9, Center 84 (3 ~ 166) 164
5455 05:58:59.677488 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5456 05:58:59.680852 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5457 05:58:59.687460 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5458 05:58:59.690957 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5459 05:58:59.693850 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5460 05:58:59.697300 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5461 05:58:59.697375 ==
5462 05:58:59.700627 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 05:58:59.706979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 05:58:59.707057 ==
5465 05:58:59.707119 DQS Delay:
5466 05:58:59.710829 DQS0 = 0, DQS1 = 0
5467 05:58:59.710903 DQM Delay:
5468 05:58:59.710965 DQM0 = 104, DQM1 = 93
5469 05:58:59.713602 DQ Delay:
5470 05:58:59.716889 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =100
5471 05:58:59.720234 DQ4 =106, DQ5 =100, DQ6 =108, DQ7 =112
5472 05:58:59.723593 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =88
5473 05:58:59.727140 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5474 05:58:59.727232
5475 05:58:59.727293
5476 05:58:59.734071 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5477 05:58:59.736762 CH0 RK1: MR19=505, MR18=2A03
5478 05:58:59.743537 CH0_RK1: MR19=0x505, MR18=0x2A03, DQSOSC=408, MR23=63, INC=65, DEC=43
5479 05:58:59.747046 [RxdqsGatingPostProcess] freq 933
5480 05:58:59.753879 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5481 05:58:59.757237 best DQS0 dly(2T, 0.5T) = (0, 10)
5482 05:58:59.757316 best DQS1 dly(2T, 0.5T) = (0, 11)
5483 05:58:59.760472 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5484 05:58:59.763721 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5485 05:58:59.766949 best DQS0 dly(2T, 0.5T) = (0, 10)
5486 05:58:59.770275 best DQS1 dly(2T, 0.5T) = (0, 10)
5487 05:58:59.773774 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5488 05:58:59.777208 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5489 05:58:59.780590 Pre-setting of DQS Precalculation
5490 05:58:59.786956 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5491 05:58:59.787040 ==
5492 05:58:59.790103 Dram Type= 6, Freq= 0, CH_1, rank 0
5493 05:58:59.793281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5494 05:58:59.793358 ==
5495 05:58:59.800049 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5496 05:58:59.803494 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5497 05:58:59.807496 [CA 0] Center 36 (6~67) winsize 62
5498 05:58:59.811027 [CA 1] Center 37 (6~68) winsize 63
5499 05:58:59.814102 [CA 2] Center 35 (5~65) winsize 61
5500 05:58:59.817334 [CA 3] Center 34 (4~65) winsize 62
5501 05:58:59.820892 [CA 4] Center 34 (4~65) winsize 62
5502 05:58:59.824319 [CA 5] Center 33 (3~64) winsize 62
5503 05:58:59.824419
5504 05:58:59.827080 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5505 05:58:59.827161
5506 05:58:59.830623 [CATrainingPosCal] consider 1 rank data
5507 05:58:59.834288 u2DelayCellTimex100 = 270/100 ps
5508 05:58:59.837164 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5509 05:58:59.843829 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5510 05:58:59.847265 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5511 05:58:59.850954 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5512 05:58:59.853859 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5513 05:58:59.857377 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5514 05:58:59.857452
5515 05:58:59.860628 CA PerBit enable=1, Macro0, CA PI delay=33
5516 05:58:59.860704
5517 05:58:59.864152 [CBTSetCACLKResult] CA Dly = 33
5518 05:58:59.867087 CS Dly: 6 (0~37)
5519 05:58:59.867167 ==
5520 05:58:59.870576 Dram Type= 6, Freq= 0, CH_1, rank 1
5521 05:58:59.874133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 05:58:59.874216 ==
5523 05:58:59.880494 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5524 05:58:59.883905 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5525 05:58:59.887777 [CA 0] Center 36 (6~67) winsize 62
5526 05:58:59.891117 [CA 1] Center 37 (6~68) winsize 63
5527 05:58:59.894538 [CA 2] Center 35 (5~65) winsize 61
5528 05:58:59.897732 [CA 3] Center 34 (4~65) winsize 62
5529 05:58:59.900560 [CA 4] Center 34 (4~65) winsize 62
5530 05:58:59.904022 [CA 5] Center 33 (3~64) winsize 62
5531 05:58:59.904094
5532 05:58:59.907555 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5533 05:58:59.907628
5534 05:58:59.910878 [CATrainingPosCal] consider 2 rank data
5535 05:58:59.913983 u2DelayCellTimex100 = 270/100 ps
5536 05:58:59.917601 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5537 05:58:59.924153 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5538 05:58:59.927127 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5539 05:58:59.930573 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5540 05:58:59.934213 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5541 05:58:59.937424 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5542 05:58:59.937505
5543 05:58:59.940619 CA PerBit enable=1, Macro0, CA PI delay=33
5544 05:58:59.940693
5545 05:58:59.944072 [CBTSetCACLKResult] CA Dly = 33
5546 05:58:59.944148 CS Dly: 7 (0~40)
5547 05:58:59.944248
5548 05:58:59.950741 ----->DramcWriteLeveling(PI) begin...
5549 05:58:59.950821 ==
5550 05:58:59.954138 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 05:58:59.957654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 05:58:59.957733 ==
5553 05:58:59.961110 Write leveling (Byte 0): 27 => 27
5554 05:58:59.963966 Write leveling (Byte 1): 28 => 28
5555 05:58:59.967229 DramcWriteLeveling(PI) end<-----
5556 05:58:59.967320
5557 05:58:59.967413 ==
5558 05:58:59.970789 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 05:58:59.973719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 05:58:59.973793 ==
5561 05:58:59.977308 [Gating] SW mode calibration
5562 05:58:59.984343 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5563 05:58:59.990861 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5564 05:58:59.994069 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 05:58:59.997372 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 05:59:00.003690 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 05:59:00.007069 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 05:59:00.010532 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 05:59:00.014062 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 05:59:00.020261 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5571 05:59:00.023684 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
5572 05:59:00.027129 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 05:59:00.034151 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 05:59:00.037562 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 05:59:00.040216 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 05:59:00.046874 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 05:59:00.050721 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 05:59:00.053932 0 15 24 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
5579 05:59:00.060722 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5580 05:59:00.064064 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 05:59:00.067189 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 05:59:00.073907 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 05:59:00.076918 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 05:59:00.080348 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 05:59:00.086912 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 05:59:00.090412 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 05:59:00.093871 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5588 05:59:00.100772 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 05:59:00.103966 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 05:59:00.107126 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 05:59:00.113855 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 05:59:00.116680 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 05:59:00.120104 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 05:59:00.127133 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 05:59:00.129829 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 05:59:00.133853 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 05:59:00.140053 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 05:59:00.143451 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 05:59:00.146729 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 05:59:00.153078 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 05:59:00.156524 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 05:59:00.159951 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5603 05:59:00.166318 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5604 05:59:00.166403 Total UI for P1: 0, mck2ui 16
5605 05:59:00.169734 best dqsien dly found for B1: ( 1, 2, 26)
5606 05:59:00.176593 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 05:59:00.179783 Total UI for P1: 0, mck2ui 16
5608 05:59:00.182899 best dqsien dly found for B0: ( 1, 2, 26)
5609 05:59:00.186468 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5610 05:59:00.190020 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5611 05:59:00.190096
5612 05:59:00.193471 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5613 05:59:00.196298 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5614 05:59:00.199491 [Gating] SW calibration Done
5615 05:59:00.199571 ==
5616 05:59:00.203292 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 05:59:00.206375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 05:59:00.206450 ==
5619 05:59:00.209594 RX Vref Scan: 0
5620 05:59:00.209689
5621 05:59:00.212854 RX Vref 0 -> 0, step: 1
5622 05:59:00.212930
5623 05:59:00.213009 RX Delay -80 -> 252, step: 8
5624 05:59:00.219386 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5625 05:59:00.222941 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5626 05:59:00.226510 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5627 05:59:00.229665 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5628 05:59:00.233145 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5629 05:59:00.236535 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5630 05:59:00.242596 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5631 05:59:00.246124 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5632 05:59:00.249441 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5633 05:59:00.253331 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5634 05:59:00.256031 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5635 05:59:00.259463 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5636 05:59:00.266419 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5637 05:59:00.269922 iDelay=208, Bit 13, Center 111 (24 ~ 199) 176
5638 05:59:00.273273 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5639 05:59:00.276071 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5640 05:59:00.276147 ==
5641 05:59:00.279564 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 05:59:00.282989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 05:59:00.286467 ==
5644 05:59:00.286538 DQS Delay:
5645 05:59:00.286618 DQS0 = 0, DQS1 = 0
5646 05:59:00.289286 DQM Delay:
5647 05:59:00.289359 DQM0 = 103, DQM1 = 99
5648 05:59:00.292736 DQ Delay:
5649 05:59:00.296282 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5650 05:59:00.299483 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5651 05:59:00.302859 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5652 05:59:00.306275 DQ12 =107, DQ13 =111, DQ14 =99, DQ15 =107
5653 05:59:00.306350
5654 05:59:00.306430
5655 05:59:00.306506 ==
5656 05:59:00.309596 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 05:59:00.313071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 05:59:00.313150 ==
5659 05:59:00.313229
5660 05:59:00.313308
5661 05:59:00.316512 TX Vref Scan disable
5662 05:59:00.316584 == TX Byte 0 ==
5663 05:59:00.322787 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5664 05:59:00.326343 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5665 05:59:00.329299 == TX Byte 1 ==
5666 05:59:00.332913 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5667 05:59:00.335858 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5668 05:59:00.335930 ==
5669 05:59:00.339192 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 05:59:00.342602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 05:59:00.342705 ==
5672 05:59:00.345913
5673 05:59:00.345980
5674 05:59:00.346040 TX Vref Scan disable
5675 05:59:00.349057 == TX Byte 0 ==
5676 05:59:00.352440 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5677 05:59:00.358994 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5678 05:59:00.359069 == TX Byte 1 ==
5679 05:59:00.362708 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5680 05:59:00.369207 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5681 05:59:00.369285
5682 05:59:00.369350 [DATLAT]
5683 05:59:00.369407 Freq=933, CH1 RK0
5684 05:59:00.369462
5685 05:59:00.372579 DATLAT Default: 0xd
5686 05:59:00.372645 0, 0xFFFF, sum = 0
5687 05:59:00.376176 1, 0xFFFF, sum = 0
5688 05:59:00.376261 2, 0xFFFF, sum = 0
5689 05:59:00.379457 3, 0xFFFF, sum = 0
5690 05:59:00.379528 4, 0xFFFF, sum = 0
5691 05:59:00.382835 5, 0xFFFF, sum = 0
5692 05:59:00.385595 6, 0xFFFF, sum = 0
5693 05:59:00.385663 7, 0xFFFF, sum = 0
5694 05:59:00.389155 8, 0xFFFF, sum = 0
5695 05:59:00.389224 9, 0xFFFF, sum = 0
5696 05:59:00.392530 10, 0x0, sum = 1
5697 05:59:00.392596 11, 0x0, sum = 2
5698 05:59:00.395991 12, 0x0, sum = 3
5699 05:59:00.396056 13, 0x0, sum = 4
5700 05:59:00.396113 best_step = 11
5701 05:59:00.396168
5702 05:59:00.398759 ==
5703 05:59:00.402186 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 05:59:00.405398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 05:59:00.405473 ==
5706 05:59:00.405567 RX Vref Scan: 1
5707 05:59:00.405629
5708 05:59:00.408874 RX Vref 0 -> 0, step: 1
5709 05:59:00.408941
5710 05:59:00.412185 RX Delay -45 -> 252, step: 4
5711 05:59:00.412270
5712 05:59:00.415504 Set Vref, RX VrefLevel [Byte0]: 56
5713 05:59:00.419107 [Byte1]: 49
5714 05:59:00.419175
5715 05:59:00.422468 Final RX Vref Byte 0 = 56 to rank0
5716 05:59:00.425894 Final RX Vref Byte 1 = 49 to rank0
5717 05:59:00.429310 Final RX Vref Byte 0 = 56 to rank1
5718 05:59:00.432719 Final RX Vref Byte 1 = 49 to rank1==
5719 05:59:00.435369 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 05:59:00.438892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 05:59:00.438962 ==
5722 05:59:00.442430 DQS Delay:
5723 05:59:00.442501 DQS0 = 0, DQS1 = 0
5724 05:59:00.445789 DQM Delay:
5725 05:59:00.445854 DQM0 = 103, DQM1 = 100
5726 05:59:00.445911 DQ Delay:
5727 05:59:00.448999 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5728 05:59:00.455648 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =104
5729 05:59:00.458941 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5730 05:59:00.462204 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =110
5731 05:59:00.462271
5732 05:59:00.462329
5733 05:59:00.468836 [DQSOSCAuto] RK0, (LSB)MR18= 0x1931, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5734 05:59:00.472197 CH1 RK0: MR19=505, MR18=1931
5735 05:59:00.479060 CH1_RK0: MR19=0x505, MR18=0x1931, DQSOSC=406, MR23=63, INC=65, DEC=43
5736 05:59:00.479133
5737 05:59:00.482188 ----->DramcWriteLeveling(PI) begin...
5738 05:59:00.482269 ==
5739 05:59:00.485372 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 05:59:00.488705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 05:59:00.488777 ==
5742 05:59:00.491986 Write leveling (Byte 0): 26 => 26
5743 05:59:00.495129 Write leveling (Byte 1): 28 => 28
5744 05:59:00.498616 DramcWriteLeveling(PI) end<-----
5745 05:59:00.498697
5746 05:59:00.498777 ==
5747 05:59:00.502078 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 05:59:00.505550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 05:59:00.505624 ==
5750 05:59:00.508833 [Gating] SW mode calibration
5751 05:59:00.514943 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5752 05:59:00.521671 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5753 05:59:00.525133 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 05:59:00.531958 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 05:59:00.535380 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 05:59:00.538667 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 05:59:00.545638 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 05:59:00.548320 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5759 05:59:00.552140 0 14 24 | B1->B0 | 2f2f 3232 | 1 0 | (1 1) (0 0)
5760 05:59:00.558806 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5761 05:59:00.562181 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5762 05:59:00.565060 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 05:59:00.571912 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 05:59:00.575358 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 05:59:00.578187 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 05:59:00.584718 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 05:59:00.588472 0 15 24 | B1->B0 | 3737 2929 | 0 0 | (0 0) (0 0)
5768 05:59:00.591397 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5769 05:59:00.595166 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 05:59:00.601399 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 05:59:00.604551 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 05:59:00.608230 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 05:59:00.614646 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 05:59:00.618257 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 05:59:00.621266 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5776 05:59:00.627778 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5777 05:59:00.631103 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 05:59:00.634456 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 05:59:00.641459 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 05:59:00.644676 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 05:59:00.648068 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 05:59:00.654929 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 05:59:00.657776 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 05:59:00.661144 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 05:59:00.667768 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 05:59:00.671198 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 05:59:00.674663 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 05:59:00.681427 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 05:59:00.684162 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 05:59:00.687590 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 05:59:00.694347 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5792 05:59:00.694428 Total UI for P1: 0, mck2ui 16
5793 05:59:00.700827 best dqsien dly found for B1: ( 1, 2, 22)
5794 05:59:00.704218 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 05:59:00.708200 Total UI for P1: 0, mck2ui 16
5796 05:59:00.710869 best dqsien dly found for B0: ( 1, 2, 24)
5797 05:59:00.714173 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5798 05:59:00.717420 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5799 05:59:00.717500
5800 05:59:00.720861 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5801 05:59:00.724191 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5802 05:59:00.727313 [Gating] SW calibration Done
5803 05:59:00.727393 ==
5804 05:59:00.731181 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 05:59:00.734050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 05:59:00.734130 ==
5807 05:59:00.737790 RX Vref Scan: 0
5808 05:59:00.737870
5809 05:59:00.740868 RX Vref 0 -> 0, step: 1
5810 05:59:00.740948
5811 05:59:00.741010 RX Delay -80 -> 252, step: 8
5812 05:59:00.747444 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5813 05:59:00.750820 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5814 05:59:00.754084 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5815 05:59:00.757426 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5816 05:59:00.760697 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5817 05:59:00.764251 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5818 05:59:00.770868 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5819 05:59:00.774266 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5820 05:59:00.777714 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5821 05:59:00.781080 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5822 05:59:00.784568 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5823 05:59:00.787999 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5824 05:59:00.794238 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5825 05:59:00.797669 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5826 05:59:00.801112 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5827 05:59:00.804234 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5828 05:59:00.804339 ==
5829 05:59:00.807573 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 05:59:00.814315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 05:59:00.814397 ==
5832 05:59:00.814461 DQS Delay:
5833 05:59:00.814521 DQS0 = 0, DQS1 = 0
5834 05:59:00.817732 DQM Delay:
5835 05:59:00.817812 DQM0 = 102, DQM1 = 99
5836 05:59:00.821066 DQ Delay:
5837 05:59:00.823875 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5838 05:59:00.827238 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5839 05:59:00.830689 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5840 05:59:00.834029 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5841 05:59:00.834127
5842 05:59:00.834238
5843 05:59:00.834297 ==
5844 05:59:00.837387 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 05:59:00.840926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 05:59:00.841009 ==
5847 05:59:00.841106
5848 05:59:00.841166
5849 05:59:00.844506 TX Vref Scan disable
5850 05:59:00.847247 == TX Byte 0 ==
5851 05:59:00.850636 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5852 05:59:00.854308 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5853 05:59:00.857537 == TX Byte 1 ==
5854 05:59:00.860946 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5855 05:59:00.863698 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5856 05:59:00.863779 ==
5857 05:59:00.867199 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 05:59:00.870709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 05:59:00.873485 ==
5860 05:59:00.873566
5861 05:59:00.873629
5862 05:59:00.873688 TX Vref Scan disable
5863 05:59:00.877554 == TX Byte 0 ==
5864 05:59:00.881024 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5865 05:59:00.887119 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5866 05:59:00.887200 == TX Byte 1 ==
5867 05:59:00.890669 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5868 05:59:00.894119 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5869 05:59:00.897646
5870 05:59:00.897725 [DATLAT]
5871 05:59:00.897788 Freq=933, CH1 RK1
5872 05:59:00.897846
5873 05:59:00.900510 DATLAT Default: 0xb
5874 05:59:00.900589 0, 0xFFFF, sum = 0
5875 05:59:00.904116 1, 0xFFFF, sum = 0
5876 05:59:00.904197 2, 0xFFFF, sum = 0
5877 05:59:00.907538 3, 0xFFFF, sum = 0
5878 05:59:00.907618 4, 0xFFFF, sum = 0
5879 05:59:00.910905 5, 0xFFFF, sum = 0
5880 05:59:00.913964 6, 0xFFFF, sum = 0
5881 05:59:00.914045 7, 0xFFFF, sum = 0
5882 05:59:00.917056 8, 0xFFFF, sum = 0
5883 05:59:00.917136 9, 0xFFFF, sum = 0
5884 05:59:00.920554 10, 0x0, sum = 1
5885 05:59:00.920640 11, 0x0, sum = 2
5886 05:59:00.923752 12, 0x0, sum = 3
5887 05:59:00.923865 13, 0x0, sum = 4
5888 05:59:00.923971 best_step = 11
5889 05:59:00.924061
5890 05:59:00.927317 ==
5891 05:59:00.927457 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 05:59:00.934293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 05:59:00.934417 ==
5894 05:59:00.934511 RX Vref Scan: 0
5895 05:59:00.934575
5896 05:59:00.937723 RX Vref 0 -> 0, step: 1
5897 05:59:00.937803
5898 05:59:00.941111 RX Delay -45 -> 252, step: 4
5899 05:59:00.944099 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5900 05:59:00.951052 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5901 05:59:00.953859 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5902 05:59:00.957417 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5903 05:59:00.960892 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5904 05:59:00.963820 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5905 05:59:00.970935 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5906 05:59:00.974489 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5907 05:59:00.976990 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5908 05:59:00.980489 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5909 05:59:00.983882 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5910 05:59:00.987552 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5911 05:59:00.993330 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5912 05:59:00.996822 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5913 05:59:01.000195 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5914 05:59:01.003823 iDelay=203, Bit 15, Center 106 (23 ~ 190) 168
5915 05:59:01.003903 ==
5916 05:59:01.006730 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 05:59:01.013803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 05:59:01.013884 ==
5919 05:59:01.013948 DQS Delay:
5920 05:59:01.016779 DQS0 = 0, DQS1 = 0
5921 05:59:01.016860 DQM Delay:
5922 05:59:01.016924 DQM0 = 105, DQM1 = 98
5923 05:59:01.020020 DQ Delay:
5924 05:59:01.023243 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5925 05:59:01.026525 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5926 05:59:01.029710 DQ8 =90, DQ9 =90, DQ10 =98, DQ11 =92
5927 05:59:01.033080 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5928 05:59:01.033160
5929 05:59:01.033224
5930 05:59:01.043588 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5931 05:59:01.043669 CH1 RK1: MR19=505, MR18=2C00
5932 05:59:01.049812 CH1_RK1: MR19=0x505, MR18=0x2C00, DQSOSC=408, MR23=63, INC=65, DEC=43
5933 05:59:01.053372 [RxdqsGatingPostProcess] freq 933
5934 05:59:01.059668 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5935 05:59:01.063324 best DQS0 dly(2T, 0.5T) = (0, 10)
5936 05:59:01.066182 best DQS1 dly(2T, 0.5T) = (0, 10)
5937 05:59:01.069706 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5938 05:59:01.073179 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5939 05:59:01.073260 best DQS0 dly(2T, 0.5T) = (0, 10)
5940 05:59:01.076883 best DQS1 dly(2T, 0.5T) = (0, 10)
5941 05:59:01.079641 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5942 05:59:01.083204 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5943 05:59:01.086615 Pre-setting of DQS Precalculation
5944 05:59:01.093313 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5945 05:59:01.099665 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5946 05:59:01.106529 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5947 05:59:01.106613
5948 05:59:01.106685
5949 05:59:01.109841 [Calibration Summary] 1866 Mbps
5950 05:59:01.109922 CH 0, Rank 0
5951 05:59:01.113073 SW Impedance : PASS
5952 05:59:01.116262 DUTY Scan : NO K
5953 05:59:01.116383 ZQ Calibration : PASS
5954 05:59:01.119431 Jitter Meter : NO K
5955 05:59:01.123238 CBT Training : PASS
5956 05:59:01.123318 Write leveling : PASS
5957 05:59:01.126567 RX DQS gating : PASS
5958 05:59:01.129791 RX DQ/DQS(RDDQC) : PASS
5959 05:59:01.129872 TX DQ/DQS : PASS
5960 05:59:01.133143 RX DATLAT : PASS
5961 05:59:01.133223 RX DQ/DQS(Engine): PASS
5962 05:59:01.136395 TX OE : NO K
5963 05:59:01.136498 All Pass.
5964 05:59:01.136590
5965 05:59:01.139454 CH 0, Rank 1
5966 05:59:01.139523 SW Impedance : PASS
5967 05:59:01.143369 DUTY Scan : NO K
5968 05:59:01.146712 ZQ Calibration : PASS
5969 05:59:01.146818 Jitter Meter : NO K
5970 05:59:01.149635 CBT Training : PASS
5971 05:59:01.152950 Write leveling : PASS
5972 05:59:01.153049 RX DQS gating : PASS
5973 05:59:01.156127 RX DQ/DQS(RDDQC) : PASS
5974 05:59:01.160099 TX DQ/DQS : PASS
5975 05:59:01.160205 RX DATLAT : PASS
5976 05:59:01.162874 RX DQ/DQS(Engine): PASS
5977 05:59:01.166318 TX OE : NO K
5978 05:59:01.166403 All Pass.
5979 05:59:01.166468
5980 05:59:01.166555 CH 1, Rank 0
5981 05:59:01.169788 SW Impedance : PASS
5982 05:59:01.173435 DUTY Scan : NO K
5983 05:59:01.173509 ZQ Calibration : PASS
5984 05:59:01.176278 Jitter Meter : NO K
5985 05:59:01.179912 CBT Training : PASS
5986 05:59:01.180017 Write leveling : PASS
5987 05:59:01.182650 RX DQS gating : PASS
5988 05:59:01.182746 RX DQ/DQS(RDDQC) : PASS
5989 05:59:01.186148 TX DQ/DQS : PASS
5990 05:59:01.189925 RX DATLAT : PASS
5991 05:59:01.189996 RX DQ/DQS(Engine): PASS
5992 05:59:01.192678 TX OE : NO K
5993 05:59:01.192750 All Pass.
5994 05:59:01.192810
5995 05:59:01.196252 CH 1, Rank 1
5996 05:59:01.196367 SW Impedance : PASS
5997 05:59:01.199483 DUTY Scan : NO K
5998 05:59:01.203039 ZQ Calibration : PASS
5999 05:59:01.203126 Jitter Meter : NO K
6000 05:59:01.206657 CBT Training : PASS
6001 05:59:01.209504 Write leveling : PASS
6002 05:59:01.209584 RX DQS gating : PASS
6003 05:59:01.212842 RX DQ/DQS(RDDQC) : PASS
6004 05:59:01.216165 TX DQ/DQS : PASS
6005 05:59:01.216299 RX DATLAT : PASS
6006 05:59:01.219465 RX DQ/DQS(Engine): PASS
6007 05:59:01.223071 TX OE : NO K
6008 05:59:01.223151 All Pass.
6009 05:59:01.223227
6010 05:59:01.223315 DramC Write-DBI off
6011 05:59:01.226586 PER_BANK_REFRESH: Hybrid Mode
6012 05:59:01.229856 TX_TRACKING: ON
6013 05:59:01.236296 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6014 05:59:01.239575 [FAST_K] Save calibration result to emmc
6015 05:59:01.246084 dramc_set_vcore_voltage set vcore to 650000
6016 05:59:01.246164 Read voltage for 400, 6
6017 05:59:01.249666 Vio18 = 0
6018 05:59:01.249745 Vcore = 650000
6019 05:59:01.249814 Vdram = 0
6020 05:59:01.249879 Vddq = 0
6021 05:59:01.252562 Vmddr = 0
6022 05:59:01.255858 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6023 05:59:01.263140 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6024 05:59:01.266235 MEM_TYPE=3, freq_sel=20
6025 05:59:01.266316 sv_algorithm_assistance_LP4_800
6026 05:59:01.272713 ============ PULL DRAM RESETB DOWN ============
6027 05:59:01.276158 ========== PULL DRAM RESETB DOWN end =========
6028 05:59:01.279587 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6029 05:59:01.283014 ===================================
6030 05:59:01.285835 LPDDR4 DRAM CONFIGURATION
6031 05:59:01.289537 ===================================
6032 05:59:01.292896 EX_ROW_EN[0] = 0x0
6033 05:59:01.292976 EX_ROW_EN[1] = 0x0
6034 05:59:01.296257 LP4Y_EN = 0x0
6035 05:59:01.296370 WORK_FSP = 0x0
6036 05:59:01.299208 WL = 0x2
6037 05:59:01.299288 RL = 0x2
6038 05:59:01.302685 BL = 0x2
6039 05:59:01.302765 RPST = 0x0
6040 05:59:01.306049 RD_PRE = 0x0
6041 05:59:01.306129 WR_PRE = 0x1
6042 05:59:01.308969 WR_PST = 0x0
6043 05:59:01.309049 DBI_WR = 0x0
6044 05:59:01.312385 DBI_RD = 0x0
6045 05:59:01.312465 OTF = 0x1
6046 05:59:01.315888 ===================================
6047 05:59:01.319342 ===================================
6048 05:59:01.322218 ANA top config
6049 05:59:01.325703 ===================================
6050 05:59:01.329279 DLL_ASYNC_EN = 0
6051 05:59:01.329363 ALL_SLAVE_EN = 1
6052 05:59:01.332291 NEW_RANK_MODE = 1
6053 05:59:01.335737 DLL_IDLE_MODE = 1
6054 05:59:01.338880 LP45_APHY_COMB_EN = 1
6055 05:59:01.342434 TX_ODT_DIS = 1
6056 05:59:01.342515 NEW_8X_MODE = 1
6057 05:59:01.345849 ===================================
6058 05:59:01.349236 ===================================
6059 05:59:01.352185 data_rate = 800
6060 05:59:01.355677 CKR = 1
6061 05:59:01.359165 DQ_P2S_RATIO = 4
6062 05:59:01.362826 ===================================
6063 05:59:01.365841 CA_P2S_RATIO = 4
6064 05:59:01.365922 DQ_CA_OPEN = 0
6065 05:59:01.368911 DQ_SEMI_OPEN = 1
6066 05:59:01.372391 CA_SEMI_OPEN = 1
6067 05:59:01.375407 CA_FULL_RATE = 0
6068 05:59:01.379256 DQ_CKDIV4_EN = 0
6069 05:59:01.382118 CA_CKDIV4_EN = 1
6070 05:59:01.382199 CA_PREDIV_EN = 0
6071 05:59:01.385661 PH8_DLY = 0
6072 05:59:01.388518 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6073 05:59:01.392102 DQ_AAMCK_DIV = 0
6074 05:59:01.395654 CA_AAMCK_DIV = 0
6075 05:59:01.398573 CA_ADMCK_DIV = 4
6076 05:59:01.398667 DQ_TRACK_CA_EN = 0
6077 05:59:01.402071 CA_PICK = 800
6078 05:59:01.405310 CA_MCKIO = 400
6079 05:59:01.408866 MCKIO_SEMI = 400
6080 05:59:01.412144 PLL_FREQ = 3016
6081 05:59:01.414882 DQ_UI_PI_RATIO = 32
6082 05:59:01.418486 CA_UI_PI_RATIO = 32
6083 05:59:01.421919 ===================================
6084 05:59:01.425549 ===================================
6085 05:59:01.425630 memory_type:LPDDR4
6086 05:59:01.428124 GP_NUM : 10
6087 05:59:01.431793 SRAM_EN : 1
6088 05:59:01.431904 MD32_EN : 0
6089 05:59:01.435361 ===================================
6090 05:59:01.438977 [ANA_INIT] >>>>>>>>>>>>>>
6091 05:59:01.441689 <<<<<< [CONFIGURE PHASE]: ANA_TX
6092 05:59:01.445193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6093 05:59:01.448764 ===================================
6094 05:59:01.451978 data_rate = 800,PCW = 0X7400
6095 05:59:01.455376 ===================================
6096 05:59:01.458190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6097 05:59:01.461771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 05:59:01.475217 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6099 05:59:01.478470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6100 05:59:01.481705 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6101 05:59:01.485162 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6102 05:59:01.488509 [ANA_INIT] flow start
6103 05:59:01.492034 [ANA_INIT] PLL >>>>>>>>
6104 05:59:01.492117 [ANA_INIT] PLL <<<<<<<<
6105 05:59:01.495276 [ANA_INIT] MIDPI >>>>>>>>
6106 05:59:01.498743 [ANA_INIT] MIDPI <<<<<<<<
6107 05:59:01.498825 [ANA_INIT] DLL >>>>>>>>
6108 05:59:01.501551 [ANA_INIT] flow end
6109 05:59:01.504870 ============ LP4 DIFF to SE enter ============
6110 05:59:01.508089 ============ LP4 DIFF to SE exit ============
6111 05:59:01.511911 [ANA_INIT] <<<<<<<<<<<<<
6112 05:59:01.515020 [Flow] Enable top DCM control >>>>>
6113 05:59:01.518416 [Flow] Enable top DCM control <<<<<
6114 05:59:01.522096 Enable DLL master slave shuffle
6115 05:59:01.528409 ==============================================================
6116 05:59:01.528497 Gating Mode config
6117 05:59:01.535299 ==============================================================
6118 05:59:01.535398 Config description:
6119 05:59:01.545296 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6120 05:59:01.551661 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6121 05:59:01.558628 SELPH_MODE 0: By rank 1: By Phase
6122 05:59:01.562030 ==============================================================
6123 05:59:01.564942 GAT_TRACK_EN = 0
6124 05:59:01.568429 RX_GATING_MODE = 2
6125 05:59:01.571927 RX_GATING_TRACK_MODE = 2
6126 05:59:01.574821 SELPH_MODE = 1
6127 05:59:01.578318 PICG_EARLY_EN = 1
6128 05:59:01.581864 VALID_LAT_VALUE = 1
6129 05:59:01.585285 ==============================================================
6130 05:59:01.588561 Enter into Gating configuration >>>>
6131 05:59:01.591943 Exit from Gating configuration <<<<
6132 05:59:01.594726 Enter into DVFS_PRE_config >>>>>
6133 05:59:01.607939 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6134 05:59:01.611642 Exit from DVFS_PRE_config <<<<<
6135 05:59:01.615228 Enter into PICG configuration >>>>
6136 05:59:01.618633 Exit from PICG configuration <<<<
6137 05:59:01.618756 [RX_INPUT] configuration >>>>>
6138 05:59:01.621283 [RX_INPUT] configuration <<<<<
6139 05:59:01.628057 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6140 05:59:01.631647 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6141 05:59:01.638212 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 05:59:01.645399 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 05:59:01.651413 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 05:59:01.658295 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 05:59:01.661542 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6146 05:59:01.664891 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6147 05:59:01.671098 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6148 05:59:01.674636 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6149 05:59:01.678041 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6150 05:59:01.681493 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6151 05:59:01.684266 ===================================
6152 05:59:01.687941 LPDDR4 DRAM CONFIGURATION
6153 05:59:01.691256 ===================================
6154 05:59:01.694706 EX_ROW_EN[0] = 0x0
6155 05:59:01.694788 EX_ROW_EN[1] = 0x0
6156 05:59:01.698208 LP4Y_EN = 0x0
6157 05:59:01.698290 WORK_FSP = 0x0
6158 05:59:01.701654 WL = 0x2
6159 05:59:01.701736 RL = 0x2
6160 05:59:01.704238 BL = 0x2
6161 05:59:01.704331 RPST = 0x0
6162 05:59:01.708499 RD_PRE = 0x0
6163 05:59:01.708580 WR_PRE = 0x1
6164 05:59:01.711075 WR_PST = 0x0
6165 05:59:01.711157 DBI_WR = 0x0
6166 05:59:01.714278 DBI_RD = 0x0
6167 05:59:01.714360 OTF = 0x1
6168 05:59:01.717784 ===================================
6169 05:59:01.724723 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6170 05:59:01.727492 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6171 05:59:01.730857 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6172 05:59:01.734403 ===================================
6173 05:59:01.737806 LPDDR4 DRAM CONFIGURATION
6174 05:59:01.740917 ===================================
6175 05:59:01.744121 EX_ROW_EN[0] = 0x10
6176 05:59:01.744226 EX_ROW_EN[1] = 0x0
6177 05:59:01.747467 LP4Y_EN = 0x0
6178 05:59:01.747549 WORK_FSP = 0x0
6179 05:59:01.750831 WL = 0x2
6180 05:59:01.750910 RL = 0x2
6181 05:59:01.754243 BL = 0x2
6182 05:59:01.754326 RPST = 0x0
6183 05:59:01.757499 RD_PRE = 0x0
6184 05:59:01.757583 WR_PRE = 0x1
6185 05:59:01.761000 WR_PST = 0x0
6186 05:59:01.761079 DBI_WR = 0x0
6187 05:59:01.764296 DBI_RD = 0x0
6188 05:59:01.764389 OTF = 0x1
6189 05:59:01.767904 ===================================
6190 05:59:01.774000 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6191 05:59:01.778802 nWR fixed to 30
6192 05:59:01.782382 [ModeRegInit_LP4] CH0 RK0
6193 05:59:01.782461 [ModeRegInit_LP4] CH0 RK1
6194 05:59:01.785817 [ModeRegInit_LP4] CH1 RK0
6195 05:59:01.788689 [ModeRegInit_LP4] CH1 RK1
6196 05:59:01.788769 match AC timing 19
6197 05:59:01.795300 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6198 05:59:01.798921 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6199 05:59:01.802101 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6200 05:59:01.808814 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6201 05:59:01.812204 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6202 05:59:01.812304 ==
6203 05:59:01.815695 Dram Type= 6, Freq= 0, CH_0, rank 0
6204 05:59:01.818922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6205 05:59:01.819002 ==
6206 05:59:01.825684 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6207 05:59:01.832167 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6208 05:59:01.835732 [CA 0] Center 36 (8~64) winsize 57
6209 05:59:01.839174 [CA 1] Center 36 (8~64) winsize 57
6210 05:59:01.842476 [CA 2] Center 36 (8~64) winsize 57
6211 05:59:01.842555 [CA 3] Center 36 (8~64) winsize 57
6212 05:59:01.845811 [CA 4] Center 36 (8~64) winsize 57
6213 05:59:01.848917 [CA 5] Center 36 (8~64) winsize 57
6214 05:59:01.848997
6215 05:59:01.851948 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6216 05:59:01.855268
6217 05:59:01.858627 [CATrainingPosCal] consider 1 rank data
6218 05:59:01.858707 u2DelayCellTimex100 = 270/100 ps
6219 05:59:01.865528 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 05:59:01.868891 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 05:59:01.872445 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 05:59:01.875514 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 05:59:01.878800 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 05:59:01.882162 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 05:59:01.882242
6226 05:59:01.885120 CA PerBit enable=1, Macro0, CA PI delay=36
6227 05:59:01.885207
6228 05:59:01.889066 [CBTSetCACLKResult] CA Dly = 36
6229 05:59:01.892167 CS Dly: 1 (0~32)
6230 05:59:01.892249 ==
6231 05:59:01.895148 Dram Type= 6, Freq= 0, CH_0, rank 1
6232 05:59:01.898503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 05:59:01.898585 ==
6234 05:59:01.905349 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 05:59:01.908595 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6236 05:59:01.911978 [CA 0] Center 36 (8~64) winsize 57
6237 05:59:01.915425 [CA 1] Center 36 (8~64) winsize 57
6238 05:59:01.918844 [CA 2] Center 36 (8~64) winsize 57
6239 05:59:01.922265 [CA 3] Center 36 (8~64) winsize 57
6240 05:59:01.925008 [CA 4] Center 36 (8~64) winsize 57
6241 05:59:01.928448 [CA 5] Center 36 (8~64) winsize 57
6242 05:59:01.928529
6243 05:59:01.931726 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6244 05:59:01.931806
6245 05:59:01.935423 [CATrainingPosCal] consider 2 rank data
6246 05:59:01.938440 u2DelayCellTimex100 = 270/100 ps
6247 05:59:01.941925 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 05:59:01.945087 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 05:59:01.948759 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 05:59:01.952205 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 05:59:01.958659 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 05:59:01.961669 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 05:59:01.961749
6254 05:59:01.965580 CA PerBit enable=1, Macro0, CA PI delay=36
6255 05:59:01.965660
6256 05:59:01.968211 [CBTSetCACLKResult] CA Dly = 36
6257 05:59:01.968299 CS Dly: 1 (0~32)
6258 05:59:01.968379
6259 05:59:01.972268 ----->DramcWriteLeveling(PI) begin...
6260 05:59:01.972390 ==
6261 05:59:01.975130 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 05:59:01.981875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 05:59:01.981957 ==
6264 05:59:01.985177 Write leveling (Byte 0): 40 => 8
6265 05:59:01.985283 Write leveling (Byte 1): 40 => 8
6266 05:59:01.988522 DramcWriteLeveling(PI) end<-----
6267 05:59:01.988603
6268 05:59:01.991725 ==
6269 05:59:01.991806 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 05:59:01.998312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 05:59:01.998432 ==
6272 05:59:02.001532 [Gating] SW mode calibration
6273 05:59:02.008467 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6274 05:59:02.011439 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6275 05:59:02.018105 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 05:59:02.021654 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 05:59:02.025131 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 05:59:02.031355 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 05:59:02.034825 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 05:59:02.038245 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 05:59:02.045373 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 05:59:02.047945 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 05:59:02.051592 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 05:59:02.054516 Total UI for P1: 0, mck2ui 16
6285 05:59:02.058320 best dqsien dly found for B0: ( 0, 14, 24)
6286 05:59:02.061557 Total UI for P1: 0, mck2ui 16
6287 05:59:02.064657 best dqsien dly found for B1: ( 0, 14, 24)
6288 05:59:02.068058 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6289 05:59:02.071090 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6290 05:59:02.071170
6291 05:59:02.078186 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 05:59:02.081660 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6293 05:59:02.081741 [Gating] SW calibration Done
6294 05:59:02.084259 ==
6295 05:59:02.087716 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 05:59:02.091324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 05:59:02.091405 ==
6298 05:59:02.091469 RX Vref Scan: 0
6299 05:59:02.091528
6300 05:59:02.094731 RX Vref 0 -> 0, step: 1
6301 05:59:02.094810
6302 05:59:02.098181 RX Delay -410 -> 252, step: 16
6303 05:59:02.101524 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6304 05:59:02.104190 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6305 05:59:02.110674 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6306 05:59:02.114056 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6307 05:59:02.117856 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6308 05:59:02.120931 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6309 05:59:02.127461 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6310 05:59:02.130627 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6311 05:59:02.134150 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6312 05:59:02.137712 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6313 05:59:02.143880 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6314 05:59:02.147418 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6315 05:59:02.150890 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6316 05:59:02.157736 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6317 05:59:02.161134 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6318 05:59:02.164198 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6319 05:59:02.164315 ==
6320 05:59:02.167322 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 05:59:02.170900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 05:59:02.170978 ==
6323 05:59:02.174130 DQS Delay:
6324 05:59:02.174208 DQS0 = 27, DQS1 = 35
6325 05:59:02.177230 DQM Delay:
6326 05:59:02.177299 DQM0 = 10, DQM1 = 11
6327 05:59:02.180832 DQ Delay:
6328 05:59:02.180915 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6329 05:59:02.183919 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6330 05:59:02.187535 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6331 05:59:02.190641 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6332 05:59:02.190715
6333 05:59:02.190775
6334 05:59:02.190831 ==
6335 05:59:02.194254 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 05:59:02.200957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 05:59:02.201033 ==
6338 05:59:02.201095
6339 05:59:02.201158
6340 05:59:02.201215 TX Vref Scan disable
6341 05:59:02.204254 == TX Byte 0 ==
6342 05:59:02.207160 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 05:59:02.210547 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 05:59:02.214031 == TX Byte 1 ==
6345 05:59:02.217599 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 05:59:02.220933 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 05:59:02.221013 ==
6348 05:59:02.223776 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 05:59:02.230504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 05:59:02.230585 ==
6351 05:59:02.230649
6352 05:59:02.230708
6353 05:59:02.233530 TX Vref Scan disable
6354 05:59:02.233607 == TX Byte 0 ==
6355 05:59:02.237243 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 05:59:02.243907 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 05:59:02.244007 == TX Byte 1 ==
6358 05:59:02.246942 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 05:59:02.250451 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 05:59:02.253880
6361 05:59:02.253977 [DATLAT]
6362 05:59:02.254065 Freq=400, CH0 RK0
6363 05:59:02.254153
6364 05:59:02.256792 DATLAT Default: 0xf
6365 05:59:02.256870 0, 0xFFFF, sum = 0
6366 05:59:02.260159 1, 0xFFFF, sum = 0
6367 05:59:02.260258 2, 0xFFFF, sum = 0
6368 05:59:02.263838 3, 0xFFFF, sum = 0
6369 05:59:02.263936 4, 0xFFFF, sum = 0
6370 05:59:02.266788 5, 0xFFFF, sum = 0
6371 05:59:02.270190 6, 0xFFFF, sum = 0
6372 05:59:02.270263 7, 0xFFFF, sum = 0
6373 05:59:02.273695 8, 0xFFFF, sum = 0
6374 05:59:02.273767 9, 0xFFFF, sum = 0
6375 05:59:02.276784 10, 0xFFFF, sum = 0
6376 05:59:02.276855 11, 0xFFFF, sum = 0
6377 05:59:02.280116 12, 0xFFFF, sum = 0
6378 05:59:02.280218 13, 0x0, sum = 1
6379 05:59:02.283204 14, 0x0, sum = 2
6380 05:59:02.283274 15, 0x0, sum = 3
6381 05:59:02.287046 16, 0x0, sum = 4
6382 05:59:02.287121 best_step = 14
6383 05:59:02.287211
6384 05:59:02.287296 ==
6385 05:59:02.290446 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 05:59:02.293683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 05:59:02.293755 ==
6388 05:59:02.296953 RX Vref Scan: 1
6389 05:59:02.297022
6390 05:59:02.300175 RX Vref 0 -> 0, step: 1
6391 05:59:02.300267
6392 05:59:02.300395 RX Delay -311 -> 252, step: 8
6393 05:59:02.303430
6394 05:59:02.303527 Set Vref, RX VrefLevel [Byte0]: 58
6395 05:59:02.306575 [Byte1]: 49
6396 05:59:02.312087
6397 05:59:02.312210 Final RX Vref Byte 0 = 58 to rank0
6398 05:59:02.315592 Final RX Vref Byte 1 = 49 to rank0
6399 05:59:02.318944 Final RX Vref Byte 0 = 58 to rank1
6400 05:59:02.322390 Final RX Vref Byte 1 = 49 to rank1==
6401 05:59:02.325247 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 05:59:02.332096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 05:59:02.332205 ==
6404 05:59:02.332316 DQS Delay:
6405 05:59:02.335624 DQS0 = 28, DQS1 = 36
6406 05:59:02.335727 DQM Delay:
6407 05:59:02.335816 DQM0 = 11, DQM1 = 12
6408 05:59:02.339105 DQ Delay:
6409 05:59:02.342322 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6410 05:59:02.342426 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6411 05:59:02.345565 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6412 05:59:02.348827 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6413 05:59:02.348907
6414 05:59:02.348979
6415 05:59:02.358831 [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b6, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6416 05:59:02.361801 CH0 RK0: MR19=C0C, MR18=C8B6
6417 05:59:02.368771 CH0_RK0: MR19=0xC0C, MR18=0xC8B6, DQSOSC=385, MR23=63, INC=398, DEC=265
6418 05:59:02.368847 ==
6419 05:59:02.371609 Dram Type= 6, Freq= 0, CH_0, rank 1
6420 05:59:02.375157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 05:59:02.375254 ==
6422 05:59:02.378512 [Gating] SW mode calibration
6423 05:59:02.385350 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6424 05:59:02.391979 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6425 05:59:02.395002 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 05:59:02.398735 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 05:59:02.405103 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 05:59:02.408575 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 05:59:02.411804 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 05:59:02.415107 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 05:59:02.421442 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 05:59:02.425174 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 05:59:02.428484 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 05:59:02.431315 Total UI for P1: 0, mck2ui 16
6435 05:59:02.434804 best dqsien dly found for B0: ( 0, 14, 24)
6436 05:59:02.438157 Total UI for P1: 0, mck2ui 16
6437 05:59:02.441537 best dqsien dly found for B1: ( 0, 14, 24)
6438 05:59:02.445033 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6439 05:59:02.451289 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6440 05:59:02.451387
6441 05:59:02.454585 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 05:59:02.457933 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6443 05:59:02.461227 [Gating] SW calibration Done
6444 05:59:02.461322 ==
6445 05:59:02.464551 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 05:59:02.467829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 05:59:02.467930 ==
6448 05:59:02.471063 RX Vref Scan: 0
6449 05:59:02.471135
6450 05:59:02.471219 RX Vref 0 -> 0, step: 1
6451 05:59:02.471279
6452 05:59:02.474755 RX Delay -410 -> 252, step: 16
6453 05:59:02.478188 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6454 05:59:02.484492 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6455 05:59:02.487742 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6456 05:59:02.491215 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6457 05:59:02.494741 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6458 05:59:02.501461 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6459 05:59:02.504714 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6460 05:59:02.507788 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6461 05:59:02.510903 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6462 05:59:02.517621 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6463 05:59:02.521314 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6464 05:59:02.524462 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6465 05:59:02.527707 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6466 05:59:02.534176 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6467 05:59:02.537384 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6468 05:59:02.540846 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6469 05:59:02.540946 ==
6470 05:59:02.544419 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 05:59:02.550886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 05:59:02.550987 ==
6473 05:59:02.551075 DQS Delay:
6474 05:59:02.554312 DQS0 = 27, DQS1 = 35
6475 05:59:02.554405 DQM Delay:
6476 05:59:02.554490 DQM0 = 11, DQM1 = 12
6477 05:59:02.557696 DQ Delay:
6478 05:59:02.561154 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6479 05:59:02.561228 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6480 05:59:02.564514 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6481 05:59:02.567805 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6482 05:59:02.567900
6483 05:59:02.567987
6484 05:59:02.571082 ==
6485 05:59:02.573980 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 05:59:02.577363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 05:59:02.577458 ==
6488 05:59:02.577528
6489 05:59:02.577585
6490 05:59:02.580708 TX Vref Scan disable
6491 05:59:02.580783 == TX Byte 0 ==
6492 05:59:02.583814 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6493 05:59:02.590931 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6494 05:59:02.591039 == TX Byte 1 ==
6495 05:59:02.594383 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6496 05:59:02.600721 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6497 05:59:02.600811 ==
6498 05:59:02.604228 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 05:59:02.607685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 05:59:02.607784 ==
6501 05:59:02.607874
6502 05:59:02.607959
6503 05:59:02.610432 TX Vref Scan disable
6504 05:59:02.610513 == TX Byte 0 ==
6505 05:59:02.613795 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6506 05:59:02.620868 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6507 05:59:02.620949 == TX Byte 1 ==
6508 05:59:02.623823 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6509 05:59:02.630870 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6510 05:59:02.630951
6511 05:59:02.631015 [DATLAT]
6512 05:59:02.631075 Freq=400, CH0 RK1
6513 05:59:02.631132
6514 05:59:02.633917 DATLAT Default: 0xe
6515 05:59:02.633997 0, 0xFFFF, sum = 0
6516 05:59:02.636972 1, 0xFFFF, sum = 0
6517 05:59:02.640523 2, 0xFFFF, sum = 0
6518 05:59:02.640638 3, 0xFFFF, sum = 0
6519 05:59:02.643640 4, 0xFFFF, sum = 0
6520 05:59:02.643722 5, 0xFFFF, sum = 0
6521 05:59:02.647335 6, 0xFFFF, sum = 0
6522 05:59:02.647417 7, 0xFFFF, sum = 0
6523 05:59:02.650581 8, 0xFFFF, sum = 0
6524 05:59:02.650662 9, 0xFFFF, sum = 0
6525 05:59:02.654205 10, 0xFFFF, sum = 0
6526 05:59:02.654287 11, 0xFFFF, sum = 0
6527 05:59:02.657393 12, 0xFFFF, sum = 0
6528 05:59:02.657476 13, 0x0, sum = 1
6529 05:59:02.660881 14, 0x0, sum = 2
6530 05:59:02.660963 15, 0x0, sum = 3
6531 05:59:02.664190 16, 0x0, sum = 4
6532 05:59:02.664271 best_step = 14
6533 05:59:02.664393
6534 05:59:02.664454 ==
6535 05:59:02.667588 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 05:59:02.670912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 05:59:02.670992 ==
6538 05:59:02.673619 RX Vref Scan: 0
6539 05:59:02.673701
6540 05:59:02.676858 RX Vref 0 -> 0, step: 1
6541 05:59:02.676932
6542 05:59:02.676993 RX Delay -311 -> 252, step: 8
6543 05:59:02.685879 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6544 05:59:02.689330 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6545 05:59:02.692600 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6546 05:59:02.695659 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6547 05:59:02.702846 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6548 05:59:02.706347 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6549 05:59:02.709099 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6550 05:59:02.712584 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6551 05:59:02.719561 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6552 05:59:02.723057 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6553 05:59:02.725853 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6554 05:59:02.729218 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6555 05:59:02.735770 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6556 05:59:02.739141 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6557 05:59:02.742408 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6558 05:59:02.748938 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6559 05:59:02.749020 ==
6560 05:59:02.752213 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 05:59:02.756039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 05:59:02.756120 ==
6563 05:59:02.756184 DQS Delay:
6564 05:59:02.759193 DQS0 = 24, DQS1 = 32
6565 05:59:02.759273 DQM Delay:
6566 05:59:02.762477 DQM0 = 8, DQM1 = 9
6567 05:59:02.762556 DQ Delay:
6568 05:59:02.765538 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6569 05:59:02.769219 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6570 05:59:02.772505 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6571 05:59:02.775825 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6572 05:59:02.775905
6573 05:59:02.775968
6574 05:59:02.782429 [DQSOSCAuto] RK1, (LSB)MR18= 0xb252, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6575 05:59:02.785977 CH0 RK1: MR19=C0C, MR18=B252
6576 05:59:02.792157 CH0_RK1: MR19=0xC0C, MR18=0xB252, DQSOSC=387, MR23=63, INC=394, DEC=262
6577 05:59:02.795538 [RxdqsGatingPostProcess] freq 400
6578 05:59:02.798900 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6579 05:59:02.802503 best DQS0 dly(2T, 0.5T) = (0, 10)
6580 05:59:02.805370 best DQS1 dly(2T, 0.5T) = (0, 10)
6581 05:59:02.808582 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6582 05:59:02.812425 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6583 05:59:02.815693 best DQS0 dly(2T, 0.5T) = (0, 10)
6584 05:59:02.818694 best DQS1 dly(2T, 0.5T) = (0, 10)
6585 05:59:02.822566 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6586 05:59:02.825426 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6587 05:59:02.829002 Pre-setting of DQS Precalculation
6588 05:59:02.831892 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6589 05:59:02.835212 ==
6590 05:59:02.835293 Dram Type= 6, Freq= 0, CH_1, rank 0
6591 05:59:02.841837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 05:59:02.841919 ==
6593 05:59:02.845175 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6594 05:59:02.852081 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6595 05:59:02.855473 [CA 0] Center 36 (8~64) winsize 57
6596 05:59:02.858870 [CA 1] Center 36 (8~64) winsize 57
6597 05:59:02.861701 [CA 2] Center 36 (8~64) winsize 57
6598 05:59:02.865122 [CA 3] Center 36 (8~64) winsize 57
6599 05:59:02.868512 [CA 4] Center 36 (8~64) winsize 57
6600 05:59:02.871822 [CA 5] Center 36 (8~64) winsize 57
6601 05:59:02.871902
6602 05:59:02.875243 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6603 05:59:02.875346
6604 05:59:02.878559 [CATrainingPosCal] consider 1 rank data
6605 05:59:02.882003 u2DelayCellTimex100 = 270/100 ps
6606 05:59:02.885273 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 05:59:02.888517 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 05:59:02.892011 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 05:59:02.894848 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 05:59:02.898399 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 05:59:02.905517 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 05:59:02.905598
6613 05:59:02.908400 CA PerBit enable=1, Macro0, CA PI delay=36
6614 05:59:02.908480
6615 05:59:02.911776 [CBTSetCACLKResult] CA Dly = 36
6616 05:59:02.911856 CS Dly: 1 (0~32)
6617 05:59:02.911920 ==
6618 05:59:02.915184 Dram Type= 6, Freq= 0, CH_1, rank 1
6619 05:59:02.918486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 05:59:02.921818 ==
6621 05:59:02.925181 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 05:59:02.931849 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6623 05:59:02.934981 [CA 0] Center 36 (8~64) winsize 57
6624 05:59:02.938302 [CA 1] Center 36 (8~64) winsize 57
6625 05:59:02.941767 [CA 2] Center 36 (8~64) winsize 57
6626 05:59:02.945280 [CA 3] Center 36 (8~64) winsize 57
6627 05:59:02.948579 [CA 4] Center 36 (8~64) winsize 57
6628 05:59:02.951897 [CA 5] Center 36 (8~64) winsize 57
6629 05:59:02.951978
6630 05:59:02.954868 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6631 05:59:02.954949
6632 05:59:02.958736 [CATrainingPosCal] consider 2 rank data
6633 05:59:02.962016 u2DelayCellTimex100 = 270/100 ps
6634 05:59:02.964675 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 05:59:02.968548 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 05:59:02.971898 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 05:59:02.974569 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 05:59:02.978079 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 05:59:02.981406 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 05:59:02.981487
6641 05:59:02.984826 CA PerBit enable=1, Macro0, CA PI delay=36
6642 05:59:02.988401
6643 05:59:02.988481 [CBTSetCACLKResult] CA Dly = 36
6644 05:59:02.991778 CS Dly: 1 (0~32)
6645 05:59:02.991858
6646 05:59:02.994549 ----->DramcWriteLeveling(PI) begin...
6647 05:59:02.994632 ==
6648 05:59:02.998164 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 05:59:03.001574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 05:59:03.001656 ==
6651 05:59:03.004428 Write leveling (Byte 0): 40 => 8
6652 05:59:03.008094 Write leveling (Byte 1): 40 => 8
6653 05:59:03.011686 DramcWriteLeveling(PI) end<-----
6654 05:59:03.011793
6655 05:59:03.011884 ==
6656 05:59:03.014492 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 05:59:03.017994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 05:59:03.018075 ==
6659 05:59:03.021477 [Gating] SW mode calibration
6660 05:59:03.027831 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6661 05:59:03.034688 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6662 05:59:03.037656 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 05:59:03.044742 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6664 05:59:03.047830 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 05:59:03.051102 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 05:59:03.058037 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 05:59:03.061452 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 05:59:03.064930 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 05:59:03.068426 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 05:59:03.074494 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 05:59:03.077884 Total UI for P1: 0, mck2ui 16
6672 05:59:03.080887 best dqsien dly found for B0: ( 0, 14, 24)
6673 05:59:03.084100 Total UI for P1: 0, mck2ui 16
6674 05:59:03.087795 best dqsien dly found for B1: ( 0, 14, 24)
6675 05:59:03.091153 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6676 05:59:03.094683 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6677 05:59:03.094764
6678 05:59:03.097431 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 05:59:03.100924 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6680 05:59:03.104329 [Gating] SW calibration Done
6681 05:59:03.104410 ==
6682 05:59:03.107520 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 05:59:03.111292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 05:59:03.111373 ==
6685 05:59:03.113972 RX Vref Scan: 0
6686 05:59:03.114052
6687 05:59:03.117487 RX Vref 0 -> 0, step: 1
6688 05:59:03.117567
6689 05:59:03.117631 RX Delay -410 -> 252, step: 16
6690 05:59:03.124591 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6691 05:59:03.127967 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6692 05:59:03.130676 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6693 05:59:03.134170 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6694 05:59:03.141017 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6695 05:59:03.144591 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6696 05:59:03.147303 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6697 05:59:03.150794 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6698 05:59:03.157370 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6699 05:59:03.160544 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6700 05:59:03.163769 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6701 05:59:03.170804 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6702 05:59:03.174221 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6703 05:59:03.177501 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6704 05:59:03.180706 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6705 05:59:03.187304 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6706 05:59:03.187386 ==
6707 05:59:03.190756 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 05:59:03.193821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 05:59:03.193902 ==
6710 05:59:03.193966 DQS Delay:
6711 05:59:03.196926 DQS0 = 35, DQS1 = 35
6712 05:59:03.197007 DQM Delay:
6713 05:59:03.200584 DQM0 = 17, DQM1 = 12
6714 05:59:03.200665 DQ Delay:
6715 05:59:03.203508 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6716 05:59:03.207055 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6717 05:59:03.210580 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6718 05:59:03.213986 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6719 05:59:03.214066
6720 05:59:03.214130
6721 05:59:03.214187 ==
6722 05:59:03.217427 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 05:59:03.220854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 05:59:03.220936 ==
6725 05:59:03.220999
6726 05:59:03.221067
6727 05:59:03.223942 TX Vref Scan disable
6728 05:59:03.227126 == TX Byte 0 ==
6729 05:59:03.230642 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 05:59:03.234045 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 05:59:03.236725 == TX Byte 1 ==
6732 05:59:03.240116 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 05:59:03.243636 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 05:59:03.243724 ==
6735 05:59:03.247075 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 05:59:03.249879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 05:59:03.249960 ==
6738 05:59:03.253490
6739 05:59:03.253570
6740 05:59:03.253633 TX Vref Scan disable
6741 05:59:03.256847 == TX Byte 0 ==
6742 05:59:03.260302 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 05:59:03.263884 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 05:59:03.267279 == TX Byte 1 ==
6745 05:59:03.270458 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 05:59:03.273582 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 05:59:03.273662
6748 05:59:03.273726 [DATLAT]
6749 05:59:03.276845 Freq=400, CH1 RK0
6750 05:59:03.276926
6751 05:59:03.276990 DATLAT Default: 0xf
6752 05:59:03.280161 0, 0xFFFF, sum = 0
6753 05:59:03.280242 1, 0xFFFF, sum = 0
6754 05:59:03.283531 2, 0xFFFF, sum = 0
6755 05:59:03.286932 3, 0xFFFF, sum = 0
6756 05:59:03.287014 4, 0xFFFF, sum = 0
6757 05:59:03.290358 5, 0xFFFF, sum = 0
6758 05:59:03.290440 6, 0xFFFF, sum = 0
6759 05:59:03.293656 7, 0xFFFF, sum = 0
6760 05:59:03.293738 8, 0xFFFF, sum = 0
6761 05:59:03.296854 9, 0xFFFF, sum = 0
6762 05:59:03.296935 10, 0xFFFF, sum = 0
6763 05:59:03.300215 11, 0xFFFF, sum = 0
6764 05:59:03.300302 12, 0xFFFF, sum = 0
6765 05:59:03.303588 13, 0x0, sum = 1
6766 05:59:03.303670 14, 0x0, sum = 2
6767 05:59:03.307032 15, 0x0, sum = 3
6768 05:59:03.307114 16, 0x0, sum = 4
6769 05:59:03.307179 best_step = 14
6770 05:59:03.310310
6771 05:59:03.310390 ==
6772 05:59:03.313273 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 05:59:03.317086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 05:59:03.317168 ==
6775 05:59:03.317232 RX Vref Scan: 1
6776 05:59:03.317291
6777 05:59:03.320290 RX Vref 0 -> 0, step: 1
6778 05:59:03.320403
6779 05:59:03.323805 RX Delay -311 -> 252, step: 8
6780 05:59:03.323885
6781 05:59:03.326578 Set Vref, RX VrefLevel [Byte0]: 56
6782 05:59:03.329865 [Byte1]: 49
6783 05:59:03.333664
6784 05:59:03.333744 Final RX Vref Byte 0 = 56 to rank0
6785 05:59:03.337594 Final RX Vref Byte 1 = 49 to rank0
6786 05:59:03.340604 Final RX Vref Byte 0 = 56 to rank1
6787 05:59:03.343629 Final RX Vref Byte 1 = 49 to rank1==
6788 05:59:03.347248 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 05:59:03.354225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 05:59:03.354307 ==
6791 05:59:03.354371 DQS Delay:
6792 05:59:03.357104 DQS0 = 28, DQS1 = 32
6793 05:59:03.357185 DQM Delay:
6794 05:59:03.357249 DQM0 = 9, DQM1 = 12
6795 05:59:03.360634 DQ Delay:
6796 05:59:03.363421 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6797 05:59:03.363501 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6798 05:59:03.367027 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6799 05:59:03.370716 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6800 05:59:03.370798
6801 05:59:03.373435
6802 05:59:03.380262 [DQSOSCAuto] RK0, (LSB)MR18= 0x8dc6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6803 05:59:03.383548 CH1 RK0: MR19=C0C, MR18=8DC6
6804 05:59:03.390341 CH1_RK0: MR19=0xC0C, MR18=0x8DC6, DQSOSC=385, MR23=63, INC=398, DEC=265
6805 05:59:03.390422 ==
6806 05:59:03.393693 Dram Type= 6, Freq= 0, CH_1, rank 1
6807 05:59:03.396739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 05:59:03.396905 ==
6809 05:59:03.400190 [Gating] SW mode calibration
6810 05:59:03.406698 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6811 05:59:03.413511 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6812 05:59:03.417094 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 05:59:03.420562 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6814 05:59:03.423767 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 05:59:03.430047 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 05:59:03.433149 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 05:59:03.436583 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 05:59:03.443622 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 05:59:03.446984 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 05:59:03.449718 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 05:59:03.453591 Total UI for P1: 0, mck2ui 16
6822 05:59:03.456714 best dqsien dly found for B0: ( 0, 14, 24)
6823 05:59:03.460456 Total UI for P1: 0, mck2ui 16
6824 05:59:03.463077 best dqsien dly found for B1: ( 0, 14, 24)
6825 05:59:03.466675 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6826 05:59:03.473540 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6827 05:59:03.473620
6828 05:59:03.476491 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 05:59:03.480063 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6830 05:59:03.483498 [Gating] SW calibration Done
6831 05:59:03.483579 ==
6832 05:59:03.486209 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 05:59:03.489697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 05:59:03.489778 ==
6835 05:59:03.489842 RX Vref Scan: 0
6836 05:59:03.493227
6837 05:59:03.493306 RX Vref 0 -> 0, step: 1
6838 05:59:03.493370
6839 05:59:03.496393 RX Delay -410 -> 252, step: 16
6840 05:59:03.499531 iDelay=230, Bit 0, Center -3 (-234 ~ 229) 464
6841 05:59:03.506182 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6842 05:59:03.509577 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6843 05:59:03.512892 iDelay=230, Bit 3, Center -11 (-234 ~ 213) 448
6844 05:59:03.516065 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6845 05:59:03.522835 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6846 05:59:03.526259 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6847 05:59:03.529735 iDelay=230, Bit 7, Center -11 (-234 ~ 213) 448
6848 05:59:03.533196 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6849 05:59:03.539568 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6850 05:59:03.542552 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6851 05:59:03.546033 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6852 05:59:03.549546 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6853 05:59:03.555850 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6854 05:59:03.559346 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6855 05:59:03.562868 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6856 05:59:03.562949 ==
6857 05:59:03.566079 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 05:59:03.569831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 05:59:03.572999 ==
6860 05:59:03.573079 DQS Delay:
6861 05:59:03.573142 DQS0 = 35, DQS1 = 35
6862 05:59:03.576059 DQM Delay:
6863 05:59:03.576140 DQM0 = 23, DQM1 = 17
6864 05:59:03.579706 DQ Delay:
6865 05:59:03.579787 DQ0 =32, DQ1 =24, DQ2 =0, DQ3 =24
6866 05:59:03.582618 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =24
6867 05:59:03.586191 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6868 05:59:03.589120 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6869 05:59:03.589201
6870 05:59:03.589264
6871 05:59:03.592505 ==
6872 05:59:03.595933 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 05:59:03.599288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 05:59:03.599410 ==
6875 05:59:03.599511
6876 05:59:03.599603
6877 05:59:03.602826 TX Vref Scan disable
6878 05:59:03.602923 == TX Byte 0 ==
6879 05:59:03.606263 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6880 05:59:03.613013 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6881 05:59:03.613094 == TX Byte 1 ==
6882 05:59:03.616235 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6883 05:59:03.619200 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6884 05:59:03.622680 ==
6885 05:59:03.626322 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 05:59:03.629366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 05:59:03.629447 ==
6888 05:59:03.629511
6889 05:59:03.629570
6890 05:59:03.633073 TX Vref Scan disable
6891 05:59:03.633153 == TX Byte 0 ==
6892 05:59:03.635939 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6893 05:59:03.642462 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6894 05:59:03.642561 == TX Byte 1 ==
6895 05:59:03.646239 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6896 05:59:03.649644 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6897 05:59:03.652883
6898 05:59:03.652963 [DATLAT]
6899 05:59:03.653027 Freq=400, CH1 RK1
6900 05:59:03.653087
6901 05:59:03.656205 DATLAT Default: 0xe
6902 05:59:03.656311 0, 0xFFFF, sum = 0
6903 05:59:03.659722 1, 0xFFFF, sum = 0
6904 05:59:03.659803 2, 0xFFFF, sum = 0
6905 05:59:03.662542 3, 0xFFFF, sum = 0
6906 05:59:03.662641 4, 0xFFFF, sum = 0
6907 05:59:03.666055 5, 0xFFFF, sum = 0
6908 05:59:03.669678 6, 0xFFFF, sum = 0
6909 05:59:03.669760 7, 0xFFFF, sum = 0
6910 05:59:03.672266 8, 0xFFFF, sum = 0
6911 05:59:03.672394 9, 0xFFFF, sum = 0
6912 05:59:03.675699 10, 0xFFFF, sum = 0
6913 05:59:03.675795 11, 0xFFFF, sum = 0
6914 05:59:03.679159 12, 0xFFFF, sum = 0
6915 05:59:03.679241 13, 0x0, sum = 1
6916 05:59:03.682312 14, 0x0, sum = 2
6917 05:59:03.682394 15, 0x0, sum = 3
6918 05:59:03.685567 16, 0x0, sum = 4
6919 05:59:03.685649 best_step = 14
6920 05:59:03.685713
6921 05:59:03.685771 ==
6922 05:59:03.689596 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 05:59:03.692272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 05:59:03.692390 ==
6925 05:59:03.695863 RX Vref Scan: 0
6926 05:59:03.695943
6927 05:59:03.699332 RX Vref 0 -> 0, step: 1
6928 05:59:03.699427
6929 05:59:03.699490 RX Delay -311 -> 252, step: 8
6930 05:59:03.707526 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6931 05:59:03.711006 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6932 05:59:03.714459 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6933 05:59:03.717972 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6934 05:59:03.724761 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6935 05:59:03.727929 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6936 05:59:03.731151 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6937 05:59:03.734738 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6938 05:59:03.740973 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6939 05:59:03.744273 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6940 05:59:03.747592 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6941 05:59:03.750787 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6942 05:59:03.757801 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6943 05:59:03.761199 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6944 05:59:03.764551 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6945 05:59:03.767530 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6946 05:59:03.771342 ==
6947 05:59:03.774784 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 05:59:03.778212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 05:59:03.778293 ==
6950 05:59:03.778357 DQS Delay:
6951 05:59:03.781011 DQS0 = 28, DQS1 = 36
6952 05:59:03.781092 DQM Delay:
6953 05:59:03.784499 DQM0 = 11, DQM1 = 15
6954 05:59:03.784579 DQ Delay:
6955 05:59:03.788104 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6956 05:59:03.791403 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6957 05:59:03.794171 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =12
6958 05:59:03.797404 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6959 05:59:03.797484
6960 05:59:03.797547
6961 05:59:03.804254 [DQSOSCAuto] RK1, (LSB)MR18= 0xc153, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6962 05:59:03.807933 CH1 RK1: MR19=C0C, MR18=C153
6963 05:59:03.814106 CH1_RK1: MR19=0xC0C, MR18=0xC153, DQSOSC=385, MR23=63, INC=398, DEC=265
6964 05:59:03.817600 [RxdqsGatingPostProcess] freq 400
6965 05:59:03.821218 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6966 05:59:03.824169 best DQS0 dly(2T, 0.5T) = (0, 10)
6967 05:59:03.827521 best DQS1 dly(2T, 0.5T) = (0, 10)
6968 05:59:03.830883 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6969 05:59:03.834192 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6970 05:59:03.837537 best DQS0 dly(2T, 0.5T) = (0, 10)
6971 05:59:03.841041 best DQS1 dly(2T, 0.5T) = (0, 10)
6972 05:59:03.843913 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6973 05:59:03.847590 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6974 05:59:03.850376 Pre-setting of DQS Precalculation
6975 05:59:03.853907 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6976 05:59:03.863611 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6977 05:59:03.870236 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6978 05:59:03.870317
6979 05:59:03.870381
6980 05:59:03.873527 [Calibration Summary] 800 Mbps
6981 05:59:03.873607 CH 0, Rank 0
6982 05:59:03.877345 SW Impedance : PASS
6983 05:59:03.877439 DUTY Scan : NO K
6984 05:59:03.880411 ZQ Calibration : PASS
6985 05:59:03.883993 Jitter Meter : NO K
6986 05:59:03.884073 CBT Training : PASS
6987 05:59:03.886946 Write leveling : PASS
6988 05:59:03.890132 RX DQS gating : PASS
6989 05:59:03.890239 RX DQ/DQS(RDDQC) : PASS
6990 05:59:03.893858 TX DQ/DQS : PASS
6991 05:59:03.897099 RX DATLAT : PASS
6992 05:59:03.897205 RX DQ/DQS(Engine): PASS
6993 05:59:03.900787 TX OE : NO K
6994 05:59:03.900875 All Pass.
6995 05:59:03.900940
6996 05:59:03.903596 CH 0, Rank 1
6997 05:59:03.903674 SW Impedance : PASS
6998 05:59:03.907671 DUTY Scan : NO K
6999 05:59:03.910770 ZQ Calibration : PASS
7000 05:59:03.910840 Jitter Meter : NO K
7001 05:59:03.913920 CBT Training : PASS
7002 05:59:03.913990 Write leveling : NO K
7003 05:59:03.917156 RX DQS gating : PASS
7004 05:59:03.920552 RX DQ/DQS(RDDQC) : PASS
7005 05:59:03.920649 TX DQ/DQS : PASS
7006 05:59:03.924109 RX DATLAT : PASS
7007 05:59:03.927002 RX DQ/DQS(Engine): PASS
7008 05:59:03.927089 TX OE : NO K
7009 05:59:03.930681 All Pass.
7010 05:59:03.930752
7011 05:59:03.930826 CH 1, Rank 0
7012 05:59:03.933542 SW Impedance : PASS
7013 05:59:03.933618 DUTY Scan : NO K
7014 05:59:03.937163 ZQ Calibration : PASS
7015 05:59:03.940597 Jitter Meter : NO K
7016 05:59:03.940696 CBT Training : PASS
7017 05:59:03.943818 Write leveling : PASS
7018 05:59:03.947225 RX DQS gating : PASS
7019 05:59:03.947335 RX DQ/DQS(RDDQC) : PASS
7020 05:59:03.950147 TX DQ/DQS : PASS
7021 05:59:03.953779 RX DATLAT : PASS
7022 05:59:03.953860 RX DQ/DQS(Engine): PASS
7023 05:59:03.956763 TX OE : NO K
7024 05:59:03.956856 All Pass.
7025 05:59:03.956918
7026 05:59:03.960170 CH 1, Rank 1
7027 05:59:03.960248 SW Impedance : PASS
7028 05:59:03.963806 DUTY Scan : NO K
7029 05:59:03.966976 ZQ Calibration : PASS
7030 05:59:03.967048 Jitter Meter : NO K
7031 05:59:03.970606 CBT Training : PASS
7032 05:59:03.970694 Write leveling : NO K
7033 05:59:03.974018 RX DQS gating : PASS
7034 05:59:03.976722 RX DQ/DQS(RDDQC) : PASS
7035 05:59:03.976814 TX DQ/DQS : PASS
7036 05:59:03.980476 RX DATLAT : PASS
7037 05:59:03.983830 RX DQ/DQS(Engine): PASS
7038 05:59:03.983917 TX OE : NO K
7039 05:59:03.986703 All Pass.
7040 05:59:03.986835
7041 05:59:03.986924 DramC Write-DBI off
7042 05:59:03.990288 PER_BANK_REFRESH: Hybrid Mode
7043 05:59:03.990361 TX_TRACKING: ON
7044 05:59:04.000549 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7045 05:59:04.003482 [FAST_K] Save calibration result to emmc
7046 05:59:04.006966 dramc_set_vcore_voltage set vcore to 725000
7047 05:59:04.009867 Read voltage for 1600, 0
7048 05:59:04.009944 Vio18 = 0
7049 05:59:04.013669 Vcore = 725000
7050 05:59:04.013796 Vdram = 0
7051 05:59:04.013861 Vddq = 0
7052 05:59:04.017073 Vmddr = 0
7053 05:59:04.020484 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7054 05:59:04.027037 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7055 05:59:04.027121 MEM_TYPE=3, freq_sel=13
7056 05:59:04.030143 sv_algorithm_assistance_LP4_3733
7057 05:59:04.036811 ============ PULL DRAM RESETB DOWN ============
7058 05:59:04.040450 ========== PULL DRAM RESETB DOWN end =========
7059 05:59:04.043332 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7060 05:59:04.046765 ===================================
7061 05:59:04.050155 LPDDR4 DRAM CONFIGURATION
7062 05:59:04.053550 ===================================
7063 05:59:04.053634 EX_ROW_EN[0] = 0x0
7064 05:59:04.057128 EX_ROW_EN[1] = 0x0
7065 05:59:04.059897 LP4Y_EN = 0x0
7066 05:59:04.059979 WORK_FSP = 0x1
7067 05:59:04.063446 WL = 0x5
7068 05:59:04.063527 RL = 0x5
7069 05:59:04.067101 BL = 0x2
7070 05:59:04.067183 RPST = 0x0
7071 05:59:04.070004 RD_PRE = 0x0
7072 05:59:04.070086 WR_PRE = 0x1
7073 05:59:04.073664 WR_PST = 0x1
7074 05:59:04.073746 DBI_WR = 0x0
7075 05:59:04.076491 DBI_RD = 0x0
7076 05:59:04.076572 OTF = 0x1
7077 05:59:04.080157 ===================================
7078 05:59:04.083691 ===================================
7079 05:59:04.086463 ANA top config
7080 05:59:04.090157 ===================================
7081 05:59:04.090234 DLL_ASYNC_EN = 0
7082 05:59:04.092987 ALL_SLAVE_EN = 0
7083 05:59:04.096454 NEW_RANK_MODE = 1
7084 05:59:04.099788 DLL_IDLE_MODE = 1
7085 05:59:04.103437 LP45_APHY_COMB_EN = 1
7086 05:59:04.103504 TX_ODT_DIS = 0
7087 05:59:04.107063 NEW_8X_MODE = 1
7088 05:59:04.109790 ===================================
7089 05:59:04.113218 ===================================
7090 05:59:04.116614 data_rate = 3200
7091 05:59:04.119804 CKR = 1
7092 05:59:04.123333 DQ_P2S_RATIO = 8
7093 05:59:04.126497 ===================================
7094 05:59:04.126570 CA_P2S_RATIO = 8
7095 05:59:04.130101 DQ_CA_OPEN = 0
7096 05:59:04.133412 DQ_SEMI_OPEN = 0
7097 05:59:04.136682 CA_SEMI_OPEN = 0
7098 05:59:04.139828 CA_FULL_RATE = 0
7099 05:59:04.143779 DQ_CKDIV4_EN = 0
7100 05:59:04.143877 CA_CKDIV4_EN = 0
7101 05:59:04.146745 CA_PREDIV_EN = 0
7102 05:59:04.149785 PH8_DLY = 12
7103 05:59:04.153618 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7104 05:59:04.156544 DQ_AAMCK_DIV = 4
7105 05:59:04.156635 CA_AAMCK_DIV = 4
7106 05:59:04.160047 CA_ADMCK_DIV = 4
7107 05:59:04.163304 DQ_TRACK_CA_EN = 0
7108 05:59:04.166695 CA_PICK = 1600
7109 05:59:04.170235 CA_MCKIO = 1600
7110 05:59:04.173744 MCKIO_SEMI = 0
7111 05:59:04.176594 PLL_FREQ = 3068
7112 05:59:04.180310 DQ_UI_PI_RATIO = 32
7113 05:59:04.180414 CA_UI_PI_RATIO = 0
7114 05:59:04.183074 ===================================
7115 05:59:04.186968 ===================================
7116 05:59:04.189864 memory_type:LPDDR4
7117 05:59:04.193689 GP_NUM : 10
7118 05:59:04.193774 SRAM_EN : 1
7119 05:59:04.196640 MD32_EN : 0
7120 05:59:04.199651 ===================================
7121 05:59:04.203262 [ANA_INIT] >>>>>>>>>>>>>>
7122 05:59:04.206664 <<<<<< [CONFIGURE PHASE]: ANA_TX
7123 05:59:04.209545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7124 05:59:04.213117 ===================================
7125 05:59:04.213206 data_rate = 3200,PCW = 0X7600
7126 05:59:04.216008 ===================================
7127 05:59:04.219725 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7128 05:59:04.226270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 05:59:04.232727 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7130 05:59:04.236218 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7131 05:59:04.239551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7132 05:59:04.242941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7133 05:59:04.246017 [ANA_INIT] flow start
7134 05:59:04.249219 [ANA_INIT] PLL >>>>>>>>
7135 05:59:04.249318 [ANA_INIT] PLL <<<<<<<<
7136 05:59:04.253075 [ANA_INIT] MIDPI >>>>>>>>
7137 05:59:04.255711 [ANA_INIT] MIDPI <<<<<<<<
7138 05:59:04.255829 [ANA_INIT] DLL >>>>>>>>
7139 05:59:04.259129 [ANA_INIT] DLL <<<<<<<<
7140 05:59:04.262352 [ANA_INIT] flow end
7141 05:59:04.266115 ============ LP4 DIFF to SE enter ============
7142 05:59:04.269120 ============ LP4 DIFF to SE exit ============
7143 05:59:04.272913 [ANA_INIT] <<<<<<<<<<<<<
7144 05:59:04.275970 [Flow] Enable top DCM control >>>>>
7145 05:59:04.279467 [Flow] Enable top DCM control <<<<<
7146 05:59:04.282422 Enable DLL master slave shuffle
7147 05:59:04.286099 ==============================================================
7148 05:59:04.289438 Gating Mode config
7149 05:59:04.295764 ==============================================================
7150 05:59:04.295840 Config description:
7151 05:59:04.306213 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7152 05:59:04.312563 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7153 05:59:04.315511 SELPH_MODE 0: By rank 1: By Phase
7154 05:59:04.322428 ==============================================================
7155 05:59:04.325973 GAT_TRACK_EN = 1
7156 05:59:04.329276 RX_GATING_MODE = 2
7157 05:59:04.332197 RX_GATING_TRACK_MODE = 2
7158 05:59:04.335648 SELPH_MODE = 1
7159 05:59:04.339288 PICG_EARLY_EN = 1
7160 05:59:04.342733 VALID_LAT_VALUE = 1
7161 05:59:04.346064 ==============================================================
7162 05:59:04.348846 Enter into Gating configuration >>>>
7163 05:59:04.352742 Exit from Gating configuration <<<<
7164 05:59:04.356171 Enter into DVFS_PRE_config >>>>>
7165 05:59:04.365590 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7166 05:59:04.369195 Exit from DVFS_PRE_config <<<<<
7167 05:59:04.372463 Enter into PICG configuration >>>>
7168 05:59:04.375728 Exit from PICG configuration <<<<
7169 05:59:04.379127 [RX_INPUT] configuration >>>>>
7170 05:59:04.382692 [RX_INPUT] configuration <<<<<
7171 05:59:04.389079 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7172 05:59:04.392131 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7173 05:59:04.398896 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 05:59:04.405620 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 05:59:04.412586 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 05:59:04.418527 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 05:59:04.421906 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7178 05:59:04.425392 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7179 05:59:04.429004 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7180 05:59:04.435256 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7181 05:59:04.438514 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7182 05:59:04.442008 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7183 05:59:04.445646 ===================================
7184 05:59:04.448379 LPDDR4 DRAM CONFIGURATION
7185 05:59:04.451927 ===================================
7186 05:59:04.452001 EX_ROW_EN[0] = 0x0
7187 05:59:04.455419 EX_ROW_EN[1] = 0x0
7188 05:59:04.458733 LP4Y_EN = 0x0
7189 05:59:04.458801 WORK_FSP = 0x1
7190 05:59:04.462188 WL = 0x5
7191 05:59:04.462262 RL = 0x5
7192 05:59:04.464813 BL = 0x2
7193 05:59:04.464881 RPST = 0x0
7194 05:59:04.468587 RD_PRE = 0x0
7195 05:59:04.468658 WR_PRE = 0x1
7196 05:59:04.471570 WR_PST = 0x1
7197 05:59:04.471645 DBI_WR = 0x0
7198 05:59:04.474877 DBI_RD = 0x0
7199 05:59:04.474947 OTF = 0x1
7200 05:59:04.478081 ===================================
7201 05:59:04.482005 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7202 05:59:04.488179 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7203 05:59:04.491553 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7204 05:59:04.495139 ===================================
7205 05:59:04.498444 LPDDR4 DRAM CONFIGURATION
7206 05:59:04.501936 ===================================
7207 05:59:04.502004 EX_ROW_EN[0] = 0x10
7208 05:59:04.504709 EX_ROW_EN[1] = 0x0
7209 05:59:04.504777 LP4Y_EN = 0x0
7210 05:59:04.508108 WORK_FSP = 0x1
7211 05:59:04.511452 WL = 0x5
7212 05:59:04.511530 RL = 0x5
7213 05:59:04.515053 BL = 0x2
7214 05:59:04.515157 RPST = 0x0
7215 05:59:04.518407 RD_PRE = 0x0
7216 05:59:04.518477 WR_PRE = 0x1
7217 05:59:04.521706 WR_PST = 0x1
7218 05:59:04.521774 DBI_WR = 0x0
7219 05:59:04.524865 DBI_RD = 0x0
7220 05:59:04.524933 OTF = 0x1
7221 05:59:04.528216 ===================================
7222 05:59:04.534930 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7223 05:59:04.535004 ==
7224 05:59:04.538374 Dram Type= 6, Freq= 0, CH_0, rank 0
7225 05:59:04.541909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7226 05:59:04.541983 ==
7227 05:59:04.544641 [Duty_Offset_Calibration]
7228 05:59:04.547913 B0:2 B1:1 CA:1
7229 05:59:04.547983
7230 05:59:04.551469 [DutyScan_Calibration_Flow] k_type=0
7231 05:59:04.559897
7232 05:59:04.559965 ==CLK 0==
7233 05:59:04.563307 Final CLK duty delay cell = 0
7234 05:59:04.566224 [0] MAX Duty = 5156%(X100), DQS PI = 22
7235 05:59:04.569809 [0] MIN Duty = 4875%(X100), DQS PI = 62
7236 05:59:04.573236 [0] AVG Duty = 5015%(X100)
7237 05:59:04.573306
7238 05:59:04.576422 CH0 CLK Duty spec in!! Max-Min= 281%
7239 05:59:04.579775 [DutyScan_Calibration_Flow] ====Done====
7240 05:59:04.579850
7241 05:59:04.583147 [DutyScan_Calibration_Flow] k_type=1
7242 05:59:04.598937
7243 05:59:04.599011 ==DQS 0 ==
7244 05:59:04.602211 Final DQS duty delay cell = -4
7245 05:59:04.605561 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7246 05:59:04.609148 [-4] MIN Duty = 4688%(X100), DQS PI = 0
7247 05:59:04.611978 [-4] AVG Duty = 4922%(X100)
7248 05:59:04.612064
7249 05:59:04.612132 ==DQS 1 ==
7250 05:59:04.616019 Final DQS duty delay cell = 0
7251 05:59:04.619248 [0] MAX Duty = 5187%(X100), DQS PI = 20
7252 05:59:04.622050 [0] MIN Duty = 5031%(X100), DQS PI = 52
7253 05:59:04.625581 [0] AVG Duty = 5109%(X100)
7254 05:59:04.625656
7255 05:59:04.629196 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7256 05:59:04.629264
7257 05:59:04.632601 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7258 05:59:04.635181 [DutyScan_Calibration_Flow] ====Done====
7259 05:59:04.635250
7260 05:59:04.638467 [DutyScan_Calibration_Flow] k_type=3
7261 05:59:04.655700
7262 05:59:04.655776 ==DQM 0 ==
7263 05:59:04.659188 Final DQM duty delay cell = 0
7264 05:59:04.662597 [0] MAX Duty = 5187%(X100), DQS PI = 32
7265 05:59:04.665454 [0] MIN Duty = 4875%(X100), DQS PI = 60
7266 05:59:04.669211 [0] AVG Duty = 5031%(X100)
7267 05:59:04.669281
7268 05:59:04.669347 ==DQM 1 ==
7269 05:59:04.672745 Final DQM duty delay cell = -4
7270 05:59:04.675620 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7271 05:59:04.678998 [-4] MIN Duty = 4813%(X100), DQS PI = 12
7272 05:59:04.682239 [-4] AVG Duty = 4891%(X100)
7273 05:59:04.682308
7274 05:59:04.685502 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7275 05:59:04.685572
7276 05:59:04.688679 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7277 05:59:04.692165 [DutyScan_Calibration_Flow] ====Done====
7278 05:59:04.692262
7279 05:59:04.695578 [DutyScan_Calibration_Flow] k_type=2
7280 05:59:04.713198
7281 05:59:04.713276 ==DQ 0 ==
7282 05:59:04.716727 Final DQ duty delay cell = 0
7283 05:59:04.720188 [0] MAX Duty = 5062%(X100), DQS PI = 26
7284 05:59:04.723544 [0] MIN Duty = 4907%(X100), DQS PI = 0
7285 05:59:04.723620 [0] AVG Duty = 4984%(X100)
7286 05:59:04.723681
7287 05:59:04.727019 ==DQ 1 ==
7288 05:59:04.729697 Final DQ duty delay cell = 0
7289 05:59:04.733196 [0] MAX Duty = 5156%(X100), DQS PI = 22
7290 05:59:04.736636 [0] MIN Duty = 4907%(X100), DQS PI = 34
7291 05:59:04.736716 [0] AVG Duty = 5031%(X100)
7292 05:59:04.736779
7293 05:59:04.740118 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7294 05:59:04.743536
7295 05:59:04.746923 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7296 05:59:04.749631 [DutyScan_Calibration_Flow] ====Done====
7297 05:59:04.749698 ==
7298 05:59:04.753580 Dram Type= 6, Freq= 0, CH_1, rank 0
7299 05:59:04.756999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7300 05:59:04.757069 ==
7301 05:59:04.760015 [Duty_Offset_Calibration]
7302 05:59:04.760122 B0:1 B1:0 CA:0
7303 05:59:04.760207
7304 05:59:04.762975 [DutyScan_Calibration_Flow] k_type=0
7305 05:59:04.772557
7306 05:59:04.772630 ==CLK 0==
7307 05:59:04.776037 Final CLK duty delay cell = -4
7308 05:59:04.779608 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7309 05:59:04.782389 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7310 05:59:04.785910 [-4] AVG Duty = 4906%(X100)
7311 05:59:04.785982
7312 05:59:04.789298 CH1 CLK Duty spec in!! Max-Min= 125%
7313 05:59:04.792529 [DutyScan_Calibration_Flow] ====Done====
7314 05:59:04.792605
7315 05:59:04.795840 [DutyScan_Calibration_Flow] k_type=1
7316 05:59:04.812728
7317 05:59:04.812807 ==DQS 0 ==
7318 05:59:04.816221 Final DQS duty delay cell = 0
7319 05:59:04.819225 [0] MAX Duty = 5094%(X100), DQS PI = 28
7320 05:59:04.822667 [0] MIN Duty = 4844%(X100), DQS PI = 50
7321 05:59:04.826164 [0] AVG Duty = 4969%(X100)
7322 05:59:04.826233
7323 05:59:04.826292 ==DQS 1 ==
7324 05:59:04.829627 Final DQS duty delay cell = 0
7325 05:59:04.833056 [0] MAX Duty = 5249%(X100), DQS PI = 16
7326 05:59:04.836394 [0] MIN Duty = 4938%(X100), DQS PI = 8
7327 05:59:04.836467 [0] AVG Duty = 5093%(X100)
7328 05:59:04.839758
7329 05:59:04.842557 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7330 05:59:04.842633
7331 05:59:04.846077 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7332 05:59:04.849662 [DutyScan_Calibration_Flow] ====Done====
7333 05:59:04.849730
7334 05:59:04.852403 [DutyScan_Calibration_Flow] k_type=3
7335 05:59:04.869772
7336 05:59:04.869848 ==DQM 0 ==
7337 05:59:04.872990 Final DQM duty delay cell = 0
7338 05:59:04.876093 [0] MAX Duty = 5218%(X100), DQS PI = 18
7339 05:59:04.879896 [0] MIN Duty = 4969%(X100), DQS PI = 46
7340 05:59:04.883023 [0] AVG Duty = 5093%(X100)
7341 05:59:04.883096
7342 05:59:04.883157 ==DQM 1 ==
7343 05:59:04.886220 Final DQM duty delay cell = 0
7344 05:59:04.889634 [0] MAX Duty = 5093%(X100), DQS PI = 16
7345 05:59:04.893149 [0] MIN Duty = 4907%(X100), DQS PI = 50
7346 05:59:04.896090 [0] AVG Duty = 5000%(X100)
7347 05:59:04.896160
7348 05:59:04.899615 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7349 05:59:04.899683
7350 05:59:04.902910 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7351 05:59:04.906126 [DutyScan_Calibration_Flow] ====Done====
7352 05:59:04.906194
7353 05:59:04.909466 [DutyScan_Calibration_Flow] k_type=2
7354 05:59:04.925867
7355 05:59:04.925970 ==DQ 0 ==
7356 05:59:04.928881 Final DQ duty delay cell = -4
7357 05:59:04.932555 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7358 05:59:04.935767 [-4] MIN Duty = 4875%(X100), DQS PI = 44
7359 05:59:04.939235 [-4] AVG Duty = 4968%(X100)
7360 05:59:04.939307
7361 05:59:04.939374 ==DQ 1 ==
7362 05:59:04.942648 Final DQ duty delay cell = 0
7363 05:59:04.945770 [0] MAX Duty = 5156%(X100), DQS PI = 18
7364 05:59:04.949306 [0] MIN Duty = 4938%(X100), DQS PI = 8
7365 05:59:04.949385 [0] AVG Duty = 5047%(X100)
7366 05:59:04.952848
7367 05:59:04.955460 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7368 05:59:04.955527
7369 05:59:04.958981 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7370 05:59:04.962509 [DutyScan_Calibration_Flow] ====Done====
7371 05:59:04.965510 nWR fixed to 30
7372 05:59:04.965587 [ModeRegInit_LP4] CH0 RK0
7373 05:59:04.968995 [ModeRegInit_LP4] CH0 RK1
7374 05:59:04.972463 [ModeRegInit_LP4] CH1 RK0
7375 05:59:04.975311 [ModeRegInit_LP4] CH1 RK1
7376 05:59:04.975386 match AC timing 5
7377 05:59:04.982516 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7378 05:59:04.986005 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7379 05:59:04.988859 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7380 05:59:04.995721 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7381 05:59:04.998888 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7382 05:59:04.998966 [MiockJmeterHQA]
7383 05:59:04.999027
7384 05:59:05.001984 [DramcMiockJmeter] u1RxGatingPI = 0
7385 05:59:05.005883 0 : 4363, 4138
7386 05:59:05.005962 4 : 4252, 4027
7387 05:59:05.009131 8 : 4363, 4137
7388 05:59:05.009200 12 : 4252, 4027
7389 05:59:05.009268 16 : 4253, 4026
7390 05:59:05.012587 20 : 4253, 4026
7391 05:59:05.012656 24 : 4363, 4137
7392 05:59:05.015300 28 : 4252, 4027
7393 05:59:05.015424 32 : 4253, 4027
7394 05:59:05.018683 36 : 4255, 4029
7395 05:59:05.018794 40 : 4360, 4137
7396 05:59:05.018894 44 : 4253, 4026
7397 05:59:05.021801 48 : 4361, 4138
7398 05:59:05.021881 52 : 4250, 4027
7399 05:59:05.025790 56 : 4250, 4027
7400 05:59:05.025867 60 : 4249, 4027
7401 05:59:05.029036 64 : 4250, 4027
7402 05:59:05.029114 68 : 4361, 4138
7403 05:59:05.032213 72 : 4250, 4026
7404 05:59:05.032357 76 : 4361, 4137
7405 05:59:05.032456 80 : 4249, 4027
7406 05:59:05.035449 84 : 4252, 4029
7407 05:59:05.035530 88 : 4250, 136
7408 05:59:05.038713 92 : 4250, 0
7409 05:59:05.038814 96 : 4253, 0
7410 05:59:05.038902 100 : 4253, 0
7411 05:59:05.042012 104 : 4250, 0
7412 05:59:05.042104 108 : 4252, 0
7413 05:59:05.045321 112 : 4250, 0
7414 05:59:05.045418 116 : 4250, 0
7415 05:59:05.045505 120 : 4250, 0
7416 05:59:05.049274 124 : 4360, 0
7417 05:59:05.049369 128 : 4361, 0
7418 05:59:05.049462 132 : 4248, 0
7419 05:59:05.052431 136 : 4361, 0
7420 05:59:05.052535 140 : 4361, 0
7421 05:59:05.055764 144 : 4361, 0
7422 05:59:05.055857 148 : 4250, 0
7423 05:59:05.055944 152 : 4249, 0
7424 05:59:05.059203 156 : 4250, 0
7425 05:59:05.059277 160 : 4250, 0
7426 05:59:05.061929 164 : 4250, 0
7427 05:59:05.062026 168 : 4250, 0
7428 05:59:05.062113 172 : 4252, 0
7429 05:59:05.065403 176 : 4250, 0
7430 05:59:05.065533 180 : 4361, 0
7431 05:59:05.068828 184 : 4250, 0
7432 05:59:05.068913 188 : 4361, 0
7433 05:59:05.068983 192 : 4360, 0
7434 05:59:05.072201 196 : 4361, 0
7435 05:59:05.072308 200 : 4250, 0
7436 05:59:05.075896 204 : 4250, 1028
7437 05:59:05.075973 208 : 4250, 3928
7438 05:59:05.078671 212 : 4252, 4029
7439 05:59:05.078748 216 : 4250, 4027
7440 05:59:05.078808 220 : 4360, 4138
7441 05:59:05.082302 224 : 4360, 4137
7442 05:59:05.082370 228 : 4250, 4027
7443 05:59:05.085159 232 : 4361, 4137
7444 05:59:05.085232 236 : 4361, 4138
7445 05:59:05.088695 240 : 4250, 4027
7446 05:59:05.088809 244 : 4250, 4027
7447 05:59:05.092271 248 : 4250, 4027
7448 05:59:05.092380 252 : 4250, 4027
7449 05:59:05.095055 256 : 4250, 4027
7450 05:59:05.095123 260 : 4250, 4026
7451 05:59:05.098591 264 : 4250, 4027
7452 05:59:05.098659 268 : 4250, 4027
7453 05:59:05.102156 272 : 4361, 4138
7454 05:59:05.102231 276 : 4360, 4137
7455 05:59:05.102289 280 : 4250, 4027
7456 05:59:05.105501 284 : 4361, 4137
7457 05:59:05.105596 288 : 4361, 4138
7458 05:59:05.108643 292 : 4249, 4027
7459 05:59:05.108732 296 : 4250, 4027
7460 05:59:05.112044 300 : 4250, 4027
7461 05:59:05.112113 304 : 4250, 4027
7462 05:59:05.115673 308 : 4249, 3941
7463 05:59:05.115747 312 : 4250, 1972
7464 05:59:05.115807
7465 05:59:05.118448 MIOCK jitter meter ch=0
7466 05:59:05.118521
7467 05:59:05.122023 1T = (312-88) = 224 dly cells
7468 05:59:05.125343 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7469 05:59:05.128502 ==
7470 05:59:05.131745 Dram Type= 6, Freq= 0, CH_0, rank 0
7471 05:59:05.135168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7472 05:59:05.135277 ==
7473 05:59:05.138555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7474 05:59:05.145060 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7475 05:59:05.148228 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7476 05:59:05.154906 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7477 05:59:05.163752 [CA 0] Center 43 (12~74) winsize 63
7478 05:59:05.166991 [CA 1] Center 43 (13~74) winsize 62
7479 05:59:05.169813 [CA 2] Center 38 (9~68) winsize 60
7480 05:59:05.173303 [CA 3] Center 38 (8~68) winsize 61
7481 05:59:05.176903 [CA 4] Center 37 (7~67) winsize 61
7482 05:59:05.180238 [CA 5] Center 36 (7~65) winsize 59
7483 05:59:05.180361
7484 05:59:05.183168 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7485 05:59:05.183257
7486 05:59:05.186702 [CATrainingPosCal] consider 1 rank data
7487 05:59:05.190292 u2DelayCellTimex100 = 290/100 ps
7488 05:59:05.193089 CA0 delay=43 (12~74),Diff = 7 PI (23 cell)
7489 05:59:05.199952 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7490 05:59:05.203523 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7491 05:59:05.206397 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7492 05:59:05.209824 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7493 05:59:05.213277 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7494 05:59:05.213358
7495 05:59:05.216726 CA PerBit enable=1, Macro0, CA PI delay=36
7496 05:59:05.216806
7497 05:59:05.220194 [CBTSetCACLKResult] CA Dly = 36
7498 05:59:05.223064 CS Dly: 9 (0~40)
7499 05:59:05.226333 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7500 05:59:05.229839 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7501 05:59:05.229917 ==
7502 05:59:05.233051 Dram Type= 6, Freq= 0, CH_0, rank 1
7503 05:59:05.236239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 05:59:05.236349 ==
7505 05:59:05.242904 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 05:59:05.246501 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 05:59:05.253335 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 05:59:05.256521 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 05:59:05.266433 [CA 0] Center 42 (12~72) winsize 61
7510 05:59:05.269792 [CA 1] Center 42 (12~73) winsize 62
7511 05:59:05.273051 [CA 2] Center 38 (8~68) winsize 61
7512 05:59:05.276241 [CA 3] Center 38 (8~68) winsize 61
7513 05:59:05.279934 [CA 4] Center 35 (6~65) winsize 60
7514 05:59:05.283269 [CA 5] Center 35 (5~65) winsize 61
7515 05:59:05.283373
7516 05:59:05.286701 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7517 05:59:05.286780
7518 05:59:05.290240 [CATrainingPosCal] consider 2 rank data
7519 05:59:05.293104 u2DelayCellTimex100 = 290/100 ps
7520 05:59:05.296606 CA0 delay=42 (12~72),Diff = 6 PI (20 cell)
7521 05:59:05.302920 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7522 05:59:05.306473 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7523 05:59:05.309317 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7524 05:59:05.312893 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7525 05:59:05.316248 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7526 05:59:05.316399
7527 05:59:05.319842 CA PerBit enable=1, Macro0, CA PI delay=36
7528 05:59:05.319916
7529 05:59:05.323221 [CBTSetCACLKResult] CA Dly = 36
7530 05:59:05.326177 CS Dly: 10 (0~42)
7531 05:59:05.329758 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 05:59:05.333180 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 05:59:05.333286
7534 05:59:05.335930 ----->DramcWriteLeveling(PI) begin...
7535 05:59:05.336003 ==
7536 05:59:05.339605 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 05:59:05.346622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 05:59:05.346697 ==
7539 05:59:05.349853 Write leveling (Byte 0): 36 => 36
7540 05:59:05.349928 Write leveling (Byte 1): 26 => 26
7541 05:59:05.353164 DramcWriteLeveling(PI) end<-----
7542 05:59:05.353235
7543 05:59:05.353295 ==
7544 05:59:05.356497 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 05:59:05.363062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 05:59:05.363144 ==
7547 05:59:05.366127 [Gating] SW mode calibration
7548 05:59:05.372804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7549 05:59:05.375740 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7550 05:59:05.382444 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 05:59:05.386008 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 05:59:05.389461 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7553 05:59:05.395600 1 4 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7554 05:59:05.399135 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7555 05:59:05.402766 1 4 20 | B1->B0 | 3232 3636 | 0 0 | (1 1) (0 0)
7556 05:59:05.408967 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7557 05:59:05.412460 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7558 05:59:05.415976 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7559 05:59:05.422614 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 05:59:05.426220 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7561 05:59:05.428925 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7562 05:59:05.432567 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0)
7563 05:59:05.438959 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 05:59:05.442380 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7565 05:59:05.445906 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 05:59:05.452506 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 05:59:05.455757 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7568 05:59:05.459253 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7569 05:59:05.465526 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7570 05:59:05.468774 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7571 05:59:05.472129 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7572 05:59:05.479177 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 05:59:05.482480 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 05:59:05.485759 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 05:59:05.492195 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 05:59:05.495592 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 05:59:05.498813 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7578 05:59:05.505852 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7579 05:59:05.509048 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7580 05:59:05.512378 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 05:59:05.518794 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 05:59:05.522460 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 05:59:05.525448 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 05:59:05.532551 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 05:59:05.535235 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 05:59:05.538806 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 05:59:05.545693 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 05:59:05.548404 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 05:59:05.551925 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 05:59:05.558781 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 05:59:05.562342 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 05:59:05.565115 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 05:59:05.568730 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 05:59:05.575431 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7595 05:59:05.578593 Total UI for P1: 0, mck2ui 16
7596 05:59:05.581932 best dqsien dly found for B0: ( 1, 9, 12)
7597 05:59:05.585512 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7598 05:59:05.588377 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 05:59:05.591995 Total UI for P1: 0, mck2ui 16
7600 05:59:05.595515 best dqsien dly found for B1: ( 1, 9, 18)
7601 05:59:05.598869 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7602 05:59:05.602219 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7603 05:59:05.605664
7604 05:59:05.608845 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7605 05:59:05.612176 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7606 05:59:05.614951 [Gating] SW calibration Done
7607 05:59:05.615030 ==
7608 05:59:05.618547 Dram Type= 6, Freq= 0, CH_0, rank 0
7609 05:59:05.621914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7610 05:59:05.622013 ==
7611 05:59:05.625331 RX Vref Scan: 0
7612 05:59:05.625425
7613 05:59:05.625513 RX Vref 0 -> 0, step: 1
7614 05:59:05.625577
7615 05:59:05.628062 RX Delay 0 -> 252, step: 8
7616 05:59:05.631756 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7617 05:59:05.634861 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7618 05:59:05.641382 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7619 05:59:05.645178 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7620 05:59:05.648121 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7621 05:59:05.651718 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7622 05:59:05.655181 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7623 05:59:05.661518 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7624 05:59:05.665083 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7625 05:59:05.668492 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7626 05:59:05.672021 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7627 05:59:05.674835 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7628 05:59:05.681890 iDelay=200, Bit 12, Center 135 (88 ~ 183) 96
7629 05:59:05.685036 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7630 05:59:05.688064 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7631 05:59:05.692009 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7632 05:59:05.692112 ==
7633 05:59:05.694819 Dram Type= 6, Freq= 0, CH_0, rank 0
7634 05:59:05.698363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 05:59:05.701988 ==
7636 05:59:05.702083 DQS Delay:
7637 05:59:05.702169 DQS0 = 0, DQS1 = 0
7638 05:59:05.704735 DQM Delay:
7639 05:59:05.704807 DQM0 = 137, DQM1 = 130
7640 05:59:05.708201 DQ Delay:
7641 05:59:05.711758 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7642 05:59:05.715115 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7643 05:59:05.718392 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7644 05:59:05.721620 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7645 05:59:05.721743
7646 05:59:05.721803
7647 05:59:05.721860 ==
7648 05:59:05.724773 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 05:59:05.728076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 05:59:05.728156 ==
7651 05:59:05.731574
7652 05:59:05.731672
7653 05:59:05.731768 TX Vref Scan disable
7654 05:59:05.734477 == TX Byte 0 ==
7655 05:59:05.738497 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7656 05:59:05.741157 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7657 05:59:05.744527 == TX Byte 1 ==
7658 05:59:05.747910 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7659 05:59:05.751315 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7660 05:59:05.751414 ==
7661 05:59:05.754559 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 05:59:05.761317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 05:59:05.761397 ==
7664 05:59:05.773017
7665 05:59:05.776498 TX Vref early break, caculate TX vref
7666 05:59:05.779275 TX Vref=16, minBit 0, minWin=23, winSum=378
7667 05:59:05.782765 TX Vref=18, minBit 0, minWin=23, winSum=387
7668 05:59:05.786295 TX Vref=20, minBit 0, minWin=24, winSum=399
7669 05:59:05.789057 TX Vref=22, minBit 3, minWin=24, winSum=409
7670 05:59:05.792468 TX Vref=24, minBit 7, minWin=24, winSum=414
7671 05:59:05.799171 TX Vref=26, minBit 2, minWin=24, winSum=424
7672 05:59:05.802434 TX Vref=28, minBit 2, minWin=25, winSum=423
7673 05:59:05.805943 TX Vref=30, minBit 0, minWin=25, winSum=415
7674 05:59:05.809167 TX Vref=32, minBit 6, minWin=23, winSum=401
7675 05:59:05.815965 [TxChooseVref] Worse bit 2, Min win 25, Win sum 423, Final Vref 28
7676 05:59:05.816045
7677 05:59:05.819396 Final TX Range 0 Vref 28
7678 05:59:05.819501
7679 05:59:05.819593 ==
7680 05:59:05.822185 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 05:59:05.825545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 05:59:05.825632 ==
7683 05:59:05.825724
7684 05:59:05.825813
7685 05:59:05.829435 TX Vref Scan disable
7686 05:59:05.835949 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7687 05:59:05.836053 == TX Byte 0 ==
7688 05:59:05.839154 u2DelayCellOfst[0]=10 cells (3 PI)
7689 05:59:05.842630 u2DelayCellOfst[1]=13 cells (4 PI)
7690 05:59:05.845933 u2DelayCellOfst[2]=10 cells (3 PI)
7691 05:59:05.849182 u2DelayCellOfst[3]=10 cells (3 PI)
7692 05:59:05.852040 u2DelayCellOfst[4]=6 cells (2 PI)
7693 05:59:05.855425 u2DelayCellOfst[5]=0 cells (0 PI)
7694 05:59:05.858744 u2DelayCellOfst[6]=16 cells (5 PI)
7695 05:59:05.858823 u2DelayCellOfst[7]=13 cells (4 PI)
7696 05:59:05.865592 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7697 05:59:05.868847 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7698 05:59:05.868926 == TX Byte 1 ==
7699 05:59:05.872497 u2DelayCellOfst[8]=3 cells (1 PI)
7700 05:59:05.875646 u2DelayCellOfst[9]=0 cells (0 PI)
7701 05:59:05.878943 u2DelayCellOfst[10]=10 cells (3 PI)
7702 05:59:05.882282 u2DelayCellOfst[11]=6 cells (2 PI)
7703 05:59:05.885875 u2DelayCellOfst[12]=10 cells (3 PI)
7704 05:59:05.888658 u2DelayCellOfst[13]=10 cells (3 PI)
7705 05:59:05.892106 u2DelayCellOfst[14]=16 cells (5 PI)
7706 05:59:05.895604 u2DelayCellOfst[15]=10 cells (3 PI)
7707 05:59:05.899001 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7708 05:59:05.902381 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7709 05:59:05.905580 DramC Write-DBI on
7710 05:59:05.905661 ==
7711 05:59:05.908778 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 05:59:05.912617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 05:59:05.912697 ==
7714 05:59:05.912759
7715 05:59:05.915878
7716 05:59:05.915955 TX Vref Scan disable
7717 05:59:05.919265 == TX Byte 0 ==
7718 05:59:05.921916 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7719 05:59:05.925426 == TX Byte 1 ==
7720 05:59:05.928918 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7721 05:59:05.928998 DramC Write-DBI off
7722 05:59:05.929061
7723 05:59:05.932121 [DATLAT]
7724 05:59:05.932224 Freq=1600, CH0 RK0
7725 05:59:05.932355
7726 05:59:05.935446 DATLAT Default: 0xf
7727 05:59:05.935524 0, 0xFFFF, sum = 0
7728 05:59:05.938902 1, 0xFFFF, sum = 0
7729 05:59:05.938983 2, 0xFFFF, sum = 0
7730 05:59:05.942274 3, 0xFFFF, sum = 0
7731 05:59:05.942354 4, 0xFFFF, sum = 0
7732 05:59:05.945420 5, 0xFFFF, sum = 0
7733 05:59:05.948619 6, 0xFFFF, sum = 0
7734 05:59:05.948699 7, 0xFFFF, sum = 0
7735 05:59:05.951817 8, 0xFFFF, sum = 0
7736 05:59:05.951910 9, 0xFFFF, sum = 0
7737 05:59:05.955140 10, 0xFFFF, sum = 0
7738 05:59:05.955220 11, 0xFFFF, sum = 0
7739 05:59:05.958464 12, 0xFFFF, sum = 0
7740 05:59:05.958544 13, 0xFFFF, sum = 0
7741 05:59:05.962154 14, 0x0, sum = 1
7742 05:59:05.962246 15, 0x0, sum = 2
7743 05:59:05.965452 16, 0x0, sum = 3
7744 05:59:05.965532 17, 0x0, sum = 4
7745 05:59:05.968968 best_step = 15
7746 05:59:05.969047
7747 05:59:05.969108 ==
7748 05:59:05.971633 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 05:59:05.975015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 05:59:05.975095 ==
7751 05:59:05.975157 RX Vref Scan: 1
7752 05:59:05.978423
7753 05:59:05.978501 Set Vref Range= 24 -> 127
7754 05:59:05.978563
7755 05:59:05.981618 RX Vref 24 -> 127, step: 1
7756 05:59:05.981697
7757 05:59:05.985386 RX Delay 27 -> 252, step: 4
7758 05:59:05.985467
7759 05:59:05.988420 Set Vref, RX VrefLevel [Byte0]: 24
7760 05:59:05.991816 [Byte1]: 24
7761 05:59:05.991887
7762 05:59:05.995222 Set Vref, RX VrefLevel [Byte0]: 25
7763 05:59:05.998630 [Byte1]: 25
7764 05:59:05.998706
7765 05:59:06.002011 Set Vref, RX VrefLevel [Byte0]: 26
7766 05:59:06.004811 [Byte1]: 26
7767 05:59:06.009081
7768 05:59:06.009150 Set Vref, RX VrefLevel [Byte0]: 27
7769 05:59:06.011802 [Byte1]: 27
7770 05:59:06.016278
7771 05:59:06.016386 Set Vref, RX VrefLevel [Byte0]: 28
7772 05:59:06.019468 [Byte1]: 28
7773 05:59:06.023803
7774 05:59:06.023878 Set Vref, RX VrefLevel [Byte0]: 29
7775 05:59:06.027147 [Byte1]: 29
7776 05:59:06.031219
7777 05:59:06.031288 Set Vref, RX VrefLevel [Byte0]: 30
7778 05:59:06.034942 [Byte1]: 30
7779 05:59:06.038736
7780 05:59:06.038807 Set Vref, RX VrefLevel [Byte0]: 31
7781 05:59:06.042027 [Byte1]: 31
7782 05:59:06.046131
7783 05:59:06.046207 Set Vref, RX VrefLevel [Byte0]: 32
7784 05:59:06.049526 [Byte1]: 32
7785 05:59:06.054173
7786 05:59:06.054250 Set Vref, RX VrefLevel [Byte0]: 33
7787 05:59:06.057426 [Byte1]: 33
7788 05:59:06.061198
7789 05:59:06.061271 Set Vref, RX VrefLevel [Byte0]: 34
7790 05:59:06.064622 [Byte1]: 34
7791 05:59:06.069282
7792 05:59:06.069352 Set Vref, RX VrefLevel [Byte0]: 35
7793 05:59:06.072471 [Byte1]: 35
7794 05:59:06.076502
7795 05:59:06.076582 Set Vref, RX VrefLevel [Byte0]: 36
7796 05:59:06.080015 [Byte1]: 36
7797 05:59:06.084132
7798 05:59:06.084212 Set Vref, RX VrefLevel [Byte0]: 37
7799 05:59:06.087657 [Byte1]: 37
7800 05:59:06.091547
7801 05:59:06.091629 Set Vref, RX VrefLevel [Byte0]: 38
7802 05:59:06.094894 [Byte1]: 38
7803 05:59:06.099176
7804 05:59:06.099256 Set Vref, RX VrefLevel [Byte0]: 39
7805 05:59:06.102370 [Byte1]: 39
7806 05:59:06.106417
7807 05:59:06.106497 Set Vref, RX VrefLevel [Byte0]: 40
7808 05:59:06.109779 [Byte1]: 40
7809 05:59:06.113950
7810 05:59:06.114029 Set Vref, RX VrefLevel [Byte0]: 41
7811 05:59:06.117426 [Byte1]: 41
7812 05:59:06.122139
7813 05:59:06.122222 Set Vref, RX VrefLevel [Byte0]: 42
7814 05:59:06.124820 [Byte1]: 42
7815 05:59:06.129469
7816 05:59:06.129552 Set Vref, RX VrefLevel [Byte0]: 43
7817 05:59:06.132444 [Byte1]: 43
7818 05:59:06.137072
7819 05:59:06.137180 Set Vref, RX VrefLevel [Byte0]: 44
7820 05:59:06.140574 [Byte1]: 44
7821 05:59:06.144600
7822 05:59:06.144680 Set Vref, RX VrefLevel [Byte0]: 45
7823 05:59:06.147749 [Byte1]: 45
7824 05:59:06.151693
7825 05:59:06.151773 Set Vref, RX VrefLevel [Byte0]: 46
7826 05:59:06.155064 [Byte1]: 46
7827 05:59:06.159133
7828 05:59:06.159239 Set Vref, RX VrefLevel [Byte0]: 47
7829 05:59:06.162546 [Byte1]: 47
7830 05:59:06.167012
7831 05:59:06.167091 Set Vref, RX VrefLevel [Byte0]: 48
7832 05:59:06.170331 [Byte1]: 48
7833 05:59:06.174458
7834 05:59:06.174534 Set Vref, RX VrefLevel [Byte0]: 49
7835 05:59:06.177877 [Byte1]: 49
7836 05:59:06.181679
7837 05:59:06.181760 Set Vref, RX VrefLevel [Byte0]: 50
7838 05:59:06.185159 [Byte1]: 50
7839 05:59:06.189303
7840 05:59:06.189376 Set Vref, RX VrefLevel [Byte0]: 51
7841 05:59:06.192780 [Byte1]: 51
7842 05:59:06.197027
7843 05:59:06.197101 Set Vref, RX VrefLevel [Byte0]: 52
7844 05:59:06.200453 [Byte1]: 52
7845 05:59:06.204524
7846 05:59:06.204597 Set Vref, RX VrefLevel [Byte0]: 53
7847 05:59:06.207850 [Byte1]: 53
7848 05:59:06.212408
7849 05:59:06.212490 Set Vref, RX VrefLevel [Byte0]: 54
7850 05:59:06.215614 [Byte1]: 54
7851 05:59:06.219962
7852 05:59:06.220037 Set Vref, RX VrefLevel [Byte0]: 55
7853 05:59:06.223031 [Byte1]: 55
7854 05:59:06.227271
7855 05:59:06.227344 Set Vref, RX VrefLevel [Byte0]: 56
7856 05:59:06.230607 [Byte1]: 56
7857 05:59:06.234749
7858 05:59:06.234852 Set Vref, RX VrefLevel [Byte0]: 57
7859 05:59:06.238006 [Byte1]: 57
7860 05:59:06.242417
7861 05:59:06.242497 Set Vref, RX VrefLevel [Byte0]: 58
7862 05:59:06.245907 [Byte1]: 58
7863 05:59:06.250076
7864 05:59:06.250158 Set Vref, RX VrefLevel [Byte0]: 59
7865 05:59:06.252773 [Byte1]: 59
7866 05:59:06.257174
7867 05:59:06.257256 Set Vref, RX VrefLevel [Byte0]: 60
7868 05:59:06.260629 [Byte1]: 60
7869 05:59:06.264846
7870 05:59:06.264927 Set Vref, RX VrefLevel [Byte0]: 61
7871 05:59:06.268178 [Byte1]: 61
7872 05:59:06.272250
7873 05:59:06.272378 Set Vref, RX VrefLevel [Byte0]: 62
7874 05:59:06.275749 [Byte1]: 62
7875 05:59:06.279769
7876 05:59:06.279843 Set Vref, RX VrefLevel [Byte0]: 63
7877 05:59:06.283089 [Byte1]: 63
7878 05:59:06.287706
7879 05:59:06.287784 Set Vref, RX VrefLevel [Byte0]: 64
7880 05:59:06.291095 [Byte1]: 64
7881 05:59:06.295220
7882 05:59:06.295294 Set Vref, RX VrefLevel [Byte0]: 65
7883 05:59:06.298013 [Byte1]: 65
7884 05:59:06.302253
7885 05:59:06.302326 Set Vref, RX VrefLevel [Byte0]: 66
7886 05:59:06.305725 [Byte1]: 66
7887 05:59:06.309986
7888 05:59:06.310059 Set Vref, RX VrefLevel [Byte0]: 67
7889 05:59:06.313459 [Byte1]: 67
7890 05:59:06.317587
7891 05:59:06.317662 Set Vref, RX VrefLevel [Byte0]: 68
7892 05:59:06.321043 [Byte1]: 68
7893 05:59:06.325123
7894 05:59:06.325203 Set Vref, RX VrefLevel [Byte0]: 69
7895 05:59:06.328565 [Byte1]: 69
7896 05:59:06.332671
7897 05:59:06.332751 Set Vref, RX VrefLevel [Byte0]: 70
7898 05:59:06.336086 [Byte1]: 70
7899 05:59:06.340003
7900 05:59:06.340077 Set Vref, RX VrefLevel [Byte0]: 71
7901 05:59:06.343817 [Byte1]: 71
7902 05:59:06.347412
7903 05:59:06.347490 Set Vref, RX VrefLevel [Byte0]: 72
7904 05:59:06.350940 [Byte1]: 72
7905 05:59:06.355021
7906 05:59:06.355096 Set Vref, RX VrefLevel [Byte0]: 73
7907 05:59:06.358465 [Byte1]: 73
7908 05:59:06.362638
7909 05:59:06.362721 Set Vref, RX VrefLevel [Byte0]: 74
7910 05:59:06.365837 [Byte1]: 74
7911 05:59:06.370508
7912 05:59:06.370584 Set Vref, RX VrefLevel [Byte0]: 75
7913 05:59:06.373838 [Byte1]: 75
7914 05:59:06.377779
7915 05:59:06.377855 Final RX Vref Byte 0 = 61 to rank0
7916 05:59:06.381150 Final RX Vref Byte 1 = 65 to rank0
7917 05:59:06.384470 Final RX Vref Byte 0 = 61 to rank1
7918 05:59:06.388040 Final RX Vref Byte 1 = 65 to rank1==
7919 05:59:06.390834 Dram Type= 6, Freq= 0, CH_0, rank 0
7920 05:59:06.397833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7921 05:59:06.397912 ==
7922 05:59:06.397999 DQS Delay:
7923 05:59:06.398077 DQS0 = 0, DQS1 = 0
7924 05:59:06.401264 DQM Delay:
7925 05:59:06.401335 DQM0 = 134, DQM1 = 127
7926 05:59:06.404223 DQ Delay:
7927 05:59:06.407572 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7928 05:59:06.410986 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7929 05:59:06.414589 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7930 05:59:06.418005 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7931 05:59:06.418079
7932 05:59:06.418158
7933 05:59:06.418238
7934 05:59:06.421399 [DramC_TX_OE_Calibration] TA2
7935 05:59:06.424245 Original DQ_B0 (3 6) =30, OEN = 27
7936 05:59:06.427647 Original DQ_B1 (3 6) =30, OEN = 27
7937 05:59:06.430829 24, 0x0, End_B0=24 End_B1=24
7938 05:59:06.430901 25, 0x0, End_B0=25 End_B1=25
7939 05:59:06.434117 26, 0x0, End_B0=26 End_B1=26
7940 05:59:06.437971 27, 0x0, End_B0=27 End_B1=27
7941 05:59:06.440861 28, 0x0, End_B0=28 End_B1=28
7942 05:59:06.440941 29, 0x0, End_B0=29 End_B1=29
7943 05:59:06.444243 30, 0x0, End_B0=30 End_B1=30
7944 05:59:06.447716 31, 0x4141, End_B0=30 End_B1=30
7945 05:59:06.451069 Byte0 end_step=30 best_step=27
7946 05:59:06.454470 Byte1 end_step=30 best_step=27
7947 05:59:06.457767 Byte0 TX OE(2T, 0.5T) = (3, 3)
7948 05:59:06.457838 Byte1 TX OE(2T, 0.5T) = (3, 3)
7949 05:59:06.461154
7950 05:59:06.461224
7951 05:59:06.467552 [DQSOSCAuto] RK0, (LSB)MR18= 0x221d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 392 ps
7952 05:59:06.470657 CH0 RK0: MR19=303, MR18=221D
7953 05:59:06.477476 CH0_RK0: MR19=0x303, MR18=0x221D, DQSOSC=392, MR23=63, INC=24, DEC=16
7954 05:59:06.477551
7955 05:59:06.480642 ----->DramcWriteLeveling(PI) begin...
7956 05:59:06.480714 ==
7957 05:59:06.483998 Dram Type= 6, Freq= 0, CH_0, rank 1
7958 05:59:06.487236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7959 05:59:06.487309 ==
7960 05:59:06.490862 Write leveling (Byte 0): 35 => 35
7961 05:59:06.494039 Write leveling (Byte 1): 27 => 27
7962 05:59:06.497320 DramcWriteLeveling(PI) end<-----
7963 05:59:06.497395
7964 05:59:06.497457 ==
7965 05:59:06.501170 Dram Type= 6, Freq= 0, CH_0, rank 1
7966 05:59:06.504250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 05:59:06.504363 ==
7968 05:59:06.507307 [Gating] SW mode calibration
7969 05:59:06.514238 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7970 05:59:06.520425 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7971 05:59:06.523760 1 4 0 | B1->B0 | 2323 1919 | 0 1 | (0 0) (0 0)
7972 05:59:06.527239 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7973 05:59:06.534526 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7974 05:59:06.537306 1 4 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
7975 05:59:06.540758 1 4 16 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7976 05:59:06.547370 1 4 20 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7977 05:59:06.550995 1 4 24 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7978 05:59:06.553760 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7979 05:59:06.560684 1 5 0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7980 05:59:06.563680 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7981 05:59:06.567108 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7982 05:59:06.573920 1 5 12 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 1)
7983 05:59:06.576815 1 5 16 | B1->B0 | 2f2f 2b2b | 0 0 | (0 1) (1 0)
7984 05:59:06.580391 1 5 20 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7985 05:59:06.587198 1 5 24 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (1 1)
7986 05:59:06.589938 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7987 05:59:06.593806 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7988 05:59:06.600245 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 05:59:06.603740 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7990 05:59:06.606575 1 6 12 | B1->B0 | 2424 3433 | 0 1 | (0 0) (1 1)
7991 05:59:06.613574 1 6 16 | B1->B0 | 3f3f 4545 | 1 1 | (0 0) (0 0)
7992 05:59:06.617102 1 6 20 | B1->B0 | 4646 4646 | 0 1 | (0 0) (0 0)
7993 05:59:06.620600 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 05:59:06.627003 1 6 28 | B1->B0 | 4646 4646 | 0 1 | (0 0) (0 0)
7995 05:59:06.630266 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 05:59:06.633806 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 05:59:06.637217 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 05:59:06.643860 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7999 05:59:06.647346 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 05:59:06.650517 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 05:59:06.656636 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 05:59:06.660127 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 05:59:06.663855 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 05:59:06.670149 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 05:59:06.673536 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 05:59:06.676973 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 05:59:06.683140 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 05:59:06.686484 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 05:59:06.689925 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 05:59:06.696973 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 05:59:06.699744 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 05:59:06.703300 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 05:59:06.709613 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 05:59:06.713096 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8015 05:59:06.716389 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 05:59:06.720199 Total UI for P1: 0, mck2ui 16
8017 05:59:06.722844 best dqsien dly found for B0: ( 1, 9, 12)
8018 05:59:06.726669 Total UI for P1: 0, mck2ui 16
8019 05:59:06.729869 best dqsien dly found for B1: ( 1, 9, 12)
8020 05:59:06.733476 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8021 05:59:06.736330 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8022 05:59:06.736421
8023 05:59:06.743372 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8024 05:59:06.746216 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8025 05:59:06.749741 [Gating] SW calibration Done
8026 05:59:06.749825 ==
8027 05:59:06.752891 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 05:59:06.756031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 05:59:06.756104 ==
8030 05:59:06.756165 RX Vref Scan: 0
8031 05:59:06.756226
8032 05:59:06.760122 RX Vref 0 -> 0, step: 1
8033 05:59:06.760229
8034 05:59:06.763476 RX Delay 0 -> 252, step: 8
8035 05:59:06.766206 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8036 05:59:06.769796 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8037 05:59:06.773335 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8038 05:59:06.779651 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8039 05:59:06.783148 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8040 05:59:06.786529 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8041 05:59:06.790007 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8042 05:59:06.792695 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8043 05:59:06.799870 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8044 05:59:06.803252 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8045 05:59:06.806122 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8046 05:59:06.809648 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8047 05:59:06.813206 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8048 05:59:06.819531 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8049 05:59:06.822880 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8050 05:59:06.826220 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8051 05:59:06.826291 ==
8052 05:59:06.829772 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 05:59:06.832517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 05:59:06.836220 ==
8055 05:59:06.836350 DQS Delay:
8056 05:59:06.836446 DQS0 = 0, DQS1 = 0
8057 05:59:06.839742 DQM Delay:
8058 05:59:06.839816 DQM0 = 137, DQM1 = 131
8059 05:59:06.842507 DQ Delay:
8060 05:59:06.845783 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8061 05:59:06.849402 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8062 05:59:06.852745 DQ8 =123, DQ9 =119, DQ10 =131, DQ11 =123
8063 05:59:06.855969 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8064 05:59:06.856036
8065 05:59:06.856097
8066 05:59:06.856153 ==
8067 05:59:06.859064 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 05:59:06.862642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 05:59:06.862711 ==
8070 05:59:06.862768
8071 05:59:06.866177
8072 05:59:06.866242 TX Vref Scan disable
8073 05:59:06.869041 == TX Byte 0 ==
8074 05:59:06.872494 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8075 05:59:06.875510 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8076 05:59:06.879315 == TX Byte 1 ==
8077 05:59:06.882665 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8078 05:59:06.886034 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8079 05:59:06.886118 ==
8080 05:59:06.888805 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 05:59:06.895706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 05:59:06.895814 ==
8083 05:59:06.908704
8084 05:59:06.911492 TX Vref early break, caculate TX vref
8085 05:59:06.915058 TX Vref=16, minBit 1, minWin=22, winSum=384
8086 05:59:06.918595 TX Vref=18, minBit 1, minWin=22, winSum=394
8087 05:59:06.922005 TX Vref=20, minBit 0, minWin=24, winSum=403
8088 05:59:06.924799 TX Vref=22, minBit 1, minWin=24, winSum=416
8089 05:59:06.928159 TX Vref=24, minBit 1, minWin=24, winSum=418
8090 05:59:06.934868 TX Vref=26, minBit 3, minWin=25, winSum=429
8091 05:59:06.938180 TX Vref=28, minBit 0, minWin=25, winSum=420
8092 05:59:06.941767 TX Vref=30, minBit 0, minWin=25, winSum=417
8093 05:59:06.945174 TX Vref=32, minBit 0, minWin=25, winSum=412
8094 05:59:06.948500 TX Vref=34, minBit 2, minWin=24, winSum=405
8095 05:59:06.955140 [TxChooseVref] Worse bit 3, Min win 25, Win sum 429, Final Vref 26
8096 05:59:06.955210
8097 05:59:06.958018 Final TX Range 0 Vref 26
8098 05:59:06.958087
8099 05:59:06.958146 ==
8100 05:59:06.961364 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 05:59:06.964871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 05:59:06.964945 ==
8103 05:59:06.965009
8104 05:59:06.965070
8105 05:59:06.968120 TX Vref Scan disable
8106 05:59:06.974640 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8107 05:59:06.974714 == TX Byte 0 ==
8108 05:59:06.978591 u2DelayCellOfst[0]=13 cells (4 PI)
8109 05:59:06.981594 u2DelayCellOfst[1]=16 cells (5 PI)
8110 05:59:06.984672 u2DelayCellOfst[2]=10 cells (3 PI)
8111 05:59:06.988337 u2DelayCellOfst[3]=6 cells (2 PI)
8112 05:59:06.991531 u2DelayCellOfst[4]=6 cells (2 PI)
8113 05:59:06.994437 u2DelayCellOfst[5]=0 cells (0 PI)
8114 05:59:06.997870 u2DelayCellOfst[6]=13 cells (4 PI)
8115 05:59:07.001453 u2DelayCellOfst[7]=16 cells (5 PI)
8116 05:59:07.004389 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8117 05:59:07.008307 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8118 05:59:07.011521 == TX Byte 1 ==
8119 05:59:07.011602 u2DelayCellOfst[8]=3 cells (1 PI)
8120 05:59:07.014926 u2DelayCellOfst[9]=0 cells (0 PI)
8121 05:59:07.017731 u2DelayCellOfst[10]=6 cells (2 PI)
8122 05:59:07.021119 u2DelayCellOfst[11]=3 cells (1 PI)
8123 05:59:07.024665 u2DelayCellOfst[12]=10 cells (3 PI)
8124 05:59:07.028120 u2DelayCellOfst[13]=13 cells (4 PI)
8125 05:59:07.031382 u2DelayCellOfst[14]=16 cells (5 PI)
8126 05:59:07.034836 u2DelayCellOfst[15]=10 cells (3 PI)
8127 05:59:07.037635 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8128 05:59:07.044183 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8129 05:59:07.044292 DramC Write-DBI on
8130 05:59:07.044407 ==
8131 05:59:07.047618 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 05:59:07.051048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 05:59:07.054603 ==
8134 05:59:07.054682
8135 05:59:07.054761
8136 05:59:07.054836 TX Vref Scan disable
8137 05:59:07.057967 == TX Byte 0 ==
8138 05:59:07.061144 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8139 05:59:07.064441 == TX Byte 1 ==
8140 05:59:07.067913 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8141 05:59:07.071449 DramC Write-DBI off
8142 05:59:07.071524
8143 05:59:07.071585 [DATLAT]
8144 05:59:07.071642 Freq=1600, CH0 RK1
8145 05:59:07.071697
8146 05:59:07.074767 DATLAT Default: 0xf
8147 05:59:07.074847 0, 0xFFFF, sum = 0
8148 05:59:07.078111 1, 0xFFFF, sum = 0
8149 05:59:07.081489 2, 0xFFFF, sum = 0
8150 05:59:07.081574 3, 0xFFFF, sum = 0
8151 05:59:07.084236 4, 0xFFFF, sum = 0
8152 05:59:07.084363 5, 0xFFFF, sum = 0
8153 05:59:07.087700 6, 0xFFFF, sum = 0
8154 05:59:07.087777 7, 0xFFFF, sum = 0
8155 05:59:07.091099 8, 0xFFFF, sum = 0
8156 05:59:07.091180 9, 0xFFFF, sum = 0
8157 05:59:07.094328 10, 0xFFFF, sum = 0
8158 05:59:07.094405 11, 0xFFFF, sum = 0
8159 05:59:07.097826 12, 0xFFFF, sum = 0
8160 05:59:07.097902 13, 0xFFFF, sum = 0
8161 05:59:07.101087 14, 0x0, sum = 1
8162 05:59:07.101160 15, 0x0, sum = 2
8163 05:59:07.104403 16, 0x0, sum = 3
8164 05:59:07.104484 17, 0x0, sum = 4
8165 05:59:07.107716 best_step = 15
8166 05:59:07.107791
8167 05:59:07.107887 ==
8168 05:59:07.110974 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 05:59:07.114662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 05:59:07.114750 ==
8171 05:59:07.117638 RX Vref Scan: 0
8172 05:59:07.117724
8173 05:59:07.117786 RX Vref 0 -> 0, step: 1
8174 05:59:07.117844
8175 05:59:07.121053 RX Delay 19 -> 252, step: 4
8176 05:59:07.124228 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8177 05:59:07.130853 iDelay=195, Bit 1, Center 136 (91 ~ 182) 92
8178 05:59:07.134275 iDelay=195, Bit 2, Center 132 (83 ~ 182) 100
8179 05:59:07.137465 iDelay=195, Bit 3, Center 134 (83 ~ 186) 104
8180 05:59:07.141008 iDelay=195, Bit 4, Center 136 (87 ~ 186) 100
8181 05:59:07.144451 iDelay=195, Bit 5, Center 124 (71 ~ 178) 108
8182 05:59:07.151084 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8183 05:59:07.154527 iDelay=195, Bit 7, Center 142 (91 ~ 194) 104
8184 05:59:07.157960 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8185 05:59:07.161499 iDelay=195, Bit 9, Center 116 (67 ~ 166) 100
8186 05:59:07.164229 iDelay=195, Bit 10, Center 126 (75 ~ 178) 104
8187 05:59:07.171376 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8188 05:59:07.174818 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8189 05:59:07.178028 iDelay=195, Bit 13, Center 132 (83 ~ 182) 100
8190 05:59:07.181262 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8191 05:59:07.184679 iDelay=195, Bit 15, Center 134 (87 ~ 182) 96
8192 05:59:07.184754 ==
8193 05:59:07.187537 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 05:59:07.194365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 05:59:07.194446 ==
8196 05:59:07.194508 DQS Delay:
8197 05:59:07.197636 DQS0 = 0, DQS1 = 0
8198 05:59:07.197715 DQM Delay:
8199 05:59:07.200821 DQM0 = 134, DQM1 = 126
8200 05:59:07.200905 DQ Delay:
8201 05:59:07.204122 DQ0 =134, DQ1 =136, DQ2 =132, DQ3 =134
8202 05:59:07.207567 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =142
8203 05:59:07.210890 DQ8 =118, DQ9 =116, DQ10 =126, DQ11 =118
8204 05:59:07.214217 DQ12 =134, DQ13 =132, DQ14 =136, DQ15 =134
8205 05:59:07.214286
8206 05:59:07.214345
8207 05:59:07.214401
8208 05:59:07.217656 [DramC_TX_OE_Calibration] TA2
8209 05:59:07.220994 Original DQ_B0 (3 6) =30, OEN = 27
8210 05:59:07.223826 Original DQ_B1 (3 6) =30, OEN = 27
8211 05:59:07.227278 24, 0x0, End_B0=24 End_B1=24
8212 05:59:07.230801 25, 0x0, End_B0=25 End_B1=25
8213 05:59:07.230866 26, 0x0, End_B0=26 End_B1=26
8214 05:59:07.234106 27, 0x0, End_B0=27 End_B1=27
8215 05:59:07.237329 28, 0x0, End_B0=28 End_B1=28
8216 05:59:07.240607 29, 0x0, End_B0=29 End_B1=29
8217 05:59:07.240679 30, 0x0, End_B0=30 End_B1=30
8218 05:59:07.243710 31, 0x4141, End_B0=30 End_B1=30
8219 05:59:07.247341 Byte0 end_step=30 best_step=27
8220 05:59:07.250655 Byte1 end_step=30 best_step=27
8221 05:59:07.253863 Byte0 TX OE(2T, 0.5T) = (3, 3)
8222 05:59:07.257276 Byte1 TX OE(2T, 0.5T) = (3, 3)
8223 05:59:07.257348
8224 05:59:07.257408
8225 05:59:07.263791 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8226 05:59:07.267116 CH0 RK1: MR19=303, MR18=2008
8227 05:59:07.274052 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8228 05:59:07.277127 [RxdqsGatingPostProcess] freq 1600
8229 05:59:07.283640 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8230 05:59:07.283741 best DQS0 dly(2T, 0.5T) = (1, 1)
8231 05:59:07.286821 best DQS1 dly(2T, 0.5T) = (1, 1)
8232 05:59:07.290237 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8233 05:59:07.293735 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8234 05:59:07.297141 best DQS0 dly(2T, 0.5T) = (1, 1)
8235 05:59:07.300648 best DQS1 dly(2T, 0.5T) = (1, 1)
8236 05:59:07.303268 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8237 05:59:07.307032 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8238 05:59:07.310436 Pre-setting of DQS Precalculation
8239 05:59:07.313707 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8240 05:59:07.313779 ==
8241 05:59:07.317103 Dram Type= 6, Freq= 0, CH_1, rank 0
8242 05:59:07.323214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 05:59:07.323316 ==
8244 05:59:07.326779 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8245 05:59:07.333720 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8246 05:59:07.336567 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8247 05:59:07.343383 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8248 05:59:07.351108 [CA 0] Center 41 (12~71) winsize 60
8249 05:59:07.353885 [CA 1] Center 41 (12~71) winsize 60
8250 05:59:07.357329 [CA 2] Center 38 (9~68) winsize 60
8251 05:59:07.361055 [CA 3] Center 37 (8~67) winsize 60
8252 05:59:07.364296 [CA 4] Center 38 (9~67) winsize 59
8253 05:59:07.367299 [CA 5] Center 37 (8~66) winsize 59
8254 05:59:07.367366
8255 05:59:07.370858 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8256 05:59:07.370926
8257 05:59:07.374338 [CATrainingPosCal] consider 1 rank data
8258 05:59:07.377667 u2DelayCellTimex100 = 290/100 ps
8259 05:59:07.380845 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8260 05:59:07.387332 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8261 05:59:07.390577 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8262 05:59:07.394376 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8263 05:59:07.397492 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8264 05:59:07.400662 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8265 05:59:07.400739
8266 05:59:07.404188 CA PerBit enable=1, Macro0, CA PI delay=37
8267 05:59:07.404290
8268 05:59:07.407745 [CBTSetCACLKResult] CA Dly = 37
8269 05:59:07.410432 CS Dly: 11 (0~42)
8270 05:59:07.413796 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8271 05:59:07.416999 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8272 05:59:07.417067 ==
8273 05:59:07.420742 Dram Type= 6, Freq= 0, CH_1, rank 1
8274 05:59:07.424022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 05:59:07.424090 ==
8276 05:59:07.430443 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8277 05:59:07.433878 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8278 05:59:07.440881 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8279 05:59:07.443676 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8280 05:59:07.453948 [CA 0] Center 42 (12~72) winsize 61
8281 05:59:07.457496 [CA 1] Center 41 (12~71) winsize 60
8282 05:59:07.460903 [CA 2] Center 38 (9~68) winsize 60
8283 05:59:07.464262 [CA 3] Center 37 (8~67) winsize 60
8284 05:59:07.467128 [CA 4] Center 38 (8~68) winsize 61
8285 05:59:07.470579 [CA 5] Center 37 (8~67) winsize 60
8286 05:59:07.470645
8287 05:59:07.474144 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8288 05:59:07.474215
8289 05:59:07.476865 [CATrainingPosCal] consider 2 rank data
8290 05:59:07.480654 u2DelayCellTimex100 = 290/100 ps
8291 05:59:07.484049 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8292 05:59:07.490184 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8293 05:59:07.493806 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8294 05:59:07.496919 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8295 05:59:07.500028 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8296 05:59:07.503464 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8297 05:59:07.503545
8298 05:59:07.506798 CA PerBit enable=1, Macro0, CA PI delay=37
8299 05:59:07.506873
8300 05:59:07.510230 [CBTSetCACLKResult] CA Dly = 37
8301 05:59:07.513472 CS Dly: 12 (0~44)
8302 05:59:07.517098 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8303 05:59:07.520446 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8304 05:59:07.520525
8305 05:59:07.523885 ----->DramcWriteLeveling(PI) begin...
8306 05:59:07.523962 ==
8307 05:59:07.527203 Dram Type= 6, Freq= 0, CH_1, rank 0
8308 05:59:07.533343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 05:59:07.533429 ==
8310 05:59:07.536899 Write leveling (Byte 0): 25 => 25
8311 05:59:07.536983 Write leveling (Byte 1): 28 => 28
8312 05:59:07.540432 DramcWriteLeveling(PI) end<-----
8313 05:59:07.540505
8314 05:59:07.540565 ==
8315 05:59:07.543822 Dram Type= 6, Freq= 0, CH_1, rank 0
8316 05:59:07.550064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 05:59:07.550138 ==
8318 05:59:07.553523 [Gating] SW mode calibration
8319 05:59:07.560248 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8320 05:59:07.563137 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8321 05:59:07.570017 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 05:59:07.573420 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 05:59:07.576799 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8324 05:59:07.583086 1 4 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
8325 05:59:07.586448 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 05:59:07.589724 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 05:59:07.593352 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 05:59:07.600138 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 05:59:07.603409 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 05:59:07.606889 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 05:59:07.613523 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
8332 05:59:07.617050 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
8333 05:59:07.619893 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 05:59:07.626913 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 05:59:07.629934 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 05:59:07.633511 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 05:59:07.639877 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 05:59:07.643097 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 05:59:07.646757 1 6 8 | B1->B0 | 2626 4343 | 0 0 | (0 0) (0 0)
8340 05:59:07.653520 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 05:59:07.656437 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 05:59:07.659906 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 05:59:07.666939 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 05:59:07.670353 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 05:59:07.673082 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 05:59:07.680045 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 05:59:07.683390 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8348 05:59:07.686851 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8349 05:59:07.692880 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 05:59:07.696454 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 05:59:07.699846 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 05:59:07.706732 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 05:59:07.709454 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 05:59:07.712999 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 05:59:07.719758 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 05:59:07.723347 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 05:59:07.726207 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 05:59:07.729616 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 05:59:07.736581 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 05:59:07.739990 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 05:59:07.742797 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 05:59:07.749237 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 05:59:07.752791 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8364 05:59:07.756139 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8365 05:59:07.763292 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 05:59:07.766169 Total UI for P1: 0, mck2ui 16
8367 05:59:07.769739 best dqsien dly found for B0: ( 1, 9, 10)
8368 05:59:07.769815 Total UI for P1: 0, mck2ui 16
8369 05:59:07.776582 best dqsien dly found for B1: ( 1, 9, 10)
8370 05:59:07.779476 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8371 05:59:07.782654 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8372 05:59:07.782726
8373 05:59:07.786119 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8374 05:59:07.789228 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8375 05:59:07.793007 [Gating] SW calibration Done
8376 05:59:07.793083 ==
8377 05:59:07.796047 Dram Type= 6, Freq= 0, CH_1, rank 0
8378 05:59:07.799652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8379 05:59:07.799726 ==
8380 05:59:07.803050 RX Vref Scan: 0
8381 05:59:07.803146
8382 05:59:07.803234 RX Vref 0 -> 0, step: 1
8383 05:59:07.805787
8384 05:59:07.805852 RX Delay 0 -> 252, step: 8
8385 05:59:07.809375 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8386 05:59:07.815955 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8387 05:59:07.819391 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8388 05:59:07.822719 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8389 05:59:07.826163 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8390 05:59:07.829716 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8391 05:59:07.835977 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8392 05:59:07.839418 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8393 05:59:07.842837 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8394 05:59:07.845663 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8395 05:59:07.849068 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8396 05:59:07.855707 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8397 05:59:07.859139 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8398 05:59:07.862556 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8399 05:59:07.866101 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8400 05:59:07.869817 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8401 05:59:07.872569 ==
8402 05:59:07.875784 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 05:59:07.879143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 05:59:07.879217 ==
8405 05:59:07.879284 DQS Delay:
8406 05:59:07.882443 DQS0 = 0, DQS1 = 0
8407 05:59:07.882516 DQM Delay:
8408 05:59:07.885887 DQM0 = 136, DQM1 = 134
8409 05:59:07.885957 DQ Delay:
8410 05:59:07.889451 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8411 05:59:07.892740 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8412 05:59:07.896091 DQ8 =123, DQ9 =123, DQ10 =131, DQ11 =127
8413 05:59:07.899350 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8414 05:59:07.899421
8415 05:59:07.899480
8416 05:59:07.899542 ==
8417 05:59:07.902550 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 05:59:07.908984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 05:59:07.909057 ==
8420 05:59:07.909119
8421 05:59:07.909183
8422 05:59:07.909239 TX Vref Scan disable
8423 05:59:07.912414 == TX Byte 0 ==
8424 05:59:07.915792 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8425 05:59:07.922681 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8426 05:59:07.922757 == TX Byte 1 ==
8427 05:59:07.925637 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8428 05:59:07.932670 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8429 05:59:07.932747 ==
8430 05:59:07.935792 Dram Type= 6, Freq= 0, CH_1, rank 0
8431 05:59:07.939168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8432 05:59:07.939247 ==
8433 05:59:07.952344
8434 05:59:07.955855 TX Vref early break, caculate TX vref
8435 05:59:07.959081 TX Vref=16, minBit 0, minWin=22, winSum=377
8436 05:59:07.962464 TX Vref=18, minBit 0, minWin=23, winSum=383
8437 05:59:07.965966 TX Vref=20, minBit 1, minWin=23, winSum=396
8438 05:59:07.968795 TX Vref=22, minBit 0, minWin=25, winSum=409
8439 05:59:07.972243 TX Vref=24, minBit 0, minWin=25, winSum=417
8440 05:59:07.978936 TX Vref=26, minBit 1, minWin=25, winSum=423
8441 05:59:07.982296 TX Vref=28, minBit 2, minWin=25, winSum=426
8442 05:59:07.985492 TX Vref=30, minBit 0, minWin=25, winSum=418
8443 05:59:07.989022 TX Vref=32, minBit 0, minWin=25, winSum=415
8444 05:59:07.992168 TX Vref=34, minBit 0, minWin=24, winSum=405
8445 05:59:07.995668 TX Vref=36, minBit 0, minWin=23, winSum=391
8446 05:59:08.002530 [TxChooseVref] Worse bit 2, Min win 25, Win sum 426, Final Vref 28
8447 05:59:08.002604
8448 05:59:08.005972 Final TX Range 0 Vref 28
8449 05:59:08.006041
8450 05:59:08.006101 ==
8451 05:59:08.009375 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 05:59:08.012099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 05:59:08.012175 ==
8454 05:59:08.012235
8455 05:59:08.012299
8456 05:59:08.015494 TX Vref Scan disable
8457 05:59:08.022084 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8458 05:59:08.022167 == TX Byte 0 ==
8459 05:59:08.025634 u2DelayCellOfst[0]=16 cells (5 PI)
8460 05:59:08.028805 u2DelayCellOfst[1]=10 cells (3 PI)
8461 05:59:08.031968 u2DelayCellOfst[2]=0 cells (0 PI)
8462 05:59:08.035234 u2DelayCellOfst[3]=6 cells (2 PI)
8463 05:59:08.039041 u2DelayCellOfst[4]=10 cells (3 PI)
8464 05:59:08.042100 u2DelayCellOfst[5]=16 cells (5 PI)
8465 05:59:08.045174 u2DelayCellOfst[6]=16 cells (5 PI)
8466 05:59:08.048583 u2DelayCellOfst[7]=6 cells (2 PI)
8467 05:59:08.052159 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8468 05:59:08.055430 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8469 05:59:08.058786 == TX Byte 1 ==
8470 05:59:08.061573 u2DelayCellOfst[8]=0 cells (0 PI)
8471 05:59:08.065015 u2DelayCellOfst[9]=6 cells (2 PI)
8472 05:59:08.065086 u2DelayCellOfst[10]=13 cells (4 PI)
8473 05:59:08.068242 u2DelayCellOfst[11]=3 cells (1 PI)
8474 05:59:08.071763 u2DelayCellOfst[12]=16 cells (5 PI)
8475 05:59:08.075293 u2DelayCellOfst[13]=16 cells (5 PI)
8476 05:59:08.078599 u2DelayCellOfst[14]=16 cells (5 PI)
8477 05:59:08.082154 u2DelayCellOfst[15]=16 cells (5 PI)
8478 05:59:08.088200 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8479 05:59:08.091584 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8480 05:59:08.091659 DramC Write-DBI on
8481 05:59:08.091720 ==
8482 05:59:08.095355 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 05:59:08.101505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 05:59:08.101579 ==
8485 05:59:08.101643
8486 05:59:08.101702
8487 05:59:08.101756 TX Vref Scan disable
8488 05:59:08.105524 == TX Byte 0 ==
8489 05:59:08.109055 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8490 05:59:08.112517 == TX Byte 1 ==
8491 05:59:08.115977 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8492 05:59:08.118712 DramC Write-DBI off
8493 05:59:08.118780
8494 05:59:08.118842 [DATLAT]
8495 05:59:08.118898 Freq=1600, CH1 RK0
8496 05:59:08.118953
8497 05:59:08.122062 DATLAT Default: 0xf
8498 05:59:08.122129 0, 0xFFFF, sum = 0
8499 05:59:08.125564 1, 0xFFFF, sum = 0
8500 05:59:08.128857 2, 0xFFFF, sum = 0
8501 05:59:08.128926 3, 0xFFFF, sum = 0
8502 05:59:08.132125 4, 0xFFFF, sum = 0
8503 05:59:08.132221 5, 0xFFFF, sum = 0
8504 05:59:08.135218 6, 0xFFFF, sum = 0
8505 05:59:08.135285 7, 0xFFFF, sum = 0
8506 05:59:08.138852 8, 0xFFFF, sum = 0
8507 05:59:08.138926 9, 0xFFFF, sum = 0
8508 05:59:08.142560 10, 0xFFFF, sum = 0
8509 05:59:08.142660 11, 0xFFFF, sum = 0
8510 05:59:08.145721 12, 0xFFFF, sum = 0
8511 05:59:08.145804 13, 0xFFFF, sum = 0
8512 05:59:08.148743 14, 0x0, sum = 1
8513 05:59:08.148827 15, 0x0, sum = 2
8514 05:59:08.151987 16, 0x0, sum = 3
8515 05:59:08.152071 17, 0x0, sum = 4
8516 05:59:08.155234 best_step = 15
8517 05:59:08.155314
8518 05:59:08.155393 ==
8519 05:59:08.159065 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 05:59:08.161857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 05:59:08.161930 ==
8522 05:59:08.165511 RX Vref Scan: 1
8523 05:59:08.165594
8524 05:59:08.165673 Set Vref Range= 24 -> 127
8525 05:59:08.165749
8526 05:59:08.168606 RX Vref 24 -> 127, step: 1
8527 05:59:08.168679
8528 05:59:08.171852 RX Delay 27 -> 252, step: 4
8529 05:59:08.171928
8530 05:59:08.175101 Set Vref, RX VrefLevel [Byte0]: 24
8531 05:59:08.178684 [Byte1]: 24
8532 05:59:08.178761
8533 05:59:08.182117 Set Vref, RX VrefLevel [Byte0]: 25
8534 05:59:08.185462 [Byte1]: 25
8535 05:59:08.185545
8536 05:59:08.188270 Set Vref, RX VrefLevel [Byte0]: 26
8537 05:59:08.191632 [Byte1]: 26
8538 05:59:08.195652
8539 05:59:08.195727 Set Vref, RX VrefLevel [Byte0]: 27
8540 05:59:08.199112 [Byte1]: 27
8541 05:59:08.203090
8542 05:59:08.203166 Set Vref, RX VrefLevel [Byte0]: 28
8543 05:59:08.206468 [Byte1]: 28
8544 05:59:08.211299
8545 05:59:08.211374 Set Vref, RX VrefLevel [Byte0]: 29
8546 05:59:08.213948 [Byte1]: 29
8547 05:59:08.218771
8548 05:59:08.218844 Set Vref, RX VrefLevel [Byte0]: 30
8549 05:59:08.221493 [Byte1]: 30
8550 05:59:08.225688
8551 05:59:08.225763 Set Vref, RX VrefLevel [Byte0]: 31
8552 05:59:08.229098 [Byte1]: 31
8553 05:59:08.233342
8554 05:59:08.233415 Set Vref, RX VrefLevel [Byte0]: 32
8555 05:59:08.236809 [Byte1]: 32
8556 05:59:08.240945
8557 05:59:08.241025 Set Vref, RX VrefLevel [Byte0]: 33
8558 05:59:08.244403 [Byte1]: 33
8559 05:59:08.248814
8560 05:59:08.248889 Set Vref, RX VrefLevel [Byte0]: 34
8561 05:59:08.252000 [Byte1]: 34
8562 05:59:08.256459
8563 05:59:08.256538 Set Vref, RX VrefLevel [Byte0]: 35
8564 05:59:08.259551 [Byte1]: 35
8565 05:59:08.263834
8566 05:59:08.263912 Set Vref, RX VrefLevel [Byte0]: 36
8567 05:59:08.266869 [Byte1]: 36
8568 05:59:08.271420
8569 05:59:08.271497 Set Vref, RX VrefLevel [Byte0]: 37
8570 05:59:08.274759 [Byte1]: 37
8571 05:59:08.279053
8572 05:59:08.279129 Set Vref, RX VrefLevel [Byte0]: 38
8573 05:59:08.282256 [Byte1]: 38
8574 05:59:08.286077
8575 05:59:08.286147 Set Vref, RX VrefLevel [Byte0]: 39
8576 05:59:08.289512 [Byte1]: 39
8577 05:59:08.293694
8578 05:59:08.293773 Set Vref, RX VrefLevel [Byte0]: 40
8579 05:59:08.297058 [Byte1]: 40
8580 05:59:08.301108
8581 05:59:08.301208 Set Vref, RX VrefLevel [Byte0]: 41
8582 05:59:08.304788 [Byte1]: 41
8583 05:59:08.308833
8584 05:59:08.308913 Set Vref, RX VrefLevel [Byte0]: 42
8585 05:59:08.312241 [Byte1]: 42
8586 05:59:08.316248
8587 05:59:08.316362 Set Vref, RX VrefLevel [Byte0]: 43
8588 05:59:08.319724 [Byte1]: 43
8589 05:59:08.323960
8590 05:59:08.324031 Set Vref, RX VrefLevel [Byte0]: 44
8591 05:59:08.327604 [Byte1]: 44
8592 05:59:08.331775
8593 05:59:08.331841 Set Vref, RX VrefLevel [Byte0]: 45
8594 05:59:08.334458 [Byte1]: 45
8595 05:59:08.339341
8596 05:59:08.339415 Set Vref, RX VrefLevel [Byte0]: 46
8597 05:59:08.342139 [Byte1]: 46
8598 05:59:08.346786
8599 05:59:08.346859 Set Vref, RX VrefLevel [Byte0]: 47
8600 05:59:08.349645 [Byte1]: 47
8601 05:59:08.354393
8602 05:59:08.354465 Set Vref, RX VrefLevel [Byte0]: 48
8603 05:59:08.357155 [Byte1]: 48
8604 05:59:08.361189
8605 05:59:08.361268 Set Vref, RX VrefLevel [Byte0]: 49
8606 05:59:08.364638 [Byte1]: 49
8607 05:59:08.369200
8608 05:59:08.369275 Set Vref, RX VrefLevel [Byte0]: 50
8609 05:59:08.372510 [Byte1]: 50
8610 05:59:08.376418
8611 05:59:08.376488 Set Vref, RX VrefLevel [Byte0]: 51
8612 05:59:08.380409 [Byte1]: 51
8613 05:59:08.384130
8614 05:59:08.384225 Set Vref, RX VrefLevel [Byte0]: 52
8615 05:59:08.387612 [Byte1]: 52
8616 05:59:08.391667
8617 05:59:08.391737 Set Vref, RX VrefLevel [Byte0]: 53
8618 05:59:08.394975 [Byte1]: 53
8619 05:59:08.398890
8620 05:59:08.398957 Set Vref, RX VrefLevel [Byte0]: 54
8621 05:59:08.402514 [Byte1]: 54
8622 05:59:08.406450
8623 05:59:08.406516 Set Vref, RX VrefLevel [Byte0]: 55
8624 05:59:08.410051 [Byte1]: 55
8625 05:59:08.414314
8626 05:59:08.414388 Set Vref, RX VrefLevel [Byte0]: 56
8627 05:59:08.417362 [Byte1]: 56
8628 05:59:08.421665
8629 05:59:08.421740 Set Vref, RX VrefLevel [Byte0]: 57
8630 05:59:08.425045 [Byte1]: 57
8631 05:59:08.429108
8632 05:59:08.429183 Set Vref, RX VrefLevel [Byte0]: 58
8633 05:59:08.432501 [Byte1]: 58
8634 05:59:08.436677
8635 05:59:08.436748 Set Vref, RX VrefLevel [Byte0]: 59
8636 05:59:08.440166 [Byte1]: 59
8637 05:59:08.444357
8638 05:59:08.444429 Set Vref, RX VrefLevel [Byte0]: 60
8639 05:59:08.447811 [Byte1]: 60
8640 05:59:08.451847
8641 05:59:08.451916 Set Vref, RX VrefLevel [Byte0]: 61
8642 05:59:08.455463 [Byte1]: 61
8643 05:59:08.459525
8644 05:59:08.459594 Set Vref, RX VrefLevel [Byte0]: 62
8645 05:59:08.463038 [Byte1]: 62
8646 05:59:08.467066
8647 05:59:08.467134 Set Vref, RX VrefLevel [Byte0]: 63
8648 05:59:08.470452 [Byte1]: 63
8649 05:59:08.474400
8650 05:59:08.474471 Set Vref, RX VrefLevel [Byte0]: 64
8651 05:59:08.477713 [Byte1]: 64
8652 05:59:08.482409
8653 05:59:08.482483 Set Vref, RX VrefLevel [Byte0]: 65
8654 05:59:08.485698 [Byte1]: 65
8655 05:59:08.489583
8656 05:59:08.489657 Set Vref, RX VrefLevel [Byte0]: 66
8657 05:59:08.492771 [Byte1]: 66
8658 05:59:08.496907
8659 05:59:08.496989 Set Vref, RX VrefLevel [Byte0]: 67
8660 05:59:08.500319 [Byte1]: 67
8661 05:59:08.505144
8662 05:59:08.505219 Set Vref, RX VrefLevel [Byte0]: 68
8663 05:59:08.507918 [Byte1]: 68
8664 05:59:08.512687
8665 05:59:08.512758 Set Vref, RX VrefLevel [Byte0]: 69
8666 05:59:08.515294 [Byte1]: 69
8667 05:59:08.519878
8668 05:59:08.519956 Set Vref, RX VrefLevel [Byte0]: 70
8669 05:59:08.523129 [Byte1]: 70
8670 05:59:08.527216
8671 05:59:08.527293 Set Vref, RX VrefLevel [Byte0]: 71
8672 05:59:08.530620 [Byte1]: 71
8673 05:59:08.535023
8674 05:59:08.535097 Set Vref, RX VrefLevel [Byte0]: 72
8675 05:59:08.538066 [Byte1]: 72
8676 05:59:08.542367
8677 05:59:08.542451 Set Vref, RX VrefLevel [Byte0]: 73
8678 05:59:08.545761 [Byte1]: 73
8679 05:59:08.549960
8680 05:59:08.550035 Set Vref, RX VrefLevel [Byte0]: 74
8681 05:59:08.553134 [Byte1]: 74
8682 05:59:08.557332
8683 05:59:08.557411 Set Vref, RX VrefLevel [Byte0]: 75
8684 05:59:08.560731 [Byte1]: 75
8685 05:59:08.565045
8686 05:59:08.565118 Set Vref, RX VrefLevel [Byte0]: 76
8687 05:59:08.568474 [Byte1]: 76
8688 05:59:08.572433
8689 05:59:08.572508 Final RX Vref Byte 0 = 60 to rank0
8690 05:59:08.575703 Final RX Vref Byte 1 = 57 to rank0
8691 05:59:08.579221 Final RX Vref Byte 0 = 60 to rank1
8692 05:59:08.582483 Final RX Vref Byte 1 = 57 to rank1==
8693 05:59:08.585760 Dram Type= 6, Freq= 0, CH_1, rank 0
8694 05:59:08.592455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8695 05:59:08.592535 ==
8696 05:59:08.592618 DQS Delay:
8697 05:59:08.592700 DQS0 = 0, DQS1 = 0
8698 05:59:08.595742 DQM Delay:
8699 05:59:08.595819 DQM0 = 133, DQM1 = 131
8700 05:59:08.599009 DQ Delay:
8701 05:59:08.602403 DQ0 =140, DQ1 =128, DQ2 =120, DQ3 =130
8702 05:59:08.605837 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8703 05:59:08.609313 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8704 05:59:08.612892 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8705 05:59:08.612966
8706 05:59:08.613045
8707 05:59:08.613120
8708 05:59:08.616209 [DramC_TX_OE_Calibration] TA2
8709 05:59:08.619073 Original DQ_B0 (3 6) =30, OEN = 27
8710 05:59:08.622660 Original DQ_B1 (3 6) =30, OEN = 27
8711 05:59:08.626092 24, 0x0, End_B0=24 End_B1=24
8712 05:59:08.626177 25, 0x0, End_B0=25 End_B1=25
8713 05:59:08.629401 26, 0x0, End_B0=26 End_B1=26
8714 05:59:08.632755 27, 0x0, End_B0=27 End_B1=27
8715 05:59:08.635486 28, 0x0, End_B0=28 End_B1=28
8716 05:59:08.635562 29, 0x0, End_B0=29 End_B1=29
8717 05:59:08.639400 30, 0x0, End_B0=30 End_B1=30
8718 05:59:08.642068 31, 0x4141, End_B0=30 End_B1=30
8719 05:59:08.645584 Byte0 end_step=30 best_step=27
8720 05:59:08.648966 Byte1 end_step=30 best_step=27
8721 05:59:08.652223 Byte0 TX OE(2T, 0.5T) = (3, 3)
8722 05:59:08.652356 Byte1 TX OE(2T, 0.5T) = (3, 3)
8723 05:59:08.655475
8724 05:59:08.655548
8725 05:59:08.662122 [DQSOSCAuto] RK0, (LSB)MR18= 0x1421, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
8726 05:59:08.665299 CH1 RK0: MR19=303, MR18=1421
8727 05:59:08.671973 CH1_RK0: MR19=0x303, MR18=0x1421, DQSOSC=393, MR23=63, INC=23, DEC=15
8728 05:59:08.672051
8729 05:59:08.675406 ----->DramcWriteLeveling(PI) begin...
8730 05:59:08.675482 ==
8731 05:59:08.678794 Dram Type= 6, Freq= 0, CH_1, rank 1
8732 05:59:08.682121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8733 05:59:08.682204 ==
8734 05:59:08.685339 Write leveling (Byte 0): 27 => 27
8735 05:59:08.688587 Write leveling (Byte 1): 29 => 29
8736 05:59:08.691979 DramcWriteLeveling(PI) end<-----
8737 05:59:08.692052
8738 05:59:08.692132 ==
8739 05:59:08.695329 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 05:59:08.698703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 05:59:08.698781 ==
8742 05:59:08.702078 [Gating] SW mode calibration
8743 05:59:08.708789 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8744 05:59:08.715611 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8745 05:59:08.718492 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 05:59:08.721850 1 4 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8747 05:59:08.728745 1 4 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8748 05:59:08.732142 1 4 12 | B1->B0 | 3434 2f2e | 1 1 | (1 1) (1 1)
8749 05:59:08.735483 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 05:59:08.742098 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 05:59:08.745382 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 05:59:08.748855 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 05:59:08.755624 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 05:59:08.758475 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8755 05:59:08.761781 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8756 05:59:08.768829 1 5 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
8757 05:59:08.771479 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 05:59:08.774742 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 05:59:08.781842 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 05:59:08.785064 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 05:59:08.788226 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 05:59:08.794676 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 05:59:08.798609 1 6 8 | B1->B0 | 3737 2323 | 1 0 | (0 0) (0 0)
8764 05:59:08.801425 1 6 12 | B1->B0 | 4646 4242 | 0 0 | (0 0) (1 1)
8765 05:59:08.808134 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 05:59:08.811896 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 05:59:08.814669 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 05:59:08.821666 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 05:59:08.825267 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 05:59:08.828018 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8771 05:59:08.831551 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8772 05:59:08.837840 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8773 05:59:08.841007 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8774 05:59:08.847785 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 05:59:08.851141 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 05:59:08.854325 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 05:59:08.858397 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 05:59:08.864298 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 05:59:08.867931 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 05:59:08.871150 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 05:59:08.877862 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 05:59:08.881314 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 05:59:08.884705 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 05:59:08.891338 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 05:59:08.894563 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 05:59:08.897635 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 05:59:08.904234 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8788 05:59:08.907967 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8789 05:59:08.911037 Total UI for P1: 0, mck2ui 16
8790 05:59:08.914305 best dqsien dly found for B1: ( 1, 9, 8)
8791 05:59:08.917532 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 05:59:08.920727 Total UI for P1: 0, mck2ui 16
8793 05:59:08.924259 best dqsien dly found for B0: ( 1, 9, 12)
8794 05:59:08.927738 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8795 05:59:08.931248 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8796 05:59:08.931319
8797 05:59:08.937439 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8798 05:59:08.941004 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8799 05:59:08.941079 [Gating] SW calibration Done
8800 05:59:08.944416 ==
8801 05:59:08.947799 Dram Type= 6, Freq= 0, CH_1, rank 1
8802 05:59:08.951156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 05:59:08.951230 ==
8804 05:59:08.951309 RX Vref Scan: 0
8805 05:59:08.951391
8806 05:59:08.954565 RX Vref 0 -> 0, step: 1
8807 05:59:08.954643
8808 05:59:08.957795 RX Delay 0 -> 252, step: 8
8809 05:59:08.961101 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8810 05:59:08.964259 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8811 05:59:08.967773 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8812 05:59:08.974521 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8813 05:59:08.977923 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8814 05:59:08.981329 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8815 05:59:08.984561 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8816 05:59:08.988055 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8817 05:59:08.994175 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8818 05:59:08.997505 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8819 05:59:09.000969 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8820 05:59:09.004516 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8821 05:59:09.007811 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8822 05:59:09.014433 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8823 05:59:09.017606 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8824 05:59:09.020619 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8825 05:59:09.020697 ==
8826 05:59:09.024255 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 05:59:09.027424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 05:59:09.027500 ==
8829 05:59:09.030614 DQS Delay:
8830 05:59:09.030691 DQS0 = 0, DQS1 = 0
8831 05:59:09.034088 DQM Delay:
8832 05:59:09.034237 DQM0 = 135, DQM1 = 133
8833 05:59:09.034334 DQ Delay:
8834 05:59:09.040659 DQ0 =139, DQ1 =135, DQ2 =119, DQ3 =131
8835 05:59:09.044190 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8836 05:59:09.047740 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8837 05:59:09.051080 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8838 05:59:09.051180
8839 05:59:09.051270
8840 05:59:09.051358 ==
8841 05:59:09.054377 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 05:59:09.057219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 05:59:09.057318 ==
8844 05:59:09.057408
8845 05:59:09.057499
8846 05:59:09.060814 TX Vref Scan disable
8847 05:59:09.064210 == TX Byte 0 ==
8848 05:59:09.067734 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8849 05:59:09.071000 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8850 05:59:09.074388 == TX Byte 1 ==
8851 05:59:09.077349 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8852 05:59:09.080818 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8853 05:59:09.080890 ==
8854 05:59:09.084265 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 05:59:09.087113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 05:59:09.090447 ==
8857 05:59:09.101374
8858 05:59:09.104985 TX Vref early break, caculate TX vref
8859 05:59:09.108364 TX Vref=16, minBit 0, minWin=23, winSum=382
8860 05:59:09.111738 TX Vref=18, minBit 1, minWin=23, winSum=392
8861 05:59:09.115066 TX Vref=20, minBit 2, minWin=23, winSum=401
8862 05:59:09.118572 TX Vref=22, minBit 0, minWin=25, winSum=410
8863 05:59:09.121380 TX Vref=24, minBit 0, minWin=25, winSum=417
8864 05:59:09.128171 TX Vref=26, minBit 0, minWin=25, winSum=421
8865 05:59:09.131309 TX Vref=28, minBit 1, minWin=25, winSum=428
8866 05:59:09.134616 TX Vref=30, minBit 1, minWin=25, winSum=421
8867 05:59:09.138050 TX Vref=32, minBit 0, minWin=25, winSum=412
8868 05:59:09.141787 TX Vref=34, minBit 0, minWin=24, winSum=403
8869 05:59:09.148121 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 28
8870 05:59:09.148204
8871 05:59:09.151733 Final TX Range 0 Vref 28
8872 05:59:09.151804
8873 05:59:09.151868 ==
8874 05:59:09.154679 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 05:59:09.157996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 05:59:09.158096 ==
8877 05:59:09.158184
8878 05:59:09.158269
8879 05:59:09.161494 TX Vref Scan disable
8880 05:59:09.167928 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8881 05:59:09.168045 == TX Byte 0 ==
8882 05:59:09.171568 u2DelayCellOfst[0]=16 cells (5 PI)
8883 05:59:09.175152 u2DelayCellOfst[1]=10 cells (3 PI)
8884 05:59:09.177984 u2DelayCellOfst[2]=0 cells (0 PI)
8885 05:59:09.181363 u2DelayCellOfst[3]=6 cells (2 PI)
8886 05:59:09.184579 u2DelayCellOfst[4]=10 cells (3 PI)
8887 05:59:09.188503 u2DelayCellOfst[5]=16 cells (5 PI)
8888 05:59:09.191468 u2DelayCellOfst[6]=16 cells (5 PI)
8889 05:59:09.191627 u2DelayCellOfst[7]=6 cells (2 PI)
8890 05:59:09.198275 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8891 05:59:09.201581 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8892 05:59:09.201737 == TX Byte 1 ==
8893 05:59:09.204694 u2DelayCellOfst[8]=0 cells (0 PI)
8894 05:59:09.208096 u2DelayCellOfst[9]=3 cells (1 PI)
8895 05:59:09.211470 u2DelayCellOfst[10]=13 cells (4 PI)
8896 05:59:09.214905 u2DelayCellOfst[11]=6 cells (2 PI)
8897 05:59:09.217825 u2DelayCellOfst[12]=13 cells (4 PI)
8898 05:59:09.221070 u2DelayCellOfst[13]=13 cells (4 PI)
8899 05:59:09.224467 u2DelayCellOfst[14]=16 cells (5 PI)
8900 05:59:09.227972 u2DelayCellOfst[15]=16 cells (5 PI)
8901 05:59:09.231604 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8902 05:59:09.237989 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8903 05:59:09.238067 DramC Write-DBI on
8904 05:59:09.238130 ==
8905 05:59:09.241424 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 05:59:09.244759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 05:59:09.247510 ==
8908 05:59:09.247579
8909 05:59:09.247639
8910 05:59:09.247696 TX Vref Scan disable
8911 05:59:09.250719 == TX Byte 0 ==
8912 05:59:09.254040 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8913 05:59:09.257797 == TX Byte 1 ==
8914 05:59:09.261076 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8915 05:59:09.264247 DramC Write-DBI off
8916 05:59:09.264353
8917 05:59:09.264430 [DATLAT]
8918 05:59:09.264507 Freq=1600, CH1 RK1
8919 05:59:09.264563
8920 05:59:09.267439 DATLAT Default: 0xf
8921 05:59:09.267505 0, 0xFFFF, sum = 0
8922 05:59:09.271182 1, 0xFFFF, sum = 0
8923 05:59:09.274116 2, 0xFFFF, sum = 0
8924 05:59:09.274185 3, 0xFFFF, sum = 0
8925 05:59:09.277561 4, 0xFFFF, sum = 0
8926 05:59:09.277628 5, 0xFFFF, sum = 0
8927 05:59:09.281189 6, 0xFFFF, sum = 0
8928 05:59:09.281258 7, 0xFFFF, sum = 0
8929 05:59:09.283863 8, 0xFFFF, sum = 0
8930 05:59:09.283956 9, 0xFFFF, sum = 0
8931 05:59:09.287517 10, 0xFFFF, sum = 0
8932 05:59:09.287618 11, 0xFFFF, sum = 0
8933 05:59:09.291016 12, 0xFFFF, sum = 0
8934 05:59:09.291086 13, 0xFFFF, sum = 0
8935 05:59:09.293966 14, 0x0, sum = 1
8936 05:59:09.294054 15, 0x0, sum = 2
8937 05:59:09.297244 16, 0x0, sum = 3
8938 05:59:09.297315 17, 0x0, sum = 4
8939 05:59:09.300498 best_step = 15
8940 05:59:09.300567
8941 05:59:09.300624 ==
8942 05:59:09.304498 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 05:59:09.307572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 05:59:09.307640 ==
8945 05:59:09.307699 RX Vref Scan: 0
8946 05:59:09.311120
8947 05:59:09.311195 RX Vref 0 -> 0, step: 1
8948 05:59:09.311257
8949 05:59:09.314134 RX Delay 19 -> 252, step: 4
8950 05:59:09.317268 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8951 05:59:09.323998 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8952 05:59:09.327236 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8953 05:59:09.330654 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8954 05:59:09.334173 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8955 05:59:09.337049 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8956 05:59:09.343913 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8957 05:59:09.347167 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8958 05:59:09.350597 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8959 05:59:09.354152 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8960 05:59:09.357069 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8961 05:59:09.363839 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8962 05:59:09.367217 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8963 05:59:09.370052 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8964 05:59:09.373447 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8965 05:59:09.377138 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8966 05:59:09.380373 ==
8967 05:59:09.383839 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 05:59:09.386644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 05:59:09.386751 ==
8970 05:59:09.386847 DQS Delay:
8971 05:59:09.390077 DQS0 = 0, DQS1 = 0
8972 05:59:09.390157 DQM Delay:
8973 05:59:09.393648 DQM0 = 134, DQM1 = 130
8974 05:59:09.393758 DQ Delay:
8975 05:59:09.397208 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8976 05:59:09.400829 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
8977 05:59:09.403548 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8978 05:59:09.407041 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8979 05:59:09.407149
8980 05:59:09.407239
8981 05:59:09.407335
8982 05:59:09.410367 [DramC_TX_OE_Calibration] TA2
8983 05:59:09.413267 Original DQ_B0 (3 6) =30, OEN = 27
8984 05:59:09.416785 Original DQ_B1 (3 6) =30, OEN = 27
8985 05:59:09.420216 24, 0x0, End_B0=24 End_B1=24
8986 05:59:09.423647 25, 0x0, End_B0=25 End_B1=25
8987 05:59:09.423729 26, 0x0, End_B0=26 End_B1=26
8988 05:59:09.427012 27, 0x0, End_B0=27 End_B1=27
8989 05:59:09.430053 28, 0x0, End_B0=28 End_B1=28
8990 05:59:09.433179 29, 0x0, End_B0=29 End_B1=29
8991 05:59:09.436925 30, 0x0, End_B0=30 End_B1=30
8992 05:59:09.437010 31, 0x4141, End_B0=30 End_B1=30
8993 05:59:09.439972 Byte0 end_step=30 best_step=27
8994 05:59:09.443207 Byte1 end_step=30 best_step=27
8995 05:59:09.446816 Byte0 TX OE(2T, 0.5T) = (3, 3)
8996 05:59:09.450387 Byte1 TX OE(2T, 0.5T) = (3, 3)
8997 05:59:09.450469
8998 05:59:09.450534
8999 05:59:09.456628 [DQSOSCAuto] RK1, (LSB)MR18= 0x2208, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9000 05:59:09.460135 CH1 RK1: MR19=303, MR18=2208
9001 05:59:09.466993 CH1_RK1: MR19=0x303, MR18=0x2208, DQSOSC=392, MR23=63, INC=24, DEC=16
9002 05:59:09.470312 [RxdqsGatingPostProcess] freq 1600
9003 05:59:09.473586 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9004 05:59:09.476938 best DQS0 dly(2T, 0.5T) = (1, 1)
9005 05:59:09.480458 best DQS1 dly(2T, 0.5T) = (1, 1)
9006 05:59:09.483161 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9007 05:59:09.486859 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9008 05:59:09.490124 best DQS0 dly(2T, 0.5T) = (1, 1)
9009 05:59:09.493520 best DQS1 dly(2T, 0.5T) = (1, 1)
9010 05:59:09.496918 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9011 05:59:09.500497 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9012 05:59:09.503217 Pre-setting of DQS Precalculation
9013 05:59:09.506675 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9014 05:59:09.513434 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9015 05:59:09.523618 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9016 05:59:09.523698
9017 05:59:09.523762
9018 05:59:09.526300 [Calibration Summary] 3200 Mbps
9019 05:59:09.526371 CH 0, Rank 0
9020 05:59:09.529730 SW Impedance : PASS
9021 05:59:09.529796 DUTY Scan : NO K
9022 05:59:09.533120 ZQ Calibration : PASS
9023 05:59:09.536514 Jitter Meter : NO K
9024 05:59:09.536583 CBT Training : PASS
9025 05:59:09.539874 Write leveling : PASS
9026 05:59:09.539945 RX DQS gating : PASS
9027 05:59:09.543278 RX DQ/DQS(RDDQC) : PASS
9028 05:59:09.546517 TX DQ/DQS : PASS
9029 05:59:09.546591 RX DATLAT : PASS
9030 05:59:09.549676 RX DQ/DQS(Engine): PASS
9031 05:59:09.553197 TX OE : PASS
9032 05:59:09.553268 All Pass.
9033 05:59:09.553327
9034 05:59:09.553386 CH 0, Rank 1
9035 05:59:09.556665 SW Impedance : PASS
9036 05:59:09.559594 DUTY Scan : NO K
9037 05:59:09.559667 ZQ Calibration : PASS
9038 05:59:09.563181 Jitter Meter : NO K
9039 05:59:09.566272 CBT Training : PASS
9040 05:59:09.566372 Write leveling : PASS
9041 05:59:09.569671 RX DQS gating : PASS
9042 05:59:09.572864 RX DQ/DQS(RDDQC) : PASS
9043 05:59:09.572937 TX DQ/DQS : PASS
9044 05:59:09.576121 RX DATLAT : PASS
9045 05:59:09.579428 RX DQ/DQS(Engine): PASS
9046 05:59:09.579498 TX OE : PASS
9047 05:59:09.579559 All Pass.
9048 05:59:09.582690
9049 05:59:09.582759 CH 1, Rank 0
9050 05:59:09.586210 SW Impedance : PASS
9051 05:59:09.586279 DUTY Scan : NO K
9052 05:59:09.589528 ZQ Calibration : PASS
9053 05:59:09.592873 Jitter Meter : NO K
9054 05:59:09.592954 CBT Training : PASS
9055 05:59:09.596467 Write leveling : PASS
9056 05:59:09.596547 RX DQS gating : PASS
9057 05:59:09.599711 RX DQ/DQS(RDDQC) : PASS
9058 05:59:09.602783 TX DQ/DQS : PASS
9059 05:59:09.602864 RX DATLAT : PASS
9060 05:59:09.606146 RX DQ/DQS(Engine): PASS
9061 05:59:09.609565 TX OE : PASS
9062 05:59:09.609645 All Pass.
9063 05:59:09.609709
9064 05:59:09.609768 CH 1, Rank 1
9065 05:59:09.613146 SW Impedance : PASS
9066 05:59:09.615858 DUTY Scan : NO K
9067 05:59:09.615938 ZQ Calibration : PASS
9068 05:59:09.619304 Jitter Meter : NO K
9069 05:59:09.622992 CBT Training : PASS
9070 05:59:09.623098 Write leveling : PASS
9071 05:59:09.626170 RX DQS gating : PASS
9072 05:59:09.629697 RX DQ/DQS(RDDQC) : PASS
9073 05:59:09.629794 TX DQ/DQS : PASS
9074 05:59:09.633130 RX DATLAT : PASS
9075 05:59:09.635897 RX DQ/DQS(Engine): PASS
9076 05:59:09.635996 TX OE : PASS
9077 05:59:09.636084 All Pass.
9078 05:59:09.639373
9079 05:59:09.639474 DramC Write-DBI on
9080 05:59:09.642819 PER_BANK_REFRESH: Hybrid Mode
9081 05:59:09.642906 TX_TRACKING: ON
9082 05:59:09.652632 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9083 05:59:09.659503 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9084 05:59:09.669769 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9085 05:59:09.672960 [FAST_K] Save calibration result to emmc
9086 05:59:09.676177 sync common calibartion params.
9087 05:59:09.676277 sync cbt_mode0:1, 1:1
9088 05:59:09.679215 dram_init: ddr_geometry: 2
9089 05:59:09.682798 dram_init: ddr_geometry: 2
9090 05:59:09.682866 dram_init: ddr_geometry: 2
9091 05:59:09.686230 0:dram_rank_size:100000000
9092 05:59:09.689100 1:dram_rank_size:100000000
9093 05:59:09.692462 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9094 05:59:09.695905 DFS_SHUFFLE_HW_MODE: ON
9095 05:59:09.698934 dramc_set_vcore_voltage set vcore to 725000
9096 05:59:09.702442 Read voltage for 1600, 0
9097 05:59:09.702514 Vio18 = 0
9098 05:59:09.706082 Vcore = 725000
9099 05:59:09.706158 Vdram = 0
9100 05:59:09.706219 Vddq = 0
9101 05:59:09.706276 Vmddr = 0
9102 05:59:09.709060 switch to 3200 Mbps bootup
9103 05:59:09.712593 [DramcRunTimeConfig]
9104 05:59:09.712662 PHYPLL
9105 05:59:09.716094 DPM_CONTROL_AFTERK: ON
9106 05:59:09.716173 PER_BANK_REFRESH: ON
9107 05:59:09.719306 REFRESH_OVERHEAD_REDUCTION: ON
9108 05:59:09.722124 CMD_PICG_NEW_MODE: OFF
9109 05:59:09.722200 XRTWTW_NEW_MODE: ON
9110 05:59:09.725610 XRTRTR_NEW_MODE: ON
9111 05:59:09.725680 TX_TRACKING: ON
9112 05:59:09.728782 RDSEL_TRACKING: OFF
9113 05:59:09.732782 DQS Precalculation for DVFS: ON
9114 05:59:09.732849 RX_TRACKING: OFF
9115 05:59:09.732911 HW_GATING DBG: ON
9116 05:59:09.735512 ZQCS_ENABLE_LP4: ON
9117 05:59:09.739022 RX_PICG_NEW_MODE: ON
9118 05:59:09.739088 TX_PICG_NEW_MODE: ON
9119 05:59:09.742473 ENABLE_RX_DCM_DPHY: ON
9120 05:59:09.746158 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9121 05:59:09.746228 DUMMY_READ_FOR_TRACKING: OFF
9122 05:59:09.748833 !!! SPM_CONTROL_AFTERK: OFF
9123 05:59:09.752267 !!! SPM could not control APHY
9124 05:59:09.755772 IMPEDANCE_TRACKING: ON
9125 05:59:09.755839 TEMP_SENSOR: ON
9126 05:59:09.759397 HW_SAVE_FOR_SR: OFF
9127 05:59:09.762121 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9128 05:59:09.765661 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9129 05:59:09.765730 Read ODT Tracking: ON
9130 05:59:09.769157 Refresh Rate DeBounce: ON
9131 05:59:09.772377 DFS_NO_QUEUE_FLUSH: ON
9132 05:59:09.775734 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9133 05:59:09.775800 ENABLE_DFS_RUNTIME_MRW: OFF
9134 05:59:09.778916 DDR_RESERVE_NEW_MODE: ON
9135 05:59:09.782234 MR_CBT_SWITCH_FREQ: ON
9136 05:59:09.782304 =========================
9137 05:59:09.802473 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9138 05:59:09.805567 dram_init: ddr_geometry: 2
9139 05:59:09.824038 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9140 05:59:09.826781 dram_init: dram init end (result: 0)
9141 05:59:09.833901 DRAM-K: Full calibration passed in 24445 msecs
9142 05:59:09.836745 MRC: failed to locate region type 0.
9143 05:59:09.836815 DRAM rank0 size:0x100000000,
9144 05:59:09.840546 DRAM rank1 size=0x100000000
9145 05:59:09.850264 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9146 05:59:09.856512 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9147 05:59:09.863447 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9148 05:59:09.870430 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9149 05:59:09.873207 DRAM rank0 size:0x100000000,
9150 05:59:09.876681 DRAM rank1 size=0x100000000
9151 05:59:09.876751 CBMEM:
9152 05:59:09.880044 IMD: root @ 0xfffff000 254 entries.
9153 05:59:09.883547 IMD: root @ 0xffffec00 62 entries.
9154 05:59:09.886859 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9155 05:59:09.890036 WARNING: RO_VPD is uninitialized or empty.
9156 05:59:09.896800 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9157 05:59:09.903642 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9158 05:59:09.916582 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9159 05:59:09.928095 BS: romstage times (exec / console): total (unknown) / 23977 ms
9160 05:59:09.928171
9161 05:59:09.928234
9162 05:59:09.938165 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9163 05:59:09.941264 ARM64: Exception handlers installed.
9164 05:59:09.944563 ARM64: Testing exception
9165 05:59:09.947848 ARM64: Done test exception
9166 05:59:09.947920 Enumerating buses...
9167 05:59:09.950764 Show all devs... Before device enumeration.
9168 05:59:09.954445 Root Device: enabled 1
9169 05:59:09.957993 CPU_CLUSTER: 0: enabled 1
9170 05:59:09.958066 CPU: 00: enabled 1
9171 05:59:09.961329 Compare with tree...
9172 05:59:09.961403 Root Device: enabled 1
9173 05:59:09.964499 CPU_CLUSTER: 0: enabled 1
9174 05:59:09.968078 CPU: 00: enabled 1
9175 05:59:09.968175 Root Device scanning...
9176 05:59:09.970827 scan_static_bus for Root Device
9177 05:59:09.974332 CPU_CLUSTER: 0 enabled
9178 05:59:09.977760 scan_static_bus for Root Device done
9179 05:59:09.981139 scan_bus: bus Root Device finished in 8 msecs
9180 05:59:09.981208 done
9181 05:59:09.987982 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9182 05:59:09.991418 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9183 05:59:09.998055 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9184 05:59:10.001260 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9185 05:59:10.004712 Allocating resources...
9186 05:59:10.004787 Reading resources...
9187 05:59:10.011096 Root Device read_resources bus 0 link: 0
9188 05:59:10.011167 DRAM rank0 size:0x100000000,
9189 05:59:10.014653 DRAM rank1 size=0x100000000
9190 05:59:10.017432 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9191 05:59:10.020997 CPU: 00 missing read_resources
9192 05:59:10.024348 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9193 05:59:10.030894 Root Device read_resources bus 0 link: 0 done
9194 05:59:10.030968 Done reading resources.
9195 05:59:10.037653 Show resources in subtree (Root Device)...After reading.
9196 05:59:10.041087 Root Device child on link 0 CPU_CLUSTER: 0
9197 05:59:10.044495 CPU_CLUSTER: 0 child on link 0 CPU: 00
9198 05:59:10.054319 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9199 05:59:10.054395 CPU: 00
9200 05:59:10.057730 Root Device assign_resources, bus 0 link: 0
9201 05:59:10.061147 CPU_CLUSTER: 0 missing set_resources
9202 05:59:10.064492 Root Device assign_resources, bus 0 link: 0 done
9203 05:59:10.067579 Done setting resources.
9204 05:59:10.074115 Show resources in subtree (Root Device)...After assigning values.
9205 05:59:10.077751 Root Device child on link 0 CPU_CLUSTER: 0
9206 05:59:10.080546 CPU_CLUSTER: 0 child on link 0 CPU: 00
9207 05:59:10.090806 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9208 05:59:10.090883 CPU: 00
9209 05:59:10.094357 Done allocating resources.
9210 05:59:10.097145 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9211 05:59:10.100652 Enabling resources...
9212 05:59:10.100724 done.
9213 05:59:10.107217 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9214 05:59:10.107293 Initializing devices...
9215 05:59:10.110707 Root Device init
9216 05:59:10.110777 init hardware done!
9217 05:59:10.113782 0x00000018: ctrlr->caps
9218 05:59:10.117287 52.000 MHz: ctrlr->f_max
9219 05:59:10.117363 0.400 MHz: ctrlr->f_min
9220 05:59:10.120927 0x40ff8080: ctrlr->voltages
9221 05:59:10.120996 sclk: 390625
9222 05:59:10.123626 Bus Width = 1
9223 05:59:10.123695 sclk: 390625
9224 05:59:10.127052 Bus Width = 1
9225 05:59:10.127118 Early init status = 3
9226 05:59:10.133984 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9227 05:59:10.137453 in-header: 03 fc 00 00 01 00 00 00
9228 05:59:10.137521 in-data: 00
9229 05:59:10.143922 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9230 05:59:10.146979 in-header: 03 fd 00 00 00 00 00 00
9231 05:59:10.150081 in-data:
9232 05:59:10.153825 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9233 05:59:10.156759 in-header: 03 fc 00 00 01 00 00 00
9234 05:59:10.160509 in-data: 00
9235 05:59:10.163632 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9236 05:59:10.168240 in-header: 03 fd 00 00 00 00 00 00
9237 05:59:10.171604 in-data:
9238 05:59:10.174349 [SSUSB] Setting up USB HOST controller...
9239 05:59:10.177659 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9240 05:59:10.181484 [SSUSB] phy power-on done.
9241 05:59:10.184490 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9242 05:59:10.191123 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9243 05:59:10.194727 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9244 05:59:10.201193 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9245 05:59:10.208066 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9246 05:59:10.214996 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9247 05:59:10.221714 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9248 05:59:10.227958 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9249 05:59:10.228033 SPM: binary array size = 0x9dc
9250 05:59:10.234910 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9251 05:59:10.241191 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9252 05:59:10.247885 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9253 05:59:10.251188 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9254 05:59:10.257238 configure_display: Starting display init
9255 05:59:10.290932 anx7625_power_on_init: Init interface.
9256 05:59:10.294220 anx7625_disable_pd_protocol: Disabled PD feature.
9257 05:59:10.297638 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9258 05:59:10.325828 anx7625_start_dp_work: Secure OCM version=00
9259 05:59:10.329192 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9260 05:59:10.343630 sp_tx_get_edid_block: EDID Block = 1
9261 05:59:10.446467 Extracted contents:
9262 05:59:10.449397 header: 00 ff ff ff ff ff ff 00
9263 05:59:10.452717 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9264 05:59:10.456368 version: 01 04
9265 05:59:10.459709 basic params: 95 1f 11 78 0a
9266 05:59:10.463168 chroma info: 76 90 94 55 54 90 27 21 50 54
9267 05:59:10.466002 established: 00 00 00
9268 05:59:10.473126 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9269 05:59:10.476104 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9270 05:59:10.482944 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9271 05:59:10.489407 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9272 05:59:10.496411 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9273 05:59:10.499209 extensions: 00
9274 05:59:10.499278 checksum: fb
9275 05:59:10.499343
9276 05:59:10.502593 Manufacturer: IVO Model 57d Serial Number 0
9277 05:59:10.506039 Made week 0 of 2020
9278 05:59:10.506121 EDID version: 1.4
9279 05:59:10.509450 Digital display
9280 05:59:10.513015 6 bits per primary color channel
9281 05:59:10.513087 DisplayPort interface
9282 05:59:10.515750 Maximum image size: 31 cm x 17 cm
9283 05:59:10.519332 Gamma: 220%
9284 05:59:10.519404 Check DPMS levels
9285 05:59:10.522913 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9286 05:59:10.526364 First detailed timing is preferred timing
9287 05:59:10.529244 Established timings supported:
9288 05:59:10.532611 Standard timings supported:
9289 05:59:10.532685 Detailed timings
9290 05:59:10.539492 Hex of detail: 383680a07038204018303c0035ae10000019
9291 05:59:10.542317 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9292 05:59:10.549213 0780 0798 07c8 0820 hborder 0
9293 05:59:10.552566 0438 043b 0447 0458 vborder 0
9294 05:59:10.555768 -hsync -vsync
9295 05:59:10.555839 Did detailed timing
9296 05:59:10.559097 Hex of detail: 000000000000000000000000000000000000
9297 05:59:10.562724 Manufacturer-specified data, tag 0
9298 05:59:10.569494 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9299 05:59:10.569578 ASCII string: InfoVision
9300 05:59:10.575548 Hex of detail: 000000fe00523134304e574635205248200a
9301 05:59:10.579134 ASCII string: R140NWF5 RH
9302 05:59:10.579215 Checksum
9303 05:59:10.579278 Checksum: 0xfb (valid)
9304 05:59:10.585900 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9305 05:59:10.588784 DSI data_rate: 832800000 bps
9306 05:59:10.592448 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9307 05:59:10.599205 anx7625_parse_edid: pixelclock(138800).
9308 05:59:10.602319 hactive(1920), hsync(48), hfp(24), hbp(88)
9309 05:59:10.605531 vactive(1080), vsync(12), vfp(3), vbp(17)
9310 05:59:10.608920 anx7625_dsi_config: config dsi.
9311 05:59:10.615501 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9312 05:59:10.628638 anx7625_dsi_config: success to config DSI
9313 05:59:10.631386 anx7625_dp_start: MIPI phy setup OK.
9314 05:59:10.634897 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9315 05:59:10.638387 mtk_ddp_mode_set invalid vrefresh 60
9316 05:59:10.641757 main_disp_path_setup
9317 05:59:10.641837 ovl_layer_smi_id_en
9318 05:59:10.644945 ovl_layer_smi_id_en
9319 05:59:10.645026 ccorr_config
9320 05:59:10.645089 aal_config
9321 05:59:10.648059 gamma_config
9322 05:59:10.648138 postmask_config
9323 05:59:10.651691 dither_config
9324 05:59:10.654781 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9325 05:59:10.661757 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9326 05:59:10.665085 Root Device init finished in 551 msecs
9327 05:59:10.668258 CPU_CLUSTER: 0 init
9328 05:59:10.674699 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9329 05:59:10.678588 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9330 05:59:10.681754 APU_MBOX 0x190000b0 = 0x10001
9331 05:59:10.685267 APU_MBOX 0x190001b0 = 0x10001
9332 05:59:10.688624 APU_MBOX 0x190005b0 = 0x10001
9333 05:59:10.691193 APU_MBOX 0x190006b0 = 0x10001
9334 05:59:10.694612 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9335 05:59:10.707611 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9336 05:59:10.719765 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9337 05:59:10.726299 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9338 05:59:10.737928 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9339 05:59:10.747078 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9340 05:59:10.750572 CPU_CLUSTER: 0 init finished in 81 msecs
9341 05:59:10.754104 Devices initialized
9342 05:59:10.757231 Show all devs... After init.
9343 05:59:10.757311 Root Device: enabled 1
9344 05:59:10.760458 CPU_CLUSTER: 0: enabled 1
9345 05:59:10.763392 CPU: 00: enabled 1
9346 05:59:10.767046 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9347 05:59:10.770114 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9348 05:59:10.773686 ELOG: NV offset 0x57f000 size 0x1000
9349 05:59:10.780106 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9350 05:59:10.786717 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9351 05:59:10.789915 ELOG: Event(17) added with size 13 at 2023-12-25 05:56:35 UTC
9352 05:59:10.796532 out: cmd=0x121: 03 db 21 01 00 00 00 00
9353 05:59:10.799920 in-header: 03 e7 00 00 2c 00 00 00
9354 05:59:10.809668 in-data: 78 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9355 05:59:10.816594 ELOG: Event(A1) added with size 10 at 2023-12-25 05:56:35 UTC
9356 05:59:10.823363 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9357 05:59:10.829946 ELOG: Event(A0) added with size 9 at 2023-12-25 05:56:35 UTC
9358 05:59:10.833061 elog_add_boot_reason: Logged dev mode boot
9359 05:59:10.839844 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9360 05:59:10.839925 Finalize devices...
9361 05:59:10.843222 Devices finalized
9362 05:59:10.846538 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9363 05:59:10.850041 Writing coreboot table at 0xffe64000
9364 05:59:10.852850 0. 000000000010a000-0000000000113fff: RAMSTAGE
9365 05:59:10.856216 1. 0000000040000000-00000000400fffff: RAM
9366 05:59:10.863217 2. 0000000040100000-000000004032afff: RAMSTAGE
9367 05:59:10.866642 3. 000000004032b000-00000000545fffff: RAM
9368 05:59:10.869953 4. 0000000054600000-000000005465ffff: BL31
9369 05:59:10.873139 5. 0000000054660000-00000000ffe63fff: RAM
9370 05:59:10.879780 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9371 05:59:10.882749 7. 0000000100000000-000000023fffffff: RAM
9372 05:59:10.886369 Passing 5 GPIOs to payload:
9373 05:59:10.889586 NAME | PORT | POLARITY | VALUE
9374 05:59:10.892967 EC in RW | 0x000000aa | low | undefined
9375 05:59:10.899723 EC interrupt | 0x00000005 | low | undefined
9376 05:59:10.902987 TPM interrupt | 0x000000ab | high | undefined
9377 05:59:10.909325 SD card detect | 0x00000011 | high | undefined
9378 05:59:10.912672 speaker enable | 0x00000093 | high | undefined
9379 05:59:10.916108 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9380 05:59:10.919615 in-header: 03 f9 00 00 02 00 00 00
9381 05:59:10.922871 in-data: 02 00
9382 05:59:10.922943 ADC[4]: Raw value=904357 ID=7
9383 05:59:10.926211 ADC[3]: Raw value=213810 ID=1
9384 05:59:10.929735 RAM Code: 0x71
9385 05:59:10.929807 ADC[6]: Raw value=75701 ID=0
9386 05:59:10.932561 ADC[5]: Raw value=213072 ID=1
9387 05:59:10.936089 SKU Code: 0x1
9388 05:59:10.939487 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5137
9389 05:59:10.942923 coreboot table: 964 bytes.
9390 05:59:10.945924 IMD ROOT 0. 0xfffff000 0x00001000
9391 05:59:10.949056 IMD SMALL 1. 0xffffe000 0x00001000
9392 05:59:10.952596 RO MCACHE 2. 0xffffc000 0x00001104
9393 05:59:10.956151 CONSOLE 3. 0xfff7c000 0x00080000
9394 05:59:10.959496 FMAP 4. 0xfff7b000 0x00000452
9395 05:59:10.962378 TIME STAMP 5. 0xfff7a000 0x00000910
9396 05:59:10.965836 VBOOT WORK 6. 0xfff66000 0x00014000
9397 05:59:10.969377 RAMOOPS 7. 0xffe66000 0x00100000
9398 05:59:10.972643 COREBOOT 8. 0xffe64000 0x00002000
9399 05:59:10.975904 IMD small region:
9400 05:59:10.979227 IMD ROOT 0. 0xffffec00 0x00000400
9401 05:59:10.982645 VPD 1. 0xffffeb80 0x0000006c
9402 05:59:10.985473 MMC STATUS 2. 0xffffeb60 0x00000004
9403 05:59:10.988932 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9404 05:59:10.992179 Probing TPM: done!
9405 05:59:10.995528 Connected to device vid:did:rid of 1ae0:0028:00
9406 05:59:11.006343 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9407 05:59:11.009376 Initialized TPM device CR50 revision 0
9408 05:59:11.012817 Checking cr50 for pending updates
9409 05:59:11.017115 Reading cr50 TPM mode
9410 05:59:11.025245 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9411 05:59:11.032513 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9412 05:59:11.071997 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9413 05:59:11.075394 Checking segment from ROM address 0x40100000
9414 05:59:11.078840 Checking segment from ROM address 0x4010001c
9415 05:59:11.085415 Loading segment from ROM address 0x40100000
9416 05:59:11.085488 code (compression=0)
9417 05:59:11.092145 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9418 05:59:11.102330 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9419 05:59:11.102409 it's not compressed!
9420 05:59:11.109385 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9421 05:59:11.112190 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9422 05:59:11.132304 Loading segment from ROM address 0x4010001c
9423 05:59:11.132399 Entry Point 0x80000000
9424 05:59:11.135826 Loaded segments
9425 05:59:11.139288 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9426 05:59:11.146057 Jumping to boot code at 0x80000000(0xffe64000)
9427 05:59:11.152438 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9428 05:59:11.159218 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9429 05:59:11.166765 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9430 05:59:11.170200 Checking segment from ROM address 0x40100000
9431 05:59:11.173573 Checking segment from ROM address 0x4010001c
9432 05:59:11.180599 Loading segment from ROM address 0x40100000
9433 05:59:11.180675 code (compression=1)
9434 05:59:11.187298 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9435 05:59:11.196697 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9436 05:59:11.196772 using LZMA
9437 05:59:11.205280 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9438 05:59:11.212067 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9439 05:59:11.215687 Loading segment from ROM address 0x4010001c
9440 05:59:11.215756 Entry Point 0x54601000
9441 05:59:11.218433 Loaded segments
9442 05:59:11.221799 NOTICE: MT8192 bl31_setup
9443 05:59:11.229189 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9444 05:59:11.232554 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9445 05:59:11.235359 WARNING: region 0:
9446 05:59:11.238881 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 05:59:11.238953 WARNING: region 1:
9448 05:59:11.245601 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9449 05:59:11.248667 WARNING: region 2:
9450 05:59:11.252472 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9451 05:59:11.255560 WARNING: region 3:
9452 05:59:11.259099 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9453 05:59:11.262170 WARNING: region 4:
9454 05:59:11.269365 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9455 05:59:11.269475 WARNING: region 5:
9456 05:59:11.272094 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9457 05:59:11.275607 WARNING: region 6:
9458 05:59:11.279013 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9459 05:59:11.282425 WARNING: region 7:
9460 05:59:11.285094 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 05:59:11.291955 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9462 05:59:11.295666 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9463 05:59:11.298668 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9464 05:59:11.305271 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9465 05:59:11.308943 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9466 05:59:11.311922 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9467 05:59:11.318709 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9468 05:59:11.322278 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9469 05:59:11.328927 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9470 05:59:11.332116 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9471 05:59:11.335527 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9472 05:59:11.341952 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9473 05:59:11.345529 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9474 05:59:11.349015 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9475 05:59:11.355246 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9476 05:59:11.358842 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9477 05:59:11.365819 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9478 05:59:11.368549 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9479 05:59:11.372166 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9480 05:59:11.378633 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9481 05:59:11.382404 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9482 05:59:11.385572 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9483 05:59:11.392039 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9484 05:59:11.395734 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9485 05:59:11.402134 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9486 05:59:11.405513 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9487 05:59:11.408828 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9488 05:59:11.415408 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9489 05:59:11.418724 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9490 05:59:11.425420 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9491 05:59:11.428834 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9492 05:59:11.432198 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9493 05:59:11.438491 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9494 05:59:11.442382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9495 05:59:11.445787 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9496 05:59:11.448585 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9497 05:59:11.455761 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9498 05:59:11.458565 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9499 05:59:11.461986 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9500 05:59:11.465451 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9501 05:59:11.471767 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9502 05:59:11.475433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9503 05:59:11.478834 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9504 05:59:11.482587 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9505 05:59:11.489026 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9506 05:59:11.491919 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9507 05:59:11.495739 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9508 05:59:11.499006 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9509 05:59:11.505388 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9510 05:59:11.508920 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9511 05:59:11.515651 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9512 05:59:11.519096 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9513 05:59:11.522434 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9514 05:59:11.528901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9515 05:59:11.532196 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9516 05:59:11.539135 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9517 05:59:11.542531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9518 05:59:11.549217 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9519 05:59:11.552583 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9520 05:59:11.555386 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9521 05:59:11.561964 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9522 05:59:11.565665 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9523 05:59:11.572110 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9524 05:59:11.575725 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9525 05:59:11.582131 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9526 05:59:11.585584 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9527 05:59:11.589227 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9528 05:59:11.595638 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9529 05:59:11.599320 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9530 05:59:11.605863 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9531 05:59:11.608794 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9532 05:59:11.615469 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9533 05:59:11.618987 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9534 05:59:11.622211 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9535 05:59:11.629021 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9536 05:59:11.632236 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9537 05:59:11.639207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9538 05:59:11.642175 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9539 05:59:11.649337 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9540 05:59:11.652494 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9541 05:59:11.655948 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9542 05:59:11.662558 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9543 05:59:11.665579 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9544 05:59:11.672663 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9545 05:59:11.676022 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9546 05:59:11.682669 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9547 05:59:11.685554 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9548 05:59:11.689225 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9549 05:59:11.695542 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9550 05:59:11.699103 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9551 05:59:11.706131 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9552 05:59:11.708878 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9553 05:59:11.716146 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9554 05:59:11.719116 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9555 05:59:11.725406 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9556 05:59:11.728835 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9557 05:59:11.732490 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9558 05:59:11.735712 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9559 05:59:11.742094 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9560 05:59:11.745561 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9561 05:59:11.748924 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9562 05:59:11.755955 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9563 05:59:11.759473 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9564 05:59:11.762105 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9565 05:59:11.769325 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9566 05:59:11.772809 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9567 05:59:11.779227 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9568 05:59:11.782502 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9569 05:59:11.785961 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9570 05:59:11.792377 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9571 05:59:11.795762 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9572 05:59:11.799023 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9573 05:59:11.806274 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9574 05:59:11.809685 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9575 05:59:11.816263 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9576 05:59:11.819060 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9577 05:59:11.822642 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9578 05:59:11.829078 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9579 05:59:11.832580 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9580 05:59:11.836259 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9581 05:59:11.839111 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9582 05:59:11.846178 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9583 05:59:11.849084 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9584 05:59:11.852766 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9585 05:59:11.859848 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9586 05:59:11.862591 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9587 05:59:11.865640 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9588 05:59:11.872637 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9589 05:59:11.876264 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9590 05:59:11.882669 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9591 05:59:11.886363 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9592 05:59:11.889222 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9593 05:59:11.896123 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9594 05:59:11.899373 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9595 05:59:11.902935 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9596 05:59:11.909513 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9597 05:59:11.912585 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9598 05:59:11.916183 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9599 05:59:11.922471 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9600 05:59:11.925798 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9601 05:59:11.933068 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9602 05:59:11.935760 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9603 05:59:11.939175 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9604 05:59:11.946164 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9605 05:59:11.949558 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9606 05:59:11.956068 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9607 05:59:11.959030 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9608 05:59:11.962553 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9609 05:59:11.969591 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9610 05:59:11.973009 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9611 05:59:11.979487 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9612 05:59:11.982801 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9613 05:59:11.986013 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9614 05:59:11.992399 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9615 05:59:11.996059 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9616 05:59:12.002875 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9617 05:59:12.006118 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9618 05:59:12.009622 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9619 05:59:12.015815 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9620 05:59:12.019270 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9621 05:59:12.022660 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9622 05:59:12.029075 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9623 05:59:12.032299 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9624 05:59:12.039470 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9625 05:59:12.042998 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9626 05:59:12.045824 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9627 05:59:12.052736 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9628 05:59:12.056077 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9629 05:59:12.062612 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9630 05:59:12.066064 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9631 05:59:12.068854 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9632 05:59:12.075980 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9633 05:59:12.078905 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9634 05:59:12.082481 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9635 05:59:12.089035 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9636 05:59:12.092585 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9637 05:59:12.099433 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9638 05:59:12.102560 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9639 05:59:12.105726 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9640 05:59:12.112283 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9641 05:59:12.115529 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9642 05:59:12.122101 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9643 05:59:12.125671 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9644 05:59:12.129078 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9645 05:59:12.135224 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9646 05:59:12.138688 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9647 05:59:12.145499 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9648 05:59:12.149093 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9649 05:59:12.152018 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9650 05:59:12.158745 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9651 05:59:12.162163 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9652 05:59:12.168572 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9653 05:59:12.172109 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9654 05:59:12.175643 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9655 05:59:12.181921 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9656 05:59:12.185428 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9657 05:59:12.192128 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9658 05:59:12.195042 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9659 05:59:12.201893 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9660 05:59:12.204749 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9661 05:59:12.208449 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9662 05:59:12.214959 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9663 05:59:12.218284 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9664 05:59:12.225136 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9665 05:59:12.228359 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9666 05:59:12.234699 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9667 05:59:12.237962 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9668 05:59:12.241365 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9669 05:59:12.247852 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9670 05:59:12.251353 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9671 05:59:12.257830 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9672 05:59:12.261029 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9673 05:59:12.267922 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9674 05:59:12.270910 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9675 05:59:12.274012 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9676 05:59:12.280648 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9677 05:59:12.284190 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9678 05:59:12.290652 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9679 05:59:12.294086 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9680 05:59:12.301039 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9681 05:59:12.304352 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9682 05:59:12.307241 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9683 05:59:12.314306 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9684 05:59:12.317620 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9685 05:59:12.324025 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9686 05:59:12.327381 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9687 05:59:12.330561 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9688 05:59:12.337306 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9689 05:59:12.340384 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9690 05:59:12.344021 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9691 05:59:12.350612 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9692 05:59:12.353836 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9693 05:59:12.357466 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9694 05:59:12.360873 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9695 05:59:12.367310 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9696 05:59:12.370831 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9697 05:59:12.377234 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9698 05:59:12.380506 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9699 05:59:12.383681 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9700 05:59:12.390321 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9701 05:59:12.393529 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9702 05:59:12.396904 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9703 05:59:12.403824 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9704 05:59:12.407190 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9705 05:59:12.409903 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9706 05:59:12.416974 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9707 05:59:12.420585 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9708 05:59:12.427016 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9709 05:59:12.430426 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9710 05:59:12.433293 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9711 05:59:12.440211 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9712 05:59:12.443544 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9713 05:59:12.446805 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9714 05:59:12.453515 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9715 05:59:12.456782 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9716 05:59:12.459993 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9717 05:59:12.466393 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9718 05:59:12.470033 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9719 05:59:12.476111 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9720 05:59:12.479741 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9721 05:59:12.483166 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9722 05:59:12.489729 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9723 05:59:12.493130 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9724 05:59:12.496494 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9725 05:59:12.502879 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9726 05:59:12.505795 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9727 05:59:12.512710 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9728 05:59:12.516414 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9729 05:59:12.519553 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9730 05:59:12.522386 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9731 05:59:12.529360 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9732 05:59:12.532999 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9733 05:59:12.535824 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9734 05:59:12.539371 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9735 05:59:12.545711 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9736 05:59:12.549104 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9737 05:59:12.552402 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9738 05:59:12.555634 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9739 05:59:12.562592 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9740 05:59:12.566203 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9741 05:59:12.569461 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9742 05:59:12.572763 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9743 05:59:12.579054 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9744 05:59:12.582632 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9745 05:59:12.588976 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9746 05:59:12.592450 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9747 05:59:12.599225 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9748 05:59:12.602615 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9749 05:59:12.606137 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9750 05:59:12.612275 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9751 05:59:12.615615 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9752 05:59:12.622432 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9753 05:59:12.625452 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9754 05:59:12.629017 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9755 05:59:12.635477 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9756 05:59:12.638958 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9757 05:59:12.645707 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9758 05:59:12.649134 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9759 05:59:12.651880 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9760 05:59:12.659043 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9761 05:59:12.662321 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9762 05:59:12.668512 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9763 05:59:12.672084 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9764 05:59:12.678528 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9765 05:59:12.682172 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9766 05:59:12.685711 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9767 05:59:12.692381 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9768 05:59:12.695561 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9769 05:59:12.702178 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9770 05:59:12.705183 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9771 05:59:12.708868 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9772 05:59:12.715159 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9773 05:59:12.718569 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9774 05:59:12.725093 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9775 05:59:12.728533 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9776 05:59:12.731770 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9777 05:59:12.738559 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9778 05:59:12.741841 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9779 05:59:12.748163 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9780 05:59:12.751936 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9781 05:59:12.758022 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9782 05:59:12.761922 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9783 05:59:12.764672 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9784 05:59:12.771539 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9785 05:59:12.774945 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9786 05:59:12.781546 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9787 05:59:12.784436 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9788 05:59:12.787973 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9789 05:59:12.794422 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9790 05:59:12.797738 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9791 05:59:12.804783 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9792 05:59:12.807663 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9793 05:59:12.811378 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9794 05:59:12.817705 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9795 05:59:12.821081 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9796 05:59:12.827922 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9797 05:59:12.831052 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9798 05:59:12.834461 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9799 05:59:12.840924 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9800 05:59:12.844227 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9801 05:59:12.851322 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9802 05:59:12.854110 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9803 05:59:12.861007 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9804 05:59:12.864385 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9805 05:59:12.867606 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9806 05:59:12.874107 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9807 05:59:12.877452 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9808 05:59:12.883701 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9809 05:59:12.887098 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9810 05:59:12.890797 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9811 05:59:12.897220 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9812 05:59:12.900756 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9813 05:59:12.907030 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9814 05:59:12.910612 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9815 05:59:12.914147 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9816 05:59:12.920346 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9817 05:59:12.923933 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9818 05:59:12.930236 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9819 05:59:12.933643 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9820 05:59:12.940278 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9821 05:59:12.944104 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9822 05:59:12.947481 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9823 05:59:12.953606 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9824 05:59:12.957431 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9825 05:59:12.963765 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9826 05:59:12.967025 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9827 05:59:12.973992 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9828 05:59:12.976814 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9829 05:59:12.983715 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9830 05:59:12.986905 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9831 05:59:12.990604 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9832 05:59:12.996674 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9833 05:59:13.000608 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9834 05:59:13.006973 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9835 05:59:13.010497 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9836 05:59:13.016894 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9837 05:59:13.020519 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9838 05:59:13.023940 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9839 05:59:13.030479 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9840 05:59:13.034006 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9841 05:59:13.040414 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9842 05:59:13.043890 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9843 05:59:13.050157 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9844 05:59:13.053625 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9845 05:59:13.057169 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9846 05:59:13.063776 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9847 05:59:13.067171 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9848 05:59:13.073787 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9849 05:59:13.076779 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9850 05:59:13.083424 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9851 05:59:13.086492 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9852 05:59:13.093394 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9853 05:59:13.096952 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9854 05:59:13.100417 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9855 05:59:13.106509 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9856 05:59:13.110259 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9857 05:59:13.117062 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9858 05:59:13.120098 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9859 05:59:13.126584 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9860 05:59:13.130208 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9861 05:59:13.133174 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9862 05:59:13.140270 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9863 05:59:13.143081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9864 05:59:13.146482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9865 05:59:13.153414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9866 05:59:13.156833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9867 05:59:13.163191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9868 05:59:13.166697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9869 05:59:13.173539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9870 05:59:13.176315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9871 05:59:13.183184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9872 05:59:13.186640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9873 05:59:13.193359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9874 05:59:13.196529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9875 05:59:13.203195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9876 05:59:13.206385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9877 05:59:13.213464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9878 05:59:13.216236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9879 05:59:13.223005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9880 05:59:13.226264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9881 05:59:13.233091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9882 05:59:13.236409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9883 05:59:13.242649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9884 05:59:13.246139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9885 05:59:13.252344 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9886 05:59:13.255782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9887 05:59:13.262762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9888 05:59:13.265513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9889 05:59:13.272497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9890 05:59:13.275766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9891 05:59:13.282901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9892 05:59:13.285491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9893 05:59:13.292654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9894 05:59:13.295476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9895 05:59:13.298833 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9896 05:59:13.302533 INFO: [APUAPC] vio 0
9897 05:59:13.309202 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9898 05:59:13.312262 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9899 05:59:13.315786 INFO: [APUAPC] D0_APC_0: 0x400510
9900 05:59:13.318708 INFO: [APUAPC] D0_APC_1: 0x0
9901 05:59:13.322214 INFO: [APUAPC] D0_APC_2: 0x1540
9902 05:59:13.325408 INFO: [APUAPC] D0_APC_3: 0x0
9903 05:59:13.328803 INFO: [APUAPC] D1_APC_0: 0xffffffff
9904 05:59:13.332446 INFO: [APUAPC] D1_APC_1: 0xffffffff
9905 05:59:13.335691 INFO: [APUAPC] D1_APC_2: 0x3fffff
9906 05:59:13.338925 INFO: [APUAPC] D1_APC_3: 0x0
9907 05:59:13.342112 INFO: [APUAPC] D2_APC_0: 0xffffffff
9908 05:59:13.345416 INFO: [APUAPC] D2_APC_1: 0xffffffff
9909 05:59:13.348830 INFO: [APUAPC] D2_APC_2: 0x3fffff
9910 05:59:13.351925 INFO: [APUAPC] D2_APC_3: 0x0
9911 05:59:13.355132 INFO: [APUAPC] D3_APC_0: 0xffffffff
9912 05:59:13.358472 INFO: [APUAPC] D3_APC_1: 0xffffffff
9913 05:59:13.361761 INFO: [APUAPC] D3_APC_2: 0x3fffff
9914 05:59:13.361832 INFO: [APUAPC] D3_APC_3: 0x0
9915 05:59:13.365324 INFO: [APUAPC] D4_APC_0: 0xffffffff
9916 05:59:13.371732 INFO: [APUAPC] D4_APC_1: 0xffffffff
9917 05:59:13.375309 INFO: [APUAPC] D4_APC_2: 0x3fffff
9918 05:59:13.375409 INFO: [APUAPC] D4_APC_3: 0x0
9919 05:59:13.378764 INFO: [APUAPC] D5_APC_0: 0xffffffff
9920 05:59:13.382178 INFO: [APUAPC] D5_APC_1: 0xffffffff
9921 05:59:13.385509 INFO: [APUAPC] D5_APC_2: 0x3fffff
9922 05:59:13.388396 INFO: [APUAPC] D5_APC_3: 0x0
9923 05:59:13.391766 INFO: [APUAPC] D6_APC_0: 0xffffffff
9924 05:59:13.395362 INFO: [APUAPC] D6_APC_1: 0xffffffff
9925 05:59:13.398770 INFO: [APUAPC] D6_APC_2: 0x3fffff
9926 05:59:13.401587 INFO: [APUAPC] D6_APC_3: 0x0
9927 05:59:13.405098 INFO: [APUAPC] D7_APC_0: 0xffffffff
9928 05:59:13.408688 INFO: [APUAPC] D7_APC_1: 0xffffffff
9929 05:59:13.411447 INFO: [APUAPC] D7_APC_2: 0x3fffff
9930 05:59:13.415109 INFO: [APUAPC] D7_APC_3: 0x0
9931 05:59:13.418812 INFO: [APUAPC] D8_APC_0: 0xffffffff
9932 05:59:13.421643 INFO: [APUAPC] D8_APC_1: 0xffffffff
9933 05:59:13.425131 INFO: [APUAPC] D8_APC_2: 0x3fffff
9934 05:59:13.428411 INFO: [APUAPC] D8_APC_3: 0x0
9935 05:59:13.431502 INFO: [APUAPC] D9_APC_0: 0xffffffff
9936 05:59:13.435168 INFO: [APUAPC] D9_APC_1: 0xffffffff
9937 05:59:13.438253 INFO: [APUAPC] D9_APC_2: 0x3fffff
9938 05:59:13.441295 INFO: [APUAPC] D9_APC_3: 0x0
9939 05:59:13.444749 INFO: [APUAPC] D10_APC_0: 0xffffffff
9940 05:59:13.448534 INFO: [APUAPC] D10_APC_1: 0xffffffff
9941 05:59:13.451613 INFO: [APUAPC] D10_APC_2: 0x3fffff
9942 05:59:13.454935 INFO: [APUAPC] D10_APC_3: 0x0
9943 05:59:13.458183 INFO: [APUAPC] D11_APC_0: 0xffffffff
9944 05:59:13.461504 INFO: [APUAPC] D11_APC_1: 0xffffffff
9945 05:59:13.464491 INFO: [APUAPC] D11_APC_2: 0x3fffff
9946 05:59:13.468078 INFO: [APUAPC] D11_APC_3: 0x0
9947 05:59:13.471627 INFO: [APUAPC] D12_APC_0: 0xffffffff
9948 05:59:13.474600 INFO: [APUAPC] D12_APC_1: 0xffffffff
9949 05:59:13.478110 INFO: [APUAPC] D12_APC_2: 0x3fffff
9950 05:59:13.481676 INFO: [APUAPC] D12_APC_3: 0x0
9951 05:59:13.484474 INFO: [APUAPC] D13_APC_0: 0xffffffff
9952 05:59:13.487836 INFO: [APUAPC] D13_APC_1: 0xffffffff
9953 05:59:13.491084 INFO: [APUAPC] D13_APC_2: 0x3fffff
9954 05:59:13.495082 INFO: [APUAPC] D13_APC_3: 0x0
9955 05:59:13.497833 INFO: [APUAPC] D14_APC_0: 0xffffffff
9956 05:59:13.501498 INFO: [APUAPC] D14_APC_1: 0xffffffff
9957 05:59:13.505002 INFO: [APUAPC] D14_APC_2: 0x3fffff
9958 05:59:13.507775 INFO: [APUAPC] D14_APC_3: 0x0
9959 05:59:13.511339 INFO: [APUAPC] D15_APC_0: 0xffffffff
9960 05:59:13.514814 INFO: [APUAPC] D15_APC_1: 0xffffffff
9961 05:59:13.517716 INFO: [APUAPC] D15_APC_2: 0x3fffff
9962 05:59:13.521236 INFO: [APUAPC] D15_APC_3: 0x0
9963 05:59:13.524764 INFO: [APUAPC] APC_CON: 0x4
9964 05:59:13.528382 INFO: [NOCDAPC] D0_APC_0: 0x0
9965 05:59:13.531239 INFO: [NOCDAPC] D0_APC_1: 0x0
9966 05:59:13.534713 INFO: [NOCDAPC] D1_APC_0: 0x0
9967 05:59:13.538159 INFO: [NOCDAPC] D1_APC_1: 0xfff
9968 05:59:13.538259 INFO: [NOCDAPC] D2_APC_0: 0x0
9969 05:59:13.541003 INFO: [NOCDAPC] D2_APC_1: 0xfff
9970 05:59:13.544470 INFO: [NOCDAPC] D3_APC_0: 0x0
9971 05:59:13.547741 INFO: [NOCDAPC] D3_APC_1: 0xfff
9972 05:59:13.551238 INFO: [NOCDAPC] D4_APC_0: 0x0
9973 05:59:13.554537 INFO: [NOCDAPC] D4_APC_1: 0xfff
9974 05:59:13.557415 INFO: [NOCDAPC] D5_APC_0: 0x0
9975 05:59:13.560747 INFO: [NOCDAPC] D5_APC_1: 0xfff
9976 05:59:13.564188 INFO: [NOCDAPC] D6_APC_0: 0x0
9977 05:59:13.567693 INFO: [NOCDAPC] D6_APC_1: 0xfff
9978 05:59:13.570984 INFO: [NOCDAPC] D7_APC_0: 0x0
9979 05:59:13.571105 INFO: [NOCDAPC] D7_APC_1: 0xfff
9980 05:59:13.574228 INFO: [NOCDAPC] D8_APC_0: 0x0
9981 05:59:13.577704 INFO: [NOCDAPC] D8_APC_1: 0xfff
9982 05:59:13.581076 INFO: [NOCDAPC] D9_APC_0: 0x0
9983 05:59:13.584283 INFO: [NOCDAPC] D9_APC_1: 0xfff
9984 05:59:13.587445 INFO: [NOCDAPC] D10_APC_0: 0x0
9985 05:59:13.591243 INFO: [NOCDAPC] D10_APC_1: 0xfff
9986 05:59:13.594426 INFO: [NOCDAPC] D11_APC_0: 0x0
9987 05:59:13.597445 INFO: [NOCDAPC] D11_APC_1: 0xfff
9988 05:59:13.600851 INFO: [NOCDAPC] D12_APC_0: 0x0
9989 05:59:13.604449 INFO: [NOCDAPC] D12_APC_1: 0xfff
9990 05:59:13.607749 INFO: [NOCDAPC] D13_APC_0: 0x0
9991 05:59:13.611018 INFO: [NOCDAPC] D13_APC_1: 0xfff
9992 05:59:13.611099 INFO: [NOCDAPC] D14_APC_0: 0x0
9993 05:59:13.614025 INFO: [NOCDAPC] D14_APC_1: 0xfff
9994 05:59:13.617502 INFO: [NOCDAPC] D15_APC_0: 0x0
9995 05:59:13.621121 INFO: [NOCDAPC] D15_APC_1: 0xfff
9996 05:59:13.623964 INFO: [NOCDAPC] APC_CON: 0x4
9997 05:59:13.627446 INFO: [APUAPC] set_apusys_apc done
9998 05:59:13.631059 INFO: [DEVAPC] devapc_init done
9999 05:59:13.633915 INFO: GICv3 without legacy support detected.
10000 05:59:13.640974 INFO: ARM GICv3 driver initialized in EL3
10001 05:59:13.643769 INFO: Maximum SPI INTID supported: 639
10002 05:59:13.647245 INFO: BL31: Initializing runtime services
10003 05:59:13.654313 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10004 05:59:13.654413 INFO: SPM: enable CPC mode
10005 05:59:13.660663 INFO: mcdi ready for mcusys-off-idle and system suspend
10006 05:59:13.664211 INFO: BL31: Preparing for EL3 exit to normal world
10007 05:59:13.670385 INFO: Entry point address = 0x80000000
10008 05:59:13.670466 INFO: SPSR = 0x8
10009 05:59:13.676791
10010 05:59:13.676896
10011 05:59:13.676987
10012 05:59:13.680022 Starting depthcharge on Spherion...
10013 05:59:13.680127
10014 05:59:13.680219 Wipe memory regions:
10015 05:59:13.680340
10016 05:59:13.680977 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10017 05:59:13.681076 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10018 05:59:13.681159 Setting prompt string to ['asurada:']
10019 05:59:13.681260 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10020 05:59:13.683008 [0x00000040000000, 0x00000054600000)
10021 05:59:13.805811
10022 05:59:13.805944 [0x00000054660000, 0x00000080000000)
10023 05:59:14.066258
10024 05:59:14.066401 [0x000000821a7280, 0x000000ffe64000)
10025 05:59:14.810333
10026 05:59:14.810476 [0x00000100000000, 0x00000240000000)
10027 05:59:16.699080
10028 05:59:16.701805 Initializing XHCI USB controller at 0x11200000.
10029 05:59:17.740249
10030 05:59:17.743440 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10031 05:59:17.743523
10032 05:59:17.743587
10033 05:59:17.743647
10034 05:59:17.743928 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10036 05:59:17.844278 asurada: tftpboot 192.168.201.1 12379448/tftp-deploy-81t6ocb1/kernel/image.itb 12379448/tftp-deploy-81t6ocb1/kernel/cmdline
10037 05:59:17.844460 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10038 05:59:17.844548 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10039 05:59:17.849149 tftpboot 192.168.201.1 12379448/tftp-deploy-81t6ocb1/kernel/image.ittp-deploy-81t6ocb1/kernel/cmdline
10040 05:59:17.849235
10041 05:59:17.849301 Waiting for link
10042 05:59:18.009880
10043 05:59:18.010022 R8152: Initializing
10044 05:59:18.010090
10045 05:59:18.012710 Version 9 (ocp_data = 6010)
10046 05:59:18.012817
10047 05:59:18.016538 R8152: Done initializing
10048 05:59:18.016622
10049 05:59:18.016688 Adding net device
10050 05:59:19.888512
10051 05:59:19.888650 done.
10052 05:59:19.888717
10053 05:59:19.888778 MAC: 00:e0:4c:78:7a:aa
10054 05:59:19.888836
10055 05:59:19.891879 Sending DHCP discover... done.
10056 05:59:19.891980
10057 05:59:19.895309 Waiting for reply... done.
10058 05:59:19.895392
10059 05:59:19.898229 Sending DHCP request... done.
10060 05:59:19.898311
10061 05:59:19.898375 Waiting for reply... done.
10062 05:59:19.898435
10063 05:59:19.901710 My ip is 192.168.201.12
10064 05:59:19.901791
10065 05:59:19.905115 The DHCP server ip is 192.168.201.1
10066 05:59:19.905197
10067 05:59:19.908460 TFTP server IP predefined by user: 192.168.201.1
10068 05:59:19.908542
10069 05:59:19.915166 Bootfile predefined by user: 12379448/tftp-deploy-81t6ocb1/kernel/image.itb
10070 05:59:19.915273
10071 05:59:19.918491 Sending tftp read request... done.
10072 05:59:19.918595
10073 05:59:19.921762 Waiting for the transfer...
10074 05:59:19.921879
10075 05:59:20.179974 00000000 ################################################################
10076 05:59:20.180104
10077 05:59:20.438949 00080000 ################################################################
10078 05:59:20.439109
10079 05:59:20.700704 00100000 ################################################################
10080 05:59:20.700873
10081 05:59:20.961044 00180000 ################################################################
10082 05:59:20.961184
10083 05:59:21.225204 00200000 ################################################################
10084 05:59:21.225349
10085 05:59:21.490711 00280000 ################################################################
10086 05:59:21.490879
10087 05:59:21.757354 00300000 ################################################################
10088 05:59:21.757506
10089 05:59:22.019554 00380000 ################################################################
10090 05:59:22.019704
10091 05:59:22.281471 00400000 ################################################################
10092 05:59:22.281611
10093 05:59:22.542073 00480000 ################################################################
10094 05:59:22.542217
10095 05:59:22.802328 00500000 ################################################################
10096 05:59:22.802480
10097 05:59:23.061209 00580000 ################################################################
10098 05:59:23.061375
10099 05:59:23.313065 00600000 ################################################################
10100 05:59:23.313204
10101 05:59:23.574019 00680000 ################################################################
10102 05:59:23.574164
10103 05:59:23.827030 00700000 ################################################################
10104 05:59:23.827176
10105 05:59:24.085743 00780000 ################################################################
10106 05:59:24.085890
10107 05:59:24.348580 00800000 ################################################################
10108 05:59:24.348728
10109 05:59:24.621019 00880000 ################################################################
10110 05:59:24.621175
10111 05:59:24.906560 00900000 ################################################################
10112 05:59:24.906747
10113 05:59:25.194555 00980000 ################################################################
10114 05:59:25.194702
10115 05:59:25.490629 00a00000 ################################################################
10116 05:59:25.490792
10117 05:59:25.793828 00a80000 ################################################################
10118 05:59:25.793961
10119 05:59:26.088586 00b00000 ################################################################
10120 05:59:26.088721
10121 05:59:26.353128 00b80000 ################################################################
10122 05:59:26.353289
10123 05:59:26.615630 00c00000 ################################################################
10124 05:59:26.615770
10125 05:59:26.884327 00c80000 ################################################################
10126 05:59:26.884473
10127 05:59:27.146152 00d00000 ################################################################
10128 05:59:27.146284
10129 05:59:27.414525 00d80000 ################################################################
10130 05:59:27.414685
10131 05:59:27.670011 00e00000 ################################################################
10132 05:59:27.670152
10133 05:59:27.963784 00e80000 ################################################################
10134 05:59:27.964320
10135 05:59:28.249817 00f00000 ################################################################
10136 05:59:28.249954
10137 05:59:28.524265 00f80000 ################################################################
10138 05:59:28.524438
10139 05:59:28.806123 01000000 ################################################################
10140 05:59:28.806260
10141 05:59:29.072746 01080000 ################################################################
10142 05:59:29.072882
10143 05:59:29.341475 01100000 ################################################################
10144 05:59:29.341614
10145 05:59:29.610571 01180000 ################################################################
10146 05:59:29.610758
10147 05:59:29.878469 01200000 ################################################################
10148 05:59:29.878648
10149 05:59:30.145694 01280000 ################################################################
10150 05:59:30.145834
10151 05:59:30.400233 01300000 ################################################################
10152 05:59:30.400427
10153 05:59:30.658836 01380000 ################################################################
10154 05:59:30.659029
10155 05:59:30.918019 01400000 ################################################################
10156 05:59:30.918190
10157 05:59:31.174342 01480000 ################################################################
10158 05:59:31.174539
10159 05:59:31.443245 01500000 ################################################################
10160 05:59:31.443425
10161 05:59:31.711863 01580000 ################################################################
10162 05:59:31.712007
10163 05:59:31.984020 01600000 ################################################################
10164 05:59:31.984183
10165 05:59:32.242146 01680000 ################################################################
10166 05:59:32.242339
10167 05:59:32.505717 01700000 ################################################################
10168 05:59:32.505898
10169 05:59:32.774435 01780000 ################################################################
10170 05:59:32.774631
10171 05:59:33.025154 01800000 ################################################################
10172 05:59:33.025304
10173 05:59:33.272170 01880000 ################################################################
10174 05:59:33.272353
10175 05:59:33.518842 01900000 ################################################################
10176 05:59:33.519036
10177 05:59:33.772641 01980000 ################################################################
10178 05:59:33.772791
10179 05:59:34.035859 01a00000 ################################################################
10180 05:59:34.035996
10181 05:59:34.311552 01a80000 ################################################################
10182 05:59:34.311720
10183 05:59:37.562802 01b00000 ################################################################
10184 05:59:37.563013
10185 05:59:37.563133 01b80000 ################################################################
10186 05:59:37.563245
10187 05:59:37.563352 01c00000 ################################################################
10188 05:59:37.563463
10189 05:59:37.563571 01c80000 ################################################################
10190 05:59:37.563684
10191 05:59:37.563789 01d00000 ################################################################
10192 05:59:37.563899
10193 05:59:37.564004 01d80000 ################################################################
10194 05:59:37.564124
10195 05:59:37.564229 01e00000 ################################################################
10196 05:59:37.564366
10197 05:59:37.564478 01e80000 ################################################################
10198 05:59:37.564593
10199 05:59:37.564689 01f00000 ################################################################
10200 05:59:37.564784
10201 05:59:37.564876 01f80000 ################################################################
10202 05:59:37.564967
10203 05:59:37.565058 02000000 ################################################################
10204 05:59:37.565164
10205 05:59:37.565259 02080000 ################################################################
10206 05:59:37.565356
10207 05:59:37.723025 02100000 ################################################################
10208 05:59:37.723187
10209 05:59:37.989024 02180000 ################################################################
10210 05:59:37.989241
10211 05:59:38.248701 02200000 ################################################################
10212 05:59:38.248858
10213 05:59:38.501318 02280000 ################################################################
10214 05:59:38.501506
10215 05:59:38.766831 02300000 ################################################################
10216 05:59:38.766971
10217 05:59:39.041607 02380000 ################################################################
10218 05:59:39.041826
10219 05:59:39.290762 02400000 ################################################################
10220 05:59:39.290953
10221 05:59:39.544683 02480000 ################################################################
10222 05:59:39.544834
10223 05:59:39.795610 02500000 ################################################################
10224 05:59:39.795759
10225 05:59:40.041927 02580000 ################################################################
10226 05:59:40.042109
10227 05:59:40.287198 02600000 ################################################################
10228 05:59:40.287382
10229 05:59:40.537620 02680000 ################################################################
10230 05:59:40.537787
10231 05:59:40.785156 02700000 ################################################################
10232 05:59:40.785305
10233 05:59:41.048187 02780000 ################################################################
10234 05:59:41.048416
10235 05:59:41.297744 02800000 ################################################################
10236 05:59:41.297918
10237 05:59:41.545756 02880000 ################################################################
10238 05:59:41.545896
10239 05:59:41.805107 02900000 ################################################################
10240 05:59:41.805250
10241 05:59:42.082344 02980000 ################################################################
10242 05:59:42.082487
10243 05:59:42.344235 02a00000 ################################################################
10244 05:59:42.344413
10245 05:59:42.606615 02a80000 ################################################################
10246 05:59:42.606769
10247 05:59:42.867064 02b00000 ################################################################
10248 05:59:42.867212
10249 05:59:43.134675 02b80000 ################################################################
10250 05:59:43.134863
10251 05:59:43.382941 02c00000 ################################################################
10252 05:59:43.383112
10253 05:59:43.654207 02c80000 ################################################################
10254 05:59:43.654367
10255 05:59:43.939176 02d00000 ################################################################
10256 05:59:43.939336
10257 05:59:44.201249 02d80000 ################################################################
10258 05:59:44.201477
10259 05:59:44.472199 02e00000 ################################################################
10260 05:59:44.472360
10261 05:59:44.746656 02e80000 ################################################################
10262 05:59:44.746805
10263 05:59:45.019848 02f00000 ################################################################
10264 05:59:45.020016
10265 05:59:45.299807 02f80000 ################################################################
10266 05:59:45.299964
10267 05:59:45.590645 03000000 ################################################################
10268 05:59:45.590785
10269 05:59:45.871182 03080000 ################################################################
10270 05:59:45.871352
10271 05:59:46.153751 03100000 ################################################################
10272 05:59:46.153899
10273 05:59:46.430191 03180000 ################################################################
10274 05:59:46.430329
10275 05:59:46.714465 03200000 ################################################################
10276 05:59:46.714608
10277 05:59:46.990194 03280000 ################################################################
10278 05:59:46.990341
10279 05:59:47.267428 03300000 ################################################################
10280 05:59:47.267572
10281 05:59:47.537236 03380000 ################################################################
10282 05:59:47.537383
10283 05:59:47.826715 03400000 ################################################################
10284 05:59:47.826859
10285 05:59:48.110021 03480000 ################################################################
10286 05:59:48.110157
10287 05:59:48.399732 03500000 ################################################################
10288 05:59:48.399867
10289 05:59:48.660500 03580000 ################################################################
10290 05:59:48.660643
10291 05:59:48.926023 03600000 ################################################################
10292 05:59:48.926165
10293 05:59:49.188452 03680000 ################################################################
10294 05:59:49.188665
10295 05:59:49.439949 03700000 ################################################################
10296 05:59:49.440102
10297 05:59:49.690514 03780000 ################################################################
10298 05:59:49.690667
10299 05:59:49.942682 03800000 ################################################################
10300 05:59:49.942834
10301 05:59:50.219259 03880000 ################################################################
10302 05:59:50.219395
10303 05:59:50.499857 03900000 ################################################################
10304 05:59:50.500006
10305 05:59:50.780923 03980000 ################################################################
10306 05:59:50.781075
10307 05:59:51.055856 03a00000 ################################################################
10308 05:59:51.056006
10309 05:59:51.340867 03a80000 ################################################################
10310 05:59:51.341018
10311 05:59:51.619742 03b00000 ################################################################
10312 05:59:51.619898
10313 05:59:51.880826 03b80000 ################################################################
10314 05:59:51.880975
10315 05:59:52.139567 03c00000 ################################################################
10316 05:59:52.139729
10317 05:59:52.393197 03c80000 ################################################################
10318 05:59:52.393337
10319 05:59:52.648022 03d00000 ################################################################
10320 05:59:52.648172
10321 05:59:52.898042 03d80000 ################################################################
10322 05:59:52.898199
10323 05:59:53.157609 03e00000 ################################################################
10324 05:59:53.157752
10325 05:59:53.414304 03e80000 ################################################################
10326 05:59:53.414436
10327 05:59:53.678046 03f00000 ################################################################
10328 05:59:53.678178
10329 05:59:53.952251 03f80000 ################################################################
10330 05:59:53.952429
10331 05:59:54.209828 04000000 ################################################################
10332 05:59:54.209965
10333 05:59:54.465613 04080000 ################################################################
10334 05:59:54.465747
10335 05:59:54.726598 04100000 ################################################################
10336 05:59:54.726738
10337 05:59:54.996796 04180000 ################################################################
10338 05:59:54.996926
10339 05:59:55.250557 04200000 ################################################################
10340 05:59:55.250721
10341 05:59:55.510150 04280000 ################################################################
10342 05:59:55.510311
10343 05:59:55.769733 04300000 ################################################################
10344 05:59:55.769867
10345 05:59:56.023268 04380000 ################################################################
10346 05:59:56.023399
10347 05:59:56.284921 04400000 ################################################################
10348 05:59:56.285053
10349 05:59:56.552087 04480000 ################################################################
10350 05:59:56.552221
10351 05:59:56.813139 04500000 ################################################################
10352 05:59:56.813322
10353 05:59:57.064680 04580000 ################################################################
10354 05:59:57.064843
10355 05:59:57.326289 04600000 ################################################################
10356 05:59:57.326419
10357 05:59:57.584978 04680000 ################################################################
10358 05:59:57.585141
10359 05:59:57.846251 04700000 ################################################################
10360 05:59:57.846388
10361 05:59:58.124038 04780000 ################################################################
10362 05:59:58.124173
10363 05:59:58.386238 04800000 ################################################################
10364 05:59:58.386374
10365 05:59:58.664169 04880000 ################################################################
10366 05:59:58.664328
10367 05:59:58.930550 04900000 ################################################################
10368 05:59:58.930775
10369 05:59:59.202844 04980000 ################################################################
10370 05:59:59.202996
10371 05:59:59.458380 04a00000 ################################################################
10372 05:59:59.458514
10373 05:59:59.736058 04a80000 ################################################################
10374 05:59:59.736223
10375 05:59:59.989746 04b00000 ################################################################
10376 05:59:59.989877
10377 06:00:00.246970 04b80000 ################################################################
10378 06:00:00.247127
10379 06:00:00.503267 04c00000 ################################################################
10380 06:00:00.503423
10381 06:00:00.755579 04c80000 ################################################################
10382 06:00:00.755715
10383 06:00:01.012526 04d00000 ################################################################
10384 06:00:01.012658
10385 06:00:01.269506 04d80000 ################################################################
10386 06:00:01.269641
10387 06:00:01.543201 04e00000 ################################################################
10388 06:00:01.543334
10389 06:00:01.810698 04e80000 ################################################################
10390 06:00:01.810833
10391 06:00:02.071707 04f00000 ################################################################
10392 06:00:02.071843
10393 06:00:02.325262 04f80000 ################################################################
10394 06:00:02.325396
10395 06:00:02.588309 05000000 ################################################################
10396 06:00:02.588470
10397 06:00:02.866418 05080000 ################################################################
10398 06:00:02.866584
10399 06:00:03.129472 05100000 ################################################################
10400 06:00:03.129604
10401 06:00:03.396780 05180000 ################################################################
10402 06:00:03.396950
10403 06:00:03.662994 05200000 ################################################################
10404 06:00:03.663152
10405 06:00:03.934319 05280000 ################################################################
10406 06:00:03.934490
10407 06:00:04.200443 05300000 ################################################################
10408 06:00:04.200582
10409 06:00:04.476485 05380000 ################################################################
10410 06:00:04.476621
10411 06:00:04.760607 05400000 ################################################################
10412 06:00:04.760744
10413 06:00:05.018970 05480000 ################################################################
10414 06:00:05.019115
10415 06:00:05.276347 05500000 ################################################################
10416 06:00:05.276482
10417 06:00:05.544852 05580000 ################################################################
10418 06:00:05.545015
10419 06:00:05.803269 05600000 ################################################################
10420 06:00:05.803439
10421 06:00:06.061024 05680000 ################################################################
10422 06:00:06.061159
10423 06:00:06.325515 05700000 ################################################################
10424 06:00:06.325679
10425 06:00:06.589226 05780000 ################################################################
10426 06:00:06.589368
10427 06:00:06.848682 05800000 ################################################################
10428 06:00:06.848856
10429 06:00:07.109425 05880000 ################################################################
10430 06:00:07.109560
10431 06:00:07.371487 05900000 ################################################################
10432 06:00:07.371649
10433 06:00:07.626706 05980000 ################################################################
10434 06:00:07.626848
10435 06:00:07.884474 05a00000 ################################################################
10436 06:00:07.884604
10437 06:00:08.139531 05a80000 ################################################################
10438 06:00:08.139698
10439 06:00:08.388664 05b00000 ################################################################
10440 06:00:08.388795
10441 06:00:08.631732 05b80000 ################################################################
10442 06:00:08.631905
10443 06:00:08.878719 05c00000 ################################################################
10444 06:00:08.878876
10445 06:00:09.129226 05c80000 ################################################################
10446 06:00:09.129368
10447 06:00:09.379015 05d00000 ################################################################
10448 06:00:09.379155
10449 06:00:09.636467 05d80000 ################################################################
10450 06:00:09.636648
10451 06:00:09.884089 05e00000 ################################################################
10452 06:00:09.884222
10453 06:00:10.136551 05e80000 ################################################################
10454 06:00:10.136689
10455 06:00:10.389396 05f00000 ################################################################
10456 06:00:10.389548
10457 06:00:10.641981 05f80000 ################################################################
10458 06:00:10.642124
10459 06:00:10.902021 06000000 ################################################################
10460 06:00:10.902153
10461 06:00:11.161536 06080000 ################################################################
10462 06:00:11.161721
10463 06:00:11.415225 06100000 ################################################################
10464 06:00:11.415390
10465 06:00:11.676324 06180000 ################################################################
10466 06:00:11.676458
10467 06:00:11.939609 06200000 ################################################################
10468 06:00:11.939750
10469 06:00:12.195001 06280000 ################################################################
10470 06:00:12.195137
10471 06:00:12.448966 06300000 ################################################################
10472 06:00:12.449103
10473 06:00:12.702124 06380000 ################################################################
10474 06:00:12.702261
10475 06:00:12.955086 06400000 ################################################################
10476 06:00:12.955222
10477 06:00:13.204477 06480000 ################################################################
10478 06:00:13.204612
10479 06:00:13.455662 06500000 ################################################################
10480 06:00:13.455820
10481 06:00:13.711697 06580000 ################################################################
10482 06:00:13.711866
10483 06:00:13.958299 06600000 ################################################################
10484 06:00:13.958469
10485 06:00:14.204689 06680000 ################################################################
10486 06:00:14.204857
10487 06:00:14.453929 06700000 ################################################################
10488 06:00:14.454089
10489 06:00:14.708317 06780000 ################################################################
10490 06:00:14.708451
10491 06:00:14.967696 06800000 ################################################################
10492 06:00:14.967865
10493 06:00:15.117330 06880000 ###################################### done.
10494 06:00:15.117464
10495 06:00:15.120101 The bootfile was 109879350 bytes long.
10496 06:00:15.120207
10497 06:00:15.123682 Sending tftp read request... done.
10498 06:00:15.123772
10499 06:00:15.123841 Waiting for the transfer...
10500 06:00:15.123947
10501 06:00:15.127252 00000000 # done.
10502 06:00:15.127339
10503 06:00:15.133836 Command line loaded dynamically from TFTP file: 12379448/tftp-deploy-81t6ocb1/kernel/cmdline
10504 06:00:15.133957
10505 06:00:15.147323 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10506 06:00:15.147421
10507 06:00:15.150401 Loading FIT.
10508 06:00:15.150510
10509 06:00:15.153873 Image ramdisk-1 has 98348206 bytes.
10510 06:00:15.153976
10511 06:00:15.154069 Image fdt-1 has 47278 bytes.
10512 06:00:15.157303
10513 06:00:15.157381 Image kernel-1 has 11481830 bytes.
10514 06:00:15.157444
10515 06:00:15.167033 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10516 06:00:15.167149
10517 06:00:15.183386 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10518 06:00:15.183503
10519 06:00:15.190426 Choosing best match conf-1 for compat google,spherion-rev2.
10520 06:00:15.194499
10521 06:00:15.199222 Connected to device vid:did:rid of 1ae0:0028:00
10522 06:00:15.207585
10523 06:00:15.210284 tpm_get_response: command 0x17b, return code 0x0
10524 06:00:15.210388
10525 06:00:15.213690 ec_init: CrosEC protocol v3 supported (256, 248)
10526 06:00:15.218112
10527 06:00:15.220898 tpm_cleanup: add release locality here.
10528 06:00:15.221004
10529 06:00:15.221103 Shutting down all USB controllers.
10530 06:00:15.224648
10531 06:00:15.224770 Removing current net device
10532 06:00:15.224871
10533 06:00:15.231626 Exiting depthcharge with code 4 at timestamp: 90815387
10534 06:00:15.231707
10535 06:00:15.234456 LZMA decompressing kernel-1 to 0x821a6718
10536 06:00:15.234564
10537 06:00:15.238089 LZMA decompressing kernel-1 to 0x40000000
10538 06:00:16.675721
10539 06:00:16.675886 jumping to kernel
10540 06:00:16.676576 end: 2.2.4 bootloader-commands (duration 00:01:03) [common]
10541 06:00:16.676680 start: 2.2.5 auto-login-action (timeout 00:03:22) [common]
10542 06:00:16.676771 Setting prompt string to ['Linux version [0-9]']
10543 06:00:16.676852 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10544 06:00:16.676934 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10545 06:00:16.758403
10546 06:00:16.761635 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10547 06:00:16.765062 start: 2.2.5.1 login-action (timeout 00:03:22) [common]
10548 06:00:16.765183 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10549 06:00:16.765261 Setting prompt string to []
10550 06:00:16.765342 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10551 06:00:16.765424 Using line separator: #'\n'#
10552 06:00:16.765490 No login prompt set.
10553 06:00:16.765557 Parsing kernel messages
10554 06:00:16.765623 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10555 06:00:16.765788 [login-action] Waiting for messages, (timeout 00:03:22)
10556 06:00:16.784761 [ 0.000000] Linux version 6.1.67-cip12 (KernelCI@build-j59664-arm64-gcc-10-defconfig-arm64-chromebook-fgc24) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023
10557 06:00:16.788144 [ 0.000000] random: crng init done
10558 06:00:16.794588 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10559 06:00:16.798272 [ 0.000000] efi: UEFI not found.
10560 06:00:16.804743 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10561 06:00:16.811542 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10562 06:00:16.821339 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10563 06:00:16.831541 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10564 06:00:16.837873 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10565 06:00:16.844275 [ 0.000000] printk: bootconsole [mtk8250] enabled
10566 06:00:16.851045 [ 0.000000] NUMA: No NUMA configuration found
10567 06:00:16.857938 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10568 06:00:16.861302 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10569 06:00:16.864260 [ 0.000000] Zone ranges:
10570 06:00:16.871131 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10571 06:00:16.874342 [ 0.000000] DMA32 empty
10572 06:00:16.881387 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10573 06:00:16.884515 [ 0.000000] Movable zone start for each node
10574 06:00:16.887893 [ 0.000000] Early memory node ranges
10575 06:00:16.894193 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10576 06:00:16.900797 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10577 06:00:16.907857 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10578 06:00:16.910637 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10579 06:00:16.917685 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10580 06:00:16.927296 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10581 06:00:16.982905 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10582 06:00:16.989164 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10583 06:00:16.996392 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10584 06:00:16.999498 [ 0.000000] psci: probing for conduit method from DT.
10585 06:00:17.005889 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10586 06:00:17.009327 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10587 06:00:17.016304 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10588 06:00:17.019788 [ 0.000000] psci: SMC Calling Convention v1.2
10589 06:00:17.026222 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10590 06:00:17.029654 [ 0.000000] Detected VIPT I-cache on CPU0
10591 06:00:17.036319 [ 0.000000] CPU features: detected: GIC system register CPU interface
10592 06:00:17.042343 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10593 06:00:17.049546 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10594 06:00:17.055904 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10595 06:00:17.062456 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10596 06:00:17.069486 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10597 06:00:17.075927 [ 0.000000] alternatives: applying boot alternatives
10598 06:00:17.079267 [ 0.000000] Fallback order for Node 0: 0
10599 06:00:17.086110 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10600 06:00:17.088849 [ 0.000000] Policy zone: Normal
10601 06:00:17.106071 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10602 06:00:17.115423 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10603 06:00:17.126916 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10604 06:00:17.136568 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10605 06:00:17.143379 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10606 06:00:17.146704 <6>[ 0.000000] software IO TLB: area num 8.
10607 06:00:17.204054 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10608 06:00:17.353581 <6>[ 0.000000] Memory: 7872676K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 480092K reserved, 32768K cma-reserved)
10609 06:00:17.359645 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10610 06:00:17.366768 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10611 06:00:17.369967 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10612 06:00:17.376897 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10613 06:00:17.383002 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10614 06:00:17.386222 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10615 06:00:17.396613 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10616 06:00:17.403150 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10617 06:00:17.406734 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10618 06:00:17.414464 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10619 06:00:17.417398 <6>[ 0.000000] GICv3: 608 SPIs implemented
10620 06:00:17.423979 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10621 06:00:17.427371 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10622 06:00:17.430860 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10623 06:00:17.440405 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10624 06:00:17.450740 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10625 06:00:17.464132 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10626 06:00:17.470430 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10627 06:00:17.480095 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10628 06:00:17.492956 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10629 06:00:17.499576 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10630 06:00:17.506370 <6>[ 0.009184] Console: colour dummy device 80x25
10631 06:00:17.516050 <6>[ 0.013940] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10632 06:00:17.523252 <6>[ 0.024446] pid_max: default: 32768 minimum: 301
10633 06:00:17.526145 <6>[ 0.029317] LSM: Security Framework initializing
10634 06:00:17.532515 <6>[ 0.034255] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10635 06:00:17.542829 <6>[ 0.042068] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10636 06:00:17.549382 <6>[ 0.051528] cblist_init_generic: Setting adjustable number of callback queues.
10637 06:00:17.555935 <6>[ 0.058973] cblist_init_generic: Setting shift to 3 and lim to 1.
10638 06:00:17.566137 <6>[ 0.065350] cblist_init_generic: Setting adjustable number of callback queues.
10639 06:00:17.572604 <6>[ 0.072778] cblist_init_generic: Setting shift to 3 and lim to 1.
10640 06:00:17.576104 <6>[ 0.079179] rcu: Hierarchical SRCU implementation.
10641 06:00:17.582484 <6>[ 0.084225] rcu: Max phase no-delay instances is 1000.
10642 06:00:17.589230 <6>[ 0.091280] EFI services will not be available.
10643 06:00:17.592860 <6>[ 0.096238] smp: Bringing up secondary CPUs ...
10644 06:00:17.600529 <6>[ 0.101286] Detected VIPT I-cache on CPU1
10645 06:00:17.607114 <6>[ 0.101355] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10646 06:00:17.614228 <6>[ 0.101384] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10647 06:00:17.617435 <6>[ 0.101716] Detected VIPT I-cache on CPU2
10648 06:00:17.627019 <6>[ 0.101765] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10649 06:00:17.633783 <6>[ 0.101780] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10650 06:00:17.637385 <6>[ 0.102035] Detected VIPT I-cache on CPU3
10651 06:00:17.643744 <6>[ 0.102081] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10652 06:00:17.650877 <6>[ 0.102095] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10653 06:00:17.654116 <6>[ 0.102400] CPU features: detected: Spectre-v4
10654 06:00:17.660405 <6>[ 0.102407] CPU features: detected: Spectre-BHB
10655 06:00:17.664165 <6>[ 0.102412] Detected PIPT I-cache on CPU4
10656 06:00:17.670340 <6>[ 0.102469] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10657 06:00:17.677709 <6>[ 0.102486] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10658 06:00:17.684192 <6>[ 0.102778] Detected PIPT I-cache on CPU5
10659 06:00:17.690413 <6>[ 0.102840] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10660 06:00:17.697374 <6>[ 0.102857] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10661 06:00:17.700274 <6>[ 0.103140] Detected PIPT I-cache on CPU6
10662 06:00:17.707412 <6>[ 0.103205] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10663 06:00:17.713846 <6>[ 0.103221] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10664 06:00:17.717048 <6>[ 0.103519] Detected PIPT I-cache on CPU7
10665 06:00:17.727244 <6>[ 0.103585] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10666 06:00:17.734150 <6>[ 0.103602] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10667 06:00:17.737434 <6>[ 0.103650] smp: Brought up 1 node, 8 CPUs
10668 06:00:17.740693 <6>[ 0.245229] SMP: Total of 8 processors activated.
10669 06:00:17.747419 <6>[ 0.250151] CPU features: detected: 32-bit EL0 Support
10670 06:00:17.757339 <6>[ 0.255514] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10671 06:00:17.763758 <6>[ 0.264314] CPU features: detected: Common not Private translations
10672 06:00:17.767318 <6>[ 0.270790] CPU features: detected: CRC32 instructions
10673 06:00:17.773653 <6>[ 0.276174] CPU features: detected: RCpc load-acquire (LDAPR)
10674 06:00:17.780356 <6>[ 0.282171] CPU features: detected: LSE atomic instructions
10675 06:00:17.787255 <6>[ 0.287952] CPU features: detected: Privileged Access Never
10676 06:00:17.790840 <6>[ 0.293732] CPU features: detected: RAS Extension Support
10677 06:00:17.797286 <6>[ 0.299340] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10678 06:00:17.803862 <6>[ 0.306561] CPU: All CPU(s) started at EL2
10679 06:00:17.807397 <6>[ 0.310905] alternatives: applying system-wide alternatives
10680 06:00:17.818912 <6>[ 0.321619] devtmpfs: initialized
10681 06:00:17.831203 <6>[ 0.330428] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10682 06:00:17.841056 <6>[ 0.340392] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10683 06:00:17.847659 <6>[ 0.348613] pinctrl core: initialized pinctrl subsystem
10684 06:00:17.850441 <6>[ 0.355282] DMI not present or invalid.
10685 06:00:17.857550 <6>[ 0.359686] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10686 06:00:17.867576 <6>[ 0.366560] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10687 06:00:17.874058 <6>[ 0.374150] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10688 06:00:17.884239 <6>[ 0.382374] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10689 06:00:17.887127 <6>[ 0.390619] audit: initializing netlink subsys (disabled)
10690 06:00:17.897693 <5>[ 0.396312] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10691 06:00:17.904473 <6>[ 0.397012] thermal_sys: Registered thermal governor 'step_wise'
10692 06:00:17.910870 <6>[ 0.404278] thermal_sys: Registered thermal governor 'power_allocator'
10693 06:00:17.914071 <6>[ 0.410532] cpuidle: using governor menu
10694 06:00:17.917297 <6>[ 0.421489] NET: Registered PF_QIPCRTR protocol family
10695 06:00:17.927461 <6>[ 0.426961] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10696 06:00:17.930453 <6>[ 0.434059] ASID allocator initialised with 32768 entries
10697 06:00:17.937477 <6>[ 0.440622] Serial: AMBA PL011 UART driver
10698 06:00:17.946168 <4>[ 0.449380] Trying to register duplicate clock ID: 134
10699 06:00:18.000757 <6>[ 0.506776] KASLR enabled
10700 06:00:18.014942 <6>[ 0.514496] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10701 06:00:18.021637 <6>[ 0.521512] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10702 06:00:18.027991 <6>[ 0.528003] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10703 06:00:18.034835 <6>[ 0.535008] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10704 06:00:18.041326 <6>[ 0.541493] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10705 06:00:18.048518 <6>[ 0.548498] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10706 06:00:18.055093 <6>[ 0.554987] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10707 06:00:18.061437 <6>[ 0.561989] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10708 06:00:18.064689 <6>[ 0.569487] ACPI: Interpreter disabled.
10709 06:00:18.072570 <6>[ 0.575896] iommu: Default domain type: Translated
10710 06:00:18.079910 <6>[ 0.581006] iommu: DMA domain TLB invalidation policy: strict mode
10711 06:00:18.083246 <5>[ 0.587661] SCSI subsystem initialized
10712 06:00:18.089203 <6>[ 0.591822] usbcore: registered new interface driver usbfs
10713 06:00:18.096386 <6>[ 0.597556] usbcore: registered new interface driver hub
10714 06:00:18.099301 <6>[ 0.603109] usbcore: registered new device driver usb
10715 06:00:18.106559 <6>[ 0.609203] pps_core: LinuxPPS API ver. 1 registered
10716 06:00:18.116214 <6>[ 0.614396] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10717 06:00:18.119759 <6>[ 0.623735] PTP clock support registered
10718 06:00:18.122466 <6>[ 0.627976] EDAC MC: Ver: 3.0.0
10719 06:00:18.130389 <6>[ 0.633126] FPGA manager framework
10720 06:00:18.136977 <6>[ 0.636804] Advanced Linux Sound Architecture Driver Initialized.
10721 06:00:18.140018 <6>[ 0.643570] vgaarb: loaded
10722 06:00:18.146573 <6>[ 0.646718] clocksource: Switched to clocksource arch_sys_counter
10723 06:00:18.150217 <5>[ 0.653148] VFS: Disk quotas dquot_6.6.0
10724 06:00:18.156617 <6>[ 0.657333] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10725 06:00:18.160199 <6>[ 0.664520] pnp: PnP ACPI: disabled
10726 06:00:18.168139 <6>[ 0.671191] NET: Registered PF_INET protocol family
10727 06:00:18.178152 <6>[ 0.676769] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10728 06:00:18.189215 <6>[ 0.689074] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10729 06:00:18.199492 <6>[ 0.697885] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10730 06:00:18.206277 <6>[ 0.705855] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10731 06:00:18.212528 <6>[ 0.714556] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10732 06:00:18.224373 <6>[ 0.724301] TCP: Hash tables configured (established 65536 bind 65536)
10733 06:00:18.231773 <6>[ 0.731157] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10734 06:00:18.238314 <6>[ 0.738353] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10735 06:00:18.244712 <6>[ 0.746055] NET: Registered PF_UNIX/PF_LOCAL protocol family
10736 06:00:18.251222 <6>[ 0.752196] RPC: Registered named UNIX socket transport module.
10737 06:00:18.254870 <6>[ 0.758349] RPC: Registered udp transport module.
10738 06:00:18.261464 <6>[ 0.763282] RPC: Registered tcp transport module.
10739 06:00:18.267865 <6>[ 0.768213] RPC: Registered tcp NFSv4.1 backchannel transport module.
10740 06:00:18.271475 <6>[ 0.774877] PCI: CLS 0 bytes, default 64
10741 06:00:18.274275 <6>[ 0.779189] Unpacking initramfs...
10742 06:00:18.299996 <6>[ 0.799301] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10743 06:00:18.309597 <6>[ 0.807951] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10744 06:00:18.312862 <6>[ 0.816813] kvm [1]: IPA Size Limit: 40 bits
10745 06:00:18.319875 <6>[ 0.821339] kvm [1]: GICv3: no GICV resource entry
10746 06:00:18.323132 <6>[ 0.826359] kvm [1]: disabling GICv2 emulation
10747 06:00:18.329320 <6>[ 0.831059] kvm [1]: GIC system register CPU interface enabled
10748 06:00:18.332888 <6>[ 0.837216] kvm [1]: vgic interrupt IRQ18
10749 06:00:18.339329 <6>[ 0.841562] kvm [1]: VHE mode initialized successfully
10750 06:00:18.345848 <5>[ 0.848051] Initialise system trusted keyrings
10751 06:00:18.352249 <6>[ 0.852826] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10752 06:00:18.360168 <6>[ 0.862790] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10753 06:00:18.366659 <5>[ 0.869152] NFS: Registering the id_resolver key type
10754 06:00:18.369804 <5>[ 0.874456] Key type id_resolver registered
10755 06:00:18.376123 <5>[ 0.878874] Key type id_legacy registered
10756 06:00:18.382914 <6>[ 0.883153] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10757 06:00:18.389252 <6>[ 0.890073] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10758 06:00:18.396149 <6>[ 0.897796] 9p: Installing v9fs 9p2000 file system support
10759 06:00:18.433036 <5>[ 0.936021] Key type asymmetric registered
10760 06:00:18.436118 <5>[ 0.940352] Asymmetric key parser 'x509' registered
10761 06:00:18.446168 <6>[ 0.945484] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10762 06:00:18.449682 <6>[ 0.953127] io scheduler mq-deadline registered
10763 06:00:18.452474 <6>[ 0.957911] io scheduler kyber registered
10764 06:00:18.471913 <6>[ 0.974782] EINJ: ACPI disabled.
10765 06:00:18.503598 <4>[ 0.999957] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10766 06:00:18.513749 <4>[ 1.010593] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10767 06:00:18.528645 <6>[ 1.031339] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10768 06:00:18.536238 <6>[ 1.039359] printk: console [ttyS0] disabled
10769 06:00:18.564417 <6>[ 1.064005] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10770 06:00:18.571050 <6>[ 1.073493] printk: console [ttyS0] enabled
10771 06:00:18.573905 <6>[ 1.073493] printk: console [ttyS0] enabled
10772 06:00:18.581060 <6>[ 1.082385] printk: bootconsole [mtk8250] disabled
10773 06:00:18.583964 <6>[ 1.082385] printk: bootconsole [mtk8250] disabled
10774 06:00:18.590977 <6>[ 1.093642] SuperH (H)SCI(F) driver initialized
10775 06:00:18.594330 <6>[ 1.098942] msm_serial: driver initialized
10776 06:00:18.607950 <6>[ 1.107929] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10777 06:00:18.618007 <6>[ 1.116475] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10778 06:00:18.624672 <6>[ 1.125018] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10779 06:00:18.635028 <6>[ 1.133651] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10780 06:00:18.644651 <6>[ 1.142358] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10781 06:00:18.651496 <6>[ 1.151078] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10782 06:00:18.661466 <6>[ 1.159619] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10783 06:00:18.668109 <6>[ 1.168429] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10784 06:00:18.678354 <6>[ 1.176973] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10785 06:00:18.690056 <6>[ 1.192631] loop: module loaded
10786 06:00:18.696302 <6>[ 1.198324] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10787 06:00:18.718559 <4>[ 1.221625] mtk-pmic-keys: Failed to locate of_node [id: -1]
10788 06:00:18.725677 <6>[ 1.228618] megasas: 07.719.03.00-rc1
10789 06:00:18.735347 <6>[ 1.238417] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10790 06:00:18.743260 <6>[ 1.246104] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10791 06:00:18.760370 <6>[ 1.262958] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10792 06:00:18.816919 <6>[ 1.313124] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10793 06:00:22.321880 <6>[ 4.825622] Freeing initrd memory: 96040K
10794 06:00:22.332920 <6>[ 4.836252] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10795 06:00:22.344240 <6>[ 4.847440] tun: Universal TUN/TAP device driver, 1.6
10796 06:00:22.347533 <6>[ 4.853511] thunder_xcv, ver 1.0
10797 06:00:22.351016 <6>[ 4.857022] thunder_bgx, ver 1.0
10798 06:00:22.353794 <6>[ 4.860517] nicpf, ver 1.0
10799 06:00:22.364857 <6>[ 4.864543] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10800 06:00:22.367705 <6>[ 4.872018] hns3: Copyright (c) 2017 Huawei Corporation.
10801 06:00:22.371241 <6>[ 4.877607] hclge is initializing
10802 06:00:22.377789 <6>[ 4.881187] e1000: Intel(R) PRO/1000 Network Driver
10803 06:00:22.384427 <6>[ 4.886317] e1000: Copyright (c) 1999-2006 Intel Corporation.
10804 06:00:22.387786 <6>[ 4.892330] e1000e: Intel(R) PRO/1000 Network Driver
10805 06:00:22.394311 <6>[ 4.897544] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10806 06:00:22.400850 <6>[ 4.903729] igb: Intel(R) Gigabit Ethernet Network Driver
10807 06:00:22.407720 <6>[ 4.909379] igb: Copyright (c) 2007-2014 Intel Corporation.
10808 06:00:22.414395 <6>[ 4.915219] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10809 06:00:22.420942 <6>[ 4.921737] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10810 06:00:22.424184 <6>[ 4.928197] sky2: driver version 1.30
10811 06:00:22.430503 <6>[ 4.933192] VFIO - User Level meta-driver version: 0.3
10812 06:00:22.438549 <6>[ 4.941435] usbcore: registered new interface driver usb-storage
10813 06:00:22.444915 <6>[ 4.947882] usbcore: registered new device driver onboard-usb-hub
10814 06:00:22.453398 <6>[ 4.957061] mt6397-rtc mt6359-rtc: registered as rtc0
10815 06:00:22.463285 <6>[ 4.962522] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-25T05:57:47 UTC (1703483867)
10816 06:00:22.466816 <6>[ 4.972105] i2c_dev: i2c /dev entries driver
10817 06:00:22.483787 <6>[ 4.983904] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10818 06:00:22.503374 <6>[ 5.006896] cpu cpu0: EM: created perf domain
10819 06:00:22.506570 <6>[ 5.011829] cpu cpu4: EM: created perf domain
10820 06:00:22.514059 <6>[ 5.017466] sdhci: Secure Digital Host Controller Interface driver
10821 06:00:22.520693 <6>[ 5.023900] sdhci: Copyright(c) Pierre Ossman
10822 06:00:22.527087 <6>[ 5.028853] Synopsys Designware Multimedia Card Interface Driver
10823 06:00:22.533737 <6>[ 5.035485] sdhci-pltfm: SDHCI platform and OF driver helper
10824 06:00:22.537070 <6>[ 5.035519] mmc0: CQHCI version 5.10
10825 06:00:22.544178 <6>[ 5.045522] ledtrig-cpu: registered to indicate activity on CPUs
10826 06:00:22.550490 <6>[ 5.052648] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10827 06:00:22.557476 <6>[ 5.059702] usbcore: registered new interface driver usbhid
10828 06:00:22.560418 <6>[ 5.065524] usbhid: USB HID core driver
10829 06:00:22.567481 <6>[ 5.069713] spi_master spi0: will run message pump with realtime priority
10830 06:00:22.613917 <6>[ 5.110940] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10831 06:00:22.633709 <6>[ 5.126589] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10832 06:00:22.640417 <6>[ 5.141545] cros-ec-spi spi0.0: Chrome EC device registered
10833 06:00:22.643686 <6>[ 5.147618] mmc0: Command Queue Engine enabled
10834 06:00:22.650387 <6>[ 5.152353] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10835 06:00:22.657226 <6>[ 5.159573] mmcblk0: mmc0:0001 DA4128 116 GiB
10836 06:00:22.663475 <6>[ 5.162358] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10837 06:00:22.670094 <6>[ 5.169773] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10838 06:00:22.677183 <6>[ 5.174677] NET: Registered PF_PACKET protocol family
10839 06:00:22.680067 <6>[ 5.180901] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10840 06:00:22.687193 <6>[ 5.184900] 9pnet: Installing 9P2000 support
10841 06:00:22.690040 <6>[ 5.190626] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10842 06:00:22.697211 <5>[ 5.194578] Key type dns_resolver registered
10843 06:00:22.703426 <6>[ 5.200377] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10844 06:00:22.707068 <6>[ 5.204855] registered taskstats version 1
10845 06:00:22.712985 <5>[ 5.215184] Loading compiled-in X.509 certificates
10846 06:00:22.740010 <4>[ 5.236929] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10847 06:00:22.750040 <4>[ 5.247609] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10848 06:00:22.756819 <3>[ 5.258134] debugfs: File 'uA_load' in directory '/' already present!
10849 06:00:22.763297 <3>[ 5.264833] debugfs: File 'min_uV' in directory '/' already present!
10850 06:00:22.769775 <3>[ 5.271507] debugfs: File 'max_uV' in directory '/' already present!
10851 06:00:22.776431 <3>[ 5.278120] debugfs: File 'constraint_flags' in directory '/' already present!
10852 06:00:22.787347 <3>[ 5.287760] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10853 06:00:22.797484 <6>[ 5.300840] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10854 06:00:22.804495 <6>[ 5.307800] xhci-mtk 11200000.usb: xHCI Host Controller
10855 06:00:22.811182 <6>[ 5.313311] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10856 06:00:22.821309 <6>[ 5.321154] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10857 06:00:22.827922 <6>[ 5.330569] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10858 06:00:22.834224 <6>[ 5.336639] xhci-mtk 11200000.usb: xHCI Host Controller
10859 06:00:22.841587 <6>[ 5.342114] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10860 06:00:22.848165 <6>[ 5.349761] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10861 06:00:22.854052 <6>[ 5.357411] hub 1-0:1.0: USB hub found
10862 06:00:22.857722 <6>[ 5.361417] hub 1-0:1.0: 1 port detected
10863 06:00:22.864196 <6>[ 5.365683] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10864 06:00:22.871249 <6>[ 5.374328] hub 2-0:1.0: USB hub found
10865 06:00:22.874127 <6>[ 5.378343] hub 2-0:1.0: 1 port detected
10866 06:00:22.882756 <6>[ 5.386473] mtk-msdc 11f70000.mmc: Got CD GPIO
10867 06:00:22.893102 <6>[ 5.392822] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10868 06:00:22.899602 <6>[ 5.400840] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10869 06:00:22.909897 <4>[ 5.408748] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10870 06:00:22.916112 <6>[ 5.418278] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10871 06:00:22.926085 <6>[ 5.426355] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10872 06:00:22.932961 <6>[ 5.434350] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10873 06:00:22.943131 <6>[ 5.442268] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10874 06:00:22.949460 <6>[ 5.450085] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10875 06:00:22.959095 <6>[ 5.457902] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10876 06:00:22.969546 <6>[ 5.468289] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10877 06:00:22.976015 <6>[ 5.476648] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10878 06:00:22.986062 <6>[ 5.485006] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10879 06:00:22.992421 <6>[ 5.493345] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10880 06:00:23.002461 <6>[ 5.501683] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10881 06:00:23.009175 <6>[ 5.510022] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10882 06:00:23.019280 <6>[ 5.518361] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10883 06:00:23.025596 <6>[ 5.526699] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10884 06:00:23.035435 <6>[ 5.535050] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10885 06:00:23.042187 <6>[ 5.543388] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10886 06:00:23.052227 <6>[ 5.551726] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10887 06:00:23.058630 <6>[ 5.560064] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10888 06:00:23.068409 <6>[ 5.568403] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10889 06:00:23.075003 <6>[ 5.576742] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10890 06:00:23.085300 <6>[ 5.585081] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10891 06:00:23.091929 <6>[ 5.593839] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10892 06:00:23.098199 <6>[ 5.600989] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10893 06:00:23.104728 <6>[ 5.607746] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10894 06:00:23.111610 <6>[ 5.614510] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10895 06:00:23.118522 <6>[ 5.621433] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10896 06:00:23.127967 <6>[ 5.628276] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10897 06:00:23.137719 <6>[ 5.637402] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10898 06:00:23.147710 <6>[ 5.646521] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10899 06:00:23.157717 <6>[ 5.655815] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10900 06:00:23.167760 <6>[ 5.665285] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10901 06:00:23.174170 <6>[ 5.674753] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10902 06:00:23.184244 <6>[ 5.683874] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10903 06:00:23.194219 <6>[ 5.693343] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10904 06:00:23.204354 <6>[ 5.702467] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10905 06:00:23.214680 <6>[ 5.711770] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10906 06:00:23.224542 <6>[ 5.721935] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10907 06:00:23.234421 <6>[ 5.733253] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10908 06:00:23.262747 <6>[ 5.763241] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10909 06:00:23.291215 <6>[ 5.794403] hub 2-1:1.0: USB hub found
10910 06:00:23.294346 <6>[ 5.798856] hub 2-1:1.0: 3 ports detected
10911 06:00:23.302743 <6>[ 5.806031] hub 2-1:1.0: USB hub found
10912 06:00:23.305588 <6>[ 5.810368] hub 2-1:1.0: 3 ports detected
10913 06:00:23.414915 <6>[ 5.915020] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10914 06:00:23.569698 <6>[ 6.072947] hub 1-1:1.0: USB hub found
10915 06:00:23.572944 <6>[ 6.077437] hub 1-1:1.0: 4 ports detected
10916 06:00:23.583267 <6>[ 6.086476] hub 1-1:1.0: USB hub found
10917 06:00:23.586286 <6>[ 6.090926] hub 1-1:1.0: 4 ports detected
10918 06:00:23.655033 <6>[ 6.155238] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10919 06:00:23.907012 <6>[ 6.407028] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10920 06:00:24.040059 <6>[ 6.542993] hub 1-1.4:1.0: USB hub found
10921 06:00:24.042897 <6>[ 6.547667] hub 1-1.4:1.0: 2 ports detected
10922 06:00:24.052724 <6>[ 6.555968] hub 1-1.4:1.0: USB hub found
10923 06:00:24.056183 <6>[ 6.560561] hub 1-1.4:1.0: 2 ports detected
10924 06:00:24.355280 <6>[ 6.855008] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10925 06:00:24.547033 <6>[ 7.047006] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10926 06:00:35.523775 <6>[ 18.032009] ALSA device list:
10927 06:00:35.530351 <6>[ 18.035294] No soundcards found.
10928 06:00:35.538775 <6>[ 18.043237] Freeing unused kernel memory: 8448K
10929 06:00:35.541761 <6>[ 18.048347] Run /init as init process
10930 06:00:35.588189 <6>[ 18.092865] NET: Registered PF_INET6 protocol family
10931 06:00:35.594873 <6>[ 18.099047] Segment Routing with IPv6
10932 06:00:35.598013 <6>[ 18.102989] In-situ OAM (IOAM) with IPv6
10933 06:00:35.634444 <30>[ 18.119438] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10934 06:00:35.637998 <30>[ 18.143244] systemd[1]: Detected architecture arm64.
10935 06:00:35.638096
10936 06:00:35.644444 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10937 06:00:35.644527
10938 06:00:35.662250 <30>[ 18.166942] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10939 06:00:35.796192 <30>[ 18.297880] systemd[1]: Queued start job for default target Graphical Interface.
10940 06:00:35.835401 <30>[ 18.340002] systemd[1]: Created slice system-getty.slice.
10941 06:00:35.841529 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10942 06:00:35.858808 <30>[ 18.363635] systemd[1]: Created slice system-modprobe.slice.
10943 06:00:35.864990 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10944 06:00:35.883134 <30>[ 18.387711] systemd[1]: Created slice system-serial\x2dgetty.slice.
10945 06:00:35.892638 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10946 06:00:35.907069 <30>[ 18.411607] systemd[1]: Created slice User and Session Slice.
10947 06:00:35.913620 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10948 06:00:35.934154 <30>[ 18.435814] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10949 06:00:35.944066 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10950 06:00:35.962515 <30>[ 18.463797] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10951 06:00:35.969175 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10952 06:00:35.993512 <30>[ 18.491484] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10953 06:00:36.000325 <30>[ 18.503761] systemd[1]: Reached target Local Encrypted Volumes.
10954 06:00:36.006413 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10955 06:00:36.023033 <30>[ 18.527540] systemd[1]: Reached target Paths.
10956 06:00:36.026321 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10957 06:00:36.042333 <30>[ 18.547002] systemd[1]: Reached target Remote File Systems.
10958 06:00:36.048496 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10959 06:00:36.066633 <30>[ 18.571378] systemd[1]: Reached target Slices.
10960 06:00:36.073034 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10961 06:00:36.085845 <30>[ 18.591041] systemd[1]: Reached target Swap.
10962 06:00:36.089512 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10963 06:00:36.109866 <30>[ 18.611468] systemd[1]: Listening on initctl Compatibility Named Pipe.
10964 06:00:36.116751 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10965 06:00:36.122900 <30>[ 18.626626] systemd[1]: Listening on Journal Audit Socket.
10966 06:00:36.129845 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10967 06:00:36.142841 <30>[ 18.647489] systemd[1]: Listening on Journal Socket (/dev/log).
10968 06:00:36.149128 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10969 06:00:36.167317 <30>[ 18.672251] systemd[1]: Listening on Journal Socket.
10970 06:00:36.173935 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10971 06:00:36.186730 <30>[ 18.691573] systemd[1]: Listening on udev Control Socket.
10972 06:00:36.193213 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10973 06:00:36.210929 <30>[ 18.716041] systemd[1]: Listening on udev Kernel Socket.
10974 06:00:36.217479 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10975 06:00:36.274146 <30>[ 18.779079] systemd[1]: Mounting Huge Pages File System...
10976 06:00:36.280784 Mounting [0;1;39mHuge Pages File System[0m...
10977 06:00:36.297066 <30>[ 18.801751] systemd[1]: Mounting POSIX Message Queue File System...
10978 06:00:36.303768 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10979 06:00:36.346435 <30>[ 18.851135] systemd[1]: Mounting Kernel Debug File System...
10980 06:00:36.352757 Mounting [0;1;39mKernel Debug File System[0m...
10981 06:00:36.369949 <30>[ 18.871304] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10982 06:00:36.382334 <30>[ 18.884186] systemd[1]: Starting Create list of static device nodes for the current kernel...
10983 06:00:36.389232 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10984 06:00:36.434368 <30>[ 18.939275] systemd[1]: Starting Load Kernel Module configfs...
10985 06:00:36.440923 Starting [0;1;39mLoad Kernel Module configfs[0m...
10986 06:00:36.457864 <30>[ 18.962691] systemd[1]: Starting Load Kernel Module drm...
10987 06:00:36.464458 Starting [0;1;39mLoad Kernel Module drm[0m...
10988 06:00:36.481295 <30>[ 18.983089] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10989 06:00:36.514638 <30>[ 19.019515] systemd[1]: Starting Journal Service...
10990 06:00:36.521133 Starting [0;1;39mJournal Service[0m...
10991 06:00:36.537094 <30>[ 19.042041] systemd[1]: Starting Load Kernel Modules...
10992 06:00:36.543926 Starting [0;1;39mLoad Kernel Modules[0m...
10993 06:00:36.564191 <30>[ 19.065574] systemd[1]: Starting Remount Root and Kernel File Systems...
10994 06:00:36.570349 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10995 06:00:36.585688 <30>[ 19.090709] systemd[1]: Starting Coldplug All udev Devices...
10996 06:00:36.592294 Starting [0;1;39mColdplug All udev Devices[0m...
10997 06:00:36.608794 <30>[ 19.113887] systemd[1]: Started Journal Service.
10998 06:00:36.615380 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10999 06:00:36.632868 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11000 06:00:36.651622 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11001 06:00:36.667443 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11002 06:00:36.691715 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11003 06:00:36.712559 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11004 06:00:36.731636 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11005 06:00:36.748303 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11006 06:00:36.768293 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11007 06:00:36.782118 See 'systemctl status systemd-remount-fs.service' for details.
11008 06:00:36.843273 Mounting [0;1;39mKernel Configuration File System[0m...
11009 06:00:36.862983 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11010 06:00:36.876226 <46>[ 19.378275] systemd-journald[186]: Received client request to flush runtime journal.
11011 06:00:36.887301 Starting [0;1;39mLoad/Save Random Seed[0m...
11012 06:00:36.907242 Starting [0;1;39mApply Kernel Variables[0m...
11013 06:00:36.924885 Starting [0;1;39mCreate System Users[0m...
11014 06:00:36.940703 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11015 06:00:36.959119 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11016 06:00:36.982923 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11017 06:00:36.995896 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11018 06:00:37.012042 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11019 06:00:37.028244 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11020 06:00:37.082906 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11021 06:00:37.106264 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11022 06:00:37.122273 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11023 06:00:37.138235 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11024 06:00:37.186896 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11025 06:00:37.215074 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11026 06:00:37.240926 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11027 06:00:37.265428 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11028 06:00:37.323703 Starting [0;1;39mNetwork Time Synchronization[0m...
11029 06:00:37.344691 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11030 06:00:37.373990 <6>[ 19.876024] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11031 06:00:37.387591 [[0;32m OK [0m] Created slice [0;1;39msyste<6>[ 19.887499] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11032 06:00:37.390609 m-systemd\x2dbacklight.slice[0m.
11033 06:00:37.400933 <6>[ 19.900771] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11034 06:00:37.407432 <4>[ 19.911327] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11035 06:00:37.417425 <4>[ 19.919392] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11036 06:00:37.426214 <6>[ 19.931142] usbcore: registered new interface driver r8152
11037 06:00:37.450793 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11038 06:00:37.466505 <3>[ 19.968234] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11039 06:00:37.473241 <3>[ 19.976387] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11040 06:00:37.483360 [[0;32m OK [<3>[ 19.985231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11041 06:00:37.490340 0m] Started [0;<6>[ 19.995684] mc: Linux media interface: v0.10
11042 06:00:37.499716 1;39mNetwork Tim<3>[ 20.000702] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11043 06:00:37.509675 e Synchronizatio<3>[ 20.010159] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11044 06:00:37.509773 n[0m.
11045 06:00:37.519816 <3>[ 20.019490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11046 06:00:37.526518 <6>[ 20.021218] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11047 06:00:37.533017 <3>[ 20.028273] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11048 06:00:37.542766 <3>[ 20.028283] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11049 06:00:37.553018 <6>[ 20.036603] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11050 06:00:37.559741 <3>[ 20.040314] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11051 06:00:37.566717 <6>[ 20.041017] videodev: Linux video capture interface: v2.00
11052 06:00:37.572762 <3>[ 20.045807] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11053 06:00:37.583487 <6>[ 20.047324] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11054 06:00:37.593039 <6>[ 20.052666] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11055 06:00:37.599808 <3>[ 20.061675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11056 06:00:37.606478 <6>[ 20.067000] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11057 06:00:37.612757 <6>[ 20.067009] pci_bus 0000:00: root bus resource [bus 00-ff]
11058 06:00:37.619190 <6>[ 20.067015] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11059 06:00:37.629397 <6>[ 20.067018] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11060 06:00:37.636101 <6>[ 20.067050] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11061 06:00:37.643069 <6>[ 20.067063] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11062 06:00:37.649306 <6>[ 20.067129] pci 0000:00:00.0: supports D1 D2
11063 06:00:37.656255 <6>[ 20.067131] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11064 06:00:37.663011 <6>[ 20.068550] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11065 06:00:37.673050 <4>[ 20.070852] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11066 06:00:37.676119 <4>[ 20.070852] Fallback method does not support PEC.
11067 06:00:37.686325 <3>[ 20.075489] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11068 06:00:37.692518 <6>[ 20.112750] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11069 06:00:37.702854 <4>[ 20.121794] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11070 06:00:37.708926 <3>[ 20.123886] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11071 06:00:37.715705 <6>[ 20.125031] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11072 06:00:37.722545 <6>[ 20.125089] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11073 06:00:37.732530 <6>[ 20.125122] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11074 06:00:37.738760 <6>[ 20.125142] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11075 06:00:37.742222 <6>[ 20.125315] pci 0000:01:00.0: supports D1 D2
11076 06:00:37.748961 <6>[ 20.125323] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11077 06:00:37.758713 <6>[ 20.125604] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11078 06:00:37.762139 <6>[ 20.128645] remoteproc remoteproc0: scp is available
11079 06:00:37.768952 <6>[ 20.128698] remoteproc remoteproc0: powering up scp
11080 06:00:37.775398 <6>[ 20.128701] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11081 06:00:37.782318 <6>[ 20.128715] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11082 06:00:37.788416 <4>[ 20.130763] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11083 06:00:37.795381 <6>[ 20.135041] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11084 06:00:37.805676 <6>[ 20.135087] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11085 06:00:37.812399 <6>[ 20.135094] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11086 06:00:37.821914 <6>[ 20.135135] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11087 06:00:37.829023 <6>[ 20.135178] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11088 06:00:37.838481 <6>[ 20.135221] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11089 06:00:37.841833 <6>[ 20.135266] pci 0000:00:00.0: PCI bridge to [bus 01]
11090 06:00:37.852424 <6>[ 20.135300] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11091 06:00:37.854967 <6>[ 20.135465] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11092 06:00:37.862124 <6>[ 20.136890] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11093 06:00:37.868637 <6>[ 20.137201] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11094 06:00:37.878114 <3>[ 20.144415] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11095 06:00:37.881540 <6>[ 20.146564] Bluetooth: Core ver 2.22
11096 06:00:37.884956 <6>[ 20.146632] NET: Registered PF_BLUETOOTH protocol family
11097 06:00:37.891567 <6>[ 20.146635] Bluetooth: HCI device and connection manager initialized
11098 06:00:37.898444 <6>[ 20.146651] Bluetooth: HCI socket layer initialized
11099 06:00:37.901734 <6>[ 20.146657] Bluetooth: L2CAP socket layer initialized
11100 06:00:37.908009 <6>[ 20.146669] Bluetooth: SCO socket layer initialized
11101 06:00:37.914776 <6>[ 20.156377] usbcore: registered new interface driver cdc_ether
11102 06:00:37.921530 <3>[ 20.159114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11103 06:00:37.928237 <6>[ 20.235102] usbcore: registered new interface driver r8153_ecm
11104 06:00:37.937771 <3>[ 20.241351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11105 06:00:37.941154 <6>[ 20.248690] usbcore: registered new interface driver btusb
11106 06:00:37.951274 <4>[ 20.254115] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11107 06:00:37.960931 <6>[ 20.254212] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11108 06:00:37.968129 <6>[ 20.254518] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11109 06:00:37.974560 <6>[ 20.254529] remoteproc remoteproc0: remote processor scp is now up
11110 06:00:37.981452 <6>[ 20.254530] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11111 06:00:37.994289 <6>[ 20.257655] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11112 06:00:38.001151 <6>[ 20.257841] usbcore: registered new interface driver uvcvideo
11113 06:00:38.008011 <3>[ 20.260332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11114 06:00:38.010870 <6>[ 20.263458] r8152 2-1.3:1.0 eth0: v1.12.13
11115 06:00:38.017819 <3>[ 20.268010] Bluetooth: hci0: Failed to load firmware file (-2)
11116 06:00:38.024490 <6>[ 20.270373] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11117 06:00:38.034341 <3>[ 20.272975] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11118 06:00:38.037731 <3>[ 20.278571] Bluetooth: hci0: Failed to set up firmware (-2)
11119 06:00:38.047627 <6>[ 20.324277] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11120 06:00:38.057195 <4>[ 20.331716] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11121 06:00:38.067448 <5>[ 20.335358] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11122 06:00:38.070926 <6>[ 20.335918] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
11123 06:00:38.080251 <6>[ 20.342533] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11124 06:00:38.087181 <5>[ 20.348225] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11125 06:00:38.100158 [[0;32m OK [0m] Finished [0<4>[ 20.599950] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11126 06:00:38.103727 <6>[ 20.609231] cfg80211: failed to load regulatory.db
11127 06:00:38.110574 ;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11128 06:00:38.131951 <3>[ 20.633438] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11129 06:00:38.138619 <3>[ 20.634276] power_supply sbs-5-000b: driver failed to report `health' property: -6
11130 06:00:38.152025 [[0;32m OK [0m] Found device [0;1;39m/dev/t<3>[ 20.654302] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11131 06:00:38.162576 <6>[ 20.657390] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11132 06:00:38.162665 tyS0[0m.
11133 06:00:38.168706 <6>[ 20.671073] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11134 06:00:38.189778 <6>[ 20.694772] mt7921e 0000:01:00.0: ASIC revision: 79610010
11135 06:00:38.215099 [[0;32m OK [0m] Finished [0;1;39mUpdate UTM<3>[ 20.716137] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11136 06:00:38.224638 P about System B<3>[ 20.716901] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
11137 06:00:38.228019 oot/Shutdown[0m.
11138 06:00:38.254386 <3>[ 20.755997] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11139 06:00:38.285288 <3>[ 20.786830] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11140 06:00:38.296654 <6>[ 20.798435] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11141 06:00:38.299561 <6>[ 20.798435]
11142 06:00:38.318514 <3>[ 20.820533] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11143 06:00:38.348230 <3>[ 20.850265] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11144 06:00:38.380085 <3>[ 20.881632] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11145 06:00:38.386366 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11146 06:00:38.401818 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11147 06:00:38.421548 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11148 06:00:38.434423 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11149 06:00:38.449813 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11150 06:00:38.470083 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11151 06:00:38.482403 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11152 06:00:38.501699 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11153 06:00:38.513933 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11154 06:00:38.530304 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11155 06:00:38.549789 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11156 06:00:38.566414 <6>[ 21.068086] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11157 06:00:38.619012 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11158 06:00:38.651023 Starting [0;1;39mUser Login Management[0m...
11159 06:00:38.671040 Starting [0;1;39mPermit User Sessions[0m...
11160 06:00:38.690111 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11161 06:00:38.715458 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11162 06:00:38.735450 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11163 06:00:38.751398 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11164 06:00:38.770575 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11165 06:00:38.787601 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11166 06:00:38.802732 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11167 06:00:38.823498 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11168 06:00:38.839709 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11169 06:00:38.900140 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11170 06:00:38.934741 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11171 06:00:38.968135
11172 06:00:38.968336
11173 06:00:38.971536 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11174 06:00:38.971642
11175 06:00:38.974887 debian-bullseye-arm64 login: root (automatic login)
11176 06:00:38.974969
11177 06:00:38.975033
11178 06:00:38.991508 Linux debian-bullseye-arm64 6.1.67-cip12 #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023 aarch64
11179 06:00:38.991610
11180 06:00:38.997845 The programs included with the Debian GNU/Linux system are free software;
11181 06:00:39.004032 the exact distribution terms for each program are described in the
11182 06:00:39.007455 individual files in /usr/share/doc/*/copyright.
11183 06:00:39.007540
11184 06:00:39.014078 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11185 06:00:39.017405 permitted by applicable law.
11186 06:00:39.017809 Matched prompt #10: / #
11188 06:00:39.018015 Setting prompt string to ['/ #']
11189 06:00:39.018107 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11191 06:00:39.018300 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11192 06:00:39.018388 start: 2.2.6 expect-shell-connection (timeout 00:03:00) [common]
11193 06:00:39.018458 Setting prompt string to ['/ #']
11194 06:00:39.018520 Forcing a shell prompt, looking for ['/ #']
11196 06:00:39.068738 / #
11197 06:00:39.068891 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11198 06:00:39.068973 Waiting using forced prompt support (timeout 00:02:30)
11199 06:00:39.074480
11200 06:00:39.074766 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11201 06:00:39.074861 start: 2.2.7 export-device-env (timeout 00:03:00) [common]
11202 06:00:39.074956 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11203 06:00:39.075045 end: 2.2 depthcharge-retry (duration 00:02:00) [common]
11204 06:00:39.075131 end: 2 depthcharge-action (duration 00:02:00) [common]
11205 06:00:39.075218 start: 3 lava-test-retry (timeout 00:05:00) [common]
11206 06:00:39.075301 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11207 06:00:39.075377 Using namespace: common
11209 06:00:39.175701 / # #
11210 06:00:39.175861 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11211 06:00:39.181415 #
11212 06:00:39.181693 Using /lava-12379448
11214 06:00:39.282020 / # export SHELL=/bin/sh
11215 06:00:39.287881 export SHELL=/bin/sh
11217 06:00:39.388415 / # . /lava-12379448/environment
11218 06:00:39.394106 . /lava-12379448/environment
11220 06:00:39.494644 / # /lava-12379448/bin/lava-test-runner /lava-12379448/0
11221 06:00:39.494806 Test shell timeout: 10s (minimum of the action and connection timeout)
11222 06:00:39.495130 <6>[ 21.922991] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11223 06:00:39.499831 /lava-12379448/bin/lava-test-runner /lava-12379448/0
11224 06:00:39.540486 + export TESTRUN_ID=0_sleep
11225 06:00:39.540631 + cd /lava-12379448/0/tests/0_sleep
11226 06:00:39.540727 + cat uuid
11227 06:00:39.540808 + UUID=12379448_1.5.2.3.1
11228 06:00:39.540887 + set +x
11229 06:00:39.540964 <LAVA_SIGNAL_STARTRUN 0_sleep 12379448_1.5.2.3.1>
11230 06:00:39.541042 + ./config/lava/sleep/sleep.sh mem
11231 06:00:39.541324 Received signal: <STARTRUN> 0_sleep 12379448_1.5.2.3.1
11232 06:00:39.541426 Starting test lava.0_sleep (12379448_1.5.2.3.1)
11233 06:00:39.541549 Skipping test definition patterns.
11234 06:00:39.541699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11235 06:00:39.541971 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11237 06:00:39.548271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11238 06:00:39.548553 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11240 06:00:39.551280 rtcwake: assuming RTC uses UTC ...
11241 06:00:39.561495 rtcwake: wakeup from "mem" using rtc0 at Mon Dec 25 0<6>[ 22.065225] PM: suspend entry (deep)
11242 06:00:39.561625 5:58:10 2023
11243 06:00:39.564241 <6>[ 22.070297] Filesystems sync: 0.000 seconds
11244 06:00:39.573059 <6>[ 22.078250] Freezing user space processes
11245 06:00:39.579344 <6>[ 22.084228] Freezing user space processes completed (elapsed 0.001 seconds)
11246 06:00:39.586127 <6>[ 22.091465] OOM killer disabled.
11247 06:00:39.589536 <6>[ 22.094948] Freezing remaining freezable tasks
11248 06:00:39.599223 <6>[ 22.101017] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11249 06:00:39.605826 <6>[ 22.108721] printk: Suspending console(s) (use no_console_suspend to debug)
11250 06:00:45.265160 <6>[ 22.267227] Disabling non-boot CPUs ...
11251 06:00:45.268434 <4>[ 22.268075] IRQ282: set affinity failed(-22).
11252 06:00:45.274916 <4>[ 22.268090] IRQ284: set affinity failed(-22).
11253 06:00:45.278549 <6>[ 22.268155] psci: CPU1 killed (polled 0 ms)
11254 06:00:45.281991 <4>[ 22.269230] IRQ282: set affinity failed(-22).
11255 06:00:45.288304 <4>[ 22.269240] IRQ284: set affinity failed(-22).
11256 06:00:45.291689 <6>[ 22.269287] psci: CPU2 killed (polled 0 ms)
11257 06:00:45.295121 <4>[ 22.270239] IRQ282: set affinity failed(-22).
11258 06:00:45.301942 <4>[ 22.270249] IRQ284: set affinity failed(-22).
11259 06:00:45.305416 <6>[ 22.270294] psci: CPU3 killed (polled 0 ms)
11260 06:00:45.308064 <4>[ 22.271016] IRQ282: set affinity failed(-22).
11261 06:00:45.314925 <4>[ 22.271020] IRQ284: set affinity failed(-22).
11262 06:00:45.318377 <6>[ 22.271043] psci: CPU4 killed (polled 0 ms)
11263 06:00:45.325009 <4>[ 22.271858] IRQ282: set affinity failed(-22).
11264 06:00:45.328249 <4>[ 22.271864] IRQ284: set affinity failed(-22).
11265 06:00:45.331722 <6>[ 22.271907] psci: CPU5 killed (polled 0 ms)
11266 06:00:45.338039 <6>[ 22.272692] psci: CPU6 killed (polled 0 ms)
11267 06:00:45.341515 <6>[ 22.273498] psci: CPU7 killed (polled 0 ms)
11268 06:00:45.344816 <6>[ 22.273967] Enabling non-boot CPUs ...
11269 06:00:45.348206 <6>[ 22.274181] Detected VIPT I-cache on CPU1
11270 06:00:45.357821 <6>[ 22.274260] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11271 06:00:45.364940 <6>[ 22.274316] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11272 06:00:45.368229 <6>[ 22.274862] CPU1 is up
11273 06:00:45.371404 <6>[ 22.274991] Detected VIPT I-cache on CPU2
11274 06:00:45.378098 <6>[ 22.275041] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11275 06:00:45.384422 <6>[ 22.275074] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11276 06:00:45.387990 <6>[ 22.275496] CPU2 is up
11277 06:00:45.390913 <6>[ 22.275621] Detected VIPT I-cache on CPU3
11278 06:00:45.397713 <6>[ 22.275671] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11279 06:00:45.404202 <6>[ 22.275705] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11280 06:00:45.407807 <6>[ 22.276153] CPU3 is up
11281 06:00:45.414470 <6>[ 22.276257] CPU features: detected: Hardware dirty bit management
11282 06:00:45.417724 <6>[ 22.276273] Detected PIPT I-cache on CPU4
11283 06:00:45.428063 <6>[ 22.276293] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11284 06:00:45.434571 <6>[ 22.276307] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11285 06:00:45.434655 <6>[ 22.276559] CPU4 is up
11286 06:00:45.441454 <6>[ 22.276676] Detected PIPT I-cache on CPU5
11287 06:00:45.447755 <6>[ 22.276698] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11288 06:00:45.454810 <6>[ 22.276712] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11289 06:00:45.458203 <6>[ 22.276956] CPU5 is up
11290 06:00:45.461048 <6>[ 22.277071] Detected PIPT I-cache on CPU6
11291 06:00:45.467812 <6>[ 22.277093] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11292 06:00:45.474622 <6>[ 22.277107] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11293 06:00:45.478016 <6>[ 22.277345] CPU6 is up
11294 06:00:45.481255 <6>[ 22.277461] Detected PIPT I-cache on CPU7
11295 06:00:45.487945 <6>[ 22.277483] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11296 06:00:45.494920 <6>[ 22.277497] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11297 06:00:45.497632 <6>[ 22.277741] CPU7 is up
11298 06:00:45.504460 <4>[ 22.419128] typec port0-partner: PM: parent port0 should not be sleeping
11299 06:00:45.507699 <6>[ 22.874045] OOM killer enabled.
11300 06:00:45.514778 <6>[ 22.877437] Restarting tasks ... done.
11301 06:00:45.517788 <5>[ 22.881809] random: crng reseeded on system resumption
11302 06:00:45.521416 <6>[ 22.888319] PM: suspend exit
11303 06:00:45.530950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=pass>
11304 06:00:45.531234 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=pass
11306 06:00:45.534504 rtcwake: assuming RTC uses UTC ...
11307 06:00:45.541231 rtcwake: wakeup from "mem" using rtc0 at Mon Dec 25 05:58:16 2023
11308 06:00:45.552994 <6>[ 22.916701] PM: suspend entry (deep)
11309 06:00:45.556415 <6>[ 22.920566] Filesystems sync: 0.000 seconds
11310 06:00:45.559744 <6>[ 22.925304] Freezing user space processes
11311 06:00:45.570696 <6>[ 22.930760] Freezing user space processes completed (elapsed 0.001 seconds)
11312 06:00:45.574105 <6>[ 22.937977] OOM killer disabled.
11313 06:00:45.577411 <6>[ 22.941456] Freezing remaining freezable tasks
11314 06:00:45.586980 <6>[ 22.947300] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11315 06:00:45.593344 <6>[ 22.954952] printk: Suspending console(s) (use no_console_suspend to debug)
11316 06:00:51.269418 <6>[ 23.039194] Disabling non-boot CPUs ...
11317 06:00:51.272899 <6>[ 23.040107] psci: CPU1 killed (polled 0 ms)
11318 06:00:51.276434 <6>[ 23.041183] psci: CPU2 killed (polled 0 ms)
11319 06:00:51.283071 <6>[ 23.042012] psci: CPU3 killed (polled 0 ms)
11320 06:00:51.286610 <6>[ 23.042570] psci: CPU4 killed (polled 0 ms)
11321 06:00:51.289914 <6>[ 23.043227] psci: CPU5 killed (polled 0 ms)
11322 06:00:51.296454 <6>[ 23.043779] psci: CPU6 killed (polled 0 ms)
11323 06:00:51.299476 <6>[ 23.044417] psci: CPU7 killed (polled 0 ms)
11324 06:00:51.303047 <6>[ 23.044724] Enabling non-boot CPUs ...
11325 06:00:51.309415 <6>[ 23.044939] Detected VIPT I-cache on CPU1
11326 06:00:51.316411 <6>[ 23.045019] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11327 06:00:51.322849 <6>[ 23.045075] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11328 06:00:51.326461 <6>[ 23.045677] CPU1 is up
11329 06:00:51.329373 <6>[ 23.045809] Detected VIPT I-cache on CPU2
11330 06:00:51.336197 <6>[ 23.045860] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11331 06:00:51.342849 <6>[ 23.045893] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11332 06:00:51.346601 <6>[ 23.046360] CPU2 is up
11333 06:00:51.349999 <6>[ 23.046484] Detected VIPT I-cache on CPU3
11334 06:00:51.356410 <6>[ 23.046535] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11335 06:00:51.363229 <6>[ 23.046568] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11336 06:00:51.366675 <6>[ 23.047062] CPU3 is up
11337 06:00:51.369512 <6>[ 23.047185] Detected PIPT I-cache on CPU4
11338 06:00:51.379947 <6>[ 23.047208] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11339 06:00:51.386715 <6>[ 23.047223] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11340 06:00:51.386862 <6>[ 23.047496] CPU4 is up
11341 06:00:51.393432 <6>[ 23.047613] Detected PIPT I-cache on CPU5
11342 06:00:51.400257 <6>[ 23.047636] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11343 06:00:51.406555 <6>[ 23.047651] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11344 06:00:51.409984 <6>[ 23.047912] CPU5 is up
11345 06:00:51.413395 <6>[ 23.048029] Detected PIPT I-cache on CPU6
11346 06:00:51.419777 <6>[ 23.048053] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11347 06:00:51.426531 <6>[ 23.048067] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11348 06:00:51.429671 <6>[ 23.048327] CPU6 is up
11349 06:00:51.433428 <6>[ 23.048449] Detected PIPT I-cache on CPU7
11350 06:00:51.439994 <6>[ 23.048473] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11351 06:00:51.446342 <6>[ 23.048488] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11352 06:00:51.450168 <6>[ 23.048755] CPU7 is up
11353 06:00:51.453520 <6>[ 23.590941] OOM killer enabled.
11354 06:00:51.460104 <6>[ 23.594331] Restarting tasks ... done.
11355 06:00:51.462971 <5>[ 23.598721] random: crng reseeded on system resumption
11356 06:00:51.466566 <6>[ 23.605098] PM: suspend exit
11357 06:00:51.477359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=pass>
11358 06:00:51.477687 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=pass
11360 06:00:51.480848 rtcwake: assuming RTC uses UTC ...
11361 06:00:51.486958 rtcwake: wakeup from "mem" using rtc0 at Mon Dec 25 05:58:22 2023
11362 06:00:51.499805 <6>[ 23.634821] PM: suspend entry (deep)
11363 06:00:51.503231 <6>[ 23.638690] Filesystems sync: 0.000 seconds
11364 06:00:51.506031 <6>[ 23.643461] Freezing user space processes
11365 06:00:51.516982 <6>[ 23.649173] Freezing user space processes completed (elapsed 0.001 seconds)
11366 06:00:51.520438 <6>[ 23.656404] OOM killer disabled.
11367 06:00:51.523901 <6>[ 23.659884] Freezing remaining freezable tasks
11368 06:00:51.533797 <6>[ 23.665820] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11369 06:00:51.540713 <6>[ 23.673486] printk: Suspending console(s) (use no_console_suspend to debug)
11370 06:00:57.266129 <6>[ 23.745554] Disabling non-boot CPUs ...
11371 06:00:57.269481 <6>[ 23.746527] psci: CPU1 killed (polled 0 ms)
11372 06:00:57.273263 <6>[ 23.747621] psci: CPU2 killed (polled 0 ms)
11373 06:00:57.279936 <6>[ 23.748610] psci: CPU3 killed (polled 0 ms)
11374 06:00:57.283378 <6>[ 23.749140] psci: CPU4 killed (polled 0 ms)
11375 06:00:57.286054 <6>[ 23.749828] psci: CPU5 killed (polled 0 ms)
11376 06:00:57.292746 <6>[ 23.750376] psci: CPU6 killed (polled 0 ms)
11377 06:00:57.296011 <6>[ 23.751032] psci: CPU7 killed (polled 0 ms)
11378 06:00:57.299516 <6>[ 23.751406] Enabling non-boot CPUs ...
11379 06:00:57.306286 <6>[ 23.751631] Detected VIPT I-cache on CPU1
11380 06:00:57.312723 <6>[ 23.751716] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11381 06:00:57.319421 <6>[ 23.751777] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11382 06:00:57.322860 <6>[ 23.752414] CPU1 is up
11383 06:00:57.326276 <6>[ 23.752551] Detected VIPT I-cache on CPU2
11384 06:00:57.333092 <6>[ 23.752606] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11385 06:00:57.339549 <6>[ 23.752643] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11386 06:00:57.343027 <6>[ 23.753162] CPU2 is up
11387 06:00:57.346068 <6>[ 23.753297] Detected VIPT I-cache on CPU3
11388 06:00:57.353027 <6>[ 23.753352] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11389 06:00:57.359608 <6>[ 23.753390] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11390 06:00:57.363323 <6>[ 23.753914] CPU3 is up
11391 06:00:57.366637 <6>[ 23.754038] Detected PIPT I-cache on CPU4
11392 06:00:57.376164 <6>[ 23.754061] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11393 06:00:57.383289 <6>[ 23.754075] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11394 06:00:57.383436 <6>[ 23.754335] CPU4 is up
11395 06:00:57.389538 <6>[ 23.754456] Detected PIPT I-cache on CPU5
11396 06:00:57.396095 <6>[ 23.754478] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11397 06:00:57.402761 <6>[ 23.754492] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11398 06:00:57.406369 <6>[ 23.754761] CPU5 is up
11399 06:00:57.409917 <6>[ 23.754885] Detected PIPT I-cache on CPU6
11400 06:00:57.415923 <6>[ 23.754907] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11401 06:00:57.423251 <6>[ 23.754921] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11402 06:00:57.426461 <6>[ 23.755162] CPU6 is up
11403 06:00:57.429371 <6>[ 23.755283] Detected PIPT I-cache on CPU7
11404 06:00:57.439503 <6>[ 23.755305] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11405 06:00:57.445886 <6>[ 23.755319] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11406 06:00:57.446008 <6>[ 23.755575] CPU7 is up
11407 06:00:57.449442 <6>[ 24.294958] OOM killer enabled.
11408 06:00:57.455869 <6>[ 24.298348] Restarting tasks ... done.
11409 06:00:57.459132 <5>[ 24.302745] random: crng reseeded on system resumption
11410 06:00:57.462921 <6>[ 24.308821] PM: suspend exit
11411 06:00:57.473205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=pass>
11412 06:00:57.473615 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=pass
11414 06:00:57.476572 rtcwake: assuming RTC uses UTC ...
11415 06:00:57.483059 rtcwake: wakeup from "mem" using rtc0 at Mon Dec 25 05:58:28 2023
11416 06:00:57.495776 <6>[ 24.338145] PM: suspend entry (deep)
11417 06:00:57.498708 <6>[ 24.342016] Filesystems sync: 0.000 seconds
11418 06:00:57.502226 <6>[ 24.346797] Freezing user space processes
11419 06:00:57.513189 <6>[ 24.352482] Freezing user space processes completed (elapsed 0.001 seconds)
11420 06:00:57.516437 <6>[ 24.359712] OOM killer disabled.
11421 06:00:57.519991 <6>[ 24.363198] Freezing remaining freezable tasks
11422 06:00:57.529903 <6>[ 24.369104] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11423 06:00:57.536554 <6>[ 24.376766] printk: Suspending console(s) (use no_console_suspend to debug)
11424 06:01:03.268253 <6>[ 24.450512] Disabling non-boot CPUs ...
11425 06:01:03.272146 <6>[ 24.451520] psci: CPU1 killed (polled 0 ms)
11426 06:01:03.275026 <6>[ 24.452580] psci: CPU2 killed (polled 0 ms)
11427 06:01:03.282207 <6>[ 24.453601] psci: CPU3 killed (polled 0 ms)
11428 06:01:03.285264 <6>[ 24.454133] psci: CPU4 killed (polled 0 ms)
11429 06:01:03.288480 <6>[ 24.454781] psci: CPU5 killed (polled 0 ms)
11430 06:01:03.295370 <6>[ 24.455460] psci: CPU6 killed (polled 0 ms)
11431 06:01:03.298659 <6>[ 24.456050] psci: CPU7 killed (polled 0 ms)
11432 06:01:03.301837 <6>[ 24.456374] Enabling non-boot CPUs ...
11433 06:01:03.308579 <6>[ 24.456601] Detected VIPT I-cache on CPU1
11434 06:01:03.315254 <6>[ 24.456686] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11435 06:01:03.322056 <6>[ 24.456746] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11436 06:01:03.324901 <6>[ 24.457380] CPU1 is up
11437 06:01:03.328739 <6>[ 24.457517] Detected VIPT I-cache on CPU2
11438 06:01:03.335445 <6>[ 24.457572] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11439 06:01:03.341750 <6>[ 24.457609] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11440 06:01:03.345014 <6>[ 24.458122] CPU2 is up
11441 06:01:03.348776 <6>[ 24.458258] Detected VIPT I-cache on CPU3
11442 06:01:03.355054 <6>[ 24.458313] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11443 06:01:03.361504 <6>[ 24.458350] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11444 06:01:03.364959 <6>[ 24.458910] CPU3 is up
11445 06:01:03.368066 <6>[ 24.459036] Detected PIPT I-cache on CPU4
11446 06:01:03.378123 <6>[ 24.459058] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11447 06:01:03.385044 <6>[ 24.459072] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11448 06:01:03.385128 <6>[ 24.459335] CPU4 is up
11449 06:01:03.391725 <6>[ 24.459458] Detected PIPT I-cache on CPU5
11450 06:01:03.398518 <6>[ 24.459480] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11451 06:01:03.404977 <6>[ 24.459494] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11452 06:01:03.408174 <6>[ 24.459747] CPU5 is up
11453 06:01:03.411395 <6>[ 24.459869] Detected PIPT I-cache on CPU6
11454 06:01:03.417892 <6>[ 24.459891] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11455 06:01:03.424887 <6>[ 24.459905] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11456 06:01:03.428187 <6>[ 24.460154] CPU6 is up
11457 06:01:03.431566 <6>[ 24.460274] Detected PIPT I-cache on CPU7
11458 06:01:03.441421 <6>[ 24.460303] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11459 06:01:03.448519 <6>[ 24.460317] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11460 06:01:03.448653 <6>[ 24.460574] CPU7 is up
11461 06:01:03.451287 <6>[ 25.002886] OOM killer enabled.
11462 06:01:03.458050 <6>[ 25.006276] Restarting tasks ... done.
11463 06:01:03.461301 <5>[ 25.010642] random: crng reseeded on system resumption
11464 06:01:03.465164 <6>[ 25.017178] PM: suspend exit
11465 06:01:03.475489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=pass>
11466 06:01:03.475757 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=pass
11468 06:01:03.479107 rtcwake: assuming RTC uses UTC ...
11469 06:01:03.485517 rtcwake: wakeup from "mem" using rtc0 at Mon Dec 25 05:58:34 2023
11470 06:01:03.497707 <6>[ 25.046020] PM: suspend entry (deep)
11471 06:01:03.501049 <6>[ 25.049933] Filesystems sync: 0.000 seconds
11472 06:01:03.504181 <6>[ 25.054672] Freezing user space processes
11473 06:01:03.515252 <6>[ 25.060355] Freezing user space processes completed (elapsed 0.001 seconds)
11474 06:01:03.518478 <6>[ 25.067604] OOM killer disabled.
11475 06:01:03.521752 <6>[ 25.071086] Freezing remaining freezable tasks
11476 06:01:03.532076 <6>[ 25.077044] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11477 06:01:03.538795 <6>[ 25.084707] printk: Suspending console(s) (use no_console_suspend to debug)
11478 06:01:09.271457 <6>[ 25.162954] Disabling non-boot CPUs ...
11479 06:01:09.274421 <6>[ 25.163867] psci: CPU1 killed (polled 0 ms)
11480 06:01:09.277937 <6>[ 25.164906] psci: CPU2 killed (polled 0 ms)
11481 06:01:09.284733 <6>[ 25.165887] psci: CPU3 killed (polled 0 ms)
11482 06:01:09.287659 <6>[ 25.166524] psci: CPU4 killed (polled 0 ms)
11483 06:01:09.291395 <6>[ 25.167241] psci: CPU5 killed (polled 0 ms)
11484 06:01:09.298087 <6>[ 25.167899] psci: CPU6 killed (polled 0 ms)
11485 06:01:09.301291 <6>[ 25.168435] psci: CPU7 killed (polled 0 ms)
11486 06:01:09.304420 <6>[ 25.168835] Enabling non-boot CPUs ...
11487 06:01:09.311177 <6>[ 25.169064] Detected VIPT I-cache on CPU1
11488 06:01:09.318086 <6>[ 25.169148] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11489 06:01:09.324779 <6>[ 25.169208] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11490 06:01:09.328170 <6>[ 25.169848] CPU1 is up
11491 06:01:09.331643 <6>[ 25.169985] Detected VIPT I-cache on CPU2
11492 06:01:09.338255 <6>[ 25.170040] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11493 06:01:09.344475 <6>[ 25.170077] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11494 06:01:09.347903 <6>[ 25.170624] CPU2 is up
11495 06:01:09.351495 <6>[ 25.170761] Detected VIPT I-cache on CPU3
11496 06:01:09.358431 <6>[ 25.170816] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11497 06:01:09.364455 <6>[ 25.170853] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11498 06:01:09.367950 <6>[ 25.171368] CPU3 is up
11499 06:01:09.371285 <6>[ 25.171493] Detected PIPT I-cache on CPU4
11500 06:01:09.381214 <6>[ 25.171515] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11501 06:01:09.388144 <6>[ 25.171529] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11502 06:01:09.388269 <6>[ 25.171791] CPU4 is up
11503 06:01:09.394567 <6>[ 25.171911] Detected PIPT I-cache on CPU5
11504 06:01:09.400868 <6>[ 25.171934] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11505 06:01:09.407900 <6>[ 25.171948] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11506 06:01:09.410822 <6>[ 25.172200] CPU5 is up
11507 06:01:09.414224 <6>[ 25.172328] Detected PIPT I-cache on CPU6
11508 06:01:09.420996 <6>[ 25.172351] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11509 06:01:09.427717 <6>[ 25.172365] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11510 06:01:09.431150 <6>[ 25.172624] CPU6 is up
11511 06:01:09.434350 <6>[ 25.172758] Detected PIPT I-cache on CPU7
11512 06:01:09.441488 <6>[ 25.172786] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11513 06:01:09.448083 <6>[ 25.172801] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11514 06:01:09.451034 <6>[ 25.173056] CPU7 is up
11515 06:01:09.454431 <6>[ 25.718849] OOM killer enabled.
11516 06:01:09.461464 <6>[ 25.722239] Restarting tasks ... done.
11517 06:01:09.464865 <5>[ 25.726631] random: crng reseeded on system resumption
11518 06:01:09.467678 <6>[ 25.733092] PM: suspend exit
11519 06:01:09.477955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=pass>
11520 06:01:09.478266 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=pass
11522 06:01:09.481383 rtcwake: assuming RTC uses UTC ...
11523 06:01:09.487674 rtcwake: wakeup from "mem" using rtc0 at Mon Dec 25 05:58:40 2023
11524 06:01:09.500456 <6>[ 25.761921] PM: suspend entry (deep)
11525 06:01:09.503274 <6>[ 25.765787] Filesystems sync: 0.000 seconds
11526 06:01:09.506612 <6>[ 25.770545] Freezing user space processes
11527 06:01:09.518333 <6>[ 25.776232] Freezing user space processes completed (elapsed 0.001 seconds)
11528 06:01:09.520990 <6>[ 25.783465] OOM killer disabled.
11529 06:01:09.524935 <6>[ 25.786948] Freezing remaining freezable tasks
11530 06:01:09.534453 <6>[ 25.792913] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11531 06:01:09.540991 <6>[ 25.800579] printk: Suspending console(s) (use no_console_suspend to debug)
11532 06:01:15.269882 <6>[ 25.874075] Disabling non-boot CPUs ...
11533 06:01:15.273033 <6>[ 25.874929] psci: CPU1 killed (polled 0 ms)
11534 06:01:15.276410 <6>[ 25.875793] psci: CPU2 killed (polled 0 ms)
11535 06:01:15.283444 <6>[ 25.876609] psci: CPU3 killed (polled 0 ms)
11536 06:01:15.286278 <6>[ 25.877083] psci: CPU4 killed (polled 0 ms)
11537 06:01:15.289674 <6>[ 25.878531] psci: CPU5 killed (polled 4 ms)
11538 06:01:15.296468 <6>[ 25.879142] psci: CPU6 killed (polled 0 ms)
11539 06:01:15.300467 <6>[ 25.880658] psci: CPU7 killed (polled 0 ms)
11540 06:01:15.303075 <6>[ 25.881010] Enabling non-boot CPUs ...
11541 06:01:15.306523 <6>[ 25.881215] Detected VIPT I-cache on CPU1
11542 06:01:15.316975 <6>[ 25.881290] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11543 06:01:15.323136 <6>[ 25.881343] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11544 06:01:15.323293 <6>[ 25.881896] CPU1 is up
11545 06:01:15.329970 <6>[ 25.882014] Detected VIPT I-cache on CPU2
11546 06:01:15.336954 <6>[ 25.882060] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11547 06:01:15.343114 <6>[ 25.882091] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11548 06:01:15.346362 <6>[ 25.882531] CPU2 is up
11549 06:01:15.350316 <6>[ 25.882649] Detected VIPT I-cache on CPU3
11550 06:01:15.356817 <6>[ 25.882695] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11551 06:01:15.363264 <6>[ 25.882726] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11552 06:01:15.366470 <6>[ 25.883156] CPU3 is up
11553 06:01:15.369775 <6>[ 25.883271] Detected PIPT I-cache on CPU4
11554 06:01:15.380046 <6>[ 25.883293] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11555 06:01:15.386614 <6>[ 25.883307] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11556 06:01:15.386769 <6>[ 25.883565] CPU4 is up
11557 06:01:15.393375 <6>[ 25.883675] Detected PIPT I-cache on CPU5
11558 06:01:15.400277 <6>[ 25.883698] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11559 06:01:15.406614 <6>[ 25.883711] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11560 06:01:15.409838 <6>[ 25.883955] CPU5 is up
11561 06:01:15.412770 <6>[ 25.884067] Detected PIPT I-cache on CPU6
11562 06:01:15.419408 <6>[ 25.884089] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11563 06:01:15.426172 <6>[ 25.884103] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11564 06:01:15.429766 <6>[ 25.884344] CPU6 is up
11565 06:01:15.433141 <6>[ 25.884459] Detected PIPT I-cache on CPU7
11566 06:01:15.439357 <6>[ 25.884488] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11567 06:01:15.446275 <6>[ 25.884501] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11568 06:01:15.449771 <6>[ 25.884767] CPU7 is up
11569 06:01:15.453180 <6>[ 26.430526] OOM killer enabled.
11570 06:01:15.460007 <6>[ 26.433915] Restarting tasks ... done.
11571 06:01:15.463130 <5>[ 26.438301] random: crng reseeded on system resumption
11572 06:01:15.466627 <6>[ 26.444766] PM: suspend exit
11573 06:01:15.476115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=pass>
11574 06:01:15.476493 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=pass
11576 06:01:15.479283 rtcwake: assuming RTC uses UTC ...
11577 06:01:15.485920 rtcwake: wakeup from "mem" using rtc0 at Mon Dec 25 05:58:46 2023
11578 06:01:15.498524 <6>[ 26.473314] PM: suspend entry (deep)
11579 06:01:15.501857 <6>[ 26.477200] Filesystems sync: 0.000 seconds
11580 06:01:15.505324 <6>[ 26.482197] Freezing user space processes
11581 06:01:15.516719 <6>[ 26.488222] Freezing user space processes completed (elapsed 0.001 seconds)
11582 06:01:15.519631 <6>[ 26.495530] OOM killer disabled.
11583 06:01:15.523267 <6>[ 26.499020] Freezing remaining freezable tasks
11584 06:01:15.533602 <6>[ 26.505173] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11585 06:01:15.540116 <6>[ 26.512863] printk: Suspending console(s) (use no_console_suspend to debug)
11586 06:01:21.267244 <6>[ 26.586240] Disabling non-boot CPUs ...
11587 06:01:21.270532 <6>[ 26.586848] psci: CPU1 killed (polled 0 ms)
11588 06:01:21.273749 <6>[ 26.587484] psci: CPU2 killed (polled 0 ms)
11589 06:01:21.280197 <6>[ 26.588097] psci: CPU3 killed (polled 0 ms)
11590 06:01:21.283593 <6>[ 26.588606] psci: CPU4 killed (polled 0 ms)
11591 06:01:21.286895 <6>[ 26.589244] psci: CPU5 killed (polled 0 ms)
11592 06:01:21.293593 <6>[ 26.589833] psci: CPU6 killed (polled 0 ms)
11593 06:01:21.297444 <6>[ 26.590401] psci: CPU7 killed (polled 0 ms)
11594 06:01:21.300398 <6>[ 26.590683] Enabling non-boot CPUs ...
11595 06:01:21.307039 <6>[ 26.590858] Detected VIPT I-cache on CPU1
11596 06:01:21.313596 <6>[ 26.590919] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11597 06:01:21.320184 <6>[ 26.590963] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11598 06:01:21.323505 <6>[ 26.591382] CPU1 is up
11599 06:01:21.326876 <6>[ 26.591471] Detected VIPT I-cache on CPU2
11600 06:01:21.333375 <6>[ 26.591502] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11601 06:01:21.340056 <6>[ 26.591523] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11602 06:01:21.343442 <6>[ 26.591806] CPU2 is up
11603 06:01:21.346848 <6>[ 26.591894] Detected VIPT I-cache on CPU3
11604 06:01:21.353525 <6>[ 26.591925] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11605 06:01:21.360827 <6>[ 26.591946] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11606 06:01:21.363916 <6>[ 26.592233] CPU3 is up
11607 06:01:21.367017 <6>[ 26.592354] Detected PIPT I-cache on CPU4
11608 06:01:21.377168 <6>[ 26.592389] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11609 06:01:21.383835 <6>[ 26.592411] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11610 06:01:21.383982 <6>[ 26.592780] CPU4 is up
11611 06:01:21.390452 <6>[ 26.592916] Detected PIPT I-cache on CPU5
11612 06:01:21.397240 <6>[ 26.592954] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11613 06:01:21.403946 <6>[ 26.592976] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11614 06:01:21.406980 <6>[ 26.593326] CPU5 is up
11615 06:01:21.410309 <6>[ 26.593444] Detected PIPT I-cache on CPU6
11616 06:01:21.416727 <6>[ 26.593481] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11617 06:01:21.423236 <6>[ 26.593504] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11618 06:01:21.426545 <6>[ 26.593866] CPU6 is up
11619 06:01:21.429902 <6>[ 26.593983] Detected PIPT I-cache on CPU7
11620 06:01:21.440585 <6>[ 26.594028] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11621 06:01:21.447191 <6>[ 26.594050] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11622 06:01:21.447324 <6>[ 26.594448] CPU7 is up
11623 06:01:21.449945 <6>[ 27.138313] OOM killer enabled.
11624 06:01:21.456721 <6>[ 27.141705] Restarting tasks ... done.
11625 06:01:21.460153 <5>[ 27.146103] random: crng reseeded on system resumption
11626 06:01:21.463526 <6>[ 27.152598] PM: suspend exit
11627 06:01:21.474197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=pass>
11628 06:01:21.474519 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=pass
11630 06:01:21.477417 rtcwake: assuming RTC uses UTC ...
11631 06:01:21.483878 rtcwake: wakeup from "mem" using rtc0 at Mon Dec 25 05:58:52 2023
11632 06:01:21.496321 <6>[ 27.181713] PM: suspend entry (deep)
11633 06:01:21.499773 <6>[ 27.185575] Filesystems sync: 0.000 seconds
11634 06:01:21.502818 <6>[ 27.190307] Freezing user space processes
11635 06:01:21.514103 <6>[ 27.196021] Freezing user space processes completed (elapsed 0.001 seconds)
11636 06:01:21.517190 <6>[ 27.203258] OOM killer disabled.
11637 06:01:21.520935 <6>[ 27.206741] Freezing remaining freezable tasks
11638 06:01:21.530775 <6>[ 27.212720] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11639 06:01:21.537392 <6>[ 27.220391] printk: Suspending console(s) (use no_console_suspend to debug)
11640 06:01:27.258350 <6>[ 27.295487] Disabling non-boot CPUs ...
11641 06:01:27.261661 <4>[ 27.296220] migrate_one_irq: 88 callbacks suppressed
11642 06:01:27.268263 <4>[ 27.296229] IRQ282: set affinity failed(-22).
11643 06:01:27.271551 <4>[ 27.296238] IRQ284: set affinity failed(-22).
11644 06:01:27.274913 <6>[ 27.296294] psci: CPU1 killed (polled 0 ms)
11645 06:01:27.282032 <4>[ 27.297301] IRQ282: set affinity failed(-22).
11646 06:01:27.285238 <4>[ 27.297310] IRQ284: set affinity failed(-22).
11647 06:01:27.292035 <6>[ 27.297361] psci: CPU2 killed (polled 0 ms)
11648 06:01:27.295263 <4>[ 27.298113] IRQ282: set affinity failed(-22).
11649 06:01:27.298582 <4>[ 27.298122] IRQ284: set affinity failed(-22).
11650 06:01:27.305196 <6>[ 27.298163] psci: CPU3 killed (polled 0 ms)
11651 06:01:27.308603 <4>[ 27.298634] IRQ282: set affinity failed(-22).
11652 06:01:27.311875 <4>[ 27.298638] IRQ284: set affinity failed(-22).
11653 06:01:27.318597 <6>[ 27.298659] psci: CPU4 killed (polled 0 ms)
11654 06:01:27.321930 <4>[ 27.299132] IRQ282: set affinity failed(-22).
11655 06:01:27.324632 <4>[ 27.299138] IRQ284: set affinity failed(-22).
11656 06:01:27.331609 <6>[ 27.300181] psci: CPU5 killed (polled 0 ms)
11657 06:01:27.334754 <6>[ 27.300758] psci: CPU6 killed (polled 0 ms)
11658 06:01:27.341315 <6>[ 27.302276] psci: CPU7 killed (polled 0 ms)
11659 06:01:27.344841 <6>[ 27.302709] Enabling non-boot CPUs ...
11660 06:01:27.348106 <6>[ 27.302917] Detected VIPT I-cache on CPU1
11661 06:01:27.354743 <6>[ 27.302992] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11662 06:01:27.361693 <6>[ 27.303046] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11663 06:01:27.364541 <6>[ 27.303595] CPU1 is up
11664 06:01:27.367918 <6>[ 27.303713] Detected VIPT I-cache on CPU2
11665 06:01:27.377862 <6>[ 27.303759] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11666 06:01:27.384664 <6>[ 27.303789] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11667 06:01:27.384761 <6>[ 27.304210] CPU2 is up
11668 06:01:27.391673 <6>[ 27.304329] Detected VIPT I-cache on CPU3
11669 06:01:27.398026 <6>[ 27.304375] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11670 06:01:27.404773 <6>[ 27.304405] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11671 06:01:27.408241 <6>[ 27.304833] CPU3 is up
11672 06:01:27.411705 <6>[ 27.304947] Detected PIPT I-cache on CPU4
11673 06:01:27.418562 <6>[ 27.304969] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11674 06:01:27.425592 <6>[ 27.304983] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11675 06:01:27.428280 <6>[ 27.305242] CPU4 is up
11676 06:01:27.431886 <6>[ 27.305352] Detected PIPT I-cache on CPU5
11677 06:01:27.438176 <6>[ 27.305375] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11678 06:01:27.444933 <6>[ 27.305389] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11679 06:01:27.448250 <6>[ 27.305630] CPU5 is up
11680 06:01:27.451871 <6>[ 27.305740] Detected PIPT I-cache on CPU6
11681 06:01:27.458493 <6>[ 27.305762] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11682 06:01:27.468119 <6>[ 27.305776] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11683 06:01:27.468223 <6>[ 27.306017] CPU6 is up
11684 06:01:27.474835 <6>[ 27.306134] Detected PIPT I-cache on CPU7
11685 06:01:27.481437 <6>[ 27.306162] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11686 06:01:27.488269 <6>[ 27.306176] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11687 06:01:27.491880 <6>[ 27.306448] CPU7 is up
11688 06:01:27.495182 <6>[ 27.893674] OOM killer enabled.
11689 06:01:27.498330 <6>[ 27.897065] Restarting tasks ... done.
11690 06:01:27.504855 <5>[ 27.901444] random: crng reseeded on system resumption
11691 06:01:27.508194 <6>[ 27.907794] PM: suspend exit
11692 06:01:27.516439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=pass>
11693 06:01:27.516739 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=pass
11695 06:01:27.519661 rtcwake: assuming RTC uses UTC ...
11696 06:01:27.526710 rtcwake: wakeup from "mem" using rtc0 at Mon Dec 25 05:58:58 2023
11697 06:01:27.538560 <6>[ 27.936679] PM: suspend entry (deep)
11698 06:01:27.542130 <6>[ 27.940547] Filesystems sync: 0.000 seconds
11699 06:01:27.544844 <6>[ 27.945277] Freezing user space processes
11700 06:01:27.555879 <6>[ 27.950427] Freezing user space processes completed (elapsed 0.000 seconds)
11701 06:01:27.559226 <6>[ 27.957650] OOM killer disabled.
11702 06:01:27.562155 <6>[ 27.961130] Freezing remaining freezable tasks
11703 06:01:27.572067 <6>[ 27.966943] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11704 06:01:27.578508 <6>[ 27.974590] printk: Suspending console(s) (use no_console_suspend to debug)
11705 06:01:33.263344 <6>[ 28.061853] Disabling non-boot CPUs ...
11706 06:01:33.266965 <6>[ 28.062642] psci: CPU1 killed (polled 0 ms)
11707 06:01:33.269635 <6>[ 28.063641] psci: CPU2 killed (polled 0 ms)
11708 06:01:33.276403 <6>[ 28.064448] psci: CPU3 killed (polled 0 ms)
11709 06:01:33.280177 <6>[ 28.064961] psci: CPU4 killed (polled 0 ms)
11710 06:01:33.283076 <6>[ 28.066423] psci: CPU5 killed (polled 4 ms)
11711 06:01:33.290102 <6>[ 28.067004] psci: CPU6 killed (polled 0 ms)
11712 06:01:33.292868 <6>[ 28.068631] psci: CPU7 killed (polled 0 ms)
11713 06:01:33.296264 <6>[ 28.068938] Enabling non-boot CPUs ...
11714 06:01:33.303227 <6>[ 28.069144] Detected VIPT I-cache on CPU1
11715 06:01:33.309398 <6>[ 28.069219] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11716 06:01:33.316231 <6>[ 28.069272] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11717 06:01:33.319526 <6>[ 28.069832] CPU1 is up
11718 06:01:33.323023 <6>[ 28.069950] Detected VIPT I-cache on CPU2
11719 06:01:33.330348 <6>[ 28.069996] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11720 06:01:33.336546 <6>[ 28.070027] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11721 06:01:33.340074 <6>[ 28.070482] CPU2 is up
11722 06:01:33.343327 <6>[ 28.070601] Detected VIPT I-cache on CPU3
11723 06:01:33.349562 <6>[ 28.070647] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11724 06:01:33.356387 <6>[ 28.070677] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11725 06:01:33.359758 <6>[ 28.071103] CPU3 is up
11726 06:01:33.363020 <6>[ 28.071217] Detected PIPT I-cache on CPU4
11727 06:01:33.373123 <6>[ 28.071239] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11728 06:01:33.379893 <6>[ 28.071253] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11729 06:01:33.379978 <6>[ 28.071512] CPU4 is up
11730 06:01:33.386777 <6>[ 28.071623] Detected PIPT I-cache on CPU5
11731 06:01:33.393446 <6>[ 28.071645] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11732 06:01:33.399877 <6>[ 28.071659] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11733 06:01:33.403379 <6>[ 28.071899] CPU5 is up
11734 06:01:33.406299 <6>[ 28.072010] Detected PIPT I-cache on CPU6
11735 06:01:33.412957 <6>[ 28.072032] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11736 06:01:33.419884 <6>[ 28.072045] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11737 06:01:33.423147 <6>[ 28.072297] CPU6 is up
11738 06:01:33.426438 <6>[ 28.072417] Detected PIPT I-cache on CPU7
11739 06:01:33.436057 <6>[ 28.072446] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11740 06:01:33.442879 <6>[ 28.072459] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11741 06:01:33.443013 <6>[ 28.072715] CPU7 is up
11742 06:01:33.446120 <6>[ 28.614368] OOM killer enabled.
11743 06:01:33.453052 <6>[ 28.617758] Restarting tasks ... done.
11744 06:01:33.456272 <5>[ 28.622115] random: crng reseeded on system resumption
11745 06:01:33.459704 <6>[ 28.628499] PM: suspend exit
11746 06:01:33.469128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=pass>
11747 06:01:33.469435 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=pass
11749 06:01:33.472346 rtcwake: assuming RTC uses UTC ...
11750 06:01:33.478621 rtcwake: wakeup from "mem" using rtc0 at Mon Dec 25 05:59:04 2023
11751 06:01:33.491598 <6>[ 28.657072] PM: suspend entry (deep)
11752 06:01:33.495028 <6>[ 28.660958] Filesystems sync: 0.000 seconds
11753 06:01:33.498806 <6>[ 28.665951] Freezing user space processes
11754 06:01:33.510387 <6>[ 28.671905] Freezing user space processes completed (elapsed 0.001 seconds)
11755 06:01:33.513282 <6>[ 28.679137] OOM killer disabled.
11756 06:01:33.516640 <6>[ 28.682620] Freezing remaining freezable tasks
11757 06:01:33.527062 <6>[ 28.688694] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11758 06:01:33.533174 <6>[ 28.696379] printk: Suspending console(s) (use no_console_suspend to debug)
11759 06:01:39.278670 <6>[ 28.783547] Disabling non-boot CPUs ...
11760 06:01:39.282305 <6>[ 28.784480] psci: CPU1 killed (polled 0 ms)
11761 06:01:39.285238 <6>[ 28.785510] psci: CPU2 killed (polled 0 ms)
11762 06:01:39.292534 <6>[ 28.786397] psci: CPU3 killed (polled 0 ms)
11763 06:01:39.295240 <6>[ 28.788060] psci: CPU4 killed (polled 0 ms)
11764 06:01:39.298582 <6>[ 28.789849] psci: CPU5 killed (polled 0 ms)
11765 06:01:39.305883 <6>[ 28.790590] psci: CPU6 killed (polled 0 ms)
11766 06:01:39.308938 <6>[ 28.792218] psci: CPU7 killed (polled 0 ms)
11767 06:01:39.312184 <6>[ 28.792649] Enabling non-boot CPUs ...
11768 06:01:39.318626 <6>[ 28.792876] Detected VIPT I-cache on CPU1
11769 06:01:39.325281 <6>[ 28.792959] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11770 06:01:39.332328 <6>[ 28.793020] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11771 06:01:39.335823 <6>[ 28.793626] CPU1 is up
11772 06:01:39.339298 <6>[ 28.793762] Detected VIPT I-cache on CPU2
11773 06:01:39.345503 <6>[ 28.793815] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11774 06:01:39.352648 <6>[ 28.793852] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11775 06:01:39.355449 <6>[ 28.794353] CPU2 is up
11776 06:01:39.358914 <6>[ 28.794485] Detected VIPT I-cache on CPU3
11777 06:01:39.365571 <6>[ 28.794537] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11778 06:01:39.372001 <6>[ 28.794575] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11779 06:01:39.375439 <6>[ 28.795055] CPU3 is up
11780 06:01:39.378847 <6>[ 28.795195] Detected PIPT I-cache on CPU4
11781 06:01:39.388511 <6>[ 28.795230] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11782 06:01:39.395244 <6>[ 28.795253] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11783 06:01:39.395382 <6>[ 28.795622] CPU4 is up
11784 06:01:39.402225 <6>[ 28.795761] Detected PIPT I-cache on CPU5
11785 06:01:39.409061 <6>[ 28.795797] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11786 06:01:39.415750 <6>[ 28.795821] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11787 06:01:39.418537 <6>[ 28.796181] CPU5 is up
11788 06:01:39.421916 <6>[ 28.796318] Detected PIPT I-cache on CPU6
11789 06:01:39.428813 <6>[ 28.796354] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11790 06:01:39.435368 <6>[ 28.796377] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11791 06:01:39.438915 <6>[ 28.796743] CPU6 is up
11792 06:01:39.442350 <6>[ 28.796884] Detected PIPT I-cache on CPU7
11793 06:01:39.448545 <6>[ 28.796929] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11794 06:01:39.455694 <6>[ 28.796952] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11795 06:01:39.458534 <6>[ 28.797341] CPU7 is up
11796 06:01:39.461994 <6>[ 29.354508] OOM killer enabled.
11797 06:01:39.468837 <6>[ 29.357898] Restarting tasks ... done.
11798 06:01:39.472336 <5>[ 29.362263] random: crng reseeded on system resumption
11799 06:01:39.475731 <6>[ 29.368739] PM: suspend exit
11800 06:01:39.486063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=pass>
11801 06:01:39.486199 + set +x
11802 06:01:39.486457 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=pass
11804 06:01:39.492394 <LAVA_SIGNAL_ENDRUN 0_sleep 12379448_1.5.2.3.1>
11805 06:01:39.492486 <LAVA_TEST_RUNNER EXIT>
11806 06:01:39.492726 Received signal: <ENDRUN> 0_sleep 12379448_1.5.2.3.1
11807 06:01:39.492812 Ending use of test pattern.
11808 06:01:39.492876 Ending test lava.0_sleep (12379448_1.5.2.3.1), duration 59.95
11810 06:01:39.493110 ok: lava_test_shell seems to have completed
11811 06:01:39.493249 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-mem-1: pass
rtcwake-mem-10: pass
rtcwake-mem-2: pass
rtcwake-mem-3: pass
rtcwake-mem-4: pass
rtcwake-mem-5: pass
rtcwake-mem-6: pass
rtcwake-mem-7: pass
rtcwake-mem-8: pass
rtcwake-mem-9: pass
11812 06:01:39.493346 end: 3.1 lava-test-shell (duration 00:01:00) [common]
11813 06:01:39.493434 end: 3 lava-test-retry (duration 00:01:00) [common]
11814 06:01:39.493522 start: 4 finalize (timeout 00:06:28) [common]
11815 06:01:39.493613 start: 4.1 power-off (timeout 00:00:30) [common]
11816 06:01:39.493769 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11817 06:01:39.571192 >> Command sent successfully.
11818 06:01:39.574136 Returned 0 in 0 seconds
11819 06:01:39.674568 end: 4.1 power-off (duration 00:00:00) [common]
11821 06:01:39.675006 start: 4.2 read-feedback (timeout 00:06:28) [common]
11822 06:01:39.675337 Listened to connection for namespace 'common' for up to 1s
11823 06:01:40.676241 Finalising connection for namespace 'common'
11824 06:01:40.676450 Disconnecting from shell: Finalise
11825 06:01:40.676571 / #
11826 06:01:40.776897 end: 4.2 read-feedback (duration 00:00:01) [common]
11827 06:01:40.777075 end: 4 finalize (duration 00:00:01) [common]
11828 06:01:40.777217 Cleaning after the job
11829 06:01:40.777338 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379448/tftp-deploy-81t6ocb1/ramdisk
11830 06:01:40.791023 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379448/tftp-deploy-81t6ocb1/kernel
11831 06:01:40.815309 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379448/tftp-deploy-81t6ocb1/dtb
11832 06:01:40.815576 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379448/tftp-deploy-81t6ocb1/modules
11833 06:01:40.823009 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12379448
11834 06:01:41.002230 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12379448
11835 06:01:41.002401 Job finished correctly