Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 18
- Kernel Errors: 32
- Errors: 1
1 06:02:06.364652 lava-dispatcher, installed at version: 2023.10
2 06:02:06.364878 start: 0 validate
3 06:02:06.365021 Start time: 2023-12-25 06:02:06.365013+00:00 (UTC)
4 06:02:06.365153 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:02:06.365291 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 06:02:06.646582 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:02:06.646786 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:02:06.912738 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:02:06.912962 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:02:07.170067 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:02:07.170264 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 06:02:07.437964 validate duration: 1.07
14 06:02:07.438253 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:02:07.438356 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:02:07.438453 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:02:07.438585 Not decompressing ramdisk as can be used compressed.
18 06:02:07.438675 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 06:02:07.438745 saving as /var/lib/lava/dispatcher/tmp/12379462/tftp-deploy-6shl4gkr/ramdisk/rootfs.cpio.gz
20 06:02:07.438813 total size: 26246609 (25 MB)
21 06:02:07.439892 progress 0 % (0 MB)
22 06:02:07.447376 progress 5 % (1 MB)
23 06:02:07.454701 progress 10 % (2 MB)
24 06:02:07.462274 progress 15 % (3 MB)
25 06:02:07.470124 progress 20 % (5 MB)
26 06:02:07.477869 progress 25 % (6 MB)
27 06:02:07.485211 progress 30 % (7 MB)
28 06:02:07.492533 progress 35 % (8 MB)
29 06:02:07.499839 progress 40 % (10 MB)
30 06:02:07.507146 progress 45 % (11 MB)
31 06:02:07.514588 progress 50 % (12 MB)
32 06:02:07.521884 progress 55 % (13 MB)
33 06:02:07.529275 progress 60 % (15 MB)
34 06:02:07.536715 progress 65 % (16 MB)
35 06:02:07.544037 progress 70 % (17 MB)
36 06:02:07.551761 progress 75 % (18 MB)
37 06:02:07.559083 progress 80 % (20 MB)
38 06:02:07.566910 progress 85 % (21 MB)
39 06:02:07.574691 progress 90 % (22 MB)
40 06:02:07.582278 progress 95 % (23 MB)
41 06:02:07.590014 progress 100 % (25 MB)
42 06:02:07.590311 25 MB downloaded in 0.15 s (165.22 MB/s)
43 06:02:07.590547 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:02:07.590991 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:02:07.591114 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:02:07.591259 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:02:07.591442 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 06:02:07.591543 saving as /var/lib/lava/dispatcher/tmp/12379462/tftp-deploy-6shl4gkr/kernel/Image
50 06:02:07.591636 total size: 50024960 (47 MB)
51 06:02:07.591731 No compression specified
52 06:02:07.593365 progress 0 % (0 MB)
53 06:02:07.608066 progress 5 % (2 MB)
54 06:02:07.622358 progress 10 % (4 MB)
55 06:02:07.636657 progress 15 % (7 MB)
56 06:02:07.651242 progress 20 % (9 MB)
57 06:02:07.665460 progress 25 % (11 MB)
58 06:02:07.679806 progress 30 % (14 MB)
59 06:02:07.694229 progress 35 % (16 MB)
60 06:02:07.708429 progress 40 % (19 MB)
61 06:02:07.722619 progress 45 % (21 MB)
62 06:02:07.736900 progress 50 % (23 MB)
63 06:02:07.750922 progress 55 % (26 MB)
64 06:02:07.764932 progress 60 % (28 MB)
65 06:02:07.779299 progress 65 % (31 MB)
66 06:02:07.793554 progress 70 % (33 MB)
67 06:02:07.807835 progress 75 % (35 MB)
68 06:02:07.822073 progress 80 % (38 MB)
69 06:02:07.836006 progress 85 % (40 MB)
70 06:02:07.850173 progress 90 % (42 MB)
71 06:02:07.864422 progress 95 % (45 MB)
72 06:02:07.878374 progress 100 % (47 MB)
73 06:02:07.878630 47 MB downloaded in 0.29 s (166.23 MB/s)
74 06:02:07.878834 end: 1.2.1 http-download (duration 00:00:00) [common]
76 06:02:07.879212 end: 1.2 download-retry (duration 00:00:00) [common]
77 06:02:07.879335 start: 1.3 download-retry (timeout 00:10:00) [common]
78 06:02:07.879451 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 06:02:07.879595 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 06:02:07.879681 saving as /var/lib/lava/dispatcher/tmp/12379462/tftp-deploy-6shl4gkr/dtb/mt8192-asurada-spherion-r0.dtb
81 06:02:07.879776 total size: 47278 (0 MB)
82 06:02:07.879874 No compression specified
83 06:02:07.881216 progress 69 % (0 MB)
84 06:02:07.881549 progress 100 % (0 MB)
85 06:02:07.881744 0 MB downloaded in 0.00 s (22.95 MB/s)
86 06:02:07.881918 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:02:07.882299 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:02:07.882418 start: 1.4 download-retry (timeout 00:10:00) [common]
90 06:02:07.882535 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 06:02:07.882687 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 06:02:07.882785 saving as /var/lib/lava/dispatcher/tmp/12379462/tftp-deploy-6shl4gkr/modules/modules.tar
93 06:02:07.882876 total size: 8619328 (8 MB)
94 06:02:07.882970 Using unxz to decompress xz
95 06:02:07.887671 progress 0 % (0 MB)
96 06:02:07.909566 progress 5 % (0 MB)
97 06:02:07.934173 progress 10 % (0 MB)
98 06:02:07.959104 progress 15 % (1 MB)
99 06:02:07.983864 progress 20 % (1 MB)
100 06:02:08.009037 progress 25 % (2 MB)
101 06:02:08.036500 progress 30 % (2 MB)
102 06:02:08.064398 progress 35 % (2 MB)
103 06:02:08.090597 progress 40 % (3 MB)
104 06:02:08.117405 progress 45 % (3 MB)
105 06:02:08.144948 progress 50 % (4 MB)
106 06:02:08.171453 progress 55 % (4 MB)
107 06:02:08.199884 progress 60 % (4 MB)
108 06:02:08.229456 progress 65 % (5 MB)
109 06:02:08.259893 progress 70 % (5 MB)
110 06:02:08.287690 progress 75 % (6 MB)
111 06:02:08.319016 progress 80 % (6 MB)
112 06:02:08.347557 progress 85 % (7 MB)
113 06:02:08.376161 progress 90 % (7 MB)
114 06:02:08.409633 progress 95 % (7 MB)
115 06:02:08.441902 progress 100 % (8 MB)
116 06:02:08.446679 8 MB downloaded in 0.56 s (14.58 MB/s)
117 06:02:08.446992 end: 1.4.1 http-download (duration 00:00:01) [common]
119 06:02:08.447391 end: 1.4 download-retry (duration 00:00:01) [common]
120 06:02:08.447488 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 06:02:08.447620 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 06:02:08.447744 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:02:08.447881 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 06:02:08.448163 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np
125 06:02:08.448369 makedir: /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin
126 06:02:08.448523 makedir: /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/tests
127 06:02:08.448660 makedir: /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/results
128 06:02:08.448828 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-add-keys
129 06:02:08.449046 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-add-sources
130 06:02:08.449222 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-background-process-start
131 06:02:08.449404 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-background-process-stop
132 06:02:08.449576 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-common-functions
133 06:02:08.449752 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-echo-ipv4
134 06:02:08.449919 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-install-packages
135 06:02:08.450102 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-installed-packages
136 06:02:08.450288 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-os-build
137 06:02:08.450484 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-probe-channel
138 06:02:08.450667 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-probe-ip
139 06:02:08.450856 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-target-ip
140 06:02:08.451043 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-target-mac
141 06:02:08.451226 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-target-storage
142 06:02:08.451425 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-test-case
143 06:02:08.451604 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-test-event
144 06:02:08.451789 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-test-feedback
145 06:02:08.451978 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-test-raise
146 06:02:08.452165 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-test-reference
147 06:02:08.452359 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-test-runner
148 06:02:08.452547 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-test-set
149 06:02:08.452734 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-test-shell
150 06:02:08.452915 Updating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-install-packages (oe)
151 06:02:08.453126 Updating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/bin/lava-installed-packages (oe)
152 06:02:08.453301 Creating /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/environment
153 06:02:08.453447 LAVA metadata
154 06:02:08.453553 - LAVA_JOB_ID=12379462
155 06:02:08.453650 - LAVA_DISPATCHER_IP=192.168.201.1
156 06:02:08.453791 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 06:02:08.453894 skipped lava-vland-overlay
158 06:02:08.454018 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 06:02:08.454138 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 06:02:08.454248 skipped lava-multinode-overlay
161 06:02:08.454364 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 06:02:08.454494 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 06:02:08.454616 Loading test definitions
164 06:02:08.454759 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 06:02:08.454878 Using /lava-12379462 at stage 0
166 06:02:08.455331 uuid=12379462_1.5.2.3.1 testdef=None
167 06:02:08.455458 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 06:02:08.455583 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 06:02:08.456359 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 06:02:08.456722 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 06:02:08.457634 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 06:02:08.458019 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 06:02:08.458926 runner path: /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 12379462_1.5.2.3.1
176 06:02:08.459124 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 06:02:08.459350 Creating lava-test-runner.conf files
179 06:02:08.459450 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379462/lava-overlay-jz3213np/lava-12379462/0 for stage 0
180 06:02:08.459575 - 0_v4l2-compliance-mtk-vcodec-enc
181 06:02:08.459705 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 06:02:08.459830 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 06:02:08.468900 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 06:02:08.469055 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 06:02:08.469176 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 06:02:08.469307 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 06:02:08.469432 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 06:02:09.250123 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 06:02:09.250562 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 06:02:09.250732 extracting modules file /var/lib/lava/dispatcher/tmp/12379462/tftp-deploy-6shl4gkr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379462/extract-overlay-ramdisk-87x6i6o3/ramdisk
191 06:02:09.559531 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 06:02:09.559717 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 06:02:09.559852 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379462/compress-overlay-5zglgo_6/overlay-1.5.2.4.tar.gz to ramdisk
194 06:02:09.559961 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379462/compress-overlay-5zglgo_6/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12379462/extract-overlay-ramdisk-87x6i6o3/ramdisk
195 06:02:09.570619 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 06:02:09.570774 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 06:02:09.570915 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 06:02:09.571044 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 06:02:09.571156 Building ramdisk /var/lib/lava/dispatcher/tmp/12379462/extract-overlay-ramdisk-87x6i6o3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12379462/extract-overlay-ramdisk-87x6i6o3/ramdisk
200 06:02:10.219024 >> 228444 blocks
201 06:02:14.352645 rename /var/lib/lava/dispatcher/tmp/12379462/extract-overlay-ramdisk-87x6i6o3/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12379462/tftp-deploy-6shl4gkr/ramdisk/ramdisk.cpio.gz
202 06:02:14.353122 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 06:02:14.353321 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 06:02:14.353486 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 06:02:14.353655 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12379462/tftp-deploy-6shl4gkr/kernel/Image'
206 06:02:27.650570 Returned 0 in 13 seconds
207 06:02:27.751244 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12379462/tftp-deploy-6shl4gkr/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12379462/tftp-deploy-6shl4gkr/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12379462/tftp-deploy-6shl4gkr/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12379462/tftp-deploy-6shl4gkr/kernel/image.itb
208 06:02:28.379790 output: FIT description: Kernel Image image with one or more FDT blobs
209 06:02:28.380199 output: Created: Mon Dec 25 06:02:28 2023
210 06:02:28.380320 output: Image 0 (kernel-1)
211 06:02:28.380393 output: Description:
212 06:02:28.380491 output: Created: Mon Dec 25 06:02:28 2023
213 06:02:28.380588 output: Type: Kernel Image
214 06:02:28.380681 output: Compression: lzma compressed
215 06:02:28.380779 output: Data Size: 11481830 Bytes = 11212.72 KiB = 10.95 MiB
216 06:02:28.380896 output: Architecture: AArch64
217 06:02:28.380990 output: OS: Linux
218 06:02:28.381082 output: Load Address: 0x00000000
219 06:02:28.381174 output: Entry Point: 0x00000000
220 06:02:28.381263 output: Hash algo: crc32
221 06:02:28.381352 output: Hash value: a47c00f1
222 06:02:28.381441 output: Image 1 (fdt-1)
223 06:02:28.381541 output: Description: mt8192-asurada-spherion-r0
224 06:02:28.381643 output: Created: Mon Dec 25 06:02:28 2023
225 06:02:28.381731 output: Type: Flat Device Tree
226 06:02:28.381816 output: Compression: uncompressed
227 06:02:28.381901 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 06:02:28.381985 output: Architecture: AArch64
229 06:02:28.382071 output: Hash algo: crc32
230 06:02:28.382154 output: Hash value: cc4352de
231 06:02:28.382237 output: Image 2 (ramdisk-1)
232 06:02:28.382348 output: Description: unavailable
233 06:02:28.382442 output: Created: Mon Dec 25 06:02:28 2023
234 06:02:28.382528 output: Type: RAMDisk Image
235 06:02:28.382616 output: Compression: Unknown Compression
236 06:02:28.382701 output: Data Size: 39357832 Bytes = 38435.38 KiB = 37.53 MiB
237 06:02:28.382786 output: Architecture: AArch64
238 06:02:28.382870 output: OS: Linux
239 06:02:28.382967 output: Load Address: unavailable
240 06:02:28.383054 output: Entry Point: unavailable
241 06:02:28.383137 output: Hash algo: crc32
242 06:02:28.383220 output: Hash value: 213c9009
243 06:02:28.383305 output: Default Configuration: 'conf-1'
244 06:02:28.383388 output: Configuration 0 (conf-1)
245 06:02:28.383471 output: Description: mt8192-asurada-spherion-r0
246 06:02:28.383556 output: Kernel: kernel-1
247 06:02:28.383639 output: Init Ramdisk: ramdisk-1
248 06:02:28.383737 output: FDT: fdt-1
249 06:02:28.383822 output: Loadables: kernel-1
250 06:02:28.383905 output:
251 06:02:28.384142 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 06:02:28.384274 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 06:02:28.384395 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 06:02:28.384551 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 06:02:28.384660 No LXC device requested
256 06:02:28.384787 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 06:02:28.384934 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 06:02:28.385051 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 06:02:28.385172 Checking files for TFTP limit of 4294967296 bytes.
260 06:02:28.385856 end: 1 tftp-deploy (duration 00:00:21) [common]
261 06:02:28.386009 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 06:02:28.386158 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 06:02:28.386339 substitutions:
264 06:02:28.386444 - {DTB}: 12379462/tftp-deploy-6shl4gkr/dtb/mt8192-asurada-spherion-r0.dtb
265 06:02:28.386552 - {INITRD}: 12379462/tftp-deploy-6shl4gkr/ramdisk/ramdisk.cpio.gz
266 06:02:28.386652 - {KERNEL}: 12379462/tftp-deploy-6shl4gkr/kernel/Image
267 06:02:28.386751 - {LAVA_MAC}: None
268 06:02:28.386849 - {PRESEED_CONFIG}: None
269 06:02:28.386927 - {PRESEED_LOCAL}: None
270 06:02:28.387024 - {RAMDISK}: 12379462/tftp-deploy-6shl4gkr/ramdisk/ramdisk.cpio.gz
271 06:02:28.387122 - {ROOT_PART}: None
272 06:02:28.387218 - {ROOT}: None
273 06:02:28.387315 - {SERVER_IP}: 192.168.201.1
274 06:02:28.387410 - {TEE}: None
275 06:02:28.387506 Parsed boot commands:
276 06:02:28.387602 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 06:02:28.387841 Parsed boot commands: tftpboot 192.168.201.1 12379462/tftp-deploy-6shl4gkr/kernel/image.itb 12379462/tftp-deploy-6shl4gkr/kernel/cmdline
278 06:02:28.387972 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 06:02:28.388103 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 06:02:28.388245 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 06:02:28.388384 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 06:02:28.388497 Not connected, no need to disconnect.
283 06:02:28.388616 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 06:02:28.388744 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 06:02:28.388850 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 06:02:28.392936 Setting prompt string to ['lava-test: # ']
287 06:02:28.393368 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 06:02:28.393533 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 06:02:28.393676 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 06:02:28.393828 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 06:02:28.394186 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 06:02:33.531948 >> Command sent successfully.
293 06:02:33.534405 Returned 0 in 5 seconds
294 06:02:33.634810 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 06:02:33.635252 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 06:02:33.635399 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 06:02:33.635527 Setting prompt string to 'Starting depthcharge on Spherion...'
299 06:02:33.635633 Changing prompt to 'Starting depthcharge on Spherion...'
300 06:02:33.635737 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 06:02:33.636117 [Enter `^Ec?' for help]
302 06:02:33.809689
303 06:02:33.809871
304 06:02:33.809978 F0: 102B 0000
305 06:02:33.810078
306 06:02:33.810176 F3: 1001 0000 [0200]
307 06:02:33.810273
308 06:02:33.813203 F3: 1001 0000
309 06:02:33.813312
310 06:02:33.813411 F7: 102D 0000
311 06:02:33.813504
312 06:02:33.816539 F1: 0000 0000
313 06:02:33.816653
314 06:02:33.816756 V0: 0000 0000 [0001]
315 06:02:33.816853
316 06:02:33.816952 00: 0007 8000
317 06:02:33.819979
318 06:02:33.820089 01: 0000 0000
319 06:02:33.820188
320 06:02:33.820290 BP: 0C00 0209 [0000]
321 06:02:33.820420
322 06:02:33.823387 G0: 1182 0000
323 06:02:33.823494
324 06:02:33.823593 EC: 0000 0021 [4000]
325 06:02:33.823692
326 06:02:33.826586 S7: 0000 0000 [0000]
327 06:02:33.826696
328 06:02:33.826789 CC: 0000 0000 [0001]
329 06:02:33.826879
330 06:02:33.830533 T0: 0000 0040 [010F]
331 06:02:33.830643
332 06:02:33.830738 Jump to BL
333 06:02:33.830836
334 06:02:33.856401
335 06:02:33.856561
336 06:02:33.856661
337 06:02:33.863429 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 06:02:33.867120 ARM64: Exception handlers installed.
339 06:02:33.870546 ARM64: Testing exception
340 06:02:33.874010 ARM64: Done test exception
341 06:02:33.880356 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 06:02:33.891248 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 06:02:33.897416 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 06:02:33.907920 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 06:02:33.914449 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 06:02:33.921171 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 06:02:33.933723 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 06:02:33.940036 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 06:02:33.959055 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 06:02:33.962092 WDT: Last reset was cold boot
351 06:02:33.965663 SPI1(PAD0) initialized at 2873684 Hz
352 06:02:33.968707 SPI5(PAD0) initialized at 992727 Hz
353 06:02:33.972250 VBOOT: Loading verstage.
354 06:02:33.979267 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 06:02:33.983221 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 06:02:33.986834 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 06:02:33.990265 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 06:02:33.996475 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 06:02:34.003178 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 06:02:34.014470 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 06:02:34.014609
362 06:02:34.014677
363 06:02:34.024498 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 06:02:34.027792 ARM64: Exception handlers installed.
365 06:02:34.031285 ARM64: Testing exception
366 06:02:34.031370 ARM64: Done test exception
367 06:02:34.038258 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 06:02:34.041898 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 06:02:34.054946 Probing TPM: . done!
370 06:02:34.055045 TPM ready after 0 ms
371 06:02:34.062563 Connected to device vid:did:rid of 1ae0:0028:00
372 06:02:34.069471 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 06:02:34.127838 Initialized TPM device CR50 revision 0
374 06:02:34.139675 tlcl_send_startup: Startup return code is 0
375 06:02:34.139859 TPM: setup succeeded
376 06:02:34.151362 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 06:02:34.159993 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 06:02:34.174358 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 06:02:34.181646 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 06:02:34.184588 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 06:02:34.188940 in-header: 03 07 00 00 08 00 00 00
382 06:02:34.192507 in-data: aa e4 47 04 13 02 00 00
383 06:02:34.195836 Chrome EC: UHEPI supported
384 06:02:34.203537 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 06:02:34.206969 in-header: 03 95 00 00 08 00 00 00
386 06:02:34.210217 in-data: 18 20 20 08 00 00 00 00
387 06:02:34.210353 Phase 1
388 06:02:34.213851 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 06:02:34.221229 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 06:02:34.224940 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 06:02:34.228270 Recovery requested (1009000e)
392 06:02:34.237294 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 06:02:34.242741 tlcl_extend: response is 0
394 06:02:34.252191 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 06:02:34.257745 tlcl_extend: response is 0
396 06:02:34.264816 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 06:02:34.284406 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 06:02:34.291174 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 06:02:34.291309
400 06:02:34.291382
401 06:02:34.301135 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 06:02:34.304741 ARM64: Exception handlers installed.
403 06:02:34.307595 ARM64: Testing exception
404 06:02:34.307690 ARM64: Done test exception
405 06:02:34.329564 pmic_efuse_setting: Set efuses in 11 msecs
406 06:02:34.333059 pmwrap_interface_init: Select PMIF_VLD_RDY
407 06:02:34.340105 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 06:02:34.343089 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 06:02:34.350722 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 06:02:34.354117 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 06:02:34.357927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 06:02:34.361987 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 06:02:34.368621 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 06:02:34.372595 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 06:02:34.376292 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 06:02:34.383768 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 06:02:34.387229 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 06:02:34.391163 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 06:02:34.394625 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 06:02:34.402368 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 06:02:34.405949 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 06:02:34.413628 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 06:02:34.420759 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 06:02:34.424232 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 06:02:34.431253 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 06:02:34.435254 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 06:02:34.442365 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 06:02:34.446580 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 06:02:34.453709 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 06:02:34.457608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 06:02:34.464725 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 06:02:34.469088 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 06:02:34.475413 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 06:02:34.479262 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 06:02:34.483228 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 06:02:34.490308 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 06:02:34.493936 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 06:02:34.497386 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 06:02:34.504811 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 06:02:34.508792 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 06:02:34.512373 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 06:02:34.520035 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 06:02:34.523563 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 06:02:34.527099 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 06:02:34.534734 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 06:02:34.538836 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 06:02:34.542423 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 06:02:34.546082 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 06:02:34.549504 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 06:02:34.557020 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 06:02:34.560582 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 06:02:34.564700 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 06:02:34.568676 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 06:02:34.572003 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 06:02:34.575529 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 06:02:34.579127 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 06:02:34.582750 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 06:02:34.594128 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 06:02:34.601919 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 06:02:34.605280 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 06:02:34.612392 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 06:02:34.623651 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 06:02:34.627753 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 06:02:34.631645 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 06:02:34.634806 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 06:02:34.644164 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x4
467 06:02:34.647322 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 06:02:34.652169 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 06:02:34.659138 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 06:02:34.667401 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 06:02:34.677407 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 06:02:34.686535 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 06:02:34.695821 [RTC]rtc_get_frequency_meter,154: input=17, output=803
474 06:02:34.705172 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 06:02:34.715400 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 06:02:34.725378 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 06:02:34.728956 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 06:02:34.732539 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 06:02:34.736050 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 06:02:34.743447 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 06:02:34.747461 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 06:02:34.751383 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 06:02:34.755095 ADC[4]: Raw value=906573 ID=7
484 06:02:34.755206 ADC[3]: Raw value=213441 ID=1
485 06:02:34.758541 RAM Code: 0x71
486 06:02:34.762433 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 06:02:34.766379 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 06:02:34.773750 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 06:02:34.782073 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 06:02:34.785294 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 06:02:34.789263 in-header: 03 07 00 00 08 00 00 00
492 06:02:34.792898 in-data: aa e4 47 04 13 02 00 00
493 06:02:34.797134 Chrome EC: UHEPI supported
494 06:02:34.804229 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 06:02:34.807825 in-header: 03 95 00 00 08 00 00 00
496 06:02:34.807989 in-data: 18 20 20 08 00 00 00 00
497 06:02:34.811313 MRC: failed to locate region type 0.
498 06:02:34.819108 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 06:02:34.822659 DRAM-K: Running full calibration
500 06:02:34.826944 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 06:02:34.830403 header.status = 0x0
502 06:02:34.833893 header.version = 0x6 (expected: 0x6)
503 06:02:34.837349 header.size = 0xd00 (expected: 0xd00)
504 06:02:34.837541 header.flags = 0x0
505 06:02:34.845302 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 06:02:34.863026 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 06:02:34.870349 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 06:02:34.870449 dram_init: ddr_geometry: 2
509 06:02:34.873648 [EMI] MDL number = 2
510 06:02:34.877814 [EMI] Get MDL freq = 0
511 06:02:34.877904 dram_init: ddr_type: 0
512 06:02:34.881030 is_discrete_lpddr4: 1
513 06:02:34.885081 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 06:02:34.885169
515 06:02:34.885237
516 06:02:34.885300 [Bian_co] ETT version 0.0.0.1
517 06:02:34.893093 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 06:02:34.893213
519 06:02:34.896530 dramc_set_vcore_voltage set vcore to 650000
520 06:02:34.896614 Read voltage for 800, 4
521 06:02:34.896681 Vio18 = 0
522 06:02:34.900067 Vcore = 650000
523 06:02:34.900177 Vdram = 0
524 06:02:34.900272 Vddq = 0
525 06:02:34.904013 Vmddr = 0
526 06:02:34.904100 dram_init: config_dvfs: 1
527 06:02:34.911425 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 06:02:34.915064 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 06:02:34.918654 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 06:02:34.922865 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 06:02:34.926476 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 06:02:34.930491 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 06:02:34.934160 MEM_TYPE=3, freq_sel=18
534 06:02:34.934279 sv_algorithm_assistance_LP4_1600
535 06:02:34.940696 ============ PULL DRAM RESETB DOWN ============
536 06:02:34.944330 ========== PULL DRAM RESETB DOWN end =========
537 06:02:34.947960 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 06:02:34.950775 ===================================
539 06:02:34.954560 LPDDR4 DRAM CONFIGURATION
540 06:02:34.958076 ===================================
541 06:02:34.958167 EX_ROW_EN[0] = 0x0
542 06:02:34.961772 EX_ROW_EN[1] = 0x0
543 06:02:34.961858 LP4Y_EN = 0x0
544 06:02:34.965330 WORK_FSP = 0x0
545 06:02:34.965428 WL = 0x2
546 06:02:34.969093 RL = 0x2
547 06:02:34.969181 BL = 0x2
548 06:02:34.971966 RPST = 0x0
549 06:02:34.972079 RD_PRE = 0x0
550 06:02:34.975443 WR_PRE = 0x1
551 06:02:34.975529 WR_PST = 0x0
552 06:02:34.978750 DBI_WR = 0x0
553 06:02:34.978864 DBI_RD = 0x0
554 06:02:34.982175 OTF = 0x1
555 06:02:34.986156 ===================================
556 06:02:34.989131 ===================================
557 06:02:34.989243 ANA top config
558 06:02:34.992016 ===================================
559 06:02:34.995602 DLL_ASYNC_EN = 0
560 06:02:34.998959 ALL_SLAVE_EN = 1
561 06:02:35.002441 NEW_RANK_MODE = 1
562 06:02:35.002530 DLL_IDLE_MODE = 1
563 06:02:35.006034 LP45_APHY_COMB_EN = 1
564 06:02:35.008793 TX_ODT_DIS = 1
565 06:02:35.012849 NEW_8X_MODE = 1
566 06:02:35.016815 ===================================
567 06:02:35.016905 ===================================
568 06:02:35.019831 data_rate = 1600
569 06:02:35.023279 CKR = 1
570 06:02:35.026801 DQ_P2S_RATIO = 8
571 06:02:35.030223 ===================================
572 06:02:35.033259 CA_P2S_RATIO = 8
573 06:02:35.036490 DQ_CA_OPEN = 0
574 06:02:35.036580 DQ_SEMI_OPEN = 0
575 06:02:35.039878 CA_SEMI_OPEN = 0
576 06:02:35.043308 CA_FULL_RATE = 0
577 06:02:35.047020 DQ_CKDIV4_EN = 1
578 06:02:35.049815 CA_CKDIV4_EN = 1
579 06:02:35.053315 CA_PREDIV_EN = 0
580 06:02:35.053400 PH8_DLY = 0
581 06:02:35.056791 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 06:02:35.060297 DQ_AAMCK_DIV = 4
583 06:02:35.063598 CA_AAMCK_DIV = 4
584 06:02:35.067114 CA_ADMCK_DIV = 4
585 06:02:35.067201 DQ_TRACK_CA_EN = 0
586 06:02:35.070019 CA_PICK = 800
587 06:02:35.073731 CA_MCKIO = 800
588 06:02:35.077261 MCKIO_SEMI = 0
589 06:02:35.080816 PLL_FREQ = 3068
590 06:02:35.080905 DQ_UI_PI_RATIO = 32
591 06:02:35.084942 CA_UI_PI_RATIO = 0
592 06:02:35.089056 ===================================
593 06:02:35.092959 ===================================
594 06:02:35.096399 memory_type:LPDDR4
595 06:02:35.096483 GP_NUM : 10
596 06:02:35.100623 SRAM_EN : 1
597 06:02:35.100730 MD32_EN : 0
598 06:02:35.104058 ===================================
599 06:02:35.108102 [ANA_INIT] >>>>>>>>>>>>>>
600 06:02:35.108217 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 06:02:35.111633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 06:02:35.115342 ===================================
603 06:02:35.118049 data_rate = 1600,PCW = 0X7600
604 06:02:35.121711 ===================================
605 06:02:35.124584 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 06:02:35.131444 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 06:02:35.135088 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 06:02:35.141689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 06:02:35.144987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 06:02:35.148166 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 06:02:35.148254 [ANA_INIT] flow start
612 06:02:35.151700 [ANA_INIT] PLL >>>>>>>>
613 06:02:35.155131 [ANA_INIT] PLL <<<<<<<<
614 06:02:35.158830 [ANA_INIT] MIDPI >>>>>>>>
615 06:02:35.158918 [ANA_INIT] MIDPI <<<<<<<<
616 06:02:35.161613 [ANA_INIT] DLL >>>>>>>>
617 06:02:35.161770 [ANA_INIT] flow end
618 06:02:35.168603 ============ LP4 DIFF to SE enter ============
619 06:02:35.171660 ============ LP4 DIFF to SE exit ============
620 06:02:35.175375 [ANA_INIT] <<<<<<<<<<<<<
621 06:02:35.178283 [Flow] Enable top DCM control >>>>>
622 06:02:35.181953 [Flow] Enable top DCM control <<<<<
623 06:02:35.182060 Enable DLL master slave shuffle
624 06:02:35.188178 ==============================================================
625 06:02:35.191767 Gating Mode config
626 06:02:35.195127 ==============================================================
627 06:02:35.198466 Config description:
628 06:02:35.208505 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 06:02:35.215441 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 06:02:35.218307 SELPH_MODE 0: By rank 1: By Phase
631 06:02:35.224734 ==============================================================
632 06:02:35.228220 GAT_TRACK_EN = 1
633 06:02:35.231613 RX_GATING_MODE = 2
634 06:02:35.235139 RX_GATING_TRACK_MODE = 2
635 06:02:35.238223 SELPH_MODE = 1
636 06:02:35.238309 PICG_EARLY_EN = 1
637 06:02:35.241711 VALID_LAT_VALUE = 1
638 06:02:35.248118 ==============================================================
639 06:02:35.251515 Enter into Gating configuration >>>>
640 06:02:35.254916 Exit from Gating configuration <<<<
641 06:02:35.258383 Enter into DVFS_PRE_config >>>>>
642 06:02:35.268256 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 06:02:35.271757 Exit from DVFS_PRE_config <<<<<
644 06:02:35.275476 Enter into PICG configuration >>>>
645 06:02:35.278428 Exit from PICG configuration <<<<
646 06:02:35.281904 [RX_INPUT] configuration >>>>>
647 06:02:35.285045 [RX_INPUT] configuration <<<<<
648 06:02:35.288664 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 06:02:35.295158 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 06:02:35.302211 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 06:02:35.308310 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 06:02:35.311816 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 06:02:35.318771 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 06:02:35.321956 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 06:02:35.328469 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 06:02:35.332086 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 06:02:35.335468 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 06:02:35.338947 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 06:02:35.345317 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 06:02:35.348718 ===================================
661 06:02:35.348804 LPDDR4 DRAM CONFIGURATION
662 06:02:35.352262 ===================================
663 06:02:35.355109 EX_ROW_EN[0] = 0x0
664 06:02:35.358700 EX_ROW_EN[1] = 0x0
665 06:02:35.358807 LP4Y_EN = 0x0
666 06:02:35.361691 WORK_FSP = 0x0
667 06:02:35.361779 WL = 0x2
668 06:02:35.365220 RL = 0x2
669 06:02:35.365303 BL = 0x2
670 06:02:35.368769 RPST = 0x0
671 06:02:35.368852 RD_PRE = 0x0
672 06:02:35.372130 WR_PRE = 0x1
673 06:02:35.372229 WR_PST = 0x0
674 06:02:35.374913 DBI_WR = 0x0
675 06:02:35.374996 DBI_RD = 0x0
676 06:02:35.378404 OTF = 0x1
677 06:02:35.381805 ===================================
678 06:02:35.385396 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 06:02:35.388224 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 06:02:35.395074 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 06:02:35.398386 ===================================
682 06:02:35.398471 LPDDR4 DRAM CONFIGURATION
683 06:02:35.401976 ===================================
684 06:02:35.405531 EX_ROW_EN[0] = 0x10
685 06:02:35.405617 EX_ROW_EN[1] = 0x0
686 06:02:35.408221 LP4Y_EN = 0x0
687 06:02:35.408348 WORK_FSP = 0x0
688 06:02:35.412050 WL = 0x2
689 06:02:35.415283 RL = 0x2
690 06:02:35.415395 BL = 0x2
691 06:02:35.418537 RPST = 0x0
692 06:02:35.418620 RD_PRE = 0x0
693 06:02:35.422113 WR_PRE = 0x1
694 06:02:35.422197 WR_PST = 0x0
695 06:02:35.425301 DBI_WR = 0x0
696 06:02:35.425412 DBI_RD = 0x0
697 06:02:35.428553 OTF = 0x1
698 06:02:35.431827 ===================================
699 06:02:35.435045 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 06:02:35.440981 nWR fixed to 40
701 06:02:35.444170 [ModeRegInit_LP4] CH0 RK0
702 06:02:35.444259 [ModeRegInit_LP4] CH0 RK1
703 06:02:35.447883 [ModeRegInit_LP4] CH1 RK0
704 06:02:35.450660 [ModeRegInit_LP4] CH1 RK1
705 06:02:35.450743 match AC timing 13
706 06:02:35.457722 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 06:02:35.460523 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 06:02:35.463944 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 06:02:35.470545 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 06:02:35.474162 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 06:02:35.474247 [EMI DOE] emi_dcm 0
712 06:02:35.481185 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 06:02:35.481272 ==
714 06:02:35.484556 Dram Type= 6, Freq= 0, CH_0, rank 0
715 06:02:35.487274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 06:02:35.487357 ==
717 06:02:35.494351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 06:02:35.500804 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 06:02:35.507904 [CA 0] Center 36 (6~67) winsize 62
720 06:02:35.511421 [CA 1] Center 36 (6~67) winsize 62
721 06:02:35.514888 [CA 2] Center 34 (4~65) winsize 62
722 06:02:35.517927 [CA 3] Center 33 (3~64) winsize 62
723 06:02:35.521381 [CA 4] Center 33 (3~64) winsize 62
724 06:02:35.524712 [CA 5] Center 32 (3~62) winsize 60
725 06:02:35.524797
726 06:02:35.527848 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 06:02:35.527933
728 06:02:35.531803 [CATrainingPosCal] consider 1 rank data
729 06:02:35.534964 u2DelayCellTimex100 = 270/100 ps
730 06:02:35.538281 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 06:02:35.541682 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 06:02:35.548206 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 06:02:35.551706 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 06:02:35.555070 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 06:02:35.558387 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 06:02:35.558492
737 06:02:35.561665 CA PerBit enable=1, Macro0, CA PI delay=32
738 06:02:35.561749
739 06:02:35.564870 [CBTSetCACLKResult] CA Dly = 32
740 06:02:35.564981 CS Dly: 4 (0~35)
741 06:02:35.565076 ==
742 06:02:35.568479 Dram Type= 6, Freq= 0, CH_0, rank 1
743 06:02:35.574900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 06:02:35.574987 ==
745 06:02:35.578358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 06:02:35.585352 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 06:02:35.594383 [CA 0] Center 36 (6~67) winsize 62
748 06:02:35.597775 [CA 1] Center 36 (6~67) winsize 62
749 06:02:35.601190 [CA 2] Center 34 (4~65) winsize 62
750 06:02:35.604808 [CA 3] Center 34 (3~65) winsize 63
751 06:02:35.607616 [CA 4] Center 32 (2~63) winsize 62
752 06:02:35.611172 [CA 5] Center 32 (2~62) winsize 61
753 06:02:35.611258
754 06:02:35.614599 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 06:02:35.614750
756 06:02:35.618179 [CATrainingPosCal] consider 2 rank data
757 06:02:35.620893 u2DelayCellTimex100 = 270/100 ps
758 06:02:35.624465 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 06:02:35.627848 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 06:02:35.634180 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 06:02:35.637561 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 06:02:35.640962 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 06:02:35.644462 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 06:02:35.644547
765 06:02:35.648146 CA PerBit enable=1, Macro0, CA PI delay=32
766 06:02:35.648230
767 06:02:35.651393 [CBTSetCACLKResult] CA Dly = 32
768 06:02:35.651478 CS Dly: 5 (0~37)
769 06:02:35.651544
770 06:02:35.654802 ----->DramcWriteLeveling(PI) begin...
771 06:02:35.654890 ==
772 06:02:35.658338 Dram Type= 6, Freq= 0, CH_0, rank 0
773 06:02:35.661915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 06:02:35.666005 ==
775 06:02:35.666091 Write leveling (Byte 0): 34 => 34
776 06:02:35.669362 Write leveling (Byte 1): 28 => 28
777 06:02:35.672719 DramcWriteLeveling(PI) end<-----
778 06:02:35.672812
779 06:02:35.672879 ==
780 06:02:35.675380 Dram Type= 6, Freq= 0, CH_0, rank 0
781 06:02:35.679092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 06:02:35.682178 ==
783 06:02:35.682269 [Gating] SW mode calibration
784 06:02:35.689163 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 06:02:35.695922 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 06:02:35.699423 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 06:02:35.706112 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 06:02:35.709663 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
789 06:02:35.712483 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 06:02:35.716104 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 06:02:35.722490 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 06:02:35.726116 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 06:02:35.729681 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 06:02:35.735982 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 06:02:35.739436 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 06:02:35.743073 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 06:02:35.749581 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 06:02:35.753135 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 06:02:35.755865 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 06:02:35.762737 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 06:02:35.766178 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 06:02:35.769722 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 06:02:35.776129 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 06:02:35.779654 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 06:02:35.783239 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 06:02:35.789854 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 06:02:35.793395 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 06:02:35.796645 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 06:02:35.800106 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 06:02:35.806098 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 06:02:35.810073 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 06:02:35.813021 0 9 8 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (1 1)
813 06:02:35.819527 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
814 06:02:35.822609 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 06:02:35.826201 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 06:02:35.832737 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 06:02:35.836273 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 06:02:35.839816 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 06:02:35.846232 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
820 06:02:35.849922 0 10 8 | B1->B0 | 3131 2525 | 0 0 | (1 0) (0 0)
821 06:02:35.853370 0 10 12 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
822 06:02:35.860218 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 06:02:35.862952 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 06:02:35.866322 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 06:02:35.873194 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 06:02:35.876608 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 06:02:35.880121 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
828 06:02:35.882949 0 11 8 | B1->B0 | 2c2c 4343 | 1 0 | (1 1) (0 0)
829 06:02:35.889995 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
830 06:02:35.893371 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 06:02:35.896679 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 06:02:35.903114 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 06:02:35.906589 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 06:02:35.910055 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 06:02:35.916283 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 06:02:35.919679 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 06:02:35.923096 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 06:02:35.929465 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 06:02:35.933440 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 06:02:35.936477 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 06:02:35.943291 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 06:02:35.946591 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 06:02:35.949494 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 06:02:35.956574 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 06:02:35.959990 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 06:02:35.963181 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 06:02:35.970032 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 06:02:35.973197 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 06:02:35.976476 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 06:02:35.980037 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 06:02:35.986169 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 06:02:35.989821 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 06:02:35.993284 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 06:02:35.996181 Total UI for P1: 0, mck2ui 16
855 06:02:35.999650 best dqsien dly found for B0: ( 0, 14, 6)
856 06:02:36.006701 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 06:02:36.006786 Total UI for P1: 0, mck2ui 16
858 06:02:36.010059 best dqsien dly found for B1: ( 0, 14, 12)
859 06:02:36.013774 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
860 06:02:36.020407 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
861 06:02:36.020493
862 06:02:36.024038 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 06:02:36.027509 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
864 06:02:36.030874 [Gating] SW calibration Done
865 06:02:36.030981 ==
866 06:02:36.034325 Dram Type= 6, Freq= 0, CH_0, rank 0
867 06:02:36.037805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 06:02:36.037889 ==
869 06:02:36.037956 RX Vref Scan: 0
870 06:02:36.038017
871 06:02:36.040485 RX Vref 0 -> 0, step: 1
872 06:02:36.040568
873 06:02:36.043849 RX Delay -130 -> 252, step: 16
874 06:02:36.047293 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 06:02:36.050727 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
876 06:02:36.057692 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 06:02:36.061052 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 06:02:36.064425 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
879 06:02:36.067854 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
880 06:02:36.071001 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
881 06:02:36.074398 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
882 06:02:36.081107 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
883 06:02:36.084277 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
884 06:02:36.087658 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
885 06:02:36.091209 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
886 06:02:36.094018 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
887 06:02:36.101051 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
888 06:02:36.104564 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
889 06:02:36.107395 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 06:02:36.107479 ==
891 06:02:36.110879 Dram Type= 6, Freq= 0, CH_0, rank 0
892 06:02:36.114354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 06:02:36.117982 ==
894 06:02:36.118066 DQS Delay:
895 06:02:36.118133 DQS0 = 0, DQS1 = 0
896 06:02:36.121237 DQM Delay:
897 06:02:36.121322 DQM0 = 89, DQM1 = 82
898 06:02:36.121389 DQ Delay:
899 06:02:36.124540 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
900 06:02:36.127827 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
901 06:02:36.131201 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
902 06:02:36.134608 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
903 06:02:36.134692
904 06:02:36.137463
905 06:02:36.137553 ==
906 06:02:36.140917 Dram Type= 6, Freq= 0, CH_0, rank 0
907 06:02:36.144180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 06:02:36.144267 ==
909 06:02:36.144427
910 06:02:36.144524
911 06:02:36.147556 TX Vref Scan disable
912 06:02:36.147661 == TX Byte 0 ==
913 06:02:36.150950 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
914 06:02:36.158078 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
915 06:02:36.158178 == TX Byte 1 ==
916 06:02:36.161514 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
917 06:02:36.168255 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
918 06:02:36.168385 ==
919 06:02:36.171446 Dram Type= 6, Freq= 0, CH_0, rank 0
920 06:02:36.174573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 06:02:36.174657 ==
922 06:02:36.188830 TX Vref=22, minBit 8, minWin=27, winSum=446
923 06:02:36.191586 TX Vref=24, minBit 8, minWin=27, winSum=452
924 06:02:36.195304 TX Vref=26, minBit 8, minWin=27, winSum=450
925 06:02:36.198223 TX Vref=28, minBit 0, minWin=28, winSum=457
926 06:02:36.201631 TX Vref=30, minBit 8, minWin=28, winSum=458
927 06:02:36.205173 TX Vref=32, minBit 5, minWin=28, winSum=456
928 06:02:36.212226 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
929 06:02:36.212355
930 06:02:36.215042 Final TX Range 1 Vref 30
931 06:02:36.215130
932 06:02:36.215198 ==
933 06:02:36.218596 Dram Type= 6, Freq= 0, CH_0, rank 0
934 06:02:36.222180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 06:02:36.222264 ==
936 06:02:36.222331
937 06:02:36.222392
938 06:02:36.225674 TX Vref Scan disable
939 06:02:36.228468 == TX Byte 0 ==
940 06:02:36.231897 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
941 06:02:36.235879 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
942 06:02:36.239110 == TX Byte 1 ==
943 06:02:36.241976 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
944 06:02:36.245352 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
945 06:02:36.245435
946 06:02:36.248840 [DATLAT]
947 06:02:36.248923 Freq=800, CH0 RK0
948 06:02:36.248989
949 06:02:36.252337 DATLAT Default: 0xa
950 06:02:36.252419 0, 0xFFFF, sum = 0
951 06:02:36.255654 1, 0xFFFF, sum = 0
952 06:02:36.255738 2, 0xFFFF, sum = 0
953 06:02:36.259065 3, 0xFFFF, sum = 0
954 06:02:36.259148 4, 0xFFFF, sum = 0
955 06:02:36.262570 5, 0xFFFF, sum = 0
956 06:02:36.262654 6, 0xFFFF, sum = 0
957 06:02:36.265368 7, 0xFFFF, sum = 0
958 06:02:36.265451 8, 0xFFFF, sum = 0
959 06:02:36.268915 9, 0x0, sum = 1
960 06:02:36.268998 10, 0x0, sum = 2
961 06:02:36.272550 11, 0x0, sum = 3
962 06:02:36.272634 12, 0x0, sum = 4
963 06:02:36.275346 best_step = 10
964 06:02:36.275428
965 06:02:36.275493 ==
966 06:02:36.278850 Dram Type= 6, Freq= 0, CH_0, rank 0
967 06:02:36.282325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 06:02:36.282408 ==
969 06:02:36.285808 RX Vref Scan: 1
970 06:02:36.285891
971 06:02:36.285955 Set Vref Range= 32 -> 127
972 06:02:36.286016
973 06:02:36.288661 RX Vref 32 -> 127, step: 1
974 06:02:36.288743
975 06:02:36.292357 RX Delay -79 -> 252, step: 8
976 06:02:36.292440
977 06:02:36.295381 Set Vref, RX VrefLevel [Byte0]: 32
978 06:02:36.298567 [Byte1]: 32
979 06:02:36.298651
980 06:02:36.301802 Set Vref, RX VrefLevel [Byte0]: 33
981 06:02:36.305606 [Byte1]: 33
982 06:02:36.308606
983 06:02:36.308689 Set Vref, RX VrefLevel [Byte0]: 34
984 06:02:36.312259 [Byte1]: 34
985 06:02:36.316414
986 06:02:36.316530 Set Vref, RX VrefLevel [Byte0]: 35
987 06:02:36.319670 [Byte1]: 35
988 06:02:36.323984
989 06:02:36.324067 Set Vref, RX VrefLevel [Byte0]: 36
990 06:02:36.327374 [Byte1]: 36
991 06:02:36.332422
992 06:02:36.332506 Set Vref, RX VrefLevel [Byte0]: 37
993 06:02:36.335193 [Byte1]: 37
994 06:02:36.339393
995 06:02:36.339475 Set Vref, RX VrefLevel [Byte0]: 38
996 06:02:36.342740 [Byte1]: 38
997 06:02:36.346635
998 06:02:36.346718 Set Vref, RX VrefLevel [Byte0]: 39
999 06:02:36.349721 [Byte1]: 39
1000 06:02:36.354049
1001 06:02:36.354132 Set Vref, RX VrefLevel [Byte0]: 40
1002 06:02:36.357544 [Byte1]: 40
1003 06:02:36.361514
1004 06:02:36.361609 Set Vref, RX VrefLevel [Byte0]: 41
1005 06:02:36.365015 [Byte1]: 41
1006 06:02:36.369077
1007 06:02:36.369159 Set Vref, RX VrefLevel [Byte0]: 42
1008 06:02:36.372594 [Byte1]: 42
1009 06:02:36.376748
1010 06:02:36.376829 Set Vref, RX VrefLevel [Byte0]: 43
1011 06:02:36.380207 [Byte1]: 43
1012 06:02:36.384532
1013 06:02:36.384614 Set Vref, RX VrefLevel [Byte0]: 44
1014 06:02:36.387318 [Byte1]: 44
1015 06:02:36.391694
1016 06:02:36.391776 Set Vref, RX VrefLevel [Byte0]: 45
1017 06:02:36.395328 [Byte1]: 45
1018 06:02:36.399421
1019 06:02:36.399503 Set Vref, RX VrefLevel [Byte0]: 46
1020 06:02:36.402582 [Byte1]: 46
1021 06:02:36.406661
1022 06:02:36.406743 Set Vref, RX VrefLevel [Byte0]: 47
1023 06:02:36.410157 [Byte1]: 47
1024 06:02:36.414172
1025 06:02:36.414266 Set Vref, RX VrefLevel [Byte0]: 48
1026 06:02:36.417584 [Byte1]: 48
1027 06:02:36.421577
1028 06:02:36.421658 Set Vref, RX VrefLevel [Byte0]: 49
1029 06:02:36.425314 [Byte1]: 49
1030 06:02:36.429649
1031 06:02:36.429735 Set Vref, RX VrefLevel [Byte0]: 50
1032 06:02:36.432930 [Byte1]: 50
1033 06:02:36.436925
1034 06:02:36.437006 Set Vref, RX VrefLevel [Byte0]: 51
1035 06:02:36.440433 [Byte1]: 51
1036 06:02:36.444635
1037 06:02:36.444715 Set Vref, RX VrefLevel [Byte0]: 52
1038 06:02:36.447442 [Byte1]: 52
1039 06:02:36.452275
1040 06:02:36.452390 Set Vref, RX VrefLevel [Byte0]: 53
1041 06:02:36.455570 [Byte1]: 53
1042 06:02:36.459510
1043 06:02:36.459590 Set Vref, RX VrefLevel [Byte0]: 54
1044 06:02:36.462987 [Byte1]: 54
1045 06:02:36.466981
1046 06:02:36.467094 Set Vref, RX VrefLevel [Byte0]: 55
1047 06:02:36.470301 [Byte1]: 55
1048 06:02:36.474707
1049 06:02:36.474788 Set Vref, RX VrefLevel [Byte0]: 56
1050 06:02:36.478138 [Byte1]: 56
1051 06:02:36.482307
1052 06:02:36.482388 Set Vref, RX VrefLevel [Byte0]: 57
1053 06:02:36.485695 [Byte1]: 57
1054 06:02:36.489882
1055 06:02:36.489969 Set Vref, RX VrefLevel [Byte0]: 58
1056 06:02:36.493410 [Byte1]: 58
1057 06:02:36.497636
1058 06:02:36.497716 Set Vref, RX VrefLevel [Byte0]: 59
1059 06:02:36.500500 [Byte1]: 59
1060 06:02:36.504682
1061 06:02:36.504763 Set Vref, RX VrefLevel [Byte0]: 60
1062 06:02:36.508150 [Byte1]: 60
1063 06:02:36.512738
1064 06:02:36.512821 Set Vref, RX VrefLevel [Byte0]: 61
1065 06:02:36.515938 [Byte1]: 61
1066 06:02:36.520078
1067 06:02:36.520158 Set Vref, RX VrefLevel [Byte0]: 62
1068 06:02:36.523073 [Byte1]: 62
1069 06:02:36.527917
1070 06:02:36.528023 Set Vref, RX VrefLevel [Byte0]: 63
1071 06:02:36.530637 [Byte1]: 63
1072 06:02:36.534822
1073 06:02:36.534903 Set Vref, RX VrefLevel [Byte0]: 64
1074 06:02:36.538590 [Byte1]: 64
1075 06:02:36.542221
1076 06:02:36.545821 Set Vref, RX VrefLevel [Byte0]: 65
1077 06:02:36.548984 [Byte1]: 65
1078 06:02:36.549066
1079 06:02:36.552451 Set Vref, RX VrefLevel [Byte0]: 66
1080 06:02:36.556034 [Byte1]: 66
1081 06:02:36.556116
1082 06:02:36.558832 Set Vref, RX VrefLevel [Byte0]: 67
1083 06:02:36.562680 [Byte1]: 67
1084 06:02:36.562762
1085 06:02:36.565902 Set Vref, RX VrefLevel [Byte0]: 68
1086 06:02:36.569222 [Byte1]: 68
1087 06:02:36.572557
1088 06:02:36.572639 Set Vref, RX VrefLevel [Byte0]: 69
1089 06:02:36.576122 [Byte1]: 69
1090 06:02:36.580413
1091 06:02:36.580500 Set Vref, RX VrefLevel [Byte0]: 70
1092 06:02:36.583732 [Byte1]: 70
1093 06:02:36.587801
1094 06:02:36.587882 Set Vref, RX VrefLevel [Byte0]: 71
1095 06:02:36.591344 [Byte1]: 71
1096 06:02:36.595500
1097 06:02:36.595580 Set Vref, RX VrefLevel [Byte0]: 72
1098 06:02:36.599114 [Byte1]: 72
1099 06:02:36.603397
1100 06:02:36.603478 Set Vref, RX VrefLevel [Byte0]: 73
1101 06:02:36.606124 [Byte1]: 73
1102 06:02:36.610299
1103 06:02:36.610430 Set Vref, RX VrefLevel [Byte0]: 74
1104 06:02:36.613927 [Byte1]: 74
1105 06:02:36.618022
1106 06:02:36.618107 Set Vref, RX VrefLevel [Byte0]: 75
1107 06:02:36.621391 [Byte1]: 75
1108 06:02:36.625876
1109 06:02:36.625963 Set Vref, RX VrefLevel [Byte0]: 76
1110 06:02:36.629190 [Byte1]: 76
1111 06:02:36.633303
1112 06:02:36.633384 Set Vref, RX VrefLevel [Byte0]: 77
1113 06:02:36.636242 [Byte1]: 77
1114 06:02:36.640724
1115 06:02:36.640888 Set Vref, RX VrefLevel [Byte0]: 78
1116 06:02:36.644459 [Byte1]: 78
1117 06:02:36.648521
1118 06:02:36.648601 Final RX Vref Byte 0 = 49 to rank0
1119 06:02:36.651672 Final RX Vref Byte 1 = 59 to rank0
1120 06:02:36.655002 Final RX Vref Byte 0 = 49 to rank1
1121 06:02:36.658185 Final RX Vref Byte 1 = 59 to rank1==
1122 06:02:36.661840 Dram Type= 6, Freq= 0, CH_0, rank 0
1123 06:02:36.668553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1124 06:02:36.668635 ==
1125 06:02:36.668700 DQS Delay:
1126 06:02:36.668759 DQS0 = 0, DQS1 = 0
1127 06:02:36.671762 DQM Delay:
1128 06:02:36.671876 DQM0 = 91, DQM1 = 85
1129 06:02:36.675178 DQ Delay:
1130 06:02:36.678688 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1131 06:02:36.681469 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1132 06:02:36.684889 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80
1133 06:02:36.688228 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1134 06:02:36.688338
1135 06:02:36.688431
1136 06:02:36.694907 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1137 06:02:36.698372 CH0 RK0: MR19=606, MR18=4B42
1138 06:02:36.704975 CH0_RK0: MR19=0x606, MR18=0x4B42, DQSOSC=391, MR23=63, INC=96, DEC=64
1139 06:02:36.705095
1140 06:02:36.708666 ----->DramcWriteLeveling(PI) begin...
1141 06:02:36.708749 ==
1142 06:02:36.711521 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 06:02:36.715059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 06:02:36.715145 ==
1145 06:02:36.717966 Write leveling (Byte 0): 34 => 34
1146 06:02:36.721568 Write leveling (Byte 1): 30 => 30
1147 06:02:36.725208 DramcWriteLeveling(PI) end<-----
1148 06:02:36.725294
1149 06:02:36.725429 ==
1150 06:02:36.728084 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 06:02:36.772641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 06:02:36.772795 ==
1153 06:02:36.772890 [Gating] SW mode calibration
1154 06:02:36.773177 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1155 06:02:36.773245 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1156 06:02:36.773306 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 06:02:36.773365 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1158 06:02:36.773421 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1159 06:02:36.773781 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1160 06:02:36.774046 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 06:02:36.774118 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 06:02:36.795037 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 06:02:36.795140 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 06:02:36.795403 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 06:02:36.795659 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 06:02:36.795736 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 06:02:36.799060 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 06:02:36.805671 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 06:02:36.808990 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 06:02:36.812466 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 06:02:36.818958 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 06:02:36.821831 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 06:02:36.825584 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1174 06:02:36.832498 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1175 06:02:36.835932 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 06:02:36.838820 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 06:02:36.845499 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 06:02:36.848884 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 06:02:36.852153 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 06:02:36.858950 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 06:02:36.862283 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 06:02:36.865956 0 9 8 | B1->B0 | 3232 2b2b | 0 0 | (0 0) (0 0)
1183 06:02:36.868785 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 06:02:36.875863 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 06:02:36.878688 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 06:02:36.882204 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 06:02:36.888701 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 06:02:36.891921 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 06:02:36.895671 0 10 4 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
1190 06:02:36.902670 0 10 8 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (0 0)
1191 06:02:36.906358 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 06:02:36.909931 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 06:02:36.914390 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 06:02:36.917492 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 06:02:36.924572 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 06:02:36.928153 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 06:02:36.930965 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1198 06:02:36.937972 0 11 8 | B1->B0 | 4242 3c3c | 1 1 | (0 0) (1 1)
1199 06:02:36.941447 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 06:02:36.945064 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 06:02:36.948424 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 06:02:36.954547 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 06:02:36.957945 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 06:02:36.961152 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 06:02:36.967966 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1206 06:02:36.971385 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1207 06:02:36.974949 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 06:02:36.981277 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 06:02:36.984670 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 06:02:36.988053 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 06:02:36.995285 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 06:02:36.998002 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 06:02:37.001497 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 06:02:37.004927 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 06:02:37.011484 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 06:02:37.014902 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 06:02:37.018105 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 06:02:37.025061 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 06:02:37.028480 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 06:02:37.031801 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 06:02:37.038099 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 06:02:37.041796 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1223 06:02:37.045074 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 06:02:37.048605 Total UI for P1: 0, mck2ui 16
1225 06:02:37.051310 best dqsien dly found for B0: ( 0, 14, 8)
1226 06:02:37.054865 Total UI for P1: 0, mck2ui 16
1227 06:02:37.058334 best dqsien dly found for B1: ( 0, 14, 8)
1228 06:02:37.061805 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1229 06:02:37.065067 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1230 06:02:37.065145
1231 06:02:37.071883 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 06:02:37.075172 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1233 06:02:37.075251 [Gating] SW calibration Done
1234 06:02:37.078666 ==
1235 06:02:37.078744 Dram Type= 6, Freq= 0, CH_0, rank 1
1236 06:02:37.085222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1237 06:02:37.085337 ==
1238 06:02:37.085427 RX Vref Scan: 0
1239 06:02:37.085502
1240 06:02:37.088458 RX Vref 0 -> 0, step: 1
1241 06:02:37.088531
1242 06:02:37.091923 RX Delay -130 -> 252, step: 16
1243 06:02:37.094810 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1244 06:02:37.098343 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1245 06:02:37.101861 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1246 06:02:37.108114 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1247 06:02:37.111551 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1248 06:02:37.114853 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1249 06:02:37.118173 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1250 06:02:37.121788 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1251 06:02:37.128599 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1252 06:02:37.131806 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1253 06:02:37.134940 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1254 06:02:37.138838 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1255 06:02:37.141774 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1256 06:02:37.148488 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1257 06:02:37.151596 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1258 06:02:37.155266 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1259 06:02:37.155370 ==
1260 06:02:37.158655 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 06:02:37.161518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1262 06:02:37.161594 ==
1263 06:02:37.164983 DQS Delay:
1264 06:02:37.165064 DQS0 = 0, DQS1 = 0
1265 06:02:37.168234 DQM Delay:
1266 06:02:37.168336 DQM0 = 88, DQM1 = 82
1267 06:02:37.168401 DQ Delay:
1268 06:02:37.171727 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1269 06:02:37.175053 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1270 06:02:37.178480 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1271 06:02:37.182073 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1272 06:02:37.182156
1273 06:02:37.182226
1274 06:02:37.182289 ==
1275 06:02:37.185436 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 06:02:37.191600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 06:02:37.191685 ==
1278 06:02:37.191750
1279 06:02:37.191810
1280 06:02:37.191867 TX Vref Scan disable
1281 06:02:37.195819 == TX Byte 0 ==
1282 06:02:37.199286 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1283 06:02:37.205561 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1284 06:02:37.205643 == TX Byte 1 ==
1285 06:02:37.209119 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1286 06:02:37.215455 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1287 06:02:37.215558 ==
1288 06:02:37.218911 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 06:02:37.222325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 06:02:37.222411 ==
1291 06:02:37.234930 TX Vref=22, minBit 8, minWin=27, winSum=447
1292 06:02:37.238249 TX Vref=24, minBit 1, minWin=28, winSum=449
1293 06:02:37.241649 TX Vref=26, minBit 1, minWin=28, winSum=456
1294 06:02:37.245062 TX Vref=28, minBit 1, minWin=28, winSum=455
1295 06:02:37.248670 TX Vref=30, minBit 8, minWin=27, winSum=453
1296 06:02:37.255318 TX Vref=32, minBit 10, minWin=27, winSum=449
1297 06:02:37.258751 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 26
1298 06:02:37.258834
1299 06:02:37.262219 Final TX Range 1 Vref 26
1300 06:02:37.262302
1301 06:02:37.262366 ==
1302 06:02:37.265480 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 06:02:37.268899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 06:02:37.268980 ==
1305 06:02:37.269044
1306 06:02:37.269103
1307 06:02:37.271929 TX Vref Scan disable
1308 06:02:37.275632 == TX Byte 0 ==
1309 06:02:37.278836 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1310 06:02:37.282005 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1311 06:02:37.285180 == TX Byte 1 ==
1312 06:02:37.288570 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1313 06:02:37.291979 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1314 06:02:37.292065
1315 06:02:37.295358 [DATLAT]
1316 06:02:37.295438 Freq=800, CH0 RK1
1317 06:02:37.295502
1318 06:02:37.298848 DATLAT Default: 0xa
1319 06:02:37.298929 0, 0xFFFF, sum = 0
1320 06:02:37.302190 1, 0xFFFF, sum = 0
1321 06:02:37.302298 2, 0xFFFF, sum = 0
1322 06:02:37.305700 3, 0xFFFF, sum = 0
1323 06:02:37.305782 4, 0xFFFF, sum = 0
1324 06:02:37.309195 5, 0xFFFF, sum = 0
1325 06:02:37.309277 6, 0xFFFF, sum = 0
1326 06:02:37.312136 7, 0xFFFF, sum = 0
1327 06:02:37.312250 8, 0xFFFF, sum = 0
1328 06:02:37.315592 9, 0x0, sum = 1
1329 06:02:37.315673 10, 0x0, sum = 2
1330 06:02:37.319195 11, 0x0, sum = 3
1331 06:02:37.319277 12, 0x0, sum = 4
1332 06:02:37.322093 best_step = 10
1333 06:02:37.322174
1334 06:02:37.322245 ==
1335 06:02:37.325567 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 06:02:37.328970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 06:02:37.329051 ==
1338 06:02:37.332762 RX Vref Scan: 0
1339 06:02:37.332842
1340 06:02:37.332906 RX Vref 0 -> 0, step: 1
1341 06:02:37.332965
1342 06:02:37.335524 RX Delay -95 -> 252, step: 8
1343 06:02:37.342301 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1344 06:02:37.345777 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1345 06:02:37.349379 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1346 06:02:37.352807 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1347 06:02:37.355579 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1348 06:02:37.359328 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1349 06:02:37.365914 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1350 06:02:37.369348 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1351 06:02:37.372870 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1352 06:02:37.375700 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1353 06:02:37.379259 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1354 06:02:37.385794 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1355 06:02:37.388913 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1356 06:02:37.392515 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1357 06:02:37.395632 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1358 06:02:37.399319 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1359 06:02:37.402398 ==
1360 06:02:37.406051 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 06:02:37.409381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 06:02:37.409457 ==
1363 06:02:37.409520 DQS Delay:
1364 06:02:37.412669 DQS0 = 0, DQS1 = 0
1365 06:02:37.412750 DQM Delay:
1366 06:02:37.416066 DQM0 = 92, DQM1 = 82
1367 06:02:37.416139 DQ Delay:
1368 06:02:37.419004 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1369 06:02:37.422568 DQ4 =96, DQ5 =84, DQ6 =96, DQ7 =100
1370 06:02:37.426087 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1371 06:02:37.428787 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1372 06:02:37.428892
1373 06:02:37.428979
1374 06:02:37.436131 [DQSOSCAuto] RK1, (LSB)MR18= 0x4011, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1375 06:02:37.439280 CH0 RK1: MR19=606, MR18=4011
1376 06:02:37.446080 CH0_RK1: MR19=0x606, MR18=0x4011, DQSOSC=393, MR23=63, INC=95, DEC=63
1377 06:02:37.449551 [RxdqsGatingPostProcess] freq 800
1378 06:02:37.452246 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1379 06:02:37.455822 Pre-setting of DQS Precalculation
1380 06:02:37.462682 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1381 06:02:37.462763 ==
1382 06:02:37.465962 Dram Type= 6, Freq= 0, CH_1, rank 0
1383 06:02:37.469265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1384 06:02:37.469373 ==
1385 06:02:37.475911 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1386 06:02:37.482382 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1387 06:02:37.490160 [CA 0] Center 36 (6~67) winsize 62
1388 06:02:37.493622 [CA 1] Center 37 (6~68) winsize 63
1389 06:02:37.496936 [CA 2] Center 35 (5~66) winsize 62
1390 06:02:37.500220 [CA 3] Center 34 (4~65) winsize 62
1391 06:02:37.503371 [CA 4] Center 35 (5~65) winsize 61
1392 06:02:37.506813 [CA 5] Center 34 (4~65) winsize 62
1393 06:02:37.506895
1394 06:02:37.510156 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1395 06:02:37.510237
1396 06:02:37.513278 [CATrainingPosCal] consider 1 rank data
1397 06:02:37.517003 u2DelayCellTimex100 = 270/100 ps
1398 06:02:37.520249 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 06:02:37.523593 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1400 06:02:37.529918 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1401 06:02:37.533443 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 06:02:37.536951 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1403 06:02:37.540514 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1404 06:02:37.540597
1405 06:02:37.543942 CA PerBit enable=1, Macro0, CA PI delay=34
1406 06:02:37.544024
1407 06:02:37.546688 [CBTSetCACLKResult] CA Dly = 34
1408 06:02:37.546770 CS Dly: 5 (0~36)
1409 06:02:37.546834 ==
1410 06:02:37.550060 Dram Type= 6, Freq= 0, CH_1, rank 1
1411 06:02:37.557062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 06:02:37.557145 ==
1413 06:02:37.560604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1414 06:02:37.567742 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1415 06:02:37.576854 [CA 0] Center 36 (6~67) winsize 62
1416 06:02:37.580412 [CA 1] Center 37 (6~68) winsize 63
1417 06:02:37.583813 [CA 2] Center 35 (5~66) winsize 62
1418 06:02:37.587744 [CA 3] Center 35 (4~66) winsize 63
1419 06:02:37.591140 [CA 4] Center 35 (5~66) winsize 62
1420 06:02:37.594654 [CA 5] Center 34 (4~65) winsize 62
1421 06:02:37.594737
1422 06:02:37.598035 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1423 06:02:37.598118
1424 06:02:37.601523 [CATrainingPosCal] consider 2 rank data
1425 06:02:37.604834 u2DelayCellTimex100 = 270/100 ps
1426 06:02:37.608220 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 06:02:37.611514 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1428 06:02:37.614802 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1429 06:02:37.618356 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 06:02:37.621716 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1431 06:02:37.624914 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1432 06:02:37.624995
1433 06:02:37.628088 CA PerBit enable=1, Macro0, CA PI delay=34
1434 06:02:37.628170
1435 06:02:37.631595 [CBTSetCACLKResult] CA Dly = 34
1436 06:02:37.635019 CS Dly: 6 (0~38)
1437 06:02:37.635100
1438 06:02:37.638321 ----->DramcWriteLeveling(PI) begin...
1439 06:02:37.638404 ==
1440 06:02:37.641979 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 06:02:37.644850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 06:02:37.644959 ==
1443 06:02:37.648426 Write leveling (Byte 0): 26 => 26
1444 06:02:37.651281 Write leveling (Byte 1): 27 => 27
1445 06:02:37.654691 DramcWriteLeveling(PI) end<-----
1446 06:02:37.654774
1447 06:02:37.654838 ==
1448 06:02:37.658065 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 06:02:37.661850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 06:02:37.661933 ==
1451 06:02:37.665403 [Gating] SW mode calibration
1452 06:02:37.671872 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1453 06:02:37.678771 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1454 06:02:37.681504 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1455 06:02:37.685030 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 06:02:37.692037 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 06:02:37.695289 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 06:02:37.698333 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 06:02:37.705003 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 06:02:37.708553 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 06:02:37.711905 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 06:02:37.718172 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 06:02:37.722081 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 06:02:37.725398 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 06:02:37.732041 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 06:02:37.735377 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 06:02:37.738769 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 06:02:37.745411 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 06:02:37.748862 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 06:02:37.752222 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1471 06:02:37.755003 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1472 06:02:37.762022 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 06:02:37.765400 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 06:02:37.768794 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 06:02:37.775047 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 06:02:37.778664 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 06:02:37.782052 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 06:02:37.788379 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 06:02:37.791812 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1480 06:02:37.795434 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1481 06:02:37.801577 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 06:02:37.804941 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 06:02:37.808915 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 06:02:37.815500 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 06:02:37.818760 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 06:02:37.822131 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1487 06:02:37.828796 0 10 4 | B1->B0 | 3030 2d2d | 1 0 | (1 0) (0 0)
1488 06:02:37.832031 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)
1489 06:02:37.835252 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 06:02:37.838532 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 06:02:37.845271 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 06:02:37.848748 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 06:02:37.851973 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 06:02:37.858839 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 06:02:37.862206 0 11 4 | B1->B0 | 2c2c 3838 | 1 0 | (0 0) (0 0)
1496 06:02:37.865832 0 11 8 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
1497 06:02:37.872055 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 06:02:37.875469 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 06:02:37.878697 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 06:02:37.885706 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 06:02:37.889066 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 06:02:37.892480 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 06:02:37.898946 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1504 06:02:37.902460 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 06:02:37.905856 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 06:02:37.909282 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 06:02:37.915597 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 06:02:37.918791 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 06:02:37.922262 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 06:02:37.928833 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 06:02:37.932118 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 06:02:37.935623 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 06:02:37.942224 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 06:02:37.945823 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 06:02:37.949102 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 06:02:37.955956 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 06:02:37.959248 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 06:02:37.962669 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1519 06:02:37.968953 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1520 06:02:37.972483 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 06:02:37.975928 Total UI for P1: 0, mck2ui 16
1522 06:02:37.979404 best dqsien dly found for B0: ( 0, 14, 4)
1523 06:02:37.982867 Total UI for P1: 0, mck2ui 16
1524 06:02:37.985502 best dqsien dly found for B1: ( 0, 14, 2)
1525 06:02:37.989078 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1526 06:02:37.992629 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1527 06:02:37.992709
1528 06:02:37.996166 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1529 06:02:37.998896 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1530 06:02:38.002352 [Gating] SW calibration Done
1531 06:02:38.002435 ==
1532 06:02:38.005888 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 06:02:38.009353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 06:02:38.009435 ==
1535 06:02:38.012759 RX Vref Scan: 0
1536 06:02:38.012896
1537 06:02:38.012979 RX Vref 0 -> 0, step: 1
1538 06:02:38.015685
1539 06:02:38.015765 RX Delay -130 -> 252, step: 16
1540 06:02:38.022800 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1541 06:02:38.026181 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1542 06:02:38.029025 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1543 06:02:38.032678 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1544 06:02:38.036099 iDelay=222, Bit 4, Center 101 (-2 ~ 205) 208
1545 06:02:38.038793 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1546 06:02:38.046174 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1547 06:02:38.048986 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1548 06:02:38.052795 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1549 06:02:38.056091 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1550 06:02:38.058797 iDelay=222, Bit 10, Center 93 (-2 ~ 189) 192
1551 06:02:38.066039 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1552 06:02:38.069370 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1553 06:02:38.072539 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1554 06:02:38.075921 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1555 06:02:38.082530 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1556 06:02:38.082614 ==
1557 06:02:38.085977 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 06:02:38.089496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 06:02:38.089580 ==
1560 06:02:38.089646 DQS Delay:
1561 06:02:38.092143 DQS0 = 0, DQS1 = 0
1562 06:02:38.092232 DQM Delay:
1563 06:02:38.095748 DQM0 = 95, DQM1 = 91
1564 06:02:38.095829 DQ Delay:
1565 06:02:38.099140 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1566 06:02:38.102748 DQ4 =101, DQ5 =109, DQ6 =101, DQ7 =93
1567 06:02:38.105816 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1568 06:02:38.109444 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1569 06:02:38.109527
1570 06:02:38.109592
1571 06:02:38.109651 ==
1572 06:02:38.112861 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 06:02:38.116467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 06:02:38.116550 ==
1575 06:02:38.119228
1576 06:02:38.119310
1577 06:02:38.119374 TX Vref Scan disable
1578 06:02:38.122797 == TX Byte 0 ==
1579 06:02:38.126317 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1580 06:02:38.129205 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1581 06:02:38.132675 == TX Byte 1 ==
1582 06:02:38.136367 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1583 06:02:38.139153 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1584 06:02:38.139282 ==
1585 06:02:38.142897 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 06:02:38.146855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 06:02:38.147003 ==
1588 06:02:38.160878 TX Vref=22, minBit 1, minWin=26, winSum=435
1589 06:02:38.164567 TX Vref=24, minBit 0, minWin=27, winSum=443
1590 06:02:38.167708 TX Vref=26, minBit 3, minWin=26, winSum=442
1591 06:02:38.170836 TX Vref=28, minBit 1, minWin=27, winSum=447
1592 06:02:38.174209 TX Vref=30, minBit 1, minWin=27, winSum=447
1593 06:02:38.177454 TX Vref=32, minBit 2, minWin=26, winSum=444
1594 06:02:38.184088 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 28
1595 06:02:38.184229
1596 06:02:38.187763 Final TX Range 1 Vref 28
1597 06:02:38.187847
1598 06:02:38.187912 ==
1599 06:02:38.191156 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 06:02:38.193999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 06:02:38.194083 ==
1602 06:02:38.197301
1603 06:02:38.197383
1604 06:02:38.197448 TX Vref Scan disable
1605 06:02:38.200686 == TX Byte 0 ==
1606 06:02:38.204033 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1607 06:02:38.207545 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1608 06:02:38.211265 == TX Byte 1 ==
1609 06:02:38.214092 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1610 06:02:38.220972 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1611 06:02:38.221057
1612 06:02:38.221125 [DATLAT]
1613 06:02:38.221214 Freq=800, CH1 RK0
1614 06:02:38.221302
1615 06:02:38.223865 DATLAT Default: 0xa
1616 06:02:38.224026 0, 0xFFFF, sum = 0
1617 06:02:38.227523 1, 0xFFFF, sum = 0
1618 06:02:38.227607 2, 0xFFFF, sum = 0
1619 06:02:38.230984 3, 0xFFFF, sum = 0
1620 06:02:38.231068 4, 0xFFFF, sum = 0
1621 06:02:38.234553 5, 0xFFFF, sum = 0
1622 06:02:38.237870 6, 0xFFFF, sum = 0
1623 06:02:38.237954 7, 0xFFFF, sum = 0
1624 06:02:38.240741 8, 0xFFFF, sum = 0
1625 06:02:38.240824 9, 0x0, sum = 1
1626 06:02:38.240890 10, 0x0, sum = 2
1627 06:02:38.244568 11, 0x0, sum = 3
1628 06:02:38.244651 12, 0x0, sum = 4
1629 06:02:38.247372 best_step = 10
1630 06:02:38.247454
1631 06:02:38.247518 ==
1632 06:02:38.250816 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 06:02:38.254286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 06:02:38.254368 ==
1635 06:02:38.258005 RX Vref Scan: 1
1636 06:02:38.258087
1637 06:02:38.258152 Set Vref Range= 32 -> 127
1638 06:02:38.258212
1639 06:02:38.260743 RX Vref 32 -> 127, step: 1
1640 06:02:38.260825
1641 06:02:38.264172 RX Delay -79 -> 252, step: 8
1642 06:02:38.264255
1643 06:02:38.267488 Set Vref, RX VrefLevel [Byte0]: 32
1644 06:02:38.270624 [Byte1]: 32
1645 06:02:38.270706
1646 06:02:38.274561 Set Vref, RX VrefLevel [Byte0]: 33
1647 06:02:38.277825 [Byte1]: 33
1648 06:02:38.280967
1649 06:02:38.281047 Set Vref, RX VrefLevel [Byte0]: 34
1650 06:02:38.284713 [Byte1]: 34
1651 06:02:38.288674
1652 06:02:38.288755 Set Vref, RX VrefLevel [Byte0]: 35
1653 06:02:38.292079 [Byte1]: 35
1654 06:02:38.295841
1655 06:02:38.295923 Set Vref, RX VrefLevel [Byte0]: 36
1656 06:02:38.299777 [Byte1]: 36
1657 06:02:38.303823
1658 06:02:38.303905 Set Vref, RX VrefLevel [Byte0]: 37
1659 06:02:38.306992 [Byte1]: 37
1660 06:02:38.311315
1661 06:02:38.311396 Set Vref, RX VrefLevel [Byte0]: 38
1662 06:02:38.314401 [Byte1]: 38
1663 06:02:38.318908
1664 06:02:38.318990 Set Vref, RX VrefLevel [Byte0]: 39
1665 06:02:38.322349 [Byte1]: 39
1666 06:02:38.326538
1667 06:02:38.326619 Set Vref, RX VrefLevel [Byte0]: 40
1668 06:02:38.330140 [Byte1]: 40
1669 06:02:38.333896
1670 06:02:38.333979 Set Vref, RX VrefLevel [Byte0]: 41
1671 06:02:38.337586 [Byte1]: 41
1672 06:02:38.341709
1673 06:02:38.341795 Set Vref, RX VrefLevel [Byte0]: 42
1674 06:02:38.344523 [Byte1]: 42
1675 06:02:38.349531
1676 06:02:38.349613 Set Vref, RX VrefLevel [Byte0]: 43
1677 06:02:38.352242 [Byte1]: 43
1678 06:02:38.356554
1679 06:02:38.356635 Set Vref, RX VrefLevel [Byte0]: 44
1680 06:02:38.359938 [Byte1]: 44
1681 06:02:38.364222
1682 06:02:38.364343 Set Vref, RX VrefLevel [Byte0]: 45
1683 06:02:38.367827 [Byte1]: 45
1684 06:02:38.372112
1685 06:02:38.372196 Set Vref, RX VrefLevel [Byte0]: 46
1686 06:02:38.374872 [Byte1]: 46
1687 06:02:38.379571
1688 06:02:38.379652 Set Vref, RX VrefLevel [Byte0]: 47
1689 06:02:38.382737 [Byte1]: 47
1690 06:02:38.386884
1691 06:02:38.386965 Set Vref, RX VrefLevel [Byte0]: 48
1692 06:02:38.390472 [Byte1]: 48
1693 06:02:38.394687
1694 06:02:38.394768 Set Vref, RX VrefLevel [Byte0]: 49
1695 06:02:38.397966 [Byte1]: 49
1696 06:02:38.401997
1697 06:02:38.402077 Set Vref, RX VrefLevel [Byte0]: 50
1698 06:02:38.405046 [Byte1]: 50
1699 06:02:38.409708
1700 06:02:38.409792 Set Vref, RX VrefLevel [Byte0]: 51
1701 06:02:38.412639 [Byte1]: 51
1702 06:02:38.416932
1703 06:02:38.417015 Set Vref, RX VrefLevel [Byte0]: 52
1704 06:02:38.420539 [Byte1]: 52
1705 06:02:38.424734
1706 06:02:38.424815 Set Vref, RX VrefLevel [Byte0]: 53
1707 06:02:38.427829 [Byte1]: 53
1708 06:02:38.432558
1709 06:02:38.432640 Set Vref, RX VrefLevel [Byte0]: 54
1710 06:02:38.435662 [Byte1]: 54
1711 06:02:38.439434
1712 06:02:38.439516 Set Vref, RX VrefLevel [Byte0]: 55
1713 06:02:38.443192 [Byte1]: 55
1714 06:02:38.447168
1715 06:02:38.447249 Set Vref, RX VrefLevel [Byte0]: 56
1716 06:02:38.450703 [Byte1]: 56
1717 06:02:38.454799
1718 06:02:38.454880 Set Vref, RX VrefLevel [Byte0]: 57
1719 06:02:38.458288 [Byte1]: 57
1720 06:02:38.462405
1721 06:02:38.462486 Set Vref, RX VrefLevel [Byte0]: 58
1722 06:02:38.465261 [Byte1]: 58
1723 06:02:38.470170
1724 06:02:38.470252 Set Vref, RX VrefLevel [Byte0]: 59
1725 06:02:38.472953 [Byte1]: 59
1726 06:02:38.477227
1727 06:02:38.477307 Set Vref, RX VrefLevel [Byte0]: 60
1728 06:02:38.480689 [Byte1]: 60
1729 06:02:38.484843
1730 06:02:38.484924 Set Vref, RX VrefLevel [Byte0]: 61
1731 06:02:38.488224 [Byte1]: 61
1732 06:02:38.492533
1733 06:02:38.492613 Set Vref, RX VrefLevel [Byte0]: 62
1734 06:02:38.496182 [Byte1]: 62
1735 06:02:38.499732
1736 06:02:38.499813 Set Vref, RX VrefLevel [Byte0]: 63
1737 06:02:38.503453 [Byte1]: 63
1738 06:02:38.507710
1739 06:02:38.507791 Set Vref, RX VrefLevel [Byte0]: 64
1740 06:02:38.511161 [Byte1]: 64
1741 06:02:38.515291
1742 06:02:38.515372 Set Vref, RX VrefLevel [Byte0]: 65
1743 06:02:38.518670 [Byte1]: 65
1744 06:02:38.522653
1745 06:02:38.522734 Set Vref, RX VrefLevel [Byte0]: 66
1746 06:02:38.526120 [Byte1]: 66
1747 06:02:38.530404
1748 06:02:38.530485 Set Vref, RX VrefLevel [Byte0]: 67
1749 06:02:38.533852 [Byte1]: 67
1750 06:02:38.537911
1751 06:02:38.537992 Set Vref, RX VrefLevel [Byte0]: 68
1752 06:02:38.541193 [Byte1]: 68
1753 06:02:38.545050
1754 06:02:38.545131 Set Vref, RX VrefLevel [Byte0]: 69
1755 06:02:38.548870 [Byte1]: 69
1756 06:02:38.553043
1757 06:02:38.553123 Set Vref, RX VrefLevel [Byte0]: 70
1758 06:02:38.556036 [Byte1]: 70
1759 06:02:38.560152
1760 06:02:38.560233 Set Vref, RX VrefLevel [Byte0]: 71
1761 06:02:38.563639 [Byte1]: 71
1762 06:02:38.568203
1763 06:02:38.568352 Set Vref, RX VrefLevel [Byte0]: 72
1764 06:02:38.571361 [Byte1]: 72
1765 06:02:38.575377
1766 06:02:38.575460 Set Vref, RX VrefLevel [Byte0]: 73
1767 06:02:38.579004 [Byte1]: 73
1768 06:02:38.583096
1769 06:02:38.583201 Set Vref, RX VrefLevel [Byte0]: 74
1770 06:02:38.586664 [Byte1]: 74
1771 06:02:38.590844
1772 06:02:38.590925 Final RX Vref Byte 0 = 58 to rank0
1773 06:02:38.593726 Final RX Vref Byte 1 = 57 to rank0
1774 06:02:38.597180 Final RX Vref Byte 0 = 58 to rank1
1775 06:02:38.600788 Final RX Vref Byte 1 = 57 to rank1==
1776 06:02:38.603679 Dram Type= 6, Freq= 0, CH_1, rank 0
1777 06:02:38.610730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1778 06:02:38.610812 ==
1779 06:02:38.610877 DQS Delay:
1780 06:02:38.610936 DQS0 = 0, DQS1 = 0
1781 06:02:38.614079 DQM Delay:
1782 06:02:38.614161 DQM0 = 96, DQM1 = 89
1783 06:02:38.617477 DQ Delay:
1784 06:02:38.620216 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1785 06:02:38.623824 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
1786 06:02:38.627037 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1787 06:02:38.630280 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1788 06:02:38.630362
1789 06:02:38.630426
1790 06:02:38.637099 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1791 06:02:38.640559 CH1 RK0: MR19=606, MR18=2B48
1792 06:02:38.647488 CH1_RK0: MR19=0x606, MR18=0x2B48, DQSOSC=391, MR23=63, INC=96, DEC=64
1793 06:02:38.647571
1794 06:02:38.651087 ----->DramcWriteLeveling(PI) begin...
1795 06:02:38.651171 ==
1796 06:02:38.653805 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 06:02:38.657319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 06:02:38.657401 ==
1799 06:02:38.660614 Write leveling (Byte 0): 29 => 29
1800 06:02:38.664032 Write leveling (Byte 1): 29 => 29
1801 06:02:38.667501 DramcWriteLeveling(PI) end<-----
1802 06:02:38.667582
1803 06:02:38.667646 ==
1804 06:02:38.671010 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 06:02:38.674479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 06:02:38.674561 ==
1807 06:02:38.677686 [Gating] SW mode calibration
1808 06:02:38.684115 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1809 06:02:38.690710 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1810 06:02:38.694132 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1811 06:02:38.697186 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1812 06:02:38.703862 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 06:02:38.707326 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 06:02:38.710878 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 06:02:38.717861 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 06:02:38.720501 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 06:02:38.723914 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 06:02:38.731026 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 06:02:38.734299 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 06:02:38.737372 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 06:02:38.740602 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 06:02:38.747251 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 06:02:38.750600 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 06:02:38.754165 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 06:02:38.760945 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 06:02:38.764254 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1827 06:02:38.767639 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1828 06:02:38.773949 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 06:02:38.777401 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 06:02:38.780915 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 06:02:38.787817 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 06:02:38.790652 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 06:02:38.793998 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 06:02:38.800699 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 06:02:38.804099 0 9 4 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)
1836 06:02:38.807282 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1837 06:02:38.814112 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 06:02:38.817528 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 06:02:38.820954 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 06:02:38.824429 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 06:02:38.830755 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 06:02:38.834128 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1843 06:02:38.837577 0 10 4 | B1->B0 | 2a2a 3333 | 0 0 | (1 0) (0 1)
1844 06:02:38.844368 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 06:02:38.847631 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 06:02:38.851420 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 06:02:38.857843 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 06:02:38.861319 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 06:02:38.864875 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 06:02:38.871254 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1851 06:02:38.874742 0 11 4 | B1->B0 | 3b3b 2727 | 1 0 | (0 0) (0 0)
1852 06:02:38.878180 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1853 06:02:38.884240 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 06:02:38.887662 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 06:02:38.891199 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 06:02:38.894679 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 06:02:38.901747 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 06:02:38.904440 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 06:02:38.908063 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1860 06:02:38.915054 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 06:02:38.918365 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 06:02:38.921758 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 06:02:38.928167 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 06:02:38.931507 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 06:02:38.934936 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 06:02:38.941088 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 06:02:38.944651 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 06:02:38.948205 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 06:02:38.955089 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 06:02:38.957815 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 06:02:38.961129 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 06:02:38.968151 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 06:02:38.971544 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 06:02:38.975048 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 06:02:38.978277 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1876 06:02:38.984563 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 06:02:38.988006 Total UI for P1: 0, mck2ui 16
1878 06:02:38.991407 best dqsien dly found for B0: ( 0, 14, 6)
1879 06:02:38.994931 Total UI for P1: 0, mck2ui 16
1880 06:02:38.998367 best dqsien dly found for B1: ( 0, 14, 4)
1881 06:02:39.001789 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1882 06:02:39.004612 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1883 06:02:39.004694
1884 06:02:39.007865 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1885 06:02:39.011137 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1886 06:02:39.014551 [Gating] SW calibration Done
1887 06:02:39.014635 ==
1888 06:02:39.018252 Dram Type= 6, Freq= 0, CH_1, rank 1
1889 06:02:39.021701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1890 06:02:39.021781 ==
1891 06:02:39.024639 RX Vref Scan: 0
1892 06:02:39.024720
1893 06:02:39.024783 RX Vref 0 -> 0, step: 1
1894 06:02:39.024842
1895 06:02:39.028028 RX Delay -130 -> 252, step: 16
1896 06:02:39.031520 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1897 06:02:39.038057 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1898 06:02:39.041545 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1899 06:02:39.044864 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1900 06:02:39.048143 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1901 06:02:39.051154 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1902 06:02:39.057834 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1903 06:02:39.061239 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1904 06:02:39.064739 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1905 06:02:39.068055 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1906 06:02:39.071455 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1907 06:02:39.077990 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1908 06:02:39.081203 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1909 06:02:39.084607 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1910 06:02:39.088142 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1911 06:02:39.094453 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1912 06:02:39.094536 ==
1913 06:02:39.097934 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 06:02:39.101203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 06:02:39.101287 ==
1916 06:02:39.101351 DQS Delay:
1917 06:02:39.104698 DQS0 = 0, DQS1 = 0
1918 06:02:39.104780 DQM Delay:
1919 06:02:39.107543 DQM0 = 94, DQM1 = 91
1920 06:02:39.107624 DQ Delay:
1921 06:02:39.111002 DQ0 =101, DQ1 =93, DQ2 =85, DQ3 =85
1922 06:02:39.114393 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1923 06:02:39.117834 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1924 06:02:39.121321 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1925 06:02:39.121405
1926 06:02:39.121469
1927 06:02:39.121528 ==
1928 06:02:39.124198 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 06:02:39.127748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 06:02:39.127830 ==
1931 06:02:39.131303
1932 06:02:39.131384
1933 06:02:39.131448 TX Vref Scan disable
1934 06:02:39.134331 == TX Byte 0 ==
1935 06:02:39.137331 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1936 06:02:39.141014 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1937 06:02:39.144341 == TX Byte 1 ==
1938 06:02:39.147361 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1939 06:02:39.150861 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1940 06:02:39.150945 ==
1941 06:02:39.154381 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 06:02:39.161319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 06:02:39.161468 ==
1944 06:02:39.173143 TX Vref=22, minBit 0, minWin=27, winSum=444
1945 06:02:39.176068 TX Vref=24, minBit 2, minWin=27, winSum=449
1946 06:02:39.179508 TX Vref=26, minBit 2, minWin=27, winSum=450
1947 06:02:39.183203 TX Vref=28, minBit 2, minWin=27, winSum=451
1948 06:02:39.186138 TX Vref=30, minBit 2, minWin=27, winSum=452
1949 06:02:39.189843 TX Vref=32, minBit 2, minWin=27, winSum=451
1950 06:02:39.196524 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 30
1951 06:02:39.196616
1952 06:02:39.199365 Final TX Range 1 Vref 30
1953 06:02:39.199446
1954 06:02:39.199510 ==
1955 06:02:39.203085 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 06:02:39.205874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 06:02:39.205950 ==
1958 06:02:39.209570
1959 06:02:39.209649
1960 06:02:39.209725 TX Vref Scan disable
1961 06:02:39.212694 == TX Byte 0 ==
1962 06:02:39.216305 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1963 06:02:39.222581 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1964 06:02:39.222700 == TX Byte 1 ==
1965 06:02:39.226182 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1966 06:02:39.229077 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1967 06:02:39.232760
1968 06:02:39.232880 [DATLAT]
1969 06:02:39.232979 Freq=800, CH1 RK1
1970 06:02:39.233073
1971 06:02:39.235823 DATLAT Default: 0xa
1972 06:02:39.235935 0, 0xFFFF, sum = 0
1973 06:02:39.239436 1, 0xFFFF, sum = 0
1974 06:02:39.239552 2, 0xFFFF, sum = 0
1975 06:02:39.243046 3, 0xFFFF, sum = 0
1976 06:02:39.243130 4, 0xFFFF, sum = 0
1977 06:02:39.245877 5, 0xFFFF, sum = 0
1978 06:02:39.249416 6, 0xFFFF, sum = 0
1979 06:02:39.249536 7, 0xFFFF, sum = 0
1980 06:02:39.252986 8, 0xFFFF, sum = 0
1981 06:02:39.253098 9, 0x0, sum = 1
1982 06:02:39.253195 10, 0x0, sum = 2
1983 06:02:39.256244 11, 0x0, sum = 3
1984 06:02:39.256356 12, 0x0, sum = 4
1985 06:02:39.259474 best_step = 10
1986 06:02:39.259579
1987 06:02:39.259646 ==
1988 06:02:39.263007 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 06:02:39.266066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 06:02:39.266174 ==
1991 06:02:39.269415 RX Vref Scan: 0
1992 06:02:39.269534
1993 06:02:39.269630 RX Vref 0 -> 0, step: 1
1994 06:02:39.269720
1995 06:02:39.272855 RX Delay -63 -> 252, step: 8
1996 06:02:39.279262 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1997 06:02:39.282364 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1998 06:02:39.286171 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1999 06:02:39.288948 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2000 06:02:39.292575 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2001 06:02:39.298975 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2002 06:02:39.302404 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2003 06:02:39.305680 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2004 06:02:39.308970 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2005 06:02:39.312896 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2006 06:02:39.315859 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2007 06:02:39.322744 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2008 06:02:39.326107 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2009 06:02:39.329100 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2010 06:02:39.332764 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2011 06:02:39.335949 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
2012 06:02:39.339614 ==
2013 06:02:39.339715 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 06:02:39.345917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 06:02:39.346021 ==
2016 06:02:39.346113 DQS Delay:
2017 06:02:39.348967 DQS0 = 0, DQS1 = 0
2018 06:02:39.349066 DQM Delay:
2019 06:02:39.352569 DQM0 = 97, DQM1 = 91
2020 06:02:39.352675 DQ Delay:
2021 06:02:39.356022 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2022 06:02:39.359139 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2023 06:02:39.362563 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2024 06:02:39.365937 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2025 06:02:39.366037
2026 06:02:39.366128
2027 06:02:39.372695 [DQSOSCAuto] RK1, (LSB)MR18= 0x440d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2028 06:02:39.375817 CH1 RK1: MR19=606, MR18=440D
2029 06:02:39.382382 CH1_RK1: MR19=0x606, MR18=0x440D, DQSOSC=392, MR23=63, INC=96, DEC=64
2030 06:02:39.385821 [RxdqsGatingPostProcess] freq 800
2031 06:02:39.392321 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2032 06:02:39.392405 Pre-setting of DQS Precalculation
2033 06:02:39.399356 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2034 06:02:39.405903 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2035 06:02:39.412238 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2036 06:02:39.412361
2037 06:02:39.412457
2038 06:02:39.415579 [Calibration Summary] 1600 Mbps
2039 06:02:39.419502 CH 0, Rank 0
2040 06:02:39.419586 SW Impedance : PASS
2041 06:02:39.422811 DUTY Scan : NO K
2042 06:02:39.426342 ZQ Calibration : PASS
2043 06:02:39.426424 Jitter Meter : NO K
2044 06:02:39.429751 CBT Training : PASS
2045 06:02:39.429831 Write leveling : PASS
2046 06:02:39.433122 RX DQS gating : PASS
2047 06:02:39.435886 RX DQ/DQS(RDDQC) : PASS
2048 06:02:39.435967 TX DQ/DQS : PASS
2049 06:02:39.439257 RX DATLAT : PASS
2050 06:02:39.442642 RX DQ/DQS(Engine): PASS
2051 06:02:39.442723 TX OE : NO K
2052 06:02:39.446173 All Pass.
2053 06:02:39.446253
2054 06:02:39.446316 CH 0, Rank 1
2055 06:02:39.449718 SW Impedance : PASS
2056 06:02:39.449799 DUTY Scan : NO K
2057 06:02:39.452683 ZQ Calibration : PASS
2058 06:02:39.456071 Jitter Meter : NO K
2059 06:02:39.456152 CBT Training : PASS
2060 06:02:39.459604 Write leveling : PASS
2061 06:02:39.459685 RX DQS gating : PASS
2062 06:02:39.463080 RX DQ/DQS(RDDQC) : PASS
2063 06:02:39.466600 TX DQ/DQS : PASS
2064 06:02:39.466680 RX DATLAT : PASS
2065 06:02:39.469991 RX DQ/DQS(Engine): PASS
2066 06:02:39.472857 TX OE : NO K
2067 06:02:39.472937 All Pass.
2068 06:02:39.473002
2069 06:02:39.473060 CH 1, Rank 0
2070 06:02:39.476268 SW Impedance : PASS
2071 06:02:39.479713 DUTY Scan : NO K
2072 06:02:39.479793 ZQ Calibration : PASS
2073 06:02:39.483092 Jitter Meter : NO K
2074 06:02:39.486411 CBT Training : PASS
2075 06:02:39.486491 Write leveling : PASS
2076 06:02:39.489458 RX DQS gating : PASS
2077 06:02:39.492649 RX DQ/DQS(RDDQC) : PASS
2078 06:02:39.492729 TX DQ/DQS : PASS
2079 06:02:39.496649 RX DATLAT : PASS
2080 06:02:39.496729 RX DQ/DQS(Engine): PASS
2081 06:02:39.499438 TX OE : NO K
2082 06:02:39.499518 All Pass.
2083 06:02:39.499581
2084 06:02:39.502944 CH 1, Rank 1
2085 06:02:39.503024 SW Impedance : PASS
2086 06:02:39.506427 DUTY Scan : NO K
2087 06:02:39.509777 ZQ Calibration : PASS
2088 06:02:39.509858 Jitter Meter : NO K
2089 06:02:39.512904 CBT Training : PASS
2090 06:02:39.516203 Write leveling : PASS
2091 06:02:39.516356 RX DQS gating : PASS
2092 06:02:39.519352 RX DQ/DQS(RDDQC) : PASS
2093 06:02:39.522930 TX DQ/DQS : PASS
2094 06:02:39.523013 RX DATLAT : PASS
2095 06:02:39.525956 RX DQ/DQS(Engine): PASS
2096 06:02:39.529405 TX OE : NO K
2097 06:02:39.529516 All Pass.
2098 06:02:39.529583
2099 06:02:39.529644 DramC Write-DBI off
2100 06:02:39.533148 PER_BANK_REFRESH: Hybrid Mode
2101 06:02:39.536252 TX_TRACKING: ON
2102 06:02:39.539616 [GetDramInforAfterCalByMRR] Vendor 6.
2103 06:02:39.542889 [GetDramInforAfterCalByMRR] Revision 606.
2104 06:02:39.546192 [GetDramInforAfterCalByMRR] Revision 2 0.
2105 06:02:39.546281 MR0 0x3b3b
2106 06:02:39.549669 MR8 0x5151
2107 06:02:39.553204 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 06:02:39.553289
2109 06:02:39.553355 MR0 0x3b3b
2110 06:02:39.553416 MR8 0x5151
2111 06:02:39.556722 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 06:02:39.556807
2113 06:02:39.566578 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2114 06:02:39.569423 [FAST_K] Save calibration result to emmc
2115 06:02:39.573007 [FAST_K] Save calibration result to emmc
2116 06:02:39.576490 dram_init: config_dvfs: 1
2117 06:02:39.579996 dramc_set_vcore_voltage set vcore to 662500
2118 06:02:39.582850 Read voltage for 1200, 2
2119 06:02:39.582936 Vio18 = 0
2120 06:02:39.586280 Vcore = 662500
2121 06:02:39.586366 Vdram = 0
2122 06:02:39.586431 Vddq = 0
2123 06:02:39.586491 Vmddr = 0
2124 06:02:39.593224 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2125 06:02:39.596506 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2126 06:02:39.599916 MEM_TYPE=3, freq_sel=15
2127 06:02:39.603048 sv_algorithm_assistance_LP4_1600
2128 06:02:39.606319 ============ PULL DRAM RESETB DOWN ============
2129 06:02:39.610287 ========== PULL DRAM RESETB DOWN end =========
2130 06:02:39.616569 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2131 06:02:39.619944 ===================================
2132 06:02:39.623434 LPDDR4 DRAM CONFIGURATION
2133 06:02:39.623549 ===================================
2134 06:02:39.627022 EX_ROW_EN[0] = 0x0
2135 06:02:39.630049 EX_ROW_EN[1] = 0x0
2136 06:02:39.630171 LP4Y_EN = 0x0
2137 06:02:39.633511 WORK_FSP = 0x0
2138 06:02:39.633622 WL = 0x4
2139 06:02:39.637097 RL = 0x4
2140 06:02:39.637181 BL = 0x2
2141 06:02:39.640314 RPST = 0x0
2142 06:02:39.640458 RD_PRE = 0x0
2143 06:02:39.643610 WR_PRE = 0x1
2144 06:02:39.643694 WR_PST = 0x0
2145 06:02:39.646965 DBI_WR = 0x0
2146 06:02:39.647047 DBI_RD = 0x0
2147 06:02:39.650447 OTF = 0x1
2148 06:02:39.653612 ===================================
2149 06:02:39.656676 ===================================
2150 06:02:39.656768 ANA top config
2151 06:02:39.660042 ===================================
2152 06:02:39.663414 DLL_ASYNC_EN = 0
2153 06:02:39.666985 ALL_SLAVE_EN = 0
2154 06:02:39.667064 NEW_RANK_MODE = 1
2155 06:02:39.670039 DLL_IDLE_MODE = 1
2156 06:02:39.673761 LP45_APHY_COMB_EN = 1
2157 06:02:39.676713 TX_ODT_DIS = 1
2158 06:02:39.680371 NEW_8X_MODE = 1
2159 06:02:39.683331 ===================================
2160 06:02:39.686852 ===================================
2161 06:02:39.686978 data_rate = 2400
2162 06:02:39.690456 CKR = 1
2163 06:02:39.693498 DQ_P2S_RATIO = 8
2164 06:02:39.697204 ===================================
2165 06:02:39.700045 CA_P2S_RATIO = 8
2166 06:02:39.703520 DQ_CA_OPEN = 0
2167 06:02:39.706973 DQ_SEMI_OPEN = 0
2168 06:02:39.707090 CA_SEMI_OPEN = 0
2169 06:02:39.710409 CA_FULL_RATE = 0
2170 06:02:39.713893 DQ_CKDIV4_EN = 0
2171 06:02:39.717200 CA_CKDIV4_EN = 0
2172 06:02:39.720483 CA_PREDIV_EN = 0
2173 06:02:39.723652 PH8_DLY = 17
2174 06:02:39.723744 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2175 06:02:39.726790 DQ_AAMCK_DIV = 4
2176 06:02:39.730165 CA_AAMCK_DIV = 4
2177 06:02:39.733634 CA_ADMCK_DIV = 4
2178 06:02:39.736953 DQ_TRACK_CA_EN = 0
2179 06:02:39.740649 CA_PICK = 1200
2180 06:02:39.740760 CA_MCKIO = 1200
2181 06:02:39.743510 MCKIO_SEMI = 0
2182 06:02:39.746911 PLL_FREQ = 2366
2183 06:02:39.750459 DQ_UI_PI_RATIO = 32
2184 06:02:39.753879 CA_UI_PI_RATIO = 0
2185 06:02:39.757388 ===================================
2186 06:02:39.760195 ===================================
2187 06:02:39.763686 memory_type:LPDDR4
2188 06:02:39.763773 GP_NUM : 10
2189 06:02:39.766979 SRAM_EN : 1
2190 06:02:39.767063 MD32_EN : 0
2191 06:02:39.770611 ===================================
2192 06:02:39.773535 [ANA_INIT] >>>>>>>>>>>>>>
2193 06:02:39.777105 <<<<<< [CONFIGURE PHASE]: ANA_TX
2194 06:02:39.780631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2195 06:02:39.784047 ===================================
2196 06:02:39.786830 data_rate = 2400,PCW = 0X5b00
2197 06:02:39.790229 ===================================
2198 06:02:39.793823 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2199 06:02:39.800199 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 06:02:39.803727 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 06:02:39.810484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2202 06:02:39.814125 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2203 06:02:39.817412 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2204 06:02:39.817525 [ANA_INIT] flow start
2205 06:02:39.820250 [ANA_INIT] PLL >>>>>>>>
2206 06:02:39.823898 [ANA_INIT] PLL <<<<<<<<
2207 06:02:39.824012 [ANA_INIT] MIDPI >>>>>>>>
2208 06:02:39.827297 [ANA_INIT] MIDPI <<<<<<<<
2209 06:02:39.830566 [ANA_INIT] DLL >>>>>>>>
2210 06:02:39.830651 [ANA_INIT] DLL <<<<<<<<
2211 06:02:39.833951 [ANA_INIT] flow end
2212 06:02:39.837122 ============ LP4 DIFF to SE enter ============
2213 06:02:39.840238 ============ LP4 DIFF to SE exit ============
2214 06:02:39.843370 [ANA_INIT] <<<<<<<<<<<<<
2215 06:02:39.847223 [Flow] Enable top DCM control >>>>>
2216 06:02:39.850468 [Flow] Enable top DCM control <<<<<
2217 06:02:39.853985 Enable DLL master slave shuffle
2218 06:02:39.860733 ==============================================================
2219 06:02:39.860815 Gating Mode config
2220 06:02:39.866950 ==============================================================
2221 06:02:39.867041 Config description:
2222 06:02:39.876810 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2223 06:02:39.883644 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2224 06:02:39.890523 SELPH_MODE 0: By rank 1: By Phase
2225 06:02:39.893450 ==============================================================
2226 06:02:39.896910 GAT_TRACK_EN = 1
2227 06:02:39.900658 RX_GATING_MODE = 2
2228 06:02:39.904077 RX_GATING_TRACK_MODE = 2
2229 06:02:39.906822 SELPH_MODE = 1
2230 06:02:39.910349 PICG_EARLY_EN = 1
2231 06:02:39.913723 VALID_LAT_VALUE = 1
2232 06:02:39.917241 ==============================================================
2233 06:02:39.920765 Enter into Gating configuration >>>>
2234 06:02:39.923518 Exit from Gating configuration <<<<
2235 06:02:39.926924 Enter into DVFS_PRE_config >>>>>
2236 06:02:39.940779 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2237 06:02:39.943528 Exit from DVFS_PRE_config <<<<<
2238 06:02:39.947064 Enter into PICG configuration >>>>
2239 06:02:39.947152 Exit from PICG configuration <<<<
2240 06:02:39.950570 [RX_INPUT] configuration >>>>>
2241 06:02:39.953948 [RX_INPUT] configuration <<<<<
2242 06:02:39.960397 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2243 06:02:39.964024 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2244 06:02:39.970586 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 06:02:39.977149 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 06:02:39.984148 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 06:02:39.990651 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 06:02:39.994089 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2249 06:02:39.997647 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2250 06:02:40.001074 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2251 06:02:40.007462 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2252 06:02:40.010437 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2253 06:02:40.014147 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2254 06:02:40.017164 ===================================
2255 06:02:40.021168 LPDDR4 DRAM CONFIGURATION
2256 06:02:40.024386 ===================================
2257 06:02:40.024475 EX_ROW_EN[0] = 0x0
2258 06:02:40.027836 EX_ROW_EN[1] = 0x0
2259 06:02:40.027912 LP4Y_EN = 0x0
2260 06:02:40.030602 WORK_FSP = 0x0
2261 06:02:40.034177 WL = 0x4
2262 06:02:40.034276 RL = 0x4
2263 06:02:40.037623 BL = 0x2
2264 06:02:40.037723 RPST = 0x0
2265 06:02:40.041077 RD_PRE = 0x0
2266 06:02:40.041157 WR_PRE = 0x1
2267 06:02:40.044440 WR_PST = 0x0
2268 06:02:40.044510 DBI_WR = 0x0
2269 06:02:40.047388 DBI_RD = 0x0
2270 06:02:40.047461 OTF = 0x1
2271 06:02:40.050899 ===================================
2272 06:02:40.054341 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2273 06:02:40.060867 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2274 06:02:40.064378 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2275 06:02:40.067817 ===================================
2276 06:02:40.070505 LPDDR4 DRAM CONFIGURATION
2277 06:02:40.073925 ===================================
2278 06:02:40.074009 EX_ROW_EN[0] = 0x10
2279 06:02:40.077296 EX_ROW_EN[1] = 0x0
2280 06:02:40.077375 LP4Y_EN = 0x0
2281 06:02:40.080627 WORK_FSP = 0x0
2282 06:02:40.080699 WL = 0x4
2283 06:02:40.084439 RL = 0x4
2284 06:02:40.084508 BL = 0x2
2285 06:02:40.087476 RPST = 0x0
2286 06:02:40.087556 RD_PRE = 0x0
2287 06:02:40.091126 WR_PRE = 0x1
2288 06:02:40.091207 WR_PST = 0x0
2289 06:02:40.094244 DBI_WR = 0x0
2290 06:02:40.094326 DBI_RD = 0x0
2291 06:02:40.097883 OTF = 0x1
2292 06:02:40.101262 ===================================
2293 06:02:40.107576 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2294 06:02:40.107688 ==
2295 06:02:40.111018 Dram Type= 6, Freq= 0, CH_0, rank 0
2296 06:02:40.114373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2297 06:02:40.114458 ==
2298 06:02:40.117856 [Duty_Offset_Calibration]
2299 06:02:40.117941 B0:2 B1:1 CA:1
2300 06:02:40.118011
2301 06:02:40.121030 [DutyScan_Calibration_Flow] k_type=0
2302 06:02:40.131919
2303 06:02:40.132042 ==CLK 0==
2304 06:02:40.134958 Final CLK duty delay cell = 0
2305 06:02:40.137967 [0] MAX Duty = 5187%(X100), DQS PI = 24
2306 06:02:40.141307 [0] MIN Duty = 4844%(X100), DQS PI = 48
2307 06:02:40.141383 [0] AVG Duty = 5015%(X100)
2308 06:02:40.144946
2309 06:02:40.148757 CH0 CLK Duty spec in!! Max-Min= 343%
2310 06:02:40.151910 [DutyScan_Calibration_Flow] ====Done====
2311 06:02:40.152014
2312 06:02:40.154794 [DutyScan_Calibration_Flow] k_type=1
2313 06:02:40.170244
2314 06:02:40.170400 ==DQS 0 ==
2315 06:02:40.173631 Final DQS duty delay cell = -4
2316 06:02:40.177136 [-4] MAX Duty = 5156%(X100), DQS PI = 24
2317 06:02:40.179988 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2318 06:02:40.183582 [-4] AVG Duty = 4953%(X100)
2319 06:02:40.183662
2320 06:02:40.183732 ==DQS 1 ==
2321 06:02:40.187051 Final DQS duty delay cell = 0
2322 06:02:40.190547 [0] MAX Duty = 5156%(X100), DQS PI = 62
2323 06:02:40.193387 [0] MIN Duty = 5000%(X100), DQS PI = 34
2324 06:02:40.196714 [0] AVG Duty = 5078%(X100)
2325 06:02:40.196795
2326 06:02:40.199878 CH0 DQS 0 Duty spec in!! Max-Min= 405%
2327 06:02:40.199964
2328 06:02:40.203796 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2329 06:02:40.207012 [DutyScan_Calibration_Flow] ====Done====
2330 06:02:40.207103
2331 06:02:40.209831 [DutyScan_Calibration_Flow] k_type=3
2332 06:02:40.226953
2333 06:02:40.227122 ==DQM 0 ==
2334 06:02:40.230404 Final DQM duty delay cell = 0
2335 06:02:40.233941 [0] MAX Duty = 5156%(X100), DQS PI = 30
2336 06:02:40.237453 [0] MIN Duty = 4875%(X100), DQS PI = 58
2337 06:02:40.237547 [0] AVG Duty = 5015%(X100)
2338 06:02:40.240366
2339 06:02:40.240445 ==DQM 1 ==
2340 06:02:40.243890 Final DQM duty delay cell = 0
2341 06:02:40.247248 [0] MAX Duty = 5093%(X100), DQS PI = 0
2342 06:02:40.250490 [0] MIN Duty = 5000%(X100), DQS PI = 16
2343 06:02:40.250584 [0] AVG Duty = 5046%(X100)
2344 06:02:40.253831
2345 06:02:40.257349 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2346 06:02:40.257454
2347 06:02:40.260261 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2348 06:02:40.263641 [DutyScan_Calibration_Flow] ====Done====
2349 06:02:40.263740
2350 06:02:40.267001 [DutyScan_Calibration_Flow] k_type=2
2351 06:02:40.283514
2352 06:02:40.283634 ==DQ 0 ==
2353 06:02:40.286657 Final DQ duty delay cell = 0
2354 06:02:40.290167 [0] MAX Duty = 5031%(X100), DQS PI = 26
2355 06:02:40.293634 [0] MIN Duty = 4875%(X100), DQS PI = 62
2356 06:02:40.293733 [0] AVG Duty = 4953%(X100)
2357 06:02:40.297103
2358 06:02:40.297173 ==DQ 1 ==
2359 06:02:40.299842 Final DQ duty delay cell = 0
2360 06:02:40.303299 [0] MAX Duty = 5093%(X100), DQS PI = 24
2361 06:02:40.306689 [0] MIN Duty = 4938%(X100), DQS PI = 36
2362 06:02:40.306770 [0] AVG Duty = 5015%(X100)
2363 06:02:40.306833
2364 06:02:40.310007 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2365 06:02:40.313230
2366 06:02:40.316614 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2367 06:02:40.320148 [DutyScan_Calibration_Flow] ====Done====
2368 06:02:40.320254 ==
2369 06:02:40.323726 Dram Type= 6, Freq= 0, CH_1, rank 0
2370 06:02:40.326445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 06:02:40.326542 ==
2372 06:02:40.329973 [Duty_Offset_Calibration]
2373 06:02:40.330072 B0:1 B1:0 CA:0
2374 06:02:40.330161
2375 06:02:40.333313 [DutyScan_Calibration_Flow] k_type=0
2376 06:02:40.343061
2377 06:02:40.343220 ==CLK 0==
2378 06:02:40.345851 Final CLK duty delay cell = -4
2379 06:02:40.349283 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2380 06:02:40.352735 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2381 06:02:40.356254 [-4] AVG Duty = 4937%(X100)
2382 06:02:40.356403
2383 06:02:40.359795 CH1 CLK Duty spec in!! Max-Min= 125%
2384 06:02:40.362534 [DutyScan_Calibration_Flow] ====Done====
2385 06:02:40.362623
2386 06:02:40.366052 [DutyScan_Calibration_Flow] k_type=1
2387 06:02:40.382572
2388 06:02:40.382718 ==DQS 0 ==
2389 06:02:40.385581 Final DQS duty delay cell = 0
2390 06:02:40.389283 [0] MAX Duty = 5094%(X100), DQS PI = 26
2391 06:02:40.392328 [0] MIN Duty = 4844%(X100), DQS PI = 0
2392 06:02:40.392427 [0] AVG Duty = 4969%(X100)
2393 06:02:40.395850
2394 06:02:40.395925 ==DQS 1 ==
2395 06:02:40.399095 Final DQS duty delay cell = 0
2396 06:02:40.402547 [0] MAX Duty = 5187%(X100), DQS PI = 18
2397 06:02:40.405938 [0] MIN Duty = 4938%(X100), DQS PI = 58
2398 06:02:40.406047 [0] AVG Duty = 5062%(X100)
2399 06:02:40.409371
2400 06:02:40.412586 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2401 06:02:40.412661
2402 06:02:40.415675 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2403 06:02:40.418962 [DutyScan_Calibration_Flow] ====Done====
2404 06:02:40.419062
2405 06:02:40.422314 [DutyScan_Calibration_Flow] k_type=3
2406 06:02:40.439262
2407 06:02:40.439380 ==DQM 0 ==
2408 06:02:40.442703 Final DQM duty delay cell = 0
2409 06:02:40.445412 [0] MAX Duty = 5156%(X100), DQS PI = 6
2410 06:02:40.449014 [0] MIN Duty = 5000%(X100), DQS PI = 62
2411 06:02:40.449119 [0] AVG Duty = 5078%(X100)
2412 06:02:40.452533
2413 06:02:40.452633 ==DQM 1 ==
2414 06:02:40.455936 Final DQM duty delay cell = 0
2415 06:02:40.458865 [0] MAX Duty = 5031%(X100), DQS PI = 26
2416 06:02:40.462316 [0] MIN Duty = 4875%(X100), DQS PI = 36
2417 06:02:40.462391 [0] AVG Duty = 4953%(X100)
2418 06:02:40.465931
2419 06:02:40.469478 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2420 06:02:40.469558
2421 06:02:40.472229 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2422 06:02:40.475790 [DutyScan_Calibration_Flow] ====Done====
2423 06:02:40.475863
2424 06:02:40.479300 [DutyScan_Calibration_Flow] k_type=2
2425 06:02:40.494938
2426 06:02:40.495030 ==DQ 0 ==
2427 06:02:40.498484 Final DQ duty delay cell = -4
2428 06:02:40.501190 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2429 06:02:40.504557 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2430 06:02:40.508046 [-4] AVG Duty = 4984%(X100)
2431 06:02:40.508115
2432 06:02:40.508175 ==DQ 1 ==
2433 06:02:40.511267 Final DQ duty delay cell = 0
2434 06:02:40.515019 [0] MAX Duty = 5125%(X100), DQS PI = 18
2435 06:02:40.518193 [0] MIN Duty = 4969%(X100), DQS PI = 10
2436 06:02:40.518270 [0] AVG Duty = 5047%(X100)
2437 06:02:40.521287
2438 06:02:40.524811 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2439 06:02:40.524886
2440 06:02:40.527906 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2441 06:02:40.531722 [DutyScan_Calibration_Flow] ====Done====
2442 06:02:40.534754 nWR fixed to 30
2443 06:02:40.534838 [ModeRegInit_LP4] CH0 RK0
2444 06:02:40.537723 [ModeRegInit_LP4] CH0 RK1
2445 06:02:40.541314 [ModeRegInit_LP4] CH1 RK0
2446 06:02:40.544721 [ModeRegInit_LP4] CH1 RK1
2447 06:02:40.544796 match AC timing 7
2448 06:02:40.551519 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2449 06:02:40.554778 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2450 06:02:40.557921 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2451 06:02:40.564937 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2452 06:02:40.567728 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2453 06:02:40.567804 ==
2454 06:02:40.571243 Dram Type= 6, Freq= 0, CH_0, rank 0
2455 06:02:40.574812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2456 06:02:40.574882 ==
2457 06:02:40.581185 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2458 06:02:40.588140 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2459 06:02:40.594868 [CA 0] Center 39 (8~70) winsize 63
2460 06:02:40.598310 [CA 1] Center 39 (8~70) winsize 63
2461 06:02:40.601624 [CA 2] Center 35 (5~66) winsize 62
2462 06:02:40.605194 [CA 3] Center 34 (4~65) winsize 62
2463 06:02:40.608393 [CA 4] Center 33 (3~64) winsize 62
2464 06:02:40.612036 [CA 5] Center 32 (3~62) winsize 60
2465 06:02:40.612113
2466 06:02:40.614791 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2467 06:02:40.614864
2468 06:02:40.618312 [CATrainingPosCal] consider 1 rank data
2469 06:02:40.621671 u2DelayCellTimex100 = 270/100 ps
2470 06:02:40.625162 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2471 06:02:40.628461 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2472 06:02:40.635117 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2473 06:02:40.638649 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2474 06:02:40.641493 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2475 06:02:40.645014 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2476 06:02:40.645086
2477 06:02:40.648495 CA PerBit enable=1, Macro0, CA PI delay=32
2478 06:02:40.648570
2479 06:02:40.651704 [CBTSetCACLKResult] CA Dly = 32
2480 06:02:40.651776 CS Dly: 6 (0~37)
2481 06:02:40.651842 ==
2482 06:02:40.655033 Dram Type= 6, Freq= 0, CH_0, rank 1
2483 06:02:40.661523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2484 06:02:40.661616 ==
2485 06:02:40.665212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2486 06:02:40.671787 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2487 06:02:40.680765 [CA 0] Center 38 (8~69) winsize 62
2488 06:02:40.684318 [CA 1] Center 38 (8~69) winsize 62
2489 06:02:40.687060 [CA 2] Center 34 (4~65) winsize 62
2490 06:02:40.690649 [CA 3] Center 34 (4~65) winsize 62
2491 06:02:40.694145 [CA 4] Center 33 (3~64) winsize 62
2492 06:02:40.697546 [CA 5] Center 32 (3~62) winsize 60
2493 06:02:40.697624
2494 06:02:40.700788 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2495 06:02:40.700865
2496 06:02:40.704134 [CATrainingPosCal] consider 2 rank data
2497 06:02:40.707083 u2DelayCellTimex100 = 270/100 ps
2498 06:02:40.710533 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2499 06:02:40.713888 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2500 06:02:40.720970 CA2 delay=35 (5~65),Diff = 3 PI (14 cell)
2501 06:02:40.724359 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2502 06:02:40.727118 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2503 06:02:40.730538 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2504 06:02:40.730616
2505 06:02:40.734043 CA PerBit enable=1, Macro0, CA PI delay=32
2506 06:02:40.734173
2507 06:02:40.737525 [CBTSetCACLKResult] CA Dly = 32
2508 06:02:40.737600 CS Dly: 6 (0~38)
2509 06:02:40.737662
2510 06:02:40.740917 ----->DramcWriteLeveling(PI) begin...
2511 06:02:40.744255 ==
2512 06:02:40.747891 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 06:02:40.750559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 06:02:40.750641 ==
2515 06:02:40.754003 Write leveling (Byte 0): 34 => 34
2516 06:02:40.757539 Write leveling (Byte 1): 29 => 29
2517 06:02:40.761032 DramcWriteLeveling(PI) end<-----
2518 06:02:40.761104
2519 06:02:40.761164 ==
2520 06:02:40.763968 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 06:02:40.767393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 06:02:40.767463 ==
2523 06:02:40.770752 [Gating] SW mode calibration
2524 06:02:40.777619 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2525 06:02:40.781200 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2526 06:02:40.787445 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
2527 06:02:40.790848 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2528 06:02:40.794254 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 06:02:40.800666 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 06:02:40.803963 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 06:02:40.807371 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 06:02:40.814099 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2533 06:02:40.817496 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2534 06:02:40.821060 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
2535 06:02:40.827868 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 06:02:40.830711 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 06:02:40.834242 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 06:02:40.841251 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 06:02:40.844621 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 06:02:40.847818 1 0 24 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
2541 06:02:40.854038 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2542 06:02:40.857774 1 1 0 | B1->B0 | 3837 4646 | 1 0 | (0 0) (0 0)
2543 06:02:40.860471 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 06:02:40.867427 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 06:02:40.870964 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 06:02:40.873762 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 06:02:40.877211 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 06:02:40.884223 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 06:02:40.887011 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2550 06:02:40.890648 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2551 06:02:40.897374 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 06:02:40.900722 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 06:02:40.903852 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 06:02:40.910698 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 06:02:40.913970 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 06:02:40.917559 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 06:02:40.924037 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 06:02:40.927253 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 06:02:40.931045 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 06:02:40.937241 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 06:02:40.940801 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 06:02:40.944457 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 06:02:40.950590 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 06:02:40.954521 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 06:02:40.957823 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2566 06:02:40.961357 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2567 06:02:40.963964 Total UI for P1: 0, mck2ui 16
2568 06:02:40.967400 best dqsien dly found for B0: ( 1, 3, 28)
2569 06:02:40.974366 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 06:02:40.978012 Total UI for P1: 0, mck2ui 16
2571 06:02:40.981443 best dqsien dly found for B1: ( 1, 4, 0)
2572 06:02:40.984215 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2573 06:02:40.987814 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2574 06:02:40.987895
2575 06:02:40.991348 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2576 06:02:40.994193 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2577 06:02:40.997609 [Gating] SW calibration Done
2578 06:02:40.997691 ==
2579 06:02:41.001252 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 06:02:41.004790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 06:02:41.004865 ==
2582 06:02:41.007562 RX Vref Scan: 0
2583 06:02:41.007634
2584 06:02:41.007700 RX Vref 0 -> 0, step: 1
2585 06:02:41.007757
2586 06:02:41.011136 RX Delay -40 -> 252, step: 8
2587 06:02:41.014714 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2588 06:02:41.021233 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2589 06:02:41.024243 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2590 06:02:41.027821 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2591 06:02:41.031357 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2592 06:02:41.034606 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2593 06:02:41.037693 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2594 06:02:41.044682 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2595 06:02:41.047941 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2596 06:02:41.051208 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2597 06:02:41.054830 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2598 06:02:41.058304 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2599 06:02:41.065126 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2600 06:02:41.068156 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2601 06:02:41.071572 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2602 06:02:41.074816 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2603 06:02:41.074926 ==
2604 06:02:41.077578 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 06:02:41.084622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 06:02:41.084732 ==
2607 06:02:41.084833 DQS Delay:
2608 06:02:41.088157 DQS0 = 0, DQS1 = 0
2609 06:02:41.088268 DQM Delay:
2610 06:02:41.088396 DQM0 = 121, DQM1 = 113
2611 06:02:41.090967 DQ Delay:
2612 06:02:41.094561 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2613 06:02:41.097969 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2614 06:02:41.101478 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2615 06:02:41.104237 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2616 06:02:41.104377
2617 06:02:41.104440
2618 06:02:41.104498 ==
2619 06:02:41.107888 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 06:02:41.111420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 06:02:41.114925 ==
2622 06:02:41.114997
2623 06:02:41.115063
2624 06:02:41.115122 TX Vref Scan disable
2625 06:02:41.117604 == TX Byte 0 ==
2626 06:02:41.121235 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2627 06:02:41.124778 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2628 06:02:41.128194 == TX Byte 1 ==
2629 06:02:41.131621 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2630 06:02:41.134882 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2631 06:02:41.134957 ==
2632 06:02:41.137982 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 06:02:41.144948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 06:02:41.145025 ==
2635 06:02:41.155736 TX Vref=22, minBit 4, minWin=24, winSum=403
2636 06:02:41.159044 TX Vref=24, minBit 0, minWin=25, winSum=408
2637 06:02:41.162275 TX Vref=26, minBit 1, minWin=25, winSum=415
2638 06:02:41.165869 TX Vref=28, minBit 13, minWin=25, winSum=422
2639 06:02:41.168839 TX Vref=30, minBit 13, minWin=25, winSum=420
2640 06:02:41.175682 TX Vref=32, minBit 4, minWin=25, winSum=415
2641 06:02:41.179265 [TxChooseVref] Worse bit 13, Min win 25, Win sum 422, Final Vref 28
2642 06:02:41.179383
2643 06:02:41.182562 Final TX Range 1 Vref 28
2644 06:02:41.182664
2645 06:02:41.182753 ==
2646 06:02:41.185395 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 06:02:41.188918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 06:02:41.189017 ==
2649 06:02:41.192251
2650 06:02:41.192395
2651 06:02:41.192480 TX Vref Scan disable
2652 06:02:41.195489 == TX Byte 0 ==
2653 06:02:41.198933 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2654 06:02:41.202332 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2655 06:02:41.205860 == TX Byte 1 ==
2656 06:02:41.208672 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2657 06:02:41.212173 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2658 06:02:41.215645
2659 06:02:41.215749 [DATLAT]
2660 06:02:41.215843 Freq=1200, CH0 RK0
2661 06:02:41.215932
2662 06:02:41.219218 DATLAT Default: 0xd
2663 06:02:41.219319 0, 0xFFFF, sum = 0
2664 06:02:41.222812 1, 0xFFFF, sum = 0
2665 06:02:41.222912 2, 0xFFFF, sum = 0
2666 06:02:41.225646 3, 0xFFFF, sum = 0
2667 06:02:41.225746 4, 0xFFFF, sum = 0
2668 06:02:41.229142 5, 0xFFFF, sum = 0
2669 06:02:41.229244 6, 0xFFFF, sum = 0
2670 06:02:41.232842 7, 0xFFFF, sum = 0
2671 06:02:41.235523 8, 0xFFFF, sum = 0
2672 06:02:41.235630 9, 0xFFFF, sum = 0
2673 06:02:41.239093 10, 0xFFFF, sum = 0
2674 06:02:41.239194 11, 0xFFFF, sum = 0
2675 06:02:41.242661 12, 0x0, sum = 1
2676 06:02:41.242763 13, 0x0, sum = 2
2677 06:02:41.245738 14, 0x0, sum = 3
2678 06:02:41.245849 15, 0x0, sum = 4
2679 06:02:41.245949 best_step = 13
2680 06:02:41.246038
2681 06:02:41.248910 ==
2682 06:02:41.252341 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 06:02:41.255776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 06:02:41.255880 ==
2685 06:02:41.255971 RX Vref Scan: 1
2686 06:02:41.256057
2687 06:02:41.259103 Set Vref Range= 32 -> 127
2688 06:02:41.259199
2689 06:02:41.262681 RX Vref 32 -> 127, step: 1
2690 06:02:41.262781
2691 06:02:41.265482 RX Delay -13 -> 252, step: 4
2692 06:02:41.265579
2693 06:02:41.269068 Set Vref, RX VrefLevel [Byte0]: 32
2694 06:02:41.272624 [Byte1]: 32
2695 06:02:41.272706
2696 06:02:41.275970 Set Vref, RX VrefLevel [Byte0]: 33
2697 06:02:41.279165 [Byte1]: 33
2698 06:02:41.279241
2699 06:02:41.282536 Set Vref, RX VrefLevel [Byte0]: 34
2700 06:02:41.285679 [Byte1]: 34
2701 06:02:41.289796
2702 06:02:41.289871 Set Vref, RX VrefLevel [Byte0]: 35
2703 06:02:41.293039 [Byte1]: 35
2704 06:02:41.297635
2705 06:02:41.297752 Set Vref, RX VrefLevel [Byte0]: 36
2706 06:02:41.301377 [Byte1]: 36
2707 06:02:41.305561
2708 06:02:41.305637 Set Vref, RX VrefLevel [Byte0]: 37
2709 06:02:41.309142 [Byte1]: 37
2710 06:02:41.313428
2711 06:02:41.313509 Set Vref, RX VrefLevel [Byte0]: 38
2712 06:02:41.316935 [Byte1]: 38
2713 06:02:41.321505
2714 06:02:41.321588 Set Vref, RX VrefLevel [Byte0]: 39
2715 06:02:41.324913 [Byte1]: 39
2716 06:02:41.329124
2717 06:02:41.329195 Set Vref, RX VrefLevel [Byte0]: 40
2718 06:02:41.332783 [Byte1]: 40
2719 06:02:41.337027
2720 06:02:41.337103 Set Vref, RX VrefLevel [Byte0]: 41
2721 06:02:41.340528 [Byte1]: 41
2722 06:02:41.345431
2723 06:02:41.345500 Set Vref, RX VrefLevel [Byte0]: 42
2724 06:02:41.348228 [Byte1]: 42
2725 06:02:41.353093
2726 06:02:41.353163 Set Vref, RX VrefLevel [Byte0]: 43
2727 06:02:41.356488 [Byte1]: 43
2728 06:02:41.361296
2729 06:02:41.361367 Set Vref, RX VrefLevel [Byte0]: 44
2730 06:02:41.364423 [Byte1]: 44
2731 06:02:41.368661
2732 06:02:41.368739 Set Vref, RX VrefLevel [Byte0]: 45
2733 06:02:41.372087 [Byte1]: 45
2734 06:02:41.376940
2735 06:02:41.377011 Set Vref, RX VrefLevel [Byte0]: 46
2736 06:02:41.379901 [Byte1]: 46
2737 06:02:41.384947
2738 06:02:41.385029 Set Vref, RX VrefLevel [Byte0]: 47
2739 06:02:41.388229 [Byte1]: 47
2740 06:02:41.392840
2741 06:02:41.392921 Set Vref, RX VrefLevel [Byte0]: 48
2742 06:02:41.396031 [Byte1]: 48
2743 06:02:41.400851
2744 06:02:41.400932 Set Vref, RX VrefLevel [Byte0]: 49
2745 06:02:41.403592 [Byte1]: 49
2746 06:02:41.408233
2747 06:02:41.408367 Set Vref, RX VrefLevel [Byte0]: 50
2748 06:02:41.411718 [Byte1]: 50
2749 06:02:41.415975
2750 06:02:41.416056 Set Vref, RX VrefLevel [Byte0]: 51
2751 06:02:41.419437 [Byte1]: 51
2752 06:02:41.424030
2753 06:02:41.424138 Set Vref, RX VrefLevel [Byte0]: 52
2754 06:02:41.427191 [Byte1]: 52
2755 06:02:41.432045
2756 06:02:41.432125 Set Vref, RX VrefLevel [Byte0]: 53
2757 06:02:41.435084 [Byte1]: 53
2758 06:02:41.440222
2759 06:02:41.440346 Set Vref, RX VrefLevel [Byte0]: 54
2760 06:02:41.443012 [Byte1]: 54
2761 06:02:41.447881
2762 06:02:41.447952 Set Vref, RX VrefLevel [Byte0]: 55
2763 06:02:41.450750 [Byte1]: 55
2764 06:02:41.455716
2765 06:02:41.455786 Set Vref, RX VrefLevel [Byte0]: 56
2766 06:02:41.458516 [Byte1]: 56
2767 06:02:41.463463
2768 06:02:41.463533 Set Vref, RX VrefLevel [Byte0]: 57
2769 06:02:41.467041 [Byte1]: 57
2770 06:02:41.471800
2771 06:02:41.471879 Set Vref, RX VrefLevel [Byte0]: 58
2772 06:02:41.475011 [Byte1]: 58
2773 06:02:41.479403
2774 06:02:41.479482 Set Vref, RX VrefLevel [Byte0]: 59
2775 06:02:41.482508 [Byte1]: 59
2776 06:02:41.487216
2777 06:02:41.487297 Set Vref, RX VrefLevel [Byte0]: 60
2778 06:02:41.490699 [Byte1]: 60
2779 06:02:41.494949
2780 06:02:41.495020 Set Vref, RX VrefLevel [Byte0]: 61
2781 06:02:41.498464 [Byte1]: 61
2782 06:02:41.503106
2783 06:02:41.503181 Set Vref, RX VrefLevel [Byte0]: 62
2784 06:02:41.506395 [Byte1]: 62
2785 06:02:41.510857
2786 06:02:41.510933 Set Vref, RX VrefLevel [Byte0]: 63
2787 06:02:41.514249 [Byte1]: 63
2788 06:02:41.518420
2789 06:02:41.518496 Set Vref, RX VrefLevel [Byte0]: 64
2790 06:02:41.522046 [Byte1]: 64
2791 06:02:41.526990
2792 06:02:41.527070 Set Vref, RX VrefLevel [Byte0]: 65
2793 06:02:41.529815 [Byte1]: 65
2794 06:02:41.534464
2795 06:02:41.534551 Set Vref, RX VrefLevel [Byte0]: 66
2796 06:02:41.537873 [Byte1]: 66
2797 06:02:41.542453
2798 06:02:41.545620 Set Vref, RX VrefLevel [Byte0]: 67
2799 06:02:41.545695 [Byte1]: 67
2800 06:02:41.550355
2801 06:02:41.550428 Set Vref, RX VrefLevel [Byte0]: 68
2802 06:02:41.553679 [Byte1]: 68
2803 06:02:41.558444
2804 06:02:41.558526 Final RX Vref Byte 0 = 56 to rank0
2805 06:02:41.561289 Final RX Vref Byte 1 = 49 to rank0
2806 06:02:41.564856 Final RX Vref Byte 0 = 56 to rank1
2807 06:02:41.568355 Final RX Vref Byte 1 = 49 to rank1==
2808 06:02:41.571961 Dram Type= 6, Freq= 0, CH_0, rank 0
2809 06:02:41.575442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2810 06:02:41.578296 ==
2811 06:02:41.578398 DQS Delay:
2812 06:02:41.578464 DQS0 = 0, DQS1 = 0
2813 06:02:41.581804 DQM Delay:
2814 06:02:41.581885 DQM0 = 121, DQM1 = 111
2815 06:02:41.585312 DQ Delay:
2816 06:02:41.588472 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =120
2817 06:02:41.591726 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2818 06:02:41.594883 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
2819 06:02:41.598136 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2820 06:02:41.598211
2821 06:02:41.598273
2822 06:02:41.605184 [DQSOSCAuto] RK0, (LSB)MR18= 0x150e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2823 06:02:41.608124 CH0 RK0: MR19=404, MR18=150E
2824 06:02:41.615608 CH0_RK0: MR19=0x404, MR18=0x150E, DQSOSC=401, MR23=63, INC=40, DEC=27
2825 06:02:41.615689
2826 06:02:41.618471 ----->DramcWriteLeveling(PI) begin...
2827 06:02:41.618578 ==
2828 06:02:41.622064 Dram Type= 6, Freq= 0, CH_0, rank 1
2829 06:02:41.624839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 06:02:41.624920 ==
2831 06:02:41.628585 Write leveling (Byte 0): 33 => 33
2832 06:02:41.631794 Write leveling (Byte 1): 29 => 29
2833 06:02:41.635031 DramcWriteLeveling(PI) end<-----
2834 06:02:41.635111
2835 06:02:41.635173 ==
2836 06:02:41.638422 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 06:02:41.645317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 06:02:41.645398 ==
2839 06:02:41.645461 [Gating] SW mode calibration
2840 06:02:41.655359 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2841 06:02:41.658767 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2842 06:02:41.661922 0 15 0 | B1->B0 | 3333 3333 | 1 0 | (1 1) (0 0)
2843 06:02:41.668315 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 06:02:41.672278 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 06:02:41.675130 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 06:02:41.682821 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 06:02:41.684934 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 06:02:41.688447 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 06:02:41.694874 0 15 28 | B1->B0 | 3030 2d2d | 0 0 | (0 1) (1 0)
2850 06:02:41.698420 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 06:02:41.701636 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 06:02:41.708423 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 06:02:41.711740 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 06:02:41.715037 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 06:02:41.722288 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 06:02:41.724947 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2857 06:02:41.728170 1 0 28 | B1->B0 | 3737 3736 | 0 1 | (0 0) (1 1)
2858 06:02:41.731560 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 06:02:41.738388 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 06:02:41.741755 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 06:02:41.744893 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 06:02:41.751799 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 06:02:41.754904 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 06:02:41.758348 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 06:02:41.765251 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2866 06:02:41.768754 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2867 06:02:41.772226 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 06:02:41.778766 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 06:02:41.781829 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 06:02:41.785473 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 06:02:41.791935 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 06:02:41.795547 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 06:02:41.798995 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 06:02:41.805230 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 06:02:41.808934 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 06:02:41.811818 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 06:02:41.815243 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 06:02:41.822124 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 06:02:41.825222 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 06:02:41.828715 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2881 06:02:41.835686 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2882 06:02:41.838497 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 06:02:41.841903 Total UI for P1: 0, mck2ui 16
2884 06:02:41.845288 best dqsien dly found for B0: ( 1, 3, 26)
2885 06:02:41.848533 Total UI for P1: 0, mck2ui 16
2886 06:02:41.851861 best dqsien dly found for B1: ( 1, 3, 26)
2887 06:02:41.855293 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2888 06:02:41.859146 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2889 06:02:41.859227
2890 06:02:41.862422 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2891 06:02:41.865751 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2892 06:02:41.869086 [Gating] SW calibration Done
2893 06:02:41.869168 ==
2894 06:02:41.872130 Dram Type= 6, Freq= 0, CH_0, rank 1
2895 06:02:41.875280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 06:02:41.878924 ==
2897 06:02:41.879005 RX Vref Scan: 0
2898 06:02:41.879070
2899 06:02:41.882310 RX Vref 0 -> 0, step: 1
2900 06:02:41.882392
2901 06:02:41.882456 RX Delay -40 -> 252, step: 8
2902 06:02:41.889178 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2903 06:02:41.892325 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2904 06:02:41.895456 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2905 06:02:41.898766 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2906 06:02:41.902322 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2907 06:02:41.909291 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2908 06:02:41.912699 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2909 06:02:41.915448 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2910 06:02:41.919022 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2911 06:02:41.922579 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2912 06:02:41.928763 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2913 06:02:41.932127 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2914 06:02:41.935477 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2915 06:02:41.939331 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2916 06:02:41.942181 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2917 06:02:41.949226 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2918 06:02:41.949310 ==
2919 06:02:41.952542 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 06:02:41.956172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 06:02:41.956314 ==
2922 06:02:41.956427 DQS Delay:
2923 06:02:41.959437 DQS0 = 0, DQS1 = 0
2924 06:02:41.959519 DQM Delay:
2925 06:02:41.962468 DQM0 = 122, DQM1 = 112
2926 06:02:41.962549 DQ Delay:
2927 06:02:41.965717 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2928 06:02:41.969105 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2929 06:02:41.972344 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2930 06:02:41.975699 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2931 06:02:41.975781
2932 06:02:41.975845
2933 06:02:41.978999 ==
2934 06:02:41.979084 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 06:02:41.985961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 06:02:41.986058 ==
2937 06:02:41.986124
2938 06:02:41.986185
2939 06:02:41.989508 TX Vref Scan disable
2940 06:02:41.989590 == TX Byte 0 ==
2941 06:02:41.992293 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2942 06:02:41.999439 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2943 06:02:41.999524 == TX Byte 1 ==
2944 06:02:42.002815 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2945 06:02:42.008844 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2946 06:02:42.008938 ==
2947 06:02:42.012713 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 06:02:42.016178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 06:02:42.016297 ==
2950 06:02:42.028194 TX Vref=22, minBit 1, minWin=25, winSum=411
2951 06:02:42.031698 TX Vref=24, minBit 13, minWin=25, winSum=416
2952 06:02:42.034470 TX Vref=26, minBit 3, minWin=25, winSum=419
2953 06:02:42.038135 TX Vref=28, minBit 12, minWin=25, winSum=421
2954 06:02:42.041491 TX Vref=30, minBit 12, minWin=25, winSum=424
2955 06:02:42.047812 TX Vref=32, minBit 12, minWin=25, winSum=425
2956 06:02:42.051460 [TxChooseVref] Worse bit 12, Min win 25, Win sum 425, Final Vref 32
2957 06:02:42.051590
2958 06:02:42.054652 Final TX Range 1 Vref 32
2959 06:02:42.054763
2960 06:02:42.054888 ==
2961 06:02:42.058288 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 06:02:42.061436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 06:02:42.061517 ==
2964 06:02:42.064642
2965 06:02:42.064722
2966 06:02:42.064785 TX Vref Scan disable
2967 06:02:42.067934 == TX Byte 0 ==
2968 06:02:42.071293 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2969 06:02:42.078114 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2970 06:02:42.078195 == TX Byte 1 ==
2971 06:02:42.081363 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2972 06:02:42.088089 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2973 06:02:42.088172
2974 06:02:42.088234 [DATLAT]
2975 06:02:42.088342 Freq=1200, CH0 RK1
2976 06:02:42.088402
2977 06:02:42.091365 DATLAT Default: 0xd
2978 06:02:42.091444 0, 0xFFFF, sum = 0
2979 06:02:42.094780 1, 0xFFFF, sum = 0
2980 06:02:42.098367 2, 0xFFFF, sum = 0
2981 06:02:42.098449 3, 0xFFFF, sum = 0
2982 06:02:42.101332 4, 0xFFFF, sum = 0
2983 06:02:42.101414 5, 0xFFFF, sum = 0
2984 06:02:42.104827 6, 0xFFFF, sum = 0
2985 06:02:42.104908 7, 0xFFFF, sum = 0
2986 06:02:42.108291 8, 0xFFFF, sum = 0
2987 06:02:42.108388 9, 0xFFFF, sum = 0
2988 06:02:42.111119 10, 0xFFFF, sum = 0
2989 06:02:42.111227 11, 0xFFFF, sum = 0
2990 06:02:42.114600 12, 0x0, sum = 1
2991 06:02:42.114708 13, 0x0, sum = 2
2992 06:02:42.117809 14, 0x0, sum = 3
2993 06:02:42.117909 15, 0x0, sum = 4
2994 06:02:42.118003 best_step = 13
2995 06:02:42.121473
2996 06:02:42.121553 ==
2997 06:02:42.124374 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 06:02:42.128067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 06:02:42.128173 ==
3000 06:02:42.128264 RX Vref Scan: 0
3001 06:02:42.128379
3002 06:02:42.131631 RX Vref 0 -> 0, step: 1
3003 06:02:42.131712
3004 06:02:42.134493 RX Delay -13 -> 252, step: 4
3005 06:02:42.138137 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3006 06:02:42.144608 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3007 06:02:42.148177 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3008 06:02:42.151091 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3009 06:02:42.154544 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3010 06:02:42.158064 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3011 06:02:42.164824 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3012 06:02:42.167917 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3013 06:02:42.171217 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3014 06:02:42.174896 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3015 06:02:42.178053 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3016 06:02:42.181515 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3017 06:02:42.187790 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3018 06:02:42.191925 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3019 06:02:42.194839 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3020 06:02:42.198002 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3021 06:02:42.198083 ==
3022 06:02:42.201787 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 06:02:42.208164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 06:02:42.208247 ==
3025 06:02:42.208351 DQS Delay:
3026 06:02:42.211659 DQS0 = 0, DQS1 = 0
3027 06:02:42.211740 DQM Delay:
3028 06:02:42.211805 DQM0 = 121, DQM1 = 110
3029 06:02:42.215184 DQ Delay:
3030 06:02:42.218104 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3031 06:02:42.221581 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3032 06:02:42.224518 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =104
3033 06:02:42.228058 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3034 06:02:42.228164
3035 06:02:42.228254
3036 06:02:42.237732 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3037 06:02:42.237815 CH0 RK1: MR19=403, MR18=10F1
3038 06:02:42.244567 CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3039 06:02:42.248075 [RxdqsGatingPostProcess] freq 1200
3040 06:02:42.254573 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3041 06:02:42.257960 best DQS0 dly(2T, 0.5T) = (0, 11)
3042 06:02:42.260887 best DQS1 dly(2T, 0.5T) = (0, 12)
3043 06:02:42.264273 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3044 06:02:42.267938 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3045 06:02:42.271483 best DQS0 dly(2T, 0.5T) = (0, 11)
3046 06:02:42.271567 best DQS1 dly(2T, 0.5T) = (0, 11)
3047 06:02:42.274404 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3048 06:02:42.277999 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3049 06:02:42.281477 Pre-setting of DQS Precalculation
3050 06:02:42.288176 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3051 06:02:42.288283 ==
3052 06:02:42.291372 Dram Type= 6, Freq= 0, CH_1, rank 0
3053 06:02:42.294363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 06:02:42.294446 ==
3055 06:02:42.301492 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3056 06:02:42.307636 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3057 06:02:42.314481 [CA 0] Center 37 (7~68) winsize 62
3058 06:02:42.318159 [CA 1] Center 37 (7~68) winsize 62
3059 06:02:42.321202 [CA 2] Center 35 (5~65) winsize 61
3060 06:02:42.324850 [CA 3] Center 34 (4~65) winsize 62
3061 06:02:42.328103 [CA 4] Center 34 (4~64) winsize 61
3062 06:02:42.330992 [CA 5] Center 33 (3~63) winsize 61
3063 06:02:42.331079
3064 06:02:42.334501 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3065 06:02:42.334584
3066 06:02:42.338086 [CATrainingPosCal] consider 1 rank data
3067 06:02:42.341408 u2DelayCellTimex100 = 270/100 ps
3068 06:02:42.344734 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3069 06:02:42.347881 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3070 06:02:42.354656 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3071 06:02:42.358337 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3072 06:02:42.361771 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3073 06:02:42.365098 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3074 06:02:42.365180
3075 06:02:42.367877 CA PerBit enable=1, Macro0, CA PI delay=33
3076 06:02:42.367959
3077 06:02:42.371338 [CBTSetCACLKResult] CA Dly = 33
3078 06:02:42.371421 CS Dly: 7 (0~38)
3079 06:02:42.371559 ==
3080 06:02:42.374913 Dram Type= 6, Freq= 0, CH_1, rank 1
3081 06:02:42.381494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 06:02:42.381586 ==
3083 06:02:42.385023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3084 06:02:42.391293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3085 06:02:42.400458 [CA 0] Center 37 (7~68) winsize 62
3086 06:02:42.403978 [CA 1] Center 37 (7~68) winsize 62
3087 06:02:42.406823 [CA 2] Center 35 (6~65) winsize 60
3088 06:02:42.410287 [CA 3] Center 35 (5~65) winsize 61
3089 06:02:42.413742 [CA 4] Center 34 (4~65) winsize 62
3090 06:02:42.417186 [CA 5] Center 34 (4~64) winsize 61
3091 06:02:42.417268
3092 06:02:42.420507 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3093 06:02:42.420592
3094 06:02:42.423740 [CATrainingPosCal] consider 2 rank data
3095 06:02:42.426794 u2DelayCellTimex100 = 270/100 ps
3096 06:02:42.430740 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3097 06:02:42.434082 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3098 06:02:42.440738 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3099 06:02:42.443895 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3100 06:02:42.446816 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3101 06:02:42.450363 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3102 06:02:42.450445
3103 06:02:42.454195 CA PerBit enable=1, Macro0, CA PI delay=33
3104 06:02:42.454277
3105 06:02:42.457452 [CBTSetCACLKResult] CA Dly = 33
3106 06:02:42.457534 CS Dly: 8 (0~40)
3107 06:02:42.457598
3108 06:02:42.460896 ----->DramcWriteLeveling(PI) begin...
3109 06:02:42.460980 ==
3110 06:02:42.463898 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 06:02:42.470876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 06:02:42.470984 ==
3113 06:02:42.474331 Write leveling (Byte 0): 26 => 26
3114 06:02:42.477101 Write leveling (Byte 1): 27 => 27
3115 06:02:42.477183 DramcWriteLeveling(PI) end<-----
3116 06:02:42.477247
3117 06:02:42.480705 ==
3118 06:02:42.480787 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 06:02:42.487310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 06:02:42.487392 ==
3121 06:02:42.490778 [Gating] SW mode calibration
3122 06:02:42.497242 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3123 06:02:42.500800 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3124 06:02:42.507721 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3125 06:02:42.510565 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 06:02:42.514143 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 06:02:42.520711 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 06:02:42.524177 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 06:02:42.527024 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 06:02:42.534036 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
3131 06:02:42.537655 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3132 06:02:42.540540 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 06:02:42.544079 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 06:02:42.551292 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 06:02:42.553913 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 06:02:42.557203 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 06:02:42.564203 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3138 06:02:42.567353 1 0 24 | B1->B0 | 2c2c 3939 | 0 0 | (0 0) (0 0)
3139 06:02:42.570584 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3140 06:02:42.577415 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 06:02:42.580991 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 06:02:42.583924 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 06:02:42.590620 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 06:02:42.594316 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 06:02:42.597756 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 06:02:42.604118 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3147 06:02:42.607651 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3148 06:02:42.611249 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 06:02:42.617360 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 06:02:42.620799 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 06:02:42.624630 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 06:02:42.627478 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 06:02:42.634545 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 06:02:42.637399 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 06:02:42.640858 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 06:02:42.647364 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 06:02:42.650842 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 06:02:42.654462 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 06:02:42.660965 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 06:02:42.664458 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 06:02:42.667376 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 06:02:42.673849 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3163 06:02:42.677212 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3164 06:02:42.680706 Total UI for P1: 0, mck2ui 16
3165 06:02:42.683999 best dqsien dly found for B0: ( 1, 3, 26)
3166 06:02:42.687664 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 06:02:42.690601 Total UI for P1: 0, mck2ui 16
3168 06:02:42.693924 best dqsien dly found for B1: ( 1, 3, 26)
3169 06:02:42.697489 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3170 06:02:42.700759 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3171 06:02:42.700842
3172 06:02:42.707409 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3173 06:02:42.710852 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3174 06:02:42.710938 [Gating] SW calibration Done
3175 06:02:42.714204 ==
3176 06:02:42.714287 Dram Type= 6, Freq= 0, CH_1, rank 0
3177 06:02:42.721137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3178 06:02:42.721255 ==
3179 06:02:42.721374 RX Vref Scan: 0
3180 06:02:42.721477
3181 06:02:42.724082 RX Vref 0 -> 0, step: 1
3182 06:02:42.724191
3183 06:02:42.727333 RX Delay -40 -> 252, step: 8
3184 06:02:42.730985 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3185 06:02:42.734597 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3186 06:02:42.737416 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3187 06:02:42.744205 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3188 06:02:42.747714 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3189 06:02:42.751134 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3190 06:02:42.754600 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3191 06:02:42.757534 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3192 06:02:42.764102 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3193 06:02:42.767660 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3194 06:02:42.771274 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3195 06:02:42.774162 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3196 06:02:42.777798 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3197 06:02:42.784011 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3198 06:02:42.787538 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3199 06:02:42.790842 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3200 06:02:42.790925 ==
3201 06:02:42.794225 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 06:02:42.797874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 06:02:42.797959 ==
3204 06:02:42.801442 DQS Delay:
3205 06:02:42.801524 DQS0 = 0, DQS1 = 0
3206 06:02:42.801591 DQM Delay:
3207 06:02:42.804321 DQM0 = 119, DQM1 = 116
3208 06:02:42.804405 DQ Delay:
3209 06:02:42.808031 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3210 06:02:42.810918 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3211 06:02:42.818037 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3212 06:02:42.820810 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3213 06:02:42.820896
3214 06:02:42.820962
3215 06:02:42.821023 ==
3216 06:02:42.824238 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 06:02:42.827551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 06:02:42.827633 ==
3219 06:02:42.827698
3220 06:02:42.827757
3221 06:02:42.831195 TX Vref Scan disable
3222 06:02:42.831278 == TX Byte 0 ==
3223 06:02:42.837918 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3224 06:02:42.841222 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3225 06:02:42.841303 == TX Byte 1 ==
3226 06:02:42.847645 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3227 06:02:42.851144 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3228 06:02:42.851226 ==
3229 06:02:42.854501 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 06:02:42.857835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 06:02:42.857943 ==
3232 06:02:42.870360 TX Vref=22, minBit 9, minWin=24, winSum=412
3233 06:02:42.873949 TX Vref=24, minBit 9, minWin=25, winSum=417
3234 06:02:42.877346 TX Vref=26, minBit 9, minWin=25, winSum=425
3235 06:02:42.880260 TX Vref=28, minBit 11, minWin=25, winSum=423
3236 06:02:42.883834 TX Vref=30, minBit 2, minWin=26, winSum=429
3237 06:02:42.890640 TX Vref=32, minBit 2, minWin=26, winSum=429
3238 06:02:42.893447 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 30
3239 06:02:42.893549
3240 06:02:42.896850 Final TX Range 1 Vref 30
3241 06:02:42.896932
3242 06:02:42.896996 ==
3243 06:02:42.900096 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 06:02:42.903632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 06:02:42.903714 ==
3246 06:02:42.907089
3247 06:02:42.907170
3248 06:02:42.907235 TX Vref Scan disable
3249 06:02:42.910732 == TX Byte 0 ==
3250 06:02:42.913568 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3251 06:02:42.917082 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3252 06:02:42.920721 == TX Byte 1 ==
3253 06:02:42.923861 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3254 06:02:42.927325 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3255 06:02:42.927425
3256 06:02:42.930997 [DATLAT]
3257 06:02:42.931078 Freq=1200, CH1 RK0
3258 06:02:42.931143
3259 06:02:42.933743 DATLAT Default: 0xd
3260 06:02:42.933824 0, 0xFFFF, sum = 0
3261 06:02:42.937324 1, 0xFFFF, sum = 0
3262 06:02:42.937407 2, 0xFFFF, sum = 0
3263 06:02:42.940170 3, 0xFFFF, sum = 0
3264 06:02:42.940278 4, 0xFFFF, sum = 0
3265 06:02:42.943724 5, 0xFFFF, sum = 0
3266 06:02:42.943807 6, 0xFFFF, sum = 0
3267 06:02:42.947163 7, 0xFFFF, sum = 0
3268 06:02:42.947246 8, 0xFFFF, sum = 0
3269 06:02:42.950640 9, 0xFFFF, sum = 0
3270 06:02:42.954191 10, 0xFFFF, sum = 0
3271 06:02:42.954274 11, 0xFFFF, sum = 0
3272 06:02:42.956837 12, 0x0, sum = 1
3273 06:02:42.956952 13, 0x0, sum = 2
3274 06:02:42.957048 14, 0x0, sum = 3
3275 06:02:42.960210 15, 0x0, sum = 4
3276 06:02:42.960297 best_step = 13
3277 06:02:42.960360
3278 06:02:42.963604 ==
3279 06:02:42.963692 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 06:02:42.970441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 06:02:42.970523 ==
3282 06:02:42.970587 RX Vref Scan: 1
3283 06:02:42.970646
3284 06:02:42.973837 Set Vref Range= 32 -> 127
3285 06:02:42.973918
3286 06:02:42.976798 RX Vref 32 -> 127, step: 1
3287 06:02:42.976879
3288 06:02:42.980224 RX Delay -5 -> 252, step: 4
3289 06:02:42.980358
3290 06:02:42.983517 Set Vref, RX VrefLevel [Byte0]: 32
3291 06:02:42.987026 [Byte1]: 32
3292 06:02:42.987107
3293 06:02:42.990287 Set Vref, RX VrefLevel [Byte0]: 33
3294 06:02:42.993435 [Byte1]: 33
3295 06:02:42.993518
3296 06:02:42.997233 Set Vref, RX VrefLevel [Byte0]: 34
3297 06:02:43.000601 [Byte1]: 34
3298 06:02:43.004510
3299 06:02:43.004590 Set Vref, RX VrefLevel [Byte0]: 35
3300 06:02:43.007509 [Byte1]: 35
3301 06:02:43.012000
3302 06:02:43.012071 Set Vref, RX VrefLevel [Byte0]: 36
3303 06:02:43.015488 [Byte1]: 36
3304 06:02:43.019870
3305 06:02:43.019950 Set Vref, RX VrefLevel [Byte0]: 37
3306 06:02:43.023298 [Byte1]: 37
3307 06:02:43.027565
3308 06:02:43.027646 Set Vref, RX VrefLevel [Byte0]: 38
3309 06:02:43.031155 [Byte1]: 38
3310 06:02:43.035494
3311 06:02:43.035574 Set Vref, RX VrefLevel [Byte0]: 39
3312 06:02:43.039199 [Byte1]: 39
3313 06:02:43.043489
3314 06:02:43.043568 Set Vref, RX VrefLevel [Byte0]: 40
3315 06:02:43.046946 [Byte1]: 40
3316 06:02:43.051338
3317 06:02:43.051419 Set Vref, RX VrefLevel [Byte0]: 41
3318 06:02:43.054951 [Byte1]: 41
3319 06:02:43.059159
3320 06:02:43.059238 Set Vref, RX VrefLevel [Byte0]: 42
3321 06:02:43.062765 [Byte1]: 42
3322 06:02:43.067056
3323 06:02:43.067136 Set Vref, RX VrefLevel [Byte0]: 43
3324 06:02:43.070620 [Byte1]: 43
3325 06:02:43.074940
3326 06:02:43.075020 Set Vref, RX VrefLevel [Byte0]: 44
3327 06:02:43.078349 [Byte1]: 44
3328 06:02:43.082616
3329 06:02:43.082696 Set Vref, RX VrefLevel [Byte0]: 45
3330 06:02:43.086349 [Byte1]: 45
3331 06:02:43.091025
3332 06:02:43.091104 Set Vref, RX VrefLevel [Byte0]: 46
3333 06:02:43.094328 [Byte1]: 46
3334 06:02:43.098477
3335 06:02:43.098557 Set Vref, RX VrefLevel [Byte0]: 47
3336 06:02:43.101943 [Byte1]: 47
3337 06:02:43.106537
3338 06:02:43.106618 Set Vref, RX VrefLevel [Byte0]: 48
3339 06:02:43.109755 [Byte1]: 48
3340 06:02:43.114180
3341 06:02:43.114256 Set Vref, RX VrefLevel [Byte0]: 49
3342 06:02:43.117744 [Byte1]: 49
3343 06:02:43.122059
3344 06:02:43.122176 Set Vref, RX VrefLevel [Byte0]: 50
3345 06:02:43.125434 [Byte1]: 50
3346 06:02:43.129750
3347 06:02:43.129828 Set Vref, RX VrefLevel [Byte0]: 51
3348 06:02:43.133022 [Byte1]: 51
3349 06:02:43.137503
3350 06:02:43.137579 Set Vref, RX VrefLevel [Byte0]: 52
3351 06:02:43.141154 [Byte1]: 52
3352 06:02:43.145604
3353 06:02:43.145712 Set Vref, RX VrefLevel [Byte0]: 53
3354 06:02:43.149166 [Byte1]: 53
3355 06:02:43.153451
3356 06:02:43.153530 Set Vref, RX VrefLevel [Byte0]: 54
3357 06:02:43.156895 [Byte1]: 54
3358 06:02:43.161255
3359 06:02:43.161335 Set Vref, RX VrefLevel [Byte0]: 55
3360 06:02:43.164883 [Byte1]: 55
3361 06:02:43.169188
3362 06:02:43.169301 Set Vref, RX VrefLevel [Byte0]: 56
3363 06:02:43.172775 [Byte1]: 56
3364 06:02:43.177102
3365 06:02:43.177183 Set Vref, RX VrefLevel [Byte0]: 57
3366 06:02:43.180560 [Byte1]: 57
3367 06:02:43.184937
3368 06:02:43.185016 Set Vref, RX VrefLevel [Byte0]: 58
3369 06:02:43.188248 [Byte1]: 58
3370 06:02:43.192538
3371 06:02:43.192614 Set Vref, RX VrefLevel [Byte0]: 59
3372 06:02:43.196085 [Byte1]: 59
3373 06:02:43.200937
3374 06:02:43.201011 Set Vref, RX VrefLevel [Byte0]: 60
3375 06:02:43.203866 [Byte1]: 60
3376 06:02:43.208746
3377 06:02:43.208853 Set Vref, RX VrefLevel [Byte0]: 61
3378 06:02:43.211612 [Byte1]: 61
3379 06:02:43.216076
3380 06:02:43.216156 Set Vref, RX VrefLevel [Byte0]: 62
3381 06:02:43.219458 [Byte1]: 62
3382 06:02:43.224557
3383 06:02:43.224638 Set Vref, RX VrefLevel [Byte0]: 63
3384 06:02:43.227347 [Byte1]: 63
3385 06:02:43.232260
3386 06:02:43.232383 Set Vref, RX VrefLevel [Byte0]: 64
3387 06:02:43.235020 [Byte1]: 64
3388 06:02:43.239995
3389 06:02:43.240106 Set Vref, RX VrefLevel [Byte0]: 65
3390 06:02:43.243286 [Byte1]: 65
3391 06:02:43.247882
3392 06:02:43.247962 Set Vref, RX VrefLevel [Byte0]: 66
3393 06:02:43.251173 [Byte1]: 66
3394 06:02:43.255758
3395 06:02:43.255833 Set Vref, RX VrefLevel [Byte0]: 67
3396 06:02:43.258882 [Byte1]: 67
3397 06:02:43.263072
3398 06:02:43.263148 Set Vref, RX VrefLevel [Byte0]: 68
3399 06:02:43.266821 [Byte1]: 68
3400 06:02:43.271469
3401 06:02:43.271573 Final RX Vref Byte 0 = 54 to rank0
3402 06:02:43.274354 Final RX Vref Byte 1 = 53 to rank0
3403 06:02:43.278057 Final RX Vref Byte 0 = 54 to rank1
3404 06:02:43.281243 Final RX Vref Byte 1 = 53 to rank1==
3405 06:02:43.284803 Dram Type= 6, Freq= 0, CH_1, rank 0
3406 06:02:43.291075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3407 06:02:43.291171 ==
3408 06:02:43.291237 DQS Delay:
3409 06:02:43.291296 DQS0 = 0, DQS1 = 0
3410 06:02:43.294499 DQM Delay:
3411 06:02:43.294589 DQM0 = 120, DQM1 = 117
3412 06:02:43.298084 DQ Delay:
3413 06:02:43.301548 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3414 06:02:43.305103 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =122
3415 06:02:43.307803 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3416 06:02:43.311380 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3417 06:02:43.311455
3418 06:02:43.311551
3419 06:02:43.317895 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3420 06:02:43.321516 CH1 RK0: MR19=404, MR18=13
3421 06:02:43.327909 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3422 06:02:43.327994
3423 06:02:43.331456 ----->DramcWriteLeveling(PI) begin...
3424 06:02:43.331530 ==
3425 06:02:43.334273 Dram Type= 6, Freq= 0, CH_1, rank 1
3426 06:02:43.337910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 06:02:43.338008 ==
3428 06:02:43.340826 Write leveling (Byte 0): 26 => 26
3429 06:02:43.344462 Write leveling (Byte 1): 27 => 27
3430 06:02:43.347885 DramcWriteLeveling(PI) end<-----
3431 06:02:43.348003
3432 06:02:43.348071 ==
3433 06:02:43.351450 Dram Type= 6, Freq= 0, CH_1, rank 1
3434 06:02:43.354802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 06:02:43.357567 ==
3436 06:02:43.357656 [Gating] SW mode calibration
3437 06:02:43.364427 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3438 06:02:43.371610 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3439 06:02:43.374470 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 06:02:43.381573 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 06:02:43.384853 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 06:02:43.388172 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 06:02:43.394438 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 06:02:43.397826 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 06:02:43.401580 0 15 24 | B1->B0 | 2929 3434 | 0 0 | (1 0) (0 1)
3446 06:02:43.408003 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3447 06:02:43.411343 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 06:02:43.414528 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 06:02:43.417885 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 06:02:43.424879 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 06:02:43.427769 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 06:02:43.431099 1 0 20 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
3453 06:02:43.437556 1 0 24 | B1->B0 | 4444 2d2d | 0 0 | (0 0) (1 1)
3454 06:02:43.441254 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 06:02:43.444779 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 06:02:43.451430 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 06:02:43.454206 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 06:02:43.457944 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 06:02:43.464502 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 06:02:43.468042 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 06:02:43.470904 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3462 06:02:43.477970 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3463 06:02:43.480995 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 06:02:43.484624 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 06:02:43.491347 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 06:02:43.494030 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 06:02:43.497529 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 06:02:43.504366 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 06:02:43.507806 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 06:02:43.510493 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 06:02:43.517321 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 06:02:43.520544 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 06:02:43.524120 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 06:02:43.530796 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 06:02:43.533977 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 06:02:43.537144 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3477 06:02:43.543671 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3478 06:02:43.547143 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3479 06:02:43.550610 Total UI for P1: 0, mck2ui 16
3480 06:02:43.554308 best dqsien dly found for B1: ( 1, 3, 22)
3481 06:02:43.557252 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 06:02:43.560884 Total UI for P1: 0, mck2ui 16
3483 06:02:43.563798 best dqsien dly found for B0: ( 1, 3, 28)
3484 06:02:43.567276 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3485 06:02:43.570962 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3486 06:02:43.571045
3487 06:02:43.573641 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3488 06:02:43.580577 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3489 06:02:43.580687 [Gating] SW calibration Done
3490 06:02:43.583338 ==
3491 06:02:43.583421 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 06:02:43.590624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 06:02:43.590707 ==
3494 06:02:43.590771 RX Vref Scan: 0
3495 06:02:43.590832
3496 06:02:43.593467 RX Vref 0 -> 0, step: 1
3497 06:02:43.593548
3498 06:02:43.597102 RX Delay -40 -> 252, step: 8
3499 06:02:43.600711 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3500 06:02:43.603993 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3501 06:02:43.606927 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3502 06:02:43.613463 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3503 06:02:43.616882 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3504 06:02:43.620386 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3505 06:02:43.623686 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3506 06:02:43.627080 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3507 06:02:43.633603 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3508 06:02:43.637125 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3509 06:02:43.640354 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3510 06:02:43.643990 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3511 06:02:43.646786 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3512 06:02:43.653591 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3513 06:02:43.656862 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3514 06:02:43.660130 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3515 06:02:43.660255 ==
3516 06:02:43.663404 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 06:02:43.666689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3518 06:02:43.670231 ==
3519 06:02:43.670343 DQS Delay:
3520 06:02:43.670440 DQS0 = 0, DQS1 = 0
3521 06:02:43.673756 DQM Delay:
3522 06:02:43.673842 DQM0 = 120, DQM1 = 118
3523 06:02:43.676678 DQ Delay:
3524 06:02:43.680017 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3525 06:02:43.683361 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3526 06:02:43.686602 DQ8 =103, DQ9 =107, DQ10 =119, DQ11 =115
3527 06:02:43.690258 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3528 06:02:43.690339
3529 06:02:43.690403
3530 06:02:43.690462 ==
3531 06:02:43.693127 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 06:02:43.696800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 06:02:43.696908 ==
3534 06:02:43.697000
3535 06:02:43.699613
3536 06:02:43.699693 TX Vref Scan disable
3537 06:02:43.703207 == TX Byte 0 ==
3538 06:02:43.706750 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3539 06:02:43.709450 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3540 06:02:43.713081 == TX Byte 1 ==
3541 06:02:43.716674 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3542 06:02:43.719650 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3543 06:02:43.719731 ==
3544 06:02:43.723226 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 06:02:43.729490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 06:02:43.729571 ==
3547 06:02:43.739860 TX Vref=22, minBit 10, minWin=25, winSum=420
3548 06:02:43.743470 TX Vref=24, minBit 1, minWin=26, winSum=425
3549 06:02:43.747076 TX Vref=26, minBit 2, minWin=26, winSum=431
3550 06:02:43.749954 TX Vref=28, minBit 9, minWin=26, winSum=437
3551 06:02:43.753550 TX Vref=30, minBit 0, minWin=27, winSum=435
3552 06:02:43.759901 TX Vref=32, minBit 10, minWin=26, winSum=434
3553 06:02:43.763328 [TxChooseVref] Worse bit 0, Min win 27, Win sum 435, Final Vref 30
3554 06:02:43.763435
3555 06:02:43.766835 Final TX Range 1 Vref 30
3556 06:02:43.766944
3557 06:02:43.767078 ==
3558 06:02:43.770323 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 06:02:43.773501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 06:02:43.773607 ==
3561 06:02:43.776589
3562 06:02:43.776663
3563 06:02:43.776734 TX Vref Scan disable
3564 06:02:43.779813 == TX Byte 0 ==
3565 06:02:43.783270 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3566 06:02:43.786348 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3567 06:02:43.789778 == TX Byte 1 ==
3568 06:02:43.793100 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3569 06:02:43.799685 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3570 06:02:43.799768
3571 06:02:43.799833 [DATLAT]
3572 06:02:43.799892 Freq=1200, CH1 RK1
3573 06:02:43.799981
3574 06:02:43.803269 DATLAT Default: 0xd
3575 06:02:43.803347 0, 0xFFFF, sum = 0
3576 06:02:43.806333 1, 0xFFFF, sum = 0
3577 06:02:43.806419 2, 0xFFFF, sum = 0
3578 06:02:43.809743 3, 0xFFFF, sum = 0
3579 06:02:43.813320 4, 0xFFFF, sum = 0
3580 06:02:43.813431 5, 0xFFFF, sum = 0
3581 06:02:43.816177 6, 0xFFFF, sum = 0
3582 06:02:43.816315 7, 0xFFFF, sum = 0
3583 06:02:43.819901 8, 0xFFFF, sum = 0
3584 06:02:43.819999 9, 0xFFFF, sum = 0
3585 06:02:43.822896 10, 0xFFFF, sum = 0
3586 06:02:43.823004 11, 0xFFFF, sum = 0
3587 06:02:43.826553 12, 0x0, sum = 1
3588 06:02:43.826662 13, 0x0, sum = 2
3589 06:02:43.830053 14, 0x0, sum = 3
3590 06:02:43.830161 15, 0x0, sum = 4
3591 06:02:43.832835 best_step = 13
3592 06:02:43.832953
3593 06:02:43.833053 ==
3594 06:02:43.836565 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 06:02:43.839448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 06:02:43.839559 ==
3597 06:02:43.839650 RX Vref Scan: 0
3598 06:02:43.843227
3599 06:02:43.843331 RX Vref 0 -> 0, step: 1
3600 06:02:43.843423
3601 06:02:43.846068 RX Delay -5 -> 252, step: 4
3602 06:02:43.849643 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3603 06:02:43.855963 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3604 06:02:43.859647 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3605 06:02:43.862636 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3606 06:02:43.866124 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3607 06:02:43.869578 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3608 06:02:43.875975 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3609 06:02:43.879581 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3610 06:02:43.882417 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3611 06:02:43.886145 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3612 06:02:43.889489 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3613 06:02:43.895626 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3614 06:02:43.899221 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3615 06:02:43.902543 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3616 06:02:43.905946 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3617 06:02:43.912582 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3618 06:02:43.912663 ==
3619 06:02:43.915693 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 06:02:43.919187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 06:02:43.919268 ==
3622 06:02:43.919331 DQS Delay:
3623 06:02:43.922447 DQS0 = 0, DQS1 = 0
3624 06:02:43.922526 DQM Delay:
3625 06:02:43.925762 DQM0 = 120, DQM1 = 118
3626 06:02:43.925843 DQ Delay:
3627 06:02:43.929136 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3628 06:02:43.932581 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3629 06:02:43.935548 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3630 06:02:43.939157 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3631 06:02:43.939238
3632 06:02:43.939300
3633 06:02:43.948821 [DQSOSCAuto] RK1, (LSB)MR18= 0x12ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3634 06:02:43.952390 CH1 RK1: MR19=403, MR18=12EE
3635 06:02:43.955867 CH1_RK1: MR19=0x403, MR18=0x12EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3636 06:02:43.958700 [RxdqsGatingPostProcess] freq 1200
3637 06:02:43.965832 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3638 06:02:43.968817 best DQS0 dly(2T, 0.5T) = (0, 11)
3639 06:02:43.972198 best DQS1 dly(2T, 0.5T) = (0, 11)
3640 06:02:43.975581 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3641 06:02:43.979038 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3642 06:02:43.982558 best DQS0 dly(2T, 0.5T) = (0, 11)
3643 06:02:43.985385 best DQS1 dly(2T, 0.5T) = (0, 11)
3644 06:02:43.989003 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3645 06:02:43.992389 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3646 06:02:43.995178 Pre-setting of DQS Precalculation
3647 06:02:43.998574 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3648 06:02:44.005535 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3649 06:02:44.012065 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3650 06:02:44.012145
3651 06:02:44.015583
3652 06:02:44.015663 [Calibration Summary] 2400 Mbps
3653 06:02:44.019203 CH 0, Rank 0
3654 06:02:44.019283 SW Impedance : PASS
3655 06:02:44.022068 DUTY Scan : NO K
3656 06:02:44.025791 ZQ Calibration : PASS
3657 06:02:44.025873 Jitter Meter : NO K
3658 06:02:44.029186 CBT Training : PASS
3659 06:02:44.031916 Write leveling : PASS
3660 06:02:44.031996 RX DQS gating : PASS
3661 06:02:44.035160 RX DQ/DQS(RDDQC) : PASS
3662 06:02:44.038476 TX DQ/DQS : PASS
3663 06:02:44.038559 RX DATLAT : PASS
3664 06:02:44.042376 RX DQ/DQS(Engine): PASS
3665 06:02:44.045617 TX OE : NO K
3666 06:02:44.045699 All Pass.
3667 06:02:44.045763
3668 06:02:44.045824 CH 0, Rank 1
3669 06:02:44.048762 SW Impedance : PASS
3670 06:02:44.051971 DUTY Scan : NO K
3671 06:02:44.052067 ZQ Calibration : PASS
3672 06:02:44.055432 Jitter Meter : NO K
3673 06:02:44.055514 CBT Training : PASS
3674 06:02:44.058823 Write leveling : PASS
3675 06:02:44.062318 RX DQS gating : PASS
3676 06:02:44.062400 RX DQ/DQS(RDDQC) : PASS
3677 06:02:44.065168 TX DQ/DQS : PASS
3678 06:02:44.068756 RX DATLAT : PASS
3679 06:02:44.068862 RX DQ/DQS(Engine): PASS
3680 06:02:44.072121 TX OE : NO K
3681 06:02:44.072233 All Pass.
3682 06:02:44.072330
3683 06:02:44.075522 CH 1, Rank 0
3684 06:02:44.075613 SW Impedance : PASS
3685 06:02:44.079113 DUTY Scan : NO K
3686 06:02:44.082038 ZQ Calibration : PASS
3687 06:02:44.082136 Jitter Meter : NO K
3688 06:02:44.085399 CBT Training : PASS
3689 06:02:44.088896 Write leveling : PASS
3690 06:02:44.089004 RX DQS gating : PASS
3691 06:02:44.092478 RX DQ/DQS(RDDQC) : PASS
3692 06:02:44.095346 TX DQ/DQS : PASS
3693 06:02:44.095480 RX DATLAT : PASS
3694 06:02:44.098496 RX DQ/DQS(Engine): PASS
3695 06:02:44.098630 TX OE : NO K
3696 06:02:44.102002 All Pass.
3697 06:02:44.102152
3698 06:02:44.102270 CH 1, Rank 1
3699 06:02:44.105595 SW Impedance : PASS
3700 06:02:44.105769 DUTY Scan : NO K
3701 06:02:44.108914 ZQ Calibration : PASS
3702 06:02:44.111662 Jitter Meter : NO K
3703 06:02:44.111744 CBT Training : PASS
3704 06:02:44.115216 Write leveling : PASS
3705 06:02:44.118873 RX DQS gating : PASS
3706 06:02:44.118955 RX DQ/DQS(RDDQC) : PASS
3707 06:02:44.121730 TX DQ/DQS : PASS
3708 06:02:44.125357 RX DATLAT : PASS
3709 06:02:44.125439 RX DQ/DQS(Engine): PASS
3710 06:02:44.128330 TX OE : NO K
3711 06:02:44.128412 All Pass.
3712 06:02:44.128476
3713 06:02:44.131737 DramC Write-DBI off
3714 06:02:44.135268 PER_BANK_REFRESH: Hybrid Mode
3715 06:02:44.135362 TX_TRACKING: ON
3716 06:02:44.144869 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3717 06:02:44.148161 [FAST_K] Save calibration result to emmc
3718 06:02:44.151783 dramc_set_vcore_voltage set vcore to 650000
3719 06:02:44.155363 Read voltage for 600, 5
3720 06:02:44.155582 Vio18 = 0
3721 06:02:44.155711 Vcore = 650000
3722 06:02:44.158565 Vdram = 0
3723 06:02:44.158707 Vddq = 0
3724 06:02:44.158815 Vmddr = 0
3725 06:02:44.164890 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3726 06:02:44.168325 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3727 06:02:44.171870 MEM_TYPE=3, freq_sel=19
3728 06:02:44.174901 sv_algorithm_assistance_LP4_1600
3729 06:02:44.178516 ============ PULL DRAM RESETB DOWN ============
3730 06:02:44.181690 ========== PULL DRAM RESETB DOWN end =========
3731 06:02:44.188147 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3732 06:02:44.191368 ===================================
3733 06:02:44.195078 LPDDR4 DRAM CONFIGURATION
3734 06:02:44.195187 ===================================
3735 06:02:44.198417 EX_ROW_EN[0] = 0x0
3736 06:02:44.201391 EX_ROW_EN[1] = 0x0
3737 06:02:44.201473 LP4Y_EN = 0x0
3738 06:02:44.204625 WORK_FSP = 0x0
3739 06:02:44.204734 WL = 0x2
3740 06:02:44.207898 RL = 0x2
3741 06:02:44.207985 BL = 0x2
3742 06:02:44.211152 RPST = 0x0
3743 06:02:44.211245 RD_PRE = 0x0
3744 06:02:44.214455 WR_PRE = 0x1
3745 06:02:44.214549 WR_PST = 0x0
3746 06:02:44.218058 DBI_WR = 0x0
3747 06:02:44.218160 DBI_RD = 0x0
3748 06:02:44.221665 OTF = 0x1
3749 06:02:44.224423 ===================================
3750 06:02:44.228021 ===================================
3751 06:02:44.228144 ANA top config
3752 06:02:44.231745 ===================================
3753 06:02:44.234470 DLL_ASYNC_EN = 0
3754 06:02:44.237964 ALL_SLAVE_EN = 1
3755 06:02:44.241438 NEW_RANK_MODE = 1
3756 06:02:44.241609 DLL_IDLE_MODE = 1
3757 06:02:44.245009 LP45_APHY_COMB_EN = 1
3758 06:02:44.247828 TX_ODT_DIS = 1
3759 06:02:44.251288 NEW_8X_MODE = 1
3760 06:02:44.254955 ===================================
3761 06:02:44.258512 ===================================
3762 06:02:44.261522 data_rate = 1200
3763 06:02:44.261900 CKR = 1
3764 06:02:44.264645 DQ_P2S_RATIO = 8
3765 06:02:44.268067 ===================================
3766 06:02:44.271642 CA_P2S_RATIO = 8
3767 06:02:44.275067 DQ_CA_OPEN = 0
3768 06:02:44.277943 DQ_SEMI_OPEN = 0
3769 06:02:44.281526 CA_SEMI_OPEN = 0
3770 06:02:44.281936 CA_FULL_RATE = 0
3771 06:02:44.285194 DQ_CKDIV4_EN = 1
3772 06:02:44.287971 CA_CKDIV4_EN = 1
3773 06:02:44.291431 CA_PREDIV_EN = 0
3774 06:02:44.294819 PH8_DLY = 0
3775 06:02:44.298213 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3776 06:02:44.298624 DQ_AAMCK_DIV = 4
3777 06:02:44.301621 CA_AAMCK_DIV = 4
3778 06:02:44.304846 CA_ADMCK_DIV = 4
3779 06:02:44.307938 DQ_TRACK_CA_EN = 0
3780 06:02:44.310915 CA_PICK = 600
3781 06:02:44.314576 CA_MCKIO = 600
3782 06:02:44.317704 MCKIO_SEMI = 0
3783 06:02:44.318120 PLL_FREQ = 2288
3784 06:02:44.321158 DQ_UI_PI_RATIO = 32
3785 06:02:44.324656 CA_UI_PI_RATIO = 0
3786 06:02:44.327582 ===================================
3787 06:02:44.330870 ===================================
3788 06:02:44.334160 memory_type:LPDDR4
3789 06:02:44.334882 GP_NUM : 10
3790 06:02:44.337493 SRAM_EN : 1
3791 06:02:44.340928 MD32_EN : 0
3792 06:02:44.344370 ===================================
3793 06:02:44.344945 [ANA_INIT] >>>>>>>>>>>>>>
3794 06:02:44.347858 <<<<<< [CONFIGURE PHASE]: ANA_TX
3795 06:02:44.351239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3796 06:02:44.354112 ===================================
3797 06:02:44.357667 data_rate = 1200,PCW = 0X5800
3798 06:02:44.361351 ===================================
3799 06:02:44.364198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3800 06:02:44.371162 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3801 06:02:44.374538 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3802 06:02:44.380927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3803 06:02:44.384482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3804 06:02:44.387373 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3805 06:02:44.390972 [ANA_INIT] flow start
3806 06:02:44.391392 [ANA_INIT] PLL >>>>>>>>
3807 06:02:44.394436 [ANA_INIT] PLL <<<<<<<<
3808 06:02:44.397370 [ANA_INIT] MIDPI >>>>>>>>
3809 06:02:44.397836 [ANA_INIT] MIDPI <<<<<<<<
3810 06:02:44.400722 [ANA_INIT] DLL >>>>>>>>
3811 06:02:44.404207 [ANA_INIT] flow end
3812 06:02:44.406994 ============ LP4 DIFF to SE enter ============
3813 06:02:44.410617 ============ LP4 DIFF to SE exit ============
3814 06:02:44.414174 [ANA_INIT] <<<<<<<<<<<<<
3815 06:02:44.417592 [Flow] Enable top DCM control >>>>>
3816 06:02:44.420556 [Flow] Enable top DCM control <<<<<
3817 06:02:44.424082 Enable DLL master slave shuffle
3818 06:02:44.426963 ==============================================================
3819 06:02:44.430499 Gating Mode config
3820 06:02:44.437352 ==============================================================
3821 06:02:44.437533 Config description:
3822 06:02:44.447335 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3823 06:02:44.454038 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3824 06:02:44.457546 SELPH_MODE 0: By rank 1: By Phase
3825 06:02:44.464194 ==============================================================
3826 06:02:44.467421 GAT_TRACK_EN = 1
3827 06:02:44.470392 RX_GATING_MODE = 2
3828 06:02:44.473731 RX_GATING_TRACK_MODE = 2
3829 06:02:44.477236 SELPH_MODE = 1
3830 06:02:44.480333 PICG_EARLY_EN = 1
3831 06:02:44.480771 VALID_LAT_VALUE = 1
3832 06:02:44.487643 ==============================================================
3833 06:02:44.490493 Enter into Gating configuration >>>>
3834 06:02:44.494093 Exit from Gating configuration <<<<
3835 06:02:44.497551 Enter into DVFS_PRE_config >>>>>
3836 06:02:44.507649 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3837 06:02:44.510599 Exit from DVFS_PRE_config <<<<<
3838 06:02:44.514057 Enter into PICG configuration >>>>
3839 06:02:44.516899 Exit from PICG configuration <<<<
3840 06:02:44.520506 [RX_INPUT] configuration >>>>>
3841 06:02:44.523942 [RX_INPUT] configuration <<<<<
3842 06:02:44.530279 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3843 06:02:44.533826 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3844 06:02:44.540273 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3845 06:02:44.546852 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3846 06:02:44.553968 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3847 06:02:44.560373 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3848 06:02:44.563887 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3849 06:02:44.567380 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3850 06:02:44.569984 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3851 06:02:44.576673 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3852 06:02:44.580623 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3853 06:02:44.583569 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3854 06:02:44.586897 ===================================
3855 06:02:44.589795 LPDDR4 DRAM CONFIGURATION
3856 06:02:44.593321 ===================================
3857 06:02:44.593742 EX_ROW_EN[0] = 0x0
3858 06:02:44.596734 EX_ROW_EN[1] = 0x0
3859 06:02:44.597149 LP4Y_EN = 0x0
3860 06:02:44.599884 WORK_FSP = 0x0
3861 06:02:44.603363 WL = 0x2
3862 06:02:44.603779 RL = 0x2
3863 06:02:44.606759 BL = 0x2
3864 06:02:44.607242 RPST = 0x0
3865 06:02:44.610207 RD_PRE = 0x0
3866 06:02:44.610730 WR_PRE = 0x1
3867 06:02:44.613703 WR_PST = 0x0
3868 06:02:44.614184 DBI_WR = 0x0
3869 06:02:44.617076 DBI_RD = 0x0
3870 06:02:44.617568 OTF = 0x1
3871 06:02:44.620183 ===================================
3872 06:02:44.623257 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3873 06:02:44.635529 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3874 06:02:44.635972 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3875 06:02:44.636752 ===================================
3876 06:02:44.640182 LPDDR4 DRAM CONFIGURATION
3877 06:02:44.642992 ===================================
3878 06:02:44.643434 EX_ROW_EN[0] = 0x10
3879 06:02:44.646592 EX_ROW_EN[1] = 0x0
3880 06:02:44.647014 LP4Y_EN = 0x0
3881 06:02:44.650080 WORK_FSP = 0x0
3882 06:02:44.650501 WL = 0x2
3883 06:02:44.652914 RL = 0x2
3884 06:02:44.656521 BL = 0x2
3885 06:02:44.656940 RPST = 0x0
3886 06:02:44.660082 RD_PRE = 0x0
3887 06:02:44.660555 WR_PRE = 0x1
3888 06:02:44.663477 WR_PST = 0x0
3889 06:02:44.663899 DBI_WR = 0x0
3890 06:02:44.666176 DBI_RD = 0x0
3891 06:02:44.666474 OTF = 0x1
3892 06:02:44.669600 ===================================
3893 06:02:44.676081 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3894 06:02:44.680433 nWR fixed to 30
3895 06:02:44.683239 [ModeRegInit_LP4] CH0 RK0
3896 06:02:44.683641 [ModeRegInit_LP4] CH0 RK1
3897 06:02:44.686833 [ModeRegInit_LP4] CH1 RK0
3898 06:02:44.690379 [ModeRegInit_LP4] CH1 RK1
3899 06:02:44.690790 match AC timing 17
3900 06:02:44.696849 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3901 06:02:44.700170 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3902 06:02:44.703327 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3903 06:02:44.710105 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3904 06:02:44.713269 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3905 06:02:44.713693 ==
3906 06:02:44.716429 Dram Type= 6, Freq= 0, CH_0, rank 0
3907 06:02:44.719818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3908 06:02:44.720269 ==
3909 06:02:44.726903 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3910 06:02:44.733106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3911 06:02:44.736603 [CA 0] Center 35 (5~66) winsize 62
3912 06:02:44.739967 [CA 1] Center 36 (5~67) winsize 63
3913 06:02:44.742918 [CA 2] Center 34 (3~65) winsize 63
3914 06:02:44.746272 [CA 3] Center 33 (2~64) winsize 63
3915 06:02:44.749883 [CA 4] Center 33 (2~64) winsize 63
3916 06:02:44.752873 [CA 5] Center 32 (2~63) winsize 62
3917 06:02:44.753330
3918 06:02:44.756272 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3919 06:02:44.756730
3920 06:02:44.759876 [CATrainingPosCal] consider 1 rank data
3921 06:02:44.763447 u2DelayCellTimex100 = 270/100 ps
3922 06:02:44.766266 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3923 06:02:44.769749 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3924 06:02:44.772635 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3925 06:02:44.775991 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3926 06:02:44.783004 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3927 06:02:44.786526 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3928 06:02:44.787049
3929 06:02:44.789389 CA PerBit enable=1, Macro0, CA PI delay=32
3930 06:02:44.789805
3931 06:02:44.793016 [CBTSetCACLKResult] CA Dly = 32
3932 06:02:44.793433 CS Dly: 4 (0~35)
3933 06:02:44.793764 ==
3934 06:02:44.796596 Dram Type= 6, Freq= 0, CH_0, rank 1
3935 06:02:44.799446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3936 06:02:44.802919 ==
3937 06:02:44.806441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3938 06:02:44.812713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3939 06:02:44.816628 [CA 0] Center 35 (5~66) winsize 62
3940 06:02:44.819332 [CA 1] Center 35 (5~66) winsize 62
3941 06:02:44.822744 [CA 2] Center 34 (3~65) winsize 63
3942 06:02:44.826290 [CA 3] Center 33 (3~64) winsize 62
3943 06:02:44.829666 [CA 4] Center 33 (2~64) winsize 63
3944 06:02:44.833077 [CA 5] Center 32 (2~63) winsize 62
3945 06:02:44.833495
3946 06:02:44.835915 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3947 06:02:44.836374
3948 06:02:44.839633 [CATrainingPosCal] consider 2 rank data
3949 06:02:44.842827 u2DelayCellTimex100 = 270/100 ps
3950 06:02:44.846195 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3951 06:02:44.849645 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3952 06:02:44.852996 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3953 06:02:44.859353 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3954 06:02:44.862579 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3955 06:02:44.865996 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3956 06:02:44.866409
3957 06:02:44.869687 CA PerBit enable=1, Macro0, CA PI delay=32
3958 06:02:44.870105
3959 06:02:44.872683 [CBTSetCACLKResult] CA Dly = 32
3960 06:02:44.873101 CS Dly: 4 (0~36)
3961 06:02:44.873428
3962 06:02:44.876185 ----->DramcWriteLeveling(PI) begin...
3963 06:02:44.876800 ==
3964 06:02:44.879481 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 06:02:44.886424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 06:02:44.886841 ==
3967 06:02:44.889520 Write leveling (Byte 0): 34 => 34
3968 06:02:44.893257 Write leveling (Byte 1): 32 => 32
3969 06:02:44.893783 DramcWriteLeveling(PI) end<-----
3970 06:02:44.894122
3971 06:02:44.895858 ==
3972 06:02:44.899470 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 06:02:44.903142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 06:02:44.903559 ==
3975 06:02:44.906025 [Gating] SW mode calibration
3976 06:02:44.913056 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3977 06:02:44.915913 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3978 06:02:44.922448 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 06:02:44.926489 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 06:02:44.929404 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3981 06:02:44.936277 0 9 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
3982 06:02:44.939495 0 9 16 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
3983 06:02:44.943075 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 06:02:44.949223 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 06:02:44.952842 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 06:02:44.956354 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 06:02:44.962641 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 06:02:44.965986 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 06:02:44.969469 0 10 12 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
3990 06:02:44.972883 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
3991 06:02:44.979178 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 06:02:44.982528 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 06:02:44.985852 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 06:02:44.992593 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 06:02:44.996038 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 06:02:44.998885 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3997 06:02:45.005919 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3998 06:02:45.009159 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 06:02:45.012566 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 06:02:45.019052 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 06:02:45.022604 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 06:02:45.025399 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 06:02:45.032372 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 06:02:45.035619 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 06:02:45.038664 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 06:02:45.045575 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 06:02:45.048891 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 06:02:45.052230 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 06:02:45.058470 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 06:02:45.062093 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 06:02:45.064979 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 06:02:45.072015 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 06:02:45.075601 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4014 06:02:45.078439 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 06:02:45.081824 Total UI for P1: 0, mck2ui 16
4016 06:02:45.085289 best dqsien dly found for B0: ( 0, 13, 12)
4017 06:02:45.088837 Total UI for P1: 0, mck2ui 16
4018 06:02:45.091686 best dqsien dly found for B1: ( 0, 13, 14)
4019 06:02:45.095212 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4020 06:02:45.098728 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4021 06:02:45.099147
4022 06:02:45.105061 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4023 06:02:45.108456 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4024 06:02:45.111606 [Gating] SW calibration Done
4025 06:02:45.112021 ==
4026 06:02:45.114784 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 06:02:45.118538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 06:02:45.118960 ==
4029 06:02:45.119325 RX Vref Scan: 0
4030 06:02:45.119640
4031 06:02:45.121881 RX Vref 0 -> 0, step: 1
4032 06:02:45.122297
4033 06:02:45.125241 RX Delay -230 -> 252, step: 16
4034 06:02:45.128483 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4035 06:02:45.131536 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4036 06:02:45.137950 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4037 06:02:45.141214 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4038 06:02:45.144980 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4039 06:02:45.147922 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4040 06:02:45.154795 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4041 06:02:45.158105 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4042 06:02:45.161474 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4043 06:02:45.164823 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4044 06:02:45.171423 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4045 06:02:45.174311 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4046 06:02:45.177929 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4047 06:02:45.181551 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4048 06:02:45.188057 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4049 06:02:45.191415 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4050 06:02:45.191860 ==
4051 06:02:45.194290 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 06:02:45.197857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 06:02:45.198289 ==
4054 06:02:45.198613 DQS Delay:
4055 06:02:45.200937 DQS0 = 0, DQS1 = 0
4056 06:02:45.201354 DQM Delay:
4057 06:02:45.204395 DQM0 = 52, DQM1 = 46
4058 06:02:45.204816 DQ Delay:
4059 06:02:45.208007 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4060 06:02:45.211576 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4061 06:02:45.214544 DQ8 =41, DQ9 =33, DQ10 =49, DQ11 =41
4062 06:02:45.218182 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4063 06:02:45.218604
4064 06:02:45.218927
4065 06:02:45.219227 ==
4066 06:02:45.220954 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 06:02:45.224516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 06:02:45.227492 ==
4069 06:02:45.228187
4070 06:02:45.228815
4071 06:02:45.229380 TX Vref Scan disable
4072 06:02:45.230759 == TX Byte 0 ==
4073 06:02:45.234161 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4074 06:02:45.237518 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4075 06:02:45.240764 == TX Byte 1 ==
4076 06:02:45.244618 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4077 06:02:45.247985 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4078 06:02:45.251002 ==
4079 06:02:45.254597 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 06:02:45.257694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 06:02:45.258274 ==
4082 06:02:45.258802
4083 06:02:45.259282
4084 06:02:45.260861 TX Vref Scan disable
4085 06:02:45.261459 == TX Byte 0 ==
4086 06:02:45.267689 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4087 06:02:45.271094 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4088 06:02:45.271718 == TX Byte 1 ==
4089 06:02:45.277540 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4090 06:02:45.280909 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4091 06:02:45.281327
4092 06:02:45.281651 [DATLAT]
4093 06:02:45.284258 Freq=600, CH0 RK0
4094 06:02:45.284726
4095 06:02:45.285068 DATLAT Default: 0x9
4096 06:02:45.287326 0, 0xFFFF, sum = 0
4097 06:02:45.287945 1, 0xFFFF, sum = 0
4098 06:02:45.291003 2, 0xFFFF, sum = 0
4099 06:02:45.294378 3, 0xFFFF, sum = 0
4100 06:02:45.294789 4, 0xFFFF, sum = 0
4101 06:02:45.297610 5, 0xFFFF, sum = 0
4102 06:02:45.297939 6, 0xFFFF, sum = 0
4103 06:02:45.301147 7, 0xFFFF, sum = 0
4104 06:02:45.301381 8, 0x0, sum = 1
4105 06:02:45.301562 9, 0x0, sum = 2
4106 06:02:45.303997 10, 0x0, sum = 3
4107 06:02:45.304347 11, 0x0, sum = 4
4108 06:02:45.307426 best_step = 9
4109 06:02:45.307624
4110 06:02:45.307764 ==
4111 06:02:45.310317 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 06:02:45.314023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 06:02:45.314204 ==
4114 06:02:45.317559 RX Vref Scan: 1
4115 06:02:45.317735
4116 06:02:45.317874 RX Vref 0 -> 0, step: 1
4117 06:02:45.318003
4118 06:02:45.320500 RX Delay -163 -> 252, step: 8
4119 06:02:45.320678
4120 06:02:45.324038 Set Vref, RX VrefLevel [Byte0]: 56
4121 06:02:45.327612 [Byte1]: 49
4122 06:02:45.331183
4123 06:02:45.331424 Final RX Vref Byte 0 = 56 to rank0
4124 06:02:45.334747 Final RX Vref Byte 1 = 49 to rank0
4125 06:02:45.337500 Final RX Vref Byte 0 = 56 to rank1
4126 06:02:45.341154 Final RX Vref Byte 1 = 49 to rank1==
4127 06:02:45.344573 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 06:02:45.351157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 06:02:45.351394 ==
4130 06:02:45.351540 DQS Delay:
4131 06:02:45.354634 DQS0 = 0, DQS1 = 0
4132 06:02:45.354921 DQM Delay:
4133 06:02:45.355172 DQM0 = 53, DQM1 = 46
4134 06:02:45.357388 DQ Delay:
4135 06:02:45.360988 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4136 06:02:45.364569 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4137 06:02:45.367362 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4138 06:02:45.370974 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4139 06:02:45.371184
4140 06:02:45.371349
4141 06:02:45.377549 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f62, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4142 06:02:45.381139 CH0 RK0: MR19=808, MR18=6F62
4143 06:02:45.387547 CH0_RK0: MR19=0x808, MR18=0x6F62, DQSOSC=389, MR23=63, INC=173, DEC=115
4144 06:02:45.387970
4145 06:02:45.391200 ----->DramcWriteLeveling(PI) begin...
4146 06:02:45.391624 ==
4147 06:02:45.394235 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 06:02:45.397659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 06:02:45.398245 ==
4150 06:02:45.401078 Write leveling (Byte 0): 35 => 35
4151 06:02:45.404264 Write leveling (Byte 1): 31 => 31
4152 06:02:45.407758 DramcWriteLeveling(PI) end<-----
4153 06:02:45.408357
4154 06:02:45.408894 ==
4155 06:02:45.411003 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 06:02:45.414226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 06:02:45.414756 ==
4158 06:02:45.418074 [Gating] SW mode calibration
4159 06:02:45.424212 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4160 06:02:45.431262 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4161 06:02:45.434554 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 06:02:45.437988 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 06:02:45.444256 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4164 06:02:45.447877 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4165 06:02:45.451268 0 9 16 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
4166 06:02:45.457797 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 06:02:45.461157 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 06:02:45.464181 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 06:02:45.471174 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 06:02:45.473933 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 06:02:45.477269 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 06:02:45.484542 0 10 12 | B1->B0 | 2929 2929 | 0 0 | (0 0) (0 0)
4173 06:02:45.487457 0 10 16 | B1->B0 | 3a3a 4343 | 0 0 | (0 0) (0 0)
4174 06:02:45.490979 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 06:02:45.497423 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 06:02:45.500344 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 06:02:45.503948 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 06:02:45.510514 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 06:02:45.513863 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 06:02:45.517146 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4181 06:02:45.523917 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 06:02:45.527644 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 06:02:45.530670 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 06:02:45.537340 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 06:02:45.540210 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 06:02:45.543268 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 06:02:45.549968 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 06:02:45.553527 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 06:02:45.556919 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 06:02:45.563390 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 06:02:45.566964 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 06:02:45.570042 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 06:02:45.576831 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 06:02:45.580221 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 06:02:45.583434 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 06:02:45.590182 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4197 06:02:45.593025 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 06:02:45.596765 Total UI for P1: 0, mck2ui 16
4199 06:02:45.600365 best dqsien dly found for B0: ( 0, 13, 12)
4200 06:02:45.603273 Total UI for P1: 0, mck2ui 16
4201 06:02:45.606798 best dqsien dly found for B1: ( 0, 13, 12)
4202 06:02:45.610349 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4203 06:02:45.613274 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4204 06:02:45.613695
4205 06:02:45.616725 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4206 06:02:45.620083 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4207 06:02:45.623646 [Gating] SW calibration Done
4208 06:02:45.624094 ==
4209 06:02:45.626476 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 06:02:45.629567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 06:02:45.630214 ==
4212 06:02:45.633263 RX Vref Scan: 0
4213 06:02:45.633923
4214 06:02:45.636614 RX Vref 0 -> 0, step: 1
4215 06:02:45.637143
4216 06:02:45.640222 RX Delay -230 -> 252, step: 16
4217 06:02:45.642990 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4218 06:02:45.646553 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4219 06:02:45.649561 iDelay=218, Bit 2, Center 57 (-86 ~ 201) 288
4220 06:02:45.653191 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4221 06:02:45.659421 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4222 06:02:45.662962 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4223 06:02:45.666298 iDelay=218, Bit 6, Center 73 (-70 ~ 217) 288
4224 06:02:45.669642 iDelay=218, Bit 7, Center 73 (-70 ~ 217) 288
4225 06:02:45.672894 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4226 06:02:45.679190 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4227 06:02:45.682850 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4228 06:02:45.685932 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4229 06:02:45.689199 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4230 06:02:45.696329 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4231 06:02:45.699162 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4232 06:02:45.702932 iDelay=218, Bit 15, Center 57 (-86 ~ 201) 288
4233 06:02:45.703223 ==
4234 06:02:45.705896 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 06:02:45.709665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 06:02:45.709929 ==
4237 06:02:45.712454 DQS Delay:
4238 06:02:45.712771 DQS0 = 0, DQS1 = 0
4239 06:02:45.713148 DQM Delay:
4240 06:02:45.715871 DQM0 = 60, DQM1 = 48
4241 06:02:45.716203 DQ Delay:
4242 06:02:45.719576 DQ0 =57, DQ1 =57, DQ2 =57, DQ3 =57
4243 06:02:45.722933 DQ4 =65, DQ5 =41, DQ6 =73, DQ7 =73
4244 06:02:45.725604 DQ8 =33, DQ9 =33, DQ10 =57, DQ11 =33
4245 06:02:45.729347 DQ12 =57, DQ13 =57, DQ14 =57, DQ15 =57
4246 06:02:45.729609
4247 06:02:45.729812
4248 06:02:45.730002 ==
4249 06:02:45.732627 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 06:02:45.739481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 06:02:45.739736 ==
4252 06:02:45.739935
4253 06:02:45.740120
4254 06:02:45.740325 TX Vref Scan disable
4255 06:02:45.743073 == TX Byte 0 ==
4256 06:02:45.746937 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4257 06:02:45.749792 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4258 06:02:45.753517 == TX Byte 1 ==
4259 06:02:45.756350 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4260 06:02:45.762779 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4261 06:02:45.763033 ==
4262 06:02:45.766340 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 06:02:45.769812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 06:02:45.770167 ==
4265 06:02:45.770428
4266 06:02:45.770670
4267 06:02:45.773500 TX Vref Scan disable
4268 06:02:45.776541 == TX Byte 0 ==
4269 06:02:45.779927 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4270 06:02:45.783416 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4271 06:02:45.786427 == TX Byte 1 ==
4272 06:02:45.789887 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4273 06:02:45.793256 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4274 06:02:45.793676
4275 06:02:45.794007 [DATLAT]
4276 06:02:45.796472 Freq=600, CH0 RK1
4277 06:02:45.796895
4278 06:02:45.799871 DATLAT Default: 0x9
4279 06:02:45.800339 0, 0xFFFF, sum = 0
4280 06:02:45.802965 1, 0xFFFF, sum = 0
4281 06:02:45.803462 2, 0xFFFF, sum = 0
4282 06:02:45.806320 3, 0xFFFF, sum = 0
4283 06:02:45.806763 4, 0xFFFF, sum = 0
4284 06:02:45.809699 5, 0xFFFF, sum = 0
4285 06:02:45.810183 6, 0xFFFF, sum = 0
4286 06:02:45.812827 7, 0xFFFF, sum = 0
4287 06:02:45.813285 8, 0x0, sum = 1
4288 06:02:45.816168 9, 0x0, sum = 2
4289 06:02:45.816703 10, 0x0, sum = 3
4290 06:02:45.817058 11, 0x0, sum = 4
4291 06:02:45.819547 best_step = 9
4292 06:02:45.820048
4293 06:02:45.820526 ==
4294 06:02:45.822852 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 06:02:45.826536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 06:02:45.826970 ==
4297 06:02:45.829562 RX Vref Scan: 0
4298 06:02:45.829977
4299 06:02:45.830303 RX Vref 0 -> 0, step: 1
4300 06:02:45.833018
4301 06:02:45.833432 RX Delay -163 -> 252, step: 8
4302 06:02:45.840359 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4303 06:02:45.843592 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4304 06:02:45.846967 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4305 06:02:45.849849 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4306 06:02:45.853807 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4307 06:02:45.860422 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4308 06:02:45.863331 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4309 06:02:45.866769 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4310 06:02:45.870279 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4311 06:02:45.876323 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4312 06:02:45.879999 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4313 06:02:45.883288 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4314 06:02:45.886119 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4315 06:02:45.889772 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4316 06:02:45.896233 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4317 06:02:45.899691 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4318 06:02:45.899772 ==
4319 06:02:45.903018 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 06:02:45.906233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 06:02:45.906315 ==
4322 06:02:45.909903 DQS Delay:
4323 06:02:45.909984 DQS0 = 0, DQS1 = 0
4324 06:02:45.910048 DQM Delay:
4325 06:02:45.913001 DQM0 = 53, DQM1 = 46
4326 06:02:45.913082 DQ Delay:
4327 06:02:45.916215 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4328 06:02:45.919520 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4329 06:02:45.922900 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4330 06:02:45.925839 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4331 06:02:45.925920
4332 06:02:45.925982
4333 06:02:45.935864 [DQSOSCAuto] RK1, (LSB)MR18= 0x6223, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4334 06:02:45.935955 CH0 RK1: MR19=808, MR18=6223
4335 06:02:45.942770 CH0_RK1: MR19=0x808, MR18=0x6223, DQSOSC=391, MR23=63, INC=171, DEC=114
4336 06:02:45.946193 [RxdqsGatingPostProcess] freq 600
4337 06:02:45.952204 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4338 06:02:45.955627 Pre-setting of DQS Precalculation
4339 06:02:45.958945 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4340 06:02:45.959026 ==
4341 06:02:45.962156 Dram Type= 6, Freq= 0, CH_1, rank 0
4342 06:02:45.969522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 06:02:45.969608 ==
4344 06:02:45.972406 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4345 06:02:45.979181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4346 06:02:45.982439 [CA 0] Center 36 (5~67) winsize 63
4347 06:02:45.986030 [CA 1] Center 36 (5~67) winsize 63
4348 06:02:45.989222 [CA 2] Center 34 (4~65) winsize 62
4349 06:02:45.992713 [CA 3] Center 34 (4~65) winsize 62
4350 06:02:45.995596 [CA 4] Center 34 (4~65) winsize 62
4351 06:02:45.999294 [CA 5] Center 34 (3~65) winsize 63
4352 06:02:45.999392
4353 06:02:46.002306 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4354 06:02:46.002387
4355 06:02:46.005888 [CATrainingPosCal] consider 1 rank data
4356 06:02:46.008574 u2DelayCellTimex100 = 270/100 ps
4357 06:02:46.012585 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4358 06:02:46.019010 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4359 06:02:46.022510 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4360 06:02:46.025330 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4361 06:02:46.028786 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4362 06:02:46.032094 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4363 06:02:46.032198
4364 06:02:46.035255 CA PerBit enable=1, Macro0, CA PI delay=34
4365 06:02:46.035340
4366 06:02:46.038842 [CBTSetCACLKResult] CA Dly = 34
4367 06:02:46.038923 CS Dly: 5 (0~36)
4368 06:02:46.042409 ==
4369 06:02:46.045262 Dram Type= 6, Freq= 0, CH_1, rank 1
4370 06:02:46.048720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 06:02:46.048803 ==
4372 06:02:46.052171 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 06:02:46.058631 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4374 06:02:46.062188 [CA 0] Center 36 (5~67) winsize 63
4375 06:02:46.065854 [CA 1] Center 36 (5~67) winsize 63
4376 06:02:46.069492 [CA 2] Center 34 (4~65) winsize 62
4377 06:02:46.072271 [CA 3] Center 34 (4~65) winsize 62
4378 06:02:46.075802 [CA 4] Center 34 (4~65) winsize 62
4379 06:02:46.079493 [CA 5] Center 34 (3~65) winsize 63
4380 06:02:46.079573
4381 06:02:46.082113 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4382 06:02:46.082193
4383 06:02:46.085447 [CATrainingPosCal] consider 2 rank data
4384 06:02:46.088823 u2DelayCellTimex100 = 270/100 ps
4385 06:02:46.092028 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4386 06:02:46.099083 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4387 06:02:46.102358 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4388 06:02:46.105531 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4389 06:02:46.109043 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 06:02:46.111916 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4391 06:02:46.111997
4392 06:02:46.115605 CA PerBit enable=1, Macro0, CA PI delay=34
4393 06:02:46.115686
4394 06:02:46.119136 [CBTSetCACLKResult] CA Dly = 34
4395 06:02:46.122270 CS Dly: 6 (0~38)
4396 06:02:46.122351
4397 06:02:46.125234 ----->DramcWriteLeveling(PI) begin...
4398 06:02:46.125316 ==
4399 06:02:46.128802 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 06:02:46.132353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 06:02:46.132472 ==
4402 06:02:46.135832 Write leveling (Byte 0): 27 => 27
4403 06:02:46.138596 Write leveling (Byte 1): 31 => 31
4404 06:02:46.142004 DramcWriteLeveling(PI) end<-----
4405 06:02:46.142085
4406 06:02:46.142147 ==
4407 06:02:46.145315 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 06:02:46.148900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 06:02:46.148981 ==
4410 06:02:46.151756 [Gating] SW mode calibration
4411 06:02:46.158917 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4412 06:02:46.165472 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4413 06:02:46.168823 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 06:02:46.171896 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 06:02:46.178805 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4416 06:02:46.181802 0 9 12 | B1->B0 | 3232 2d2d | 0 0 | (0 0) (0 0)
4417 06:02:46.185267 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 06:02:46.191757 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 06:02:46.195418 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 06:02:46.198313 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 06:02:46.205439 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 06:02:46.208225 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 06:02:46.211662 0 10 8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4424 06:02:46.218108 0 10 12 | B1->B0 | 3737 3a3a | 0 0 | (1 1) (0 0)
4425 06:02:46.221433 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4426 06:02:46.225110 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 06:02:46.228128 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 06:02:46.234909 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 06:02:46.238396 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 06:02:46.241732 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 06:02:46.248139 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 06:02:46.251326 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4433 06:02:46.255416 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 06:02:46.261687 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 06:02:46.265395 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 06:02:46.268748 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 06:02:46.275364 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 06:02:46.278862 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 06:02:46.282228 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 06:02:46.288718 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 06:02:46.291575 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 06:02:46.295050 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 06:02:46.301466 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 06:02:46.305221 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 06:02:46.307973 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 06:02:46.315203 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 06:02:46.317898 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 06:02:46.321381 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4449 06:02:46.324914 Total UI for P1: 0, mck2ui 16
4450 06:02:46.327789 best dqsien dly found for B0: ( 0, 13, 10)
4451 06:02:46.334932 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 06:02:46.335356 Total UI for P1: 0, mck2ui 16
4453 06:02:46.341612 best dqsien dly found for B1: ( 0, 13, 12)
4454 06:02:46.344961 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4455 06:02:46.347797 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4456 06:02:46.348219
4457 06:02:46.351079 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4458 06:02:46.354414 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4459 06:02:46.357671 [Gating] SW calibration Done
4460 06:02:46.358090 ==
4461 06:02:46.361429 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 06:02:46.364388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 06:02:46.364843 ==
4464 06:02:46.367594 RX Vref Scan: 0
4465 06:02:46.368013
4466 06:02:46.368385 RX Vref 0 -> 0, step: 1
4467 06:02:46.368703
4468 06:02:46.371110 RX Delay -230 -> 252, step: 16
4469 06:02:46.377983 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4470 06:02:46.381115 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4471 06:02:46.384387 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4472 06:02:46.387691 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4473 06:02:46.391271 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4474 06:02:46.397687 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4475 06:02:46.401128 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4476 06:02:46.404692 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4477 06:02:46.407571 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4478 06:02:46.414669 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4479 06:02:46.417622 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4480 06:02:46.421078 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4481 06:02:46.424582 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4482 06:02:46.430901 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4483 06:02:46.434297 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4484 06:02:46.437914 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4485 06:02:46.438472 ==
4486 06:02:46.440748 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 06:02:46.444163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 06:02:46.444680 ==
4489 06:02:46.447673 DQS Delay:
4490 06:02:46.448090 DQS0 = 0, DQS1 = 0
4491 06:02:46.450924 DQM Delay:
4492 06:02:46.451533 DQM0 = 50, DQM1 = 46
4493 06:02:46.452194 DQ Delay:
4494 06:02:46.454288 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4495 06:02:46.457921 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4496 06:02:46.460745 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4497 06:02:46.464259 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4498 06:02:46.464983
4499 06:02:46.465584
4500 06:02:46.467214 ==
4501 06:02:46.467709 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 06:02:46.474275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 06:02:46.474712 ==
4504 06:02:46.475045
4505 06:02:46.475414
4506 06:02:46.477125 TX Vref Scan disable
4507 06:02:46.477544 == TX Byte 0 ==
4508 06:02:46.483923 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4509 06:02:46.487013 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4510 06:02:46.487449 == TX Byte 1 ==
4511 06:02:46.493581 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4512 06:02:46.496895 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4513 06:02:46.497319 ==
4514 06:02:46.500640 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 06:02:46.503723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 06:02:46.504145 ==
4517 06:02:46.504538
4518 06:02:46.504853
4519 06:02:46.507090 TX Vref Scan disable
4520 06:02:46.510617 == TX Byte 0 ==
4521 06:02:46.513558 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4522 06:02:46.517145 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4523 06:02:46.520554 == TX Byte 1 ==
4524 06:02:46.523759 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4525 06:02:46.526894 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4526 06:02:46.527318
4527 06:02:46.530023 [DATLAT]
4528 06:02:46.530442 Freq=600, CH1 RK0
4529 06:02:46.530777
4530 06:02:46.533531 DATLAT Default: 0x9
4531 06:02:46.534104 0, 0xFFFF, sum = 0
4532 06:02:46.537144 1, 0xFFFF, sum = 0
4533 06:02:46.537569 2, 0xFFFF, sum = 0
4534 06:02:46.539919 3, 0xFFFF, sum = 0
4535 06:02:46.540377 4, 0xFFFF, sum = 0
4536 06:02:46.543500 5, 0xFFFF, sum = 0
4537 06:02:46.543923 6, 0xFFFF, sum = 0
4538 06:02:46.547150 7, 0xFFFF, sum = 0
4539 06:02:46.547578 8, 0x0, sum = 1
4540 06:02:46.550020 9, 0x0, sum = 2
4541 06:02:46.550445 10, 0x0, sum = 3
4542 06:02:46.553511 11, 0x0, sum = 4
4543 06:02:46.553938 best_step = 9
4544 06:02:46.554271
4545 06:02:46.554581 ==
4546 06:02:46.556951 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 06:02:46.560273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 06:02:46.563760 ==
4549 06:02:46.564182 RX Vref Scan: 1
4550 06:02:46.564575
4551 06:02:46.566687 RX Vref 0 -> 0, step: 1
4552 06:02:46.567104
4553 06:02:46.570344 RX Delay -163 -> 252, step: 8
4554 06:02:46.570763
4555 06:02:46.573759 Set Vref, RX VrefLevel [Byte0]: 54
4556 06:02:46.576558 [Byte1]: 53
4557 06:02:46.576979
4558 06:02:46.580039 Final RX Vref Byte 0 = 54 to rank0
4559 06:02:46.583649 Final RX Vref Byte 1 = 53 to rank0
4560 06:02:46.586519 Final RX Vref Byte 0 = 54 to rank1
4561 06:02:46.589969 Final RX Vref Byte 1 = 53 to rank1==
4562 06:02:46.593357 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 06:02:46.596618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 06:02:46.597041 ==
4565 06:02:46.599863 DQS Delay:
4566 06:02:46.600330 DQS0 = 0, DQS1 = 0
4567 06:02:46.600671 DQM Delay:
4568 06:02:46.603526 DQM0 = 48, DQM1 = 45
4569 06:02:46.603943 DQ Delay:
4570 06:02:46.606366 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =44
4571 06:02:46.609891 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4572 06:02:46.613174 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4573 06:02:46.616696 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4574 06:02:46.617116
4575 06:02:46.617443
4576 06:02:46.626656 [DQSOSCAuto] RK0, (LSB)MR18= 0x486e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4577 06:02:46.627082 CH1 RK0: MR19=808, MR18=486E
4578 06:02:46.632726 CH1_RK0: MR19=0x808, MR18=0x486E, DQSOSC=389, MR23=63, INC=173, DEC=115
4579 06:02:46.633265
4580 06:02:46.636461 ----->DramcWriteLeveling(PI) begin...
4581 06:02:46.639686 ==
4582 06:02:46.640106 Dram Type= 6, Freq= 0, CH_1, rank 1
4583 06:02:46.646459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 06:02:46.646884 ==
4585 06:02:46.649591 Write leveling (Byte 0): 28 => 28
4586 06:02:46.653112 Write leveling (Byte 1): 31 => 31
4587 06:02:46.656243 DramcWriteLeveling(PI) end<-----
4588 06:02:46.656708
4589 06:02:46.657042 ==
4590 06:02:46.659793 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 06:02:46.662480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 06:02:46.663009 ==
4593 06:02:46.666132 [Gating] SW mode calibration
4594 06:02:46.673152 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4595 06:02:46.675894 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4596 06:02:46.682774 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 06:02:46.686453 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4598 06:02:46.689133 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4599 06:02:46.696337 0 9 12 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 0)
4600 06:02:46.699074 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4601 06:02:46.702427 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 06:02:46.709444 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 06:02:46.712385 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 06:02:46.715984 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 06:02:46.722861 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 06:02:46.725623 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4607 06:02:46.729150 0 10 12 | B1->B0 | 3939 3939 | 1 0 | (0 0) (0 0)
4608 06:02:46.735912 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4609 06:02:46.739275 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 06:02:46.742253 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 06:02:46.749081 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 06:02:46.752448 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 06:02:46.756013 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 06:02:46.762650 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 06:02:46.766141 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 06:02:46.769284 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 06:02:46.775426 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 06:02:46.779253 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 06:02:46.782253 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 06:02:46.789381 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 06:02:46.791996 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 06:02:46.795625 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 06:02:46.802192 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 06:02:46.805671 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 06:02:46.809205 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 06:02:46.815541 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 06:02:46.819232 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 06:02:46.822534 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 06:02:46.825297 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 06:02:46.832213 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 06:02:46.835702 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 06:02:46.838668 Total UI for P1: 0, mck2ui 16
4633 06:02:46.841922 best dqsien dly found for B0: ( 0, 13, 10)
4634 06:02:46.845324 Total UI for P1: 0, mck2ui 16
4635 06:02:46.848806 best dqsien dly found for B1: ( 0, 13, 10)
4636 06:02:46.852170 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4637 06:02:46.855047 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4638 06:02:46.855684
4639 06:02:46.858390 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4640 06:02:46.865149 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4641 06:02:46.865684 [Gating] SW calibration Done
4642 06:02:46.866063 ==
4643 06:02:46.868659 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 06:02:46.875344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 06:02:46.875774 ==
4646 06:02:46.876104 RX Vref Scan: 0
4647 06:02:46.876454
4648 06:02:46.878792 RX Vref 0 -> 0, step: 1
4649 06:02:46.879200
4650 06:02:46.882018 RX Delay -230 -> 252, step: 16
4651 06:02:46.885419 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4652 06:02:46.888483 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4653 06:02:46.894964 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4654 06:02:46.898494 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4655 06:02:46.901447 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4656 06:02:46.904836 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4657 06:02:46.907985 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4658 06:02:46.914344 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4659 06:02:46.917888 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4660 06:02:46.921307 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4661 06:02:46.924745 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4662 06:02:46.931171 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4663 06:02:46.934613 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4664 06:02:46.938035 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4665 06:02:46.940855 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4666 06:02:46.947583 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4667 06:02:46.948150 ==
4668 06:02:46.950952 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 06:02:46.954417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 06:02:46.954957 ==
4671 06:02:46.955430 DQS Delay:
4672 06:02:46.957319 DQS0 = 0, DQS1 = 0
4673 06:02:46.957809 DQM Delay:
4674 06:02:46.960882 DQM0 = 49, DQM1 = 47
4675 06:02:46.961308 DQ Delay:
4676 06:02:46.964234 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4677 06:02:46.967439 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4678 06:02:46.970895 DQ8 =25, DQ9 =41, DQ10 =49, DQ11 =41
4679 06:02:46.974254 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4680 06:02:46.974671
4681 06:02:46.975002
4682 06:02:46.975308 ==
4683 06:02:46.977735 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 06:02:46.980677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 06:02:46.981243 ==
4686 06:02:46.984231
4687 06:02:46.984704
4688 06:02:46.985042 TX Vref Scan disable
4689 06:02:46.987660 == TX Byte 0 ==
4690 06:02:46.990777 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4691 06:02:46.994211 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4692 06:02:46.996949 == TX Byte 1 ==
4693 06:02:47.000452 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4694 06:02:47.003959 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4695 06:02:47.007324 ==
4696 06:02:47.007512 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 06:02:47.013648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 06:02:47.013873 ==
4699 06:02:47.014019
4700 06:02:47.014151
4701 06:02:47.016879 TX Vref Scan disable
4702 06:02:47.017061 == TX Byte 0 ==
4703 06:02:47.023583 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4704 06:02:47.027335 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4705 06:02:47.027598 == TX Byte 1 ==
4706 06:02:47.033985 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4707 06:02:47.037045 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4708 06:02:47.037258
4709 06:02:47.037423 [DATLAT]
4710 06:02:47.040399 Freq=600, CH1 RK1
4711 06:02:47.040655
4712 06:02:47.040858 DATLAT Default: 0x9
4713 06:02:47.043818 0, 0xFFFF, sum = 0
4714 06:02:47.044078 1, 0xFFFF, sum = 0
4715 06:02:47.047365 2, 0xFFFF, sum = 0
4716 06:02:47.047702 3, 0xFFFF, sum = 0
4717 06:02:47.050411 4, 0xFFFF, sum = 0
4718 06:02:47.050834 5, 0xFFFF, sum = 0
4719 06:02:47.053977 6, 0xFFFF, sum = 0
4720 06:02:47.057358 7, 0xFFFF, sum = 0
4721 06:02:47.057875 8, 0x0, sum = 1
4722 06:02:47.058260 9, 0x0, sum = 2
4723 06:02:47.060785 10, 0x0, sum = 3
4724 06:02:47.061262 11, 0x0, sum = 4
4725 06:02:47.063461 best_step = 9
4726 06:02:47.063881
4727 06:02:47.064460 ==
4728 06:02:47.067219 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 06:02:47.070668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 06:02:47.071083 ==
4731 06:02:47.073990 RX Vref Scan: 0
4732 06:02:47.074405
4733 06:02:47.074734 RX Vref 0 -> 0, step: 1
4734 06:02:47.075046
4735 06:02:47.077339 RX Delay -179 -> 252, step: 8
4736 06:02:47.083966 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4737 06:02:47.087725 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4738 06:02:47.091300 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4739 06:02:47.094730 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4740 06:02:47.097595 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4741 06:02:47.103969 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4742 06:02:47.107709 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4743 06:02:47.111069 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4744 06:02:47.113738 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4745 06:02:47.117472 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4746 06:02:47.124336 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4747 06:02:47.128019 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4748 06:02:47.130442 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4749 06:02:47.134048 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4750 06:02:47.141098 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4751 06:02:47.144022 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4752 06:02:47.144481 ==
4753 06:02:47.147672 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 06:02:47.150629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 06:02:47.151063 ==
4756 06:02:47.154144 DQS Delay:
4757 06:02:47.154576 DQS0 = 0, DQS1 = 0
4758 06:02:47.154904 DQM Delay:
4759 06:02:47.157445 DQM0 = 49, DQM1 = 45
4760 06:02:47.157856 DQ Delay:
4761 06:02:47.160250 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4762 06:02:47.164374 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4763 06:02:47.167626 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4764 06:02:47.170629 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4765 06:02:47.171050
4766 06:02:47.171378
4767 06:02:47.180138 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4768 06:02:47.180714 CH1 RK1: MR19=808, MR18=6C23
4769 06:02:47.186898 CH1_RK1: MR19=0x808, MR18=0x6C23, DQSOSC=389, MR23=63, INC=173, DEC=115
4770 06:02:47.190084 [RxdqsGatingPostProcess] freq 600
4771 06:02:47.197006 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4772 06:02:47.200692 Pre-setting of DQS Precalculation
4773 06:02:47.204326 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4774 06:02:47.210214 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4775 06:02:47.220774 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4776 06:02:47.221299
4777 06:02:47.221633
4778 06:02:47.223545 [Calibration Summary] 1200 Mbps
4779 06:02:47.223969 CH 0, Rank 0
4780 06:02:47.227281 SW Impedance : PASS
4781 06:02:47.227808 DUTY Scan : NO K
4782 06:02:47.230225 ZQ Calibration : PASS
4783 06:02:47.233946 Jitter Meter : NO K
4784 06:02:47.234366 CBT Training : PASS
4785 06:02:47.236813 Write leveling : PASS
4786 06:02:47.237235 RX DQS gating : PASS
4787 06:02:47.240455 RX DQ/DQS(RDDQC) : PASS
4788 06:02:47.243162 TX DQ/DQS : PASS
4789 06:02:47.243585 RX DATLAT : PASS
4790 06:02:47.246661 RX DQ/DQS(Engine): PASS
4791 06:02:47.250257 TX OE : NO K
4792 06:02:47.250714 All Pass.
4793 06:02:47.251066
4794 06:02:47.251379 CH 0, Rank 1
4795 06:02:47.253732 SW Impedance : PASS
4796 06:02:47.256592 DUTY Scan : NO K
4797 06:02:47.257012 ZQ Calibration : PASS
4798 06:02:47.259989 Jitter Meter : NO K
4799 06:02:47.263268 CBT Training : PASS
4800 06:02:47.263692 Write leveling : PASS
4801 06:02:47.266782 RX DQS gating : PASS
4802 06:02:47.270233 RX DQ/DQS(RDDQC) : PASS
4803 06:02:47.270656 TX DQ/DQS : PASS
4804 06:02:47.273616 RX DATLAT : PASS
4805 06:02:47.276784 RX DQ/DQS(Engine): PASS
4806 06:02:47.277206 TX OE : NO K
4807 06:02:47.277541 All Pass.
4808 06:02:47.277915
4809 06:02:47.280462 CH 1, Rank 0
4810 06:02:47.283583 SW Impedance : PASS
4811 06:02:47.284008 DUTY Scan : NO K
4812 06:02:47.286848 ZQ Calibration : PASS
4813 06:02:47.287149 Jitter Meter : NO K
4814 06:02:47.289734 CBT Training : PASS
4815 06:02:47.293292 Write leveling : PASS
4816 06:02:47.293631 RX DQS gating : PASS
4817 06:02:47.296376 RX DQ/DQS(RDDQC) : PASS
4818 06:02:47.299999 TX DQ/DQS : PASS
4819 06:02:47.300314 RX DATLAT : PASS
4820 06:02:47.302876 RX DQ/DQS(Engine): PASS
4821 06:02:47.306287 TX OE : NO K
4822 06:02:47.306505 All Pass.
4823 06:02:47.306705
4824 06:02:47.306897 CH 1, Rank 1
4825 06:02:47.310392 SW Impedance : PASS
4826 06:02:47.313419 DUTY Scan : NO K
4827 06:02:47.313847 ZQ Calibration : PASS
4828 06:02:47.316831 Jitter Meter : NO K
4829 06:02:47.320221 CBT Training : PASS
4830 06:02:47.320690 Write leveling : PASS
4831 06:02:47.323339 RX DQS gating : PASS
4832 06:02:47.326573 RX DQ/DQS(RDDQC) : PASS
4833 06:02:47.327024 TX DQ/DQS : PASS
4834 06:02:47.330003 RX DATLAT : PASS
4835 06:02:47.330416 RX DQ/DQS(Engine): PASS
4836 06:02:47.333538 TX OE : NO K
4837 06:02:47.333965 All Pass.
4838 06:02:47.334295
4839 06:02:47.337047 DramC Write-DBI off
4840 06:02:47.339931 PER_BANK_REFRESH: Hybrid Mode
4841 06:02:47.340376 TX_TRACKING: ON
4842 06:02:47.349982 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4843 06:02:47.352835 [FAST_K] Save calibration result to emmc
4844 06:02:47.356127 dramc_set_vcore_voltage set vcore to 662500
4845 06:02:47.359628 Read voltage for 933, 3
4846 06:02:47.359732 Vio18 = 0
4847 06:02:47.362449 Vcore = 662500
4848 06:02:47.362545 Vdram = 0
4849 06:02:47.362643 Vddq = 0
4850 06:02:47.362734 Vmddr = 0
4851 06:02:47.369642 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4852 06:02:47.373093 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4853 06:02:47.376245 MEM_TYPE=3, freq_sel=17
4854 06:02:47.379713 sv_algorithm_assistance_LP4_1600
4855 06:02:47.383608 ============ PULL DRAM RESETB DOWN ============
4856 06:02:47.389940 ========== PULL DRAM RESETB DOWN end =========
4857 06:02:47.393406 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4858 06:02:47.396357 ===================================
4859 06:02:47.399573 LPDDR4 DRAM CONFIGURATION
4860 06:02:47.402884 ===================================
4861 06:02:47.403532 EX_ROW_EN[0] = 0x0
4862 06:02:47.406873 EX_ROW_EN[1] = 0x0
4863 06:02:47.407382 LP4Y_EN = 0x0
4864 06:02:47.409624 WORK_FSP = 0x0
4865 06:02:47.410046 WL = 0x3
4866 06:02:47.412657 RL = 0x3
4867 06:02:47.413105 BL = 0x2
4868 06:02:47.415970 RPST = 0x0
4869 06:02:47.416570 RD_PRE = 0x0
4870 06:02:47.419474 WR_PRE = 0x1
4871 06:02:47.420104 WR_PST = 0x0
4872 06:02:47.423110 DBI_WR = 0x0
4873 06:02:47.426310 DBI_RD = 0x0
4874 06:02:47.426724 OTF = 0x1
4875 06:02:47.429481 ===================================
4876 06:02:47.433186 ===================================
4877 06:02:47.433615 ANA top config
4878 06:02:47.436196 ===================================
4879 06:02:47.439570 DLL_ASYNC_EN = 0
4880 06:02:47.442896 ALL_SLAVE_EN = 1
4881 06:02:47.446461 NEW_RANK_MODE = 1
4882 06:02:47.449316 DLL_IDLE_MODE = 1
4883 06:02:47.449956 LP45_APHY_COMB_EN = 1
4884 06:02:47.452727 TX_ODT_DIS = 1
4885 06:02:47.455906 NEW_8X_MODE = 1
4886 06:02:47.459433 ===================================
4887 06:02:47.462770 ===================================
4888 06:02:47.466177 data_rate = 1866
4889 06:02:47.469551 CKR = 1
4890 06:02:47.469999 DQ_P2S_RATIO = 8
4891 06:02:47.473008 ===================================
4892 06:02:47.475851 CA_P2S_RATIO = 8
4893 06:02:47.479545 DQ_CA_OPEN = 0
4894 06:02:47.483063 DQ_SEMI_OPEN = 0
4895 06:02:47.485891 CA_SEMI_OPEN = 0
4896 06:02:47.489493 CA_FULL_RATE = 0
4897 06:02:47.490175 DQ_CKDIV4_EN = 1
4898 06:02:47.492274 CA_CKDIV4_EN = 1
4899 06:02:47.495954 CA_PREDIV_EN = 0
4900 06:02:47.499583 PH8_DLY = 0
4901 06:02:47.502397 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4902 06:02:47.505890 DQ_AAMCK_DIV = 4
4903 06:02:47.506319 CA_AAMCK_DIV = 4
4904 06:02:47.509619 CA_ADMCK_DIV = 4
4905 06:02:47.512504 DQ_TRACK_CA_EN = 0
4906 06:02:47.515833 CA_PICK = 933
4907 06:02:47.519172 CA_MCKIO = 933
4908 06:02:47.522852 MCKIO_SEMI = 0
4909 06:02:47.523396 PLL_FREQ = 3732
4910 06:02:47.526042 DQ_UI_PI_RATIO = 32
4911 06:02:47.529372 CA_UI_PI_RATIO = 0
4912 06:02:47.532732 ===================================
4913 06:02:47.535643 ===================================
4914 06:02:47.539222 memory_type:LPDDR4
4915 06:02:47.542752 GP_NUM : 10
4916 06:02:47.543180 SRAM_EN : 1
4917 06:02:47.546305 MD32_EN : 0
4918 06:02:47.549131 ===================================
4919 06:02:47.549562 [ANA_INIT] >>>>>>>>>>>>>>
4920 06:02:47.552434 <<<<<< [CONFIGURE PHASE]: ANA_TX
4921 06:02:47.555681 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4922 06:02:47.559176 ===================================
4923 06:02:47.562581 data_rate = 1866,PCW = 0X8f00
4924 06:02:47.565731 ===================================
4925 06:02:47.569891 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4926 06:02:47.576210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 06:02:47.579062 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4928 06:02:47.585612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4929 06:02:47.588929 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4930 06:02:47.593049 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4931 06:02:47.593486 [ANA_INIT] flow start
4932 06:02:47.595524 [ANA_INIT] PLL >>>>>>>>
4933 06:02:47.599179 [ANA_INIT] PLL <<<<<<<<
4934 06:02:47.602375 [ANA_INIT] MIDPI >>>>>>>>
4935 06:02:47.602804 [ANA_INIT] MIDPI <<<<<<<<
4936 06:02:47.605994 [ANA_INIT] DLL >>>>>>>>
4937 06:02:47.608909 [ANA_INIT] flow end
4938 06:02:47.612482 ============ LP4 DIFF to SE enter ============
4939 06:02:47.616199 ============ LP4 DIFF to SE exit ============
4940 06:02:47.619192 [ANA_INIT] <<<<<<<<<<<<<
4941 06:02:47.622677 [Flow] Enable top DCM control >>>>>
4942 06:02:47.626215 [Flow] Enable top DCM control <<<<<
4943 06:02:47.628933 Enable DLL master slave shuffle
4944 06:02:47.632889 ==============================================================
4945 06:02:47.636072 Gating Mode config
4946 06:02:47.639529 ==============================================================
4947 06:02:47.642611 Config description:
4948 06:02:47.652775 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4949 06:02:47.659197 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4950 06:02:47.662689 SELPH_MODE 0: By rank 1: By Phase
4951 06:02:47.669179 ==============================================================
4952 06:02:47.672587 GAT_TRACK_EN = 1
4953 06:02:47.675343 RX_GATING_MODE = 2
4954 06:02:47.678784 RX_GATING_TRACK_MODE = 2
4955 06:02:47.681851 SELPH_MODE = 1
4956 06:02:47.685457 PICG_EARLY_EN = 1
4957 06:02:47.688988 VALID_LAT_VALUE = 1
4958 06:02:47.691971 ==============================================================
4959 06:02:47.695326 Enter into Gating configuration >>>>
4960 06:02:47.698485 Exit from Gating configuration <<<<
4961 06:02:47.701726 Enter into DVFS_PRE_config >>>>>
4962 06:02:47.711929 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4963 06:02:47.715214 Exit from DVFS_PRE_config <<<<<
4964 06:02:47.718271 Enter into PICG configuration >>>>
4965 06:02:47.721878 Exit from PICG configuration <<<<
4966 06:02:47.724572 [RX_INPUT] configuration >>>>>
4967 06:02:47.727976 [RX_INPUT] configuration <<<<<
4968 06:02:47.734896 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4969 06:02:47.737789 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4970 06:02:47.744898 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 06:02:47.751691 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 06:02:47.757559 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 06:02:47.764213 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 06:02:47.767548 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4975 06:02:47.771165 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4976 06:02:47.774716 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4977 06:02:47.781173 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4978 06:02:47.784580 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4979 06:02:47.788069 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4980 06:02:47.791258 ===================================
4981 06:02:47.794942 LPDDR4 DRAM CONFIGURATION
4982 06:02:47.797812 ===================================
4983 06:02:47.797896 EX_ROW_EN[0] = 0x0
4984 06:02:47.801282 EX_ROW_EN[1] = 0x0
4985 06:02:47.804775 LP4Y_EN = 0x0
4986 06:02:47.804857 WORK_FSP = 0x0
4987 06:02:47.807572 WL = 0x3
4988 06:02:47.807654 RL = 0x3
4989 06:02:47.811060 BL = 0x2
4990 06:02:47.811157 RPST = 0x0
4991 06:02:47.814559 RD_PRE = 0x0
4992 06:02:47.814663 WR_PRE = 0x1
4993 06:02:47.817402 WR_PST = 0x0
4994 06:02:47.817505 DBI_WR = 0x0
4995 06:02:47.820893 DBI_RD = 0x0
4996 06:02:47.820977 OTF = 0x1
4997 06:02:47.824402 ===================================
4998 06:02:47.828090 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4999 06:02:47.834096 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5000 06:02:47.837331 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 06:02:47.841082 ===================================
5002 06:02:47.844037 LPDDR4 DRAM CONFIGURATION
5003 06:02:47.847744 ===================================
5004 06:02:47.847827 EX_ROW_EN[0] = 0x10
5005 06:02:47.850688 EX_ROW_EN[1] = 0x0
5006 06:02:47.850838 LP4Y_EN = 0x0
5007 06:02:47.854498 WORK_FSP = 0x0
5008 06:02:47.854581 WL = 0x3
5009 06:02:47.857387 RL = 0x3
5010 06:02:47.860800 BL = 0x2
5011 06:02:47.860882 RPST = 0x0
5012 06:02:47.864012 RD_PRE = 0x0
5013 06:02:47.864152 WR_PRE = 0x1
5014 06:02:47.867419 WR_PST = 0x0
5015 06:02:47.867520 DBI_WR = 0x0
5016 06:02:47.870874 DBI_RD = 0x0
5017 06:02:47.870979 OTF = 0x1
5018 06:02:47.873852 ===================================
5019 06:02:47.880989 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5020 06:02:47.884677 nWR fixed to 30
5021 06:02:47.888140 [ModeRegInit_LP4] CH0 RK0
5022 06:02:47.888218 [ModeRegInit_LP4] CH0 RK1
5023 06:02:47.891090 [ModeRegInit_LP4] CH1 RK0
5024 06:02:47.894550 [ModeRegInit_LP4] CH1 RK1
5025 06:02:47.894652 match AC timing 9
5026 06:02:47.901504 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5027 06:02:47.904420 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5028 06:02:47.908025 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5029 06:02:47.914409 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5030 06:02:47.918120 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5031 06:02:47.918246 ==
5032 06:02:47.920878 Dram Type= 6, Freq= 0, CH_0, rank 0
5033 06:02:47.924832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5034 06:02:47.924928 ==
5035 06:02:47.931134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5036 06:02:47.937529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5037 06:02:47.941171 [CA 0] Center 37 (6~68) winsize 63
5038 06:02:47.944892 [CA 1] Center 37 (7~68) winsize 62
5039 06:02:47.947800 [CA 2] Center 34 (4~65) winsize 62
5040 06:02:47.951281 [CA 3] Center 33 (3~64) winsize 62
5041 06:02:47.954732 [CA 4] Center 33 (2~64) winsize 63
5042 06:02:47.957449 [CA 5] Center 32 (2~62) winsize 61
5043 06:02:47.957564
5044 06:02:47.960748 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5045 06:02:47.960824
5046 06:02:47.964250 [CATrainingPosCal] consider 1 rank data
5047 06:02:47.967722 u2DelayCellTimex100 = 270/100 ps
5048 06:02:47.971183 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5049 06:02:47.974145 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5050 06:02:47.977776 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5051 06:02:47.981230 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5052 06:02:47.984434 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5053 06:02:47.987331 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5054 06:02:47.991124
5055 06:02:47.994084 CA PerBit enable=1, Macro0, CA PI delay=32
5056 06:02:47.994172
5057 06:02:47.997657 [CBTSetCACLKResult] CA Dly = 32
5058 06:02:47.997740 CS Dly: 5 (0~36)
5059 06:02:47.997863 ==
5060 06:02:48.001165 Dram Type= 6, Freq= 0, CH_0, rank 1
5061 06:02:48.003818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 06:02:48.003932 ==
5063 06:02:48.010906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5064 06:02:48.017071 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5065 06:02:48.020682 [CA 0] Center 37 (6~68) winsize 63
5066 06:02:48.024158 [CA 1] Center 37 (6~68) winsize 63
5067 06:02:48.027762 [CA 2] Center 34 (4~65) winsize 62
5068 06:02:48.030439 [CA 3] Center 34 (3~65) winsize 63
5069 06:02:48.033860 [CA 4] Center 32 (2~63) winsize 62
5070 06:02:48.037397 [CA 5] Center 32 (2~62) winsize 61
5071 06:02:48.037471
5072 06:02:48.040891 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5073 06:02:48.040968
5074 06:02:48.043838 [CATrainingPosCal] consider 2 rank data
5075 06:02:48.047367 u2DelayCellTimex100 = 270/100 ps
5076 06:02:48.050801 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5077 06:02:48.053789 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5078 06:02:48.057295 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5079 06:02:48.060901 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5080 06:02:48.067239 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5081 06:02:48.070169 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5082 06:02:48.070271
5083 06:02:48.073846 CA PerBit enable=1, Macro0, CA PI delay=32
5084 06:02:48.073944
5085 06:02:48.076790 [CBTSetCACLKResult] CA Dly = 32
5086 06:02:48.076895 CS Dly: 5 (0~37)
5087 06:02:48.076984
5088 06:02:48.080365 ----->DramcWriteLeveling(PI) begin...
5089 06:02:48.080449 ==
5090 06:02:48.083882 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 06:02:48.090117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 06:02:48.090195 ==
5093 06:02:48.093316 Write leveling (Byte 0): 33 => 33
5094 06:02:48.097032 Write leveling (Byte 1): 29 => 29
5095 06:02:48.097116 DramcWriteLeveling(PI) end<-----
5096 06:02:48.097180
5097 06:02:48.100159 ==
5098 06:02:48.103196 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 06:02:48.106875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 06:02:48.106956 ==
5101 06:02:48.110320 [Gating] SW mode calibration
5102 06:02:48.116703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5103 06:02:48.120050 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5104 06:02:48.126810 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
5105 06:02:48.130194 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 06:02:48.133041 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 06:02:48.139728 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 06:02:48.143307 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 06:02:48.146985 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 06:02:48.153398 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5111 06:02:48.156875 0 14 28 | B1->B0 | 3333 2525 | 0 0 | (0 0) (1 0)
5112 06:02:48.159720 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5113 06:02:48.166909 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 06:02:48.169598 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 06:02:48.173327 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 06:02:48.179588 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 06:02:48.183241 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 06:02:48.186732 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5119 06:02:48.193135 0 15 28 | B1->B0 | 2323 3d3c | 0 1 | (0 0) (0 0)
5120 06:02:48.196771 1 0 0 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
5121 06:02:48.199583 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 06:02:48.206504 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 06:02:48.209939 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 06:02:48.212685 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 06:02:48.219830 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 06:02:48.223146 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5127 06:02:48.226478 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5128 06:02:48.233024 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5129 06:02:48.236156 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 06:02:48.239778 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 06:02:48.242761 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 06:02:48.249633 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 06:02:48.252901 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 06:02:48.256112 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 06:02:48.262500 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 06:02:48.266177 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 06:02:48.269507 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 06:02:48.275927 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 06:02:48.279511 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 06:02:48.282469 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 06:02:48.289481 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 06:02:48.293135 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5143 06:02:48.296022 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5144 06:02:48.302540 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 06:02:48.302625 Total UI for P1: 0, mck2ui 16
5146 06:02:48.309797 best dqsien dly found for B0: ( 1, 2, 26)
5147 06:02:48.309882 Total UI for P1: 0, mck2ui 16
5148 06:02:48.315856 best dqsien dly found for B1: ( 1, 2, 30)
5149 06:02:48.319147 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5150 06:02:48.322482 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5151 06:02:48.322566
5152 06:02:48.326074 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5153 06:02:48.329478 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5154 06:02:48.332306 [Gating] SW calibration Done
5155 06:02:48.332390 ==
5156 06:02:48.335889 Dram Type= 6, Freq= 0, CH_0, rank 0
5157 06:02:48.339472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5158 06:02:48.339556 ==
5159 06:02:48.342298 RX Vref Scan: 0
5160 06:02:48.342382
5161 06:02:48.342466 RX Vref 0 -> 0, step: 1
5162 06:02:48.342546
5163 06:02:48.345777 RX Delay -80 -> 252, step: 8
5164 06:02:48.349044 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5165 06:02:48.355979 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5166 06:02:48.358922 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5167 06:02:48.362317 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5168 06:02:48.366063 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5169 06:02:48.369255 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5170 06:02:48.372319 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5171 06:02:48.379224 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5172 06:02:48.382508 iDelay=208, Bit 8, Center 83 (0 ~ 167) 168
5173 06:02:48.385923 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5174 06:02:48.388797 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5175 06:02:48.392136 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5176 06:02:48.399097 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5177 06:02:48.402225 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5178 06:02:48.405792 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5179 06:02:48.408578 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5180 06:02:48.408648 ==
5181 06:02:48.412268 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 06:02:48.415803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 06:02:48.415871 ==
5184 06:02:48.418615 DQS Delay:
5185 06:02:48.418689 DQS0 = 0, DQS1 = 0
5186 06:02:48.422254 DQM Delay:
5187 06:02:48.422328 DQM0 = 105, DQM1 = 93
5188 06:02:48.422390 DQ Delay:
5189 06:02:48.429085 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5190 06:02:48.432278 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5191 06:02:48.435565 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5192 06:02:48.439064 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5193 06:02:48.439133
5194 06:02:48.439199
5195 06:02:48.439257 ==
5196 06:02:48.441927 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 06:02:48.445561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 06:02:48.445639 ==
5199 06:02:48.445699
5200 06:02:48.445755
5201 06:02:48.449145 TX Vref Scan disable
5202 06:02:48.449214 == TX Byte 0 ==
5203 06:02:48.455173 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5204 06:02:48.458745 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5205 06:02:48.458816 == TX Byte 1 ==
5206 06:02:48.465232 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5207 06:02:48.468799 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5208 06:02:48.468874 ==
5209 06:02:48.472208 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 06:02:48.475095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 06:02:48.475165 ==
5212 06:02:48.475225
5213 06:02:48.475286
5214 06:02:48.478584 TX Vref Scan disable
5215 06:02:48.482024 == TX Byte 0 ==
5216 06:02:48.485694 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5217 06:02:48.488558 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5218 06:02:48.492009 == TX Byte 1 ==
5219 06:02:48.495553 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5220 06:02:48.498508 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5221 06:02:48.498597
5222 06:02:48.501756 [DATLAT]
5223 06:02:48.501837 Freq=933, CH0 RK0
5224 06:02:48.501905
5225 06:02:48.504942 DATLAT Default: 0xd
5226 06:02:48.505022 0, 0xFFFF, sum = 0
5227 06:02:48.508814 1, 0xFFFF, sum = 0
5228 06:02:48.508901 2, 0xFFFF, sum = 0
5229 06:02:48.511908 3, 0xFFFF, sum = 0
5230 06:02:48.512045 4, 0xFFFF, sum = 0
5231 06:02:48.515147 5, 0xFFFF, sum = 0
5232 06:02:48.515233 6, 0xFFFF, sum = 0
5233 06:02:48.518781 7, 0xFFFF, sum = 0
5234 06:02:48.518880 8, 0xFFFF, sum = 0
5235 06:02:48.521922 9, 0xFFFF, sum = 0
5236 06:02:48.522033 10, 0x0, sum = 1
5237 06:02:48.525173 11, 0x0, sum = 2
5238 06:02:48.525249 12, 0x0, sum = 3
5239 06:02:48.528683 13, 0x0, sum = 4
5240 06:02:48.528759 best_step = 11
5241 06:02:48.528827
5242 06:02:48.528886 ==
5243 06:02:48.531391 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 06:02:48.538487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 06:02:48.538565 ==
5246 06:02:48.538633 RX Vref Scan: 1
5247 06:02:48.538692
5248 06:02:48.541826 RX Vref 0 -> 0, step: 1
5249 06:02:48.541907
5250 06:02:48.545095 RX Delay -53 -> 252, step: 4
5251 06:02:48.545175
5252 06:02:48.548517 Set Vref, RX VrefLevel [Byte0]: 56
5253 06:02:48.552049 [Byte1]: 49
5254 06:02:48.552120
5255 06:02:48.554895 Final RX Vref Byte 0 = 56 to rank0
5256 06:02:48.558256 Final RX Vref Byte 1 = 49 to rank0
5257 06:02:48.561582 Final RX Vref Byte 0 = 56 to rank1
5258 06:02:48.564950 Final RX Vref Byte 1 = 49 to rank1==
5259 06:02:48.567962 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 06:02:48.571482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 06:02:48.571593 ==
5262 06:02:48.574822 DQS Delay:
5263 06:02:48.574895 DQS0 = 0, DQS1 = 0
5264 06:02:48.574956 DQM Delay:
5265 06:02:48.578299 DQM0 = 105, DQM1 = 95
5266 06:02:48.578372 DQ Delay:
5267 06:02:48.581214 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5268 06:02:48.584594 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =112
5269 06:02:48.588159 DQ8 =86, DQ9 =88, DQ10 =94, DQ11 =90
5270 06:02:48.591594 DQ12 =98, DQ13 =98, DQ14 =106, DQ15 =102
5271 06:02:48.594406
5272 06:02:48.594477
5273 06:02:48.601518 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5274 06:02:48.604428 CH0 RK0: MR19=505, MR18=3129
5275 06:02:48.611460 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5276 06:02:48.611558
5277 06:02:48.614231 ----->DramcWriteLeveling(PI) begin...
5278 06:02:48.614302 ==
5279 06:02:48.617617 Dram Type= 6, Freq= 0, CH_0, rank 1
5280 06:02:48.621168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 06:02:48.621249 ==
5282 06:02:48.624660 Write leveling (Byte 0): 34 => 34
5283 06:02:48.627916 Write leveling (Byte 1): 29 => 29
5284 06:02:48.631166 DramcWriteLeveling(PI) end<-----
5285 06:02:48.631259
5286 06:02:48.631320 ==
5287 06:02:48.634428 Dram Type= 6, Freq= 0, CH_0, rank 1
5288 06:02:48.638211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 06:02:48.638288 ==
5290 06:02:48.641130 [Gating] SW mode calibration
5291 06:02:48.647896 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5292 06:02:48.654443 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5293 06:02:48.657695 0 14 0 | B1->B0 | 3232 3030 | 1 1 | (1 1) (1 1)
5294 06:02:48.664184 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 06:02:48.667715 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 06:02:48.671171 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 06:02:48.674123 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 06:02:48.681055 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 06:02:48.683829 0 14 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5300 06:02:48.687254 0 14 28 | B1->B0 | 2929 2b2b | 0 0 | (0 1) (0 1)
5301 06:02:48.694115 0 15 0 | B1->B0 | 2424 2525 | 1 0 | (1 0) (0 0)
5302 06:02:48.697653 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 06:02:48.700447 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 06:02:48.707591 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 06:02:48.711211 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 06:02:48.713970 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 06:02:48.720883 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5308 06:02:48.724166 0 15 28 | B1->B0 | 3535 3232 | 0 0 | (0 0) (0 0)
5309 06:02:48.727790 1 0 0 | B1->B0 | 4646 4444 | 0 1 | (0 0) (0 0)
5310 06:02:48.734161 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 06:02:48.737777 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 06:02:48.740566 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 06:02:48.747650 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 06:02:48.750359 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 06:02:48.753750 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5316 06:02:48.760356 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5317 06:02:48.764108 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 06:02:48.767151 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 06:02:48.773913 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 06:02:48.777514 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 06:02:48.780643 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 06:02:48.786928 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 06:02:48.790482 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 06:02:48.793502 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 06:02:48.800604 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 06:02:48.803453 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 06:02:48.807014 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 06:02:48.813481 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 06:02:48.816969 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 06:02:48.820451 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 06:02:48.823294 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 06:02:48.830261 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5333 06:02:48.833830 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 06:02:48.836685 Total UI for P1: 0, mck2ui 16
5335 06:02:48.840195 best dqsien dly found for B0: ( 1, 2, 28)
5336 06:02:48.843738 Total UI for P1: 0, mck2ui 16
5337 06:02:48.846625 best dqsien dly found for B1: ( 1, 2, 28)
5338 06:02:48.850252 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5339 06:02:48.853914 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5340 06:02:48.853998
5341 06:02:48.856780 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5342 06:02:48.860213 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5343 06:02:48.863960 [Gating] SW calibration Done
5344 06:02:48.864044 ==
5345 06:02:48.866595 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 06:02:48.873808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 06:02:48.873892 ==
5348 06:02:48.873978 RX Vref Scan: 0
5349 06:02:48.874059
5350 06:02:48.877261 RX Vref 0 -> 0, step: 1
5351 06:02:48.877344
5352 06:02:48.879996 RX Delay -80 -> 252, step: 8
5353 06:02:48.883382 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5354 06:02:48.886686 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5355 06:02:48.890470 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5356 06:02:48.893741 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5357 06:02:48.900114 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5358 06:02:48.903193 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5359 06:02:48.906831 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5360 06:02:48.909790 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5361 06:02:48.913287 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5362 06:02:48.916301 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5363 06:02:48.923370 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5364 06:02:48.926851 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5365 06:02:48.929627 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5366 06:02:48.932957 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5367 06:02:48.936237 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5368 06:02:48.939881 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5369 06:02:48.943278 ==
5370 06:02:48.943383 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 06:02:48.949704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 06:02:48.949815 ==
5373 06:02:48.949906 DQS Delay:
5374 06:02:48.953256 DQS0 = 0, DQS1 = 0
5375 06:02:48.953358 DQM Delay:
5376 06:02:48.956763 DQM0 = 105, DQM1 = 93
5377 06:02:48.956856 DQ Delay:
5378 06:02:48.959535 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5379 06:02:48.963350 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5380 06:02:48.966106 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5381 06:02:48.969644 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5382 06:02:48.969717
5383 06:02:48.969777
5384 06:02:48.969841 ==
5385 06:02:48.972950 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 06:02:48.976527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 06:02:48.976632 ==
5388 06:02:48.976720
5389 06:02:48.979392
5390 06:02:48.979463 TX Vref Scan disable
5391 06:02:48.983074 == TX Byte 0 ==
5392 06:02:48.986575 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5393 06:02:48.989427 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5394 06:02:48.992732 == TX Byte 1 ==
5395 06:02:48.996410 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5396 06:02:48.999214 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5397 06:02:48.999312 ==
5398 06:02:49.002761 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 06:02:49.010228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 06:02:49.010303 ==
5401 06:02:49.010379
5402 06:02:49.010437
5403 06:02:49.010492 TX Vref Scan disable
5404 06:02:49.014140 == TX Byte 0 ==
5405 06:02:49.016851 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5406 06:02:49.023620 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5407 06:02:49.023694 == TX Byte 1 ==
5408 06:02:49.027038 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5409 06:02:49.034042 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5410 06:02:49.034144
5411 06:02:49.034233 [DATLAT]
5412 06:02:49.034322 Freq=933, CH0 RK1
5413 06:02:49.034440
5414 06:02:49.037194 DATLAT Default: 0xb
5415 06:02:49.037283 0, 0xFFFF, sum = 0
5416 06:02:49.040222 1, 0xFFFF, sum = 0
5417 06:02:49.040361 2, 0xFFFF, sum = 0
5418 06:02:49.043659 3, 0xFFFF, sum = 0
5419 06:02:49.046754 4, 0xFFFF, sum = 0
5420 06:02:49.046827 5, 0xFFFF, sum = 0
5421 06:02:49.050485 6, 0xFFFF, sum = 0
5422 06:02:49.050587 7, 0xFFFF, sum = 0
5423 06:02:49.056917 8, 0xFFFF, sum = 0
5424 06:02:49.057005 9, 0xFFFF, sum = 0
5425 06:02:49.057091 10, 0x0, sum = 1
5426 06:02:49.057170 11, 0x0, sum = 2
5427 06:02:49.060266 12, 0x0, sum = 3
5428 06:02:49.060406 13, 0x0, sum = 4
5429 06:02:49.060487 best_step = 11
5430 06:02:49.060563
5431 06:02:49.063811 ==
5432 06:02:49.063908 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 06:02:49.070119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 06:02:49.070227 ==
5435 06:02:49.070327 RX Vref Scan: 0
5436 06:02:49.070433
5437 06:02:49.073579 RX Vref 0 -> 0, step: 1
5438 06:02:49.073702
5439 06:02:49.076902 RX Delay -53 -> 252, step: 4
5440 06:02:49.080230 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5441 06:02:49.086726 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5442 06:02:49.090191 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5443 06:02:49.093733 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5444 06:02:49.097127 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5445 06:02:49.099782 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5446 06:02:49.106623 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5447 06:02:49.109932 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5448 06:02:49.113196 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5449 06:02:49.116525 iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172
5450 06:02:49.120031 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5451 06:02:49.123236 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5452 06:02:49.130049 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5453 06:02:49.133526 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5454 06:02:49.136482 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5455 06:02:49.139754 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5456 06:02:49.139835 ==
5457 06:02:49.143207 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 06:02:49.150123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 06:02:49.150207 ==
5460 06:02:49.150292 DQS Delay:
5461 06:02:49.153402 DQS0 = 0, DQS1 = 0
5462 06:02:49.153502 DQM Delay:
5463 06:02:49.153600 DQM0 = 103, DQM1 = 94
5464 06:02:49.156768 DQ Delay:
5465 06:02:49.159791 DQ0 =100, DQ1 =106, DQ2 =102, DQ3 =100
5466 06:02:49.163512 DQ4 =106, DQ5 =96, DQ6 =108, DQ7 =112
5467 06:02:49.166405 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =88
5468 06:02:49.169565 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5469 06:02:49.169650
5470 06:02:49.169735
5471 06:02:49.176586 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5472 06:02:49.180079 CH0 RK1: MR19=505, MR18=2A03
5473 06:02:49.186881 CH0_RK1: MR19=0x505, MR18=0x2A03, DQSOSC=408, MR23=63, INC=65, DEC=43
5474 06:02:49.189673 [RxdqsGatingPostProcess] freq 933
5475 06:02:49.196720 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5476 06:02:49.199832 best DQS0 dly(2T, 0.5T) = (0, 10)
5477 06:02:49.199916 best DQS1 dly(2T, 0.5T) = (0, 10)
5478 06:02:49.202872 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5479 06:02:49.206211 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5480 06:02:49.209616 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 06:02:49.213044 best DQS1 dly(2T, 0.5T) = (0, 10)
5482 06:02:49.216494 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 06:02:49.219950 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5484 06:02:49.223165 Pre-setting of DQS Precalculation
5485 06:02:49.229374 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5486 06:02:49.229464 ==
5487 06:02:49.232686 Dram Type= 6, Freq= 0, CH_1, rank 0
5488 06:02:49.236074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 06:02:49.236158 ==
5490 06:02:49.243050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5491 06:02:49.246339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5492 06:02:49.250675 [CA 0] Center 36 (6~67) winsize 62
5493 06:02:49.254271 [CA 1] Center 36 (6~67) winsize 62
5494 06:02:49.256989 [CA 2] Center 34 (4~65) winsize 62
5495 06:02:49.260571 [CA 3] Center 34 (4~65) winsize 62
5496 06:02:49.263815 [CA 4] Center 34 (4~65) winsize 62
5497 06:02:49.267413 [CA 5] Center 33 (3~64) winsize 62
5498 06:02:49.267498
5499 06:02:49.270104 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5500 06:02:49.270202
5501 06:02:49.274172 [CATrainingPosCal] consider 1 rank data
5502 06:02:49.276812 u2DelayCellTimex100 = 270/100 ps
5503 06:02:49.280493 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5504 06:02:49.287072 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5505 06:02:49.290542 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5506 06:02:49.293299 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5507 06:02:49.296834 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5508 06:02:49.300392 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5509 06:02:49.300495
5510 06:02:49.303793 CA PerBit enable=1, Macro0, CA PI delay=33
5511 06:02:49.303879
5512 06:02:49.306551 [CBTSetCACLKResult] CA Dly = 33
5513 06:02:49.306636 CS Dly: 6 (0~37)
5514 06:02:49.310118 ==
5515 06:02:49.313503 Dram Type= 6, Freq= 0, CH_1, rank 1
5516 06:02:49.316600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 06:02:49.316684 ==
5518 06:02:49.320116 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5519 06:02:49.327023 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5520 06:02:49.330329 [CA 0] Center 36 (6~67) winsize 62
5521 06:02:49.334268 [CA 1] Center 37 (7~68) winsize 62
5522 06:02:49.336862 [CA 2] Center 35 (4~66) winsize 63
5523 06:02:49.340550 [CA 3] Center 34 (4~65) winsize 62
5524 06:02:49.343575 [CA 4] Center 34 (4~65) winsize 62
5525 06:02:49.346804 [CA 5] Center 33 (3~64) winsize 62
5526 06:02:49.346889
5527 06:02:49.350701 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5528 06:02:49.350785
5529 06:02:49.353372 [CATrainingPosCal] consider 2 rank data
5530 06:02:49.356981 u2DelayCellTimex100 = 270/100 ps
5531 06:02:49.360406 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5532 06:02:49.363691 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5533 06:02:49.370292 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5534 06:02:49.373792 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5535 06:02:49.376628 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5536 06:02:49.380257 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5537 06:02:49.380348
5538 06:02:49.383580 CA PerBit enable=1, Macro0, CA PI delay=33
5539 06:02:49.383679
5540 06:02:49.386787 [CBTSetCACLKResult] CA Dly = 33
5541 06:02:49.386870 CS Dly: 7 (0~40)
5542 06:02:49.386955
5543 06:02:49.393243 ----->DramcWriteLeveling(PI) begin...
5544 06:02:49.393322 ==
5545 06:02:49.396696 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 06:02:49.399982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 06:02:49.400058 ==
5548 06:02:49.403509 Write leveling (Byte 0): 28 => 28
5549 06:02:49.407036 Write leveling (Byte 1): 28 => 28
5550 06:02:49.410485 DramcWriteLeveling(PI) end<-----
5551 06:02:49.410564
5552 06:02:49.410624 ==
5553 06:02:49.413263 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 06:02:49.416720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 06:02:49.416817 ==
5556 06:02:49.419965 [Gating] SW mode calibration
5557 06:02:49.426573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5558 06:02:49.433606 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5559 06:02:49.436433 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 06:02:49.439924 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 06:02:49.446906 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 06:02:49.450199 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 06:02:49.453317 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 06:02:49.460024 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 06:02:49.462938 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 1)
5566 06:02:49.466615 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
5567 06:02:49.473390 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 06:02:49.476733 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 06:02:49.479632 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 06:02:49.483151 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 06:02:49.489501 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 06:02:49.492842 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 06:02:49.496280 0 15 24 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)
5574 06:02:49.503063 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5575 06:02:49.506252 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 06:02:49.509616 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 06:02:49.516660 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 06:02:49.520036 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 06:02:49.522840 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 06:02:49.529660 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 06:02:49.533010 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5582 06:02:49.536277 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 06:02:49.542718 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 06:02:49.546198 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 06:02:49.549891 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 06:02:49.556008 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 06:02:49.559607 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 06:02:49.562992 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 06:02:49.569084 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 06:02:49.572462 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 06:02:49.576104 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 06:02:49.582400 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 06:02:49.585854 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 06:02:49.589099 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 06:02:49.596003 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 06:02:49.599462 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 06:02:49.602176 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5598 06:02:49.609090 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 06:02:49.609172 Total UI for P1: 0, mck2ui 16
5600 06:02:49.615833 best dqsien dly found for B0: ( 1, 2, 24)
5601 06:02:49.615915 Total UI for P1: 0, mck2ui 16
5602 06:02:49.622125 best dqsien dly found for B1: ( 1, 2, 26)
5603 06:02:49.625660 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5604 06:02:49.629120 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5605 06:02:49.629202
5606 06:02:49.632669 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5607 06:02:49.635384 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5608 06:02:49.638888 [Gating] SW calibration Done
5609 06:02:49.638970 ==
5610 06:02:49.642106 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 06:02:49.645564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 06:02:49.645673 ==
5613 06:02:49.648891 RX Vref Scan: 0
5614 06:02:49.648971
5615 06:02:49.649036 RX Vref 0 -> 0, step: 1
5616 06:02:49.649194
5617 06:02:49.652343 RX Delay -80 -> 252, step: 8
5618 06:02:49.655925 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5619 06:02:49.662262 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5620 06:02:49.665886 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5621 06:02:49.669312 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5622 06:02:49.672167 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5623 06:02:49.675652 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5624 06:02:49.679161 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5625 06:02:49.685269 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5626 06:02:49.688521 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5627 06:02:49.691851 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5628 06:02:49.695572 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5629 06:02:49.698956 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5630 06:02:49.701940 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5631 06:02:49.708844 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5632 06:02:49.712178 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5633 06:02:49.715610 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5634 06:02:49.715694 ==
5635 06:02:49.718906 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 06:02:49.722218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 06:02:49.722302 ==
5638 06:02:49.725482 DQS Delay:
5639 06:02:49.725565 DQS0 = 0, DQS1 = 0
5640 06:02:49.728722 DQM Delay:
5641 06:02:49.728821 DQM0 = 102, DQM1 = 98
5642 06:02:49.728922 DQ Delay:
5643 06:02:49.731969 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5644 06:02:49.735422 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5645 06:02:49.738932 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5646 06:02:49.742461 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5647 06:02:49.745220
5648 06:02:49.745301
5649 06:02:49.745365 ==
5650 06:02:49.748799 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 06:02:49.752202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 06:02:49.752318 ==
5653 06:02:49.752402
5654 06:02:49.752463
5655 06:02:49.755445 TX Vref Scan disable
5656 06:02:49.755526 == TX Byte 0 ==
5657 06:02:49.762174 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5658 06:02:49.764936 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5659 06:02:49.765017 == TX Byte 1 ==
5660 06:02:49.771853 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5661 06:02:49.775460 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5662 06:02:49.775542 ==
5663 06:02:49.778244 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 06:02:49.781612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 06:02:49.781694 ==
5666 06:02:49.781758
5667 06:02:49.781817
5668 06:02:49.785189 TX Vref Scan disable
5669 06:02:49.788719 == TX Byte 0 ==
5670 06:02:49.791543 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5671 06:02:49.794961 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5672 06:02:49.798460 == TX Byte 1 ==
5673 06:02:49.801872 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5674 06:02:49.805273 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5675 06:02:49.805372
5676 06:02:49.808570 [DATLAT]
5677 06:02:49.808650 Freq=933, CH1 RK0
5678 06:02:49.808715
5679 06:02:49.811458 DATLAT Default: 0xd
5680 06:02:49.811539 0, 0xFFFF, sum = 0
5681 06:02:49.814804 1, 0xFFFF, sum = 0
5682 06:02:49.814887 2, 0xFFFF, sum = 0
5683 06:02:49.818125 3, 0xFFFF, sum = 0
5684 06:02:49.818208 4, 0xFFFF, sum = 0
5685 06:02:49.821983 5, 0xFFFF, sum = 0
5686 06:02:49.822066 6, 0xFFFF, sum = 0
5687 06:02:49.824993 7, 0xFFFF, sum = 0
5688 06:02:49.825076 8, 0xFFFF, sum = 0
5689 06:02:49.827991 9, 0xFFFF, sum = 0
5690 06:02:49.828073 10, 0x0, sum = 1
5691 06:02:49.831474 11, 0x0, sum = 2
5692 06:02:49.831556 12, 0x0, sum = 3
5693 06:02:49.834950 13, 0x0, sum = 4
5694 06:02:49.835033 best_step = 11
5695 06:02:49.835097
5696 06:02:49.835156 ==
5697 06:02:49.838416 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 06:02:49.844928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 06:02:49.845010 ==
5700 06:02:49.845074 RX Vref Scan: 1
5701 06:02:49.845135
5702 06:02:49.848187 RX Vref 0 -> 0, step: 1
5703 06:02:49.848269
5704 06:02:49.851321 RX Delay -45 -> 252, step: 4
5705 06:02:49.851403
5706 06:02:49.854966 Set Vref, RX VrefLevel [Byte0]: 54
5707 06:02:49.858127 [Byte1]: 53
5708 06:02:49.858209
5709 06:02:49.861350 Final RX Vref Byte 0 = 54 to rank0
5710 06:02:49.865013 Final RX Vref Byte 1 = 53 to rank0
5711 06:02:49.868440 Final RX Vref Byte 0 = 54 to rank1
5712 06:02:49.871903 Final RX Vref Byte 1 = 53 to rank1==
5713 06:02:49.875093 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 06:02:49.877790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 06:02:49.877876 ==
5716 06:02:49.881396 DQS Delay:
5717 06:02:49.881477 DQS0 = 0, DQS1 = 0
5718 06:02:49.881542 DQM Delay:
5719 06:02:49.884821 DQM0 = 103, DQM1 = 98
5720 06:02:49.884903 DQ Delay:
5721 06:02:49.888360 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5722 06:02:49.891896 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5723 06:02:49.894623 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5724 06:02:49.898180 DQ12 =104, DQ13 =106, DQ14 =104, DQ15 =104
5725 06:02:49.898262
5726 06:02:49.901700
5727 06:02:49.908130 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5728 06:02:49.911542 CH1 RK0: MR19=505, MR18=1A32
5729 06:02:49.918289 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5730 06:02:49.918372
5731 06:02:49.921681 ----->DramcWriteLeveling(PI) begin...
5732 06:02:49.921763 ==
5733 06:02:49.924530 Dram Type= 6, Freq= 0, CH_1, rank 1
5734 06:02:49.928088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 06:02:49.928170 ==
5736 06:02:49.931675 Write leveling (Byte 0): 28 => 28
5737 06:02:49.934390 Write leveling (Byte 1): 28 => 28
5738 06:02:49.937564 DramcWriteLeveling(PI) end<-----
5739 06:02:49.937646
5740 06:02:49.937710 ==
5741 06:02:49.941001 Dram Type= 6, Freq= 0, CH_1, rank 1
5742 06:02:49.944803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 06:02:49.944885 ==
5744 06:02:49.948107 [Gating] SW mode calibration
5745 06:02:49.954464 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5746 06:02:49.961240 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5747 06:02:49.964521 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 06:02:49.967822 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 06:02:49.973981 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 06:02:49.977766 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 06:02:49.980980 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 06:02:49.987305 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5753 06:02:49.991155 0 14 24 | B1->B0 | 2e2e 3131 | 0 1 | (0 1) (1 0)
5754 06:02:49.994554 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
5755 06:02:50.000861 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 06:02:50.004251 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 06:02:50.007675 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 06:02:50.014072 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 06:02:50.017479 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 06:02:50.020903 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 06:02:50.027672 0 15 24 | B1->B0 | 3333 2d2d | 1 1 | (0 0) (0 0)
5762 06:02:50.030450 0 15 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5763 06:02:50.034008 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 06:02:50.040216 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 06:02:50.043975 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 06:02:50.047047 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 06:02:50.054019 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 06:02:50.057399 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 06:02:50.060512 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5770 06:02:50.067068 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5771 06:02:50.070220 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 06:02:50.073575 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 06:02:50.080472 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 06:02:50.083703 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 06:02:50.086886 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 06:02:50.093500 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 06:02:50.096914 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 06:02:50.100083 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 06:02:50.106915 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 06:02:50.110276 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 06:02:50.113857 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 06:02:50.120330 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 06:02:50.123828 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 06:02:50.126559 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5785 06:02:50.129877 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5786 06:02:50.136935 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5787 06:02:50.139805 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 06:02:50.143394 Total UI for P1: 0, mck2ui 16
5789 06:02:50.146849 best dqsien dly found for B0: ( 1, 2, 26)
5790 06:02:50.150214 Total UI for P1: 0, mck2ui 16
5791 06:02:50.153334 best dqsien dly found for B1: ( 1, 2, 24)
5792 06:02:50.156437 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5793 06:02:50.159931 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5794 06:02:50.160036
5795 06:02:50.163453 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5796 06:02:50.166829 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5797 06:02:50.169822 [Gating] SW calibration Done
5798 06:02:50.169903 ==
5799 06:02:50.173276 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 06:02:50.179834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 06:02:50.179915 ==
5802 06:02:50.179980 RX Vref Scan: 0
5803 06:02:50.180040
5804 06:02:50.183544 RX Vref 0 -> 0, step: 1
5805 06:02:50.183625
5806 06:02:50.186858 RX Delay -80 -> 252, step: 8
5807 06:02:50.190171 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5808 06:02:50.193430 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5809 06:02:50.196962 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5810 06:02:50.199739 iDelay=208, Bit 3, Center 99 (16 ~ 183) 168
5811 06:02:50.206815 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5812 06:02:50.210139 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5813 06:02:50.213427 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5814 06:02:50.216825 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5815 06:02:50.220016 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5816 06:02:50.223395 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5817 06:02:50.230293 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5818 06:02:50.233045 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5819 06:02:50.236462 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5820 06:02:50.239896 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5821 06:02:50.243449 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5822 06:02:50.249906 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5823 06:02:50.249988 ==
5824 06:02:50.253349 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 06:02:50.256251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 06:02:50.256375 ==
5827 06:02:50.256441 DQS Delay:
5828 06:02:50.259477 DQS0 = 0, DQS1 = 0
5829 06:02:50.259558 DQM Delay:
5830 06:02:50.263291 DQM0 = 105, DQM1 = 99
5831 06:02:50.263372 DQ Delay:
5832 06:02:50.266286 DQ0 =111, DQ1 =103, DQ2 =95, DQ3 =99
5833 06:02:50.270020 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5834 06:02:50.272736 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5835 06:02:50.276220 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5836 06:02:50.276341
5837 06:02:50.276406
5838 06:02:50.276467 ==
5839 06:02:50.279823 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 06:02:50.285953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 06:02:50.286064 ==
5842 06:02:50.286131
5843 06:02:50.286191
5844 06:02:50.286248 TX Vref Scan disable
5845 06:02:50.290116 == TX Byte 0 ==
5846 06:02:50.293261 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5847 06:02:50.299663 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5848 06:02:50.299775 == TX Byte 1 ==
5849 06:02:50.303400 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5850 06:02:50.309725 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5851 06:02:50.309806 ==
5852 06:02:50.313241 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 06:02:50.316659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 06:02:50.316741 ==
5855 06:02:50.316805
5856 06:02:50.316864
5857 06:02:50.319991 TX Vref Scan disable
5858 06:02:50.320073 == TX Byte 0 ==
5859 06:02:50.326301 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5860 06:02:50.329526 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5861 06:02:50.329607 == TX Byte 1 ==
5862 06:02:50.335910 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5863 06:02:50.339271 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5864 06:02:50.339351
5865 06:02:50.339414 [DATLAT]
5866 06:02:50.342604 Freq=933, CH1 RK1
5867 06:02:50.342684
5868 06:02:50.342748 DATLAT Default: 0xb
5869 06:02:50.346095 0, 0xFFFF, sum = 0
5870 06:02:50.346177 1, 0xFFFF, sum = 0
5871 06:02:50.349631 2, 0xFFFF, sum = 0
5872 06:02:50.349712 3, 0xFFFF, sum = 0
5873 06:02:50.352520 4, 0xFFFF, sum = 0
5874 06:02:50.356069 5, 0xFFFF, sum = 0
5875 06:02:50.356151 6, 0xFFFF, sum = 0
5876 06:02:50.359545 7, 0xFFFF, sum = 0
5877 06:02:50.359627 8, 0xFFFF, sum = 0
5878 06:02:50.362408 9, 0xFFFF, sum = 0
5879 06:02:50.362489 10, 0x0, sum = 1
5880 06:02:50.365955 11, 0x0, sum = 2
5881 06:02:50.366037 12, 0x0, sum = 3
5882 06:02:50.369450 13, 0x0, sum = 4
5883 06:02:50.369532 best_step = 11
5884 06:02:50.369595
5885 06:02:50.369654 ==
5886 06:02:50.372776 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 06:02:50.375885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 06:02:50.375966 ==
5889 06:02:50.378988 RX Vref Scan: 0
5890 06:02:50.379069
5891 06:02:50.382711 RX Vref 0 -> 0, step: 1
5892 06:02:50.382792
5893 06:02:50.382856 RX Delay -45 -> 252, step: 4
5894 06:02:50.390004 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5895 06:02:50.393506 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5896 06:02:50.396960 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5897 06:02:50.400343 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5898 06:02:50.403628 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5899 06:02:50.410404 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5900 06:02:50.413225 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5901 06:02:50.416482 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5902 06:02:50.419808 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5903 06:02:50.423087 iDelay=203, Bit 9, Center 92 (7 ~ 178) 172
5904 06:02:50.429979 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5905 06:02:50.433422 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5906 06:02:50.436952 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5907 06:02:50.440602 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5908 06:02:50.443103 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5909 06:02:50.450037 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5910 06:02:50.450120 ==
5911 06:02:50.453168 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 06:02:50.456688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 06:02:50.456771 ==
5914 06:02:50.456834 DQS Delay:
5915 06:02:50.460128 DQS0 = 0, DQS1 = 0
5916 06:02:50.460236 DQM Delay:
5917 06:02:50.462969 DQM0 = 104, DQM1 = 100
5918 06:02:50.463049 DQ Delay:
5919 06:02:50.466447 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =100
5920 06:02:50.470087 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5921 06:02:50.473499 DQ8 =92, DQ9 =92, DQ10 =98, DQ11 =94
5922 06:02:50.476801 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5923 06:02:50.476882
5924 06:02:50.476945
5925 06:02:50.486350 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5926 06:02:50.486459 CH1 RK1: MR19=504, MR18=2BFF
5927 06:02:50.493216 CH1_RK1: MR19=0x504, MR18=0x2BFF, DQSOSC=408, MR23=63, INC=65, DEC=43
5928 06:02:50.496295 [RxdqsGatingPostProcess] freq 933
5929 06:02:50.503145 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5930 06:02:50.506570 best DQS0 dly(2T, 0.5T) = (0, 10)
5931 06:02:50.510045 best DQS1 dly(2T, 0.5T) = (0, 10)
5932 06:02:50.512577 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5933 06:02:50.515851 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5934 06:02:50.519224 best DQS0 dly(2T, 0.5T) = (0, 10)
5935 06:02:50.522763 best DQS1 dly(2T, 0.5T) = (0, 10)
5936 06:02:50.526249 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5937 06:02:50.529745 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5938 06:02:50.529828 Pre-setting of DQS Precalculation
5939 06:02:50.536559 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5940 06:02:50.542798 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5941 06:02:50.549298 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5942 06:02:50.549386
5943 06:02:50.549451
5944 06:02:50.552753 [Calibration Summary] 1866 Mbps
5945 06:02:50.556211 CH 0, Rank 0
5946 06:02:50.556294 SW Impedance : PASS
5947 06:02:50.559578 DUTY Scan : NO K
5948 06:02:50.562660 ZQ Calibration : PASS
5949 06:02:50.562734 Jitter Meter : NO K
5950 06:02:50.566418 CBT Training : PASS
5951 06:02:50.566507 Write leveling : PASS
5952 06:02:50.569626 RX DQS gating : PASS
5953 06:02:50.572435 RX DQ/DQS(RDDQC) : PASS
5954 06:02:50.572530 TX DQ/DQS : PASS
5955 06:02:50.575959 RX DATLAT : PASS
5956 06:02:50.579478 RX DQ/DQS(Engine): PASS
5957 06:02:50.579559 TX OE : NO K
5958 06:02:50.582910 All Pass.
5959 06:02:50.582993
5960 06:02:50.583057 CH 0, Rank 1
5961 06:02:50.586475 SW Impedance : PASS
5962 06:02:50.586602 DUTY Scan : NO K
5963 06:02:50.589416 ZQ Calibration : PASS
5964 06:02:50.592871 Jitter Meter : NO K
5965 06:02:50.592952 CBT Training : PASS
5966 06:02:50.596300 Write leveling : PASS
5967 06:02:50.599621 RX DQS gating : PASS
5968 06:02:50.599703 RX DQ/DQS(RDDQC) : PASS
5969 06:02:50.602876 TX DQ/DQS : PASS
5970 06:02:50.606204 RX DATLAT : PASS
5971 06:02:50.606284 RX DQ/DQS(Engine): PASS
5972 06:02:50.609361 TX OE : NO K
5973 06:02:50.609442 All Pass.
5974 06:02:50.609506
5975 06:02:50.612683 CH 1, Rank 0
5976 06:02:50.612764 SW Impedance : PASS
5977 06:02:50.616003 DUTY Scan : NO K
5978 06:02:50.616083 ZQ Calibration : PASS
5979 06:02:50.619275 Jitter Meter : NO K
5980 06:02:50.622668 CBT Training : PASS
5981 06:02:50.622749 Write leveling : PASS
5982 06:02:50.626029 RX DQS gating : PASS
5983 06:02:50.629456 RX DQ/DQS(RDDQC) : PASS
5984 06:02:50.629566 TX DQ/DQS : PASS
5985 06:02:50.632246 RX DATLAT : PASS
5986 06:02:50.635631 RX DQ/DQS(Engine): PASS
5987 06:02:50.635729 TX OE : NO K
5988 06:02:50.639176 All Pass.
5989 06:02:50.639272
5990 06:02:50.639360 CH 1, Rank 1
5991 06:02:50.642565 SW Impedance : PASS
5992 06:02:50.642642 DUTY Scan : NO K
5993 06:02:50.645983 ZQ Calibration : PASS
5994 06:02:50.649222 Jitter Meter : NO K
5995 06:02:50.649296 CBT Training : PASS
5996 06:02:50.652440 Write leveling : PASS
5997 06:02:50.655739 RX DQS gating : PASS
5998 06:02:50.655818 RX DQ/DQS(RDDQC) : PASS
5999 06:02:50.658919 TX DQ/DQS : PASS
6000 06:02:50.662425 RX DATLAT : PASS
6001 06:02:50.662523 RX DQ/DQS(Engine): PASS
6002 06:02:50.665898 TX OE : NO K
6003 06:02:50.665969 All Pass.
6004 06:02:50.666030
6005 06:02:50.668817 DramC Write-DBI off
6006 06:02:50.672081 PER_BANK_REFRESH: Hybrid Mode
6007 06:02:50.672155 TX_TRACKING: ON
6008 06:02:50.682209 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6009 06:02:50.685176 [FAST_K] Save calibration result to emmc
6010 06:02:50.689085 dramc_set_vcore_voltage set vcore to 650000
6011 06:02:50.692019 Read voltage for 400, 6
6012 06:02:50.692088 Vio18 = 0
6013 06:02:50.692154 Vcore = 650000
6014 06:02:50.695520 Vdram = 0
6015 06:02:50.695612 Vddq = 0
6016 06:02:50.695700 Vmddr = 0
6017 06:02:50.702394 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6018 06:02:50.705705 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6019 06:02:50.708615 MEM_TYPE=3, freq_sel=20
6020 06:02:50.711928 sv_algorithm_assistance_LP4_800
6021 06:02:50.715760 ============ PULL DRAM RESETB DOWN ============
6022 06:02:50.718875 ========== PULL DRAM RESETB DOWN end =========
6023 06:02:50.725381 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6024 06:02:50.728608 ===================================
6025 06:02:50.728734 LPDDR4 DRAM CONFIGURATION
6026 06:02:50.731963 ===================================
6027 06:02:50.735325 EX_ROW_EN[0] = 0x0
6028 06:02:50.738843 EX_ROW_EN[1] = 0x0
6029 06:02:50.738911 LP4Y_EN = 0x0
6030 06:02:50.742353 WORK_FSP = 0x0
6031 06:02:50.742469 WL = 0x2
6032 06:02:50.745118 RL = 0x2
6033 06:02:50.745196 BL = 0x2
6034 06:02:50.748715 RPST = 0x0
6035 06:02:50.748813 RD_PRE = 0x0
6036 06:02:50.752066 WR_PRE = 0x1
6037 06:02:50.752160 WR_PST = 0x0
6038 06:02:50.755456 DBI_WR = 0x0
6039 06:02:50.755538 DBI_RD = 0x0
6040 06:02:50.759062 OTF = 0x1
6041 06:02:50.762433 ===================================
6042 06:02:50.765963 ===================================
6043 06:02:50.766036 ANA top config
6044 06:02:50.769159 ===================================
6045 06:02:50.772352 DLL_ASYNC_EN = 0
6046 06:02:50.775859 ALL_SLAVE_EN = 1
6047 06:02:50.775928 NEW_RANK_MODE = 1
6048 06:02:50.778578 DLL_IDLE_MODE = 1
6049 06:02:50.782006 LP45_APHY_COMB_EN = 1
6050 06:02:50.785556 TX_ODT_DIS = 1
6051 06:02:50.788908 NEW_8X_MODE = 1
6052 06:02:50.792279 ===================================
6053 06:02:50.792377 ===================================
6054 06:02:50.795609 data_rate = 800
6055 06:02:50.798808 CKR = 1
6056 06:02:50.801797 DQ_P2S_RATIO = 4
6057 06:02:50.805308 ===================================
6058 06:02:50.808749 CA_P2S_RATIO = 4
6059 06:02:50.812108 DQ_CA_OPEN = 0
6060 06:02:50.815066 DQ_SEMI_OPEN = 1
6061 06:02:50.815166 CA_SEMI_OPEN = 1
6062 06:02:50.818448 CA_FULL_RATE = 0
6063 06:02:50.821632 DQ_CKDIV4_EN = 0
6064 06:02:50.824958 CA_CKDIV4_EN = 1
6065 06:02:50.828890 CA_PREDIV_EN = 0
6066 06:02:50.831632 PH8_DLY = 0
6067 06:02:50.831705 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6068 06:02:50.835517 DQ_AAMCK_DIV = 0
6069 06:02:50.838699 CA_AAMCK_DIV = 0
6070 06:02:50.842074 CA_ADMCK_DIV = 4
6071 06:02:50.844896 DQ_TRACK_CA_EN = 0
6072 06:02:50.848282 CA_PICK = 800
6073 06:02:50.848405 CA_MCKIO = 400
6074 06:02:50.851977 MCKIO_SEMI = 400
6075 06:02:50.855483 PLL_FREQ = 3016
6076 06:02:50.858238 DQ_UI_PI_RATIO = 32
6077 06:02:50.861691 CA_UI_PI_RATIO = 32
6078 06:02:50.865238 ===================================
6079 06:02:50.868111 ===================================
6080 06:02:50.871522 memory_type:LPDDR4
6081 06:02:50.871595 GP_NUM : 10
6082 06:02:50.874913 SRAM_EN : 1
6083 06:02:50.878330 MD32_EN : 0
6084 06:02:50.878406 ===================================
6085 06:02:50.881719 [ANA_INIT] >>>>>>>>>>>>>>
6086 06:02:50.884694 <<<<<< [CONFIGURE PHASE]: ANA_TX
6087 06:02:50.888189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6088 06:02:50.891656 ===================================
6089 06:02:50.895140 data_rate = 800,PCW = 0X7400
6090 06:02:50.898004 ===================================
6091 06:02:50.901434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6092 06:02:50.908344 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6093 06:02:50.918121 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6094 06:02:50.921295 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6095 06:02:50.924723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6096 06:02:50.928036 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6097 06:02:50.931856 [ANA_INIT] flow start
6098 06:02:50.934718 [ANA_INIT] PLL >>>>>>>>
6099 06:02:50.934831 [ANA_INIT] PLL <<<<<<<<
6100 06:02:50.937783 [ANA_INIT] MIDPI >>>>>>>>
6101 06:02:50.940846 [ANA_INIT] MIDPI <<<<<<<<
6102 06:02:50.944405 [ANA_INIT] DLL >>>>>>>>
6103 06:02:50.944489 [ANA_INIT] flow end
6104 06:02:50.947535 ============ LP4 DIFF to SE enter ============
6105 06:02:50.954727 ============ LP4 DIFF to SE exit ============
6106 06:02:50.954830 [ANA_INIT] <<<<<<<<<<<<<
6107 06:02:50.957752 [Flow] Enable top DCM control >>>>>
6108 06:02:50.961282 [Flow] Enable top DCM control <<<<<
6109 06:02:50.964738 Enable DLL master slave shuffle
6110 06:02:50.971073 ==============================================================
6111 06:02:50.974484 Gating Mode config
6112 06:02:50.977357 ==============================================================
6113 06:02:50.980915 Config description:
6114 06:02:50.990978 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6115 06:02:50.997441 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6116 06:02:51.000948 SELPH_MODE 0: By rank 1: By Phase
6117 06:02:51.007388 ==============================================================
6118 06:02:51.010952 GAT_TRACK_EN = 0
6119 06:02:51.013889 RX_GATING_MODE = 2
6120 06:02:51.013990 RX_GATING_TRACK_MODE = 2
6121 06:02:51.017336 SELPH_MODE = 1
6122 06:02:51.020770 PICG_EARLY_EN = 1
6123 06:02:51.024383 VALID_LAT_VALUE = 1
6124 06:02:51.030778 ==============================================================
6125 06:02:51.034250 Enter into Gating configuration >>>>
6126 06:02:51.037471 Exit from Gating configuration <<<<
6127 06:02:51.040683 Enter into DVFS_PRE_config >>>>>
6128 06:02:51.050749 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6129 06:02:51.054215 Exit from DVFS_PRE_config <<<<<
6130 06:02:51.057472 Enter into PICG configuration >>>>
6131 06:02:51.060597 Exit from PICG configuration <<<<
6132 06:02:51.063859 [RX_INPUT] configuration >>>>>
6133 06:02:51.067453 [RX_INPUT] configuration <<<<<
6134 06:02:51.070339 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6135 06:02:51.077527 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6136 06:02:51.083693 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6137 06:02:51.090532 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6138 06:02:51.094025 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 06:02:51.100844 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 06:02:51.104121 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6141 06:02:51.110520 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6142 06:02:51.114219 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6143 06:02:51.117078 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6144 06:02:51.120583 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6145 06:02:51.127011 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6146 06:02:51.130429 ===================================
6147 06:02:51.130529 LPDDR4 DRAM CONFIGURATION
6148 06:02:51.133947 ===================================
6149 06:02:51.136770 EX_ROW_EN[0] = 0x0
6150 06:02:51.140396 EX_ROW_EN[1] = 0x0
6151 06:02:51.140491 LP4Y_EN = 0x0
6152 06:02:51.143850 WORK_FSP = 0x0
6153 06:02:51.143947 WL = 0x2
6154 06:02:51.146629 RL = 0x2
6155 06:02:51.146729 BL = 0x2
6156 06:02:51.149984 RPST = 0x0
6157 06:02:51.150076 RD_PRE = 0x0
6158 06:02:51.153613 WR_PRE = 0x1
6159 06:02:51.153712 WR_PST = 0x0
6160 06:02:51.157052 DBI_WR = 0x0
6161 06:02:51.157148 DBI_RD = 0x0
6162 06:02:51.159979 OTF = 0x1
6163 06:02:51.163454 ===================================
6164 06:02:51.166811 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6165 06:02:51.170244 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6166 06:02:51.176436 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6167 06:02:51.179688 ===================================
6168 06:02:51.179790 LPDDR4 DRAM CONFIGURATION
6169 06:02:51.183398 ===================================
6170 06:02:51.186337 EX_ROW_EN[0] = 0x10
6171 06:02:51.189743 EX_ROW_EN[1] = 0x0
6172 06:02:51.189815 LP4Y_EN = 0x0
6173 06:02:51.193099 WORK_FSP = 0x0
6174 06:02:51.193170 WL = 0x2
6175 06:02:51.196372 RL = 0x2
6176 06:02:51.196445 BL = 0x2
6177 06:02:51.199940 RPST = 0x0
6178 06:02:51.200041 RD_PRE = 0x0
6179 06:02:51.203172 WR_PRE = 0x1
6180 06:02:51.203269 WR_PST = 0x0
6181 06:02:51.206808 DBI_WR = 0x0
6182 06:02:51.206906 DBI_RD = 0x0
6183 06:02:51.209534 OTF = 0x1
6184 06:02:51.212918 ===================================
6185 06:02:51.219990 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6186 06:02:51.223034 nWR fixed to 30
6187 06:02:51.226230 [ModeRegInit_LP4] CH0 RK0
6188 06:02:51.226311 [ModeRegInit_LP4] CH0 RK1
6189 06:02:51.229878 [ModeRegInit_LP4] CH1 RK0
6190 06:02:51.233244 [ModeRegInit_LP4] CH1 RK1
6191 06:02:51.233321 match AC timing 19
6192 06:02:51.239596 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6193 06:02:51.243047 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6194 06:02:51.246586 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6195 06:02:51.252827 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6196 06:02:51.256386 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6197 06:02:51.256488 ==
6198 06:02:51.259765 Dram Type= 6, Freq= 0, CH_0, rank 0
6199 06:02:51.262653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6200 06:02:51.262755 ==
6201 06:02:51.269075 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6202 06:02:51.275914 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6203 06:02:51.279421 [CA 0] Center 36 (8~64) winsize 57
6204 06:02:51.282217 [CA 1] Center 36 (8~64) winsize 57
6205 06:02:51.285749 [CA 2] Center 36 (8~64) winsize 57
6206 06:02:51.285823 [CA 3] Center 36 (8~64) winsize 57
6207 06:02:51.289325 [CA 4] Center 36 (8~64) winsize 57
6208 06:02:51.292200 [CA 5] Center 36 (8~64) winsize 57
6209 06:02:51.292320
6210 06:02:51.299159 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6211 06:02:51.299260
6212 06:02:51.302426 [CATrainingPosCal] consider 1 rank data
6213 06:02:51.305428 u2DelayCellTimex100 = 270/100 ps
6214 06:02:51.309222 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 06:02:51.312387 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 06:02:51.315752 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 06:02:51.319177 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 06:02:51.322595 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 06:02:51.325622 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 06:02:51.325706
6221 06:02:51.329000 CA PerBit enable=1, Macro0, CA PI delay=36
6222 06:02:51.329115
6223 06:02:51.332142 [CBTSetCACLKResult] CA Dly = 36
6224 06:02:51.336113 CS Dly: 1 (0~32)
6225 06:02:51.336196 ==
6226 06:02:51.339130 Dram Type= 6, Freq= 0, CH_0, rank 1
6227 06:02:51.342178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6228 06:02:51.342262 ==
6229 06:02:51.348805 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6230 06:02:51.352237 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6231 06:02:51.355635 [CA 0] Center 36 (8~64) winsize 57
6232 06:02:51.359267 [CA 1] Center 36 (8~64) winsize 57
6233 06:02:51.361973 [CA 2] Center 36 (8~64) winsize 57
6234 06:02:51.365477 [CA 3] Center 36 (8~64) winsize 57
6235 06:02:51.369085 [CA 4] Center 36 (8~64) winsize 57
6236 06:02:51.371819 [CA 5] Center 36 (8~64) winsize 57
6237 06:02:51.371902
6238 06:02:51.375278 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6239 06:02:51.375362
6240 06:02:51.378648 [CATrainingPosCal] consider 2 rank data
6241 06:02:51.382156 u2DelayCellTimex100 = 270/100 ps
6242 06:02:51.385011 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 06:02:51.388587 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 06:02:51.395514 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 06:02:51.398251 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 06:02:51.401682 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 06:02:51.405177 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 06:02:51.405261
6249 06:02:51.408668 CA PerBit enable=1, Macro0, CA PI delay=36
6250 06:02:51.408751
6251 06:02:51.411506 [CBTSetCACLKResult] CA Dly = 36
6252 06:02:51.411589 CS Dly: 1 (0~32)
6253 06:02:51.411674
6254 06:02:51.414772 ----->DramcWriteLeveling(PI) begin...
6255 06:02:51.418535 ==
6256 06:02:51.421604 Dram Type= 6, Freq= 0, CH_0, rank 0
6257 06:02:51.425108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 06:02:51.425214 ==
6259 06:02:51.428645 Write leveling (Byte 0): 40 => 8
6260 06:02:51.431334 Write leveling (Byte 1): 40 => 8
6261 06:02:51.435358 DramcWriteLeveling(PI) end<-----
6262 06:02:51.435441
6263 06:02:51.435526 ==
6264 06:02:51.437953 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 06:02:51.441321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 06:02:51.441404 ==
6267 06:02:51.444782 [Gating] SW mode calibration
6268 06:02:51.451798 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6269 06:02:51.455077 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6270 06:02:51.461599 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6271 06:02:51.464787 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 06:02:51.468193 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 06:02:51.474567 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 06:02:51.478339 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 06:02:51.481367 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 06:02:51.488153 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 06:02:51.491686 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 06:02:51.495097 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 06:02:51.497925 Total UI for P1: 0, mck2ui 16
6280 06:02:51.501423 best dqsien dly found for B0: ( 0, 14, 24)
6281 06:02:51.504949 Total UI for P1: 0, mck2ui 16
6282 06:02:51.508466 best dqsien dly found for B1: ( 0, 14, 24)
6283 06:02:51.511207 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6284 06:02:51.514784 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6285 06:02:51.514869
6286 06:02:51.521131 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6287 06:02:51.524635 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6288 06:02:51.527947 [Gating] SW calibration Done
6289 06:02:51.528030 ==
6290 06:02:51.531319 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 06:02:51.534525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 06:02:51.534609 ==
6293 06:02:51.534707 RX Vref Scan: 0
6294 06:02:51.534802
6295 06:02:51.537779 RX Vref 0 -> 0, step: 1
6296 06:02:51.537881
6297 06:02:51.541081 RX Delay -410 -> 252, step: 16
6298 06:02:51.544706 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6299 06:02:51.550987 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6300 06:02:51.554516 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6301 06:02:51.558036 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6302 06:02:51.560877 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6303 06:02:51.567912 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6304 06:02:51.570702 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6305 06:02:51.574192 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6306 06:02:51.577701 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6307 06:02:51.584115 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6308 06:02:51.587230 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6309 06:02:51.590850 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6310 06:02:51.596945 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6311 06:02:51.600461 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6312 06:02:51.604190 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6313 06:02:51.606975 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6314 06:02:51.607127 ==
6315 06:02:51.610598 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 06:02:51.616914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 06:02:51.616996 ==
6318 06:02:51.617060 DQS Delay:
6319 06:02:51.620441 DQS0 = 27, DQS1 = 35
6320 06:02:51.620521 DQM Delay:
6321 06:02:51.620585 DQM0 = 9, DQM1 = 11
6322 06:02:51.623948 DQ Delay:
6323 06:02:51.626760 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6324 06:02:51.630182 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6325 06:02:51.630262 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6326 06:02:51.633638 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6327 06:02:51.637009
6328 06:02:51.637092
6329 06:02:51.637185 ==
6330 06:02:51.640301 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 06:02:51.643782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 06:02:51.643878 ==
6333 06:02:51.643967
6334 06:02:51.644053
6335 06:02:51.647377 TX Vref Scan disable
6336 06:02:51.647450 == TX Byte 0 ==
6337 06:02:51.650169 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 06:02:51.657232 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 06:02:51.657309 == TX Byte 1 ==
6340 06:02:51.660388 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 06:02:51.667080 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 06:02:51.667183 ==
6343 06:02:51.669921 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 06:02:51.673375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 06:02:51.673445 ==
6346 06:02:51.673505
6347 06:02:51.673561
6348 06:02:51.677019 TX Vref Scan disable
6349 06:02:51.677086 == TX Byte 0 ==
6350 06:02:51.679834 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 06:02:51.686706 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 06:02:51.686777 == TX Byte 1 ==
6353 06:02:51.690078 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 06:02:51.696836 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 06:02:51.696938
6356 06:02:51.697028 [DATLAT]
6357 06:02:51.700222 Freq=400, CH0 RK0
6358 06:02:51.700371
6359 06:02:51.700469 DATLAT Default: 0xf
6360 06:02:51.703054 0, 0xFFFF, sum = 0
6361 06:02:51.703186 1, 0xFFFF, sum = 0
6362 06:02:51.706588 2, 0xFFFF, sum = 0
6363 06:02:51.706692 3, 0xFFFF, sum = 0
6364 06:02:51.709812 4, 0xFFFF, sum = 0
6365 06:02:51.709922 5, 0xFFFF, sum = 0
6366 06:02:51.713029 6, 0xFFFF, sum = 0
6367 06:02:51.713143 7, 0xFFFF, sum = 0
6368 06:02:51.716308 8, 0xFFFF, sum = 0
6369 06:02:51.716459 9, 0xFFFF, sum = 0
6370 06:02:51.719591 10, 0xFFFF, sum = 0
6371 06:02:51.719751 11, 0xFFFF, sum = 0
6372 06:02:51.722892 12, 0xFFFF, sum = 0
6373 06:02:51.722989 13, 0x0, sum = 1
6374 06:02:51.726602 14, 0x0, sum = 2
6375 06:02:51.726795 15, 0x0, sum = 3
6376 06:02:51.729887 16, 0x0, sum = 4
6377 06:02:51.730004 best_step = 14
6378 06:02:51.730100
6379 06:02:51.730189 ==
6380 06:02:51.733195 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 06:02:51.739850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 06:02:51.739982 ==
6383 06:02:51.740055 RX Vref Scan: 1
6384 06:02:51.740117
6385 06:02:51.743198 RX Vref 0 -> 0, step: 1
6386 06:02:51.743301
6387 06:02:51.746332 RX Delay -311 -> 252, step: 8
6388 06:02:51.746446
6389 06:02:51.749792 Set Vref, RX VrefLevel [Byte0]: 56
6390 06:02:51.752704 [Byte1]: 49
6391 06:02:51.752786
6392 06:02:51.756247 Final RX Vref Byte 0 = 56 to rank0
6393 06:02:51.759859 Final RX Vref Byte 1 = 49 to rank0
6394 06:02:51.763145 Final RX Vref Byte 0 = 56 to rank1
6395 06:02:51.766515 Final RX Vref Byte 1 = 49 to rank1==
6396 06:02:51.769592 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 06:02:51.772952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 06:02:51.776306 ==
6399 06:02:51.776402 DQS Delay:
6400 06:02:51.776466 DQS0 = 28, DQS1 = 36
6401 06:02:51.779681 DQM Delay:
6402 06:02:51.779774 DQM0 = 10, DQM1 = 13
6403 06:02:51.783174 DQ Delay:
6404 06:02:51.783256 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6405 06:02:51.786060 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6406 06:02:51.789693 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6407 06:02:51.793134 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6408 06:02:51.793214
6409 06:02:51.793278
6410 06:02:51.802621 [DQSOSCAuto] RK0, (LSB)MR18= 0xc9b6, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6411 06:02:51.806214 CH0 RK0: MR19=C0C, MR18=C9B6
6412 06:02:51.809827 CH0_RK0: MR19=0xC0C, MR18=0xC9B6, DQSOSC=384, MR23=63, INC=400, DEC=267
6413 06:02:51.813337 ==
6414 06:02:51.815986 Dram Type= 6, Freq= 0, CH_0, rank 1
6415 06:02:51.819492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 06:02:51.819574 ==
6417 06:02:51.822743 [Gating] SW mode calibration
6418 06:02:51.829774 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6419 06:02:51.833187 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6420 06:02:51.839421 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 06:02:51.842759 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 06:02:51.846227 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 06:02:51.852736 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 06:02:51.856525 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 06:02:51.859500 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 06:02:51.866187 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 06:02:51.869884 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 06:02:51.872939 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 06:02:51.876071 Total UI for P1: 0, mck2ui 16
6430 06:02:51.879420 best dqsien dly found for B0: ( 0, 14, 24)
6431 06:02:51.882585 Total UI for P1: 0, mck2ui 16
6432 06:02:51.885933 best dqsien dly found for B1: ( 0, 14, 24)
6433 06:02:51.889197 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6434 06:02:51.892624 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6435 06:02:51.892705
6436 06:02:51.896168 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6437 06:02:51.902483 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6438 06:02:51.902602 [Gating] SW calibration Done
6439 06:02:51.905860 ==
6440 06:02:51.905950 Dram Type= 6, Freq= 0, CH_0, rank 1
6441 06:02:51.912704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 06:02:51.912816 ==
6443 06:02:51.912884 RX Vref Scan: 0
6444 06:02:51.912959
6445 06:02:51.916201 RX Vref 0 -> 0, step: 1
6446 06:02:51.916332
6447 06:02:51.919182 RX Delay -410 -> 252, step: 16
6448 06:02:51.922586 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6449 06:02:51.926109 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6450 06:02:51.932820 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6451 06:02:51.935602 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6452 06:02:51.939073 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6453 06:02:51.942518 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6454 06:02:51.948796 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6455 06:02:51.952196 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6456 06:02:51.955685 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6457 06:02:51.959089 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6458 06:02:51.965439 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6459 06:02:51.968945 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6460 06:02:51.972350 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6461 06:02:51.975461 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6462 06:02:51.982225 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6463 06:02:51.985250 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6464 06:02:51.985331 ==
6465 06:02:51.989164 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 06:02:51.991990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 06:02:51.992072 ==
6468 06:02:51.995471 DQS Delay:
6469 06:02:51.995552 DQS0 = 19, DQS1 = 35
6470 06:02:51.998558 DQM Delay:
6471 06:02:51.998638 DQM0 = 5, DQM1 = 11
6472 06:02:51.998702 DQ Delay:
6473 06:02:52.002012 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6474 06:02:52.005352 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6475 06:02:52.008582 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6476 06:02:52.011953 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6477 06:02:52.012059
6478 06:02:52.012150
6479 06:02:52.012237 ==
6480 06:02:52.015840 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 06:02:52.022142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 06:02:52.022224 ==
6483 06:02:52.022295
6484 06:02:52.022356
6485 06:02:52.022417 TX Vref Scan disable
6486 06:02:52.025517 == TX Byte 0 ==
6487 06:02:52.028992 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6488 06:02:52.032421 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6489 06:02:52.035325 == TX Byte 1 ==
6490 06:02:52.039171 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6491 06:02:52.041952 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6492 06:02:52.042031 ==
6493 06:02:52.045469 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 06:02:52.048963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 06:02:52.052447 ==
6496 06:02:52.052530
6497 06:02:52.052593
6498 06:02:52.052653 TX Vref Scan disable
6499 06:02:52.055143 == TX Byte 0 ==
6500 06:02:52.058702 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6501 06:02:52.062134 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6502 06:02:52.065070 == TX Byte 1 ==
6503 06:02:52.068519 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6504 06:02:52.072065 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6505 06:02:52.072165
6506 06:02:52.075580 [DATLAT]
6507 06:02:52.075669 Freq=400, CH0 RK1
6508 06:02:52.075737
6509 06:02:52.078402 DATLAT Default: 0xe
6510 06:02:52.078486 0, 0xFFFF, sum = 0
6511 06:02:52.081720 1, 0xFFFF, sum = 0
6512 06:02:52.081809 2, 0xFFFF, sum = 0
6513 06:02:52.085172 3, 0xFFFF, sum = 0
6514 06:02:52.085264 4, 0xFFFF, sum = 0
6515 06:02:52.088627 5, 0xFFFF, sum = 0
6516 06:02:52.088716 6, 0xFFFF, sum = 0
6517 06:02:52.091830 7, 0xFFFF, sum = 0
6518 06:02:52.091922 8, 0xFFFF, sum = 0
6519 06:02:52.095228 9, 0xFFFF, sum = 0
6520 06:02:52.095314 10, 0xFFFF, sum = 0
6521 06:02:52.098870 11, 0xFFFF, sum = 0
6522 06:02:52.098955 12, 0xFFFF, sum = 0
6523 06:02:52.101560 13, 0x0, sum = 1
6524 06:02:52.101645 14, 0x0, sum = 2
6525 06:02:52.104923 15, 0x0, sum = 3
6526 06:02:52.105046 16, 0x0, sum = 4
6527 06:02:52.108314 best_step = 14
6528 06:02:52.108454
6529 06:02:52.108521 ==
6530 06:02:52.111761 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 06:02:52.115153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 06:02:52.115275 ==
6533 06:02:52.118402 RX Vref Scan: 0
6534 06:02:52.118524
6535 06:02:52.118607 RX Vref 0 -> 0, step: 1
6536 06:02:52.118700
6537 06:02:52.121717 RX Delay -311 -> 252, step: 8
6538 06:02:52.129907 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6539 06:02:52.132726 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6540 06:02:52.136169 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6541 06:02:52.139523 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6542 06:02:52.146151 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6543 06:02:52.149754 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6544 06:02:52.152808 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6545 06:02:52.156308 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6546 06:02:52.162819 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6547 06:02:52.166482 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6548 06:02:52.169823 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6549 06:02:52.173316 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6550 06:02:52.179579 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6551 06:02:52.183233 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6552 06:02:52.186425 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6553 06:02:52.192751 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6554 06:02:52.192833 ==
6555 06:02:52.196157 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 06:02:52.199516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 06:02:52.199598 ==
6558 06:02:52.199663 DQS Delay:
6559 06:02:52.203024 DQS0 = 24, DQS1 = 32
6560 06:02:52.203104 DQM Delay:
6561 06:02:52.206386 DQM0 = 7, DQM1 = 9
6562 06:02:52.206467 DQ Delay:
6563 06:02:52.210020 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6564 06:02:52.213062 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6565 06:02:52.216440 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6566 06:02:52.220030 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6567 06:02:52.220127
6568 06:02:52.220193
6569 06:02:52.226321 [DQSOSCAuto] RK1, (LSB)MR18= 0xba5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6570 06:02:52.229856 CH0 RK1: MR19=C0C, MR18=BA5C
6571 06:02:52.236091 CH0_RK1: MR19=0xC0C, MR18=0xBA5C, DQSOSC=386, MR23=63, INC=396, DEC=264
6572 06:02:52.239438 [RxdqsGatingPostProcess] freq 400
6573 06:02:52.242937 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6574 06:02:52.246564 best DQS0 dly(2T, 0.5T) = (0, 10)
6575 06:02:52.249769 best DQS1 dly(2T, 0.5T) = (0, 10)
6576 06:02:52.252991 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6577 06:02:52.256070 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6578 06:02:52.259077 best DQS0 dly(2T, 0.5T) = (0, 10)
6579 06:02:52.262737 best DQS1 dly(2T, 0.5T) = (0, 10)
6580 06:02:52.266231 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6581 06:02:52.269267 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6582 06:02:52.272406 Pre-setting of DQS Precalculation
6583 06:02:52.275896 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6584 06:02:52.276030 ==
6585 06:02:52.279296 Dram Type= 6, Freq= 0, CH_1, rank 0
6586 06:02:52.285614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 06:02:52.285840 ==
6588 06:02:52.289083 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6589 06:02:52.296076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6590 06:02:52.298961 [CA 0] Center 36 (8~64) winsize 57
6591 06:02:52.302313 [CA 1] Center 36 (8~64) winsize 57
6592 06:02:52.305886 [CA 2] Center 36 (8~64) winsize 57
6593 06:02:52.309453 [CA 3] Center 36 (8~64) winsize 57
6594 06:02:52.312252 [CA 4] Center 36 (8~64) winsize 57
6595 06:02:52.315807 [CA 5] Center 36 (8~64) winsize 57
6596 06:02:52.316104
6597 06:02:52.319193 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6598 06:02:52.319490
6599 06:02:52.322547 [CATrainingPosCal] consider 1 rank data
6600 06:02:52.325781 u2DelayCellTimex100 = 270/100 ps
6601 06:02:52.329340 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 06:02:52.332132 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 06:02:52.335525 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 06:02:52.339011 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 06:02:52.342495 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 06:02:52.349349 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 06:02:52.349475
6608 06:02:52.352060 CA PerBit enable=1, Macro0, CA PI delay=36
6609 06:02:52.352193
6610 06:02:52.355763 [CBTSetCACLKResult] CA Dly = 36
6611 06:02:52.355855 CS Dly: 1 (0~32)
6612 06:02:52.355928 ==
6613 06:02:52.358643 Dram Type= 6, Freq= 0, CH_1, rank 1
6614 06:02:52.362042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 06:02:52.365588 ==
6616 06:02:52.368792 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6617 06:02:52.375679 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6618 06:02:52.379055 [CA 0] Center 36 (8~64) winsize 57
6619 06:02:52.382604 [CA 1] Center 36 (8~64) winsize 57
6620 06:02:52.385729 [CA 2] Center 36 (8~64) winsize 57
6621 06:02:52.388806 [CA 3] Center 36 (8~64) winsize 57
6622 06:02:52.391794 [CA 4] Center 36 (8~64) winsize 57
6623 06:02:52.395348 [CA 5] Center 36 (8~64) winsize 57
6624 06:02:52.395429
6625 06:02:52.398415 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6626 06:02:52.398496
6627 06:02:52.401800 [CATrainingPosCal] consider 2 rank data
6628 06:02:52.405401 u2DelayCellTimex100 = 270/100 ps
6629 06:02:52.408437 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 06:02:52.412594 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 06:02:52.415367 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 06:02:52.418759 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 06:02:52.422397 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 06:02:52.425262 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 06:02:52.425676
6636 06:02:52.428733 CA PerBit enable=1, Macro0, CA PI delay=36
6637 06:02:52.431975
6638 06:02:52.432433 [CBTSetCACLKResult] CA Dly = 36
6639 06:02:52.435430 CS Dly: 1 (0~32)
6640 06:02:52.435850
6641 06:02:52.438734 ----->DramcWriteLeveling(PI) begin...
6642 06:02:52.439162 ==
6643 06:02:52.442309 Dram Type= 6, Freq= 0, CH_1, rank 0
6644 06:02:52.445616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 06:02:52.446123 ==
6646 06:02:52.449097 Write leveling (Byte 0): 40 => 8
6647 06:02:52.451887 Write leveling (Byte 1): 40 => 8
6648 06:02:52.455645 DramcWriteLeveling(PI) end<-----
6649 06:02:52.456217
6650 06:02:52.456661 ==
6651 06:02:52.458489 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 06:02:52.461974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 06:02:52.462398 ==
6654 06:02:52.465448 [Gating] SW mode calibration
6655 06:02:52.471960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6656 06:02:52.478783 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6657 06:02:52.481895 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6658 06:02:52.488212 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6659 06:02:52.491377 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 06:02:52.494842 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 06:02:52.501726 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 06:02:52.504493 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 06:02:52.507877 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 06:02:52.514858 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 06:02:52.518079 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 06:02:52.521205 Total UI for P1: 0, mck2ui 16
6667 06:02:52.524255 best dqsien dly found for B0: ( 0, 14, 24)
6668 06:02:52.527722 Total UI for P1: 0, mck2ui 16
6669 06:02:52.531017 best dqsien dly found for B1: ( 0, 14, 24)
6670 06:02:52.534306 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6671 06:02:52.537846 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6672 06:02:52.537931
6673 06:02:52.541314 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6674 06:02:52.543983 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6675 06:02:52.547894 [Gating] SW calibration Done
6676 06:02:52.548415 ==
6677 06:02:52.551208 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 06:02:52.554840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 06:02:52.558214 ==
6680 06:02:52.558635 RX Vref Scan: 0
6681 06:02:52.558970
6682 06:02:52.561401 RX Vref 0 -> 0, step: 1
6683 06:02:52.561821
6684 06:02:52.564873 RX Delay -410 -> 252, step: 16
6685 06:02:52.567673 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6686 06:02:52.571145 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6687 06:02:52.574617 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6688 06:02:52.580834 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6689 06:02:52.584485 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6690 06:02:52.588032 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6691 06:02:52.590745 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6692 06:02:52.597524 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6693 06:02:52.600822 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6694 06:02:52.604719 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6695 06:02:52.612089 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6696 06:02:52.614475 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6697 06:02:52.617167 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6698 06:02:52.620627 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6699 06:02:52.624863 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6700 06:02:52.630476 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6701 06:02:52.630708 ==
6702 06:02:52.633701 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 06:02:52.637244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 06:02:52.637430 ==
6705 06:02:52.637591 DQS Delay:
6706 06:02:52.640783 DQS0 = 35, DQS1 = 35
6707 06:02:52.640970 DQM Delay:
6708 06:02:52.643833 DQM0 = 17, DQM1 = 13
6709 06:02:52.644056 DQ Delay:
6710 06:02:52.646947 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6711 06:02:52.650224 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6712 06:02:52.654100 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6713 06:02:52.657301 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =16
6714 06:02:52.657488
6715 06:02:52.657634
6716 06:02:52.657767 ==
6717 06:02:52.660138 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 06:02:52.663948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 06:02:52.664104 ==
6720 06:02:52.667374
6721 06:02:52.667508
6722 06:02:52.667611 TX Vref Scan disable
6723 06:02:52.670551 == TX Byte 0 ==
6724 06:02:52.673745 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 06:02:52.676975 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 06:02:52.680619 == TX Byte 1 ==
6727 06:02:52.684070 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 06:02:52.687469 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 06:02:52.687601 ==
6730 06:02:52.690175 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 06:02:52.693723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 06:02:52.697233 ==
6733 06:02:52.697423
6734 06:02:52.697532
6735 06:02:52.697635 TX Vref Scan disable
6736 06:02:52.700511 == TX Byte 0 ==
6737 06:02:52.703962 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 06:02:52.707366 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 06:02:52.710627 == TX Byte 1 ==
6740 06:02:52.714104 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 06:02:52.717241 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 06:02:52.717356
6743 06:02:52.717446 [DATLAT]
6744 06:02:52.720509 Freq=400, CH1 RK0
6745 06:02:52.720635
6746 06:02:52.724077 DATLAT Default: 0xf
6747 06:02:52.724202 0, 0xFFFF, sum = 0
6748 06:02:52.727168 1, 0xFFFF, sum = 0
6749 06:02:52.727391 2, 0xFFFF, sum = 0
6750 06:02:52.730768 3, 0xFFFF, sum = 0
6751 06:02:52.731008 4, 0xFFFF, sum = 0
6752 06:02:52.734192 5, 0xFFFF, sum = 0
6753 06:02:52.734429 6, 0xFFFF, sum = 0
6754 06:02:52.737562 7, 0xFFFF, sum = 0
6755 06:02:52.737756 8, 0xFFFF, sum = 0
6756 06:02:52.740380 9, 0xFFFF, sum = 0
6757 06:02:52.740605 10, 0xFFFF, sum = 0
6758 06:02:52.744078 11, 0xFFFF, sum = 0
6759 06:02:52.744418 12, 0xFFFF, sum = 0
6760 06:02:52.747320 13, 0x0, sum = 1
6761 06:02:52.747581 14, 0x0, sum = 2
6762 06:02:52.750758 15, 0x0, sum = 3
6763 06:02:52.751087 16, 0x0, sum = 4
6764 06:02:52.754150 best_step = 14
6765 06:02:52.754570
6766 06:02:52.754913 ==
6767 06:02:52.757905 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 06:02:52.760582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 06:02:52.761006 ==
6770 06:02:52.761342 RX Vref Scan: 1
6771 06:02:52.764000
6772 06:02:52.764450 RX Vref 0 -> 0, step: 1
6773 06:02:52.764790
6774 06:02:52.767571 RX Delay -311 -> 252, step: 8
6775 06:02:52.767998
6776 06:02:52.770865 Set Vref, RX VrefLevel [Byte0]: 54
6777 06:02:52.773908 [Byte1]: 53
6778 06:02:52.778439
6779 06:02:52.778848 Final RX Vref Byte 0 = 54 to rank0
6780 06:02:52.781464 Final RX Vref Byte 1 = 53 to rank0
6781 06:02:52.784989 Final RX Vref Byte 0 = 54 to rank1
6782 06:02:52.788507 Final RX Vref Byte 1 = 53 to rank1==
6783 06:02:52.791789 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 06:02:52.798019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 06:02:52.798447 ==
6786 06:02:52.798978 DQS Delay:
6787 06:02:52.801245 DQS0 = 32, DQS1 = 32
6788 06:02:52.801739 DQM Delay:
6789 06:02:52.802197 DQM0 = 13, DQM1 = 10
6790 06:02:52.804810 DQ Delay:
6791 06:02:52.808192 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6792 06:02:52.808677 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6793 06:02:52.811716 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6794 06:02:52.814471 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6795 06:02:52.814885
6796 06:02:52.817848
6797 06:02:52.824993 [DQSOSCAuto] RK0, (LSB)MR18= 0x90c8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6798 06:02:52.828243 CH1 RK0: MR19=C0C, MR18=90C8
6799 06:02:52.834808 CH1_RK0: MR19=0xC0C, MR18=0x90C8, DQSOSC=385, MR23=63, INC=398, DEC=265
6800 06:02:52.835226 ==
6801 06:02:52.838203 Dram Type= 6, Freq= 0, CH_1, rank 1
6802 06:02:52.840948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 06:02:52.841367 ==
6804 06:02:52.844656 [Gating] SW mode calibration
6805 06:02:52.851400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6806 06:02:52.858042 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6807 06:02:52.861542 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6808 06:02:52.864696 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6809 06:02:52.871707 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6810 06:02:52.874469 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 06:02:52.878148 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 06:02:52.881515 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 06:02:52.888243 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 06:02:52.890816 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 06:02:52.894166 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 06:02:52.897591 Total UI for P1: 0, mck2ui 16
6817 06:02:52.901129 best dqsien dly found for B0: ( 0, 14, 24)
6818 06:02:52.904506 Total UI for P1: 0, mck2ui 16
6819 06:02:52.907785 best dqsien dly found for B1: ( 0, 14, 24)
6820 06:02:52.910964 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6821 06:02:52.917798 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6822 06:02:52.918342
6823 06:02:52.921028 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6824 06:02:52.924781 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6825 06:02:52.927331 [Gating] SW calibration Done
6826 06:02:52.927790 ==
6827 06:02:52.931023 Dram Type= 6, Freq= 0, CH_1, rank 1
6828 06:02:52.934395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 06:02:52.934953 ==
6830 06:02:52.935314 RX Vref Scan: 0
6831 06:02:52.937845
6832 06:02:52.938297 RX Vref 0 -> 0, step: 1
6833 06:02:52.938673
6834 06:02:52.941023 RX Delay -410 -> 252, step: 16
6835 06:02:52.944306 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6836 06:02:52.951434 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6837 06:02:52.953923 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6838 06:02:52.957321 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6839 06:02:52.961705 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6840 06:02:52.967895 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6841 06:02:52.971119 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6842 06:02:52.974573 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6843 06:02:52.977563 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6844 06:02:52.984619 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6845 06:02:52.988160 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6846 06:02:52.990914 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6847 06:02:52.994294 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6848 06:02:53.000935 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6849 06:02:53.004330 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6850 06:02:53.008208 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6851 06:02:53.008814 ==
6852 06:02:53.011552 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 06:02:53.014303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 06:02:53.017396 ==
6855 06:02:53.017855 DQS Delay:
6856 06:02:53.018216 DQS0 = 35, DQS1 = 35
6857 06:02:53.020915 DQM Delay:
6858 06:02:53.021494 DQM0 = 17, DQM1 = 14
6859 06:02:53.023848 DQ Delay:
6860 06:02:53.028068 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6861 06:02:53.028665 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6862 06:02:53.031312 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6863 06:02:53.034330 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6864 06:02:53.034874
6865 06:02:53.035277
6866 06:02:53.037592 ==
6867 06:02:53.041099 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 06:02:53.044454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 06:02:53.044914 ==
6870 06:02:53.045279
6871 06:02:53.045616
6872 06:02:53.047112 TX Vref Scan disable
6873 06:02:53.047567 == TX Byte 0 ==
6874 06:02:53.050816 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6875 06:02:53.057257 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6876 06:02:53.057673 == TX Byte 1 ==
6877 06:02:53.060749 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6878 06:02:53.067207 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6879 06:02:53.067541 ==
6880 06:02:53.070483 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 06:02:53.073989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 06:02:53.074188 ==
6883 06:02:53.074331
6884 06:02:53.074461
6885 06:02:53.076764 TX Vref Scan disable
6886 06:02:53.076942 == TX Byte 0 ==
6887 06:02:53.080013 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6888 06:02:53.086559 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6889 06:02:53.086689 == TX Byte 1 ==
6890 06:02:53.090074 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6891 06:02:53.096914 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6892 06:02:53.097015
6893 06:02:53.097094 [DATLAT]
6894 06:02:53.097166 Freq=400, CH1 RK1
6895 06:02:53.097237
6896 06:02:53.100494 DATLAT Default: 0xe
6897 06:02:53.100584 0, 0xFFFF, sum = 0
6898 06:02:53.103247 1, 0xFFFF, sum = 0
6899 06:02:53.103331 2, 0xFFFF, sum = 0
6900 06:02:53.106660 3, 0xFFFF, sum = 0
6901 06:02:53.109857 4, 0xFFFF, sum = 0
6902 06:02:53.109939 5, 0xFFFF, sum = 0
6903 06:02:53.113384 6, 0xFFFF, sum = 0
6904 06:02:53.113467 7, 0xFFFF, sum = 0
6905 06:02:53.116807 8, 0xFFFF, sum = 0
6906 06:02:53.116889 9, 0xFFFF, sum = 0
6907 06:02:53.120332 10, 0xFFFF, sum = 0
6908 06:02:53.120415 11, 0xFFFF, sum = 0
6909 06:02:53.123172 12, 0xFFFF, sum = 0
6910 06:02:53.123254 13, 0x0, sum = 1
6911 06:02:53.126660 14, 0x0, sum = 2
6912 06:02:53.126742 15, 0x0, sum = 3
6913 06:02:53.130239 16, 0x0, sum = 4
6914 06:02:53.130320 best_step = 14
6915 06:02:53.130385
6916 06:02:53.130443 ==
6917 06:02:53.133650 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 06:02:53.137028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 06:02:53.139564 ==
6920 06:02:53.139685 RX Vref Scan: 0
6921 06:02:53.139754
6922 06:02:53.142982 RX Vref 0 -> 0, step: 1
6923 06:02:53.143064
6924 06:02:53.146989 RX Delay -311 -> 252, step: 8
6925 06:02:53.149686 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6926 06:02:53.156488 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6927 06:02:53.159832 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6928 06:02:53.163827 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6929 06:02:53.166923 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6930 06:02:53.173451 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6931 06:02:53.176880 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6932 06:02:53.180296 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6933 06:02:53.183211 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6934 06:02:53.189896 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6935 06:02:53.193130 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6936 06:02:53.196729 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6937 06:02:53.200183 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6938 06:02:53.206567 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6939 06:02:53.210196 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6940 06:02:53.212903 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6941 06:02:53.212988 ==
6942 06:02:53.216265 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 06:02:53.219855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 06:02:53.223502 ==
6945 06:02:53.223585 DQS Delay:
6946 06:02:53.223686 DQS0 = 28, DQS1 = 32
6947 06:02:53.226369 DQM Delay:
6948 06:02:53.226450 DQM0 = 11, DQM1 = 11
6949 06:02:53.230246 DQ Delay:
6950 06:02:53.230806 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6951 06:02:53.233776 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
6952 06:02:53.236679 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6953 06:02:53.240080 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6954 06:02:53.240635
6955 06:02:53.240973
6956 06:02:53.249886 [DQSOSCAuto] RK1, (LSB)MR18= 0xc255, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6957 06:02:53.253452 CH1 RK1: MR19=C0C, MR18=C255
6958 06:02:53.259923 CH1_RK1: MR19=0xC0C, MR18=0xC255, DQSOSC=385, MR23=63, INC=398, DEC=265
6959 06:02:53.260439 [RxdqsGatingPostProcess] freq 400
6960 06:02:53.267046 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6961 06:02:53.270329 best DQS0 dly(2T, 0.5T) = (0, 10)
6962 06:02:53.273113 best DQS1 dly(2T, 0.5T) = (0, 10)
6963 06:02:53.277161 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6964 06:02:53.280165 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6965 06:02:53.283545 best DQS0 dly(2T, 0.5T) = (0, 10)
6966 06:02:53.286637 best DQS1 dly(2T, 0.5T) = (0, 10)
6967 06:02:53.290185 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6968 06:02:53.293239 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6969 06:02:53.296588 Pre-setting of DQS Precalculation
6970 06:02:53.299821 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6971 06:02:53.306483 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6972 06:02:53.312882 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6973 06:02:53.316321
6974 06:02:53.316750
6975 06:02:53.317082 [Calibration Summary] 800 Mbps
6976 06:02:53.319729 CH 0, Rank 0
6977 06:02:53.320215 SW Impedance : PASS
6978 06:02:53.323336 DUTY Scan : NO K
6979 06:02:53.326571 ZQ Calibration : PASS
6980 06:02:53.326984 Jitter Meter : NO K
6981 06:02:53.329383 CBT Training : PASS
6982 06:02:53.332958 Write leveling : PASS
6983 06:02:53.333373 RX DQS gating : PASS
6984 06:02:53.336680 RX DQ/DQS(RDDQC) : PASS
6985 06:02:53.339458 TX DQ/DQS : PASS
6986 06:02:53.339868 RX DATLAT : PASS
6987 06:02:53.342863 RX DQ/DQS(Engine): PASS
6988 06:02:53.346354 TX OE : NO K
6989 06:02:53.346826 All Pass.
6990 06:02:53.347207
6991 06:02:53.347621 CH 0, Rank 1
6992 06:02:53.349824 SW Impedance : PASS
6993 06:02:53.352793 DUTY Scan : NO K
6994 06:02:53.353236 ZQ Calibration : PASS
6995 06:02:53.356368 Jitter Meter : NO K
6996 06:02:53.359141 CBT Training : PASS
6997 06:02:53.359550 Write leveling : NO K
6998 06:02:53.362634 RX DQS gating : PASS
6999 06:02:53.366157 RX DQ/DQS(RDDQC) : PASS
7000 06:02:53.366569 TX DQ/DQS : PASS
7001 06:02:53.369733 RX DATLAT : PASS
7002 06:02:53.370145 RX DQ/DQS(Engine): PASS
7003 06:02:53.372871 TX OE : NO K
7004 06:02:53.373281 All Pass.
7005 06:02:53.373611
7006 06:02:53.376064 CH 1, Rank 0
7007 06:02:53.376510 SW Impedance : PASS
7008 06:02:53.379037 DUTY Scan : NO K
7009 06:02:53.382862 ZQ Calibration : PASS
7010 06:02:53.383392 Jitter Meter : NO K
7011 06:02:53.386002 CBT Training : PASS
7012 06:02:53.389223 Write leveling : PASS
7013 06:02:53.389632 RX DQS gating : PASS
7014 06:02:53.392377 RX DQ/DQS(RDDQC) : PASS
7015 06:02:53.395708 TX DQ/DQS : PASS
7016 06:02:53.396138 RX DATLAT : PASS
7017 06:02:53.398889 RX DQ/DQS(Engine): PASS
7018 06:02:53.402582 TX OE : NO K
7019 06:02:53.402993 All Pass.
7020 06:02:53.403321
7021 06:02:53.403620 CH 1, Rank 1
7022 06:02:53.405893 SW Impedance : PASS
7023 06:02:53.409301 DUTY Scan : NO K
7024 06:02:53.409715 ZQ Calibration : PASS
7025 06:02:53.412539 Jitter Meter : NO K
7026 06:02:53.415550 CBT Training : PASS
7027 06:02:53.415963 Write leveling : NO K
7028 06:02:53.419339 RX DQS gating : PASS
7029 06:02:53.422194 RX DQ/DQS(RDDQC) : PASS
7030 06:02:53.422606 TX DQ/DQS : PASS
7031 06:02:53.425756 RX DATLAT : PASS
7032 06:02:53.426169 RX DQ/DQS(Engine): PASS
7033 06:02:53.429290 TX OE : NO K
7034 06:02:53.429703 All Pass.
7035 06:02:53.430089
7036 06:02:53.432562 DramC Write-DBI off
7037 06:02:53.435202 PER_BANK_REFRESH: Hybrid Mode
7038 06:02:53.435612 TX_TRACKING: ON
7039 06:02:53.445893 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7040 06:02:53.449223 [FAST_K] Save calibration result to emmc
7041 06:02:53.452215 dramc_set_vcore_voltage set vcore to 725000
7042 06:02:53.455822 Read voltage for 1600, 0
7043 06:02:53.456235 Vio18 = 0
7044 06:02:53.459134 Vcore = 725000
7045 06:02:53.459574 Vdram = 0
7046 06:02:53.459905 Vddq = 0
7047 06:02:53.460349 Vmddr = 0
7048 06:02:53.465739 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7049 06:02:53.469189 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7050 06:02:53.471986 MEM_TYPE=3, freq_sel=13
7051 06:02:53.475557 sv_algorithm_assistance_LP4_3733
7052 06:02:53.479014 ============ PULL DRAM RESETB DOWN ============
7053 06:02:53.485287 ========== PULL DRAM RESETB DOWN end =========
7054 06:02:53.489028 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7055 06:02:53.492091 ===================================
7056 06:02:53.495652 LPDDR4 DRAM CONFIGURATION
7057 06:02:53.498601 ===================================
7058 06:02:53.499083 EX_ROW_EN[0] = 0x0
7059 06:02:53.502295 EX_ROW_EN[1] = 0x0
7060 06:02:53.502815 LP4Y_EN = 0x0
7061 06:02:53.505528 WORK_FSP = 0x1
7062 06:02:53.506073 WL = 0x5
7063 06:02:53.508774 RL = 0x5
7064 06:02:53.509206 BL = 0x2
7065 06:02:53.511789 RPST = 0x0
7066 06:02:53.512234 RD_PRE = 0x0
7067 06:02:53.515300 WR_PRE = 0x1
7068 06:02:53.518667 WR_PST = 0x1
7069 06:02:53.519191 DBI_WR = 0x0
7070 06:02:53.521979 DBI_RD = 0x0
7071 06:02:53.522482 OTF = 0x1
7072 06:02:53.525297 ===================================
7073 06:02:53.528487 ===================================
7074 06:02:53.528951 ANA top config
7075 06:02:53.532321 ===================================
7076 06:02:53.535560 DLL_ASYNC_EN = 0
7077 06:02:53.538951 ALL_SLAVE_EN = 0
7078 06:02:53.542289 NEW_RANK_MODE = 1
7079 06:02:53.545027 DLL_IDLE_MODE = 1
7080 06:02:53.545446 LP45_APHY_COMB_EN = 1
7081 06:02:53.548619 TX_ODT_DIS = 0
7082 06:02:53.551999 NEW_8X_MODE = 1
7083 06:02:53.555354 ===================================
7084 06:02:53.559071 ===================================
7085 06:02:53.561962 data_rate = 3200
7086 06:02:53.565409 CKR = 1
7087 06:02:53.566013 DQ_P2S_RATIO = 8
7088 06:02:53.568205 ===================================
7089 06:02:53.571873 CA_P2S_RATIO = 8
7090 06:02:53.575331 DQ_CA_OPEN = 0
7091 06:02:53.578849 DQ_SEMI_OPEN = 0
7092 06:02:53.581803 CA_SEMI_OPEN = 0
7093 06:02:53.585299 CA_FULL_RATE = 0
7094 06:02:53.585718 DQ_CKDIV4_EN = 0
7095 06:02:53.588867 CA_CKDIV4_EN = 0
7096 06:02:53.591513 CA_PREDIV_EN = 0
7097 06:02:53.595384 PH8_DLY = 12
7098 06:02:53.598571 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7099 06:02:53.601956 DQ_AAMCK_DIV = 4
7100 06:02:53.602375 CA_AAMCK_DIV = 4
7101 06:02:53.605357 CA_ADMCK_DIV = 4
7102 06:02:53.608745 DQ_TRACK_CA_EN = 0
7103 06:02:53.611370 CA_PICK = 1600
7104 06:02:53.614687 CA_MCKIO = 1600
7105 06:02:53.618725 MCKIO_SEMI = 0
7106 06:02:53.621294 PLL_FREQ = 3068
7107 06:02:53.624882 DQ_UI_PI_RATIO = 32
7108 06:02:53.625322 CA_UI_PI_RATIO = 0
7109 06:02:53.628166 ===================================
7110 06:02:53.631646 ===================================
7111 06:02:53.634953 memory_type:LPDDR4
7112 06:02:53.638027 GP_NUM : 10
7113 06:02:53.638466 SRAM_EN : 1
7114 06:02:53.641521 MD32_EN : 0
7115 06:02:53.645056 ===================================
7116 06:02:53.648018 [ANA_INIT] >>>>>>>>>>>>>>
7117 06:02:53.648536 <<<<<< [CONFIGURE PHASE]: ANA_TX
7118 06:02:53.654733 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7119 06:02:53.655451 ===================================
7120 06:02:53.657847 data_rate = 3200,PCW = 0X7600
7121 06:02:53.661745 ===================================
7122 06:02:53.664405 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7123 06:02:53.671441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7124 06:02:53.678157 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7125 06:02:53.681537 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7126 06:02:53.684977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7127 06:02:53.687752 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7128 06:02:53.691321 [ANA_INIT] flow start
7129 06:02:53.691771 [ANA_INIT] PLL >>>>>>>>
7130 06:02:53.694856 [ANA_INIT] PLL <<<<<<<<
7131 06:02:53.697806 [ANA_INIT] MIDPI >>>>>>>>
7132 06:02:53.701186 [ANA_INIT] MIDPI <<<<<<<<
7133 06:02:53.701659 [ANA_INIT] DLL >>>>>>>>
7134 06:02:53.704713 [ANA_INIT] DLL <<<<<<<<
7135 06:02:53.705252 [ANA_INIT] flow end
7136 06:02:53.711225 ============ LP4 DIFF to SE enter ============
7137 06:02:53.714737 ============ LP4 DIFF to SE exit ============
7138 06:02:53.718166 [ANA_INIT] <<<<<<<<<<<<<
7139 06:02:53.721575 [Flow] Enable top DCM control >>>>>
7140 06:02:53.724964 [Flow] Enable top DCM control <<<<<
7141 06:02:53.725404 Enable DLL master slave shuffle
7142 06:02:53.731006 ==============================================================
7143 06:02:53.734577 Gating Mode config
7144 06:02:53.737977 ==============================================================
7145 06:02:53.741455 Config description:
7146 06:02:53.750842 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7147 06:02:53.757840 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7148 06:02:53.761003 SELPH_MODE 0: By rank 1: By Phase
7149 06:02:53.767748 ==============================================================
7150 06:02:53.771125 GAT_TRACK_EN = 1
7151 06:02:53.774144 RX_GATING_MODE = 2
7152 06:02:53.777612 RX_GATING_TRACK_MODE = 2
7153 06:02:53.781182 SELPH_MODE = 1
7154 06:02:53.781698 PICG_EARLY_EN = 1
7155 06:02:53.784135 VALID_LAT_VALUE = 1
7156 06:02:53.791053 ==============================================================
7157 06:02:53.794540 Enter into Gating configuration >>>>
7158 06:02:53.797462 Exit from Gating configuration <<<<
7159 06:02:53.800970 Enter into DVFS_PRE_config >>>>>
7160 06:02:53.810920 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7161 06:02:53.814469 Exit from DVFS_PRE_config <<<<<
7162 06:02:53.817224 Enter into PICG configuration >>>>
7163 06:02:53.820787 Exit from PICG configuration <<<<
7164 06:02:53.824404 [RX_INPUT] configuration >>>>>
7165 06:02:53.827132 [RX_INPUT] configuration <<<<<
7166 06:02:53.830514 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7167 06:02:53.837325 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7168 06:02:53.843881 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7169 06:02:53.850815 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7170 06:02:53.857773 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 06:02:53.860467 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 06:02:53.867312 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7173 06:02:53.870647 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7174 06:02:53.873624 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7175 06:02:53.877260 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7176 06:02:53.884049 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7177 06:02:53.887298 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7178 06:02:53.890550 ===================================
7179 06:02:53.893615 LPDDR4 DRAM CONFIGURATION
7180 06:02:53.897473 ===================================
7181 06:02:53.897894 EX_ROW_EN[0] = 0x0
7182 06:02:53.900425 EX_ROW_EN[1] = 0x0
7183 06:02:53.901017 LP4Y_EN = 0x0
7184 06:02:53.904019 WORK_FSP = 0x1
7185 06:02:53.904473 WL = 0x5
7186 06:02:53.906921 RL = 0x5
7187 06:02:53.907328 BL = 0x2
7188 06:02:53.909996 RPST = 0x0
7189 06:02:53.913791 RD_PRE = 0x0
7190 06:02:53.914203 WR_PRE = 0x1
7191 06:02:53.916702 WR_PST = 0x1
7192 06:02:53.917113 DBI_WR = 0x0
7193 06:02:53.920068 DBI_RD = 0x0
7194 06:02:53.920526 OTF = 0x1
7195 06:02:53.923445 ===================================
7196 06:02:53.927064 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7197 06:02:53.933518 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7198 06:02:53.936785 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7199 06:02:53.940184 ===================================
7200 06:02:53.943493 LPDDR4 DRAM CONFIGURATION
7201 06:02:53.946682 ===================================
7202 06:02:53.947098 EX_ROW_EN[0] = 0x10
7203 06:02:53.949776 EX_ROW_EN[1] = 0x0
7204 06:02:53.950222 LP4Y_EN = 0x0
7205 06:02:53.953567 WORK_FSP = 0x1
7206 06:02:53.954127 WL = 0x5
7207 06:02:53.956317 RL = 0x5
7208 06:02:53.956743 BL = 0x2
7209 06:02:53.959871 RPST = 0x0
7210 06:02:53.963295 RD_PRE = 0x0
7211 06:02:53.963735 WR_PRE = 0x1
7212 06:02:53.966332 WR_PST = 0x1
7213 06:02:53.966744 DBI_WR = 0x0
7214 06:02:53.969963 DBI_RD = 0x0
7215 06:02:53.970388 OTF = 0x1
7216 06:02:53.973008 ===================================
7217 06:02:53.980259 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7218 06:02:53.980746 ==
7219 06:02:53.982964 Dram Type= 6, Freq= 0, CH_0, rank 0
7220 06:02:53.986513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7221 06:02:53.986956 ==
7222 06:02:53.990093 [Duty_Offset_Calibration]
7223 06:02:53.990533 B0:2 B1:1 CA:1
7224 06:02:53.993009
7225 06:02:53.996490 [DutyScan_Calibration_Flow] k_type=0
7226 06:02:54.004851
7227 06:02:54.005263 ==CLK 0==
7228 06:02:54.008065 Final CLK duty delay cell = 0
7229 06:02:54.010911 [0] MAX Duty = 5156%(X100), DQS PI = 22
7230 06:02:54.014704 [0] MIN Duty = 4875%(X100), DQS PI = 0
7231 06:02:54.015128 [0] AVG Duty = 5015%(X100)
7232 06:02:54.015460
7233 06:02:54.017752 CH0 CLK Duty spec in!! Max-Min= 281%
7234 06:02:54.024946 [DutyScan_Calibration_Flow] ====Done====
7235 06:02:54.025366
7236 06:02:54.027645 [DutyScan_Calibration_Flow] k_type=1
7237 06:02:54.043445
7238 06:02:54.043934 ==DQS 0 ==
7239 06:02:54.047058 Final DQS duty delay cell = -4
7240 06:02:54.050462 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7241 06:02:54.053933 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7242 06:02:54.057199 [-4] AVG Duty = 4891%(X100)
7243 06:02:54.057644
7244 06:02:54.057978 ==DQS 1 ==
7245 06:02:54.060350 Final DQS duty delay cell = 0
7246 06:02:54.063550 [0] MAX Duty = 5187%(X100), DQS PI = 10
7247 06:02:54.066632 [0] MIN Duty = 5031%(X100), DQS PI = 52
7248 06:02:54.070551 [0] AVG Duty = 5109%(X100)
7249 06:02:54.070976
7250 06:02:54.073443 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7251 06:02:54.073870
7252 06:02:54.076658 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7253 06:02:54.080038 [DutyScan_Calibration_Flow] ====Done====
7254 06:02:54.080492
7255 06:02:54.083573 [DutyScan_Calibration_Flow] k_type=3
7256 06:02:54.100570
7257 06:02:54.101000 ==DQM 0 ==
7258 06:02:54.103362 Final DQM duty delay cell = 0
7259 06:02:54.106854 [0] MAX Duty = 5187%(X100), DQS PI = 26
7260 06:02:54.110242 [0] MIN Duty = 4876%(X100), DQS PI = 60
7261 06:02:54.113802 [0] AVG Duty = 5031%(X100)
7262 06:02:54.114225
7263 06:02:54.114561 ==DQM 1 ==
7264 06:02:54.116644 Final DQM duty delay cell = -4
7265 06:02:54.120183 [-4] MAX Duty = 4969%(X100), DQS PI = 60
7266 06:02:54.123788 [-4] MIN Duty = 4813%(X100), DQS PI = 14
7267 06:02:54.126661 [-4] AVG Duty = 4891%(X100)
7268 06:02:54.127086
7269 06:02:54.129960 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7270 06:02:54.130387
7271 06:02:54.133182 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7272 06:02:54.136523 [DutyScan_Calibration_Flow] ====Done====
7273 06:02:54.136949
7274 06:02:54.140366 [DutyScan_Calibration_Flow] k_type=2
7275 06:02:54.157579
7276 06:02:54.158008 ==DQ 0 ==
7277 06:02:54.161430 Final DQ duty delay cell = 0
7278 06:02:54.164423 [0] MAX Duty = 5062%(X100), DQS PI = 26
7279 06:02:54.167954 [0] MIN Duty = 4907%(X100), DQS PI = 0
7280 06:02:54.168423 [0] AVG Duty = 4984%(X100)
7281 06:02:54.168768
7282 06:02:54.170820 ==DQ 1 ==
7283 06:02:54.174147 Final DQ duty delay cell = 0
7284 06:02:54.178157 [0] MAX Duty = 5156%(X100), DQS PI = 22
7285 06:02:54.180783 [0] MIN Duty = 4907%(X100), DQS PI = 34
7286 06:02:54.181211 [0] AVG Duty = 5031%(X100)
7287 06:02:54.181547
7288 06:02:54.184401 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7289 06:02:54.187995
7290 06:02:54.191372 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7291 06:02:54.194170 [DutyScan_Calibration_Flow] ====Done====
7292 06:02:54.194591 ==
7293 06:02:54.197651 Dram Type= 6, Freq= 0, CH_1, rank 0
7294 06:02:54.201225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7295 06:02:54.201650 ==
7296 06:02:54.204061 [Duty_Offset_Calibration]
7297 06:02:54.204548 B0:1 B1:0 CA:0
7298 06:02:54.204886
7299 06:02:54.207626 [DutyScan_Calibration_Flow] k_type=0
7300 06:02:54.217404
7301 06:02:54.217823 ==CLK 0==
7302 06:02:54.220706 Final CLK duty delay cell = -4
7303 06:02:54.223537 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7304 06:02:54.227103 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7305 06:02:54.230642 [-4] AVG Duty = 4906%(X100)
7306 06:02:54.230941
7307 06:02:54.233417 CH1 CLK Duty spec in!! Max-Min= 125%
7308 06:02:54.236970 [DutyScan_Calibration_Flow] ====Done====
7309 06:02:54.237268
7310 06:02:54.240121 [DutyScan_Calibration_Flow] k_type=1
7311 06:02:54.257291
7312 06:02:54.257603 ==DQS 0 ==
7313 06:02:54.260545 Final DQS duty delay cell = 0
7314 06:02:54.264019 [0] MAX Duty = 5062%(X100), DQS PI = 10
7315 06:02:54.267505 [0] MIN Duty = 4844%(X100), DQS PI = 0
7316 06:02:54.267807 [0] AVG Duty = 4953%(X100)
7317 06:02:54.270259
7318 06:02:54.270557 ==DQS 1 ==
7319 06:02:54.274137 Final DQS duty delay cell = 0
7320 06:02:54.277567 [0] MAX Duty = 5249%(X100), DQS PI = 16
7321 06:02:54.280355 [0] MIN Duty = 4938%(X100), DQS PI = 8
7322 06:02:54.280666 [0] AVG Duty = 5093%(X100)
7323 06:02:54.280905
7324 06:02:54.287408 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7325 06:02:54.287713
7326 06:02:54.290838 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7327 06:02:54.293971 [DutyScan_Calibration_Flow] ====Done====
7328 06:02:54.294272
7329 06:02:54.296993 [DutyScan_Calibration_Flow] k_type=3
7330 06:02:54.313684
7331 06:02:54.314169 ==DQM 0 ==
7332 06:02:54.317145 Final DQM duty delay cell = 0
7333 06:02:54.320743 [0] MAX Duty = 5218%(X100), DQS PI = 18
7334 06:02:54.324157 [0] MIN Duty = 4969%(X100), DQS PI = 48
7335 06:02:54.324578 [0] AVG Duty = 5093%(X100)
7336 06:02:54.327163
7337 06:02:54.327536 ==DQM 1 ==
7338 06:02:54.330730 Final DQM duty delay cell = 0
7339 06:02:54.334217 [0] MAX Duty = 5093%(X100), DQS PI = 16
7340 06:02:54.337756 [0] MIN Duty = 4907%(X100), DQS PI = 34
7341 06:02:54.340636 [0] AVG Duty = 5000%(X100)
7342 06:02:54.341011
7343 06:02:54.344030 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7344 06:02:54.344540
7345 06:02:54.347469 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7346 06:02:54.350631 [DutyScan_Calibration_Flow] ====Done====
7347 06:02:54.351080
7348 06:02:54.353637 [DutyScan_Calibration_Flow] k_type=2
7349 06:02:54.370147
7350 06:02:54.370533 ==DQ 0 ==
7351 06:02:54.373145 Final DQ duty delay cell = -4
7352 06:02:54.376581 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7353 06:02:54.380388 [-4] MIN Duty = 4875%(X100), DQS PI = 44
7354 06:02:54.383239 [-4] AVG Duty = 4953%(X100)
7355 06:02:54.383622
7356 06:02:54.383923 ==DQ 1 ==
7357 06:02:54.386661 Final DQ duty delay cell = 0
7358 06:02:54.390078 [0] MAX Duty = 5124%(X100), DQS PI = 18
7359 06:02:54.393329 [0] MIN Duty = 4938%(X100), DQS PI = 8
7360 06:02:54.396462 [0] AVG Duty = 5031%(X100)
7361 06:02:54.396991
7362 06:02:54.399737 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7363 06:02:54.400167
7364 06:02:54.402891 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7365 06:02:54.406296 [DutyScan_Calibration_Flow] ====Done====
7366 06:02:54.409916 nWR fixed to 30
7367 06:02:54.413253 [ModeRegInit_LP4] CH0 RK0
7368 06:02:54.413664 [ModeRegInit_LP4] CH0 RK1
7369 06:02:54.416259 [ModeRegInit_LP4] CH1 RK0
7370 06:02:54.419633 [ModeRegInit_LP4] CH1 RK1
7371 06:02:54.420032 match AC timing 5
7372 06:02:54.426506 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7373 06:02:54.429389 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7374 06:02:54.432913 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7375 06:02:54.439537 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7376 06:02:54.443202 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7377 06:02:54.443578 [MiockJmeterHQA]
7378 06:02:54.443949
7379 06:02:54.446746 [DramcMiockJmeter] u1RxGatingPI = 0
7380 06:02:54.449504 0 : 4253, 4026
7381 06:02:54.449893 4 : 4252, 4027
7382 06:02:54.452840 8 : 4252, 4027
7383 06:02:54.453227 12 : 4365, 4140
7384 06:02:54.453598 16 : 4255, 4029
7385 06:02:54.456011 20 : 4255, 4030
7386 06:02:54.456616 24 : 4252, 4027
7387 06:02:54.460056 28 : 4363, 4137
7388 06:02:54.460678 32 : 4363, 4137
7389 06:02:54.463330 36 : 4252, 4027
7390 06:02:54.463763 40 : 4255, 4030
7391 06:02:54.466277 44 : 4253, 4026
7392 06:02:54.466661 48 : 4252, 4027
7393 06:02:54.467022 52 : 4255, 4029
7394 06:02:54.469759 56 : 4363, 4137
7395 06:02:54.470150 60 : 4253, 4027
7396 06:02:54.473353 64 : 4253, 4026
7397 06:02:54.473736 68 : 4250, 4027
7398 06:02:54.476517 72 : 4255, 4029
7399 06:02:54.476902 76 : 4250, 4026
7400 06:02:54.479884 80 : 4360, 4137
7401 06:02:54.480268 84 : 4250, 4026
7402 06:02:54.480653 88 : 4250, 76
7403 06:02:54.482821 92 : 4361, 0
7404 06:02:54.483226 96 : 4252, 0
7405 06:02:54.483668 100 : 4250, 0
7406 06:02:54.486305 104 : 4249, 0
7407 06:02:54.486711 108 : 4250, 0
7408 06:02:54.489866 112 : 4253, 0
7409 06:02:54.490266 116 : 4253, 0
7410 06:02:54.490637 120 : 4250, 0
7411 06:02:54.492605 124 : 4253, 0
7412 06:02:54.492987 128 : 4360, 0
7413 06:02:54.496337 132 : 4250, 0
7414 06:02:54.496752 136 : 4250, 0
7415 06:02:54.497193 140 : 4255, 0
7416 06:02:54.499669 144 : 4250, 0
7417 06:02:54.500068 148 : 4363, 0
7418 06:02:54.502955 152 : 4250, 0
7419 06:02:54.503466 156 : 4253, 0
7420 06:02:54.503898 160 : 4255, 0
7421 06:02:54.505929 164 : 4250, 0
7422 06:02:54.506312 168 : 4250, 0
7423 06:02:54.509410 172 : 4255, 0
7424 06:02:54.509817 176 : 4255, 0
7425 06:02:54.510232 180 : 4250, 0
7426 06:02:54.512887 184 : 4250, 0
7427 06:02:54.513269 188 : 4360, 0
7428 06:02:54.516209 192 : 4250, 0
7429 06:02:54.516679 196 : 4360, 0
7430 06:02:54.517107 200 : 4250, 0
7431 06:02:54.519484 204 : 4250, 1218
7432 06:02:54.519910 208 : 4360, 4067
7433 06:02:54.522437 212 : 4253, 4029
7434 06:02:54.522834 216 : 4255, 4029
7435 06:02:54.526067 220 : 4361, 4137
7436 06:02:54.526482 224 : 4252, 4030
7437 06:02:54.528879 228 : 4250, 4027
7438 06:02:54.529279 232 : 4250, 4027
7439 06:02:54.529585 236 : 4360, 4137
7440 06:02:54.532776 240 : 4250, 4026
7441 06:02:54.533160 244 : 4361, 4137
7442 06:02:54.535922 248 : 4361, 4137
7443 06:02:54.536335 252 : 4250, 4027
7444 06:02:54.539234 256 : 4250, 4026
7445 06:02:54.539615 260 : 4253, 4029
7446 06:02:54.542118 264 : 4250, 4027
7447 06:02:54.542505 268 : 4250, 4027
7448 06:02:54.545820 272 : 4250, 4027
7449 06:02:54.546201 276 : 4253, 4029
7450 06:02:54.549460 280 : 4250, 4026
7451 06:02:54.549879 284 : 4360, 4138
7452 06:02:54.552204 288 : 4360, 4138
7453 06:02:54.552620 292 : 4250, 4026
7454 06:02:54.552960 296 : 4250, 4026
7455 06:02:54.555823 300 : 4250, 4027
7456 06:02:54.556209 304 : 4250, 4027
7457 06:02:54.559129 308 : 4253, 3941
7458 06:02:54.559553 312 : 4253, 2034
7459 06:02:54.559934
7460 06:02:54.562639 MIOCK jitter meter ch=0
7461 06:02:54.563020
7462 06:02:54.565510 1T = (312-88) = 224 dly cells
7463 06:02:54.572360 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7464 06:02:54.572742 ==
7465 06:02:54.575879 Dram Type= 6, Freq= 0, CH_0, rank 0
7466 06:02:54.579105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7467 06:02:54.579611 ==
7468 06:02:54.585876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7469 06:02:54.588606 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7470 06:02:54.592120 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7471 06:02:54.598667 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7472 06:02:54.607538 [CA 0] Center 42 (12~73) winsize 62
7473 06:02:54.610985 [CA 1] Center 42 (12~73) winsize 62
7474 06:02:54.614587 [CA 2] Center 37 (8~67) winsize 60
7475 06:02:54.617455 [CA 3] Center 37 (7~67) winsize 61
7476 06:02:54.621080 [CA 4] Center 36 (6~66) winsize 61
7477 06:02:54.624568 [CA 5] Center 35 (6~64) winsize 59
7478 06:02:54.624952
7479 06:02:54.627819 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7480 06:02:54.628244
7481 06:02:54.631457 [CATrainingPosCal] consider 1 rank data
7482 06:02:54.634736 u2DelayCellTimex100 = 290/100 ps
7483 06:02:54.637960 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7484 06:02:54.644598 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7485 06:02:54.647873 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7486 06:02:54.650763 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7487 06:02:54.654353 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7488 06:02:54.657481 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7489 06:02:54.657945
7490 06:02:54.660609 CA PerBit enable=1, Macro0, CA PI delay=35
7491 06:02:54.661077
7492 06:02:54.664336 [CBTSetCACLKResult] CA Dly = 35
7493 06:02:54.667746 CS Dly: 9 (0~40)
7494 06:02:54.671164 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7495 06:02:54.674433 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7496 06:02:54.674821 ==
7497 06:02:54.677200 Dram Type= 6, Freq= 0, CH_0, rank 1
7498 06:02:54.680872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7499 06:02:54.681263 ==
7500 06:02:54.687147 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7501 06:02:54.690615 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7502 06:02:54.697222 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7503 06:02:54.700718 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7504 06:02:54.711014 [CA 0] Center 43 (13~73) winsize 61
7505 06:02:54.714415 [CA 1] Center 43 (13~73) winsize 61
7506 06:02:54.717211 [CA 2] Center 38 (8~68) winsize 61
7507 06:02:54.720884 [CA 3] Center 38 (8~68) winsize 61
7508 06:02:54.724565 [CA 4] Center 36 (6~66) winsize 61
7509 06:02:54.727372 [CA 5] Center 35 (6~65) winsize 60
7510 06:02:54.727812
7511 06:02:54.730967 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7512 06:02:54.731400
7513 06:02:54.734299 [CATrainingPosCal] consider 2 rank data
7514 06:02:54.737733 u2DelayCellTimex100 = 290/100 ps
7515 06:02:54.744104 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7516 06:02:54.747674 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7517 06:02:54.750878 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7518 06:02:54.754175 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7519 06:02:54.757586 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7520 06:02:54.760945 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7521 06:02:54.761330
7522 06:02:54.764132 CA PerBit enable=1, Macro0, CA PI delay=35
7523 06:02:54.764547
7524 06:02:54.767519 [CBTSetCACLKResult] CA Dly = 35
7525 06:02:54.770778 CS Dly: 10 (0~42)
7526 06:02:54.773843 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7527 06:02:54.777531 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7528 06:02:54.777940
7529 06:02:54.780401 ----->DramcWriteLeveling(PI) begin...
7530 06:02:54.780793 ==
7531 06:02:54.783962 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 06:02:54.787203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 06:02:54.790735 ==
7534 06:02:54.791118 Write leveling (Byte 0): 34 => 34
7535 06:02:54.794175 Write leveling (Byte 1): 26 => 26
7536 06:02:54.797569 DramcWriteLeveling(PI) end<-----
7537 06:02:54.797949
7538 06:02:54.798275 ==
7539 06:02:54.800828 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 06:02:54.807537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 06:02:54.807938 ==
7542 06:02:54.808248 [Gating] SW mode calibration
7543 06:02:54.816911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7544 06:02:54.820536 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7545 06:02:54.826918 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7546 06:02:54.830590 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 06:02:54.833841 1 4 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7548 06:02:54.840663 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
7549 06:02:54.843990 1 4 16 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
7550 06:02:54.846795 1 4 20 | B1->B0 | 3434 3535 | 0 1 | (0 0) (1 1)
7551 06:02:54.850486 1 4 24 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7552 06:02:54.857301 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7553 06:02:54.860695 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7554 06:02:54.864119 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 06:02:54.870461 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 1)
7556 06:02:54.873880 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
7557 06:02:54.877225 1 5 16 | B1->B0 | 3333 2424 | 0 0 | (0 0) (1 0)
7558 06:02:54.883697 1 5 20 | B1->B0 | 2626 2828 | 0 0 | (1 0) (1 1)
7559 06:02:54.886983 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 06:02:54.890279 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 06:02:54.896728 1 6 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
7562 06:02:54.900655 1 6 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7563 06:02:54.903785 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7564 06:02:54.910381 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7565 06:02:54.913420 1 6 16 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
7566 06:02:54.916967 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7567 06:02:54.923264 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 06:02:54.926636 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 06:02:54.930229 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 06:02:54.937057 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 06:02:54.939967 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7572 06:02:54.943628 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7573 06:02:54.950421 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7574 06:02:54.953213 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7575 06:02:54.956483 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7576 06:02:54.963084 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 06:02:54.966642 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 06:02:54.969870 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 06:02:54.976709 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 06:02:54.980063 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 06:02:54.983063 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 06:02:54.990041 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 06:02:54.993591 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 06:02:54.996402 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 06:02:54.999735 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 06:02:55.006501 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 06:02:55.010081 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 06:02:55.013016 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7589 06:02:55.019810 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7590 06:02:55.023417 Total UI for P1: 0, mck2ui 16
7591 06:02:55.026581 best dqsien dly found for B0: ( 1, 9, 12)
7592 06:02:55.029660 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7593 06:02:55.032965 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 06:02:55.036388 Total UI for P1: 0, mck2ui 16
7595 06:02:55.039533 best dqsien dly found for B1: ( 1, 9, 18)
7596 06:02:55.043166 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7597 06:02:55.046616 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7598 06:02:55.047145
7599 06:02:55.052871 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7600 06:02:55.056212 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7601 06:02:55.059666 [Gating] SW calibration Done
7602 06:02:55.060086 ==
7603 06:02:55.062766 Dram Type= 6, Freq= 0, CH_0, rank 0
7604 06:02:55.066184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 06:02:55.066607 ==
7606 06:02:55.066940 RX Vref Scan: 0
7607 06:02:55.069768
7608 06:02:55.070208 RX Vref 0 -> 0, step: 1
7609 06:02:55.070560
7610 06:02:55.073227 RX Delay 0 -> 252, step: 8
7611 06:02:55.075936 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7612 06:02:55.079351 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7613 06:02:55.086435 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7614 06:02:55.089393 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7615 06:02:55.092813 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7616 06:02:55.095644 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7617 06:02:55.099300 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7618 06:02:55.106245 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7619 06:02:55.108959 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7620 06:02:55.112436 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7621 06:02:55.115861 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7622 06:02:55.119382 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7623 06:02:55.126063 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7624 06:02:55.129212 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7625 06:02:55.132415 iDelay=200, Bit 14, Center 143 (96 ~ 191) 96
7626 06:02:55.135957 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7627 06:02:55.136593 ==
7628 06:02:55.139477 Dram Type= 6, Freq= 0, CH_0, rank 0
7629 06:02:55.142279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 06:02:55.146130 ==
7631 06:02:55.146551 DQS Delay:
7632 06:02:55.146886 DQS0 = 0, DQS1 = 0
7633 06:02:55.148842 DQM Delay:
7634 06:02:55.149258 DQM0 = 137, DQM1 = 130
7635 06:02:55.152820 DQ Delay:
7636 06:02:55.155722 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7637 06:02:55.159201 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7638 06:02:55.162495 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7639 06:02:55.165836 DQ12 =131, DQ13 =139, DQ14 =143, DQ15 =135
7640 06:02:55.166305
7641 06:02:55.166803
7642 06:02:55.167311 ==
7643 06:02:55.168807 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 06:02:55.172461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 06:02:55.173067 ==
7646 06:02:55.173590
7647 06:02:55.176011
7648 06:02:55.176638 TX Vref Scan disable
7649 06:02:55.178769 == TX Byte 0 ==
7650 06:02:55.182197 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7651 06:02:55.185515 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7652 06:02:55.188930 == TX Byte 1 ==
7653 06:02:55.192413 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7654 06:02:55.195826 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7655 06:02:55.196383 ==
7656 06:02:55.199135 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 06:02:55.205205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 06:02:55.205630 ==
7659 06:02:55.216805
7660 06:02:55.220383 TX Vref early break, caculate TX vref
7661 06:02:55.223277 TX Vref=16, minBit 7, minWin=22, winSum=377
7662 06:02:55.226854 TX Vref=18, minBit 0, minWin=23, winSum=386
7663 06:02:55.230516 TX Vref=20, minBit 7, minWin=23, winSum=402
7664 06:02:55.233771 TX Vref=22, minBit 2, minWin=25, winSum=411
7665 06:02:55.236452 TX Vref=24, minBit 0, minWin=25, winSum=421
7666 06:02:55.243236 TX Vref=26, minBit 1, minWin=25, winSum=430
7667 06:02:55.246473 TX Vref=28, minBit 1, minWin=25, winSum=426
7668 06:02:55.250736 TX Vref=30, minBit 0, minWin=25, winSum=420
7669 06:02:55.253821 TX Vref=32, minBit 1, minWin=24, winSum=407
7670 06:02:55.260176 [TxChooseVref] Worse bit 1, Min win 25, Win sum 430, Final Vref 26
7671 06:02:55.260785
7672 06:02:55.263529 Final TX Range 0 Vref 26
7673 06:02:55.263941
7674 06:02:55.264272 ==
7675 06:02:55.266880 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 06:02:55.270060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 06:02:55.270521 ==
7678 06:02:55.270867
7679 06:02:55.271200
7680 06:02:55.273464 TX Vref Scan disable
7681 06:02:55.276772 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7682 06:02:55.280363 == TX Byte 0 ==
7683 06:02:55.283831 u2DelayCellOfst[0]=13 cells (4 PI)
7684 06:02:55.286634 u2DelayCellOfst[1]=13 cells (4 PI)
7685 06:02:55.289954 u2DelayCellOfst[2]=10 cells (3 PI)
7686 06:02:55.293316 u2DelayCellOfst[3]=10 cells (3 PI)
7687 06:02:55.296704 u2DelayCellOfst[4]=6 cells (2 PI)
7688 06:02:55.297309 u2DelayCellOfst[5]=0 cells (0 PI)
7689 06:02:55.300210 u2DelayCellOfst[6]=16 cells (5 PI)
7690 06:02:55.303594 u2DelayCellOfst[7]=16 cells (5 PI)
7691 06:02:55.310175 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7692 06:02:55.313442 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7693 06:02:55.313855 == TX Byte 1 ==
7694 06:02:55.316985 u2DelayCellOfst[8]=0 cells (0 PI)
7695 06:02:55.319720 u2DelayCellOfst[9]=0 cells (0 PI)
7696 06:02:55.323266 u2DelayCellOfst[10]=6 cells (2 PI)
7697 06:02:55.326144 u2DelayCellOfst[11]=3 cells (1 PI)
7698 06:02:55.329841 u2DelayCellOfst[12]=6 cells (2 PI)
7699 06:02:55.333416 u2DelayCellOfst[13]=6 cells (2 PI)
7700 06:02:55.336323 u2DelayCellOfst[14]=13 cells (4 PI)
7701 06:02:55.339539 u2DelayCellOfst[15]=10 cells (3 PI)
7702 06:02:55.342901 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7703 06:02:55.346359 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7704 06:02:55.349908 DramC Write-DBI on
7705 06:02:55.350355 ==
7706 06:02:55.352673 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 06:02:55.355992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 06:02:55.356514 ==
7709 06:02:55.356890
7710 06:02:55.357268
7711 06:02:55.359303 TX Vref Scan disable
7712 06:02:55.362642 == TX Byte 0 ==
7713 06:02:55.366146 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7714 06:02:55.369273 == TX Byte 1 ==
7715 06:02:55.372590 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7716 06:02:55.373170 DramC Write-DBI off
7717 06:02:55.373642
7718 06:02:55.375905 [DATLAT]
7719 06:02:55.376449 Freq=1600, CH0 RK0
7720 06:02:55.376861
7721 06:02:55.379569 DATLAT Default: 0xf
7722 06:02:55.380149 0, 0xFFFF, sum = 0
7723 06:02:55.382723 1, 0xFFFF, sum = 0
7724 06:02:55.383213 2, 0xFFFF, sum = 0
7725 06:02:55.385939 3, 0xFFFF, sum = 0
7726 06:02:55.386357 4, 0xFFFF, sum = 0
7727 06:02:55.389397 5, 0xFFFF, sum = 0
7728 06:02:55.389955 6, 0xFFFF, sum = 0
7729 06:02:55.392817 7, 0xFFFF, sum = 0
7730 06:02:55.393239 8, 0xFFFF, sum = 0
7731 06:02:55.396174 9, 0xFFFF, sum = 0
7732 06:02:55.396713 10, 0xFFFF, sum = 0
7733 06:02:55.399453 11, 0xFFFF, sum = 0
7734 06:02:55.402986 12, 0xFFFF, sum = 0
7735 06:02:55.403443 13, 0xFFFF, sum = 0
7736 06:02:55.406428 14, 0x0, sum = 1
7737 06:02:55.406873 15, 0x0, sum = 2
7738 06:02:55.407306 16, 0x0, sum = 3
7739 06:02:55.410018 17, 0x0, sum = 4
7740 06:02:55.410660 best_step = 15
7741 06:02:55.411001
7742 06:02:55.413041 ==
7743 06:02:55.413612 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 06:02:55.419617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 06:02:55.420125 ==
7746 06:02:55.420528 RX Vref Scan: 1
7747 06:02:55.420846
7748 06:02:55.423114 Set Vref Range= 24 -> 127
7749 06:02:55.423597
7750 06:02:55.426457 RX Vref 24 -> 127, step: 1
7751 06:02:55.426927
7752 06:02:55.429516 RX Delay 27 -> 252, step: 4
7753 06:02:55.430018
7754 06:02:55.433277 Set Vref, RX VrefLevel [Byte0]: 24
7755 06:02:55.435942 [Byte1]: 24
7756 06:02:55.436429
7757 06:02:55.439430 Set Vref, RX VrefLevel [Byte0]: 25
7758 06:02:55.442812 [Byte1]: 25
7759 06:02:55.443354
7760 06:02:55.446116 Set Vref, RX VrefLevel [Byte0]: 26
7761 06:02:55.449492 [Byte1]: 26
7762 06:02:55.449988
7763 06:02:55.453055 Set Vref, RX VrefLevel [Byte0]: 27
7764 06:02:55.455815 [Byte1]: 27
7765 06:02:55.460079
7766 06:02:55.460549 Set Vref, RX VrefLevel [Byte0]: 28
7767 06:02:55.463199 [Byte1]: 28
7768 06:02:55.467731
7769 06:02:55.468207 Set Vref, RX VrefLevel [Byte0]: 29
7770 06:02:55.471045 [Byte1]: 29
7771 06:02:55.475410
7772 06:02:55.475951 Set Vref, RX VrefLevel [Byte0]: 30
7773 06:02:55.478786 [Byte1]: 30
7774 06:02:55.483329
7775 06:02:55.483889 Set Vref, RX VrefLevel [Byte0]: 31
7776 06:02:55.485807 [Byte1]: 31
7777 06:02:55.490469
7778 06:02:55.490880 Set Vref, RX VrefLevel [Byte0]: 32
7779 06:02:55.493205 [Byte1]: 32
7780 06:02:55.497661
7781 06:02:55.498072 Set Vref, RX VrefLevel [Byte0]: 33
7782 06:02:55.500745 [Byte1]: 33
7783 06:02:55.505461
7784 06:02:55.505999 Set Vref, RX VrefLevel [Byte0]: 34
7785 06:02:55.508623 [Byte1]: 34
7786 06:02:55.512675
7787 06:02:55.513087 Set Vref, RX VrefLevel [Byte0]: 35
7788 06:02:55.516120 [Byte1]: 35
7789 06:02:55.519915
7790 06:02:55.520368 Set Vref, RX VrefLevel [Byte0]: 36
7791 06:02:55.523828 [Byte1]: 36
7792 06:02:55.527702
7793 06:02:55.528115 Set Vref, RX VrefLevel [Byte0]: 37
7794 06:02:55.530962 [Byte1]: 37
7795 06:02:55.535338
7796 06:02:55.535753 Set Vref, RX VrefLevel [Byte0]: 38
7797 06:02:55.539030 [Byte1]: 38
7798 06:02:55.542938
7799 06:02:55.543354 Set Vref, RX VrefLevel [Byte0]: 39
7800 06:02:55.546455 [Byte1]: 39
7801 06:02:55.550837
7802 06:02:55.551251 Set Vref, RX VrefLevel [Byte0]: 40
7803 06:02:55.553462 [Byte1]: 40
7804 06:02:55.558199
7805 06:02:55.558612 Set Vref, RX VrefLevel [Byte0]: 41
7806 06:02:55.561571 [Byte1]: 41
7807 06:02:55.565891
7808 06:02:55.566545 Set Vref, RX VrefLevel [Byte0]: 42
7809 06:02:55.569092 [Byte1]: 42
7810 06:02:55.573289
7811 06:02:55.573705 Set Vref, RX VrefLevel [Byte0]: 43
7812 06:02:55.576218 [Byte1]: 43
7813 06:02:55.580166
7814 06:02:55.580628 Set Vref, RX VrefLevel [Byte0]: 44
7815 06:02:55.583641 [Byte1]: 44
7816 06:02:55.587887
7817 06:02:55.588457 Set Vref, RX VrefLevel [Byte0]: 45
7818 06:02:55.591495 [Byte1]: 45
7819 06:02:55.595702
7820 06:02:55.596190 Set Vref, RX VrefLevel [Byte0]: 46
7821 06:02:55.599098 [Byte1]: 46
7822 06:02:55.603296
7823 06:02:55.603709 Set Vref, RX VrefLevel [Byte0]: 47
7824 06:02:55.606563 [Byte1]: 47
7825 06:02:55.610903
7826 06:02:55.611345 Set Vref, RX VrefLevel [Byte0]: 48
7827 06:02:55.613659 [Byte1]: 48
7828 06:02:55.618579
7829 06:02:55.619018 Set Vref, RX VrefLevel [Byte0]: 49
7830 06:02:55.621331 [Byte1]: 49
7831 06:02:55.625709
7832 06:02:55.626149 Set Vref, RX VrefLevel [Byte0]: 50
7833 06:02:55.628790 [Byte1]: 50
7834 06:02:55.633333
7835 06:02:55.633748 Set Vref, RX VrefLevel [Byte0]: 51
7836 06:02:55.636392 [Byte1]: 51
7837 06:02:55.641060
7838 06:02:55.641548 Set Vref, RX VrefLevel [Byte0]: 52
7839 06:02:55.644025 [Byte1]: 52
7840 06:02:55.648221
7841 06:02:55.648697 Set Vref, RX VrefLevel [Byte0]: 53
7842 06:02:55.651912 [Byte1]: 53
7843 06:02:55.656106
7844 06:02:55.656615 Set Vref, RX VrefLevel [Byte0]: 54
7845 06:02:55.659283 [Byte1]: 54
7846 06:02:55.663337
7847 06:02:55.663755 Set Vref, RX VrefLevel [Byte0]: 55
7848 06:02:55.666501 [Byte1]: 55
7849 06:02:55.671158
7850 06:02:55.671734 Set Vref, RX VrefLevel [Byte0]: 56
7851 06:02:55.674192 [Byte1]: 56
7852 06:02:55.678816
7853 06:02:55.679313 Set Vref, RX VrefLevel [Byte0]: 57
7854 06:02:55.681825 [Byte1]: 57
7855 06:02:55.685877
7856 06:02:55.686292 Set Vref, RX VrefLevel [Byte0]: 58
7857 06:02:55.689359 [Byte1]: 58
7858 06:02:55.693488
7859 06:02:55.694058 Set Vref, RX VrefLevel [Byte0]: 59
7860 06:02:55.696983 [Byte1]: 59
7861 06:02:55.701303
7862 06:02:55.701766 Set Vref, RX VrefLevel [Byte0]: 60
7863 06:02:55.704002 [Byte1]: 60
7864 06:02:55.708778
7865 06:02:55.709193 Set Vref, RX VrefLevel [Byte0]: 61
7866 06:02:55.715045 [Byte1]: 61
7867 06:02:55.715488
7868 06:02:55.718554 Set Vref, RX VrefLevel [Byte0]: 62
7869 06:02:55.721577 [Byte1]: 62
7870 06:02:55.721993
7871 06:02:55.724834 Set Vref, RX VrefLevel [Byte0]: 63
7872 06:02:55.728358 [Byte1]: 63
7873 06:02:55.728777
7874 06:02:55.731871 Set Vref, RX VrefLevel [Byte0]: 64
7875 06:02:55.734837 [Byte1]: 64
7876 06:02:55.738417
7877 06:02:55.739233 Set Vref, RX VrefLevel [Byte0]: 65
7878 06:02:55.741695 [Byte1]: 65
7879 06:02:55.745929
7880 06:02:55.746381 Set Vref, RX VrefLevel [Byte0]: 66
7881 06:02:55.749443 [Byte1]: 66
7882 06:02:55.754150
7883 06:02:55.754654 Set Vref, RX VrefLevel [Byte0]: 67
7884 06:02:55.756777 [Byte1]: 67
7885 06:02:55.760997
7886 06:02:55.761596 Set Vref, RX VrefLevel [Byte0]: 68
7887 06:02:55.764990 [Byte1]: 68
7888 06:02:55.768880
7889 06:02:55.769302 Set Vref, RX VrefLevel [Byte0]: 69
7890 06:02:55.772411 [Byte1]: 69
7891 06:02:55.776231
7892 06:02:55.776775 Set Vref, RX VrefLevel [Byte0]: 70
7893 06:02:55.779453 [Byte1]: 70
7894 06:02:55.784057
7895 06:02:55.784575 Set Vref, RX VrefLevel [Byte0]: 71
7896 06:02:55.787001 [Byte1]: 71
7897 06:02:55.791609
7898 06:02:55.792019 Set Vref, RX VrefLevel [Byte0]: 72
7899 06:02:55.794504 [Byte1]: 72
7900 06:02:55.798906
7901 06:02:55.799402 Set Vref, RX VrefLevel [Byte0]: 73
7902 06:02:55.802447 [Byte1]: 73
7903 06:02:55.806827
7904 06:02:55.807287 Final RX Vref Byte 0 = 61 to rank0
7905 06:02:55.809691 Final RX Vref Byte 1 = 62 to rank0
7906 06:02:55.813179 Final RX Vref Byte 0 = 61 to rank1
7907 06:02:55.816739 Final RX Vref Byte 1 = 62 to rank1==
7908 06:02:55.819362 Dram Type= 6, Freq= 0, CH_0, rank 0
7909 06:02:55.826414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7910 06:02:55.826830 ==
7911 06:02:55.827221 DQS Delay:
7912 06:02:55.827535 DQS0 = 0, DQS1 = 0
7913 06:02:55.829991 DQM Delay:
7914 06:02:55.830400 DQM0 = 134, DQM1 = 127
7915 06:02:55.833547 DQ Delay:
7916 06:02:55.836471 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7917 06:02:55.840045 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7918 06:02:55.842867 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7919 06:02:55.846374 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7920 06:02:55.846787
7921 06:02:55.847111
7922 06:02:55.847454
7923 06:02:55.849754 [DramC_TX_OE_Calibration] TA2
7924 06:02:55.853331 Original DQ_B0 (3 6) =30, OEN = 27
7925 06:02:55.855936 Original DQ_B1 (3 6) =30, OEN = 27
7926 06:02:55.859755 24, 0x0, End_B0=24 End_B1=24
7927 06:02:55.860174 25, 0x0, End_B0=25 End_B1=25
7928 06:02:55.863075 26, 0x0, End_B0=26 End_B1=26
7929 06:02:55.865947 27, 0x0, End_B0=27 End_B1=27
7930 06:02:55.869459 28, 0x0, End_B0=28 End_B1=28
7931 06:02:55.873098 29, 0x0, End_B0=29 End_B1=29
7932 06:02:55.873525 30, 0x0, End_B0=30 End_B1=30
7933 06:02:55.876242 31, 0x4141, End_B0=30 End_B1=30
7934 06:02:55.879918 Byte0 end_step=30 best_step=27
7935 06:02:55.882700 Byte1 end_step=30 best_step=27
7936 06:02:55.886276 Byte0 TX OE(2T, 0.5T) = (3, 3)
7937 06:02:55.889589 Byte1 TX OE(2T, 0.5T) = (3, 3)
7938 06:02:55.890008
7939 06:02:55.890335
7940 06:02:55.896212 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7941 06:02:55.899306 CH0 RK0: MR19=303, MR18=2622
7942 06:02:55.906233 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
7943 06:02:55.906648
7944 06:02:55.909113 ----->DramcWriteLeveling(PI) begin...
7945 06:02:55.909536 ==
7946 06:02:55.912550 Dram Type= 6, Freq= 0, CH_0, rank 1
7947 06:02:55.915884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7948 06:02:55.916338 ==
7949 06:02:55.918944 Write leveling (Byte 0): 34 => 34
7950 06:02:55.922668 Write leveling (Byte 1): 25 => 25
7951 06:02:55.926247 DramcWriteLeveling(PI) end<-----
7952 06:02:55.926659
7953 06:02:55.927027 ==
7954 06:02:55.929539 Dram Type= 6, Freq= 0, CH_0, rank 1
7955 06:02:55.932404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7956 06:02:55.932821 ==
7957 06:02:55.936201 [Gating] SW mode calibration
7958 06:02:55.942101 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7959 06:02:55.949311 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7960 06:02:55.952027 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7961 06:02:55.959088 1 4 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7962 06:02:55.961987 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7963 06:02:55.965595 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7964 06:02:55.969123 1 4 16 | B1->B0 | 2f2f 3635 | 0 1 | (0 0) (1 1)
7965 06:02:55.976071 1 4 20 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7966 06:02:55.978916 1 4 24 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7967 06:02:55.982156 1 4 28 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
7968 06:02:55.989262 1 5 0 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7969 06:02:55.992110 1 5 4 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7970 06:02:55.995836 1 5 8 | B1->B0 | 3434 3636 | 1 1 | (1 0) (1 0)
7971 06:02:56.002272 1 5 12 | B1->B0 | 3434 3636 | 1 0 | (1 0) (1 0)
7972 06:02:56.005746 1 5 16 | B1->B0 | 2f2f 2828 | 0 0 | (0 0) (0 0)
7973 06:02:56.009237 1 5 20 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 0)
7974 06:02:56.015858 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7975 06:02:56.019321 1 5 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7976 06:02:56.022830 1 6 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7977 06:02:56.029495 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7978 06:02:56.032487 1 6 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7979 06:02:56.035885 1 6 12 | B1->B0 | 2525 3636 | 0 0 | (0 0) (0 0)
7980 06:02:56.043032 1 6 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7981 06:02:56.046221 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7982 06:02:56.049519 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 06:02:56.052447 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (1 1)
7984 06:02:56.059029 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 06:02:56.062559 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 06:02:56.065964 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 06:02:56.072182 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7988 06:02:56.075737 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7989 06:02:56.079184 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 06:02:56.086071 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 06:02:56.089483 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 06:02:56.092349 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 06:02:56.099504 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 06:02:56.103022 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 06:02:56.105572 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 06:02:56.112332 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 06:02:56.115671 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 06:02:56.119188 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 06:02:56.125712 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 06:02:56.128792 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 06:02:56.132235 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 06:02:56.138508 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 06:02:56.142020 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8004 06:02:56.145596 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 06:02:56.148800 Total UI for P1: 0, mck2ui 16
8006 06:02:56.152169 best dqsien dly found for B0: ( 1, 9, 12)
8007 06:02:56.154928 Total UI for P1: 0, mck2ui 16
8008 06:02:56.158414 best dqsien dly found for B1: ( 1, 9, 12)
8009 06:02:56.162073 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8010 06:02:56.165514 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8011 06:02:56.165941
8012 06:02:56.171831 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8013 06:02:56.175039 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8014 06:02:56.175466 [Gating] SW calibration Done
8015 06:02:56.178850 ==
8016 06:02:56.181907 Dram Type= 6, Freq= 0, CH_0, rank 1
8017 06:02:56.184841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8018 06:02:56.185268 ==
8019 06:02:56.185602 RX Vref Scan: 0
8020 06:02:56.185913
8021 06:02:56.188752 RX Vref 0 -> 0, step: 1
8022 06:02:56.189175
8023 06:02:56.191607 RX Delay 0 -> 252, step: 8
8024 06:02:56.195214 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8025 06:02:56.198540 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8026 06:02:56.201767 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8027 06:02:56.208705 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8028 06:02:56.211800 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8029 06:02:56.215339 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8030 06:02:56.218731 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8031 06:02:56.221718 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8032 06:02:56.228476 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8033 06:02:56.231723 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8034 06:02:56.234966 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8035 06:02:56.238571 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8036 06:02:56.242074 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8037 06:02:56.248385 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8038 06:02:56.252057 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8039 06:02:56.254787 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8040 06:02:56.255245 ==
8041 06:02:56.258438 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 06:02:56.261557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 06:02:56.264793 ==
8044 06:02:56.265220 DQS Delay:
8045 06:02:56.265552 DQS0 = 0, DQS1 = 0
8046 06:02:56.268381 DQM Delay:
8047 06:02:56.268806 DQM0 = 137, DQM1 = 130
8048 06:02:56.271304 DQ Delay:
8049 06:02:56.274792 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8050 06:02:56.278342 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8051 06:02:56.281764 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8052 06:02:56.284520 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8053 06:02:56.285010
8054 06:02:56.285345
8055 06:02:56.285654 ==
8056 06:02:56.288033 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 06:02:56.291527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 06:02:56.291951 ==
8059 06:02:56.292314
8060 06:02:56.295102
8061 06:02:56.295525 TX Vref Scan disable
8062 06:02:56.298375 == TX Byte 0 ==
8063 06:02:56.301389 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8064 06:02:56.304778 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8065 06:02:56.308253 == TX Byte 1 ==
8066 06:02:56.311747 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8067 06:02:56.315004 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8068 06:02:56.315454 ==
8069 06:02:56.318271 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 06:02:56.324403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 06:02:56.324833 ==
8072 06:02:56.337510
8073 06:02:56.340744 TX Vref early break, caculate TX vref
8074 06:02:56.344071 TX Vref=16, minBit 0, minWin=23, winSum=386
8075 06:02:56.346914 TX Vref=18, minBit 1, minWin=23, winSum=396
8076 06:02:56.350419 TX Vref=20, minBit 1, minWin=23, winSum=409
8077 06:02:56.354132 TX Vref=22, minBit 1, minWin=24, winSum=411
8078 06:02:56.357039 TX Vref=24, minBit 1, minWin=25, winSum=418
8079 06:02:56.363953 TX Vref=26, minBit 1, minWin=26, winSum=429
8080 06:02:56.367295 TX Vref=28, minBit 3, minWin=25, winSum=426
8081 06:02:56.370515 TX Vref=30, minBit 0, minWin=25, winSum=418
8082 06:02:56.373885 TX Vref=32, minBit 1, minWin=24, winSum=408
8083 06:02:56.377246 TX Vref=34, minBit 0, minWin=24, winSum=404
8084 06:02:56.383921 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 26
8085 06:02:56.384390
8086 06:02:56.387253 Final TX Range 0 Vref 26
8087 06:02:56.387690
8088 06:02:56.388020 ==
8089 06:02:56.390692 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 06:02:56.394307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 06:02:56.394733 ==
8092 06:02:56.395065
8093 06:02:56.395545
8094 06:02:56.397045 TX Vref Scan disable
8095 06:02:56.403794 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8096 06:02:56.404209 == TX Byte 0 ==
8097 06:02:56.407106 u2DelayCellOfst[0]=13 cells (4 PI)
8098 06:02:56.410138 u2DelayCellOfst[1]=16 cells (5 PI)
8099 06:02:56.413666 u2DelayCellOfst[2]=10 cells (3 PI)
8100 06:02:56.417283 u2DelayCellOfst[3]=10 cells (3 PI)
8101 06:02:56.420620 u2DelayCellOfst[4]=6 cells (2 PI)
8102 06:02:56.423985 u2DelayCellOfst[5]=0 cells (0 PI)
8103 06:02:56.427012 u2DelayCellOfst[6]=13 cells (4 PI)
8104 06:02:56.427425 u2DelayCellOfst[7]=13 cells (4 PI)
8105 06:02:56.433918 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8106 06:02:56.437357 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8107 06:02:56.437794 == TX Byte 1 ==
8108 06:02:56.440646 u2DelayCellOfst[8]=3 cells (1 PI)
8109 06:02:56.444004 u2DelayCellOfst[9]=0 cells (0 PI)
8110 06:02:56.447164 u2DelayCellOfst[10]=6 cells (2 PI)
8111 06:02:56.450036 u2DelayCellOfst[11]=3 cells (1 PI)
8112 06:02:56.453615 u2DelayCellOfst[12]=13 cells (4 PI)
8113 06:02:56.456806 u2DelayCellOfst[13]=10 cells (3 PI)
8114 06:02:56.460036 u2DelayCellOfst[14]=13 cells (4 PI)
8115 06:02:56.463480 u2DelayCellOfst[15]=10 cells (3 PI)
8116 06:02:56.467245 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8117 06:02:56.473551 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8118 06:02:56.474132 DramC Write-DBI on
8119 06:02:56.474640 ==
8120 06:02:56.476762 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 06:02:56.480245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 06:02:56.480715 ==
8123 06:02:56.483738
8124 06:02:56.484235
8125 06:02:56.484635 TX Vref Scan disable
8126 06:02:56.487231 == TX Byte 0 ==
8127 06:02:56.490609 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8128 06:02:56.493921 == TX Byte 1 ==
8129 06:02:56.496701 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8130 06:02:56.500362 DramC Write-DBI off
8131 06:02:56.500892
8132 06:02:56.501227 [DATLAT]
8133 06:02:56.501533 Freq=1600, CH0 RK1
8134 06:02:56.501829
8135 06:02:56.503192 DATLAT Default: 0xf
8136 06:02:56.503606 0, 0xFFFF, sum = 0
8137 06:02:56.506743 1, 0xFFFF, sum = 0
8138 06:02:56.510133 2, 0xFFFF, sum = 0
8139 06:02:56.510648 3, 0xFFFF, sum = 0
8140 06:02:56.513944 4, 0xFFFF, sum = 0
8141 06:02:56.514622 5, 0xFFFF, sum = 0
8142 06:02:56.517225 6, 0xFFFF, sum = 0
8143 06:02:56.517760 7, 0xFFFF, sum = 0
8144 06:02:56.519919 8, 0xFFFF, sum = 0
8145 06:02:56.520541 9, 0xFFFF, sum = 0
8146 06:02:56.523590 10, 0xFFFF, sum = 0
8147 06:02:56.524198 11, 0xFFFF, sum = 0
8148 06:02:56.526950 12, 0xFFFF, sum = 0
8149 06:02:56.527371 13, 0xFFFF, sum = 0
8150 06:02:56.529899 14, 0x0, sum = 1
8151 06:02:56.530338 15, 0x0, sum = 2
8152 06:02:56.533406 16, 0x0, sum = 3
8153 06:02:56.533946 17, 0x0, sum = 4
8154 06:02:56.536734 best_step = 15
8155 06:02:56.537145
8156 06:02:56.537469 ==
8157 06:02:56.540382 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 06:02:56.543488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 06:02:56.544153 ==
8160 06:02:56.546693 RX Vref Scan: 0
8161 06:02:56.547256
8162 06:02:56.547772 RX Vref 0 -> 0, step: 1
8163 06:02:56.548254
8164 06:02:56.550181 RX Delay 19 -> 252, step: 4
8165 06:02:56.553093 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8166 06:02:56.560215 iDelay=191, Bit 1, Center 136 (91 ~ 182) 92
8167 06:02:56.562960 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8168 06:02:56.566296 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8169 06:02:56.569532 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8170 06:02:56.573356 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8171 06:02:56.579984 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8172 06:02:56.582861 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8173 06:02:56.586172 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8174 06:02:56.589594 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8175 06:02:56.592910 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8176 06:02:56.599916 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8177 06:02:56.603490 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8178 06:02:56.606221 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8179 06:02:56.609486 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8180 06:02:56.613398 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8181 06:02:56.616178 ==
8182 06:02:56.616685 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 06:02:56.623638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 06:02:56.624148 ==
8185 06:02:56.624529 DQS Delay:
8186 06:02:56.626369 DQS0 = 0, DQS1 = 0
8187 06:02:56.626805 DQM Delay:
8188 06:02:56.629247 DQM0 = 134, DQM1 = 127
8189 06:02:56.629779 DQ Delay:
8190 06:02:56.633197 DQ0 =134, DQ1 =136, DQ2 =132, DQ3 =134
8191 06:02:56.636569 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8192 06:02:56.639352 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8193 06:02:56.642792 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =136
8194 06:02:56.643209
8195 06:02:56.643532
8196 06:02:56.643831
8197 06:02:56.646258 [DramC_TX_OE_Calibration] TA2
8198 06:02:56.649767 Original DQ_B0 (3 6) =30, OEN = 27
8199 06:02:56.652718 Original DQ_B1 (3 6) =30, OEN = 27
8200 06:02:56.656274 24, 0x0, End_B0=24 End_B1=24
8201 06:02:56.659862 25, 0x0, End_B0=25 End_B1=25
8202 06:02:56.660314 26, 0x0, End_B0=26 End_B1=26
8203 06:02:56.662573 27, 0x0, End_B0=27 End_B1=27
8204 06:02:56.665984 28, 0x0, End_B0=28 End_B1=28
8205 06:02:56.669422 29, 0x0, End_B0=29 End_B1=29
8206 06:02:56.669842 30, 0x0, End_B0=30 End_B1=30
8207 06:02:56.672889 31, 0x4141, End_B0=30 End_B1=30
8208 06:02:56.676348 Byte0 end_step=30 best_step=27
8209 06:02:56.679832 Byte1 end_step=30 best_step=27
8210 06:02:56.683268 Byte0 TX OE(2T, 0.5T) = (3, 3)
8211 06:02:56.686633 Byte1 TX OE(2T, 0.5T) = (3, 3)
8212 06:02:56.687062
8213 06:02:56.687386
8214 06:02:56.692959 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
8215 06:02:56.696271 CH0 RK1: MR19=303, MR18=1D06
8216 06:02:56.702866 CH0_RK1: MR19=0x303, MR18=0x1D06, DQSOSC=395, MR23=63, INC=23, DEC=15
8217 06:02:56.706367 [RxdqsGatingPostProcess] freq 1600
8218 06:02:56.709750 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8219 06:02:56.713366 best DQS0 dly(2T, 0.5T) = (1, 1)
8220 06:02:56.716216 best DQS1 dly(2T, 0.5T) = (1, 1)
8221 06:02:56.719868 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8222 06:02:56.723087 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8223 06:02:56.726634 best DQS0 dly(2T, 0.5T) = (1, 1)
8224 06:02:56.729870 best DQS1 dly(2T, 0.5T) = (1, 1)
8225 06:02:56.733157 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8226 06:02:56.736571 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8227 06:02:56.739805 Pre-setting of DQS Precalculation
8228 06:02:56.743003 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8229 06:02:56.743525 ==
8230 06:02:56.746724 Dram Type= 6, Freq= 0, CH_1, rank 0
8231 06:02:56.749933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8232 06:02:56.750436 ==
8233 06:02:56.756824 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8234 06:02:56.759528 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8235 06:02:56.766532 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8236 06:02:56.769342 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8237 06:02:56.780094 [CA 0] Center 41 (12~71) winsize 60
8238 06:02:56.783007 [CA 1] Center 41 (12~71) winsize 60
8239 06:02:56.786617 [CA 2] Center 38 (9~68) winsize 60
8240 06:02:56.790138 [CA 3] Center 37 (8~66) winsize 59
8241 06:02:56.793704 [CA 4] Center 37 (8~67) winsize 60
8242 06:02:56.796200 [CA 5] Center 36 (7~66) winsize 60
8243 06:02:56.796668
8244 06:02:56.799803 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8245 06:02:56.800455
8246 06:02:56.806005 [CATrainingPosCal] consider 1 rank data
8247 06:02:56.806421 u2DelayCellTimex100 = 290/100 ps
8248 06:02:56.812869 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8249 06:02:56.816057 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8250 06:02:56.819794 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8251 06:02:56.823050 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8252 06:02:56.825828 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8253 06:02:56.829314 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8254 06:02:56.829745
8255 06:02:56.832754 CA PerBit enable=1, Macro0, CA PI delay=36
8256 06:02:56.833167
8257 06:02:56.836233 [CBTSetCACLKResult] CA Dly = 36
8258 06:02:56.839805 CS Dly: 10 (0~41)
8259 06:02:56.842397 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8260 06:02:56.845938 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8261 06:02:56.846352 ==
8262 06:02:56.849467 Dram Type= 6, Freq= 0, CH_1, rank 1
8263 06:02:56.855825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 06:02:56.856241 ==
8265 06:02:56.859276 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 06:02:56.865859 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 06:02:56.869043 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 06:02:56.875633 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 06:02:56.882863 [CA 0] Center 42 (12~72) winsize 61
8270 06:02:56.886612 [CA 1] Center 41 (12~71) winsize 60
8271 06:02:56.890270 [CA 2] Center 38 (9~68) winsize 60
8272 06:02:56.892767 [CA 3] Center 38 (8~68) winsize 61
8273 06:02:56.896147 [CA 4] Center 38 (8~69) winsize 62
8274 06:02:56.899956 [CA 5] Center 37 (7~67) winsize 61
8275 06:02:56.900716
8276 06:02:56.903205 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8277 06:02:56.903768
8278 06:02:56.906141 [CATrainingPosCal] consider 2 rank data
8279 06:02:56.909699 u2DelayCellTimex100 = 290/100 ps
8280 06:02:56.913306 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8281 06:02:56.919534 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8282 06:02:56.922872 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8283 06:02:56.926559 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8284 06:02:56.930084 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8285 06:02:56.932747 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8286 06:02:56.933183
8287 06:02:56.936076 CA PerBit enable=1, Macro0, CA PI delay=36
8288 06:02:56.936539
8289 06:02:56.939507 [CBTSetCACLKResult] CA Dly = 36
8290 06:02:56.943137 CS Dly: 12 (0~45)
8291 06:02:56.946168 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 06:02:56.949650 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 06:02:56.950088
8294 06:02:56.952957 ----->DramcWriteLeveling(PI) begin...
8295 06:02:56.953376 ==
8296 06:02:56.956208 Dram Type= 6, Freq= 0, CH_1, rank 0
8297 06:02:56.959707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 06:02:56.963314 ==
8299 06:02:56.963789 Write leveling (Byte 0): 26 => 26
8300 06:02:56.966092 Write leveling (Byte 1): 28 => 28
8301 06:02:56.969738 DramcWriteLeveling(PI) end<-----
8302 06:02:56.970158
8303 06:02:56.970484 ==
8304 06:02:56.973274 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 06:02:56.979548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 06:02:56.979966 ==
8307 06:02:56.980328 [Gating] SW mode calibration
8308 06:02:56.989722 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8309 06:02:56.993109 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8310 06:02:56.996148 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8311 06:02:57.002698 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8312 06:02:57.006215 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
8313 06:02:57.009059 1 4 12 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
8314 06:02:57.016111 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 06:02:57.019422 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 06:02:57.023028 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 06:02:57.030041 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 06:02:57.032831 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 06:02:57.036436 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 06:02:57.042543 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
8321 06:02:57.046004 1 5 12 | B1->B0 | 2a2a 2424 | 0 0 | (0 1) (1 0)
8322 06:02:57.049575 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 06:02:57.055889 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 06:02:57.059375 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 06:02:57.062507 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 06:02:57.069268 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 06:02:57.072814 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 06:02:57.076130 1 6 8 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
8329 06:02:57.082587 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 06:02:57.085772 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 06:02:57.089178 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 06:02:57.095580 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 06:02:57.098990 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 06:02:57.102662 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 06:02:57.108853 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 06:02:57.112120 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8337 06:02:57.115576 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8338 06:02:57.122392 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 06:02:57.125448 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 06:02:57.129166 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 06:02:57.135228 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 06:02:57.138891 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 06:02:57.142380 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 06:02:57.148562 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 06:02:57.152115 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 06:02:57.155767 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 06:02:57.158710 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 06:02:57.165240 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 06:02:57.168771 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 06:02:57.172333 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 06:02:57.178513 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 06:02:57.181836 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8353 06:02:57.185153 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8354 06:02:57.192625 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 06:02:57.195436 Total UI for P1: 0, mck2ui 16
8356 06:02:57.199030 best dqsien dly found for B0: ( 1, 9, 10)
8357 06:02:57.199603 Total UI for P1: 0, mck2ui 16
8358 06:02:57.205273 best dqsien dly found for B1: ( 1, 9, 10)
8359 06:02:57.208602 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8360 06:02:57.212348 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8361 06:02:57.212772
8362 06:02:57.215562 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8363 06:02:57.218729 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8364 06:02:57.222117 [Gating] SW calibration Done
8365 06:02:57.222541 ==
8366 06:02:57.225598 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 06:02:57.228532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 06:02:57.228959 ==
8369 06:02:57.231870 RX Vref Scan: 0
8370 06:02:57.232318
8371 06:02:57.232671 RX Vref 0 -> 0, step: 1
8372 06:02:57.235477
8373 06:02:57.236183 RX Delay 0 -> 252, step: 8
8374 06:02:57.238647 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8375 06:02:57.245192 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8376 06:02:57.248280 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8377 06:02:57.251893 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8378 06:02:57.255078 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8379 06:02:57.258643 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8380 06:02:57.265395 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8381 06:02:57.268215 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8382 06:02:57.271628 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8383 06:02:57.275183 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8384 06:02:57.278652 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8385 06:02:57.285055 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8386 06:02:57.288614 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8387 06:02:57.291536 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8388 06:02:57.295167 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8389 06:02:57.298588 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8390 06:02:57.299160 ==
8391 06:02:57.301357 Dram Type= 6, Freq= 0, CH_1, rank 0
8392 06:02:57.308084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 06:02:57.308675 ==
8394 06:02:57.309148 DQS Delay:
8395 06:02:57.311821 DQS0 = 0, DQS1 = 0
8396 06:02:57.312351 DQM Delay:
8397 06:02:57.315252 DQM0 = 136, DQM1 = 133
8398 06:02:57.315777 DQ Delay:
8399 06:02:57.318356 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8400 06:02:57.321415 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8401 06:02:57.324982 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8402 06:02:57.327914 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8403 06:02:57.328137
8404 06:02:57.328331
8405 06:02:57.328497 ==
8406 06:02:57.331488 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 06:02:57.337823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 06:02:57.338110 ==
8409 06:02:57.338277
8410 06:02:57.338428
8411 06:02:57.338570 TX Vref Scan disable
8412 06:02:57.341298 == TX Byte 0 ==
8413 06:02:57.344550 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8414 06:02:57.347929 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8415 06:02:57.351574 == TX Byte 1 ==
8416 06:02:57.354923 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8417 06:02:57.358292 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8418 06:02:57.361293 ==
8419 06:02:57.365156 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 06:02:57.368389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 06:02:57.368604 ==
8422 06:02:57.381482
8423 06:02:57.384183 TX Vref early break, caculate TX vref
8424 06:02:57.387972 TX Vref=16, minBit 1, minWin=22, winSum=377
8425 06:02:57.391441 TX Vref=18, minBit 0, minWin=23, winSum=384
8426 06:02:57.394307 TX Vref=20, minBit 0, minWin=24, winSum=391
8427 06:02:57.397686 TX Vref=22, minBit 0, minWin=24, winSum=407
8428 06:02:57.401335 TX Vref=24, minBit 6, minWin=24, winSum=410
8429 06:02:57.407493 TX Vref=26, minBit 0, minWin=25, winSum=424
8430 06:02:57.411172 TX Vref=28, minBit 0, minWin=25, winSum=424
8431 06:02:57.414480 TX Vref=30, minBit 0, minWin=25, winSum=419
8432 06:02:57.418023 TX Vref=32, minBit 0, minWin=24, winSum=412
8433 06:02:57.421101 TX Vref=34, minBit 0, minWin=24, winSum=406
8434 06:02:57.424633 TX Vref=36, minBit 0, minWin=23, winSum=389
8435 06:02:57.431607 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
8436 06:02:57.432029
8437 06:02:57.434391 Final TX Range 0 Vref 26
8438 06:02:57.434810
8439 06:02:57.435137 ==
8440 06:02:57.437679 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 06:02:57.440819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 06:02:57.441267 ==
8443 06:02:57.441628
8444 06:02:57.441937
8445 06:02:57.444151 TX Vref Scan disable
8446 06:02:57.451329 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8447 06:02:57.451747 == TX Byte 0 ==
8448 06:02:57.454653 u2DelayCellOfst[0]=16 cells (5 PI)
8449 06:02:57.457607 u2DelayCellOfst[1]=10 cells (3 PI)
8450 06:02:57.460819 u2DelayCellOfst[2]=0 cells (0 PI)
8451 06:02:57.464409 u2DelayCellOfst[3]=6 cells (2 PI)
8452 06:02:57.467911 u2DelayCellOfst[4]=6 cells (2 PI)
8453 06:02:57.471371 u2DelayCellOfst[5]=16 cells (5 PI)
8454 06:02:57.474151 u2DelayCellOfst[6]=13 cells (4 PI)
8455 06:02:57.477436 u2DelayCellOfst[7]=6 cells (2 PI)
8456 06:02:57.480806 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8457 06:02:57.484133 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8458 06:02:57.487873 == TX Byte 1 ==
8459 06:02:57.488322 u2DelayCellOfst[8]=0 cells (0 PI)
8460 06:02:57.491106 u2DelayCellOfst[9]=3 cells (1 PI)
8461 06:02:57.494526 u2DelayCellOfst[10]=13 cells (4 PI)
8462 06:02:57.497999 u2DelayCellOfst[11]=6 cells (2 PI)
8463 06:02:57.500959 u2DelayCellOfst[12]=16 cells (5 PI)
8464 06:02:57.504644 u2DelayCellOfst[13]=16 cells (5 PI)
8465 06:02:57.508172 u2DelayCellOfst[14]=16 cells (5 PI)
8466 06:02:57.511553 u2DelayCellOfst[15]=16 cells (5 PI)
8467 06:02:57.514351 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8468 06:02:57.521246 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8469 06:02:57.521794 DramC Write-DBI on
8470 06:02:57.522141 ==
8471 06:02:57.524530 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 06:02:57.527973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 06:02:57.531404 ==
8474 06:02:57.531817
8475 06:02:57.532142
8476 06:02:57.532486 TX Vref Scan disable
8477 06:02:57.534299 == TX Byte 0 ==
8478 06:02:57.537598 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8479 06:02:57.541058 == TX Byte 1 ==
8480 06:02:57.544674 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8481 06:02:57.547395 DramC Write-DBI off
8482 06:02:57.547806
8483 06:02:57.548132 [DATLAT]
8484 06:02:57.548518 Freq=1600, CH1 RK0
8485 06:02:57.548827
8486 06:02:57.551040 DATLAT Default: 0xf
8487 06:02:57.551454 0, 0xFFFF, sum = 0
8488 06:02:57.554664 1, 0xFFFF, sum = 0
8489 06:02:57.555087 2, 0xFFFF, sum = 0
8490 06:02:57.558110 3, 0xFFFF, sum = 0
8491 06:02:57.561295 4, 0xFFFF, sum = 0
8492 06:02:57.561728 5, 0xFFFF, sum = 0
8493 06:02:57.564414 6, 0xFFFF, sum = 0
8494 06:02:57.564866 7, 0xFFFF, sum = 0
8495 06:02:57.567415 8, 0xFFFF, sum = 0
8496 06:02:57.567835 9, 0xFFFF, sum = 0
8497 06:02:57.571193 10, 0xFFFF, sum = 0
8498 06:02:57.571636 11, 0xFFFF, sum = 0
8499 06:02:57.574155 12, 0xFFFF, sum = 0
8500 06:02:57.574588 13, 0xFFFF, sum = 0
8501 06:02:57.577299 14, 0x0, sum = 1
8502 06:02:57.577721 15, 0x0, sum = 2
8503 06:02:57.580895 16, 0x0, sum = 3
8504 06:02:57.581316 17, 0x0, sum = 4
8505 06:02:57.584377 best_step = 15
8506 06:02:57.584770
8507 06:02:57.585167 ==
8508 06:02:57.587360 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 06:02:57.590761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 06:02:57.591307 ==
8511 06:02:57.593767 RX Vref Scan: 1
8512 06:02:57.594185
8513 06:02:57.594516 Set Vref Range= 24 -> 127
8514 06:02:57.594826
8515 06:02:57.597144 RX Vref 24 -> 127, step: 1
8516 06:02:57.597596
8517 06:02:57.601005 RX Delay 27 -> 252, step: 4
8518 06:02:57.601415
8519 06:02:57.604066 Set Vref, RX VrefLevel [Byte0]: 24
8520 06:02:57.607647 [Byte1]: 24
8521 06:02:57.608059
8522 06:02:57.610959 Set Vref, RX VrefLevel [Byte0]: 25
8523 06:02:57.614485 [Byte1]: 25
8524 06:02:57.614898
8525 06:02:57.617040 Set Vref, RX VrefLevel [Byte0]: 26
8526 06:02:57.620601 [Byte1]: 26
8527 06:02:57.624852
8528 06:02:57.625264 Set Vref, RX VrefLevel [Byte0]: 27
8529 06:02:57.627588 [Byte1]: 27
8530 06:02:57.632101
8531 06:02:57.632564 Set Vref, RX VrefLevel [Byte0]: 28
8532 06:02:57.635514 [Byte1]: 28
8533 06:02:57.644372
8534 06:02:57.644895 Set Vref, RX VrefLevel [Byte0]: 29
8535 06:02:57.645237 [Byte1]: 29
8536 06:02:57.647455
8537 06:02:57.647863 Set Vref, RX VrefLevel [Byte0]: 30
8538 06:02:57.650348 [Byte1]: 30
8539 06:02:57.654551
8540 06:02:57.654961 Set Vref, RX VrefLevel [Byte0]: 31
8541 06:02:57.658103 [Byte1]: 31
8542 06:02:57.662404
8543 06:02:57.662817 Set Vref, RX VrefLevel [Byte0]: 32
8544 06:02:57.665843 [Byte1]: 32
8545 06:02:57.669889
8546 06:02:57.670461 Set Vref, RX VrefLevel [Byte0]: 33
8547 06:02:57.673008 [Byte1]: 33
8548 06:02:57.677092
8549 06:02:57.677508 Set Vref, RX VrefLevel [Byte0]: 34
8550 06:02:57.680487 [Byte1]: 34
8551 06:02:57.685262
8552 06:02:57.685674 Set Vref, RX VrefLevel [Byte0]: 35
8553 06:02:57.687986 [Byte1]: 35
8554 06:02:57.691995
8555 06:02:57.692455 Set Vref, RX VrefLevel [Byte0]: 36
8556 06:02:57.695515 [Byte1]: 36
8557 06:02:57.700115
8558 06:02:57.700623 Set Vref, RX VrefLevel [Byte0]: 37
8559 06:02:57.703209 [Byte1]: 37
8560 06:02:57.707497
8561 06:02:57.707946 Set Vref, RX VrefLevel [Byte0]: 38
8562 06:02:57.711058 [Byte1]: 38
8563 06:02:57.714819
8564 06:02:57.715234 Set Vref, RX VrefLevel [Byte0]: 39
8565 06:02:57.718425 [Byte1]: 39
8566 06:02:57.722598
8567 06:02:57.723078 Set Vref, RX VrefLevel [Byte0]: 40
8568 06:02:57.725826 [Byte1]: 40
8569 06:02:57.730076
8570 06:02:57.730485 Set Vref, RX VrefLevel [Byte0]: 41
8571 06:02:57.732925 [Byte1]: 41
8572 06:02:57.737785
8573 06:02:57.738194 Set Vref, RX VrefLevel [Byte0]: 42
8574 06:02:57.740944 [Byte1]: 42
8575 06:02:57.745214
8576 06:02:57.745628 Set Vref, RX VrefLevel [Byte0]: 43
8577 06:02:57.748564 [Byte1]: 43
8578 06:02:57.752922
8579 06:02:57.753331 Set Vref, RX VrefLevel [Byte0]: 44
8580 06:02:57.755666 [Byte1]: 44
8581 06:02:57.759966
8582 06:02:57.760453 Set Vref, RX VrefLevel [Byte0]: 45
8583 06:02:57.763410 [Byte1]: 45
8584 06:02:57.767646
8585 06:02:57.768176 Set Vref, RX VrefLevel [Byte0]: 46
8586 06:02:57.771095 [Byte1]: 46
8587 06:02:57.775338
8588 06:02:57.775771 Set Vref, RX VrefLevel [Byte0]: 47
8589 06:02:57.778376 [Byte1]: 47
8590 06:02:57.782247
8591 06:02:57.782553 Set Vref, RX VrefLevel [Byte0]: 48
8592 06:02:57.785574 [Byte1]: 48
8593 06:02:57.790189
8594 06:02:57.790487 Set Vref, RX VrefLevel [Byte0]: 49
8595 06:02:57.793588 [Byte1]: 49
8596 06:02:57.797714
8597 06:02:57.798133 Set Vref, RX VrefLevel [Byte0]: 50
8598 06:02:57.801276 [Byte1]: 50
8599 06:02:57.804791
8600 06:02:57.805090 Set Vref, RX VrefLevel [Byte0]: 51
8601 06:02:57.808498 [Byte1]: 51
8602 06:02:57.812506
8603 06:02:57.812949 Set Vref, RX VrefLevel [Byte0]: 52
8604 06:02:57.816027 [Byte1]: 52
8605 06:02:57.820161
8606 06:02:57.820684 Set Vref, RX VrefLevel [Byte0]: 53
8607 06:02:57.823391 [Byte1]: 53
8608 06:02:57.828087
8609 06:02:57.828419 Set Vref, RX VrefLevel [Byte0]: 54
8610 06:02:57.830752 [Byte1]: 54
8611 06:02:57.835616
8612 06:02:57.836009 Set Vref, RX VrefLevel [Byte0]: 55
8613 06:02:57.838973 [Byte1]: 55
8614 06:02:57.842903
8615 06:02:57.843220 Set Vref, RX VrefLevel [Byte0]: 56
8616 06:02:57.846414 [Byte1]: 56
8617 06:02:57.850560
8618 06:02:57.850959 Set Vref, RX VrefLevel [Byte0]: 57
8619 06:02:57.853870 [Byte1]: 57
8620 06:02:57.858070
8621 06:02:57.858569 Set Vref, RX VrefLevel [Byte0]: 58
8622 06:02:57.861293 [Byte1]: 58
8623 06:02:57.865723
8624 06:02:57.866142 Set Vref, RX VrefLevel [Byte0]: 59
8625 06:02:57.869274 [Byte1]: 59
8626 06:02:57.873424
8627 06:02:57.873893 Set Vref, RX VrefLevel [Byte0]: 60
8628 06:02:57.876384 [Byte1]: 60
8629 06:02:57.880452
8630 06:02:57.880874 Set Vref, RX VrefLevel [Byte0]: 61
8631 06:02:57.883844 [Byte1]: 61
8632 06:02:57.888354
8633 06:02:57.888776 Set Vref, RX VrefLevel [Byte0]: 62
8634 06:02:57.891494 [Byte1]: 62
8635 06:02:57.895787
8636 06:02:57.896203 Set Vref, RX VrefLevel [Byte0]: 63
8637 06:02:57.898935 [Byte1]: 63
8638 06:02:57.903301
8639 06:02:57.903861 Set Vref, RX VrefLevel [Byte0]: 64
8640 06:02:57.906643 [Byte1]: 64
8641 06:02:57.910714
8642 06:02:57.911288 Set Vref, RX VrefLevel [Byte0]: 65
8643 06:02:57.914286 [Byte1]: 65
8644 06:02:57.918492
8645 06:02:57.918910 Set Vref, RX VrefLevel [Byte0]: 66
8646 06:02:57.921980 [Byte1]: 66
8647 06:02:57.925791
8648 06:02:57.926281 Set Vref, RX VrefLevel [Byte0]: 67
8649 06:02:57.929091 [Byte1]: 67
8650 06:02:57.933547
8651 06:02:57.934029 Set Vref, RX VrefLevel [Byte0]: 68
8652 06:02:57.936233 [Byte1]: 68
8653 06:02:57.940867
8654 06:02:57.941098 Set Vref, RX VrefLevel [Byte0]: 69
8655 06:02:57.944240 [Byte1]: 69
8656 06:02:57.948277
8657 06:02:57.948528 Set Vref, RX VrefLevel [Byte0]: 70
8658 06:02:57.951194 [Byte1]: 70
8659 06:02:57.955476
8660 06:02:57.955701 Set Vref, RX VrefLevel [Byte0]: 71
8661 06:02:57.958787 [Byte1]: 71
8662 06:02:57.962966
8663 06:02:57.963083 Set Vref, RX VrefLevel [Byte0]: 72
8664 06:02:57.966318 [Byte1]: 72
8665 06:02:57.970963
8666 06:02:57.971057 Set Vref, RX VrefLevel [Byte0]: 73
8667 06:02:57.973529 [Byte1]: 73
8668 06:02:57.978364
8669 06:02:57.978497 Set Vref, RX VrefLevel [Byte0]: 74
8670 06:02:57.981266 [Byte1]: 74
8671 06:02:57.985657
8672 06:02:57.985800 Set Vref, RX VrefLevel [Byte0]: 75
8673 06:02:57.988765 [Byte1]: 75
8674 06:02:57.993186
8675 06:02:57.993309 Set Vref, RX VrefLevel [Byte0]: 76
8676 06:02:57.996658 [Byte1]: 76
8677 06:02:58.000737
8678 06:02:58.000867 Final RX Vref Byte 0 = 57 to rank0
8679 06:02:58.004001 Final RX Vref Byte 1 = 58 to rank0
8680 06:02:58.007050 Final RX Vref Byte 0 = 57 to rank1
8681 06:02:58.010845 Final RX Vref Byte 1 = 58 to rank1==
8682 06:02:58.014330 Dram Type= 6, Freq= 0, CH_1, rank 0
8683 06:02:58.020761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8684 06:02:58.020847 ==
8685 06:02:58.020934 DQS Delay:
8686 06:02:58.021015 DQS0 = 0, DQS1 = 0
8687 06:02:58.024235 DQM Delay:
8688 06:02:58.024361 DQM0 = 133, DQM1 = 131
8689 06:02:58.027744 DQ Delay:
8690 06:02:58.030437 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8691 06:02:58.034001 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8692 06:02:58.037576 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8693 06:02:58.040981 DQ12 =140, DQ13 =138, DQ14 =140, DQ15 =140
8694 06:02:58.041065
8695 06:02:58.041151
8696 06:02:58.041232
8697 06:02:58.043887 [DramC_TX_OE_Calibration] TA2
8698 06:02:58.047019 Original DQ_B0 (3 6) =30, OEN = 27
8699 06:02:58.050809 Original DQ_B1 (3 6) =30, OEN = 27
8700 06:02:58.054030 24, 0x0, End_B0=24 End_B1=24
8701 06:02:58.054134 25, 0x0, End_B0=25 End_B1=25
8702 06:02:58.057244 26, 0x0, End_B0=26 End_B1=26
8703 06:02:58.060882 27, 0x0, End_B0=27 End_B1=27
8704 06:02:58.064124 28, 0x0, End_B0=28 End_B1=28
8705 06:02:58.064223 29, 0x0, End_B0=29 End_B1=29
8706 06:02:58.067122 30, 0x0, End_B0=30 End_B1=30
8707 06:02:58.070651 31, 0x5151, End_B0=30 End_B1=30
8708 06:02:58.074210 Byte0 end_step=30 best_step=27
8709 06:02:58.077222 Byte1 end_step=30 best_step=27
8710 06:02:58.080705 Byte0 TX OE(2T, 0.5T) = (3, 3)
8711 06:02:58.080839 Byte1 TX OE(2T, 0.5T) = (3, 3)
8712 06:02:58.084198
8713 06:02:58.084373
8714 06:02:58.091144 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8715 06:02:58.094198 CH1 RK0: MR19=303, MR18=1725
8716 06:02:58.100519 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8717 06:02:58.100673
8718 06:02:58.103787 ----->DramcWriteLeveling(PI) begin...
8719 06:02:58.103896 ==
8720 06:02:58.107678 Dram Type= 6, Freq= 0, CH_1, rank 1
8721 06:02:58.110634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8722 06:02:58.110810 ==
8723 06:02:58.114148 Write leveling (Byte 0): 27 => 27
8724 06:02:58.117427 Write leveling (Byte 1): 29 => 29
8725 06:02:58.120920 DramcWriteLeveling(PI) end<-----
8726 06:02:58.121106
8727 06:02:58.121230 ==
8728 06:02:58.123955 Dram Type= 6, Freq= 0, CH_1, rank 1
8729 06:02:58.127325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8730 06:02:58.127504 ==
8731 06:02:58.131002 [Gating] SW mode calibration
8732 06:02:58.137546 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8733 06:02:58.143946 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8734 06:02:58.147502 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8735 06:02:58.151216 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8736 06:02:58.157344 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8737 06:02:58.160822 1 4 12 | B1->B0 | 3434 2b2b | 0 1 | (0 0) (0 0)
8738 06:02:58.163963 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 06:02:58.170953 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 06:02:58.174086 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8741 06:02:58.178060 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8742 06:02:58.184394 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8743 06:02:58.187532 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8744 06:02:58.190657 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8745 06:02:58.197722 1 5 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8746 06:02:58.200483 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8747 06:02:58.204158 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 06:02:58.210812 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 06:02:58.213975 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 06:02:58.218067 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 06:02:58.220570 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 06:02:58.227488 1 6 8 | B1->B0 | 302f 2323 | 1 0 | (0 0) (0 0)
8753 06:02:58.230708 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8754 06:02:58.234151 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 06:02:58.240853 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 06:02:58.244155 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8757 06:02:58.247423 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 06:02:58.253912 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8759 06:02:58.257691 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8760 06:02:58.261043 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8761 06:02:58.267378 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8762 06:02:58.270475 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8763 06:02:58.274174 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 06:02:58.280446 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 06:02:58.283769 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 06:02:58.287196 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 06:02:58.293731 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 06:02:58.296836 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 06:02:58.300519 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 06:02:58.307369 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 06:02:58.310287 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 06:02:58.313751 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 06:02:58.320277 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 06:02:58.323325 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 06:02:58.326597 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8776 06:02:58.333414 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8777 06:02:58.336932 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8778 06:02:58.340379 Total UI for P1: 0, mck2ui 16
8779 06:02:58.343575 best dqsien dly found for B1: ( 1, 9, 6)
8780 06:02:58.346841 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8781 06:02:58.353603 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 06:02:58.354020 Total UI for P1: 0, mck2ui 16
8783 06:02:58.356519 best dqsien dly found for B0: ( 1, 9, 12)
8784 06:02:58.363465 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8785 06:02:58.366477 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8786 06:02:58.367060
8787 06:02:58.370137 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8788 06:02:58.373113 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8789 06:02:58.376365 [Gating] SW calibration Done
8790 06:02:58.377127 ==
8791 06:02:58.379765 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 06:02:58.383297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 06:02:58.384048 ==
8794 06:02:58.386683 RX Vref Scan: 0
8795 06:02:58.387427
8796 06:02:58.388105 RX Vref 0 -> 0, step: 1
8797 06:02:58.388821
8798 06:02:58.389868 RX Delay 0 -> 252, step: 8
8799 06:02:58.392916 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8800 06:02:58.396241 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8801 06:02:58.402801 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8802 06:02:58.405984 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8803 06:02:58.409380 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8804 06:02:58.412777 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8805 06:02:58.416503 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8806 06:02:58.422711 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8807 06:02:58.426215 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8808 06:02:58.429754 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8809 06:02:58.433092 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8810 06:02:58.436367 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8811 06:02:58.442889 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8812 06:02:58.446411 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8813 06:02:58.449405 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8814 06:02:58.452812 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8815 06:02:58.452910 ==
8816 06:02:58.456269 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 06:02:58.463167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 06:02:58.463251 ==
8819 06:02:58.463315 DQS Delay:
8820 06:02:58.463375 DQS0 = 0, DQS1 = 0
8821 06:02:58.466385 DQM Delay:
8822 06:02:58.466468 DQM0 = 135, DQM1 = 133
8823 06:02:58.469456 DQ Delay:
8824 06:02:58.472936 DQ0 =139, DQ1 =135, DQ2 =119, DQ3 =131
8825 06:02:58.476201 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8826 06:02:58.479761 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8827 06:02:58.482810 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8828 06:02:58.483064
8829 06:02:58.483253
8830 06:02:58.483427 ==
8831 06:02:58.486346 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 06:02:58.489678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 06:02:58.493347 ==
8834 06:02:58.493667
8835 06:02:58.493868
8836 06:02:58.494050 TX Vref Scan disable
8837 06:02:58.496783 == TX Byte 0 ==
8838 06:02:58.499448 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8839 06:02:58.502902 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8840 06:02:58.506474 == TX Byte 1 ==
8841 06:02:58.509875 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8842 06:02:58.512587 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8843 06:02:58.516489 ==
8844 06:02:58.516789 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 06:02:58.523009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 06:02:58.523306 ==
8847 06:02:58.534608
8848 06:02:58.538141 TX Vref early break, caculate TX vref
8849 06:02:58.541543 TX Vref=16, minBit 0, minWin=23, winSum=384
8850 06:02:58.544876 TX Vref=18, minBit 0, minWin=24, winSum=392
8851 06:02:58.547732 TX Vref=20, minBit 0, minWin=24, winSum=394
8852 06:02:58.551472 TX Vref=22, minBit 0, minWin=25, winSum=409
8853 06:02:58.554860 TX Vref=24, minBit 0, minWin=24, winSum=416
8854 06:02:58.561309 TX Vref=26, minBit 0, minWin=26, winSum=426
8855 06:02:58.564676 TX Vref=28, minBit 1, minWin=25, winSum=424
8856 06:02:58.568195 TX Vref=30, minBit 1, minWin=25, winSum=418
8857 06:02:58.571559 TX Vref=32, minBit 1, minWin=25, winSum=414
8858 06:02:58.574601 TX Vref=34, minBit 0, minWin=24, winSum=403
8859 06:02:58.581314 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
8860 06:02:58.581907
8861 06:02:58.584977 Final TX Range 0 Vref 26
8862 06:02:58.585395
8863 06:02:58.585724 ==
8864 06:02:58.588168 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 06:02:58.591408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 06:02:58.591953 ==
8867 06:02:58.592463
8868 06:02:58.592794
8869 06:02:58.594563 TX Vref Scan disable
8870 06:02:58.601572 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8871 06:02:58.602024 == TX Byte 0 ==
8872 06:02:58.604586 u2DelayCellOfst[0]=16 cells (5 PI)
8873 06:02:58.608467 u2DelayCellOfst[1]=10 cells (3 PI)
8874 06:02:58.611186 u2DelayCellOfst[2]=0 cells (0 PI)
8875 06:02:58.614668 u2DelayCellOfst[3]=6 cells (2 PI)
8876 06:02:58.618023 u2DelayCellOfst[4]=6 cells (2 PI)
8877 06:02:58.621531 u2DelayCellOfst[5]=16 cells (5 PI)
8878 06:02:58.621995 u2DelayCellOfst[6]=16 cells (5 PI)
8879 06:02:58.624854 u2DelayCellOfst[7]=6 cells (2 PI)
8880 06:02:58.631427 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8881 06:02:58.634446 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8882 06:02:58.634900 == TX Byte 1 ==
8883 06:02:58.638110 u2DelayCellOfst[8]=0 cells (0 PI)
8884 06:02:58.641593 u2DelayCellOfst[9]=3 cells (1 PI)
8885 06:02:58.644839 u2DelayCellOfst[10]=10 cells (3 PI)
8886 06:02:58.648262 u2DelayCellOfst[11]=6 cells (2 PI)
8887 06:02:58.651496 u2DelayCellOfst[12]=13 cells (4 PI)
8888 06:02:58.654913 u2DelayCellOfst[13]=16 cells (5 PI)
8889 06:02:58.658124 u2DelayCellOfst[14]=16 cells (5 PI)
8890 06:02:58.661386 u2DelayCellOfst[15]=16 cells (5 PI)
8891 06:02:58.664874 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8892 06:02:58.667803 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8893 06:02:58.671037 DramC Write-DBI on
8894 06:02:58.671467 ==
8895 06:02:58.674411 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 06:02:58.678034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 06:02:58.678465 ==
8898 06:02:58.678800
8899 06:02:58.679110
8900 06:02:58.681224 TX Vref Scan disable
8901 06:02:58.684513 == TX Byte 0 ==
8902 06:02:58.687950 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8903 06:02:58.691413 == TX Byte 1 ==
8904 06:02:58.694245 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8905 06:02:58.694765 DramC Write-DBI off
8906 06:02:58.695103
8907 06:02:58.697626 [DATLAT]
8908 06:02:58.698120 Freq=1600, CH1 RK1
8909 06:02:58.698460
8910 06:02:58.700824 DATLAT Default: 0xf
8911 06:02:58.701245 0, 0xFFFF, sum = 0
8912 06:02:58.704401 1, 0xFFFF, sum = 0
8913 06:02:58.704891 2, 0xFFFF, sum = 0
8914 06:02:58.707758 3, 0xFFFF, sum = 0
8915 06:02:58.708187 4, 0xFFFF, sum = 0
8916 06:02:58.711249 5, 0xFFFF, sum = 0
8917 06:02:58.711676 6, 0xFFFF, sum = 0
8918 06:02:58.714355 7, 0xFFFF, sum = 0
8919 06:02:58.714781 8, 0xFFFF, sum = 0
8920 06:02:58.717796 9, 0xFFFF, sum = 0
8921 06:02:58.721079 10, 0xFFFF, sum = 0
8922 06:02:58.721509 11, 0xFFFF, sum = 0
8923 06:02:58.724166 12, 0xFFFF, sum = 0
8924 06:02:58.724659 13, 0xFFFF, sum = 0
8925 06:02:58.727706 14, 0x0, sum = 1
8926 06:02:58.728120 15, 0x0, sum = 2
8927 06:02:58.731251 16, 0x0, sum = 3
8928 06:02:58.731681 17, 0x0, sum = 4
8929 06:02:58.732015 best_step = 15
8930 06:02:58.734062
8931 06:02:58.734476 ==
8932 06:02:58.737609 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 06:02:58.740788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 06:02:58.741203 ==
8935 06:02:58.741528 RX Vref Scan: 0
8936 06:02:58.741830
8937 06:02:58.744270 RX Vref 0 -> 0, step: 1
8938 06:02:58.744728
8939 06:02:58.747360 RX Delay 19 -> 252, step: 4
8940 06:02:58.750597 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8941 06:02:58.754168 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8942 06:02:58.761123 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8943 06:02:58.763837 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8944 06:02:58.767041 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8945 06:02:58.770901 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8946 06:02:58.774410 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8947 06:02:58.780702 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8948 06:02:58.784004 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8949 06:02:58.787514 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8950 06:02:58.790792 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8951 06:02:58.793818 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8952 06:02:58.800752 iDelay=195, Bit 12, Center 142 (91 ~ 194) 104
8953 06:02:58.804137 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8954 06:02:58.807508 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8955 06:02:58.810999 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8956 06:02:58.811459 ==
8957 06:02:58.813798 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 06:02:58.820701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 06:02:58.821405 ==
8960 06:02:58.821915 DQS Delay:
8961 06:02:58.822460 DQS0 = 0, DQS1 = 0
8962 06:02:58.823520 DQM Delay:
8963 06:02:58.824129 DQM0 = 134, DQM1 = 131
8964 06:02:58.826917 DQ Delay:
8965 06:02:58.830182 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
8966 06:02:58.834144 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8967 06:02:58.836975 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8968 06:02:58.840756 DQ12 =142, DQ13 =138, DQ14 =136, DQ15 =140
8969 06:02:58.841181
8970 06:02:58.841513
8971 06:02:58.841820
8972 06:02:58.843999 [DramC_TX_OE_Calibration] TA2
8973 06:02:58.847593 Original DQ_B0 (3 6) =30, OEN = 27
8974 06:02:58.850261 Original DQ_B1 (3 6) =30, OEN = 27
8975 06:02:58.853791 24, 0x0, End_B0=24 End_B1=24
8976 06:02:58.854221 25, 0x0, End_B0=25 End_B1=25
8977 06:02:58.856883 26, 0x0, End_B0=26 End_B1=26
8978 06:02:58.860728 27, 0x0, End_B0=27 End_B1=27
8979 06:02:58.864032 28, 0x0, End_B0=28 End_B1=28
8980 06:02:58.866747 29, 0x0, End_B0=29 End_B1=29
8981 06:02:58.867175 30, 0x0, End_B0=30 End_B1=30
8982 06:02:58.870267 31, 0x4141, End_B0=30 End_B1=30
8983 06:02:58.873644 Byte0 end_step=30 best_step=27
8984 06:02:58.876933 Byte1 end_step=30 best_step=27
8985 06:02:58.880275 Byte0 TX OE(2T, 0.5T) = (3, 3)
8986 06:02:58.883461 Byte1 TX OE(2T, 0.5T) = (3, 3)
8987 06:02:58.883924
8988 06:02:58.884259
8989 06:02:58.890211 [DQSOSCAuto] RK1, (LSB)MR18= 0x2005, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
8990 06:02:58.893656 CH1 RK1: MR19=303, MR18=2005
8991 06:02:58.900408 CH1_RK1: MR19=0x303, MR18=0x2005, DQSOSC=393, MR23=63, INC=23, DEC=15
8992 06:02:58.903662 [RxdqsGatingPostProcess] freq 1600
8993 06:02:58.907001 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8994 06:02:58.910562 best DQS0 dly(2T, 0.5T) = (1, 1)
8995 06:02:58.913362 best DQS1 dly(2T, 0.5T) = (1, 1)
8996 06:02:58.917309 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8997 06:02:58.920540 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8998 06:02:58.923621 best DQS0 dly(2T, 0.5T) = (1, 1)
8999 06:02:58.927126 best DQS1 dly(2T, 0.5T) = (1, 1)
9000 06:02:58.930120 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9001 06:02:58.933557 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9002 06:02:58.937087 Pre-setting of DQS Precalculation
9003 06:02:58.940185 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9004 06:02:58.946730 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9005 06:02:58.953452 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9006 06:02:58.953901
9007 06:02:58.956770
9008 06:02:58.957191 [Calibration Summary] 3200 Mbps
9009 06:02:58.960067 CH 0, Rank 0
9010 06:02:58.960534 SW Impedance : PASS
9011 06:02:58.963743 DUTY Scan : NO K
9012 06:02:58.966491 ZQ Calibration : PASS
9013 06:02:58.966914 Jitter Meter : NO K
9014 06:02:58.969796 CBT Training : PASS
9015 06:02:58.973711 Write leveling : PASS
9016 06:02:58.974131 RX DQS gating : PASS
9017 06:02:58.976507 RX DQ/DQS(RDDQC) : PASS
9018 06:02:58.979948 TX DQ/DQS : PASS
9019 06:02:58.980414 RX DATLAT : PASS
9020 06:02:58.983400 RX DQ/DQS(Engine): PASS
9021 06:02:58.986697 TX OE : PASS
9022 06:02:58.987119 All Pass.
9023 06:02:58.987471
9024 06:02:58.987771 CH 0, Rank 1
9025 06:02:58.990186 SW Impedance : PASS
9026 06:02:58.993278 DUTY Scan : NO K
9027 06:02:58.993738 ZQ Calibration : PASS
9028 06:02:58.996781 Jitter Meter : NO K
9029 06:02:58.997265 CBT Training : PASS
9030 06:02:59.000197 Write leveling : PASS
9031 06:02:59.003569 RX DQS gating : PASS
9032 06:02:59.003981 RX DQ/DQS(RDDQC) : PASS
9033 06:02:59.006524 TX DQ/DQS : PASS
9034 06:02:59.009848 RX DATLAT : PASS
9035 06:02:59.010319 RX DQ/DQS(Engine): PASS
9036 06:02:59.013438 TX OE : PASS
9037 06:02:59.013843 All Pass.
9038 06:02:59.014269
9039 06:02:59.016502 CH 1, Rank 0
9040 06:02:59.016919 SW Impedance : PASS
9041 06:02:59.019637 DUTY Scan : NO K
9042 06:02:59.023133 ZQ Calibration : PASS
9043 06:02:59.023589 Jitter Meter : NO K
9044 06:02:59.026853 CBT Training : PASS
9045 06:02:59.030273 Write leveling : PASS
9046 06:02:59.030689 RX DQS gating : PASS
9047 06:02:59.033132 RX DQ/DQS(RDDQC) : PASS
9048 06:02:59.036673 TX DQ/DQS : PASS
9049 06:02:59.037116 RX DATLAT : PASS
9050 06:02:59.039597 RX DQ/DQS(Engine): PASS
9051 06:02:59.043048 TX OE : PASS
9052 06:02:59.043478 All Pass.
9053 06:02:59.043909
9054 06:02:59.044448 CH 1, Rank 1
9055 06:02:59.046617 SW Impedance : PASS
9056 06:02:59.049566 DUTY Scan : NO K
9057 06:02:59.049925 ZQ Calibration : PASS
9058 06:02:59.053107 Jitter Meter : NO K
9059 06:02:59.053406 CBT Training : PASS
9060 06:02:59.055937 Write leveling : PASS
9061 06:02:59.059386 RX DQS gating : PASS
9062 06:02:59.059611 RX DQ/DQS(RDDQC) : PASS
9063 06:02:59.062566 TX DQ/DQS : PASS
9064 06:02:59.065771 RX DATLAT : PASS
9065 06:02:59.065923 RX DQ/DQS(Engine): PASS
9066 06:02:59.069544 TX OE : PASS
9067 06:02:59.069731 All Pass.
9068 06:02:59.069911
9069 06:02:59.072620 DramC Write-DBI on
9070 06:02:59.076156 PER_BANK_REFRESH: Hybrid Mode
9071 06:02:59.076319 TX_TRACKING: ON
9072 06:02:59.085938 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9073 06:02:59.093012 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9074 06:02:59.099168 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9075 06:02:59.106435 [FAST_K] Save calibration result to emmc
9076 06:02:59.106909 sync common calibartion params.
9077 06:02:59.109175 sync cbt_mode0:1, 1:1
9078 06:02:59.112834 dram_init: ddr_geometry: 2
9079 06:02:59.113329 dram_init: ddr_geometry: 2
9080 06:02:59.116028 dram_init: ddr_geometry: 2
9081 06:02:59.119430 0:dram_rank_size:100000000
9082 06:02:59.122509 1:dram_rank_size:100000000
9083 06:02:59.125560 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9084 06:02:59.129131 DFS_SHUFFLE_HW_MODE: ON
9085 06:02:59.132459 dramc_set_vcore_voltage set vcore to 725000
9086 06:02:59.136112 Read voltage for 1600, 0
9087 06:02:59.136550 Vio18 = 0
9088 06:02:59.138901 Vcore = 725000
9089 06:02:59.139312 Vdram = 0
9090 06:02:59.139643 Vddq = 0
9091 06:02:59.139950 Vmddr = 0
9092 06:02:59.142568 switch to 3200 Mbps bootup
9093 06:02:59.146019 [DramcRunTimeConfig]
9094 06:02:59.146502 PHYPLL
9095 06:02:59.146831 DPM_CONTROL_AFTERK: ON
9096 06:02:59.148740 PER_BANK_REFRESH: ON
9097 06:02:59.152273 REFRESH_OVERHEAD_REDUCTION: ON
9098 06:02:59.155780 CMD_PICG_NEW_MODE: OFF
9099 06:02:59.156326 XRTWTW_NEW_MODE: ON
9100 06:02:59.159350 XRTRTR_NEW_MODE: ON
9101 06:02:59.159839 TX_TRACKING: ON
9102 06:02:59.162947 RDSEL_TRACKING: OFF
9103 06:02:59.163453 DQS Precalculation for DVFS: ON
9104 06:02:59.165482 RX_TRACKING: OFF
9105 06:02:59.165899 HW_GATING DBG: ON
9106 06:02:59.169055 ZQCS_ENABLE_LP4: ON
9107 06:02:59.172338 RX_PICG_NEW_MODE: ON
9108 06:02:59.172761 TX_PICG_NEW_MODE: ON
9109 06:02:59.175687 ENABLE_RX_DCM_DPHY: ON
9110 06:02:59.178921 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9111 06:02:59.179348 DUMMY_READ_FOR_TRACKING: OFF
9112 06:02:59.182005 !!! SPM_CONTROL_AFTERK: OFF
9113 06:02:59.186019 !!! SPM could not control APHY
9114 06:02:59.188753 IMPEDANCE_TRACKING: ON
9115 06:02:59.189172 TEMP_SENSOR: ON
9116 06:02:59.192478 HW_SAVE_FOR_SR: OFF
9117 06:02:59.192917 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9118 06:02:59.199183 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9119 06:02:59.199699 Read ODT Tracking: ON
9120 06:02:59.202250 Refresh Rate DeBounce: ON
9121 06:02:59.205760 DFS_NO_QUEUE_FLUSH: ON
9122 06:02:59.206178 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9123 06:02:59.208736 ENABLE_DFS_RUNTIME_MRW: OFF
9124 06:02:59.212205 DDR_RESERVE_NEW_MODE: ON
9125 06:02:59.215614 MR_CBT_SWITCH_FREQ: ON
9126 06:02:59.216279 =========================
9127 06:02:59.234973 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9128 06:02:59.238301 dram_init: ddr_geometry: 2
9129 06:02:59.256673 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9130 06:02:59.260213 dram_init: dram init end (result: 0)
9131 06:02:59.266599 DRAM-K: Full calibration passed in 24432 msecs
9132 06:02:59.270099 MRC: failed to locate region type 0.
9133 06:02:59.270582 DRAM rank0 size:0x100000000,
9134 06:02:59.273590 DRAM rank1 size=0x100000000
9135 06:02:59.283351 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9136 06:02:59.289987 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9137 06:02:59.296645 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9138 06:02:59.303682 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9139 06:02:59.307305 DRAM rank0 size:0x100000000,
9140 06:02:59.309989 DRAM rank1 size=0x100000000
9141 06:02:59.310414 CBMEM:
9142 06:02:59.313193 IMD: root @ 0xfffff000 254 entries.
9143 06:02:59.316739 IMD: root @ 0xffffec00 62 entries.
9144 06:02:59.319792 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9145 06:02:59.323282 WARNING: RO_VPD is uninitialized or empty.
9146 06:02:59.329562 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9147 06:02:59.336489 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9148 06:02:59.349149 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9149 06:02:59.360843 BS: romstage times (exec / console): total (unknown) / 23968 ms
9150 06:02:59.361362
9151 06:02:59.361698
9152 06:02:59.371021 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9153 06:02:59.374555 ARM64: Exception handlers installed.
9154 06:02:59.377388 ARM64: Testing exception
9155 06:02:59.380922 ARM64: Done test exception
9156 06:02:59.381383 Enumerating buses...
9157 06:02:59.384425 Show all devs... Before device enumeration.
9158 06:02:59.387395 Root Device: enabled 1
9159 06:02:59.390881 CPU_CLUSTER: 0: enabled 1
9160 06:02:59.391312 CPU: 00: enabled 1
9161 06:02:59.394268 Compare with tree...
9162 06:02:59.394697 Root Device: enabled 1
9163 06:02:59.397625 CPU_CLUSTER: 0: enabled 1
9164 06:02:59.401005 CPU: 00: enabled 1
9165 06:02:59.401455 Root Device scanning...
9166 06:02:59.404398 scan_static_bus for Root Device
9167 06:02:59.407324 CPU_CLUSTER: 0 enabled
9168 06:02:59.410877 scan_static_bus for Root Device done
9169 06:02:59.414304 scan_bus: bus Root Device finished in 8 msecs
9170 06:02:59.414732 done
9171 06:02:59.420529 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9172 06:02:59.424257 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9173 06:02:59.430861 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9174 06:02:59.434049 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9175 06:02:59.437668 Allocating resources...
9176 06:02:59.438104 Reading resources...
9177 06:02:59.443903 Root Device read_resources bus 0 link: 0
9178 06:02:59.444370 DRAM rank0 size:0x100000000,
9179 06:02:59.447886 DRAM rank1 size=0x100000000
9180 06:02:59.450972 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9181 06:02:59.454199 CPU: 00 missing read_resources
9182 06:02:59.457386 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9183 06:02:59.464376 Root Device read_resources bus 0 link: 0 done
9184 06:02:59.464825 Done reading resources.
9185 06:02:59.470950 Show resources in subtree (Root Device)...After reading.
9186 06:02:59.473814 Root Device child on link 0 CPU_CLUSTER: 0
9187 06:02:59.477066 CPU_CLUSTER: 0 child on link 0 CPU: 00
9188 06:02:59.487221 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9189 06:02:59.487644 CPU: 00
9190 06:02:59.490745 Root Device assign_resources, bus 0 link: 0
9191 06:02:59.494199 CPU_CLUSTER: 0 missing set_resources
9192 06:02:59.496955 Root Device assign_resources, bus 0 link: 0 done
9193 06:02:59.500420 Done setting resources.
9194 06:02:59.507026 Show resources in subtree (Root Device)...After assigning values.
9195 06:02:59.510521 Root Device child on link 0 CPU_CLUSTER: 0
9196 06:02:59.513836 CPU_CLUSTER: 0 child on link 0 CPU: 00
9197 06:02:59.523797 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9198 06:02:59.524342 CPU: 00
9199 06:02:59.527578 Done allocating resources.
9200 06:02:59.530981 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9201 06:02:59.533781 Enabling resources...
9202 06:02:59.534197 done.
9203 06:02:59.540709 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9204 06:02:59.541227 Initializing devices...
9205 06:02:59.543875 Root Device init
9206 06:02:59.544335 init hardware done!
9207 06:02:59.547011 0x00000018: ctrlr->caps
9208 06:02:59.550354 52.000 MHz: ctrlr->f_max
9209 06:02:59.550793 0.400 MHz: ctrlr->f_min
9210 06:02:59.553926 0x40ff8080: ctrlr->voltages
9211 06:02:59.554353 sclk: 390625
9212 06:02:59.557331 Bus Width = 1
9213 06:02:59.557760 sclk: 390625
9214 06:02:59.558290 Bus Width = 1
9215 06:02:59.560630 Early init status = 3
9216 06:02:59.567213 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9217 06:02:59.570132 in-header: 03 fc 00 00 01 00 00 00
9218 06:02:59.570559 in-data: 00
9219 06:02:59.577243 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9220 06:02:59.580748 in-header: 03 fd 00 00 00 00 00 00
9221 06:02:59.581166 in-data:
9222 06:02:59.586765 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9223 06:02:59.590551 in-header: 03 fc 00 00 01 00 00 00
9224 06:02:59.593630 in-data: 00
9225 06:02:59.597175 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9226 06:02:59.601333 in-header: 03 fd 00 00 00 00 00 00
9227 06:02:59.604259 in-data:
9228 06:02:59.607807 [SSUSB] Setting up USB HOST controller...
9229 06:02:59.610608 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9230 06:02:59.614481 [SSUSB] phy power-on done.
9231 06:02:59.617018 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9232 06:02:59.624223 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9233 06:02:59.627683 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9234 06:02:59.633785 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9235 06:02:59.640754 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9236 06:02:59.647125 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9237 06:02:59.653902 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9238 06:02:59.660390 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9239 06:02:59.663976 SPM: binary array size = 0x9dc
9240 06:02:59.667585 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9241 06:02:59.673957 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9242 06:02:59.680458 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9243 06:02:59.683664 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9244 06:02:59.690647 configure_display: Starting display init
9245 06:02:59.723951 anx7625_power_on_init: Init interface.
9246 06:02:59.727248 anx7625_disable_pd_protocol: Disabled PD feature.
9247 06:02:59.730480 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9248 06:02:59.758452 anx7625_start_dp_work: Secure OCM version=00
9249 06:02:59.762115 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9250 06:02:59.776891 sp_tx_get_edid_block: EDID Block = 1
9251 06:02:59.879306 Extracted contents:
9252 06:02:59.882722 header: 00 ff ff ff ff ff ff 00
9253 06:02:59.885564 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9254 06:02:59.889226 version: 01 04
9255 06:02:59.892617 basic params: 95 1f 11 78 0a
9256 06:02:59.895556 chroma info: 76 90 94 55 54 90 27 21 50 54
9257 06:02:59.899510 established: 00 00 00
9258 06:02:59.906073 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9259 06:02:59.908883 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9260 06:02:59.915821 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9261 06:02:59.922345 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9262 06:02:59.928663 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9263 06:02:59.931942 extensions: 00
9264 06:02:59.932640 checksum: fb
9265 06:02:59.933087
9266 06:02:59.935283 Manufacturer: IVO Model 57d Serial Number 0
9267 06:02:59.938851 Made week 0 of 2020
9268 06:02:59.939404 EDID version: 1.4
9269 06:02:59.942221 Digital display
9270 06:02:59.945533 6 bits per primary color channel
9271 06:02:59.945959 DisplayPort interface
9272 06:02:59.948649 Maximum image size: 31 cm x 17 cm
9273 06:02:59.952219 Gamma: 220%
9274 06:02:59.952811 Check DPMS levels
9275 06:02:59.955443 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9276 06:02:59.961522 First detailed timing is preferred timing
9277 06:02:59.961952 Established timings supported:
9278 06:02:59.965030 Standard timings supported:
9279 06:02:59.968655 Detailed timings
9280 06:02:59.971943 Hex of detail: 383680a07038204018303c0035ae10000019
9281 06:02:59.978760 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9282 06:02:59.981864 0780 0798 07c8 0820 hborder 0
9283 06:02:59.984764 0438 043b 0447 0458 vborder 0
9284 06:02:59.988343 -hsync -vsync
9285 06:02:59.988869 Did detailed timing
9286 06:02:59.994642 Hex of detail: 000000000000000000000000000000000000
9287 06:02:59.998180 Manufacturer-specified data, tag 0
9288 06:03:00.001737 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9289 06:03:00.004976 ASCII string: InfoVision
9290 06:03:00.008501 Hex of detail: 000000fe00523134304e574635205248200a
9291 06:03:00.011184 ASCII string: R140NWF5 RH
9292 06:03:00.011604 Checksum
9293 06:03:00.014748 Checksum: 0xfb (valid)
9294 06:03:00.018333 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9295 06:03:00.021180 DSI data_rate: 832800000 bps
9296 06:03:00.027827 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9297 06:03:00.031059 anx7625_parse_edid: pixelclock(138800).
9298 06:03:00.034295 hactive(1920), hsync(48), hfp(24), hbp(88)
9299 06:03:00.037656 vactive(1080), vsync(12), vfp(3), vbp(17)
9300 06:03:00.041026 anx7625_dsi_config: config dsi.
9301 06:03:00.047834 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9302 06:03:00.061014 anx7625_dsi_config: success to config DSI
9303 06:03:00.064139 anx7625_dp_start: MIPI phy setup OK.
9304 06:03:00.068004 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9305 06:03:00.071190 mtk_ddp_mode_set invalid vrefresh 60
9306 06:03:00.074428 main_disp_path_setup
9307 06:03:00.074808 ovl_layer_smi_id_en
9308 06:03:00.077915 ovl_layer_smi_id_en
9309 06:03:00.078213 ccorr_config
9310 06:03:00.078450 aal_config
9311 06:03:00.080665 gamma_config
9312 06:03:00.080962 postmask_config
9313 06:03:00.084112 dither_config
9314 06:03:00.087497 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9315 06:03:00.094065 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9316 06:03:00.097529 Root Device init finished in 551 msecs
9317 06:03:00.101058 CPU_CLUSTER: 0 init
9318 06:03:00.107955 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9319 06:03:00.111252 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9320 06:03:00.114693 APU_MBOX 0x190000b0 = 0x10001
9321 06:03:00.117303 APU_MBOX 0x190001b0 = 0x10001
9322 06:03:00.120761 APU_MBOX 0x190005b0 = 0x10001
9323 06:03:00.124394 APU_MBOX 0x190006b0 = 0x10001
9324 06:03:00.127629 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9325 06:03:00.140477 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9326 06:03:00.152309 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9327 06:03:00.159026 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9328 06:03:00.170635 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9329 06:03:00.179683 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9330 06:03:00.183187 CPU_CLUSTER: 0 init finished in 81 msecs
9331 06:03:00.186430 Devices initialized
9332 06:03:00.190073 Show all devs... After init.
9333 06:03:00.190207 Root Device: enabled 1
9334 06:03:00.192879 CPU_CLUSTER: 0: enabled 1
9335 06:03:00.196077 CPU: 00: enabled 1
9336 06:03:00.199922 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9337 06:03:00.203191 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9338 06:03:00.206700 ELOG: NV offset 0x57f000 size 0x1000
9339 06:03:00.212808 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9340 06:03:00.219452 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9341 06:03:00.222859 ELOG: Event(17) added with size 13 at 2023-12-25 06:00:25 UTC
9342 06:03:00.226257 out: cmd=0x121: 03 db 21 01 00 00 00 00
9343 06:03:00.229848 in-header: 03 f4 00 00 2c 00 00 00
9344 06:03:00.243130 in-data: 6b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9345 06:03:00.249781 ELOG: Event(A1) added with size 10 at 2023-12-25 06:00:25 UTC
9346 06:03:00.256209 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9347 06:03:00.262894 ELOG: Event(A0) added with size 9 at 2023-12-25 06:00:25 UTC
9348 06:03:00.266332 elog_add_boot_reason: Logged dev mode boot
9349 06:03:00.269771 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9350 06:03:00.273323 Finalize devices...
9351 06:03:00.273406 Devices finalized
9352 06:03:00.280233 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9353 06:03:00.283052 Writing coreboot table at 0xffe64000
9354 06:03:00.286426 0. 000000000010a000-0000000000113fff: RAMSTAGE
9355 06:03:00.289845 1. 0000000040000000-00000000400fffff: RAM
9356 06:03:00.293052 2. 0000000040100000-000000004032afff: RAMSTAGE
9357 06:03:00.299766 3. 000000004032b000-00000000545fffff: RAM
9358 06:03:00.303215 4. 0000000054600000-000000005465ffff: BL31
9359 06:03:00.306516 5. 0000000054660000-00000000ffe63fff: RAM
9360 06:03:00.309703 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9361 06:03:00.316225 7. 0000000100000000-000000023fffffff: RAM
9362 06:03:00.316318 Passing 5 GPIOs to payload:
9363 06:03:00.323010 NAME | PORT | POLARITY | VALUE
9364 06:03:00.326379 EC in RW | 0x000000aa | low | undefined
9365 06:03:00.333152 EC interrupt | 0x00000005 | low | undefined
9366 06:03:00.336648 TPM interrupt | 0x000000ab | high | undefined
9367 06:03:00.339591 SD card detect | 0x00000011 | high | undefined
9368 06:03:00.346456 speaker enable | 0x00000093 | high | undefined
9369 06:03:00.349249 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9370 06:03:00.352848 in-header: 03 f9 00 00 02 00 00 00
9371 06:03:00.352934 in-data: 02 00
9372 06:03:00.356171 ADC[4]: Raw value=904357 ID=7
9373 06:03:00.359361 ADC[3]: Raw value=213441 ID=1
9374 06:03:00.359448 RAM Code: 0x71
9375 06:03:00.362626 ADC[6]: Raw value=75701 ID=0
9376 06:03:00.366043 ADC[5]: Raw value=213072 ID=1
9377 06:03:00.366125 SKU Code: 0x1
9378 06:03:00.373154 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5137
9379 06:03:00.375854 coreboot table: 964 bytes.
9380 06:03:00.379302 IMD ROOT 0. 0xfffff000 0x00001000
9381 06:03:00.382980 IMD SMALL 1. 0xffffe000 0x00001000
9382 06:03:00.385815 RO MCACHE 2. 0xffffc000 0x00001104
9383 06:03:00.389347 CONSOLE 3. 0xfff7c000 0x00080000
9384 06:03:00.392826 FMAP 4. 0xfff7b000 0x00000452
9385 06:03:00.396442 TIME STAMP 5. 0xfff7a000 0x00000910
9386 06:03:00.399693 VBOOT WORK 6. 0xfff66000 0x00014000
9387 06:03:00.403077 RAMOOPS 7. 0xffe66000 0x00100000
9388 06:03:00.406262 COREBOOT 8. 0xffe64000 0x00002000
9389 06:03:00.406344 IMD small region:
9390 06:03:00.409215 IMD ROOT 0. 0xffffec00 0x00000400
9391 06:03:00.412501 VPD 1. 0xffffeb80 0x0000006c
9392 06:03:00.415863 MMC STATUS 2. 0xffffeb60 0x00000004
9393 06:03:00.423143 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9394 06:03:00.423226 Probing TPM: done!
9395 06:03:00.429473 Connected to device vid:did:rid of 1ae0:0028:00
9396 06:03:00.436129 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9397 06:03:00.443926 Initialized TPM device CR50 revision 0
9398 06:03:00.444015 Checking cr50 for pending updates
9399 06:03:00.449395 Reading cr50 TPM mode
9400 06:03:00.458364 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9401 06:03:00.465046 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9402 06:03:00.504691 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9403 06:03:00.508142 Checking segment from ROM address 0x40100000
9404 06:03:00.511358 Checking segment from ROM address 0x4010001c
9405 06:03:00.517820 Loading segment from ROM address 0x40100000
9406 06:03:00.517902 code (compression=0)
9407 06:03:00.528267 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9408 06:03:00.535046 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9409 06:03:00.535130 it's not compressed!
9410 06:03:00.541468 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9411 06:03:00.544855 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9412 06:03:00.565461 Loading segment from ROM address 0x4010001c
9413 06:03:00.565559 Entry Point 0x80000000
9414 06:03:00.568901 Loaded segments
9415 06:03:00.572186 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9416 06:03:00.578444 Jumping to boot code at 0x80000000(0xffe64000)
9417 06:03:00.585353 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9418 06:03:00.591822 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9419 06:03:00.600066 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9420 06:03:00.602983 Checking segment from ROM address 0x40100000
9421 06:03:00.606369 Checking segment from ROM address 0x4010001c
9422 06:03:00.613272 Loading segment from ROM address 0x40100000
9423 06:03:00.613359 code (compression=1)
9424 06:03:00.619396 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9425 06:03:00.629396 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9426 06:03:00.629493 using LZMA
9427 06:03:00.638138 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9428 06:03:00.644985 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9429 06:03:00.648139 Loading segment from ROM address 0x4010001c
9430 06:03:00.648455 Entry Point 0x54601000
9431 06:03:00.651676 Loaded segments
9432 06:03:00.654938 NOTICE: MT8192 bl31_setup
9433 06:03:00.661612 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9434 06:03:00.665002 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9435 06:03:00.668534 WARNING: region 0:
9436 06:03:00.671755 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9437 06:03:00.671986 WARNING: region 1:
9438 06:03:00.678488 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9439 06:03:00.681780 WARNING: region 2:
9440 06:03:00.685302 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9441 06:03:00.688338 WARNING: region 3:
9442 06:03:00.691843 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9443 06:03:00.695514 WARNING: region 4:
9444 06:03:00.701823 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9445 06:03:00.702336 WARNING: region 5:
9446 06:03:00.705227 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 06:03:00.708877 WARNING: region 6:
9448 06:03:00.711609 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9449 06:03:00.715486 WARNING: region 7:
9450 06:03:00.718950 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 06:03:00.725473 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9452 06:03:00.729026 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9453 06:03:00.731927 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9454 06:03:00.738675 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9455 06:03:00.742037 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9456 06:03:00.745248 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9457 06:03:00.751934 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9458 06:03:00.755140 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9459 06:03:00.758362 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9460 06:03:00.765348 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9461 06:03:00.768829 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9462 06:03:00.771687 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9463 06:03:00.778505 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9464 06:03:00.781692 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9465 06:03:00.788199 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9466 06:03:00.791680 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9467 06:03:00.794999 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9468 06:03:00.801790 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9469 06:03:00.805532 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9470 06:03:00.811738 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9471 06:03:00.815260 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9472 06:03:00.818754 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9473 06:03:00.825520 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9474 06:03:00.828336 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9475 06:03:00.835533 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9476 06:03:00.839019 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9477 06:03:00.842574 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9478 06:03:00.848804 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9479 06:03:00.852638 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9480 06:03:00.855187 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9481 06:03:00.862318 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9482 06:03:00.865603 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9483 06:03:00.868981 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9484 06:03:00.875703 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9485 06:03:00.878866 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9486 06:03:00.881963 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9487 06:03:00.885509 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9488 06:03:00.892212 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9489 06:03:00.895436 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9490 06:03:00.898625 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9491 06:03:00.902540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9492 06:03:00.908880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9493 06:03:00.912393 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9494 06:03:00.916153 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9495 06:03:00.919001 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9496 06:03:00.926263 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9497 06:03:00.929426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9498 06:03:00.932454 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9499 06:03:00.939187 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9500 06:03:00.942885 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9501 06:03:00.946498 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9502 06:03:00.952773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9503 06:03:00.955948 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9504 06:03:00.962834 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9505 06:03:00.966078 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9506 06:03:00.972655 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9507 06:03:00.976453 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9508 06:03:00.979611 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9509 06:03:00.985666 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9510 06:03:00.989022 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9511 06:03:00.996083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9512 06:03:00.998856 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9513 06:03:01.006351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9514 06:03:01.008925 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9515 06:03:01.012203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9516 06:03:01.019256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9517 06:03:01.022682 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9518 06:03:01.028944 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9519 06:03:01.032328 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9520 06:03:01.039267 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9521 06:03:01.042398 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9522 06:03:01.045520 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9523 06:03:01.052741 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9524 06:03:01.055954 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9525 06:03:01.062976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9526 06:03:01.066405 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9527 06:03:01.072968 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9528 06:03:01.076767 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9529 06:03:01.079203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9530 06:03:01.086152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9531 06:03:01.089601 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9532 06:03:01.096049 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9533 06:03:01.099152 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9534 06:03:01.106081 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9535 06:03:01.109527 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9536 06:03:01.112755 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9537 06:03:01.119874 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9538 06:03:01.123212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9539 06:03:01.129457 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9540 06:03:01.132830 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9541 06:03:01.139228 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9542 06:03:01.142967 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9543 06:03:01.146087 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9544 06:03:01.152821 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9545 06:03:01.155754 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9546 06:03:01.162540 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9547 06:03:01.165910 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9548 06:03:01.169273 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9549 06:03:01.172794 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9550 06:03:01.179712 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9551 06:03:01.183436 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9552 06:03:01.186385 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9553 06:03:01.193496 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9554 06:03:01.196844 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9555 06:03:01.203083 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9556 06:03:01.206300 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9557 06:03:01.209562 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9558 06:03:01.216611 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9559 06:03:01.220147 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9560 06:03:01.226362 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9561 06:03:01.229929 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9562 06:03:01.233047 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9563 06:03:01.239409 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9564 06:03:01.243098 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9565 06:03:01.249871 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9566 06:03:01.252913 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9567 06:03:01.256426 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9568 06:03:01.259890 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9569 06:03:01.266225 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9570 06:03:01.269561 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9571 06:03:01.273254 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9572 06:03:01.276228 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9573 06:03:01.282797 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9574 06:03:01.286233 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9575 06:03:01.289267 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9576 06:03:01.296632 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9577 06:03:01.299181 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9578 06:03:01.306153 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9579 06:03:01.309550 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9580 06:03:01.312889 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9581 06:03:01.319707 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9582 06:03:01.323092 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9583 06:03:01.325889 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9584 06:03:01.332698 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9585 06:03:01.335943 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9586 06:03:01.342563 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9587 06:03:01.346280 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9588 06:03:01.349331 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9589 06:03:01.355940 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9590 06:03:01.359421 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9591 06:03:01.366305 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9592 06:03:01.369736 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9593 06:03:01.372504 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9594 06:03:01.379531 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9595 06:03:01.383028 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9596 06:03:01.386322 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9597 06:03:01.392435 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9598 06:03:01.396308 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9599 06:03:01.402945 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9600 06:03:01.406238 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9601 06:03:01.409640 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9602 06:03:01.416340 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9603 06:03:01.419814 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9604 06:03:01.426953 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9605 06:03:01.429494 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9606 06:03:01.433197 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9607 06:03:01.440099 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9608 06:03:01.443436 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9609 06:03:01.446953 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9610 06:03:01.453192 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9611 06:03:01.456384 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9612 06:03:01.463468 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9613 06:03:01.466223 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9614 06:03:01.469959 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9615 06:03:01.476402 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9616 06:03:01.479712 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9617 06:03:01.486083 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9618 06:03:01.489438 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9619 06:03:01.492744 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9620 06:03:01.499844 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9621 06:03:01.503387 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9622 06:03:01.509929 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9623 06:03:01.512869 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9624 06:03:01.516497 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9625 06:03:01.522799 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9626 06:03:01.526407 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9627 06:03:01.529559 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9628 06:03:01.535863 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9629 06:03:01.539460 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9630 06:03:01.546352 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9631 06:03:01.549841 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9632 06:03:01.553297 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9633 06:03:01.559356 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9634 06:03:01.562822 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9635 06:03:01.569782 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9636 06:03:01.572896 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9637 06:03:01.576174 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9638 06:03:01.582694 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9639 06:03:01.585939 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9640 06:03:01.592185 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9641 06:03:01.595597 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9642 06:03:01.598926 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9643 06:03:01.606260 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9644 06:03:01.609479 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9645 06:03:01.616026 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9646 06:03:01.619224 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9647 06:03:01.625436 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9648 06:03:01.628860 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9649 06:03:01.632217 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9650 06:03:01.639194 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9651 06:03:01.642529 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9652 06:03:01.648525 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9653 06:03:01.652467 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9654 06:03:01.656001 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9655 06:03:01.662592 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9656 06:03:01.665918 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9657 06:03:01.671973 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9658 06:03:01.675573 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9659 06:03:01.682536 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9660 06:03:01.685769 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9661 06:03:01.689028 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9662 06:03:01.695353 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9663 06:03:01.698584 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9664 06:03:01.705223 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9665 06:03:01.708549 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9666 06:03:01.711721 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9667 06:03:01.719036 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9668 06:03:01.722237 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9669 06:03:01.728815 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9670 06:03:01.732257 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9671 06:03:01.738928 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9672 06:03:01.742511 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9673 06:03:01.745970 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9674 06:03:01.751946 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9675 06:03:01.755225 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9676 06:03:01.762094 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9677 06:03:01.764996 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9678 06:03:01.768340 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9679 06:03:01.775544 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9680 06:03:01.778465 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9681 06:03:01.781997 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9682 06:03:01.785001 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9683 06:03:01.791488 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9684 06:03:01.795324 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9685 06:03:01.798086 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9686 06:03:01.804820 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9687 06:03:01.808904 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9688 06:03:01.812280 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9689 06:03:01.818592 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9690 06:03:01.821679 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9691 06:03:01.825152 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9692 06:03:01.832405 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9693 06:03:01.835041 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9694 06:03:01.838753 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9695 06:03:01.845558 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9696 06:03:01.849056 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9697 06:03:01.854890 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9698 06:03:01.858211 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9699 06:03:01.861455 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9700 06:03:01.868596 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9701 06:03:01.871911 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9702 06:03:01.878409 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9703 06:03:01.881748 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9704 06:03:01.885244 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9705 06:03:01.891157 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9706 06:03:01.894995 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9707 06:03:01.897933 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9708 06:03:01.904715 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9709 06:03:01.907816 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9710 06:03:01.911515 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9711 06:03:01.917613 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9712 06:03:01.921210 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9713 06:03:01.928062 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9714 06:03:01.931265 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9715 06:03:01.934430 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9716 06:03:01.941394 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9717 06:03:01.944612 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9718 06:03:01.948157 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9719 06:03:01.955018 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9720 06:03:01.957498 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9721 06:03:01.960935 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9722 06:03:01.964567 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9723 06:03:01.971385 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9724 06:03:01.974883 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9725 06:03:01.977775 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9726 06:03:01.980996 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9727 06:03:01.988144 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9728 06:03:01.990700 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9729 06:03:01.994232 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9730 06:03:01.997939 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9731 06:03:02.004049 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9732 06:03:02.007803 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9733 06:03:02.011029 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9734 06:03:02.017410 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9735 06:03:02.020860 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9736 06:03:02.027219 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9737 06:03:02.030974 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9738 06:03:02.037538 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9739 06:03:02.040789 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9740 06:03:02.043867 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9741 06:03:02.050805 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9742 06:03:02.053735 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9743 06:03:02.060652 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9744 06:03:02.063710 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9745 06:03:02.067298 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9746 06:03:02.073734 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9747 06:03:02.077105 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9748 06:03:02.083361 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9749 06:03:02.087373 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9750 06:03:02.090546 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9751 06:03:02.096866 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9752 06:03:02.100243 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9753 06:03:02.107393 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9754 06:03:02.110632 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9755 06:03:02.113830 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9756 06:03:02.120361 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9757 06:03:02.123631 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9758 06:03:02.130620 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9759 06:03:02.134039 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9760 06:03:02.137524 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9761 06:03:02.143928 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9762 06:03:02.147441 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9763 06:03:02.153775 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9764 06:03:02.157224 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9765 06:03:02.159772 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9766 06:03:02.166760 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9767 06:03:02.170315 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9768 06:03:02.176388 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9769 06:03:02.179695 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9770 06:03:02.186760 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9771 06:03:02.189859 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9772 06:03:02.193473 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9773 06:03:02.200198 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9774 06:03:02.203617 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9775 06:03:02.210309 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9776 06:03:02.213590 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9777 06:03:02.216692 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9778 06:03:02.223242 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9779 06:03:02.226608 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9780 06:03:02.233190 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9781 06:03:02.236444 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9782 06:03:02.240403 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9783 06:03:02.246605 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9784 06:03:02.249827 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9785 06:03:02.256744 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9786 06:03:02.259971 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9787 06:03:02.266318 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9788 06:03:02.269687 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9789 06:03:02.272963 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9790 06:03:02.279619 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9791 06:03:02.283201 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9792 06:03:02.289817 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9793 06:03:02.293173 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9794 06:03:02.296661 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9795 06:03:02.302766 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9796 06:03:02.306166 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9797 06:03:02.309555 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9798 06:03:02.315940 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9799 06:03:02.318964 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9800 06:03:02.326126 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9801 06:03:02.328960 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9802 06:03:02.335352 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9803 06:03:02.339002 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9804 06:03:02.342052 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9805 06:03:02.348607 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9806 06:03:02.351943 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9807 06:03:02.359111 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9808 06:03:02.362271 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9809 06:03:02.368616 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9810 06:03:02.372283 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9811 06:03:02.379646 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9812 06:03:02.382809 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9813 06:03:02.386133 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9814 06:03:02.392194 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9815 06:03:02.395441 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9816 06:03:02.402306 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9817 06:03:02.405823 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9818 06:03:02.411917 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9819 06:03:02.415414 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9820 06:03:02.418717 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9821 06:03:02.425215 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9822 06:03:02.428705 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9823 06:03:02.435337 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9824 06:03:02.438614 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9825 06:03:02.445613 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9826 06:03:02.448957 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9827 06:03:02.455416 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9828 06:03:02.458551 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9829 06:03:02.462175 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9830 06:03:02.468382 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9831 06:03:02.471632 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9832 06:03:02.478498 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9833 06:03:02.481622 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9834 06:03:02.488474 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9835 06:03:02.491861 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9836 06:03:02.495188 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9837 06:03:02.502214 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9838 06:03:02.505370 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9839 06:03:02.511837 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9840 06:03:02.515280 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9841 06:03:02.521331 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9842 06:03:02.524865 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9843 06:03:02.528437 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9844 06:03:02.535642 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9845 06:03:02.538084 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9846 06:03:02.544757 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9847 06:03:02.548737 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9848 06:03:02.555197 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9849 06:03:02.558713 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9850 06:03:02.561987 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9851 06:03:02.568533 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9852 06:03:02.571924 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9853 06:03:02.578106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9854 06:03:02.581425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9855 06:03:02.585208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9856 06:03:02.591324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9857 06:03:02.594738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9858 06:03:02.600994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9859 06:03:02.604682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9860 06:03:02.611087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9861 06:03:02.614578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9862 06:03:02.621041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9863 06:03:02.625104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9864 06:03:02.630909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9865 06:03:02.634577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9866 06:03:02.643392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9867 06:03:02.644154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9868 06:03:02.650874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9869 06:03:02.654161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9870 06:03:02.661032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9871 06:03:02.663926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9872 06:03:02.670950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9873 06:03:02.673755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9874 06:03:02.681091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9875 06:03:02.684599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9876 06:03:02.690937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9877 06:03:02.694195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9878 06:03:02.700708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9879 06:03:02.703892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9880 06:03:02.710487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9881 06:03:02.713575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9882 06:03:02.720597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9883 06:03:02.723756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9884 06:03:02.730422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9885 06:03:02.733882 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9886 06:03:02.736979 INFO: [APUAPC] vio 0
9887 06:03:02.740683 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9888 06:03:02.747352 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9889 06:03:02.750794 INFO: [APUAPC] D0_APC_0: 0x400510
9890 06:03:02.751362 INFO: [APUAPC] D0_APC_1: 0x0
9891 06:03:02.753881 INFO: [APUAPC] D0_APC_2: 0x1540
9892 06:03:02.757725 INFO: [APUAPC] D0_APC_3: 0x0
9893 06:03:02.760628 INFO: [APUAPC] D1_APC_0: 0xffffffff
9894 06:03:02.763832 INFO: [APUAPC] D1_APC_1: 0xffffffff
9895 06:03:02.767364 INFO: [APUAPC] D1_APC_2: 0x3fffff
9896 06:03:02.770032 INFO: [APUAPC] D1_APC_3: 0x0
9897 06:03:02.773849 INFO: [APUAPC] D2_APC_0: 0xffffffff
9898 06:03:02.776683 INFO: [APUAPC] D2_APC_1: 0xffffffff
9899 06:03:02.780005 INFO: [APUAPC] D2_APC_2: 0x3fffff
9900 06:03:02.783456 INFO: [APUAPC] D2_APC_3: 0x0
9901 06:03:02.786791 INFO: [APUAPC] D3_APC_0: 0xffffffff
9902 06:03:02.790389 INFO: [APUAPC] D3_APC_1: 0xffffffff
9903 06:03:02.793902 INFO: [APUAPC] D3_APC_2: 0x3fffff
9904 06:03:02.796664 INFO: [APUAPC] D3_APC_3: 0x0
9905 06:03:02.800149 INFO: [APUAPC] D4_APC_0: 0xffffffff
9906 06:03:02.803659 INFO: [APUAPC] D4_APC_1: 0xffffffff
9907 06:03:02.807047 INFO: [APUAPC] D4_APC_2: 0x3fffff
9908 06:03:02.809749 INFO: [APUAPC] D4_APC_3: 0x0
9909 06:03:02.813392 INFO: [APUAPC] D5_APC_0: 0xffffffff
9910 06:03:02.816757 INFO: [APUAPC] D5_APC_1: 0xffffffff
9911 06:03:02.820206 INFO: [APUAPC] D5_APC_2: 0x3fffff
9912 06:03:02.823487 INFO: [APUAPC] D5_APC_3: 0x0
9913 06:03:02.827028 INFO: [APUAPC] D6_APC_0: 0xffffffff
9914 06:03:02.830018 INFO: [APUAPC] D6_APC_1: 0xffffffff
9915 06:03:02.833372 INFO: [APUAPC] D6_APC_2: 0x3fffff
9916 06:03:02.837018 INFO: [APUAPC] D6_APC_3: 0x0
9917 06:03:02.840722 INFO: [APUAPC] D7_APC_0: 0xffffffff
9918 06:03:02.843250 INFO: [APUAPC] D7_APC_1: 0xffffffff
9919 06:03:02.846524 INFO: [APUAPC] D7_APC_2: 0x3fffff
9920 06:03:02.850155 INFO: [APUAPC] D7_APC_3: 0x0
9921 06:03:02.853809 INFO: [APUAPC] D8_APC_0: 0xffffffff
9922 06:03:02.857125 INFO: [APUAPC] D8_APC_1: 0xffffffff
9923 06:03:02.859807 INFO: [APUAPC] D8_APC_2: 0x3fffff
9924 06:03:02.863102 INFO: [APUAPC] D8_APC_3: 0x0
9925 06:03:02.866931 INFO: [APUAPC] D9_APC_0: 0xffffffff
9926 06:03:02.870090 INFO: [APUAPC] D9_APC_1: 0xffffffff
9927 06:03:02.873218 INFO: [APUAPC] D9_APC_2: 0x3fffff
9928 06:03:02.873690 INFO: [APUAPC] D9_APC_3: 0x0
9929 06:03:02.879936 INFO: [APUAPC] D10_APC_0: 0xffffffff
9930 06:03:02.883540 INFO: [APUAPC] D10_APC_1: 0xffffffff
9931 06:03:02.886417 INFO: [APUAPC] D10_APC_2: 0x3fffff
9932 06:03:02.890288 INFO: [APUAPC] D10_APC_3: 0x0
9933 06:03:02.893156 INFO: [APUAPC] D11_APC_0: 0xffffffff
9934 06:03:02.896578 INFO: [APUAPC] D11_APC_1: 0xffffffff
9935 06:03:02.899651 INFO: [APUAPC] D11_APC_2: 0x3fffff
9936 06:03:02.903226 INFO: [APUAPC] D11_APC_3: 0x0
9937 06:03:02.906467 INFO: [APUAPC] D12_APC_0: 0xffffffff
9938 06:03:02.909573 INFO: [APUAPC] D12_APC_1: 0xffffffff
9939 06:03:02.913148 INFO: [APUAPC] D12_APC_2: 0x3fffff
9940 06:03:02.916694 INFO: [APUAPC] D12_APC_3: 0x0
9941 06:03:02.919479 INFO: [APUAPC] D13_APC_0: 0xffffffff
9942 06:03:02.923018 INFO: [APUAPC] D13_APC_1: 0xffffffff
9943 06:03:02.926799 INFO: [APUAPC] D13_APC_2: 0x3fffff
9944 06:03:02.929983 INFO: [APUAPC] D13_APC_3: 0x0
9945 06:03:02.933348 INFO: [APUAPC] D14_APC_0: 0xffffffff
9946 06:03:02.936437 INFO: [APUAPC] D14_APC_1: 0xffffffff
9947 06:03:02.939717 INFO: [APUAPC] D14_APC_2: 0x3fffff
9948 06:03:02.942852 INFO: [APUAPC] D14_APC_3: 0x0
9949 06:03:02.946078 INFO: [APUAPC] D15_APC_0: 0xffffffff
9950 06:03:02.949635 INFO: [APUAPC] D15_APC_1: 0xffffffff
9951 06:03:02.953218 INFO: [APUAPC] D15_APC_2: 0x3fffff
9952 06:03:02.956675 INFO: [APUAPC] D15_APC_3: 0x0
9953 06:03:02.957167 INFO: [APUAPC] APC_CON: 0x4
9954 06:03:02.959517 INFO: [NOCDAPC] D0_APC_0: 0x0
9955 06:03:02.962931 INFO: [NOCDAPC] D0_APC_1: 0x0
9956 06:03:02.966607 INFO: [NOCDAPC] D1_APC_0: 0x0
9957 06:03:02.970495 INFO: [NOCDAPC] D1_APC_1: 0xfff
9958 06:03:02.972806 INFO: [NOCDAPC] D2_APC_0: 0x0
9959 06:03:02.976149 INFO: [NOCDAPC] D2_APC_1: 0xfff
9960 06:03:02.979659 INFO: [NOCDAPC] D3_APC_0: 0x0
9961 06:03:02.982777 INFO: [NOCDAPC] D3_APC_1: 0xfff
9962 06:03:02.983196 INFO: [NOCDAPC] D4_APC_0: 0x0
9963 06:03:02.986389 INFO: [NOCDAPC] D4_APC_1: 0xfff
9964 06:03:02.989600 INFO: [NOCDAPC] D5_APC_0: 0x0
9965 06:03:02.993030 INFO: [NOCDAPC] D5_APC_1: 0xfff
9966 06:03:02.996398 INFO: [NOCDAPC] D6_APC_0: 0x0
9967 06:03:02.999925 INFO: [NOCDAPC] D6_APC_1: 0xfff
9968 06:03:03.002748 INFO: [NOCDAPC] D7_APC_0: 0x0
9969 06:03:03.005970 INFO: [NOCDAPC] D7_APC_1: 0xfff
9970 06:03:03.009918 INFO: [NOCDAPC] D8_APC_0: 0x0
9971 06:03:03.013030 INFO: [NOCDAPC] D8_APC_1: 0xfff
9972 06:03:03.015888 INFO: [NOCDAPC] D9_APC_0: 0x0
9973 06:03:03.016442 INFO: [NOCDAPC] D9_APC_1: 0xfff
9974 06:03:03.019406 INFO: [NOCDAPC] D10_APC_0: 0x0
9975 06:03:03.023103 INFO: [NOCDAPC] D10_APC_1: 0xfff
9976 06:03:03.026530 INFO: [NOCDAPC] D11_APC_0: 0x0
9977 06:03:03.029654 INFO: [NOCDAPC] D11_APC_1: 0xfff
9978 06:03:03.032576 INFO: [NOCDAPC] D12_APC_0: 0x0
9979 06:03:03.036523 INFO: [NOCDAPC] D12_APC_1: 0xfff
9980 06:03:03.039351 INFO: [NOCDAPC] D13_APC_0: 0x0
9981 06:03:03.042753 INFO: [NOCDAPC] D13_APC_1: 0xfff
9982 06:03:03.046345 INFO: [NOCDAPC] D14_APC_0: 0x0
9983 06:03:03.049708 INFO: [NOCDAPC] D14_APC_1: 0xfff
9984 06:03:03.052733 INFO: [NOCDAPC] D15_APC_0: 0x0
9985 06:03:03.056859 INFO: [NOCDAPC] D15_APC_1: 0xfff
9986 06:03:03.059467 INFO: [NOCDAPC] APC_CON: 0x4
9987 06:03:03.062983 INFO: [APUAPC] set_apusys_apc done
9988 06:03:03.065951 INFO: [DEVAPC] devapc_init done
9989 06:03:03.069555 INFO: GICv3 without legacy support detected.
9990 06:03:03.072906 INFO: ARM GICv3 driver initialized in EL3
9991 06:03:03.076265 INFO: Maximum SPI INTID supported: 639
9992 06:03:03.079977 INFO: BL31: Initializing runtime services
9993 06:03:03.086356 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9994 06:03:03.089369 INFO: SPM: enable CPC mode
9995 06:03:03.092616 INFO: mcdi ready for mcusys-off-idle and system suspend
9996 06:03:03.099644 INFO: BL31: Preparing for EL3 exit to normal world
9997 06:03:03.103037 INFO: Entry point address = 0x80000000
9998 06:03:03.103464 INFO: SPSR = 0x8
9999 06:03:03.110119
10000 06:03:03.110538
10001 06:03:03.110869
10002 06:03:03.113509 Starting depthcharge on Spherion...
10003 06:03:03.113933
10004 06:03:03.114266 Wipe memory regions:
10005 06:03:03.114576
10006 06:03:03.117179 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10007 06:03:03.117697 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10008 06:03:03.118102 Setting prompt string to ['asurada:']
10009 06:03:03.118477 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10010 06:03:03.119201 [0x00000040000000, 0x00000054600000)
10011 06:03:03.239061
10012 06:03:03.239551 [0x00000054660000, 0x00000080000000)
10013 06:03:03.499058
10014 06:03:03.499222 [0x000000821a7280, 0x000000ffe64000)
10015 06:03:04.244162
10016 06:03:04.244686 [0x00000100000000, 0x00000240000000)
10017 06:03:06.134927
10018 06:03:06.138048 Initializing XHCI USB controller at 0x11200000.
10019 06:03:07.176112
10020 06:03:07.179139 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10021 06:03:07.179688
10022 06:03:07.180167
10023 06:03:07.180707
10024 06:03:07.181664 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10026 06:03:07.283087 asurada: tftpboot 192.168.201.1 12379462/tftp-deploy-6shl4gkr/kernel/image.itb 12379462/tftp-deploy-6shl4gkr/kernel/cmdline
10027 06:03:07.283671 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10028 06:03:07.284107 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10029 06:03:07.288682 tftpboot 192.168.201.1 12379462/tftp-deploy-6shl4gkr/kernel/image.ittp-deploy-6shl4gkr/kernel/cmdline
10030 06:03:07.289226
10031 06:03:07.289720 Waiting for link
10032 06:03:07.449405
10033 06:03:07.449860 R8152: Initializing
10034 06:03:07.450193
10035 06:03:07.452638 Version 9 (ocp_data = 6010)
10036 06:03:07.453035
10037 06:03:07.455643 R8152: Done initializing
10038 06:03:07.456145
10039 06:03:07.456711 Adding net device
10040 06:03:09.397052
10041 06:03:09.397197 done.
10042 06:03:09.397266
10043 06:03:09.397359 MAC: 00:e0:4c:78:7a:aa
10044 06:03:09.397447
10045 06:03:09.400281 Sending DHCP discover... done.
10046 06:03:09.400408
10047 06:03:09.403758 Waiting for reply... done.
10048 06:03:09.403841
10049 06:03:09.407443 Sending DHCP request... done.
10050 06:03:09.407529
10051 06:03:09.407592 Waiting for reply... done.
10052 06:03:09.407651
10053 06:03:09.410375 My ip is 192.168.201.12
10054 06:03:09.410444
10055 06:03:09.413524 The DHCP server ip is 192.168.201.1
10056 06:03:09.413596
10057 06:03:09.416738 TFTP server IP predefined by user: 192.168.201.1
10058 06:03:09.416809
10059 06:03:09.423413 Bootfile predefined by user: 12379462/tftp-deploy-6shl4gkr/kernel/image.itb
10060 06:03:09.423497
10061 06:03:09.426941 Sending tftp read request... done.
10062 06:03:09.427024
10063 06:03:09.430414 Waiting for the transfer...
10064 06:03:09.430497
10065 06:03:09.698159 00000000 ################################################################
10066 06:03:09.698306
10067 06:03:09.957657 00080000 ################################################################
10068 06:03:09.957808
10069 06:03:10.214789 00100000 ################################################################
10070 06:03:10.214963
10071 06:03:10.467784 00180000 ################################################################
10072 06:03:10.467925
10073 06:03:10.720814 00200000 ################################################################
10074 06:03:10.720961
10075 06:03:10.979078 00280000 ################################################################
10076 06:03:10.979227
10077 06:03:11.230084 00300000 ################################################################
10078 06:03:11.230229
10079 06:03:11.479261 00380000 ################################################################
10080 06:03:11.479414
10081 06:03:11.725282 00400000 ################################################################
10082 06:03:11.725439
10083 06:03:11.972021 00480000 ################################################################
10084 06:03:11.972166
10085 06:03:12.216103 00500000 ################################################################
10086 06:03:12.216255
10087 06:03:12.464437 00580000 ################################################################
10088 06:03:12.464645
10089 06:03:12.725045 00600000 ################################################################
10090 06:03:12.725190
10091 06:03:12.990512 00680000 ################################################################
10092 06:03:12.990644
10093 06:03:13.255775 00700000 ################################################################
10094 06:03:13.255914
10095 06:03:13.507778 00780000 ################################################################
10096 06:03:13.507926
10097 06:03:13.754671 00800000 ################################################################
10098 06:03:13.754833
10099 06:03:14.009216 00880000 ################################################################
10100 06:03:14.009348
10101 06:03:14.274928 00900000 ################################################################
10102 06:03:14.275092
10103 06:03:14.534665 00980000 ################################################################
10104 06:03:14.534833
10105 06:03:14.793304 00a00000 ################################################################
10106 06:03:14.793443
10107 06:03:15.058035 00a80000 ################################################################
10108 06:03:15.058199
10109 06:03:15.308486 00b00000 ################################################################
10110 06:03:15.308636
10111 06:03:15.568239 00b80000 ################################################################
10112 06:03:15.568428
10113 06:03:15.826900 00c00000 ################################################################
10114 06:03:15.827043
10115 06:03:16.088375 00c80000 ################################################################
10116 06:03:16.088539
10117 06:03:16.346637 00d00000 ################################################################
10118 06:03:16.346815
10119 06:03:16.615371 00d80000 ################################################################
10120 06:03:16.615512
10121 06:03:16.891529 00e00000 ################################################################
10122 06:03:16.891670
10123 06:03:17.162597 00e80000 ################################################################
10124 06:03:17.162737
10125 06:03:17.445110 00f00000 ################################################################
10126 06:03:17.445249
10127 06:03:17.716589 00f80000 ################################################################
10128 06:03:17.716736
10129 06:03:17.985332 01000000 ################################################################
10130 06:03:17.985465
10131 06:03:18.255707 01080000 ################################################################
10132 06:03:18.255836
10133 06:03:18.521113 01100000 ################################################################
10134 06:03:18.521246
10135 06:03:18.780762 01180000 ################################################################
10136 06:03:18.780893
10137 06:03:19.045410 01200000 ################################################################
10138 06:03:19.045551
10139 06:03:19.319633 01280000 ################################################################
10140 06:03:19.319805
10141 06:03:19.585050 01300000 ################################################################
10142 06:03:19.585183
10143 06:03:19.843568 01380000 ################################################################
10144 06:03:19.843726
10145 06:03:20.107185 01400000 ################################################################
10146 06:03:20.107323
10147 06:03:20.375811 01480000 ################################################################
10148 06:03:20.375946
10149 06:03:20.654159 01500000 ################################################################
10150 06:03:20.654290
10151 06:03:20.926087 01580000 ################################################################
10152 06:03:20.926217
10153 06:03:21.205936 01600000 ################################################################
10154 06:03:21.206113
10155 06:03:21.492901 01680000 ################################################################
10156 06:03:21.493033
10157 06:03:21.754001 01700000 ################################################################
10158 06:03:21.754135
10159 06:03:22.040126 01780000 ################################################################
10160 06:03:22.040265
10161 06:03:22.311841 01800000 ################################################################
10162 06:03:22.311976
10163 06:03:22.577195 01880000 ################################################################
10164 06:03:22.577340
10165 06:03:22.848163 01900000 ################################################################
10166 06:03:22.848306
10167 06:03:23.155281 01980000 ################################################################
10168 06:03:23.155420
10169 06:03:23.441800 01a00000 ################################################################
10170 06:03:23.441938
10171 06:03:23.716969 01a80000 ################################################################
10172 06:03:23.717102
10173 06:03:23.983894 01b00000 ################################################################
10174 06:03:23.984040
10175 06:03:24.241070 01b80000 ################################################################
10176 06:03:24.241200
10177 06:03:24.510549 01c00000 ################################################################
10178 06:03:24.510693
10179 06:03:24.778865 01c80000 ################################################################
10180 06:03:24.778998
10181 06:03:25.028131 01d00000 ################################################################
10182 06:03:25.028273
10183 06:03:25.276191 01d80000 ################################################################
10184 06:03:25.276389
10185 06:03:25.546641 01e00000 ################################################################
10186 06:03:25.546781
10187 06:03:25.808921 01e80000 ################################################################
10188 06:03:25.809069
10189 06:03:26.081892 01f00000 ################################################################
10190 06:03:26.082033
10191 06:03:26.346637 01f80000 ################################################################
10192 06:03:26.346798
10193 06:03:26.604571 02000000 ################################################################
10194 06:03:26.604727
10195 06:03:26.877094 02080000 ################################################################
10196 06:03:26.877241
10197 06:03:27.144582 02100000 ################################################################
10198 06:03:27.144723
10199 06:03:27.409532 02180000 ################################################################
10200 06:03:27.409665
10201 06:03:27.684557 02200000 ################################################################
10202 06:03:27.684702
10203 06:03:27.962988 02280000 ################################################################
10204 06:03:27.963127
10205 06:03:28.245169 02300000 ################################################################
10206 06:03:28.245307
10207 06:03:28.499334 02380000 ################################################################
10208 06:03:28.499471
10209 06:03:28.763491 02400000 ################################################################
10210 06:03:28.763630
10211 06:03:29.018478 02480000 ################################################################
10212 06:03:29.018610
10213 06:03:29.286264 02500000 ################################################################
10214 06:03:29.286455
10215 06:03:29.549063 02580000 ################################################################
10216 06:03:29.549274
10217 06:03:29.816974 02600000 ################################################################
10218 06:03:29.817130
10219 06:03:30.077156 02680000 ################################################################
10220 06:03:30.077329
10221 06:03:30.344023 02700000 ################################################################
10222 06:03:30.344170
10223 06:03:30.602590 02780000 ################################################################
10224 06:03:30.602758
10225 06:03:30.854479 02800000 ################################################################
10226 06:03:30.854623
10227 06:03:31.126354 02880000 ################################################################
10228 06:03:31.126555
10229 06:03:31.401010 02900000 ################################################################
10230 06:03:31.401289
10231 06:03:31.672974 02980000 ################################################################
10232 06:03:31.673136
10233 06:03:31.949901 02a00000 ################################################################
10234 06:03:31.950055
10235 06:03:32.222150 02a80000 ################################################################
10236 06:03:32.222287
10237 06:03:32.501791 02b00000 ################################################################
10238 06:03:32.502015
10239 06:03:32.773863 02b80000 ################################################################
10240 06:03:32.774015
10241 06:03:33.029743 02c00000 ################################################################
10242 06:03:33.029908
10243 06:03:33.286544 02c80000 ################################################################
10244 06:03:33.286682
10245 06:03:33.548296 02d00000 ################################################################
10246 06:03:33.548455
10247 06:03:33.807834 02d80000 ################################################################
10248 06:03:33.807973
10249 06:03:34.072670 02e00000 ################################################################
10250 06:03:34.072892
10251 06:03:34.319930 02e80000 ################################################################
10252 06:03:34.320109
10253 06:03:34.586147 02f00000 ################################################################
10254 06:03:34.586327
10255 06:03:34.837516 02f80000 ################################################################
10256 06:03:34.837683
10257 06:03:35.096672 03000000 ################################################################
10258 06:03:35.096857
10259 06:03:35.113138 03080000 ##### done.
10260 06:03:35.113232
10261 06:03:35.116826 The bootfile was 50888974 bytes long.
10262 06:03:35.116915
10263 06:03:35.119629 Sending tftp read request... done.
10264 06:03:35.119710
10265 06:03:35.119774 Waiting for the transfer...
10266 06:03:35.119843
10267 06:03:35.123115 00000000 # done.
10268 06:03:35.123198
10269 06:03:35.129858 Command line loaded dynamically from TFTP file: 12379462/tftp-deploy-6shl4gkr/kernel/cmdline
10270 06:03:35.129944
10271 06:03:35.143112 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10272 06:03:35.143201
10273 06:03:35.146711 Loading FIT.
10274 06:03:35.146795
10275 06:03:35.149518 Image ramdisk-1 has 39357832 bytes.
10276 06:03:35.149600
10277 06:03:35.149663 Image fdt-1 has 47278 bytes.
10278 06:03:35.152997
10279 06:03:35.153078 Image kernel-1 has 11481830 bytes.
10280 06:03:35.153141
10281 06:03:35.163491 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10282 06:03:35.163597
10283 06:03:35.179911 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10284 06:03:35.180009
10285 06:03:35.186694 Choosing best match conf-1 for compat google,spherion-rev2.
10286 06:03:35.190425
10287 06:03:35.195147 Connected to device vid:did:rid of 1ae0:0028:00
10288 06:03:35.203450
10289 06:03:35.206481 tpm_get_response: command 0x17b, return code 0x0
10290 06:03:35.206563
10291 06:03:35.209646 ec_init: CrosEC protocol v3 supported (256, 248)
10292 06:03:35.213909
10293 06:03:35.216931 tpm_cleanup: add release locality here.
10294 06:03:35.217013
10295 06:03:35.217077 Shutting down all USB controllers.
10296 06:03:35.220585
10297 06:03:35.220665 Removing current net device
10298 06:03:35.220730
10299 06:03:35.227210 Exiting depthcharge with code 4 at timestamp: 61367031
10300 06:03:35.227293
10301 06:03:35.230367 LZMA decompressing kernel-1 to 0x821a6718
10302 06:03:35.230448
10303 06:03:35.234044 LZMA decompressing kernel-1 to 0x40000000
10304 06:03:36.670715
10305 06:03:36.670847 jumping to kernel
10306 06:03:36.671373 end: 2.2.4 bootloader-commands (duration 00:00:34) [common]
10307 06:03:36.671482 start: 2.2.5 auto-login-action (timeout 00:03:52) [common]
10308 06:03:36.671561 Setting prompt string to ['Linux version [0-9]']
10309 06:03:36.671635 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10310 06:03:36.671705 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10311 06:03:36.752813
10312 06:03:36.756021 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10313 06:03:36.759792 start: 2.2.5.1 login-action (timeout 00:03:52) [common]
10314 06:03:36.759898 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10315 06:03:36.759997 Setting prompt string to []
10316 06:03:36.760112 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10317 06:03:36.760222 Using line separator: #'\n'#
10318 06:03:36.760334 No login prompt set.
10319 06:03:36.760414 Parsing kernel messages
10320 06:03:36.760469 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10321 06:03:36.760570 [login-action] Waiting for messages, (timeout 00:03:52)
10322 06:03:36.779677 [ 0.000000] Linux version 6.1.67-cip12 (KernelCI@build-j59664-arm64-gcc-10-defconfig-arm64-chromebook-fgc24) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023
10323 06:03:36.783322 [ 0.000000] random: crng init done
10324 06:03:36.789458 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10325 06:03:36.792963 [ 0.000000] efi: UEFI not found.
10326 06:03:36.799138 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10327 06:03:36.806152 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10328 06:03:36.815714 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10329 06:03:36.826038 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10330 06:03:36.832244 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10331 06:03:36.835995 [ 0.000000] printk: bootconsole [mtk8250] enabled
10332 06:03:36.844752 [ 0.000000] NUMA: No NUMA configuration found
10333 06:03:36.851531 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10334 06:03:36.858608 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10335 06:03:36.858750 [ 0.000000] Zone ranges:
10336 06:03:36.864845 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10337 06:03:36.868231 [ 0.000000] DMA32 empty
10338 06:03:36.874622 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10339 06:03:36.877912 [ 0.000000] Movable zone start for each node
10340 06:03:36.881086 [ 0.000000] Early memory node ranges
10341 06:03:36.888161 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10342 06:03:36.894656 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10343 06:03:36.901532 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10344 06:03:36.907918 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10345 06:03:36.914887 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10346 06:03:36.921169 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10347 06:03:36.977077 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10348 06:03:36.984006 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10349 06:03:36.990739 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10350 06:03:36.994070 [ 0.000000] psci: probing for conduit method from DT.
10351 06:03:37.000609 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10352 06:03:37.003739 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10353 06:03:37.010733 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10354 06:03:37.014144 [ 0.000000] psci: SMC Calling Convention v1.2
10355 06:03:37.020864 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10356 06:03:37.023700 [ 0.000000] Detected VIPT I-cache on CPU0
10357 06:03:37.030514 [ 0.000000] CPU features: detected: GIC system register CPU interface
10358 06:03:37.037069 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10359 06:03:37.043877 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10360 06:03:37.050474 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10361 06:03:37.056841 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10362 06:03:37.063635 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10363 06:03:37.070278 [ 0.000000] alternatives: applying boot alternatives
10364 06:03:37.073490 [ 0.000000] Fallback order for Node 0: 0
10365 06:03:37.080258 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10366 06:03:37.083645 [ 0.000000] Policy zone: Normal
10367 06:03:37.099977 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10368 06:03:37.110164 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10369 06:03:37.121684 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10370 06:03:37.131311 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10371 06:03:37.138292 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10372 06:03:37.140996 <6>[ 0.000000] software IO TLB: area num 8.
10373 06:03:37.197442 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10374 06:03:37.347201 <6>[ 0.000000] Memory: 7930284K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 422484K reserved, 32768K cma-reserved)
10375 06:03:37.353368 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10376 06:03:37.360519 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10377 06:03:37.363926 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10378 06:03:37.370169 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10379 06:03:37.376664 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10380 06:03:37.380005 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10381 06:03:37.389898 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10382 06:03:37.396891 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10383 06:03:37.400143 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10384 06:03:37.407509 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10385 06:03:37.411386 <6>[ 0.000000] GICv3: 608 SPIs implemented
10386 06:03:37.417640 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10387 06:03:37.420934 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10388 06:03:37.424533 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10389 06:03:37.434352 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10390 06:03:37.444913 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10391 06:03:37.457980 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10392 06:03:37.464300 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10393 06:03:37.473440 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10394 06:03:37.486714 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10395 06:03:37.492939 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10396 06:03:37.500052 <6>[ 0.009227] Console: colour dummy device 80x25
10397 06:03:37.509786 <6>[ 0.013982] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10398 06:03:37.516719 <6>[ 0.024488] pid_max: default: 32768 minimum: 301
10399 06:03:37.520190 <6>[ 0.029358] LSM: Security Framework initializing
10400 06:03:37.526402 <6>[ 0.034326] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10401 06:03:37.536445 <6>[ 0.042141] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10402 06:03:37.542821 <6>[ 0.051551] cblist_init_generic: Setting adjustable number of callback queues.
10403 06:03:37.549782 <6>[ 0.058994] cblist_init_generic: Setting shift to 3 and lim to 1.
10404 06:03:37.560003 <6>[ 0.065333] cblist_init_generic: Setting adjustable number of callback queues.
10405 06:03:37.563127 <6>[ 0.072760] cblist_init_generic: Setting shift to 3 and lim to 1.
10406 06:03:37.569925 <6>[ 0.079163] rcu: Hierarchical SRCU implementation.
10407 06:03:37.576174 <6>[ 0.084210] rcu: Max phase no-delay instances is 1000.
10408 06:03:37.582820 <6>[ 0.091233] EFI services will not be available.
10409 06:03:37.586318 <6>[ 0.096188] smp: Bringing up secondary CPUs ...
10410 06:03:37.594159 <6>[ 0.101239] Detected VIPT I-cache on CPU1
10411 06:03:37.600809 <6>[ 0.101307] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10412 06:03:37.607239 <6>[ 0.101338] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10413 06:03:37.610593 <6>[ 0.101671] Detected VIPT I-cache on CPU2
10414 06:03:37.617477 <6>[ 0.101720] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10415 06:03:37.624202 <6>[ 0.101736] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10416 06:03:37.630545 <6>[ 0.101990] Detected VIPT I-cache on CPU3
10417 06:03:37.637552 <6>[ 0.102036] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10418 06:03:37.643857 <6>[ 0.102050] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10419 06:03:37.647095 <6>[ 0.102350] CPU features: detected: Spectre-v4
10420 06:03:37.654165 <6>[ 0.102357] CPU features: detected: Spectre-BHB
10421 06:03:37.657414 <6>[ 0.102362] Detected PIPT I-cache on CPU4
10422 06:03:37.664011 <6>[ 0.102417] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10423 06:03:37.670991 <6>[ 0.102434] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10424 06:03:37.677326 <6>[ 0.102728] Detected PIPT I-cache on CPU5
10425 06:03:37.684303 <6>[ 0.102791] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10426 06:03:37.690579 <6>[ 0.102808] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10427 06:03:37.693873 <6>[ 0.103089] Detected PIPT I-cache on CPU6
10428 06:03:37.700323 <6>[ 0.103153] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10429 06:03:37.707015 <6>[ 0.103169] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10430 06:03:37.713830 <6>[ 0.103468] Detected PIPT I-cache on CPU7
10431 06:03:37.720560 <6>[ 0.103534] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10432 06:03:37.726767 <6>[ 0.103550] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10433 06:03:37.730297 <6>[ 0.103597] smp: Brought up 1 node, 8 CPUs
10434 06:03:37.736590 <6>[ 0.244987] SMP: Total of 8 processors activated.
10435 06:03:37.740143 <6>[ 0.249908] CPU features: detected: 32-bit EL0 Support
10436 06:03:37.749944 <6>[ 0.255271] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10437 06:03:37.756817 <6>[ 0.264072] CPU features: detected: Common not Private translations
10438 06:03:37.760100 <6>[ 0.270548] CPU features: detected: CRC32 instructions
10439 06:03:37.766936 <6>[ 0.275899] CPU features: detected: RCpc load-acquire (LDAPR)
10440 06:03:37.773026 <6>[ 0.281859] CPU features: detected: LSE atomic instructions
10441 06:03:37.779943 <6>[ 0.287641] CPU features: detected: Privileged Access Never
10442 06:03:37.783043 <6>[ 0.293421] CPU features: detected: RAS Extension Support
10443 06:03:37.793181 <6>[ 0.299029] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10444 06:03:37.796015 <6>[ 0.306247] CPU: All CPU(s) started at EL2
10445 06:03:37.803073 <6>[ 0.310563] alternatives: applying system-wide alternatives
10446 06:03:37.811977 <6>[ 0.321318] devtmpfs: initialized
10447 06:03:37.824204 <6>[ 0.330296] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10448 06:03:37.834396 <6>[ 0.340261] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10449 06:03:37.841078 <6>[ 0.348509] pinctrl core: initialized pinctrl subsystem
10450 06:03:37.844440 <6>[ 0.355176] DMI not present or invalid.
10451 06:03:37.850866 <6>[ 0.359589] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10452 06:03:37.860685 <6>[ 0.366463] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10453 06:03:37.867414 <6>[ 0.374049] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10454 06:03:37.877686 <6>[ 0.382280] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10455 06:03:37.880584 <6>[ 0.390522] audit: initializing netlink subsys (disabled)
10456 06:03:37.890589 <5>[ 0.396217] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10457 06:03:37.897153 <6>[ 0.396922] thermal_sys: Registered thermal governor 'step_wise'
10458 06:03:37.903942 <6>[ 0.404183] thermal_sys: Registered thermal governor 'power_allocator'
10459 06:03:37.906780 <6>[ 0.410440] cpuidle: using governor menu
10460 06:03:37.913983 <6>[ 0.421407] NET: Registered PF_QIPCRTR protocol family
10461 06:03:37.920329 <6>[ 0.426881] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10462 06:03:37.926868 <6>[ 0.433984] ASID allocator initialised with 32768 entries
10463 06:03:37.930198 <6>[ 0.440524] Serial: AMBA PL011 UART driver
10464 06:03:37.939830 <4>[ 0.449283] Trying to register duplicate clock ID: 134
10465 06:03:37.995731 <6>[ 0.508643] KASLR enabled
10466 06:03:38.010689 <6>[ 0.516416] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10467 06:03:38.017091 <6>[ 0.523430] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10468 06:03:38.023463 <6>[ 0.529919] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10469 06:03:38.030440 <6>[ 0.536926] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10470 06:03:38.036790 <6>[ 0.543415] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10471 06:03:38.043594 <6>[ 0.550421] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10472 06:03:38.050124 <6>[ 0.556910] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10473 06:03:38.056670 <6>[ 0.563915] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10474 06:03:38.060027 <6>[ 0.571435] ACPI: Interpreter disabled.
10475 06:03:38.068382 <6>[ 0.577859] iommu: Default domain type: Translated
10476 06:03:38.075175 <6>[ 0.582972] iommu: DMA domain TLB invalidation policy: strict mode
10477 06:03:38.078469 <5>[ 0.589634] SCSI subsystem initialized
10478 06:03:38.085117 <6>[ 0.593798] usbcore: registered new interface driver usbfs
10479 06:03:38.091616 <6>[ 0.599530] usbcore: registered new interface driver hub
10480 06:03:38.094760 <6>[ 0.605083] usbcore: registered new device driver usb
10481 06:03:38.101754 <6>[ 0.611187] pps_core: LinuxPPS API ver. 1 registered
10482 06:03:38.111710 <6>[ 0.616381] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10483 06:03:38.115144 <6>[ 0.625728] PTP clock support registered
10484 06:03:38.118267 <6>[ 0.629969] EDAC MC: Ver: 3.0.0
10485 06:03:38.125970 <6>[ 0.635125] FPGA manager framework
10486 06:03:38.132196 <6>[ 0.638805] Advanced Linux Sound Architecture Driver Initialized.
10487 06:03:38.135789 <6>[ 0.645583] vgaarb: loaded
10488 06:03:38.142148 <6>[ 0.648741] clocksource: Switched to clocksource arch_sys_counter
10489 06:03:38.145567 <5>[ 0.655178] VFS: Disk quotas dquot_6.6.0
10490 06:03:38.152409 <6>[ 0.659365] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10491 06:03:38.155671 <6>[ 0.666556] pnp: PnP ACPI: disabled
10492 06:03:38.163709 <6>[ 0.673262] NET: Registered PF_INET protocol family
10493 06:03:38.173520 <6>[ 0.678853] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10494 06:03:38.185448 <6>[ 0.691164] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10495 06:03:38.195327 <6>[ 0.699977] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10496 06:03:38.201467 <6>[ 0.707945] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10497 06:03:38.208521 <6>[ 0.716645] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10498 06:03:38.220094 <6>[ 0.726370] TCP: Hash tables configured (established 65536 bind 65536)
10499 06:03:38.226638 <6>[ 0.733231] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10500 06:03:38.233551 <6>[ 0.740431] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10501 06:03:38.239766 <6>[ 0.748130] NET: Registered PF_UNIX/PF_LOCAL protocol family
10502 06:03:38.246552 <6>[ 0.754293] RPC: Registered named UNIX socket transport module.
10503 06:03:38.250080 <6>[ 0.760447] RPC: Registered udp transport module.
10504 06:03:38.256984 <6>[ 0.765379] RPC: Registered tcp transport module.
10505 06:03:38.263277 <6>[ 0.770310] RPC: Registered tcp NFSv4.1 backchannel transport module.
10506 06:03:38.266569 <6>[ 0.776976] PCI: CLS 0 bytes, default 64
10507 06:03:38.269863 <6>[ 0.781303] Unpacking initramfs...
10508 06:03:38.294587 <6>[ 0.800853] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10509 06:03:38.304402 <6>[ 0.809505] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10510 06:03:38.307891 <6>[ 0.818361] kvm [1]: IPA Size Limit: 40 bits
10511 06:03:38.315001 <6>[ 0.822890] kvm [1]: GICv3: no GICV resource entry
10512 06:03:38.317716 <6>[ 0.827912] kvm [1]: disabling GICv2 emulation
10513 06:03:38.324772 <6>[ 0.832598] kvm [1]: GIC system register CPU interface enabled
10514 06:03:38.328181 <6>[ 0.838758] kvm [1]: vgic interrupt IRQ18
10515 06:03:38.334844 <6>[ 0.843124] kvm [1]: VHE mode initialized successfully
10516 06:03:38.341327 <5>[ 0.849516] Initialise system trusted keyrings
10517 06:03:38.348049 <6>[ 0.854346] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10518 06:03:38.355188 <6>[ 0.864400] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10519 06:03:38.362049 <5>[ 0.870864] NFS: Registering the id_resolver key type
10520 06:03:38.364905 <5>[ 0.876174] Key type id_resolver registered
10521 06:03:38.371390 <5>[ 0.880591] Key type id_legacy registered
10522 06:03:38.378646 <6>[ 0.884869] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10523 06:03:38.384773 <6>[ 0.891796] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10524 06:03:38.391656 <6>[ 0.899527] 9p: Installing v9fs 9p2000 file system support
10525 06:03:38.429040 <5>[ 0.938060] Key type asymmetric registered
10526 06:03:38.431930 <5>[ 0.942392] Asymmetric key parser 'x509' registered
10527 06:03:38.442146 <6>[ 0.947525] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10528 06:03:38.445549 <6>[ 0.955141] io scheduler mq-deadline registered
10529 06:03:38.448283 <6>[ 0.959917] io scheduler kyber registered
10530 06:03:38.467584 <6>[ 0.976750] EINJ: ACPI disabled.
10531 06:03:38.499277 <4>[ 1.002141] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10532 06:03:38.509128 <4>[ 1.012755] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10533 06:03:38.524022 <6>[ 1.033336] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10534 06:03:38.531591 <6>[ 1.041335] printk: console [ttyS0] disabled
10535 06:03:38.559663 <6>[ 1.065979] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10536 06:03:38.566482 <6>[ 1.075470] printk: console [ttyS0] enabled
10537 06:03:38.569759 <6>[ 1.075470] printk: console [ttyS0] enabled
10538 06:03:38.576530 <6>[ 1.084362] printk: bootconsole [mtk8250] disabled
10539 06:03:38.579985 <6>[ 1.084362] printk: bootconsole [mtk8250] disabled
10540 06:03:38.586284 <6>[ 1.095406] SuperH (H)SCI(F) driver initialized
10541 06:03:38.589757 <6>[ 1.100682] msm_serial: driver initialized
10542 06:03:38.603406 <6>[ 1.109607] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10543 06:03:38.613773 <6>[ 1.118152] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10544 06:03:38.620165 <6>[ 1.126693] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10545 06:03:38.629875 <6>[ 1.135322] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10546 06:03:38.636851 <6>[ 1.144030] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10547 06:03:38.646602 <6>[ 1.152752] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10548 06:03:38.656816 <6>[ 1.161292] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10549 06:03:38.663513 <6>[ 1.170086] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10550 06:03:38.673113 <6>[ 1.178629] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10551 06:03:38.684500 <6>[ 1.194046] loop: module loaded
10552 06:03:38.691184 <6>[ 1.199945] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10553 06:03:38.713891 <4>[ 1.223454] mtk-pmic-keys: Failed to locate of_node [id: -1]
10554 06:03:38.720939 <6>[ 1.230463] megasas: 07.719.03.00-rc1
10555 06:03:38.730993 <6>[ 1.240255] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10556 06:03:38.742406 <6>[ 1.252119] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10557 06:03:38.759743 <6>[ 1.268826] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10558 06:03:38.816023 <6>[ 1.318984] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10559 06:03:39.872233 <6>[ 2.381777] Freeing initrd memory: 38432K
10560 06:03:39.882644 <6>[ 2.392140] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10561 06:03:39.893605 <6>[ 2.403243] tun: Universal TUN/TAP device driver, 1.6
10562 06:03:39.897103 <6>[ 2.409333] thunder_xcv, ver 1.0
10563 06:03:39.900037 <6>[ 2.412837] thunder_bgx, ver 1.0
10564 06:03:39.903659 <6>[ 2.416327] nicpf, ver 1.0
10565 06:03:39.913889 <6>[ 2.420352] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10566 06:03:39.917397 <6>[ 2.427828] hns3: Copyright (c) 2017 Huawei Corporation.
10567 06:03:39.920738 <6>[ 2.433415] hclge is initializing
10568 06:03:39.927516 <6>[ 2.436997] e1000: Intel(R) PRO/1000 Network Driver
10569 06:03:39.934391 <6>[ 2.442127] e1000: Copyright (c) 1999-2006 Intel Corporation.
10570 06:03:39.937371 <6>[ 2.448140] e1000e: Intel(R) PRO/1000 Network Driver
10571 06:03:39.944228 <6>[ 2.453355] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10572 06:03:39.950637 <6>[ 2.459551] igb: Intel(R) Gigabit Ethernet Network Driver
10573 06:03:39.957736 <6>[ 2.465200] igb: Copyright (c) 2007-2014 Intel Corporation.
10574 06:03:39.964412 <6>[ 2.471038] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10575 06:03:39.970835 <6>[ 2.477555] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10576 06:03:39.974208 <6>[ 2.484017] sky2: driver version 1.30
10577 06:03:39.980496 <6>[ 2.489020] VFIO - User Level meta-driver version: 0.3
10578 06:03:39.987338 <6>[ 2.497308] usbcore: registered new interface driver usb-storage
10579 06:03:39.994562 <6>[ 2.503750] usbcore: registered new device driver onboard-usb-hub
10580 06:03:40.003712 <6>[ 2.512952] mt6397-rtc mt6359-rtc: registered as rtc0
10581 06:03:40.013525 <6>[ 2.518414] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-25T06:01:05 UTC (1703484065)
10582 06:03:40.016739 <6>[ 2.527978] i2c_dev: i2c /dev entries driver
10583 06:03:40.033318 <6>[ 2.539839] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10584 06:03:40.053088 <6>[ 2.562853] cpu cpu0: EM: created perf domain
10585 06:03:40.056239 <6>[ 2.567797] cpu cpu4: EM: created perf domain
10586 06:03:40.063634 <6>[ 2.573421] sdhci: Secure Digital Host Controller Interface driver
10587 06:03:40.070434 <6>[ 2.579853] sdhci: Copyright(c) Pierre Ossman
10588 06:03:40.076997 <6>[ 2.584807] Synopsys Designware Multimedia Card Interface Driver
10589 06:03:40.083608 <6>[ 2.591457] sdhci-pltfm: SDHCI platform and OF driver helper
10590 06:03:40.087011 <6>[ 2.591501] mmc0: CQHCI version 5.10
10591 06:03:40.093814 <6>[ 2.601689] ledtrig-cpu: registered to indicate activity on CPUs
10592 06:03:40.100247 <6>[ 2.608755] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10593 06:03:40.107295 <6>[ 2.615824] usbcore: registered new interface driver usbhid
10594 06:03:40.110592 <6>[ 2.621646] usbhid: USB HID core driver
10595 06:03:40.117044 <6>[ 2.625850] spi_master spi0: will run message pump with realtime priority
10596 06:03:40.161845 <6>[ 2.664508] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10597 06:03:40.181304 <6>[ 2.680549] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10598 06:03:40.184397 <6>[ 2.694089] mmc0: Command Queue Engine enabled
10599 06:03:40.191079 <6>[ 2.698841] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10600 06:03:40.197448 <6>[ 2.706649] mmcblk0: mmc0:0001 DA4128 116 GiB
10601 06:03:40.204063 <6>[ 2.711491] cros-ec-spi spi0.0: Chrome EC device registered
10602 06:03:40.207236 <6>[ 2.715378] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10603 06:03:40.214547 <6>[ 2.724328] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10604 06:03:40.221392 <6>[ 2.730372] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10605 06:03:40.227690 <6>[ 2.736529] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10606 06:03:40.245046 <6>[ 2.751073] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10607 06:03:40.252511 <6>[ 2.761911] NET: Registered PF_PACKET protocol family
10608 06:03:40.255449 <6>[ 2.767309] 9pnet: Installing 9P2000 support
10609 06:03:40.262388 <5>[ 2.771874] Key type dns_resolver registered
10610 06:03:40.265703 <6>[ 2.776877] registered taskstats version 1
10611 06:03:40.271817 <5>[ 2.781268] Loading compiled-in X.509 certificates
10612 06:03:40.303613 <4>[ 2.806619] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10613 06:03:40.313775 <4>[ 2.817425] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10614 06:03:40.320235 <3>[ 2.827965] debugfs: File 'uA_load' in directory '/' already present!
10615 06:03:40.326890 <3>[ 2.834669] debugfs: File 'min_uV' in directory '/' already present!
10616 06:03:40.333444 <3>[ 2.841277] debugfs: File 'max_uV' in directory '/' already present!
10617 06:03:40.340568 <3>[ 2.847885] debugfs: File 'constraint_flags' in directory '/' already present!
10618 06:03:40.351338 <3>[ 2.857747] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10619 06:03:40.364327 <6>[ 2.873917] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10620 06:03:40.370818 <6>[ 2.880702] xhci-mtk 11200000.usb: xHCI Host Controller
10621 06:03:40.377454 <6>[ 2.886201] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10622 06:03:40.387858 <6>[ 2.894179] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10623 06:03:40.394935 <6>[ 2.903590] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10624 06:03:40.401308 <6>[ 2.909659] xhci-mtk 11200000.usb: xHCI Host Controller
10625 06:03:40.408059 <6>[ 2.915136] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10626 06:03:40.414486 <6>[ 2.922786] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10627 06:03:40.421530 <6>[ 2.930578] hub 1-0:1.0: USB hub found
10628 06:03:40.424170 <6>[ 2.934603] hub 1-0:1.0: 1 port detected
10629 06:03:40.431142 <6>[ 2.938892] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10630 06:03:40.437994 <6>[ 2.947603] hub 2-0:1.0: USB hub found
10631 06:03:40.441418 <6>[ 2.951625] hub 2-0:1.0: 1 port detected
10632 06:03:40.448884 <6>[ 2.958607] mtk-msdc 11f70000.mmc: Got CD GPIO
10633 06:03:40.461102 <6>[ 2.967526] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10634 06:03:40.467612 <6>[ 2.975558] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10635 06:03:40.477706 <4>[ 2.983485] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10636 06:03:40.487914 <6>[ 2.993029] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10637 06:03:40.494575 <6>[ 3.001106] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10638 06:03:40.500949 <6>[ 3.009256] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10639 06:03:40.510722 <6>[ 3.017213] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10640 06:03:40.517839 <6>[ 3.025036] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10641 06:03:40.527484 <6>[ 3.032854] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10642 06:03:40.537523 <6>[ 3.043270] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10643 06:03:40.543743 <6>[ 3.051635] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10644 06:03:40.553937 <6>[ 3.059975] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10645 06:03:40.560524 <6>[ 3.068313] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10646 06:03:40.570499 <6>[ 3.076651] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10647 06:03:40.580082 <6>[ 3.084990] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10648 06:03:40.586994 <6>[ 3.093329] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10649 06:03:40.596970 <6>[ 3.101667] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10650 06:03:40.603178 <6>[ 3.110005] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10651 06:03:40.612764 <6>[ 3.118344] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10652 06:03:40.619793 <6>[ 3.126689] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10653 06:03:40.629570 <6>[ 3.135028] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10654 06:03:40.636067 <6>[ 3.143367] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10655 06:03:40.646459 <6>[ 3.151706] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10656 06:03:40.652734 <6>[ 3.160046] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10657 06:03:40.659731 <6>[ 3.168796] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10658 06:03:40.666478 <6>[ 3.175939] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10659 06:03:40.672779 <6>[ 3.182688] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10660 06:03:40.683021 <6>[ 3.189443] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10661 06:03:40.689845 <6>[ 3.196376] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10662 06:03:40.696734 <6>[ 3.203216] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10663 06:03:40.705892 <6>[ 3.212342] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10664 06:03:40.716430 <6>[ 3.221461] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10665 06:03:40.725950 <6>[ 3.230760] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10666 06:03:40.736309 <6>[ 3.240231] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10667 06:03:40.742780 <6>[ 3.249714] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10668 06:03:40.752554 <6>[ 3.258835] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10669 06:03:40.762483 <6>[ 3.268304] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10670 06:03:40.773007 <6>[ 3.277425] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10671 06:03:40.782461 <6>[ 3.286718] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10672 06:03:40.792632 <6>[ 3.296879] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10673 06:03:40.802706 <6>[ 3.308951] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10674 06:03:40.830557 <6>[ 3.337279] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10675 06:03:40.859217 <6>[ 3.368518] hub 2-1:1.0: USB hub found
10676 06:03:40.862374 <6>[ 3.372994] hub 2-1:1.0: 3 ports detected
10677 06:03:40.870427 <6>[ 3.380406] hub 2-1:1.0: USB hub found
10678 06:03:40.874137 <6>[ 3.384827] hub 2-1:1.0: 3 ports detected
10679 06:03:40.982841 <6>[ 3.489046] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10680 06:03:41.137242 <6>[ 3.646553] hub 1-1:1.0: USB hub found
10681 06:03:41.139887 <6>[ 3.651033] hub 1-1:1.0: 4 ports detected
10682 06:03:41.149152 <6>[ 3.658779] hub 1-1:1.0: USB hub found
10683 06:03:41.152303 <6>[ 3.663084] hub 1-1:1.0: 4 ports detected
10684 06:03:41.218827 <6>[ 3.725237] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10685 06:03:41.474757 <6>[ 3.981049] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10686 06:03:41.606797 <6>[ 4.116542] hub 1-1.4:1.0: USB hub found
10687 06:03:41.610080 <6>[ 4.121209] hub 1-1.4:1.0: 2 ports detected
10688 06:03:41.620069 <6>[ 4.129585] hub 1-1.4:1.0: USB hub found
10689 06:03:41.622893 <6>[ 4.134178] hub 1-1.4:1.0: 2 ports detected
10690 06:03:41.922448 <6>[ 4.429016] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10691 06:03:42.114374 <6>[ 4.621063] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10692 06:03:53.084045 <6>[ 15.597975] ALSA device list:
10693 06:03:53.090247 <6>[ 15.601259] No soundcards found.
10694 06:03:53.097802 <6>[ 15.609130] Freeing unused kernel memory: 8448K
10695 06:03:53.101227 <6>[ 15.614184] Run /init as init process
10696 06:03:53.150278 <6>[ 15.661679] NET: Registered PF_INET6 protocol family
10697 06:03:53.157473 <6>[ 15.668335] Segment Routing with IPv6
10698 06:03:53.160792 <6>[ 15.672295] In-situ OAM (IOAM) with IPv6
10699 06:03:53.198564 <30>[ 15.689495] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10700 06:03:53.201280 <30>[ 15.713322] systemd[1]: Detected architecture arm64.
10701 06:03:53.201377
10702 06:03:53.208185 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10703 06:03:53.208274
10704 06:03:53.222048 <30>[ 15.733024] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10705 06:03:53.375238 <30>[ 15.883040] systemd[1]: Queued start job for default target Graphical Interface.
10706 06:03:53.414290 <30>[ 15.925518] systemd[1]: Created slice system-getty.slice.
10707 06:03:53.420762 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10708 06:03:53.438458 <30>[ 15.949449] systemd[1]: Created slice system-modprobe.slice.
10709 06:03:53.444750 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10710 06:03:53.467054 <30>[ 15.977980] systemd[1]: Created slice system-serial\x2dgetty.slice.
10711 06:03:53.476970 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10712 06:03:53.490020 <30>[ 16.001279] systemd[1]: Created slice User and Session Slice.
10713 06:03:53.497040 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10714 06:03:53.518021 <30>[ 16.025562] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10715 06:03:53.527234 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10716 06:03:53.545578 <30>[ 16.053550] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10717 06:03:53.552039 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10718 06:03:53.577066 <30>[ 16.081413] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10719 06:03:53.583516 <30>[ 16.093618] systemd[1]: Reached target Local Encrypted Volumes.
10720 06:03:53.589953 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10721 06:03:53.606385 <30>[ 16.117463] systemd[1]: Reached target Paths.
10722 06:03:53.609830 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10723 06:03:53.625606 <30>[ 16.136985] systemd[1]: Reached target Remote File Systems.
10724 06:03:53.632455 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10725 06:03:53.645602 <30>[ 16.156949] systemd[1]: Reached target Slices.
10726 06:03:53.649013 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10727 06:03:53.666104 <30>[ 16.176990] systemd[1]: Reached target Swap.
10728 06:03:53.669055 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10729 06:03:53.690051 <30>[ 16.197885] systemd[1]: Listening on initctl Compatibility Named Pipe.
10730 06:03:53.696408 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10731 06:03:53.711157 <30>[ 16.221793] systemd[1]: Listening on Journal Audit Socket.
10732 06:03:53.717418 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10733 06:03:53.734804 <30>[ 16.246105] systemd[1]: Listening on Journal Socket (/dev/log).
10734 06:03:53.741497 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10735 06:03:53.759197 <30>[ 16.270140] systemd[1]: Listening on Journal Socket.
10736 06:03:53.765444 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10737 06:03:53.782248 <30>[ 16.289648] systemd[1]: Listening on Network Service Netlink Socket.
10738 06:03:53.788160 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10739 06:03:53.803056 <30>[ 16.314171] systemd[1]: Listening on udev Control Socket.
10740 06:03:53.810002 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10741 06:03:53.827118 <30>[ 16.337994] systemd[1]: Listening on udev Kernel Socket.
10742 06:03:53.833816 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10743 06:03:53.874099 <30>[ 16.385106] systemd[1]: Mounting Huge Pages File System...
10744 06:03:53.880515 Mounting [0;1;39mHuge Pages File System[0m...
10745 06:03:53.895710 <30>[ 16.406641] systemd[1]: Mounting POSIX Message Queue File System...
10746 06:03:53.902522 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10747 06:03:53.919894 <30>[ 16.430961] systemd[1]: Mounting Kernel Debug File System...
10748 06:03:53.926723 Mounting [0;1;39mKernel Debug File System[0m...
10749 06:03:53.945564 <30>[ 16.453252] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10750 06:03:53.957419 <30>[ 16.465189] systemd[1]: Starting Create list of static device nodes for the current kernel...
10751 06:03:53.964230 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10752 06:03:53.986463 <30>[ 16.497271] systemd[1]: Starting Load Kernel Module configfs...
10753 06:03:53.992736 Starting [0;1;39mLoad Kernel Module configfs[0m...
10754 06:03:54.010305 <30>[ 16.521612] systemd[1]: Starting Load Kernel Module drm...
10755 06:03:54.017311 Starting [0;1;39mLoad Kernel Module drm[0m...
10756 06:03:54.033613 <30>[ 16.541413] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10757 06:03:54.048251 <30>[ 16.559417] systemd[1]: Starting Journal Service...
10758 06:03:54.054458 Starting [0;1;39mJournal Service[0m...
10759 06:03:54.074938 <30>[ 16.586154] systemd[1]: Starting Load Kernel Modules...
10760 06:03:54.081958 Starting [0;1;39mLoad Kernel Modules[0m...
10761 06:03:54.125996 <30>[ 16.633978] systemd[1]: Starting Remount Root and Kernel File Systems...
10762 06:03:54.132670 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10763 06:03:54.148094 <30>[ 16.659339] systemd[1]: Starting Coldplug All udev Devices...
10764 06:03:54.154968 Starting [0;1;39mColdplug All udev Devices[0m...
10765 06:03:54.172704 <30>[ 16.683890] systemd[1]: Started Journal Service.
10766 06:03:54.179183 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10767 06:03:54.195855 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10768 06:03:54.211104 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10769 06:03:54.227014 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10770 06:03:54.246793 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10771 06:03:54.264315 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10772 06:03:54.285020 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10773 06:03:54.303671 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10774 06:03:54.323946 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10775 06:03:54.338195 See 'systemctl status systemd-remount-fs.service' for details.
10776 06:03:54.395920 Mounting [0;1;39mKernel Configuration File System[0m...
10777 06:03:54.414731 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10778 06:03:54.428463 <46>[ 16.936546] systemd-journald[180]: Received client request to flush runtime journal.
10779 06:03:54.438383 Starting [0;1;39mLoad/Save Random Seed[0m...
10780 06:03:54.459467 Starting [0;1;39mApply Kernel Variables[0m...
10781 06:03:54.479057 Starting [0;1;39mCreate System Users[0m...
10782 06:03:54.496928 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10783 06:03:54.514504 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10784 06:03:54.535151 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10785 06:03:54.547815 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10786 06:03:54.563322 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10787 06:03:54.579470 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10788 06:03:54.622412 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10789 06:03:54.648207 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10790 06:03:54.666856 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10791 06:03:54.685734 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10792 06:03:54.730472 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10793 06:03:54.753232 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10794 06:03:54.770874 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10795 06:03:54.790603 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10796 06:03:54.812020 Starting [0;1;39mNetwork Service[0m...
10797 06:03:54.836877 Starting [0;1;39mNetwork Time Synchronization[0m...
10798 06:03:54.859446 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10799 06:03:54.876785 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10800 06:03:54.907158 Starting [0;1;39mNetwork Name Resolution[0m...
10801 06:03:54.934537 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10802 06:03:54.952782 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10803 06:03:55.010937 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m<6>[ 17.518876] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10804 06:03:55.017832 <6>[ 17.524976] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10805 06:03:55.017940 .
10806 06:03:55.029647 <6>[ 17.537386] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10807 06:03:55.039557 [[0;32m OK [<6>[ 17.546923] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10808 06:03:55.045749 0m] Reached targ<6>[ 17.549150] remoteproc remoteproc0: scp is available
10809 06:03:55.055919 <3>[ 17.562344] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10810 06:03:55.062857 et [0;1;39mSyst<6>[ 17.563691] remoteproc remoteproc0: powering up scp
10811 06:03:55.072718 em Time Set[0m.<3>[ 17.573669] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10812 06:03:55.072815
10813 06:03:55.078821 <6>[ 17.578109] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10814 06:03:55.085824 <6>[ 17.578180] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10815 06:03:55.092446 <3>[ 17.587650] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10816 06:03:55.102156 <4>[ 17.588818] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10817 06:03:55.109132 <4>[ 17.604828] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10818 06:03:55.116033 <3>[ 17.617283] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10819 06:03:55.125801 <3>[ 17.633075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10820 06:03:55.135777 [[0;32m OK [<6>[ 17.633789] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10821 06:03:55.142047 <3>[ 17.641623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10822 06:03:55.148757 0m] Reached targ<6>[ 17.649520] mc: Linux media interface: v0.10
10823 06:03:55.158433 et [0;1;39mSyst<3>[ 17.664352] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10824 06:03:55.168503 em Time Synchron<3>[ 17.673818] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10825 06:03:55.168600 ized[0m.
10826 06:03:55.175119 <4>[ 17.678676] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10827 06:03:55.181733 <4>[ 17.678676] Fallback method does not support PEC.
10828 06:03:55.188408 <3>[ 17.683482] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10829 06:03:55.198943 <3>[ 17.683608] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10830 06:03:55.206041 <3>[ 17.683615] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10831 06:03:55.212173 <6>[ 17.702418] usbcore: registered new interface driver r8152
10832 06:03:55.219305 <6>[ 17.704848] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10833 06:03:55.225973 <6>[ 17.704864] pci_bus 0000:00: root bus resource [bus 00-ff]
10834 06:03:55.232289 <6>[ 17.704870] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10835 06:03:55.241922 <6>[ 17.704875] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10836 06:03:55.248941 <6>[ 17.704910] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10837 06:03:55.255152 <6>[ 17.704931] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10838 06:03:55.262133 <6>[ 17.705016] pci 0000:00:00.0: supports D1 D2
10839 06:03:55.268811 <6>[ 17.705020] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10840 06:03:55.275201 <3>[ 17.706071] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10841 06:03:55.285387 <3>[ 17.706880] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10842 06:03:55.291693 <3>[ 17.715110] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 06:03:55.302027 <6>[ 17.715436] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10844 06:03:55.308341 <6>[ 17.719803] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10845 06:03:55.315537 <6>[ 17.719839] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10846 06:03:55.322235 <6>[ 17.719858] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10847 06:03:55.331908 <6>[ 17.719873] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10848 06:03:55.334689 <6>[ 17.719989] pci 0000:01:00.0: supports D1 D2
10849 06:03:55.341878 <6>[ 17.719991] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10850 06:03:55.348089 <3>[ 17.722266] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10851 06:03:55.357734 <3>[ 17.722274] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10852 06:03:55.364553 <3>[ 17.722280] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10853 06:03:55.374370 <3>[ 17.722284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10854 06:03:55.380957 <3>[ 17.723853] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10855 06:03:55.387777 <6>[ 17.728328] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10856 06:03:55.398100 <6>[ 17.735091] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10857 06:03:55.404198 <6>[ 17.735111] remoteproc remoteproc0: remote processor scp is now up
10858 06:03:55.411157 <6>[ 17.738687] videodev: Linux video capture interface: v2.00
10859 06:03:55.417642 <6>[ 17.745714] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10860 06:03:55.427484 <6>[ 17.748074] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10861 06:03:55.437285 <6>[ 17.898283] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10862 06:03:55.444184 <6>[ 17.905456] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10863 06:03:55.454297 <6>[ 17.906890] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10864 06:03:55.460610 <6>[ 17.908470] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10865 06:03:55.467379 <6>[ 17.914286] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10866 06:03:55.477061 <6>[ 17.920358] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10867 06:03:55.483989 <6>[ 17.926786] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10868 06:03:55.493886 <6>[ 17.933082] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10869 06:03:55.501036 <4>[ 17.952061] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10870 06:03:55.511311 <6>[ 17.952516] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10871 06:03:55.518069 <4>[ 17.960547] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10872 06:03:55.524814 <6>[ 17.968747] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10873 06:03:55.531625 <6>[ 17.968768] pci 0000:00:00.0: PCI bridge to [bus 01]
10874 06:03:55.539208 <6>[ 17.970677] usbcore: registered new interface driver cdc_ether
10875 06:03:55.542173 <6>[ 17.977788] usbcore: registered new interface driver r8153_ecm
10876 06:03:55.553060 <6>[ 17.984183] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10877 06:03:55.555771 <6>[ 17.984716] Bluetooth: Core ver 2.22
10878 06:03:55.559269 <6>[ 17.984796] NET: Registered PF_BLUETOOTH protocol family
10879 06:03:55.566181 <6>[ 17.984798] Bluetooth: HCI device and connection manager initialized
10880 06:03:55.572597 <6>[ 17.984820] Bluetooth: HCI socket layer initialized
10881 06:03:55.579413 <6>[ 17.984826] Bluetooth: L2CAP socket layer initialized
10882 06:03:55.582750 <6>[ 17.984839] Bluetooth: SCO socket layer initialized
10883 06:03:55.589065 <6>[ 18.002724] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10884 06:03:55.596179 <6>[ 18.009401] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10885 06:03:55.609387 <6>[ 18.020198] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10886 06:03:55.615916 <6>[ 18.027143] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10887 06:03:55.619129 <6>[ 18.028840] r8152 2-1.3:1.0 eth0: v1.12.13
10888 06:03:55.625282 <6>[ 18.034565] usbcore: registered new interface driver uvcvideo
10889 06:03:55.632149 <6>[ 18.035093] usbcore: registered new interface driver btusb
10890 06:03:55.639045 <6>[ 18.035242] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10891 06:03:55.648791 <4>[ 18.035962] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10892 06:03:55.654960 <3>[ 18.035983] Bluetooth: hci0: Failed to load firmware file (-2)
10893 06:03:55.658773 <3>[ 18.035991] Bluetooth: hci0: Failed to set up firmware (-2)
10894 06:03:55.671640 <4>[ 18.035998] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10895 06:03:55.678367 <3>[ 18.036018] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 06:03:55.688343 <3>[ 18.037695] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10897 06:03:55.695404 <6>[ 18.041436] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10898 06:03:55.701485 <6>[ 18.043287] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10899 06:03:55.708705 <3>[ 18.053943] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 06:03:55.717898 <3>[ 18.056518] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10901 06:03:55.728143 <3>[ 18.074683] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 06:03:55.741378 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd<5>[ 18.247836] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10903 06:03:55.741484 _backlight[0m...
10904 06:03:55.756511 <3>[ 18.264080] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 06:03:55.762933 <5>[ 18.269680] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10906 06:03:55.772969 <4>[ 18.279786] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10907 06:03:55.776359 <6>[ 18.288674] cfg80211: failed to load regulatory.db
10908 06:03:55.782866 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10909 06:03:55.800018 <3>[ 18.308049] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 06:03:55.811960 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10911 06:03:55.829472 <3>[ 18.337443] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 06:03:55.839157 [[0;32m OK [0m] Found device<6>[ 18.348432] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10913 06:03:55.849830 [0;1;39m/dev/t<6>[ 18.357037] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10914 06:03:55.849924 tyS0[0m.
10915 06:03:55.860201 <3>[ 18.367495] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 06:03:55.873634 <6>[ 18.385011] mt7921e 0000:01:00.0: ASIC revision: 79610010
10917 06:03:55.977919 [[0;32m OK [<6>[ 18.486133] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10918 06:03:55.980976 <6>[ 18.486133]
10919 06:03:55.984052 0m] Reached target [0;1;39mBluetooth[0m.
10920 06:03:55.997839 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10921 06:03:56.017121 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10922 06:03:56.029653 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10923 06:03:56.050135 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10924 06:03:56.065577 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10925 06:03:56.078062 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10926 06:03:56.097408 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10927 06:03:56.110125 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10928 06:03:56.126170 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10929 06:03:56.145535 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10930 06:03:56.182946 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10931 06:03:56.216613 Starting [0;1;39mUser Login Management[0m...
10932 06:03:56.234448 Starting [0;1;39mPermit User Sessions[0m...
10933 06:03:56.249240 <6>[ 18.757029] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10934 06:03:56.258198 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10935 06:03:56.310859 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10936 06:03:56.328269 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10937 06:03:56.345613 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10938 06:03:56.390122 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10939 06:03:56.406767 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10940 06:03:56.422530 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10941 06:03:56.439612 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10942 06:03:56.454130 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10943 06:03:56.514326 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10944 06:03:56.545114 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10945 06:03:56.582137
10946 06:03:56.582275
10947 06:03:56.584838 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10948 06:03:56.584922
10949 06:03:56.588321 debian-bullseye-arm64 login: root (automatic login)
10950 06:03:56.588417
10951 06:03:56.588481
10952 06:03:56.603802 Linux debian-bullseye-arm64 6.1.67-cip12 #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023 aarch64
10953 06:03:56.603923
10954 06:03:56.610897 The programs included with the Debian GNU/Linux system are free software;
10955 06:03:56.617243 the exact distribution terms for each program are described in the
10956 06:03:56.620777 individual files in /usr/share/doc/*/copyright.
10957 06:03:56.620884
10958 06:03:56.627160 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10959 06:03:56.630639 permitted by applicable law.
10960 06:03:56.631017 Matched prompt #10: / #
10962 06:03:56.631221 Setting prompt string to ['/ #']
10963 06:03:56.631330 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10965 06:03:56.631528 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10966 06:03:56.631613 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
10967 06:03:56.631683 Setting prompt string to ['/ #']
10968 06:03:56.631743 Forcing a shell prompt, looking for ['/ #']
10970 06:03:56.681985 / #
10971 06:03:56.682203 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10972 06:03:56.682288 Waiting using forced prompt support (timeout 00:02:30)
10973 06:03:56.687697
10974 06:03:56.687974 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10975 06:03:56.688072 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
10976 06:03:56.688195 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10977 06:03:56.688310 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
10978 06:03:56.688431 end: 2 depthcharge-action (duration 00:01:28) [common]
10979 06:03:56.688517 start: 3 lava-test-retry (timeout 00:08:11) [common]
10980 06:03:56.688607 start: 3.1 lava-test-shell (timeout 00:08:11) [common]
10981 06:03:56.688679 Using namespace: common
10983 06:03:56.789173 / # #
10984 06:03:56.789698 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10985 06:03:56.795155 #
10986 06:03:56.795925 Using /lava-12379462
10988 06:03:56.896863 / # export SHELL=/bin/sh
10989 06:03:56.902735 export SHELL=/bin/sh
10991 06:03:57.003330 / # . /lava-12379462/environment
10992 06:03:57.008640 . /lava-12379462/environment
10994 06:03:57.109271 / # /lava-12379462/bin/lava-test-runner /lava-12379462/0
10995 06:03:57.109540 Test shell timeout: 10s (minimum of the action and connection timeout)
10996 06:03:57.110187 /lava-12379462/bin/lava-test-runner /lava-12379462/0<6>[ 19.612376] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10997 06:03:57.114304
10998 06:03:57.156461 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
10999 06:03:57.156607 + cd /lava-12379462/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11000 06:03:57.156700 + cat uuid
11001 06:03:57.156782 + UUID=12379462_1.5.2.3.1
11002 06:03:57.156886 + set +x
11003 06:03:57.157174 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 12379462_1.5.2.3.1>
11004 06:03:57.157470 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 12379462_1.5.2.3.1
11005 06:03:57.157581 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (12379462_1.5.2.3.1)
11006 06:03:57.157713 Skipping test definition patterns.
11007 06:03:57.160177 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11008 06:03:57.166907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11009 06:03:57.166994 device: /dev/video2
11010 06:03:57.167253 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11012 06:03:57.179686 <4>[ 19.687447] use of bytesused == 0 is deprecated and will be removed in the future,
11013 06:03:57.182332 <4>[ 19.695379] use the actual size instead.
11014 06:03:57.198012 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11015 06:03:57.210983 <6>[ 19.719353] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
11016 06:03:57.217978 <6>[ 19.727266] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
11017 06:03:57.220863 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11018 06:03:57.232245
11019 06:03:57.245965 Compliance test for mtk-vcodec-enc device /dev/video2:
11020 06:03:57.251570
11021 06:03:57.259974 Driver Info:
11022 06:03:57.270019 Driver name : mtk-vcodec-enc
11023 06:03:57.283341 Card type : MT8192 video encoder
11024 06:03:57.298510 Bus info : platform:17020000.vcodec
11025 06:03:57.307568 Driver version : 6.1.67
11026 06:03:57.318524 Capabilities : 0x84204000
11027 06:03:57.328770 Video Memory-to-Memory Multiplanar
11028 06:03:57.339920 Streaming
11029 06:03:57.350550 Extended Pix Format
11030 06:03:57.361429 Device Capabilities
11031 06:03:57.372952 Device Caps : 0x04204000
11032 06:03:57.383572 Video Memory-to-Memory Multiplanar
11033 06:03:57.394474 Streaming
11034 06:03:57.404363 Extended Pix Format
11035 06:03:57.415388 Detected Stateful Encoder
11036 06:03:57.426266
11037 06:03:57.440458 Required ioctls:
11038 06:03:57.456011 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11039 06:03:57.456109 test VIDIOC_QUERYCAP: OK
11040 06:03:57.456315 Received signal: <TESTSET> START Required-ioctls
11041 06:03:57.456393 Starting test_set Required-ioctls
11042 06:03:57.480006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11043 06:03:57.480332 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11045 06:03:57.483451 test invalid ioctls: OK
11046 06:03:57.505133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11047 06:03:57.505242
11048 06:03:57.505484 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11050 06:03:57.516172 Allow for multiple opens:
11051 06:03:57.523001 <LAVA_SIGNAL_TESTSET STOP>
11052 06:03:57.523265 Received signal: <TESTSET> STOP
11053 06:03:57.523337 Closing test_set Required-ioctls
11054 06:03:57.533329 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11055 06:03:57.533602 Received signal: <TESTSET> START Allow-for-multiple-opens
11056 06:03:57.533676 Starting test_set Allow-for-multiple-opens
11057 06:03:57.536071 test second /dev/video2 open: OK
11058 06:03:57.557844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11059 06:03:57.558115 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11061 06:03:57.561316 test VIDIOC_QUERYCAP: OK
11062 06:03:57.583760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11063 06:03:57.584031 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11065 06:03:57.586731 test VIDIOC_G/S_PRIORITY: OK
11066 06:03:57.608224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11067 06:03:57.608559 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11069 06:03:57.611391 test for unlimited opens: OK
11070 06:03:57.632559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11071 06:03:57.632665
11072 06:03:57.632923 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11074 06:03:57.644265 Debug ioctls:
11075 06:03:57.652107 <LAVA_SIGNAL_TESTSET STOP>
11076 06:03:57.652371 Received signal: <TESTSET> STOP
11077 06:03:57.652446 Closing test_set Allow-for-multiple-opens
11078 06:03:57.661749 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11079 06:03:57.662006 Received signal: <TESTSET> START Debug-ioctls
11080 06:03:57.662080 Starting test_set Debug-ioctls
11081 06:03:57.665233 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11082 06:03:57.687304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11083 06:03:57.687572 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11085 06:03:57.693785 test VIDIOC_LOG_STATUS: OK (Not Supported)
11086 06:03:57.716465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11087 06:03:57.716581
11088 06:03:57.716845 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11090 06:03:57.725313 Input ioctls:
11091 06:03:57.732634 <LAVA_SIGNAL_TESTSET STOP>
11092 06:03:57.732922 Received signal: <TESTSET> STOP
11093 06:03:57.732998 Closing test_set Debug-ioctls
11094 06:03:57.742222 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11095 06:03:57.742482 Received signal: <TESTSET> START Input-ioctls
11096 06:03:57.742559 Starting test_set Input-ioctls
11097 06:03:57.744782 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11098 06:03:57.769752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11099 06:03:57.770038 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11101 06:03:57.772563 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11102 06:03:57.789145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11103 06:03:57.789403 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11105 06:03:57.796002 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11106 06:03:57.814532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11107 06:03:57.814812 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11109 06:03:57.820669 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11110 06:03:57.840432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11111 06:03:57.840711 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11113 06:03:57.843680 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11114 06:03:57.864686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11115 06:03:57.864962 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11117 06:03:57.868142 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11118 06:03:57.891145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11119 06:03:57.891411 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11121 06:03:57.894827 Inputs: 0 Audio Inputs: 0 Tuners: 0
11122 06:03:57.902427
11123 06:03:57.919444 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11124 06:03:57.945837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11125 06:03:57.946135 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11127 06:03:57.952063 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11128 06:03:57.972244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11129 06:03:57.972522 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11131 06:03:57.975470 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11132 06:03:57.996657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11133 06:03:57.996913 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11135 06:03:58.002994 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11136 06:03:58.026275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11137 06:03:58.026542 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11139 06:03:58.032408 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11140 06:03:58.053188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11141 06:03:58.053442 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11143 06:03:58.056419
11144 06:03:58.074420 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11145 06:03:58.096426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11146 06:03:58.096684 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11148 06:03:58.102581 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11149 06:03:58.128703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11150 06:03:58.128963 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11152 06:03:58.131930 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11153 06:03:58.151786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11154 06:03:58.152041 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11156 06:03:58.155268 test VIDIOC_G/S_EDID: OK (Not Supported)
11157 06:03:58.179285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11158 06:03:58.179369
11159 06:03:58.179603 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11161 06:03:58.190845 Control ioctls:
11162 06:03:58.197156 <LAVA_SIGNAL_TESTSET STOP>
11163 06:03:58.197415 Received signal: <TESTSET> STOP
11164 06:03:58.197485 Closing test_set Input-ioctls
11165 06:03:58.206773 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11166 06:03:58.207076 Received signal: <TESTSET> START Control-ioctls
11167 06:03:58.207177 Starting test_set Control-ioctls
11168 06:03:58.210411 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11169 06:03:58.235681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11170 06:03:58.235842 test VIDIOC_QUERYCTRL: OK
11171 06:03:58.236111 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11173 06:03:58.256842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11174 06:03:58.257212 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11176 06:03:58.260240 test VIDIOC_G/S_CTRL: OK
11177 06:03:58.306943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11178 06:03:58.307635 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11180 06:03:58.310376 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11181 06:03:58.331631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11182 06:03:58.332393 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11184 06:03:58.341680 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11185 06:03:58.350787 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11186 06:03:58.376456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11187 06:03:58.377098 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11189 06:03:58.379979 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11190 06:03:58.396655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11191 06:03:58.397344 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11193 06:03:58.400305 Standard Controls: 16 Private Controls: 0
11194 06:03:58.408071
11195 06:03:58.421045 Format ioctls:
11196 06:03:58.429107 <LAVA_SIGNAL_TESTSET STOP>
11197 06:03:58.429785 Received signal: <TESTSET> STOP
11198 06:03:58.430271 Closing test_set Control-ioctls
11199 06:03:58.438723 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11200 06:03:58.439157 Received signal: <TESTSET> START Format-ioctls
11201 06:03:58.439347 Starting test_set Format-ioctls
11202 06:03:58.441715 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11203 06:03:58.468575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11204 06:03:58.469036 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11206 06:03:58.471480 test VIDIOC_G/S_PARM: OK
11207 06:03:58.489240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11208 06:03:58.489688 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11210 06:03:58.492915 test VIDIOC_G_FBUF: OK (Not Supported)
11211 06:03:58.519719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11212 06:03:58.520391 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11214 06:03:58.522903 test VIDIOC_G_FMT: OK
11215 06:03:58.544810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11216 06:03:58.545758 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11218 06:03:58.547956 test VIDIOC_TRY_FMT: OK
11219 06:03:58.575978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11220 06:03:58.576798 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11222 06:03:58.585588 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11223 06:03:58.586018 test VIDIOC_S_FMT: FAIL
11224 06:03:58.612222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11225 06:03:58.613025 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11227 06:03:58.615760 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11228 06:03:58.637676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11229 06:03:58.638470 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11231 06:03:58.640931 test Cropping: OK
11232 06:03:58.663205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11233 06:03:58.663971 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11235 06:03:58.666888 test Composing: OK (Not Supported)
11236 06:03:58.689099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11237 06:03:58.689818 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11239 06:03:58.692398 test Scaling: OK (Not Supported)
11240 06:03:58.717035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11241 06:03:58.717642
11242 06:03:58.718241 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11244 06:03:58.729001 Codec ioctls:
11245 06:03:58.735846 <LAVA_SIGNAL_TESTSET STOP>
11246 06:03:58.736626 Received signal: <TESTSET> STOP
11247 06:03:58.737089 Closing test_set Format-ioctls
11248 06:03:58.745643 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11249 06:03:58.746381 Received signal: <TESTSET> START Codec-ioctls
11250 06:03:58.746788 Starting test_set Codec-ioctls
11251 06:03:58.748962 test VIDIOC_(TRY_)ENCODER_CMD: OK
11252 06:03:58.770309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11253 06:03:58.771107 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11255 06:03:58.776661 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11256 06:03:58.796804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11257 06:03:58.797581 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11259 06:03:58.802798 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11260 06:03:58.820729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11261 06:03:58.821242
11262 06:03:58.821831 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11264 06:03:58.831454 Buffer ioctls:
11265 06:03:58.841128 <LAVA_SIGNAL_TESTSET STOP>
11266 06:03:58.841947 Received signal: <TESTSET> STOP
11267 06:03:58.842318 Closing test_set Codec-ioctls
11268 06:03:58.851955 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11269 06:03:58.852800 Received signal: <TESTSET> START Buffer-ioctls
11270 06:03:58.853163 Starting test_set Buffer-ioctls
11271 06:03:58.855111 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11272 06:03:58.880360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11273 06:03:58.880870 test VIDIOC_EXPBUF: OK
11274 06:03:58.881462 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11276 06:03:58.902581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11277 06:03:58.903343 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11279 06:03:58.906053 test Requests: OK (Not Supported)
11280 06:03:58.932220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11281 06:03:58.932801
11282 06:03:58.933401 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11284 06:03:58.942320 Test input 0:
11285 06:03:58.952797
11286 06:03:58.965983 Streaming ioctls:
11287 06:03:58.973149 <LAVA_SIGNAL_TESTSET STOP>
11288 06:03:58.973929 Received signal: <TESTSET> STOP
11289 06:03:58.974277 Closing test_set Buffer-ioctls
11290 06:03:58.983578 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11291 06:03:58.984404 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11292 06:03:58.984762 Starting test_set Streaming-ioctls_Test-input-0
11293 06:03:58.986241 test read/write: OK (Not Supported)
11294 06:03:59.009114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11295 06:03:59.009882 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11297 06:03:59.016272 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11298 06:03:59.027689 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11299 06:03:59.032386 test blocking wait: FAIL
11300 06:03:59.064054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11301 06:03:59.064904 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11303 06:03:59.073773 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11304 06:03:59.077111 test MMAP (select): FAIL
11305 06:03:59.102249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11306 06:03:59.103013 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11308 06:03:59.108803 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11309 06:03:59.113257 test MMAP (epoll): FAIL
11310 06:03:59.143162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11311 06:03:59.143878 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11313 06:03:59.153198 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11314 06:03:59.160114 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11315 06:03:59.167086 test USERPTR (select): FAIL
11316 06:03:59.194731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11317 06:03:59.195524 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11319 06:03:59.201122 test DMABUF: Cannot test, specify --expbuf-device
11320 06:03:59.204854
11321 06:03:59.227022 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11322 06:03:59.231159 <LAVA_TEST_RUNNER EXIT>
11323 06:03:59.231841 ok: lava_test_shell seems to have completed
11324 06:03:59.232217 Marking unfinished test run as failed
11326 06:03:59.236937 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11327 06:03:59.237525 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11328 06:03:59.237965 end: 3 lava-test-retry (duration 00:00:03) [common]
11329 06:03:59.238431 start: 4 finalize (timeout 00:08:08) [common]
11330 06:03:59.238893 start: 4.1 power-off (timeout 00:00:30) [common]
11331 06:03:59.239625 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11332 06:03:59.360445 >> Command sent successfully.
11333 06:03:59.364743 Returned 0 in 0 seconds
11334 06:03:59.465758 end: 4.1 power-off (duration 00:00:00) [common]
11336 06:03:59.467749 start: 4.2 read-feedback (timeout 00:08:08) [common]
11337 06:03:59.469206 Listened to connection for namespace 'common' for up to 1s
11338 06:04:00.469849 Finalising connection for namespace 'common'
11339 06:04:00.470535 Disconnecting from shell: Finalise
11340 06:04:00.470923 / #
11341 06:04:00.571905 end: 4.2 read-feedback (duration 00:00:01) [common]
11342 06:04:00.572645 end: 4 finalize (duration 00:00:01) [common]
11343 06:04:00.573218 Cleaning after the job
11344 06:04:00.573763 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379462/tftp-deploy-6shl4gkr/ramdisk
11345 06:04:00.598654 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379462/tftp-deploy-6shl4gkr/kernel
11346 06:04:00.620470 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379462/tftp-deploy-6shl4gkr/dtb
11347 06:04:00.620817 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379462/tftp-deploy-6shl4gkr/modules
11348 06:04:00.631361 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12379462
11349 06:04:00.701268 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12379462
11350 06:04:00.701439 Job finished correctly