Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 16
- Kernel Errors: 35
- Errors: 1
1 06:01:51.045654 lava-dispatcher, installed at version: 2023.10
2 06:01:51.045867 start: 0 validate
3 06:01:51.046009 Start time: 2023-12-25 06:01:51.046002+00:00 (UTC)
4 06:01:51.046130 Using caching service: 'http://localhost/cache/?uri=%s'
5 06:01:51.046255 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 06:01:51.320094 Using caching service: 'http://localhost/cache/?uri=%s'
7 06:01:51.320764 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 06:01:51.591463 Using caching service: 'http://localhost/cache/?uri=%s'
9 06:01:51.592176 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 06:01:51.855408 Using caching service: 'http://localhost/cache/?uri=%s'
11 06:01:51.856138 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.67-cip12%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 06:01:52.133358 validate duration: 1.09
14 06:01:52.134644 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:01:52.135126 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:01:52.135569 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:01:52.136130 Not decompressing ramdisk as can be used compressed.
18 06:01:52.136551 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 06:01:52.136892 saving as /var/lib/lava/dispatcher/tmp/12379478/tftp-deploy-13tqp04d/ramdisk/rootfs.cpio.gz
20 06:01:52.137211 total size: 26246609 (25 MB)
21 06:01:52.142059 progress 0 % (0 MB)
22 06:01:52.169550 progress 5 % (1 MB)
23 06:01:52.181943 progress 10 % (2 MB)
24 06:01:52.191059 progress 15 % (3 MB)
25 06:01:52.198793 progress 20 % (5 MB)
26 06:01:52.205711 progress 25 % (6 MB)
27 06:01:52.212440 progress 30 % (7 MB)
28 06:01:52.219165 progress 35 % (8 MB)
29 06:01:52.225846 progress 40 % (10 MB)
30 06:01:52.232561 progress 45 % (11 MB)
31 06:01:52.239263 progress 50 % (12 MB)
32 06:01:52.246357 progress 55 % (13 MB)
33 06:01:52.253119 progress 60 % (15 MB)
34 06:01:52.259952 progress 65 % (16 MB)
35 06:01:52.266667 progress 70 % (17 MB)
36 06:01:52.273320 progress 75 % (18 MB)
37 06:01:52.280089 progress 80 % (20 MB)
38 06:01:52.286775 progress 85 % (21 MB)
39 06:01:52.293307 progress 90 % (22 MB)
40 06:01:52.300180 progress 95 % (23 MB)
41 06:01:52.306858 progress 100 % (25 MB)
42 06:01:52.307102 25 MB downloaded in 0.17 s (147.32 MB/s)
43 06:01:52.307259 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:01:52.307494 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:01:52.307578 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:01:52.307659 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:01:52.307796 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 06:01:52.307862 saving as /var/lib/lava/dispatcher/tmp/12379478/tftp-deploy-13tqp04d/kernel/Image
50 06:01:52.307924 total size: 50024960 (47 MB)
51 06:01:52.307983 No compression specified
52 06:01:52.309075 progress 0 % (0 MB)
53 06:01:52.321851 progress 5 % (2 MB)
54 06:01:52.334462 progress 10 % (4 MB)
55 06:01:52.347265 progress 15 % (7 MB)
56 06:01:52.360306 progress 20 % (9 MB)
57 06:01:52.373153 progress 25 % (11 MB)
58 06:01:52.385923 progress 30 % (14 MB)
59 06:01:52.398912 progress 35 % (16 MB)
60 06:01:52.411715 progress 40 % (19 MB)
61 06:01:52.424502 progress 45 % (21 MB)
62 06:01:52.437349 progress 50 % (23 MB)
63 06:01:52.450078 progress 55 % (26 MB)
64 06:01:52.462913 progress 60 % (28 MB)
65 06:01:52.475743 progress 65 % (31 MB)
66 06:01:52.488421 progress 70 % (33 MB)
67 06:01:52.501115 progress 75 % (35 MB)
68 06:01:52.513998 progress 80 % (38 MB)
69 06:01:52.526656 progress 85 % (40 MB)
70 06:01:52.539361 progress 90 % (42 MB)
71 06:01:52.552077 progress 95 % (45 MB)
72 06:01:52.564511 progress 100 % (47 MB)
73 06:01:52.564712 47 MB downloaded in 0.26 s (185.79 MB/s)
74 06:01:52.564875 end: 1.2.1 http-download (duration 00:00:00) [common]
76 06:01:52.565212 end: 1.2 download-retry (duration 00:00:00) [common]
77 06:01:52.565298 start: 1.3 download-retry (timeout 00:10:00) [common]
78 06:01:52.565397 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 06:01:52.565584 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 06:01:52.565655 saving as /var/lib/lava/dispatcher/tmp/12379478/tftp-deploy-13tqp04d/dtb/mt8192-asurada-spherion-r0.dtb
81 06:01:52.565716 total size: 47278 (0 MB)
82 06:01:52.565775 No compression specified
83 06:01:52.567000 progress 69 % (0 MB)
84 06:01:52.567269 progress 100 % (0 MB)
85 06:01:52.567461 0 MB downloaded in 0.00 s (25.87 MB/s)
86 06:01:52.567581 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:01:52.567797 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:01:52.567879 start: 1.4 download-retry (timeout 00:10:00) [common]
90 06:01:52.567961 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 06:01:52.568073 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.67-cip12/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 06:01:52.568137 saving as /var/lib/lava/dispatcher/tmp/12379478/tftp-deploy-13tqp04d/modules/modules.tar
93 06:01:52.568195 total size: 8619328 (8 MB)
94 06:01:52.568253 Using unxz to decompress xz
95 06:01:52.572460 progress 0 % (0 MB)
96 06:01:52.593489 progress 5 % (0 MB)
97 06:01:52.617647 progress 10 % (0 MB)
98 06:01:52.641034 progress 15 % (1 MB)
99 06:01:52.665469 progress 20 % (1 MB)
100 06:01:52.689875 progress 25 % (2 MB)
101 06:01:52.715236 progress 30 % (2 MB)
102 06:01:52.740929 progress 35 % (2 MB)
103 06:01:52.764241 progress 40 % (3 MB)
104 06:01:52.788379 progress 45 % (3 MB)
105 06:01:52.813383 progress 50 % (4 MB)
106 06:01:52.837176 progress 55 % (4 MB)
107 06:01:52.861796 progress 60 % (4 MB)
108 06:01:52.887200 progress 65 % (5 MB)
109 06:01:52.914211 progress 70 % (5 MB)
110 06:01:52.937288 progress 75 % (6 MB)
111 06:01:52.963874 progress 80 % (6 MB)
112 06:01:52.989211 progress 85 % (7 MB)
113 06:01:53.013899 progress 90 % (7 MB)
114 06:01:53.042978 progress 95 % (7 MB)
115 06:01:53.072795 progress 100 % (8 MB)
116 06:01:53.077382 8 MB downloaded in 0.51 s (16.14 MB/s)
117 06:01:53.077641 end: 1.4.1 http-download (duration 00:00:01) [common]
119 06:01:53.077910 end: 1.4 download-retry (duration 00:00:01) [common]
120 06:01:53.078003 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 06:01:53.078096 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 06:01:53.078172 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:01:53.078258 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 06:01:53.078483 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1
125 06:01:53.078619 makedir: /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin
126 06:01:53.078730 makedir: /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/tests
127 06:01:53.078866 makedir: /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/results
128 06:01:53.078987 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-add-keys
129 06:01:53.079133 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-add-sources
130 06:01:53.079263 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-background-process-start
131 06:01:53.079393 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-background-process-stop
132 06:01:53.079520 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-common-functions
133 06:01:53.079645 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-echo-ipv4
134 06:01:53.079769 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-install-packages
135 06:01:53.079894 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-installed-packages
136 06:01:53.080020 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-os-build
137 06:01:53.080144 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-probe-channel
138 06:01:53.080267 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-probe-ip
139 06:01:53.080391 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-target-ip
140 06:01:53.080516 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-target-mac
141 06:01:53.080646 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-target-storage
142 06:01:53.080773 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-test-case
143 06:01:53.080900 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-test-event
144 06:01:53.081024 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-test-feedback
145 06:01:53.081148 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-test-raise
146 06:01:53.081271 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-test-reference
147 06:01:53.081394 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-test-runner
148 06:01:53.081524 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-test-set
149 06:01:53.081649 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-test-shell
150 06:01:53.081776 Updating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-install-packages (oe)
151 06:01:53.081926 Updating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/bin/lava-installed-packages (oe)
152 06:01:53.082047 Creating /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/environment
153 06:01:53.082145 LAVA metadata
154 06:01:53.082215 - LAVA_JOB_ID=12379478
155 06:01:53.082280 - LAVA_DISPATCHER_IP=192.168.201.1
156 06:01:53.082379 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 06:01:53.082445 skipped lava-vland-overlay
158 06:01:53.082516 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 06:01:53.082593 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 06:01:53.082658 skipped lava-multinode-overlay
161 06:01:53.082730 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 06:01:53.082811 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 06:01:53.082883 Loading test definitions
164 06:01:53.082970 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 06:01:53.083041 Using /lava-12379478 at stage 0
166 06:01:53.083346 uuid=12379478_1.5.2.3.1 testdef=None
167 06:01:53.083431 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 06:01:53.083511 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 06:01:53.084013 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 06:01:53.084224 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 06:01:53.084823 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 06:01:53.085046 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 06:01:53.085636 runner path: /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/0/tests/0_v4l2-compliance-uvc test_uuid 12379478_1.5.2.3.1
176 06:01:53.085795 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 06:01:53.085995 Creating lava-test-runner.conf files
179 06:01:53.086056 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12379478/lava-overlay-9_mg_3w1/lava-12379478/0 for stage 0
180 06:01:53.086146 - 0_v4l2-compliance-uvc
181 06:01:53.086239 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 06:01:53.086323 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 06:01:53.092906 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 06:01:53.093010 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 06:01:53.093094 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 06:01:53.093177 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 06:01:53.093262 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 06:01:53.815494 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 06:01:53.815883 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 06:01:53.816002 extracting modules file /var/lib/lava/dispatcher/tmp/12379478/tftp-deploy-13tqp04d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12379478/extract-overlay-ramdisk-ht0ahm6h/ramdisk
191 06:01:54.049921 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 06:01:54.050098 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 06:01:54.050191 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379478/compress-overlay-_04h60q1/overlay-1.5.2.4.tar.gz to ramdisk
194 06:01:54.050258 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12379478/compress-overlay-_04h60q1/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12379478/extract-overlay-ramdisk-ht0ahm6h/ramdisk
195 06:01:54.058980 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 06:01:54.059147 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 06:01:54.059268 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 06:01:54.059387 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 06:01:54.059499 Building ramdisk /var/lib/lava/dispatcher/tmp/12379478/extract-overlay-ramdisk-ht0ahm6h/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12379478/extract-overlay-ramdisk-ht0ahm6h/ramdisk
200 06:01:54.674729 >> 228444 blocks
201 06:01:58.514637 rename /var/lib/lava/dispatcher/tmp/12379478/extract-overlay-ramdisk-ht0ahm6h/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12379478/tftp-deploy-13tqp04d/ramdisk/ramdisk.cpio.gz
202 06:01:58.515096 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 06:01:58.515220 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 06:01:58.515321 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 06:01:58.515425 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12379478/tftp-deploy-13tqp04d/kernel/Image'
206 06:02:10.780656 Returned 0 in 12 seconds
207 06:02:10.881702 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12379478/tftp-deploy-13tqp04d/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12379478/tftp-deploy-13tqp04d/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12379478/tftp-deploy-13tqp04d/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12379478/tftp-deploy-13tqp04d/kernel/image.itb
208 06:02:11.521174 output: FIT description: Kernel Image image with one or more FDT blobs
209 06:02:11.521627 output: Created: Mon Dec 25 06:02:11 2023
210 06:02:11.521701 output: Image 0 (kernel-1)
211 06:02:11.521763 output: Description:
212 06:02:11.521823 output: Created: Mon Dec 25 06:02:11 2023
213 06:02:11.521883 output: Type: Kernel Image
214 06:02:11.521940 output: Compression: lzma compressed
215 06:02:11.522001 output: Data Size: 11481830 Bytes = 11212.72 KiB = 10.95 MiB
216 06:02:11.522060 output: Architecture: AArch64
217 06:02:11.522119 output: OS: Linux
218 06:02:11.522176 output: Load Address: 0x00000000
219 06:02:11.522232 output: Entry Point: 0x00000000
220 06:02:11.522289 output: Hash algo: crc32
221 06:02:11.522343 output: Hash value: a47c00f1
222 06:02:11.522397 output: Image 1 (fdt-1)
223 06:02:11.522449 output: Description: mt8192-asurada-spherion-r0
224 06:02:11.522500 output: Created: Mon Dec 25 06:02:11 2023
225 06:02:11.522551 output: Type: Flat Device Tree
226 06:02:11.522602 output: Compression: uncompressed
227 06:02:11.522652 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 06:02:11.522703 output: Architecture: AArch64
229 06:02:11.522753 output: Hash algo: crc32
230 06:02:11.522803 output: Hash value: cc4352de
231 06:02:11.522854 output: Image 2 (ramdisk-1)
232 06:02:11.522904 output: Description: unavailable
233 06:02:11.522954 output: Created: Mon Dec 25 06:02:11 2023
234 06:02:11.523004 output: Type: RAMDisk Image
235 06:02:11.523054 output: Compression: Unknown Compression
236 06:02:11.523104 output: Data Size: 39349680 Bytes = 38427.42 KiB = 37.53 MiB
237 06:02:11.523155 output: Architecture: AArch64
238 06:02:11.523205 output: OS: Linux
239 06:02:11.523255 output: Load Address: unavailable
240 06:02:11.523306 output: Entry Point: unavailable
241 06:02:11.523356 output: Hash algo: crc32
242 06:02:11.523405 output: Hash value: 387faa42
243 06:02:11.523455 output: Default Configuration: 'conf-1'
244 06:02:11.523506 output: Configuration 0 (conf-1)
245 06:02:11.523556 output: Description: mt8192-asurada-spherion-r0
246 06:02:11.523606 output: Kernel: kernel-1
247 06:02:11.523656 output: Init Ramdisk: ramdisk-1
248 06:02:11.523706 output: FDT: fdt-1
249 06:02:11.523756 output: Loadables: kernel-1
250 06:02:11.523806 output:
251 06:02:11.524008 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 06:02:11.524101 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 06:02:11.524203 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 06:02:11.524295 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 06:02:11.524370 No LXC device requested
256 06:02:11.524447 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 06:02:11.524526 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 06:02:11.524598 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 06:02:11.524664 Checking files for TFTP limit of 4294967296 bytes.
260 06:02:11.525153 end: 1 tftp-deploy (duration 00:00:19) [common]
261 06:02:11.525255 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 06:02:11.525342 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 06:02:11.525461 substitutions:
264 06:02:11.525559 - {DTB}: 12379478/tftp-deploy-13tqp04d/dtb/mt8192-asurada-spherion-r0.dtb
265 06:02:11.525621 - {INITRD}: 12379478/tftp-deploy-13tqp04d/ramdisk/ramdisk.cpio.gz
266 06:02:11.525679 - {KERNEL}: 12379478/tftp-deploy-13tqp04d/kernel/Image
267 06:02:11.525748 - {LAVA_MAC}: None
268 06:02:11.525802 - {PRESEED_CONFIG}: None
269 06:02:11.525854 - {PRESEED_LOCAL}: None
270 06:02:11.525906 - {RAMDISK}: 12379478/tftp-deploy-13tqp04d/ramdisk/ramdisk.cpio.gz
271 06:02:11.525958 - {ROOT_PART}: None
272 06:02:11.526010 - {ROOT}: None
273 06:02:11.526061 - {SERVER_IP}: 192.168.201.1
274 06:02:11.526112 - {TEE}: None
275 06:02:11.526163 Parsed boot commands:
276 06:02:11.526216 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 06:02:11.526396 Parsed boot commands: tftpboot 192.168.201.1 12379478/tftp-deploy-13tqp04d/kernel/image.itb 12379478/tftp-deploy-13tqp04d/kernel/cmdline
278 06:02:11.526481 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 06:02:11.526565 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 06:02:11.526658 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 06:02:11.526741 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 06:02:11.526806 Not connected, no need to disconnect.
283 06:02:11.526875 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 06:02:11.526950 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 06:02:11.527011 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 06:02:11.531087 Setting prompt string to ['lava-test: # ']
287 06:02:11.531481 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 06:02:11.531590 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 06:02:11.531683 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 06:02:11.531817 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 06:02:11.532069 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 06:02:16.675548 >> Command sent successfully.
293 06:02:16.686153 Returned 0 in 5 seconds
294 06:02:16.787298 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 06:02:16.789053 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 06:02:16.789798 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 06:02:16.790270 Setting prompt string to 'Starting depthcharge on Spherion...'
299 06:02:16.790614 Changing prompt to 'Starting depthcharge on Spherion...'
300 06:02:16.790955 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 06:02:16.792133 [Enter `^Ec?' for help]
302 06:02:16.950109
303 06:02:16.950636
304 06:02:16.950975 F0: 102B 0000
305 06:02:16.951300
306 06:02:16.951667 F3: 1001 0000 [0200]
307 06:02:16.951971
308 06:02:16.953464 F3: 1001 0000
309 06:02:16.953910
310 06:02:16.954235 F7: 102D 0000
311 06:02:16.954541
312 06:02:16.957722 F1: 0000 0000
313 06:02:16.958165
314 06:02:16.958598 V0: 0000 0000 [0001]
315 06:02:16.959108
316 06:02:16.959639 00: 0007 8000
317 06:02:16.960183
318 06:02:16.961046 01: 0000 0000
319 06:02:16.961399
320 06:02:16.961764 BP: 0C00 0209 [0000]
321 06:02:16.962062
322 06:02:16.964802 G0: 1182 0000
323 06:02:16.965276
324 06:02:16.965665 EC: 0000 0021 [4000]
325 06:02:16.965987
326 06:02:16.968357 S7: 0000 0000 [0000]
327 06:02:16.968777
328 06:02:16.969127 CC: 0000 0000 [0001]
329 06:02:16.969437
330 06:02:16.971640 T0: 0000 0040 [010F]
331 06:02:16.972061
332 06:02:16.972393 Jump to BL
333 06:02:16.972702
334 06:02:16.996667
335 06:02:16.996800
336 06:02:16.996888
337 06:02:17.004040 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 06:02:17.008017 ARM64: Exception handlers installed.
339 06:02:17.011490 ARM64: Testing exception
340 06:02:17.014949 ARM64: Done test exception
341 06:02:17.021787 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 06:02:17.029238 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 06:02:17.036720 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 06:02:17.047559 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 06:02:17.053664 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 06:02:17.064599 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 06:02:17.075016 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 06:02:17.081155 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 06:02:17.099115 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 06:02:17.102643 WDT: Last reset was cold boot
351 06:02:17.106029 SPI1(PAD0) initialized at 2873684 Hz
352 06:02:17.109417 SPI5(PAD0) initialized at 992727 Hz
353 06:02:17.112934 VBOOT: Loading verstage.
354 06:02:17.119058 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 06:02:17.122649 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 06:02:17.126024 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 06:02:17.129567 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 06:02:17.136960 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 06:02:17.143194 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 06:02:17.154988 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
361 06:02:17.155627
362 06:02:17.156184
363 06:02:17.164870 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 06:02:17.168544 ARM64: Exception handlers installed.
365 06:02:17.171441 ARM64: Testing exception
366 06:02:17.171884 ARM64: Done test exception
367 06:02:17.179723 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 06:02:17.182167 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 06:02:17.196127 Probing TPM: . done!
370 06:02:17.196651 TPM ready after 0 ms
371 06:02:17.202511 Connected to device vid:did:rid of 1ae0:0028:00
372 06:02:17.212770 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 06:02:17.250566 Initialized TPM device CR50 revision 0
374 06:02:17.262292 tlcl_send_startup: Startup return code is 0
375 06:02:17.262806 TPM: setup succeeded
376 06:02:17.273635 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 06:02:17.282495 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 06:02:17.294460 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 06:02:17.303754 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 06:02:17.306949 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 06:02:17.310512 in-header: 03 07 00 00 08 00 00 00
382 06:02:17.314428 in-data: aa e4 47 04 13 02 00 00
383 06:02:17.317732 Chrome EC: UHEPI supported
384 06:02:17.324569 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 06:02:17.328501 in-header: 03 9d 00 00 08 00 00 00
386 06:02:17.332158 in-data: 10 20 20 08 00 00 00 00
387 06:02:17.332585 Phase 1
388 06:02:17.335779 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 06:02:17.343099 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 06:02:17.350308 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 06:02:17.350758 Recovery requested (1009000e)
392 06:02:17.359043 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 06:02:17.364803 tlcl_extend: response is 0
394 06:02:17.372515 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 06:02:17.378110 tlcl_extend: response is 0
396 06:02:17.383928 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 06:02:17.405681 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
398 06:02:17.412278 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 06:02:17.412710
400 06:02:17.413049
401 06:02:17.423379 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 06:02:17.423947 ARM64: Exception handlers installed.
403 06:02:17.426710 ARM64: Testing exception
404 06:02:17.430094 ARM64: Done test exception
405 06:02:17.448124 pmic_efuse_setting: Set efuses in 11 msecs
406 06:02:17.457104 pmwrap_interface_init: Select PMIF_VLD_RDY
407 06:02:17.460213 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 06:02:17.464072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 06:02:17.468415 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 06:02:17.475336 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 06:02:17.479025 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 06:02:17.483013 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 06:02:17.490461 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 06:02:17.494149 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 06:02:17.497233 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 06:02:17.504206 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 06:02:17.507508 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 06:02:17.510915 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 06:02:17.517414 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 06:02:17.524214 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 06:02:17.527524 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 06:02:17.534299 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 06:02:17.540479 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 06:02:17.547072 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 06:02:17.551070 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 06:02:17.558417 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 06:02:17.561875 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 06:02:17.568967 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 06:02:17.572093 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 06:02:17.579122 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 06:02:17.582576 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 06:02:17.589264 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 06:02:17.596419 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 06:02:17.599372 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 06:02:17.606323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 06:02:17.609638 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 06:02:17.613314 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 06:02:17.620920 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 06:02:17.624616 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 06:02:17.631064 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 06:02:17.635201 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 06:02:17.638674 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 06:02:17.645651 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 06:02:17.649042 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 06:02:17.652871 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 06:02:17.659806 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 06:02:17.662622 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 06:02:17.665881 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 06:02:17.672824 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 06:02:17.676332 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 06:02:17.679948 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 06:02:17.685755 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 06:02:17.689213 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 06:02:17.692604 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 06:02:17.696291 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 06:02:17.702831 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 06:02:17.706212 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 06:02:17.712863 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 06:02:17.723118 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 06:02:17.726170 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 06:02:17.735821 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 06:02:17.742427 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 06:02:17.749648 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 06:02:17.753320 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 06:02:17.756135 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 06:02:17.763234 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 06:02:17.770116 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 06:02:17.773270 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 06:02:17.776733 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 06:02:17.787638 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 06:02:17.791218 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 06:02:17.797596 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 06:02:17.801319 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 06:02:17.804801 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 06:02:17.808236 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 06:02:17.811448 ADC[4]: Raw value=895191 ID=7
477 06:02:17.814410 ADC[3]: Raw value=214180 ID=1
478 06:02:17.814888 RAM Code: 0x71
479 06:02:17.820928 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 06:02:17.824439 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 06:02:17.834497 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 06:02:17.841906 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 06:02:17.845280 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 06:02:17.848938 in-header: 03 07 00 00 08 00 00 00
485 06:02:17.851975 in-data: aa e4 47 04 13 02 00 00
486 06:02:17.852496 Chrome EC: UHEPI supported
487 06:02:17.858268 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 06:02:17.862871 in-header: 03 95 00 00 08 00 00 00
489 06:02:17.866449 in-data: 18 20 20 08 00 00 00 00
490 06:02:17.870403 MRC: failed to locate region type 0.
491 06:02:17.877549 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 06:02:17.880928 DRAM-K: Running full calibration
493 06:02:17.884219 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 06:02:17.887917 header.status = 0x0
495 06:02:17.891117 header.version = 0x6 (expected: 0x6)
496 06:02:17.893924 header.size = 0xd00 (expected: 0xd00)
497 06:02:17.898461 header.flags = 0x0
498 06:02:17.901229 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 06:02:17.919719 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
500 06:02:17.926572 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 06:02:17.929889 dram_init: ddr_geometry: 2
502 06:02:17.932683 [EMI] MDL number = 2
503 06:02:17.933110 [EMI] Get MDL freq = 0
504 06:02:17.936337 dram_init: ddr_type: 0
505 06:02:17.936867 is_discrete_lpddr4: 1
506 06:02:17.939935 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 06:02:17.940513
508 06:02:17.940858
509 06:02:17.943251 [Bian_co] ETT version 0.0.0.1
510 06:02:17.949626 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 06:02:17.950150
512 06:02:17.953467 dramc_set_vcore_voltage set vcore to 650000
513 06:02:17.954034 Read voltage for 800, 4
514 06:02:17.956428 Vio18 = 0
515 06:02:17.956960 Vcore = 650000
516 06:02:17.957301 Vdram = 0
517 06:02:17.959344 Vddq = 0
518 06:02:17.959767 Vmddr = 0
519 06:02:17.962670 dram_init: config_dvfs: 1
520 06:02:17.966274 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 06:02:17.972619 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 06:02:17.976502 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 06:02:17.979899 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 06:02:17.983346 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 06:02:17.986491 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 06:02:17.989996 MEM_TYPE=3, freq_sel=18
527 06:02:17.993203 sv_algorithm_assistance_LP4_1600
528 06:02:17.996413 ============ PULL DRAM RESETB DOWN ============
529 06:02:17.999320 ========== PULL DRAM RESETB DOWN end =========
530 06:02:18.006462 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 06:02:18.009833 ===================================
532 06:02:18.012998 LPDDR4 DRAM CONFIGURATION
533 06:02:18.016149 ===================================
534 06:02:18.016577 EX_ROW_EN[0] = 0x0
535 06:02:18.019666 EX_ROW_EN[1] = 0x0
536 06:02:18.020088 LP4Y_EN = 0x0
537 06:02:18.023473 WORK_FSP = 0x0
538 06:02:18.024140 WL = 0x2
539 06:02:18.026099 RL = 0x2
540 06:02:18.026579 BL = 0x2
541 06:02:18.029594 RPST = 0x0
542 06:02:18.030022 RD_PRE = 0x0
543 06:02:18.033528 WR_PRE = 0x1
544 06:02:18.034071 WR_PST = 0x0
545 06:02:18.035951 DBI_WR = 0x0
546 06:02:18.036376 DBI_RD = 0x0
547 06:02:18.039220 OTF = 0x1
548 06:02:18.042813 ===================================
549 06:02:18.045945 ===================================
550 06:02:18.046505 ANA top config
551 06:02:18.049174 ===================================
552 06:02:18.052837 DLL_ASYNC_EN = 0
553 06:02:18.056488 ALL_SLAVE_EN = 1
554 06:02:18.059656 NEW_RANK_MODE = 1
555 06:02:18.060091 DLL_IDLE_MODE = 1
556 06:02:18.062686 LP45_APHY_COMB_EN = 1
557 06:02:18.066229 TX_ODT_DIS = 1
558 06:02:18.069528 NEW_8X_MODE = 1
559 06:02:18.073066 ===================================
560 06:02:18.076333 ===================================
561 06:02:18.079669 data_rate = 1600
562 06:02:18.080201 CKR = 1
563 06:02:18.083039 DQ_P2S_RATIO = 8
564 06:02:18.086412 ===================================
565 06:02:18.089561 CA_P2S_RATIO = 8
566 06:02:18.093245 DQ_CA_OPEN = 0
567 06:02:18.096829 DQ_SEMI_OPEN = 0
568 06:02:18.097368 CA_SEMI_OPEN = 0
569 06:02:18.100424 CA_FULL_RATE = 0
570 06:02:18.104453 DQ_CKDIV4_EN = 1
571 06:02:18.107737 CA_CKDIV4_EN = 1
572 06:02:18.108214 CA_PREDIV_EN = 0
573 06:02:18.111486 PH8_DLY = 0
574 06:02:18.114839 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 06:02:18.119056 DQ_AAMCK_DIV = 4
576 06:02:18.119519 CA_AAMCK_DIV = 4
577 06:02:18.122441 CA_ADMCK_DIV = 4
578 06:02:18.126707 DQ_TRACK_CA_EN = 0
579 06:02:18.129802 CA_PICK = 800
580 06:02:18.133370 CA_MCKIO = 800
581 06:02:18.133982 MCKIO_SEMI = 0
582 06:02:18.137525 PLL_FREQ = 3068
583 06:02:18.141062 DQ_UI_PI_RATIO = 32
584 06:02:18.144342 CA_UI_PI_RATIO = 0
585 06:02:18.144761 ===================================
586 06:02:18.148391 ===================================
587 06:02:18.152523 memory_type:LPDDR4
588 06:02:18.153034 GP_NUM : 10
589 06:02:18.155775 SRAM_EN : 1
590 06:02:18.159799 MD32_EN : 0
591 06:02:18.160243 ===================================
592 06:02:18.163224 [ANA_INIT] >>>>>>>>>>>>>>
593 06:02:18.166775 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 06:02:18.170555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 06:02:18.174394 ===================================
596 06:02:18.174810 data_rate = 1600,PCW = 0X7600
597 06:02:18.177815 ===================================
598 06:02:18.181278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 06:02:18.187672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 06:02:18.194421 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 06:02:18.197820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 06:02:18.201247 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 06:02:18.204647 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 06:02:18.208555 [ANA_INIT] flow start
605 06:02:18.209095 [ANA_INIT] PLL >>>>>>>>
606 06:02:18.212031 [ANA_INIT] PLL <<<<<<<<
607 06:02:18.215820 [ANA_INIT] MIDPI >>>>>>>>
608 06:02:18.216500 [ANA_INIT] MIDPI <<<<<<<<
609 06:02:18.219031 [ANA_INIT] DLL >>>>>>>>
610 06:02:18.219460 [ANA_INIT] flow end
611 06:02:18.223231 ============ LP4 DIFF to SE enter ============
612 06:02:18.230693 ============ LP4 DIFF to SE exit ============
613 06:02:18.231122 [ANA_INIT] <<<<<<<<<<<<<
614 06:02:18.234205 [Flow] Enable top DCM control >>>>>
615 06:02:18.237983 [Flow] Enable top DCM control <<<<<
616 06:02:18.241559 Enable DLL master slave shuffle
617 06:02:18.245834 ==============================================================
618 06:02:18.249006 Gating Mode config
619 06:02:18.252026 ==============================================================
620 06:02:18.255841 Config description:
621 06:02:18.265604 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 06:02:18.271866 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 06:02:18.275408 SELPH_MODE 0: By rank 1: By Phase
624 06:02:18.282008 ==============================================================
625 06:02:18.285229 GAT_TRACK_EN = 1
626 06:02:18.288637 RX_GATING_MODE = 2
627 06:02:18.292362 RX_GATING_TRACK_MODE = 2
628 06:02:18.295440 SELPH_MODE = 1
629 06:02:18.295979 PICG_EARLY_EN = 1
630 06:02:18.298949 VALID_LAT_VALUE = 1
631 06:02:18.305751 ==============================================================
632 06:02:18.309002 Enter into Gating configuration >>>>
633 06:02:18.312452 Exit from Gating configuration <<<<
634 06:02:18.315335 Enter into DVFS_PRE_config >>>>>
635 06:02:18.325853 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 06:02:18.329293 Exit from DVFS_PRE_config <<<<<
637 06:02:18.332074 Enter into PICG configuration >>>>
638 06:02:18.335647 Exit from PICG configuration <<<<
639 06:02:18.338803 [RX_INPUT] configuration >>>>>
640 06:02:18.342054 [RX_INPUT] configuration <<<<<
641 06:02:18.345704 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 06:02:18.352842 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 06:02:18.359127 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 06:02:18.365448 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 06:02:18.372339 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 06:02:18.375581 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 06:02:18.381871 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 06:02:18.385592 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 06:02:18.388922 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 06:02:18.392064 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 06:02:18.395662 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 06:02:18.402175 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 06:02:18.405769 ===================================
654 06:02:18.406444 LPDDR4 DRAM CONFIGURATION
655 06:02:18.409015 ===================================
656 06:02:18.412067 EX_ROW_EN[0] = 0x0
657 06:02:18.415297 EX_ROW_EN[1] = 0x0
658 06:02:18.415757 LP4Y_EN = 0x0
659 06:02:18.418727 WORK_FSP = 0x0
660 06:02:18.419152 WL = 0x2
661 06:02:18.421937 RL = 0x2
662 06:02:18.422529 BL = 0x2
663 06:02:18.425442 RPST = 0x0
664 06:02:18.425910 RD_PRE = 0x0
665 06:02:18.428842 WR_PRE = 0x1
666 06:02:18.429465 WR_PST = 0x0
667 06:02:18.432145 DBI_WR = 0x0
668 06:02:18.432712 DBI_RD = 0x0
669 06:02:18.435184 OTF = 0x1
670 06:02:18.438670 ===================================
671 06:02:18.442144 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 06:02:18.445068 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 06:02:18.452106 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 06:02:18.455534 ===================================
675 06:02:18.455959 LPDDR4 DRAM CONFIGURATION
676 06:02:18.458855 ===================================
677 06:02:18.462064 EX_ROW_EN[0] = 0x10
678 06:02:18.465518 EX_ROW_EN[1] = 0x0
679 06:02:18.466179 LP4Y_EN = 0x0
680 06:02:18.468849 WORK_FSP = 0x0
681 06:02:18.469268 WL = 0x2
682 06:02:18.471935 RL = 0x2
683 06:02:18.472350 BL = 0x2
684 06:02:18.475511 RPST = 0x0
685 06:02:18.475942 RD_PRE = 0x0
686 06:02:18.478438 WR_PRE = 0x1
687 06:02:18.478867 WR_PST = 0x0
688 06:02:18.481933 DBI_WR = 0x0
689 06:02:18.482351 DBI_RD = 0x0
690 06:02:18.485388 OTF = 0x1
691 06:02:18.488812 ===================================
692 06:02:18.495408 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 06:02:18.498658 nWR fixed to 40
694 06:02:18.499085 [ModeRegInit_LP4] CH0 RK0
695 06:02:18.502341 [ModeRegInit_LP4] CH0 RK1
696 06:02:18.505521 [ModeRegInit_LP4] CH1 RK0
697 06:02:18.508276 [ModeRegInit_LP4] CH1 RK1
698 06:02:18.508700 match AC timing 13
699 06:02:18.515455 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 06:02:18.518088 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 06:02:18.521994 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 06:02:18.528480 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 06:02:18.531558 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 06:02:18.531977 [EMI DOE] emi_dcm 0
705 06:02:18.538144 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 06:02:18.538565 ==
707 06:02:18.541819 Dram Type= 6, Freq= 0, CH_0, rank 0
708 06:02:18.545421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 06:02:18.545992 ==
710 06:02:18.552013 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 06:02:18.555147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 06:02:18.565978 [CA 0] Center 38 (7~69) winsize 63
713 06:02:18.569372 [CA 1] Center 38 (7~69) winsize 63
714 06:02:18.572302 [CA 2] Center 35 (5~66) winsize 62
715 06:02:18.575758 [CA 3] Center 35 (5~66) winsize 62
716 06:02:18.579304 [CA 4] Center 34 (4~65) winsize 62
717 06:02:18.582638 [CA 5] Center 34 (4~64) winsize 61
718 06:02:18.583160
719 06:02:18.585918 [CmdBusTrainingLP45] Vref(ca) range 1: 32
720 06:02:18.586346
721 06:02:18.588655 [CATrainingPosCal] consider 1 rank data
722 06:02:18.592090 u2DelayCellTimex100 = 270/100 ps
723 06:02:18.595707 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 06:02:18.599528 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
725 06:02:18.605707 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 06:02:18.609179 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 06:02:18.612550 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 06:02:18.615680 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
729 06:02:18.616103
730 06:02:18.618992 CA PerBit enable=1, Macro0, CA PI delay=34
731 06:02:18.619462
732 06:02:18.622372 [CBTSetCACLKResult] CA Dly = 34
733 06:02:18.622789 CS Dly: 6 (0~37)
734 06:02:18.623119 ==
735 06:02:18.625957 Dram Type= 6, Freq= 0, CH_0, rank 1
736 06:02:18.632447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 06:02:18.632868 ==
738 06:02:18.635363 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 06:02:18.642207 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 06:02:18.652277 [CA 0] Center 38 (7~69) winsize 63
741 06:02:18.656248 [CA 1] Center 38 (7~69) winsize 63
742 06:02:18.659580 [CA 2] Center 35 (5~66) winsize 62
743 06:02:18.663000 [CA 3] Center 35 (5~66) winsize 62
744 06:02:18.667109 [CA 4] Center 34 (4~65) winsize 62
745 06:02:18.670751 [CA 5] Center 34 (4~65) winsize 62
746 06:02:18.671264
747 06:02:18.673642 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 06:02:18.674069
749 06:02:18.677790 [CATrainingPosCal] consider 2 rank data
750 06:02:18.681281 u2DelayCellTimex100 = 270/100 ps
751 06:02:18.684580 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 06:02:18.687962 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
753 06:02:18.691380 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 06:02:18.694906 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 06:02:18.698761 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 06:02:18.701792 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 06:02:18.702211
758 06:02:18.705394 CA PerBit enable=1, Macro0, CA PI delay=34
759 06:02:18.705842
760 06:02:18.709373 [CBTSetCACLKResult] CA Dly = 34
761 06:02:18.709835 CS Dly: 6 (0~38)
762 06:02:18.710169
763 06:02:18.712783 ----->DramcWriteLeveling(PI) begin...
764 06:02:18.713302 ==
765 06:02:18.716759 Dram Type= 6, Freq= 0, CH_0, rank 0
766 06:02:18.720193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 06:02:18.720618 ==
768 06:02:18.723856 Write leveling (Byte 0): 32 => 32
769 06:02:18.727213 Write leveling (Byte 1): 32 => 32
770 06:02:18.731240 DramcWriteLeveling(PI) end<-----
771 06:02:18.731787
772 06:02:18.732299 ==
773 06:02:18.734614 Dram Type= 6, Freq= 0, CH_0, rank 0
774 06:02:18.738636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 06:02:18.739053 ==
776 06:02:18.742328 [Gating] SW mode calibration
777 06:02:18.749420 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 06:02:18.753577 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 06:02:18.757021 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 06:02:18.760524 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 06:02:18.768209 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
782 06:02:18.771554 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 06:02:18.775664 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
784 06:02:18.779643 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 06:02:18.782801 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 06:02:18.786969 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 06:02:18.793754 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 06:02:18.797422 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 06:02:18.801257 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 06:02:18.804736 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 06:02:18.812196 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 06:02:18.816204 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 06:02:18.819770 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 06:02:18.823456 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 06:02:18.826686 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 06:02:18.834056 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 06:02:18.838082 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
798 06:02:18.842103 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 06:02:18.845643 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 06:02:18.848894 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 06:02:18.852805 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 06:02:18.860115 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 06:02:18.864102 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 06:02:18.867816 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 06:02:18.871405 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 06:02:18.874887 0 9 12 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
807 06:02:18.882425 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 06:02:18.886436 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 06:02:18.889891 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 06:02:18.893320 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 06:02:18.897264 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 06:02:18.904926 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
813 06:02:18.907892 0 10 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
814 06:02:18.911901 0 10 12 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
815 06:02:18.915449 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 06:02:18.919363 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 06:02:18.922748 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 06:02:18.930333 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 06:02:18.933998 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 06:02:18.937385 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 06:02:18.941648 0 11 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
822 06:02:18.945081 0 11 12 | B1->B0 | 3030 4343 | 0 0 | (0 0) (0 0)
823 06:02:18.952322 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 06:02:18.956045 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 06:02:18.960229 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 06:02:18.963928 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 06:02:18.967804 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 06:02:18.971582 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 06:02:18.979275 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 06:02:18.981948 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 06:02:18.985345 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 06:02:18.992385 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 06:02:18.995484 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 06:02:18.998477 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 06:02:19.001892 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 06:02:19.008704 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 06:02:19.011966 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 06:02:19.015547 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 06:02:19.022045 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 06:02:19.025940 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 06:02:19.028877 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 06:02:19.035342 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 06:02:19.038253 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 06:02:19.041807 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 06:02:19.048794 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 06:02:19.051693 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 06:02:19.055176 Total UI for P1: 0, mck2ui 16
848 06:02:19.058376 best dqsien dly found for B0: ( 0, 14, 10)
849 06:02:19.061775 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 06:02:19.064895 Total UI for P1: 0, mck2ui 16
851 06:02:19.068320 best dqsien dly found for B1: ( 0, 14, 12)
852 06:02:19.071776 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
853 06:02:19.075148 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 06:02:19.075332
855 06:02:19.081676 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 06:02:19.085024 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 06:02:19.085289 [Gating] SW calibration Done
858 06:02:19.088312 ==
859 06:02:19.091913 Dram Type= 6, Freq= 0, CH_0, rank 0
860 06:02:19.095079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 06:02:19.095348 ==
862 06:02:19.095509 RX Vref Scan: 0
863 06:02:19.095655
864 06:02:19.098979 RX Vref 0 -> 0, step: 1
865 06:02:19.099244
866 06:02:19.101690 RX Delay -130 -> 252, step: 16
867 06:02:19.105198 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
868 06:02:19.108769 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
869 06:02:19.115622 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 06:02:19.118367 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 06:02:19.121596 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
872 06:02:19.125612 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 06:02:19.128509 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 06:02:19.132022 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 06:02:19.138720 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 06:02:19.142436 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 06:02:19.145597 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 06:02:19.148819 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 06:02:19.152479 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 06:02:19.158908 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 06:02:19.162239 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 06:02:19.165852 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 06:02:19.166377 ==
884 06:02:19.168434 Dram Type= 6, Freq= 0, CH_0, rank 0
885 06:02:19.172085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 06:02:19.175439 ==
887 06:02:19.175959 DQS Delay:
888 06:02:19.176302 DQS0 = 0, DQS1 = 0
889 06:02:19.178237 DQM Delay:
890 06:02:19.178661 DQM0 = 79, DQM1 = 69
891 06:02:19.181767 DQ Delay:
892 06:02:19.182195 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77
893 06:02:19.184850 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
894 06:02:19.188308 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 06:02:19.191584 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 06:02:19.192010
897 06:02:19.195439
898 06:02:19.195862 ==
899 06:02:19.198845 Dram Type= 6, Freq= 0, CH_0, rank 0
900 06:02:19.202768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 06:02:19.203193 ==
902 06:02:19.203529
903 06:02:19.203842
904 06:02:19.204345 TX Vref Scan disable
905 06:02:19.206194 == TX Byte 0 ==
906 06:02:19.209646 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
907 06:02:19.216459 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
908 06:02:19.216990 == TX Byte 1 ==
909 06:02:19.219647 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
910 06:02:19.225879 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
911 06:02:19.226307 ==
912 06:02:19.229235 Dram Type= 6, Freq= 0, CH_0, rank 0
913 06:02:19.232680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 06:02:19.233206 ==
915 06:02:19.244794 TX Vref=22, minBit 14, minWin=26, winSum=436
916 06:02:19.248452 TX Vref=24, minBit 0, minWin=27, winSum=439
917 06:02:19.252271 TX Vref=26, minBit 0, minWin=27, winSum=444
918 06:02:19.255162 TX Vref=28, minBit 4, minWin=27, winSum=443
919 06:02:19.258526 TX Vref=30, minBit 9, minWin=27, winSum=442
920 06:02:19.262231 TX Vref=32, minBit 4, minWin=27, winSum=443
921 06:02:19.269062 [TxChooseVref] Worse bit 0, Min win 27, Win sum 444, Final Vref 26
922 06:02:19.269761
923 06:02:19.271562 Final TX Range 1 Vref 26
924 06:02:19.271988
925 06:02:19.272324 ==
926 06:02:19.275343 Dram Type= 6, Freq= 0, CH_0, rank 0
927 06:02:19.278992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 06:02:19.279521 ==
929 06:02:19.279865
930 06:02:19.281643
931 06:02:19.282084 TX Vref Scan disable
932 06:02:19.285358 == TX Byte 0 ==
933 06:02:19.288086 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
934 06:02:19.291855 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
935 06:02:19.295229 == TX Byte 1 ==
936 06:02:19.298396 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
937 06:02:19.301840 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
938 06:02:19.305178
939 06:02:19.305643 [DATLAT]
940 06:02:19.305982 Freq=800, CH0 RK0
941 06:02:19.306300
942 06:02:19.308380 DATLAT Default: 0xa
943 06:02:19.308802 0, 0xFFFF, sum = 0
944 06:02:19.311772 1, 0xFFFF, sum = 0
945 06:02:19.312192 2, 0xFFFF, sum = 0
946 06:02:19.315529 3, 0xFFFF, sum = 0
947 06:02:19.316057 4, 0xFFFF, sum = 0
948 06:02:19.318077 5, 0xFFFF, sum = 0
949 06:02:19.321578 6, 0xFFFF, sum = 0
950 06:02:19.322187 7, 0xFFFF, sum = 0
951 06:02:19.325049 8, 0xFFFF, sum = 0
952 06:02:19.325470 9, 0x0, sum = 1
953 06:02:19.325886 10, 0x0, sum = 2
954 06:02:19.328763 11, 0x0, sum = 3
955 06:02:19.329299 12, 0x0, sum = 4
956 06:02:19.332007 best_step = 10
957 06:02:19.332540
958 06:02:19.332876 ==
959 06:02:19.335267 Dram Type= 6, Freq= 0, CH_0, rank 0
960 06:02:19.338794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 06:02:19.339214 ==
962 06:02:19.341664 RX Vref Scan: 1
963 06:02:19.342079
964 06:02:19.342408 Set Vref Range= 32 -> 127
965 06:02:19.342766
966 06:02:19.345215 RX Vref 32 -> 127, step: 1
967 06:02:19.345748
968 06:02:19.348422 RX Delay -111 -> 252, step: 8
969 06:02:19.348804
970 06:02:19.351837 Set Vref, RX VrefLevel [Byte0]: 32
971 06:02:19.355340 [Byte1]: 32
972 06:02:19.355880
973 06:02:19.358364 Set Vref, RX VrefLevel [Byte0]: 33
974 06:02:19.362365 [Byte1]: 33
975 06:02:19.365446
976 06:02:19.365914 Set Vref, RX VrefLevel [Byte0]: 34
977 06:02:19.369348 [Byte1]: 34
978 06:02:19.373338
979 06:02:19.373959 Set Vref, RX VrefLevel [Byte0]: 35
980 06:02:19.376295 [Byte1]: 35
981 06:02:19.380996
982 06:02:19.381551 Set Vref, RX VrefLevel [Byte0]: 36
983 06:02:19.384271 [Byte1]: 36
984 06:02:19.388750
985 06:02:19.389283 Set Vref, RX VrefLevel [Byte0]: 37
986 06:02:19.392331 [Byte1]: 37
987 06:02:19.396061
988 06:02:19.396582 Set Vref, RX VrefLevel [Byte0]: 38
989 06:02:19.399693 [Byte1]: 38
990 06:02:19.404331
991 06:02:19.404847 Set Vref, RX VrefLevel [Byte0]: 39
992 06:02:19.407004 [Byte1]: 39
993 06:02:19.411681
994 06:02:19.412196 Set Vref, RX VrefLevel [Byte0]: 40
995 06:02:19.415209 [Byte1]: 40
996 06:02:19.419077
997 06:02:19.419493 Set Vref, RX VrefLevel [Byte0]: 41
998 06:02:19.421992 [Byte1]: 41
999 06:02:19.427005
1000 06:02:19.427520 Set Vref, RX VrefLevel [Byte0]: 42
1001 06:02:19.430283 [Byte1]: 42
1002 06:02:19.434038
1003 06:02:19.434451 Set Vref, RX VrefLevel [Byte0]: 43
1004 06:02:19.437441 [Byte1]: 43
1005 06:02:19.442199
1006 06:02:19.442765 Set Vref, RX VrefLevel [Byte0]: 44
1007 06:02:19.445538 [Byte1]: 44
1008 06:02:19.449621
1009 06:02:19.450236 Set Vref, RX VrefLevel [Byte0]: 45
1010 06:02:19.453197 [Byte1]: 45
1011 06:02:19.457330
1012 06:02:19.457837 Set Vref, RX VrefLevel [Byte0]: 46
1013 06:02:19.460753 [Byte1]: 46
1014 06:02:19.465255
1015 06:02:19.465728 Set Vref, RX VrefLevel [Byte0]: 47
1016 06:02:19.468810 [Byte1]: 47
1017 06:02:19.472875
1018 06:02:19.473302 Set Vref, RX VrefLevel [Byte0]: 48
1019 06:02:19.475706 [Byte1]: 48
1020 06:02:19.480199
1021 06:02:19.480641 Set Vref, RX VrefLevel [Byte0]: 49
1022 06:02:19.483464 [Byte1]: 49
1023 06:02:19.487873
1024 06:02:19.488290 Set Vref, RX VrefLevel [Byte0]: 50
1025 06:02:19.491242 [Byte1]: 50
1026 06:02:19.495402
1027 06:02:19.495808 Set Vref, RX VrefLevel [Byte0]: 51
1028 06:02:19.498651 [Byte1]: 51
1029 06:02:19.503242
1030 06:02:19.503666 Set Vref, RX VrefLevel [Byte0]: 52
1031 06:02:19.506141 [Byte1]: 52
1032 06:02:19.510948
1033 06:02:19.511473 Set Vref, RX VrefLevel [Byte0]: 53
1034 06:02:19.514184 [Byte1]: 53
1035 06:02:19.518196
1036 06:02:19.518634 Set Vref, RX VrefLevel [Byte0]: 54
1037 06:02:19.521616 [Byte1]: 54
1038 06:02:19.526041
1039 06:02:19.526480 Set Vref, RX VrefLevel [Byte0]: 55
1040 06:02:19.529356 [Byte1]: 55
1041 06:02:19.533579
1042 06:02:19.533995 Set Vref, RX VrefLevel [Byte0]: 56
1043 06:02:19.536855 [Byte1]: 56
1044 06:02:19.541267
1045 06:02:19.541735 Set Vref, RX VrefLevel [Byte0]: 57
1046 06:02:19.544766 [Byte1]: 57
1047 06:02:19.548867
1048 06:02:19.549280 Set Vref, RX VrefLevel [Byte0]: 58
1049 06:02:19.552395 [Byte1]: 58
1050 06:02:19.556324
1051 06:02:19.556749 Set Vref, RX VrefLevel [Byte0]: 59
1052 06:02:19.560178 [Byte1]: 59
1053 06:02:19.564847
1054 06:02:19.565366 Set Vref, RX VrefLevel [Byte0]: 60
1055 06:02:19.567764 [Byte1]: 60
1056 06:02:19.571654
1057 06:02:19.572072 Set Vref, RX VrefLevel [Byte0]: 61
1058 06:02:19.575378 [Byte1]: 61
1059 06:02:19.579911
1060 06:02:19.580430 Set Vref, RX VrefLevel [Byte0]: 62
1061 06:02:19.583077 [Byte1]: 62
1062 06:02:19.587064
1063 06:02:19.587646 Set Vref, RX VrefLevel [Byte0]: 63
1064 06:02:19.590568 [Byte1]: 63
1065 06:02:19.594960
1066 06:02:19.595484 Set Vref, RX VrefLevel [Byte0]: 64
1067 06:02:19.597760 [Byte1]: 64
1068 06:02:19.602381
1069 06:02:19.602893 Set Vref, RX VrefLevel [Byte0]: 65
1070 06:02:19.606031 [Byte1]: 65
1071 06:02:19.610403
1072 06:02:19.610919 Set Vref, RX VrefLevel [Byte0]: 66
1073 06:02:19.613273 [Byte1]: 66
1074 06:02:19.618105
1075 06:02:19.618629 Set Vref, RX VrefLevel [Byte0]: 67
1076 06:02:19.620774 [Byte1]: 67
1077 06:02:19.625591
1078 06:02:19.626006 Set Vref, RX VrefLevel [Byte0]: 68
1079 06:02:19.628779 [Byte1]: 68
1080 06:02:19.633028
1081 06:02:19.633729 Set Vref, RX VrefLevel [Byte0]: 69
1082 06:02:19.636210 [Byte1]: 69
1083 06:02:19.640595
1084 06:02:19.641068 Set Vref, RX VrefLevel [Byte0]: 70
1085 06:02:19.644053 [Byte1]: 70
1086 06:02:19.648671
1087 06:02:19.649194 Set Vref, RX VrefLevel [Byte0]: 71
1088 06:02:19.652030 [Byte1]: 71
1089 06:02:19.656015
1090 06:02:19.656533 Set Vref, RX VrefLevel [Byte0]: 72
1091 06:02:19.659653 [Byte1]: 72
1092 06:02:19.663270
1093 06:02:19.663709 Set Vref, RX VrefLevel [Byte0]: 73
1094 06:02:19.666817 [Byte1]: 73
1095 06:02:19.671668
1096 06:02:19.672188 Set Vref, RX VrefLevel [Byte0]: 74
1097 06:02:19.674426 [Byte1]: 74
1098 06:02:19.679446
1099 06:02:19.679962 Set Vref, RX VrefLevel [Byte0]: 75
1100 06:02:19.682139 [Byte1]: 75
1101 06:02:19.686407
1102 06:02:19.686904 Set Vref, RX VrefLevel [Byte0]: 76
1103 06:02:19.689420 [Byte1]: 76
1104 06:02:19.694263
1105 06:02:19.694777 Set Vref, RX VrefLevel [Byte0]: 77
1106 06:02:19.697635 [Byte1]: 77
1107 06:02:19.702299
1108 06:02:19.702810 Set Vref, RX VrefLevel [Byte0]: 78
1109 06:02:19.705177 [Byte1]: 78
1110 06:02:19.710101
1111 06:02:19.710609 Set Vref, RX VrefLevel [Byte0]: 79
1112 06:02:19.713061 [Byte1]: 79
1113 06:02:19.717020
1114 06:02:19.717560 Set Vref, RX VrefLevel [Byte0]: 80
1115 06:02:19.720452 [Byte1]: 80
1116 06:02:19.724617
1117 06:02:19.725029 Final RX Vref Byte 0 = 59 to rank0
1118 06:02:19.727885 Final RX Vref Byte 1 = 59 to rank0
1119 06:02:19.731328 Final RX Vref Byte 0 = 59 to rank1
1120 06:02:19.734648 Final RX Vref Byte 1 = 59 to rank1==
1121 06:02:19.738169 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 06:02:19.744756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 06:02:19.745176 ==
1124 06:02:19.745548 DQS Delay:
1125 06:02:19.745869 DQS0 = 0, DQS1 = 0
1126 06:02:19.748446 DQM Delay:
1127 06:02:19.748973 DQM0 = 82, DQM1 = 68
1128 06:02:19.751170 DQ Delay:
1129 06:02:19.754490 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1130 06:02:19.754909 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1131 06:02:19.758403 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1132 06:02:19.761809 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =76
1133 06:02:19.764756
1134 06:02:19.765269
1135 06:02:19.771374 [DQSOSCAuto] RK0, (LSB)MR18= 0x2524, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1136 06:02:19.775071 CH0 RK0: MR19=606, MR18=2524
1137 06:02:19.781818 CH0_RK0: MR19=0x606, MR18=0x2524, DQSOSC=400, MR23=63, INC=92, DEC=61
1138 06:02:19.782339
1139 06:02:19.785163 ----->DramcWriteLeveling(PI) begin...
1140 06:02:19.785727 ==
1141 06:02:19.788134 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 06:02:19.791285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 06:02:19.791709 ==
1144 06:02:19.794758 Write leveling (Byte 0): 31 => 31
1145 06:02:19.798224 Write leveling (Byte 1): 31 => 31
1146 06:02:19.801546 DramcWriteLeveling(PI) end<-----
1147 06:02:19.802067
1148 06:02:19.802400 ==
1149 06:02:19.805346 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 06:02:19.808144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 06:02:19.808672 ==
1152 06:02:19.811298 [Gating] SW mode calibration
1153 06:02:19.818023 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 06:02:19.824751 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 06:02:19.828474 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 06:02:19.831664 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 06:02:19.838016 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1158 06:02:19.841770 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 06:02:19.844565 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 06:02:19.851545 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 06:02:19.854818 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 06:02:19.858069 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 06:02:19.865095 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 06:02:19.868547 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 06:02:19.871882 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 06:02:19.916383 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 06:02:19.916963 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 06:02:19.917674 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 06:02:19.918019 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 06:02:19.918339 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 06:02:19.918697 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1172 06:02:19.918992 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1173 06:02:19.919275 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1174 06:02:19.919554 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 06:02:19.919881 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 06:02:19.959378 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 06:02:19.960338 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 06:02:19.960774 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 06:02:19.961095 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 06:02:19.961514 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1181 06:02:19.961934 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1182 06:02:19.962247 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1183 06:02:19.962540 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 06:02:19.962825 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 06:02:19.963106 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 06:02:19.964429 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 06:02:19.967599 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 06:02:19.974348 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1189 06:02:19.977705 0 10 8 | B1->B0 | 3131 2626 | 0 0 | (0 1) (0 0)
1190 06:02:19.981369 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1191 06:02:19.988070 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 06:02:19.991306 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 06:02:19.994591 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 06:02:19.997996 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 06:02:20.004612 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 06:02:20.008330 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
1197 06:02:20.011096 0 11 8 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (0 0)
1198 06:02:20.017793 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1199 06:02:20.020953 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 06:02:20.024398 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 06:02:20.030897 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 06:02:20.034940 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 06:02:20.038363 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 06:02:20.042215 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1205 06:02:20.049757 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1206 06:02:20.053221 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 06:02:20.056059 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 06:02:20.060023 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 06:02:20.067222 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 06:02:20.070523 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 06:02:20.073750 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 06:02:20.077095 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 06:02:20.083930 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 06:02:20.086949 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 06:02:20.090626 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 06:02:20.097225 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 06:02:20.100484 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 06:02:20.103449 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 06:02:20.110241 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 06:02:20.113523 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1221 06:02:20.117401 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1222 06:02:20.120432 Total UI for P1: 0, mck2ui 16
1223 06:02:20.123622 best dqsien dly found for B0: ( 0, 14, 4)
1224 06:02:20.130339 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 06:02:20.130859 Total UI for P1: 0, mck2ui 16
1226 06:02:20.136899 best dqsien dly found for B1: ( 0, 14, 8)
1227 06:02:20.139804 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1228 06:02:20.143813 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 06:02:20.144331
1230 06:02:20.146856 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1231 06:02:20.149765 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 06:02:20.153534 [Gating] SW calibration Done
1233 06:02:20.154051 ==
1234 06:02:20.156864 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 06:02:20.159808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 06:02:20.160322 ==
1237 06:02:20.162905 RX Vref Scan: 0
1238 06:02:20.163390
1239 06:02:20.163715 RX Vref 0 -> 0, step: 1
1240 06:02:20.164013
1241 06:02:20.166383 RX Delay -130 -> 252, step: 16
1242 06:02:20.173219 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1243 06:02:20.176737 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1244 06:02:20.180241 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1245 06:02:20.183244 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1246 06:02:20.186331 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1247 06:02:20.192986 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1248 06:02:20.196533 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1249 06:02:20.199630 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1250 06:02:20.203234 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1251 06:02:20.206079 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1252 06:02:20.209726 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1253 06:02:20.216491 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1254 06:02:20.219671 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1255 06:02:20.223162 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1256 06:02:20.226199 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1257 06:02:20.232589 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1258 06:02:20.233006 ==
1259 06:02:20.236445 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 06:02:20.239558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 06:02:20.240077 ==
1262 06:02:20.240578 DQS Delay:
1263 06:02:20.242487 DQS0 = 0, DQS1 = 0
1264 06:02:20.242900 DQM Delay:
1265 06:02:20.245899 DQM0 = 76, DQM1 = 69
1266 06:02:20.246313 DQ Delay:
1267 06:02:20.249339 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1268 06:02:20.253047 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1269 06:02:20.256049 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1270 06:02:20.259720 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1271 06:02:20.260239
1272 06:02:20.260637
1273 06:02:20.260951 ==
1274 06:02:20.262749 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 06:02:20.266410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 06:02:20.266937 ==
1277 06:02:20.267270
1278 06:02:20.267572
1279 06:02:20.270038 TX Vref Scan disable
1280 06:02:20.273054 == TX Byte 0 ==
1281 06:02:20.276447 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1282 06:02:20.279063 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1283 06:02:20.282751 == TX Byte 1 ==
1284 06:02:20.285888 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1285 06:02:20.288940 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1286 06:02:20.289360 ==
1287 06:02:20.292901 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 06:02:20.298945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 06:02:20.299362 ==
1290 06:02:20.311009 TX Vref=22, minBit 12, minWin=26, winSum=433
1291 06:02:20.314211 TX Vref=24, minBit 1, minWin=27, winSum=438
1292 06:02:20.317575 TX Vref=26, minBit 1, minWin=27, winSum=442
1293 06:02:20.320408 TX Vref=28, minBit 1, minWin=27, winSum=439
1294 06:02:20.323839 TX Vref=30, minBit 1, minWin=27, winSum=441
1295 06:02:20.330756 TX Vref=32, minBit 1, minWin=27, winSum=444
1296 06:02:20.334402 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 32
1297 06:02:20.334809
1298 06:02:20.337390 Final TX Range 1 Vref 32
1299 06:02:20.337845
1300 06:02:20.338165 ==
1301 06:02:20.340657 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 06:02:20.344227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 06:02:20.344649 ==
1304 06:02:20.347667
1305 06:02:20.348237
1306 06:02:20.348567 TX Vref Scan disable
1307 06:02:20.350465 == TX Byte 0 ==
1308 06:02:20.354461 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1309 06:02:20.357618 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1310 06:02:20.360818 == TX Byte 1 ==
1311 06:02:20.364043 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1312 06:02:20.367495 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1313 06:02:20.371026
1314 06:02:20.371447 [DATLAT]
1315 06:02:20.371798 Freq=800, CH0 RK1
1316 06:02:20.372102
1317 06:02:20.374421 DATLAT Default: 0xa
1318 06:02:20.374823 0, 0xFFFF, sum = 0
1319 06:02:20.377185 1, 0xFFFF, sum = 0
1320 06:02:20.377629 2, 0xFFFF, sum = 0
1321 06:02:20.380785 3, 0xFFFF, sum = 0
1322 06:02:20.381193 4, 0xFFFF, sum = 0
1323 06:02:20.384164 5, 0xFFFF, sum = 0
1324 06:02:20.384575 6, 0xFFFF, sum = 0
1325 06:02:20.387501 7, 0xFFFF, sum = 0
1326 06:02:20.390462 8, 0xFFFF, sum = 0
1327 06:02:20.390870 9, 0x0, sum = 1
1328 06:02:20.391266 10, 0x0, sum = 2
1329 06:02:20.394609 11, 0x0, sum = 3
1330 06:02:20.395117 12, 0x0, sum = 4
1331 06:02:20.397770 best_step = 10
1332 06:02:20.398388
1333 06:02:20.398722 ==
1334 06:02:20.400785 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 06:02:20.403963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 06:02:20.404378 ==
1337 06:02:20.408213 RX Vref Scan: 0
1338 06:02:20.408716
1339 06:02:20.409035 RX Vref 0 -> 0, step: 1
1340 06:02:20.409328
1341 06:02:20.410426 RX Delay -111 -> 252, step: 8
1342 06:02:20.417381 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1343 06:02:20.420991 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1344 06:02:20.424080 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1345 06:02:20.427707 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1346 06:02:20.430511 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1347 06:02:20.437583 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1348 06:02:20.440616 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1349 06:02:20.444267 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1350 06:02:20.447732 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1351 06:02:20.450907 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1352 06:02:20.457298 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1353 06:02:20.461100 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1354 06:02:20.464444 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1355 06:02:20.467490 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1356 06:02:20.470635 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1357 06:02:20.477569 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1358 06:02:20.478069 ==
1359 06:02:20.480691 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 06:02:20.483834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 06:02:20.484249 ==
1362 06:02:20.484569 DQS Delay:
1363 06:02:20.487726 DQS0 = 0, DQS1 = 0
1364 06:02:20.488228 DQM Delay:
1365 06:02:20.491004 DQM0 = 80, DQM1 = 70
1366 06:02:20.491438 DQ Delay:
1367 06:02:20.493931 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1368 06:02:20.497331 DQ4 =84, DQ5 =64, DQ6 =92, DQ7 =88
1369 06:02:20.500599 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1370 06:02:20.504379 DQ12 =76, DQ13 =72, DQ14 =80, DQ15 =76
1371 06:02:20.504886
1372 06:02:20.505208
1373 06:02:20.514161 [DQSOSCAuto] RK1, (LSB)MR18= 0x4520, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1374 06:02:20.514668 CH0 RK1: MR19=606, MR18=4520
1375 06:02:20.520763 CH0_RK1: MR19=0x606, MR18=0x4520, DQSOSC=392, MR23=63, INC=96, DEC=64
1376 06:02:20.523854 [RxdqsGatingPostProcess] freq 800
1377 06:02:20.530576 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 06:02:20.533942 Pre-setting of DQS Precalculation
1379 06:02:20.537344 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 06:02:20.537794 ==
1381 06:02:20.540490 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 06:02:20.543963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 06:02:20.547068 ==
1384 06:02:20.550648 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 06:02:20.557111 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 06:02:20.566053 [CA 0] Center 36 (6~66) winsize 61
1387 06:02:20.569644 [CA 1] Center 36 (6~67) winsize 62
1388 06:02:20.572189 [CA 2] Center 34 (5~64) winsize 60
1389 06:02:20.575782 [CA 3] Center 34 (4~64) winsize 61
1390 06:02:20.579355 [CA 4] Center 34 (4~65) winsize 62
1391 06:02:20.582727 [CA 5] Center 34 (4~64) winsize 61
1392 06:02:20.583263
1393 06:02:20.586024 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 06:02:20.586430
1395 06:02:20.588839 [CATrainingPosCal] consider 1 rank data
1396 06:02:20.592110 u2DelayCellTimex100 = 270/100 ps
1397 06:02:20.595480 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1398 06:02:20.599108 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 06:02:20.605468 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1400 06:02:20.608864 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1401 06:02:20.612343 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 06:02:20.615586 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1403 06:02:20.616390
1404 06:02:20.618567 CA PerBit enable=1, Macro0, CA PI delay=34
1405 06:02:20.619199
1406 06:02:20.622118 [CBTSetCACLKResult] CA Dly = 34
1407 06:02:20.622709 CS Dly: 5 (0~36)
1408 06:02:20.625461 ==
1409 06:02:20.625913 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 06:02:20.632120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 06:02:20.632346 ==
1412 06:02:20.635148 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 06:02:20.641778 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 06:02:20.651801 [CA 0] Center 37 (7~67) winsize 61
1415 06:02:20.654743 [CA 1] Center 36 (6~67) winsize 62
1416 06:02:20.658301 [CA 2] Center 35 (5~65) winsize 61
1417 06:02:20.661440 [CA 3] Center 33 (3~64) winsize 62
1418 06:02:20.665132 [CA 4] Center 34 (4~65) winsize 62
1419 06:02:20.668545 [CA 5] Center 33 (3~64) winsize 62
1420 06:02:20.668793
1421 06:02:20.671878 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 06:02:20.672389
1423 06:02:20.675180 [CATrainingPosCal] consider 2 rank data
1424 06:02:20.678551 u2DelayCellTimex100 = 270/100 ps
1425 06:02:20.681765 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1426 06:02:20.685144 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 06:02:20.691942 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1428 06:02:20.695921 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 06:02:20.696330 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 06:02:20.702757 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1431 06:02:20.703168
1432 06:02:20.706284 CA PerBit enable=1, Macro0, CA PI delay=34
1433 06:02:20.706695
1434 06:02:20.707014 [CBTSetCACLKResult] CA Dly = 34
1435 06:02:20.709791 CS Dly: 6 (0~38)
1436 06:02:20.710198
1437 06:02:20.713405 ----->DramcWriteLeveling(PI) begin...
1438 06:02:20.713970 ==
1439 06:02:20.717667 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 06:02:20.721011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 06:02:20.721417 ==
1442 06:02:20.724990 Write leveling (Byte 0): 29 => 29
1443 06:02:20.728556 Write leveling (Byte 1): 29 => 29
1444 06:02:20.731604 DramcWriteLeveling(PI) end<-----
1445 06:02:20.732019
1446 06:02:20.732343 ==
1447 06:02:20.735050 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 06:02:20.738603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 06:02:20.739012 ==
1450 06:02:20.741979 [Gating] SW mode calibration
1451 06:02:20.748493 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 06:02:20.751835 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 06:02:20.758267 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 06:02:20.761555 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1455 06:02:20.765288 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 06:02:20.771887 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 06:02:20.775033 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 06:02:20.778936 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 06:02:20.785087 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 06:02:20.788836 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 06:02:20.791869 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 06:02:20.798951 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 06:02:20.802229 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 06:02:20.805681 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 06:02:20.812044 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 06:02:20.815336 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 06:02:20.819059 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 06:02:20.825238 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 06:02:20.828798 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 06:02:20.831611 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1471 06:02:20.835475 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1472 06:02:20.842055 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 06:02:20.845645 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 06:02:20.849016 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 06:02:20.855397 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 06:02:20.858763 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 06:02:20.862372 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 06:02:20.868676 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 06:02:20.872115 0 9 8 | B1->B0 | 2727 2828 | 0 1 | (0 0) (1 1)
1480 06:02:20.875670 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 06:02:20.882470 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 06:02:20.885929 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 06:02:20.889132 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 06:02:20.895465 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 06:02:20.899283 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 06:02:20.902223 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1487 06:02:20.906086 0 10 8 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 0)
1488 06:02:20.912329 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1489 06:02:20.915601 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 06:02:20.922101 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 06:02:20.925369 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 06:02:20.928838 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 06:02:20.931712 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 06:02:20.938988 0 11 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1495 06:02:20.941744 0 11 8 | B1->B0 | 3939 3434 | 0 0 | (0 0) (1 1)
1496 06:02:20.945439 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 06:02:20.951842 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 06:02:20.955380 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 06:02:20.961462 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 06:02:20.965160 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 06:02:20.968255 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 06:02:20.972080 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 06:02:20.978544 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1504 06:02:20.981736 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 06:02:20.984701 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 06:02:20.991449 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 06:02:20.994779 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 06:02:20.998444 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 06:02:21.004817 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 06:02:21.008162 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 06:02:21.011615 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 06:02:21.017885 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 06:02:21.021213 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 06:02:21.024976 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 06:02:21.031213 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 06:02:21.034525 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 06:02:21.038026 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 06:02:21.044253 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 06:02:21.047617 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1520 06:02:21.051143 Total UI for P1: 0, mck2ui 16
1521 06:02:21.054550 best dqsien dly found for B0: ( 0, 14, 6)
1522 06:02:21.057763 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 06:02:21.060972 Total UI for P1: 0, mck2ui 16
1524 06:02:21.064561 best dqsien dly found for B1: ( 0, 14, 8)
1525 06:02:21.068073 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1526 06:02:21.071529 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1527 06:02:21.072050
1528 06:02:21.074498 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1529 06:02:21.081436 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1530 06:02:21.082006 [Gating] SW calibration Done
1531 06:02:21.082347 ==
1532 06:02:21.084860 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 06:02:21.091482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 06:02:21.092019 ==
1535 06:02:21.092361 RX Vref Scan: 0
1536 06:02:21.092673
1537 06:02:21.094625 RX Vref 0 -> 0, step: 1
1538 06:02:21.095053
1539 06:02:21.097700 RX Delay -130 -> 252, step: 16
1540 06:02:21.100999 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1541 06:02:21.104613 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1542 06:02:21.107962 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1543 06:02:21.114386 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1544 06:02:21.117781 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1545 06:02:21.121001 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1546 06:02:21.124192 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1547 06:02:21.127838 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1548 06:02:21.134504 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1549 06:02:21.138090 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1550 06:02:21.140914 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1551 06:02:21.144691 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1552 06:02:21.147857 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1553 06:02:21.154254 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1554 06:02:21.157663 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1555 06:02:21.161445 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1556 06:02:21.162001 ==
1557 06:02:21.164563 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 06:02:21.167797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 06:02:21.168347 ==
1560 06:02:21.171667 DQS Delay:
1561 06:02:21.172187 DQS0 = 0, DQS1 = 0
1562 06:02:21.174293 DQM Delay:
1563 06:02:21.174710 DQM0 = 81, DQM1 = 72
1564 06:02:21.175043 DQ Delay:
1565 06:02:21.177690 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1566 06:02:21.181513 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1567 06:02:21.184798 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1568 06:02:21.187345 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1569 06:02:21.187967
1570 06:02:21.188516
1571 06:02:21.189030 ==
1572 06:02:21.190478 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 06:02:21.197674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 06:02:21.198095 ==
1575 06:02:21.198460
1576 06:02:21.198780
1577 06:02:21.199083 TX Vref Scan disable
1578 06:02:21.201152 == TX Byte 0 ==
1579 06:02:21.204499 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1580 06:02:21.208295 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1581 06:02:21.211489 == TX Byte 1 ==
1582 06:02:21.214729 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1583 06:02:21.221189 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1584 06:02:21.221655 ==
1585 06:02:21.224469 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 06:02:21.227832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 06:02:21.228251 ==
1588 06:02:21.240488 TX Vref=22, minBit 0, minWin=27, winSum=440
1589 06:02:21.244194 TX Vref=24, minBit 1, minWin=26, winSum=439
1590 06:02:21.247474 TX Vref=26, minBit 4, minWin=27, winSum=443
1591 06:02:21.250685 TX Vref=28, minBit 4, minWin=27, winSum=447
1592 06:02:21.254133 TX Vref=30, minBit 5, minWin=27, winSum=448
1593 06:02:21.257846 TX Vref=32, minBit 4, minWin=27, winSum=446
1594 06:02:21.264285 [TxChooseVref] Worse bit 5, Min win 27, Win sum 448, Final Vref 30
1595 06:02:21.264807
1596 06:02:21.267399 Final TX Range 1 Vref 30
1597 06:02:21.267819
1598 06:02:21.268154 ==
1599 06:02:21.271099 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 06:02:21.274656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 06:02:21.275094 ==
1602 06:02:21.275633
1603 06:02:21.276113
1604 06:02:21.277826 TX Vref Scan disable
1605 06:02:21.281168 == TX Byte 0 ==
1606 06:02:21.284313 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1607 06:02:21.287853 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1608 06:02:21.291318 == TX Byte 1 ==
1609 06:02:21.294202 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1610 06:02:21.297878 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1611 06:02:21.298395
1612 06:02:21.301032 [DATLAT]
1613 06:02:21.301447 Freq=800, CH1 RK0
1614 06:02:21.301837
1615 06:02:21.304599 DATLAT Default: 0xa
1616 06:02:21.305015 0, 0xFFFF, sum = 0
1617 06:02:21.307462 1, 0xFFFF, sum = 0
1618 06:02:21.307885 2, 0xFFFF, sum = 0
1619 06:02:21.311062 3, 0xFFFF, sum = 0
1620 06:02:21.311484 4, 0xFFFF, sum = 0
1621 06:02:21.314413 5, 0xFFFF, sum = 0
1622 06:02:21.314939 6, 0xFFFF, sum = 0
1623 06:02:21.317720 7, 0xFFFF, sum = 0
1624 06:02:21.318245 8, 0xFFFF, sum = 0
1625 06:02:21.321290 9, 0x0, sum = 1
1626 06:02:21.321758 10, 0x0, sum = 2
1627 06:02:21.324729 11, 0x0, sum = 3
1628 06:02:21.325254 12, 0x0, sum = 4
1629 06:02:21.327929 best_step = 10
1630 06:02:21.328343
1631 06:02:21.328672 ==
1632 06:02:21.331495 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 06:02:21.334606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 06:02:21.335233 ==
1635 06:02:21.335762 RX Vref Scan: 1
1636 06:02:21.336294
1637 06:02:21.337682 Set Vref Range= 32 -> 127
1638 06:02:21.338096
1639 06:02:21.341294 RX Vref 32 -> 127, step: 1
1640 06:02:21.341769
1641 06:02:21.344203 RX Delay -111 -> 252, step: 8
1642 06:02:21.344641
1643 06:02:21.347684 Set Vref, RX VrefLevel [Byte0]: 32
1644 06:02:21.350645 [Byte1]: 32
1645 06:02:21.351190
1646 06:02:21.354124 Set Vref, RX VrefLevel [Byte0]: 33
1647 06:02:21.357764 [Byte1]: 33
1648 06:02:21.358195
1649 06:02:21.361300 Set Vref, RX VrefLevel [Byte0]: 34
1650 06:02:21.364459 [Byte1]: 34
1651 06:02:21.368628
1652 06:02:21.369150 Set Vref, RX VrefLevel [Byte0]: 35
1653 06:02:21.372117 [Byte1]: 35
1654 06:02:21.375751
1655 06:02:21.376159 Set Vref, RX VrefLevel [Byte0]: 36
1656 06:02:21.379214 [Byte1]: 36
1657 06:02:21.383754
1658 06:02:21.384257 Set Vref, RX VrefLevel [Byte0]: 37
1659 06:02:21.386755 [Byte1]: 37
1660 06:02:21.391323
1661 06:02:21.391731 Set Vref, RX VrefLevel [Byte0]: 38
1662 06:02:21.395174 [Byte1]: 38
1663 06:02:21.398970
1664 06:02:21.399382 Set Vref, RX VrefLevel [Byte0]: 39
1665 06:02:21.402491 [Byte1]: 39
1666 06:02:21.406603
1667 06:02:21.407109 Set Vref, RX VrefLevel [Byte0]: 40
1668 06:02:21.410323 [Byte1]: 40
1669 06:02:21.414456
1670 06:02:21.414961 Set Vref, RX VrefLevel [Byte0]: 41
1671 06:02:21.417733 [Byte1]: 41
1672 06:02:21.422117
1673 06:02:21.422656 Set Vref, RX VrefLevel [Byte0]: 42
1674 06:02:21.425536 [Byte1]: 42
1675 06:02:21.429881
1676 06:02:21.430434 Set Vref, RX VrefLevel [Byte0]: 43
1677 06:02:21.432813 [Byte1]: 43
1678 06:02:21.437622
1679 06:02:21.438144 Set Vref, RX VrefLevel [Byte0]: 44
1680 06:02:21.440543 [Byte1]: 44
1681 06:02:21.444975
1682 06:02:21.445506 Set Vref, RX VrefLevel [Byte0]: 45
1683 06:02:21.447989 [Byte1]: 45
1684 06:02:21.452559
1685 06:02:21.452979 Set Vref, RX VrefLevel [Byte0]: 46
1686 06:02:21.455766 [Byte1]: 46
1687 06:02:21.460060
1688 06:02:21.460525 Set Vref, RX VrefLevel [Byte0]: 47
1689 06:02:21.463408 [Byte1]: 47
1690 06:02:21.467849
1691 06:02:21.468375 Set Vref, RX VrefLevel [Byte0]: 48
1692 06:02:21.471111 [Byte1]: 48
1693 06:02:21.475641
1694 06:02:21.476076 Set Vref, RX VrefLevel [Byte0]: 49
1695 06:02:21.478797 [Byte1]: 49
1696 06:02:21.483627
1697 06:02:21.484130 Set Vref, RX VrefLevel [Byte0]: 50
1698 06:02:21.486168 [Byte1]: 50
1699 06:02:21.490740
1700 06:02:21.491311 Set Vref, RX VrefLevel [Byte0]: 51
1701 06:02:21.493861 [Byte1]: 51
1702 06:02:21.498421
1703 06:02:21.498926 Set Vref, RX VrefLevel [Byte0]: 52
1704 06:02:21.501985 [Byte1]: 52
1705 06:02:21.506255
1706 06:02:21.506667 Set Vref, RX VrefLevel [Byte0]: 53
1707 06:02:21.512829 [Byte1]: 53
1708 06:02:21.513425
1709 06:02:21.515867 Set Vref, RX VrefLevel [Byte0]: 54
1710 06:02:21.519342 [Byte1]: 54
1711 06:02:21.519850
1712 06:02:21.522930 Set Vref, RX VrefLevel [Byte0]: 55
1713 06:02:21.526221 [Byte1]: 55
1714 06:02:21.526729
1715 06:02:21.529878 Set Vref, RX VrefLevel [Byte0]: 56
1716 06:02:21.532486 [Byte1]: 56
1717 06:02:21.536762
1718 06:02:21.537267 Set Vref, RX VrefLevel [Byte0]: 57
1719 06:02:21.539671 [Byte1]: 57
1720 06:02:21.544028
1721 06:02:21.544437 Set Vref, RX VrefLevel [Byte0]: 58
1722 06:02:21.547387 [Byte1]: 58
1723 06:02:21.551978
1724 06:02:21.552689 Set Vref, RX VrefLevel [Byte0]: 59
1725 06:02:21.555076 [Byte1]: 59
1726 06:02:21.559832
1727 06:02:21.560236 Set Vref, RX VrefLevel [Byte0]: 60
1728 06:02:21.563159 [Byte1]: 60
1729 06:02:21.567403
1730 06:02:21.567978 Set Vref, RX VrefLevel [Byte0]: 61
1731 06:02:21.570270 [Byte1]: 61
1732 06:02:21.575243
1733 06:02:21.575651 Set Vref, RX VrefLevel [Byte0]: 62
1734 06:02:21.578468 [Byte1]: 62
1735 06:02:21.582555
1736 06:02:21.583066 Set Vref, RX VrefLevel [Byte0]: 63
1737 06:02:21.586179 [Byte1]: 63
1738 06:02:21.590052
1739 06:02:21.590460 Set Vref, RX VrefLevel [Byte0]: 64
1740 06:02:21.593698 [Byte1]: 64
1741 06:02:21.598396
1742 06:02:21.598904 Set Vref, RX VrefLevel [Byte0]: 65
1743 06:02:21.601648 [Byte1]: 65
1744 06:02:21.605871
1745 06:02:21.606379 Set Vref, RX VrefLevel [Byte0]: 66
1746 06:02:21.608624 [Byte1]: 66
1747 06:02:21.613037
1748 06:02:21.613588 Set Vref, RX VrefLevel [Byte0]: 67
1749 06:02:21.616368 [Byte1]: 67
1750 06:02:21.620811
1751 06:02:21.621320 Set Vref, RX VrefLevel [Byte0]: 68
1752 06:02:21.624346 [Byte1]: 68
1753 06:02:21.628934
1754 06:02:21.629443 Set Vref, RX VrefLevel [Byte0]: 69
1755 06:02:21.631836 [Byte1]: 69
1756 06:02:21.636212
1757 06:02:21.636716 Set Vref, RX VrefLevel [Byte0]: 70
1758 06:02:21.639520 [Byte1]: 70
1759 06:02:21.643481
1760 06:02:21.643888 Set Vref, RX VrefLevel [Byte0]: 71
1761 06:02:21.647103 [Byte1]: 71
1762 06:02:21.651853
1763 06:02:21.652375 Set Vref, RX VrefLevel [Byte0]: 72
1764 06:02:21.655060 [Byte1]: 72
1765 06:02:21.659137
1766 06:02:21.659547 Set Vref, RX VrefLevel [Byte0]: 73
1767 06:02:21.662522 [Byte1]: 73
1768 06:02:21.666531
1769 06:02:21.666939 Set Vref, RX VrefLevel [Byte0]: 74
1770 06:02:21.670181 [Byte1]: 74
1771 06:02:21.674406
1772 06:02:21.674910 Set Vref, RX VrefLevel [Byte0]: 75
1773 06:02:21.677844 [Byte1]: 75
1774 06:02:21.682203
1775 06:02:21.682617 Set Vref, RX VrefLevel [Byte0]: 76
1776 06:02:21.685429 [Byte1]: 76
1777 06:02:21.689425
1778 06:02:21.689885 Final RX Vref Byte 0 = 60 to rank0
1779 06:02:21.692883 Final RX Vref Byte 1 = 56 to rank0
1780 06:02:21.696742 Final RX Vref Byte 0 = 60 to rank1
1781 06:02:21.699683 Final RX Vref Byte 1 = 56 to rank1==
1782 06:02:21.703257 Dram Type= 6, Freq= 0, CH_1, rank 0
1783 06:02:21.709892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1784 06:02:21.710440 ==
1785 06:02:21.710783 DQS Delay:
1786 06:02:21.711152 DQS0 = 0, DQS1 = 0
1787 06:02:21.713075 DQM Delay:
1788 06:02:21.713519 DQM0 = 81, DQM1 = 71
1789 06:02:21.716817 DQ Delay:
1790 06:02:21.719683 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1791 06:02:21.720093 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1792 06:02:21.723299 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1793 06:02:21.726377 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1794 06:02:21.729219
1795 06:02:21.729720
1796 06:02:21.736329 [DQSOSCAuto] RK0, (LSB)MR18= 0x131e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1797 06:02:21.739692 CH1 RK0: MR19=606, MR18=131E
1798 06:02:21.746471 CH1_RK0: MR19=0x606, MR18=0x131E, DQSOSC=402, MR23=63, INC=91, DEC=60
1799 06:02:21.746888
1800 06:02:21.749993 ----->DramcWriteLeveling(PI) begin...
1801 06:02:21.750411 ==
1802 06:02:21.752858 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 06:02:21.756009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 06:02:21.756430 ==
1805 06:02:21.759720 Write leveling (Byte 0): 28 => 28
1806 06:02:21.762915 Write leveling (Byte 1): 29 => 29
1807 06:02:21.766433 DramcWriteLeveling(PI) end<-----
1808 06:02:21.766851
1809 06:02:21.767177 ==
1810 06:02:21.769593 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 06:02:21.772708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 06:02:21.773122 ==
1813 06:02:21.776196 [Gating] SW mode calibration
1814 06:02:21.782573 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1815 06:02:21.789588 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1816 06:02:21.793184 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1817 06:02:21.796237 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1818 06:02:21.803044 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 06:02:21.805937 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 06:02:21.809150 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 06:02:21.815858 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 06:02:21.819395 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 06:02:21.822779 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 06:02:21.829055 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 06:02:21.832638 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 06:02:21.836064 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 06:02:21.842446 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 06:02:21.845721 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 06:02:21.849341 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 06:02:21.856457 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 06:02:21.859033 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 06:02:21.862416 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 06:02:21.869825 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1834 06:02:21.872617 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1835 06:02:21.875582 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 06:02:21.879089 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 06:02:21.886197 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 06:02:21.889520 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 06:02:21.892714 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 06:02:21.899154 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 06:02:21.902336 0 9 4 | B1->B0 | 2323 2929 | 1 1 | (1 1) (1 1)
1842 06:02:21.906367 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1843 06:02:21.912633 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 06:02:21.916133 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 06:02:21.919418 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 06:02:21.925689 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 06:02:21.928860 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 06:02:21.932063 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1849 06:02:21.938791 0 10 4 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (0 1)
1850 06:02:21.942183 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1851 06:02:21.945935 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 06:02:21.952127 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 06:02:21.955591 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 06:02:21.959209 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 06:02:21.965660 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 06:02:21.969247 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
1857 06:02:21.972813 0 11 4 | B1->B0 | 2727 3938 | 1 1 | (0 0) (0 0)
1858 06:02:21.978971 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1859 06:02:21.982611 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 06:02:21.985738 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 06:02:21.992678 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 06:02:21.996389 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 06:02:21.998679 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 06:02:22.002235 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 06:02:22.008949 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1866 06:02:22.012377 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1867 06:02:22.015937 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1868 06:02:22.022292 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 06:02:22.026068 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 06:02:22.029385 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 06:02:22.035851 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 06:02:22.039135 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 06:02:22.042629 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 06:02:22.049067 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 06:02:22.052575 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 06:02:22.055552 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 06:02:22.062224 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 06:02:22.065543 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 06:02:22.068579 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 06:02:22.075694 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 06:02:22.079017 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1882 06:02:22.082093 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 06:02:22.086071 Total UI for P1: 0, mck2ui 16
1884 06:02:22.088953 best dqsien dly found for B0: ( 0, 14, 4)
1885 06:02:22.092525 Total UI for P1: 0, mck2ui 16
1886 06:02:22.095712 best dqsien dly found for B1: ( 0, 14, 6)
1887 06:02:22.098867 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1888 06:02:22.102463 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1889 06:02:22.102972
1890 06:02:22.105961 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1891 06:02:22.109321 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1892 06:02:22.112778 [Gating] SW calibration Done
1893 06:02:22.113192 ==
1894 06:02:22.115961 Dram Type= 6, Freq= 0, CH_1, rank 1
1895 06:02:22.118881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1896 06:02:22.122221 ==
1897 06:02:22.122640 RX Vref Scan: 0
1898 06:02:22.122979
1899 06:02:22.125690 RX Vref 0 -> 0, step: 1
1900 06:02:22.126357
1901 06:02:22.129318 RX Delay -130 -> 252, step: 16
1902 06:02:22.132164 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1903 06:02:22.135693 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1904 06:02:22.139110 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1905 06:02:22.142273 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1906 06:02:22.149000 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1907 06:02:22.152326 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1908 06:02:22.155716 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1909 06:02:22.158732 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1910 06:02:22.162106 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1911 06:02:22.169087 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1912 06:02:22.172264 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1913 06:02:22.175936 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1914 06:02:22.179265 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1915 06:02:22.185559 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1916 06:02:22.188940 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1917 06:02:22.191980 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1918 06:02:22.192396 ==
1919 06:02:22.195267 Dram Type= 6, Freq= 0, CH_1, rank 1
1920 06:02:22.198734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1921 06:02:22.199153 ==
1922 06:02:22.202140 DQS Delay:
1923 06:02:22.202553 DQS0 = 0, DQS1 = 0
1924 06:02:22.202879 DQM Delay:
1925 06:02:22.205358 DQM0 = 78, DQM1 = 71
1926 06:02:22.205805 DQ Delay:
1927 06:02:22.208525 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1928 06:02:22.211848 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1929 06:02:22.215340 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1930 06:02:22.218628 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1931 06:02:22.219046
1932 06:02:22.219377
1933 06:02:22.219686 ==
1934 06:02:22.221912 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 06:02:22.228489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 06:02:22.228911 ==
1937 06:02:22.229248
1938 06:02:22.229607
1939 06:02:22.229917 TX Vref Scan disable
1940 06:02:22.232518 == TX Byte 0 ==
1941 06:02:22.235346 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1942 06:02:22.242378 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1943 06:02:22.242804 == TX Byte 1 ==
1944 06:02:22.245789 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1945 06:02:22.252474 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1946 06:02:22.253048 ==
1947 06:02:22.255768 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 06:02:22.259317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 06:02:22.259830 ==
1950 06:02:22.271329 TX Vref=22, minBit 1, minWin=27, winSum=446
1951 06:02:22.275225 TX Vref=24, minBit 1, minWin=27, winSum=451
1952 06:02:22.278313 TX Vref=26, minBit 0, minWin=28, winSum=456
1953 06:02:22.281465 TX Vref=28, minBit 1, minWin=27, winSum=454
1954 06:02:22.284505 TX Vref=30, minBit 0, minWin=28, winSum=459
1955 06:02:22.288057 TX Vref=32, minBit 1, minWin=27, winSum=456
1956 06:02:22.294814 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
1957 06:02:22.295312
1958 06:02:22.297717 Final TX Range 1 Vref 30
1959 06:02:22.298137
1960 06:02:22.298464 ==
1961 06:02:22.301207 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 06:02:22.304782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 06:02:22.305255 ==
1964 06:02:22.305771
1965 06:02:22.307972
1966 06:02:22.308386 TX Vref Scan disable
1967 06:02:22.311479 == TX Byte 0 ==
1968 06:02:22.315142 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1969 06:02:22.317856 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1970 06:02:22.321388 == TX Byte 1 ==
1971 06:02:22.324730 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1972 06:02:22.328023 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1973 06:02:22.331473
1974 06:02:22.331888 [DATLAT]
1975 06:02:22.332221 Freq=800, CH1 RK1
1976 06:02:22.332532
1977 06:02:22.334391 DATLAT Default: 0xa
1978 06:02:22.334844 0, 0xFFFF, sum = 0
1979 06:02:22.337905 1, 0xFFFF, sum = 0
1980 06:02:22.338329 2, 0xFFFF, sum = 0
1981 06:02:22.341675 3, 0xFFFF, sum = 0
1982 06:02:22.342099 4, 0xFFFF, sum = 0
1983 06:02:22.344584 5, 0xFFFF, sum = 0
1984 06:02:22.345014 6, 0xFFFF, sum = 0
1985 06:02:22.348061 7, 0xFFFF, sum = 0
1986 06:02:22.350966 8, 0xFFFF, sum = 0
1987 06:02:22.351390 9, 0x0, sum = 1
1988 06:02:22.351727 10, 0x0, sum = 2
1989 06:02:22.354557 11, 0x0, sum = 3
1990 06:02:22.354979 12, 0x0, sum = 4
1991 06:02:22.357881 best_step = 10
1992 06:02:22.358298
1993 06:02:22.358627 ==
1994 06:02:22.361235 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 06:02:22.364719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 06:02:22.365162 ==
1997 06:02:22.368078 RX Vref Scan: 0
1998 06:02:22.368514
1999 06:02:22.368868 RX Vref 0 -> 0, step: 1
2000 06:02:22.369206
2001 06:02:22.371043 RX Delay -111 -> 252, step: 8
2002 06:02:22.378264 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2003 06:02:22.381517 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2004 06:02:22.384737 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2005 06:02:22.387771 iDelay=209, Bit 3, Center 76 (-47 ~ 200) 248
2006 06:02:22.391327 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2007 06:02:22.398270 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2008 06:02:22.401337 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2009 06:02:22.404560 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2010 06:02:22.407976 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2011 06:02:22.411234 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2012 06:02:22.417987 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2013 06:02:22.421338 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2014 06:02:22.424625 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2015 06:02:22.427631 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2016 06:02:22.431117 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2017 06:02:22.437906 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2018 06:02:22.438336 ==
2019 06:02:22.440943 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 06:02:22.444683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 06:02:22.445093 ==
2022 06:02:22.445414 DQS Delay:
2023 06:02:22.447610 DQS0 = 0, DQS1 = 0
2024 06:02:22.448051 DQM Delay:
2025 06:02:22.451305 DQM0 = 78, DQM1 = 73
2026 06:02:22.451857 DQ Delay:
2027 06:02:22.454199 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2028 06:02:22.457875 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2029 06:02:22.461451 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2030 06:02:22.464298 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2031 06:02:22.464707
2032 06:02:22.465031
2033 06:02:22.474199 [DQSOSCAuto] RK1, (LSB)MR18= 0x223a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2034 06:02:22.474607 CH1 RK1: MR19=606, MR18=223A
2035 06:02:22.481132 CH1_RK1: MR19=0x606, MR18=0x223A, DQSOSC=395, MR23=63, INC=94, DEC=63
2036 06:02:22.484149 [RxdqsGatingPostProcess] freq 800
2037 06:02:22.491252 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2038 06:02:22.494275 Pre-setting of DQS Precalculation
2039 06:02:22.497323 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2040 06:02:22.504152 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2041 06:02:22.513755 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2042 06:02:22.513841
2043 06:02:22.513905
2044 06:02:22.513963 [Calibration Summary] 1600 Mbps
2045 06:02:22.516997 CH 0, Rank 0
2046 06:02:22.517065 SW Impedance : PASS
2047 06:02:22.520574 DUTY Scan : NO K
2048 06:02:22.523853 ZQ Calibration : PASS
2049 06:02:22.523926 Jitter Meter : NO K
2050 06:02:22.526882 CBT Training : PASS
2051 06:02:22.530617 Write leveling : PASS
2052 06:02:22.530687 RX DQS gating : PASS
2053 06:02:22.533825 RX DQ/DQS(RDDQC) : PASS
2054 06:02:22.537054 TX DQ/DQS : PASS
2055 06:02:22.537148 RX DATLAT : PASS
2056 06:02:22.540361 RX DQ/DQS(Engine): PASS
2057 06:02:22.543707 TX OE : NO K
2058 06:02:22.543806 All Pass.
2059 06:02:22.543894
2060 06:02:22.543979 CH 0, Rank 1
2061 06:02:22.547262 SW Impedance : PASS
2062 06:02:22.550178 DUTY Scan : NO K
2063 06:02:22.550247 ZQ Calibration : PASS
2064 06:02:22.553832 Jitter Meter : NO K
2065 06:02:22.557377 CBT Training : PASS
2066 06:02:22.557496 Write leveling : PASS
2067 06:02:22.560421 RX DQS gating : PASS
2068 06:02:22.560506 RX DQ/DQS(RDDQC) : PASS
2069 06:02:22.564118 TX DQ/DQS : PASS
2070 06:02:22.567288 RX DATLAT : PASS
2071 06:02:22.567388 RX DQ/DQS(Engine): PASS
2072 06:02:22.570788 TX OE : NO K
2073 06:02:22.570888 All Pass.
2074 06:02:22.570967
2075 06:02:22.574009 CH 1, Rank 0
2076 06:02:22.574421 SW Impedance : PASS
2077 06:02:22.577425 DUTY Scan : NO K
2078 06:02:22.580566 ZQ Calibration : PASS
2079 06:02:22.580977 Jitter Meter : NO K
2080 06:02:22.584203 CBT Training : PASS
2081 06:02:22.587325 Write leveling : PASS
2082 06:02:22.587735 RX DQS gating : PASS
2083 06:02:22.590910 RX DQ/DQS(RDDQC) : PASS
2084 06:02:22.594053 TX DQ/DQS : PASS
2085 06:02:22.594468 RX DATLAT : PASS
2086 06:02:22.597326 RX DQ/DQS(Engine): PASS
2087 06:02:22.597800 TX OE : NO K
2088 06:02:22.600733 All Pass.
2089 06:02:22.601141
2090 06:02:22.601461 CH 1, Rank 1
2091 06:02:22.604409 SW Impedance : PASS
2092 06:02:22.604819 DUTY Scan : NO K
2093 06:02:22.607477 ZQ Calibration : PASS
2094 06:02:22.610937 Jitter Meter : NO K
2095 06:02:22.611353 CBT Training : PASS
2096 06:02:22.614299 Write leveling : PASS
2097 06:02:22.617378 RX DQS gating : PASS
2098 06:02:22.617838 RX DQ/DQS(RDDQC) : PASS
2099 06:02:22.621208 TX DQ/DQS : PASS
2100 06:02:22.624184 RX DATLAT : PASS
2101 06:02:22.624596 RX DQ/DQS(Engine): PASS
2102 06:02:22.627687 TX OE : NO K
2103 06:02:22.628194 All Pass.
2104 06:02:22.628536
2105 06:02:22.631322 DramC Write-DBI off
2106 06:02:22.634112 PER_BANK_REFRESH: Hybrid Mode
2107 06:02:22.634530 TX_TRACKING: ON
2108 06:02:22.637283 [GetDramInforAfterCalByMRR] Vendor 6.
2109 06:02:22.640748 [GetDramInforAfterCalByMRR] Revision 606.
2110 06:02:22.644202 [GetDramInforAfterCalByMRR] Revision 2 0.
2111 06:02:22.647343 MR0 0x3b3b
2112 06:02:22.647914 MR8 0x5151
2113 06:02:22.650914 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 06:02:22.651458
2115 06:02:22.651896 MR0 0x3b3b
2116 06:02:22.654351 MR8 0x5151
2117 06:02:22.657326 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 06:02:22.657846
2119 06:02:22.664556 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2120 06:02:22.670927 [FAST_K] Save calibration result to emmc
2121 06:02:22.674310 [FAST_K] Save calibration result to emmc
2122 06:02:22.674725 dram_init: config_dvfs: 1
2123 06:02:22.677380 dramc_set_vcore_voltage set vcore to 662500
2124 06:02:22.680918 Read voltage for 1200, 2
2125 06:02:22.681332 Vio18 = 0
2126 06:02:22.684383 Vcore = 662500
2127 06:02:22.684793 Vdram = 0
2128 06:02:22.685116 Vddq = 0
2129 06:02:22.687591 Vmddr = 0
2130 06:02:22.690857 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2131 06:02:22.697698 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2132 06:02:22.698120 MEM_TYPE=3, freq_sel=15
2133 06:02:22.701176 sv_algorithm_assistance_LP4_1600
2134 06:02:22.707359 ============ PULL DRAM RESETB DOWN ============
2135 06:02:22.710910 ========== PULL DRAM RESETB DOWN end =========
2136 06:02:22.713908 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2137 06:02:22.717451 ===================================
2138 06:02:22.720805 LPDDR4 DRAM CONFIGURATION
2139 06:02:22.724334 ===================================
2140 06:02:22.727556 EX_ROW_EN[0] = 0x0
2141 06:02:22.728002 EX_ROW_EN[1] = 0x0
2142 06:02:22.730738 LP4Y_EN = 0x0
2143 06:02:22.731181 WORK_FSP = 0x0
2144 06:02:22.734149 WL = 0x4
2145 06:02:22.734583 RL = 0x4
2146 06:02:22.737771 BL = 0x2
2147 06:02:22.738204 RPST = 0x0
2148 06:02:22.740555 RD_PRE = 0x0
2149 06:02:22.740967 WR_PRE = 0x1
2150 06:02:22.744266 WR_PST = 0x0
2151 06:02:22.744832 DBI_WR = 0x0
2152 06:02:22.747754 DBI_RD = 0x0
2153 06:02:22.748312 OTF = 0x1
2154 06:02:22.750623 ===================================
2155 06:02:22.754266 ===================================
2156 06:02:22.757433 ANA top config
2157 06:02:22.760588 ===================================
2158 06:02:22.761003 DLL_ASYNC_EN = 0
2159 06:02:22.763896 ALL_SLAVE_EN = 0
2160 06:02:22.767422 NEW_RANK_MODE = 1
2161 06:02:22.770964 DLL_IDLE_MODE = 1
2162 06:02:22.774043 LP45_APHY_COMB_EN = 1
2163 06:02:22.774597 TX_ODT_DIS = 1
2164 06:02:22.777461 NEW_8X_MODE = 1
2165 06:02:22.781033 ===================================
2166 06:02:22.784039 ===================================
2167 06:02:22.787573 data_rate = 2400
2168 06:02:22.790922 CKR = 1
2169 06:02:22.794326 DQ_P2S_RATIO = 8
2170 06:02:22.797578 ===================================
2171 06:02:22.801022 CA_P2S_RATIO = 8
2172 06:02:22.801436 DQ_CA_OPEN = 0
2173 06:02:22.804078 DQ_SEMI_OPEN = 0
2174 06:02:22.807412 CA_SEMI_OPEN = 0
2175 06:02:22.810684 CA_FULL_RATE = 0
2176 06:02:22.814386 DQ_CKDIV4_EN = 0
2177 06:02:22.814800 CA_CKDIV4_EN = 0
2178 06:02:22.817531 CA_PREDIV_EN = 0
2179 06:02:22.820948 PH8_DLY = 17
2180 06:02:22.823854 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2181 06:02:22.827411 DQ_AAMCK_DIV = 4
2182 06:02:22.830757 CA_AAMCK_DIV = 4
2183 06:02:22.831182 CA_ADMCK_DIV = 4
2184 06:02:22.834482 DQ_TRACK_CA_EN = 0
2185 06:02:22.837547 CA_PICK = 1200
2186 06:02:22.841021 CA_MCKIO = 1200
2187 06:02:22.843857 MCKIO_SEMI = 0
2188 06:02:22.847450 PLL_FREQ = 2366
2189 06:02:22.850917 DQ_UI_PI_RATIO = 32
2190 06:02:22.851329 CA_UI_PI_RATIO = 0
2191 06:02:22.853915 ===================================
2192 06:02:22.857454 ===================================
2193 06:02:22.860807 memory_type:LPDDR4
2194 06:02:22.864036 GP_NUM : 10
2195 06:02:22.864504 SRAM_EN : 1
2196 06:02:22.867857 MD32_EN : 0
2197 06:02:22.871004 ===================================
2198 06:02:22.874168 [ANA_INIT] >>>>>>>>>>>>>>
2199 06:02:22.877322 <<<<<< [CONFIGURE PHASE]: ANA_TX
2200 06:02:22.881021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2201 06:02:22.884502 ===================================
2202 06:02:22.884944 data_rate = 2400,PCW = 0X5b00
2203 06:02:22.887548 ===================================
2204 06:02:22.891083 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2205 06:02:22.898060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 06:02:22.904575 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 06:02:22.908020 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2208 06:02:22.911400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2209 06:02:22.914604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2210 06:02:22.917960 [ANA_INIT] flow start
2211 06:02:22.918393 [ANA_INIT] PLL >>>>>>>>
2212 06:02:22.921602 [ANA_INIT] PLL <<<<<<<<
2213 06:02:22.924622 [ANA_INIT] MIDPI >>>>>>>>
2214 06:02:22.925033 [ANA_INIT] MIDPI <<<<<<<<
2215 06:02:22.928157 [ANA_INIT] DLL >>>>>>>>
2216 06:02:22.930969 [ANA_INIT] DLL <<<<<<<<
2217 06:02:22.931384 [ANA_INIT] flow end
2218 06:02:22.937693 ============ LP4 DIFF to SE enter ============
2219 06:02:22.941002 ============ LP4 DIFF to SE exit ============
2220 06:02:22.944744 [ANA_INIT] <<<<<<<<<<<<<
2221 06:02:22.947913 [Flow] Enable top DCM control >>>>>
2222 06:02:22.951443 [Flow] Enable top DCM control <<<<<
2223 06:02:22.951862 Enable DLL master slave shuffle
2224 06:02:22.957957 ==============================================================
2225 06:02:22.960980 Gating Mode config
2226 06:02:22.964580 ==============================================================
2227 06:02:22.968047 Config description:
2228 06:02:22.977580 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2229 06:02:22.984738 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2230 06:02:22.987549 SELPH_MODE 0: By rank 1: By Phase
2231 06:02:22.994401 ==============================================================
2232 06:02:22.998136 GAT_TRACK_EN = 1
2233 06:02:23.000954 RX_GATING_MODE = 2
2234 06:02:23.004470 RX_GATING_TRACK_MODE = 2
2235 06:02:23.004881 SELPH_MODE = 1
2236 06:02:23.007883 PICG_EARLY_EN = 1
2237 06:02:23.011463 VALID_LAT_VALUE = 1
2238 06:02:23.017577 ==============================================================
2239 06:02:23.020991 Enter into Gating configuration >>>>
2240 06:02:23.024337 Exit from Gating configuration <<<<
2241 06:02:23.027590 Enter into DVFS_PRE_config >>>>>
2242 06:02:23.037830 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2243 06:02:23.041027 Exit from DVFS_PRE_config <<<<<
2244 06:02:23.044384 Enter into PICG configuration >>>>
2245 06:02:23.047603 Exit from PICG configuration <<<<
2246 06:02:23.051260 [RX_INPUT] configuration >>>>>
2247 06:02:23.054936 [RX_INPUT] configuration <<<<<
2248 06:02:23.057908 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2249 06:02:23.064521 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2250 06:02:23.071415 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 06:02:23.074374 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 06:02:23.081146 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 06:02:23.088178 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 06:02:23.091056 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2255 06:02:23.097907 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2256 06:02:23.101277 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2257 06:02:23.104670 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2258 06:02:23.108129 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2259 06:02:23.114590 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2260 06:02:23.117909 ===================================
2261 06:02:23.118337 LPDDR4 DRAM CONFIGURATION
2262 06:02:23.121382 ===================================
2263 06:02:23.124377 EX_ROW_EN[0] = 0x0
2264 06:02:23.127769 EX_ROW_EN[1] = 0x0
2265 06:02:23.128198 LP4Y_EN = 0x0
2266 06:02:23.130934 WORK_FSP = 0x0
2267 06:02:23.131414 WL = 0x4
2268 06:02:23.134542 RL = 0x4
2269 06:02:23.134967 BL = 0x2
2270 06:02:23.138223 RPST = 0x0
2271 06:02:23.138647 RD_PRE = 0x0
2272 06:02:23.141161 WR_PRE = 0x1
2273 06:02:23.141643 WR_PST = 0x0
2274 06:02:23.144660 DBI_WR = 0x0
2275 06:02:23.145069 DBI_RD = 0x0
2276 06:02:23.147605 OTF = 0x1
2277 06:02:23.151239 ===================================
2278 06:02:23.154397 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2279 06:02:23.157757 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2280 06:02:23.164377 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2281 06:02:23.168024 ===================================
2282 06:02:23.168442 LPDDR4 DRAM CONFIGURATION
2283 06:02:23.170959 ===================================
2284 06:02:23.174360 EX_ROW_EN[0] = 0x10
2285 06:02:23.174773 EX_ROW_EN[1] = 0x0
2286 06:02:23.178181 LP4Y_EN = 0x0
2287 06:02:23.178594 WORK_FSP = 0x0
2288 06:02:23.181038 WL = 0x4
2289 06:02:23.184258 RL = 0x4
2290 06:02:23.184673 BL = 0x2
2291 06:02:23.187795 RPST = 0x0
2292 06:02:23.188205 RD_PRE = 0x0
2293 06:02:23.191115 WR_PRE = 0x1
2294 06:02:23.191754 WR_PST = 0x0
2295 06:02:23.194679 DBI_WR = 0x0
2296 06:02:23.195169 DBI_RD = 0x0
2297 06:02:23.198059 OTF = 0x1
2298 06:02:23.201443 ===================================
2299 06:02:23.204621 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2300 06:02:23.207969 ==
2301 06:02:23.211215 Dram Type= 6, Freq= 0, CH_0, rank 0
2302 06:02:23.214177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2303 06:02:23.214595 ==
2304 06:02:23.217791 [Duty_Offset_Calibration]
2305 06:02:23.218094 B0:2 B1:0 CA:3
2306 06:02:23.218346
2307 06:02:23.220670 [DutyScan_Calibration_Flow] k_type=0
2308 06:02:23.230835
2309 06:02:23.231124 ==CLK 0==
2310 06:02:23.233766 Final CLK duty delay cell = 0
2311 06:02:23.236930 [0] MAX Duty = 5031%(X100), DQS PI = 12
2312 06:02:23.240422 [0] MIN Duty = 4906%(X100), DQS PI = 54
2313 06:02:23.240732 [0] AVG Duty = 4968%(X100)
2314 06:02:23.244065
2315 06:02:23.246993 CH0 CLK Duty spec in!! Max-Min= 125%
2316 06:02:23.250672 [DutyScan_Calibration_Flow] ====Done====
2317 06:02:23.250966
2318 06:02:23.253739 [DutyScan_Calibration_Flow] k_type=1
2319 06:02:23.268844
2320 06:02:23.269165 ==DQS 0 ==
2321 06:02:23.272402 Final DQS duty delay cell = 0
2322 06:02:23.276150 [0] MAX Duty = 5093%(X100), DQS PI = 28
2323 06:02:23.278992 [0] MIN Duty = 4907%(X100), DQS PI = 2
2324 06:02:23.279278 [0] AVG Duty = 5000%(X100)
2325 06:02:23.282714
2326 06:02:23.282996 ==DQS 1 ==
2327 06:02:23.285432 Final DQS duty delay cell = -4
2328 06:02:23.288980 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2329 06:02:23.292496 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2330 06:02:23.295684 [-4] AVG Duty = 4922%(X100)
2331 06:02:23.296093
2332 06:02:23.299057 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2333 06:02:23.299345
2334 06:02:23.302260 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2335 06:02:23.305804 [DutyScan_Calibration_Flow] ====Done====
2336 06:02:23.306221
2337 06:02:23.308994 [DutyScan_Calibration_Flow] k_type=3
2338 06:02:23.326852
2339 06:02:23.327264 ==DQM 0 ==
2340 06:02:23.329730 Final DQM duty delay cell = 0
2341 06:02:23.333033 [0] MAX Duty = 5124%(X100), DQS PI = 28
2342 06:02:23.336153 [0] MIN Duty = 4876%(X100), DQS PI = 48
2343 06:02:23.339967 [0] AVG Duty = 5000%(X100)
2344 06:02:23.340495
2345 06:02:23.340952 ==DQM 1 ==
2346 06:02:23.342957 Final DQM duty delay cell = 4
2347 06:02:23.346206 [4] MAX Duty = 5124%(X100), DQS PI = 50
2348 06:02:23.349940 [4] MIN Duty = 5000%(X100), DQS PI = 40
2349 06:02:23.352780 [4] AVG Duty = 5062%(X100)
2350 06:02:23.353152
2351 06:02:23.356312 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2352 06:02:23.356702
2353 06:02:23.359784 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2354 06:02:23.362647 [DutyScan_Calibration_Flow] ====Done====
2355 06:02:23.362859
2356 06:02:23.366040 [DutyScan_Calibration_Flow] k_type=2
2357 06:02:23.381036
2358 06:02:23.381156 ==DQ 0 ==
2359 06:02:23.384766 Final DQ duty delay cell = -4
2360 06:02:23.388321 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2361 06:02:23.391327 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2362 06:02:23.395042 [-4] AVG Duty = 4969%(X100)
2363 06:02:23.395138
2364 06:02:23.395212 ==DQ 1 ==
2365 06:02:23.397711 Final DQ duty delay cell = -4
2366 06:02:23.401053 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2367 06:02:23.405228 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2368 06:02:23.408011 [-4] AVG Duty = 4938%(X100)
2369 06:02:23.408111
2370 06:02:23.411677 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2371 06:02:23.411773
2372 06:02:23.414565 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2373 06:02:23.417918 [DutyScan_Calibration_Flow] ====Done====
2374 06:02:23.418032 ==
2375 06:02:23.421093 Dram Type= 6, Freq= 0, CH_1, rank 0
2376 06:02:23.424484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2377 06:02:23.424583 ==
2378 06:02:23.428102 [Duty_Offset_Calibration]
2379 06:02:23.428206 B0:1 B1:-2 CA:1
2380 06:02:23.428287
2381 06:02:23.431327 [DutyScan_Calibration_Flow] k_type=0
2382 06:02:23.441618
2383 06:02:23.441744 ==CLK 0==
2384 06:02:23.445037 Final CLK duty delay cell = 0
2385 06:02:23.448508 [0] MAX Duty = 5031%(X100), DQS PI = 18
2386 06:02:23.452243 [0] MIN Duty = 4844%(X100), DQS PI = 58
2387 06:02:23.452427 [0] AVG Duty = 4937%(X100)
2388 06:02:23.455087
2389 06:02:23.458693 CH1 CLK Duty spec in!! Max-Min= 187%
2390 06:02:23.461802 [DutyScan_Calibration_Flow] ====Done====
2391 06:02:23.462080
2392 06:02:23.464936 [DutyScan_Calibration_Flow] k_type=1
2393 06:02:23.480629
2394 06:02:23.481035 ==DQS 0 ==
2395 06:02:23.483915 Final DQS duty delay cell = -4
2396 06:02:23.487383 [-4] MAX Duty = 4969%(X100), DQS PI = 8
2397 06:02:23.490741 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2398 06:02:23.494044 [-4] AVG Duty = 4922%(X100)
2399 06:02:23.494453
2400 06:02:23.494863 ==DQS 1 ==
2401 06:02:23.497254 Final DQS duty delay cell = 0
2402 06:02:23.500925 [0] MAX Duty = 5093%(X100), DQS PI = 0
2403 06:02:23.503902 [0] MIN Duty = 4875%(X100), DQS PI = 28
2404 06:02:23.507248 [0] AVG Duty = 4984%(X100)
2405 06:02:23.507683
2406 06:02:23.510421 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2407 06:02:23.510871
2408 06:02:23.513995 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2409 06:02:23.517528 [DutyScan_Calibration_Flow] ====Done====
2410 06:02:23.518107
2411 06:02:23.520566 [DutyScan_Calibration_Flow] k_type=3
2412 06:02:23.537280
2413 06:02:23.537759 ==DQM 0 ==
2414 06:02:23.540591 Final DQM duty delay cell = 0
2415 06:02:23.543938 [0] MAX Duty = 5000%(X100), DQS PI = 22
2416 06:02:23.546909 [0] MIN Duty = 4844%(X100), DQS PI = 52
2417 06:02:23.550471 [0] AVG Duty = 4922%(X100)
2418 06:02:23.550930
2419 06:02:23.551335 ==DQM 1 ==
2420 06:02:23.553684 Final DQM duty delay cell = 0
2421 06:02:23.557102 [0] MAX Duty = 5031%(X100), DQS PI = 36
2422 06:02:23.560196 [0] MIN Duty = 4907%(X100), DQS PI = 0
2423 06:02:23.560678 [0] AVG Duty = 4969%(X100)
2424 06:02:23.563912
2425 06:02:23.567028 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2426 06:02:23.567483
2427 06:02:23.570656 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2428 06:02:23.574195 [DutyScan_Calibration_Flow] ====Done====
2429 06:02:23.574688
2430 06:02:23.576944 [DutyScan_Calibration_Flow] k_type=2
2431 06:02:23.593685
2432 06:02:23.594168 ==DQ 0 ==
2433 06:02:23.597034 Final DQ duty delay cell = 0
2434 06:02:23.600399 [0] MAX Duty = 5062%(X100), DQS PI = 14
2435 06:02:23.603329 [0] MIN Duty = 4938%(X100), DQS PI = 56
2436 06:02:23.603793 [0] AVG Duty = 5000%(X100)
2437 06:02:23.606741
2438 06:02:23.607176 ==DQ 1 ==
2439 06:02:23.610243 Final DQ duty delay cell = 0
2440 06:02:23.613599 [0] MAX Duty = 5125%(X100), DQS PI = 36
2441 06:02:23.616905 [0] MIN Duty = 4969%(X100), DQS PI = 26
2442 06:02:23.617319 [0] AVG Duty = 5047%(X100)
2443 06:02:23.617765
2444 06:02:23.620232 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2445 06:02:23.623563
2446 06:02:23.626505 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2447 06:02:23.630391 [DutyScan_Calibration_Flow] ====Done====
2448 06:02:23.633430 nWR fixed to 30
2449 06:02:23.633888 [ModeRegInit_LP4] CH0 RK0
2450 06:02:23.637051 [ModeRegInit_LP4] CH0 RK1
2451 06:02:23.639810 [ModeRegInit_LP4] CH1 RK0
2452 06:02:23.640222 [ModeRegInit_LP4] CH1 RK1
2453 06:02:23.643223 match AC timing 7
2454 06:02:23.646829 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2455 06:02:23.650332 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2456 06:02:23.656721 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2457 06:02:23.660243 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2458 06:02:23.666817 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2459 06:02:23.667358 ==
2460 06:02:23.669966 Dram Type= 6, Freq= 0, CH_0, rank 0
2461 06:02:23.673533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2462 06:02:23.673947 ==
2463 06:02:23.680377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2464 06:02:23.686200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2465 06:02:23.693548 [CA 0] Center 40 (10~71) winsize 62
2466 06:02:23.697004 [CA 1] Center 39 (9~70) winsize 62
2467 06:02:23.700132 [CA 2] Center 36 (6~66) winsize 61
2468 06:02:23.703711 [CA 3] Center 35 (5~66) winsize 62
2469 06:02:23.706670 [CA 4] Center 34 (4~65) winsize 62
2470 06:02:23.710278 [CA 5] Center 33 (3~64) winsize 62
2471 06:02:23.710727
2472 06:02:23.713999 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2473 06:02:23.714451
2474 06:02:23.716969 [CATrainingPosCal] consider 1 rank data
2475 06:02:23.720384 u2DelayCellTimex100 = 270/100 ps
2476 06:02:23.723236 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2477 06:02:23.730528 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2478 06:02:23.733699 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2479 06:02:23.736896 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2480 06:02:23.740404 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2481 06:02:23.743409 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2482 06:02:23.743882
2483 06:02:23.747191 CA PerBit enable=1, Macro0, CA PI delay=33
2484 06:02:23.747612
2485 06:02:23.750455 [CBTSetCACLKResult] CA Dly = 33
2486 06:02:23.750982 CS Dly: 7 (0~38)
2487 06:02:23.753908 ==
2488 06:02:23.757018 Dram Type= 6, Freq= 0, CH_0, rank 1
2489 06:02:23.760389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2490 06:02:23.760873 ==
2491 06:02:23.763366 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2492 06:02:23.770243 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2493 06:02:23.779804 [CA 0] Center 40 (10~71) winsize 62
2494 06:02:23.782789 [CA 1] Center 40 (10~70) winsize 61
2495 06:02:23.786538 [CA 2] Center 35 (5~66) winsize 62
2496 06:02:23.789705 [CA 3] Center 35 (5~66) winsize 62
2497 06:02:23.792747 [CA 4] Center 34 (4~65) winsize 62
2498 06:02:23.796214 [CA 5] Center 33 (3~63) winsize 61
2499 06:02:23.796665
2500 06:02:23.799724 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2501 06:02:23.800166
2502 06:02:23.803051 [CATrainingPosCal] consider 2 rank data
2503 06:02:23.806614 u2DelayCellTimex100 = 270/100 ps
2504 06:02:23.809679 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2505 06:02:23.816248 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2506 06:02:23.819540 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2507 06:02:23.823396 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2508 06:02:23.826463 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2509 06:02:23.829523 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2510 06:02:23.830007
2511 06:02:23.832930 CA PerBit enable=1, Macro0, CA PI delay=33
2512 06:02:23.833402
2513 06:02:23.836106 [CBTSetCACLKResult] CA Dly = 33
2514 06:02:23.836652 CS Dly: 8 (0~40)
2515 06:02:23.839493
2516 06:02:23.842885 ----->DramcWriteLeveling(PI) begin...
2517 06:02:23.843311 ==
2518 06:02:23.846728 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 06:02:23.849624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 06:02:23.850045 ==
2521 06:02:23.853214 Write leveling (Byte 0): 32 => 32
2522 06:02:23.856637 Write leveling (Byte 1): 28 => 28
2523 06:02:23.860067 DramcWriteLeveling(PI) end<-----
2524 06:02:23.860514
2525 06:02:23.860867 ==
2526 06:02:23.862956 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 06:02:23.866391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 06:02:23.866812 ==
2529 06:02:23.869973 [Gating] SW mode calibration
2530 06:02:23.876396 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2531 06:02:23.882886 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2532 06:02:23.886561 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2533 06:02:23.889814 0 15 4 | B1->B0 | 2424 3232 | 0 1 | (0 0) (1 1)
2534 06:02:23.896632 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 06:02:23.899435 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 06:02:23.903065 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 06:02:23.906072 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 06:02:23.913158 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 06:02:23.916002 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2540 06:02:23.919358 1 0 0 | B1->B0 | 3232 2e2e | 1 0 | (1 0) (1 0)
2541 06:02:23.925781 1 0 4 | B1->B0 | 2727 2323 | 0 0 | (0 1) (0 0)
2542 06:02:23.929378 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 06:02:23.932473 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 06:02:23.939516 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 06:02:23.942961 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 06:02:23.945962 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 06:02:23.952945 1 0 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2548 06:02:23.956104 1 1 0 | B1->B0 | 2828 3636 | 0 0 | (0 0) (1 1)
2549 06:02:23.959443 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2550 06:02:23.966436 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 06:02:23.969228 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 06:02:23.972714 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 06:02:23.980008 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 06:02:23.982936 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 06:02:23.986456 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2556 06:02:23.993040 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2557 06:02:23.996476 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 06:02:23.999692 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 06:02:24.002758 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 06:02:24.009706 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 06:02:24.012833 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 06:02:24.016474 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 06:02:24.023003 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 06:02:24.026067 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 06:02:24.029747 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 06:02:24.036245 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 06:02:24.039733 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 06:02:24.043262 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 06:02:24.049555 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 06:02:24.052951 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 06:02:24.055990 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2572 06:02:24.063144 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2573 06:02:24.063558 Total UI for P1: 0, mck2ui 16
2574 06:02:24.069462 best dqsien dly found for B0: ( 1, 3, 28)
2575 06:02:24.073169 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2576 06:02:24.076189 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 06:02:24.079409 Total UI for P1: 0, mck2ui 16
2578 06:02:24.083014 best dqsien dly found for B1: ( 1, 4, 2)
2579 06:02:24.086266 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2580 06:02:24.089858 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2581 06:02:24.090276
2582 06:02:24.093262 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2583 06:02:24.099419 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2584 06:02:24.099835 [Gating] SW calibration Done
2585 06:02:24.100167 ==
2586 06:02:24.103411 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 06:02:24.109761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 06:02:24.110184 ==
2589 06:02:24.110519 RX Vref Scan: 0
2590 06:02:24.110827
2591 06:02:24.113370 RX Vref 0 -> 0, step: 1
2592 06:02:24.113844
2593 06:02:24.116762 RX Delay -40 -> 252, step: 8
2594 06:02:24.119899 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2595 06:02:24.123323 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2596 06:02:24.126131 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2597 06:02:24.133153 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2598 06:02:24.136564 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2599 06:02:24.139725 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2600 06:02:24.143082 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2601 06:02:24.146397 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2602 06:02:24.149610 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2603 06:02:24.156402 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2604 06:02:24.159768 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2605 06:02:24.162914 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2606 06:02:24.166259 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2607 06:02:24.169366 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2608 06:02:24.176511 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2609 06:02:24.179990 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2610 06:02:24.180556 ==
2611 06:02:24.182999 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 06:02:24.186201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 06:02:24.186831 ==
2614 06:02:24.187358 DQS Delay:
2615 06:02:24.189933 DQS0 = 0, DQS1 = 0
2616 06:02:24.190223 DQM Delay:
2617 06:02:24.192804 DQM0 = 112, DQM1 = 102
2618 06:02:24.193193 DQ Delay:
2619 06:02:24.196627 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2620 06:02:24.200199 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2621 06:02:24.203115 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2622 06:02:24.206586 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2623 06:02:24.206876
2624 06:02:24.207102
2625 06:02:24.210120 ==
2626 06:02:24.212761 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 06:02:24.216201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 06:02:24.216502 ==
2629 06:02:24.216731
2630 06:02:24.216941
2631 06:02:24.219908 TX Vref Scan disable
2632 06:02:24.220297 == TX Byte 0 ==
2633 06:02:24.223126 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2634 06:02:24.229948 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2635 06:02:24.230247 == TX Byte 1 ==
2636 06:02:24.233593 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2637 06:02:24.239771 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2638 06:02:24.240161 ==
2639 06:02:24.243377 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 06:02:24.246254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 06:02:24.246561 ==
2642 06:02:24.258473 TX Vref=22, minBit 8, minWin=25, winSum=416
2643 06:02:24.262339 TX Vref=24, minBit 8, minWin=25, winSum=425
2644 06:02:24.265541 TX Vref=26, minBit 8, minWin=25, winSum=428
2645 06:02:24.269107 TX Vref=28, minBit 8, minWin=26, winSum=433
2646 06:02:24.272041 TX Vref=30, minBit 8, minWin=25, winSum=432
2647 06:02:24.278943 TX Vref=32, minBit 8, minWin=25, winSum=429
2648 06:02:24.282363 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 28
2649 06:02:24.282913
2650 06:02:24.285861 Final TX Range 1 Vref 28
2651 06:02:24.286413
2652 06:02:24.286771 ==
2653 06:02:24.288972 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 06:02:24.292591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 06:02:24.293138 ==
2656 06:02:24.293765
2657 06:02:24.295499
2658 06:02:24.296180 TX Vref Scan disable
2659 06:02:24.298805 == TX Byte 0 ==
2660 06:02:24.302209 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2661 06:02:24.305592 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2662 06:02:24.308587 == TX Byte 1 ==
2663 06:02:24.312273 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2664 06:02:24.315431 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2665 06:02:24.316008
2666 06:02:24.318854 [DATLAT]
2667 06:02:24.319387 Freq=1200, CH0 RK0
2668 06:02:24.319810
2669 06:02:24.322294 DATLAT Default: 0xd
2670 06:02:24.322867 0, 0xFFFF, sum = 0
2671 06:02:24.325750 1, 0xFFFF, sum = 0
2672 06:02:24.326350 2, 0xFFFF, sum = 0
2673 06:02:24.328709 3, 0xFFFF, sum = 0
2674 06:02:24.329125 4, 0xFFFF, sum = 0
2675 06:02:24.332443 5, 0xFFFF, sum = 0
2676 06:02:24.332855 6, 0xFFFF, sum = 0
2677 06:02:24.335269 7, 0xFFFF, sum = 0
2678 06:02:24.335682 8, 0xFFFF, sum = 0
2679 06:02:24.339056 9, 0xFFFF, sum = 0
2680 06:02:24.342255 10, 0xFFFF, sum = 0
2681 06:02:24.342674 11, 0xFFFF, sum = 0
2682 06:02:24.345691 12, 0x0, sum = 1
2683 06:02:24.346234 13, 0x0, sum = 2
2684 06:02:24.346572 14, 0x0, sum = 3
2685 06:02:24.348831 15, 0x0, sum = 4
2686 06:02:24.349246 best_step = 13
2687 06:02:24.349721
2688 06:02:24.350033 ==
2689 06:02:24.351963 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 06:02:24.359187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 06:02:24.359686 ==
2692 06:02:24.360010 RX Vref Scan: 1
2693 06:02:24.360309
2694 06:02:24.362065 Set Vref Range= 32 -> 127
2695 06:02:24.362475
2696 06:02:24.365639 RX Vref 32 -> 127, step: 1
2697 06:02:24.366048
2698 06:02:24.369184 RX Delay -37 -> 252, step: 4
2699 06:02:24.369636
2700 06:02:24.372857 Set Vref, RX VrefLevel [Byte0]: 32
2701 06:02:24.375767 [Byte1]: 32
2702 06:02:24.376268
2703 06:02:24.379373 Set Vref, RX VrefLevel [Byte0]: 33
2704 06:02:24.382234 [Byte1]: 33
2705 06:02:24.382647
2706 06:02:24.386000 Set Vref, RX VrefLevel [Byte0]: 34
2707 06:02:24.388969 [Byte1]: 34
2708 06:02:24.393703
2709 06:02:24.394243 Set Vref, RX VrefLevel [Byte0]: 35
2710 06:02:24.396854 [Byte1]: 35
2711 06:02:24.401151
2712 06:02:24.401706 Set Vref, RX VrefLevel [Byte0]: 36
2713 06:02:24.404532 [Byte1]: 36
2714 06:02:24.409154
2715 06:02:24.409708 Set Vref, RX VrefLevel [Byte0]: 37
2716 06:02:24.412945 [Byte1]: 37
2717 06:02:24.417102
2718 06:02:24.417656 Set Vref, RX VrefLevel [Byte0]: 38
2719 06:02:24.420635 [Byte1]: 38
2720 06:02:24.425403
2721 06:02:24.425977 Set Vref, RX VrefLevel [Byte0]: 39
2722 06:02:24.428548 [Byte1]: 39
2723 06:02:24.433341
2724 06:02:24.433911 Set Vref, RX VrefLevel [Byte0]: 40
2725 06:02:24.436617 [Byte1]: 40
2726 06:02:24.441576
2727 06:02:24.442103 Set Vref, RX VrefLevel [Byte0]: 41
2728 06:02:24.444402 [Byte1]: 41
2729 06:02:24.448757
2730 06:02:24.449395 Set Vref, RX VrefLevel [Byte0]: 42
2731 06:02:24.452126 [Byte1]: 42
2732 06:02:24.456920
2733 06:02:24.457330 Set Vref, RX VrefLevel [Byte0]: 43
2734 06:02:24.460197 [Byte1]: 43
2735 06:02:24.465565
2736 06:02:24.466079 Set Vref, RX VrefLevel [Byte0]: 44
2737 06:02:24.468978 [Byte1]: 44
2738 06:02:24.473667
2739 06:02:24.474177 Set Vref, RX VrefLevel [Byte0]: 45
2740 06:02:24.476980 [Byte1]: 45
2741 06:02:24.481344
2742 06:02:24.481947 Set Vref, RX VrefLevel [Byte0]: 46
2743 06:02:24.485024 [Byte1]: 46
2744 06:02:24.489549
2745 06:02:24.490289 Set Vref, RX VrefLevel [Byte0]: 47
2746 06:02:24.492459 [Byte1]: 47
2747 06:02:24.497061
2748 06:02:24.497552 Set Vref, RX VrefLevel [Byte0]: 48
2749 06:02:24.500959 [Byte1]: 48
2750 06:02:24.505587
2751 06:02:24.506136 Set Vref, RX VrefLevel [Byte0]: 49
2752 06:02:24.509080 [Byte1]: 49
2753 06:02:24.513046
2754 06:02:24.513655 Set Vref, RX VrefLevel [Byte0]: 50
2755 06:02:24.516201 [Byte1]: 50
2756 06:02:24.521015
2757 06:02:24.521428 Set Vref, RX VrefLevel [Byte0]: 51
2758 06:02:24.524304 [Byte1]: 51
2759 06:02:24.529383
2760 06:02:24.529902 Set Vref, RX VrefLevel [Byte0]: 52
2761 06:02:24.532196 [Byte1]: 52
2762 06:02:24.536974
2763 06:02:24.537525 Set Vref, RX VrefLevel [Byte0]: 53
2764 06:02:24.540388 [Byte1]: 53
2765 06:02:24.544827
2766 06:02:24.545423 Set Vref, RX VrefLevel [Byte0]: 54
2767 06:02:24.548129 [Byte1]: 54
2768 06:02:24.552815
2769 06:02:24.553221 Set Vref, RX VrefLevel [Byte0]: 55
2770 06:02:24.556554 [Byte1]: 55
2771 06:02:24.560741
2772 06:02:24.561149 Set Vref, RX VrefLevel [Byte0]: 56
2773 06:02:24.564175 [Byte1]: 56
2774 06:02:24.569161
2775 06:02:24.569617 Set Vref, RX VrefLevel [Byte0]: 57
2776 06:02:24.572444 [Byte1]: 57
2777 06:02:24.577108
2778 06:02:24.577713 Set Vref, RX VrefLevel [Byte0]: 58
2779 06:02:24.580639 [Byte1]: 58
2780 06:02:24.585399
2781 06:02:24.586005 Set Vref, RX VrefLevel [Byte0]: 59
2782 06:02:24.588300 [Byte1]: 59
2783 06:02:24.592810
2784 06:02:24.593667 Set Vref, RX VrefLevel [Byte0]: 60
2785 06:02:24.596449 [Byte1]: 60
2786 06:02:24.600808
2787 06:02:24.601274 Set Vref, RX VrefLevel [Byte0]: 61
2788 06:02:24.604326 [Byte1]: 61
2789 06:02:24.609100
2790 06:02:24.612097 Set Vref, RX VrefLevel [Byte0]: 62
2791 06:02:24.612516 [Byte1]: 62
2792 06:02:24.617098
2793 06:02:24.617691 Set Vref, RX VrefLevel [Byte0]: 63
2794 06:02:24.620514 [Byte1]: 63
2795 06:02:24.625200
2796 06:02:24.625830 Set Vref, RX VrefLevel [Byte0]: 64
2797 06:02:24.628569 [Byte1]: 64
2798 06:02:24.633002
2799 06:02:24.633413 Set Vref, RX VrefLevel [Byte0]: 65
2800 06:02:24.636465 [Byte1]: 65
2801 06:02:24.641145
2802 06:02:24.641595 Set Vref, RX VrefLevel [Byte0]: 66
2803 06:02:24.644631 [Byte1]: 66
2804 06:02:24.649190
2805 06:02:24.649671 Set Vref, RX VrefLevel [Byte0]: 67
2806 06:02:24.652612 [Byte1]: 67
2807 06:02:24.657193
2808 06:02:24.657681 Set Vref, RX VrefLevel [Byte0]: 68
2809 06:02:24.660708 [Byte1]: 68
2810 06:02:24.665198
2811 06:02:24.665651 Set Vref, RX VrefLevel [Byte0]: 69
2812 06:02:24.668142 [Byte1]: 69
2813 06:02:24.673210
2814 06:02:24.673737 Set Vref, RX VrefLevel [Byte0]: 70
2815 06:02:24.676589 [Byte1]: 70
2816 06:02:24.681541
2817 06:02:24.681975 Set Vref, RX VrefLevel [Byte0]: 71
2818 06:02:24.684407 [Byte1]: 71
2819 06:02:24.689558
2820 06:02:24.690067 Set Vref, RX VrefLevel [Byte0]: 72
2821 06:02:24.692308 [Byte1]: 72
2822 06:02:24.696909
2823 06:02:24.697532 Set Vref, RX VrefLevel [Byte0]: 73
2824 06:02:24.700265 [Byte1]: 73
2825 06:02:24.705401
2826 06:02:24.705983 Final RX Vref Byte 0 = 59 to rank0
2827 06:02:24.708607 Final RX Vref Byte 1 = 54 to rank0
2828 06:02:24.711921 Final RX Vref Byte 0 = 59 to rank1
2829 06:02:24.715513 Final RX Vref Byte 1 = 54 to rank1==
2830 06:02:24.718423 Dram Type= 6, Freq= 0, CH_0, rank 0
2831 06:02:24.725441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2832 06:02:24.726043 ==
2833 06:02:24.726411 DQS Delay:
2834 06:02:24.728044 DQS0 = 0, DQS1 = 0
2835 06:02:24.728505 DQM Delay:
2836 06:02:24.728870 DQM0 = 111, DQM1 = 101
2837 06:02:24.731802 DQ Delay:
2838 06:02:24.734884 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
2839 06:02:24.738482 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2840 06:02:24.741563 DQ8 =90, DQ9 =86, DQ10 =102, DQ11 =94
2841 06:02:24.744987 DQ12 =108, DQ13 =106, DQ14 =116, DQ15 =110
2842 06:02:24.745613
2843 06:02:24.745994
2844 06:02:24.751758 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2845 06:02:24.754856 CH0 RK0: MR19=303, MR18=FBFB
2846 06:02:24.761256 CH0_RK0: MR19=0x303, MR18=0xFBFB, DQSOSC=412, MR23=63, INC=38, DEC=25
2847 06:02:24.761714
2848 06:02:24.765787 ----->DramcWriteLeveling(PI) begin...
2849 06:02:24.766312 ==
2850 06:02:24.768712 Dram Type= 6, Freq= 0, CH_0, rank 1
2851 06:02:24.771528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2852 06:02:24.774917 ==
2853 06:02:24.775444 Write leveling (Byte 0): 32 => 32
2854 06:02:24.778458 Write leveling (Byte 1): 29 => 29
2855 06:02:24.781783 DramcWriteLeveling(PI) end<-----
2856 06:02:24.782434
2857 06:02:24.782896 ==
2858 06:02:24.785246 Dram Type= 6, Freq= 0, CH_0, rank 1
2859 06:02:24.791806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2860 06:02:24.792328 ==
2861 06:02:24.792660 [Gating] SW mode calibration
2862 06:02:24.802169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2863 06:02:24.805097 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2864 06:02:24.811851 0 15 0 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
2865 06:02:24.814971 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 06:02:24.818165 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 06:02:24.822222 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 06:02:24.827939 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 06:02:24.831397 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 06:02:24.835077 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2871 06:02:24.841533 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
2872 06:02:24.844716 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 06:02:24.848039 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 06:02:24.854947 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 06:02:24.858539 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 06:02:24.861336 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 06:02:24.868140 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 06:02:24.871591 1 0 24 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
2879 06:02:24.874973 1 0 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
2880 06:02:24.881655 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2881 06:02:24.884630 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 06:02:24.888159 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 06:02:24.894962 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 06:02:24.898406 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 06:02:24.901828 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 06:02:24.905025 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 06:02:24.911452 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 06:02:24.914938 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 06:02:24.917984 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 06:02:24.925030 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 06:02:24.928361 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 06:02:24.931488 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 06:02:24.938474 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 06:02:24.941605 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 06:02:24.945007 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 06:02:24.951415 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 06:02:24.954896 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 06:02:24.958489 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 06:02:24.964826 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 06:02:24.968364 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 06:02:24.971518 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 06:02:24.978272 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2903 06:02:24.981432 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2904 06:02:24.984863 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2905 06:02:24.987926 Total UI for P1: 0, mck2ui 16
2906 06:02:24.991309 best dqsien dly found for B0: ( 1, 3, 26)
2907 06:02:24.994742 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 06:02:24.998031 Total UI for P1: 0, mck2ui 16
2909 06:02:25.001502 best dqsien dly found for B1: ( 1, 4, 0)
2910 06:02:25.005051 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2911 06:02:25.011390 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2912 06:02:25.011801
2913 06:02:25.014961 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2914 06:02:25.018151 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2915 06:02:25.021653 [Gating] SW calibration Done
2916 06:02:25.022108 ==
2917 06:02:25.024666 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 06:02:25.028132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 06:02:25.028770 ==
2920 06:02:25.029362 RX Vref Scan: 0
2921 06:02:25.029915
2922 06:02:25.031627 RX Vref 0 -> 0, step: 1
2923 06:02:25.032144
2924 06:02:25.035106 RX Delay -40 -> 252, step: 8
2925 06:02:25.038429 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2926 06:02:25.041569 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2927 06:02:25.048429 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2928 06:02:25.051502 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2929 06:02:25.055091 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2930 06:02:25.058043 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2931 06:02:25.061387 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2932 06:02:25.068451 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2933 06:02:25.071803 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2934 06:02:25.074776 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2935 06:02:25.078047 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2936 06:02:25.081559 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2937 06:02:25.085098 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2938 06:02:25.091541 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2939 06:02:25.094935 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2940 06:02:25.098433 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2941 06:02:25.098974 ==
2942 06:02:25.101588 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 06:02:25.104716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 06:02:25.105127 ==
2945 06:02:25.108354 DQS Delay:
2946 06:02:25.108773 DQS0 = 0, DQS1 = 0
2947 06:02:25.111564 DQM Delay:
2948 06:02:25.111979 DQM0 = 113, DQM1 = 101
2949 06:02:25.114925 DQ Delay:
2950 06:02:25.118005 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2951 06:02:25.121687 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2952 06:02:25.125219 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2953 06:02:25.128309 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
2954 06:02:25.128720
2955 06:02:25.129046
2956 06:02:25.129349 ==
2957 06:02:25.131663 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 06:02:25.135169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 06:02:25.135587 ==
2960 06:02:25.135916
2961 06:02:25.136224
2962 06:02:25.138026 TX Vref Scan disable
2963 06:02:25.141419 == TX Byte 0 ==
2964 06:02:25.144658 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2965 06:02:25.147875 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2966 06:02:25.151446 == TX Byte 1 ==
2967 06:02:25.154768 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2968 06:02:25.158007 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2969 06:02:25.158453 ==
2970 06:02:25.161665 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 06:02:25.164506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 06:02:25.167797 ==
2973 06:02:25.177944 TX Vref=22, minBit 5, minWin=26, winSum=429
2974 06:02:25.181876 TX Vref=24, minBit 1, minWin=26, winSum=433
2975 06:02:25.184650 TX Vref=26, minBit 0, minWin=27, winSum=436
2976 06:02:25.188185 TX Vref=28, minBit 8, minWin=26, winSum=440
2977 06:02:25.191719 TX Vref=30, minBit 1, minWin=27, winSum=444
2978 06:02:25.194901 TX Vref=32, minBit 8, minWin=26, winSum=439
2979 06:02:25.201435 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 30
2980 06:02:25.202067
2981 06:02:25.204744 Final TX Range 1 Vref 30
2982 06:02:25.205373
2983 06:02:25.205926 ==
2984 06:02:25.208463 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 06:02:25.211708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 06:02:25.212183 ==
2987 06:02:25.212634
2988 06:02:25.213135
2989 06:02:25.214898 TX Vref Scan disable
2990 06:02:25.218384 == TX Byte 0 ==
2991 06:02:25.221763 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2992 06:02:25.224917 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2993 06:02:25.228382 == TX Byte 1 ==
2994 06:02:25.231456 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2995 06:02:25.235217 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2996 06:02:25.235660
2997 06:02:25.238091 [DATLAT]
2998 06:02:25.238525 Freq=1200, CH0 RK1
2999 06:02:25.238855
3000 06:02:25.241928 DATLAT Default: 0xd
3001 06:02:25.242397 0, 0xFFFF, sum = 0
3002 06:02:25.244685 1, 0xFFFF, sum = 0
3003 06:02:25.245246 2, 0xFFFF, sum = 0
3004 06:02:25.248363 3, 0xFFFF, sum = 0
3005 06:02:25.248973 4, 0xFFFF, sum = 0
3006 06:02:25.251508 5, 0xFFFF, sum = 0
3007 06:02:25.252084 6, 0xFFFF, sum = 0
3008 06:02:25.254961 7, 0xFFFF, sum = 0
3009 06:02:25.255499 8, 0xFFFF, sum = 0
3010 06:02:25.258392 9, 0xFFFF, sum = 0
3011 06:02:25.261762 10, 0xFFFF, sum = 0
3012 06:02:25.262206 11, 0xFFFF, sum = 0
3013 06:02:25.264881 12, 0x0, sum = 1
3014 06:02:25.265297 13, 0x0, sum = 2
3015 06:02:25.265706 14, 0x0, sum = 3
3016 06:02:25.268325 15, 0x0, sum = 4
3017 06:02:25.268780 best_step = 13
3018 06:02:25.269124
3019 06:02:25.271366 ==
3020 06:02:25.271840 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 06:02:25.278085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 06:02:25.278533 ==
3023 06:02:25.278969 RX Vref Scan: 0
3024 06:02:25.279434
3025 06:02:25.281592 RX Vref 0 -> 0, step: 1
3026 06:02:25.282171
3027 06:02:25.284798 RX Delay -37 -> 252, step: 4
3028 06:02:25.287777 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3029 06:02:25.294887 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3030 06:02:25.297723 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3031 06:02:25.301056 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3032 06:02:25.304834 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3033 06:02:25.308043 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3034 06:02:25.311245 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3035 06:02:25.317881 iDelay=195, Bit 7, Center 116 (43 ~ 190) 148
3036 06:02:25.321228 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3037 06:02:25.324448 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3038 06:02:25.328371 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3039 06:02:25.331032 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3040 06:02:25.338066 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3041 06:02:25.341818 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3042 06:02:25.344828 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3043 06:02:25.347948 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3044 06:02:25.348390 ==
3045 06:02:25.351331 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 06:02:25.357762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 06:02:25.358227 ==
3048 06:02:25.358590 DQS Delay:
3049 06:02:25.361332 DQS0 = 0, DQS1 = 0
3050 06:02:25.361954 DQM Delay:
3051 06:02:25.362458 DQM0 = 110, DQM1 = 101
3052 06:02:25.364647 DQ Delay:
3053 06:02:25.368229 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3054 06:02:25.371050 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =116
3055 06:02:25.374748 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3056 06:02:25.377791 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3057 06:02:25.378211
3058 06:02:25.378580
3059 06:02:25.388017 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3060 06:02:25.388456 CH0 RK1: MR19=403, MR18=13FB
3061 06:02:25.394661 CH0_RK1: MR19=0x403, MR18=0x13FB, DQSOSC=402, MR23=63, INC=40, DEC=27
3062 06:02:25.397855 [RxdqsGatingPostProcess] freq 1200
3063 06:02:25.404814 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3064 06:02:25.407843 best DQS0 dly(2T, 0.5T) = (0, 11)
3065 06:02:25.411294 best DQS1 dly(2T, 0.5T) = (0, 12)
3066 06:02:25.414323 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3067 06:02:25.414805 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3068 06:02:25.417904 best DQS0 dly(2T, 0.5T) = (0, 11)
3069 06:02:25.421220 best DQS1 dly(2T, 0.5T) = (0, 12)
3070 06:02:25.424339 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3071 06:02:25.427655 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3072 06:02:25.431083 Pre-setting of DQS Precalculation
3073 06:02:25.437992 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3074 06:02:25.438504 ==
3075 06:02:25.441064 Dram Type= 6, Freq= 0, CH_1, rank 0
3076 06:02:25.444591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 06:02:25.445004 ==
3078 06:02:25.451218 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3079 06:02:25.454379 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3080 06:02:25.464029 [CA 0] Center 37 (7~67) winsize 61
3081 06:02:25.467436 [CA 1] Center 37 (7~68) winsize 62
3082 06:02:25.470855 [CA 2] Center 34 (4~64) winsize 61
3083 06:02:25.474121 [CA 3] Center 33 (3~64) winsize 62
3084 06:02:25.477822 [CA 4] Center 34 (4~64) winsize 61
3085 06:02:25.480801 [CA 5] Center 33 (3~63) winsize 61
3086 06:02:25.481230
3087 06:02:25.483945 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3088 06:02:25.484464
3089 06:02:25.487666 [CATrainingPosCal] consider 1 rank data
3090 06:02:25.490568 u2DelayCellTimex100 = 270/100 ps
3091 06:02:25.494142 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3092 06:02:25.500553 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 06:02:25.504186 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3094 06:02:25.507363 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3095 06:02:25.510485 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 06:02:25.513922 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3097 06:02:25.514379
3098 06:02:25.517553 CA PerBit enable=1, Macro0, CA PI delay=33
3099 06:02:25.518027
3100 06:02:25.520474 [CBTSetCACLKResult] CA Dly = 33
3101 06:02:25.520931 CS Dly: 6 (0~37)
3102 06:02:25.524183 ==
3103 06:02:25.524741 Dram Type= 6, Freq= 0, CH_1, rank 1
3104 06:02:25.530661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 06:02:25.531214 ==
3106 06:02:25.534116 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3107 06:02:25.540500 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3108 06:02:25.549613 [CA 0] Center 37 (7~68) winsize 62
3109 06:02:25.552937 [CA 1] Center 37 (7~68) winsize 62
3110 06:02:25.556022 [CA 2] Center 34 (4~65) winsize 62
3111 06:02:25.559590 [CA 3] Center 33 (3~64) winsize 62
3112 06:02:25.563081 [CA 4] Center 34 (4~65) winsize 62
3113 06:02:25.566736 [CA 5] Center 33 (3~63) winsize 61
3114 06:02:25.567146
3115 06:02:25.569831 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3116 06:02:25.570379
3117 06:02:25.572801 [CATrainingPosCal] consider 2 rank data
3118 06:02:25.576436 u2DelayCellTimex100 = 270/100 ps
3119 06:02:25.579471 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3120 06:02:25.582852 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3121 06:02:25.589542 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 06:02:25.593085 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3123 06:02:25.596295 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3124 06:02:25.599900 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3125 06:02:25.600459
3126 06:02:25.602932 CA PerBit enable=1, Macro0, CA PI delay=33
3127 06:02:25.603394
3128 06:02:25.606436 [CBTSetCACLKResult] CA Dly = 33
3129 06:02:25.606883 CS Dly: 7 (0~40)
3130 06:02:25.607257
3131 06:02:25.609270 ----->DramcWriteLeveling(PI) begin...
3132 06:02:25.612755 ==
3133 06:02:25.616340 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 06:02:25.619701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 06:02:25.620178 ==
3136 06:02:25.623064 Write leveling (Byte 0): 23 => 23
3137 06:02:25.626087 Write leveling (Byte 1): 30 => 30
3138 06:02:25.629796 DramcWriteLeveling(PI) end<-----
3139 06:02:25.630235
3140 06:02:25.630582 ==
3141 06:02:25.632598 Dram Type= 6, Freq= 0, CH_1, rank 0
3142 06:02:25.636318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 06:02:25.636728 ==
3144 06:02:25.639603 [Gating] SW mode calibration
3145 06:02:25.646342 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3146 06:02:25.653001 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3147 06:02:25.656079 0 15 0 | B1->B0 | 2c2c 2525 | 0 0 | (0 0) (0 0)
3148 06:02:25.659709 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 06:02:25.662960 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 06:02:25.669321 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 06:02:25.672686 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 06:02:25.676189 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 06:02:25.682899 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 06:02:25.686317 0 15 28 | B1->B0 | 2d2d 3030 | 1 1 | (1 1) (1 1)
3155 06:02:25.689589 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 06:02:25.696058 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 06:02:25.699460 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 06:02:25.703152 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 06:02:25.709579 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 06:02:25.713107 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 06:02:25.716268 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3162 06:02:25.723075 1 0 28 | B1->B0 | 3e3e 3636 | 0 0 | (0 0) (0 0)
3163 06:02:25.726322 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 06:02:25.729470 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 06:02:25.736205 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 06:02:25.739748 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 06:02:25.742538 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 06:02:25.749455 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 06:02:25.752835 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 06:02:25.756030 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3171 06:02:25.762685 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3172 06:02:25.766396 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 06:02:25.769398 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 06:02:25.773043 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 06:02:25.779425 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 06:02:25.782696 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 06:02:25.786041 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 06:02:25.792988 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 06:02:25.795894 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 06:02:25.799125 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 06:02:25.806253 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 06:02:25.809356 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 06:02:25.813025 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 06:02:25.819470 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 06:02:25.823185 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 06:02:25.826089 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3187 06:02:25.832730 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3188 06:02:25.833277 Total UI for P1: 0, mck2ui 16
3189 06:02:25.838968 best dqsien dly found for B1: ( 1, 3, 28)
3190 06:02:25.842731 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 06:02:25.846464 Total UI for P1: 0, mck2ui 16
3192 06:02:25.849208 best dqsien dly found for B0: ( 1, 3, 30)
3193 06:02:25.852603 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3194 06:02:25.856058 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3195 06:02:25.856633
3196 06:02:25.859538 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3197 06:02:25.862613 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3198 06:02:25.866030 [Gating] SW calibration Done
3199 06:02:25.866480 ==
3200 06:02:25.869024 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 06:02:25.872613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 06:02:25.873183 ==
3203 06:02:25.876095 RX Vref Scan: 0
3204 06:02:25.876669
3205 06:02:25.879340 RX Vref 0 -> 0, step: 1
3206 06:02:25.879792
3207 06:02:25.880236 RX Delay -40 -> 252, step: 8
3208 06:02:25.885949 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3209 06:02:25.889469 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3210 06:02:25.892400 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3211 06:02:25.896207 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3212 06:02:25.898861 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3213 06:02:25.905777 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3214 06:02:25.909323 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3215 06:02:25.912373 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3216 06:02:25.915795 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3217 06:02:25.919227 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3218 06:02:25.925570 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3219 06:02:25.929424 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3220 06:02:25.932451 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3221 06:02:25.935496 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3222 06:02:25.939080 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3223 06:02:25.945899 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3224 06:02:25.946455 ==
3225 06:02:25.949264 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 06:02:25.952855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 06:02:25.953287 ==
3228 06:02:25.953850 DQS Delay:
3229 06:02:25.956097 DQS0 = 0, DQS1 = 0
3230 06:02:25.956648 DQM Delay:
3231 06:02:25.959172 DQM0 = 114, DQM1 = 106
3232 06:02:25.959643 DQ Delay:
3233 06:02:25.962248 DQ0 =115, DQ1 =111, DQ2 =99, DQ3 =115
3234 06:02:25.965847 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3235 06:02:25.969385 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3236 06:02:25.972445 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3237 06:02:25.972940
3238 06:02:25.973465
3239 06:02:25.974046 ==
3240 06:02:25.975999 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 06:02:25.982640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 06:02:25.983100 ==
3243 06:02:25.983582
3244 06:02:25.984094
3245 06:02:25.984494 TX Vref Scan disable
3246 06:02:25.986293 == TX Byte 0 ==
3247 06:02:25.989818 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3248 06:02:25.993177 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3249 06:02:25.996064 == TX Byte 1 ==
3250 06:02:25.999317 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3251 06:02:26.003068 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3252 06:02:26.006010 ==
3253 06:02:26.009664 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 06:02:26.012917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 06:02:26.013448 ==
3256 06:02:26.025035 TX Vref=22, minBit 3, minWin=24, winSum=412
3257 06:02:26.027529 TX Vref=24, minBit 1, minWin=25, winSum=418
3258 06:02:26.031138 TX Vref=26, minBit 1, minWin=26, winSum=427
3259 06:02:26.034609 TX Vref=28, minBit 1, minWin=26, winSum=427
3260 06:02:26.037592 TX Vref=30, minBit 1, minWin=26, winSum=426
3261 06:02:26.044363 TX Vref=32, minBit 1, minWin=26, winSum=424
3262 06:02:26.047892 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 26
3263 06:02:26.048308
3264 06:02:26.051143 Final TX Range 1 Vref 26
3265 06:02:26.051558
3266 06:02:26.051890 ==
3267 06:02:26.054479 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 06:02:26.057842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 06:02:26.058270 ==
3270 06:02:26.058598
3271 06:02:26.061037
3272 06:02:26.061444 TX Vref Scan disable
3273 06:02:26.064589 == TX Byte 0 ==
3274 06:02:26.068196 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3275 06:02:26.071258 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3276 06:02:26.074221 == TX Byte 1 ==
3277 06:02:26.077881 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3278 06:02:26.081266 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3279 06:02:26.081752
3280 06:02:26.085009 [DATLAT]
3281 06:02:26.085577 Freq=1200, CH1 RK0
3282 06:02:26.085919
3283 06:02:26.087952 DATLAT Default: 0xd
3284 06:02:26.088465 0, 0xFFFF, sum = 0
3285 06:02:26.091217 1, 0xFFFF, sum = 0
3286 06:02:26.091694 2, 0xFFFF, sum = 0
3287 06:02:26.095097 3, 0xFFFF, sum = 0
3288 06:02:26.095634 4, 0xFFFF, sum = 0
3289 06:02:26.097688 5, 0xFFFF, sum = 0
3290 06:02:26.098108 6, 0xFFFF, sum = 0
3291 06:02:26.101613 7, 0xFFFF, sum = 0
3292 06:02:26.104724 8, 0xFFFF, sum = 0
3293 06:02:26.105145 9, 0xFFFF, sum = 0
3294 06:02:26.107706 10, 0xFFFF, sum = 0
3295 06:02:26.108120 11, 0xFFFF, sum = 0
3296 06:02:26.110968 12, 0x0, sum = 1
3297 06:02:26.111382 13, 0x0, sum = 2
3298 06:02:26.114381 14, 0x0, sum = 3
3299 06:02:26.114795 15, 0x0, sum = 4
3300 06:02:26.115122 best_step = 13
3301 06:02:26.115421
3302 06:02:26.117828 ==
3303 06:02:26.121197 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 06:02:26.124502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 06:02:26.124914 ==
3306 06:02:26.125239 RX Vref Scan: 1
3307 06:02:26.125583
3308 06:02:26.128408 Set Vref Range= 32 -> 127
3309 06:02:26.128915
3310 06:02:26.131267 RX Vref 32 -> 127, step: 1
3311 06:02:26.131780
3312 06:02:26.134725 RX Delay -21 -> 252, step: 4
3313 06:02:26.135236
3314 06:02:26.138003 Set Vref, RX VrefLevel [Byte0]: 32
3315 06:02:26.141355 [Byte1]: 32
3316 06:02:26.141813
3317 06:02:26.144833 Set Vref, RX VrefLevel [Byte0]: 33
3318 06:02:26.148241 [Byte1]: 33
3319 06:02:26.148650
3320 06:02:26.150909 Set Vref, RX VrefLevel [Byte0]: 34
3321 06:02:26.154456 [Byte1]: 34
3322 06:02:26.158656
3323 06:02:26.159063 Set Vref, RX VrefLevel [Byte0]: 35
3324 06:02:26.161990 [Byte1]: 35
3325 06:02:26.166651
3326 06:02:26.167058 Set Vref, RX VrefLevel [Byte0]: 36
3327 06:02:26.170055 [Byte1]: 36
3328 06:02:26.174209
3329 06:02:26.174641 Set Vref, RX VrefLevel [Byte0]: 37
3330 06:02:26.178115 [Byte1]: 37
3331 06:02:26.182737
3332 06:02:26.183228 Set Vref, RX VrefLevel [Byte0]: 38
3333 06:02:26.185742 [Byte1]: 38
3334 06:02:26.190209
3335 06:02:26.190734 Set Vref, RX VrefLevel [Byte0]: 39
3336 06:02:26.193893 [Byte1]: 39
3337 06:02:26.198246
3338 06:02:26.198828 Set Vref, RX VrefLevel [Byte0]: 40
3339 06:02:26.201774 [Byte1]: 40
3340 06:02:26.206337
3341 06:02:26.206742 Set Vref, RX VrefLevel [Byte0]: 41
3342 06:02:26.209657 [Byte1]: 41
3343 06:02:26.214186
3344 06:02:26.214603 Set Vref, RX VrefLevel [Byte0]: 42
3345 06:02:26.217756 [Byte1]: 42
3346 06:02:26.221710
3347 06:02:26.222117 Set Vref, RX VrefLevel [Byte0]: 43
3348 06:02:26.228598 [Byte1]: 43
3349 06:02:26.229008
3350 06:02:26.232352 Set Vref, RX VrefLevel [Byte0]: 44
3351 06:02:26.234984 [Byte1]: 44
3352 06:02:26.235397
3353 06:02:26.238461 Set Vref, RX VrefLevel [Byte0]: 45
3354 06:02:26.241956 [Byte1]: 45
3355 06:02:26.245690
3356 06:02:26.246095 Set Vref, RX VrefLevel [Byte0]: 46
3357 06:02:26.249290 [Byte1]: 46
3358 06:02:26.253878
3359 06:02:26.254285 Set Vref, RX VrefLevel [Byte0]: 47
3360 06:02:26.256779 [Byte1]: 47
3361 06:02:26.261791
3362 06:02:26.262198 Set Vref, RX VrefLevel [Byte0]: 48
3363 06:02:26.264869 [Byte1]: 48
3364 06:02:26.269511
3365 06:02:26.269927 Set Vref, RX VrefLevel [Byte0]: 49
3366 06:02:26.273289 [Byte1]: 49
3367 06:02:26.277774
3368 06:02:26.278285 Set Vref, RX VrefLevel [Byte0]: 50
3369 06:02:26.280841 [Byte1]: 50
3370 06:02:26.285545
3371 06:02:26.285957 Set Vref, RX VrefLevel [Byte0]: 51
3372 06:02:26.288858 [Byte1]: 51
3373 06:02:26.293363
3374 06:02:26.293815 Set Vref, RX VrefLevel [Byte0]: 52
3375 06:02:26.296313 [Byte1]: 52
3376 06:02:26.301296
3377 06:02:26.301759 Set Vref, RX VrefLevel [Byte0]: 53
3378 06:02:26.304247 [Byte1]: 53
3379 06:02:26.309195
3380 06:02:26.309662 Set Vref, RX VrefLevel [Byte0]: 54
3381 06:02:26.312954 [Byte1]: 54
3382 06:02:26.317348
3383 06:02:26.317798 Set Vref, RX VrefLevel [Byte0]: 55
3384 06:02:26.320935 [Byte1]: 55
3385 06:02:26.325194
3386 06:02:26.325772 Set Vref, RX VrefLevel [Byte0]: 56
3387 06:02:26.328350 [Byte1]: 56
3388 06:02:26.332731
3389 06:02:26.333148 Set Vref, RX VrefLevel [Byte0]: 57
3390 06:02:26.336065 [Byte1]: 57
3391 06:02:26.341031
3392 06:02:26.341589 Set Vref, RX VrefLevel [Byte0]: 58
3393 06:02:26.344624 [Byte1]: 58
3394 06:02:26.348759
3395 06:02:26.349275 Set Vref, RX VrefLevel [Byte0]: 59
3396 06:02:26.352277 [Byte1]: 59
3397 06:02:26.357009
3398 06:02:26.357432 Set Vref, RX VrefLevel [Byte0]: 60
3399 06:02:26.360204 [Byte1]: 60
3400 06:02:26.364588
3401 06:02:26.365104 Set Vref, RX VrefLevel [Byte0]: 61
3402 06:02:26.368007 [Byte1]: 61
3403 06:02:26.372389
3404 06:02:26.372894 Set Vref, RX VrefLevel [Byte0]: 62
3405 06:02:26.375948 [Byte1]: 62
3406 06:02:26.380810
3407 06:02:26.381322 Set Vref, RX VrefLevel [Byte0]: 63
3408 06:02:26.384058 [Byte1]: 63
3409 06:02:26.388731
3410 06:02:26.389242 Set Vref, RX VrefLevel [Byte0]: 64
3411 06:02:26.391787 [Byte1]: 64
3412 06:02:26.396618
3413 06:02:26.397170 Final RX Vref Byte 0 = 58 to rank0
3414 06:02:26.400235 Final RX Vref Byte 1 = 50 to rank0
3415 06:02:26.402956 Final RX Vref Byte 0 = 58 to rank1
3416 06:02:26.406299 Final RX Vref Byte 1 = 50 to rank1==
3417 06:02:26.410002 Dram Type= 6, Freq= 0, CH_1, rank 0
3418 06:02:26.416903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 06:02:26.417550 ==
3420 06:02:26.417940 DQS Delay:
3421 06:02:26.418285 DQS0 = 0, DQS1 = 0
3422 06:02:26.419530 DQM Delay:
3423 06:02:26.419987 DQM0 = 114, DQM1 = 106
3424 06:02:26.422744 DQ Delay:
3425 06:02:26.426928 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =112
3426 06:02:26.429434 DQ4 =110, DQ5 =124, DQ6 =124, DQ7 =112
3427 06:02:26.433465 DQ8 =90, DQ9 =100, DQ10 =104, DQ11 =100
3428 06:02:26.436437 DQ12 =116, DQ13 =112, DQ14 =116, DQ15 =112
3429 06:02:26.436953
3430 06:02:26.437290
3431 06:02:26.446136 [DQSOSCAuto] RK0, (LSB)MR18= 0xeef5, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3432 06:02:26.446643 CH1 RK0: MR19=303, MR18=EEF5
3433 06:02:26.452809 CH1_RK0: MR19=0x303, MR18=0xEEF5, DQSOSC=414, MR23=63, INC=38, DEC=25
3434 06:02:26.453243
3435 06:02:26.456282 ----->DramcWriteLeveling(PI) begin...
3436 06:02:26.456708 ==
3437 06:02:26.459083 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 06:02:26.465842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 06:02:26.466258 ==
3440 06:02:26.469359 Write leveling (Byte 0): 24 => 24
3441 06:02:26.469830 Write leveling (Byte 1): 28 => 28
3442 06:02:26.473006 DramcWriteLeveling(PI) end<-----
3443 06:02:26.473416
3444 06:02:26.473776 ==
3445 06:02:26.476279 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 06:02:26.482679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 06:02:26.483146 ==
3448 06:02:26.485879 [Gating] SW mode calibration
3449 06:02:26.492493 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3450 06:02:26.495725 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3451 06:02:26.502599 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 06:02:26.505800 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 06:02:26.509431 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 06:02:26.515738 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 06:02:26.519247 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 06:02:26.522250 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3457 06:02:26.528861 0 15 24 | B1->B0 | 3434 2525 | 0 0 | (0 1) (0 0)
3458 06:02:26.532473 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3459 06:02:26.535685 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 06:02:26.542292 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 06:02:26.545445 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 06:02:26.548902 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 06:02:26.552317 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 06:02:26.559060 1 0 20 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
3465 06:02:26.562648 1 0 24 | B1->B0 | 2726 4646 | 1 0 | (0 0) (0 0)
3466 06:02:26.565758 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3467 06:02:26.572377 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 06:02:26.575981 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 06:02:26.579017 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 06:02:26.585605 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 06:02:26.589193 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 06:02:26.592313 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 06:02:26.598603 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3474 06:02:26.602107 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3475 06:02:26.605275 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 06:02:26.611806 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 06:02:26.615340 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 06:02:26.618709 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 06:02:26.625530 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 06:02:26.628234 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 06:02:26.631531 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 06:02:26.638221 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 06:02:26.641874 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 06:02:26.644751 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 06:02:26.651524 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 06:02:26.654584 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 06:02:26.658562 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 06:02:26.664510 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 06:02:26.668016 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3490 06:02:26.671400 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3491 06:02:26.674766 Total UI for P1: 0, mck2ui 16
3492 06:02:26.677946 best dqsien dly found for B0: ( 1, 3, 24)
3493 06:02:26.684517 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 06:02:26.684940 Total UI for P1: 0, mck2ui 16
3495 06:02:26.691457 best dqsien dly found for B1: ( 1, 3, 28)
3496 06:02:26.694360 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3497 06:02:26.697791 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3498 06:02:26.698333
3499 06:02:26.701310 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3500 06:02:26.704212 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3501 06:02:26.707745 [Gating] SW calibration Done
3502 06:02:26.708162 ==
3503 06:02:26.711008 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 06:02:26.714549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 06:02:26.714971 ==
3506 06:02:26.717576 RX Vref Scan: 0
3507 06:02:26.717993
3508 06:02:26.718325 RX Vref 0 -> 0, step: 1
3509 06:02:26.718632
3510 06:02:26.721182 RX Delay -40 -> 252, step: 8
3511 06:02:26.727674 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3512 06:02:26.730993 iDelay=200, Bit 1, Center 107 (40 ~ 175) 136
3513 06:02:26.734455 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3514 06:02:26.737452 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3515 06:02:26.741008 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3516 06:02:26.743948 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3517 06:02:26.750599 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3518 06:02:26.754163 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3519 06:02:26.757789 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3520 06:02:26.760611 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3521 06:02:26.764098 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3522 06:02:26.770552 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3523 06:02:26.773583 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3524 06:02:26.777040 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3525 06:02:26.780673 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3526 06:02:26.787281 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3527 06:02:26.787694 ==
3528 06:02:26.790740 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 06:02:26.793766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 06:02:26.794178 ==
3531 06:02:26.794500 DQS Delay:
3532 06:02:26.796951 DQS0 = 0, DQS1 = 0
3533 06:02:26.797361 DQM Delay:
3534 06:02:26.800539 DQM0 = 110, DQM1 = 107
3535 06:02:26.800950 DQ Delay:
3536 06:02:26.803462 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3537 06:02:26.806689 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3538 06:02:26.809979 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3539 06:02:26.813237 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3540 06:02:26.813317
3541 06:02:26.813380
3542 06:02:26.813439 ==
3543 06:02:26.816537 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 06:02:26.823159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 06:02:26.823240 ==
3546 06:02:26.823303
3547 06:02:26.823362
3548 06:02:26.826735 TX Vref Scan disable
3549 06:02:26.826815 == TX Byte 0 ==
3550 06:02:26.829607 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3551 06:02:26.836580 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3552 06:02:26.836660 == TX Byte 1 ==
3553 06:02:26.839311 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3554 06:02:26.846414 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3555 06:02:26.846495 ==
3556 06:02:26.849286 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 06:02:26.853374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 06:02:26.853455 ==
3559 06:02:26.865502 TX Vref=22, minBit 9, minWin=25, winSum=422
3560 06:02:26.868354 TX Vref=24, minBit 8, minWin=26, winSum=432
3561 06:02:26.872258 TX Vref=26, minBit 4, minWin=26, winSum=431
3562 06:02:26.875514 TX Vref=28, minBit 1, minWin=26, winSum=433
3563 06:02:26.878316 TX Vref=30, minBit 3, minWin=26, winSum=432
3564 06:02:26.885657 TX Vref=32, minBit 0, minWin=26, winSum=432
3565 06:02:26.888450 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 28
3566 06:02:26.888862
3567 06:02:26.892306 Final TX Range 1 Vref 28
3568 06:02:26.892821
3569 06:02:26.893151 ==
3570 06:02:26.894955 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 06:02:26.898396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 06:02:26.901816 ==
3573 06:02:26.902332
3574 06:02:26.902658
3575 06:02:26.902956 TX Vref Scan disable
3576 06:02:26.905337 == TX Byte 0 ==
3577 06:02:26.908297 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3578 06:02:26.914878 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3579 06:02:26.915412 == TX Byte 1 ==
3580 06:02:26.918257 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3581 06:02:26.925179 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3582 06:02:26.925718
3583 06:02:26.926058 [DATLAT]
3584 06:02:26.926366 Freq=1200, CH1 RK1
3585 06:02:26.926668
3586 06:02:26.928368 DATLAT Default: 0xd
3587 06:02:26.928783 0, 0xFFFF, sum = 0
3588 06:02:26.931648 1, 0xFFFF, sum = 0
3589 06:02:26.934722 2, 0xFFFF, sum = 0
3590 06:02:26.935147 3, 0xFFFF, sum = 0
3591 06:02:26.938514 4, 0xFFFF, sum = 0
3592 06:02:26.939047 5, 0xFFFF, sum = 0
3593 06:02:26.941562 6, 0xFFFF, sum = 0
3594 06:02:26.941987 7, 0xFFFF, sum = 0
3595 06:02:26.945194 8, 0xFFFF, sum = 0
3596 06:02:26.945762 9, 0xFFFF, sum = 0
3597 06:02:26.948132 10, 0xFFFF, sum = 0
3598 06:02:26.948548 11, 0xFFFF, sum = 0
3599 06:02:26.951236 12, 0x0, sum = 1
3600 06:02:26.951652 13, 0x0, sum = 2
3601 06:02:26.954668 14, 0x0, sum = 3
3602 06:02:26.955082 15, 0x0, sum = 4
3603 06:02:26.958048 best_step = 13
3604 06:02:26.958460
3605 06:02:26.959025 ==
3606 06:02:26.961471 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 06:02:26.965302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 06:02:26.965871 ==
3609 06:02:26.966210 RX Vref Scan: 0
3610 06:02:26.968274
3611 06:02:26.968784 RX Vref 0 -> 0, step: 1
3612 06:02:26.969110
3613 06:02:26.971440 RX Delay -21 -> 252, step: 4
3614 06:02:26.977863 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3615 06:02:26.981630 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3616 06:02:26.984482 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3617 06:02:26.988013 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3618 06:02:26.991450 iDelay=195, Bit 4, Center 106 (35 ~ 178) 144
3619 06:02:26.998102 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3620 06:02:27.001472 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3621 06:02:27.004317 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3622 06:02:27.007680 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3623 06:02:27.011259 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3624 06:02:27.018046 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3625 06:02:27.021059 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3626 06:02:27.024700 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3627 06:02:27.027635 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3628 06:02:27.030722 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3629 06:02:27.037829 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3630 06:02:27.038340 ==
3631 06:02:27.040776 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 06:02:27.043939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 06:02:27.044361 ==
3634 06:02:27.044691 DQS Delay:
3635 06:02:27.047337 DQS0 = 0, DQS1 = 0
3636 06:02:27.047756 DQM Delay:
3637 06:02:27.050596 DQM0 = 111, DQM1 = 109
3638 06:02:27.051011 DQ Delay:
3639 06:02:27.053866 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3640 06:02:27.057086 DQ4 =106, DQ5 =120, DQ6 =122, DQ7 =110
3641 06:02:27.060030 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =102
3642 06:02:27.067028 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3643 06:02:27.067524
3644 06:02:27.067875
3645 06:02:27.073739 [DQSOSCAuto] RK1, (LSB)MR18= 0xf808, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3646 06:02:27.076640 CH1 RK1: MR19=304, MR18=F808
3647 06:02:27.083795 CH1_RK1: MR19=0x304, MR18=0xF808, DQSOSC=406, MR23=63, INC=39, DEC=26
3648 06:02:27.087205 [RxdqsGatingPostProcess] freq 1200
3649 06:02:27.090284 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3650 06:02:27.093944 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 06:02:27.097096 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 06:02:27.100676 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 06:02:27.103139 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 06:02:27.106394 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 06:02:27.109550 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 06:02:27.113154 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 06:02:27.116571 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 06:02:27.120000 Pre-setting of DQS Precalculation
3659 06:02:27.122977 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3660 06:02:27.133169 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3661 06:02:27.140081 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3662 06:02:27.140593
3663 06:02:27.140925
3664 06:02:27.142844 [Calibration Summary] 2400 Mbps
3665 06:02:27.143259 CH 0, Rank 0
3666 06:02:27.146276 SW Impedance : PASS
3667 06:02:27.146753 DUTY Scan : NO K
3668 06:02:27.149983 ZQ Calibration : PASS
3669 06:02:27.152734 Jitter Meter : NO K
3670 06:02:27.153149 CBT Training : PASS
3671 06:02:27.155906 Write leveling : PASS
3672 06:02:27.159486 RX DQS gating : PASS
3673 06:02:27.159905 RX DQ/DQS(RDDQC) : PASS
3674 06:02:27.163115 TX DQ/DQS : PASS
3675 06:02:27.165871 RX DATLAT : PASS
3676 06:02:27.166288 RX DQ/DQS(Engine): PASS
3677 06:02:27.169219 TX OE : NO K
3678 06:02:27.169790 All Pass.
3679 06:02:27.170127
3680 06:02:27.172837 CH 0, Rank 1
3681 06:02:27.173336 SW Impedance : PASS
3682 06:02:27.176297 DUTY Scan : NO K
3683 06:02:27.178839 ZQ Calibration : PASS
3684 06:02:27.179254 Jitter Meter : NO K
3685 06:02:27.182154 CBT Training : PASS
3686 06:02:27.185445 Write leveling : PASS
3687 06:02:27.185998 RX DQS gating : PASS
3688 06:02:27.188760 RX DQ/DQS(RDDQC) : PASS
3689 06:02:27.192238 TX DQ/DQS : PASS
3690 06:02:27.192701 RX DATLAT : PASS
3691 06:02:27.195856 RX DQ/DQS(Engine): PASS
3692 06:02:27.198658 TX OE : NO K
3693 06:02:27.199076 All Pass.
3694 06:02:27.199403
3695 06:02:27.199706 CH 1, Rank 0
3696 06:02:27.201951 SW Impedance : PASS
3697 06:02:27.205200 DUTY Scan : NO K
3698 06:02:27.205645 ZQ Calibration : PASS
3699 06:02:27.209080 Jitter Meter : NO K
3700 06:02:27.209533 CBT Training : PASS
3701 06:02:27.212151 Write leveling : PASS
3702 06:02:27.215056 RX DQS gating : PASS
3703 06:02:27.215472 RX DQ/DQS(RDDQC) : PASS
3704 06:02:27.218888 TX DQ/DQS : PASS
3705 06:02:27.221968 RX DATLAT : PASS
3706 06:02:27.222382 RX DQ/DQS(Engine): PASS
3707 06:02:27.225122 TX OE : NO K
3708 06:02:27.225575 All Pass.
3709 06:02:27.225909
3710 06:02:27.228552 CH 1, Rank 1
3711 06:02:27.228977 SW Impedance : PASS
3712 06:02:27.232101 DUTY Scan : NO K
3713 06:02:27.234929 ZQ Calibration : PASS
3714 06:02:27.235341 Jitter Meter : NO K
3715 06:02:27.238512 CBT Training : PASS
3716 06:02:27.241976 Write leveling : PASS
3717 06:02:27.242473 RX DQS gating : PASS
3718 06:02:27.245408 RX DQ/DQS(RDDQC) : PASS
3719 06:02:27.248151 TX DQ/DQS : PASS
3720 06:02:27.248565 RX DATLAT : PASS
3721 06:02:27.251581 RX DQ/DQS(Engine): PASS
3722 06:02:27.255102 TX OE : NO K
3723 06:02:27.255519 All Pass.
3724 06:02:27.255845
3725 06:02:27.256153 DramC Write-DBI off
3726 06:02:27.257997 PER_BANK_REFRESH: Hybrid Mode
3727 06:02:27.261196 TX_TRACKING: ON
3728 06:02:27.267857 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3729 06:02:27.271207 [FAST_K] Save calibration result to emmc
3730 06:02:27.277913 dramc_set_vcore_voltage set vcore to 650000
3731 06:02:27.278064 Read voltage for 600, 5
3732 06:02:27.281389 Vio18 = 0
3733 06:02:27.281554 Vcore = 650000
3734 06:02:27.281675 Vdram = 0
3735 06:02:27.284289 Vddq = 0
3736 06:02:27.284416 Vmddr = 0
3737 06:02:27.287820 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3738 06:02:27.294568 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3739 06:02:27.297799 MEM_TYPE=3, freq_sel=19
3740 06:02:27.300922 sv_algorithm_assistance_LP4_1600
3741 06:02:27.304270 ============ PULL DRAM RESETB DOWN ============
3742 06:02:27.307284 ========== PULL DRAM RESETB DOWN end =========
3743 06:02:27.310722 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3744 06:02:27.317228 ===================================
3745 06:02:27.317332 LPDDR4 DRAM CONFIGURATION
3746 06:02:27.320706 ===================================
3747 06:02:27.323736 EX_ROW_EN[0] = 0x0
3748 06:02:27.323849 EX_ROW_EN[1] = 0x0
3749 06:02:27.327191 LP4Y_EN = 0x0
3750 06:02:27.327274 WORK_FSP = 0x0
3751 06:02:27.330709 WL = 0x2
3752 06:02:27.333690 RL = 0x2
3753 06:02:27.333797 BL = 0x2
3754 06:02:27.336899 RPST = 0x0
3755 06:02:27.337004 RD_PRE = 0x0
3756 06:02:27.340267 WR_PRE = 0x1
3757 06:02:27.340348 WR_PST = 0x0
3758 06:02:27.343307 DBI_WR = 0x0
3759 06:02:27.343421 DBI_RD = 0x0
3760 06:02:27.346936 OTF = 0x1
3761 06:02:27.350293 ===================================
3762 06:02:27.353808 ===================================
3763 06:02:27.353893 ANA top config
3764 06:02:27.356594 ===================================
3765 06:02:27.359931 DLL_ASYNC_EN = 0
3766 06:02:27.363368 ALL_SLAVE_EN = 1
3767 06:02:27.363481 NEW_RANK_MODE = 1
3768 06:02:27.366610 DLL_IDLE_MODE = 1
3769 06:02:27.370111 LP45_APHY_COMB_EN = 1
3770 06:02:27.373608 TX_ODT_DIS = 1
3771 06:02:27.376638 NEW_8X_MODE = 1
3772 06:02:27.379738 ===================================
3773 06:02:27.383301 ===================================
3774 06:02:27.383384 data_rate = 1200
3775 06:02:27.386725 CKR = 1
3776 06:02:27.390244 DQ_P2S_RATIO = 8
3777 06:02:27.393303 ===================================
3778 06:02:27.396828 CA_P2S_RATIO = 8
3779 06:02:27.400294 DQ_CA_OPEN = 0
3780 06:02:27.403582 DQ_SEMI_OPEN = 0
3781 06:02:27.403762 CA_SEMI_OPEN = 0
3782 06:02:27.406742 CA_FULL_RATE = 0
3783 06:02:27.409913 DQ_CKDIV4_EN = 1
3784 06:02:27.413498 CA_CKDIV4_EN = 1
3785 06:02:27.416766 CA_PREDIV_EN = 0
3786 06:02:27.420416 PH8_DLY = 0
3787 06:02:27.420666 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3788 06:02:27.423509 DQ_AAMCK_DIV = 4
3789 06:02:27.426291 CA_AAMCK_DIV = 4
3790 06:02:27.429851 CA_ADMCK_DIV = 4
3791 06:02:27.433152 DQ_TRACK_CA_EN = 0
3792 06:02:27.436769 CA_PICK = 600
3793 06:02:27.440016 CA_MCKIO = 600
3794 06:02:27.440314 MCKIO_SEMI = 0
3795 06:02:27.443267 PLL_FREQ = 2288
3796 06:02:27.446615 DQ_UI_PI_RATIO = 32
3797 06:02:27.450000 CA_UI_PI_RATIO = 0
3798 06:02:27.452822 ===================================
3799 06:02:27.456542 ===================================
3800 06:02:27.459449 memory_type:LPDDR4
3801 06:02:27.459867 GP_NUM : 10
3802 06:02:27.462621 SRAM_EN : 1
3803 06:02:27.466141 MD32_EN : 0
3804 06:02:27.469304 ===================================
3805 06:02:27.469767 [ANA_INIT] >>>>>>>>>>>>>>
3806 06:02:27.472716 <<<<<< [CONFIGURE PHASE]: ANA_TX
3807 06:02:27.476367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3808 06:02:27.479601 ===================================
3809 06:02:27.482870 data_rate = 1200,PCW = 0X5800
3810 06:02:27.486433 ===================================
3811 06:02:27.489051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3812 06:02:27.496040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 06:02:27.498890 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 06:02:27.506002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3815 06:02:27.509440 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3816 06:02:27.512418 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3817 06:02:27.515850 [ANA_INIT] flow start
3818 06:02:27.516359 [ANA_INIT] PLL >>>>>>>>
3819 06:02:27.519663 [ANA_INIT] PLL <<<<<<<<
3820 06:02:27.522582 [ANA_INIT] MIDPI >>>>>>>>
3821 06:02:27.523002 [ANA_INIT] MIDPI <<<<<<<<
3822 06:02:27.526056 [ANA_INIT] DLL >>>>>>>>
3823 06:02:27.528820 [ANA_INIT] flow end
3824 06:02:27.532473 ============ LP4 DIFF to SE enter ============
3825 06:02:27.535813 ============ LP4 DIFF to SE exit ============
3826 06:02:27.539169 [ANA_INIT] <<<<<<<<<<<<<
3827 06:02:27.542322 [Flow] Enable top DCM control >>>>>
3828 06:02:27.545880 [Flow] Enable top DCM control <<<<<
3829 06:02:27.549241 Enable DLL master slave shuffle
3830 06:02:27.552648 ==============================================================
3831 06:02:27.555661 Gating Mode config
3832 06:02:27.562342 ==============================================================
3833 06:02:27.562758 Config description:
3834 06:02:27.572079 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3835 06:02:27.578808 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3836 06:02:27.581924 SELPH_MODE 0: By rank 1: By Phase
3837 06:02:27.588811 ==============================================================
3838 06:02:27.591765 GAT_TRACK_EN = 1
3839 06:02:27.595129 RX_GATING_MODE = 2
3840 06:02:27.598957 RX_GATING_TRACK_MODE = 2
3841 06:02:27.602099 SELPH_MODE = 1
3842 06:02:27.605648 PICG_EARLY_EN = 1
3843 06:02:27.609150 VALID_LAT_VALUE = 1
3844 06:02:27.611765 ==============================================================
3845 06:02:27.615547 Enter into Gating configuration >>>>
3846 06:02:27.618172 Exit from Gating configuration <<<<
3847 06:02:27.621687 Enter into DVFS_PRE_config >>>>>
3848 06:02:27.635188 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3849 06:02:27.638020 Exit from DVFS_PRE_config <<<<<
3850 06:02:27.641161 Enter into PICG configuration >>>>
3851 06:02:27.641891 Exit from PICG configuration <<<<
3852 06:02:27.644797 [RX_INPUT] configuration >>>>>
3853 06:02:27.648069 [RX_INPUT] configuration <<<<<
3854 06:02:27.654796 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3855 06:02:27.658165 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3856 06:02:27.664410 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 06:02:27.671257 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 06:02:27.677747 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 06:02:27.684639 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 06:02:27.687989 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3861 06:02:27.691407 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3862 06:02:27.694337 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3863 06:02:27.701021 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3864 06:02:27.704610 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3865 06:02:27.707645 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 06:02:27.710726 ===================================
3867 06:02:27.714144 LPDDR4 DRAM CONFIGURATION
3868 06:02:27.717800 ===================================
3869 06:02:27.721391 EX_ROW_EN[0] = 0x0
3870 06:02:27.721942 EX_ROW_EN[1] = 0x0
3871 06:02:27.724665 LP4Y_EN = 0x0
3872 06:02:27.725174 WORK_FSP = 0x0
3873 06:02:27.727349 WL = 0x2
3874 06:02:27.727754 RL = 0x2
3875 06:02:27.730821 BL = 0x2
3876 06:02:27.731233 RPST = 0x0
3877 06:02:27.734209 RD_PRE = 0x0
3878 06:02:27.734619 WR_PRE = 0x1
3879 06:02:27.737359 WR_PST = 0x0
3880 06:02:27.737916 DBI_WR = 0x0
3881 06:02:27.740612 DBI_RD = 0x0
3882 06:02:27.741032 OTF = 0x1
3883 06:02:27.744103 ===================================
3884 06:02:27.750967 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3885 06:02:27.754180 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3886 06:02:27.757522 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 06:02:27.760681 ===================================
3888 06:02:27.763642 LPDDR4 DRAM CONFIGURATION
3889 06:02:27.767249 ===================================
3890 06:02:27.770973 EX_ROW_EN[0] = 0x10
3891 06:02:27.771483 EX_ROW_EN[1] = 0x0
3892 06:02:27.773575 LP4Y_EN = 0x0
3893 06:02:27.774024 WORK_FSP = 0x0
3894 06:02:27.776782 WL = 0x2
3895 06:02:27.777195 RL = 0x2
3896 06:02:27.780674 BL = 0x2
3897 06:02:27.781187 RPST = 0x0
3898 06:02:27.783541 RD_PRE = 0x0
3899 06:02:27.783954 WR_PRE = 0x1
3900 06:02:27.787357 WR_PST = 0x0
3901 06:02:27.787869 DBI_WR = 0x0
3902 06:02:27.790383 DBI_RD = 0x0
3903 06:02:27.790795 OTF = 0x1
3904 06:02:27.793693 ===================================
3905 06:02:27.800308 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3906 06:02:27.805246 nWR fixed to 30
3907 06:02:27.808769 [ModeRegInit_LP4] CH0 RK0
3908 06:02:27.809287 [ModeRegInit_LP4] CH0 RK1
3909 06:02:27.812101 [ModeRegInit_LP4] CH1 RK0
3910 06:02:27.815636 [ModeRegInit_LP4] CH1 RK1
3911 06:02:27.816140 match AC timing 17
3912 06:02:27.821592 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3913 06:02:27.825385 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3914 06:02:27.828193 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3915 06:02:27.835062 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3916 06:02:27.838612 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3917 06:02:27.839027 ==
3918 06:02:27.841789 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 06:02:27.844956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3920 06:02:27.845369 ==
3921 06:02:27.851800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3922 06:02:27.858441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3923 06:02:27.861766 [CA 0] Center 37 (7~67) winsize 61
3924 06:02:27.864560 [CA 1] Center 37 (7~67) winsize 61
3925 06:02:27.868310 [CA 2] Center 35 (5~65) winsize 61
3926 06:02:27.871935 [CA 3] Center 35 (5~65) winsize 61
3927 06:02:27.874801 [CA 4] Center 34 (4~65) winsize 62
3928 06:02:27.878142 [CA 5] Center 34 (4~64) winsize 61
3929 06:02:27.878794
3930 06:02:27.881650 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3931 06:02:27.882157
3932 06:02:27.884646 [CATrainingPosCal] consider 1 rank data
3933 06:02:27.887886 u2DelayCellTimex100 = 270/100 ps
3934 06:02:27.891350 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3935 06:02:27.894548 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3936 06:02:27.897928 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3937 06:02:27.901322 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3938 06:02:27.904588 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3939 06:02:27.910988 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3940 06:02:27.911495
3941 06:02:27.914300 CA PerBit enable=1, Macro0, CA PI delay=34
3942 06:02:27.914714
3943 06:02:27.917733 [CBTSetCACLKResult] CA Dly = 34
3944 06:02:27.918145 CS Dly: 5 (0~36)
3945 06:02:27.918474 ==
3946 06:02:27.921573 Dram Type= 6, Freq= 0, CH_0, rank 1
3947 06:02:27.924530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 06:02:27.927750 ==
3949 06:02:27.931009 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 06:02:27.937631 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3951 06:02:27.941346 [CA 0] Center 37 (7~67) winsize 61
3952 06:02:27.944455 [CA 1] Center 36 (6~67) winsize 62
3953 06:02:27.947878 [CA 2] Center 35 (5~65) winsize 61
3954 06:02:27.950766 [CA 3] Center 35 (5~65) winsize 61
3955 06:02:27.954151 [CA 4] Center 34 (4~65) winsize 62
3956 06:02:27.957541 [CA 5] Center 34 (3~65) winsize 63
3957 06:02:27.958043
3958 06:02:27.961291 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3959 06:02:27.961857
3960 06:02:27.963955 [CATrainingPosCal] consider 2 rank data
3961 06:02:27.967727 u2DelayCellTimex100 = 270/100 ps
3962 06:02:27.970276 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3963 06:02:27.974301 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3964 06:02:27.980482 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3965 06:02:27.984054 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3966 06:02:27.987797 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3967 06:02:27.990436 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3968 06:02:27.990852
3969 06:02:27.993639 CA PerBit enable=1, Macro0, CA PI delay=34
3970 06:02:27.994141
3971 06:02:27.996902 [CBTSetCACLKResult] CA Dly = 34
3972 06:02:27.997417 CS Dly: 6 (0~38)
3973 06:02:27.997813
3974 06:02:28.000633 ----->DramcWriteLeveling(PI) begin...
3975 06:02:28.003734 ==
3976 06:02:28.006659 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 06:02:28.010092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 06:02:28.010505 ==
3979 06:02:28.013699 Write leveling (Byte 0): 35 => 35
3980 06:02:28.017231 Write leveling (Byte 1): 30 => 30
3981 06:02:28.020085 DramcWriteLeveling(PI) end<-----
3982 06:02:28.020495
3983 06:02:28.020819 ==
3984 06:02:28.023908 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 06:02:28.027436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 06:02:28.027949 ==
3987 06:02:28.030202 [Gating] SW mode calibration
3988 06:02:28.036786 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3989 06:02:28.043294 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3990 06:02:28.046475 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 06:02:28.049793 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 06:02:28.056403 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 06:02:28.059702 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3994 06:02:28.062886 0 9 16 | B1->B0 | 2f2f 2d2d | 1 1 | (1 1) (0 0)
3995 06:02:28.070012 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 06:02:28.073226 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 06:02:28.076748 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 06:02:28.083089 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 06:02:28.086581 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 06:02:28.089435 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 06:02:28.096339 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4002 06:02:28.099519 0 10 16 | B1->B0 | 3131 3c3c | 0 0 | (0 0) (0 0)
4003 06:02:28.102906 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 06:02:28.109845 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 06:02:28.112704 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 06:02:28.116213 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 06:02:28.123031 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 06:02:28.126171 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 06:02:28.129292 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 06:02:28.132781 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4011 06:02:28.139343 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 06:02:28.142865 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 06:02:28.146066 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 06:02:28.152841 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 06:02:28.155478 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 06:02:28.158935 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 06:02:28.165630 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 06:02:28.168879 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 06:02:28.172106 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 06:02:28.178652 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 06:02:28.182156 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 06:02:28.185414 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 06:02:28.192088 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 06:02:28.195548 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 06:02:28.198484 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 06:02:28.205321 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4027 06:02:28.208205 Total UI for P1: 0, mck2ui 16
4028 06:02:28.211655 best dqsien dly found for B0: ( 0, 13, 14)
4029 06:02:28.215129 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 06:02:28.218480 Total UI for P1: 0, mck2ui 16
4031 06:02:28.221329 best dqsien dly found for B1: ( 0, 13, 18)
4032 06:02:28.225102 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4033 06:02:28.228263 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4034 06:02:28.228778
4035 06:02:28.231565 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4036 06:02:28.238455 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4037 06:02:28.238992 [Gating] SW calibration Done
4038 06:02:28.241865 ==
4039 06:02:28.242411 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 06:02:28.248240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 06:02:28.248789 ==
4042 06:02:28.249244 RX Vref Scan: 0
4043 06:02:28.249746
4044 06:02:28.251182 RX Vref 0 -> 0, step: 1
4045 06:02:28.251611
4046 06:02:28.254558 RX Delay -230 -> 252, step: 16
4047 06:02:28.257923 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4048 06:02:28.261452 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4049 06:02:28.267611 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4050 06:02:28.271410 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4051 06:02:28.274093 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4052 06:02:28.277822 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4053 06:02:28.284541 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4054 06:02:28.287995 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4055 06:02:28.291153 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4056 06:02:28.294335 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4057 06:02:28.297231 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4058 06:02:28.303704 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4059 06:02:28.307375 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4060 06:02:28.310291 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4061 06:02:28.314348 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4062 06:02:28.320678 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4063 06:02:28.321196 ==
4064 06:02:28.324206 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 06:02:28.327351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 06:02:28.327888 ==
4067 06:02:28.328337 DQS Delay:
4068 06:02:28.330834 DQS0 = 0, DQS1 = 0
4069 06:02:28.331369 DQM Delay:
4070 06:02:28.334109 DQM0 = 37, DQM1 = 29
4071 06:02:28.334539 DQ Delay:
4072 06:02:28.337166 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4073 06:02:28.340568 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4074 06:02:28.343793 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4075 06:02:28.347560 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4076 06:02:28.348094
4077 06:02:28.348545
4078 06:02:28.348964 ==
4079 06:02:28.350034 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 06:02:28.353544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 06:02:28.356878 ==
4082 06:02:28.357311
4083 06:02:28.357821
4084 06:02:28.358240 TX Vref Scan disable
4085 06:02:28.360346 == TX Byte 0 ==
4086 06:02:28.363877 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4087 06:02:28.370181 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4088 06:02:28.370619 == TX Byte 1 ==
4089 06:02:28.373659 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4090 06:02:28.380299 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4091 06:02:28.380836 ==
4092 06:02:28.383839 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 06:02:28.386322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 06:02:28.386755 ==
4095 06:02:28.387196
4096 06:02:28.387611
4097 06:02:28.389718 TX Vref Scan disable
4098 06:02:28.393595 == TX Byte 0 ==
4099 06:02:28.396290 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4100 06:02:28.399703 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4101 06:02:28.403449 == TX Byte 1 ==
4102 06:02:28.406406 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4103 06:02:28.409304 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4104 06:02:28.409777
4105 06:02:28.413358 [DATLAT]
4106 06:02:28.413965 Freq=600, CH0 RK0
4107 06:02:28.414418
4108 06:02:28.416379 DATLAT Default: 0x9
4109 06:02:28.416810 0, 0xFFFF, sum = 0
4110 06:02:28.419245 1, 0xFFFF, sum = 0
4111 06:02:28.419684 2, 0xFFFF, sum = 0
4112 06:02:28.423239 3, 0xFFFF, sum = 0
4113 06:02:28.423767 4, 0xFFFF, sum = 0
4114 06:02:28.426411 5, 0xFFFF, sum = 0
4115 06:02:28.426851 6, 0xFFFF, sum = 0
4116 06:02:28.429641 7, 0xFFFF, sum = 0
4117 06:02:28.430175 8, 0x0, sum = 1
4118 06:02:28.432830 9, 0x0, sum = 2
4119 06:02:28.433267 10, 0x0, sum = 3
4120 06:02:28.436684 11, 0x0, sum = 4
4121 06:02:28.437226 best_step = 9
4122 06:02:28.437742
4123 06:02:28.438256 ==
4124 06:02:28.439289 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 06:02:28.442694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 06:02:28.443106 ==
4127 06:02:28.445949 RX Vref Scan: 1
4128 06:02:28.446361
4129 06:02:28.449265 RX Vref 0 -> 0, step: 1
4130 06:02:28.449753
4131 06:02:28.450091 RX Delay -195 -> 252, step: 8
4132 06:02:28.452470
4133 06:02:28.452882 Set Vref, RX VrefLevel [Byte0]: 59
4134 06:02:28.456093 [Byte1]: 54
4135 06:02:28.460500
4136 06:02:28.460916 Final RX Vref Byte 0 = 59 to rank0
4137 06:02:28.464093 Final RX Vref Byte 1 = 54 to rank0
4138 06:02:28.467461 Final RX Vref Byte 0 = 59 to rank1
4139 06:02:28.471203 Final RX Vref Byte 1 = 54 to rank1==
4140 06:02:28.473930 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 06:02:28.480953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 06:02:28.481550 ==
4143 06:02:28.482188 DQS Delay:
4144 06:02:28.484436 DQS0 = 0, DQS1 = 0
4145 06:02:28.484952 DQM Delay:
4146 06:02:28.485286 DQM0 = 35, DQM1 = 29
4147 06:02:28.487212 DQ Delay:
4148 06:02:28.490382 DQ0 =36, DQ1 =40, DQ2 =32, DQ3 =32
4149 06:02:28.493994 DQ4 =36, DQ5 =20, DQ6 =40, DQ7 =48
4150 06:02:28.497337 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4151 06:02:28.500338 DQ12 =32, DQ13 =36, DQ14 =44, DQ15 =36
4152 06:02:28.500751
4153 06:02:28.501076
4154 06:02:28.507278 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a39, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4155 06:02:28.510769 CH0 RK0: MR19=808, MR18=3A39
4156 06:02:28.517430 CH0_RK0: MR19=0x808, MR18=0x3A39, DQSOSC=398, MR23=63, INC=165, DEC=110
4157 06:02:28.518005
4158 06:02:28.520514 ----->DramcWriteLeveling(PI) begin...
4159 06:02:28.520932 ==
4160 06:02:28.523933 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 06:02:28.527567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 06:02:28.528083 ==
4163 06:02:28.530286 Write leveling (Byte 0): 33 => 33
4164 06:02:28.533899 Write leveling (Byte 1): 29 => 29
4165 06:02:28.536974 DramcWriteLeveling(PI) end<-----
4166 06:02:28.537536
4167 06:02:28.537886 ==
4168 06:02:28.540500 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 06:02:28.543690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 06:02:28.544111 ==
4171 06:02:28.547507 [Gating] SW mode calibration
4172 06:02:28.553730 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4173 06:02:28.560062 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4174 06:02:28.563536 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 06:02:28.570143 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 06:02:28.573802 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 06:02:28.577160 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4178 06:02:28.583596 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4179 06:02:28.587085 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 06:02:28.590777 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 06:02:28.596797 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 06:02:28.600334 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 06:02:28.603412 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 06:02:28.610297 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 06:02:28.613424 0 10 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4186 06:02:28.616281 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4187 06:02:28.619887 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 06:02:28.626745 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 06:02:28.629933 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 06:02:28.633018 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 06:02:28.639956 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 06:02:28.642972 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 06:02:28.646368 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4194 06:02:28.653212 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4195 06:02:28.656020 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 06:02:28.659513 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 06:02:28.666335 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 06:02:28.669309 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 06:02:28.672645 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 06:02:28.679717 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 06:02:28.683024 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 06:02:28.686036 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 06:02:28.693333 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 06:02:28.695837 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 06:02:28.699266 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 06:02:28.705663 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 06:02:28.708926 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 06:02:28.712981 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 06:02:28.718952 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4210 06:02:28.722394 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 06:02:28.725582 Total UI for P1: 0, mck2ui 16
4212 06:02:28.729124 best dqsien dly found for B0: ( 0, 13, 12)
4213 06:02:28.732764 Total UI for P1: 0, mck2ui 16
4214 06:02:28.735930 best dqsien dly found for B1: ( 0, 13, 14)
4215 06:02:28.738801 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4216 06:02:28.742613 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4217 06:02:28.743130
4218 06:02:28.745923 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4219 06:02:28.748926 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4220 06:02:28.752427 [Gating] SW calibration Done
4221 06:02:28.752937 ==
4222 06:02:28.755890 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 06:02:28.761836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 06:02:28.762276 ==
4225 06:02:28.762609 RX Vref Scan: 0
4226 06:02:28.762933
4227 06:02:28.765088 RX Vref 0 -> 0, step: 1
4228 06:02:28.765533
4229 06:02:28.768575 RX Delay -230 -> 252, step: 16
4230 06:02:28.772318 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4231 06:02:28.775340 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4232 06:02:28.778638 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4233 06:02:28.785027 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4234 06:02:28.788735 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4235 06:02:28.792068 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4236 06:02:28.795225 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4237 06:02:28.801452 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4238 06:02:28.805539 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4239 06:02:28.808279 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4240 06:02:28.811844 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4241 06:02:28.817872 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4242 06:02:28.821729 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4243 06:02:28.824674 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4244 06:02:28.828473 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4245 06:02:28.834398 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4246 06:02:28.834838 ==
4247 06:02:28.838032 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 06:02:28.841105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 06:02:28.841580 ==
4250 06:02:28.841920 DQS Delay:
4251 06:02:28.844743 DQS0 = 0, DQS1 = 0
4252 06:02:28.845159 DQM Delay:
4253 06:02:28.847985 DQM0 = 39, DQM1 = 28
4254 06:02:28.848666 DQ Delay:
4255 06:02:28.851303 DQ0 =41, DQ1 =33, DQ2 =41, DQ3 =33
4256 06:02:28.854560 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4257 06:02:28.857918 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =17
4258 06:02:28.860919 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4259 06:02:28.861334
4260 06:02:28.861799
4261 06:02:28.862253 ==
4262 06:02:28.864293 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 06:02:28.867818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 06:02:28.868272 ==
4265 06:02:28.870824
4266 06:02:28.871242
4267 06:02:28.871571 TX Vref Scan disable
4268 06:02:28.874152 == TX Byte 0 ==
4269 06:02:28.877811 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4270 06:02:28.880522 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4271 06:02:28.884035 == TX Byte 1 ==
4272 06:02:28.887145 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4273 06:02:28.890446 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4274 06:02:28.893730 ==
4275 06:02:28.897075 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 06:02:28.900590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 06:02:28.901008 ==
4278 06:02:28.901337
4279 06:02:28.901705
4280 06:02:28.903937 TX Vref Scan disable
4281 06:02:28.906802 == TX Byte 0 ==
4282 06:02:28.910131 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4283 06:02:28.913956 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4284 06:02:28.916957 == TX Byte 1 ==
4285 06:02:28.920414 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4286 06:02:28.923565 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4287 06:02:28.923987
4288 06:02:28.924322 [DATLAT]
4289 06:02:28.926612 Freq=600, CH0 RK1
4290 06:02:28.927046
4291 06:02:28.927402 DATLAT Default: 0x9
4292 06:02:28.930101 0, 0xFFFF, sum = 0
4293 06:02:28.933665 1, 0xFFFF, sum = 0
4294 06:02:28.934121 2, 0xFFFF, sum = 0
4295 06:02:28.936609 3, 0xFFFF, sum = 0
4296 06:02:28.937232 4, 0xFFFF, sum = 0
4297 06:02:28.940226 5, 0xFFFF, sum = 0
4298 06:02:28.940739 6, 0xFFFF, sum = 0
4299 06:02:28.943691 7, 0xFFFF, sum = 0
4300 06:02:28.944107 8, 0x0, sum = 1
4301 06:02:28.946661 9, 0x0, sum = 2
4302 06:02:28.947083 10, 0x0, sum = 3
4303 06:02:28.947419 11, 0x0, sum = 4
4304 06:02:28.950177 best_step = 9
4305 06:02:28.950592
4306 06:02:28.950917 ==
4307 06:02:28.953600 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 06:02:28.956371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 06:02:28.956669 ==
4310 06:02:28.960031 RX Vref Scan: 0
4311 06:02:28.960324
4312 06:02:28.960567 RX Vref 0 -> 0, step: 1
4313 06:02:28.962892
4314 06:02:28.963186 RX Delay -195 -> 252, step: 8
4315 06:02:28.971242 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4316 06:02:28.974121 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4317 06:02:28.977425 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4318 06:02:28.980922 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4319 06:02:28.987730 iDelay=205, Bit 4, Center 28 (-131 ~ 188) 320
4320 06:02:28.990533 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4321 06:02:28.993762 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4322 06:02:28.997087 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4323 06:02:29.003992 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4324 06:02:29.007410 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4325 06:02:29.010922 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4326 06:02:29.013972 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4327 06:02:29.017523 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4328 06:02:29.023907 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4329 06:02:29.027409 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4330 06:02:29.030768 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4331 06:02:29.031147 ==
4332 06:02:29.033763 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 06:02:29.040506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 06:02:29.040891 ==
4335 06:02:29.041193 DQS Delay:
4336 06:02:29.041505 DQS0 = 0, DQS1 = 0
4337 06:02:29.043388 DQM Delay:
4338 06:02:29.043765 DQM0 = 33, DQM1 = 28
4339 06:02:29.046925 DQ Delay:
4340 06:02:29.050005 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4341 06:02:29.053803 DQ4 =28, DQ5 =20, DQ6 =44, DQ7 =44
4342 06:02:29.056784 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4343 06:02:29.060697 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4344 06:02:29.061218
4345 06:02:29.061726
4346 06:02:29.066628 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4347 06:02:29.070111 CH0 RK1: MR19=808, MR18=6D3C
4348 06:02:29.076942 CH0_RK1: MR19=0x808, MR18=0x6D3C, DQSOSC=389, MR23=63, INC=173, DEC=115
4349 06:02:29.079884 [RxdqsGatingPostProcess] freq 600
4350 06:02:29.083181 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4351 06:02:29.086648 Pre-setting of DQS Precalculation
4352 06:02:29.093746 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4353 06:02:29.094141 ==
4354 06:02:29.096644 Dram Type= 6, Freq= 0, CH_1, rank 0
4355 06:02:29.100036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 06:02:29.100262 ==
4357 06:02:29.106273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4358 06:02:29.113024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4359 06:02:29.116278 [CA 0] Center 35 (5~66) winsize 62
4360 06:02:29.119257 [CA 1] Center 36 (6~66) winsize 61
4361 06:02:29.122949 [CA 2] Center 34 (4~65) winsize 62
4362 06:02:29.125920 [CA 3] Center 34 (4~65) winsize 62
4363 06:02:29.129510 [CA 4] Center 34 (4~65) winsize 62
4364 06:02:29.132722 [CA 5] Center 33 (3~64) winsize 62
4365 06:02:29.132872
4366 06:02:29.136346 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4367 06:02:29.136496
4368 06:02:29.139484 [CATrainingPosCal] consider 1 rank data
4369 06:02:29.143058 u2DelayCellTimex100 = 270/100 ps
4370 06:02:29.145948 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4371 06:02:29.149411 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4372 06:02:29.152791 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4373 06:02:29.156440 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4374 06:02:29.159887 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4375 06:02:29.162932 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4376 06:02:29.163314
4377 06:02:29.169782 CA PerBit enable=1, Macro0, CA PI delay=33
4378 06:02:29.170364
4379 06:02:29.170937 [CBTSetCACLKResult] CA Dly = 33
4380 06:02:29.172823 CS Dly: 4 (0~35)
4381 06:02:29.173331 ==
4382 06:02:29.175876 Dram Type= 6, Freq= 0, CH_1, rank 1
4383 06:02:29.179122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 06:02:29.179541 ==
4385 06:02:29.185589 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4386 06:02:29.192866 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4387 06:02:29.196316 [CA 0] Center 36 (6~66) winsize 61
4388 06:02:29.199245 [CA 1] Center 36 (6~66) winsize 61
4389 06:02:29.202846 [CA 2] Center 34 (4~65) winsize 62
4390 06:02:29.206094 [CA 3] Center 34 (3~65) winsize 63
4391 06:02:29.209342 [CA 4] Center 34 (4~65) winsize 62
4392 06:02:29.212282 [CA 5] Center 33 (3~64) winsize 62
4393 06:02:29.212694
4394 06:02:29.215862 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4395 06:02:29.216435
4396 06:02:29.218821 [CATrainingPosCal] consider 2 rank data
4397 06:02:29.222180 u2DelayCellTimex100 = 270/100 ps
4398 06:02:29.225586 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4399 06:02:29.228989 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4400 06:02:29.232224 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4401 06:02:29.235399 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 06:02:29.238981 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 06:02:29.245533 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4404 06:02:29.246108
4405 06:02:29.249004 CA PerBit enable=1, Macro0, CA PI delay=33
4406 06:02:29.249418
4407 06:02:29.251972 [CBTSetCACLKResult] CA Dly = 33
4408 06:02:29.252389 CS Dly: 4 (0~36)
4409 06:02:29.252714
4410 06:02:29.255303 ----->DramcWriteLeveling(PI) begin...
4411 06:02:29.255722 ==
4412 06:02:29.258943 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 06:02:29.265146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 06:02:29.265614 ==
4415 06:02:29.268437 Write leveling (Byte 0): 31 => 31
4416 06:02:29.268853 Write leveling (Byte 1): 31 => 31
4417 06:02:29.271683 DramcWriteLeveling(PI) end<-----
4418 06:02:29.272125
4419 06:02:29.272462 ==
4420 06:02:29.275492 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 06:02:29.281611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 06:02:29.282084 ==
4423 06:02:29.285000 [Gating] SW mode calibration
4424 06:02:29.292224 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4425 06:02:29.295133 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4426 06:02:29.301264 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 06:02:29.305003 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 06:02:29.308612 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4429 06:02:29.315144 0 9 12 | B1->B0 | 3333 3131 | 1 1 | (1 0) (1 0)
4430 06:02:29.318593 0 9 16 | B1->B0 | 2424 2c2c | 0 0 | (1 0) (1 0)
4431 06:02:29.321387 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 06:02:29.328135 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 06:02:29.331701 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 06:02:29.334799 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 06:02:29.341119 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 06:02:29.344392 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 06:02:29.347695 0 10 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
4438 06:02:29.354219 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4439 06:02:29.357479 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 06:02:29.361078 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 06:02:29.367492 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 06:02:29.370753 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 06:02:29.373863 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 06:02:29.380680 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 06:02:29.383778 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4446 06:02:29.387759 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 06:02:29.393612 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 06:02:29.397344 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 06:02:29.400811 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 06:02:29.407292 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 06:02:29.410242 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 06:02:29.413800 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 06:02:29.420038 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 06:02:29.423505 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 06:02:29.426949 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 06:02:29.433198 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 06:02:29.436892 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 06:02:29.440101 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 06:02:29.446911 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 06:02:29.449829 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 06:02:29.453251 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4462 06:02:29.456523 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 06:02:29.459744 Total UI for P1: 0, mck2ui 16
4464 06:02:29.463302 best dqsien dly found for B0: ( 0, 13, 12)
4465 06:02:29.466269 Total UI for P1: 0, mck2ui 16
4466 06:02:29.469660 best dqsien dly found for B1: ( 0, 13, 12)
4467 06:02:29.476405 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4468 06:02:29.479739 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4469 06:02:29.479852
4470 06:02:29.483216 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4471 06:02:29.486028 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4472 06:02:29.489428 [Gating] SW calibration Done
4473 06:02:29.489547 ==
4474 06:02:29.492584 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 06:02:29.496076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 06:02:29.496159 ==
4477 06:02:29.499948 RX Vref Scan: 0
4478 06:02:29.500029
4479 06:02:29.500094 RX Vref 0 -> 0, step: 1
4480 06:02:29.500155
4481 06:02:29.503267 RX Delay -230 -> 252, step: 16
4482 06:02:29.506274 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4483 06:02:29.512582 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4484 06:02:29.516187 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4485 06:02:29.519689 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4486 06:02:29.523095 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4487 06:02:29.529468 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4488 06:02:29.532929 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4489 06:02:29.535688 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4490 06:02:29.539743 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4491 06:02:29.542574 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4492 06:02:29.549544 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4493 06:02:29.552641 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4494 06:02:29.556309 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4495 06:02:29.559742 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4496 06:02:29.566008 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4497 06:02:29.569525 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4498 06:02:29.569951 ==
4499 06:02:29.572956 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 06:02:29.575981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 06:02:29.576405 ==
4502 06:02:29.579129 DQS Delay:
4503 06:02:29.579693 DQS0 = 0, DQS1 = 0
4504 06:02:29.582487 DQM Delay:
4505 06:02:29.583079 DQM0 = 39, DQM1 = 31
4506 06:02:29.583554 DQ Delay:
4507 06:02:29.585755 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4508 06:02:29.589312 DQ4 =33, DQ5 =49, DQ6 =57, DQ7 =33
4509 06:02:29.592179 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4510 06:02:29.596179 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4511 06:02:29.596728
4512 06:02:29.597202
4513 06:02:29.598810 ==
4514 06:02:29.602433 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 06:02:29.605840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 06:02:29.606356 ==
4517 06:02:29.606691
4518 06:02:29.606997
4519 06:02:29.609242 TX Vref Scan disable
4520 06:02:29.609733 == TX Byte 0 ==
4521 06:02:29.615478 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4522 06:02:29.619324 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4523 06:02:29.619835 == TX Byte 1 ==
4524 06:02:29.625812 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4525 06:02:29.628714 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4526 06:02:29.629229 ==
4527 06:02:29.632166 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 06:02:29.635396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 06:02:29.635851 ==
4530 06:02:29.636192
4531 06:02:29.636497
4532 06:02:29.638700 TX Vref Scan disable
4533 06:02:29.641970 == TX Byte 0 ==
4534 06:02:29.645418 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4535 06:02:29.648913 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4536 06:02:29.652536 == TX Byte 1 ==
4537 06:02:29.655599 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4538 06:02:29.658627 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4539 06:02:29.659151
4540 06:02:29.661787 [DATLAT]
4541 06:02:29.662206 Freq=600, CH1 RK0
4542 06:02:29.662543
4543 06:02:29.665464 DATLAT Default: 0x9
4544 06:02:29.665925 0, 0xFFFF, sum = 0
4545 06:02:29.668328 1, 0xFFFF, sum = 0
4546 06:02:29.668766 2, 0xFFFF, sum = 0
4547 06:02:29.671663 3, 0xFFFF, sum = 0
4548 06:02:29.672090 4, 0xFFFF, sum = 0
4549 06:02:29.675205 5, 0xFFFF, sum = 0
4550 06:02:29.675627 6, 0xFFFF, sum = 0
4551 06:02:29.678500 7, 0xFFFF, sum = 0
4552 06:02:29.678991 8, 0x0, sum = 1
4553 06:02:29.681410 9, 0x0, sum = 2
4554 06:02:29.681863 10, 0x0, sum = 3
4555 06:02:29.685180 11, 0x0, sum = 4
4556 06:02:29.685767 best_step = 9
4557 06:02:29.686109
4558 06:02:29.686416 ==
4559 06:02:29.688241 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 06:02:29.695057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 06:02:29.695574 ==
4562 06:02:29.695908 RX Vref Scan: 1
4563 06:02:29.696218
4564 06:02:29.697983 RX Vref 0 -> 0, step: 1
4565 06:02:29.698410
4566 06:02:29.701287 RX Delay -179 -> 252, step: 8
4567 06:02:29.701755
4568 06:02:29.704556 Set Vref, RX VrefLevel [Byte0]: 58
4569 06:02:29.707848 [Byte1]: 50
4570 06:02:29.707930
4571 06:02:29.711167 Final RX Vref Byte 0 = 58 to rank0
4572 06:02:29.714143 Final RX Vref Byte 1 = 50 to rank0
4573 06:02:29.717410 Final RX Vref Byte 0 = 58 to rank1
4574 06:02:29.720969 Final RX Vref Byte 1 = 50 to rank1==
4575 06:02:29.723920 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 06:02:29.727739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 06:02:29.727917 ==
4578 06:02:29.731072 DQS Delay:
4579 06:02:29.731183 DQS0 = 0, DQS1 = 0
4580 06:02:29.733946 DQM Delay:
4581 06:02:29.734046 DQM0 = 38, DQM1 = 28
4582 06:02:29.734127 DQ Delay:
4583 06:02:29.737461 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4584 06:02:29.741241 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4585 06:02:29.743975 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4586 06:02:29.747322 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4587 06:02:29.747516
4588 06:02:29.747654
4589 06:02:29.757557 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f2c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
4590 06:02:29.761018 CH1 RK0: MR19=808, MR18=1F2C
4591 06:02:29.763903 CH1_RK0: MR19=0x808, MR18=0x1F2C, DQSOSC=401, MR23=63, INC=163, DEC=108
4592 06:02:29.767348
4593 06:02:29.771071 ----->DramcWriteLeveling(PI) begin...
4594 06:02:29.771398 ==
4595 06:02:29.774521 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 06:02:29.777108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 06:02:29.777442 ==
4598 06:02:29.781291 Write leveling (Byte 0): 29 => 29
4599 06:02:29.784125 Write leveling (Byte 1): 28 => 28
4600 06:02:29.787599 DramcWriteLeveling(PI) end<-----
4601 06:02:29.788143
4602 06:02:29.788611 ==
4603 06:02:29.790666 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 06:02:29.794159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 06:02:29.794580 ==
4606 06:02:29.797374 [Gating] SW mode calibration
4607 06:02:29.804405 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4608 06:02:29.810506 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4609 06:02:29.813854 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 06:02:29.817606 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 06:02:29.824137 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4612 06:02:29.827209 0 9 12 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (0 0)
4613 06:02:29.830951 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4614 06:02:29.837131 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 06:02:29.840410 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 06:02:29.843596 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 06:02:29.850789 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 06:02:29.853705 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 06:02:29.857178 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 06:02:29.863488 0 10 12 | B1->B0 | 3333 3c3c | 0 0 | (0 0) (0 0)
4621 06:02:29.866955 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 06:02:29.870325 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 06:02:29.877564 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 06:02:29.880575 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 06:02:29.883884 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 06:02:29.887548 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 06:02:29.893717 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 06:02:29.897254 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4629 06:02:29.903375 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 06:02:29.906825 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 06:02:29.910291 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 06:02:29.913670 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 06:02:29.920420 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 06:02:29.923235 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 06:02:29.926926 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 06:02:29.933561 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 06:02:29.936446 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 06:02:29.940043 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 06:02:29.946624 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 06:02:29.949676 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 06:02:29.952947 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 06:02:29.959512 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 06:02:29.962652 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 06:02:29.966024 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4645 06:02:29.969540 Total UI for P1: 0, mck2ui 16
4646 06:02:29.972579 best dqsien dly found for B0: ( 0, 13, 10)
4647 06:02:29.979224 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 06:02:29.982946 Total UI for P1: 0, mck2ui 16
4649 06:02:29.986318 best dqsien dly found for B1: ( 0, 13, 12)
4650 06:02:29.989578 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4651 06:02:29.993018 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4652 06:02:29.993575
4653 06:02:29.995697 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4654 06:02:29.999147 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4655 06:02:30.002952 [Gating] SW calibration Done
4656 06:02:30.003473 ==
4657 06:02:30.005979 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 06:02:30.009386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 06:02:30.009837 ==
4660 06:02:30.012745 RX Vref Scan: 0
4661 06:02:30.013162
4662 06:02:30.015710 RX Vref 0 -> 0, step: 1
4663 06:02:30.016222
4664 06:02:30.016556 RX Delay -230 -> 252, step: 16
4665 06:02:30.022437 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4666 06:02:30.026049 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4667 06:02:30.028969 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4668 06:02:30.032460 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4669 06:02:30.038881 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4670 06:02:30.042206 iDelay=218, Bit 5, Center 41 (-134 ~ 217) 352
4671 06:02:30.045444 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4672 06:02:30.048931 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4673 06:02:30.055584 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4674 06:02:30.058739 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4675 06:02:30.062109 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4676 06:02:30.065347 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4677 06:02:30.071931 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4678 06:02:30.074977 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4679 06:02:30.078746 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4680 06:02:30.081977 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4681 06:02:30.082398 ==
4682 06:02:30.085111 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 06:02:30.092271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 06:02:30.092789 ==
4685 06:02:30.093132 DQS Delay:
4686 06:02:30.095261 DQS0 = 0, DQS1 = 0
4687 06:02:30.095680 DQM Delay:
4688 06:02:30.096012 DQM0 = 34, DQM1 = 30
4689 06:02:30.098476 DQ Delay:
4690 06:02:30.101747 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4691 06:02:30.105526 DQ4 =33, DQ5 =41, DQ6 =49, DQ7 =33
4692 06:02:30.108395 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4693 06:02:30.111479 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4694 06:02:30.111898
4695 06:02:30.112230
4696 06:02:30.112537 ==
4697 06:02:30.115034 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 06:02:30.118214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 06:02:30.118640 ==
4700 06:02:30.118971
4701 06:02:30.119279
4702 06:02:30.121891 TX Vref Scan disable
4703 06:02:30.122397 == TX Byte 0 ==
4704 06:02:30.128367 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4705 06:02:30.131927 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4706 06:02:30.135395 == TX Byte 1 ==
4707 06:02:30.138149 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4708 06:02:30.141728 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4709 06:02:30.142239 ==
4710 06:02:30.145244 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 06:02:30.147813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 06:02:30.151562 ==
4713 06:02:30.152079
4714 06:02:30.152413
4715 06:02:30.152720 TX Vref Scan disable
4716 06:02:30.155350 == TX Byte 0 ==
4717 06:02:30.158360 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4718 06:02:30.165521 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4719 06:02:30.166033 == TX Byte 1 ==
4720 06:02:30.168245 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4721 06:02:30.175094 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4722 06:02:30.175604
4723 06:02:30.175932 [DATLAT]
4724 06:02:30.176237 Freq=600, CH1 RK1
4725 06:02:30.176536
4726 06:02:30.178521 DATLAT Default: 0x9
4727 06:02:30.178933 0, 0xFFFF, sum = 0
4728 06:02:30.181511 1, 0xFFFF, sum = 0
4729 06:02:30.185158 2, 0xFFFF, sum = 0
4730 06:02:30.185760 3, 0xFFFF, sum = 0
4731 06:02:30.188671 4, 0xFFFF, sum = 0
4732 06:02:30.189184 5, 0xFFFF, sum = 0
4733 06:02:30.191065 6, 0xFFFF, sum = 0
4734 06:02:30.191481 7, 0xFFFF, sum = 0
4735 06:02:30.194756 8, 0x0, sum = 1
4736 06:02:30.195276 9, 0x0, sum = 2
4737 06:02:30.195745 10, 0x0, sum = 3
4738 06:02:30.197739 11, 0x0, sum = 4
4739 06:02:30.198237 best_step = 9
4740 06:02:30.198672
4741 06:02:30.201003 ==
4742 06:02:30.201444 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 06:02:30.207759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 06:02:30.208311 ==
4745 06:02:30.208782 RX Vref Scan: 0
4746 06:02:30.209105
4747 06:02:30.210944 RX Vref 0 -> 0, step: 1
4748 06:02:30.211379
4749 06:02:30.214536 RX Delay -195 -> 252, step: 8
4750 06:02:30.221567 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4751 06:02:30.224378 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4752 06:02:30.227714 iDelay=205, Bit 2, Center 20 (-139 ~ 180) 320
4753 06:02:30.231181 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4754 06:02:30.234708 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4755 06:02:30.241138 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4756 06:02:30.244657 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4757 06:02:30.247798 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4758 06:02:30.251239 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4759 06:02:30.254376 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4760 06:02:30.261013 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4761 06:02:30.264742 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4762 06:02:30.267266 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4763 06:02:30.270703 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4764 06:02:30.277680 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4765 06:02:30.280512 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4766 06:02:30.280932 ==
4767 06:02:30.284169 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 06:02:30.287564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 06:02:30.288076 ==
4770 06:02:30.291194 DQS Delay:
4771 06:02:30.291610 DQS0 = 0, DQS1 = 0
4772 06:02:30.294072 DQM Delay:
4773 06:02:30.294487 DQM0 = 36, DQM1 = 29
4774 06:02:30.294817 DQ Delay:
4775 06:02:30.297181 DQ0 =40, DQ1 =32, DQ2 =20, DQ3 =32
4776 06:02:30.300642 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =36
4777 06:02:30.304301 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4778 06:02:30.307081 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4779 06:02:30.307499
4780 06:02:30.307827
4781 06:02:30.317112 [DQSOSCAuto] RK1, (LSB)MR18= 0x3656, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4782 06:02:30.321074 CH1 RK1: MR19=808, MR18=3656
4783 06:02:30.327219 CH1_RK1: MR19=0x808, MR18=0x3656, DQSOSC=393, MR23=63, INC=169, DEC=113
4784 06:02:30.327641 [RxdqsGatingPostProcess] freq 600
4785 06:02:30.333769 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4786 06:02:30.337283 Pre-setting of DQS Precalculation
4787 06:02:30.340207 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4788 06:02:30.350220 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4789 06:02:30.357359 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4790 06:02:30.357975
4791 06:02:30.358313
4792 06:02:30.360561 [Calibration Summary] 1200 Mbps
4793 06:02:30.361004 CH 0, Rank 0
4794 06:02:30.363394 SW Impedance : PASS
4795 06:02:30.363768 DUTY Scan : NO K
4796 06:02:30.366906 ZQ Calibration : PASS
4797 06:02:30.370441 Jitter Meter : NO K
4798 06:02:30.370953 CBT Training : PASS
4799 06:02:30.373226 Write leveling : PASS
4800 06:02:30.376516 RX DQS gating : PASS
4801 06:02:30.376931 RX DQ/DQS(RDDQC) : PASS
4802 06:02:30.380057 TX DQ/DQS : PASS
4803 06:02:30.383958 RX DATLAT : PASS
4804 06:02:30.384534 RX DQ/DQS(Engine): PASS
4805 06:02:30.386622 TX OE : NO K
4806 06:02:30.387037 All Pass.
4807 06:02:30.387368
4808 06:02:30.390076 CH 0, Rank 1
4809 06:02:30.390491 SW Impedance : PASS
4810 06:02:30.393661 DUTY Scan : NO K
4811 06:02:30.396780 ZQ Calibration : PASS
4812 06:02:30.397192 Jitter Meter : NO K
4813 06:02:30.399658 CBT Training : PASS
4814 06:02:30.403750 Write leveling : PASS
4815 06:02:30.404282 RX DQS gating : PASS
4816 06:02:30.406868 RX DQ/DQS(RDDQC) : PASS
4817 06:02:30.410031 TX DQ/DQS : PASS
4818 06:02:30.410542 RX DATLAT : PASS
4819 06:02:30.413546 RX DQ/DQS(Engine): PASS
4820 06:02:30.414054 TX OE : NO K
4821 06:02:30.416942 All Pass.
4822 06:02:30.417449
4823 06:02:30.417845 CH 1, Rank 0
4824 06:02:30.420220 SW Impedance : PASS
4825 06:02:30.420730 DUTY Scan : NO K
4826 06:02:30.423246 ZQ Calibration : PASS
4827 06:02:30.426181 Jitter Meter : NO K
4828 06:02:30.426600 CBT Training : PASS
4829 06:02:30.429624 Write leveling : PASS
4830 06:02:30.433251 RX DQS gating : PASS
4831 06:02:30.433805 RX DQ/DQS(RDDQC) : PASS
4832 06:02:30.436883 TX DQ/DQS : PASS
4833 06:02:30.439378 RX DATLAT : PASS
4834 06:02:30.439798 RX DQ/DQS(Engine): PASS
4835 06:02:30.442775 TX OE : NO K
4836 06:02:30.443197 All Pass.
4837 06:02:30.443525
4838 06:02:30.446007 CH 1, Rank 1
4839 06:02:30.446424 SW Impedance : PASS
4840 06:02:30.449599 DUTY Scan : NO K
4841 06:02:30.452836 ZQ Calibration : PASS
4842 06:02:30.453255 Jitter Meter : NO K
4843 06:02:30.456297 CBT Training : PASS
4844 06:02:30.459230 Write leveling : PASS
4845 06:02:30.459651 RX DQS gating : PASS
4846 06:02:30.463070 RX DQ/DQS(RDDQC) : PASS
4847 06:02:30.465953 TX DQ/DQS : PASS
4848 06:02:30.466416 RX DATLAT : PASS
4849 06:02:30.469412 RX DQ/DQS(Engine): PASS
4850 06:02:30.469998 TX OE : NO K
4851 06:02:30.472897 All Pass.
4852 06:02:30.473343
4853 06:02:30.473785 DramC Write-DBI off
4854 06:02:30.476302 PER_BANK_REFRESH: Hybrid Mode
4855 06:02:30.479316 TX_TRACKING: ON
4856 06:02:30.485757 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4857 06:02:30.489438 [FAST_K] Save calibration result to emmc
4858 06:02:30.495987 dramc_set_vcore_voltage set vcore to 662500
4859 06:02:30.496552 Read voltage for 933, 3
4860 06:02:30.497047 Vio18 = 0
4861 06:02:30.499275 Vcore = 662500
4862 06:02:30.499826 Vdram = 0
4863 06:02:30.500296 Vddq = 0
4864 06:02:30.502885 Vmddr = 0
4865 06:02:30.505923 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4866 06:02:30.512668 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4867 06:02:30.513087 MEM_TYPE=3, freq_sel=17
4868 06:02:30.515986 sv_algorithm_assistance_LP4_1600
4869 06:02:30.522524 ============ PULL DRAM RESETB DOWN ============
4870 06:02:30.525962 ========== PULL DRAM RESETB DOWN end =========
4871 06:02:30.529415 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4872 06:02:30.532411 ===================================
4873 06:02:30.535907 LPDDR4 DRAM CONFIGURATION
4874 06:02:30.539234 ===================================
4875 06:02:30.542371 EX_ROW_EN[0] = 0x0
4876 06:02:30.542790 EX_ROW_EN[1] = 0x0
4877 06:02:30.545674 LP4Y_EN = 0x0
4878 06:02:30.546091 WORK_FSP = 0x0
4879 06:02:30.548733 WL = 0x3
4880 06:02:30.549160 RL = 0x3
4881 06:02:30.552287 BL = 0x2
4882 06:02:30.552704 RPST = 0x0
4883 06:02:30.556024 RD_PRE = 0x0
4884 06:02:30.556439 WR_PRE = 0x1
4885 06:02:30.559094 WR_PST = 0x0
4886 06:02:30.559513 DBI_WR = 0x0
4887 06:02:30.562531 DBI_RD = 0x0
4888 06:02:30.562946 OTF = 0x1
4889 06:02:30.565747 ===================================
4890 06:02:30.568854 ===================================
4891 06:02:30.572219 ANA top config
4892 06:02:30.575607 ===================================
4893 06:02:30.578761 DLL_ASYNC_EN = 0
4894 06:02:30.579177 ALL_SLAVE_EN = 1
4895 06:02:30.582257 NEW_RANK_MODE = 1
4896 06:02:30.586010 DLL_IDLE_MODE = 1
4897 06:02:30.588924 LP45_APHY_COMB_EN = 1
4898 06:02:30.589339 TX_ODT_DIS = 1
4899 06:02:30.592606 NEW_8X_MODE = 1
4900 06:02:30.595627 ===================================
4901 06:02:30.599113 ===================================
4902 06:02:30.602790 data_rate = 1866
4903 06:02:30.605470 CKR = 1
4904 06:02:30.609079 DQ_P2S_RATIO = 8
4905 06:02:30.611970 ===================================
4906 06:02:30.615508 CA_P2S_RATIO = 8
4907 06:02:30.615958 DQ_CA_OPEN = 0
4908 06:02:30.618814 DQ_SEMI_OPEN = 0
4909 06:02:30.622172 CA_SEMI_OPEN = 0
4910 06:02:30.625846 CA_FULL_RATE = 0
4911 06:02:30.628889 DQ_CKDIV4_EN = 1
4912 06:02:30.632027 CA_CKDIV4_EN = 1
4913 06:02:30.632447 CA_PREDIV_EN = 0
4914 06:02:30.635543 PH8_DLY = 0
4915 06:02:30.638537 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4916 06:02:30.641558 DQ_AAMCK_DIV = 4
4917 06:02:30.645508 CA_AAMCK_DIV = 4
4918 06:02:30.648667 CA_ADMCK_DIV = 4
4919 06:02:30.649369 DQ_TRACK_CA_EN = 0
4920 06:02:30.651805 CA_PICK = 933
4921 06:02:30.655130 CA_MCKIO = 933
4922 06:02:30.658442 MCKIO_SEMI = 0
4923 06:02:30.661921 PLL_FREQ = 3732
4924 06:02:30.664871 DQ_UI_PI_RATIO = 32
4925 06:02:30.668384 CA_UI_PI_RATIO = 0
4926 06:02:30.671499 ===================================
4927 06:02:30.675167 ===================================
4928 06:02:30.675349 memory_type:LPDDR4
4929 06:02:30.678213 GP_NUM : 10
4930 06:02:30.681441 SRAM_EN : 1
4931 06:02:30.681697 MD32_EN : 0
4932 06:02:30.684720 ===================================
4933 06:02:30.688312 [ANA_INIT] >>>>>>>>>>>>>>
4934 06:02:30.691387 <<<<<< [CONFIGURE PHASE]: ANA_TX
4935 06:02:30.694514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4936 06:02:30.698378 ===================================
4937 06:02:30.701239 data_rate = 1866,PCW = 0X8f00
4938 06:02:30.704913 ===================================
4939 06:02:30.707934 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4940 06:02:30.711416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4941 06:02:30.718095 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4942 06:02:30.721578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4943 06:02:30.724579 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4944 06:02:30.728095 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4945 06:02:30.731418 [ANA_INIT] flow start
4946 06:02:30.734823 [ANA_INIT] PLL >>>>>>>>
4947 06:02:30.735240 [ANA_INIT] PLL <<<<<<<<
4948 06:02:30.738487 [ANA_INIT] MIDPI >>>>>>>>
4949 06:02:30.741430 [ANA_INIT] MIDPI <<<<<<<<
4950 06:02:30.741878 [ANA_INIT] DLL >>>>>>>>
4951 06:02:30.745099 [ANA_INIT] flow end
4952 06:02:30.748000 ============ LP4 DIFF to SE enter ============
4953 06:02:30.754735 ============ LP4 DIFF to SE exit ============
4954 06:02:30.755251 [ANA_INIT] <<<<<<<<<<<<<
4955 06:02:30.757977 [Flow] Enable top DCM control >>>>>
4956 06:02:30.761391 [Flow] Enable top DCM control <<<<<
4957 06:02:30.764526 Enable DLL master slave shuffle
4958 06:02:30.770968 ==============================================================
4959 06:02:30.771392 Gating Mode config
4960 06:02:30.778009 ==============================================================
4961 06:02:30.780983 Config description:
4962 06:02:30.788065 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4963 06:02:30.794532 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4964 06:02:30.800762 SELPH_MODE 0: By rank 1: By Phase
4965 06:02:30.808051 ==============================================================
4966 06:02:30.810925 GAT_TRACK_EN = 1
4967 06:02:30.811344 RX_GATING_MODE = 2
4968 06:02:30.814201 RX_GATING_TRACK_MODE = 2
4969 06:02:30.817424 SELPH_MODE = 1
4970 06:02:30.820815 PICG_EARLY_EN = 1
4971 06:02:30.824244 VALID_LAT_VALUE = 1
4972 06:02:30.831000 ==============================================================
4973 06:02:30.833955 Enter into Gating configuration >>>>
4974 06:02:30.837361 Exit from Gating configuration <<<<
4975 06:02:30.840565 Enter into DVFS_PRE_config >>>>>
4976 06:02:30.850947 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4977 06:02:30.854334 Exit from DVFS_PRE_config <<<<<
4978 06:02:30.857461 Enter into PICG configuration >>>>
4979 06:02:30.860925 Exit from PICG configuration <<<<
4980 06:02:30.863927 [RX_INPUT] configuration >>>>>
4981 06:02:30.867432 [RX_INPUT] configuration <<<<<
4982 06:02:30.870536 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4983 06:02:30.877378 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4984 06:02:30.884003 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4985 06:02:30.887421 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4986 06:02:30.894203 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4987 06:02:30.900717 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4988 06:02:30.904331 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4989 06:02:30.907271 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4990 06:02:30.913997 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4991 06:02:30.917443 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4992 06:02:30.920836 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4993 06:02:30.927130 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4994 06:02:30.930869 ===================================
4995 06:02:30.931289 LPDDR4 DRAM CONFIGURATION
4996 06:02:30.934105 ===================================
4997 06:02:30.937248 EX_ROW_EN[0] = 0x0
4998 06:02:30.940938 EX_ROW_EN[1] = 0x0
4999 06:02:30.941356 LP4Y_EN = 0x0
5000 06:02:30.943912 WORK_FSP = 0x0
5001 06:02:30.944423 WL = 0x3
5002 06:02:30.946930 RL = 0x3
5003 06:02:30.947349 BL = 0x2
5004 06:02:30.949996 RPST = 0x0
5005 06:02:30.950555 RD_PRE = 0x0
5006 06:02:30.953562 WR_PRE = 0x1
5007 06:02:30.953983 WR_PST = 0x0
5008 06:02:30.957179 DBI_WR = 0x0
5009 06:02:30.957649 DBI_RD = 0x0
5010 06:02:30.960069 OTF = 0x1
5011 06:02:30.963769 ===================================
5012 06:02:30.966826 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5013 06:02:30.970282 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5014 06:02:30.976800 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5015 06:02:30.980263 ===================================
5016 06:02:30.980685 LPDDR4 DRAM CONFIGURATION
5017 06:02:30.983416 ===================================
5018 06:02:30.986734 EX_ROW_EN[0] = 0x10
5019 06:02:30.989930 EX_ROW_EN[1] = 0x0
5020 06:02:30.990348 LP4Y_EN = 0x0
5021 06:02:30.993613 WORK_FSP = 0x0
5022 06:02:30.994037 WL = 0x3
5023 06:02:30.996548 RL = 0x3
5024 06:02:30.996963 BL = 0x2
5025 06:02:31.000218 RPST = 0x0
5026 06:02:31.000635 RD_PRE = 0x0
5027 06:02:31.003153 WR_PRE = 0x1
5028 06:02:31.003566 WR_PST = 0x0
5029 06:02:31.006426 DBI_WR = 0x0
5030 06:02:31.006842 DBI_RD = 0x0
5031 06:02:31.009729 OTF = 0x1
5032 06:02:31.013302 ===================================
5033 06:02:31.019949 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5034 06:02:31.023368 nWR fixed to 30
5035 06:02:31.023791 [ModeRegInit_LP4] CH0 RK0
5036 06:02:31.026380 [ModeRegInit_LP4] CH0 RK1
5037 06:02:31.029669 [ModeRegInit_LP4] CH1 RK0
5038 06:02:31.030086 [ModeRegInit_LP4] CH1 RK1
5039 06:02:31.033175 match AC timing 9
5040 06:02:31.036376 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5041 06:02:31.039861 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5042 06:02:31.046274 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5043 06:02:31.049879 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5044 06:02:31.056616 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5045 06:02:31.057037 ==
5046 06:02:31.059766 Dram Type= 6, Freq= 0, CH_0, rank 0
5047 06:02:31.063222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5048 06:02:31.063643 ==
5049 06:02:31.069720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5050 06:02:31.076351 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5051 06:02:31.079909 [CA 0] Center 38 (8~69) winsize 62
5052 06:02:31.082834 [CA 1] Center 38 (8~69) winsize 62
5053 06:02:31.086326 [CA 2] Center 35 (5~66) winsize 62
5054 06:02:31.089967 [CA 3] Center 35 (5~65) winsize 61
5055 06:02:31.093212 [CA 4] Center 34 (4~65) winsize 62
5056 06:02:31.093681 [CA 5] Center 33 (3~64) winsize 62
5057 06:02:31.096282
5058 06:02:31.099458 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5059 06:02:31.099876
5060 06:02:31.102963 [CATrainingPosCal] consider 1 rank data
5061 06:02:31.106020 u2DelayCellTimex100 = 270/100 ps
5062 06:02:31.109558 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5063 06:02:31.112840 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5064 06:02:31.116303 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5065 06:02:31.119710 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5066 06:02:31.122826 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5067 06:02:31.126225 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5068 06:02:31.126645
5069 06:02:31.129581 CA PerBit enable=1, Macro0, CA PI delay=33
5070 06:02:31.132620
5071 06:02:31.133037 [CBTSetCACLKResult] CA Dly = 33
5072 06:02:31.135818 CS Dly: 7 (0~38)
5073 06:02:31.136236 ==
5074 06:02:31.139189 Dram Type= 6, Freq= 0, CH_0, rank 1
5075 06:02:31.142320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5076 06:02:31.142741 ==
5077 06:02:31.149385 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5078 06:02:31.155540 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5079 06:02:31.159438 [CA 0] Center 38 (8~69) winsize 62
5080 06:02:31.162313 [CA 1] Center 38 (8~69) winsize 62
5081 06:02:31.165517 [CA 2] Center 35 (5~66) winsize 62
5082 06:02:31.169233 [CA 3] Center 35 (5~66) winsize 62
5083 06:02:31.172258 [CA 4] Center 34 (3~65) winsize 63
5084 06:02:31.175353 [CA 5] Center 33 (3~64) winsize 62
5085 06:02:31.175771
5086 06:02:31.179020 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5087 06:02:31.179495
5088 06:02:31.182113 [CATrainingPosCal] consider 2 rank data
5089 06:02:31.185643 u2DelayCellTimex100 = 270/100 ps
5090 06:02:31.189121 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5091 06:02:31.192187 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5092 06:02:31.195685 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5093 06:02:31.198675 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5094 06:02:31.202001 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5095 06:02:31.205294 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5096 06:02:31.208647
5097 06:02:31.211954 CA PerBit enable=1, Macro0, CA PI delay=33
5098 06:02:31.212394
5099 06:02:31.215371 [CBTSetCACLKResult] CA Dly = 33
5100 06:02:31.215783 CS Dly: 7 (0~39)
5101 06:02:31.216111
5102 06:02:31.218633 ----->DramcWriteLeveling(PI) begin...
5103 06:02:31.219054 ==
5104 06:02:31.222263 Dram Type= 6, Freq= 0, CH_0, rank 0
5105 06:02:31.225549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 06:02:31.228507 ==
5107 06:02:31.228921 Write leveling (Byte 0): 33 => 33
5108 06:02:31.232317 Write leveling (Byte 1): 29 => 29
5109 06:02:31.235248 DramcWriteLeveling(PI) end<-----
5110 06:02:31.235805
5111 06:02:31.236229 ==
5112 06:02:31.238282 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 06:02:31.244911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 06:02:31.245436 ==
5115 06:02:31.248211 [Gating] SW mode calibration
5116 06:02:31.255356 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5117 06:02:31.258191 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5118 06:02:31.264859 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5119 06:02:31.268296 0 14 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
5120 06:02:31.271866 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 06:02:31.278142 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 06:02:31.281790 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 06:02:31.285176 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 06:02:31.291692 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 06:02:31.295313 0 14 28 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5126 06:02:31.298070 0 15 0 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
5127 06:02:31.301354 0 15 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5128 06:02:31.308258 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 06:02:31.311998 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 06:02:31.314918 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 06:02:31.321598 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 06:02:31.325141 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 06:02:31.327763 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5134 06:02:31.334571 1 0 0 | B1->B0 | 2c2c 3a3a | 0 0 | (0 0) (0 0)
5135 06:02:31.337643 1 0 4 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
5136 06:02:31.341297 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 06:02:31.347828 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 06:02:31.351060 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 06:02:31.354245 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 06:02:31.361323 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 06:02:31.364485 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5142 06:02:31.367638 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5143 06:02:31.374873 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 06:02:31.378022 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 06:02:31.381321 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 06:02:31.388045 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 06:02:31.390997 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 06:02:31.394298 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 06:02:31.400692 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 06:02:31.404115 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 06:02:31.407970 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 06:02:31.414055 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 06:02:31.417183 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 06:02:31.420651 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 06:02:31.427142 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 06:02:31.430576 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 06:02:31.433720 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5158 06:02:31.440100 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5159 06:02:31.443275 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5160 06:02:31.446985 Total UI for P1: 0, mck2ui 16
5161 06:02:31.450557 best dqsien dly found for B0: ( 1, 2, 30)
5162 06:02:31.453416 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 06:02:31.457000 Total UI for P1: 0, mck2ui 16
5164 06:02:31.459949 best dqsien dly found for B1: ( 1, 3, 4)
5165 06:02:31.463497 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5166 06:02:31.466425 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5167 06:02:31.466506
5168 06:02:31.472951 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5169 06:02:31.476441 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5170 06:02:31.476521 [Gating] SW calibration Done
5171 06:02:31.479983 ==
5172 06:02:31.482957 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 06:02:31.486454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 06:02:31.486535 ==
5175 06:02:31.486599 RX Vref Scan: 0
5176 06:02:31.486658
5177 06:02:31.489867 RX Vref 0 -> 0, step: 1
5178 06:02:31.489947
5179 06:02:31.492742 RX Delay -80 -> 252, step: 8
5180 06:02:31.496197 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5181 06:02:31.499778 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5182 06:02:31.502683 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5183 06:02:31.509576 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5184 06:02:31.513037 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5185 06:02:31.516007 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5186 06:02:31.519336 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5187 06:02:31.522965 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5188 06:02:31.526158 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5189 06:02:31.532881 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5190 06:02:31.536095 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5191 06:02:31.539293 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5192 06:02:31.542475 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5193 06:02:31.549200 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5194 06:02:31.552656 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5195 06:02:31.555607 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5196 06:02:31.555687 ==
5197 06:02:31.559334 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 06:02:31.562234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 06:02:31.562315 ==
5200 06:02:31.565757 DQS Delay:
5201 06:02:31.565837 DQS0 = 0, DQS1 = 0
5202 06:02:31.569211 DQM Delay:
5203 06:02:31.569291 DQM0 = 94, DQM1 = 82
5204 06:02:31.569355 DQ Delay:
5205 06:02:31.572182 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5206 06:02:31.575799 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5207 06:02:31.578682 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5208 06:02:31.582119 DQ12 =83, DQ13 =91, DQ14 =91, DQ15 =91
5209 06:02:31.582199
5210 06:02:31.585649
5211 06:02:31.585728 ==
5212 06:02:31.588564 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 06:02:31.592115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 06:02:31.592196 ==
5215 06:02:31.592260
5216 06:02:31.592318
5217 06:02:31.595480 TX Vref Scan disable
5218 06:02:31.595560 == TX Byte 0 ==
5219 06:02:31.601812 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5220 06:02:31.604921 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5221 06:02:31.605001 == TX Byte 1 ==
5222 06:02:31.611616 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5223 06:02:31.615141 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5224 06:02:31.615221 ==
5225 06:02:31.618013 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 06:02:31.621472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 06:02:31.621572 ==
5228 06:02:31.621636
5229 06:02:31.621694
5230 06:02:31.624963 TX Vref Scan disable
5231 06:02:31.628463 == TX Byte 0 ==
5232 06:02:31.631858 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5233 06:02:31.634775 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5234 06:02:31.638030 == TX Byte 1 ==
5235 06:02:31.641351 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5236 06:02:31.644581 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5237 06:02:31.644668
5238 06:02:31.648232 [DATLAT]
5239 06:02:31.648313 Freq=933, CH0 RK0
5240 06:02:31.648378
5241 06:02:31.651336 DATLAT Default: 0xd
5242 06:02:31.651426 0, 0xFFFF, sum = 0
5243 06:02:31.654701 1, 0xFFFF, sum = 0
5244 06:02:31.654783 2, 0xFFFF, sum = 0
5245 06:02:31.657731 3, 0xFFFF, sum = 0
5246 06:02:31.657814 4, 0xFFFF, sum = 0
5247 06:02:31.661030 5, 0xFFFF, sum = 0
5248 06:02:31.661114 6, 0xFFFF, sum = 0
5249 06:02:31.664557 7, 0xFFFF, sum = 0
5250 06:02:31.664639 8, 0xFFFF, sum = 0
5251 06:02:31.667584 9, 0xFFFF, sum = 0
5252 06:02:31.670771 10, 0x0, sum = 1
5253 06:02:31.670882 11, 0x0, sum = 2
5254 06:02:31.670960 12, 0x0, sum = 3
5255 06:02:31.674567 13, 0x0, sum = 4
5256 06:02:31.674670 best_step = 11
5257 06:02:31.674752
5258 06:02:31.674816 ==
5259 06:02:31.677555 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 06:02:31.684456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 06:02:31.684539 ==
5262 06:02:31.684605 RX Vref Scan: 1
5263 06:02:31.684666
5264 06:02:31.687945 RX Vref 0 -> 0, step: 1
5265 06:02:31.688026
5266 06:02:31.690996 RX Delay -77 -> 252, step: 4
5267 06:02:31.691079
5268 06:02:31.694494 Set Vref, RX VrefLevel [Byte0]: 59
5269 06:02:31.697444 [Byte1]: 54
5270 06:02:31.697572
5271 06:02:31.700890 Final RX Vref Byte 0 = 59 to rank0
5272 06:02:31.703812 Final RX Vref Byte 1 = 54 to rank0
5273 06:02:31.707458 Final RX Vref Byte 0 = 59 to rank1
5274 06:02:31.710459 Final RX Vref Byte 1 = 54 to rank1==
5275 06:02:31.713968 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 06:02:31.717318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 06:02:31.720868 ==
5278 06:02:31.720949 DQS Delay:
5279 06:02:31.721013 DQS0 = 0, DQS1 = 0
5280 06:02:31.724287 DQM Delay:
5281 06:02:31.724369 DQM0 = 95, DQM1 = 83
5282 06:02:31.727208 DQ Delay:
5283 06:02:31.727289 DQ0 =92, DQ1 =96, DQ2 =94, DQ3 =92
5284 06:02:31.730810 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5285 06:02:31.734275 DQ8 =78, DQ9 =68, DQ10 =84, DQ11 =78
5286 06:02:31.737231 DQ12 =86, DQ13 =86, DQ14 =94, DQ15 =90
5287 06:02:31.740814
5288 06:02:31.740894
5289 06:02:31.747490 [DQSOSCAuto] RK0, (LSB)MR18= 0x1211, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5290 06:02:31.750349 CH0 RK0: MR19=505, MR18=1211
5291 06:02:31.757160 CH0_RK0: MR19=0x505, MR18=0x1211, DQSOSC=416, MR23=63, INC=62, DEC=41
5292 06:02:31.757262
5293 06:02:31.760524 ----->DramcWriteLeveling(PI) begin...
5294 06:02:31.760651 ==
5295 06:02:31.763597 Dram Type= 6, Freq= 0, CH_0, rank 1
5296 06:02:31.767062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 06:02:31.767151 ==
5298 06:02:31.770497 Write leveling (Byte 0): 32 => 32
5299 06:02:31.773858 Write leveling (Byte 1): 32 => 32
5300 06:02:31.777226 DramcWriteLeveling(PI) end<-----
5301 06:02:31.777306
5302 06:02:31.777368 ==
5303 06:02:31.779958 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 06:02:31.783872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 06:02:31.783960 ==
5306 06:02:31.786799 [Gating] SW mode calibration
5307 06:02:31.793239 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5308 06:02:31.800004 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5309 06:02:31.803458 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5310 06:02:31.809999 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 06:02:31.813404 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 06:02:31.816938 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 06:02:31.819834 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 06:02:31.826730 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 06:02:31.829716 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 06:02:31.833111 0 14 28 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (1 1)
5317 06:02:31.840276 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5318 06:02:31.843379 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 06:02:31.846307 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 06:02:31.853156 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 06:02:31.856523 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 06:02:31.859542 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 06:02:31.866233 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 06:02:31.869436 0 15 28 | B1->B0 | 2626 3636 | 0 1 | (0 0) (0 0)
5325 06:02:31.873327 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5326 06:02:31.879777 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 06:02:31.883261 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 06:02:31.886199 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 06:02:31.893243 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 06:02:31.896472 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 06:02:31.899859 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5332 06:02:31.906157 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5333 06:02:31.909641 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5334 06:02:31.913190 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 06:02:31.919844 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 06:02:31.922957 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 06:02:31.926359 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 06:02:31.933091 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 06:02:31.936134 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 06:02:31.939729 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 06:02:31.946444 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 06:02:31.950109 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 06:02:31.953182 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 06:02:31.959661 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 06:02:31.963040 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 06:02:31.966351 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 06:02:31.972625 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5348 06:02:31.976183 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5349 06:02:31.979828 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5350 06:02:31.983064 Total UI for P1: 0, mck2ui 16
5351 06:02:31.985937 best dqsien dly found for B0: ( 1, 2, 26)
5352 06:02:31.989795 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5353 06:02:31.996379 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 06:02:31.999693 Total UI for P1: 0, mck2ui 16
5355 06:02:32.002744 best dqsien dly found for B1: ( 1, 3, 2)
5356 06:02:32.006486 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5357 06:02:32.009431 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5358 06:02:32.009906
5359 06:02:32.013070 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5360 06:02:32.015799 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5361 06:02:32.019431 [Gating] SW calibration Done
5362 06:02:32.020152 ==
5363 06:02:32.022811 Dram Type= 6, Freq= 0, CH_0, rank 1
5364 06:02:32.025951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 06:02:32.026465 ==
5366 06:02:32.029676 RX Vref Scan: 0
5367 06:02:32.030209
5368 06:02:32.030662 RX Vref 0 -> 0, step: 1
5369 06:02:32.032641
5370 06:02:32.033201 RX Delay -80 -> 252, step: 8
5371 06:02:32.039366 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5372 06:02:32.042700 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5373 06:02:32.045466 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5374 06:02:32.049004 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5375 06:02:32.052675 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5376 06:02:32.055745 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5377 06:02:32.062581 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5378 06:02:32.065540 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5379 06:02:32.069205 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5380 06:02:32.072658 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5381 06:02:32.075470 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5382 06:02:32.082720 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5383 06:02:32.085429 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5384 06:02:32.088887 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5385 06:02:32.092460 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5386 06:02:32.095453 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5387 06:02:32.095872 ==
5388 06:02:32.099025 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 06:02:32.105345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 06:02:32.105807 ==
5391 06:02:32.106139 DQS Delay:
5392 06:02:32.108943 DQS0 = 0, DQS1 = 0
5393 06:02:32.109359 DQM Delay:
5394 06:02:32.111839 DQM0 = 92, DQM1 = 84
5395 06:02:32.112338 DQ Delay:
5396 06:02:32.115328 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5397 06:02:32.118665 DQ4 =91, DQ5 =79, DQ6 =99, DQ7 =103
5398 06:02:32.121841 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =79
5399 06:02:32.125537 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5400 06:02:32.125958
5401 06:02:32.126287
5402 06:02:32.126596 ==
5403 06:02:32.128496 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 06:02:32.132187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 06:02:32.132605 ==
5406 06:02:32.132936
5407 06:02:32.133243
5408 06:02:32.135445 TX Vref Scan disable
5409 06:02:32.138303 == TX Byte 0 ==
5410 06:02:32.142446 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5411 06:02:32.145342 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5412 06:02:32.148683 == TX Byte 1 ==
5413 06:02:32.151679 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5414 06:02:32.155565 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5415 06:02:32.155986 ==
5416 06:02:32.158163 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 06:02:32.161816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 06:02:32.165193 ==
5419 06:02:32.165681
5420 06:02:32.166051
5421 06:02:32.166361 TX Vref Scan disable
5422 06:02:32.168699 == TX Byte 0 ==
5423 06:02:32.171716 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5424 06:02:32.178303 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5425 06:02:32.178722 == TX Byte 1 ==
5426 06:02:32.181979 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5427 06:02:32.188061 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5428 06:02:32.188487
5429 06:02:32.188817 [DATLAT]
5430 06:02:32.189123 Freq=933, CH0 RK1
5431 06:02:32.189422
5432 06:02:32.191419 DATLAT Default: 0xb
5433 06:02:32.191837 0, 0xFFFF, sum = 0
5434 06:02:32.194995 1, 0xFFFF, sum = 0
5435 06:02:32.199715 2, 0xFFFF, sum = 0
5436 06:02:32.200135 3, 0xFFFF, sum = 0
5437 06:02:32.201134 4, 0xFFFF, sum = 0
5438 06:02:32.201614 5, 0xFFFF, sum = 0
5439 06:02:32.204860 6, 0xFFFF, sum = 0
5440 06:02:32.205281 7, 0xFFFF, sum = 0
5441 06:02:32.208364 8, 0xFFFF, sum = 0
5442 06:02:32.208835 9, 0xFFFF, sum = 0
5443 06:02:32.211939 10, 0x0, sum = 1
5444 06:02:32.212358 11, 0x0, sum = 2
5445 06:02:32.214683 12, 0x0, sum = 3
5446 06:02:32.215107 13, 0x0, sum = 4
5447 06:02:32.215445 best_step = 11
5448 06:02:32.215754
5449 06:02:32.218384 ==
5450 06:02:32.222043 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 06:02:32.225092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 06:02:32.225639 ==
5453 06:02:32.225983 RX Vref Scan: 0
5454 06:02:32.226290
5455 06:02:32.228107 RX Vref 0 -> 0, step: 1
5456 06:02:32.228519
5457 06:02:32.231408 RX Delay -77 -> 252, step: 4
5458 06:02:32.235161 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5459 06:02:32.241435 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5460 06:02:32.245092 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5461 06:02:32.247936 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5462 06:02:32.251632 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5463 06:02:32.254575 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5464 06:02:32.261446 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5465 06:02:32.264511 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5466 06:02:32.267774 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5467 06:02:32.270817 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5468 06:02:32.274682 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5469 06:02:32.280926 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5470 06:02:32.284312 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5471 06:02:32.287991 iDelay=199, Bit 13, Center 90 (-5 ~ 186) 192
5472 06:02:32.291184 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5473 06:02:32.294752 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5474 06:02:32.295171 ==
5475 06:02:32.297985 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 06:02:32.304199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 06:02:32.304620 ==
5478 06:02:32.304953 DQS Delay:
5479 06:02:32.307980 DQS0 = 0, DQS1 = 0
5480 06:02:32.308396 DQM Delay:
5481 06:02:32.308729 DQM0 = 92, DQM1 = 84
5482 06:02:32.311256 DQ Delay:
5483 06:02:32.314601 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =88
5484 06:02:32.317598 DQ4 =90, DQ5 =80, DQ6 =106, DQ7 =102
5485 06:02:32.321078 DQ8 =78, DQ9 =68, DQ10 =84, DQ11 =78
5486 06:02:32.324731 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5487 06:02:32.325147
5488 06:02:32.325515
5489 06:02:32.330792 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5490 06:02:32.334594 CH0 RK1: MR19=505, MR18=2A0C
5491 06:02:32.341176 CH0_RK1: MR19=0x505, MR18=0x2A0C, DQSOSC=408, MR23=63, INC=65, DEC=43
5492 06:02:32.344692 [RxdqsGatingPostProcess] freq 933
5493 06:02:32.347640 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5494 06:02:32.351143 best DQS0 dly(2T, 0.5T) = (0, 10)
5495 06:02:32.354085 best DQS1 dly(2T, 0.5T) = (0, 11)
5496 06:02:32.357747 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5497 06:02:32.360645 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5498 06:02:32.364190 best DQS0 dly(2T, 0.5T) = (0, 10)
5499 06:02:32.367393 best DQS1 dly(2T, 0.5T) = (0, 11)
5500 06:02:32.370763 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5501 06:02:32.374219 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5502 06:02:32.377562 Pre-setting of DQS Precalculation
5503 06:02:32.380287 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5504 06:02:32.383897 ==
5505 06:02:32.387044 Dram Type= 6, Freq= 0, CH_1, rank 0
5506 06:02:32.390439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 06:02:32.390861 ==
5508 06:02:32.393523 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5509 06:02:32.400452 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5510 06:02:32.403913 [CA 0] Center 37 (7~67) winsize 61
5511 06:02:32.407516 [CA 1] Center 37 (7~67) winsize 61
5512 06:02:32.411026 [CA 2] Center 34 (5~64) winsize 60
5513 06:02:32.413917 [CA 3] Center 34 (4~64) winsize 61
5514 06:02:32.417574 [CA 4] Center 34 (5~64) winsize 60
5515 06:02:32.420417 [CA 5] Center 33 (4~63) winsize 60
5516 06:02:32.420835
5517 06:02:32.423966 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5518 06:02:32.424384
5519 06:02:32.427044 [CATrainingPosCal] consider 1 rank data
5520 06:02:32.430714 u2DelayCellTimex100 = 270/100 ps
5521 06:02:32.433790 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5522 06:02:32.440605 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5523 06:02:32.443539 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5524 06:02:32.447080 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5525 06:02:32.450513 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5526 06:02:32.453591 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5527 06:02:32.454012
5528 06:02:32.456960 CA PerBit enable=1, Macro0, CA PI delay=33
5529 06:02:32.457376
5530 06:02:32.460138 [CBTSetCACLKResult] CA Dly = 33
5531 06:02:32.463756 CS Dly: 6 (0~37)
5532 06:02:32.464171 ==
5533 06:02:32.466807 Dram Type= 6, Freq= 0, CH_1, rank 1
5534 06:02:32.469950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 06:02:32.470370 ==
5536 06:02:32.476996 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5537 06:02:32.479764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5538 06:02:32.484343 [CA 0] Center 37 (8~67) winsize 60
5539 06:02:32.487681 [CA 1] Center 37 (7~67) winsize 61
5540 06:02:32.490477 [CA 2] Center 35 (5~65) winsize 61
5541 06:02:32.493962 [CA 3] Center 34 (4~64) winsize 61
5542 06:02:32.497308 [CA 4] Center 34 (5~64) winsize 60
5543 06:02:32.501025 [CA 5] Center 34 (4~64) winsize 61
5544 06:02:32.501430
5545 06:02:32.503831 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5546 06:02:32.504255
5547 06:02:32.506861 [CATrainingPosCal] consider 2 rank data
5548 06:02:32.510305 u2DelayCellTimex100 = 270/100 ps
5549 06:02:32.513678 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5550 06:02:32.520367 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5551 06:02:32.523791 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5552 06:02:32.527275 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5553 06:02:32.530429 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5554 06:02:32.533739 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5555 06:02:32.534285
5556 06:02:32.537219 CA PerBit enable=1, Macro0, CA PI delay=33
5557 06:02:32.537771
5558 06:02:32.540816 [CBTSetCACLKResult] CA Dly = 33
5559 06:02:32.541382 CS Dly: 7 (0~39)
5560 06:02:32.543868
5561 06:02:32.547505 ----->DramcWriteLeveling(PI) begin...
5562 06:02:32.548041 ==
5563 06:02:32.550556 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 06:02:32.553893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 06:02:32.554335 ==
5566 06:02:32.556879 Write leveling (Byte 0): 26 => 26
5567 06:02:32.560401 Write leveling (Byte 1): 30 => 30
5568 06:02:32.563442 DramcWriteLeveling(PI) end<-----
5569 06:02:32.563872
5570 06:02:32.564243 ==
5571 06:02:32.567057 Dram Type= 6, Freq= 0, CH_1, rank 0
5572 06:02:32.570144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 06:02:32.570581 ==
5574 06:02:32.573665 [Gating] SW mode calibration
5575 06:02:32.580227 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5576 06:02:32.587003 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5577 06:02:32.590218 0 14 0 | B1->B0 | 3231 3232 | 1 1 | (1 1) (0 0)
5578 06:02:32.593321 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 06:02:32.600288 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 06:02:32.603704 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 06:02:32.606868 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 06:02:32.613068 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 06:02:32.616404 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 06:02:32.620035 0 14 28 | B1->B0 | 2e2e 3131 | 0 1 | (0 1) (1 1)
5585 06:02:32.627027 0 15 0 | B1->B0 | 2525 2626 | 0 0 | (1 0) (1 0)
5586 06:02:32.629707 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 06:02:32.633466 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 06:02:32.639935 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 06:02:32.643320 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 06:02:32.646360 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 06:02:32.649982 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 06:02:32.656508 0 15 28 | B1->B0 | 3434 3333 | 0 0 | (0 0) (1 1)
5593 06:02:32.659710 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 06:02:32.666040 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 06:02:32.669410 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 06:02:32.673001 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 06:02:32.676505 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 06:02:32.682529 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 06:02:32.686053 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 06:02:32.689505 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5601 06:02:32.695954 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 06:02:32.699736 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 06:02:32.702356 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 06:02:32.709247 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 06:02:32.712837 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 06:02:32.716081 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 06:02:32.722633 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 06:02:32.726443 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 06:02:32.729551 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 06:02:32.736577 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 06:02:32.739821 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 06:02:32.742916 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 06:02:32.749121 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 06:02:32.752437 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 06:02:32.756258 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 06:02:32.762664 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5617 06:02:32.766009 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5618 06:02:32.769141 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 06:02:32.772526 Total UI for P1: 0, mck2ui 16
5620 06:02:32.776334 best dqsien dly found for B0: ( 1, 2, 30)
5621 06:02:32.778984 Total UI for P1: 0, mck2ui 16
5622 06:02:32.782490 best dqsien dly found for B1: ( 1, 2, 30)
5623 06:02:32.786024 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5624 06:02:32.788641 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5625 06:02:32.789196
5626 06:02:32.795825 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5627 06:02:32.798980 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5628 06:02:32.799481 [Gating] SW calibration Done
5629 06:02:32.801995 ==
5630 06:02:32.805329 Dram Type= 6, Freq= 0, CH_1, rank 0
5631 06:02:32.809312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5632 06:02:32.809978 ==
5633 06:02:32.810320 RX Vref Scan: 0
5634 06:02:32.810626
5635 06:02:32.811950 RX Vref 0 -> 0, step: 1
5636 06:02:32.812362
5637 06:02:32.815411 RX Delay -80 -> 252, step: 8
5638 06:02:32.818704 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5639 06:02:32.822084 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5640 06:02:32.825949 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5641 06:02:32.832324 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5642 06:02:32.835715 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5643 06:02:32.838696 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5644 06:02:32.842087 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5645 06:02:32.845146 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5646 06:02:32.848561 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5647 06:02:32.855763 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5648 06:02:32.858891 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5649 06:02:32.861738 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5650 06:02:32.865102 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5651 06:02:32.868359 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5652 06:02:32.875233 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5653 06:02:32.878709 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5654 06:02:32.879121 ==
5655 06:02:32.881646 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 06:02:32.885001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 06:02:32.885416 ==
5658 06:02:32.888566 DQS Delay:
5659 06:02:32.888973 DQS0 = 0, DQS1 = 0
5660 06:02:32.889295 DQM Delay:
5661 06:02:32.891707 DQM0 = 94, DQM1 = 86
5662 06:02:32.892209 DQ Delay:
5663 06:02:32.895349 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5664 06:02:32.898461 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5665 06:02:32.901426 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5666 06:02:32.904837 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5667 06:02:32.905345
5668 06:02:32.905740
5669 06:02:32.908348 ==
5670 06:02:32.908872 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 06:02:32.914896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 06:02:32.915400 ==
5673 06:02:32.915819
5674 06:02:32.916187
5675 06:02:32.918124 TX Vref Scan disable
5676 06:02:32.918562 == TX Byte 0 ==
5677 06:02:32.921463 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5678 06:02:32.928074 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5679 06:02:32.928630 == TX Byte 1 ==
5680 06:02:32.931161 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5681 06:02:32.937865 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5682 06:02:32.938376 ==
5683 06:02:32.940942 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 06:02:32.944792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 06:02:32.945320 ==
5686 06:02:32.945726
5687 06:02:32.946035
5688 06:02:32.948136 TX Vref Scan disable
5689 06:02:32.951418 == TX Byte 0 ==
5690 06:02:32.954171 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5691 06:02:32.957916 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5692 06:02:32.960869 == TX Byte 1 ==
5693 06:02:32.963914 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5694 06:02:32.967430 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5695 06:02:32.967937
5696 06:02:32.971126 [DATLAT]
5697 06:02:32.971628 Freq=933, CH1 RK0
5698 06:02:32.972091
5699 06:02:32.974149 DATLAT Default: 0xd
5700 06:02:32.974572 0, 0xFFFF, sum = 0
5701 06:02:32.977846 1, 0xFFFF, sum = 0
5702 06:02:32.978368 2, 0xFFFF, sum = 0
5703 06:02:32.981226 3, 0xFFFF, sum = 0
5704 06:02:32.981804 4, 0xFFFF, sum = 0
5705 06:02:32.984130 5, 0xFFFF, sum = 0
5706 06:02:32.984647 6, 0xFFFF, sum = 0
5707 06:02:32.987247 7, 0xFFFF, sum = 0
5708 06:02:32.987800 8, 0xFFFF, sum = 0
5709 06:02:32.990845 9, 0xFFFF, sum = 0
5710 06:02:32.991258 10, 0x0, sum = 1
5711 06:02:32.994019 11, 0x0, sum = 2
5712 06:02:32.994538 12, 0x0, sum = 3
5713 06:02:32.997382 13, 0x0, sum = 4
5714 06:02:32.997956 best_step = 11
5715 06:02:32.998345
5716 06:02:32.998656 ==
5717 06:02:33.000721 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 06:02:33.007223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 06:02:33.007733 ==
5720 06:02:33.008063 RX Vref Scan: 1
5721 06:02:33.008363
5722 06:02:33.010577 RX Vref 0 -> 0, step: 1
5723 06:02:33.011119
5724 06:02:33.013913 RX Delay -61 -> 252, step: 4
5725 06:02:33.014420
5726 06:02:33.017039 Set Vref, RX VrefLevel [Byte0]: 58
5727 06:02:33.020307 [Byte1]: 50
5728 06:02:33.020719
5729 06:02:33.023810 Final RX Vref Byte 0 = 58 to rank0
5730 06:02:33.027076 Final RX Vref Byte 1 = 50 to rank0
5731 06:02:33.030262 Final RX Vref Byte 0 = 58 to rank1
5732 06:02:33.033459 Final RX Vref Byte 1 = 50 to rank1==
5733 06:02:33.037034 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 06:02:33.040204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 06:02:33.040722 ==
5736 06:02:33.043757 DQS Delay:
5737 06:02:33.044167 DQS0 = 0, DQS1 = 0
5738 06:02:33.046883 DQM Delay:
5739 06:02:33.047289 DQM0 = 95, DQM1 = 87
5740 06:02:33.047614 DQ Delay:
5741 06:02:33.050160 DQ0 =98, DQ1 =90, DQ2 =84, DQ3 =92
5742 06:02:33.053088 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =92
5743 06:02:33.057044 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =80
5744 06:02:33.059954 DQ12 =96, DQ13 =92, DQ14 =94, DQ15 =94
5745 06:02:33.060460
5746 06:02:33.060786
5747 06:02:33.069824 [DQSOSCAuto] RK0, (LSB)MR18= 0xfd06, (MSB)MR19= 0x405, tDQSOscB0 = 420 ps tDQSOscB1 = 423 ps
5748 06:02:33.073238 CH1 RK0: MR19=405, MR18=FD06
5749 06:02:33.080570 CH1_RK0: MR19=0x405, MR18=0xFD06, DQSOSC=420, MR23=63, INC=61, DEC=40
5750 06:02:33.081097
5751 06:02:33.083530 ----->DramcWriteLeveling(PI) begin...
5752 06:02:33.084040 ==
5753 06:02:33.086587 Dram Type= 6, Freq= 0, CH_1, rank 1
5754 06:02:33.089601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 06:02:33.090020 ==
5756 06:02:33.093338 Write leveling (Byte 0): 27 => 27
5757 06:02:33.096276 Write leveling (Byte 1): 27 => 27
5758 06:02:33.099758 DramcWriteLeveling(PI) end<-----
5759 06:02:33.100269
5760 06:02:33.100592 ==
5761 06:02:33.103287 Dram Type= 6, Freq= 0, CH_1, rank 1
5762 06:02:33.105949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 06:02:33.106378 ==
5764 06:02:33.109254 [Gating] SW mode calibration
5765 06:02:33.116017 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5766 06:02:33.123016 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5767 06:02:33.125750 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 06:02:33.129595 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 06:02:33.136223 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 06:02:33.139762 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5771 06:02:33.142207 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 06:02:33.149123 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 06:02:33.152631 0 14 24 | B1->B0 | 3232 2d2d | 1 0 | (1 1) (0 0)
5774 06:02:33.155867 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5775 06:02:33.162087 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5776 06:02:33.165468 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 06:02:33.168904 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 06:02:33.175454 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 06:02:33.178764 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 06:02:33.182157 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 06:02:33.188718 0 15 24 | B1->B0 | 2727 2f2f | 0 1 | (0 0) (0 0)
5782 06:02:33.192239 0 15 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5783 06:02:33.195648 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 06:02:33.201854 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 06:02:33.205130 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 06:02:33.208139 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 06:02:33.215026 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 06:02:33.218497 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 06:02:33.222378 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5790 06:02:33.228569 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5791 06:02:33.231758 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5792 06:02:33.235462 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 06:02:33.241669 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 06:02:33.245209 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 06:02:33.248311 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 06:02:33.255155 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 06:02:33.258235 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 06:02:33.261452 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 06:02:33.267765 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 06:02:33.271612 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 06:02:33.274657 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 06:02:33.281289 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 06:02:33.284767 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 06:02:33.288067 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5805 06:02:33.294282 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5806 06:02:33.297330 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5807 06:02:33.300682 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 06:02:33.304173 Total UI for P1: 0, mck2ui 16
5809 06:02:33.307433 best dqsien dly found for B0: ( 1, 2, 24)
5810 06:02:33.310845 Total UI for P1: 0, mck2ui 16
5811 06:02:33.314292 best dqsien dly found for B1: ( 1, 2, 30)
5812 06:02:33.317588 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5813 06:02:33.320607 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5814 06:02:33.321016
5815 06:02:33.327756 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5816 06:02:33.330692 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5817 06:02:33.334302 [Gating] SW calibration Done
5818 06:02:33.334809 ==
5819 06:02:33.337760 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 06:02:33.340870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 06:02:33.341382 ==
5822 06:02:33.341774 RX Vref Scan: 0
5823 06:02:33.342083
5824 06:02:33.344216 RX Vref 0 -> 0, step: 1
5825 06:02:33.344727
5826 06:02:33.346995 RX Delay -80 -> 252, step: 8
5827 06:02:33.350415 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5828 06:02:33.353624 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5829 06:02:33.360426 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5830 06:02:33.363786 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5831 06:02:33.367250 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5832 06:02:33.370544 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5833 06:02:33.373804 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5834 06:02:33.376972 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5835 06:02:33.383556 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5836 06:02:33.386397 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5837 06:02:33.389983 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5838 06:02:33.393468 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5839 06:02:33.396750 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5840 06:02:33.403113 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5841 06:02:33.406520 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5842 06:02:33.409640 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5843 06:02:33.410056 ==
5844 06:02:33.412949 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 06:02:33.416212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 06:02:33.416433 ==
5847 06:02:33.419500 DQS Delay:
5848 06:02:33.419775 DQS0 = 0, DQS1 = 0
5849 06:02:33.422805 DQM Delay:
5850 06:02:33.422981 DQM0 = 93, DQM1 = 89
5851 06:02:33.423121 DQ Delay:
5852 06:02:33.426570 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5853 06:02:33.429564 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5854 06:02:33.432947 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5855 06:02:33.436128 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5856 06:02:33.436365
5857 06:02:33.436484
5858 06:02:33.439470 ==
5859 06:02:33.442937 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 06:02:33.445800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 06:02:33.446004 ==
5862 06:02:33.446132
5863 06:02:33.446250
5864 06:02:33.449621 TX Vref Scan disable
5865 06:02:33.449851 == TX Byte 0 ==
5866 06:02:33.455889 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5867 06:02:33.459192 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5868 06:02:33.459475 == TX Byte 1 ==
5869 06:02:33.465791 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5870 06:02:33.468765 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5871 06:02:33.468999 ==
5872 06:02:33.472336 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 06:02:33.476039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 06:02:33.476520 ==
5875 06:02:33.476826
5876 06:02:33.477103
5877 06:02:33.479075 TX Vref Scan disable
5878 06:02:33.482585 == TX Byte 0 ==
5879 06:02:33.486011 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5880 06:02:33.489648 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5881 06:02:33.492532 == TX Byte 1 ==
5882 06:02:33.495759 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5883 06:02:33.499293 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5884 06:02:33.499802
5885 06:02:33.502583 [DATLAT]
5886 06:02:33.503123 Freq=933, CH1 RK1
5887 06:02:33.503460
5888 06:02:33.505366 DATLAT Default: 0xb
5889 06:02:33.505822 0, 0xFFFF, sum = 0
5890 06:02:33.509321 1, 0xFFFF, sum = 0
5891 06:02:33.509912 2, 0xFFFF, sum = 0
5892 06:02:33.512694 3, 0xFFFF, sum = 0
5893 06:02:33.513242 4, 0xFFFF, sum = 0
5894 06:02:33.515149 5, 0xFFFF, sum = 0
5895 06:02:33.515573 6, 0xFFFF, sum = 0
5896 06:02:33.518650 7, 0xFFFF, sum = 0
5897 06:02:33.519067 8, 0xFFFF, sum = 0
5898 06:02:33.522061 9, 0xFFFF, sum = 0
5899 06:02:33.522476 10, 0x0, sum = 1
5900 06:02:33.525468 11, 0x0, sum = 2
5901 06:02:33.525927 12, 0x0, sum = 3
5902 06:02:33.528799 13, 0x0, sum = 4
5903 06:02:33.529320 best_step = 11
5904 06:02:33.529717
5905 06:02:33.530087 ==
5906 06:02:33.532115 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 06:02:33.538503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 06:02:33.538948 ==
5909 06:02:33.539284 RX Vref Scan: 0
5910 06:02:33.539614
5911 06:02:33.542055 RX Vref 0 -> 0, step: 1
5912 06:02:33.542472
5913 06:02:33.545270 RX Delay -61 -> 252, step: 4
5914 06:02:33.548154 iDelay=203, Bit 0, Center 98 (3 ~ 194) 192
5915 06:02:33.554874 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5916 06:02:33.558185 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5917 06:02:33.561588 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5918 06:02:33.565059 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5919 06:02:33.568478 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5920 06:02:33.571253 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5921 06:02:33.577992 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5922 06:02:33.581029 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5923 06:02:33.584780 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5924 06:02:33.587901 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5925 06:02:33.590812 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5926 06:02:33.598222 iDelay=203, Bit 12, Center 94 (-1 ~ 190) 192
5927 06:02:33.601113 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5928 06:02:33.604364 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5929 06:02:33.607883 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5930 06:02:33.608298 ==
5931 06:02:33.610847 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 06:02:33.614046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 06:02:33.617337 ==
5934 06:02:33.617786 DQS Delay:
5935 06:02:33.618119 DQS0 = 0, DQS1 = 0
5936 06:02:33.620995 DQM Delay:
5937 06:02:33.621422 DQM0 = 93, DQM1 = 89
5938 06:02:33.624378 DQ Delay:
5939 06:02:33.627771 DQ0 =98, DQ1 =88, DQ2 =84, DQ3 =90
5940 06:02:33.630938 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =90
5941 06:02:33.634077 DQ8 =78, DQ9 =80, DQ10 =92, DQ11 =84
5942 06:02:33.637331 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =94
5943 06:02:33.637805
5944 06:02:33.638165
5945 06:02:33.643873 [DQSOSCAuto] RK1, (LSB)MR18= 0x1124, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5946 06:02:33.646959 CH1 RK1: MR19=505, MR18=1124
5947 06:02:33.653940 CH1_RK1: MR19=0x505, MR18=0x1124, DQSOSC=410, MR23=63, INC=64, DEC=42
5948 06:02:33.657583 [RxdqsGatingPostProcess] freq 933
5949 06:02:33.660468 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5950 06:02:33.663706 best DQS0 dly(2T, 0.5T) = (0, 10)
5951 06:02:33.666996 best DQS1 dly(2T, 0.5T) = (0, 10)
5952 06:02:33.670334 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5953 06:02:33.673993 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5954 06:02:33.676748 best DQS0 dly(2T, 0.5T) = (0, 10)
5955 06:02:33.680280 best DQS1 dly(2T, 0.5T) = (0, 10)
5956 06:02:33.683168 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5957 06:02:33.686666 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5958 06:02:33.690276 Pre-setting of DQS Precalculation
5959 06:02:33.693364 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5960 06:02:33.703469 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5961 06:02:33.709859 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5962 06:02:33.710277
5963 06:02:33.710603
5964 06:02:33.713305 [Calibration Summary] 1866 Mbps
5965 06:02:33.713764 CH 0, Rank 0
5966 06:02:33.716583 SW Impedance : PASS
5967 06:02:33.717127 DUTY Scan : NO K
5968 06:02:33.719859 ZQ Calibration : PASS
5969 06:02:33.723277 Jitter Meter : NO K
5970 06:02:33.723768 CBT Training : PASS
5971 06:02:33.726135 Write leveling : PASS
5972 06:02:33.729776 RX DQS gating : PASS
5973 06:02:33.730307 RX DQ/DQS(RDDQC) : PASS
5974 06:02:33.733124 TX DQ/DQS : PASS
5975 06:02:33.736589 RX DATLAT : PASS
5976 06:02:33.737099 RX DQ/DQS(Engine): PASS
5977 06:02:33.739904 TX OE : NO K
5978 06:02:33.740433 All Pass.
5979 06:02:33.740781
5980 06:02:33.742751 CH 0, Rank 1
5981 06:02:33.743174 SW Impedance : PASS
5982 06:02:33.746223 DUTY Scan : NO K
5983 06:02:33.749579 ZQ Calibration : PASS
5984 06:02:33.749987 Jitter Meter : NO K
5985 06:02:33.752640 CBT Training : PASS
5986 06:02:33.756367 Write leveling : PASS
5987 06:02:33.756869 RX DQS gating : PASS
5988 06:02:33.759450 RX DQ/DQS(RDDQC) : PASS
5989 06:02:33.762782 TX DQ/DQS : PASS
5990 06:02:33.763195 RX DATLAT : PASS
5991 06:02:33.766320 RX DQ/DQS(Engine): PASS
5992 06:02:33.766741 TX OE : NO K
5993 06:02:33.769552 All Pass.
5994 06:02:33.770063
5995 06:02:33.770390 CH 1, Rank 0
5996 06:02:33.772947 SW Impedance : PASS
5997 06:02:33.773578 DUTY Scan : NO K
5998 06:02:33.776286 ZQ Calibration : PASS
5999 06:02:33.779394 Jitter Meter : NO K
6000 06:02:33.780038 CBT Training : PASS
6001 06:02:33.782690 Write leveling : PASS
6002 06:02:33.786376 RX DQS gating : PASS
6003 06:02:33.786882 RX DQ/DQS(RDDQC) : PASS
6004 06:02:33.789468 TX DQ/DQS : PASS
6005 06:02:33.792347 RX DATLAT : PASS
6006 06:02:33.792763 RX DQ/DQS(Engine): PASS
6007 06:02:33.796172 TX OE : NO K
6008 06:02:33.796677 All Pass.
6009 06:02:33.797006
6010 06:02:33.799561 CH 1, Rank 1
6011 06:02:33.800079 SW Impedance : PASS
6012 06:02:33.802439 DUTY Scan : NO K
6013 06:02:33.806007 ZQ Calibration : PASS
6014 06:02:33.806588 Jitter Meter : NO K
6015 06:02:33.808880 CBT Training : PASS
6016 06:02:33.812780 Write leveling : PASS
6017 06:02:33.813312 RX DQS gating : PASS
6018 06:02:33.815309 RX DQ/DQS(RDDQC) : PASS
6019 06:02:33.818934 TX DQ/DQS : PASS
6020 06:02:33.819346 RX DATLAT : PASS
6021 06:02:33.821752 RX DQ/DQS(Engine): PASS
6022 06:02:33.825627 TX OE : NO K
6023 06:02:33.826138 All Pass.
6024 06:02:33.826468
6025 06:02:33.826772 DramC Write-DBI off
6026 06:02:33.828501 PER_BANK_REFRESH: Hybrid Mode
6027 06:02:33.832469 TX_TRACKING: ON
6028 06:02:33.838276 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6029 06:02:33.845267 [FAST_K] Save calibration result to emmc
6030 06:02:33.848672 dramc_set_vcore_voltage set vcore to 650000
6031 06:02:33.849172 Read voltage for 400, 6
6032 06:02:33.851530 Vio18 = 0
6033 06:02:33.851940 Vcore = 650000
6034 06:02:33.852260 Vdram = 0
6035 06:02:33.855014 Vddq = 0
6036 06:02:33.855515 Vmddr = 0
6037 06:02:33.858536 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6038 06:02:33.865558 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6039 06:02:33.868464 MEM_TYPE=3, freq_sel=20
6040 06:02:33.871544 sv_algorithm_assistance_LP4_800
6041 06:02:33.875129 ============ PULL DRAM RESETB DOWN ============
6042 06:02:33.877996 ========== PULL DRAM RESETB DOWN end =========
6043 06:02:33.885221 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6044 06:02:33.888077 ===================================
6045 06:02:33.888588 LPDDR4 DRAM CONFIGURATION
6046 06:02:33.891382 ===================================
6047 06:02:33.894637 EX_ROW_EN[0] = 0x0
6048 06:02:33.895046 EX_ROW_EN[1] = 0x0
6049 06:02:33.897833 LP4Y_EN = 0x0
6050 06:02:33.898241 WORK_FSP = 0x0
6051 06:02:33.901182 WL = 0x2
6052 06:02:33.901723 RL = 0x2
6053 06:02:33.904582 BL = 0x2
6054 06:02:33.904997 RPST = 0x0
6055 06:02:33.908183 RD_PRE = 0x0
6056 06:02:33.911779 WR_PRE = 0x1
6057 06:02:33.912302 WR_PST = 0x0
6058 06:02:33.914565 DBI_WR = 0x0
6059 06:02:33.914983 DBI_RD = 0x0
6060 06:02:33.917909 OTF = 0x1
6061 06:02:33.921325 ===================================
6062 06:02:33.924647 ===================================
6063 06:02:33.925066 ANA top config
6064 06:02:33.927626 ===================================
6065 06:02:33.931086 DLL_ASYNC_EN = 0
6066 06:02:33.934476 ALL_SLAVE_EN = 1
6067 06:02:33.934894 NEW_RANK_MODE = 1
6068 06:02:33.937957 DLL_IDLE_MODE = 1
6069 06:02:33.941283 LP45_APHY_COMB_EN = 1
6070 06:02:33.944711 TX_ODT_DIS = 1
6071 06:02:33.945131 NEW_8X_MODE = 1
6072 06:02:33.947910 ===================================
6073 06:02:33.951086 ===================================
6074 06:02:33.954421 data_rate = 800
6075 06:02:33.957195 CKR = 1
6076 06:02:33.960763 DQ_P2S_RATIO = 4
6077 06:02:33.964369 ===================================
6078 06:02:33.967412 CA_P2S_RATIO = 4
6079 06:02:33.970751 DQ_CA_OPEN = 0
6080 06:02:33.973888 DQ_SEMI_OPEN = 1
6081 06:02:33.974113 CA_SEMI_OPEN = 1
6082 06:02:33.977242 CA_FULL_RATE = 0
6083 06:02:33.980771 DQ_CKDIV4_EN = 0
6084 06:02:33.983821 CA_CKDIV4_EN = 1
6085 06:02:33.986944 CA_PREDIV_EN = 0
6086 06:02:33.990433 PH8_DLY = 0
6087 06:02:33.990614 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6088 06:02:33.993865 DQ_AAMCK_DIV = 0
6089 06:02:33.997363 CA_AAMCK_DIV = 0
6090 06:02:34.001034 CA_ADMCK_DIV = 4
6091 06:02:34.004113 DQ_TRACK_CA_EN = 0
6092 06:02:34.007241 CA_PICK = 800
6093 06:02:34.007663 CA_MCKIO = 400
6094 06:02:34.010657 MCKIO_SEMI = 400
6095 06:02:34.014048 PLL_FREQ = 3016
6096 06:02:34.017642 DQ_UI_PI_RATIO = 32
6097 06:02:34.020506 CA_UI_PI_RATIO = 32
6098 06:02:34.024032 ===================================
6099 06:02:34.027616 ===================================
6100 06:02:34.030400 memory_type:LPDDR4
6101 06:02:34.030920 GP_NUM : 10
6102 06:02:34.033536 SRAM_EN : 1
6103 06:02:34.037298 MD32_EN : 0
6104 06:02:34.040924 ===================================
6105 06:02:34.041441 [ANA_INIT] >>>>>>>>>>>>>>
6106 06:02:34.043550 <<<<<< [CONFIGURE PHASE]: ANA_TX
6107 06:02:34.046726 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6108 06:02:34.050398 ===================================
6109 06:02:34.053806 data_rate = 800,PCW = 0X7400
6110 06:02:34.057343 ===================================
6111 06:02:34.060447 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6112 06:02:34.066842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6113 06:02:34.076720 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6114 06:02:34.080135 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6115 06:02:34.086878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6116 06:02:34.090238 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6117 06:02:34.090784 [ANA_INIT] flow start
6118 06:02:34.093517 [ANA_INIT] PLL >>>>>>>>
6119 06:02:34.096716 [ANA_INIT] PLL <<<<<<<<
6120 06:02:34.097248 [ANA_INIT] MIDPI >>>>>>>>
6121 06:02:34.100649 [ANA_INIT] MIDPI <<<<<<<<
6122 06:02:34.103324 [ANA_INIT] DLL >>>>>>>>
6123 06:02:34.103842 [ANA_INIT] flow end
6124 06:02:34.110203 ============ LP4 DIFF to SE enter ============
6125 06:02:34.113263 ============ LP4 DIFF to SE exit ============
6126 06:02:34.113733 [ANA_INIT] <<<<<<<<<<<<<
6127 06:02:34.116586 [Flow] Enable top DCM control >>>>>
6128 06:02:34.119719 [Flow] Enable top DCM control <<<<<
6129 06:02:34.122848 Enable DLL master slave shuffle
6130 06:02:34.129969 ==============================================================
6131 06:02:34.133139 Gating Mode config
6132 06:02:34.136422 ==============================================================
6133 06:02:34.140168 Config description:
6134 06:02:34.149779 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6135 06:02:34.156640 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6136 06:02:34.159544 SELPH_MODE 0: By rank 1: By Phase
6137 06:02:34.166113 ==============================================================
6138 06:02:34.169413 GAT_TRACK_EN = 0
6139 06:02:34.173324 RX_GATING_MODE = 2
6140 06:02:34.176191 RX_GATING_TRACK_MODE = 2
6141 06:02:34.176617 SELPH_MODE = 1
6142 06:02:34.179785 PICG_EARLY_EN = 1
6143 06:02:34.182360 VALID_LAT_VALUE = 1
6144 06:02:34.189586 ==============================================================
6145 06:02:34.192260 Enter into Gating configuration >>>>
6146 06:02:34.195660 Exit from Gating configuration <<<<
6147 06:02:34.199017 Enter into DVFS_PRE_config >>>>>
6148 06:02:34.209023 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6149 06:02:34.212105 Exit from DVFS_PRE_config <<<<<
6150 06:02:34.215427 Enter into PICG configuration >>>>
6151 06:02:34.218962 Exit from PICG configuration <<<<
6152 06:02:34.221976 [RX_INPUT] configuration >>>>>
6153 06:02:34.225818 [RX_INPUT] configuration <<<<<
6154 06:02:34.228505 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6155 06:02:34.235586 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6156 06:02:34.242257 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6157 06:02:34.249005 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6158 06:02:34.255592 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6159 06:02:34.262186 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6160 06:02:34.265393 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6161 06:02:34.269040 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6162 06:02:34.271918 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6163 06:02:34.275137 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6164 06:02:34.281828 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6165 06:02:34.285240 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6166 06:02:34.289055 ===================================
6167 06:02:34.291971 LPDDR4 DRAM CONFIGURATION
6168 06:02:34.295346 ===================================
6169 06:02:34.295760 EX_ROW_EN[0] = 0x0
6170 06:02:34.298032 EX_ROW_EN[1] = 0x0
6171 06:02:34.298441 LP4Y_EN = 0x0
6172 06:02:34.301550 WORK_FSP = 0x0
6173 06:02:34.301983 WL = 0x2
6174 06:02:34.304850 RL = 0x2
6175 06:02:34.308488 BL = 0x2
6176 06:02:34.309000 RPST = 0x0
6177 06:02:34.311853 RD_PRE = 0x0
6178 06:02:34.312413 WR_PRE = 0x1
6179 06:02:34.314699 WR_PST = 0x0
6180 06:02:34.315168 DBI_WR = 0x0
6181 06:02:34.318179 DBI_RD = 0x0
6182 06:02:34.318735 OTF = 0x1
6183 06:02:34.321558 ===================================
6184 06:02:34.324776 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6185 06:02:34.331615 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6186 06:02:34.335046 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6187 06:02:34.338086 ===================================
6188 06:02:34.341643 LPDDR4 DRAM CONFIGURATION
6189 06:02:34.344775 ===================================
6190 06:02:34.345186 EX_ROW_EN[0] = 0x10
6191 06:02:34.348223 EX_ROW_EN[1] = 0x0
6192 06:02:34.348746 LP4Y_EN = 0x0
6193 06:02:34.351439 WORK_FSP = 0x0
6194 06:02:34.352020 WL = 0x2
6195 06:02:34.354303 RL = 0x2
6196 06:02:34.358155 BL = 0x2
6197 06:02:34.358668 RPST = 0x0
6198 06:02:34.361297 RD_PRE = 0x0
6199 06:02:34.361860 WR_PRE = 0x1
6200 06:02:34.364995 WR_PST = 0x0
6201 06:02:34.365557 DBI_WR = 0x0
6202 06:02:34.367662 DBI_RD = 0x0
6203 06:02:34.368073 OTF = 0x1
6204 06:02:34.371114 ===================================
6205 06:02:34.377831 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6206 06:02:34.381605 nWR fixed to 30
6207 06:02:34.385340 [ModeRegInit_LP4] CH0 RK0
6208 06:02:34.385906 [ModeRegInit_LP4] CH0 RK1
6209 06:02:34.388043 [ModeRegInit_LP4] CH1 RK0
6210 06:02:34.391674 [ModeRegInit_LP4] CH1 RK1
6211 06:02:34.392196 match AC timing 19
6212 06:02:34.398425 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6213 06:02:34.402153 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6214 06:02:34.405025 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6215 06:02:34.411742 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6216 06:02:34.415267 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6217 06:02:34.415776 ==
6218 06:02:34.417899 Dram Type= 6, Freq= 0, CH_0, rank 0
6219 06:02:34.421241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6220 06:02:34.421711 ==
6221 06:02:34.428422 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6222 06:02:34.434456 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6223 06:02:34.438076 [CA 0] Center 36 (8~64) winsize 57
6224 06:02:34.441333 [CA 1] Center 36 (8~64) winsize 57
6225 06:02:34.444359 [CA 2] Center 36 (8~64) winsize 57
6226 06:02:34.448015 [CA 3] Center 36 (8~64) winsize 57
6227 06:02:34.451282 [CA 4] Center 36 (8~64) winsize 57
6228 06:02:34.451952 [CA 5] Center 36 (8~64) winsize 57
6229 06:02:34.454553
6230 06:02:34.457820 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6231 06:02:34.458349
6232 06:02:34.460863 [CATrainingPosCal] consider 1 rank data
6233 06:02:34.464485 u2DelayCellTimex100 = 270/100 ps
6234 06:02:34.467461 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 06:02:34.470409 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 06:02:34.474098 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 06:02:34.477577 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 06:02:34.480824 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 06:02:34.484256 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 06:02:34.484841
6241 06:02:34.487579 CA PerBit enable=1, Macro0, CA PI delay=36
6242 06:02:34.488121
6243 06:02:34.490754 [CBTSetCACLKResult] CA Dly = 36
6244 06:02:34.494331 CS Dly: 1 (0~32)
6245 06:02:34.494939 ==
6246 06:02:34.497190 Dram Type= 6, Freq= 0, CH_0, rank 1
6247 06:02:34.500847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 06:02:34.501368 ==
6249 06:02:34.507220 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6250 06:02:34.513877 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6251 06:02:34.517443 [CA 0] Center 36 (8~64) winsize 57
6252 06:02:34.520162 [CA 1] Center 36 (8~64) winsize 57
6253 06:02:34.520580 [CA 2] Center 36 (8~64) winsize 57
6254 06:02:34.523504 [CA 3] Center 36 (8~64) winsize 57
6255 06:02:34.526865 [CA 4] Center 36 (8~64) winsize 57
6256 06:02:34.530366 [CA 5] Center 36 (8~64) winsize 57
6257 06:02:34.530885
6258 06:02:34.534089 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6259 06:02:34.537035
6260 06:02:34.540627 [CATrainingPosCal] consider 2 rank data
6261 06:02:34.541146 u2DelayCellTimex100 = 270/100 ps
6262 06:02:34.547173 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 06:02:34.550197 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 06:02:34.553886 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 06:02:34.556820 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 06:02:34.560194 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 06:02:34.563532 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 06:02:34.564206
6269 06:02:34.566426 CA PerBit enable=1, Macro0, CA PI delay=36
6270 06:02:34.566839
6271 06:02:34.570340 [CBTSetCACLKResult] CA Dly = 36
6272 06:02:34.573869 CS Dly: 1 (0~32)
6273 06:02:34.574391
6274 06:02:34.576695 ----->DramcWriteLeveling(PI) begin...
6275 06:02:34.577127 ==
6276 06:02:34.580280 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 06:02:34.583064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 06:02:34.583483 ==
6279 06:02:34.586474 Write leveling (Byte 0): 40 => 8
6280 06:02:34.590019 Write leveling (Byte 1): 40 => 8
6281 06:02:34.593286 DramcWriteLeveling(PI) end<-----
6282 06:02:34.593864
6283 06:02:34.594202 ==
6284 06:02:34.596396 Dram Type= 6, Freq= 0, CH_0, rank 0
6285 06:02:34.600154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 06:02:34.600673 ==
6287 06:02:34.603513 [Gating] SW mode calibration
6288 06:02:34.609816 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6289 06:02:34.616510 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6290 06:02:34.619559 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6291 06:02:34.622769 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6292 06:02:34.629445 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6293 06:02:34.632770 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6294 06:02:34.636046 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6295 06:02:34.642440 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6296 06:02:34.645991 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 06:02:34.649464 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 06:02:34.656038 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 06:02:34.656552 Total UI for P1: 0, mck2ui 16
6300 06:02:34.662810 best dqsien dly found for B0: ( 0, 14, 24)
6301 06:02:34.663221 Total UI for P1: 0, mck2ui 16
6302 06:02:34.669046 best dqsien dly found for B1: ( 0, 14, 24)
6303 06:02:34.672753 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6304 06:02:34.675828 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6305 06:02:34.676241
6306 06:02:34.679702 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6307 06:02:34.682321 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6308 06:02:34.685581 [Gating] SW calibration Done
6309 06:02:34.685992 ==
6310 06:02:34.688822 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 06:02:34.692554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 06:02:34.693065 ==
6313 06:02:34.695681 RX Vref Scan: 0
6314 06:02:34.696091
6315 06:02:34.699023 RX Vref 0 -> 0, step: 1
6316 06:02:34.699429
6317 06:02:34.699746 RX Delay -410 -> 252, step: 16
6318 06:02:34.705062 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6319 06:02:34.708645 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6320 06:02:34.712095 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6321 06:02:34.715699 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6322 06:02:34.721963 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6323 06:02:34.725750 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6324 06:02:34.729205 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6325 06:02:34.732491 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6326 06:02:34.738405 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6327 06:02:34.741648 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6328 06:02:34.745510 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6329 06:02:34.751908 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6330 06:02:34.755185 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6331 06:02:34.758710 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6332 06:02:34.761415 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6333 06:02:34.768499 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6334 06:02:34.769007 ==
6335 06:02:34.771903 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 06:02:34.774981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 06:02:34.775555 ==
6338 06:02:34.775904 DQS Delay:
6339 06:02:34.777864 DQS0 = 59, DQS1 = 59
6340 06:02:34.778286 DQM Delay:
6341 06:02:34.782014 DQM0 = 19, DQM1 = 10
6342 06:02:34.782522 DQ Delay:
6343 06:02:34.784679 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6344 06:02:34.788573 DQ4 =24, DQ5 =0, DQ6 =32, DQ7 =32
6345 06:02:34.792004 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6346 06:02:34.794607 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6347 06:02:34.795036
6348 06:02:34.795356
6349 06:02:34.795651 ==
6350 06:02:34.798061 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 06:02:34.801629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 06:02:34.802137 ==
6353 06:02:34.802463
6354 06:02:34.804714
6355 06:02:34.805162 TX Vref Scan disable
6356 06:02:34.808053 == TX Byte 0 ==
6357 06:02:34.811384 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6358 06:02:34.814615 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6359 06:02:34.817852 == TX Byte 1 ==
6360 06:02:34.821691 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 06:02:34.825052 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 06:02:34.825816 ==
6363 06:02:34.828257 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 06:02:34.831462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 06:02:34.831970 ==
6366 06:02:34.834435
6367 06:02:34.834838
6368 06:02:34.835160 TX Vref Scan disable
6369 06:02:34.838053 == TX Byte 0 ==
6370 06:02:34.841016 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6371 06:02:34.844353 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6372 06:02:34.847830 == TX Byte 1 ==
6373 06:02:34.850687 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6374 06:02:34.854376 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6375 06:02:34.854783
6376 06:02:34.855102 [DATLAT]
6377 06:02:34.857776 Freq=400, CH0 RK0
6378 06:02:34.858183
6379 06:02:34.860915 DATLAT Default: 0xf
6380 06:02:34.861416 0, 0xFFFF, sum = 0
6381 06:02:34.864486 1, 0xFFFF, sum = 0
6382 06:02:34.864994 2, 0xFFFF, sum = 0
6383 06:02:34.867667 3, 0xFFFF, sum = 0
6384 06:02:34.868077 4, 0xFFFF, sum = 0
6385 06:02:34.871077 5, 0xFFFF, sum = 0
6386 06:02:34.871490 6, 0xFFFF, sum = 0
6387 06:02:34.874384 7, 0xFFFF, sum = 0
6388 06:02:34.874899 8, 0xFFFF, sum = 0
6389 06:02:34.877661 9, 0xFFFF, sum = 0
6390 06:02:34.878220 10, 0xFFFF, sum = 0
6391 06:02:34.880864 11, 0xFFFF, sum = 0
6392 06:02:34.881373 12, 0xFFFF, sum = 0
6393 06:02:34.883998 13, 0x0, sum = 1
6394 06:02:34.884405 14, 0x0, sum = 2
6395 06:02:34.887727 15, 0x0, sum = 3
6396 06:02:34.888240 16, 0x0, sum = 4
6397 06:02:34.890844 best_step = 14
6398 06:02:34.891350
6399 06:02:34.891713 ==
6400 06:02:34.894050 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 06:02:34.897218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 06:02:34.897677 ==
6403 06:02:34.900435 RX Vref Scan: 1
6404 06:02:34.901071
6405 06:02:34.901412 RX Vref 0 -> 0, step: 1
6406 06:02:34.901778
6407 06:02:34.903623 RX Delay -359 -> 252, step: 8
6408 06:02:34.904028
6409 06:02:34.907157 Set Vref, RX VrefLevel [Byte0]: 59
6410 06:02:34.910522 [Byte1]: 54
6411 06:02:34.915790
6412 06:02:34.916286 Final RX Vref Byte 0 = 59 to rank0
6413 06:02:34.918714 Final RX Vref Byte 1 = 54 to rank0
6414 06:02:34.922320 Final RX Vref Byte 0 = 59 to rank1
6415 06:02:34.925389 Final RX Vref Byte 1 = 54 to rank1==
6416 06:02:34.928640 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 06:02:34.935298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 06:02:34.935869 ==
6419 06:02:34.936206 DQS Delay:
6420 06:02:34.938587 DQS0 = 60, DQS1 = 68
6421 06:02:34.938989 DQM Delay:
6422 06:02:34.939308 DQM0 = 15, DQM1 = 13
6423 06:02:34.941868 DQ Delay:
6424 06:02:34.945730 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6425 06:02:34.949095 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6426 06:02:34.949523 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6427 06:02:34.951598 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6428 06:02:34.955421
6429 06:02:34.955827
6430 06:02:34.962111 [DQSOSCAuto] RK0, (LSB)MR18= 0x8482, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6431 06:02:34.964684 CH0 RK0: MR19=C0C, MR18=8482
6432 06:02:34.971738 CH0_RK0: MR19=0xC0C, MR18=0x8482, DQSOSC=393, MR23=63, INC=382, DEC=254
6433 06:02:34.972258 ==
6434 06:02:34.975272 Dram Type= 6, Freq= 0, CH_0, rank 1
6435 06:02:34.978440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 06:02:34.978855 ==
6437 06:02:34.982043 [Gating] SW mode calibration
6438 06:02:34.988978 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6439 06:02:34.995021 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6440 06:02:34.998305 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6441 06:02:35.001563 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6442 06:02:35.007897 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 06:02:35.011318 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6444 06:02:35.014879 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 06:02:35.021258 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 06:02:35.024992 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 06:02:35.027942 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 06:02:35.034294 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 06:02:35.034742 Total UI for P1: 0, mck2ui 16
6450 06:02:35.040989 best dqsien dly found for B0: ( 0, 14, 24)
6451 06:02:35.041459 Total UI for P1: 0, mck2ui 16
6452 06:02:35.047882 best dqsien dly found for B1: ( 0, 14, 24)
6453 06:02:35.051391 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6454 06:02:35.054339 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6455 06:02:35.054749
6456 06:02:35.057854 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6457 06:02:35.061315 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6458 06:02:35.064485 [Gating] SW calibration Done
6459 06:02:35.065024 ==
6460 06:02:35.067422 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 06:02:35.071003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 06:02:35.071416 ==
6463 06:02:35.074885 RX Vref Scan: 0
6464 06:02:35.075394
6465 06:02:35.075725 RX Vref 0 -> 0, step: 1
6466 06:02:35.076032
6467 06:02:35.077513 RX Delay -410 -> 252, step: 16
6468 06:02:35.084510 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6469 06:02:35.087666 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6470 06:02:35.091278 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6471 06:02:35.093981 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6472 06:02:35.100875 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6473 06:02:35.104256 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6474 06:02:35.107836 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6475 06:02:35.110543 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6476 06:02:35.117751 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6477 06:02:35.121073 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6478 06:02:35.123881 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6479 06:02:35.127232 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6480 06:02:35.133707 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6481 06:02:35.137469 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6482 06:02:35.140302 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6483 06:02:35.143566 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6484 06:02:35.147137 ==
6485 06:02:35.150418 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 06:02:35.154208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 06:02:35.154620 ==
6488 06:02:35.154944 DQS Delay:
6489 06:02:35.157005 DQS0 = 59, DQS1 = 59
6490 06:02:35.157412 DQM Delay:
6491 06:02:35.160854 DQM0 = 17, DQM1 = 10
6492 06:02:35.161361 DQ Delay:
6493 06:02:35.163578 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6494 06:02:35.167125 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6495 06:02:35.170449 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6496 06:02:35.173923 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6497 06:02:35.174333
6498 06:02:35.174658
6499 06:02:35.174961 ==
6500 06:02:35.177282 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 06:02:35.180159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 06:02:35.180568 ==
6503 06:02:35.180891
6504 06:02:35.181188
6505 06:02:35.183948 TX Vref Scan disable
6506 06:02:35.184476 == TX Byte 0 ==
6507 06:02:35.190446 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6508 06:02:35.193629 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6509 06:02:35.194145 == TX Byte 1 ==
6510 06:02:35.200107 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6511 06:02:35.203379 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6512 06:02:35.203991 ==
6513 06:02:35.206678 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 06:02:35.210194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 06:02:35.210796 ==
6516 06:02:35.211270
6517 06:02:35.211738
6518 06:02:35.213629 TX Vref Scan disable
6519 06:02:35.214110 == TX Byte 0 ==
6520 06:02:35.219923 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6521 06:02:35.223485 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6522 06:02:35.223706 == TX Byte 1 ==
6523 06:02:35.230052 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6524 06:02:35.232914 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6525 06:02:35.233090
6526 06:02:35.233230 [DATLAT]
6527 06:02:35.236860 Freq=400, CH0 RK1
6528 06:02:35.237035
6529 06:02:35.237175 DATLAT Default: 0xe
6530 06:02:35.239613 0, 0xFFFF, sum = 0
6531 06:02:35.239808 1, 0xFFFF, sum = 0
6532 06:02:35.243759 2, 0xFFFF, sum = 0
6533 06:02:35.244031 3, 0xFFFF, sum = 0
6534 06:02:35.246276 4, 0xFFFF, sum = 0
6535 06:02:35.246476 5, 0xFFFF, sum = 0
6536 06:02:35.250115 6, 0xFFFF, sum = 0
6537 06:02:35.253679 7, 0xFFFF, sum = 0
6538 06:02:35.253978 8, 0xFFFF, sum = 0
6539 06:02:35.256427 9, 0xFFFF, sum = 0
6540 06:02:35.256640 10, 0xFFFF, sum = 0
6541 06:02:35.260270 11, 0xFFFF, sum = 0
6542 06:02:35.260614 12, 0xFFFF, sum = 0
6543 06:02:35.263297 13, 0x0, sum = 1
6544 06:02:35.263717 14, 0x0, sum = 2
6545 06:02:35.266638 15, 0x0, sum = 3
6546 06:02:35.267062 16, 0x0, sum = 4
6547 06:02:35.267328 best_step = 14
6548 06:02:35.270083
6549 06:02:35.270590 ==
6550 06:02:35.273308 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 06:02:35.276700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 06:02:35.277226 ==
6553 06:02:35.277662 RX Vref Scan: 0
6554 06:02:35.277975
6555 06:02:35.279827 RX Vref 0 -> 0, step: 1
6556 06:02:35.280235
6557 06:02:35.283261 RX Delay -359 -> 252, step: 8
6558 06:02:35.290377 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6559 06:02:35.294085 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6560 06:02:35.297078 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6561 06:02:35.299936 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6562 06:02:35.306874 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6563 06:02:35.310021 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6564 06:02:35.313540 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6565 06:02:35.316652 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6566 06:02:35.323302 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6567 06:02:35.326425 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6568 06:02:35.329923 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6569 06:02:35.336337 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6570 06:02:35.339977 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6571 06:02:35.343427 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6572 06:02:35.346192 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6573 06:02:35.353177 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6574 06:02:35.353732 ==
6575 06:02:35.356276 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 06:02:35.359553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 06:02:35.359983 ==
6578 06:02:35.360316 DQS Delay:
6579 06:02:35.363017 DQS0 = 60, DQS1 = 72
6580 06:02:35.363523 DQM Delay:
6581 06:02:35.366354 DQM0 = 11, DQM1 = 18
6582 06:02:35.366762 DQ Delay:
6583 06:02:35.370167 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6584 06:02:35.372799 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6585 06:02:35.376543 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6586 06:02:35.379758 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6587 06:02:35.380169
6588 06:02:35.380492
6589 06:02:35.386155 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6590 06:02:35.389409 CH0 RK1: MR19=C0C, MR18=BE73
6591 06:02:35.396140 CH0_RK1: MR19=0xC0C, MR18=0xBE73, DQSOSC=386, MR23=63, INC=396, DEC=264
6592 06:02:35.399699 [RxdqsGatingPostProcess] freq 400
6593 06:02:35.406263 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6594 06:02:35.409520 best DQS0 dly(2T, 0.5T) = (0, 10)
6595 06:02:35.412667 best DQS1 dly(2T, 0.5T) = (0, 10)
6596 06:02:35.416090 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6597 06:02:35.416503 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6598 06:02:35.419111 best DQS0 dly(2T, 0.5T) = (0, 10)
6599 06:02:35.422859 best DQS1 dly(2T, 0.5T) = (0, 10)
6600 06:02:35.425971 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6601 06:02:35.429254 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6602 06:02:35.432766 Pre-setting of DQS Precalculation
6603 06:02:35.438967 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6604 06:02:35.439401 ==
6605 06:02:35.442490 Dram Type= 6, Freq= 0, CH_1, rank 0
6606 06:02:35.445960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 06:02:35.446452 ==
6608 06:02:35.452102 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6609 06:02:35.459144 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6610 06:02:35.459562 [CA 0] Center 36 (8~64) winsize 57
6611 06:02:35.462182 [CA 1] Center 36 (8~64) winsize 57
6612 06:02:35.465942 [CA 2] Center 36 (8~64) winsize 57
6613 06:02:35.468929 [CA 3] Center 36 (8~64) winsize 57
6614 06:02:35.472185 [CA 4] Center 36 (8~64) winsize 57
6615 06:02:35.475554 [CA 5] Center 36 (8~64) winsize 57
6616 06:02:35.475971
6617 06:02:35.479031 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6618 06:02:35.479446
6619 06:02:35.482333 [CATrainingPosCal] consider 1 rank data
6620 06:02:35.485396 u2DelayCellTimex100 = 270/100 ps
6621 06:02:35.489127 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 06:02:35.492431 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 06:02:35.498617 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 06:02:35.502292 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 06:02:35.505651 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 06:02:35.508578 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 06:02:35.508995
6628 06:02:35.512105 CA PerBit enable=1, Macro0, CA PI delay=36
6629 06:02:35.512524
6630 06:02:35.515610 [CBTSetCACLKResult] CA Dly = 36
6631 06:02:35.516029 CS Dly: 1 (0~32)
6632 06:02:35.518392 ==
6633 06:02:35.518810 Dram Type= 6, Freq= 0, CH_1, rank 1
6634 06:02:35.525286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 06:02:35.525786 ==
6636 06:02:35.528883 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6637 06:02:35.535519 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6638 06:02:35.538995 [CA 0] Center 36 (8~64) winsize 57
6639 06:02:35.541894 [CA 1] Center 36 (8~64) winsize 57
6640 06:02:35.545448 [CA 2] Center 36 (8~64) winsize 57
6641 06:02:35.548884 [CA 3] Center 36 (8~64) winsize 57
6642 06:02:35.551781 [CA 4] Center 36 (8~64) winsize 57
6643 06:02:35.555126 [CA 5] Center 36 (8~64) winsize 57
6644 06:02:35.555544
6645 06:02:35.558921 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6646 06:02:35.559340
6647 06:02:35.561630 [CATrainingPosCal] consider 2 rank data
6648 06:02:35.565081 u2DelayCellTimex100 = 270/100 ps
6649 06:02:35.568485 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 06:02:35.572258 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 06:02:35.575085 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 06:02:35.578399 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 06:02:35.585542 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 06:02:35.588537 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 06:02:35.588950
6656 06:02:35.591518 CA PerBit enable=1, Macro0, CA PI delay=36
6657 06:02:35.591929
6658 06:02:35.595299 [CBTSetCACLKResult] CA Dly = 36
6659 06:02:35.595810 CS Dly: 1 (0~32)
6660 06:02:35.596141
6661 06:02:35.598206 ----->DramcWriteLeveling(PI) begin...
6662 06:02:35.598619 ==
6663 06:02:35.601845 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 06:02:35.608181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 06:02:35.608680 ==
6666 06:02:35.611357 Write leveling (Byte 0): 40 => 8
6667 06:02:35.611773 Write leveling (Byte 1): 40 => 8
6668 06:02:35.615162 DramcWriteLeveling(PI) end<-----
6669 06:02:35.615573
6670 06:02:35.615902 ==
6671 06:02:35.617959 Dram Type= 6, Freq= 0, CH_1, rank 0
6672 06:02:35.624998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 06:02:35.625415 ==
6674 06:02:35.628271 [Gating] SW mode calibration
6675 06:02:35.634810 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6676 06:02:35.637965 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6677 06:02:35.644884 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6678 06:02:35.647613 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6679 06:02:35.651302 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6680 06:02:35.658270 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6681 06:02:35.660989 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 06:02:35.664905 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6683 06:02:35.671032 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 06:02:35.674511 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 06:02:35.678170 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 06:02:35.681144 Total UI for P1: 0, mck2ui 16
6687 06:02:35.684454 best dqsien dly found for B0: ( 0, 14, 24)
6688 06:02:35.688046 Total UI for P1: 0, mck2ui 16
6689 06:02:35.691210 best dqsien dly found for B1: ( 0, 14, 24)
6690 06:02:35.694365 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6691 06:02:35.697452 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6692 06:02:35.697934
6693 06:02:35.704280 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6694 06:02:35.707650 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6695 06:02:35.708223 [Gating] SW calibration Done
6696 06:02:35.710599 ==
6697 06:02:35.713970 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 06:02:35.718030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 06:02:35.718449 ==
6700 06:02:35.718846 RX Vref Scan: 0
6701 06:02:35.719166
6702 06:02:35.721247 RX Vref 0 -> 0, step: 1
6703 06:02:35.721703
6704 06:02:35.724295 RX Delay -410 -> 252, step: 16
6705 06:02:35.727465 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6706 06:02:35.730968 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6707 06:02:35.738114 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6708 06:02:35.740889 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6709 06:02:35.743941 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6710 06:02:35.747217 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6711 06:02:35.754024 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6712 06:02:35.757201 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6713 06:02:35.760507 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6714 06:02:35.764038 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6715 06:02:35.770616 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6716 06:02:35.773729 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6717 06:02:35.777454 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6718 06:02:35.784464 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6719 06:02:35.787277 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6720 06:02:35.790757 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6721 06:02:35.791270 ==
6722 06:02:35.794368 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 06:02:35.797061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 06:02:35.797615 ==
6725 06:02:35.800747 DQS Delay:
6726 06:02:35.801258 DQS0 = 51, DQS1 = 67
6727 06:02:35.804064 DQM Delay:
6728 06:02:35.804584 DQM0 = 13, DQM1 = 19
6729 06:02:35.807455 DQ Delay:
6730 06:02:35.807933 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6731 06:02:35.810276 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6732 06:02:35.813743 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6733 06:02:35.817304 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6734 06:02:35.817868
6735 06:02:35.818209
6736 06:02:35.818517 ==
6737 06:02:35.820531 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 06:02:35.827409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 06:02:35.827923 ==
6740 06:02:35.828255
6741 06:02:35.828590
6742 06:02:35.828887 TX Vref Scan disable
6743 06:02:35.830157 == TX Byte 0 ==
6744 06:02:35.834084 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 06:02:35.837368 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 06:02:35.840194 == TX Byte 1 ==
6747 06:02:35.843761 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 06:02:35.846996 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 06:02:35.850360 ==
6750 06:02:35.853834 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 06:02:35.856676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 06:02:35.857151 ==
6753 06:02:35.857740
6754 06:02:35.858076
6755 06:02:35.860290 TX Vref Scan disable
6756 06:02:35.860705 == TX Byte 0 ==
6757 06:02:35.863504 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 06:02:35.870169 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 06:02:35.870682 == TX Byte 1 ==
6760 06:02:35.873442 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 06:02:35.879773 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 06:02:35.880195
6763 06:02:35.880525 [DATLAT]
6764 06:02:35.880831 Freq=400, CH1 RK0
6765 06:02:35.881129
6766 06:02:35.883023 DATLAT Default: 0xf
6767 06:02:35.883440 0, 0xFFFF, sum = 0
6768 06:02:35.886450 1, 0xFFFF, sum = 0
6769 06:02:35.890289 2, 0xFFFF, sum = 0
6770 06:02:35.890803 3, 0xFFFF, sum = 0
6771 06:02:35.893245 4, 0xFFFF, sum = 0
6772 06:02:35.893813 5, 0xFFFF, sum = 0
6773 06:02:35.896765 6, 0xFFFF, sum = 0
6774 06:02:35.897284 7, 0xFFFF, sum = 0
6775 06:02:35.900263 8, 0xFFFF, sum = 0
6776 06:02:35.900777 9, 0xFFFF, sum = 0
6777 06:02:35.902994 10, 0xFFFF, sum = 0
6778 06:02:35.903413 11, 0xFFFF, sum = 0
6779 06:02:35.906445 12, 0xFFFF, sum = 0
6780 06:02:35.906863 13, 0x0, sum = 1
6781 06:02:35.909995 14, 0x0, sum = 2
6782 06:02:35.910412 15, 0x0, sum = 3
6783 06:02:35.913355 16, 0x0, sum = 4
6784 06:02:35.913832 best_step = 14
6785 06:02:35.914161
6786 06:02:35.914464 ==
6787 06:02:35.916090 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 06:02:35.919942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 06:02:35.922561 ==
6790 06:02:35.922974 RX Vref Scan: 1
6791 06:02:35.923298
6792 06:02:35.926337 RX Vref 0 -> 0, step: 1
6793 06:02:35.926749
6794 06:02:35.929194 RX Delay -375 -> 252, step: 8
6795 06:02:35.929640
6796 06:02:35.932893 Set Vref, RX VrefLevel [Byte0]: 58
6797 06:02:35.936292 [Byte1]: 50
6798 06:02:35.936814
6799 06:02:35.939366 Final RX Vref Byte 0 = 58 to rank0
6800 06:02:35.943047 Final RX Vref Byte 1 = 50 to rank0
6801 06:02:35.946469 Final RX Vref Byte 0 = 58 to rank1
6802 06:02:35.949350 Final RX Vref Byte 1 = 50 to rank1==
6803 06:02:35.952593 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 06:02:35.955928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 06:02:35.959168 ==
6806 06:02:35.959583 DQS Delay:
6807 06:02:35.959913 DQS0 = 56, DQS1 = 64
6808 06:02:35.962582 DQM Delay:
6809 06:02:35.963101 DQM0 = 13, DQM1 = 10
6810 06:02:35.965801 DQ Delay:
6811 06:02:35.966213 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6812 06:02:35.969183 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6813 06:02:35.972571 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6814 06:02:35.975746 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6815 06:02:35.976162
6816 06:02:35.976487
6817 06:02:35.985676 [DQSOSCAuto] RK0, (LSB)MR18= 0x5265, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 399 ps
6818 06:02:35.989147 CH1 RK0: MR19=C0C, MR18=5265
6819 06:02:35.995673 CH1_RK0: MR19=0xC0C, MR18=0x5265, DQSOSC=397, MR23=63, INC=374, DEC=249
6820 06:02:35.996272 ==
6821 06:02:35.999198 Dram Type= 6, Freq= 0, CH_1, rank 1
6822 06:02:36.002106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 06:02:36.002525 ==
6824 06:02:36.005654 [Gating] SW mode calibration
6825 06:02:36.012211 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6826 06:02:36.018830 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6827 06:02:36.022044 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6828 06:02:36.025648 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6829 06:02:36.028422 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6830 06:02:36.035145 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6831 06:02:36.038632 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6832 06:02:36.041664 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6833 06:02:36.048566 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 06:02:36.051905 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 06:02:36.054929 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 06:02:36.058448 Total UI for P1: 0, mck2ui 16
6837 06:02:36.062020 best dqsien dly found for B0: ( 0, 14, 24)
6838 06:02:36.065343 Total UI for P1: 0, mck2ui 16
6839 06:02:36.068433 best dqsien dly found for B1: ( 0, 14, 24)
6840 06:02:36.071764 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6841 06:02:36.078338 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6842 06:02:36.078850
6843 06:02:36.081577 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6844 06:02:36.085179 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6845 06:02:36.088590 [Gating] SW calibration Done
6846 06:02:36.089004 ==
6847 06:02:36.091413 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 06:02:36.095022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 06:02:36.095535 ==
6850 06:02:36.095873 RX Vref Scan: 0
6851 06:02:36.098276
6852 06:02:36.098739 RX Vref 0 -> 0, step: 1
6853 06:02:36.099309
6854 06:02:36.101622 RX Delay -410 -> 252, step: 16
6855 06:02:36.104859 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6856 06:02:36.111283 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6857 06:02:36.114634 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6858 06:02:36.118055 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6859 06:02:36.121566 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6860 06:02:36.127973 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6861 06:02:36.131010 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6862 06:02:36.134299 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6863 06:02:36.138155 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6864 06:02:36.144323 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6865 06:02:36.147768 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6866 06:02:36.151339 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6867 06:02:36.157915 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6868 06:02:36.161754 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6869 06:02:36.164457 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6870 06:02:36.168196 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6871 06:02:36.168722 ==
6872 06:02:36.170787 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 06:02:36.177881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 06:02:36.178434 ==
6875 06:02:36.178881 DQS Delay:
6876 06:02:36.181211 DQS0 = 59, DQS1 = 59
6877 06:02:36.181672 DQM Delay:
6878 06:02:36.184834 DQM0 = 19, DQM1 = 12
6879 06:02:36.185337 DQ Delay:
6880 06:02:36.187628 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6881 06:02:36.191214 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6882 06:02:36.194392 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6883 06:02:36.197866 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6884 06:02:36.198281
6885 06:02:36.198610
6886 06:02:36.198915 ==
6887 06:02:36.200956 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 06:02:36.204087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 06:02:36.204682 ==
6890 06:02:36.205020
6891 06:02:36.205325
6892 06:02:36.207434 TX Vref Scan disable
6893 06:02:36.207970 == TX Byte 0 ==
6894 06:02:36.214118 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6895 06:02:36.217447 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6896 06:02:36.217948 == TX Byte 1 ==
6897 06:02:36.220774 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6898 06:02:36.227054 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6899 06:02:36.227479 ==
6900 06:02:36.230528 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 06:02:36.234023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 06:02:36.234446 ==
6903 06:02:36.234925
6904 06:02:36.235328
6905 06:02:36.237150 TX Vref Scan disable
6906 06:02:36.237632 == TX Byte 0 ==
6907 06:02:36.243971 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6908 06:02:36.246855 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6909 06:02:36.247384 == TX Byte 1 ==
6910 06:02:36.253866 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6911 06:02:36.256925 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6912 06:02:36.257346
6913 06:02:36.257903 [DATLAT]
6914 06:02:36.260032 Freq=400, CH1 RK1
6915 06:02:36.260458
6916 06:02:36.260886 DATLAT Default: 0xe
6917 06:02:36.263678 0, 0xFFFF, sum = 0
6918 06:02:36.264108 1, 0xFFFF, sum = 0
6919 06:02:36.267049 2, 0xFFFF, sum = 0
6920 06:02:36.267481 3, 0xFFFF, sum = 0
6921 06:02:36.270348 4, 0xFFFF, sum = 0
6922 06:02:36.270773 5, 0xFFFF, sum = 0
6923 06:02:36.273703 6, 0xFFFF, sum = 0
6924 06:02:36.274115 7, 0xFFFF, sum = 0
6925 06:02:36.277100 8, 0xFFFF, sum = 0
6926 06:02:36.277707 9, 0xFFFF, sum = 0
6927 06:02:36.280082 10, 0xFFFF, sum = 0
6928 06:02:36.283655 11, 0xFFFF, sum = 0
6929 06:02:36.284172 12, 0xFFFF, sum = 0
6930 06:02:36.286813 13, 0x0, sum = 1
6931 06:02:36.287228 14, 0x0, sum = 2
6932 06:02:36.287559 15, 0x0, sum = 3
6933 06:02:36.290300 16, 0x0, sum = 4
6934 06:02:36.290715 best_step = 14
6935 06:02:36.291041
6936 06:02:36.293239 ==
6937 06:02:36.293670 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 06:02:36.300098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 06:02:36.300508 ==
6940 06:02:36.300832 RX Vref Scan: 0
6941 06:02:36.301133
6942 06:02:36.303400 RX Vref 0 -> 0, step: 1
6943 06:02:36.303807
6944 06:02:36.306252 RX Delay -359 -> 252, step: 8
6945 06:02:36.313173 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6946 06:02:36.317210 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6947 06:02:36.320275 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6948 06:02:36.323677 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6949 06:02:36.330253 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6950 06:02:36.333296 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6951 06:02:36.336983 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6952 06:02:36.343321 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6953 06:02:36.346248 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6954 06:02:36.349670 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6955 06:02:36.353284 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6956 06:02:36.359697 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6957 06:02:36.363121 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6958 06:02:36.366278 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6959 06:02:36.369590 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6960 06:02:36.376263 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6961 06:02:36.376757 ==
6962 06:02:36.380158 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 06:02:36.383018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 06:02:36.383435 ==
6965 06:02:36.383762 DQS Delay:
6966 06:02:36.386031 DQS0 = 60, DQS1 = 64
6967 06:02:36.386438 DQM Delay:
6968 06:02:36.389667 DQM0 = 12, DQM1 = 10
6969 06:02:36.390179 DQ Delay:
6970 06:02:36.392494 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6971 06:02:36.396080 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6972 06:02:36.400023 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6973 06:02:36.402613 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6974 06:02:36.403024
6975 06:02:36.403349
6976 06:02:36.409118 [DQSOSCAuto] RK1, (LSB)MR18= 0x75a5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6977 06:02:36.412580 CH1 RK1: MR19=C0C, MR18=75A5
6978 06:02:36.419187 CH1_RK1: MR19=0xC0C, MR18=0x75A5, DQSOSC=389, MR23=63, INC=390, DEC=260
6979 06:02:36.422672 [RxdqsGatingPostProcess] freq 400
6980 06:02:36.429453 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6981 06:02:36.432433 best DQS0 dly(2T, 0.5T) = (0, 10)
6982 06:02:36.435830 best DQS1 dly(2T, 0.5T) = (0, 10)
6983 06:02:36.438943 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6984 06:02:36.442343 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6985 06:02:36.442783 best DQS0 dly(2T, 0.5T) = (0, 10)
6986 06:02:36.445984 best DQS1 dly(2T, 0.5T) = (0, 10)
6987 06:02:36.448844 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6988 06:02:36.452433 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6989 06:02:36.455782 Pre-setting of DQS Precalculation
6990 06:02:36.462571 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6991 06:02:36.469139 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6992 06:02:36.475758 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6993 06:02:36.476285
6994 06:02:36.476752
6995 06:02:36.478656 [Calibration Summary] 800 Mbps
6996 06:02:36.479135 CH 0, Rank 0
6997 06:02:36.482141 SW Impedance : PASS
6998 06:02:36.485700 DUTY Scan : NO K
6999 06:02:36.486145 ZQ Calibration : PASS
7000 06:02:36.488609 Jitter Meter : NO K
7001 06:02:36.491879 CBT Training : PASS
7002 06:02:36.492445 Write leveling : PASS
7003 06:02:36.495320 RX DQS gating : PASS
7004 06:02:36.498601 RX DQ/DQS(RDDQC) : PASS
7005 06:02:36.499051 TX DQ/DQS : PASS
7006 06:02:36.501884 RX DATLAT : PASS
7007 06:02:36.505317 RX DQ/DQS(Engine): PASS
7008 06:02:36.505815 TX OE : NO K
7009 06:02:36.506430 All Pass.
7010 06:02:36.508717
7011 06:02:36.509316 CH 0, Rank 1
7012 06:02:36.511950 SW Impedance : PASS
7013 06:02:36.512536 DUTY Scan : NO K
7014 06:02:36.515359 ZQ Calibration : PASS
7015 06:02:36.515855 Jitter Meter : NO K
7016 06:02:36.518445 CBT Training : PASS
7017 06:02:36.521916 Write leveling : NO K
7018 06:02:36.522325 RX DQS gating : PASS
7019 06:02:36.525178 RX DQ/DQS(RDDQC) : PASS
7020 06:02:36.528798 TX DQ/DQS : PASS
7021 06:02:36.529309 RX DATLAT : PASS
7022 06:02:36.532144 RX DQ/DQS(Engine): PASS
7023 06:02:36.535316 TX OE : NO K
7024 06:02:36.535829 All Pass.
7025 06:02:36.536158
7026 06:02:36.536459 CH 1, Rank 0
7027 06:02:36.538392 SW Impedance : PASS
7028 06:02:36.542022 DUTY Scan : NO K
7029 06:02:36.542530 ZQ Calibration : PASS
7030 06:02:36.545681 Jitter Meter : NO K
7031 06:02:36.548685 CBT Training : PASS
7032 06:02:36.549193 Write leveling : PASS
7033 06:02:36.551884 RX DQS gating : PASS
7034 06:02:36.555712 RX DQ/DQS(RDDQC) : PASS
7035 06:02:36.556224 TX DQ/DQS : PASS
7036 06:02:36.558309 RX DATLAT : PASS
7037 06:02:36.562052 RX DQ/DQS(Engine): PASS
7038 06:02:36.562561 TX OE : NO K
7039 06:02:36.562893 All Pass.
7040 06:02:36.565063
7041 06:02:36.565544 CH 1, Rank 1
7042 06:02:36.568635 SW Impedance : PASS
7043 06:02:36.569140 DUTY Scan : NO K
7044 06:02:36.571690 ZQ Calibration : PASS
7045 06:02:36.572101 Jitter Meter : NO K
7046 06:02:36.575098 CBT Training : PASS
7047 06:02:36.578084 Write leveling : NO K
7048 06:02:36.578495 RX DQS gating : PASS
7049 06:02:36.581359 RX DQ/DQS(RDDQC) : PASS
7050 06:02:36.585297 TX DQ/DQS : PASS
7051 06:02:36.585905 RX DATLAT : PASS
7052 06:02:36.588534 RX DQ/DQS(Engine): PASS
7053 06:02:36.591966 TX OE : NO K
7054 06:02:36.592420 All Pass.
7055 06:02:36.592783
7056 06:02:36.594763 DramC Write-DBI off
7057 06:02:36.595222 PER_BANK_REFRESH: Hybrid Mode
7058 06:02:36.598507 TX_TRACKING: ON
7059 06:02:36.605227 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7060 06:02:36.611656 [FAST_K] Save calibration result to emmc
7061 06:02:36.614833 dramc_set_vcore_voltage set vcore to 725000
7062 06:02:36.615403 Read voltage for 1600, 0
7063 06:02:36.618017 Vio18 = 0
7064 06:02:36.618442 Vcore = 725000
7065 06:02:36.618905 Vdram = 0
7066 06:02:36.621760 Vddq = 0
7067 06:02:36.622207 Vmddr = 0
7068 06:02:36.624985 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7069 06:02:36.631230 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7070 06:02:36.634642 MEM_TYPE=3, freq_sel=13
7071 06:02:36.638165 sv_algorithm_assistance_LP4_3733
7072 06:02:36.641128 ============ PULL DRAM RESETB DOWN ============
7073 06:02:36.644501 ========== PULL DRAM RESETB DOWN end =========
7074 06:02:36.651419 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7075 06:02:36.654335 ===================================
7076 06:02:36.654744 LPDDR4 DRAM CONFIGURATION
7077 06:02:36.658232 ===================================
7078 06:02:36.661293 EX_ROW_EN[0] = 0x0
7079 06:02:36.661854 EX_ROW_EN[1] = 0x0
7080 06:02:36.664154 LP4Y_EN = 0x0
7081 06:02:36.667565 WORK_FSP = 0x1
7082 06:02:36.667972 WL = 0x5
7083 06:02:36.671078 RL = 0x5
7084 06:02:36.671486 BL = 0x2
7085 06:02:36.674294 RPST = 0x0
7086 06:02:36.674733 RD_PRE = 0x0
7087 06:02:36.678131 WR_PRE = 0x1
7088 06:02:36.678698 WR_PST = 0x1
7089 06:02:36.680965 DBI_WR = 0x0
7090 06:02:36.681372 DBI_RD = 0x0
7091 06:02:36.684751 OTF = 0x1
7092 06:02:36.687830 ===================================
7093 06:02:36.691138 ===================================
7094 06:02:36.691546 ANA top config
7095 06:02:36.694516 ===================================
7096 06:02:36.697850 DLL_ASYNC_EN = 0
7097 06:02:36.701017 ALL_SLAVE_EN = 0
7098 06:02:36.701571 NEW_RANK_MODE = 1
7099 06:02:36.703944 DLL_IDLE_MODE = 1
7100 06:02:36.707456 LP45_APHY_COMB_EN = 1
7101 06:02:36.710863 TX_ODT_DIS = 0
7102 06:02:36.713822 NEW_8X_MODE = 1
7103 06:02:36.717391 ===================================
7104 06:02:36.720779 ===================================
7105 06:02:36.721291 data_rate = 3200
7106 06:02:36.724269 CKR = 1
7107 06:02:36.727107 DQ_P2S_RATIO = 8
7108 06:02:36.731061 ===================================
7109 06:02:36.734197 CA_P2S_RATIO = 8
7110 06:02:36.737444 DQ_CA_OPEN = 0
7111 06:02:36.741103 DQ_SEMI_OPEN = 0
7112 06:02:36.741667 CA_SEMI_OPEN = 0
7113 06:02:36.743778 CA_FULL_RATE = 0
7114 06:02:36.747819 DQ_CKDIV4_EN = 0
7115 06:02:36.750782 CA_CKDIV4_EN = 0
7116 06:02:36.754350 CA_PREDIV_EN = 0
7117 06:02:36.757433 PH8_DLY = 12
7118 06:02:36.757873 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7119 06:02:36.760748 DQ_AAMCK_DIV = 4
7120 06:02:36.763661 CA_AAMCK_DIV = 4
7121 06:02:36.767142 CA_ADMCK_DIV = 4
7122 06:02:36.770531 DQ_TRACK_CA_EN = 0
7123 06:02:36.774038 CA_PICK = 1600
7124 06:02:36.776928 CA_MCKIO = 1600
7125 06:02:36.777341 MCKIO_SEMI = 0
7126 06:02:36.780318 PLL_FREQ = 3068
7127 06:02:36.783631 DQ_UI_PI_RATIO = 32
7128 06:02:36.787230 CA_UI_PI_RATIO = 0
7129 06:02:36.790460 ===================================
7130 06:02:36.793904 ===================================
7131 06:02:36.796989 memory_type:LPDDR4
7132 06:02:36.797572 GP_NUM : 10
7133 06:02:36.800262 SRAM_EN : 1
7134 06:02:36.803803 MD32_EN : 0
7135 06:02:36.807000 ===================================
7136 06:02:36.807424 [ANA_INIT] >>>>>>>>>>>>>>
7137 06:02:36.810253 <<<<<< [CONFIGURE PHASE]: ANA_TX
7138 06:02:36.813741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7139 06:02:36.816657 ===================================
7140 06:02:36.820233 data_rate = 3200,PCW = 0X7600
7141 06:02:36.823456 ===================================
7142 06:02:36.826674 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7143 06:02:36.833591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7144 06:02:36.836784 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7145 06:02:36.843874 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7146 06:02:36.846826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7147 06:02:36.849644 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7148 06:02:36.850062 [ANA_INIT] flow start
7149 06:02:36.852864 [ANA_INIT] PLL >>>>>>>>
7150 06:02:36.856555 [ANA_INIT] PLL <<<<<<<<
7151 06:02:36.860035 [ANA_INIT] MIDPI >>>>>>>>
7152 06:02:36.860446 [ANA_INIT] MIDPI <<<<<<<<
7153 06:02:36.862652 [ANA_INIT] DLL >>>>>>>>
7154 06:02:36.866349 [ANA_INIT] DLL <<<<<<<<
7155 06:02:36.866762 [ANA_INIT] flow end
7156 06:02:36.872463 ============ LP4 DIFF to SE enter ============
7157 06:02:36.876198 ============ LP4 DIFF to SE exit ============
7158 06:02:36.876616 [ANA_INIT] <<<<<<<<<<<<<
7159 06:02:36.879477 [Flow] Enable top DCM control >>>>>
7160 06:02:36.882862 [Flow] Enable top DCM control <<<<<
7161 06:02:36.886029 Enable DLL master slave shuffle
7162 06:02:36.892726 ==============================================================
7163 06:02:36.895937 Gating Mode config
7164 06:02:36.899522 ==============================================================
7165 06:02:36.902787 Config description:
7166 06:02:36.912533 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7167 06:02:36.919026 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7168 06:02:36.922481 SELPH_MODE 0: By rank 1: By Phase
7169 06:02:36.929277 ==============================================================
7170 06:02:36.932390 GAT_TRACK_EN = 1
7171 06:02:36.935969 RX_GATING_MODE = 2
7172 06:02:36.938898 RX_GATING_TRACK_MODE = 2
7173 06:02:36.939321 SELPH_MODE = 1
7174 06:02:36.942487 PICG_EARLY_EN = 1
7175 06:02:36.945347 VALID_LAT_VALUE = 1
7176 06:02:36.952472 ==============================================================
7177 06:02:36.955426 Enter into Gating configuration >>>>
7178 06:02:36.958993 Exit from Gating configuration <<<<
7179 06:02:36.961958 Enter into DVFS_PRE_config >>>>>
7180 06:02:36.972049 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7181 06:02:36.975410 Exit from DVFS_PRE_config <<<<<
7182 06:02:36.978591 Enter into PICG configuration >>>>
7183 06:02:36.981813 Exit from PICG configuration <<<<
7184 06:02:36.984876 [RX_INPUT] configuration >>>>>
7185 06:02:36.988305 [RX_INPUT] configuration <<<<<
7186 06:02:36.992046 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7187 06:02:36.998167 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7188 06:02:37.004878 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7189 06:02:37.011606 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7190 06:02:37.017886 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7191 06:02:37.024703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7192 06:02:37.027690 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7193 06:02:37.031290 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7194 06:02:37.034935 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7195 06:02:37.040872 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7196 06:02:37.044397 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7197 06:02:37.047852 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7198 06:02:37.050762 ===================================
7199 06:02:37.054287 LPDDR4 DRAM CONFIGURATION
7200 06:02:37.057980 ===================================
7201 06:02:37.058418 EX_ROW_EN[0] = 0x0
7202 06:02:37.060845 EX_ROW_EN[1] = 0x0
7203 06:02:37.064553 LP4Y_EN = 0x0
7204 06:02:37.065094 WORK_FSP = 0x1
7205 06:02:37.067473 WL = 0x5
7206 06:02:37.067880 RL = 0x5
7207 06:02:37.071199 BL = 0x2
7208 06:02:37.071609 RPST = 0x0
7209 06:02:37.074223 RD_PRE = 0x0
7210 06:02:37.074629 WR_PRE = 0x1
7211 06:02:37.077626 WR_PST = 0x1
7212 06:02:37.078036 DBI_WR = 0x0
7213 06:02:37.081098 DBI_RD = 0x0
7214 06:02:37.081534 OTF = 0x1
7215 06:02:37.084111 ===================================
7216 06:02:37.087846 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7217 06:02:37.094306 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7218 06:02:37.097463 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7219 06:02:37.100463 ===================================
7220 06:02:37.104088 LPDDR4 DRAM CONFIGURATION
7221 06:02:37.107492 ===================================
7222 06:02:37.107916 EX_ROW_EN[0] = 0x10
7223 06:02:37.110685 EX_ROW_EN[1] = 0x0
7224 06:02:37.114042 LP4Y_EN = 0x0
7225 06:02:37.114448 WORK_FSP = 0x1
7226 06:02:37.116994 WL = 0x5
7227 06:02:37.117399 RL = 0x5
7228 06:02:37.120364 BL = 0x2
7229 06:02:37.120772 RPST = 0x0
7230 06:02:37.123543 RD_PRE = 0x0
7231 06:02:37.123951 WR_PRE = 0x1
7232 06:02:37.126829 WR_PST = 0x1
7233 06:02:37.127239 DBI_WR = 0x0
7234 06:02:37.130401 DBI_RD = 0x0
7235 06:02:37.130810 OTF = 0x1
7236 06:02:37.133996 ===================================
7237 06:02:37.140127 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7238 06:02:37.140588 ==
7239 06:02:37.143988 Dram Type= 6, Freq= 0, CH_0, rank 0
7240 06:02:37.147007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7241 06:02:37.150015 ==
7242 06:02:37.150423 [Duty_Offset_Calibration]
7243 06:02:37.153560 B0:2 B1:0 CA:3
7244 06:02:37.153969
7245 06:02:37.156690 [DutyScan_Calibration_Flow] k_type=0
7246 06:02:37.165270
7247 06:02:37.165708 ==CLK 0==
7248 06:02:37.168999 Final CLK duty delay cell = 0
7249 06:02:37.172016 [0] MAX Duty = 5031%(X100), DQS PI = 12
7250 06:02:37.175678 [0] MIN Duty = 4907%(X100), DQS PI = 6
7251 06:02:37.176133 [0] AVG Duty = 4969%(X100)
7252 06:02:37.178606
7253 06:02:37.182406 CH0 CLK Duty spec in!! Max-Min= 124%
7254 06:02:37.185390 [DutyScan_Calibration_Flow] ====Done====
7255 06:02:37.185831
7256 06:02:37.188802 [DutyScan_Calibration_Flow] k_type=1
7257 06:02:37.205142
7258 06:02:37.205589 ==DQS 0 ==
7259 06:02:37.208275 Final DQS duty delay cell = 0
7260 06:02:37.211492 [0] MAX Duty = 5125%(X100), DQS PI = 30
7261 06:02:37.215113 [0] MIN Duty = 4906%(X100), DQS PI = 48
7262 06:02:37.218675 [0] AVG Duty = 5015%(X100)
7263 06:02:37.219162
7264 06:02:37.219498 ==DQS 1 ==
7265 06:02:37.221462 Final DQS duty delay cell = 0
7266 06:02:37.225070 [0] MAX Duty = 5156%(X100), DQS PI = 30
7267 06:02:37.228357 [0] MIN Duty = 5031%(X100), DQS PI = 12
7268 06:02:37.231671 [0] AVG Duty = 5093%(X100)
7269 06:02:37.232092
7270 06:02:37.234888 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7271 06:02:37.235345
7272 06:02:37.238740 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7273 06:02:37.241846 [DutyScan_Calibration_Flow] ====Done====
7274 06:02:37.242350
7275 06:02:37.245227 [DutyScan_Calibration_Flow] k_type=3
7276 06:02:37.263464
7277 06:02:37.263871 ==DQM 0 ==
7278 06:02:37.266500 Final DQM duty delay cell = 0
7279 06:02:37.270085 [0] MAX Duty = 5187%(X100), DQS PI = 30
7280 06:02:37.273114 [0] MIN Duty = 4844%(X100), DQS PI = 52
7281 06:02:37.276555 [0] AVG Duty = 5015%(X100)
7282 06:02:37.276962
7283 06:02:37.277286 ==DQM 1 ==
7284 06:02:37.279627 Final DQM duty delay cell = 4
7285 06:02:37.283323 [4] MAX Duty = 5187%(X100), DQS PI = 62
7286 06:02:37.286298 [4] MIN Duty = 5031%(X100), DQS PI = 10
7287 06:02:37.289980 [4] AVG Duty = 5109%(X100)
7288 06:02:37.290390
7289 06:02:37.292884 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7290 06:02:37.293291
7291 06:02:37.296333 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7292 06:02:37.299208 [DutyScan_Calibration_Flow] ====Done====
7293 06:02:37.299617
7294 06:02:37.302741 [DutyScan_Calibration_Flow] k_type=2
7295 06:02:37.319552
7296 06:02:37.319959 ==DQ 0 ==
7297 06:02:37.322792 Final DQ duty delay cell = -4
7298 06:02:37.325783 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7299 06:02:37.329426 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7300 06:02:37.332706 [-4] AVG Duty = 4938%(X100)
7301 06:02:37.332993
7302 06:02:37.333219 ==DQ 1 ==
7303 06:02:37.336011 Final DQ duty delay cell = 0
7304 06:02:37.339096 [0] MAX Duty = 5156%(X100), DQS PI = 58
7305 06:02:37.342393 [0] MIN Duty = 5000%(X100), DQS PI = 14
7306 06:02:37.345874 [0] AVG Duty = 5078%(X100)
7307 06:02:37.346161
7308 06:02:37.348889 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7309 06:02:37.349394
7310 06:02:37.352300 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7311 06:02:37.355538 [DutyScan_Calibration_Flow] ====Done====
7312 06:02:37.355952 ==
7313 06:02:37.358916 Dram Type= 6, Freq= 0, CH_1, rank 0
7314 06:02:37.362210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7315 06:02:37.362597 ==
7316 06:02:37.365236 [Duty_Offset_Calibration]
7317 06:02:37.365561 B0:1 B1:-2 CA:1
7318 06:02:37.365826
7319 06:02:37.368942 [DutyScan_Calibration_Flow] k_type=0
7320 06:02:37.380056
7321 06:02:37.380375 ==CLK 0==
7322 06:02:37.382904 Final CLK duty delay cell = 0
7323 06:02:37.386685 [0] MAX Duty = 5062%(X100), DQS PI = 22
7324 06:02:37.389712 [0] MIN Duty = 4844%(X100), DQS PI = 0
7325 06:02:37.390004 [0] AVG Duty = 4953%(X100)
7326 06:02:37.393169
7327 06:02:37.396211 CH1 CLK Duty spec in!! Max-Min= 218%
7328 06:02:37.399786 [DutyScan_Calibration_Flow] ====Done====
7329 06:02:37.400220
7330 06:02:37.403182 [DutyScan_Calibration_Flow] k_type=1
7331 06:02:37.419317
7332 06:02:37.419732 ==DQS 0 ==
7333 06:02:37.422527 Final DQS duty delay cell = 0
7334 06:02:37.425934 [0] MAX Duty = 5187%(X100), DQS PI = 24
7335 06:02:37.429658 [0] MIN Duty = 5031%(X100), DQS PI = 54
7336 06:02:37.432247 [0] AVG Duty = 5109%(X100)
7337 06:02:37.432656
7338 06:02:37.432982 ==DQS 1 ==
7339 06:02:37.435669 Final DQS duty delay cell = 0
7340 06:02:37.439232 [0] MAX Duty = 5093%(X100), DQS PI = 62
7341 06:02:37.442652 [0] MIN Duty = 4844%(X100), DQS PI = 24
7342 06:02:37.446208 [0] AVG Duty = 4968%(X100)
7343 06:02:37.446619
7344 06:02:37.449221 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7345 06:02:37.449676
7346 06:02:37.452748 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7347 06:02:37.455790 [DutyScan_Calibration_Flow] ====Done====
7348 06:02:37.456198
7349 06:02:37.459188 [DutyScan_Calibration_Flow] k_type=3
7350 06:02:37.476251
7351 06:02:37.476711 ==DQM 0 ==
7352 06:02:37.479761 Final DQM duty delay cell = 0
7353 06:02:37.483178 [0] MAX Duty = 5031%(X100), DQS PI = 24
7354 06:02:37.485899 [0] MIN Duty = 4813%(X100), DQS PI = 56
7355 06:02:37.489573 [0] AVG Duty = 4922%(X100)
7356 06:02:37.489992
7357 06:02:37.490322 ==DQM 1 ==
7358 06:02:37.492717 Final DQM duty delay cell = 0
7359 06:02:37.496244 [0] MAX Duty = 5093%(X100), DQS PI = 36
7360 06:02:37.499702 [0] MIN Duty = 4875%(X100), DQS PI = 24
7361 06:02:37.502750 [0] AVG Duty = 4984%(X100)
7362 06:02:37.503163
7363 06:02:37.506326 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7364 06:02:37.506739
7365 06:02:37.509167 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7366 06:02:37.512628 [DutyScan_Calibration_Flow] ====Done====
7367 06:02:37.513040
7368 06:02:37.516148 [DutyScan_Calibration_Flow] k_type=2
7369 06:02:37.533316
7370 06:02:37.533766 ==DQ 0 ==
7371 06:02:37.536519 Final DQ duty delay cell = 0
7372 06:02:37.539624 [0] MAX Duty = 5093%(X100), DQS PI = 22
7373 06:02:37.542972 [0] MIN Duty = 4907%(X100), DQS PI = 62
7374 06:02:37.543567 [0] AVG Duty = 5000%(X100)
7375 06:02:37.546330
7376 06:02:37.546741 ==DQ 1 ==
7377 06:02:37.549806 Final DQ duty delay cell = 0
7378 06:02:37.553225 [0] MAX Duty = 5125%(X100), DQS PI = 34
7379 06:02:37.556491 [0] MIN Duty = 4938%(X100), DQS PI = 24
7380 06:02:37.556904 [0] AVG Duty = 5031%(X100)
7381 06:02:37.557236
7382 06:02:37.559682 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7383 06:02:37.562925
7384 06:02:37.566492 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7385 06:02:37.569403 [DutyScan_Calibration_Flow] ====Done====
7386 06:02:37.573087 nWR fixed to 30
7387 06:02:37.573552 [ModeRegInit_LP4] CH0 RK0
7388 06:02:37.575927 [ModeRegInit_LP4] CH0 RK1
7389 06:02:37.579159 [ModeRegInit_LP4] CH1 RK0
7390 06:02:37.582645 [ModeRegInit_LP4] CH1 RK1
7391 06:02:37.583060 match AC timing 5
7392 06:02:37.589467 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7393 06:02:37.592990 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7394 06:02:37.596037 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7395 06:02:37.603169 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7396 06:02:37.606031 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7397 06:02:37.606450 [MiockJmeterHQA]
7398 06:02:37.606781
7399 06:02:37.609216 [DramcMiockJmeter] u1RxGatingPI = 0
7400 06:02:37.612316 0 : 4257, 4029
7401 06:02:37.612899 4 : 4255, 4029
7402 06:02:37.615842 8 : 4367, 4142
7403 06:02:37.616306 12 : 4258, 4029
7404 06:02:37.616776 16 : 4260, 4031
7405 06:02:37.619021 20 : 4258, 4029
7406 06:02:37.619452 24 : 4255, 4030
7407 06:02:37.622609 28 : 4258, 4029
7408 06:02:37.623028 32 : 4253, 4029
7409 06:02:37.625676 36 : 4259, 4031
7410 06:02:37.626099 40 : 4252, 4029
7411 06:02:37.629342 44 : 4257, 4029
7412 06:02:37.629806 48 : 4258, 4029
7413 06:02:37.630145 52 : 4257, 4029
7414 06:02:37.632413 56 : 4371, 4142
7415 06:02:37.632834 60 : 4252, 4029
7416 06:02:37.635934 64 : 4253, 4029
7417 06:02:37.636358 68 : 4254, 4029
7418 06:02:37.638988 72 : 4252, 4029
7419 06:02:37.639410 76 : 4257, 4032
7420 06:02:37.642290 80 : 4255, 4029
7421 06:02:37.642710 84 : 4252, 4030
7422 06:02:37.643046 88 : 4255, 4031
7423 06:02:37.645418 92 : 4361, 4138
7424 06:02:37.645883 96 : 4254, 4029
7425 06:02:37.648790 100 : 4250, 4027
7426 06:02:37.649213 104 : 4365, 3810
7427 06:02:37.652130 108 : 4365, 3
7428 06:02:37.652551 112 : 4366, 0
7429 06:02:37.652889 116 : 4255, 0
7430 06:02:37.655665 120 : 4255, 0
7431 06:02:37.656088 124 : 4252, 0
7432 06:02:37.658830 128 : 4368, 0
7433 06:02:37.659252 132 : 4253, 0
7434 06:02:37.659611 136 : 4253, 0
7435 06:02:37.662102 140 : 4255, 0
7436 06:02:37.662526 144 : 4257, 0
7437 06:02:37.665339 148 : 4253, 0
7438 06:02:37.665795 152 : 4252, 0
7439 06:02:37.666332 156 : 4258, 0
7440 06:02:37.668780 160 : 4252, 0
7441 06:02:37.669200 164 : 4253, 0
7442 06:02:37.671793 168 : 4257, 0
7443 06:02:37.672218 172 : 4253, 0
7444 06:02:37.672564 176 : 4253, 0
7445 06:02:37.675173 180 : 4252, 0
7446 06:02:37.675595 184 : 4257, 0
7447 06:02:37.675934 188 : 4253, 0
7448 06:02:37.678945 192 : 4252, 0
7449 06:02:37.679366 196 : 4257, 0
7450 06:02:37.682302 200 : 4255, 0
7451 06:02:37.682722 204 : 4365, 0
7452 06:02:37.683056 208 : 4363, 0
7453 06:02:37.685229 212 : 4252, 0
7454 06:02:37.685693 216 : 4366, 0
7455 06:02:37.688907 220 : 4365, 0
7456 06:02:37.689327 224 : 4250, 0
7457 06:02:37.689720 228 : 4363, 0
7458 06:02:37.691941 232 : 4250, 1
7459 06:02:37.692361 236 : 4250, 1182
7460 06:02:37.695624 240 : 4368, 4142
7461 06:02:37.696047 244 : 4255, 4029
7462 06:02:37.698527 248 : 4365, 4140
7463 06:02:37.698946 252 : 4255, 4030
7464 06:02:37.702210 256 : 4250, 4026
7465 06:02:37.702631 260 : 4253, 4029
7466 06:02:37.702966 264 : 4253, 4029
7467 06:02:37.705400 268 : 4363, 4140
7468 06:02:37.705867 272 : 4252, 4030
7469 06:02:37.708896 276 : 4363, 4140
7470 06:02:37.709548 280 : 4252, 4029
7471 06:02:37.711528 284 : 4363, 4140
7472 06:02:37.712085 288 : 4255, 4029
7473 06:02:37.715461 292 : 4255, 4029
7474 06:02:37.715882 296 : 4365, 4139
7475 06:02:37.718690 300 : 4252, 4029
7476 06:02:37.719114 304 : 4254, 4030
7477 06:02:37.722233 308 : 4257, 4031
7478 06:02:37.722655 312 : 4255, 4030
7479 06:02:37.725190 316 : 4252, 4029
7480 06:02:37.725658 320 : 4363, 4139
7481 06:02:37.726004 324 : 4252, 4030
7482 06:02:37.728344 328 : 4255, 4030
7483 06:02:37.728767 332 : 4252, 4029
7484 06:02:37.732080 336 : 4363, 4140
7485 06:02:37.732503 340 : 4255, 4029
7486 06:02:37.734909 344 : 4365, 4140
7487 06:02:37.735334 348 : 4255, 4029
7488 06:02:37.738528 352 : 4366, 4130
7489 06:02:37.739050 356 : 4253, 2805
7490 06:02:37.742036 360 : 4255, 1
7491 06:02:37.742461
7492 06:02:37.742793 MIOCK jitter meter ch=0
7493 06:02:37.743100
7494 06:02:37.745077 1T = (360-108) = 252 dly cells
7495 06:02:37.751397 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7496 06:02:37.751826 ==
7497 06:02:37.755006 Dram Type= 6, Freq= 0, CH_0, rank 0
7498 06:02:37.758407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7499 06:02:37.758826 ==
7500 06:02:37.765158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7501 06:02:37.768137 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7502 06:02:37.771306 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7503 06:02:37.778146 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7504 06:02:37.787989 [CA 0] Center 44 (14~75) winsize 62
7505 06:02:37.791425 [CA 1] Center 43 (13~74) winsize 62
7506 06:02:37.794741 [CA 2] Center 40 (11~69) winsize 59
7507 06:02:37.797983 [CA 3] Center 39 (10~68) winsize 59
7508 06:02:37.801458 [CA 4] Center 37 (8~67) winsize 60
7509 06:02:37.804390 [CA 5] Center 37 (7~67) winsize 61
7510 06:02:37.804803
7511 06:02:37.808030 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7512 06:02:37.808447
7513 06:02:37.814650 [CATrainingPosCal] consider 1 rank data
7514 06:02:37.815078 u2DelayCellTimex100 = 258/100 ps
7515 06:02:37.821509 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7516 06:02:37.824555 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7517 06:02:37.828200 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7518 06:02:37.831080 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7519 06:02:37.834578 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7520 06:02:37.837912 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7521 06:02:37.838325
7522 06:02:37.841033 CA PerBit enable=1, Macro0, CA PI delay=37
7523 06:02:37.841450
7524 06:02:37.844412 [CBTSetCACLKResult] CA Dly = 37
7525 06:02:37.847708 CS Dly: 11 (0~42)
7526 06:02:37.851223 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7527 06:02:37.854039 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7528 06:02:37.854452 ==
7529 06:02:37.857773 Dram Type= 6, Freq= 0, CH_0, rank 1
7530 06:02:37.863911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 06:02:37.864356 ==
7532 06:02:37.867745 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7533 06:02:37.874278 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7534 06:02:37.877593 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7535 06:02:37.884273 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7536 06:02:37.892036 [CA 0] Center 44 (13~75) winsize 63
7537 06:02:37.895044 [CA 1] Center 43 (13~74) winsize 62
7538 06:02:37.898602 [CA 2] Center 39 (10~69) winsize 60
7539 06:02:37.902002 [CA 3] Center 39 (10~68) winsize 59
7540 06:02:37.905437 [CA 4] Center 37 (8~67) winsize 60
7541 06:02:37.908624 [CA 5] Center 36 (7~66) winsize 60
7542 06:02:37.909038
7543 06:02:37.911413 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7544 06:02:37.911830
7545 06:02:37.918484 [CATrainingPosCal] consider 2 rank data
7546 06:02:37.918900 u2DelayCellTimex100 = 258/100 ps
7547 06:02:37.924807 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7548 06:02:37.928466 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7549 06:02:37.931325 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7550 06:02:37.934807 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7551 06:02:37.938606 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7552 06:02:37.941589 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7553 06:02:37.942005
7554 06:02:37.945345 CA PerBit enable=1, Macro0, CA PI delay=36
7555 06:02:37.945808
7556 06:02:37.948318 [CBTSetCACLKResult] CA Dly = 36
7557 06:02:37.951423 CS Dly: 11 (0~43)
7558 06:02:37.954896 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7559 06:02:37.957983 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7560 06:02:37.958395
7561 06:02:37.961726 ----->DramcWriteLeveling(PI) begin...
7562 06:02:37.962145 ==
7563 06:02:37.964991 Dram Type= 6, Freq= 0, CH_0, rank 0
7564 06:02:37.971223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 06:02:37.971638 ==
7566 06:02:37.974755 Write leveling (Byte 0): 35 => 35
7567 06:02:37.977629 Write leveling (Byte 1): 28 => 28
7568 06:02:37.981303 DramcWriteLeveling(PI) end<-----
7569 06:02:37.981768
7570 06:02:37.982098 ==
7571 06:02:37.984498 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 06:02:37.987638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 06:02:37.988066 ==
7574 06:02:37.991173 [Gating] SW mode calibration
7575 06:02:37.997660 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7576 06:02:38.004634 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7577 06:02:38.007597 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 06:02:38.010942 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 06:02:38.017449 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 06:02:38.021049 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 06:02:38.023953 1 4 16 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
7582 06:02:38.030498 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7583 06:02:38.034436 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7584 06:02:38.037354 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7585 06:02:38.041193 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 06:02:38.047142 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 06:02:38.050590 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 06:02:38.054121 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7589 06:02:38.060853 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
7590 06:02:38.063676 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (0 0) (1 0)
7591 06:02:38.067295 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7592 06:02:38.073874 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7593 06:02:38.077278 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 06:02:38.080178 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 06:02:38.087289 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 06:02:38.090073 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 06:02:38.093545 1 6 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7598 06:02:38.100077 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7599 06:02:38.103526 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7600 06:02:38.106917 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 06:02:38.113554 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 06:02:38.117221 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 06:02:38.120024 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 06:02:38.127030 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 06:02:38.130107 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7606 06:02:38.133679 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7607 06:02:38.140429 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7608 06:02:38.143482 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 06:02:38.147091 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 06:02:38.153748 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 06:02:38.156713 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 06:02:38.159697 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 06:02:38.166370 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 06:02:38.169966 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 06:02:38.172898 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 06:02:38.179777 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 06:02:38.182986 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 06:02:38.185980 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 06:02:38.193058 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 06:02:38.196181 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7621 06:02:38.199503 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7622 06:02:38.205855 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7623 06:02:38.209190 Total UI for P1: 0, mck2ui 16
7624 06:02:38.212416 best dqsien dly found for B0: ( 1, 9, 14)
7625 06:02:38.215538 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 06:02:38.219286 Total UI for P1: 0, mck2ui 16
7627 06:02:38.222362 best dqsien dly found for B1: ( 1, 9, 20)
7628 06:02:38.225607 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7629 06:02:38.229224 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7630 06:02:38.229717
7631 06:02:38.232145 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7632 06:02:38.235495 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7633 06:02:38.239132 [Gating] SW calibration Done
7634 06:02:38.239552 ==
7635 06:02:38.242459 Dram Type= 6, Freq= 0, CH_0, rank 0
7636 06:02:38.249095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7637 06:02:38.249549 ==
7638 06:02:38.249893 RX Vref Scan: 0
7639 06:02:38.250223
7640 06:02:38.252199 RX Vref 0 -> 0, step: 1
7641 06:02:38.252616
7642 06:02:38.255314 RX Delay 0 -> 252, step: 8
7643 06:02:38.258876 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7644 06:02:38.261958 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7645 06:02:38.265614 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7646 06:02:38.268592 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7647 06:02:38.274932 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7648 06:02:38.278505 iDelay=200, Bit 5, Center 115 (64 ~ 167) 104
7649 06:02:38.282043 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7650 06:02:38.285021 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7651 06:02:38.288624 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7652 06:02:38.295232 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7653 06:02:38.298780 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7654 06:02:38.301520 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7655 06:02:38.304896 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7656 06:02:38.311567 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7657 06:02:38.314565 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7658 06:02:38.318298 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7659 06:02:38.318715 ==
7660 06:02:38.321644 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 06:02:38.325059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 06:02:38.325606 ==
7663 06:02:38.328271 DQS Delay:
7664 06:02:38.328800 DQS0 = 0, DQS1 = 0
7665 06:02:38.331462 DQM Delay:
7666 06:02:38.331876 DQM0 = 129, DQM1 = 124
7667 06:02:38.332207 DQ Delay:
7668 06:02:38.338493 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =123
7669 06:02:38.341582 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =143
7670 06:02:38.344772 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7671 06:02:38.347986 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7672 06:02:38.348401
7673 06:02:38.348729
7674 06:02:38.349034 ==
7675 06:02:38.351238 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 06:02:38.354757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 06:02:38.355175 ==
7678 06:02:38.355506
7679 06:02:38.355812
7680 06:02:38.358137 TX Vref Scan disable
7681 06:02:38.361354 == TX Byte 0 ==
7682 06:02:38.364471 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7683 06:02:38.367969 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7684 06:02:38.371677 == TX Byte 1 ==
7685 06:02:38.374742 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7686 06:02:38.377686 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7687 06:02:38.378289 ==
7688 06:02:38.381172 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 06:02:38.384885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 06:02:38.387802 ==
7691 06:02:38.399962
7692 06:02:38.403081 TX Vref early break, caculate TX vref
7693 06:02:38.406072 TX Vref=16, minBit 8, minWin=21, winSum=358
7694 06:02:38.409765 TX Vref=18, minBit 8, minWin=21, winSum=367
7695 06:02:38.412632 TX Vref=20, minBit 8, minWin=22, winSum=377
7696 06:02:38.416216 TX Vref=22, minBit 8, minWin=23, winSum=387
7697 06:02:38.419507 TX Vref=24, minBit 8, minWin=24, winSum=401
7698 06:02:38.426212 TX Vref=26, minBit 4, minWin=24, winSum=405
7699 06:02:38.429606 TX Vref=28, minBit 10, minWin=24, winSum=404
7700 06:02:38.432610 TX Vref=30, minBit 0, minWin=24, winSum=400
7701 06:02:38.436318 TX Vref=32, minBit 9, minWin=23, winSum=387
7702 06:02:38.439345 TX Vref=34, minBit 8, minWin=21, winSum=381
7703 06:02:38.446040 [TxChooseVref] Worse bit 4, Min win 24, Win sum 405, Final Vref 26
7704 06:02:38.446457
7705 06:02:38.449630 Final TX Range 0 Vref 26
7706 06:02:38.450054
7707 06:02:38.450385 ==
7708 06:02:38.452391 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 06:02:38.456146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 06:02:38.456781 ==
7711 06:02:38.457153
7712 06:02:38.457466
7713 06:02:38.459490 TX Vref Scan disable
7714 06:02:38.466057 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7715 06:02:38.466475 == TX Byte 0 ==
7716 06:02:38.469424 u2DelayCellOfst[0]=11 cells (3 PI)
7717 06:02:38.472358 u2DelayCellOfst[1]=15 cells (4 PI)
7718 06:02:38.475827 u2DelayCellOfst[2]=11 cells (3 PI)
7719 06:02:38.479305 u2DelayCellOfst[3]=7 cells (2 PI)
7720 06:02:38.482500 u2DelayCellOfst[4]=7 cells (2 PI)
7721 06:02:38.485799 u2DelayCellOfst[5]=0 cells (0 PI)
7722 06:02:38.489305 u2DelayCellOfst[6]=18 cells (5 PI)
7723 06:02:38.492839 u2DelayCellOfst[7]=15 cells (4 PI)
7724 06:02:38.495684 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7725 06:02:38.499189 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7726 06:02:38.502585 == TX Byte 1 ==
7727 06:02:38.505611 u2DelayCellOfst[8]=0 cells (0 PI)
7728 06:02:38.506104 u2DelayCellOfst[9]=0 cells (0 PI)
7729 06:02:38.509048 u2DelayCellOfst[10]=7 cells (2 PI)
7730 06:02:38.512392 u2DelayCellOfst[11]=3 cells (1 PI)
7731 06:02:38.515917 u2DelayCellOfst[12]=11 cells (3 PI)
7732 06:02:38.519000 u2DelayCellOfst[13]=11 cells (3 PI)
7733 06:02:38.522298 u2DelayCellOfst[14]=15 cells (4 PI)
7734 06:02:38.525533 u2DelayCellOfst[15]=11 cells (3 PI)
7735 06:02:38.529328 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7736 06:02:38.535404 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7737 06:02:38.535822 DramC Write-DBI on
7738 06:02:38.536152 ==
7739 06:02:38.538940 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 06:02:38.545667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 06:02:38.546154 ==
7742 06:02:38.546490
7743 06:02:38.546797
7744 06:02:38.547089 TX Vref Scan disable
7745 06:02:38.549313 == TX Byte 0 ==
7746 06:02:38.552635 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7747 06:02:38.555889 == TX Byte 1 ==
7748 06:02:38.559365 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7749 06:02:38.562359 DramC Write-DBI off
7750 06:02:38.562770
7751 06:02:38.563098 [DATLAT]
7752 06:02:38.563400 Freq=1600, CH0 RK0
7753 06:02:38.563697
7754 06:02:38.566061 DATLAT Default: 0xf
7755 06:02:38.566475 0, 0xFFFF, sum = 0
7756 06:02:38.569126 1, 0xFFFF, sum = 0
7757 06:02:38.572608 2, 0xFFFF, sum = 0
7758 06:02:38.573026 3, 0xFFFF, sum = 0
7759 06:02:38.575607 4, 0xFFFF, sum = 0
7760 06:02:38.576027 5, 0xFFFF, sum = 0
7761 06:02:38.579088 6, 0xFFFF, sum = 0
7762 06:02:38.579533 7, 0xFFFF, sum = 0
7763 06:02:38.582421 8, 0xFFFF, sum = 0
7764 06:02:38.582841 9, 0xFFFF, sum = 0
7765 06:02:38.585710 10, 0xFFFF, sum = 0
7766 06:02:38.586133 11, 0xFFFF, sum = 0
7767 06:02:38.589325 12, 0xFFFF, sum = 0
7768 06:02:38.589764 13, 0xFFFF, sum = 0
7769 06:02:38.592645 14, 0x0, sum = 1
7770 06:02:38.593074 15, 0x0, sum = 2
7771 06:02:38.595693 16, 0x0, sum = 3
7772 06:02:38.596113 17, 0x0, sum = 4
7773 06:02:38.599038 best_step = 15
7774 06:02:38.599603
7775 06:02:38.599944 ==
7776 06:02:38.602357 Dram Type= 6, Freq= 0, CH_0, rank 0
7777 06:02:38.605762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7778 06:02:38.606181 ==
7779 06:02:38.609228 RX Vref Scan: 1
7780 06:02:38.609778
7781 06:02:38.610204 Set Vref Range= 24 -> 127
7782 06:02:38.610541
7783 06:02:38.612157 RX Vref 24 -> 127, step: 1
7784 06:02:38.612700
7785 06:02:38.615850 RX Delay 11 -> 252, step: 4
7786 06:02:38.616381
7787 06:02:38.619441 Set Vref, RX VrefLevel [Byte0]: 24
7788 06:02:38.622599 [Byte1]: 24
7789 06:02:38.623017
7790 06:02:38.625632 Set Vref, RX VrefLevel [Byte0]: 25
7791 06:02:38.629310 [Byte1]: 25
7792 06:02:38.629775
7793 06:02:38.632165 Set Vref, RX VrefLevel [Byte0]: 26
7794 06:02:38.635394 [Byte1]: 26
7795 06:02:38.639503
7796 06:02:38.640013 Set Vref, RX VrefLevel [Byte0]: 27
7797 06:02:38.643038 [Byte1]: 27
7798 06:02:38.647195
7799 06:02:38.647654 Set Vref, RX VrefLevel [Byte0]: 28
7800 06:02:38.650332 [Byte1]: 28
7801 06:02:38.655049
7802 06:02:38.655634 Set Vref, RX VrefLevel [Byte0]: 29
7803 06:02:38.658234 [Byte1]: 29
7804 06:02:38.662169
7805 06:02:38.662732 Set Vref, RX VrefLevel [Byte0]: 30
7806 06:02:38.665527 [Byte1]: 30
7807 06:02:38.670017
7808 06:02:38.670429 Set Vref, RX VrefLevel [Byte0]: 31
7809 06:02:38.673405 [Byte1]: 31
7810 06:02:38.677719
7811 06:02:38.678145 Set Vref, RX VrefLevel [Byte0]: 32
7812 06:02:38.681531 [Byte1]: 32
7813 06:02:38.685426
7814 06:02:38.686006 Set Vref, RX VrefLevel [Byte0]: 33
7815 06:02:38.688752 [Byte1]: 33
7816 06:02:38.693164
7817 06:02:38.695903 Set Vref, RX VrefLevel [Byte0]: 34
7818 06:02:38.699543 [Byte1]: 34
7819 06:02:38.700087
7820 06:02:38.702760 Set Vref, RX VrefLevel [Byte0]: 35
7821 06:02:38.706376 [Byte1]: 35
7822 06:02:38.706789
7823 06:02:38.709889 Set Vref, RX VrefLevel [Byte0]: 36
7824 06:02:38.712426 [Byte1]: 36
7825 06:02:38.713029
7826 06:02:38.715640 Set Vref, RX VrefLevel [Byte0]: 37
7827 06:02:38.719201 [Byte1]: 37
7828 06:02:38.723408
7829 06:02:38.723952 Set Vref, RX VrefLevel [Byte0]: 38
7830 06:02:38.726808 [Byte1]: 38
7831 06:02:38.731002
7832 06:02:38.731426 Set Vref, RX VrefLevel [Byte0]: 39
7833 06:02:38.734717 [Byte1]: 39
7834 06:02:38.738743
7835 06:02:38.739156 Set Vref, RX VrefLevel [Byte0]: 40
7836 06:02:38.742019 [Byte1]: 40
7837 06:02:38.746172
7838 06:02:38.746611 Set Vref, RX VrefLevel [Byte0]: 41
7839 06:02:38.749651 [Byte1]: 41
7840 06:02:38.754081
7841 06:02:38.754500 Set Vref, RX VrefLevel [Byte0]: 42
7842 06:02:38.757000 [Byte1]: 42
7843 06:02:38.761713
7844 06:02:38.762149 Set Vref, RX VrefLevel [Byte0]: 43
7845 06:02:38.764718 [Byte1]: 43
7846 06:02:38.769313
7847 06:02:38.769777 Set Vref, RX VrefLevel [Byte0]: 44
7848 06:02:38.772712 [Byte1]: 44
7849 06:02:38.776587
7850 06:02:38.777003 Set Vref, RX VrefLevel [Byte0]: 45
7851 06:02:38.779900 [Byte1]: 45
7852 06:02:38.784138
7853 06:02:38.784553 Set Vref, RX VrefLevel [Byte0]: 46
7854 06:02:38.787644 [Byte1]: 46
7855 06:02:38.792018
7856 06:02:38.794999 Set Vref, RX VrefLevel [Byte0]: 47
7857 06:02:38.798609 [Byte1]: 47
7858 06:02:38.799025
7859 06:02:38.801856 Set Vref, RX VrefLevel [Byte0]: 48
7860 06:02:38.805196 [Byte1]: 48
7861 06:02:38.805799
7862 06:02:38.808151 Set Vref, RX VrefLevel [Byte0]: 49
7863 06:02:38.811301 [Byte1]: 49
7864 06:02:38.814779
7865 06:02:38.815195 Set Vref, RX VrefLevel [Byte0]: 50
7866 06:02:38.817943 [Byte1]: 50
7867 06:02:38.822456
7868 06:02:38.822872 Set Vref, RX VrefLevel [Byte0]: 51
7869 06:02:38.825894 [Byte1]: 51
7870 06:02:38.829717
7871 06:02:38.830136 Set Vref, RX VrefLevel [Byte0]: 52
7872 06:02:38.833471 [Byte1]: 52
7873 06:02:38.837610
7874 06:02:38.838028 Set Vref, RX VrefLevel [Byte0]: 53
7875 06:02:38.840813 [Byte1]: 53
7876 06:02:38.845353
7877 06:02:38.845839 Set Vref, RX VrefLevel [Byte0]: 54
7878 06:02:38.848306 [Byte1]: 54
7879 06:02:38.852869
7880 06:02:38.853286 Set Vref, RX VrefLevel [Byte0]: 55
7881 06:02:38.856325 [Byte1]: 55
7882 06:02:38.860594
7883 06:02:38.861101 Set Vref, RX VrefLevel [Byte0]: 56
7884 06:02:38.863486 [Byte1]: 56
7885 06:02:38.868629
7886 06:02:38.869134 Set Vref, RX VrefLevel [Byte0]: 57
7887 06:02:38.871592 [Byte1]: 57
7888 06:02:38.875793
7889 06:02:38.876210 Set Vref, RX VrefLevel [Byte0]: 58
7890 06:02:38.878812 [Byte1]: 58
7891 06:02:38.883686
7892 06:02:38.884156 Set Vref, RX VrefLevel [Byte0]: 59
7893 06:02:38.886453 [Byte1]: 59
7894 06:02:38.891098
7895 06:02:38.891612 Set Vref, RX VrefLevel [Byte0]: 60
7896 06:02:38.894154 [Byte1]: 60
7897 06:02:38.898457
7898 06:02:38.898885 Set Vref, RX VrefLevel [Byte0]: 61
7899 06:02:38.901739 [Byte1]: 61
7900 06:02:38.905993
7901 06:02:38.906410 Set Vref, RX VrefLevel [Byte0]: 62
7902 06:02:38.909449 [Byte1]: 62
7903 06:02:38.913558
7904 06:02:38.913981 Set Vref, RX VrefLevel [Byte0]: 63
7905 06:02:38.916956 [Byte1]: 63
7906 06:02:38.921391
7907 06:02:38.921878 Set Vref, RX VrefLevel [Byte0]: 64
7908 06:02:38.924430 [Byte1]: 64
7909 06:02:38.929109
7910 06:02:38.929575 Set Vref, RX VrefLevel [Byte0]: 65
7911 06:02:38.932629 [Byte1]: 65
7912 06:02:38.936802
7913 06:02:38.937217 Set Vref, RX VrefLevel [Byte0]: 66
7914 06:02:38.939498 [Byte1]: 66
7915 06:02:38.944229
7916 06:02:38.944645 Set Vref, RX VrefLevel [Byte0]: 67
7917 06:02:38.947457 [Byte1]: 67
7918 06:02:38.951797
7919 06:02:38.952214 Set Vref, RX VrefLevel [Byte0]: 68
7920 06:02:38.955267 [Byte1]: 68
7921 06:02:38.959730
7922 06:02:38.960148 Set Vref, RX VrefLevel [Byte0]: 69
7923 06:02:38.962936 [Byte1]: 69
7924 06:02:38.967071
7925 06:02:38.967485 Set Vref, RX VrefLevel [Byte0]: 70
7926 06:02:38.970206 [Byte1]: 70
7927 06:02:38.974304
7928 06:02:38.974722 Set Vref, RX VrefLevel [Byte0]: 71
7929 06:02:38.977941 [Byte1]: 71
7930 06:02:38.982132
7931 06:02:38.982548 Set Vref, RX VrefLevel [Byte0]: 72
7932 06:02:38.985730 [Byte1]: 72
7933 06:02:38.989965
7934 06:02:38.992682 Set Vref, RX VrefLevel [Byte0]: 73
7935 06:02:38.996168 [Byte1]: 73
7936 06:02:38.996590
7937 06:02:38.999607 Set Vref, RX VrefLevel [Byte0]: 74
7938 06:02:39.003290 [Byte1]: 74
7939 06:02:39.003711
7940 06:02:39.006499 Set Vref, RX VrefLevel [Byte0]: 75
7941 06:02:39.009296 [Byte1]: 75
7942 06:02:39.012364
7943 06:02:39.012445 Set Vref, RX VrefLevel [Byte0]: 76
7944 06:02:39.015419 [Byte1]: 76
7945 06:02:39.019562
7946 06:02:39.019643 Set Vref, RX VrefLevel [Byte0]: 77
7947 06:02:39.023152 [Byte1]: 77
7948 06:02:39.027691
7949 06:02:39.027771 Set Vref, RX VrefLevel [Byte0]: 78
7950 06:02:39.031266 [Byte1]: 78
7951 06:02:39.035145
7952 06:02:39.035226 Final RX Vref Byte 0 = 64 to rank0
7953 06:02:39.038673 Final RX Vref Byte 1 = 58 to rank0
7954 06:02:39.041727 Final RX Vref Byte 0 = 64 to rank1
7955 06:02:39.045007 Final RX Vref Byte 1 = 58 to rank1==
7956 06:02:39.048611 Dram Type= 6, Freq= 0, CH_0, rank 0
7957 06:02:39.055230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 06:02:39.055340 ==
7959 06:02:39.055428 DQS Delay:
7960 06:02:39.055510 DQS0 = 0, DQS1 = 0
7961 06:02:39.058557 DQM Delay:
7962 06:02:39.058667 DQM0 = 126, DQM1 = 120
7963 06:02:39.061509 DQ Delay:
7964 06:02:39.064816 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7965 06:02:39.068516 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7966 06:02:39.071400 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
7967 06:02:39.075166 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7968 06:02:39.075338
7969 06:02:39.075473
7970 06:02:39.075598
7971 06:02:39.078307 [DramC_TX_OE_Calibration] TA2
7972 06:02:39.081613 Original DQ_B0 (3 6) =30, OEN = 27
7973 06:02:39.084706 Original DQ_B1 (3 6) =30, OEN = 27
7974 06:02:39.088320 24, 0x0, End_B0=24 End_B1=24
7975 06:02:39.088624 25, 0x0, End_B0=25 End_B1=25
7976 06:02:39.091396 26, 0x0, End_B0=26 End_B1=26
7977 06:02:39.095004 27, 0x0, End_B0=27 End_B1=27
7978 06:02:39.098105 28, 0x0, End_B0=28 End_B1=28
7979 06:02:39.101871 29, 0x0, End_B0=29 End_B1=29
7980 06:02:39.102295 30, 0x0, End_B0=30 End_B1=30
7981 06:02:39.104584 31, 0x4141, End_B0=30 End_B1=30
7982 06:02:39.108130 Byte0 end_step=30 best_step=27
7983 06:02:39.111672 Byte1 end_step=30 best_step=27
7984 06:02:39.114608 Byte0 TX OE(2T, 0.5T) = (3, 3)
7985 06:02:39.117846 Byte1 TX OE(2T, 0.5T) = (3, 3)
7986 06:02:39.118262
7987 06:02:39.118587
7988 06:02:39.124738 [DQSOSCAuto] RK0, (LSB)MR18= 0x1010, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
7989 06:02:39.128155 CH0 RK0: MR19=303, MR18=1010
7990 06:02:39.134218 CH0_RK0: MR19=0x303, MR18=0x1010, DQSOSC=401, MR23=63, INC=22, DEC=15
7991 06:02:39.134546
7992 06:02:39.137469 ----->DramcWriteLeveling(PI) begin...
7993 06:02:39.137726 ==
7994 06:02:39.140930 Dram Type= 6, Freq= 0, CH_0, rank 1
7995 06:02:39.144471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7996 06:02:39.144657 ==
7997 06:02:39.147440 Write leveling (Byte 0): 33 => 33
7998 06:02:39.151080 Write leveling (Byte 1): 27 => 27
7999 06:02:39.154186 DramcWriteLeveling(PI) end<-----
8000 06:02:39.154336
8001 06:02:39.154455 ==
8002 06:02:39.157244 Dram Type= 6, Freq= 0, CH_0, rank 1
8003 06:02:39.160977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 06:02:39.163873 ==
8005 06:02:39.164023 [Gating] SW mode calibration
8006 06:02:39.170614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8007 06:02:39.177676 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8008 06:02:39.180760 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 06:02:39.187097 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 06:02:39.190991 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 06:02:39.194008 1 4 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
8012 06:02:39.200678 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8013 06:02:39.204190 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8014 06:02:39.207210 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 06:02:39.213974 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 06:02:39.216928 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 06:02:39.220541 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 06:02:39.227111 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8019 06:02:39.230723 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
8020 06:02:39.233366 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8021 06:02:39.240165 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8022 06:02:39.243635 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8023 06:02:39.246860 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 06:02:39.253214 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 06:02:39.256704 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 06:02:39.260448 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
8027 06:02:39.266469 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8028 06:02:39.269990 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (1 1) (0 0)
8029 06:02:39.273536 1 6 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8030 06:02:39.279996 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 06:02:39.283540 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 06:02:39.286613 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 06:02:39.292864 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8034 06:02:39.296487 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8035 06:02:39.299458 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8036 06:02:39.306068 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8037 06:02:39.309709 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8038 06:02:39.312821 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 06:02:39.319535 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 06:02:39.322729 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 06:02:39.326130 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 06:02:39.332789 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 06:02:39.336408 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 06:02:39.339494 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 06:02:39.345739 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 06:02:39.349183 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 06:02:39.352445 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 06:02:39.359071 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 06:02:39.362762 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 06:02:39.365961 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8051 06:02:39.372562 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8052 06:02:39.375553 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8053 06:02:39.379077 Total UI for P1: 0, mck2ui 16
8054 06:02:39.382285 best dqsien dly found for B0: ( 1, 9, 10)
8055 06:02:39.385948 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8056 06:02:39.391930 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 06:02:39.392362 Total UI for P1: 0, mck2ui 16
8058 06:02:39.398861 best dqsien dly found for B1: ( 1, 9, 18)
8059 06:02:39.402155 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8060 06:02:39.405540 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8061 06:02:39.405959
8062 06:02:39.408697 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8063 06:02:39.411873 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8064 06:02:39.415535 [Gating] SW calibration Done
8065 06:02:39.416202 ==
8066 06:02:39.418486 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 06:02:39.421983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 06:02:39.422401 ==
8069 06:02:39.425431 RX Vref Scan: 0
8070 06:02:39.425836
8071 06:02:39.426147 RX Vref 0 -> 0, step: 1
8072 06:02:39.426444
8073 06:02:39.428433 RX Delay 0 -> 252, step: 8
8074 06:02:39.431698 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8075 06:02:39.438510 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8076 06:02:39.442126 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8077 06:02:39.445127 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8078 06:02:39.448474 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8079 06:02:39.452274 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8080 06:02:39.458401 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8081 06:02:39.461668 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8082 06:02:39.465115 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8083 06:02:39.468828 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8084 06:02:39.471813 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8085 06:02:39.478558 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8086 06:02:39.481239 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8087 06:02:39.485169 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8088 06:02:39.487873 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8089 06:02:39.494493 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8090 06:02:39.495059 ==
8091 06:02:39.498011 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 06:02:39.501143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 06:02:39.501645 ==
8094 06:02:39.502005 DQS Delay:
8095 06:02:39.504516 DQS0 = 0, DQS1 = 0
8096 06:02:39.504932 DQM Delay:
8097 06:02:39.507950 DQM0 = 128, DQM1 = 121
8098 06:02:39.508369 DQ Delay:
8099 06:02:39.510827 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8100 06:02:39.514491 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8101 06:02:39.518002 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8102 06:02:39.520710 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8103 06:02:39.521126
8104 06:02:39.521454
8105 06:02:39.524555 ==
8106 06:02:39.527648 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 06:02:39.531174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 06:02:39.531595 ==
8109 06:02:39.531927
8110 06:02:39.532233
8111 06:02:39.534356 TX Vref Scan disable
8112 06:02:39.534881 == TX Byte 0 ==
8113 06:02:39.537411 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8114 06:02:39.544455 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8115 06:02:39.544877 == TX Byte 1 ==
8116 06:02:39.547703 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8117 06:02:39.554286 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8118 06:02:39.554710 ==
8119 06:02:39.557771 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 06:02:39.560610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 06:02:39.561027 ==
8122 06:02:39.575886
8123 06:02:39.579277 TX Vref early break, caculate TX vref
8124 06:02:39.582559 TX Vref=16, minBit 8, minWin=21, winSum=361
8125 06:02:39.585473 TX Vref=18, minBit 0, minWin=22, winSum=376
8126 06:02:39.589173 TX Vref=20, minBit 8, minWin=22, winSum=376
8127 06:02:39.592441 TX Vref=22, minBit 7, minWin=23, winSum=392
8128 06:02:39.595731 TX Vref=24, minBit 1, minWin=23, winSum=389
8129 06:02:39.602397 TX Vref=26, minBit 8, minWin=24, winSum=406
8130 06:02:39.605252 TX Vref=28, minBit 8, minWin=24, winSum=406
8131 06:02:39.608765 TX Vref=30, minBit 8, minWin=24, winSum=406
8132 06:02:39.612129 TX Vref=32, minBit 8, minWin=22, winSum=394
8133 06:02:39.615193 TX Vref=34, minBit 8, minWin=22, winSum=389
8134 06:02:39.618479 TX Vref=36, minBit 8, minWin=22, winSum=375
8135 06:02:39.625377 [TxChooseVref] Worse bit 8, Min win 24, Win sum 406, Final Vref 26
8136 06:02:39.625839
8137 06:02:39.628343 Final TX Range 0 Vref 26
8138 06:02:39.628762
8139 06:02:39.629091 ==
8140 06:02:39.631870 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 06:02:39.635222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 06:02:39.635642 ==
8143 06:02:39.638510
8144 06:02:39.638923
8145 06:02:39.639256 TX Vref Scan disable
8146 06:02:39.645414 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8147 06:02:39.645880 == TX Byte 0 ==
8148 06:02:39.648384 u2DelayCellOfst[0]=15 cells (4 PI)
8149 06:02:39.651661 u2DelayCellOfst[1]=18 cells (5 PI)
8150 06:02:39.655023 u2DelayCellOfst[2]=11 cells (3 PI)
8151 06:02:39.658437 u2DelayCellOfst[3]=11 cells (3 PI)
8152 06:02:39.661252 u2DelayCellOfst[4]=7 cells (2 PI)
8153 06:02:39.664783 u2DelayCellOfst[5]=0 cells (0 PI)
8154 06:02:39.668180 u2DelayCellOfst[6]=18 cells (5 PI)
8155 06:02:39.671714 u2DelayCellOfst[7]=18 cells (5 PI)
8156 06:02:39.674816 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8157 06:02:39.677999 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8158 06:02:39.681377 == TX Byte 1 ==
8159 06:02:39.685088 u2DelayCellOfst[8]=0 cells (0 PI)
8160 06:02:39.687902 u2DelayCellOfst[9]=0 cells (0 PI)
8161 06:02:39.691350 u2DelayCellOfst[10]=7 cells (2 PI)
8162 06:02:39.694834 u2DelayCellOfst[11]=3 cells (1 PI)
8163 06:02:39.698194 u2DelayCellOfst[12]=15 cells (4 PI)
8164 06:02:39.698803 u2DelayCellOfst[13]=11 cells (3 PI)
8165 06:02:39.701149 u2DelayCellOfst[14]=18 cells (5 PI)
8166 06:02:39.704676 u2DelayCellOfst[15]=15 cells (4 PI)
8167 06:02:39.711275 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8168 06:02:39.714767 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8169 06:02:39.715185 DramC Write-DBI on
8170 06:02:39.718027 ==
8171 06:02:39.721468 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 06:02:39.724646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 06:02:39.725062 ==
8174 06:02:39.725392
8175 06:02:39.725765
8176 06:02:39.728253 TX Vref Scan disable
8177 06:02:39.728666 == TX Byte 0 ==
8178 06:02:39.734557 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8179 06:02:39.735070 == TX Byte 1 ==
8180 06:02:39.737993 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8181 06:02:39.741381 DramC Write-DBI off
8182 06:02:39.741945
8183 06:02:39.742280 [DATLAT]
8184 06:02:39.744517 Freq=1600, CH0 RK1
8185 06:02:39.744933
8186 06:02:39.745261 DATLAT Default: 0xf
8187 06:02:39.748142 0, 0xFFFF, sum = 0
8188 06:02:39.748712 1, 0xFFFF, sum = 0
8189 06:02:39.751104 2, 0xFFFF, sum = 0
8190 06:02:39.751540 3, 0xFFFF, sum = 0
8191 06:02:39.754721 4, 0xFFFF, sum = 0
8192 06:02:39.755140 5, 0xFFFF, sum = 0
8193 06:02:39.758066 6, 0xFFFF, sum = 0
8194 06:02:39.758577 7, 0xFFFF, sum = 0
8195 06:02:39.761398 8, 0xFFFF, sum = 0
8196 06:02:39.764603 9, 0xFFFF, sum = 0
8197 06:02:39.765141 10, 0xFFFF, sum = 0
8198 06:02:39.768296 11, 0xFFFF, sum = 0
8199 06:02:39.768843 12, 0xFFFF, sum = 0
8200 06:02:39.771087 13, 0xCFFF, sum = 0
8201 06:02:39.771652 14, 0x0, sum = 1
8202 06:02:39.774582 15, 0x0, sum = 2
8203 06:02:39.775149 16, 0x0, sum = 3
8204 06:02:39.777957 17, 0x0, sum = 4
8205 06:02:39.778527 best_step = 15
8206 06:02:39.778893
8207 06:02:39.779230 ==
8208 06:02:39.781592 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 06:02:39.784845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 06:02:39.785403 ==
8211 06:02:39.787585 RX Vref Scan: 0
8212 06:02:39.788042
8213 06:02:39.791168 RX Vref 0 -> 0, step: 1
8214 06:02:39.791585
8215 06:02:39.791920 RX Delay 3 -> 252, step: 4
8216 06:02:39.798387 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8217 06:02:39.801601 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8218 06:02:39.805323 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8219 06:02:39.807864 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8220 06:02:39.811368 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8221 06:02:39.817961 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8222 06:02:39.820939 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8223 06:02:39.824175 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8224 06:02:39.827978 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8225 06:02:39.831296 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8226 06:02:39.837653 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8227 06:02:39.841410 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8228 06:02:39.844422 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8229 06:02:39.847884 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8230 06:02:39.854246 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8231 06:02:39.857615 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8232 06:02:39.858036 ==
8233 06:02:39.860941 Dram Type= 6, Freq= 0, CH_0, rank 1
8234 06:02:39.864260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8235 06:02:39.864678 ==
8236 06:02:39.867632 DQS Delay:
8237 06:02:39.868046 DQS0 = 0, DQS1 = 0
8238 06:02:39.868376 DQM Delay:
8239 06:02:39.870672 DQM0 = 124, DQM1 = 118
8240 06:02:39.871088 DQ Delay:
8241 06:02:39.874219 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8242 06:02:39.877140 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8243 06:02:39.883419 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
8244 06:02:39.887046 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8245 06:02:39.887460
8246 06:02:39.887789
8247 06:02:39.888092
8248 06:02:39.890311 [DramC_TX_OE_Calibration] TA2
8249 06:02:39.894031 Original DQ_B0 (3 6) =30, OEN = 27
8250 06:02:39.896974 Original DQ_B1 (3 6) =30, OEN = 27
8251 06:02:39.897391 24, 0x0, End_B0=24 End_B1=24
8252 06:02:39.900501 25, 0x0, End_B0=25 End_B1=25
8253 06:02:39.903486 26, 0x0, End_B0=26 End_B1=26
8254 06:02:39.907228 27, 0x0, End_B0=27 End_B1=27
8255 06:02:39.907652 28, 0x0, End_B0=28 End_B1=28
8256 06:02:39.910035 29, 0x0, End_B0=29 End_B1=29
8257 06:02:39.913335 30, 0x0, End_B0=30 End_B1=30
8258 06:02:39.917171 31, 0x4141, End_B0=30 End_B1=30
8259 06:02:39.920080 Byte0 end_step=30 best_step=27
8260 06:02:39.923625 Byte1 end_step=30 best_step=27
8261 06:02:39.924092 Byte0 TX OE(2T, 0.5T) = (3, 3)
8262 06:02:39.926371 Byte1 TX OE(2T, 0.5T) = (3, 3)
8263 06:02:39.926787
8264 06:02:39.927114
8265 06:02:39.936580 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8266 06:02:39.940112 CH0 RK1: MR19=303, MR18=210F
8267 06:02:39.943424 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8268 06:02:39.946621 [RxdqsGatingPostProcess] freq 1600
8269 06:02:39.953092 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8270 06:02:39.956420 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 06:02:39.959347 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 06:02:39.963278 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 06:02:39.965983 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 06:02:39.969429 best DQS0 dly(2T, 0.5T) = (1, 1)
8275 06:02:39.972617 best DQS1 dly(2T, 0.5T) = (1, 1)
8276 06:02:39.975913 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8277 06:02:39.979338 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8278 06:02:39.979758 Pre-setting of DQS Precalculation
8279 06:02:39.986032 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8280 06:02:39.986448 ==
8281 06:02:39.989694 Dram Type= 6, Freq= 0, CH_1, rank 0
8282 06:02:39.992848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 06:02:39.993271 ==
8284 06:02:39.999131 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8285 06:02:40.002569 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8286 06:02:40.006007 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8287 06:02:40.012835 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8288 06:02:40.022349 [CA 0] Center 42 (13~71) winsize 59
8289 06:02:40.025628 [CA 1] Center 42 (13~72) winsize 60
8290 06:02:40.029459 [CA 2] Center 37 (9~66) winsize 58
8291 06:02:40.032000 [CA 3] Center 37 (8~66) winsize 59
8292 06:02:40.035430 [CA 4] Center 37 (8~67) winsize 60
8293 06:02:40.038958 [CA 5] Center 36 (7~66) winsize 60
8294 06:02:40.039374
8295 06:02:40.042128 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8296 06:02:40.042542
8297 06:02:40.045092 [CATrainingPosCal] consider 1 rank data
8298 06:02:40.048535 u2DelayCellTimex100 = 258/100 ps
8299 06:02:40.051892 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8300 06:02:40.058693 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8301 06:02:40.062141 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8302 06:02:40.065624 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8303 06:02:40.068919 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8304 06:02:40.072143 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8305 06:02:40.072565
8306 06:02:40.075374 CA PerBit enable=1, Macro0, CA PI delay=36
8307 06:02:40.075790
8308 06:02:40.078536 [CBTSetCACLKResult] CA Dly = 36
8309 06:02:40.081676 CS Dly: 10 (0~41)
8310 06:02:40.085044 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8311 06:02:40.088289 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8312 06:02:40.088831 ==
8313 06:02:40.091780 Dram Type= 6, Freq= 0, CH_1, rank 1
8314 06:02:40.094850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8315 06:02:40.098109 ==
8316 06:02:40.101584 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8317 06:02:40.105323 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8318 06:02:40.111240 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8319 06:02:40.117945 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8320 06:02:40.125194 [CA 0] Center 42 (13~72) winsize 60
8321 06:02:40.128883 [CA 1] Center 42 (12~72) winsize 61
8322 06:02:40.131948 [CA 2] Center 38 (9~67) winsize 59
8323 06:02:40.135455 [CA 3] Center 36 (7~66) winsize 60
8324 06:02:40.139102 [CA 4] Center 38 (8~68) winsize 61
8325 06:02:40.142052 [CA 5] Center 36 (6~66) winsize 61
8326 06:02:40.142466
8327 06:02:40.145865 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8328 06:02:40.146276
8329 06:02:40.148757 [CATrainingPosCal] consider 2 rank data
8330 06:02:40.151794 u2DelayCellTimex100 = 258/100 ps
8331 06:02:40.155164 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8332 06:02:40.161598 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8333 06:02:40.164910 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8334 06:02:40.168382 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8335 06:02:40.171866 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8336 06:02:40.174860 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8337 06:02:40.175277
8338 06:02:40.178594 CA PerBit enable=1, Macro0, CA PI delay=36
8339 06:02:40.179011
8340 06:02:40.181609 [CBTSetCACLKResult] CA Dly = 36
8341 06:02:40.185341 CS Dly: 11 (0~43)
8342 06:02:40.188352 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8343 06:02:40.191627 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8344 06:02:40.192197
8345 06:02:40.194950 ----->DramcWriteLeveling(PI) begin...
8346 06:02:40.195457 ==
8347 06:02:40.198125 Dram Type= 6, Freq= 0, CH_1, rank 0
8348 06:02:40.204669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 06:02:40.205099 ==
8350 06:02:40.207920 Write leveling (Byte 0): 25 => 25
8351 06:02:40.208336 Write leveling (Byte 1): 27 => 27
8352 06:02:40.211399 DramcWriteLeveling(PI) end<-----
8353 06:02:40.211957
8354 06:02:40.215046 ==
8355 06:02:40.215463 Dram Type= 6, Freq= 0, CH_1, rank 0
8356 06:02:40.221188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 06:02:40.221270 ==
8358 06:02:40.224141 [Gating] SW mode calibration
8359 06:02:40.231279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8360 06:02:40.234331 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8361 06:02:40.240839 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 06:02:40.244381 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 06:02:40.247938 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 06:02:40.254241 1 4 12 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
8365 06:02:40.257286 1 4 16 | B1->B0 | 3434 3332 | 0 1 | (0 0) (0 0)
8366 06:02:40.260745 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 06:02:40.267457 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 06:02:40.270574 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 06:02:40.273838 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 06:02:40.280626 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 06:02:40.284303 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 06:02:40.287240 1 5 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
8373 06:02:40.294275 1 5 16 | B1->B0 | 2a2a 2c2c | 0 0 | (0 1) (1 0)
8374 06:02:40.297577 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 06:02:40.300400 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 06:02:40.304216 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 06:02:40.310689 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 06:02:40.314057 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 06:02:40.317206 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 06:02:40.323921 1 6 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8381 06:02:40.327159 1 6 16 | B1->B0 | 4444 4040 | 0 1 | (0 0) (0 0)
8382 06:02:40.330939 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 06:02:40.337518 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 06:02:40.340598 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 06:02:40.343931 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 06:02:40.350436 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 06:02:40.353980 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 06:02:40.356843 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 06:02:40.363802 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8390 06:02:40.366731 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8391 06:02:40.370447 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 06:02:40.377073 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 06:02:40.379905 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 06:02:40.383197 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 06:02:40.390548 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 06:02:40.393512 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 06:02:40.396673 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 06:02:40.403220 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 06:02:40.406755 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 06:02:40.409742 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 06:02:40.416529 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 06:02:40.420007 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 06:02:40.423508 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 06:02:40.429831 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8405 06:02:40.433654 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8406 06:02:40.436690 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 06:02:40.440108 Total UI for P1: 0, mck2ui 16
8408 06:02:40.443206 best dqsien dly found for B0: ( 1, 9, 14)
8409 06:02:40.446813 Total UI for P1: 0, mck2ui 16
8410 06:02:40.449792 best dqsien dly found for B1: ( 1, 9, 16)
8411 06:02:40.453441 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8412 06:02:40.456703 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8413 06:02:40.457166
8414 06:02:40.463246 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8415 06:02:40.466771 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8416 06:02:40.469913 [Gating] SW calibration Done
8417 06:02:40.470347 ==
8418 06:02:40.473567 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 06:02:40.476457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 06:02:40.476895 ==
8421 06:02:40.477336 RX Vref Scan: 0
8422 06:02:40.477895
8423 06:02:40.480051 RX Vref 0 -> 0, step: 1
8424 06:02:40.480482
8425 06:02:40.482922 RX Delay 0 -> 252, step: 8
8426 06:02:40.486382 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8427 06:02:40.489664 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8428 06:02:40.493033 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8429 06:02:40.499682 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8430 06:02:40.503292 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8431 06:02:40.506333 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8432 06:02:40.510000 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8433 06:02:40.516175 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8434 06:02:40.519290 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8435 06:02:40.523044 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8436 06:02:40.526085 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8437 06:02:40.529453 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8438 06:02:40.536232 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8439 06:02:40.539353 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8440 06:02:40.542424 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8441 06:02:40.545643 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8442 06:02:40.546094 ==
8443 06:02:40.549075 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 06:02:40.555909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 06:02:40.556432 ==
8446 06:02:40.556818 DQS Delay:
8447 06:02:40.558952 DQS0 = 0, DQS1 = 0
8448 06:02:40.559554 DQM Delay:
8449 06:02:40.559973 DQM0 = 132, DQM1 = 126
8450 06:02:40.562951 DQ Delay:
8451 06:02:40.565875 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8452 06:02:40.568849 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8453 06:02:40.572548 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8454 06:02:40.576271 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8455 06:02:40.576850
8456 06:02:40.577246
8457 06:02:40.577842 ==
8458 06:02:40.578978 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 06:02:40.585372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 06:02:40.585956 ==
8461 06:02:40.586513
8462 06:02:40.587065
8463 06:02:40.587508 TX Vref Scan disable
8464 06:02:40.588534 == TX Byte 0 ==
8465 06:02:40.592099 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8466 06:02:40.595573 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8467 06:02:40.598878 == TX Byte 1 ==
8468 06:02:40.602168 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8469 06:02:40.608650 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8470 06:02:40.609101 ==
8471 06:02:40.611639 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 06:02:40.615095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 06:02:40.615556 ==
8474 06:02:40.627349
8475 06:02:40.631111 TX Vref early break, caculate TX vref
8476 06:02:40.633969 TX Vref=16, minBit 10, minWin=22, winSum=365
8477 06:02:40.637919 TX Vref=18, minBit 11, minWin=22, winSum=374
8478 06:02:40.640840 TX Vref=20, minBit 11, minWin=22, winSum=386
8479 06:02:40.643810 TX Vref=22, minBit 5, minWin=24, winSum=396
8480 06:02:40.650804 TX Vref=24, minBit 11, minWin=24, winSum=406
8481 06:02:40.654054 TX Vref=26, minBit 1, minWin=25, winSum=417
8482 06:02:40.657362 TX Vref=28, minBit 1, minWin=25, winSum=422
8483 06:02:40.660720 TX Vref=30, minBit 0, minWin=25, winSum=417
8484 06:02:40.663553 TX Vref=32, minBit 0, minWin=24, winSum=409
8485 06:02:40.667227 TX Vref=34, minBit 0, minWin=24, winSum=399
8486 06:02:40.673169 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 28
8487 06:02:40.673661
8488 06:02:40.676772 Final TX Range 0 Vref 28
8489 06:02:40.677374
8490 06:02:40.677936 ==
8491 06:02:40.679880 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 06:02:40.683339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 06:02:40.683944 ==
8494 06:02:40.684482
8495 06:02:40.686737
8496 06:02:40.687294 TX Vref Scan disable
8497 06:02:40.693180 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8498 06:02:40.693655 == TX Byte 0 ==
8499 06:02:40.696984 u2DelayCellOfst[0]=22 cells (6 PI)
8500 06:02:40.699949 u2DelayCellOfst[1]=15 cells (4 PI)
8501 06:02:40.703077 u2DelayCellOfst[2]=0 cells (0 PI)
8502 06:02:40.706242 u2DelayCellOfst[3]=7 cells (2 PI)
8503 06:02:40.709538 u2DelayCellOfst[4]=11 cells (3 PI)
8504 06:02:40.712965 u2DelayCellOfst[5]=22 cells (6 PI)
8505 06:02:40.716361 u2DelayCellOfst[6]=18 cells (5 PI)
8506 06:02:40.719379 u2DelayCellOfst[7]=3 cells (1 PI)
8507 06:02:40.722660 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8508 06:02:40.726264 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8509 06:02:40.729315 == TX Byte 1 ==
8510 06:02:40.732725 u2DelayCellOfst[8]=0 cells (0 PI)
8511 06:02:40.736225 u2DelayCellOfst[9]=3 cells (1 PI)
8512 06:02:40.739876 u2DelayCellOfst[10]=11 cells (3 PI)
8513 06:02:40.740237 u2DelayCellOfst[11]=7 cells (2 PI)
8514 06:02:40.743133 u2DelayCellOfst[12]=15 cells (4 PI)
8515 06:02:40.746559 u2DelayCellOfst[13]=18 cells (5 PI)
8516 06:02:40.749366 u2DelayCellOfst[14]=18 cells (5 PI)
8517 06:02:40.753160 u2DelayCellOfst[15]=18 cells (5 PI)
8518 06:02:40.759634 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8519 06:02:40.763168 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8520 06:02:40.763585 DramC Write-DBI on
8521 06:02:40.763976 ==
8522 06:02:40.766487 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 06:02:40.773141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 06:02:40.773586 ==
8525 06:02:40.773923
8526 06:02:40.774231
8527 06:02:40.774527 TX Vref Scan disable
8528 06:02:40.777158 == TX Byte 0 ==
8529 06:02:40.780626 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8530 06:02:40.783587 == TX Byte 1 ==
8531 06:02:40.787009 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8532 06:02:40.790484 DramC Write-DBI off
8533 06:02:40.791054
8534 06:02:40.791513 [DATLAT]
8535 06:02:40.791843 Freq=1600, CH1 RK0
8536 06:02:40.792264
8537 06:02:40.793455 DATLAT Default: 0xf
8538 06:02:40.794105 0, 0xFFFF, sum = 0
8539 06:02:40.796887 1, 0xFFFF, sum = 0
8540 06:02:40.800393 2, 0xFFFF, sum = 0
8541 06:02:40.800960 3, 0xFFFF, sum = 0
8542 06:02:40.804032 4, 0xFFFF, sum = 0
8543 06:02:40.804620 5, 0xFFFF, sum = 0
8544 06:02:40.806888 6, 0xFFFF, sum = 0
8545 06:02:40.807414 7, 0xFFFF, sum = 0
8546 06:02:40.810485 8, 0xFFFF, sum = 0
8547 06:02:40.811015 9, 0xFFFF, sum = 0
8548 06:02:40.813392 10, 0xFFFF, sum = 0
8549 06:02:40.814019 11, 0xFFFF, sum = 0
8550 06:02:40.816797 12, 0xFFFF, sum = 0
8551 06:02:40.817362 13, 0x8FFF, sum = 0
8552 06:02:40.820037 14, 0x0, sum = 1
8553 06:02:40.820702 15, 0x0, sum = 2
8554 06:02:40.823800 16, 0x0, sum = 3
8555 06:02:40.824420 17, 0x0, sum = 4
8556 06:02:40.826770 best_step = 15
8557 06:02:40.827337
8558 06:02:40.827834 ==
8559 06:02:40.830087 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 06:02:40.833273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 06:02:40.833735 ==
8562 06:02:40.836804 RX Vref Scan: 1
8563 06:02:40.837213
8564 06:02:40.837647 Set Vref Range= 24 -> 127
8565 06:02:40.837971
8566 06:02:40.840128 RX Vref 24 -> 127, step: 1
8567 06:02:40.840536
8568 06:02:40.843350 RX Delay 11 -> 252, step: 4
8569 06:02:40.843760
8570 06:02:40.846274 Set Vref, RX VrefLevel [Byte0]: 24
8571 06:02:40.850015 [Byte1]: 24
8572 06:02:40.850431
8573 06:02:40.853029 Set Vref, RX VrefLevel [Byte0]: 25
8574 06:02:40.856498 [Byte1]: 25
8575 06:02:40.860085
8576 06:02:40.860496 Set Vref, RX VrefLevel [Byte0]: 26
8577 06:02:40.863632 [Byte1]: 26
8578 06:02:40.867487
8579 06:02:40.867898 Set Vref, RX VrefLevel [Byte0]: 27
8580 06:02:40.870910 [Byte1]: 27
8581 06:02:40.875784
8582 06:02:40.876294 Set Vref, RX VrefLevel [Byte0]: 28
8583 06:02:40.878468 [Byte1]: 28
8584 06:02:40.883012
8585 06:02:40.883426 Set Vref, RX VrefLevel [Byte0]: 29
8586 06:02:40.885966 [Byte1]: 29
8587 06:02:40.890365
8588 06:02:40.890793 Set Vref, RX VrefLevel [Byte0]: 30
8589 06:02:40.894057 [Byte1]: 30
8590 06:02:40.898283
8591 06:02:40.898826 Set Vref, RX VrefLevel [Byte0]: 31
8592 06:02:40.901936 [Byte1]: 31
8593 06:02:40.905272
8594 06:02:40.905744 Set Vref, RX VrefLevel [Byte0]: 32
8595 06:02:40.908833 [Byte1]: 32
8596 06:02:40.913512
8597 06:02:40.914038 Set Vref, RX VrefLevel [Byte0]: 33
8598 06:02:40.916391 [Byte1]: 33
8599 06:02:40.921216
8600 06:02:40.921657 Set Vref, RX VrefLevel [Byte0]: 34
8601 06:02:40.924126 [Byte1]: 34
8602 06:02:40.928988
8603 06:02:40.929403 Set Vref, RX VrefLevel [Byte0]: 35
8604 06:02:40.931931 [Byte1]: 35
8605 06:02:40.935698
8606 06:02:40.936191 Set Vref, RX VrefLevel [Byte0]: 36
8607 06:02:40.939218 [Byte1]: 36
8608 06:02:40.943566
8609 06:02:40.943981 Set Vref, RX VrefLevel [Byte0]: 37
8610 06:02:40.947330 [Byte1]: 37
8611 06:02:40.951133
8612 06:02:40.951549 Set Vref, RX VrefLevel [Byte0]: 38
8613 06:02:40.954951 [Byte1]: 38
8614 06:02:40.959044
8615 06:02:40.959496 Set Vref, RX VrefLevel [Byte0]: 39
8616 06:02:40.962197 [Byte1]: 39
8617 06:02:40.966598
8618 06:02:40.967016 Set Vref, RX VrefLevel [Byte0]: 40
8619 06:02:40.969644 [Byte1]: 40
8620 06:02:40.974428
8621 06:02:40.974843 Set Vref, RX VrefLevel [Byte0]: 41
8622 06:02:40.977610 [Byte1]: 41
8623 06:02:40.981647
8624 06:02:40.982116 Set Vref, RX VrefLevel [Byte0]: 42
8625 06:02:40.985298 [Byte1]: 42
8626 06:02:40.989374
8627 06:02:40.989853 Set Vref, RX VrefLevel [Byte0]: 43
8628 06:02:40.992502 [Byte1]: 43
8629 06:02:40.997471
8630 06:02:40.997945 Set Vref, RX VrefLevel [Byte0]: 44
8631 06:02:41.000154 [Byte1]: 44
8632 06:02:41.004864
8633 06:02:41.005387 Set Vref, RX VrefLevel [Byte0]: 45
8634 06:02:41.008249 [Byte1]: 45
8635 06:02:41.012048
8636 06:02:41.012467 Set Vref, RX VrefLevel [Byte0]: 46
8637 06:02:41.015649 [Byte1]: 46
8638 06:02:41.019674
8639 06:02:41.020090 Set Vref, RX VrefLevel [Byte0]: 47
8640 06:02:41.023330 [Byte1]: 47
8641 06:02:41.027495
8642 06:02:41.027910 Set Vref, RX VrefLevel [Byte0]: 48
8643 06:02:41.031020 [Byte1]: 48
8644 06:02:41.035117
8645 06:02:41.035534 Set Vref, RX VrefLevel [Byte0]: 49
8646 06:02:41.038140 [Byte1]: 49
8647 06:02:41.042773
8648 06:02:41.043339 Set Vref, RX VrefLevel [Byte0]: 50
8649 06:02:41.045737 [Byte1]: 50
8650 06:02:41.050590
8651 06:02:41.051009 Set Vref, RX VrefLevel [Byte0]: 51
8652 06:02:41.053452 [Byte1]: 51
8653 06:02:41.057760
8654 06:02:41.058209 Set Vref, RX VrefLevel [Byte0]: 52
8655 06:02:41.061246 [Byte1]: 52
8656 06:02:41.065931
8657 06:02:41.066347 Set Vref, RX VrefLevel [Byte0]: 53
8658 06:02:41.068954 [Byte1]: 53
8659 06:02:41.073403
8660 06:02:41.073876 Set Vref, RX VrefLevel [Byte0]: 54
8661 06:02:41.076554 [Byte1]: 54
8662 06:02:41.080506
8663 06:02:41.081028 Set Vref, RX VrefLevel [Byte0]: 55
8664 06:02:41.083990 [Byte1]: 55
8665 06:02:41.088104
8666 06:02:41.088857 Set Vref, RX VrefLevel [Byte0]: 56
8667 06:02:41.091566 [Byte1]: 56
8668 06:02:41.095916
8669 06:02:41.096347 Set Vref, RX VrefLevel [Byte0]: 57
8670 06:02:41.099501 [Byte1]: 57
8671 06:02:41.103422
8672 06:02:41.103969 Set Vref, RX VrefLevel [Byte0]: 58
8673 06:02:41.106800 [Byte1]: 58
8674 06:02:41.110843
8675 06:02:41.111257 Set Vref, RX VrefLevel [Byte0]: 59
8676 06:02:41.114268 [Byte1]: 59
8677 06:02:41.118712
8678 06:02:41.119129 Set Vref, RX VrefLevel [Byte0]: 60
8679 06:02:41.121920 [Byte1]: 60
8680 06:02:41.126139
8681 06:02:41.126561 Set Vref, RX VrefLevel [Byte0]: 61
8682 06:02:41.129893 [Byte1]: 61
8683 06:02:41.133967
8684 06:02:41.134571 Set Vref, RX VrefLevel [Byte0]: 62
8685 06:02:41.137259 [Byte1]: 62
8686 06:02:41.141549
8687 06:02:41.141969 Set Vref, RX VrefLevel [Byte0]: 63
8688 06:02:41.145067 [Byte1]: 63
8689 06:02:41.149439
8690 06:02:41.150047 Set Vref, RX VrefLevel [Byte0]: 64
8691 06:02:41.152494 [Byte1]: 64
8692 06:02:41.156702
8693 06:02:41.157116 Set Vref, RX VrefLevel [Byte0]: 65
8694 06:02:41.160294 [Byte1]: 65
8695 06:02:41.164350
8696 06:02:41.164866 Set Vref, RX VrefLevel [Byte0]: 66
8697 06:02:41.167851 [Byte1]: 66
8698 06:02:41.171957
8699 06:02:41.172371 Set Vref, RX VrefLevel [Byte0]: 67
8700 06:02:41.175563 [Byte1]: 67
8701 06:02:41.179461
8702 06:02:41.179877 Set Vref, RX VrefLevel [Byte0]: 68
8703 06:02:41.182953 [Byte1]: 68
8704 06:02:41.187205
8705 06:02:41.187623 Set Vref, RX VrefLevel [Byte0]: 69
8706 06:02:41.190970 [Byte1]: 69
8707 06:02:41.195047
8708 06:02:41.195464 Set Vref, RX VrefLevel [Byte0]: 70
8709 06:02:41.197993 [Byte1]: 70
8710 06:02:41.202566
8711 06:02:41.202982 Set Vref, RX VrefLevel [Byte0]: 71
8712 06:02:41.206095 [Byte1]: 71
8713 06:02:41.210005
8714 06:02:41.210419 Set Vref, RX VrefLevel [Byte0]: 72
8715 06:02:41.213190 [Byte1]: 72
8716 06:02:41.218052
8717 06:02:41.218469 Set Vref, RX VrefLevel [Byte0]: 73
8718 06:02:41.221104 [Byte1]: 73
8719 06:02:41.225321
8720 06:02:41.225909 Final RX Vref Byte 0 = 57 to rank0
8721 06:02:41.228621 Final RX Vref Byte 1 = 53 to rank0
8722 06:02:41.232097 Final RX Vref Byte 0 = 57 to rank1
8723 06:02:41.235282 Final RX Vref Byte 1 = 53 to rank1==
8724 06:02:41.238900 Dram Type= 6, Freq= 0, CH_1, rank 0
8725 06:02:41.245329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 06:02:41.245815 ==
8727 06:02:41.246152 DQS Delay:
8728 06:02:41.246461 DQS0 = 0, DQS1 = 0
8729 06:02:41.248904 DQM Delay:
8730 06:02:41.249316 DQM0 = 130, DQM1 = 123
8731 06:02:41.251948 DQ Delay:
8732 06:02:41.255225 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8733 06:02:41.258298 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =128
8734 06:02:41.262029 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8735 06:02:41.265042 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8736 06:02:41.265459
8737 06:02:41.265843
8738 06:02:41.266154
8739 06:02:41.268467 [DramC_TX_OE_Calibration] TA2
8740 06:02:41.271958 Original DQ_B0 (3 6) =30, OEN = 27
8741 06:02:41.275187 Original DQ_B1 (3 6) =30, OEN = 27
8742 06:02:41.278547 24, 0x0, End_B0=24 End_B1=24
8743 06:02:41.279006 25, 0x0, End_B0=25 End_B1=25
8744 06:02:41.281390 26, 0x0, End_B0=26 End_B1=26
8745 06:02:41.284993 27, 0x0, End_B0=27 End_B1=27
8746 06:02:41.288497 28, 0x0, End_B0=28 End_B1=28
8747 06:02:41.291952 29, 0x0, End_B0=29 End_B1=29
8748 06:02:41.292411 30, 0x0, End_B0=30 End_B1=30
8749 06:02:41.295156 31, 0x4141, End_B0=30 End_B1=30
8750 06:02:41.298226 Byte0 end_step=30 best_step=27
8751 06:02:41.301182 Byte1 end_step=30 best_step=27
8752 06:02:41.304547 Byte0 TX OE(2T, 0.5T) = (3, 3)
8753 06:02:41.308714 Byte1 TX OE(2T, 0.5T) = (3, 3)
8754 06:02:41.309236
8755 06:02:41.309628
8756 06:02:41.314605 [DQSOSCAuto] RK0, (LSB)MR18= 0x80d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8757 06:02:41.318132 CH1 RK0: MR19=303, MR18=80D
8758 06:02:41.324575 CH1_RK0: MR19=0x303, MR18=0x80D, DQSOSC=403, MR23=63, INC=22, DEC=15
8759 06:02:41.325122
8760 06:02:41.328223 ----->DramcWriteLeveling(PI) begin...
8761 06:02:41.328742 ==
8762 06:02:41.331171 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 06:02:41.334157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 06:02:41.334582 ==
8765 06:02:41.337776 Write leveling (Byte 0): 23 => 23
8766 06:02:41.341435 Write leveling (Byte 1): 27 => 27
8767 06:02:41.344649 DramcWriteLeveling(PI) end<-----
8768 06:02:41.345154
8769 06:02:41.345539 ==
8770 06:02:41.347600 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 06:02:41.351066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 06:02:41.351579 ==
8773 06:02:41.354356 [Gating] SW mode calibration
8774 06:02:41.361428 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8775 06:02:41.367779 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8776 06:02:41.371002 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 06:02:41.377591 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 06:02:41.380644 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 0)
8779 06:02:41.384509 1 4 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
8780 06:02:41.390920 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 06:02:41.394120 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 06:02:41.397406 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 06:02:41.403964 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 06:02:41.406963 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 06:02:41.410950 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8786 06:02:41.417407 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
8787 06:02:41.420681 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8788 06:02:41.423762 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 06:02:41.430305 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 06:02:41.433391 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 06:02:41.436962 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 06:02:41.440625 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 06:02:41.447364 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8794 06:02:41.450598 1 6 8 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
8795 06:02:41.453974 1 6 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8796 06:02:41.460450 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 06:02:41.463349 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 06:02:41.466478 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 06:02:41.473360 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 06:02:41.477099 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 06:02:41.480001 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 06:02:41.486681 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8803 06:02:41.490047 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8804 06:02:41.493076 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 06:02:41.499489 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 06:02:41.502946 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 06:02:41.506413 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 06:02:41.513121 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 06:02:41.516115 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 06:02:41.519924 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 06:02:41.526400 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 06:02:41.529963 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 06:02:41.532344 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 06:02:41.538992 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 06:02:41.542475 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 06:02:41.546219 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 06:02:41.552535 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 06:02:41.556068 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8819 06:02:41.559103 Total UI for P1: 0, mck2ui 16
8820 06:02:41.562628 best dqsien dly found for B0: ( 1, 9, 6)
8821 06:02:41.565826 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8822 06:02:41.572448 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 06:02:41.575848 Total UI for P1: 0, mck2ui 16
8824 06:02:41.579203 best dqsien dly found for B1: ( 1, 9, 10)
8825 06:02:41.582418 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8826 06:02:41.585880 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8827 06:02:41.586438
8828 06:02:41.589408 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8829 06:02:41.592334 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8830 06:02:41.595620 [Gating] SW calibration Done
8831 06:02:41.596173 ==
8832 06:02:41.598416 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 06:02:41.602247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 06:02:41.602974 ==
8835 06:02:41.605460 RX Vref Scan: 0
8836 06:02:41.606055
8837 06:02:41.608916 RX Vref 0 -> 0, step: 1
8838 06:02:41.609469
8839 06:02:41.609883 RX Delay 0 -> 252, step: 8
8840 06:02:41.615192 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8841 06:02:41.618660 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8842 06:02:41.621519 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8843 06:02:41.624966 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8844 06:02:41.628650 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8845 06:02:41.635014 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8846 06:02:41.638445 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8847 06:02:41.641601 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8848 06:02:41.644955 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8849 06:02:41.648903 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8850 06:02:41.655040 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8851 06:02:41.658229 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8852 06:02:41.661516 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8853 06:02:41.664778 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8854 06:02:41.671047 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8855 06:02:41.674736 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8856 06:02:41.675430 ==
8857 06:02:41.677649 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 06:02:41.681044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 06:02:41.681520 ==
8860 06:02:41.681965 DQS Delay:
8861 06:02:41.684616 DQS0 = 0, DQS1 = 0
8862 06:02:41.685041 DQM Delay:
8863 06:02:41.687895 DQM0 = 132, DQM1 = 127
8864 06:02:41.688320 DQ Delay:
8865 06:02:41.690885 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8866 06:02:41.694514 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =131
8867 06:02:41.697863 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8868 06:02:41.704144 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8869 06:02:41.704618
8870 06:02:41.705044
8871 06:02:41.705391 ==
8872 06:02:41.707460 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 06:02:41.710768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 06:02:41.711248 ==
8875 06:02:41.711699
8876 06:02:41.712157
8877 06:02:41.714253 TX Vref Scan disable
8878 06:02:41.714668 == TX Byte 0 ==
8879 06:02:41.720564 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8880 06:02:41.724157 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8881 06:02:41.724572 == TX Byte 1 ==
8882 06:02:41.730790 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8883 06:02:41.733904 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8884 06:02:41.734319 ==
8885 06:02:41.737749 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 06:02:41.740747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 06:02:41.741165 ==
8888 06:02:41.756178
8889 06:02:41.758960 TX Vref early break, caculate TX vref
8890 06:02:41.762409 TX Vref=16, minBit 0, minWin=22, winSum=380
8891 06:02:41.765968 TX Vref=18, minBit 0, minWin=23, winSum=388
8892 06:02:41.769061 TX Vref=20, minBit 0, minWin=23, winSum=398
8893 06:02:41.772544 TX Vref=22, minBit 0, minWin=23, winSum=404
8894 06:02:41.775920 TX Vref=24, minBit 5, minWin=24, winSum=413
8895 06:02:41.782307 TX Vref=26, minBit 0, minWin=25, winSum=420
8896 06:02:41.785650 TX Vref=28, minBit 5, minWin=24, winSum=420
8897 06:02:41.788955 TX Vref=30, minBit 0, minWin=25, winSum=419
8898 06:02:41.792047 TX Vref=32, minBit 0, minWin=24, winSum=411
8899 06:02:41.795559 TX Vref=34, minBit 0, minWin=23, winSum=400
8900 06:02:41.799365 TX Vref=36, minBit 1, minWin=22, winSum=389
8901 06:02:41.805761 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 26
8902 06:02:41.806293
8903 06:02:41.808571 Final TX Range 0 Vref 26
8904 06:02:41.809147
8905 06:02:41.809571 ==
8906 06:02:41.812449 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 06:02:41.815580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 06:02:41.816088 ==
8909 06:02:41.816628
8910 06:02:41.817200
8911 06:02:41.819303 TX Vref Scan disable
8912 06:02:41.825715 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8913 06:02:41.826245 == TX Byte 0 ==
8914 06:02:41.828721 u2DelayCellOfst[0]=18 cells (5 PI)
8915 06:02:41.832047 u2DelayCellOfst[1]=11 cells (3 PI)
8916 06:02:41.835759 u2DelayCellOfst[2]=0 cells (0 PI)
8917 06:02:41.839015 u2DelayCellOfst[3]=3 cells (1 PI)
8918 06:02:41.842467 u2DelayCellOfst[4]=7 cells (2 PI)
8919 06:02:41.845328 u2DelayCellOfst[5]=18 cells (5 PI)
8920 06:02:41.848896 u2DelayCellOfst[6]=18 cells (5 PI)
8921 06:02:41.852279 u2DelayCellOfst[7]=3 cells (1 PI)
8922 06:02:41.855614 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8923 06:02:41.859026 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8924 06:02:41.861821 == TX Byte 1 ==
8925 06:02:41.865082 u2DelayCellOfst[8]=0 cells (0 PI)
8926 06:02:41.865541 u2DelayCellOfst[9]=7 cells (2 PI)
8927 06:02:41.868378 u2DelayCellOfst[10]=11 cells (3 PI)
8928 06:02:41.872046 u2DelayCellOfst[11]=7 cells (2 PI)
8929 06:02:41.874967 u2DelayCellOfst[12]=15 cells (4 PI)
8930 06:02:41.878188 u2DelayCellOfst[13]=18 cells (5 PI)
8931 06:02:41.881653 u2DelayCellOfst[14]=22 cells (6 PI)
8932 06:02:41.885171 u2DelayCellOfst[15]=18 cells (5 PI)
8933 06:02:41.891828 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8934 06:02:41.894885 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8935 06:02:41.895064 DramC Write-DBI on
8936 06:02:41.895228 ==
8937 06:02:41.898513 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 06:02:41.904452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 06:02:41.904633 ==
8940 06:02:41.904779
8941 06:02:41.904911
8942 06:02:41.905038 TX Vref Scan disable
8943 06:02:41.908633 == TX Byte 0 ==
8944 06:02:41.912307 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8945 06:02:41.915382 == TX Byte 1 ==
8946 06:02:41.918921 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8947 06:02:41.921814 DramC Write-DBI off
8948 06:02:41.922134
8949 06:02:41.922419 [DATLAT]
8950 06:02:41.922666 Freq=1600, CH1 RK1
8951 06:02:41.922900
8952 06:02:41.925444 DATLAT Default: 0xf
8953 06:02:41.928373 0, 0xFFFF, sum = 0
8954 06:02:41.928815 1, 0xFFFF, sum = 0
8955 06:02:41.932052 2, 0xFFFF, sum = 0
8956 06:02:41.932652 3, 0xFFFF, sum = 0
8957 06:02:41.935473 4, 0xFFFF, sum = 0
8958 06:02:41.935912 5, 0xFFFF, sum = 0
8959 06:02:41.938620 6, 0xFFFF, sum = 0
8960 06:02:41.939045 7, 0xFFFF, sum = 0
8961 06:02:41.941760 8, 0xFFFF, sum = 0
8962 06:02:41.942187 9, 0xFFFF, sum = 0
8963 06:02:41.945232 10, 0xFFFF, sum = 0
8964 06:02:41.945700 11, 0xFFFF, sum = 0
8965 06:02:41.948343 12, 0xFFFF, sum = 0
8966 06:02:41.948853 13, 0x8FFF, sum = 0
8967 06:02:41.951918 14, 0x0, sum = 1
8968 06:02:41.952340 15, 0x0, sum = 2
8969 06:02:41.955163 16, 0x0, sum = 3
8970 06:02:41.955589 17, 0x0, sum = 4
8971 06:02:41.958553 best_step = 15
8972 06:02:41.958972
8973 06:02:41.959306 ==
8974 06:02:41.961738 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 06:02:41.965170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 06:02:41.965642 ==
8977 06:02:41.968197 RX Vref Scan: 0
8978 06:02:41.968617
8979 06:02:41.968948 RX Vref 0 -> 0, step: 1
8980 06:02:41.969259
8981 06:02:41.971456 RX Delay 11 -> 252, step: 4
8982 06:02:41.978113 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8983 06:02:41.981614 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8984 06:02:41.985045 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8985 06:02:41.988170 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8986 06:02:41.991562 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8987 06:02:41.998363 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8988 06:02:42.001030 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8989 06:02:42.004715 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8990 06:02:42.007478 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8991 06:02:42.011116 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
8992 06:02:42.017688 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8993 06:02:42.020624 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8994 06:02:42.024051 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8995 06:02:42.027579 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8996 06:02:42.030595 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8997 06:02:42.037380 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8998 06:02:42.037461 ==
8999 06:02:42.040400 Dram Type= 6, Freq= 0, CH_1, rank 1
9000 06:02:42.043648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9001 06:02:42.043729 ==
9002 06:02:42.043793 DQS Delay:
9003 06:02:42.047416 DQS0 = 0, DQS1 = 0
9004 06:02:42.047497 DQM Delay:
9005 06:02:42.050915 DQM0 = 129, DQM1 = 125
9006 06:02:42.050995 DQ Delay:
9007 06:02:42.054094 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =126
9008 06:02:42.057151 DQ4 =126, DQ5 =140, DQ6 =140, DQ7 =124
9009 06:02:42.060364 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
9010 06:02:42.067175 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =134
9011 06:02:42.067262
9012 06:02:42.067331
9013 06:02:42.067394
9014 06:02:42.067455 [DramC_TX_OE_Calibration] TA2
9015 06:02:42.070655 Original DQ_B0 (3 6) =30, OEN = 27
9016 06:02:42.074129 Original DQ_B1 (3 6) =30, OEN = 27
9017 06:02:42.077084 24, 0x0, End_B0=24 End_B1=24
9018 06:02:42.080784 25, 0x0, End_B0=25 End_B1=25
9019 06:02:42.083680 26, 0x0, End_B0=26 End_B1=26
9020 06:02:42.083799 27, 0x0, End_B0=27 End_B1=27
9021 06:02:42.087382 28, 0x0, End_B0=28 End_B1=28
9022 06:02:42.090589 29, 0x0, End_B0=29 End_B1=29
9023 06:02:42.093619 30, 0x0, End_B0=30 End_B1=30
9024 06:02:42.097330 31, 0x4141, End_B0=30 End_B1=30
9025 06:02:42.100255 Byte0 end_step=30 best_step=27
9026 06:02:42.100420 Byte1 end_step=30 best_step=27
9027 06:02:42.103732 Byte0 TX OE(2T, 0.5T) = (3, 3)
9028 06:02:42.106812 Byte1 TX OE(2T, 0.5T) = (3, 3)
9029 06:02:42.107012
9030 06:02:42.107170
9031 06:02:42.117252 [DQSOSCAuto] RK1, (LSB)MR18= 0x101c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9032 06:02:42.117583 CH1 RK1: MR19=303, MR18=101C
9033 06:02:42.123493 CH1_RK1: MR19=0x303, MR18=0x101C, DQSOSC=395, MR23=63, INC=23, DEC=15
9034 06:02:42.126865 [RxdqsGatingPostProcess] freq 1600
9035 06:02:42.133941 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9036 06:02:42.136700 best DQS0 dly(2T, 0.5T) = (1, 1)
9037 06:02:42.140261 best DQS1 dly(2T, 0.5T) = (1, 1)
9038 06:02:42.143636 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9039 06:02:42.147059 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9040 06:02:42.147479 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 06:02:42.150312 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 06:02:42.153459 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 06:02:42.157239 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 06:02:42.160170 Pre-setting of DQS Precalculation
9045 06:02:42.167396 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9046 06:02:42.173656 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9047 06:02:42.180458 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9048 06:02:42.181025
9049 06:02:42.181366
9050 06:02:42.183522 [Calibration Summary] 3200 Mbps
9051 06:02:42.183942 CH 0, Rank 0
9052 06:02:42.186774 SW Impedance : PASS
9053 06:02:42.190371 DUTY Scan : NO K
9054 06:02:42.190881 ZQ Calibration : PASS
9055 06:02:42.193438 Jitter Meter : NO K
9056 06:02:42.196793 CBT Training : PASS
9057 06:02:42.197210 Write leveling : PASS
9058 06:02:42.200636 RX DQS gating : PASS
9059 06:02:42.204530 RX DQ/DQS(RDDQC) : PASS
9060 06:02:42.205046 TX DQ/DQS : PASS
9061 06:02:42.206420 RX DATLAT : PASS
9062 06:02:42.209980 RX DQ/DQS(Engine): PASS
9063 06:02:42.210497 TX OE : PASS
9064 06:02:42.210838 All Pass.
9065 06:02:42.213185
9066 06:02:42.213658 CH 0, Rank 1
9067 06:02:42.216494 SW Impedance : PASS
9068 06:02:42.217082 DUTY Scan : NO K
9069 06:02:42.219743 ZQ Calibration : PASS
9070 06:02:42.223149 Jitter Meter : NO K
9071 06:02:42.223567 CBT Training : PASS
9072 06:02:42.226705 Write leveling : PASS
9073 06:02:42.227126 RX DQS gating : PASS
9074 06:02:42.230229 RX DQ/DQS(RDDQC) : PASS
9075 06:02:42.233201 TX DQ/DQS : PASS
9076 06:02:42.233771 RX DATLAT : PASS
9077 06:02:42.236327 RX DQ/DQS(Engine): PASS
9078 06:02:42.239657 TX OE : PASS
9079 06:02:42.240077 All Pass.
9080 06:02:42.240412
9081 06:02:42.240720 CH 1, Rank 0
9082 06:02:42.243503 SW Impedance : PASS
9083 06:02:42.246663 DUTY Scan : NO K
9084 06:02:42.247184 ZQ Calibration : PASS
9085 06:02:42.249432 Jitter Meter : NO K
9086 06:02:42.253258 CBT Training : PASS
9087 06:02:42.253841 Write leveling : PASS
9088 06:02:42.256237 RX DQS gating : PASS
9089 06:02:42.259950 RX DQ/DQS(RDDQC) : PASS
9090 06:02:42.260459 TX DQ/DQS : PASS
9091 06:02:42.262875 RX DATLAT : PASS
9092 06:02:42.266429 RX DQ/DQS(Engine): PASS
9093 06:02:42.266845 TX OE : PASS
9094 06:02:42.269896 All Pass.
9095 06:02:42.270428
9096 06:02:42.270763 CH 1, Rank 1
9097 06:02:42.272596 SW Impedance : PASS
9098 06:02:42.273013 DUTY Scan : NO K
9099 06:02:42.276263 ZQ Calibration : PASS
9100 06:02:42.279749 Jitter Meter : NO K
9101 06:02:42.280256 CBT Training : PASS
9102 06:02:42.282296 Write leveling : PASS
9103 06:02:42.285989 RX DQS gating : PASS
9104 06:02:42.286405 RX DQ/DQS(RDDQC) : PASS
9105 06:02:42.289200 TX DQ/DQS : PASS
9106 06:02:42.289750 RX DATLAT : PASS
9107 06:02:42.292621 RX DQ/DQS(Engine): PASS
9108 06:02:42.295669 TX OE : PASS
9109 06:02:42.296137 All Pass.
9110 06:02:42.296469
9111 06:02:42.298979 DramC Write-DBI on
9112 06:02:42.299392 PER_BANK_REFRESH: Hybrid Mode
9113 06:02:42.302518 TX_TRACKING: ON
9114 06:02:42.312246 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9115 06:02:42.319121 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9116 06:02:42.326101 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9117 06:02:42.329131 [FAST_K] Save calibration result to emmc
9118 06:02:42.332589 sync common calibartion params.
9119 06:02:42.335584 sync cbt_mode0:1, 1:1
9120 06:02:42.338381 dram_init: ddr_geometry: 2
9121 06:02:42.338803 dram_init: ddr_geometry: 2
9122 06:02:42.342228 dram_init: ddr_geometry: 2
9123 06:02:42.345452 0:dram_rank_size:100000000
9124 06:02:42.346020 1:dram_rank_size:100000000
9125 06:02:42.352042 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9126 06:02:42.355043 DFS_SHUFFLE_HW_MODE: ON
9127 06:02:42.358580 dramc_set_vcore_voltage set vcore to 725000
9128 06:02:42.362090 Read voltage for 1600, 0
9129 06:02:42.362510 Vio18 = 0
9130 06:02:42.362843 Vcore = 725000
9131 06:02:42.365353 Vdram = 0
9132 06:02:42.365821 Vddq = 0
9133 06:02:42.366155 Vmddr = 0
9134 06:02:42.368846 switch to 3200 Mbps bootup
9135 06:02:42.369356 [DramcRunTimeConfig]
9136 06:02:42.372109 PHYPLL
9137 06:02:42.372559 DPM_CONTROL_AFTERK: ON
9138 06:02:42.375425 PER_BANK_REFRESH: ON
9139 06:02:42.379009 REFRESH_OVERHEAD_REDUCTION: ON
9140 06:02:42.379518 CMD_PICG_NEW_MODE: OFF
9141 06:02:42.381889 XRTWTW_NEW_MODE: ON
9142 06:02:42.382400 XRTRTR_NEW_MODE: ON
9143 06:02:42.385134 TX_TRACKING: ON
9144 06:02:42.385627 RDSEL_TRACKING: OFF
9145 06:02:42.388560 DQS Precalculation for DVFS: ON
9146 06:02:42.391860 RX_TRACKING: OFF
9147 06:02:42.392281 HW_GATING DBG: ON
9148 06:02:42.395113 ZQCS_ENABLE_LP4: ON
9149 06:02:42.395529 RX_PICG_NEW_MODE: ON
9150 06:02:42.398399 TX_PICG_NEW_MODE: ON
9151 06:02:42.401646 ENABLE_RX_DCM_DPHY: ON
9152 06:02:42.402224 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9153 06:02:42.405233 DUMMY_READ_FOR_TRACKING: OFF
9154 06:02:42.408879 !!! SPM_CONTROL_AFTERK: OFF
9155 06:02:42.411648 !!! SPM could not control APHY
9156 06:02:42.412165 IMPEDANCE_TRACKING: ON
9157 06:02:42.415074 TEMP_SENSOR: ON
9158 06:02:42.415588 HW_SAVE_FOR_SR: OFF
9159 06:02:42.418309 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9160 06:02:42.425414 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9161 06:02:42.426001 Read ODT Tracking: ON
9162 06:02:42.428282 Refresh Rate DeBounce: ON
9163 06:02:42.428791 DFS_NO_QUEUE_FLUSH: ON
9164 06:02:42.431844 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9165 06:02:42.434503 ENABLE_DFS_RUNTIME_MRW: OFF
9166 06:02:42.437881 DDR_RESERVE_NEW_MODE: ON
9167 06:02:42.438301 MR_CBT_SWITCH_FREQ: ON
9168 06:02:42.441380 =========================
9169 06:02:42.460493 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9170 06:02:42.464144 dram_init: ddr_geometry: 2
9171 06:02:42.482273 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9172 06:02:42.485425 dram_init: dram init end (result: 0)
9173 06:02:42.492504 DRAM-K: Full calibration passed in 24600 msecs
9174 06:02:42.496086 MRC: failed to locate region type 0.
9175 06:02:42.496643 DRAM rank0 size:0x100000000,
9176 06:02:42.498790 DRAM rank1 size=0x100000000
9177 06:02:42.508747 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9178 06:02:42.515830 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9179 06:02:42.522292 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9180 06:02:42.529318 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9181 06:02:42.532122 DRAM rank0 size:0x100000000,
9182 06:02:42.535415 DRAM rank1 size=0x100000000
9183 06:02:42.535876 CBMEM:
9184 06:02:42.538938 IMD: root @ 0xfffff000 254 entries.
9185 06:02:42.541986 IMD: root @ 0xffffec00 62 entries.
9186 06:02:42.545776 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9187 06:02:42.549267 WARNING: RO_VPD is uninitialized or empty.
9188 06:02:42.555626 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9189 06:02:42.562514 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9190 06:02:42.575165 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9191 06:02:42.586362 BS: romstage times (exec / console): total (unknown) / 24063 ms
9192 06:02:42.586968
9193 06:02:42.587339
9194 06:02:42.596266 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9195 06:02:42.599486 ARM64: Exception handlers installed.
9196 06:02:42.603023 ARM64: Testing exception
9197 06:02:42.606300 ARM64: Done test exception
9198 06:02:42.606859 Enumerating buses...
9199 06:02:42.609389 Show all devs... Before device enumeration.
9200 06:02:42.613080 Root Device: enabled 1
9201 06:02:42.616459 CPU_CLUSTER: 0: enabled 1
9202 06:02:42.617012 CPU: 00: enabled 1
9203 06:02:42.619728 Compare with tree...
9204 06:02:42.620281 Root Device: enabled 1
9205 06:02:42.622847 CPU_CLUSTER: 0: enabled 1
9206 06:02:42.626078 CPU: 00: enabled 1
9207 06:02:42.626629 Root Device scanning...
9208 06:02:42.629590 scan_static_bus for Root Device
9209 06:02:42.632511 CPU_CLUSTER: 0 enabled
9210 06:02:42.635699 scan_static_bus for Root Device done
9211 06:02:42.639046 scan_bus: bus Root Device finished in 8 msecs
9212 06:02:42.639510 done
9213 06:02:42.645710 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9214 06:02:42.649647 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9215 06:02:42.655922 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9216 06:02:42.659044 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9217 06:02:42.662345 Allocating resources...
9218 06:02:42.665288 Reading resources...
9219 06:02:42.669246 Root Device read_resources bus 0 link: 0
9220 06:02:42.672444 DRAM rank0 size:0x100000000,
9221 06:02:42.672864 DRAM rank1 size=0x100000000
9222 06:02:42.676081 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9223 06:02:42.678545 CPU: 00 missing read_resources
9224 06:02:42.685363 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9225 06:02:42.688645 Root Device read_resources bus 0 link: 0 done
9226 06:02:42.689155 Done reading resources.
9227 06:02:42.695318 Show resources in subtree (Root Device)...After reading.
9228 06:02:42.698421 Root Device child on link 0 CPU_CLUSTER: 0
9229 06:02:42.701725 CPU_CLUSTER: 0 child on link 0 CPU: 00
9230 06:02:42.711848 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9231 06:02:42.712353 CPU: 00
9232 06:02:42.715197 Root Device assign_resources, bus 0 link: 0
9233 06:02:42.718817 CPU_CLUSTER: 0 missing set_resources
9234 06:02:42.725176 Root Device assign_resources, bus 0 link: 0 done
9235 06:02:42.725761 Done setting resources.
9236 06:02:42.731981 Show resources in subtree (Root Device)...After assigning values.
9237 06:02:42.735601 Root Device child on link 0 CPU_CLUSTER: 0
9238 06:02:42.738065 CPU_CLUSTER: 0 child on link 0 CPU: 00
9239 06:02:42.748737 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9240 06:02:42.749243 CPU: 00
9241 06:02:42.751632 Done allocating resources.
9242 06:02:42.758364 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9243 06:02:42.758875 Enabling resources...
9244 06:02:42.759238 done.
9245 06:02:42.764801 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9246 06:02:42.768387 Initializing devices...
9247 06:02:42.768892 Root Device init
9248 06:02:42.771522 init hardware done!
9249 06:02:42.771940 0x00000018: ctrlr->caps
9250 06:02:42.774702 52.000 MHz: ctrlr->f_max
9251 06:02:42.778282 0.400 MHz: ctrlr->f_min
9252 06:02:42.778800 0x40ff8080: ctrlr->voltages
9253 06:02:42.781909 sclk: 390625
9254 06:02:42.782480 Bus Width = 1
9255 06:02:42.782822 sclk: 390625
9256 06:02:42.785212 Bus Width = 1
9257 06:02:42.785781 Early init status = 3
9258 06:02:42.791425 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9259 06:02:42.794849 in-header: 03 fc 00 00 01 00 00 00
9260 06:02:42.798324 in-data: 00
9261 06:02:42.801170 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9262 06:02:42.805293 in-header: 03 fd 00 00 00 00 00 00
9263 06:02:42.808144 in-data:
9264 06:02:42.811661 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9265 06:02:42.814975 in-header: 03 fc 00 00 01 00 00 00
9266 06:02:42.818521 in-data: 00
9267 06:02:42.821894 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9268 06:02:42.826447 in-header: 03 fd 00 00 00 00 00 00
9269 06:02:42.830110 in-data:
9270 06:02:42.832910 [SSUSB] Setting up USB HOST controller...
9271 06:02:42.835945 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9272 06:02:42.839617 [SSUSB] phy power-on done.
9273 06:02:42.842824 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9274 06:02:42.849807 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9275 06:02:42.853140 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9276 06:02:42.859577 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9277 06:02:42.866025 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9278 06:02:42.872289 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9279 06:02:42.879078 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9280 06:02:42.885391 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9281 06:02:42.888892 SPM: binary array size = 0x9dc
9282 06:02:42.892088 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9283 06:02:42.898957 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9284 06:02:42.905391 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9285 06:02:42.912107 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9286 06:02:42.915325 configure_display: Starting display init
9287 06:02:42.949737 anx7625_power_on_init: Init interface.
9288 06:02:42.952785 anx7625_disable_pd_protocol: Disabled PD feature.
9289 06:02:42.956128 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9290 06:02:42.984272 anx7625_start_dp_work: Secure OCM version=00
9291 06:02:42.987477 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9292 06:02:43.001936 sp_tx_get_edid_block: EDID Block = 1
9293 06:02:43.104766 Extracted contents:
9294 06:02:43.108044 header: 00 ff ff ff ff ff ff 00
9295 06:02:43.111698 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9296 06:02:43.114468 version: 01 04
9297 06:02:43.118059 basic params: 95 1f 11 78 0a
9298 06:02:43.121306 chroma info: 76 90 94 55 54 90 27 21 50 54
9299 06:02:43.124831 established: 00 00 00
9300 06:02:43.131186 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9301 06:02:43.134319 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9302 06:02:43.140775 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9303 06:02:43.148050 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9304 06:02:43.154033 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9305 06:02:43.157426 extensions: 00
9306 06:02:43.157977 checksum: fb
9307 06:02:43.158419
9308 06:02:43.160804 Manufacturer: IVO Model 57d Serial Number 0
9309 06:02:43.164308 Made week 0 of 2020
9310 06:02:43.167641 EDID version: 1.4
9311 06:02:43.168162 Digital display
9312 06:02:43.170871 6 bits per primary color channel
9313 06:02:43.171385 DisplayPort interface
9314 06:02:43.173966 Maximum image size: 31 cm x 17 cm
9315 06:02:43.177024 Gamma: 220%
9316 06:02:43.177566 Check DPMS levels
9317 06:02:43.180376 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9318 06:02:43.187186 First detailed timing is preferred timing
9319 06:02:43.187605 Established timings supported:
9320 06:02:43.190386 Standard timings supported:
9321 06:02:43.193957 Detailed timings
9322 06:02:43.197597 Hex of detail: 383680a07038204018303c0035ae10000019
9323 06:02:43.203740 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9324 06:02:43.207548 0780 0798 07c8 0820 hborder 0
9325 06:02:43.210385 0438 043b 0447 0458 vborder 0
9326 06:02:43.213660 -hsync -vsync
9327 06:02:43.214077 Did detailed timing
9328 06:02:43.220077 Hex of detail: 000000000000000000000000000000000000
9329 06:02:43.223371 Manufacturer-specified data, tag 0
9330 06:02:43.226952 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9331 06:02:43.229908 ASCII string: InfoVision
9332 06:02:43.233466 Hex of detail: 000000fe00523134304e574635205248200a
9333 06:02:43.236724 ASCII string: R140NWF5 RH
9334 06:02:43.237142 Checksum
9335 06:02:43.239970 Checksum: 0xfb (valid)
9336 06:02:43.243445 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9337 06:02:43.246910 DSI data_rate: 832800000 bps
9338 06:02:43.253379 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9339 06:02:43.257194 anx7625_parse_edid: pixelclock(138800).
9340 06:02:43.260205 hactive(1920), hsync(48), hfp(24), hbp(88)
9341 06:02:43.263505 vactive(1080), vsync(12), vfp(3), vbp(17)
9342 06:02:43.266601 anx7625_dsi_config: config dsi.
9343 06:02:43.273170 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9344 06:02:43.286813 anx7625_dsi_config: success to config DSI
9345 06:02:43.289874 anx7625_dp_start: MIPI phy setup OK.
9346 06:02:43.293139 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9347 06:02:43.296365 mtk_ddp_mode_set invalid vrefresh 60
9348 06:02:43.299848 main_disp_path_setup
9349 06:02:43.300388 ovl_layer_smi_id_en
9350 06:02:43.302856 ovl_layer_smi_id_en
9351 06:02:43.303269 ccorr_config
9352 06:02:43.303594 aal_config
9353 06:02:43.306186 gamma_config
9354 06:02:43.306610 postmask_config
9355 06:02:43.309693 dither_config
9356 06:02:43.313623 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9357 06:02:43.319501 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9358 06:02:43.323333 Root Device init finished in 551 msecs
9359 06:02:43.326579 CPU_CLUSTER: 0 init
9360 06:02:43.333615 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9361 06:02:43.336559 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9362 06:02:43.340036 APU_MBOX 0x190000b0 = 0x10001
9363 06:02:43.343488 APU_MBOX 0x190001b0 = 0x10001
9364 06:02:43.346122 APU_MBOX 0x190005b0 = 0x10001
9365 06:02:43.349360 APU_MBOX 0x190006b0 = 0x10001
9366 06:02:43.352951 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9367 06:02:43.366037 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9368 06:02:43.378256 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9369 06:02:43.385155 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9370 06:02:43.396725 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9371 06:02:43.405537 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9372 06:02:43.409089 CPU_CLUSTER: 0 init finished in 81 msecs
9373 06:02:43.412286 Devices initialized
9374 06:02:43.415451 Show all devs... After init.
9375 06:02:43.415963 Root Device: enabled 1
9376 06:02:43.418925 CPU_CLUSTER: 0: enabled 1
9377 06:02:43.422488 CPU: 00: enabled 1
9378 06:02:43.424973 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9379 06:02:43.428263 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9380 06:02:43.431612 ELOG: NV offset 0x57f000 size 0x1000
9381 06:02:43.438279 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9382 06:02:43.445233 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9383 06:02:43.448052 ELOG: Event(17) added with size 13 at 2023-12-25 06:02:43 UTC
9384 06:02:43.454901 out: cmd=0x121: 03 db 21 01 00 00 00 00
9385 06:02:43.458112 in-header: 03 3f 00 00 2c 00 00 00
9386 06:02:43.471590 in-data: 1f 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9387 06:02:43.474554 ELOG: Event(A1) added with size 10 at 2023-12-25 06:02:43 UTC
9388 06:02:43.484134 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9389 06:02:43.487590 ELOG: Event(A0) added with size 9 at 2023-12-25 06:02:43 UTC
9390 06:02:43.491026 elog_add_boot_reason: Logged dev mode boot
9391 06:02:43.498298 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9392 06:02:43.498842 Finalize devices...
9393 06:02:43.501179 Devices finalized
9394 06:02:43.504648 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9395 06:02:43.507634 Writing coreboot table at 0xffe64000
9396 06:02:43.514696 0. 000000000010a000-0000000000113fff: RAMSTAGE
9397 06:02:43.517775 1. 0000000040000000-00000000400fffff: RAM
9398 06:02:43.521690 2. 0000000040100000-000000004032afff: RAMSTAGE
9399 06:02:43.524767 3. 000000004032b000-00000000545fffff: RAM
9400 06:02:43.527909 4. 0000000054600000-000000005465ffff: BL31
9401 06:02:43.534213 5. 0000000054660000-00000000ffe63fff: RAM
9402 06:02:43.537691 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9403 06:02:43.541054 7. 0000000100000000-000000023fffffff: RAM
9404 06:02:43.544709 Passing 5 GPIOs to payload:
9405 06:02:43.548032 NAME | PORT | POLARITY | VALUE
9406 06:02:43.554178 EC in RW | 0x000000aa | low | undefined
9407 06:02:43.557653 EC interrupt | 0x00000005 | low | undefined
9408 06:02:43.564284 TPM interrupt | 0x000000ab | high | undefined
9409 06:02:43.567689 SD card detect | 0x00000011 | high | undefined
9410 06:02:43.574357 speaker enable | 0x00000093 | high | undefined
9411 06:02:43.577312 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9412 06:02:43.580848 in-header: 03 f9 00 00 02 00 00 00
9413 06:02:43.581359 in-data: 02 00
9414 06:02:43.583874 ADC[4]: Raw value=895191 ID=7
9415 06:02:43.587267 ADC[3]: Raw value=213440 ID=1
9416 06:02:43.587683 RAM Code: 0x71
9417 06:02:43.590887 ADC[6]: Raw value=74722 ID=0
9418 06:02:43.594046 ADC[5]: Raw value=212330 ID=1
9419 06:02:43.594464 SKU Code: 0x1
9420 06:02:43.600761 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4d57
9421 06:02:43.604245 coreboot table: 964 bytes.
9422 06:02:43.606951 IMD ROOT 0. 0xfffff000 0x00001000
9423 06:02:43.610633 IMD SMALL 1. 0xffffe000 0x00001000
9424 06:02:43.613544 RO MCACHE 2. 0xffffc000 0x00001104
9425 06:02:43.616842 CONSOLE 3. 0xfff7c000 0x00080000
9426 06:02:43.620355 FMAP 4. 0xfff7b000 0x00000452
9427 06:02:43.623536 TIME STAMP 5. 0xfff7a000 0x00000910
9428 06:02:43.626638 VBOOT WORK 6. 0xfff66000 0x00014000
9429 06:02:43.630033 RAMOOPS 7. 0xffe66000 0x00100000
9430 06:02:43.633290 COREBOOT 8. 0xffe64000 0x00002000
9431 06:02:43.633815 IMD small region:
9432 06:02:43.636899 IMD ROOT 0. 0xffffec00 0x00000400
9433 06:02:43.639913 VPD 1. 0xffffeb80 0x0000006c
9434 06:02:43.643018 MMC STATUS 2. 0xffffeb60 0x00000004
9435 06:02:43.649751 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9436 06:02:43.650191 Probing TPM: done!
9437 06:02:43.657046 Connected to device vid:did:rid of 1ae0:0028:00
9438 06:02:43.662881 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9439 06:02:43.670391 Initialized TPM device CR50 revision 0
9440 06:02:43.670893 Checking cr50 for pending updates
9441 06:02:43.676667 Reading cr50 TPM mode
9442 06:02:43.684869 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9443 06:02:43.691627 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9444 06:02:43.731929 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9445 06:02:43.735320 Checking segment from ROM address 0x40100000
9446 06:02:43.738584 Checking segment from ROM address 0x4010001c
9447 06:02:43.745606 Loading segment from ROM address 0x40100000
9448 06:02:43.746103 code (compression=0)
9449 06:02:43.752330 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9450 06:02:43.762008 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9451 06:02:43.762508 it's not compressed!
9452 06:02:43.768410 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9453 06:02:43.771768 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9454 06:02:43.792404 Loading segment from ROM address 0x4010001c
9455 06:02:43.792920 Entry Point 0x80000000
9456 06:02:43.795606 Loaded segments
9457 06:02:43.798732 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9458 06:02:43.805570 Jumping to boot code at 0x80000000(0xffe64000)
9459 06:02:43.812244 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9460 06:02:43.818948 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9461 06:02:43.826405 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9462 06:02:43.829748 Checking segment from ROM address 0x40100000
9463 06:02:43.833414 Checking segment from ROM address 0x4010001c
9464 06:02:43.839585 Loading segment from ROM address 0x40100000
9465 06:02:43.840082 code (compression=1)
9466 06:02:43.846593 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9467 06:02:43.856782 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9468 06:02:43.857298 using LZMA
9469 06:02:43.864741 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9470 06:02:43.871731 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9471 06:02:43.875186 Loading segment from ROM address 0x4010001c
9472 06:02:43.875755 Entry Point 0x54601000
9473 06:02:43.878524 Loaded segments
9474 06:02:43.881449 NOTICE: MT8192 bl31_setup
9475 06:02:43.888449 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9476 06:02:43.892206 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9477 06:02:43.895507 WARNING: region 0:
9478 06:02:43.898311 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 06:02:43.898726 WARNING: region 1:
9480 06:02:43.905572 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9481 06:02:43.908534 WARNING: region 2:
9482 06:02:43.911846 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9483 06:02:43.915152 WARNING: region 3:
9484 06:02:43.918486 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9485 06:02:43.922122 WARNING: region 4:
9486 06:02:43.928948 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9487 06:02:43.929458 WARNING: region 5:
9488 06:02:43.931836 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 06:02:43.934966 WARNING: region 6:
9490 06:02:43.938581 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 06:02:43.941717 WARNING: region 7:
9492 06:02:43.944803 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 06:02:43.951536 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9494 06:02:43.955248 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9495 06:02:43.958537 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9496 06:02:43.964766 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9497 06:02:43.968184 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9498 06:02:43.971522 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9499 06:02:43.978186 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9500 06:02:43.981594 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9501 06:02:43.988037 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9502 06:02:43.991776 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9503 06:02:43.994729 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9504 06:02:44.001239 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9505 06:02:44.004868 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9506 06:02:44.007917 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9507 06:02:44.014627 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9508 06:02:44.018309 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9509 06:02:44.024625 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9510 06:02:44.027824 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9511 06:02:44.031210 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9512 06:02:44.038200 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9513 06:02:44.041557 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9514 06:02:44.044994 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9515 06:02:44.051654 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9516 06:02:44.054420 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9517 06:02:44.061517 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9518 06:02:44.064865 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9519 06:02:44.068026 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9520 06:02:44.075191 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9521 06:02:44.078361 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9522 06:02:44.084783 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9523 06:02:44.088515 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9524 06:02:44.092050 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9525 06:02:44.098065 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9526 06:02:44.101257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9527 06:02:44.104882 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9528 06:02:44.108295 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9529 06:02:44.114808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9530 06:02:44.118144 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9531 06:02:44.121472 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9532 06:02:44.124903 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9533 06:02:44.131726 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9534 06:02:44.134715 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9535 06:02:44.137906 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9536 06:02:44.141432 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9537 06:02:44.147809 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9538 06:02:44.151517 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9539 06:02:44.154414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9540 06:02:44.157618 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9541 06:02:44.164418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9542 06:02:44.167900 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9543 06:02:44.174773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9544 06:02:44.177686 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9545 06:02:44.184109 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9546 06:02:44.187612 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9547 06:02:44.191174 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9548 06:02:44.197681 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9549 06:02:44.201225 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9550 06:02:44.207745 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9551 06:02:44.211107 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9552 06:02:44.217152 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9553 06:02:44.220678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9554 06:02:44.227498 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9555 06:02:44.230711 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9556 06:02:44.233908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9557 06:02:44.241102 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9558 06:02:44.244332 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9559 06:02:44.250731 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9560 06:02:44.254074 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9561 06:02:44.260752 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9562 06:02:44.264257 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9563 06:02:44.267393 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9564 06:02:44.274657 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9565 06:02:44.277384 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9566 06:02:44.284144 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9567 06:02:44.287540 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9568 06:02:44.293871 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9569 06:02:44.297546 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9570 06:02:44.300930 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9571 06:02:44.307420 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9572 06:02:44.310951 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9573 06:02:44.317804 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9574 06:02:44.320738 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9575 06:02:44.327381 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9576 06:02:44.330811 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9577 06:02:44.333754 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9578 06:02:44.340460 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9579 06:02:44.344003 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9580 06:02:44.350485 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9581 06:02:44.353954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9582 06:02:44.360425 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9583 06:02:44.363914 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9584 06:02:44.366944 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9585 06:02:44.373715 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9586 06:02:44.377068 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9587 06:02:44.383962 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9588 06:02:44.386911 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9589 06:02:44.393790 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9590 06:02:44.397121 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9591 06:02:44.400098 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9592 06:02:44.403761 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9593 06:02:44.410245 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9594 06:02:44.413759 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9595 06:02:44.416749 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9596 06:02:44.423937 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9597 06:02:44.427246 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9598 06:02:44.430520 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9599 06:02:44.436783 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9600 06:02:44.440529 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9601 06:02:44.446935 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9602 06:02:44.450520 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9603 06:02:44.453377 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9604 06:02:44.460426 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9605 06:02:44.463838 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9606 06:02:44.470528 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9607 06:02:44.474026 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9608 06:02:44.476998 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9609 06:02:44.483876 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9610 06:02:44.487112 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9611 06:02:44.490292 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9612 06:02:44.496760 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9613 06:02:44.500213 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9614 06:02:44.503992 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9615 06:02:44.506951 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9616 06:02:44.513821 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9617 06:02:44.517296 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9618 06:02:44.520223 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9619 06:02:44.527428 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9620 06:02:44.530326 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9621 06:02:44.536817 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9622 06:02:44.540396 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9623 06:02:44.543614 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9624 06:02:44.550342 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9625 06:02:44.553956 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9626 06:02:44.556886 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9627 06:02:44.563729 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9628 06:02:44.567397 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9629 06:02:44.573723 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9630 06:02:44.577176 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9631 06:02:44.580684 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9632 06:02:44.587221 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9633 06:02:44.591039 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9634 06:02:44.597512 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9635 06:02:44.600432 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9636 06:02:44.604067 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9637 06:02:44.610667 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9638 06:02:44.613759 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9639 06:02:44.617022 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9640 06:02:44.624322 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9641 06:02:44.627212 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9642 06:02:44.634191 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9643 06:02:44.637305 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9644 06:02:44.640763 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9645 06:02:44.648020 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9646 06:02:44.650934 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9647 06:02:44.654479 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9648 06:02:44.660893 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9649 06:02:44.664065 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9650 06:02:44.670835 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9651 06:02:44.674449 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9652 06:02:44.677448 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9653 06:02:44.684325 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9654 06:02:44.687288 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9655 06:02:44.693872 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9656 06:02:44.697177 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9657 06:02:44.700698 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9658 06:02:44.707572 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9659 06:02:44.710777 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9660 06:02:44.716877 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9661 06:02:44.720229 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9662 06:02:44.723343 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9663 06:02:44.730173 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9664 06:02:44.733963 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9665 06:02:44.740396 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9666 06:02:44.743858 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9667 06:02:44.746639 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9668 06:02:44.753823 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9669 06:02:44.756687 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9670 06:02:44.763576 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9671 06:02:44.766425 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9672 06:02:44.770001 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9673 06:02:44.776983 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9674 06:02:44.780353 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9675 06:02:44.786559 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9676 06:02:44.789705 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9677 06:02:44.793254 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9678 06:02:44.800077 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9679 06:02:44.803532 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9680 06:02:44.810102 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9681 06:02:44.813070 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9682 06:02:44.816467 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9683 06:02:44.823399 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9684 06:02:44.826328 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9685 06:02:44.832710 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9686 06:02:44.836062 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9687 06:02:44.839889 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9688 06:02:44.846064 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9689 06:02:44.849680 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9690 06:02:44.856509 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9691 06:02:44.859984 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9692 06:02:44.866124 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9693 06:02:44.869573 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9694 06:02:44.873043 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9695 06:02:44.879580 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9696 06:02:44.883041 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9697 06:02:44.889130 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9698 06:02:44.893049 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9699 06:02:44.899461 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9700 06:02:44.903144 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9701 06:02:44.905926 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9702 06:02:44.912674 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9703 06:02:44.915924 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9704 06:02:44.922445 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9705 06:02:44.926092 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9706 06:02:44.929097 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9707 06:02:44.935711 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9708 06:02:44.938932 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9709 06:02:44.945621 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9710 06:02:44.949311 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9711 06:02:44.955978 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9712 06:02:44.959051 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9713 06:02:44.962248 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9714 06:02:44.968741 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9715 06:02:44.972741 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9716 06:02:44.978680 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9717 06:02:44.982021 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9718 06:02:44.985927 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9719 06:02:44.992418 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9720 06:02:44.995326 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9721 06:02:45.002150 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9722 06:02:45.006056 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9723 06:02:45.008846 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9724 06:02:45.012401 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9725 06:02:45.018823 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9726 06:02:45.022315 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9727 06:02:45.025257 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9728 06:02:45.031762 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9729 06:02:45.034965 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9730 06:02:45.038409 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9731 06:02:45.044851 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9732 06:02:45.047873 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9733 06:02:45.055065 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9734 06:02:45.058364 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9735 06:02:45.061467 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9736 06:02:45.067790 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9737 06:02:45.071310 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9738 06:02:45.074543 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9739 06:02:45.081645 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9740 06:02:45.084518 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9741 06:02:45.087842 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9742 06:02:45.094682 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9743 06:02:45.097438 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9744 06:02:45.104520 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9745 06:02:45.108021 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9746 06:02:45.111536 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9747 06:02:45.117867 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9748 06:02:45.121033 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9749 06:02:45.127851 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9750 06:02:45.131215 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9751 06:02:45.134410 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9752 06:02:45.140882 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9753 06:02:45.144235 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9754 06:02:45.147524 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9755 06:02:45.154134 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9756 06:02:45.157169 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9757 06:02:45.160620 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9758 06:02:45.167167 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9759 06:02:45.170384 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9760 06:02:45.177206 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9761 06:02:45.180325 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9762 06:02:45.183406 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9763 06:02:45.186955 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9764 06:02:45.193395 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9765 06:02:45.196916 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9766 06:02:45.200290 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9767 06:02:45.203342 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9768 06:02:45.209756 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9769 06:02:45.213391 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9770 06:02:45.216268 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9771 06:02:45.219964 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9772 06:02:45.226624 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9773 06:02:45.229967 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9774 06:02:45.232786 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9775 06:02:45.239202 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9776 06:02:45.243029 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9777 06:02:45.249133 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9778 06:02:45.252691 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9779 06:02:45.256282 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9780 06:02:45.262830 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9781 06:02:45.266150 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9782 06:02:45.269603 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9783 06:02:45.276351 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9784 06:02:45.279453 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9785 06:02:45.285949 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9786 06:02:45.289523 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9787 06:02:45.296403 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9788 06:02:45.299204 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9789 06:02:45.302318 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9790 06:02:45.309180 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9791 06:02:45.312459 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9792 06:02:45.319014 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9793 06:02:45.322257 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9794 06:02:45.325832 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9795 06:02:45.332297 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9796 06:02:45.335979 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9797 06:02:45.342177 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9798 06:02:45.345782 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9799 06:02:45.348855 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9800 06:02:45.355720 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9801 06:02:45.358668 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9802 06:02:45.365253 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9803 06:02:45.369074 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9804 06:02:45.375364 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9805 06:02:45.378967 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9806 06:02:45.381857 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9807 06:02:45.388923 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9808 06:02:45.392058 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9809 06:02:45.398581 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9810 06:02:45.402135 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9811 06:02:45.408886 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9812 06:02:45.411790 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9813 06:02:45.415257 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9814 06:02:45.421760 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9815 06:02:45.425288 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9816 06:02:45.431611 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9817 06:02:45.434869 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9818 06:02:45.438249 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9819 06:02:45.445212 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9820 06:02:45.448134 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9821 06:02:45.455057 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9822 06:02:45.458199 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9823 06:02:45.461797 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9824 06:02:45.468448 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9825 06:02:45.471682 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9826 06:02:45.478110 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9827 06:02:45.481728 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9828 06:02:45.487998 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9829 06:02:45.491351 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9830 06:02:45.494838 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9831 06:02:45.501615 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9832 06:02:45.505220 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9833 06:02:45.511157 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9834 06:02:45.514929 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9835 06:02:45.517893 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9836 06:02:45.524241 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9837 06:02:45.527377 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9838 06:02:45.534352 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9839 06:02:45.537535 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9840 06:02:45.540974 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9841 06:02:45.547525 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9842 06:02:45.550632 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9843 06:02:45.557332 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9844 06:02:45.560709 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9845 06:02:45.567694 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9846 06:02:45.570786 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9847 06:02:45.574173 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9848 06:02:45.580818 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9849 06:02:45.583742 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9850 06:02:45.590424 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9851 06:02:45.593824 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9852 06:02:45.600420 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9853 06:02:45.603965 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9854 06:02:45.606844 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9855 06:02:45.613744 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9856 06:02:45.616724 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9857 06:02:45.623522 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9858 06:02:45.626935 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9859 06:02:45.633527 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9860 06:02:45.637109 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9861 06:02:45.643308 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9862 06:02:45.646555 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9863 06:02:45.650136 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9864 06:02:45.656634 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9865 06:02:45.660234 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9866 06:02:45.666355 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9867 06:02:45.670050 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9868 06:02:45.676863 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9869 06:02:45.679857 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9870 06:02:45.683164 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9871 06:02:45.689591 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9872 06:02:45.692920 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9873 06:02:45.699227 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9874 06:02:45.702669 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9875 06:02:45.709352 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9876 06:02:45.712854 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9877 06:02:45.719136 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9878 06:02:45.722823 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9879 06:02:45.726477 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9880 06:02:45.732470 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9881 06:02:45.736048 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9882 06:02:45.742469 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9883 06:02:45.745989 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9884 06:02:45.752711 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9885 06:02:45.755845 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9886 06:02:45.759130 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9887 06:02:45.765925 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9888 06:02:45.768754 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9889 06:02:45.775810 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9890 06:02:45.779063 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9891 06:02:45.785701 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9892 06:02:45.789175 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9893 06:02:45.795145 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9894 06:02:45.798578 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9895 06:02:45.801780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9896 06:02:45.809038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9897 06:02:45.812197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9898 06:02:45.818587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9899 06:02:45.822082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9900 06:02:45.829012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9901 06:02:45.831800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9902 06:02:45.838553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9903 06:02:45.841980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9904 06:02:45.848340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9905 06:02:45.851287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9906 06:02:45.858441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9907 06:02:45.861715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9908 06:02:45.867970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9909 06:02:45.872017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9910 06:02:45.878407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9911 06:02:45.881861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9912 06:02:45.884741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9913 06:02:45.891530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9914 06:02:45.894886 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9915 06:02:45.901470 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9916 06:02:45.904969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9917 06:02:45.911724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9918 06:02:45.914630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9919 06:02:45.921436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9920 06:02:45.924643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9921 06:02:45.931192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9922 06:02:45.937847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9923 06:02:45.941131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9924 06:02:45.947604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9925 06:02:45.951039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9926 06:02:45.957987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9927 06:02:45.960852 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9928 06:02:45.961266 INFO: [APUAPC] vio 0
9929 06:02:45.968235 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9930 06:02:45.971749 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9931 06:02:45.974956 INFO: [APUAPC] D0_APC_0: 0x400510
9932 06:02:45.978440 INFO: [APUAPC] D0_APC_1: 0x0
9933 06:02:45.981766 INFO: [APUAPC] D0_APC_2: 0x1540
9934 06:02:45.984826 INFO: [APUAPC] D0_APC_3: 0x0
9935 06:02:45.988415 INFO: [APUAPC] D1_APC_0: 0xffffffff
9936 06:02:45.991678 INFO: [APUAPC] D1_APC_1: 0xffffffff
9937 06:02:45.994995 INFO: [APUAPC] D1_APC_2: 0x3fffff
9938 06:02:45.998359 INFO: [APUAPC] D1_APC_3: 0x0
9939 06:02:46.001771 INFO: [APUAPC] D2_APC_0: 0xffffffff
9940 06:02:46.004797 INFO: [APUAPC] D2_APC_1: 0xffffffff
9941 06:02:46.008384 INFO: [APUAPC] D2_APC_2: 0x3fffff
9942 06:02:46.011417 INFO: [APUAPC] D2_APC_3: 0x0
9943 06:02:46.014552 INFO: [APUAPC] D3_APC_0: 0xffffffff
9944 06:02:46.018184 INFO: [APUAPC] D3_APC_1: 0xffffffff
9945 06:02:46.021682 INFO: [APUAPC] D3_APC_2: 0x3fffff
9946 06:02:46.024684 INFO: [APUAPC] D3_APC_3: 0x0
9947 06:02:46.028024 INFO: [APUAPC] D4_APC_0: 0xffffffff
9948 06:02:46.031113 INFO: [APUAPC] D4_APC_1: 0xffffffff
9949 06:02:46.034693 INFO: [APUAPC] D4_APC_2: 0x3fffff
9950 06:02:46.035204 INFO: [APUAPC] D4_APC_3: 0x0
9951 06:02:46.041201 INFO: [APUAPC] D5_APC_0: 0xffffffff
9952 06:02:46.044638 INFO: [APUAPC] D5_APC_1: 0xffffffff
9953 06:02:46.047602 INFO: [APUAPC] D5_APC_2: 0x3fffff
9954 06:02:46.048014 INFO: [APUAPC] D5_APC_3: 0x0
9955 06:02:46.051357 INFO: [APUAPC] D6_APC_0: 0xffffffff
9956 06:02:46.054619 INFO: [APUAPC] D6_APC_1: 0xffffffff
9957 06:02:46.057694 INFO: [APUAPC] D6_APC_2: 0x3fffff
9958 06:02:46.060999 INFO: [APUAPC] D6_APC_3: 0x0
9959 06:02:46.064304 INFO: [APUAPC] D7_APC_0: 0xffffffff
9960 06:02:46.067634 INFO: [APUAPC] D7_APC_1: 0xffffffff
9961 06:02:46.071133 INFO: [APUAPC] D7_APC_2: 0x3fffff
9962 06:02:46.074733 INFO: [APUAPC] D7_APC_3: 0x0
9963 06:02:46.077456 INFO: [APUAPC] D8_APC_0: 0xffffffff
9964 06:02:46.080461 INFO: [APUAPC] D8_APC_1: 0xffffffff
9965 06:02:46.083938 INFO: [APUAPC] D8_APC_2: 0x3fffff
9966 06:02:46.087460 INFO: [APUAPC] D8_APC_3: 0x0
9967 06:02:46.090520 INFO: [APUAPC] D9_APC_0: 0xffffffff
9968 06:02:46.094126 INFO: [APUAPC] D9_APC_1: 0xffffffff
9969 06:02:46.097304 INFO: [APUAPC] D9_APC_2: 0x3fffff
9970 06:02:46.100791 INFO: [APUAPC] D9_APC_3: 0x0
9971 06:02:46.103897 INFO: [APUAPC] D10_APC_0: 0xffffffff
9972 06:02:46.107265 INFO: [APUAPC] D10_APC_1: 0xffffffff
9973 06:02:46.110511 INFO: [APUAPC] D10_APC_2: 0x3fffff
9974 06:02:46.113505 INFO: [APUAPC] D10_APC_3: 0x0
9975 06:02:46.116812 INFO: [APUAPC] D11_APC_0: 0xffffffff
9976 06:02:46.120114 INFO: [APUAPC] D11_APC_1: 0xffffffff
9977 06:02:46.123298 INFO: [APUAPC] D11_APC_2: 0x3fffff
9978 06:02:46.126801 INFO: [APUAPC] D11_APC_3: 0x0
9979 06:02:46.129743 INFO: [APUAPC] D12_APC_0: 0xffffffff
9980 06:02:46.132891 INFO: [APUAPC] D12_APC_1: 0xffffffff
9981 06:02:46.136345 INFO: [APUAPC] D12_APC_2: 0x3fffff
9982 06:02:46.139826 INFO: [APUAPC] D12_APC_3: 0x0
9983 06:02:46.143358 INFO: [APUAPC] D13_APC_0: 0xffffffff
9984 06:02:46.149720 INFO: [APUAPC] D13_APC_1: 0xffffffff
9985 06:02:46.153019 INFO: [APUAPC] D13_APC_2: 0x3fffff
9986 06:02:46.153108 INFO: [APUAPC] D13_APC_3: 0x0
9987 06:02:46.156615 INFO: [APUAPC] D14_APC_0: 0xffffffff
9988 06:02:46.162593 INFO: [APUAPC] D14_APC_1: 0xffffffff
9989 06:02:46.166544 INFO: [APUAPC] D14_APC_2: 0x3fffff
9990 06:02:46.166648 INFO: [APUAPC] D14_APC_3: 0x0
9991 06:02:46.169463 INFO: [APUAPC] D15_APC_0: 0xffffffff
9992 06:02:46.176059 INFO: [APUAPC] D15_APC_1: 0xffffffff
9993 06:02:46.179639 INFO: [APUAPC] D15_APC_2: 0x3fffff
9994 06:02:46.179727 INFO: [APUAPC] D15_APC_3: 0x0
9995 06:02:46.183218 INFO: [APUAPC] APC_CON: 0x4
9996 06:02:46.186168 INFO: [NOCDAPC] D0_APC_0: 0x0
9997 06:02:46.189707 INFO: [NOCDAPC] D0_APC_1: 0x0
9998 06:02:46.192536 INFO: [NOCDAPC] D1_APC_0: 0x0
9999 06:02:46.196136 INFO: [NOCDAPC] D1_APC_1: 0xfff
10000 06:02:46.199617 INFO: [NOCDAPC] D2_APC_0: 0x0
10001 06:02:46.202522 INFO: [NOCDAPC] D2_APC_1: 0xfff
10002 06:02:46.206188 INFO: [NOCDAPC] D3_APC_0: 0x0
10003 06:02:46.209468 INFO: [NOCDAPC] D3_APC_1: 0xfff
10004 06:02:46.209544 INFO: [NOCDAPC] D4_APC_0: 0x0
10005 06:02:46.212610 INFO: [NOCDAPC] D4_APC_1: 0xfff
10006 06:02:46.216012 INFO: [NOCDAPC] D5_APC_0: 0x0
10007 06:02:46.219196 INFO: [NOCDAPC] D5_APC_1: 0xfff
10008 06:02:46.222267 INFO: [NOCDAPC] D6_APC_0: 0x0
10009 06:02:46.225747 INFO: [NOCDAPC] D6_APC_1: 0xfff
10010 06:02:46.228845 INFO: [NOCDAPC] D7_APC_0: 0x0
10011 06:02:46.232570 INFO: [NOCDAPC] D7_APC_1: 0xfff
10012 06:02:46.236264 INFO: [NOCDAPC] D8_APC_0: 0x0
10013 06:02:46.239126 INFO: [NOCDAPC] D8_APC_1: 0xfff
10014 06:02:46.242509 INFO: [NOCDAPC] D9_APC_0: 0x0
10015 06:02:46.242617 INFO: [NOCDAPC] D9_APC_1: 0xfff
10016 06:02:46.246067 INFO: [NOCDAPC] D10_APC_0: 0x0
10017 06:02:46.249091 INFO: [NOCDAPC] D10_APC_1: 0xfff
10018 06:02:46.252294 INFO: [NOCDAPC] D11_APC_0: 0x0
10019 06:02:46.256034 INFO: [NOCDAPC] D11_APC_1: 0xfff
10020 06:02:46.259655 INFO: [NOCDAPC] D12_APC_0: 0x0
10021 06:02:46.262805 INFO: [NOCDAPC] D12_APC_1: 0xfff
10022 06:02:46.265769 INFO: [NOCDAPC] D13_APC_0: 0x0
10023 06:02:46.269337 INFO: [NOCDAPC] D13_APC_1: 0xfff
10024 06:02:46.272432 INFO: [NOCDAPC] D14_APC_0: 0x0
10025 06:02:46.276051 INFO: [NOCDAPC] D14_APC_1: 0xfff
10026 06:02:46.279080 INFO: [NOCDAPC] D15_APC_0: 0x0
10027 06:02:46.282642 INFO: [NOCDAPC] D15_APC_1: 0xfff
10028 06:02:46.286215 INFO: [NOCDAPC] APC_CON: 0x4
10029 06:02:46.289283 INFO: [APUAPC] set_apusys_apc done
10030 06:02:46.289790 INFO: [DEVAPC] devapc_init done
10031 06:02:46.296320 INFO: GICv3 without legacy support detected.
10032 06:02:46.299177 INFO: ARM GICv3 driver initialized in EL3
10033 06:02:46.302874 INFO: Maximum SPI INTID supported: 639
10034 06:02:46.305743 INFO: BL31: Initializing runtime services
10035 06:02:46.312274 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10036 06:02:46.316053 INFO: SPM: enable CPC mode
10037 06:02:46.319551 INFO: mcdi ready for mcusys-off-idle and system suspend
10038 06:02:46.326032 INFO: BL31: Preparing for EL3 exit to normal world
10039 06:02:46.329331 INFO: Entry point address = 0x80000000
10040 06:02:46.329859 INFO: SPSR = 0x8
10041 06:02:46.336424
10042 06:02:46.336879
10043 06:02:46.337327
10044 06:02:46.339947 Starting depthcharge on Spherion...
10045 06:02:46.340474
10046 06:02:46.340919 Wipe memory regions:
10047 06:02:46.341438
10048 06:02:46.344338 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10049 06:02:46.344875 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10050 06:02:46.345359 Setting prompt string to ['asurada:']
10051 06:02:46.345856 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10052 06:02:46.346674 [0x00000040000000, 0x00000054600000)
10053 06:02:46.465548
10054 06:02:46.466115 [0x00000054660000, 0x00000080000000)
10055 06:02:46.726081
10056 06:02:46.726565 [0x000000821a7280, 0x000000ffe64000)
10057 06:02:47.470621
10058 06:02:47.471115 [0x00000100000000, 0x00000240000000)
10059 06:02:49.361168
10060 06:02:49.364172 Initializing XHCI USB controller at 0x11200000.
10061 06:02:50.401792
10062 06:02:50.404906 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10063 06:02:50.405322
10064 06:02:50.405695
10065 06:02:50.406003
10066 06:02:50.406730 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10068 06:02:50.507831 asurada: tftpboot 192.168.201.1 12379478/tftp-deploy-13tqp04d/kernel/image.itb 12379478/tftp-deploy-13tqp04d/kernel/cmdline
10069 06:02:50.508472 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10070 06:02:50.508938 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10071 06:02:50.513632 tftpboot 192.168.201.1 12379478/tftp-deploy-13tqp04d/kernel/image.ittp-deploy-13tqp04d/kernel/cmdline
10072 06:02:50.514048
10073 06:02:50.514374 Waiting for link
10074 06:02:50.673414
10075 06:02:50.674066 R8152: Initializing
10076 06:02:50.674566
10077 06:02:50.676871 Version 6 (ocp_data = 5c30)
10078 06:02:50.677332
10079 06:02:50.680383 R8152: Done initializing
10080 06:02:50.680832
10081 06:02:50.681285 Adding net device
10082 06:02:52.612198
10083 06:02:52.612358 done.
10084 06:02:52.612457
10085 06:02:52.612538 MAC: 00:24:32:30:78:ff
10086 06:02:52.612634
10087 06:02:52.615641 Sending DHCP discover... done.
10088 06:02:52.615742
10089 06:02:52.618528 Waiting for reply... done.
10090 06:02:52.618612
10091 06:02:52.621834 Sending DHCP request... done.
10092 06:02:52.621918
10093 06:02:52.627003 Waiting for reply... done.
10094 06:02:52.627086
10095 06:02:52.627171 My ip is 192.168.201.21
10096 06:02:52.627251
10097 06:02:52.630426 The DHCP server ip is 192.168.201.1
10098 06:02:52.630510
10099 06:02:52.636780 TFTP server IP predefined by user: 192.168.201.1
10100 06:02:52.636863
10101 06:02:52.643592 Bootfile predefined by user: 12379478/tftp-deploy-13tqp04d/kernel/image.itb
10102 06:02:52.643675
10103 06:02:52.647002 Sending tftp read request... done.
10104 06:02:52.647084
10105 06:02:52.650923 Waiting for the transfer...
10106 06:02:52.651004
10107 06:02:53.227597 00000000 ################################################################
10108 06:02:53.227770
10109 06:02:53.765695 00080000 ################################################################
10110 06:02:53.765867
10111 06:02:54.299332 00100000 ################################################################
10112 06:02:54.299478
10113 06:02:54.850044 00180000 ################################################################
10114 06:02:54.850191
10115 06:02:55.388598 00200000 ################################################################
10116 06:02:55.388741
10117 06:02:55.946399 00280000 ################################################################
10118 06:02:55.946547
10119 06:02:56.504158 00300000 ################################################################
10120 06:02:56.504308
10121 06:02:57.047121 00380000 ################################################################
10122 06:02:57.047267
10123 06:02:57.585702 00400000 ################################################################
10124 06:02:57.585854
10125 06:02:58.136716 00480000 ################################################################
10126 06:02:58.136862
10127 06:02:58.681361 00500000 ################################################################
10128 06:02:58.681564
10129 06:02:59.237604 00580000 ################################################################
10130 06:02:59.237742
10131 06:02:59.795909 00600000 ################################################################
10132 06:02:59.796070
10133 06:03:00.355846 00680000 ################################################################
10134 06:03:00.355994
10135 06:03:00.909152 00700000 ################################################################
10136 06:03:00.909363
10137 06:03:01.499804 00780000 ################################################################
10138 06:03:01.499953
10139 06:03:02.076891 00800000 ################################################################
10140 06:03:02.077038
10141 06:03:02.621615 00880000 ################################################################
10142 06:03:02.621792
10143 06:03:03.161803 00900000 ################################################################
10144 06:03:03.162281
10145 06:03:03.810695 00980000 ################################################################
10146 06:03:03.810841
10147 06:03:04.342697 00a00000 ################################################################
10148 06:03:04.342853
10149 06:03:04.906700 00a80000 ################################################################
10150 06:03:04.906847
10151 06:03:05.468168 00b00000 ################################################################
10152 06:03:05.468340
10153 06:03:06.017727 00b80000 ################################################################
10154 06:03:06.017876
10155 06:03:06.560802 00c00000 ################################################################
10156 06:03:06.560947
10157 06:03:07.099421 00c80000 ################################################################
10158 06:03:07.099566
10159 06:03:07.648114 00d00000 ################################################################
10160 06:03:07.648283
10161 06:03:08.202396 00d80000 ################################################################
10162 06:03:08.202548
10163 06:03:08.755920 00e00000 ################################################################
10164 06:03:08.756054
10165 06:03:09.310377 00e80000 ################################################################
10166 06:03:09.310537
10167 06:03:09.855833 00f00000 ################################################################
10168 06:03:09.855980
10169 06:03:10.394028 00f80000 ################################################################
10170 06:03:10.394249
10171 06:03:10.959187 01000000 ################################################################
10172 06:03:10.959328
10173 06:03:11.506617 01080000 ################################################################
10174 06:03:11.506776
10175 06:03:12.086312 01100000 ################################################################
10176 06:03:12.086461
10177 06:03:12.640958 01180000 ################################################################
10178 06:03:12.641105
10179 06:03:13.175449 01200000 ################################################################
10180 06:03:13.175629
10181 06:03:13.725769 01280000 ################################################################
10182 06:03:13.725940
10183 06:03:14.282882 01300000 ################################################################
10184 06:03:14.283023
10185 06:03:14.836164 01380000 ################################################################
10186 06:03:14.836315
10187 06:03:15.392204 01400000 ################################################################
10188 06:03:15.392357
10189 06:03:15.945950 01480000 ################################################################
10190 06:03:15.946095
10191 06:03:16.501217 01500000 ################################################################
10192 06:03:16.501364
10193 06:03:17.048306 01580000 ################################################################
10194 06:03:17.048483
10195 06:03:17.613384 01600000 ################################################################
10196 06:03:17.613566
10197 06:03:18.184410 01680000 ################################################################
10198 06:03:18.184555
10199 06:03:18.763193 01700000 ################################################################
10200 06:03:18.763325
10201 06:03:19.314295 01780000 ################################################################
10202 06:03:19.314445
10203 06:03:19.888754 01800000 ################################################################
10204 06:03:19.888901
10205 06:03:20.458352 01880000 ################################################################
10206 06:03:20.458502
10207 06:03:21.037063 01900000 ################################################################
10208 06:03:21.037216
10209 06:03:21.580477 01980000 ################################################################
10210 06:03:21.580633
10211 06:03:22.136425 01a00000 ################################################################
10212 06:03:22.136608
10213 06:03:22.678219 01a80000 ################################################################
10214 06:03:22.678369
10215 06:03:23.233766 01b00000 ################################################################
10216 06:03:23.233918
10217 06:03:23.790514 01b80000 ################################################################
10218 06:03:23.790675
10219 06:03:24.343740 01c00000 ################################################################
10220 06:03:24.343952
10221 06:03:24.908657 01c80000 ################################################################
10222 06:03:24.908812
10223 06:03:25.470754 01d00000 ################################################################
10224 06:03:25.470911
10225 06:03:26.027521 01d80000 ################################################################
10226 06:03:26.027672
10227 06:03:26.593488 01e00000 ################################################################
10228 06:03:26.593677
10229 06:03:27.150307 01e80000 ################################################################
10230 06:03:27.150490
10231 06:03:27.720667 01f00000 ################################################################
10232 06:03:27.720824
10233 06:03:28.286484 01f80000 ################################################################
10234 06:03:28.286640
10235 06:03:28.850662 02000000 ################################################################
10236 06:03:28.850812
10237 06:03:29.414786 02080000 ################################################################
10238 06:03:29.414939
10239 06:03:29.979862 02100000 ################################################################
10240 06:03:29.980009
10241 06:03:30.544336 02180000 ################################################################
10242 06:03:30.544523
10243 06:03:31.093463 02200000 ################################################################
10244 06:03:31.093641
10245 06:03:31.680964 02280000 ################################################################
10246 06:03:31.681106
10247 06:03:32.282298 02300000 ################################################################
10248 06:03:32.282431
10249 06:03:32.867696 02380000 ################################################################
10250 06:03:32.867866
10251 06:03:33.453646 02400000 ################################################################
10252 06:03:33.453785
10253 06:03:34.033178 02480000 ################################################################
10254 06:03:34.033324
10255 06:03:34.707277 02500000 ################################################################
10256 06:03:34.707782
10257 06:03:35.418031 02580000 ################################################################
10258 06:03:35.418525
10259 06:03:36.129189 02600000 ################################################################
10260 06:03:36.129728
10261 06:03:36.754624 02680000 ################################################################
10262 06:03:36.754777
10263 06:03:37.331219 02700000 ################################################################
10264 06:03:37.331347
10265 06:03:37.902418 02780000 ################################################################
10266 06:03:37.902608
10267 06:03:38.445625 02800000 ################################################################
10268 06:03:38.445762
10269 06:03:39.001531 02880000 ################################################################
10270 06:03:39.001667
10271 06:03:39.632382 02900000 ################################################################
10272 06:03:39.632937
10273 06:03:40.293889 02980000 ################################################################
10274 06:03:40.294026
10275 06:03:40.864504 02a00000 ################################################################
10276 06:03:40.864668
10277 06:03:41.438107 02a80000 ################################################################
10278 06:03:41.438239
10279 06:03:42.007837 02b00000 ################################################################
10280 06:03:42.007983
10281 06:03:42.541915 02b80000 ################################################################
10282 06:03:42.542055
10283 06:03:43.096942 02c00000 ################################################################
10284 06:03:43.097120
10285 06:03:43.639757 02c80000 ################################################################
10286 06:03:43.639901
10287 06:03:44.206063 02d00000 ################################################################
10288 06:03:44.206197
10289 06:03:44.738313 02d80000 ################################################################
10290 06:03:44.738457
10291 06:03:45.282998 02e00000 ################################################################
10292 06:03:45.283140
10293 06:03:45.826772 02e80000 ################################################################
10294 06:03:45.826946
10295 06:03:46.378877 02f00000 ################################################################
10296 06:03:46.379048
10297 06:03:46.922416 02f80000 ################################################################
10298 06:03:46.922560
10299 06:03:47.449737 03000000 ################################################################
10300 06:03:47.449869
10301 06:03:47.476268 03080000 #### done.
10302 06:03:47.476389
10303 06:03:47.479300 The bootfile was 50880822 bytes long.
10304 06:03:47.479406
10305 06:03:47.482810 Sending tftp read request... done.
10306 06:03:47.482893
10307 06:03:47.483016 Waiting for the transfer...
10308 06:03:47.485780
10309 06:03:47.485859 00000000 # done.
10310 06:03:47.485924
10311 06:03:47.492389 Command line loaded dynamically from TFTP file: 12379478/tftp-deploy-13tqp04d/kernel/cmdline
10312 06:03:47.492497
10313 06:03:47.506089 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10314 06:03:47.506174
10315 06:03:47.509473 Loading FIT.
10316 06:03:47.509587
10317 06:03:47.512417 Image ramdisk-1 has 39349680 bytes.
10318 06:03:47.512512
10319 06:03:47.515990 Image fdt-1 has 47278 bytes.
10320 06:03:47.516061
10321 06:03:47.516119 Image kernel-1 has 11481830 bytes.
10322 06:03:47.518913
10323 06:03:47.526332 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10324 06:03:47.526407
10325 06:03:47.542299 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10326 06:03:47.545878
10327 06:03:47.548949 Choosing best match conf-1 for compat google,spherion-rev2.
10328 06:03:47.553374
10329 06:03:47.557948 Connected to device vid:did:rid of 1ae0:0028:00
10330 06:03:47.566171
10331 06:03:47.569885 tpm_get_response: command 0x17b, return code 0x0
10332 06:03:47.569982
10333 06:03:47.572697 ec_init: CrosEC protocol v3 supported (256, 248)
10334 06:03:47.577000
10335 06:03:47.580386 tpm_cleanup: add release locality here.
10336 06:03:47.580484
10337 06:03:47.580572 Shutting down all USB controllers.
10338 06:03:47.583364
10339 06:03:47.583434 Removing current net device
10340 06:03:47.583493
10341 06:03:47.589856 Exiting depthcharge with code 4 at timestamp: 90589730
10342 06:03:47.589933
10343 06:03:47.593230 LZMA decompressing kernel-1 to 0x821a6718
10344 06:03:47.593329
10345 06:03:47.596732 LZMA decompressing kernel-1 to 0x40000000
10346 06:03:49.034358
10347 06:03:49.035007 jumping to kernel
10348 06:03:49.037087 end: 2.2.4 bootloader-commands (duration 00:01:03) [common]
10349 06:03:49.037626 start: 2.2.5 auto-login-action (timeout 00:03:22) [common]
10350 06:03:49.038046 Setting prompt string to ['Linux version [0-9]']
10351 06:03:49.038424 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10352 06:03:49.038782 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10353 06:03:49.117183
10354 06:03:49.119886 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10355 06:03:49.123907 start: 2.2.5.1 login-action (timeout 00:03:22) [common]
10356 06:03:49.124363 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10357 06:03:49.124933 Setting prompt string to []
10358 06:03:49.125513 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10359 06:03:49.125924 Using line separator: #'\n'#
10360 06:03:49.126234 No login prompt set.
10361 06:03:49.126575 Parsing kernel messages
10362 06:03:49.126895 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10363 06:03:49.127434 [login-action] Waiting for messages, (timeout 00:03:22)
10364 06:03:49.143525 [ 0.000000] Linux version 6.1.67-cip12 (KernelCI@build-j59664-arm64-gcc-10-defconfig-arm64-chromebook-fgc24) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023
10365 06:03:49.146426 [ 0.000000] random: crng init done
10366 06:03:49.153452 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10367 06:03:49.156250 [ 0.000000] efi: UEFI not found.
10368 06:03:49.162886 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10369 06:03:49.169633 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10370 06:03:49.179400 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10371 06:03:49.189163 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10372 06:03:49.195975 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10373 06:03:49.202725 [ 0.000000] printk: bootconsole [mtk8250] enabled
10374 06:03:49.209128 [ 0.000000] NUMA: No NUMA configuration found
10375 06:03:49.216125 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10376 06:03:49.222448 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10377 06:03:49.222795 [ 0.000000] Zone ranges:
10378 06:03:49.228769 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10379 06:03:49.232113 [ 0.000000] DMA32 empty
10380 06:03:49.238675 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10381 06:03:49.242080 [ 0.000000] Movable zone start for each node
10382 06:03:49.245526 [ 0.000000] Early memory node ranges
10383 06:03:49.252059 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10384 06:03:49.258578 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10385 06:03:49.264920 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10386 06:03:49.271905 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10387 06:03:49.278194 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10388 06:03:49.284598 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10389 06:03:49.340904 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10390 06:03:49.347267 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10391 06:03:49.354226 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10392 06:03:49.357203 [ 0.000000] psci: probing for conduit method from DT.
10393 06:03:49.364238 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10394 06:03:49.367240 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10395 06:03:49.373720 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10396 06:03:49.377304 [ 0.000000] psci: SMC Calling Convention v1.2
10397 06:03:49.384009 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10398 06:03:49.386936 [ 0.000000] Detected VIPT I-cache on CPU0
10399 06:03:49.394017 [ 0.000000] CPU features: detected: GIC system register CPU interface
10400 06:03:49.400276 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10401 06:03:49.406864 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10402 06:03:49.413509 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10403 06:03:49.420298 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10404 06:03:49.430290 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10405 06:03:49.433382 [ 0.000000] alternatives: applying boot alternatives
10406 06:03:49.439799 [ 0.000000] Fallback order for Node 0: 0
10407 06:03:49.446613 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10408 06:03:49.449610 [ 0.000000] Policy zone: Normal
10409 06:03:49.463172 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10410 06:03:49.472978 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10411 06:03:49.485621 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10412 06:03:49.495389 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10413 06:03:49.502012 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10414 06:03:49.505264 <6>[ 0.000000] software IO TLB: area num 8.
10415 06:03:49.561669 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10416 06:03:49.711656 <6>[ 0.000000] Memory: 7930292K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 422476K reserved, 32768K cma-reserved)
10417 06:03:49.717966 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10418 06:03:49.724952 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10419 06:03:49.727851 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10420 06:03:49.734363 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10421 06:03:49.740949 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10422 06:03:49.744315 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10423 06:03:49.754200 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10424 06:03:49.760891 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10425 06:03:49.767561 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10426 06:03:49.773753 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10427 06:03:49.777552 <6>[ 0.000000] GICv3: 608 SPIs implemented
10428 06:03:49.780805 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10429 06:03:49.787205 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10430 06:03:49.790702 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10431 06:03:49.797182 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10432 06:03:49.810408 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10433 06:03:49.823954 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10434 06:03:49.830200 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10435 06:03:49.838281 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10436 06:03:49.851294 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10437 06:03:49.857693 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10438 06:03:49.864905 <6>[ 0.009230] Console: colour dummy device 80x25
10439 06:03:49.874756 <6>[ 0.013956] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10440 06:03:49.878105 <6>[ 0.024398] pid_max: default: 32768 minimum: 301
10441 06:03:49.884443 <6>[ 0.029268] LSM: Security Framework initializing
10442 06:03:49.891303 <6>[ 0.034206] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10443 06:03:49.900781 <6>[ 0.042020] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10444 06:03:49.907682 <6>[ 0.051443] cblist_init_generic: Setting adjustable number of callback queues.
10445 06:03:49.914642 <6>[ 0.058886] cblist_init_generic: Setting shift to 3 and lim to 1.
10446 06:03:49.924555 <6>[ 0.065263] cblist_init_generic: Setting adjustable number of callback queues.
10447 06:03:49.930928 <6>[ 0.072690] cblist_init_generic: Setting shift to 3 and lim to 1.
10448 06:03:49.934400 <6>[ 0.079130] rcu: Hierarchical SRCU implementation.
10449 06:03:49.940702 <6>[ 0.084177] rcu: Max phase no-delay instances is 1000.
10450 06:03:49.947612 <6>[ 0.091196] EFI services will not be available.
10451 06:03:49.950544 <6>[ 0.096157] smp: Bringing up secondary CPUs ...
10452 06:03:49.958747 <6>[ 0.101208] Detected VIPT I-cache on CPU1
10453 06:03:49.965803 <6>[ 0.101278] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10454 06:03:49.972225 <6>[ 0.101309] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10455 06:03:49.975617 <6>[ 0.101636] Detected VIPT I-cache on CPU2
10456 06:03:49.981968 <6>[ 0.101683] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10457 06:03:49.988858 <6>[ 0.101699] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10458 06:03:49.995667 <6>[ 0.101953] Detected VIPT I-cache on CPU3
10459 06:03:50.001862 <6>[ 0.101998] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10460 06:03:50.008496 <6>[ 0.102012] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10461 06:03:50.012076 <6>[ 0.102316] CPU features: detected: Spectre-v4
10462 06:03:50.018572 <6>[ 0.102323] CPU features: detected: Spectre-BHB
10463 06:03:50.021648 <6>[ 0.102328] Detected PIPT I-cache on CPU4
10464 06:03:50.028530 <6>[ 0.102386] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10465 06:03:50.035386 <6>[ 0.102403] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10466 06:03:50.041611 <6>[ 0.102697] Detected PIPT I-cache on CPU5
10467 06:03:50.048103 <6>[ 0.102759] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10468 06:03:50.055252 <6>[ 0.102775] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10469 06:03:50.058083 <6>[ 0.103055] Detected PIPT I-cache on CPU6
10470 06:03:50.064629 <6>[ 0.103119] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10471 06:03:50.071356 <6>[ 0.103135] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10472 06:03:50.077639 <6>[ 0.103434] Detected PIPT I-cache on CPU7
10473 06:03:50.084550 <6>[ 0.103499] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10474 06:03:50.090761 <6>[ 0.103515] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10475 06:03:50.094114 <6>[ 0.103562] smp: Brought up 1 node, 8 CPUs
10476 06:03:50.100819 <6>[ 0.244807] SMP: Total of 8 processors activated.
10477 06:03:50.104346 <6>[ 0.249728] CPU features: detected: 32-bit EL0 Support
10478 06:03:50.114003 <6>[ 0.255092] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10479 06:03:50.120504 <6>[ 0.263946] CPU features: detected: Common not Private translations
10480 06:03:50.127344 <6>[ 0.270422] CPU features: detected: CRC32 instructions
10481 06:03:50.130546 <6>[ 0.275774] CPU features: detected: RCpc load-acquire (LDAPR)
10482 06:03:50.137220 <6>[ 0.281733] CPU features: detected: LSE atomic instructions
10483 06:03:50.143600 <6>[ 0.287515] CPU features: detected: Privileged Access Never
10484 06:03:50.150514 <6>[ 0.293299] CPU features: detected: RAS Extension Support
10485 06:03:50.157330 <6>[ 0.298943] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10486 06:03:50.160214 <6>[ 0.306207] CPU: All CPU(s) started at EL2
10487 06:03:50.167277 <6>[ 0.310549] alternatives: applying system-wide alternatives
10488 06:03:50.176607 <6>[ 0.321273] devtmpfs: initialized
10489 06:03:50.192247 <6>[ 0.330118] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10490 06:03:50.198673 <6>[ 0.340080] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10491 06:03:50.205238 <6>[ 0.348290] pinctrl core: initialized pinctrl subsystem
10492 06:03:50.208748 <6>[ 0.354959] DMI not present or invalid.
10493 06:03:50.215259 <6>[ 0.359367] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10494 06:03:50.225163 <6>[ 0.366226] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10495 06:03:50.231799 <6>[ 0.373794] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10496 06:03:50.241319 <6>[ 0.382017] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10497 06:03:50.245099 <6>[ 0.390257] audit: initializing netlink subsys (disabled)
10498 06:03:50.254761 <5>[ 0.395948] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10499 06:03:50.261098 <6>[ 0.396652] thermal_sys: Registered thermal governor 'step_wise'
10500 06:03:50.267979 <6>[ 0.403911] thermal_sys: Registered thermal governor 'power_allocator'
10501 06:03:50.271111 <6>[ 0.410170] cpuidle: using governor menu
10502 06:03:50.277709 <6>[ 0.421131] NET: Registered PF_QIPCRTR protocol family
10503 06:03:50.284547 <6>[ 0.426611] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10504 06:03:50.291260 <6>[ 0.433712] ASID allocator initialised with 32768 entries
10505 06:03:50.294047 <6>[ 0.440270] Serial: AMBA PL011 UART driver
10506 06:03:50.304517 <4>[ 0.449029] Trying to register duplicate clock ID: 134
10507 06:03:50.358795 <6>[ 0.506456] KASLR enabled
10508 06:03:50.373136 <6>[ 0.514185] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10509 06:03:50.379088 <6>[ 0.521201] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10510 06:03:50.386267 <6>[ 0.527692] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10511 06:03:50.392788 <6>[ 0.534697] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10512 06:03:50.399320 <6>[ 0.541181] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10513 06:03:50.405993 <6>[ 0.548184] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10514 06:03:50.412731 <6>[ 0.554669] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10515 06:03:50.419369 <6>[ 0.561672] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10516 06:03:50.422466 <6>[ 0.569185] ACPI: Interpreter disabled.
10517 06:03:50.430656 <6>[ 0.575532] iommu: Default domain type: Translated
10518 06:03:50.437469 <6>[ 0.580642] iommu: DMA domain TLB invalidation policy: strict mode
10519 06:03:50.440733 <5>[ 0.587300] SCSI subsystem initialized
10520 06:03:50.447452 <6>[ 0.591457] usbcore: registered new interface driver usbfs
10521 06:03:50.454197 <6>[ 0.597187] usbcore: registered new interface driver hub
10522 06:03:50.457251 <6>[ 0.602740] usbcore: registered new device driver usb
10523 06:03:50.464140 <6>[ 0.608830] pps_core: LinuxPPS API ver. 1 registered
10524 06:03:50.473800 <6>[ 0.614024] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10525 06:03:50.477102 <6>[ 0.623369] PTP clock support registered
10526 06:03:50.480747 <6>[ 0.627609] EDAC MC: Ver: 3.0.0
10527 06:03:50.488185 <6>[ 0.632752] FPGA manager framework
10528 06:03:50.494563 <6>[ 0.636431] Advanced Linux Sound Architecture Driver Initialized.
10529 06:03:50.498119 <6>[ 0.643204] vgaarb: loaded
10530 06:03:50.504443 <6>[ 0.646359] clocksource: Switched to clocksource arch_sys_counter
10531 06:03:50.507963 <5>[ 0.652791] VFS: Disk quotas dquot_6.6.0
10532 06:03:50.514179 <6>[ 0.656978] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10533 06:03:50.517447 <6>[ 0.664163] pnp: PnP ACPI: disabled
10534 06:03:50.526469 <6>[ 0.670849] NET: Registered PF_INET protocol family
10535 06:03:50.535797 <6>[ 0.676429] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10536 06:03:50.547350 <6>[ 0.688716] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10537 06:03:50.557255 <6>[ 0.697531] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10538 06:03:50.564010 <6>[ 0.705500] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10539 06:03:50.573746 <6>[ 0.714200] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10540 06:03:50.580227 <6>[ 0.723953] TCP: Hash tables configured (established 65536 bind 65536)
10541 06:03:50.587079 <6>[ 0.730811] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10542 06:03:50.597050 <6>[ 0.738010] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10543 06:03:50.603402 <6>[ 0.745706] NET: Registered PF_UNIX/PF_LOCAL protocol family
10544 06:03:50.606776 <6>[ 0.751851] RPC: Registered named UNIX socket transport module.
10545 06:03:50.613005 <6>[ 0.758004] RPC: Registered udp transport module.
10546 06:03:50.616475 <6>[ 0.762937] RPC: Registered tcp transport module.
10547 06:03:50.623182 <6>[ 0.767867] RPC: Registered tcp NFSv4.1 backchannel transport module.
10548 06:03:50.630033 <6>[ 0.774529] PCI: CLS 0 bytes, default 64
10549 06:03:50.632954 <6>[ 0.778933] Unpacking initramfs...
10550 06:03:50.642947 <6>[ 0.782657] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10551 06:03:50.649594 <6>[ 0.791295] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10552 06:03:50.655971 <6>[ 0.800151] kvm [1]: IPA Size Limit: 40 bits
10553 06:03:50.659385 <6>[ 0.804681] kvm [1]: GICv3: no GICV resource entry
10554 06:03:50.666323 <6>[ 0.809702] kvm [1]: disabling GICv2 emulation
10555 06:03:50.669191 <6>[ 0.814385] kvm [1]: GIC system register CPU interface enabled
10556 06:03:50.675688 <6>[ 0.820559] kvm [1]: vgic interrupt IRQ18
10557 06:03:50.682570 <6>[ 0.826408] kvm [1]: VHE mode initialized successfully
10558 06:03:50.689236 <5>[ 0.832843] Initialise system trusted keyrings
10559 06:03:50.696005 <6>[ 0.837662] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10560 06:03:50.702763 <6>[ 0.847683] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10561 06:03:50.709369 <5>[ 0.854048] NFS: Registering the id_resolver key type
10562 06:03:50.713011 <5>[ 0.859346] Key type id_resolver registered
10563 06:03:50.719204 <5>[ 0.863761] Key type id_legacy registered
10564 06:03:50.726072 <6>[ 0.868048] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10565 06:03:50.732142 <6>[ 0.874974] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10566 06:03:50.739263 <6>[ 0.882685] 9p: Installing v9fs 9p2000 file system support
10567 06:03:50.775277 <5>[ 0.920268] Key type asymmetric registered
10568 06:03:50.778772 <5>[ 0.924597] Asymmetric key parser 'x509' registered
10569 06:03:50.789068 <6>[ 0.929734] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10570 06:03:50.791815 <6>[ 0.937349] io scheduler mq-deadline registered
10571 06:03:50.795162 <6>[ 0.942108] io scheduler kyber registered
10572 06:03:50.814177 <6>[ 0.959247] EINJ: ACPI disabled.
10573 06:03:50.846210 <4>[ 0.984547] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10574 06:03:50.855917 <4>[ 0.995175] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10575 06:03:50.870639 <6>[ 1.015602] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10576 06:03:50.878658 <6>[ 1.023568] printk: console [ttyS0] disabled
10577 06:03:50.906891 <6>[ 1.048228] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10578 06:03:50.913743 <6>[ 1.057704] printk: console [ttyS0] enabled
10579 06:03:50.916770 <6>[ 1.057704] printk: console [ttyS0] enabled
10580 06:03:50.923246 <6>[ 1.066598] printk: bootconsole [mtk8250] disabled
10581 06:03:50.926720 <6>[ 1.066598] printk: bootconsole [mtk8250] disabled
10582 06:03:50.933848 <6>[ 1.077658] SuperH (H)SCI(F) driver initialized
10583 06:03:50.936732 <6>[ 1.082946] msm_serial: driver initialized
10584 06:03:50.950680 <6>[ 1.091850] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10585 06:03:50.960358 <6>[ 1.100398] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10586 06:03:50.967100 <6>[ 1.108941] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10587 06:03:50.976722 <6>[ 1.117570] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10588 06:03:50.983127 <6>[ 1.126276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10589 06:03:50.993237 <6>[ 1.134990] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10590 06:03:51.002881 <6>[ 1.143529] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10591 06:03:51.009626 <6>[ 1.152325] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10592 06:03:51.019628 <6>[ 1.160867] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10593 06:03:51.031299 <6>[ 1.176549] loop: module loaded
10594 06:03:51.037820 <6>[ 1.182555] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10595 06:03:51.060784 <4>[ 1.205792] mtk-pmic-keys: Failed to locate of_node [id: -1]
10596 06:03:51.067077 <6>[ 1.212505] megasas: 07.719.03.00-rc1
10597 06:03:51.076950 <6>[ 1.222097] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10598 06:03:51.088035 <6>[ 1.229750] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10599 06:03:51.101641 <6>[ 1.246484] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10600 06:03:51.157786 <6>[ 1.296278] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10601 06:03:52.225534 <6>[ 2.370703] Freeing initrd memory: 38424K
10602 06:03:52.235667 <6>[ 2.380906] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10603 06:03:52.246852 <6>[ 2.391955] tun: Universal TUN/TAP device driver, 1.6
10604 06:03:52.250252 <6>[ 2.398028] thunder_xcv, ver 1.0
10605 06:03:52.253368 <6>[ 2.401532] thunder_bgx, ver 1.0
10606 06:03:52.256639 <6>[ 2.405030] nicpf, ver 1.0
10607 06:03:52.266891 <6>[ 2.409059] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10608 06:03:52.270346 <6>[ 2.416536] hns3: Copyright (c) 2017 Huawei Corporation.
10609 06:03:52.277259 <6>[ 2.422124] hclge is initializing
10610 06:03:52.280562 <6>[ 2.425709] e1000: Intel(R) PRO/1000 Network Driver
10611 06:03:52.286834 <6>[ 2.430838] e1000: Copyright (c) 1999-2006 Intel Corporation.
10612 06:03:52.290270 <6>[ 2.436855] e1000e: Intel(R) PRO/1000 Network Driver
10613 06:03:52.296813 <6>[ 2.442071] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10614 06:03:52.303230 <6>[ 2.448257] igb: Intel(R) Gigabit Ethernet Network Driver
10615 06:03:52.310037 <6>[ 2.453907] igb: Copyright (c) 2007-2014 Intel Corporation.
10616 06:03:52.316482 <6>[ 2.459744] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10617 06:03:52.323459 <6>[ 2.466262] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10618 06:03:52.326540 <6>[ 2.472735] sky2: driver version 1.30
10619 06:03:52.333306 <6>[ 2.477748] VFIO - User Level meta-driver version: 0.3
10620 06:03:52.340836 <6>[ 2.486015] usbcore: registered new interface driver usb-storage
10621 06:03:52.347315 <6>[ 2.492463] usbcore: registered new device driver onboard-usb-hub
10622 06:03:52.356325 <6>[ 2.501632] mt6397-rtc mt6359-rtc: registered as rtc0
10623 06:03:52.366169 <6>[ 2.507092] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-25T06:03:52 UTC (1703484232)
10624 06:03:52.369660 <6>[ 2.516662] i2c_dev: i2c /dev entries driver
10625 06:03:52.386279 <6>[ 2.528454] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10626 06:03:52.406202 <6>[ 2.551460] cpu cpu0: EM: created perf domain
10627 06:03:52.409207 <6>[ 2.556386] cpu cpu4: EM: created perf domain
10628 06:03:52.416506 <6>[ 2.561993] sdhci: Secure Digital Host Controller Interface driver
10629 06:03:52.423581 <6>[ 2.568427] sdhci: Copyright(c) Pierre Ossman
10630 06:03:52.429917 <6>[ 2.573380] Synopsys Designware Multimedia Card Interface Driver
10631 06:03:52.436504 <6>[ 2.580023] sdhci-pltfm: SDHCI platform and OF driver helper
10632 06:03:52.440021 <6>[ 2.580062] mmc0: CQHCI version 5.10
10633 06:03:52.446322 <6>[ 2.589964] ledtrig-cpu: registered to indicate activity on CPUs
10634 06:03:52.453246 <6>[ 2.597106] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10635 06:03:52.460166 <6>[ 2.604165] usbcore: registered new interface driver usbhid
10636 06:03:52.462966 <6>[ 2.609987] usbhid: USB HID core driver
10637 06:03:52.469812 <6>[ 2.614193] spi_master spi0: will run message pump with realtime priority
10638 06:03:52.513806 <6>[ 2.652301] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10639 06:03:52.533188 <6>[ 2.668458] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10640 06:03:52.537309 <6>[ 2.682203] mmc0: Command Queue Engine enabled
10641 06:03:52.543566 <6>[ 2.687023] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10642 06:03:52.550228 <6>[ 2.693888] cros-ec-spi spi0.0: Chrome EC device registered
10643 06:03:52.553642 <6>[ 2.694344] mmcblk0: mmc0:0001 DA4128 116 GiB
10644 06:03:52.568662 <6>[ 2.713589] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10645 06:03:52.576292 <6>[ 2.721189] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10646 06:03:52.586343 <6>[ 2.724486] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10647 06:03:52.589781 <6>[ 2.727142] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10648 06:03:52.596444 <6>[ 2.736946] NET: Registered PF_PACKET protocol family
10649 06:03:52.602561 <6>[ 2.741720] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10650 06:03:52.606362 <6>[ 2.746328] 9pnet: Installing 9P2000 support
10651 06:03:52.612696 <5>[ 2.757327] Key type dns_resolver registered
10652 06:03:52.615878 <6>[ 2.762281] registered taskstats version 1
10653 06:03:52.622397 <5>[ 2.766678] Loading compiled-in X.509 certificates
10654 06:03:52.651766 <4>[ 2.789868] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10655 06:03:52.661431 <4>[ 2.800819] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10656 06:03:52.667684 <3>[ 2.811368] debugfs: File 'uA_load' in directory '/' already present!
10657 06:03:52.674444 <3>[ 2.818125] debugfs: File 'min_uV' in directory '/' already present!
10658 06:03:52.680985 <3>[ 2.824794] debugfs: File 'max_uV' in directory '/' already present!
10659 06:03:52.687592 <3>[ 2.831413] debugfs: File 'constraint_flags' in directory '/' already present!
10660 06:03:52.699437 <3>[ 2.841193] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10661 06:03:52.708638 <6>[ 2.853513] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10662 06:03:52.715315 <6>[ 2.860311] xhci-mtk 11200000.usb: xHCI Host Controller
10663 06:03:52.721978 <6>[ 2.865814] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10664 06:03:52.731852 <6>[ 2.873644] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10665 06:03:52.738961 <6>[ 2.883065] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10666 06:03:52.745468 <6>[ 2.889105] xhci-mtk 11200000.usb: xHCI Host Controller
10667 06:03:52.752039 <6>[ 2.894579] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10668 06:03:52.758414 <6>[ 2.902222] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10669 06:03:52.765193 <6>[ 2.909869] hub 1-0:1.0: USB hub found
10670 06:03:52.768599 <6>[ 2.913881] hub 1-0:1.0: 1 port detected
10671 06:03:52.774680 <6>[ 2.918135] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10672 06:03:52.781955 <6>[ 2.926684] hub 2-0:1.0: USB hub found
10673 06:03:52.784651 <6>[ 2.930689] hub 2-0:1.0: 1 port detected
10674 06:03:52.793616 <6>[ 2.938398] mtk-msdc 11f70000.mmc: Got CD GPIO
10675 06:03:52.803313 <6>[ 2.945096] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10676 06:03:52.809934 <6>[ 2.953139] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10677 06:03:52.820329 <4>[ 2.961041] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10678 06:03:52.830028 <6>[ 2.970572] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10679 06:03:52.836252 <6>[ 2.978650] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10680 06:03:52.843009 <6>[ 2.986678] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10681 06:03:52.852978 <6>[ 2.994600] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10682 06:03:52.859896 <6>[ 3.002427] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10683 06:03:52.869241 <6>[ 3.010245] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10684 06:03:52.879759 <6>[ 3.020647] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10685 06:03:52.886085 <6>[ 3.029036] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10686 06:03:52.896202 <6>[ 3.037380] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10687 06:03:52.902657 <6>[ 3.045723] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10688 06:03:52.912702 <6>[ 3.054063] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10689 06:03:52.922150 <6>[ 3.062405] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10690 06:03:52.929192 <6>[ 3.070745] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10691 06:03:52.939000 <6>[ 3.079083] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10692 06:03:52.945329 <6>[ 3.087424] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10693 06:03:52.955744 <6>[ 3.095763] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10694 06:03:52.961977 <6>[ 3.104103] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10695 06:03:52.971892 <6>[ 3.112442] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10696 06:03:52.978691 <6>[ 3.120780] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10697 06:03:52.988685 <6>[ 3.129118] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10698 06:03:52.995170 <6>[ 3.137456] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10699 06:03:53.002087 <6>[ 3.146191] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10700 06:03:53.008617 <6>[ 3.153329] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10701 06:03:53.014862 <6>[ 3.160088] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10702 06:03:53.025035 <6>[ 3.166845] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10703 06:03:53.031551 <6>[ 3.173771] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10704 06:03:53.038580 <6>[ 3.180622] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10705 06:03:53.048373 <6>[ 3.189749] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10706 06:03:53.058178 <6>[ 3.198867] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10707 06:03:53.068157 <6>[ 3.208160] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10708 06:03:53.077824 <6>[ 3.217630] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10709 06:03:53.084502 <6>[ 3.227098] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10710 06:03:53.094574 <6>[ 3.236218] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10711 06:03:53.104169 <6>[ 3.245689] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10712 06:03:53.114107 <6>[ 3.254807] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10713 06:03:53.124115 <6>[ 3.264100] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10714 06:03:53.134117 <6>[ 3.274260] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10715 06:03:53.144329 <6>[ 3.285791] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10716 06:03:53.192892 <6>[ 3.334631] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10717 06:03:53.347168 <6>[ 3.492082] hub 1-1:1.0: USB hub found
10718 06:03:53.350699 <6>[ 3.496576] hub 1-1:1.0: 4 ports detected
10719 06:03:53.360126 <6>[ 3.504969] hub 1-1:1.0: USB hub found
10720 06:03:53.363023 <6>[ 3.509311] hub 1-1:1.0: 4 ports detected
10721 06:03:53.473071 <6>[ 3.614741] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10722 06:03:53.498712 <6>[ 3.643431] hub 2-1:1.0: USB hub found
10723 06:03:53.501801 <6>[ 3.647862] hub 2-1:1.0: 3 ports detected
10724 06:03:53.510259 <6>[ 3.655077] hub 2-1:1.0: USB hub found
10725 06:03:53.513191 <6>[ 3.659437] hub 2-1:1.0: 3 ports detected
10726 06:03:53.688412 <6>[ 3.830629] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10727 06:03:53.820436 <6>[ 3.965624] hub 1-1.4:1.0: USB hub found
10728 06:03:53.823650 <6>[ 3.970167] hub 1-1.4:1.0: 2 ports detected
10729 06:03:53.832930 <6>[ 3.977701] hub 1-1.4:1.0: USB hub found
10730 06:03:53.836032 <6>[ 3.982302] hub 1-1.4:1.0: 2 ports detected
10731 06:03:53.901434 <6>[ 4.042877] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10732 06:03:54.132597 <6>[ 4.274667] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10733 06:03:54.324369 <6>[ 4.466647] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10734 06:04:05.418759 <6>[ 15.567629] ALSA device list:
10735 06:04:05.423845 <6>[ 15.570920] No soundcards found.
10736 06:04:05.432308 <6>[ 15.578906] Freeing unused kernel memory: 8448K
10737 06:04:05.435316 <6>[ 15.583992] Run /init as init process
10738 06:04:05.485780 <6>[ 15.632729] NET: Registered PF_INET6 protocol family
10739 06:04:05.492784 <6>[ 15.639319] Segment Routing with IPv6
10740 06:04:05.495673 <6>[ 15.643274] In-situ OAM (IOAM) with IPv6
10741 06:04:05.530560 <30>[ 15.657853] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10742 06:04:05.534325 <30>[ 15.681776] systemd[1]: Detected architecture arm64.
10743 06:04:05.537488
10744 06:04:05.540553 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10745 06:04:05.540628
10746 06:04:05.555964 <30>[ 15.702789] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10747 06:04:05.696892 <30>[ 15.840263] systemd[1]: Queued start job for default target Graphical Interface.
10748 06:04:05.736769 <30>[ 15.883370] systemd[1]: Created slice system-getty.slice.
10749 06:04:05.743271 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10750 06:04:05.760148 <30>[ 15.907012] systemd[1]: Created slice system-modprobe.slice.
10751 06:04:05.766654 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10752 06:04:05.784954 <30>[ 15.931804] systemd[1]: Created slice system-serial\x2dgetty.slice.
10753 06:04:05.795241 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10754 06:04:05.808263 <30>[ 15.955056] systemd[1]: Created slice User and Session Slice.
10755 06:04:05.814835 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10756 06:04:05.836102 <30>[ 15.979251] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10757 06:04:05.845585 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10758 06:04:05.864142 <30>[ 16.007366] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10759 06:04:05.870230 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10760 06:04:05.894888 <30>[ 16.035179] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10761 06:04:05.901860 <30>[ 16.047515] systemd[1]: Reached target Local Encrypted Volumes.
10762 06:04:05.908202 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10763 06:04:05.924367 <30>[ 16.071177] systemd[1]: Reached target Paths.
10764 06:04:05.930845 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10765 06:04:05.944032 <30>[ 16.090688] systemd[1]: Reached target Remote File Systems.
10766 06:04:05.950800 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10767 06:04:05.968494 <30>[ 16.115002] systemd[1]: Reached target Slices.
10768 06:04:05.974739 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10769 06:04:05.987827 <30>[ 16.134662] systemd[1]: Reached target Swap.
10770 06:04:05.991475 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10771 06:04:06.012159 <30>[ 16.155165] systemd[1]: Listening on initctl Compatibility Named Pipe.
10772 06:04:06.018537 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10773 06:04:06.024933 <30>[ 16.170332] systemd[1]: Listening on Journal Audit Socket.
10774 06:04:06.031274 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10775 06:04:06.044394 <30>[ 16.191159] systemd[1]: Listening on Journal Socket (/dev/log).
10776 06:04:06.051301 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10777 06:04:06.069592 <30>[ 16.215923] systemd[1]: Listening on Journal Socket.
10778 06:04:06.075918 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10779 06:04:06.091799 <30>[ 16.235368] systemd[1]: Listening on Network Service Netlink Socket.
10780 06:04:06.098300 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10781 06:04:06.112465 <30>[ 16.259243] systemd[1]: Listening on udev Control Socket.
10782 06:04:06.118748 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10783 06:04:06.136844 <30>[ 16.283722] systemd[1]: Listening on udev Kernel Socket.
10784 06:04:06.143542 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10785 06:04:06.196121 <30>[ 16.342932] systemd[1]: Mounting Huge Pages File System...
10786 06:04:06.202695 Mounting [0;1;39mHuge Pages File System[0m...
10787 06:04:06.217781 <30>[ 16.364529] systemd[1]: Mounting POSIX Message Queue File System...
10788 06:04:06.224563 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10789 06:04:06.241746 <30>[ 16.388455] systemd[1]: Mounting Kernel Debug File System...
10790 06:04:06.248062 Mounting [0;1;39mKernel Debug File System[0m...
10791 06:04:06.267817 <30>[ 16.411116] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10792 06:04:06.279189 <30>[ 16.422912] systemd[1]: Starting Create list of static device nodes for the current kernel...
10793 06:04:06.286014 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10794 06:04:06.308240 <30>[ 16.455103] systemd[1]: Starting Load Kernel Module configfs...
10795 06:04:06.314911 Starting [0;1;39mLoad Kernel Module configfs[0m...
10796 06:04:06.332563 <30>[ 16.479054] systemd[1]: Starting Load Kernel Module drm...
10797 06:04:06.339121 Starting [0;1;39mLoad Kernel Module drm[0m...
10798 06:04:06.359651 <30>[ 16.503116] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10799 06:04:06.408130 <30>[ 16.555100] systemd[1]: Starting Journal Service...
10800 06:04:06.411697 Starting [0;1;39mJournal Service[0m...
10801 06:04:06.430850 <30>[ 16.577759] systemd[1]: Starting Load Kernel Modules...
10802 06:04:06.437446 Starting [0;1;39mLoad Kernel Modules[0m...
10803 06:04:06.458010 <30>[ 16.601367] systemd[1]: Starting Remount Root and Kernel File Systems...
10804 06:04:06.464443 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10805 06:04:06.482668 <30>[ 16.629704] systemd[1]: Starting Coldplug All udev Devices...
10806 06:04:06.489220 Starting [0;1;39mColdplug All udev Devices[0m...
10807 06:04:06.506479 <30>[ 16.653372] systemd[1]: Started Journal Service.
10808 06:04:06.513005 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10809 06:04:06.532109 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10810 06:04:06.548645 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10811 06:04:06.564735 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10812 06:04:06.584734 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10813 06:04:06.601639 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10814 06:04:06.623000 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10815 06:04:06.641822 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10816 06:04:06.661869 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10817 06:04:06.675574 See 'systemctl status systemd-remount-fs.service' for details.
10818 06:04:06.732582 Mounting [0;1;39mKernel Configuration File System[0m...
10819 06:04:06.752960 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10820 06:04:06.765954 <46>[ 16.909624] systemd-journald[177]: Received client request to flush runtime journal.
10821 06:04:06.776333 Starting [0;1;39mLoad/Save Random Seed[0m...
10822 06:04:06.799618 Starting [0;1;39mApply Kernel Variables[0m...
10823 06:04:06.825130 Starting [0;1;39mCreate System Users[0m...
10824 06:04:06.849862 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10825 06:04:06.872187 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10826 06:04:06.889019 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10827 06:04:06.901843 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10828 06:04:06.917870 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10829 06:04:06.933767 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10830 06:04:06.976539 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10831 06:04:07.000535 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10832 06:04:07.012399 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10833 06:04:07.031973 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10834 06:04:07.080959 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10835 06:04:07.107444 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10836 06:04:07.126410 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10837 06:04:07.137698 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10838 06:04:07.193845 Starting [0;1;39mNetwork Service[0m...
10839 06:04:07.217750 Starting [0;1;39mNetwork Time Synchronization[0m...
10840 06:04:07.238266 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10841 06:04:07.270077 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10842 06:04:07.326324 <6>[ 17.469282] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10843 06:04:07.336174 <6>[ 17.478120] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10844 06:04:07.342917 <6>[ 17.486939] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10845 06:04:07.349245 Starting [0;1;39mNetwork Name Resolution[0m...
10846 06:04:07.367599 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10847 06:04:07.383154 <6>[ 17.526476] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10848 06:04:07.393247 <3>[ 17.536322] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10849 06:04:07.399527 <3>[ 17.544639] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10850 06:04:07.409802 <4>[ 17.550124] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10851 06:04:07.416184 <3>[ 17.552806] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10852 06:04:07.422560 <6>[ 17.559359] remoteproc remoteproc0: scp is available
10853 06:04:07.429642 <3>[ 17.559373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 06:04:07.439203 <3>[ 17.559391] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10855 06:04:07.446155 <3>[ 17.559400] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 06:04:07.456001 <3>[ 17.559409] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 06:04:07.462978 <3>[ 17.559417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10858 06:04:07.469083 <3>[ 17.559465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 06:04:07.478924 <3>[ 17.559521] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10860 06:04:07.485651 <3>[ 17.559529] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10861 06:04:07.495836 <3>[ 17.559536] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10862 06:04:07.502493 <3>[ 17.559589] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10863 06:04:07.512595 <3>[ 17.559596] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10864 06:04:07.518972 <3>[ 17.559603] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10865 06:04:07.529020 <3>[ 17.559610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10866 06:04:07.535584 <3>[ 17.559617] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10867 06:04:07.545652 <3>[ 17.559662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10868 06:04:07.552923 <4>[ 17.569822] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10869 06:04:07.556651 <6>[ 17.573929] remoteproc remoteproc0: powering up scp
10870 06:04:07.559674 <6>[ 17.598012] mc: Linux media interface: v0.10
10871 06:04:07.570080 <6>[ 17.606111] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10872 06:04:07.576553 <6>[ 17.606160] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10873 06:04:07.582677 <6>[ 17.631479] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10874 06:04:07.586421 <6>[ 17.634611] usbcore: registered new interface driver r8152
10875 06:04:07.597192 <6>[ 17.645652] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10876 06:04:07.600344 <6>[ 17.646818] pci_bus 0000:00: root bus resource [bus 00-ff]
10877 06:04:07.606979 <6>[ 17.646848] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10878 06:04:07.617437 <6>[ 17.646860] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10879 06:04:07.624319 <6>[ 17.647025] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10880 06:04:07.634157 <4>[ 17.672801] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10881 06:04:07.637394 <4>[ 17.672801] Fallback method does not support PEC.
10882 06:04:07.643802 <6>[ 17.679729] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10883 06:04:07.653588 <3>[ 17.705743] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 06:04:07.663991 <6>[ 17.706445] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10885 06:04:07.667191 <6>[ 17.707996] pci 0000:00:00.0: supports D1 D2
10886 06:04:07.673625 <6>[ 17.722885] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10887 06:04:07.683797 <6>[ 17.726558] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10888 06:04:07.690360 <6>[ 17.727973] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10889 06:04:07.699912 <6>[ 17.746778] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10890 06:04:07.707198 <6>[ 17.747006] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10891 06:04:07.716678 <3>[ 17.748099] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 06:04:07.723613 <3>[ 17.752095] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10893 06:04:07.733948 <6>[ 17.752847] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10894 06:04:07.740809 <4>[ 17.757878] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10895 06:04:07.751721 <4>[ 17.757887] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10896 06:04:07.758065 <6>[ 17.759744] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10897 06:04:07.765671 <6>[ 17.765858] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10898 06:04:07.771881 <6>[ 17.765877] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10899 06:04:07.778572 <6>[ 17.765883] remoteproc remoteproc0: remote processor scp is now up
10900 06:04:07.789200 <3>[ 17.771392] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 06:04:07.795855 <6>[ 17.775922] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10902 06:04:07.802558 <6>[ 17.801085] videodev: Linux video capture interface: v2.00
10903 06:04:07.806142 <6>[ 17.801440] Bluetooth: Core ver 2.22
10904 06:04:07.809441 <6>[ 17.801503] NET: Registered PF_BLUETOOTH protocol family
10905 06:04:07.816073 <6>[ 17.801505] Bluetooth: HCI device and connection manager initialized
10906 06:04:07.822621 <6>[ 17.801518] Bluetooth: HCI socket layer initialized
10907 06:04:07.826313 <6>[ 17.801522] Bluetooth: L2CAP socket layer initialized
10908 06:04:07.833632 <6>[ 17.801528] Bluetooth: SCO socket layer initialized
10909 06:04:07.839434 <6>[ 17.805844] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10910 06:04:07.846656 <6>[ 17.805962] pci 0000:01:00.0: supports D1 D2
10911 06:04:07.850167 <6>[ 17.806206] usbcore: registered new interface driver cdc_ether
10912 06:04:07.860306 <6>[ 17.808236] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10913 06:04:07.867613 <6>[ 17.810525] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10914 06:04:07.871113 <6>[ 17.818469] r8152 2-1.3:1.0 eth0: v1.12.13
10915 06:04:07.877765 <6>[ 17.819671] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10916 06:04:07.884152 <6>[ 17.819922] usbcore: registered new interface driver r8153_ecm
10917 06:04:07.891160 <6>[ 17.835196] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10918 06:04:07.898407 <6>[ 17.854504] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10919 06:04:07.904674 <6>[ 17.859259] usbcore: registered new interface driver btusb
10920 06:04:07.915354 <4>[ 17.859868] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10921 06:04:07.918851 <3>[ 17.859877] Bluetooth: hci0: Failed to load firmware file (-2)
10922 06:04:07.925416 <3>[ 17.859885] Bluetooth: hci0: Failed to set up firmware (-2)
10923 06:04:07.935945 <4>[ 17.859889] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10924 06:04:07.945593 <6>[ 17.867108] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10925 06:04:07.952513 <6>[ 17.885493] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10926 06:04:07.958794 <3>[ 17.889335] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10927 06:04:07.968975 <6>[ 17.893835] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10928 06:04:07.978683 <3>[ 17.897644] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 06:04:07.985068 <3>[ 17.898620] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10930 06:04:07.998243 <6>[ 17.902914] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10931 06:04:08.004906 <6>[ 17.909134] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10932 06:04:08.011458 <6>[ 17.916324] usbcore: registered new interface driver uvcvideo
10933 06:04:08.021919 <3>[ 17.921991] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 06:04:08.028407 <6>[ 17.924649] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10935 06:04:08.034672 <6>[ 17.925368] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10936 06:04:08.044452 <3>[ 17.948701] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 06:04:08.051024 <6>[ 17.953056] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10938 06:04:08.060992 <3>[ 17.977217] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 06:04:08.068052 <6>[ 17.979484] pci 0000:00:00.0: PCI bridge to [bus 01]
10940 06:04:08.074479 <6>[ 17.979492] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10941 06:04:08.080697 <6>[ 18.225921] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10942 06:04:08.087702 [[0;32m OK [<6>[ 18.232908] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10943 06:04:08.097767 0m] Finished [0<6>[ 18.240552] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10944 06:04:08.100633 ;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10945 06:04:08.112867 <5>[ 18.255794] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10946 06:04:08.121786 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10947 06:04:08.133879 <5>[ 18.276985] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10948 06:04:08.140304 <4>[ 18.283910] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10949 06:04:08.146918 <6>[ 18.292792] cfg80211: failed to load regulatory.db
10950 06:04:08.182831 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10951 06:04:08.192975 <6>[ 18.336222] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10952 06:04:08.199455 <6>[ 18.343735] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10953 06:04:08.223905 <6>[ 18.370525] mt7921e 0000:01:00.0: ASIC revision: 79610010
10954 06:04:08.323045 <6>[ 18.466158] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10955 06:04:08.326650 <6>[ 18.466158]
10956 06:04:08.344970 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10957 06:04:08.360475 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10958 06:04:08.376495 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10959 06:04:08.395524 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10960 06:04:08.408702 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10961 06:04:08.424386 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10962 06:04:08.443865 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10963 06:04:08.476352 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10964 06:04:08.498316 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10965 06:04:08.513147 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10966 06:04:08.532569 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10967 06:04:08.547412 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10968 06:04:08.560183 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10969 06:04:08.581358 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10970 06:04:08.591743 <6>[ 18.734661] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10971 06:04:08.598099 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10972 06:04:08.612654 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10973 06:04:08.649274 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10974 06:04:08.681931 Starting [0;1;39mUser Login Management[0m...
10975 06:04:08.701094 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10976 06:04:08.722458 Starting [0;1;39mPermit User Sessions[0m...
10977 06:04:08.739207 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10978 06:04:08.762650 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10979 06:04:08.813323 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10980 06:04:08.861380 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10981 06:04:08.868175 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10982 06:04:08.881266 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10983 06:04:08.889043 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10984 06:04:08.905229 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10985 06:04:08.957422 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10986 06:04:08.988885 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10987 06:04:09.028104
10988 06:04:09.028634
10989 06:04:09.031915 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10990 06:04:09.032446
10991 06:04:09.034543 debian-bullseye-arm64 login: root (automatic login)
10992 06:04:09.035067
10993 06:04:09.035516
10994 06:04:09.050258 Linux debian-bullseye-arm64 6.1.67-cip12 #1 SMP PREEMPT Mon Dec 25 05:44:53 UTC 2023 aarch64
10995 06:04:09.050781
10996 06:04:09.057578 The programs included with the Debian GNU/Linux system are free software;
10997 06:04:09.063922 the exact distribution terms for each program are described in the
10998 06:04:09.066820 individual files in /usr/share/doc/*/copyright.
10999 06:04:09.067255
11000 06:04:09.073993 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11001 06:04:09.077331 permitted by applicable law.
11002 06:04:09.079022 Matched prompt #10: / #
11004 06:04:09.080261 Setting prompt string to ['/ #']
11005 06:04:09.080803 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11007 06:04:09.082064 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11008 06:04:09.082589 start: 2.2.6 expect-shell-connection (timeout 00:03:02) [common]
11009 06:04:09.082988 Setting prompt string to ['/ #']
11010 06:04:09.083387 Forcing a shell prompt, looking for ['/ #']
11012 06:04:09.134414 / #
11013 06:04:09.135049 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11014 06:04:09.135649 Waiting using forced prompt support (timeout 00:02:30)
11015 06:04:09.140823
11016 06:04:09.141722 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11017 06:04:09.142265 start: 2.2.7 export-device-env (timeout 00:03:02) [common]
11018 06:04:09.142828 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11019 06:04:09.143323 end: 2.2 depthcharge-retry (duration 00:01:58) [common]
11020 06:04:09.143822 end: 2 depthcharge-action (duration 00:01:58) [common]
11021 06:04:09.144346 start: 3 lava-test-retry (timeout 00:07:43) [common]
11022 06:04:09.144882 start: 3.1 lava-test-shell (timeout 00:07:43) [common]
11023 06:04:09.145303 Using namespace: common
11025 06:04:09.246759 / # #
11026 06:04:09.247423 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11027 06:04:09.252937 #
11028 06:04:09.253214 Using /lava-12379478
11030 06:04:09.353761 / # export SHELL=/bin/sh
11031 06:04:09.362864 export SHELL=/bin/sh<6>[ 19.505682] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11032 06:04:09.363405
11033 06:04:09.369234 <6>[ 19.513839] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11035 06:04:09.471027 / # . /lava-12379478/environment
11036 06:04:09.471845 . /lava-12379478/environment<6>[ 19.595530] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11037 06:04:09.477333
11039 06:04:09.579059 / # /lava-12379478/bin/lava-test-runner /lava-12379478/0
11040 06:04:09.579659 Test shell timeout: 10s (minimum of the action and connection timeout)
11041 06:04:09.586092 /lava-12379478/bin/lava-test-runner /lava-12379478/0
11042 06:04:09.609977 + export TESTRUN_ID=0_v4l2-compliance-uvc
11043 06:04:09.613611 + cd /lava-12379478/0/tests/0_v4l2-compliance-uvc
11044 06:04:09.614049 + cat uuid
11045 06:04:09.616734 + UUID=12379478_1.5.2.3.1
11046 06:04:09.617172 + set +x
11047 06:04:09.623742 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 12379478_1.5.2.3.1>
11048 06:04:09.624474 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 12379478_1.5.2.3.1
11049 06:04:09.624874 Starting test lava.0_v4l2-compliance-uvc (12379478_1.5.2.3.1)
11050 06:04:09.625412 Skipping test definition patterns.
11051 06:04:09.627092 + /usr/bin/v4l2-parser.sh -d uvcvideo
11052 06:04:09.633693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11053 06:04:09.634231 device: /dev/video0
11054 06:04:09.634960 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11056 06:04:16.124115 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11057 06:04:16.136921 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11058 06:04:16.146352
11059 06:04:16.162213 Compliance test for uvcvideo device /dev/video0:
11060 06:04:16.170004
11061 06:04:16.186148 Driver Info:
11062 06:04:16.196910 Driver name : uvcvideo
11063 06:04:16.213458 Card type : HD User Facing: HD User Facing
11064 06:04:16.225329 Bus info : usb-11200000.usb-1.4.1
11065 06:04:16.231016 Driver version : 6.1.67
11066 06:04:16.241088 Capabilities : 0x84a00001
11067 06:04:16.259322 Metadata Capture
11068 06:04:16.270384 Streaming
11069 06:04:16.285065 Extended Pix Format
11070 06:04:16.295603 Device Capabilities
11071 06:04:16.309876 Device Caps : 0x04200001
11072 06:04:16.323027 Streaming
11073 06:04:16.334994 Extended Pix Format
11074 06:04:16.346214 Media Driver Info:
11075 06:04:16.357559 Driver name : uvcvideo
11076 06:04:16.375161 Model : HD User Facing: HD User Facing
11077 06:04:16.381540 Serial : 200901010001
11078 06:04:16.400236 Bus info : usb-11200000.usb-1.4.1
11079 06:04:16.407895 Media version : 6.1.67
11080 06:04:16.427548 Hardware revision: 0x00009758 (38744)
11081 06:04:16.435211 Driver version : 6.1.67
11082 06:04:16.450097 Interface Info:
11083 06:04:16.464986 <LAVA_SIGNAL_TESTSET START Interface-Info>
11084 06:04:16.465556 ID : 0x03000002
11085 06:04:16.466172 Received signal: <TESTSET> START Interface-Info
11086 06:04:16.466536 Starting test_set Interface-Info
11087 06:04:16.476610 Type : V4L Video
11088 06:04:16.488452 Entity Info:
11089 06:04:16.494720 <LAVA_SIGNAL_TESTSET STOP>
11090 06:04:16.495517 Received signal: <TESTSET> STOP
11091 06:04:16.495899 Closing test_set Interface-Info
11092 06:04:16.504403 <LAVA_SIGNAL_TESTSET START Entity-Info>
11093 06:04:16.505184 Received signal: <TESTSET> START Entity-Info
11094 06:04:16.505588 Starting test_set Entity-Info
11095 06:04:16.507300 ID : 0x00000001 (1)
11096 06:04:16.518246 Name : HD User Facing: HD User Facing
11097 06:04:16.528056 Function : V4L2 I/O
11098 06:04:16.542316 Flags : default
11099 06:04:16.556576 Pad 0x01000007 : 0: Sink
11100 06:04:16.576163 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11101 06:04:16.576729
11102 06:04:16.586389 Required ioctls:
11103 06:04:16.598297 <LAVA_SIGNAL_TESTSET STOP>
11104 06:04:16.599077 Received signal: <TESTSET> STOP
11105 06:04:16.599425 Closing test_set Entity-Info
11106 06:04:16.608628 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11107 06:04:16.609407 Received signal: <TESTSET> START Required-ioctls
11108 06:04:16.609798 Starting test_set Required-ioctls
11109 06:04:16.611824 test MC information (see 'Media Driver Info' above): OK
11110 06:04:16.636061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11111 06:04:16.636886 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11113 06:04:16.639598 test VIDIOC_QUERYCAP: OK
11114 06:04:16.657666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11115 06:04:16.658477 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11117 06:04:16.660111 test invalid ioctls: OK
11118 06:04:16.683183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11119 06:04:16.683712
11120 06:04:16.684309 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11122 06:04:16.694839 Allow for multiple opens:
11123 06:04:16.701501 <LAVA_SIGNAL_TESTSET STOP>
11124 06:04:16.702357 Received signal: <TESTSET> STOP
11125 06:04:16.702731 Closing test_set Required-ioctls
11126 06:04:16.711859 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11127 06:04:16.712633 Received signal: <TESTSET> START Allow-for-multiple-opens
11128 06:04:16.712987 Starting test_set Allow-for-multiple-opens
11129 06:04:16.714547 test second /dev/video0 open: OK
11130 06:04:16.735037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11131 06:04:16.735821 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11133 06:04:16.737653 test VIDIOC_QUERYCAP: OK
11134 06:04:16.765097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11135 06:04:16.765893 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11137 06:04:16.768278 test VIDIOC_G/S_PRIORITY: OK
11138 06:04:16.789871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11139 06:04:16.790648 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11141 06:04:16.792725 test for unlimited opens: OK
11142 06:04:16.814658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11143 06:04:16.815139
11144 06:04:16.815725 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11146 06:04:16.825328 Debug ioctls:
11147 06:04:16.832279 <LAVA_SIGNAL_TESTSET STOP>
11148 06:04:16.833084 Received signal: <TESTSET> STOP
11149 06:04:16.833438 Closing test_set Allow-for-multiple-opens
11150 06:04:16.841924 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11151 06:04:16.842706 Received signal: <TESTSET> START Debug-ioctls
11152 06:04:16.843059 Starting test_set Debug-ioctls
11153 06:04:16.845619 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11154 06:04:16.865125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11155 06:04:16.865965 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11157 06:04:16.871531 test VIDIOC_LOG_STATUS: OK (Not Supported)
11158 06:04:16.890644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11159 06:04:16.891154
11160 06:04:16.891750 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11162 06:04:16.902171 Input ioctls:
11163 06:04:16.909992 <LAVA_SIGNAL_TESTSET STOP>
11164 06:04:16.910773 Received signal: <TESTSET> STOP
11165 06:04:16.911140 Closing test_set Debug-ioctls
11166 06:04:16.918227 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11167 06:04:16.918987 Received signal: <TESTSET> START Input-ioctls
11168 06:04:16.919358 Starting test_set Input-ioctls
11169 06:04:16.922171 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11170 06:04:16.951588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11171 06:04:16.952377 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11173 06:04:16.955008 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11174 06:04:16.974452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11175 06:04:16.975234 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11177 06:04:16.980951 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11178 06:04:17.001646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11179 06:04:17.002452 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11181 06:04:17.008217 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11182 06:04:17.028351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11183 06:04:17.029132 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11185 06:04:17.031006 test VIDIOC_G/S/ENUMINPUT: OK
11186 06:04:17.051367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11187 06:04:17.052124 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11189 06:04:17.054935 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11190 06:04:17.077383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11191 06:04:17.078220 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11193 06:04:17.080305 Inputs: 1 Audio Inputs: 0 Tuners: 0
11194 06:04:17.089644
11195 06:04:17.106911 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11196 06:04:17.128962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11197 06:04:17.129777 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11199 06:04:17.135644 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11200 06:04:17.154854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11201 06:04:17.155643 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11203 06:04:17.161308 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11204 06:04:17.180821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11205 06:04:17.181660 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11207 06:04:17.187459 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11208 06:04:17.206441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11209 06:04:17.207248 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11211 06:04:17.213226 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11212 06:04:17.230115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11213 06:04:17.230905 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11215 06:04:17.233308
11216 06:04:17.249829 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11217 06:04:17.272523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11218 06:04:17.273314 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11220 06:04:17.278795 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11221 06:04:17.300739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11222 06:04:17.301546 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11224 06:04:17.303752 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11225 06:04:17.324226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11226 06:04:17.325018 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11228 06:04:17.326724 test VIDIOC_G/S_EDID: OK (Not Supported)
11229 06:04:17.349881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11230 06:04:17.350387
11231 06:04:17.350979 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11233 06:04:17.366257 Control ioctls (Input 0):
11234 06:04:17.373335 <LAVA_SIGNAL_TESTSET STOP>
11235 06:04:17.374158 Received signal: <TESTSET> STOP
11236 06:04:17.374516 Closing test_set Input-ioctls
11237 06:04:17.382619 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11238 06:04:17.383390 Received signal: <TESTSET> START Control-ioctls-Input-0
11239 06:04:17.383745 Starting test_set Control-ioctls-Input-0
11240 06:04:17.385695 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11241 06:04:17.412073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11242 06:04:17.412582 test VIDIOC_QUERYCTRL: OK
11243 06:04:17.413173 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11245 06:04:17.435007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11246 06:04:17.435784 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11248 06:04:17.437785 test VIDIOC_G/S_CTRL: OK
11249 06:04:17.458349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11250 06:04:17.459124 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11252 06:04:17.461690 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11253 06:04:17.484804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11254 06:04:17.485616 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11256 06:04:17.491167 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11257 06:04:17.517224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11258 06:04:17.518098 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11260 06:04:17.519775 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11261 06:04:17.538039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11262 06:04:17.538710 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11264 06:04:17.541698 Standard Controls: 16 Private Controls: 0
11265 06:04:17.548720
11266 06:04:17.561395 Format ioctls (Input 0):
11267 06:04:17.569167 <LAVA_SIGNAL_TESTSET STOP>
11268 06:04:17.570026 Received signal: <TESTSET> STOP
11269 06:04:17.570422 Closing test_set Control-ioctls-Input-0
11270 06:04:17.579832 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11271 06:04:17.580609 Received signal: <TESTSET> START Format-ioctls-Input-0
11272 06:04:17.581024 Starting test_set Format-ioctls-Input-0
11273 06:04:17.583322 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11274 06:04:17.611754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11275 06:04:17.612581 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11277 06:04:17.614421 test VIDIOC_G/S_PARM: OK
11278 06:04:17.637162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11279 06:04:17.637919 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11281 06:04:17.640161 test VIDIOC_G_FBUF: OK (Not Supported)
11282 06:04:17.667180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11283 06:04:17.667984 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11285 06:04:17.670179 test VIDIOC_G_FMT: OK
11286 06:04:17.692197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11287 06:04:17.692992 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11289 06:04:17.695494 test VIDIOC_TRY_FMT: OK
11290 06:04:17.718360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11291 06:04:17.719137 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11293 06:04:17.724370 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11294 06:04:17.730147 test VIDIOC_S_FMT: OK
11295 06:04:17.756131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11296 06:04:17.756907 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11298 06:04:17.759059 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11299 06:04:17.781779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11300 06:04:17.782560 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11302 06:04:17.784585 test Cropping: OK (Not Supported)
11303 06:04:17.808596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11304 06:04:17.809454 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11306 06:04:17.811677 test Composing: OK (Not Supported)
11307 06:04:17.833548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11308 06:04:17.834325 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11310 06:04:17.836466 test Scaling: OK (Not Supported)
11311 06:04:17.860809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11312 06:04:17.861325
11313 06:04:17.861981 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11315 06:04:17.871148 Codec ioctls (Input 0):
11316 06:04:17.878096 <LAVA_SIGNAL_TESTSET STOP>
11317 06:04:17.878868 Received signal: <TESTSET> STOP
11318 06:04:17.879216 Closing test_set Format-ioctls-Input-0
11319 06:04:17.887878 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11320 06:04:17.888830 Received signal: <TESTSET> START Codec-ioctls-Input-0
11321 06:04:17.889213 Starting test_set Codec-ioctls-Input-0
11322 06:04:17.890647 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11323 06:04:17.914097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11324 06:04:17.914937 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11326 06:04:17.920684 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11327 06:04:17.939529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11328 06:04:17.940306 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11330 06:04:17.946018 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11331 06:04:17.964733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11332 06:04:17.965239
11333 06:04:17.965888 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11335 06:04:17.977809 Buffer ioctls (Input 0):
11336 06:04:17.987383 <LAVA_SIGNAL_TESTSET STOP>
11337 06:04:17.988150 Received signal: <TESTSET> STOP
11338 06:04:17.988530 Closing test_set Codec-ioctls-Input-0
11339 06:04:17.997757 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11340 06:04:17.998515 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11341 06:04:17.998885 Starting test_set Buffer-ioctls-Input-0
11342 06:04:18.000797 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11343 06:04:18.025371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11344 06:04:18.025931 test VIDIOC_EXPBUF: OK
11345 06:04:18.026537 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11347 06:04:18.051625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11348 06:04:18.052383 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11350 06:04:18.055601 test Requests: OK (Not Supported)
11351 06:04:18.076990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11352 06:04:18.077549
11353 06:04:18.078151 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11355 06:04:18.087649 Test input 0:
11356 06:04:18.101193
11357 06:04:18.113096 Streaming ioctls:
11358 06:04:18.120650 <LAVA_SIGNAL_TESTSET STOP>
11359 06:04:18.121427 Received signal: <TESTSET> STOP
11360 06:04:18.121799 Closing test_set Buffer-ioctls-Input-0
11361 06:04:18.130810 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11362 06:04:18.131587 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11363 06:04:18.131959 Starting test_set Streaming-ioctls_Test-input-0
11364 06:04:18.134372 test read/write: OK (Not Supported)
11365 06:04:18.155705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11366 06:04:18.156501 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11368 06:04:18.158693 test blocking wait: OK
11369 06:04:18.181590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11370 06:04:18.182401 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11372 06:04:18.190891 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11373 06:04:18.194238 test MMAP (no poll): FAIL
11374 06:04:18.218016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11375 06:04:18.218786 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11377 06:04:18.228037 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11378 06:04:18.233025 test MMAP (select): FAIL
11379 06:04:18.257952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11380 06:04:18.258730 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11382 06:04:18.267549 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11383 06:04:18.273808 test MMAP (epoll): FAIL
11384 06:04:18.298105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11385 06:04:18.298608
11386 06:04:18.299200 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11388 06:04:18.312885
11389 06:04:18.502559
11390 06:04:18.512208 test USERPTR (no poll): OK
11391 06:04:18.537670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11392 06:04:18.538257
11393 06:04:18.538858 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11395 06:04:18.550683
11396 06:04:18.750654
11397 06:04:18.761661 test USERPTR (select): OK
11398 06:04:18.786144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11399 06:04:18.786921 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11401 06:04:18.792496 test DMABUF: Cannot test, specify --expbuf-device
11402 06:04:18.797721
11403 06:04:18.818999 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11404 06:04:18.822407 <LAVA_TEST_RUNNER EXIT>
11405 06:04:18.823076 ok: lava_test_shell seems to have completed
11406 06:04:18.823445 Marking unfinished test run as failed
11408 06:04:18.828161 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11409 06:04:18.828772 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11410 06:04:18.829208 end: 3 lava-test-retry (duration 00:00:10) [common]
11411 06:04:18.829681 start: 4 finalize (timeout 00:07:33) [common]
11412 06:04:18.830134 start: 4.1 power-off (timeout 00:00:30) [common]
11413 06:04:18.830870 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11414 06:04:18.953179 >> Command sent successfully.
11415 06:04:18.957035 Returned 0 in 0 seconds
11416 06:04:19.057962 end: 4.1 power-off (duration 00:00:00) [common]
11418 06:04:19.059345 start: 4.2 read-feedback (timeout 00:07:33) [common]
11419 06:04:19.060539 Listened to connection for namespace 'common' for up to 1s
11420 06:04:20.061126 Finalising connection for namespace 'common'
11421 06:04:20.061763 Disconnecting from shell: Finalise
11422 06:04:20.062128 / #
11423 06:04:20.162752 end: 4.2 read-feedback (duration 00:00:01) [common]
11424 06:04:20.162930 end: 4 finalize (duration 00:00:01) [common]
11425 06:04:20.163055 Cleaning after the job
11426 06:04:20.163165 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379478/tftp-deploy-13tqp04d/ramdisk
11427 06:04:20.169411 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379478/tftp-deploy-13tqp04d/kernel
11428 06:04:20.186139 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379478/tftp-deploy-13tqp04d/dtb
11429 06:04:20.186330 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12379478/tftp-deploy-13tqp04d/modules
11430 06:04:20.193587 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12379478
11431 06:04:20.262385 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12379478
11432 06:04:20.262541 Job finished correctly